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`timescale 1ns/100ps /** * `timescale time_unit base / precision base * * -Specifies the time units and precision for delays: * -time_unit is the amount of time a delay of 1 represents. * The time unit must be 1 10 or 100 * -base is the time base for each unit, ranging from seconds * to femtoseconds, and must be: s ms us ns ps or fs * -precision and base represent how many decimal points of * precision to use relative to the time units. */ /** * This is written by Zhiyang Ong * for EE577b Homework 2, Question 2 */ // Testbench for behavioral model for the decoder // Import the modules that will be tested for in this testbench `include "encoder_pl.v" `include "decoder_pl.v" `include "pipelinedec.v" // IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui module tb_pipeline(); /** * Declare signal types for testbench to drive and monitor * signals during the simulation of the arbiter * * The reg data type holds a value until a new value is driven * onto it in an "initial" or "always" block. It can only be * assigned a value in an "always" or "initial" block, and is * used to apply stimulus to the inputs of the DUT. * * The wire type is a passive data type that holds a value driven * onto it by a port, assign statement or reg type. Wires cannot be * assigned values inside "always" and "initial" blocks. They can * be used to hold the values of the DUT's outputs */ // Declare "wire" signals: outputs from the DUTs // Output of stage 1 wire [13:0] c; // Output of stage 2 wire [13:0] cx; // Output of stage 3 wire [3:0] q; //wire [10:0] rb; // Declare "reg" signals: inputs to the DUTs // 1st stage reg [3:0] b; reg [3:0] r_b; reg [13:0] e; reg [13:0] r_e; // 2nd stage reg [13:0] r_c; reg [13:0] rr_e; reg [3:0] rr_b; //reg [15:1] err; // 3rd stage //reg [14:0] cx; //reg [10:0] qx; reg [13:0] r_qx; reg [3:0] rb; reg clk,reset; reg [13:0] e2; encoder enc ( // instance_name(signal name), // Signal name can be the same as the instance name r_b,c); decoder dec ( // instance_name(signal name), // Signal name can be the same as the instance name r_qx,q); large_xor xr ( // instance_name(signal name), // Signal name can be the same as the instance name r_c,rr_e,cx); /** * Each sequential control block, such as the initial or always * block, will execute concurrently in every module at the start * of the simulation */ always begin // Clock frequency is arbitrarily chosen #10 clk = 0; #10 clk = 1; end // Create the register (flip-flop) for the initial/1st stage always@(posedge clk) begin if(reset) begin r_b<=0; r_e<=0; end else begin r_e<=e; r_b<=b; end end // Create the register (flip-flop) for the 2nd stage always@(posedge clk) begin if(reset) begin r_c<=0; rr_e<=0; rr_b<=0; end else begin r_c<=c; rr_e<=r_e; rr_b<=r_b; end end // Create the register (flip-flop) for the 3rd stage always@(posedge clk) begin if(reset) begin rb<=0; end else begin r_qx<=cx; rb<=rr_b; e2<=rr_e; end end /** * Initial block start executing sequentially @ t=0 * If and when a delay is encountered, the execution of this block * pauses or waits until the delay time has passed, before resuming * execution * * Each intial or always block executes concurrently; that is, * multiple "always" or "initial" blocks will execute simultaneously * * E.g. * always * begin * #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns * // Clock signal has a period of 20 ns or 50 MHz * end */ initial begin // "$time" indicates the current time in the simulation $display(" << Starting the simulation >>"); reset=1; #20; reset=0; b = $random; e = 14'b00000000000000; $display(q, "<< Displaying q >>"); $display(rb, "<< Displaying rb >>"); #20; b = $random; e = 14'b00000000000000; $display(q, "<< Displaying q >>"); $display(rb, "<< Displaying rb >>"); #20; b = $random; e = 14'b00000100000000; $display(q, "<< Displaying q >>"); $display(rb, "<< Displaying rb >>"); #20; b = $random; e = 14'b00000000000000; $display(q, "<< Displaying q >>"); $display(rb, "<< Displaying rb >>"); #20; b = $random; e = 14'b00000000000000; $display(q, "<< Displaying q >>"); $display(rb, "<< Displaying rb >>"); #20; b = $random; e = 14'b00000001000000; $display(q, "<< Displaying q >>"); $display(rb, "<< Displaying rb >>"); #20; b = $random; e = 14'b00000000000000; $display(q, "<< Displaying q >>"); $display(rb, "<< Displaying rb >>"); #20; b = $random; e = 14'b00000000000000; $display(q, "<< Displaying q >>"); $display(rb, "<< Displaying rb >>"); #20; b = $random; e = 14'b00000100000000; $display(q, "<< Displaying q >>"); $display(rb, "<< Displaying rb >>"); #20; b = $random; e = 14'b00000000000000; $display(q, "<< Displaying q >>"); $display(rb, "<< Displaying rb >>"); #300; $display(" << Finishing the simulation >>"); $finish; end endmodule

/////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2018 Xilinx, Inc. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2018.3 // \ \ Description : Xilinx Unified Simulation Library Component // / / 288K-bit High-Density Memory Building Block // /___/ /\ Filename : URAM288.v // \ \ / \ // \___\/\___\ // /////////////////////////////////////////////////////////////////////////////// // Revision: // 10/31/2014 - Initial functional version // End Revision: /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps / 1 ps `celldefine module URAM288 #( `ifdef XIL_TIMING parameter LOC = "UNPLACED", `endif parameter integer AUTO_SLEEP_LATENCY = 8, parameter integer AVG_CONS_INACTIVE_CYCLES = 10, parameter BWE_MODE_A = "PARITY_INTERLEAVED", parameter BWE_MODE_B = "PARITY_INTERLEAVED", parameter CASCADE_ORDER_A = "NONE", parameter CASCADE_ORDER_B = "NONE", parameter EN_AUTO_SLEEP_MODE = "FALSE", parameter EN_ECC_RD_A = "FALSE", parameter EN_ECC_RD_B = "FALSE", parameter EN_ECC_WR_A = "FALSE", parameter EN_ECC_WR_B = "FALSE", parameter IREG_PRE_A = "FALSE", parameter IREG_PRE_B = "FALSE", parameter [0:0] IS_CLK_INVERTED = 1'b0, parameter [0:0] IS_EN_A_INVERTED = 1'b0, parameter [0:0] IS_EN_B_INVERTED = 1'b0, parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0, parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0, parameter [0:0] IS_RST_A_INVERTED = 1'b0, parameter [0:0] IS_RST_B_INVERTED = 1'b0, parameter MATRIX_ID = "NONE", parameter integer NUM_UNIQUE_SELF_ADDR_A = 1, parameter integer NUM_UNIQUE_SELF_ADDR_B = 1, parameter integer NUM_URAM_IN_MATRIX = 1, parameter OREG_A = "FALSE", parameter OREG_B = "FALSE", parameter OREG_ECC_A = "FALSE", parameter OREG_ECC_B = "FALSE", parameter REG_CAS_A = "FALSE", parameter REG_CAS_B = "FALSE", parameter RST_MODE_A = "SYNC", parameter RST_MODE_B = "SYNC", parameter [10:0] SELF_ADDR_A = 11'h000, parameter [10:0] SELF_ADDR_B = 11'h000, parameter [10:0] SELF_MASK_A = 11'h7FF, parameter [10:0] SELF_MASK_B = 11'h7FF, parameter USE_EXT_CE_A = "FALSE", parameter USE_EXT_CE_B = "FALSE" )( output [22:0] CAS_OUT_ADDR_A, output [22:0] CAS_OUT_ADDR_B, output [8:0] CAS_OUT_BWE_A, output [8:0] CAS_OUT_BWE_B, output CAS_OUT_DBITERR_A, output CAS_OUT_DBITERR_B, output [71:0] CAS_OUT_DIN_A, output [71:0] CAS_OUT_DIN_B, output [71:0] CAS_OUT_DOUT_A, output [71:0] CAS_OUT_DOUT_B, output CAS_OUT_EN_A, output CAS_OUT_EN_B, output CAS_OUT_RDACCESS_A, output CAS_OUT_RDACCESS_B, output CAS_OUT_RDB_WR_A, output CAS_OUT_RDB_WR_B, output CAS_OUT_SBITERR_A, output CAS_OUT_SBITERR_B, output DBITERR_A, output DBITERR_B, output [71:0] DOUT_A, output [71:0] DOUT_B, output RDACCESS_A, output RDACCESS_B, output SBITERR_A, output SBITERR_B, input [22:0] ADDR_A, input [22:0] ADDR_B, input [8:0] BWE_A, input [8:0] BWE_B, input [22:0] CAS_IN_ADDR_A, input [22:0] CAS_IN_ADDR_B, input [8:0] CAS_IN_BWE_A, input [8:0] CAS_IN_BWE_B, input CAS_IN_DBITERR_A, input CAS_IN_DBITERR_B, input [71:0] CAS_IN_DIN_A, input [71:0] CAS_IN_DIN_B, input [71:0] CAS_IN_DOUT_A, input [71:0] CAS_IN_DOUT_B, input CAS_IN_EN_A, input CAS_IN_EN_B, input CAS_IN_RDACCESS_A, input CAS_IN_RDACCESS_B, input CAS_IN_RDB_WR_A, input CAS_IN_RDB_WR_B, input CAS_IN_SBITERR_A, input CAS_IN_SBITERR_B, input CLK, input [71:0] DIN_A, input [71:0] DIN_B, input EN_A, input EN_B, input INJECT_DBITERR_A, input INJECT_DBITERR_B, input INJECT_SBITERR_A, input INJECT_SBITERR_B, input OREG_CE_A, input OREG_CE_B, input OREG_ECC_CE_A, input OREG_ECC_CE_B, input RDB_WR_A, input RDB_WR_B, input RST_A, input RST_B, input SLEEP ); // define constants localparam MODULE_NAME = "URAM288"; // Parameter encodings and registers localparam BWE_MODE_A_PARITY_INDEPENDENT = 1; localparam BWE_MODE_A_PARITY_INTERLEAVED = 0; localparam BWE_MODE_B_PARITY_INDEPENDENT = 1; localparam BWE_MODE_B_PARITY_INTERLEAVED = 0; localparam CASCADE_ORDER_A_FIRST = 1; localparam CASCADE_ORDER_A_LAST = 2; localparam CASCADE_ORDER_A_MIDDLE = 3; localparam CASCADE_ORDER_A_NONE = 0; localparam CASCADE_ORDER_B_FIRST = 1; localparam CASCADE_ORDER_B_LAST = 2; localparam CASCADE_ORDER_B_MIDDLE = 3; localparam CASCADE_ORDER_B_NONE = 0; localparam EN_AUTO_SLEEP_MODE_FALSE = 0; localparam EN_AUTO_SLEEP_MODE_TRUE = 1; localparam EN_ECC_RD_A_FALSE = 0; localparam EN_ECC_RD_A_TRUE = 1; localparam EN_ECC_RD_B_FALSE = 0; localparam EN_ECC_RD_B_TRUE = 1; localparam EN_ECC_WR_A_FALSE = 0; localparam EN_ECC_WR_A_TRUE = 1; localparam EN_ECC_WR_B_FALSE = 0; localparam EN_ECC_WR_B_TRUE = 1; localparam IREG_PRE_A_FALSE = 0; localparam IREG_PRE_A_TRUE = 1; localparam IREG_PRE_B_FALSE = 0; localparam IREG_PRE_B_TRUE = 1; localparam OREG_A_FALSE = 0; localparam OREG_A_TRUE = 1; localparam OREG_B_FALSE = 0; localparam OREG_B_TRUE = 1; localparam OREG_ECC_A_FALSE = 0; localparam OREG_ECC_A_TRUE = 1; localparam OREG_ECC_B_FALSE = 0; localparam OREG_ECC_B_TRUE = 1; localparam REG_CAS_A_FALSE = 0; localparam REG_CAS_A_TRUE = 1; localparam REG_CAS_B_FALSE = 0; localparam REG_CAS_B_TRUE = 1; localparam RST_MODE_A_ASYNC = 1; localparam RST_MODE_A_SYNC = 0; localparam RST_MODE_B_ASYNC = 1; localparam RST_MODE_B_SYNC = 0; localparam USE_EXT_CE_A_FALSE = 0; localparam USE_EXT_CE_A_TRUE = 1; localparam USE_EXT_CE_B_FALSE = 0; localparam USE_EXT_CE_B_TRUE = 1; reg trig_attr; // include dynamic registers - XILINX test only `ifdef XIL_DR `include "URAM288_dr.v" `else reg [31:0] AUTO_SLEEP_LATENCY_REG = AUTO_SLEEP_LATENCY; reg [31:0] AVG_CONS_INACTIVE_CYCLES_REG = AVG_CONS_INACTIVE_CYCLES; reg [144:1] BWE_MODE_A_REG = BWE_MODE_A; reg [144:1] BWE_MODE_B_REG = BWE_MODE_B; reg [48:1] CASCADE_ORDER_A_REG = CASCADE_ORDER_A; reg [48:1] CASCADE_ORDER_B_REG = CASCADE_ORDER_B; reg [40:1] EN_AUTO_SLEEP_MODE_REG = EN_AUTO_SLEEP_MODE; reg [40:1] EN_ECC_RD_A_REG = EN_ECC_RD_A; reg [40:1] EN_ECC_RD_B_REG = EN_ECC_RD_B; reg [40:1] EN_ECC_WR_A_REG = EN_ECC_WR_A; reg [40:1] EN_ECC_WR_B_REG = EN_ECC_WR_B; reg [40:1] IREG_PRE_A_REG = IREG_PRE_A; reg [40:1] IREG_PRE_B_REG = IREG_PRE_B; reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED; reg [0:0] IS_EN_A_INVERTED_REG = IS_EN_A_INVERTED; reg [0:0] IS_EN_B_INVERTED_REG = IS_EN_B_INVERTED; reg [0:0] IS_RDB_WR_A_INVERTED_REG = IS_RDB_WR_A_INVERTED; reg [0:0] IS_RDB_WR_B_INVERTED_REG = IS_RDB_WR_B_INVERTED; reg [0:0] IS_RST_A_INVERTED_REG = IS_RST_A_INVERTED; reg [0:0] IS_RST_B_INVERTED_REG = IS_RST_B_INVERTED; reg [32:1] MATRIX_ID_REG = MATRIX_ID; reg [31:0] NUM_UNIQUE_SELF_ADDR_A_REG = NUM_UNIQUE_SELF_ADDR_A; reg [31:0] NUM_UNIQUE_SELF_ADDR_B_REG = NUM_UNIQUE_SELF_ADDR_B; reg [31:0] NUM_URAM_IN_MATRIX_REG = NUM_URAM_IN_MATRIX; reg [40:1] OREG_A_REG = OREG_A; reg [40:1] OREG_B_REG = OREG_B; reg [40:1] OREG_ECC_A_REG = OREG_ECC_A; reg [40:1] OREG_ECC_B_REG = OREG_ECC_B; reg [40:1] REG_CAS_A_REG = REG_CAS_A; reg [40:1] REG_CAS_B_REG = REG_CAS_B; reg [40:1] RST_MODE_A_REG = RST_MODE_A; reg [40:1] RST_MODE_B_REG = RST_MODE_B; reg [10:0] SELF_ADDR_A_REG = SELF_ADDR_A; reg [10:0] SELF_ADDR_B_REG = SELF_ADDR_B; reg [10:0] SELF_MASK_A_REG = SELF_MASK_A; reg [10:0] SELF_MASK_B_REG = SELF_MASK_B; reg [40:1] USE_EXT_CE_A_REG = USE_EXT_CE_A; reg [40:1] USE_EXT_CE_B_REG = USE_EXT_CE_B; `endif `ifdef XIL_XECLIB wire [3:0] AUTO_SLEEP_LATENCY_BIN; wire [16:0] AVG_CONS_INACTIVE_CYCLES_BIN; wire BWE_MODE_A_BIN; wire BWE_MODE_B_BIN; wire [1:0] CASCADE_ORDER_A_BIN; wire [1:0] CASCADE_ORDER_B_BIN; wire EN_AUTO_SLEEP_MODE_BIN; wire EN_ECC_RD_A_BIN; wire EN_ECC_RD_B_BIN; wire EN_ECC_WR_A_BIN; wire EN_ECC_WR_B_BIN; wire IREG_PRE_A_BIN; wire IREG_PRE_B_BIN; wire [11:0] NUM_UNIQUE_SELF_ADDR_A_BIN; wire [11:0] NUM_UNIQUE_SELF_ADDR_B_BIN; wire [11:0] NUM_URAM_IN_MATRIX_BIN; wire OREG_A_BIN; wire OREG_B_BIN; wire OREG_ECC_A_BIN; wire OREG_ECC_B_BIN; wire REG_CAS_A_BIN; wire REG_CAS_B_BIN; wire RST_MODE_A_BIN; wire RST_MODE_B_BIN; wire USE_EXT_CE_A_BIN; wire USE_EXT_CE_B_BIN; `else reg [3:0] AUTO_SLEEP_LATENCY_BIN; reg [16:0] AVG_CONS_INACTIVE_CYCLES_BIN; reg BWE_MODE_A_BIN; reg BWE_MODE_B_BIN; reg [1:0] CASCADE_ORDER_A_BIN; reg [1:0] CASCADE_ORDER_B_BIN; reg EN_AUTO_SLEEP_MODE_BIN; reg EN_ECC_RD_A_BIN; reg EN_ECC_RD_B_BIN; reg EN_ECC_WR_A_BIN; reg EN_ECC_WR_B_BIN; reg IREG_PRE_A_BIN; reg IREG_PRE_B_BIN; reg [11:0] NUM_UNIQUE_SELF_ADDR_A_BIN; reg [11:0] NUM_UNIQUE_SELF_ADDR_B_BIN; reg [11:0] NUM_URAM_IN_MATRIX_BIN; reg OREG_A_BIN; reg OREG_B_BIN; reg OREG_ECC_A_BIN; reg OREG_ECC_B_BIN; reg REG_CAS_A_BIN; reg REG_CAS_B_BIN; reg RST_MODE_A_BIN; reg RST_MODE_B_BIN; reg USE_EXT_CE_A_BIN; reg USE_EXT_CE_B_BIN; `endif `ifdef XIL_XECLIB reg glblGSR = 1'b0; `else tri0 glblGSR = glbl.GSR; `endif wire CAS_IN_DBITERR_A_in; wire CAS_IN_DBITERR_B_in; wire CAS_IN_EN_A_in; wire CAS_IN_EN_B_in; wire CAS_IN_RDACCESS_A_in; wire CAS_IN_RDACCESS_B_in; wire CAS_IN_RDB_WR_A_in; wire CAS_IN_RDB_WR_B_in; wire CAS_IN_SBITERR_A_in; wire CAS_IN_SBITERR_B_in; wire CLK_in; wire EN_A_in; wire EN_B_in; wire INJECT_DBITERR_A_in; wire INJECT_DBITERR_B_in; wire INJECT_SBITERR_A_in; wire INJECT_SBITERR_B_in; wire OREG_CE_A_in; wire OREG_CE_B_in; wire OREG_ECC_CE_A_in; wire OREG_ECC_CE_B_in; wire RDB_WR_A_in; wire RDB_WR_B_in; wire RST_A_in; wire RST_B_in; wire SLEEP_in; wire [22:0] ADDR_A_in; wire [22:0] ADDR_B_in; wire [22:0] CAS_IN_ADDR_A_in; wire [22:0] CAS_IN_ADDR_B_in; wire [71:0] CAS_IN_DIN_A_in; wire [71:0] CAS_IN_DIN_B_in; wire [71:0] CAS_IN_DOUT_A_in; wire [71:0] CAS_IN_DOUT_B_in; wire [71:0] DIN_A_in; wire [71:0] DIN_B_in; wire [8:0] BWE_A_in; wire [8:0] BWE_B_in; wire [8:0] CAS_IN_BWE_A_in; wire [8:0] CAS_IN_BWE_B_in; `ifdef XIL_TIMING wire CAS_IN_DBITERR_A_delay; wire CAS_IN_DBITERR_B_delay; wire CAS_IN_EN_A_delay; wire CAS_IN_EN_B_delay; wire CAS_IN_RDACCESS_A_delay; wire CAS_IN_RDACCESS_B_delay; wire CAS_IN_RDB_WR_A_delay; wire CAS_IN_RDB_WR_B_delay; wire CAS_IN_SBITERR_A_delay; wire CAS_IN_SBITERR_B_delay; wire CLK_delay; wire EN_A_delay; wire EN_B_delay; wire INJECT_DBITERR_A_delay; wire INJECT_DBITERR_B_delay; wire INJECT_SBITERR_A_delay; wire INJECT_SBITERR_B_delay; wire OREG_CE_A_delay; wire OREG_CE_B_delay; wire OREG_ECC_CE_A_delay; wire OREG_ECC_CE_B_delay; wire RDB_WR_A_delay; wire RDB_WR_B_delay; wire RST_A_delay; wire RST_B_delay; wire SLEEP_delay; wire [22:0] ADDR_A_delay; wire [22:0] ADDR_B_delay; wire [22:0] CAS_IN_ADDR_A_delay; wire [22:0] CAS_IN_ADDR_B_delay; wire [71:0] CAS_IN_DIN_A_delay; wire [71:0] CAS_IN_DIN_B_delay; wire [71:0] CAS_IN_DOUT_A_delay; wire [71:0] CAS_IN_DOUT_B_delay; wire [71:0] DIN_A_delay; wire [71:0] DIN_B_delay; wire [8:0] BWE_A_delay; wire [8:0] BWE_B_delay; wire [8:0] CAS_IN_BWE_A_delay; wire [8:0] CAS_IN_BWE_B_delay; `endif `ifdef XIL_TIMING assign ADDR_A_in = ADDR_A_delay; assign ADDR_B_in = ADDR_B_delay; assign BWE_A_in = BWE_A_delay; assign BWE_B_in = BWE_B_delay; assign CAS_IN_ADDR_A_in[0] = (CAS_IN_ADDR_A[0] !== 1'bz) && CAS_IN_ADDR_A_delay[0]; // rv 0 assign CAS_IN_ADDR_A_in[10] = (CAS_IN_ADDR_A[10] !== 1'bz) && CAS_IN_ADDR_A_delay[10]; // rv 0 assign CAS_IN_ADDR_A_in[11] = (CAS_IN_ADDR_A[11] !== 1'bz) && CAS_IN_ADDR_A_delay[11]; // rv 0 assign CAS_IN_ADDR_A_in[12] = (CAS_IN_ADDR_A[12] !== 1'bz) && CAS_IN_ADDR_A_delay[12]; // rv 0 assign CAS_IN_ADDR_A_in[13] = (CAS_IN_ADDR_A[13] !== 1'bz) && CAS_IN_ADDR_A_delay[13]; // rv 0 assign CAS_IN_ADDR_A_in[14] = (CAS_IN_ADDR_A[14] !== 1'bz) && CAS_IN_ADDR_A_delay[14]; // rv 0 assign CAS_IN_ADDR_A_in[15] = (CAS_IN_ADDR_A[15] !== 1'bz) && CAS_IN_ADDR_A_delay[15]; // rv 0 assign CAS_IN_ADDR_A_in[16] = (CAS_IN_ADDR_A[16] !== 1'bz) && CAS_IN_ADDR_A_delay[16]; // rv 0 assign CAS_IN_ADDR_A_in[17] = (CAS_IN_ADDR_A[17] !== 1'bz) && CAS_IN_ADDR_A_delay[17]; // rv 0 assign CAS_IN_ADDR_A_in[18] = (CAS_IN_ADDR_A[18] !== 1'bz) && CAS_IN_ADDR_A_delay[18]; // rv 0 assign CAS_IN_ADDR_A_in[19] = (CAS_IN_ADDR_A[19] !== 1'bz) && CAS_IN_ADDR_A_delay[19]; // rv 0 assign CAS_IN_ADDR_A_in[1] = (CAS_IN_ADDR_A[1] !== 1'bz) && CAS_IN_ADDR_A_delay[1]; // rv 0 assign CAS_IN_ADDR_A_in[20] = (CAS_IN_ADDR_A[20] !== 1'bz) && CAS_IN_ADDR_A_delay[20]; // rv 0 assign CAS_IN_ADDR_A_in[21] = (CAS_IN_ADDR_A[21] !== 1'bz) && CAS_IN_ADDR_A_delay[21]; // rv 0 assign CAS_IN_ADDR_A_in[22] = (CAS_IN_ADDR_A[22] !== 1'bz) && CAS_IN_ADDR_A_delay[22]; // rv 0 assign CAS_IN_ADDR_A_in[2] = (CAS_IN_ADDR_A[2] !== 1'bz) && CAS_IN_ADDR_A_delay[2]; // rv 0 assign CAS_IN_ADDR_A_in[3] = (CAS_IN_ADDR_A[3] !== 1'bz) && CAS_IN_ADDR_A_delay[3]; // rv 0 assign CAS_IN_ADDR_A_in[4] = (CAS_IN_ADDR_A[4] !== 1'bz) && CAS_IN_ADDR_A_delay[4]; // rv 0 assign CAS_IN_ADDR_A_in[5] = (CAS_IN_ADDR_A[5] !== 1'bz) && CAS_IN_ADDR_A_delay[5]; // rv 0 assign CAS_IN_ADDR_A_in[6] = (CAS_IN_ADDR_A[6] !== 1'bz) && CAS_IN_ADDR_A_delay[6]; // rv 0 assign CAS_IN_ADDR_A_in[7] = (CAS_IN_ADDR_A[7] !== 1'bz) && CAS_IN_ADDR_A_delay[7]; // rv 0 assign CAS_IN_ADDR_A_in[8] = (CAS_IN_ADDR_A[8] !== 1'bz) && CAS_IN_ADDR_A_delay[8]; // rv 0 assign CAS_IN_ADDR_A_in[9] = (CAS_IN_ADDR_A[9] !== 1'bz) && CAS_IN_ADDR_A_delay[9]; // rv 0 assign CAS_IN_ADDR_B_in[0] = (CAS_IN_ADDR_B[0] !== 1'bz) && CAS_IN_ADDR_B_delay[0]; // rv 0 assign CAS_IN_ADDR_B_in[10] = (CAS_IN_ADDR_B[10] !== 1'bz) && CAS_IN_ADDR_B_delay[10]; // rv 0 assign CAS_IN_ADDR_B_in[11] = (CAS_IN_ADDR_B[11] !== 1'bz) && CAS_IN_ADDR_B_delay[11]; // rv 0 assign CAS_IN_ADDR_B_in[12] = (CAS_IN_ADDR_B[12] !== 1'bz) && CAS_IN_ADDR_B_delay[12]; // rv 0 assign CAS_IN_ADDR_B_in[13] = (CAS_IN_ADDR_B[13] !== 1'bz) && CAS_IN_ADDR_B_delay[13]; // rv 0 assign CAS_IN_ADDR_B_in[14] = (CAS_IN_ADDR_B[14] !== 1'bz) && CAS_IN_ADDR_B_delay[14]; // rv 0 assign CAS_IN_ADDR_B_in[15] = (CAS_IN_ADDR_B[15] !== 1'bz) && CAS_IN_ADDR_B_delay[15]; // rv 0 assign CAS_IN_ADDR_B_in[16] = (CAS_IN_ADDR_B[16] !== 1'bz) && CAS_IN_ADDR_B_delay[16]; // rv 0 assign CAS_IN_ADDR_B_in[17] = (CAS_IN_ADDR_B[17] !== 1'bz) && CAS_IN_ADDR_B_delay[17]; // rv 0 assign CAS_IN_ADDR_B_in[18] = (CAS_IN_ADDR_B[18] !== 1'bz) && CAS_IN_ADDR_B_delay[18]; // rv 0 assign CAS_IN_ADDR_B_in[19] = (CAS_IN_ADDR_B[19] !== 1'bz) && CAS_IN_ADDR_B_delay[19]; // rv 0 assign CAS_IN_ADDR_B_in[1] = (CAS_IN_ADDR_B[1] !== 1'bz) && CAS_IN_ADDR_B_delay[1]; // rv 0 assign CAS_IN_ADDR_B_in[20] = (CAS_IN_ADDR_B[20] !== 1'bz) && CAS_IN_ADDR_B_delay[20]; // rv 0 assign CAS_IN_ADDR_B_in[21] = (CAS_IN_ADDR_B[21] !== 1'bz) && CAS_IN_ADDR_B_delay[21]; // rv 0 assign CAS_IN_ADDR_B_in[22] = (CAS_IN_ADDR_B[22] !== 1'bz) && CAS_IN_ADDR_B_delay[22]; // rv 0 assign CAS_IN_ADDR_B_in[2] = (CAS_IN_ADDR_B[2] !== 1'bz) && CAS_IN_ADDR_B_delay[2]; // rv 0 assign CAS_IN_ADDR_B_in[3] = (CAS_IN_ADDR_B[3] !== 1'bz) && CAS_IN_ADDR_B_delay[3]; // rv 0 assign CAS_IN_ADDR_B_in[4] = (CAS_IN_ADDR_B[4] !== 1'bz) && CAS_IN_ADDR_B_delay[4]; // rv 0 assign CAS_IN_ADDR_B_in[5] = (CAS_IN_ADDR_B[5] !== 1'bz) && CAS_IN_ADDR_B_delay[5]; // rv 0 assign CAS_IN_ADDR_B_in[6] = (CAS_IN_ADDR_B[6] !== 1'bz) && CAS_IN_ADDR_B_delay[6]; // rv 0 assign CAS_IN_ADDR_B_in[7] = (CAS_IN_ADDR_B[7] !== 1'bz) && CAS_IN_ADDR_B_delay[7]; // rv 0 assign CAS_IN_ADDR_B_in[8] = (CAS_IN_ADDR_B[8] !== 1'bz) && CAS_IN_ADDR_B_delay[8]; // rv 0 assign CAS_IN_ADDR_B_in[9] = (CAS_IN_ADDR_B[9] !== 1'bz) && CAS_IN_ADDR_B_delay[9]; // rv 0 assign CAS_IN_BWE_A_in[0] = (CAS_IN_BWE_A[0] !== 1'bz) && CAS_IN_BWE_A_delay[0]; // rv 0 assign CAS_IN_BWE_A_in[1] = (CAS_IN_BWE_A[1] !== 1'bz) && CAS_IN_BWE_A_delay[1]; // rv 0 assign CAS_IN_BWE_A_in[2] = (CAS_IN_BWE_A[2] !== 1'bz) && CAS_IN_BWE_A_delay[2]; // rv 0 assign CAS_IN_BWE_A_in[3] = (CAS_IN_BWE_A[3] !== 1'bz) && CAS_IN_BWE_A_delay[3]; // rv 0 assign CAS_IN_BWE_A_in[4] = (CAS_IN_BWE_A[4] !== 1'bz) && CAS_IN_BWE_A_delay[4]; // rv 0 assign CAS_IN_BWE_A_in[5] = (CAS_IN_BWE_A[5] !== 1'bz) && CAS_IN_BWE_A_delay[5]; // rv 0 assign CAS_IN_BWE_A_in[6] = (CAS_IN_BWE_A[6] !== 1'bz) && CAS_IN_BWE_A_delay[6]; // rv 0 assign CAS_IN_BWE_A_in[7] = (CAS_IN_BWE_A[7] !== 1'bz) && CAS_IN_BWE_A_delay[7]; // rv 0 assign CAS_IN_BWE_A_in[8] = (CAS_IN_BWE_A[8] !== 1'bz) && CAS_IN_BWE_A_delay[8]; // rv 0 assign CAS_IN_BWE_B_in[0] = (CAS_IN_BWE_B[0] !== 1'bz) && CAS_IN_BWE_B_delay[0]; // rv 0 assign CAS_IN_BWE_B_in[1] = (CAS_IN_BWE_B[1] !== 1'bz) && CAS_IN_BWE_B_delay[1]; // rv 0 assign CAS_IN_BWE_B_in[2] = (CAS_IN_BWE_B[2] !== 1'bz) && CAS_IN_BWE_B_delay[2]; // rv 0 assign CAS_IN_BWE_B_in[3] = (CAS_IN_BWE_B[3] !== 1'bz) && CAS_IN_BWE_B_delay[3]; // rv 0 assign CAS_IN_BWE_B_in[4] = (CAS_IN_BWE_B[4] !== 1'bz) && CAS_IN_BWE_B_delay[4]; // rv 0 assign CAS_IN_BWE_B_in[5] = (CAS_IN_BWE_B[5] !== 1'bz) && CAS_IN_BWE_B_delay[5]; // rv 0 assign CAS_IN_BWE_B_in[6] = (CAS_IN_BWE_B[6] !== 1'bz) && CAS_IN_BWE_B_delay[6]; // rv 0 assign CAS_IN_BWE_B_in[7] = (CAS_IN_BWE_B[7] !== 1'bz) && CAS_IN_BWE_B_delay[7]; // rv 0 assign CAS_IN_BWE_B_in[8] = (CAS_IN_BWE_B[8] !== 1'bz) && CAS_IN_BWE_B_delay[8]; // rv 0 assign CAS_IN_DBITERR_A_in = (CAS_IN_DBITERR_A !== 1'bz) && CAS_IN_DBITERR_A_delay; // rv 0 assign CAS_IN_DBITERR_B_in = (CAS_IN_DBITERR_B !== 1'bz) && CAS_IN_DBITERR_B_delay; // rv 0 assign CAS_IN_DIN_A_in[0] = (CAS_IN_DIN_A[0] !== 1'bz) && CAS_IN_DIN_A_delay[0]; // rv 0 assign CAS_IN_DIN_A_in[10] = (CAS_IN_DIN_A[10] !== 1'bz) && CAS_IN_DIN_A_delay[10]; // rv 0 assign CAS_IN_DIN_A_in[11] = (CAS_IN_DIN_A[11] !== 1'bz) && CAS_IN_DIN_A_delay[11]; // rv 0 assign CAS_IN_DIN_A_in[12] = (CAS_IN_DIN_A[12] !== 1'bz) && CAS_IN_DIN_A_delay[12]; // rv 0 assign CAS_IN_DIN_A_in[13] = (CAS_IN_DIN_A[13] !== 1'bz) && CAS_IN_DIN_A_delay[13]; // rv 0 assign CAS_IN_DIN_A_in[14] = (CAS_IN_DIN_A[14] !== 1'bz) && CAS_IN_DIN_A_delay[14]; // rv 0 assign CAS_IN_DIN_A_in[15] = (CAS_IN_DIN_A[15] !== 1'bz) && CAS_IN_DIN_A_delay[15]; // rv 0 assign CAS_IN_DIN_A_in[16] = (CAS_IN_DIN_A[16] !== 1'bz) && CAS_IN_DIN_A_delay[16]; // rv 0 assign CAS_IN_DIN_A_in[17] = (CAS_IN_DIN_A[17] !== 1'bz) && CAS_IN_DIN_A_delay[17]; // rv 0 assign CAS_IN_DIN_A_in[18] = (CAS_IN_DIN_A[18] !== 1'bz) && CAS_IN_DIN_A_delay[18]; // rv 0 assign CAS_IN_DIN_A_in[19] = (CAS_IN_DIN_A[19] !== 1'bz) && CAS_IN_DIN_A_delay[19]; // rv 0 assign CAS_IN_DIN_A_in[1] = (CAS_IN_DIN_A[1] !== 1'bz) && CAS_IN_DIN_A_delay[1]; // rv 0 assign CAS_IN_DIN_A_in[20] = (CAS_IN_DIN_A[20] !== 1'bz) && CAS_IN_DIN_A_delay[20]; // rv 0 assign CAS_IN_DIN_A_in[21] = (CAS_IN_DIN_A[21] !== 1'bz) && CAS_IN_DIN_A_delay[21]; // rv 0 assign CAS_IN_DIN_A_in[22] = (CAS_IN_DIN_A[22] !== 1'bz) && CAS_IN_DIN_A_delay[22]; // rv 0 assign CAS_IN_DIN_A_in[23] = (CAS_IN_DIN_A[23] !== 1'bz) && CAS_IN_DIN_A_delay[23]; // rv 0 assign CAS_IN_DIN_A_in[24] = (CAS_IN_DIN_A[24] !== 1'bz) && CAS_IN_DIN_A_delay[24]; // rv 0 assign CAS_IN_DIN_A_in[25] = (CAS_IN_DIN_A[25] !== 1'bz) && CAS_IN_DIN_A_delay[25]; // rv 0 assign CAS_IN_DIN_A_in[26] = (CAS_IN_DIN_A[26] !== 1'bz) && CAS_IN_DIN_A_delay[26]; // rv 0 assign CAS_IN_DIN_A_in[27] = (CAS_IN_DIN_A[27] !== 1'bz) && CAS_IN_DIN_A_delay[27]; // rv 0 assign CAS_IN_DIN_A_in[28] = (CAS_IN_DIN_A[28] !== 1'bz) && CAS_IN_DIN_A_delay[28]; // rv 0 assign CAS_IN_DIN_A_in[29] = (CAS_IN_DIN_A[29] !== 1'bz) && CAS_IN_DIN_A_delay[29]; // rv 0 assign CAS_IN_DIN_A_in[2] = (CAS_IN_DIN_A[2] !== 1'bz) && CAS_IN_DIN_A_delay[2]; // rv 0 assign CAS_IN_DIN_A_in[30] = (CAS_IN_DIN_A[30] !== 1'bz) && CAS_IN_DIN_A_delay[30]; // rv 0 assign CAS_IN_DIN_A_in[31] = (CAS_IN_DIN_A[31] !== 1'bz) && CAS_IN_DIN_A_delay[31]; // rv 0 assign CAS_IN_DIN_A_in[32] = (CAS_IN_DIN_A[32] !== 1'bz) && CAS_IN_DIN_A_delay[32]; // rv 0 assign CAS_IN_DIN_A_in[33] = (CAS_IN_DIN_A[33] !== 1'bz) && CAS_IN_DIN_A_delay[33]; // rv 0 assign CAS_IN_DIN_A_in[34] = (CAS_IN_DIN_A[34] !== 1'bz) && CAS_IN_DIN_A_delay[34]; // rv 0 assign CAS_IN_DIN_A_in[35] = (CAS_IN_DIN_A[35] !== 1'bz) && CAS_IN_DIN_A_delay[35]; // rv 0 assign CAS_IN_DIN_A_in[36] = (CAS_IN_DIN_A[36] !== 1'bz) && CAS_IN_DIN_A_delay[36]; // rv 0 assign CAS_IN_DIN_A_in[37] = (CAS_IN_DIN_A[37] !== 1'bz) && CAS_IN_DIN_A_delay[37]; // rv 0 assign CAS_IN_DIN_A_in[38] = (CAS_IN_DIN_A[38] !== 1'bz) && CAS_IN_DIN_A_delay[38]; // rv 0 assign CAS_IN_DIN_A_in[39] = (CAS_IN_DIN_A[39] !== 1'bz) && CAS_IN_DIN_A_delay[39]; // rv 0 assign CAS_IN_DIN_A_in[3] = (CAS_IN_DIN_A[3] !== 1'bz) && CAS_IN_DIN_A_delay[3]; // rv 0 assign CAS_IN_DIN_A_in[40] = (CAS_IN_DIN_A[40] !== 1'bz) && CAS_IN_DIN_A_delay[40]; // rv 0 assign CAS_IN_DIN_A_in[41] = (CAS_IN_DIN_A[41] !== 1'bz) && CAS_IN_DIN_A_delay[41]; // rv 0 assign CAS_IN_DIN_A_in[42] = (CAS_IN_DIN_A[42] !== 1'bz) && CAS_IN_DIN_A_delay[42]; // rv 0 assign CAS_IN_DIN_A_in[43] = (CAS_IN_DIN_A[43] !== 1'bz) && CAS_IN_DIN_A_delay[43]; // rv 0 assign CAS_IN_DIN_A_in[44] = (CAS_IN_DIN_A[44] !== 1'bz) && CAS_IN_DIN_A_delay[44]; // rv 0 assign CAS_IN_DIN_A_in[45] = (CAS_IN_DIN_A[45] !== 1'bz) && CAS_IN_DIN_A_delay[45]; // rv 0 assign CAS_IN_DIN_A_in[46] = (CAS_IN_DIN_A[46] !== 1'bz) && CAS_IN_DIN_A_delay[46]; // rv 0 assign CAS_IN_DIN_A_in[47] = (CAS_IN_DIN_A[47] !== 1'bz) && CAS_IN_DIN_A_delay[47]; // rv 0 assign CAS_IN_DIN_A_in[48] = (CAS_IN_DIN_A[48] !== 1'bz) && CAS_IN_DIN_A_delay[48]; // rv 0 assign CAS_IN_DIN_A_in[49] = (CAS_IN_DIN_A[49] !== 1'bz) && CAS_IN_DIN_A_delay[49]; // rv 0 assign CAS_IN_DIN_A_in[4] = (CAS_IN_DIN_A[4] !== 1'bz) && CAS_IN_DIN_A_delay[4]; // rv 0 assign CAS_IN_DIN_A_in[50] = (CAS_IN_DIN_A[50] !== 1'bz) && CAS_IN_DIN_A_delay[50]; // rv 0 assign CAS_IN_DIN_A_in[51] = (CAS_IN_DIN_A[51] !== 1'bz) && CAS_IN_DIN_A_delay[51]; // rv 0 assign CAS_IN_DIN_A_in[52] = (CAS_IN_DIN_A[52] !== 1'bz) && CAS_IN_DIN_A_delay[52]; // rv 0 assign CAS_IN_DIN_A_in[53] = (CAS_IN_DIN_A[53] !== 1'bz) && CAS_IN_DIN_A_delay[53]; // rv 0 assign CAS_IN_DIN_A_in[54] = (CAS_IN_DIN_A[54] !== 1'bz) && CAS_IN_DIN_A_delay[54]; // rv 0 assign CAS_IN_DIN_A_in[55] = (CAS_IN_DIN_A[55] !== 1'bz) && CAS_IN_DIN_A_delay[55]; // rv 0 assign CAS_IN_DIN_A_in[56] = (CAS_IN_DIN_A[56] !== 1'bz) && CAS_IN_DIN_A_delay[56]; // rv 0 assign CAS_IN_DIN_A_in[57] = (CAS_IN_DIN_A[57] !== 1'bz) && CAS_IN_DIN_A_delay[57]; // rv 0 assign CAS_IN_DIN_A_in[58] = (CAS_IN_DIN_A[58] !== 1'bz) && CAS_IN_DIN_A_delay[58]; // rv 0 assign CAS_IN_DIN_A_in[59] = (CAS_IN_DIN_A[59] !== 1'bz) && CAS_IN_DIN_A_delay[59]; // rv 0 assign CAS_IN_DIN_A_in[5] = (CAS_IN_DIN_A[5] !== 1'bz) && CAS_IN_DIN_A_delay[5]; // rv 0 assign CAS_IN_DIN_A_in[60] = (CAS_IN_DIN_A[60] !== 1'bz) && CAS_IN_DIN_A_delay[60]; // rv 0 assign CAS_IN_DIN_A_in[61] = (CAS_IN_DIN_A[61] !== 1'bz) && CAS_IN_DIN_A_delay[61]; // rv 0 assign CAS_IN_DIN_A_in[62] = (CAS_IN_DIN_A[62] !== 1'bz) && CAS_IN_DIN_A_delay[62]; // rv 0 assign CAS_IN_DIN_A_in[63] = (CAS_IN_DIN_A[63] !== 1'bz) && CAS_IN_DIN_A_delay[63]; // rv 0 assign CAS_IN_DIN_A_in[64] = (CAS_IN_DIN_A[64] !== 1'bz) && CAS_IN_DIN_A_delay[64]; // rv 0 assign CAS_IN_DIN_A_in[65] = (CAS_IN_DIN_A[65] !== 1'bz) && CAS_IN_DIN_A_delay[65]; // rv 0 assign CAS_IN_DIN_A_in[66] = (CAS_IN_DIN_A[66] !== 1'bz) && CAS_IN_DIN_A_delay[66]; // rv 0 assign CAS_IN_DIN_A_in[67] = (CAS_IN_DIN_A[67] !== 1'bz) && CAS_IN_DIN_A_delay[67]; // rv 0 assign CAS_IN_DIN_A_in[68] = (CAS_IN_DIN_A[68] !== 1'bz) && CAS_IN_DIN_A_delay[68]; // rv 0 assign CAS_IN_DIN_A_in[69] = (CAS_IN_DIN_A[69] !== 1'bz) && CAS_IN_DIN_A_delay[69]; // rv 0 assign CAS_IN_DIN_A_in[6] = (CAS_IN_DIN_A[6] !== 1'bz) && CAS_IN_DIN_A_delay[6]; // rv 0 assign CAS_IN_DIN_A_in[70] = (CAS_IN_DIN_A[70] !== 1'bz) && CAS_IN_DIN_A_delay[70]; // rv 0 assign CAS_IN_DIN_A_in[71] = (CAS_IN_DIN_A[71] !== 1'bz) && CAS_IN_DIN_A_delay[71]; // rv 0 assign CAS_IN_DIN_A_in[7] = (CAS_IN_DIN_A[7] !== 1'bz) && CAS_IN_DIN_A_delay[7]; // rv 0 assign CAS_IN_DIN_A_in[8] = (CAS_IN_DIN_A[8] !== 1'bz) && CAS_IN_DIN_A_delay[8]; // rv 0 assign CAS_IN_DIN_A_in[9] = (CAS_IN_DIN_A[9] !== 1'bz) && CAS_IN_DIN_A_delay[9]; // rv 0 assign CAS_IN_DIN_B_in[0] = (CAS_IN_DIN_B[0] !== 1'bz) && CAS_IN_DIN_B_delay[0]; // rv 0 assign CAS_IN_DIN_B_in[10] = (CAS_IN_DIN_B[10] !== 1'bz) && CAS_IN_DIN_B_delay[10]; // rv 0 assign CAS_IN_DIN_B_in[11] = (CAS_IN_DIN_B[11] !== 1'bz) && CAS_IN_DIN_B_delay[11]; // rv 0 assign CAS_IN_DIN_B_in[12] = (CAS_IN_DIN_B[12] !== 1'bz) && CAS_IN_DIN_B_delay[12]; // rv 0 assign CAS_IN_DIN_B_in[13] = (CAS_IN_DIN_B[13] !== 1'bz) && CAS_IN_DIN_B_delay[13]; // rv 0 assign CAS_IN_DIN_B_in[14] = (CAS_IN_DIN_B[14] !== 1'bz) && CAS_IN_DIN_B_delay[14]; // rv 0 assign CAS_IN_DIN_B_in[15] = (CAS_IN_DIN_B[15] !== 1'bz) && CAS_IN_DIN_B_delay[15]; // rv 0 assign CAS_IN_DIN_B_in[16] = (CAS_IN_DIN_B[16] !== 1'bz) && CAS_IN_DIN_B_delay[16]; // rv 0 assign CAS_IN_DIN_B_in[17] = (CAS_IN_DIN_B[17] !== 1'bz) && CAS_IN_DIN_B_delay[17]; // rv 0 assign CAS_IN_DIN_B_in[18] = (CAS_IN_DIN_B[18] !== 1'bz) && CAS_IN_DIN_B_delay[18]; // rv 0 assign CAS_IN_DIN_B_in[19] = (CAS_IN_DIN_B[19] !== 1'bz) && CAS_IN_DIN_B_delay[19]; // rv 0 assign CAS_IN_DIN_B_in[1] = (CAS_IN_DIN_B[1] !== 1'bz) && CAS_IN_DIN_B_delay[1]; // rv 0 assign CAS_IN_DIN_B_in[20] = (CAS_IN_DIN_B[20] !== 1'bz) && CAS_IN_DIN_B_delay[20]; // rv 0 assign CAS_IN_DIN_B_in[21] = (CAS_IN_DIN_B[21] !== 1'bz) && CAS_IN_DIN_B_delay[21]; // rv 0 assign CAS_IN_DIN_B_in[22] = (CAS_IN_DIN_B[22] !== 1'bz) && CAS_IN_DIN_B_delay[22]; // rv 0 assign CAS_IN_DIN_B_in[23] = (CAS_IN_DIN_B[23] !== 1'bz) && CAS_IN_DIN_B_delay[23]; // rv 0 assign CAS_IN_DIN_B_in[24] = (CAS_IN_DIN_B[24] !== 1'bz) && CAS_IN_DIN_B_delay[24]; // rv 0 assign CAS_IN_DIN_B_in[25] = (CAS_IN_DIN_B[25] !== 1'bz) && CAS_IN_DIN_B_delay[25]; // rv 0 assign CAS_IN_DIN_B_in[26] = (CAS_IN_DIN_B[26] !== 1'bz) && CAS_IN_DIN_B_delay[26]; // rv 0 assign CAS_IN_DIN_B_in[27] = (CAS_IN_DIN_B[27] !== 1'bz) && CAS_IN_DIN_B_delay[27]; // rv 0 assign CAS_IN_DIN_B_in[28] = (CAS_IN_DIN_B[28] !== 1'bz) && CAS_IN_DIN_B_delay[28]; // rv 0 assign CAS_IN_DIN_B_in[29] = (CAS_IN_DIN_B[29] !== 1'bz) && CAS_IN_DIN_B_delay[29]; // rv 0 assign CAS_IN_DIN_B_in[2] = (CAS_IN_DIN_B[2] !== 1'bz) && CAS_IN_DIN_B_delay[2]; // rv 0 assign CAS_IN_DIN_B_in[30] = (CAS_IN_DIN_B[30] !== 1'bz) && CAS_IN_DIN_B_delay[30]; // rv 0 assign CAS_IN_DIN_B_in[31] = (CAS_IN_DIN_B[31] !== 1'bz) && CAS_IN_DIN_B_delay[31]; // rv 0 assign CAS_IN_DIN_B_in[32] = (CAS_IN_DIN_B[32] !== 1'bz) && CAS_IN_DIN_B_delay[32]; // rv 0 assign CAS_IN_DIN_B_in[33] = (CAS_IN_DIN_B[33] !== 1'bz) && CAS_IN_DIN_B_delay[33]; // rv 0 assign CAS_IN_DIN_B_in[34] = (CAS_IN_DIN_B[34] !== 1'bz) && CAS_IN_DIN_B_delay[34]; // rv 0 assign CAS_IN_DIN_B_in[35] = (CAS_IN_DIN_B[35] !== 1'bz) && CAS_IN_DIN_B_delay[35]; // rv 0 assign CAS_IN_DIN_B_in[36] = (CAS_IN_DIN_B[36] !== 1'bz) && CAS_IN_DIN_B_delay[36]; // rv 0 assign CAS_IN_DIN_B_in[37] = (CAS_IN_DIN_B[37] !== 1'bz) && CAS_IN_DIN_B_delay[37]; // rv 0 assign CAS_IN_DIN_B_in[38] = (CAS_IN_DIN_B[38] !== 1'bz) && CAS_IN_DIN_B_delay[38]; // rv 0 assign CAS_IN_DIN_B_in[39] = (CAS_IN_DIN_B[39] !== 1'bz) && CAS_IN_DIN_B_delay[39]; // rv 0 assign CAS_IN_DIN_B_in[3] = (CAS_IN_DIN_B[3] !== 1'bz) && CAS_IN_DIN_B_delay[3]; // rv 0 assign CAS_IN_DIN_B_in[40] = (CAS_IN_DIN_B[40] !== 1'bz) && CAS_IN_DIN_B_delay[40]; // rv 0 assign CAS_IN_DIN_B_in[41] = (CAS_IN_DIN_B[41] !== 1'bz) && CAS_IN_DIN_B_delay[41]; // rv 0 assign CAS_IN_DIN_B_in[42] = (CAS_IN_DIN_B[42] !== 1'bz) && CAS_IN_DIN_B_delay[42]; // rv 0 assign CAS_IN_DIN_B_in[43] = (CAS_IN_DIN_B[43] !== 1'bz) && CAS_IN_DIN_B_delay[43]; // rv 0 assign CAS_IN_DIN_B_in[44] = (CAS_IN_DIN_B[44] !== 1'bz) && CAS_IN_DIN_B_delay[44]; // rv 0 assign CAS_IN_DIN_B_in[45] = (CAS_IN_DIN_B[45] !== 1'bz) && CAS_IN_DIN_B_delay[45]; // rv 0 assign CAS_IN_DIN_B_in[46] = (CAS_IN_DIN_B[46] !== 1'bz) && CAS_IN_DIN_B_delay[46]; // rv 0 assign CAS_IN_DIN_B_in[47] = (CAS_IN_DIN_B[47] !== 1'bz) && CAS_IN_DIN_B_delay[47]; // rv 0 assign CAS_IN_DIN_B_in[48] = (CAS_IN_DIN_B[48] !== 1'bz) && CAS_IN_DIN_B_delay[48]; // rv 0 assign CAS_IN_DIN_B_in[49] = (CAS_IN_DIN_B[49] !== 1'bz) && CAS_IN_DIN_B_delay[49]; // rv 0 assign CAS_IN_DIN_B_in[4] = (CAS_IN_DIN_B[4] !== 1'bz) && CAS_IN_DIN_B_delay[4]; // rv 0 assign CAS_IN_DIN_B_in[50] = (CAS_IN_DIN_B[50] !== 1'bz) && CAS_IN_DIN_B_delay[50]; // rv 0 assign CAS_IN_DIN_B_in[51] = (CAS_IN_DIN_B[51] !== 1'bz) && CAS_IN_DIN_B_delay[51]; // rv 0 assign CAS_IN_DIN_B_in[52] = (CAS_IN_DIN_B[52] !== 1'bz) && CAS_IN_DIN_B_delay[52]; // rv 0 assign CAS_IN_DIN_B_in[53] = (CAS_IN_DIN_B[53] !== 1'bz) && CAS_IN_DIN_B_delay[53]; // rv 0 assign CAS_IN_DIN_B_in[54] = (CAS_IN_DIN_B[54] !== 1'bz) && CAS_IN_DIN_B_delay[54]; // rv 0 assign CAS_IN_DIN_B_in[55] = (CAS_IN_DIN_B[55] !== 1'bz) && CAS_IN_DIN_B_delay[55]; // rv 0 assign CAS_IN_DIN_B_in[56] = (CAS_IN_DIN_B[56] !== 1'bz) && CAS_IN_DIN_B_delay[56]; // rv 0 assign CAS_IN_DIN_B_in[57] = (CAS_IN_DIN_B[57] !== 1'bz) && CAS_IN_DIN_B_delay[57]; // rv 0 assign CAS_IN_DIN_B_in[58] = (CAS_IN_DIN_B[58] !== 1'bz) && CAS_IN_DIN_B_delay[58]; // rv 0 assign CAS_IN_DIN_B_in[59] = (CAS_IN_DIN_B[59] !== 1'bz) && CAS_IN_DIN_B_delay[59]; // rv 0 assign CAS_IN_DIN_B_in[5] = (CAS_IN_DIN_B[5] !== 1'bz) && CAS_IN_DIN_B_delay[5]; // rv 0 assign CAS_IN_DIN_B_in[60] = (CAS_IN_DIN_B[60] !== 1'bz) && CAS_IN_DIN_B_delay[60]; // rv 0 assign CAS_IN_DIN_B_in[61] = (CAS_IN_DIN_B[61] !== 1'bz) && CAS_IN_DIN_B_delay[61]; // rv 0 assign CAS_IN_DIN_B_in[62] = (CAS_IN_DIN_B[62] !== 1'bz) && CAS_IN_DIN_B_delay[62]; // rv 0 assign CAS_IN_DIN_B_in[63] = (CAS_IN_DIN_B[63] !== 1'bz) && CAS_IN_DIN_B_delay[63]; // rv 0 assign CAS_IN_DIN_B_in[64] = (CAS_IN_DIN_B[64] !== 1'bz) && CAS_IN_DIN_B_delay[64]; // rv 0 assign CAS_IN_DIN_B_in[65] = (CAS_IN_DIN_B[65] !== 1'bz) && CAS_IN_DIN_B_delay[65]; // rv 0 assign CAS_IN_DIN_B_in[66] = (CAS_IN_DIN_B[66] !== 1'bz) && CAS_IN_DIN_B_delay[66]; // rv 0 assign CAS_IN_DIN_B_in[67] = (CAS_IN_DIN_B[67] !== 1'bz) && CAS_IN_DIN_B_delay[67]; // rv 0 assign CAS_IN_DIN_B_in[68] = (CAS_IN_DIN_B[68] !== 1'bz) && CAS_IN_DIN_B_delay[68]; // rv 0 assign CAS_IN_DIN_B_in[69] = (CAS_IN_DIN_B[69] !== 1'bz) && CAS_IN_DIN_B_delay[69]; // rv 0 assign CAS_IN_DIN_B_in[6] = (CAS_IN_DIN_B[6] !== 1'bz) && CAS_IN_DIN_B_delay[6]; // rv 0 assign CAS_IN_DIN_B_in[70] = (CAS_IN_DIN_B[70] !== 1'bz) && CAS_IN_DIN_B_delay[70]; // rv 0 assign CAS_IN_DIN_B_in[71] = (CAS_IN_DIN_B[71] !== 1'bz) && CAS_IN_DIN_B_delay[71]; // rv 0 assign CAS_IN_DIN_B_in[7] = (CAS_IN_DIN_B[7] !== 1'bz) && CAS_IN_DIN_B_delay[7]; // rv 0 assign CAS_IN_DIN_B_in[8] = (CAS_IN_DIN_B[8] !== 1'bz) && CAS_IN_DIN_B_delay[8]; // rv 0 assign CAS_IN_DIN_B_in[9] = (CAS_IN_DIN_B[9] !== 1'bz) && CAS_IN_DIN_B_delay[9]; // rv 0 assign CAS_IN_DOUT_A_in[0] = (CAS_IN_DOUT_A[0] !== 1'bz) && CAS_IN_DOUT_A_delay[0]; // rv 0 assign CAS_IN_DOUT_A_in[10] = (CAS_IN_DOUT_A[10] !== 1'bz) && CAS_IN_DOUT_A_delay[10]; // rv 0 assign CAS_IN_DOUT_A_in[11] = (CAS_IN_DOUT_A[11] !== 1'bz) && CAS_IN_DOUT_A_delay[11]; // rv 0 assign CAS_IN_DOUT_A_in[12] = (CAS_IN_DOUT_A[12] !== 1'bz) && CAS_IN_DOUT_A_delay[12]; // rv 0 assign CAS_IN_DOUT_A_in[13] = (CAS_IN_DOUT_A[13] !== 1'bz) && CAS_IN_DOUT_A_delay[13]; // rv 0 assign CAS_IN_DOUT_A_in[14] = (CAS_IN_DOUT_A[14] !== 1'bz) && CAS_IN_DOUT_A_delay[14]; // rv 0 assign CAS_IN_DOUT_A_in[15] = (CAS_IN_DOUT_A[15] !== 1'bz) && CAS_IN_DOUT_A_delay[15]; // rv 0 assign CAS_IN_DOUT_A_in[16] = (CAS_IN_DOUT_A[16] !== 1'bz) && CAS_IN_DOUT_A_delay[16]; // rv 0 assign CAS_IN_DOUT_A_in[17] = (CAS_IN_DOUT_A[17] !== 1'bz) && CAS_IN_DOUT_A_delay[17]; // rv 0 assign CAS_IN_DOUT_A_in[18] = (CAS_IN_DOUT_A[18] !== 1'bz) && CAS_IN_DOUT_A_delay[18]; // rv 0 assign CAS_IN_DOUT_A_in[19] = (CAS_IN_DOUT_A[19] !== 1'bz) && CAS_IN_DOUT_A_delay[19]; // rv 0 assign CAS_IN_DOUT_A_in[1] = (CAS_IN_DOUT_A[1] !== 1'bz) && CAS_IN_DOUT_A_delay[1]; // rv 0 assign CAS_IN_DOUT_A_in[20] = (CAS_IN_DOUT_A[20] !== 1'bz) && CAS_IN_DOUT_A_delay[20]; // rv 0 assign CAS_IN_DOUT_A_in[21] = (CAS_IN_DOUT_A[21] !== 1'bz) && CAS_IN_DOUT_A_delay[21]; // rv 0 assign CAS_IN_DOUT_A_in[22] = (CAS_IN_DOUT_A[22] !== 1'bz) && CAS_IN_DOUT_A_delay[22]; // rv 0 assign CAS_IN_DOUT_A_in[23] = (CAS_IN_DOUT_A[23] !== 1'bz) && CAS_IN_DOUT_A_delay[23]; // rv 0 assign CAS_IN_DOUT_A_in[24] = (CAS_IN_DOUT_A[24] !== 1'bz) && CAS_IN_DOUT_A_delay[24]; // rv 0 assign CAS_IN_DOUT_A_in[25] = (CAS_IN_DOUT_A[25] !== 1'bz) && CAS_IN_DOUT_A_delay[25]; // rv 0 assign CAS_IN_DOUT_A_in[26] = (CAS_IN_DOUT_A[26] !== 1'bz) && CAS_IN_DOUT_A_delay[26]; // rv 0 assign CAS_IN_DOUT_A_in[27] = (CAS_IN_DOUT_A[27] !== 1'bz) && CAS_IN_DOUT_A_delay[27]; // rv 0 assign CAS_IN_DOUT_A_in[28] = (CAS_IN_DOUT_A[28] !== 1'bz) && CAS_IN_DOUT_A_delay[28]; // rv 0 assign CAS_IN_DOUT_A_in[29] = (CAS_IN_DOUT_A[29] !== 1'bz) && CAS_IN_DOUT_A_delay[29]; // rv 0 assign CAS_IN_DOUT_A_in[2] = (CAS_IN_DOUT_A[2] !== 1'bz) && CAS_IN_DOUT_A_delay[2]; // rv 0 assign CAS_IN_DOUT_A_in[30] = (CAS_IN_DOUT_A[30] !== 1'bz) && CAS_IN_DOUT_A_delay[30]; // rv 0 assign CAS_IN_DOUT_A_in[31] = (CAS_IN_DOUT_A[31] !== 1'bz) && CAS_IN_DOUT_A_delay[31]; // rv 0 assign CAS_IN_DOUT_A_in[32] = (CAS_IN_DOUT_A[32] !== 1'bz) && CAS_IN_DOUT_A_delay[32]; // rv 0 assign CAS_IN_DOUT_A_in[33] = (CAS_IN_DOUT_A[33] !== 1'bz) && CAS_IN_DOUT_A_delay[33]; // rv 0 assign CAS_IN_DOUT_A_in[34] = (CAS_IN_DOUT_A[34] !== 1'bz) && CAS_IN_DOUT_A_delay[34]; // rv 0 assign CAS_IN_DOUT_A_in[35] = (CAS_IN_DOUT_A[35] !== 1'bz) && CAS_IN_DOUT_A_delay[35]; // rv 0 assign CAS_IN_DOUT_A_in[36] = (CAS_IN_DOUT_A[36] !== 1'bz) && CAS_IN_DOUT_A_delay[36]; // rv 0 assign CAS_IN_DOUT_A_in[37] = (CAS_IN_DOUT_A[37] !== 1'bz) && CAS_IN_DOUT_A_delay[37]; // rv 0 assign CAS_IN_DOUT_A_in[38] = (CAS_IN_DOUT_A[38] !== 1'bz) && CAS_IN_DOUT_A_delay[38]; // rv 0 assign CAS_IN_DOUT_A_in[39] = (CAS_IN_DOUT_A[39] !== 1'bz) && CAS_IN_DOUT_A_delay[39]; // rv 0 assign CAS_IN_DOUT_A_in[3] = (CAS_IN_DOUT_A[3] !== 1'bz) && CAS_IN_DOUT_A_delay[3]; // rv 0 assign CAS_IN_DOUT_A_in[40] = (CAS_IN_DOUT_A[40] !== 1'bz) && CAS_IN_DOUT_A_delay[40]; // rv 0 assign CAS_IN_DOUT_A_in[41] = (CAS_IN_DOUT_A[41] !== 1'bz) && CAS_IN_DOUT_A_delay[41]; // rv 0 assign CAS_IN_DOUT_A_in[42] = (CAS_IN_DOUT_A[42] !== 1'bz) && CAS_IN_DOUT_A_delay[42]; // rv 0 assign CAS_IN_DOUT_A_in[43] = (CAS_IN_DOUT_A[43] !== 1'bz) && CAS_IN_DOUT_A_delay[43]; // rv 0 assign CAS_IN_DOUT_A_in[44] = (CAS_IN_DOUT_A[44] !== 1'bz) && CAS_IN_DOUT_A_delay[44]; // rv 0 assign CAS_IN_DOUT_A_in[45] = (CAS_IN_DOUT_A[45] !== 1'bz) && CAS_IN_DOUT_A_delay[45]; // rv 0 assign CAS_IN_DOUT_A_in[46] = (CAS_IN_DOUT_A[46] !== 1'bz) && CAS_IN_DOUT_A_delay[46]; // rv 0 assign CAS_IN_DOUT_A_in[47] = (CAS_IN_DOUT_A[47] !== 1'bz) && CAS_IN_DOUT_A_delay[47]; // rv 0 assign CAS_IN_DOUT_A_in[48] = (CAS_IN_DOUT_A[48] !== 1'bz) && CAS_IN_DOUT_A_delay[48]; // rv 0 assign CAS_IN_DOUT_A_in[49] = (CAS_IN_DOUT_A[49] !== 1'bz) && CAS_IN_DOUT_A_delay[49]; // rv 0 assign CAS_IN_DOUT_A_in[4] = (CAS_IN_DOUT_A[4] !== 1'bz) && CAS_IN_DOUT_A_delay[4]; // rv 0 assign CAS_IN_DOUT_A_in[50] = (CAS_IN_DOUT_A[50] !== 1'bz) && CAS_IN_DOUT_A_delay[50]; // rv 0 assign CAS_IN_DOUT_A_in[51] = (CAS_IN_DOUT_A[51] !== 1'bz) && CAS_IN_DOUT_A_delay[51]; // rv 0 assign CAS_IN_DOUT_A_in[52] = (CAS_IN_DOUT_A[52] !== 1'bz) && CAS_IN_DOUT_A_delay[52]; // rv 0 assign CAS_IN_DOUT_A_in[53] = (CAS_IN_DOUT_A[53] !== 1'bz) && CAS_IN_DOUT_A_delay[53]; // rv 0 assign CAS_IN_DOUT_A_in[54] = (CAS_IN_DOUT_A[54] !== 1'bz) && CAS_IN_DOUT_A_delay[54]; // rv 0 assign CAS_IN_DOUT_A_in[55] = (CAS_IN_DOUT_A[55] !== 1'bz) && CAS_IN_DOUT_A_delay[55]; // rv 0 assign CAS_IN_DOUT_A_in[56] = (CAS_IN_DOUT_A[56] !== 1'bz) && CAS_IN_DOUT_A_delay[56]; // rv 0 assign CAS_IN_DOUT_A_in[57] = (CAS_IN_DOUT_A[57] !== 1'bz) && CAS_IN_DOUT_A_delay[57]; // rv 0 assign CAS_IN_DOUT_A_in[58] = (CAS_IN_DOUT_A[58] !== 1'bz) && CAS_IN_DOUT_A_delay[58]; // rv 0 assign CAS_IN_DOUT_A_in[59] = (CAS_IN_DOUT_A[59] !== 1'bz) && CAS_IN_DOUT_A_delay[59]; // rv 0 assign CAS_IN_DOUT_A_in[5] = (CAS_IN_DOUT_A[5] !== 1'bz) && CAS_IN_DOUT_A_delay[5]; // rv 0 assign CAS_IN_DOUT_A_in[60] = (CAS_IN_DOUT_A[60] !== 1'bz) && CAS_IN_DOUT_A_delay[60]; // rv 0 assign CAS_IN_DOUT_A_in[61] = (CAS_IN_DOUT_A[61] !== 1'bz) && CAS_IN_DOUT_A_delay[61]; // rv 0 assign CAS_IN_DOUT_A_in[62] = (CAS_IN_DOUT_A[62] !== 1'bz) && CAS_IN_DOUT_A_delay[62]; // rv 0 assign CAS_IN_DOUT_A_in[63] = (CAS_IN_DOUT_A[63] !== 1'bz) && CAS_IN_DOUT_A_delay[63]; // rv 0 assign CAS_IN_DOUT_A_in[64] = (CAS_IN_DOUT_A[64] !== 1'bz) && CAS_IN_DOUT_A_delay[64]; // rv 0 assign CAS_IN_DOUT_A_in[65] = (CAS_IN_DOUT_A[65] !== 1'bz) && CAS_IN_DOUT_A_delay[65]; // rv 0 assign CAS_IN_DOUT_A_in[66] = (CAS_IN_DOUT_A[66] !== 1'bz) && CAS_IN_DOUT_A_delay[66]; // rv 0 assign CAS_IN_DOUT_A_in[67] = (CAS_IN_DOUT_A[67] !== 1'bz) && CAS_IN_DOUT_A_delay[67]; // rv 0 assign CAS_IN_DOUT_A_in[68] = (CAS_IN_DOUT_A[68] !== 1'bz) && CAS_IN_DOUT_A_delay[68]; // rv 0 assign CAS_IN_DOUT_A_in[69] = (CAS_IN_DOUT_A[69] !== 1'bz) && CAS_IN_DOUT_A_delay[69]; // rv 0 assign CAS_IN_DOUT_A_in[6] = (CAS_IN_DOUT_A[6] !== 1'bz) && CAS_IN_DOUT_A_delay[6]; // rv 0 assign CAS_IN_DOUT_A_in[70] = (CAS_IN_DOUT_A[70] !== 1'bz) && CAS_IN_DOUT_A_delay[70]; // rv 0 assign CAS_IN_DOUT_A_in[71] = (CAS_IN_DOUT_A[71] !== 1'bz) && CAS_IN_DOUT_A_delay[71]; // rv 0 assign CAS_IN_DOUT_A_in[7] = (CAS_IN_DOUT_A[7] !== 1'bz) && CAS_IN_DOUT_A_delay[7]; // rv 0 assign CAS_IN_DOUT_A_in[8] = (CAS_IN_DOUT_A[8] !== 1'bz) && CAS_IN_DOUT_A_delay[8]; // rv 0 assign CAS_IN_DOUT_A_in[9] = (CAS_IN_DOUT_A[9] !== 1'bz) && CAS_IN_DOUT_A_delay[9]; // rv 0 assign CAS_IN_DOUT_B_in[0] = (CAS_IN_DOUT_B[0] !== 1'bz) && CAS_IN_DOUT_B_delay[0]; // rv 0 assign CAS_IN_DOUT_B_in[10] = (CAS_IN_DOUT_B[10] !== 1'bz) && CAS_IN_DOUT_B_delay[10]; // rv 0 assign CAS_IN_DOUT_B_in[11] = (CAS_IN_DOUT_B[11] !== 1'bz) && CAS_IN_DOUT_B_delay[11]; // rv 0 assign CAS_IN_DOUT_B_in[12] = (CAS_IN_DOUT_B[12] !== 1'bz) && CAS_IN_DOUT_B_delay[12]; // rv 0 assign CAS_IN_DOUT_B_in[13] = (CAS_IN_DOUT_B[13] !== 1'bz) && CAS_IN_DOUT_B_delay[13]; // rv 0 assign CAS_IN_DOUT_B_in[14] = (CAS_IN_DOUT_B[14] !== 1'bz) && CAS_IN_DOUT_B_delay[14]; // rv 0 assign CAS_IN_DOUT_B_in[15] = (CAS_IN_DOUT_B[15] !== 1'bz) && CAS_IN_DOUT_B_delay[15]; // rv 0 assign CAS_IN_DOUT_B_in[16] = (CAS_IN_DOUT_B[16] !== 1'bz) && CAS_IN_DOUT_B_delay[16]; // rv 0 assign CAS_IN_DOUT_B_in[17] = (CAS_IN_DOUT_B[17] !== 1'bz) && CAS_IN_DOUT_B_delay[17]; // rv 0 assign CAS_IN_DOUT_B_in[18] = (CAS_IN_DOUT_B[18] !== 1'bz) && CAS_IN_DOUT_B_delay[18]; // rv 0 assign CAS_IN_DOUT_B_in[19] = (CAS_IN_DOUT_B[19] !== 1'bz) && CAS_IN_DOUT_B_delay[19]; // rv 0 assign CAS_IN_DOUT_B_in[1] = (CAS_IN_DOUT_B[1] !== 1'bz) && CAS_IN_DOUT_B_delay[1]; // rv 0 assign CAS_IN_DOUT_B_in[20] = (CAS_IN_DOUT_B[20] !== 1'bz) && CAS_IN_DOUT_B_delay[20]; // rv 0 assign CAS_IN_DOUT_B_in[21] = (CAS_IN_DOUT_B[21] !== 1'bz) && CAS_IN_DOUT_B_delay[21]; // rv 0 assign CAS_IN_DOUT_B_in[22] = (CAS_IN_DOUT_B[22] !== 1'bz) && CAS_IN_DOUT_B_delay[22]; // rv 0 assign CAS_IN_DOUT_B_in[23] = (CAS_IN_DOUT_B[23] !== 1'bz) && CAS_IN_DOUT_B_delay[23]; // rv 0 assign CAS_IN_DOUT_B_in[24] = (CAS_IN_DOUT_B[24] !== 1'bz) && CAS_IN_DOUT_B_delay[24]; // rv 0 assign CAS_IN_DOUT_B_in[25] = (CAS_IN_DOUT_B[25] !== 1'bz) && CAS_IN_DOUT_B_delay[25]; // rv 0 assign CAS_IN_DOUT_B_in[26] = (CAS_IN_DOUT_B[26] !== 1'bz) && CAS_IN_DOUT_B_delay[26]; // rv 0 assign CAS_IN_DOUT_B_in[27] = (CAS_IN_DOUT_B[27] !== 1'bz) && CAS_IN_DOUT_B_delay[27]; // rv 0 assign CAS_IN_DOUT_B_in[28] = (CAS_IN_DOUT_B[28] !== 1'bz) && CAS_IN_DOUT_B_delay[28]; // rv 0 assign CAS_IN_DOUT_B_in[29] = (CAS_IN_DOUT_B[29] !== 1'bz) && CAS_IN_DOUT_B_delay[29]; // rv 0 assign CAS_IN_DOUT_B_in[2] = (CAS_IN_DOUT_B[2] !== 1'bz) && CAS_IN_DOUT_B_delay[2]; // rv 0 assign CAS_IN_DOUT_B_in[30] = (CAS_IN_DOUT_B[30] !== 1'bz) && CAS_IN_DOUT_B_delay[30]; // rv 0 assign CAS_IN_DOUT_B_in[31] = (CAS_IN_DOUT_B[31] !== 1'bz) && CAS_IN_DOUT_B_delay[31]; // rv 0 assign CAS_IN_DOUT_B_in[32] = (CAS_IN_DOUT_B[32] !== 1'bz) && CAS_IN_DOUT_B_delay[32]; // rv 0 assign CAS_IN_DOUT_B_in[33] = (CAS_IN_DOUT_B[33] !== 1'bz) && CAS_IN_DOUT_B_delay[33]; // rv 0 assign CAS_IN_DOUT_B_in[34] = (CAS_IN_DOUT_B[34] !== 1'bz) && CAS_IN_DOUT_B_delay[34]; // rv 0 assign CAS_IN_DOUT_B_in[35] = (CAS_IN_DOUT_B[35] !== 1'bz) && CAS_IN_DOUT_B_delay[35]; // rv 0 assign CAS_IN_DOUT_B_in[36] = (CAS_IN_DOUT_B[36] !== 1'bz) && CAS_IN_DOUT_B_delay[36]; // rv 0 assign CAS_IN_DOUT_B_in[37] = (CAS_IN_DOUT_B[37] !== 1'bz) && CAS_IN_DOUT_B_delay[37]; // rv 0 assign CAS_IN_DOUT_B_in[38] = (CAS_IN_DOUT_B[38] !== 1'bz) && CAS_IN_DOUT_B_delay[38]; // rv 0 assign CAS_IN_DOUT_B_in[39] = (CAS_IN_DOUT_B[39] !== 1'bz) && CAS_IN_DOUT_B_delay[39]; // rv 0 assign CAS_IN_DOUT_B_in[3] = (CAS_IN_DOUT_B[3] !== 1'bz) && CAS_IN_DOUT_B_delay[3]; // rv 0 assign CAS_IN_DOUT_B_in[40] = (CAS_IN_DOUT_B[40] !== 1'bz) && CAS_IN_DOUT_B_delay[40]; // rv 0 assign CAS_IN_DOUT_B_in[41] = (CAS_IN_DOUT_B[41] !== 1'bz) && CAS_IN_DOUT_B_delay[41]; // rv 0 assign CAS_IN_DOUT_B_in[42] = (CAS_IN_DOUT_B[42] !== 1'bz) && CAS_IN_DOUT_B_delay[42]; // rv 0 assign CAS_IN_DOUT_B_in[43] = (CAS_IN_DOUT_B[43] !== 1'bz) && CAS_IN_DOUT_B_delay[43]; // rv 0 assign CAS_IN_DOUT_B_in[44] = (CAS_IN_DOUT_B[44] !== 1'bz) && CAS_IN_DOUT_B_delay[44]; // rv 0 assign CAS_IN_DOUT_B_in[45] = (CAS_IN_DOUT_B[45] !== 1'bz) && CAS_IN_DOUT_B_delay[45]; // rv 0 assign CAS_IN_DOUT_B_in[46] = (CAS_IN_DOUT_B[46] !== 1'bz) && CAS_IN_DOUT_B_delay[46]; // rv 0 assign CAS_IN_DOUT_B_in[47] = (CAS_IN_DOUT_B[47] !== 1'bz) && CAS_IN_DOUT_B_delay[47]; // rv 0 assign CAS_IN_DOUT_B_in[48] = (CAS_IN_DOUT_B[48] !== 1'bz) && CAS_IN_DOUT_B_delay[48]; // rv 0 assign CAS_IN_DOUT_B_in[49] = (CAS_IN_DOUT_B[49] !== 1'bz) && CAS_IN_DOUT_B_delay[49]; // rv 0 assign CAS_IN_DOUT_B_in[4] = (CAS_IN_DOUT_B[4] !== 1'bz) && CAS_IN_DOUT_B_delay[4]; // rv 0 assign CAS_IN_DOUT_B_in[50] = (CAS_IN_DOUT_B[50] !== 1'bz) && CAS_IN_DOUT_B_delay[50]; // rv 0 assign CAS_IN_DOUT_B_in[51] = (CAS_IN_DOUT_B[51] !== 1'bz) && CAS_IN_DOUT_B_delay[51]; // rv 0 assign CAS_IN_DOUT_B_in[52] = (CAS_IN_DOUT_B[52] !== 1'bz) && CAS_IN_DOUT_B_delay[52]; // rv 0 assign CAS_IN_DOUT_B_in[53] = (CAS_IN_DOUT_B[53] !== 1'bz) && CAS_IN_DOUT_B_delay[53]; // rv 0 assign CAS_IN_DOUT_B_in[54] = (CAS_IN_DOUT_B[54] !== 1'bz) && CAS_IN_DOUT_B_delay[54]; // rv 0 assign CAS_IN_DOUT_B_in[55] = (CAS_IN_DOUT_B[55] !== 1'bz) && CAS_IN_DOUT_B_delay[55]; // rv 0 assign CAS_IN_DOUT_B_in[56] = (CAS_IN_DOUT_B[56] !== 1'bz) && CAS_IN_DOUT_B_delay[56]; // rv 0 assign CAS_IN_DOUT_B_in[57] = (CAS_IN_DOUT_B[57] !== 1'bz) && CAS_IN_DOUT_B_delay[57]; // rv 0 assign CAS_IN_DOUT_B_in[58] = (CAS_IN_DOUT_B[58] !== 1'bz) && CAS_IN_DOUT_B_delay[58]; // rv 0 assign CAS_IN_DOUT_B_in[59] = (CAS_IN_DOUT_B[59] !== 1'bz) && CAS_IN_DOUT_B_delay[59]; // rv 0 assign CAS_IN_DOUT_B_in[5] = (CAS_IN_DOUT_B[5] !== 1'bz) && CAS_IN_DOUT_B_delay[5]; // rv 0 assign CAS_IN_DOUT_B_in[60] = (CAS_IN_DOUT_B[60] !== 1'bz) && CAS_IN_DOUT_B_delay[60]; // rv 0 assign CAS_IN_DOUT_B_in[61] = (CAS_IN_DOUT_B[61] !== 1'bz) && CAS_IN_DOUT_B_delay[61]; // rv 0 assign CAS_IN_DOUT_B_in[62] = (CAS_IN_DOUT_B[62] !== 1'bz) && CAS_IN_DOUT_B_delay[62]; // rv 0 assign CAS_IN_DOUT_B_in[63] = (CAS_IN_DOUT_B[63] !== 1'bz) && CAS_IN_DOUT_B_delay[63]; // rv 0 assign CAS_IN_DOUT_B_in[64] = (CAS_IN_DOUT_B[64] !== 1'bz) && CAS_IN_DOUT_B_delay[64]; // rv 0 assign CAS_IN_DOUT_B_in[65] = (CAS_IN_DOUT_B[65] !== 1'bz) && CAS_IN_DOUT_B_delay[65]; // rv 0 assign CAS_IN_DOUT_B_in[66] = (CAS_IN_DOUT_B[66] !== 1'bz) && CAS_IN_DOUT_B_delay[66]; // rv 0 assign CAS_IN_DOUT_B_in[67] = (CAS_IN_DOUT_B[67] !== 1'bz) && CAS_IN_DOUT_B_delay[67]; // rv 0 assign CAS_IN_DOUT_B_in[68] = (CAS_IN_DOUT_B[68] !== 1'bz) && CAS_IN_DOUT_B_delay[68]; // rv 0 assign CAS_IN_DOUT_B_in[69] = (CAS_IN_DOUT_B[69] !== 1'bz) && CAS_IN_DOUT_B_delay[69]; // rv 0 assign CAS_IN_DOUT_B_in[6] = (CAS_IN_DOUT_B[6] !== 1'bz) && CAS_IN_DOUT_B_delay[6]; // rv 0 assign CAS_IN_DOUT_B_in[70] = (CAS_IN_DOUT_B[70] !== 1'bz) && CAS_IN_DOUT_B_delay[70]; // rv 0 assign CAS_IN_DOUT_B_in[71] = (CAS_IN_DOUT_B[71] !== 1'bz) && CAS_IN_DOUT_B_delay[71]; // rv 0 assign CAS_IN_DOUT_B_in[7] = (CAS_IN_DOUT_B[7] !== 1'bz) && CAS_IN_DOUT_B_delay[7]; // rv 0 assign CAS_IN_DOUT_B_in[8] = (CAS_IN_DOUT_B[8] !== 1'bz) && CAS_IN_DOUT_B_delay[8]; // rv 0 assign CAS_IN_DOUT_B_in[9] = (CAS_IN_DOUT_B[9] !== 1'bz) && CAS_IN_DOUT_B_delay[9]; // rv 0 assign CAS_IN_EN_A_in = (CAS_IN_EN_A !== 1'bz) && CAS_IN_EN_A_delay; // rv 0 assign CAS_IN_EN_B_in = (CAS_IN_EN_B !== 1'bz) && CAS_IN_EN_B_delay; // rv 0 assign CAS_IN_RDACCESS_A_in = (CAS_IN_RDACCESS_A !== 1'bz) && CAS_IN_RDACCESS_A_delay; // rv 0 assign CAS_IN_RDACCESS_B_in = (CAS_IN_RDACCESS_B !== 1'bz) && CAS_IN_RDACCESS_B_delay; // rv 0 assign CAS_IN_RDB_WR_A_in = (CAS_IN_RDB_WR_A !== 1'bz) && CAS_IN_RDB_WR_A_delay; // rv 0 assign CAS_IN_RDB_WR_B_in = (CAS_IN_RDB_WR_B !== 1'bz) && CAS_IN_RDB_WR_B_delay; // rv 0 assign CAS_IN_SBITERR_A_in = (CAS_IN_SBITERR_A !== 1'bz) && CAS_IN_SBITERR_A_delay; // rv 0 assign CAS_IN_SBITERR_B_in = (CAS_IN_SBITERR_B !== 1'bz) && CAS_IN_SBITERR_B_delay; // rv 0 assign CLK_in = (CLK !== 1'bz) && (CLK_delay ^ IS_CLK_INVERTED_REG); // rv 0 assign DIN_A_in = DIN_A_delay; assign DIN_B_in = DIN_B_delay; assign EN_A_in = (EN_A !== 1'bz) && (EN_A_delay ^ IS_EN_A_INVERTED_REG); // rv 0 assign EN_B_in = (EN_B !== 1'bz) && (EN_B_delay ^ IS_EN_B_INVERTED_REG); // rv 0 assign INJECT_DBITERR_A_in = (INJECT_DBITERR_A !== 1'bz) && INJECT_DBITERR_A_delay; // rv 0 assign INJECT_DBITERR_B_in = (INJECT_DBITERR_B !== 1'bz) && INJECT_DBITERR_B_delay; // rv 0 assign INJECT_SBITERR_A_in = (INJECT_SBITERR_A !== 1'bz) && INJECT_SBITERR_A_delay; // rv 0 assign INJECT_SBITERR_B_in = (INJECT_SBITERR_B !== 1'bz) && INJECT_SBITERR_B_delay; // rv 0 assign OREG_CE_A_in = (OREG_CE_A === 1'bz) || OREG_CE_A_delay; // rv 1 assign OREG_CE_B_in = (OREG_CE_B === 1'bz) || OREG_CE_B_delay; // rv 1 assign OREG_ECC_CE_A_in = (OREG_ECC_CE_A === 1'bz) || OREG_ECC_CE_A_delay; // rv 1 assign OREG_ECC_CE_B_in = (OREG_ECC_CE_B === 1'bz) || OREG_ECC_CE_B_delay; // rv 1 assign RDB_WR_A_in = (RDB_WR_A !== 1'bz) && (RDB_WR_A_delay ^ IS_RDB_WR_A_INVERTED_REG); // rv 0 assign RDB_WR_B_in = (RDB_WR_B !== 1'bz) && (RDB_WR_B_delay ^ IS_RDB_WR_B_INVERTED_REG); // rv 0 assign RST_A_in = (RST_A !== 1'bz) && (RST_A_delay ^ IS_RST_A_INVERTED_REG); // rv 0 assign RST_B_in = (RST_B !== 1'bz) && (RST_B_delay ^ IS_RST_B_INVERTED_REG); // rv 0 assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0 `else assign ADDR_A_in = ADDR_A; assign ADDR_B_in = ADDR_B; assign BWE_A_in[0] = (BWE_A[0] === 1'bz) || BWE_A[0]; // rv 1 assign BWE_A_in[1] = (BWE_A[1] === 1'bz) || BWE_A[1]; // rv 1 assign BWE_A_in[2] = (BWE_A[2] === 1'bz) || BWE_A[2]; // rv 1 assign BWE_A_in[3] = (BWE_A[3] === 1'bz) || BWE_A[3]; // rv 1 assign BWE_A_in[4] = (BWE_A[4] === 1'bz) || BWE_A[4]; // rv 1 assign BWE_A_in[5] = (BWE_A[5] === 1'bz) || BWE_A[5]; // rv 1 assign BWE_A_in[6] = (BWE_A[6] === 1'bz) || BWE_A[6]; // rv 1 assign BWE_A_in[7] = (BWE_A[7] === 1'bz) || BWE_A[7]; // rv 1 assign BWE_A_in[8] = (BWE_A[8] === 1'bz) || BWE_A[8]; // rv 1 assign BWE_B_in[0] = (BWE_B[0] === 1'bz) || BWE_B[0]; // rv 1 assign BWE_B_in[1] = (BWE_B[1] === 1'bz) || BWE_B[1]; // rv 1 assign BWE_B_in[2] = (BWE_B[2] === 1'bz) || BWE_B[2]; // rv 1 assign BWE_B_in[3] = (BWE_B[3] === 1'bz) || BWE_B[3]; // rv 1 assign BWE_B_in[4] = (BWE_B[4] === 1'bz) || BWE_B[4]; // rv 1 assign BWE_B_in[5] = (BWE_B[5] === 1'bz) || BWE_B[5]; // rv 1 assign BWE_B_in[6] = (BWE_B[6] === 1'bz) || BWE_B[6]; // rv 1 assign BWE_B_in[7] = (BWE_B[7] === 1'bz) || BWE_B[7]; // rv 1 assign BWE_B_in[8] = (BWE_B[8] === 1'bz) || BWE_B[8]; // rv 1 assign CAS_IN_ADDR_A_in[0] = (CAS_IN_ADDR_A[0] !== 1'bz) && CAS_IN_ADDR_A[0]; // rv 0 assign CAS_IN_ADDR_A_in[10] = (CAS_IN_ADDR_A[10] !== 1'bz) && CAS_IN_ADDR_A[10]; // rv 0 assign CAS_IN_ADDR_A_in[11] = (CAS_IN_ADDR_A[11] !== 1'bz) && CAS_IN_ADDR_A[11]; // rv 0 assign CAS_IN_ADDR_A_in[12] = (CAS_IN_ADDR_A[12] !== 1'bz) && CAS_IN_ADDR_A[12]; // rv 0 assign CAS_IN_ADDR_A_in[13] = (CAS_IN_ADDR_A[13] !== 1'bz) && CAS_IN_ADDR_A[13]; // rv 0 assign CAS_IN_ADDR_A_in[14] = (CAS_IN_ADDR_A[14] !== 1'bz) && CAS_IN_ADDR_A[14]; // rv 0 assign CAS_IN_ADDR_A_in[15] = (CAS_IN_ADDR_A[15] !== 1'bz) && CAS_IN_ADDR_A[15]; // rv 0 assign CAS_IN_ADDR_A_in[16] = (CAS_IN_ADDR_A[16] !== 1'bz) && CAS_IN_ADDR_A[16]; // rv 0 assign CAS_IN_ADDR_A_in[17] = (CAS_IN_ADDR_A[17] !== 1'bz) && CAS_IN_ADDR_A[17]; // rv 0 assign CAS_IN_ADDR_A_in[18] = (CAS_IN_ADDR_A[18] !== 1'bz) && CAS_IN_ADDR_A[18]; // rv 0 assign CAS_IN_ADDR_A_in[19] = (CAS_IN_ADDR_A[19] !== 1'bz) && CAS_IN_ADDR_A[19]; // rv 0 assign CAS_IN_ADDR_A_in[1] = (CAS_IN_ADDR_A[1] !== 1'bz) && CAS_IN_ADDR_A[1]; // rv 0 assign CAS_IN_ADDR_A_in[20] = (CAS_IN_ADDR_A[20] !== 1'bz) && CAS_IN_ADDR_A[20]; // rv 0 assign CAS_IN_ADDR_A_in[21] = (CAS_IN_ADDR_A[21] !== 1'bz) && CAS_IN_ADDR_A[21]; // rv 0 assign CAS_IN_ADDR_A_in[22] = (CAS_IN_ADDR_A[22] !== 1'bz) && CAS_IN_ADDR_A[22]; // rv 0 assign CAS_IN_ADDR_A_in[2] = (CAS_IN_ADDR_A[2] !== 1'bz) && CAS_IN_ADDR_A[2]; // rv 0 assign CAS_IN_ADDR_A_in[3] = (CAS_IN_ADDR_A[3] !== 1'bz) && CAS_IN_ADDR_A[3]; // rv 0 assign CAS_IN_ADDR_A_in[4] = (CAS_IN_ADDR_A[4] !== 1'bz) && CAS_IN_ADDR_A[4]; // rv 0 assign CAS_IN_ADDR_A_in[5] = (CAS_IN_ADDR_A[5] !== 1'bz) && CAS_IN_ADDR_A[5]; // rv 0 assign CAS_IN_ADDR_A_in[6] = (CAS_IN_ADDR_A[6] !== 1'bz) && CAS_IN_ADDR_A[6]; // rv 0 assign CAS_IN_ADDR_A_in[7] = (CAS_IN_ADDR_A[7] !== 1'bz) && CAS_IN_ADDR_A[7]; // rv 0 assign CAS_IN_ADDR_A_in[8] = (CAS_IN_ADDR_A[8] !== 1'bz) && CAS_IN_ADDR_A[8]; // rv 0 assign CAS_IN_ADDR_A_in[9] = (CAS_IN_ADDR_A[9] !== 1'bz) && CAS_IN_ADDR_A[9]; // rv 0 assign CAS_IN_ADDR_B_in[0] = (CAS_IN_ADDR_B[0] !== 1'bz) && CAS_IN_ADDR_B[0]; // rv 0 assign CAS_IN_ADDR_B_in[10] = (CAS_IN_ADDR_B[10] !== 1'bz) && CAS_IN_ADDR_B[10]; // rv 0 assign CAS_IN_ADDR_B_in[11] = (CAS_IN_ADDR_B[11] !== 1'bz) && CAS_IN_ADDR_B[11]; // rv 0 assign CAS_IN_ADDR_B_in[12] = (CAS_IN_ADDR_B[12] !== 1'bz) && CAS_IN_ADDR_B[12]; // rv 0 assign CAS_IN_ADDR_B_in[13] = (CAS_IN_ADDR_B[13] !== 1'bz) && CAS_IN_ADDR_B[13]; // rv 0 assign CAS_IN_ADDR_B_in[14] = (CAS_IN_ADDR_B[14] !== 1'bz) && CAS_IN_ADDR_B[14]; // rv 0 assign CAS_IN_ADDR_B_in[15] = (CAS_IN_ADDR_B[15] !== 1'bz) && CAS_IN_ADDR_B[15]; // rv 0 assign CAS_IN_ADDR_B_in[16] = (CAS_IN_ADDR_B[16] !== 1'bz) && CAS_IN_ADDR_B[16]; // rv 0 assign CAS_IN_ADDR_B_in[17] = (CAS_IN_ADDR_B[17] !== 1'bz) && CAS_IN_ADDR_B[17]; // rv 0 assign CAS_IN_ADDR_B_in[18] = (CAS_IN_ADDR_B[18] !== 1'bz) && CAS_IN_ADDR_B[18]; // rv 0 assign CAS_IN_ADDR_B_in[19] = (CAS_IN_ADDR_B[19] !== 1'bz) && CAS_IN_ADDR_B[19]; // rv 0 assign CAS_IN_ADDR_B_in[1] = (CAS_IN_ADDR_B[1] !== 1'bz) && CAS_IN_ADDR_B[1]; // rv 0 assign CAS_IN_ADDR_B_in[20] = (CAS_IN_ADDR_B[20] !== 1'bz) && CAS_IN_ADDR_B[20]; // rv 0 assign CAS_IN_ADDR_B_in[21] = (CAS_IN_ADDR_B[21] !== 1'bz) && CAS_IN_ADDR_B[21]; // rv 0 assign CAS_IN_ADDR_B_in[22] = (CAS_IN_ADDR_B[22] !== 1'bz) && CAS_IN_ADDR_B[22]; // rv 0 assign CAS_IN_ADDR_B_in[2] = (CAS_IN_ADDR_B[2] !== 1'bz) && CAS_IN_ADDR_B[2]; // rv 0 assign CAS_IN_ADDR_B_in[3] = (CAS_IN_ADDR_B[3] !== 1'bz) && CAS_IN_ADDR_B[3]; // rv 0 assign CAS_IN_ADDR_B_in[4] = (CAS_IN_ADDR_B[4] !== 1'bz) && CAS_IN_ADDR_B[4]; // rv 0 assign CAS_IN_ADDR_B_in[5] = (CAS_IN_ADDR_B[5] !== 1'bz) && CAS_IN_ADDR_B[5]; // rv 0 assign CAS_IN_ADDR_B_in[6] = (CAS_IN_ADDR_B[6] !== 1'bz) && CAS_IN_ADDR_B[6]; // rv 0 assign CAS_IN_ADDR_B_in[7] = (CAS_IN_ADDR_B[7] !== 1'bz) && CAS_IN_ADDR_B[7]; // rv 0 assign CAS_IN_ADDR_B_in[8] = (CAS_IN_ADDR_B[8] !== 1'bz) && CAS_IN_ADDR_B[8]; // rv 0 assign CAS_IN_ADDR_B_in[9] = (CAS_IN_ADDR_B[9] !== 1'bz) && CAS_IN_ADDR_B[9]; // rv 0 assign CAS_IN_BWE_A_in[0] = (CAS_IN_BWE_A[0] !== 1'bz) && CAS_IN_BWE_A[0]; // rv 0 assign CAS_IN_BWE_A_in[1] = (CAS_IN_BWE_A[1] !== 1'bz) && CAS_IN_BWE_A[1]; // rv 0 assign CAS_IN_BWE_A_in[2] = (CAS_IN_BWE_A[2] !== 1'bz) && CAS_IN_BWE_A[2]; // rv 0 assign CAS_IN_BWE_A_in[3] = (CAS_IN_BWE_A[3] !== 1'bz) && CAS_IN_BWE_A[3]; // rv 0 assign CAS_IN_BWE_A_in[4] = (CAS_IN_BWE_A[4] !== 1'bz) && CAS_IN_BWE_A[4]; // rv 0 assign CAS_IN_BWE_A_in[5] = (CAS_IN_BWE_A[5] !== 1'bz) && CAS_IN_BWE_A[5]; // rv 0 assign CAS_IN_BWE_A_in[6] = (CAS_IN_BWE_A[6] !== 1'bz) && CAS_IN_BWE_A[6]; // rv 0 assign CAS_IN_BWE_A_in[7] = (CAS_IN_BWE_A[7] !== 1'bz) && CAS_IN_BWE_A[7]; // rv 0 assign CAS_IN_BWE_A_in[8] = (CAS_IN_BWE_A[8] !== 1'bz) && CAS_IN_BWE_A[8]; // rv 0 assign CAS_IN_BWE_B_in[0] = (CAS_IN_BWE_B[0] !== 1'bz) && CAS_IN_BWE_B[0]; // rv 0 assign CAS_IN_BWE_B_in[1] = (CAS_IN_BWE_B[1] !== 1'bz) && CAS_IN_BWE_B[1]; // rv 0 assign CAS_IN_BWE_B_in[2] = (CAS_IN_BWE_B[2] !== 1'bz) && CAS_IN_BWE_B[2]; // rv 0 assign CAS_IN_BWE_B_in[3] = (CAS_IN_BWE_B[3] !== 1'bz) && CAS_IN_BWE_B[3]; // rv 0 assign CAS_IN_BWE_B_in[4] = (CAS_IN_BWE_B[4] !== 1'bz) && CAS_IN_BWE_B[4]; // rv 0 assign CAS_IN_BWE_B_in[5] = (CAS_IN_BWE_B[5] !== 1'bz) && CAS_IN_BWE_B[5]; // rv 0 assign CAS_IN_BWE_B_in[6] = (CAS_IN_BWE_B[6] !== 1'bz) && CAS_IN_BWE_B[6]; // rv 0 assign CAS_IN_BWE_B_in[7] = (CAS_IN_BWE_B[7] !== 1'bz) && CAS_IN_BWE_B[7]; // rv 0 assign CAS_IN_BWE_B_in[8] = (CAS_IN_BWE_B[8] !== 1'bz) && CAS_IN_BWE_B[8]; // rv 0 assign CAS_IN_DBITERR_A_in = (CAS_IN_DBITERR_A !== 1'bz) && CAS_IN_DBITERR_A; // rv 0 assign CAS_IN_DBITERR_B_in = (CAS_IN_DBITERR_B !== 1'bz) && CAS_IN_DBITERR_B; // rv 0 assign CAS_IN_DIN_A_in[0] = (CAS_IN_DIN_A[0] !== 1'bz) && CAS_IN_DIN_A[0]; // rv 0 assign CAS_IN_DIN_A_in[10] = (CAS_IN_DIN_A[10] !== 1'bz) && CAS_IN_DIN_A[10]; // rv 0 assign CAS_IN_DIN_A_in[11] = (CAS_IN_DIN_A[11] !== 1'bz) && CAS_IN_DIN_A[11]; // rv 0 assign CAS_IN_DIN_A_in[12] = (CAS_IN_DIN_A[12] !== 1'bz) && CAS_IN_DIN_A[12]; // rv 0 assign CAS_IN_DIN_A_in[13] = (CAS_IN_DIN_A[13] !== 1'bz) && CAS_IN_DIN_A[13]; // rv 0 assign CAS_IN_DIN_A_in[14] = (CAS_IN_DIN_A[14] !== 1'bz) && CAS_IN_DIN_A[14]; // rv 0 assign CAS_IN_DIN_A_in[15] = (CAS_IN_DIN_A[15] !== 1'bz) && CAS_IN_DIN_A[15]; // rv 0 assign CAS_IN_DIN_A_in[16] = (CAS_IN_DIN_A[16] !== 1'bz) && CAS_IN_DIN_A[16]; // rv 0 assign CAS_IN_DIN_A_in[17] = (CAS_IN_DIN_A[17] !== 1'bz) && CAS_IN_DIN_A[17]; // rv 0 assign CAS_IN_DIN_A_in[18] = (CAS_IN_DIN_A[18] !== 1'bz) && CAS_IN_DIN_A[18]; // rv 0 assign CAS_IN_DIN_A_in[19] = (CAS_IN_DIN_A[19] !== 1'bz) && CAS_IN_DIN_A[19]; // rv 0 assign CAS_IN_DIN_A_in[1] = (CAS_IN_DIN_A[1] !== 1'bz) && CAS_IN_DIN_A[1]; // rv 0 assign CAS_IN_DIN_A_in[20] = (CAS_IN_DIN_A[20] !== 1'bz) && CAS_IN_DIN_A[20]; // rv 0 assign CAS_IN_DIN_A_in[21] = (CAS_IN_DIN_A[21] !== 1'bz) && CAS_IN_DIN_A[21]; // rv 0 assign CAS_IN_DIN_A_in[22] = (CAS_IN_DIN_A[22] !== 1'bz) && CAS_IN_DIN_A[22]; // rv 0 assign CAS_IN_DIN_A_in[23] = (CAS_IN_DIN_A[23] !== 1'bz) && CAS_IN_DIN_A[23]; // rv 0 assign CAS_IN_DIN_A_in[24] = (CAS_IN_DIN_A[24] !== 1'bz) && CAS_IN_DIN_A[24]; // rv 0 assign CAS_IN_DIN_A_in[25] = (CAS_IN_DIN_A[25] !== 1'bz) && CAS_IN_DIN_A[25]; // rv 0 assign CAS_IN_DIN_A_in[26] = (CAS_IN_DIN_A[26] !== 1'bz) && CAS_IN_DIN_A[26]; // rv 0 assign CAS_IN_DIN_A_in[27] = (CAS_IN_DIN_A[27] !== 1'bz) && CAS_IN_DIN_A[27]; // rv 0 assign CAS_IN_DIN_A_in[28] = (CAS_IN_DIN_A[28] !== 1'bz) && CAS_IN_DIN_A[28]; // rv 0 assign CAS_IN_DIN_A_in[29] = (CAS_IN_DIN_A[29] !== 1'bz) && CAS_IN_DIN_A[29]; // rv 0 assign CAS_IN_DIN_A_in[2] = (CAS_IN_DIN_A[2] !== 1'bz) && CAS_IN_DIN_A[2]; // rv 0 assign CAS_IN_DIN_A_in[30] = (CAS_IN_DIN_A[30] !== 1'bz) && CAS_IN_DIN_A[30]; // rv 0 assign CAS_IN_DIN_A_in[31] = (CAS_IN_DIN_A[31] !== 1'bz) && CAS_IN_DIN_A[31]; // rv 0 assign CAS_IN_DIN_A_in[32] = (CAS_IN_DIN_A[32] !== 1'bz) && CAS_IN_DIN_A[32]; // rv 0 assign CAS_IN_DIN_A_in[33] = (CAS_IN_DIN_A[33] !== 1'bz) && CAS_IN_DIN_A[33]; // rv 0 assign CAS_IN_DIN_A_in[34] = (CAS_IN_DIN_A[34] !== 1'bz) && CAS_IN_DIN_A[34]; // rv 0 assign CAS_IN_DIN_A_in[35] = (CAS_IN_DIN_A[35] !== 1'bz) && CAS_IN_DIN_A[35]; // rv 0 assign CAS_IN_DIN_A_in[36] = (CAS_IN_DIN_A[36] !== 1'bz) && CAS_IN_DIN_A[36]; // rv 0 assign CAS_IN_DIN_A_in[37] = (CAS_IN_DIN_A[37] !== 1'bz) && CAS_IN_DIN_A[37]; // rv 0 assign CAS_IN_DIN_A_in[38] = (CAS_IN_DIN_A[38] !== 1'bz) && CAS_IN_DIN_A[38]; // rv 0 assign CAS_IN_DIN_A_in[39] = (CAS_IN_DIN_A[39] !== 1'bz) && CAS_IN_DIN_A[39]; // rv 0 assign CAS_IN_DIN_A_in[3] = (CAS_IN_DIN_A[3] !== 1'bz) && CAS_IN_DIN_A[3]; // rv 0 assign CAS_IN_DIN_A_in[40] = (CAS_IN_DIN_A[40] !== 1'bz) && CAS_IN_DIN_A[40]; // rv 0 assign CAS_IN_DIN_A_in[41] = (CAS_IN_DIN_A[41] !== 1'bz) && CAS_IN_DIN_A[41]; // rv 0 assign CAS_IN_DIN_A_in[42] = (CAS_IN_DIN_A[42] !== 1'bz) && CAS_IN_DIN_A[42]; // rv 0 assign CAS_IN_DIN_A_in[43] = (CAS_IN_DIN_A[43] !== 1'bz) && CAS_IN_DIN_A[43]; // rv 0 assign CAS_IN_DIN_A_in[44] = (CAS_IN_DIN_A[44] !== 1'bz) && CAS_IN_DIN_A[44]; // rv 0 assign CAS_IN_DIN_A_in[45] = (CAS_IN_DIN_A[45] !== 1'bz) && CAS_IN_DIN_A[45]; // rv 0 assign CAS_IN_DIN_A_in[46] = (CAS_IN_DIN_A[46] !== 1'bz) && CAS_IN_DIN_A[46]; // rv 0 assign CAS_IN_DIN_A_in[47] = (CAS_IN_DIN_A[47] !== 1'bz) && CAS_IN_DIN_A[47]; // rv 0 assign CAS_IN_DIN_A_in[48] = (CAS_IN_DIN_A[48] !== 1'bz) && CAS_IN_DIN_A[48]; // rv 0 assign CAS_IN_DIN_A_in[49] = (CAS_IN_DIN_A[49] !== 1'bz) && CAS_IN_DIN_A[49]; // rv 0 assign CAS_IN_DIN_A_in[4] = (CAS_IN_DIN_A[4] !== 1'bz) && CAS_IN_DIN_A[4]; // rv 0 assign CAS_IN_DIN_A_in[50] = (CAS_IN_DIN_A[50] !== 1'bz) && CAS_IN_DIN_A[50]; // rv 0 assign CAS_IN_DIN_A_in[51] = (CAS_IN_DIN_A[51] !== 1'bz) && CAS_IN_DIN_A[51]; // rv 0 assign CAS_IN_DIN_A_in[52] = (CAS_IN_DIN_A[52] !== 1'bz) && CAS_IN_DIN_A[52]; // rv 0 assign CAS_IN_DIN_A_in[53] = (CAS_IN_DIN_A[53] !== 1'bz) && CAS_IN_DIN_A[53]; // rv 0 assign CAS_IN_DIN_A_in[54] = (CAS_IN_DIN_A[54] !== 1'bz) && CAS_IN_DIN_A[54]; // rv 0 assign CAS_IN_DIN_A_in[55] = (CAS_IN_DIN_A[55] !== 1'bz) && CAS_IN_DIN_A[55]; // rv 0 assign CAS_IN_DIN_A_in[56] = (CAS_IN_DIN_A[56] !== 1'bz) && CAS_IN_DIN_A[56]; // rv 0 assign CAS_IN_DIN_A_in[57] = (CAS_IN_DIN_A[57] !== 1'bz) && CAS_IN_DIN_A[57]; // rv 0 assign CAS_IN_DIN_A_in[58] = (CAS_IN_DIN_A[58] !== 1'bz) && CAS_IN_DIN_A[58]; // rv 0 assign CAS_IN_DIN_A_in[59] = (CAS_IN_DIN_A[59] !== 1'bz) && CAS_IN_DIN_A[59]; // rv 0 assign CAS_IN_DIN_A_in[5] = (CAS_IN_DIN_A[5] !== 1'bz) && CAS_IN_DIN_A[5]; // rv 0 assign CAS_IN_DIN_A_in[60] = (CAS_IN_DIN_A[60] !== 1'bz) && CAS_IN_DIN_A[60]; // rv 0 assign CAS_IN_DIN_A_in[61] = (CAS_IN_DIN_A[61] !== 1'bz) && CAS_IN_DIN_A[61]; // rv 0 assign CAS_IN_DIN_A_in[62] = (CAS_IN_DIN_A[62] !== 1'bz) && CAS_IN_DIN_A[62]; // rv 0 assign CAS_IN_DIN_A_in[63] = (CAS_IN_DIN_A[63] !== 1'bz) && CAS_IN_DIN_A[63]; // rv 0 assign CAS_IN_DIN_A_in[64] = (CAS_IN_DIN_A[64] !== 1'bz) && CAS_IN_DIN_A[64]; // rv 0 assign CAS_IN_DIN_A_in[65] = (CAS_IN_DIN_A[65] !== 1'bz) && CAS_IN_DIN_A[65]; // rv 0 assign CAS_IN_DIN_A_in[66] = (CAS_IN_DIN_A[66] !== 1'bz) && CAS_IN_DIN_A[66]; // rv 0 assign CAS_IN_DIN_A_in[67] = (CAS_IN_DIN_A[67] !== 1'bz) && CAS_IN_DIN_A[67]; // rv 0 assign CAS_IN_DIN_A_in[68] = (CAS_IN_DIN_A[68] !== 1'bz) && CAS_IN_DIN_A[68]; // rv 0 assign CAS_IN_DIN_A_in[69] = (CAS_IN_DIN_A[69] !== 1'bz) && CAS_IN_DIN_A[69]; // rv 0 assign CAS_IN_DIN_A_in[6] = (CAS_IN_DIN_A[6] !== 1'bz) && CAS_IN_DIN_A[6]; // rv 0 assign CAS_IN_DIN_A_in[70] = (CAS_IN_DIN_A[70] !== 1'bz) && CAS_IN_DIN_A[70]; // rv 0 assign CAS_IN_DIN_A_in[71] = (CAS_IN_DIN_A[71] !== 1'bz) && CAS_IN_DIN_A[71]; // rv 0 assign CAS_IN_DIN_A_in[7] = (CAS_IN_DIN_A[7] !== 1'bz) && CAS_IN_DIN_A[7]; // rv 0 assign CAS_IN_DIN_A_in[8] = (CAS_IN_DIN_A[8] !== 1'bz) && CAS_IN_DIN_A[8]; // rv 0 assign CAS_IN_DIN_A_in[9] = (CAS_IN_DIN_A[9] !== 1'bz) && CAS_IN_DIN_A[9]; // rv 0 assign CAS_IN_DIN_B_in[0] = (CAS_IN_DIN_B[0] !== 1'bz) && CAS_IN_DIN_B[0]; // rv 0 assign CAS_IN_DIN_B_in[10] = (CAS_IN_DIN_B[10] !== 1'bz) && CAS_IN_DIN_B[10]; // rv 0 assign CAS_IN_DIN_B_in[11] = (CAS_IN_DIN_B[11] !== 1'bz) && CAS_IN_DIN_B[11]; // rv 0 assign CAS_IN_DIN_B_in[12] = (CAS_IN_DIN_B[12] !== 1'bz) && CAS_IN_DIN_B[12]; // rv 0 assign CAS_IN_DIN_B_in[13] = (CAS_IN_DIN_B[13] !== 1'bz) && CAS_IN_DIN_B[13]; // rv 0 assign CAS_IN_DIN_B_in[14] = (CAS_IN_DIN_B[14] !== 1'bz) && CAS_IN_DIN_B[14]; // rv 0 assign CAS_IN_DIN_B_in[15] = (CAS_IN_DIN_B[15] !== 1'bz) && CAS_IN_DIN_B[15]; // rv 0 assign CAS_IN_DIN_B_in[16] = (CAS_IN_DIN_B[16] !== 1'bz) && CAS_IN_DIN_B[16]; // rv 0 assign CAS_IN_DIN_B_in[17] = (CAS_IN_DIN_B[17] !== 1'bz) && CAS_IN_DIN_B[17]; // rv 0 assign CAS_IN_DIN_B_in[18] = (CAS_IN_DIN_B[18] !== 1'bz) && CAS_IN_DIN_B[18]; // rv 0 assign CAS_IN_DIN_B_in[19] = (CAS_IN_DIN_B[19] !== 1'bz) && CAS_IN_DIN_B[19]; // rv 0 assign CAS_IN_DIN_B_in[1] = (CAS_IN_DIN_B[1] !== 1'bz) && CAS_IN_DIN_B[1]; // rv 0 assign CAS_IN_DIN_B_in[20] = (CAS_IN_DIN_B[20] !== 1'bz) && CAS_IN_DIN_B[20]; // rv 0 assign CAS_IN_DIN_B_in[21] = (CAS_IN_DIN_B[21] !== 1'bz) && CAS_IN_DIN_B[21]; // rv 0 assign CAS_IN_DIN_B_in[22] = (CAS_IN_DIN_B[22] !== 1'bz) && CAS_IN_DIN_B[22]; // rv 0 assign CAS_IN_DIN_B_in[23] = (CAS_IN_DIN_B[23] !== 1'bz) && CAS_IN_DIN_B[23]; // rv 0 assign CAS_IN_DIN_B_in[24] = (CAS_IN_DIN_B[24] !== 1'bz) && CAS_IN_DIN_B[24]; // rv 0 assign CAS_IN_DIN_B_in[25] = (CAS_IN_DIN_B[25] !== 1'bz) && CAS_IN_DIN_B[25]; // rv 0 assign CAS_IN_DIN_B_in[26] = (CAS_IN_DIN_B[26] !== 1'bz) && CAS_IN_DIN_B[26]; // rv 0 assign CAS_IN_DIN_B_in[27] = (CAS_IN_DIN_B[27] !== 1'bz) && CAS_IN_DIN_B[27]; // rv 0 assign CAS_IN_DIN_B_in[28] = (CAS_IN_DIN_B[28] !== 1'bz) && CAS_IN_DIN_B[28]; // rv 0 assign CAS_IN_DIN_B_in[29] = (CAS_IN_DIN_B[29] !== 1'bz) && CAS_IN_DIN_B[29]; // rv 0 assign CAS_IN_DIN_B_in[2] = (CAS_IN_DIN_B[2] !== 1'bz) && CAS_IN_DIN_B[2]; // rv 0 assign CAS_IN_DIN_B_in[30] = (CAS_IN_DIN_B[30] !== 1'bz) && CAS_IN_DIN_B[30]; // rv 0 assign CAS_IN_DIN_B_in[31] = (CAS_IN_DIN_B[31] !== 1'bz) && CAS_IN_DIN_B[31]; // rv 0 assign CAS_IN_DIN_B_in[32] = (CAS_IN_DIN_B[32] !== 1'bz) && CAS_IN_DIN_B[32]; // rv 0 assign CAS_IN_DIN_B_in[33] = (CAS_IN_DIN_B[33] !== 1'bz) && CAS_IN_DIN_B[33]; // rv 0 assign CAS_IN_DIN_B_in[34] = (CAS_IN_DIN_B[34] !== 1'bz) && CAS_IN_DIN_B[34]; // rv 0 assign CAS_IN_DIN_B_in[35] = (CAS_IN_DIN_B[35] !== 1'bz) && CAS_IN_DIN_B[35]; // rv 0 assign CAS_IN_DIN_B_in[36] = (CAS_IN_DIN_B[36] !== 1'bz) && CAS_IN_DIN_B[36]; // rv 0 assign CAS_IN_DIN_B_in[37] = (CAS_IN_DIN_B[37] !== 1'bz) && CAS_IN_DIN_B[37]; // rv 0 assign CAS_IN_DIN_B_in[38] = (CAS_IN_DIN_B[38] !== 1'bz) && CAS_IN_DIN_B[38]; // rv 0 assign CAS_IN_DIN_B_in[39] = (CAS_IN_DIN_B[39] !== 1'bz) && CAS_IN_DIN_B[39]; // rv 0 assign CAS_IN_DIN_B_in[3] = (CAS_IN_DIN_B[3] !== 1'bz) && CAS_IN_DIN_B[3]; // rv 0 assign CAS_IN_DIN_B_in[40] = (CAS_IN_DIN_B[40] !== 1'bz) && CAS_IN_DIN_B[40]; // rv 0 assign CAS_IN_DIN_B_in[41] = (CAS_IN_DIN_B[41] !== 1'bz) && CAS_IN_DIN_B[41]; // rv 0 assign CAS_IN_DIN_B_in[42] = (CAS_IN_DIN_B[42] !== 1'bz) && CAS_IN_DIN_B[42]; // rv 0 assign CAS_IN_DIN_B_in[43] = (CAS_IN_DIN_B[43] !== 1'bz) && CAS_IN_DIN_B[43]; // rv 0 assign CAS_IN_DIN_B_in[44] = (CAS_IN_DIN_B[44] !== 1'bz) && CAS_IN_DIN_B[44]; // rv 0 assign CAS_IN_DIN_B_in[45] = (CAS_IN_DIN_B[45] !== 1'bz) && CAS_IN_DIN_B[45]; // rv 0 assign CAS_IN_DIN_B_in[46] = (CAS_IN_DIN_B[46] !== 1'bz) && CAS_IN_DIN_B[46]; // rv 0 assign CAS_IN_DIN_B_in[47] = (CAS_IN_DIN_B[47] !== 1'bz) && CAS_IN_DIN_B[47]; // rv 0 assign CAS_IN_DIN_B_in[48] = (CAS_IN_DIN_B[48] !== 1'bz) && CAS_IN_DIN_B[48]; // rv 0 assign CAS_IN_DIN_B_in[49] = (CAS_IN_DIN_B[49] !== 1'bz) && CAS_IN_DIN_B[49]; // rv 0 assign CAS_IN_DIN_B_in[4] = (CAS_IN_DIN_B[4] !== 1'bz) && CAS_IN_DIN_B[4]; // rv 0 assign CAS_IN_DIN_B_in[50] = (CAS_IN_DIN_B[50] !== 1'bz) && CAS_IN_DIN_B[50]; // rv 0 assign CAS_IN_DIN_B_in[51] = (CAS_IN_DIN_B[51] !== 1'bz) && CAS_IN_DIN_B[51]; // rv 0 assign CAS_IN_DIN_B_in[52] = (CAS_IN_DIN_B[52] !== 1'bz) && CAS_IN_DIN_B[52]; // rv 0 assign CAS_IN_DIN_B_in[53] = (CAS_IN_DIN_B[53] !== 1'bz) && CAS_IN_DIN_B[53]; // rv 0 assign CAS_IN_DIN_B_in[54] = (CAS_IN_DIN_B[54] !== 1'bz) && CAS_IN_DIN_B[54]; // rv 0 assign CAS_IN_DIN_B_in[55] = (CAS_IN_DIN_B[55] !== 1'bz) && CAS_IN_DIN_B[55]; // rv 0 assign CAS_IN_DIN_B_in[56] = (CAS_IN_DIN_B[56] !== 1'bz) && CAS_IN_DIN_B[56]; // rv 0 assign CAS_IN_DIN_B_in[57] = (CAS_IN_DIN_B[57] !== 1'bz) && CAS_IN_DIN_B[57]; // rv 0 assign CAS_IN_DIN_B_in[58] = (CAS_IN_DIN_B[58] !== 1'bz) && CAS_IN_DIN_B[58]; // rv 0 assign CAS_IN_DIN_B_in[59] = (CAS_IN_DIN_B[59] !== 1'bz) && CAS_IN_DIN_B[59]; // rv 0 assign CAS_IN_DIN_B_in[5] = (CAS_IN_DIN_B[5] !== 1'bz) && CAS_IN_DIN_B[5]; // rv 0 assign CAS_IN_DIN_B_in[60] = (CAS_IN_DIN_B[60] !== 1'bz) && CAS_IN_DIN_B[60]; // rv 0 assign CAS_IN_DIN_B_in[61] = (CAS_IN_DIN_B[61] !== 1'bz) && CAS_IN_DIN_B[61]; // rv 0 assign CAS_IN_DIN_B_in[62] = (CAS_IN_DIN_B[62] !== 1'bz) && CAS_IN_DIN_B[62]; // rv 0 assign CAS_IN_DIN_B_in[63] = (CAS_IN_DIN_B[63] !== 1'bz) && CAS_IN_DIN_B[63]; // rv 0 assign CAS_IN_DIN_B_in[64] = (CAS_IN_DIN_B[64] !== 1'bz) && CAS_IN_DIN_B[64]; // rv 0 assign CAS_IN_DIN_B_in[65] = (CAS_IN_DIN_B[65] !== 1'bz) && CAS_IN_DIN_B[65]; // rv 0 assign CAS_IN_DIN_B_in[66] = (CAS_IN_DIN_B[66] !== 1'bz) && CAS_IN_DIN_B[66]; // rv 0 assign CAS_IN_DIN_B_in[67] = (CAS_IN_DIN_B[67] !== 1'bz) && CAS_IN_DIN_B[67]; // rv 0 assign CAS_IN_DIN_B_in[68] = (CAS_IN_DIN_B[68] !== 1'bz) && CAS_IN_DIN_B[68]; // rv 0 assign CAS_IN_DIN_B_in[69] = (CAS_IN_DIN_B[69] !== 1'bz) && CAS_IN_DIN_B[69]; // rv 0 assign CAS_IN_DIN_B_in[6] = (CAS_IN_DIN_B[6] !== 1'bz) && CAS_IN_DIN_B[6]; // rv 0 assign CAS_IN_DIN_B_in[70] = (CAS_IN_DIN_B[70] !== 1'bz) && CAS_IN_DIN_B[70]; // rv 0 assign CAS_IN_DIN_B_in[71] = (CAS_IN_DIN_B[71] !== 1'bz) && CAS_IN_DIN_B[71]; // rv 0 assign CAS_IN_DIN_B_in[7] = (CAS_IN_DIN_B[7] !== 1'bz) && CAS_IN_DIN_B[7]; // rv 0 assign CAS_IN_DIN_B_in[8] = (CAS_IN_DIN_B[8] !== 1'bz) && CAS_IN_DIN_B[8]; // rv 0 assign CAS_IN_DIN_B_in[9] = (CAS_IN_DIN_B[9] !== 1'bz) && CAS_IN_DIN_B[9]; // rv 0 assign CAS_IN_DOUT_A_in[0] = (CAS_IN_DOUT_A[0] !== 1'bz) && CAS_IN_DOUT_A[0]; // rv 0 assign CAS_IN_DOUT_A_in[10] = (CAS_IN_DOUT_A[10] !== 1'bz) && CAS_IN_DOUT_A[10]; // rv 0 assign CAS_IN_DOUT_A_in[11] = (CAS_IN_DOUT_A[11] !== 1'bz) && CAS_IN_DOUT_A[11]; // rv 0 assign CAS_IN_DOUT_A_in[12] = (CAS_IN_DOUT_A[12] !== 1'bz) && CAS_IN_DOUT_A[12]; // rv 0 assign CAS_IN_DOUT_A_in[13] = (CAS_IN_DOUT_A[13] !== 1'bz) && CAS_IN_DOUT_A[13]; // rv 0 assign CAS_IN_DOUT_A_in[14] = (CAS_IN_DOUT_A[14] !== 1'bz) && CAS_IN_DOUT_A[14]; // rv 0 assign CAS_IN_DOUT_A_in[15] = (CAS_IN_DOUT_A[15] !== 1'bz) && CAS_IN_DOUT_A[15]; // rv 0 assign CAS_IN_DOUT_A_in[16] = (CAS_IN_DOUT_A[16] !== 1'bz) && CAS_IN_DOUT_A[16]; // rv 0 assign CAS_IN_DOUT_A_in[17] = (CAS_IN_DOUT_A[17] !== 1'bz) && CAS_IN_DOUT_A[17]; // rv 0 assign CAS_IN_DOUT_A_in[18] = (CAS_IN_DOUT_A[18] !== 1'bz) && CAS_IN_DOUT_A[18]; // rv 0 assign CAS_IN_DOUT_A_in[19] = (CAS_IN_DOUT_A[19] !== 1'bz) && CAS_IN_DOUT_A[19]; // rv 0 assign CAS_IN_DOUT_A_in[1] = (CAS_IN_DOUT_A[1] !== 1'bz) && CAS_IN_DOUT_A[1]; // rv 0 assign CAS_IN_DOUT_A_in[20] = (CAS_IN_DOUT_A[20] !== 1'bz) && CAS_IN_DOUT_A[20]; // rv 0 assign CAS_IN_DOUT_A_in[21] = (CAS_IN_DOUT_A[21] !== 1'bz) && CAS_IN_DOUT_A[21]; // rv 0 assign CAS_IN_DOUT_A_in[22] = (CAS_IN_DOUT_A[22] !== 1'bz) && CAS_IN_DOUT_A[22]; // rv 0 assign CAS_IN_DOUT_A_in[23] = (CAS_IN_DOUT_A[23] !== 1'bz) && CAS_IN_DOUT_A[23]; // rv 0 assign CAS_IN_DOUT_A_in[24] = (CAS_IN_DOUT_A[24] !== 1'bz) && CAS_IN_DOUT_A[24]; // rv 0 assign CAS_IN_DOUT_A_in[25] = (CAS_IN_DOUT_A[25] !== 1'bz) && CAS_IN_DOUT_A[25]; // rv 0 assign CAS_IN_DOUT_A_in[26] = (CAS_IN_DOUT_A[26] !== 1'bz) && CAS_IN_DOUT_A[26]; // rv 0 assign CAS_IN_DOUT_A_in[27] = (CAS_IN_DOUT_A[27] !== 1'bz) && CAS_IN_DOUT_A[27]; // rv 0 assign CAS_IN_DOUT_A_in[28] = (CAS_IN_DOUT_A[28] !== 1'bz) && CAS_IN_DOUT_A[28]; // rv 0 assign CAS_IN_DOUT_A_in[29] = (CAS_IN_DOUT_A[29] !== 1'bz) && CAS_IN_DOUT_A[29]; // rv 0 assign CAS_IN_DOUT_A_in[2] = (CAS_IN_DOUT_A[2] !== 1'bz) && CAS_IN_DOUT_A[2]; // rv 0 assign CAS_IN_DOUT_A_in[30] = (CAS_IN_DOUT_A[30] !== 1'bz) && CAS_IN_DOUT_A[30]; // rv 0 assign CAS_IN_DOUT_A_in[31] = (CAS_IN_DOUT_A[31] !== 1'bz) && CAS_IN_DOUT_A[31]; // rv 0 assign CAS_IN_DOUT_A_in[32] = (CAS_IN_DOUT_A[32] !== 1'bz) && CAS_IN_DOUT_A[32]; // rv 0 assign CAS_IN_DOUT_A_in[33] = (CAS_IN_DOUT_A[33] !== 1'bz) && CAS_IN_DOUT_A[33]; // rv 0 assign CAS_IN_DOUT_A_in[34] = (CAS_IN_DOUT_A[34] !== 1'bz) && CAS_IN_DOUT_A[34]; // rv 0 assign CAS_IN_DOUT_A_in[35] = (CAS_IN_DOUT_A[35] !== 1'bz) && CAS_IN_DOUT_A[35]; // rv 0 assign CAS_IN_DOUT_A_in[36] = (CAS_IN_DOUT_A[36] !== 1'bz) && CAS_IN_DOUT_A[36]; // rv 0 assign CAS_IN_DOUT_A_in[37] = (CAS_IN_DOUT_A[37] !== 1'bz) && CAS_IN_DOUT_A[37]; // rv 0 assign CAS_IN_DOUT_A_in[38] = (CAS_IN_DOUT_A[38] !== 1'bz) && CAS_IN_DOUT_A[38]; // rv 0 assign CAS_IN_DOUT_A_in[39] = (CAS_IN_DOUT_A[39] !== 1'bz) && CAS_IN_DOUT_A[39]; // rv 0 assign CAS_IN_DOUT_A_in[3] = (CAS_IN_DOUT_A[3] !== 1'bz) && CAS_IN_DOUT_A[3]; // rv 0 assign CAS_IN_DOUT_A_in[40] = (CAS_IN_DOUT_A[40] !== 1'bz) && CAS_IN_DOUT_A[40]; // rv 0 assign CAS_IN_DOUT_A_in[41] = (CAS_IN_DOUT_A[41] !== 1'bz) && CAS_IN_DOUT_A[41]; // rv 0 assign CAS_IN_DOUT_A_in[42] = (CAS_IN_DOUT_A[42] !== 1'bz) && CAS_IN_DOUT_A[42]; // rv 0 assign CAS_IN_DOUT_A_in[43] = (CAS_IN_DOUT_A[43] !== 1'bz) && CAS_IN_DOUT_A[43]; // rv 0 assign CAS_IN_DOUT_A_in[44] = (CAS_IN_DOUT_A[44] !== 1'bz) && CAS_IN_DOUT_A[44]; // rv 0 assign CAS_IN_DOUT_A_in[45] = (CAS_IN_DOUT_A[45] !== 1'bz) && CAS_IN_DOUT_A[45]; // rv 0 assign CAS_IN_DOUT_A_in[46] = (CAS_IN_DOUT_A[46] !== 1'bz) && CAS_IN_DOUT_A[46]; // rv 0 assign CAS_IN_DOUT_A_in[47] = (CAS_IN_DOUT_A[47] !== 1'bz) && CAS_IN_DOUT_A[47]; // rv 0 assign CAS_IN_DOUT_A_in[48] = (CAS_IN_DOUT_A[48] !== 1'bz) && CAS_IN_DOUT_A[48]; // rv 0 assign CAS_IN_DOUT_A_in[49] = (CAS_IN_DOUT_A[49] !== 1'bz) && CAS_IN_DOUT_A[49]; // rv 0 assign CAS_IN_DOUT_A_in[4] = (CAS_IN_DOUT_A[4] !== 1'bz) && CAS_IN_DOUT_A[4]; // rv 0 assign CAS_IN_DOUT_A_in[50] = (CAS_IN_DOUT_A[50] !== 1'bz) && CAS_IN_DOUT_A[50]; // rv 0 assign CAS_IN_DOUT_A_in[51] = (CAS_IN_DOUT_A[51] !== 1'bz) && CAS_IN_DOUT_A[51]; // rv 0 assign CAS_IN_DOUT_A_in[52] = (CAS_IN_DOUT_A[52] !== 1'bz) && CAS_IN_DOUT_A[52]; // rv 0 assign CAS_IN_DOUT_A_in[53] = (CAS_IN_DOUT_A[53] !== 1'bz) && CAS_IN_DOUT_A[53]; // rv 0 assign CAS_IN_DOUT_A_in[54] = (CAS_IN_DOUT_A[54] !== 1'bz) && CAS_IN_DOUT_A[54]; // rv 0 assign CAS_IN_DOUT_A_in[55] = (CAS_IN_DOUT_A[55] !== 1'bz) && CAS_IN_DOUT_A[55]; // rv 0 assign CAS_IN_DOUT_A_in[56] = (CAS_IN_DOUT_A[56] !== 1'bz) && CAS_IN_DOUT_A[56]; // rv 0 assign CAS_IN_DOUT_A_in[57] = (CAS_IN_DOUT_A[57] !== 1'bz) && CAS_IN_DOUT_A[57]; // rv 0 assign CAS_IN_DOUT_A_in[58] = (CAS_IN_DOUT_A[58] !== 1'bz) && CAS_IN_DOUT_A[58]; // rv 0 assign CAS_IN_DOUT_A_in[59] = (CAS_IN_DOUT_A[59] !== 1'bz) && CAS_IN_DOUT_A[59]; // rv 0 assign CAS_IN_DOUT_A_in[5] = (CAS_IN_DOUT_A[5] !== 1'bz) && CAS_IN_DOUT_A[5]; // rv 0 assign CAS_IN_DOUT_A_in[60] = (CAS_IN_DOUT_A[60] !== 1'bz) && CAS_IN_DOUT_A[60]; // rv 0 assign CAS_IN_DOUT_A_in[61] = (CAS_IN_DOUT_A[61] !== 1'bz) && CAS_IN_DOUT_A[61]; // rv 0 assign CAS_IN_DOUT_A_in[62] = (CAS_IN_DOUT_A[62] !== 1'bz) && CAS_IN_DOUT_A[62]; // rv 0 assign CAS_IN_DOUT_A_in[63] = (CAS_IN_DOUT_A[63] !== 1'bz) && CAS_IN_DOUT_A[63]; // rv 0 assign CAS_IN_DOUT_A_in[64] = (CAS_IN_DOUT_A[64] !== 1'bz) && CAS_IN_DOUT_A[64]; // rv 0 assign CAS_IN_DOUT_A_in[65] = (CAS_IN_DOUT_A[65] !== 1'bz) && CAS_IN_DOUT_A[65]; // rv 0 assign CAS_IN_DOUT_A_in[66] = (CAS_IN_DOUT_A[66] !== 1'bz) && CAS_IN_DOUT_A[66]; // rv 0 assign CAS_IN_DOUT_A_in[67] = (CAS_IN_DOUT_A[67] !== 1'bz) && CAS_IN_DOUT_A[67]; // rv 0 assign CAS_IN_DOUT_A_in[68] = (CAS_IN_DOUT_A[68] !== 1'bz) && CAS_IN_DOUT_A[68]; // rv 0 assign CAS_IN_DOUT_A_in[69] = (CAS_IN_DOUT_A[69] !== 1'bz) && CAS_IN_DOUT_A[69]; // rv 0 assign CAS_IN_DOUT_A_in[6] = (CAS_IN_DOUT_A[6] !== 1'bz) && CAS_IN_DOUT_A[6]; // rv 0 assign CAS_IN_DOUT_A_in[70] = (CAS_IN_DOUT_A[70] !== 1'bz) && CAS_IN_DOUT_A[70]; // rv 0 assign CAS_IN_DOUT_A_in[71] = (CAS_IN_DOUT_A[71] !== 1'bz) && CAS_IN_DOUT_A[71]; // rv 0 assign CAS_IN_DOUT_A_in[7] = (CAS_IN_DOUT_A[7] !== 1'bz) && CAS_IN_DOUT_A[7]; // rv 0 assign CAS_IN_DOUT_A_in[8] = (CAS_IN_DOUT_A[8] !== 1'bz) && CAS_IN_DOUT_A[8]; // rv 0 assign CAS_IN_DOUT_A_in[9] = (CAS_IN_DOUT_A[9] !== 1'bz) && CAS_IN_DOUT_A[9]; // rv 0 assign CAS_IN_DOUT_B_in[0] = (CAS_IN_DOUT_B[0] !== 1'bz) && CAS_IN_DOUT_B[0]; // rv 0 assign CAS_IN_DOUT_B_in[10] = (CAS_IN_DOUT_B[10] !== 1'bz) && CAS_IN_DOUT_B[10]; // rv 0 assign CAS_IN_DOUT_B_in[11] = (CAS_IN_DOUT_B[11] !== 1'bz) && CAS_IN_DOUT_B[11]; // rv 0 assign CAS_IN_DOUT_B_in[12] = (CAS_IN_DOUT_B[12] !== 1'bz) && CAS_IN_DOUT_B[12]; // rv 0 assign CAS_IN_DOUT_B_in[13] = (CAS_IN_DOUT_B[13] !== 1'bz) && CAS_IN_DOUT_B[13]; // rv 0 assign CAS_IN_DOUT_B_in[14] = (CAS_IN_DOUT_B[14] !== 1'bz) && CAS_IN_DOUT_B[14]; // rv 0 assign CAS_IN_DOUT_B_in[15] = (CAS_IN_DOUT_B[15] !== 1'bz) && CAS_IN_DOUT_B[15]; // rv 0 assign CAS_IN_DOUT_B_in[16] = (CAS_IN_DOUT_B[16] !== 1'bz) && CAS_IN_DOUT_B[16]; // rv 0 assign CAS_IN_DOUT_B_in[17] = (CAS_IN_DOUT_B[17] !== 1'bz) && CAS_IN_DOUT_B[17]; // rv 0 assign CAS_IN_DOUT_B_in[18] = (CAS_IN_DOUT_B[18] !== 1'bz) && CAS_IN_DOUT_B[18]; // rv 0 assign CAS_IN_DOUT_B_in[19] = (CAS_IN_DOUT_B[19] !== 1'bz) && CAS_IN_DOUT_B[19]; // rv 0 assign CAS_IN_DOUT_B_in[1] = (CAS_IN_DOUT_B[1] !== 1'bz) && CAS_IN_DOUT_B[1]; // rv 0 assign CAS_IN_DOUT_B_in[20] = (CAS_IN_DOUT_B[20] !== 1'bz) && CAS_IN_DOUT_B[20]; // rv 0 assign CAS_IN_DOUT_B_in[21] = (CAS_IN_DOUT_B[21] !== 1'bz) && CAS_IN_DOUT_B[21]; // rv 0 assign CAS_IN_DOUT_B_in[22] = (CAS_IN_DOUT_B[22] !== 1'bz) && CAS_IN_DOUT_B[22]; // rv 0 assign CAS_IN_DOUT_B_in[23] = (CAS_IN_DOUT_B[23] !== 1'bz) && CAS_IN_DOUT_B[23]; // rv 0 assign CAS_IN_DOUT_B_in[24] = (CAS_IN_DOUT_B[24] !== 1'bz) && CAS_IN_DOUT_B[24]; // rv 0 assign CAS_IN_DOUT_B_in[25] = (CAS_IN_DOUT_B[25] !== 1'bz) && CAS_IN_DOUT_B[25]; // rv 0 assign CAS_IN_DOUT_B_in[26] = (CAS_IN_DOUT_B[26] !== 1'bz) && CAS_IN_DOUT_B[26]; // rv 0 assign CAS_IN_DOUT_B_in[27] = (CAS_IN_DOUT_B[27] !== 1'bz) && CAS_IN_DOUT_B[27]; // rv 0 assign CAS_IN_DOUT_B_in[28] = (CAS_IN_DOUT_B[28] !== 1'bz) && CAS_IN_DOUT_B[28]; // rv 0 assign CAS_IN_DOUT_B_in[29] = (CAS_IN_DOUT_B[29] !== 1'bz) && CAS_IN_DOUT_B[29]; // rv 0 assign CAS_IN_DOUT_B_in[2] = (CAS_IN_DOUT_B[2] !== 1'bz) && CAS_IN_DOUT_B[2]; // rv 0 assign CAS_IN_DOUT_B_in[30] = (CAS_IN_DOUT_B[30] !== 1'bz) && CAS_IN_DOUT_B[30]; // rv 0 assign CAS_IN_DOUT_B_in[31] = (CAS_IN_DOUT_B[31] !== 1'bz) && CAS_IN_DOUT_B[31]; // rv 0 assign CAS_IN_DOUT_B_in[32] = (CAS_IN_DOUT_B[32] !== 1'bz) && CAS_IN_DOUT_B[32]; // rv 0 assign CAS_IN_DOUT_B_in[33] = (CAS_IN_DOUT_B[33] !== 1'bz) && CAS_IN_DOUT_B[33]; // rv 0 assign CAS_IN_DOUT_B_in[34] = (CAS_IN_DOUT_B[34] !== 1'bz) && CAS_IN_DOUT_B[34]; // rv 0 assign CAS_IN_DOUT_B_in[35] = (CAS_IN_DOUT_B[35] !== 1'bz) && CAS_IN_DOUT_B[35]; // rv 0 assign CAS_IN_DOUT_B_in[36] = (CAS_IN_DOUT_B[36] !== 1'bz) && CAS_IN_DOUT_B[36]; // rv 0 assign CAS_IN_DOUT_B_in[37] = (CAS_IN_DOUT_B[37] !== 1'bz) && CAS_IN_DOUT_B[37]; // rv 0 assign CAS_IN_DOUT_B_in[38] = (CAS_IN_DOUT_B[38] !== 1'bz) && CAS_IN_DOUT_B[38]; // rv 0 assign CAS_IN_DOUT_B_in[39] = (CAS_IN_DOUT_B[39] !== 1'bz) && CAS_IN_DOUT_B[39]; // rv 0 assign CAS_IN_DOUT_B_in[3] = (CAS_IN_DOUT_B[3] !== 1'bz) && CAS_IN_DOUT_B[3]; // rv 0 assign CAS_IN_DOUT_B_in[40] = (CAS_IN_DOUT_B[40] !== 1'bz) && CAS_IN_DOUT_B[40]; // rv 0 assign CAS_IN_DOUT_B_in[41] = (CAS_IN_DOUT_B[41] !== 1'bz) && CAS_IN_DOUT_B[41]; // rv 0 assign CAS_IN_DOUT_B_in[42] = (CAS_IN_DOUT_B[42] !== 1'bz) && CAS_IN_DOUT_B[42]; // rv 0 assign CAS_IN_DOUT_B_in[43] = (CAS_IN_DOUT_B[43] !== 1'bz) && CAS_IN_DOUT_B[43]; // rv 0 assign CAS_IN_DOUT_B_in[44] = (CAS_IN_DOUT_B[44] !== 1'bz) && CAS_IN_DOUT_B[44]; // rv 0 assign CAS_IN_DOUT_B_in[45] = (CAS_IN_DOUT_B[45] !== 1'bz) && CAS_IN_DOUT_B[45]; // rv 0 assign CAS_IN_DOUT_B_in[46] = (CAS_IN_DOUT_B[46] !== 1'bz) && CAS_IN_DOUT_B[46]; // rv 0 assign CAS_IN_DOUT_B_in[47] = (CAS_IN_DOUT_B[47] !== 1'bz) && CAS_IN_DOUT_B[47]; // rv 0 assign CAS_IN_DOUT_B_in[48] = (CAS_IN_DOUT_B[48] !== 1'bz) && CAS_IN_DOUT_B[48]; // rv 0 assign CAS_IN_DOUT_B_in[49] = (CAS_IN_DOUT_B[49] !== 1'bz) && CAS_IN_DOUT_B[49]; // rv 0 assign CAS_IN_DOUT_B_in[4] = (CAS_IN_DOUT_B[4] !== 1'bz) && CAS_IN_DOUT_B[4]; // rv 0 assign CAS_IN_DOUT_B_in[50] = (CAS_IN_DOUT_B[50] !== 1'bz) && CAS_IN_DOUT_B[50]; // rv 0 assign CAS_IN_DOUT_B_in[51] = (CAS_IN_DOUT_B[51] !== 1'bz) && CAS_IN_DOUT_B[51]; // rv 0 assign CAS_IN_DOUT_B_in[52] = (CAS_IN_DOUT_B[52] !== 1'bz) && CAS_IN_DOUT_B[52]; // rv 0 assign CAS_IN_DOUT_B_in[53] = (CAS_IN_DOUT_B[53] !== 1'bz) && CAS_IN_DOUT_B[53]; // rv 0 assign CAS_IN_DOUT_B_in[54] = (CAS_IN_DOUT_B[54] !== 1'bz) && CAS_IN_DOUT_B[54]; // rv 0 assign CAS_IN_DOUT_B_in[55] = (CAS_IN_DOUT_B[55] !== 1'bz) && CAS_IN_DOUT_B[55]; // rv 0 assign CAS_IN_DOUT_B_in[56] = (CAS_IN_DOUT_B[56] !== 1'bz) && CAS_IN_DOUT_B[56]; // rv 0 assign CAS_IN_DOUT_B_in[57] = (CAS_IN_DOUT_B[57] !== 1'bz) && CAS_IN_DOUT_B[57]; // rv 0 assign CAS_IN_DOUT_B_in[58] = (CAS_IN_DOUT_B[58] !== 1'bz) && CAS_IN_DOUT_B[58]; // rv 0 assign CAS_IN_DOUT_B_in[59] = (CAS_IN_DOUT_B[59] !== 1'bz) && CAS_IN_DOUT_B[59]; // rv 0 assign CAS_IN_DOUT_B_in[5] = (CAS_IN_DOUT_B[5] !== 1'bz) && CAS_IN_DOUT_B[5]; // rv 0 assign CAS_IN_DOUT_B_in[60] = (CAS_IN_DOUT_B[60] !== 1'bz) && CAS_IN_DOUT_B[60]; // rv 0 assign CAS_IN_DOUT_B_in[61] = (CAS_IN_DOUT_B[61] !== 1'bz) && CAS_IN_DOUT_B[61]; // rv 0 assign CAS_IN_DOUT_B_in[62] = (CAS_IN_DOUT_B[62] !== 1'bz) && CAS_IN_DOUT_B[62]; // rv 0 assign CAS_IN_DOUT_B_in[63] = (CAS_IN_DOUT_B[63] !== 1'bz) && CAS_IN_DOUT_B[63]; // rv 0 assign CAS_IN_DOUT_B_in[64] = (CAS_IN_DOUT_B[64] !== 1'bz) && CAS_IN_DOUT_B[64]; // rv 0 assign CAS_IN_DOUT_B_in[65] = (CAS_IN_DOUT_B[65] !== 1'bz) && CAS_IN_DOUT_B[65]; // rv 0 assign CAS_IN_DOUT_B_in[66] = (CAS_IN_DOUT_B[66] !== 1'bz) && CAS_IN_DOUT_B[66]; // rv 0 assign CAS_IN_DOUT_B_in[67] = (CAS_IN_DOUT_B[67] !== 1'bz) && CAS_IN_DOUT_B[67]; // rv 0 assign CAS_IN_DOUT_B_in[68] = (CAS_IN_DOUT_B[68] !== 1'bz) && CAS_IN_DOUT_B[68]; // rv 0 assign CAS_IN_DOUT_B_in[69] = (CAS_IN_DOUT_B[69] !== 1'bz) && CAS_IN_DOUT_B[69]; // rv 0 assign CAS_IN_DOUT_B_in[6] = (CAS_IN_DOUT_B[6] !== 1'bz) && CAS_IN_DOUT_B[6]; // rv 0 assign CAS_IN_DOUT_B_in[70] = (CAS_IN_DOUT_B[70] !== 1'bz) && CAS_IN_DOUT_B[70]; // rv 0 assign CAS_IN_DOUT_B_in[71] = (CAS_IN_DOUT_B[71] !== 1'bz) && CAS_IN_DOUT_B[71]; // rv 0 assign CAS_IN_DOUT_B_in[7] = (CAS_IN_DOUT_B[7] !== 1'bz) && CAS_IN_DOUT_B[7]; // rv 0 assign CAS_IN_DOUT_B_in[8] = (CAS_IN_DOUT_B[8] !== 1'bz) && CAS_IN_DOUT_B[8]; // rv 0 assign CAS_IN_DOUT_B_in[9] = (CAS_IN_DOUT_B[9] !== 1'bz) && CAS_IN_DOUT_B[9]; // rv 0 assign CAS_IN_EN_A_in = (CAS_IN_EN_A !== 1'bz) && CAS_IN_EN_A; // rv 0 assign CAS_IN_EN_B_in = (CAS_IN_EN_B !== 1'bz) && CAS_IN_EN_B; // rv 0 assign CAS_IN_RDACCESS_A_in = (CAS_IN_RDACCESS_A !== 1'bz) && CAS_IN_RDACCESS_A; // rv 0 assign CAS_IN_RDACCESS_B_in = (CAS_IN_RDACCESS_B !== 1'bz) && CAS_IN_RDACCESS_B; // rv 0 assign CAS_IN_RDB_WR_A_in = (CAS_IN_RDB_WR_A !== 1'bz) && CAS_IN_RDB_WR_A; // rv 0 assign CAS_IN_RDB_WR_B_in = (CAS_IN_RDB_WR_B !== 1'bz) && CAS_IN_RDB_WR_B; // rv 0 assign CAS_IN_SBITERR_A_in = (CAS_IN_SBITERR_A !== 1'bz) && CAS_IN_SBITERR_A; // rv 0 assign CAS_IN_SBITERR_B_in = (CAS_IN_SBITERR_B !== 1'bz) && CAS_IN_SBITERR_B; // rv 0 assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0 assign DIN_A_in = DIN_A; assign DIN_B_in = DIN_B; assign EN_A_in = (EN_A !== 1'bz) && (EN_A ^ IS_EN_A_INVERTED_REG); // rv 0 assign EN_B_in = (EN_B !== 1'bz) && (EN_B ^ IS_EN_B_INVERTED_REG); // rv 0 assign INJECT_DBITERR_A_in = (INJECT_DBITERR_A !== 1'bz) && INJECT_DBITERR_A; // rv 0 assign INJECT_DBITERR_B_in = (INJECT_DBITERR_B !== 1'bz) && INJECT_DBITERR_B; // rv 0 assign INJECT_SBITERR_A_in = (INJECT_SBITERR_A !== 1'bz) && INJECT_SBITERR_A; // rv 0 assign INJECT_SBITERR_B_in = (INJECT_SBITERR_B !== 1'bz) && INJECT_SBITERR_B; // rv 0 assign OREG_CE_A_in = (OREG_CE_A === 1'bz) || OREG_CE_A; // rv 1 assign OREG_CE_B_in = (OREG_CE_B === 1'bz) || OREG_CE_B; // rv 1 assign OREG_ECC_CE_A_in = (OREG_ECC_CE_A === 1'bz) || OREG_ECC_CE_A; // rv 1 assign OREG_ECC_CE_B_in = (OREG_ECC_CE_B === 1'bz) || OREG_ECC_CE_B; // rv 1 assign RDB_WR_A_in = (RDB_WR_A !== 1'bz) && (RDB_WR_A ^ IS_RDB_WR_A_INVERTED_REG); // rv 0 assign RDB_WR_B_in = (RDB_WR_B !== 1'bz) && (RDB_WR_B ^ IS_RDB_WR_B_INVERTED_REG); // rv 0 assign RST_A_in = (RST_A !== 1'bz) && (RST_A ^ IS_RST_A_INVERTED_REG); // rv 0 assign RST_B_in = (RST_B !== 1'bz) && (RST_B ^ IS_RST_B_INVERTED_REG); // rv 0 assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0 `endif `ifndef XIL_XECLIB reg attr_test; reg attr_err; initial begin trig_attr = 1'b0; `ifdef XIL_ATTR_TEST attr_test = 1'b1; `else attr_test = 1'b0; `endif attr_err = 1'b0; #1; trig_attr = ~trig_attr; end `endif `ifdef XIL_XECLIB assign AUTO_SLEEP_LATENCY_BIN = AUTO_SLEEP_LATENCY_REG[3:0]; assign AVG_CONS_INACTIVE_CYCLES_BIN = AVG_CONS_INACTIVE_CYCLES_REG[16:0]; assign BWE_MODE_A_BIN = (BWE_MODE_A_REG == "PARITY_INTERLEAVED") ? BWE_MODE_A_PARITY_INTERLEAVED : (BWE_MODE_A_REG == "PARITY_INDEPENDENT") ? BWE_MODE_A_PARITY_INDEPENDENT : BWE_MODE_A_PARITY_INTERLEAVED; assign BWE_MODE_B_BIN = (BWE_MODE_B_REG == "PARITY_INTERLEAVED") ? BWE_MODE_B_PARITY_INTERLEAVED : (BWE_MODE_B_REG == "PARITY_INDEPENDENT") ? BWE_MODE_B_PARITY_INDEPENDENT : BWE_MODE_B_PARITY_INTERLEAVED; assign CASCADE_ORDER_A_BIN = (CASCADE_ORDER_A_REG == "NONE") ? CASCADE_ORDER_A_NONE : (CASCADE_ORDER_A_REG == "FIRST") ? CASCADE_ORDER_A_FIRST : (CASCADE_ORDER_A_REG == "LAST") ? CASCADE_ORDER_A_LAST : (CASCADE_ORDER_A_REG == "MIDDLE") ? CASCADE_ORDER_A_MIDDLE : CASCADE_ORDER_A_NONE; assign CASCADE_ORDER_B_BIN = (CASCADE_ORDER_B_REG == "NONE") ? CASCADE_ORDER_B_NONE : (CASCADE_ORDER_B_REG == "FIRST") ? CASCADE_ORDER_B_FIRST : (CASCADE_ORDER_B_REG == "LAST") ? CASCADE_ORDER_B_LAST : (CASCADE_ORDER_B_REG == "MIDDLE") ? CASCADE_ORDER_B_MIDDLE : CASCADE_ORDER_B_NONE; assign EN_AUTO_SLEEP_MODE_BIN = (EN_AUTO_SLEEP_MODE_REG == "FALSE") ? EN_AUTO_SLEEP_MODE_FALSE : (EN_AUTO_SLEEP_MODE_REG == "TRUE") ? EN_AUTO_SLEEP_MODE_TRUE : EN_AUTO_SLEEP_MODE_FALSE; assign EN_ECC_RD_A_BIN = (EN_ECC_RD_A_REG == "FALSE") ? EN_ECC_RD_A_FALSE : (EN_ECC_RD_A_REG == "TRUE") ? EN_ECC_RD_A_TRUE : EN_ECC_RD_A_FALSE; assign EN_ECC_RD_B_BIN = (EN_ECC_RD_B_REG == "FALSE") ? EN_ECC_RD_B_FALSE : (EN_ECC_RD_B_REG == "TRUE") ? EN_ECC_RD_B_TRUE : EN_ECC_RD_B_FALSE; assign EN_ECC_WR_A_BIN = (EN_ECC_WR_A_REG == "FALSE") ? EN_ECC_WR_A_FALSE : (EN_ECC_WR_A_REG == "TRUE") ? EN_ECC_WR_A_TRUE : EN_ECC_WR_A_FALSE; assign EN_ECC_WR_B_BIN = (EN_ECC_WR_B_REG == "FALSE") ? EN_ECC_WR_B_FALSE : (EN_ECC_WR_B_REG == "TRUE") ? EN_ECC_WR_B_TRUE : EN_ECC_WR_B_FALSE; assign IREG_PRE_A_BIN = (IREG_PRE_A_REG == "FALSE") ? IREG_PRE_A_FALSE : (IREG_PRE_A_REG == "TRUE") ? IREG_PRE_A_TRUE : IREG_PRE_A_FALSE; assign IREG_PRE_B_BIN = (IREG_PRE_B_REG == "FALSE") ? IREG_PRE_B_FALSE : (IREG_PRE_B_REG == "TRUE") ? IREG_PRE_B_TRUE : IREG_PRE_B_FALSE; assign NUM_UNIQUE_SELF_ADDR_A_BIN = NUM_UNIQUE_SELF_ADDR_A_REG[11:0]; assign NUM_UNIQUE_SELF_ADDR_B_BIN = NUM_UNIQUE_SELF_ADDR_B_REG[11:0]; assign NUM_URAM_IN_MATRIX_BIN = NUM_URAM_IN_MATRIX_REG[11:0]; assign OREG_A_BIN = (OREG_A_REG == "FALSE") ? OREG_A_FALSE : (OREG_A_REG == "TRUE") ? OREG_A_TRUE : OREG_A_FALSE; assign OREG_B_BIN = (OREG_B_REG == "FALSE") ? OREG_B_FALSE : (OREG_B_REG == "TRUE") ? OREG_B_TRUE : OREG_B_FALSE; assign OREG_ECC_A_BIN = (OREG_ECC_A_REG == "FALSE") ? OREG_ECC_A_FALSE : (OREG_ECC_A_REG == "TRUE") ? OREG_ECC_A_TRUE : OREG_ECC_A_FALSE; assign OREG_ECC_B_BIN = (OREG_ECC_B_REG == "FALSE") ? OREG_ECC_B_FALSE : (OREG_ECC_B_REG == "TRUE") ? OREG_ECC_B_TRUE : OREG_ECC_B_FALSE; assign REG_CAS_A_BIN = (REG_CAS_A_REG == "FALSE") ? REG_CAS_A_FALSE : (REG_CAS_A_REG == "TRUE") ? REG_CAS_A_TRUE : REG_CAS_A_FALSE; assign REG_CAS_B_BIN = (REG_CAS_B_REG == "FALSE") ? REG_CAS_B_FALSE : (REG_CAS_B_REG == "TRUE") ? REG_CAS_B_TRUE : REG_CAS_B_FALSE; assign RST_MODE_A_BIN = (RST_MODE_A_REG == "SYNC") ? RST_MODE_A_SYNC : (RST_MODE_A_REG == "ASYNC") ? RST_MODE_A_ASYNC : RST_MODE_A_SYNC; assign RST_MODE_B_BIN = (RST_MODE_B_REG == "SYNC") ? RST_MODE_B_SYNC : (RST_MODE_B_REG == "ASYNC") ? RST_MODE_B_ASYNC : RST_MODE_B_SYNC; assign USE_EXT_CE_A_BIN = (USE_EXT_CE_A_REG == "FALSE") ? USE_EXT_CE_A_FALSE : (USE_EXT_CE_A_REG == "TRUE") ? USE_EXT_CE_A_TRUE : USE_EXT_CE_A_FALSE; assign USE_EXT_CE_B_BIN = (USE_EXT_CE_B_REG == "FALSE") ? USE_EXT_CE_B_FALSE : (USE_EXT_CE_B_REG == "TRUE") ? USE_EXT_CE_B_TRUE : USE_EXT_CE_B_FALSE; `else always @ (trig_attr) begin #1; AUTO_SLEEP_LATENCY_BIN = AUTO_SLEEP_LATENCY_REG[3:0]; AVG_CONS_INACTIVE_CYCLES_BIN = AVG_CONS_INACTIVE_CYCLES_REG[16:0]; BWE_MODE_A_BIN = (BWE_MODE_A_REG == "PARITY_INTERLEAVED") ? BWE_MODE_A_PARITY_INTERLEAVED : (BWE_MODE_A_REG == "PARITY_INDEPENDENT") ? BWE_MODE_A_PARITY_INDEPENDENT : BWE_MODE_A_PARITY_INTERLEAVED; BWE_MODE_B_BIN = (BWE_MODE_B_REG == "PARITY_INTERLEAVED") ? BWE_MODE_B_PARITY_INTERLEAVED : (BWE_MODE_B_REG == "PARITY_INDEPENDENT") ? BWE_MODE_B_PARITY_INDEPENDENT : BWE_MODE_B_PARITY_INTERLEAVED; CASCADE_ORDER_A_BIN = (CASCADE_ORDER_A_REG == "NONE") ? CASCADE_ORDER_A_NONE : (CASCADE_ORDER_A_REG == "FIRST") ? CASCADE_ORDER_A_FIRST : (CASCADE_ORDER_A_REG == "LAST") ? CASCADE_ORDER_A_LAST : (CASCADE_ORDER_A_REG == "MIDDLE") ? CASCADE_ORDER_A_MIDDLE : CASCADE_ORDER_A_NONE; CASCADE_ORDER_B_BIN = (CASCADE_ORDER_B_REG == "NONE") ? CASCADE_ORDER_B_NONE : (CASCADE_ORDER_B_REG == "FIRST") ? CASCADE_ORDER_B_FIRST : (CASCADE_ORDER_B_REG == "LAST") ? CASCADE_ORDER_B_LAST : (CASCADE_ORDER_B_REG == "MIDDLE") ? CASCADE_ORDER_B_MIDDLE : CASCADE_ORDER_B_NONE; EN_AUTO_SLEEP_MODE_BIN = (EN_AUTO_SLEEP_MODE_REG == "FALSE") ? EN_AUTO_SLEEP_MODE_FALSE : (EN_AUTO_SLEEP_MODE_REG == "TRUE") ? EN_AUTO_SLEEP_MODE_TRUE : EN_AUTO_SLEEP_MODE_FALSE; EN_ECC_RD_A_BIN = (EN_ECC_RD_A_REG == "FALSE") ? EN_ECC_RD_A_FALSE : (EN_ECC_RD_A_REG == "TRUE") ? EN_ECC_RD_A_TRUE : EN_ECC_RD_A_FALSE; EN_ECC_RD_B_BIN = (EN_ECC_RD_B_REG == "FALSE") ? EN_ECC_RD_B_FALSE : (EN_ECC_RD_B_REG == "TRUE") ? EN_ECC_RD_B_TRUE : EN_ECC_RD_B_FALSE; EN_ECC_WR_A_BIN = (EN_ECC_WR_A_REG == "FALSE") ? EN_ECC_WR_A_FALSE : (EN_ECC_WR_A_REG == "TRUE") ? EN_ECC_WR_A_TRUE : EN_ECC_WR_A_FALSE; EN_ECC_WR_B_BIN = (EN_ECC_WR_B_REG == "FALSE") ? EN_ECC_WR_B_FALSE : (EN_ECC_WR_B_REG == "TRUE") ? EN_ECC_WR_B_TRUE : EN_ECC_WR_B_FALSE; IREG_PRE_A_BIN = (IREG_PRE_A_REG == "FALSE") ? IREG_PRE_A_FALSE : (IREG_PRE_A_REG == "TRUE") ? IREG_PRE_A_TRUE : IREG_PRE_A_FALSE; IREG_PRE_B_BIN = (IREG_PRE_B_REG == "FALSE") ? IREG_PRE_B_FALSE : (IREG_PRE_B_REG == "TRUE") ? IREG_PRE_B_TRUE : IREG_PRE_B_FALSE; NUM_UNIQUE_SELF_ADDR_A_BIN = NUM_UNIQUE_SELF_ADDR_A_REG[11:0]; NUM_UNIQUE_SELF_ADDR_B_BIN = NUM_UNIQUE_SELF_ADDR_B_REG[11:0]; NUM_URAM_IN_MATRIX_BIN = NUM_URAM_IN_MATRIX_REG[11:0]; OREG_A_BIN = (OREG_A_REG == "FALSE") ? OREG_A_FALSE : (OREG_A_REG == "TRUE") ? OREG_A_TRUE : OREG_A_FALSE; OREG_B_BIN = (OREG_B_REG == "FALSE") ? OREG_B_FALSE : (OREG_B_REG == "TRUE") ? OREG_B_TRUE : OREG_B_FALSE; OREG_ECC_A_BIN = (OREG_ECC_A_REG == "FALSE") ? OREG_ECC_A_FALSE : (OREG_ECC_A_REG == "TRUE") ? OREG_ECC_A_TRUE : OREG_ECC_A_FALSE; OREG_ECC_B_BIN = (OREG_ECC_B_REG == "FALSE") ? OREG_ECC_B_FALSE : (OREG_ECC_B_REG == "TRUE") ? OREG_ECC_B_TRUE : OREG_ECC_B_FALSE; REG_CAS_A_BIN = (REG_CAS_A_REG == "FALSE") ? REG_CAS_A_FALSE : (REG_CAS_A_REG == "TRUE") ? REG_CAS_A_TRUE : REG_CAS_A_FALSE; REG_CAS_B_BIN = (REG_CAS_B_REG == "FALSE") ? REG_CAS_B_FALSE : (REG_CAS_B_REG == "TRUE") ? REG_CAS_B_TRUE : REG_CAS_B_FALSE; RST_MODE_A_BIN = (RST_MODE_A_REG == "SYNC") ? RST_MODE_A_SYNC : (RST_MODE_A_REG == "ASYNC") ? RST_MODE_A_ASYNC : RST_MODE_A_SYNC; RST_MODE_B_BIN = (RST_MODE_B_REG == "SYNC") ? RST_MODE_B_SYNC : (RST_MODE_B_REG == "ASYNC") ? RST_MODE_B_ASYNC : RST_MODE_B_SYNC; USE_EXT_CE_A_BIN = (USE_EXT_CE_A_REG == "FALSE") ? USE_EXT_CE_A_FALSE : (USE_EXT_CE_A_REG == "TRUE") ? USE_EXT_CE_A_TRUE : USE_EXT_CE_A_FALSE; USE_EXT_CE_B_BIN = (USE_EXT_CE_B_REG == "FALSE") ? USE_EXT_CE_B_FALSE : (USE_EXT_CE_B_REG == "TRUE") ? USE_EXT_CE_B_TRUE : USE_EXT_CE_B_FALSE; end `endif `ifndef XIL_XECLIB always @ (trig_attr) begin #1; if ((attr_test == 1'b1) || ((AUTO_SLEEP_LATENCY_REG != 8) && (AUTO_SLEEP_LATENCY_REG != 3) && (AUTO_SLEEP_LATENCY_REG != 4) && (AUTO_SLEEP_LATENCY_REG != 5) && (AUTO_SLEEP_LATENCY_REG != 6) && (AUTO_SLEEP_LATENCY_REG != 7) && (AUTO_SLEEP_LATENCY_REG != 9) && (AUTO_SLEEP_LATENCY_REG != 10) && (AUTO_SLEEP_LATENCY_REG != 11) && (AUTO_SLEEP_LATENCY_REG != 12) && (AUTO_SLEEP_LATENCY_REG != 13) && (AUTO_SLEEP_LATENCY_REG != 14) && (AUTO_SLEEP_LATENCY_REG != 15))) begin $display("Error: [Unisim %s-101] AUTO_SLEEP_LATENCY attribute is set to %d. Legal values for this attribute are 8, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, AUTO_SLEEP_LATENCY_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((AVG_CONS_INACTIVE_CYCLES_REG < 10) || (AVG_CONS_INACTIVE_CYCLES_REG > 100000))) begin $display("Error: [Unisim %s-102] AVG_CONS_INACTIVE_CYCLES attribute is set to %d. Legal values for this attribute are 10 to 100000. Instance: %m", MODULE_NAME, AVG_CONS_INACTIVE_CYCLES_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((BWE_MODE_A_REG != "PARITY_INTERLEAVED") && (BWE_MODE_A_REG != "PARITY_INDEPENDENT"))) begin $display("Error: [Unisim %s-103] BWE_MODE_A attribute is set to %s. Legal values for this attribute are PARITY_INTERLEAVED or PARITY_INDEPENDENT. Instance: %m", MODULE_NAME, BWE_MODE_A_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((BWE_MODE_B_REG != "PARITY_INTERLEAVED") && (BWE_MODE_B_REG != "PARITY_INDEPENDENT"))) begin $display("Error: [Unisim %s-104] BWE_MODE_B attribute is set to %s. Legal values for this attribute are PARITY_INTERLEAVED or PARITY_INDEPENDENT. Instance: %m", MODULE_NAME, BWE_MODE_B_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CASCADE_ORDER_A_REG != "NONE") && (CASCADE_ORDER_A_REG != "FIRST") && (CASCADE_ORDER_A_REG != "LAST") && (CASCADE_ORDER_A_REG != "MIDDLE"))) begin $display("Error: [Unisim %s-105] CASCADE_ORDER_A attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CASCADE_ORDER_B_REG != "NONE") && (CASCADE_ORDER_B_REG != "FIRST") && (CASCADE_ORDER_B_REG != "LAST") && (CASCADE_ORDER_B_REG != "MIDDLE"))) begin $display("Error: [Unisim %s-106] CASCADE_ORDER_B attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((EN_AUTO_SLEEP_MODE_REG != "FALSE") && (EN_AUTO_SLEEP_MODE_REG != "TRUE"))) begin $display("Error: [Unisim %s-107] EN_AUTO_SLEEP_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((EN_ECC_RD_A_REG != "FALSE") && (EN_ECC_RD_A_REG != "TRUE"))) begin $display("Error: [Unisim %s-108] EN_ECC_RD_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_RD_A_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((EN_ECC_RD_B_REG != "FALSE") && (EN_ECC_RD_B_REG != "TRUE"))) begin $display("Error: [Unisim %s-109] EN_ECC_RD_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_RD_B_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((EN_ECC_WR_A_REG != "FALSE") && (EN_ECC_WR_A_REG != "TRUE"))) begin $display("Error: [Unisim %s-110] EN_ECC_WR_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WR_A_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((EN_ECC_WR_B_REG != "FALSE") && (EN_ECC_WR_B_REG != "TRUE"))) begin $display("Error: [Unisim %s-111] EN_ECC_WR_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WR_B_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((IREG_PRE_A_REG != "FALSE") && (IREG_PRE_A_REG != "TRUE"))) begin $display("Error: [Unisim %s-112] IREG_PRE_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IREG_PRE_A_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((IREG_PRE_B_REG != "FALSE") && (IREG_PRE_B_REG != "TRUE"))) begin $display("Error: [Unisim %s-113] IREG_PRE_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IREG_PRE_B_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((NUM_UNIQUE_SELF_ADDR_A_REG < 1) || (NUM_UNIQUE_SELF_ADDR_A_REG > 2048))) begin $display("Error: [Unisim %s-122] NUM_UNIQUE_SELF_ADDR_A attribute is set to %d. Legal values for this attribute are 1 to 2048. Instance: %m", MODULE_NAME, NUM_UNIQUE_SELF_ADDR_A_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((NUM_UNIQUE_SELF_ADDR_B_REG < 1) || (NUM_UNIQUE_SELF_ADDR_B_REG > 2048))) begin $display("Error: [Unisim %s-123] NUM_UNIQUE_SELF_ADDR_B attribute is set to %d. Legal values for this attribute are 1 to 2048. Instance: %m", MODULE_NAME, NUM_UNIQUE_SELF_ADDR_B_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((NUM_URAM_IN_MATRIX_REG < 1) || (NUM_URAM_IN_MATRIX_REG > 2048))) begin $display("Error: [Unisim %s-124] NUM_URAM_IN_MATRIX attribute is set to %d. Legal values for this attribute are 1 to 2048. Instance: %m", MODULE_NAME, NUM_URAM_IN_MATRIX_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((OREG_A_REG != "FALSE") && (OREG_A_REG != "TRUE"))) begin $display("Error: [Unisim %s-125] OREG_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_A_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((OREG_B_REG != "FALSE") && (OREG_B_REG != "TRUE"))) begin $display("Error: [Unisim %s-126] OREG_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_B_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((OREG_ECC_A_REG != "FALSE") && (OREG_ECC_A_REG != "TRUE"))) begin $display("Error: [Unisim %s-127] OREG_ECC_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_ECC_A_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((OREG_ECC_B_REG != "FALSE") && (OREG_ECC_B_REG != "TRUE"))) begin $display("Error: [Unisim %s-128] OREG_ECC_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_ECC_B_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((REG_CAS_A_REG != "FALSE") && (REG_CAS_A_REG != "TRUE"))) begin $display("Error: [Unisim %s-129] REG_CAS_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, REG_CAS_A_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((REG_CAS_B_REG != "FALSE") && (REG_CAS_B_REG != "TRUE"))) begin $display("Error: [Unisim %s-130] REG_CAS_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, REG_CAS_B_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((RST_MODE_A_REG != "SYNC") && (RST_MODE_A_REG != "ASYNC"))) begin $display("Error: [Unisim %s-131] RST_MODE_A attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, RST_MODE_A_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((RST_MODE_B_REG != "SYNC") && (RST_MODE_B_REG != "ASYNC"))) begin $display("Error: [Unisim %s-132] RST_MODE_B attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, RST_MODE_B_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((USE_EXT_CE_A_REG != "FALSE") && (USE_EXT_CE_A_REG != "TRUE"))) begin $display("Error: [Unisim %s-137] USE_EXT_CE_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_EXT_CE_A_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((USE_EXT_CE_B_REG != "FALSE") && (USE_EXT_CE_B_REG != "TRUE"))) begin $display("Error: [Unisim %s-138] USE_EXT_CE_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_EXT_CE_B_REG); attr_err = 1'b1; end if (attr_err == 1'b1) #1 $finish; end `endif `ifdef XIL_TIMING reg notifier; `endif // begin behavioral model // define tasks, functions reg cas_a_warning = 1'b0; reg cas_b_warning = 1'b0; task is_cas_a_zero; integer i; begin cas_a_warning = 1'b0; for (i=0;i<=22;i=i+1) begin if (CAS_IN_ADDR_A[i] !== 1'b0) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-15] CAS_IN_ADDR_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); end end for (i=0;i<=8;i=i+1) begin if (CAS_IN_BWE_A[i] !== 1'b0) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-15] CAS_IN_BWE_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); end end if (CAS_IN_DBITERR_A !== 1'b0) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-15] CAS_IN_DBITERR_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); end for (i=0;i<=71;i=i+1) begin if (CAS_IN_DIN_A[i] !== 1'b0) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-15] CAS_IN_DIN_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); end end for (i=0;i<=71;i=i+1) begin if (CAS_IN_DOUT_A[i] !== 1'b0) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-15] CAS_IN_DOUT_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); end end if (CAS_IN_EN_A !== 1'b0) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-15] CAS_IN_EN_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); end if (CAS_IN_RDACCESS_A !== 1'b0) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-15] CAS_IN_RDACCESS_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); end if (CAS_IN_RDB_WR_A !== 1'b0) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-15] CAS_IN_RDB_WR_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); end if (CAS_IN_SBITERR_A !== 1'b0) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-15] CAS_IN_SBITERR_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); end end endtask // is_cas_a_zero task is_cas_a_floating; integer i; begin cas_a_warning = 1'b0; for (i=0;i<=22;i=i+1) begin if (CAS_IN_ADDR_A[i] === 1'bz) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-16] CAS_IN_ADDR_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); end end for (i=0;i<=8;i=i+1) begin if (CAS_IN_BWE_A[i] === 1'bz) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-16] CAS_IN_BWE_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); end end if (CAS_IN_DBITERR_A === 1'bz) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-16] CAS_IN_DBITERR_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); end for (i=0;i<=71;i=i+1) begin if (CAS_IN_DIN_A[i] === 1'bz) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-16] CAS_IN_DIN_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); end end for (i=0;i<=71;i=i+1) begin if (CAS_IN_DOUT_A[i] === 1'bz) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-16] CAS_IN_DOUT_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG); end end if (CAS_IN_EN_A === 1'bz) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-16] CAS_IN_EN_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); end if (CAS_IN_RDACCESS_A === 1'bz) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-16] CAS_IN_RDACCESS_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); end if (CAS_IN_RDB_WR_A === 1'bz) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-16] CAS_IN_RDB_WR_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); end if (CAS_IN_SBITERR_A === 1'bz) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-16] CAS_IN_SBITERR_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); end end endtask // is_cas_a_floating task is_cas_b_zero; integer i; begin cas_b_warning = 1'b0; for (i=0;i<=22;i=i+1) begin if (CAS_IN_ADDR_B[i] !== 1'b0) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-17] CAS_IN_ADDR_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG); end end for (i=0;i<=8;i=i+1) begin if (CAS_IN_BWE_B[i] !== 1'b0) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-17] CAS_IN_BWE_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG); end end if (CAS_IN_DBITERR_B !== 1'b0) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-17] CAS_IN_DBITERR_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); end for (i=0;i<=71;i=i+1) begin if (CAS_IN_DIN_B[i] !== 1'b0) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-17] CAS_IN_DIN_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG); end end for (i=0;i<=71;i=i+1) begin if (CAS_IN_DOUT_B[i] !== 1'b0) begin cas_a_warning = 1'b1; $display("Warning: [Unisim %s-17] CAS_IN_DOUT_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG); end end if (CAS_IN_EN_B !== 1'b0) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-17] CAS_IN_EN_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); end if (CAS_IN_RDACCESS_B !== 1'b0) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-17] CAS_IN_RDACCESS_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); end if (CAS_IN_RDB_WR_B !== 1'b0) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-17] CAS_IN_RDB_WR_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); end if (CAS_IN_SBITERR_B !== 1'b0) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-17] CAS_IN_SBITERR_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); end end endtask // is_cas_b_zero task is_cas_b_floating; integer i; begin cas_b_warning = 1'b0; for (i=0;i<=22;i=i+1) begin if (CAS_IN_ADDR_B[i] === 1'bz) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-18] CAS_IN_ADDR_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i); end end for (i=0;i<=8;i=i+1) begin if (CAS_IN_BWE_B[i] === 1'bz) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-18] CAS_IN_BWE_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i); end end if (CAS_IN_DBITERR_B === 1'bz) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-18] CAS_IN_DBITERR_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); end for (i=0;i<=71;i=i+1) begin if (CAS_IN_DIN_B[i] === 1'bz) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-18] CAS_IN_DIN_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i); end end for (i=0;i<=71;i=i+1) begin if (CAS_IN_DOUT_B[i] === 1'bz) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-18] CAS_IN_DOUT_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i); end end if (CAS_IN_EN_B === 1'bz) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-18] CAS_IN_EN_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); end if (CAS_IN_RDACCESS_B === 1'bz) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-18] CAS_IN_RDACCESS_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); end if (CAS_IN_RDB_WR_B === 1'bz) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-18] CAS_IN_RDB_WR_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); end if (CAS_IN_SBITERR_B === 1'bz) begin cas_b_warning = 1'b1; $display("Warning: [Unisim %s-18] CAS_IN_SBITERR_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME); end end endtask // is_cas_b_floating function [7:0] fn_ecc ( input encode, input [63:0] d_i, input [7:0] dp_i ); reg ecc_7; begin fn_ecc[0] = d_i[0] ^ d_i[1] ^ d_i[3] ^ d_i[4] ^ d_i[6] ^ d_i[8] ^ d_i[10] ^ d_i[11] ^ d_i[13] ^ d_i[15] ^ d_i[17] ^ d_i[19] ^ d_i[21] ^ d_i[23] ^ d_i[25] ^ d_i[26] ^ d_i[28] ^ d_i[30] ^ d_i[32] ^ d_i[34] ^ d_i[36] ^ d_i[38] ^ d_i[40] ^ d_i[42] ^ d_i[44] ^ d_i[46] ^ d_i[48] ^ d_i[50] ^ d_i[52] ^ d_i[54] ^ d_i[56] ^ d_i[57] ^ d_i[59] ^ d_i[61] ^ d_i[63]; fn_ecc[1] = d_i[0] ^ d_i[2] ^ d_i[3] ^ d_i[5] ^ d_i[6] ^ d_i[9] ^ d_i[10] ^ d_i[12] ^ d_i[13] ^ d_i[16] ^ d_i[17] ^ d_i[20] ^ d_i[21] ^ d_i[24] ^ d_i[25] ^ d_i[27] ^ d_i[28] ^ d_i[31] ^ d_i[32] ^ d_i[35] ^ d_i[36] ^ d_i[39] ^ d_i[40] ^ d_i[43] ^ d_i[44] ^ d_i[47] ^ d_i[48] ^ d_i[51] ^ d_i[52] ^ d_i[55] ^ d_i[56] ^ d_i[58] ^ d_i[59] ^ d_i[62] ^ d_i[63]; fn_ecc[2] = d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^ d_i[10] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ d_i[56] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63]; fn_ecc[3] = d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^ d_i[10] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[49] ^ d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ d_i[56]; fn_ecc[4] = d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ d_i[56]; fn_ecc[5] = d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ d_i[56]; fn_ecc[6] = d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63]; ecc_7 = d_i[0] ^ d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^ d_i[10] ^ d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^ d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^ d_i[56] ^ d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63]; if (encode) begin fn_ecc[7] = ecc_7 ^ fn_ecc[0] ^ fn_ecc[1] ^ fn_ecc[2] ^ fn_ecc[3] ^ fn_ecc[4] ^ fn_ecc[5] ^ fn_ecc[6]; end else begin fn_ecc[7] = ecc_7 ^ dp_i[0] ^ dp_i[1] ^ dp_i[2] ^ dp_i[3] ^ dp_i[4] ^ dp_i[5] ^ dp_i[6]; end end endfunction // fn_ecc function [71:0] fn_cor_bit ( input [6:0] error_bit, input [63:0] d_i, input [7:0] dp_i ); reg [71:0] cor_int; begin cor_int = {d_i[63:57], dp_i[6], d_i[56:26], dp_i[5], d_i[25:11], dp_i[4], d_i[10:4], dp_i[3], d_i[3:1], dp_i[2], d_i[0], dp_i[1:0], dp_i[7]}; cor_int[error_bit] = ~cor_int[error_bit]; fn_cor_bit = {cor_int[0], cor_int[64], cor_int[32], cor_int[16], cor_int[8], cor_int[4], cor_int[2:1], cor_int[71:65], cor_int[63:33], cor_int[31:17], cor_int[15:9], cor_int[7:5], cor_int[3]}; end endfunction // fn_cor_bit `ifndef XIL_XECLIB always @ (trig_attr) begin #1; if ((attr_test == 1'b1) || ((CASCADE_ORDER_A_REG != "NONE") && (USE_EXT_CE_A_REG == "TRUE"))) begin $display("Error: [Unisim %s-1] CASCADE_ORDER_A attribute is set to %s and USE_EXT_CE_A attribute is set to %s. EXT_CE_A can not be used in cascaded URAM applications. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG, USE_EXT_CE_A_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((CASCADE_ORDER_B_REG != "NONE") && (USE_EXT_CE_B_REG == "TRUE"))) begin $display("Error: [Unisim %s-2] CASCADE_ORDER_B attribute is set to %s and USE_EXT_CE_B attribute is set to %s. EXT_CE_B can not be used in cascaded URAM applications. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG, USE_EXT_CE_B_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || (CASCADE_ORDER_A_REG == "NONE") || (CASCADE_ORDER_A_REG == "FIRST")) begin is_cas_a_zero; if (cas_a_warning) $display("Warning: [Unisim %s-13] CASCADE_ORDER_A attribute is set to %s and some or all of the CASCADE signals are not tied low. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly tied off. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); end if ((attr_test == 1'b1) || (CASCADE_ORDER_A_REG == "LAST") || (CASCADE_ORDER_A_REG == "MIDDLE")) begin is_cas_a_floating; if (cas_a_warning) $display("Warning: [Unisim %s-13] CASCADE_ORDER_A attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG); end if ((attr_test == 1'b1) || (CASCADE_ORDER_B_REG == "NONE") || (CASCADE_ORDER_B_REG == "FIRST")) begin is_cas_b_zero; if (cas_b_warning) $display("Warning: [Unisim %s-14] CASCADE_ORDER_B attribute is set to %s and some or all of the CASCADE signals are not tied low. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly tied off. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); end if ((attr_test == 1'b1) || (CASCADE_ORDER_B_REG == "LAST") || (CASCADE_ORDER_B_REG == "MIDDLE")) begin is_cas_b_floating; if (cas_b_warning) $display("Warning: [Unisim %s-14] CASCADE_ORDER_B attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG); end if ((attr_test == 1'b1) || ((EN_AUTO_SLEEP_MODE_REG == "TRUE") && (USE_EXT_CE_A_REG == "TRUE"))) begin $display("Error: [Unisim %s-19] EN_AUTO_SLEEP_MODE attribute is set to %s and USE_EXT_CE_A is set to %s. External OREG CE cannot be used when AUTO_SLEEP_MODE is enabled. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG, USE_EXT_CE_A_REG); attr_err = 1'b1; end if ((attr_test == 1'b1) || ((EN_AUTO_SLEEP_MODE_REG == "TRUE") && (USE_EXT_CE_B_REG == "TRUE"))) begin $display("Error: [Unisim %s-20] EN_AUTO_SLEEP_MODE attribute is set to %s and USE_EXT_CE_B is set to %s. External OREG CE cannot be used when AUTO_SLEEP_MODE is enabled. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG, USE_EXT_CE_B_REG); attr_err = 1'b1; end if (attr_err == 1'b1) #1 $finish; end `endif localparam mem_width = 72; localparam mem_depth = 4 * 1024; localparam encode = 1'b1; localparam decode = 1'b0; localparam [22:0] ADDR_INIT = 23'b0; localparam [8:0] BWE_INIT = 9'b0; localparam [mem_width-1:0] D_INIT = {mem_width{1'b0}}; localparam [mem_width-1:0] D_UNDEF = {mem_width{1'bx}}; reg [mem_width-1 : 0 ] mem [0 : mem_depth-1]; integer wa; reg [11:0] ram_addr_a; reg [11:0] ram_addr_b; reg ram_ce_a; reg ram_ce_b; reg DEEPSLEEP_in = 1'b0; reg SHUTDOWN_in = 1'b0; reg ram_ce_a_int=0; reg ram_ce_b_int=0; reg ram_ce_a_pre=0; reg ram_ce_b_pre=0; reg [15:1] ram_ce_a_fifo; reg [15:1] ram_ce_b_fifo; reg [71:0] ram_bwe_a; reg [71:0] ram_bwe_b; reg ram_we_a; reg ram_we_b; reg ram_we_a_event = 1'b0; reg ram_we_b_event = 1'b0; reg [71:0] ram_data_a; reg [71:0] ram_data_b; // input register stages // decisions simulate faster than assignments - wider muxes, less busses reg [22:0] ADDR_A_reg; reg [22:0] ADDR_B_reg; reg [8:0] BWE_A_reg; reg [8:0] BWE_B_reg; reg [71:0] DIN_A_reg; reg [71:0] DIN_B_reg; reg EN_A_reg; reg EN_B_reg; reg INJECT_DBITERR_A_reg; reg INJECT_DBITERR_B_reg; reg INJECT_SBITERR_A_reg; reg INJECT_SBITERR_B_reg; reg RDB_WR_A_reg; reg RDB_WR_B_reg; reg [22:0] ADDR_A_int; reg [22:0] ADDR_B_int; reg [8:0] BWE_A_int; reg [8:0] BWE_B_int; reg [71:0] DIN_A_int; reg [71:0] DIN_B_int; reg EN_A_int; reg EN_B_int; reg INJECT_DBITERR_A_int; reg INJECT_DBITERR_B_int; reg INJECT_SBITERR_A_int; reg INJECT_SBITERR_B_int; reg RDB_WR_A_int; reg RDB_WR_B_int; reg RST_A_async = 1'b0; reg RST_B_async = 1'b0; reg RST_A_sync = 1'b0; reg RST_B_sync = 1'b0; integer wake_count; wire auto_sleep; reg shut_down; reg a_sleep; reg auto_sleep_A; reg auto_sleep_B; wire auto_wake_up_A; wire auto_wake_up_B; reg CAS_OUT_DBITERR_A_out; reg CAS_OUT_DBITERR_B_out; reg CAS_OUT_EN_A_out; reg CAS_OUT_EN_B_out; reg CAS_OUT_RDACCESS_A_out; reg CAS_OUT_RDACCESS_B_out; reg CAS_OUT_RDB_WR_A_out; reg CAS_OUT_RDB_WR_B_out; reg CAS_OUT_SBITERR_A_out; reg CAS_OUT_SBITERR_B_out; reg DBITERR_A_out; reg DBITERR_B_out; reg RDACCESS_A_out; reg RDACCESS_B_out; reg SBITERR_A_out; reg SBITERR_B_out; reg [22:0] CAS_OUT_ADDR_A_out; reg [22:0] CAS_OUT_ADDR_B_out; reg [71:0] CAS_OUT_DIN_A_out; reg [71:0] CAS_OUT_DIN_B_out; reg [71:0] CAS_OUT_DOUT_A_out; reg [71:0] CAS_OUT_DOUT_B_out; reg [71:0] DOUT_A_out; reg [71:0] DOUT_B_out; reg [8:0] CAS_OUT_BWE_A_out; reg [8:0] CAS_OUT_BWE_B_out; assign CAS_OUT_ADDR_A = CAS_OUT_ADDR_A_out; assign CAS_OUT_ADDR_B = CAS_OUT_ADDR_B_out; assign CAS_OUT_BWE_A = CAS_OUT_BWE_A_out; assign CAS_OUT_BWE_B = CAS_OUT_BWE_B_out; assign CAS_OUT_DBITERR_A = DBITERR_A_out; assign CAS_OUT_DBITERR_B = DBITERR_B_out; assign CAS_OUT_DIN_A = CAS_OUT_DIN_A_out; assign CAS_OUT_DIN_B = CAS_OUT_DIN_B_out; assign CAS_OUT_DOUT_A = DOUT_A_out; assign CAS_OUT_DOUT_B = DOUT_B_out; assign CAS_OUT_EN_A = CAS_OUT_EN_A_out; assign CAS_OUT_EN_B = CAS_OUT_EN_B_out; assign CAS_OUT_RDACCESS_A = RDACCESS_A_out; assign CAS_OUT_RDACCESS_B = RDACCESS_B_out; assign CAS_OUT_RDB_WR_A = CAS_OUT_RDB_WR_A_out; assign CAS_OUT_RDB_WR_B = CAS_OUT_RDB_WR_B_out; assign CAS_OUT_SBITERR_A = SBITERR_A_out; assign CAS_OUT_SBITERR_B = SBITERR_B_out; assign DBITERR_A = DBITERR_A_out; assign DBITERR_B = DBITERR_B_out; assign DOUT_A = DOUT_A_out; assign DOUT_B = DOUT_B_out; assign RDACCESS_A = RDACCESS_A_out; assign RDACCESS_B = RDACCESS_B_out; assign SBITERR_A = SBITERR_A_out; assign SBITERR_B = SBITERR_B_out; `ifndef XIL_XECLIB reg INIT_RAM = 1'b0; initial begin #100; INIT_RAM = 1'b1; end `endif `ifndef XIL_XECLIB reg rst_a_warn_once = 1'b0; reg rst_b_warn_once = 1'b0; always @(posedge CLK_in) begin if ((attr_test == 1'b1) || ((EN_A_int == 1'b1) && (RDB_WR_A_int == 1'b0) && ((RST_A_sync == 1'b1) || (RST_A_async == 1'b1)) && (CASCADE_ORDER_A_BIN != CASCADE_ORDER_A_NONE) && (REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin if (rst_a_warn_once == 1'b0) begin $display("Warning: [Unisim %s-11] At time (%.3f) ns: CASCADE_ORDER_A attribute is set to %s and REG_CAS_A attribute is set to %s with RST_A and a READ command both active. In certain circumstances the implementation tools optimize the uram pipeline to achieve optimal timing. This is achieved by manipulating the REG_CAS_A attributes. This will not alter the latency of the pipeline but may result in different reset behavior pre and post implementation under these conditions. To avoid this, deassert EN_A when RST_A is active. Instance: %m", MODULE_NAME, $time/1000.0, CASCADE_ORDER_A_REG, REG_CAS_A_REG); rst_a_warn_once = 1'b1; end end else begin rst_a_warn_once = 1'b0; end end always @(posedge CLK_in) begin if ((attr_test == 1'b1) || ((EN_B_int == 1'b1) && (RDB_WR_B_int == 1'b0) && ((RST_B_sync == 1'b1) || (RST_B_async == 1'b1)) && (CASCADE_ORDER_B_BIN != CASCADE_ORDER_B_NONE) && (REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin if (rst_b_warn_once == 1'b0) begin $display("Warning: [Unisim %s-12] At time (%.3f) ns: CASCADE_ORDER_B attribute is set to %s and REG_CAS_B attribute is set to %s with RST_B and a READ command both active. In certain circumstances the implementation tools optimize the uram pipeline to achieve optimal timing. This is achieved by manipulating the REG_CAS_B attributes. This will not alter the latency of the pipeline but may result in different reset behavior pre and post implementation under these conditions. To avoid this, deassert EN_B when RST_B is active. Instance: %m", MODULE_NAME, $time/1000.0, CASCADE_ORDER_B_REG, REG_CAS_B_REG); rst_b_warn_once = 1'b1; end end else begin rst_b_warn_once = 1'b0; end end `endif always @ (*) begin if (RST_MODE_A_BIN == RST_MODE_A_ASYNC) begin RST_A_async = RST_A_in; end end always @ (*) begin if (RST_MODE_B_BIN == RST_MODE_B_ASYNC) begin RST_B_async = RST_B_in; end end always @ (posedge CLK_in) begin if ((RST_MODE_A_BIN == RST_MODE_A_SYNC) && (RST_A_sync !== RST_A_in)) RST_A_sync <= RST_A_in; if ((RST_MODE_B_BIN == RST_MODE_B_SYNC) && (RST_B_sync !== RST_B_in)) RST_B_sync <= RST_B_in; end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || (((CASCADE_ORDER_A_BIN != CASCADE_ORDER_A_NONE) && (REG_CAS_A_BIN == REG_CAS_A_FALSE)) && (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) && (IREG_PRE_A_BIN == IREG_PRE_A_FALSE)))) begin ADDR_A_reg <= ADDR_INIT; EN_A_reg <= 1'b0; RDB_WR_A_reg <= 1'b0; BWE_A_reg <= BWE_INIT; DIN_A_reg <= D_INIT; INJECT_DBITERR_A_reg <= 1'b0; INJECT_SBITERR_A_reg <= 1'b0; end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && (REG_CAS_A_BIN == REG_CAS_A_TRUE)) begin EN_A_reg <= CAS_IN_EN_A_in; if (CAS_IN_EN_A_in) begin ADDR_A_reg[22:12] <= CAS_IN_ADDR_A_in[22:12]; end if (CAS_IN_EN_A_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin ADDR_A_reg[11:0] <= CAS_IN_ADDR_A_in[11:0]; BWE_A_reg <= CAS_IN_BWE_A_in; DIN_A_reg <= CAS_IN_DIN_A_in; RDB_WR_A_reg <= CAS_IN_RDB_WR_A_in; end end else begin EN_A_reg <= EN_A_in; if (EN_A_in) begin ADDR_A_reg[22:12] <= ADDR_A_in[22:12]; end if (EN_A_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin ADDR_A_reg[11:0] <= ADDR_A_in[11:0]; BWE_A_reg <= BWE_A_in; DIN_A_reg <= DIN_A_in; INJECT_DBITERR_A_reg <= INJECT_DBITERR_A_in; INJECT_SBITERR_A_reg <= INJECT_SBITERR_A_in; RDB_WR_A_reg <= RDB_WR_A_in; end end end always @ (*) begin if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin ADDR_A_int = CAS_IN_ADDR_A_in; end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) && (IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) || (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && (REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin ADDR_A_int = ADDR_A_reg; end else begin ADDR_A_int = ADDR_A_in; end end always @ (*) begin if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin BWE_A_int = CAS_IN_BWE_A_in; end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) && (IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) || (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && (REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin BWE_A_int = BWE_A_reg; end else begin BWE_A_int = BWE_A_in; end end always @ (*) begin if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin DIN_A_int = CAS_IN_DIN_A_in; end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) && (IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) || (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && (REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin DIN_A_int = DIN_A_reg; end else begin DIN_A_int = DIN_A_in; end end always @ (*) begin if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin EN_A_int = CAS_IN_EN_A_in; end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) && (IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) || (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && (REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin EN_A_int = EN_A_reg; end else begin EN_A_int = EN_A_in; end end always @ (*) begin if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin INJECT_DBITERR_A_int = INJECT_DBITERR_A_reg; end else begin INJECT_DBITERR_A_int = INJECT_DBITERR_A_in; end end always @ (*) begin if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin INJECT_SBITERR_A_int = INJECT_SBITERR_A_reg; end else begin INJECT_SBITERR_A_int = INJECT_SBITERR_A_in; end end always @ (*) begin if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin RDB_WR_A_int = CAS_IN_RDB_WR_A_in; end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) && (IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) || (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && (REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin RDB_WR_A_int = RDB_WR_A_reg; end else begin RDB_WR_A_int = RDB_WR_A_in; end end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || (((CASCADE_ORDER_B_BIN != CASCADE_ORDER_B_NONE) && (REG_CAS_B_BIN == REG_CAS_B_FALSE)) && (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) && (IREG_PRE_B_BIN == IREG_PRE_B_FALSE)))) begin ADDR_B_reg <= ADDR_INIT; EN_B_reg <= 1'b0; RDB_WR_B_reg <= 1'b0; BWE_B_reg <= BWE_INIT; DIN_B_reg <= D_INIT; INJECT_DBITERR_B_reg <= 1'b0; INJECT_SBITERR_B_reg <= 1'b0; end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && (REG_CAS_B_BIN == REG_CAS_B_TRUE)) begin EN_B_reg <= CAS_IN_EN_B_in; if (CAS_IN_EN_B_in) begin ADDR_B_reg[22:12] <= CAS_IN_ADDR_B_in[22:12]; end if (CAS_IN_EN_B_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin ADDR_B_reg[11:0] <= CAS_IN_ADDR_B_in[11:0]; BWE_B_reg <= CAS_IN_BWE_B_in; DIN_B_reg <= CAS_IN_DIN_B_in; RDB_WR_B_reg <= CAS_IN_RDB_WR_B_in; end end else begin EN_B_reg <= EN_B_in; if (EN_B_in) begin ADDR_B_reg[22:12] <= ADDR_B_in[22:12]; end if (EN_B_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin ADDR_B_reg[11:0] <= ADDR_B_in[11:0]; BWE_B_reg <= BWE_B_in; DIN_B_reg <= DIN_B_in; INJECT_DBITERR_B_reg <= INJECT_DBITERR_B_in; INJECT_SBITERR_B_reg <= INJECT_SBITERR_B_in; RDB_WR_B_reg <= RDB_WR_B_in; end end end always @ (*) begin if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin ADDR_B_int = CAS_IN_ADDR_B_in; end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) && (IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) || (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && (REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin ADDR_B_int = ADDR_B_reg; end else begin ADDR_B_int = ADDR_B_in; end end always @ (*) begin if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin BWE_B_int = CAS_IN_BWE_B_in; end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) && (IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) || (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && (REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin BWE_B_int = BWE_B_reg; end else begin BWE_B_int = BWE_B_in; end end always @ (*) begin if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin DIN_B_int = CAS_IN_DIN_B_in; end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) && (IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) || (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && (REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin DIN_B_int = DIN_B_reg; end else begin DIN_B_int = DIN_B_in; end end always @ (*) begin if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin EN_B_int = CAS_IN_EN_B_in; end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) && (IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) || (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && (REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin EN_B_int = EN_B_reg; end else begin EN_B_int = EN_B_in; end end always @ (*) begin if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin INJECT_DBITERR_B_int = INJECT_DBITERR_B_reg; end else begin INJECT_DBITERR_B_int = INJECT_DBITERR_B_in; end end always @ (*) begin if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin INJECT_SBITERR_B_int = INJECT_SBITERR_B_reg; end else begin INJECT_SBITERR_B_int = INJECT_SBITERR_B_in; end end always @ (*) begin if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin RDB_WR_B_int = CAS_IN_RDB_WR_B_in; end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) && (IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) || (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && (REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin RDB_WR_B_int = RDB_WR_B_reg; end else begin RDB_WR_B_int = RDB_WR_B_in; end end // cascade out - input controls always @ (*) begin if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin CAS_OUT_ADDR_A_out = ADDR_INIT; end else begin CAS_OUT_ADDR_A_out = ADDR_A_int; end end always @ (*) begin if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin CAS_OUT_BWE_A_out = BWE_INIT; end else begin CAS_OUT_BWE_A_out = BWE_A_int; end end always @ (*) begin if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin CAS_OUT_DIN_A_out = D_INIT; end else begin CAS_OUT_DIN_A_out = DIN_A_int; end end always @ (*) begin if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin CAS_OUT_EN_A_out = 1'b0; end else begin CAS_OUT_EN_A_out = EN_A_int; end end always @ (*) begin if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin CAS_OUT_RDB_WR_A_out = 1'b0; end else begin CAS_OUT_RDB_WR_A_out = RDB_WR_A_int; end end always @ (*) begin if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin CAS_OUT_ADDR_B_out = ADDR_INIT; end else begin CAS_OUT_ADDR_B_out = ADDR_B_int; end end always @ (*) begin if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin CAS_OUT_BWE_B_out = BWE_INIT; end else begin CAS_OUT_BWE_B_out = BWE_B_int; end end always @ (*) begin if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin CAS_OUT_DIN_B_out = D_INIT; end else begin CAS_OUT_DIN_B_out = DIN_B_int; end end always @ (*) begin if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin CAS_OUT_EN_B_out = 1'b0; end else begin CAS_OUT_EN_B_out = EN_B_int; end end always @ (*) begin if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin CAS_OUT_RDB_WR_B_out = 1'b0; end else begin CAS_OUT_RDB_WR_B_out = RDB_WR_B_int; end end // cascade=data out - outputs reg [71:0] ram_data_a_lat; reg [71:0] ram_data_a_out; // reg [71:0] ram_data_a_hold=D_INIT; reg [71:0] ram_data_a_reg; reg [71:0] ram_data_a_ecc=72'h000000000000000000; reg [71:0] ram_data_b_lat; reg [71:0] ram_data_b_out; reg [71:0] ram_data_b_reg; reg [71:0] ram_data_b_ecc=72'h000000000000000000; reg RDACCESS_A_lat; // reg RDACCESS_A_hold; reg RDACCESS_B_lat; reg RDACCESS_A_int; reg RDACCESS_B_int; reg SBITERR_A_ecc=1'b0; reg DBITERR_A_ecc=1'b0; reg SBITERR_B_ecc=1'b0; reg DBITERR_B_ecc=1'b0; reg DBITERR_A_reg; reg DBITERR_B_reg; reg [71:0] DOUT_A_reg; reg [71:0] DOUT_B_reg; reg RDACCESS_A_reg; reg RDACCESS_B_reg; reg SBITERR_A_reg; reg SBITERR_B_reg; reg RDACCESS_A_ecc_reg; reg RDACCESS_B_ecc_reg; reg CAS_IN_DBITERR_A_reg; reg CAS_IN_DBITERR_B_reg; reg [71:0] CAS_IN_DOUT_A_reg; reg [71:0] CAS_IN_DOUT_B_reg; reg CAS_IN_RDACCESS_A_reg; reg CAS_IN_RDACCESS_B_reg; reg CAS_IN_SBITERR_A_reg; reg CAS_IN_SBITERR_B_reg; reg data_A_enable = 1'b0; reg data_B_enable = 1'b0; // data/cas reg `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_A_async) begin if (RST_A_async || RST_A_in || glblGSR || (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin `else always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin if (RST_A_in || glblGSR || (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin `endif CAS_IN_DBITERR_A_reg <= 1'b0; CAS_IN_DOUT_A_reg <= D_INIT; CAS_IN_RDACCESS_A_reg <= 1'b0; CAS_IN_SBITERR_A_reg <= 1'b0; end else begin if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) begin CAS_IN_RDACCESS_A_reg <= CAS_IN_RDACCESS_A_in; if (CAS_IN_RDACCESS_A_in) begin CAS_IN_DBITERR_A_reg <= CAS_IN_DBITERR_A_in; CAS_IN_DOUT_A_reg <= CAS_IN_DOUT_A_in; CAS_IN_SBITERR_A_reg <= CAS_IN_SBITERR_A_in; end end end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_B_async) begin if (RST_B_async || RST_B_in || glblGSR || (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin `else always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin if (RST_B_in || glblGSR || (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin `endif CAS_IN_DBITERR_B_reg <= 1'b0; CAS_IN_DOUT_B_reg <= D_INIT; CAS_IN_RDACCESS_B_reg <= 1'b0; CAS_IN_SBITERR_B_reg <= 1'b0; end else begin if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) begin CAS_IN_RDACCESS_B_reg <= CAS_IN_RDACCESS_B_in; if (CAS_IN_RDACCESS_B_in) begin CAS_IN_DBITERR_B_reg <= CAS_IN_DBITERR_B_in; CAS_IN_DOUT_B_reg <= CAS_IN_DOUT_B_in; CAS_IN_SBITERR_B_reg <= CAS_IN_SBITERR_B_in; end end end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_A_async) begin if (RST_A_async || RST_A_in || glblGSR || `else always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin if (RST_A_in || glblGSR || `endif shut_down || SHUTDOWN_in) begin RDACCESS_A_int = 1'b0; end else begin if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_ECC_CE_A_in) begin RDACCESS_A_int = RDACCESS_A_ecc_reg; end else begin RDACCESS_A_int = 1'b0; end end else if (OREG_A_BIN == OREG_A_TRUE) begin if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_CE_A_in) begin RDACCESS_A_int = RDACCESS_A_reg; end else begin RDACCESS_A_int = 1'b0; end end else begin RDACCESS_A_int = RDACCESS_A_lat; end end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_B_async) begin if (RST_B_async || RST_B_in || glblGSR || `else always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin if (RST_B_in || glblGSR || `endif shut_down || SHUTDOWN_in) begin RDACCESS_B_int = 1'b0; end else begin if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_ECC_CE_B_in) begin RDACCESS_B_int = RDACCESS_B_ecc_reg; end else begin RDACCESS_B_int = 1'b0; end end else if (OREG_B_BIN == OREG_B_TRUE) begin if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_CE_B_in) begin RDACCESS_B_int = RDACCESS_B_reg; end else begin RDACCESS_B_int = 1'b0; end end else begin RDACCESS_B_int = RDACCESS_B_lat; end end end reg cas_out_mux_sel_a; reg cas_out_mux_sel_b; reg cas_out_mux_sel_a_reg; reg cas_out_mux_sel_b_reg; always @ (*) begin if ((CAS_IN_RDACCESS_A_in && REG_CAS_A_BIN == REG_CAS_A_FALSE) || (CAS_IN_RDACCESS_A_reg && REG_CAS_A_BIN == REG_CAS_A_TRUE) || RDACCESS_A_int) begin cas_out_mux_sel_a = ~RDACCESS_A_int; end else begin cas_out_mux_sel_a = ~cas_out_mux_sel_a_reg; end end always @ (*) begin if ((CAS_IN_RDACCESS_B_in && (REG_CAS_B_BIN == REG_CAS_B_FALSE)) || (CAS_IN_RDACCESS_B_reg && (REG_CAS_B_BIN == REG_CAS_B_TRUE)) || RDACCESS_B_int) begin cas_out_mux_sel_b = ~RDACCESS_B_int; end else begin cas_out_mux_sel_b = ~cas_out_mux_sel_b_reg; end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_A_async) begin if (RST_A_async || RST_A_in || glblGSR) begin `else always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin if (RST_A_in || glblGSR) begin `endif cas_out_mux_sel_a_reg <= 1'b0; end else begin cas_out_mux_sel_a_reg <= ~cas_out_mux_sel_a; end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_B_async) begin if (RST_B_async || RST_B_in || glblGSR) begin `else always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin if (RST_B_in || glblGSR) begin `endif cas_out_mux_sel_b_reg <= 1'b0; end else begin cas_out_mux_sel_b_reg <= ~cas_out_mux_sel_b; end end // data out mux always @ (*) begin if (RST_A_async || RST_A_sync || glblGSR) begin RDACCESS_A_out = 1'b0; end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && cas_out_mux_sel_a) begin if (REG_CAS_A_BIN == REG_CAS_A_TRUE) begin RDACCESS_A_out = CAS_IN_RDACCESS_A_reg; end else begin RDACCESS_A_out = CAS_IN_RDACCESS_A_in; end end else begin RDACCESS_A_out = RDACCESS_A_int; end end always @ (*) begin if (RST_A_async || RST_A_sync || shut_down || glblGSR) begin DBITERR_A_out = 1'b0; SBITERR_A_out = 1'b0; end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && cas_out_mux_sel_a) begin if (REG_CAS_A_BIN == REG_CAS_A_TRUE) begin DBITERR_A_out = CAS_IN_DBITERR_A_reg; SBITERR_A_out = CAS_IN_SBITERR_A_reg; end else begin DBITERR_A_out = CAS_IN_DBITERR_A_in; SBITERR_A_out = CAS_IN_SBITERR_A_in; end end else if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin DBITERR_A_out = DBITERR_A_reg; SBITERR_A_out = SBITERR_A_reg; end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin DBITERR_A_out = DBITERR_A_ecc; SBITERR_A_out = SBITERR_A_ecc; end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_A_async) begin if (RST_A_async || RST_A_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin `else always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin if (RST_A_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin `endif data_A_enable <= 1'b0; end else if ((OREG_A_BIN == OREG_A_TRUE) && ram_ce_a && ~ram_we_a) begin data_A_enable <= 1'b1; end else if ((OREG_A_BIN == OREG_A_FALSE) && ram_ce_a_int && ~RDB_WR_A_int) begin data_A_enable <= 1'b1; end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_B_async) begin if (RST_B_async || RST_B_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin `else always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin if (RST_B_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin `endif data_B_enable <= 1'b0; end else if ((OREG_B_BIN == OREG_B_TRUE) && ram_ce_b && ~ram_we_b) begin data_B_enable <= 1'b1; end else if ((OREG_B_BIN == OREG_B_FALSE) && ram_ce_b_int && ~RDB_WR_B_int) begin data_B_enable <= 1'b1; end end always @ (posedge CLK_in) begin if (ram_ce_a && ~ram_we_a && SLEEP_in && ~a_sleep && (OREG_A_BIN == OREG_A_TRUE)) begin $display("Warning: [Unisim %s-3] At time (%.3f) ns: Port A READ access at ADDR (%h) just prior to SLEEP with SLEEP asserted and OREG_A attribute set to (%s) will result in READ data getting lost. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a, OREG_A_REG); end else if (ram_ce_a && ram_we_a && SLEEP_in && ~a_sleep) begin $display("Warning: [Unisim %s-4] At time (%.3f) ns: Port A WRITE access at ADDR (%h) just prior to SLEEP with SLEEP asserted will result in WRITE data getting ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a); end else if (ram_ce_a_pre && a_sleep && SLEEP_in) begin $display("Warning: [Unisim %s-5] At time (%.3f) ns: Port A access at ADDR (%h) during SLEEP will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a); end else if (ram_ce_a_pre && a_sleep && ~SLEEP_in) begin $display("Warning: [Unisim %s-6] At time (%.3f) ns: Port A access at ADDR (%h) during WAKEUP time will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a); end end always @ (posedge CLK_in) begin if (ram_ce_b && ~ram_we_b && SLEEP_in && ~a_sleep && (OREG_B_BIN == OREG_B_TRUE)) begin $display("Warning: [Unisim %s-7] At time (%.3f) ns: Port B READ access at ADDR (%h) just prior to SLEEP with SLEEP asserted and OREG_B attribute set to (%s) will result in READ data getting lost. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b, OREG_B_REG); end else if (ram_ce_b && ram_we_b && SLEEP_in && ~a_sleep) begin $display("Warning: [Unisim %s-8] At time (%.3f) ns: Port B WRITE access at ADDR (%h) just prior to SLEEP with SLEEP asserted will result in WRITE data getting ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b); end else if (ram_ce_b_pre && a_sleep && SLEEP_in) begin $display("Warning: [Unisim %s-9] At time (%.3f) ns: Port B access at ADDR (%h) during SLEEP will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b); end else if (ram_ce_b_pre && a_sleep && ~SLEEP_in) begin $display("Warning: [Unisim %s-10] At time (%.3f) ns: Port B access at ADDR (%h) during WAKEUP time will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b); end end always @ (*) begin if (RST_A_async || RST_A_sync || glblGSR) begin DOUT_A_out = D_INIT; end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) || (CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) && cas_out_mux_sel_a) begin if (REG_CAS_A_BIN == REG_CAS_A_TRUE) begin DOUT_A_out = CAS_IN_DOUT_A_reg; end else begin DOUT_A_out = CAS_IN_DOUT_A_in; end end else if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin DOUT_A_out = DOUT_A_reg; end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin DOUT_A_out = ram_data_a_ecc; end else if (data_A_enable) begin if (OREG_A_BIN == OREG_A_TRUE) begin DOUT_A_out = ram_data_a_reg; end else begin DOUT_A_out = ram_data_a_lat; end end else begin DOUT_A_out = D_INIT; end end always @ (*) begin if (RST_B_async || RST_B_sync || glblGSR) begin RDACCESS_B_out = 1'b0; end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && cas_out_mux_sel_b) begin if (REG_CAS_B_BIN == REG_CAS_B_TRUE) begin RDACCESS_B_out = CAS_IN_RDACCESS_B_reg; end else begin RDACCESS_B_out = CAS_IN_RDACCESS_B_in; end end else begin RDACCESS_B_out = RDACCESS_B_int; end end always @ (*) begin if (RST_B_async || RST_B_sync || shut_down || glblGSR) begin DBITERR_B_out = 1'b0; SBITERR_B_out = 1'b0; end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && cas_out_mux_sel_b) begin if (REG_CAS_B_BIN == REG_CAS_B_TRUE) begin DBITERR_B_out = CAS_IN_DBITERR_B_reg; SBITERR_B_out = CAS_IN_SBITERR_B_reg; end else begin DBITERR_B_out = CAS_IN_DBITERR_B_in; SBITERR_B_out = CAS_IN_SBITERR_B_in; end end else if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin DBITERR_B_out = DBITERR_B_reg; SBITERR_B_out = SBITERR_B_reg; end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin DBITERR_B_out = DBITERR_B_ecc; SBITERR_B_out = SBITERR_B_ecc; end end always @ (*) begin if (RST_B_async || RST_B_sync || glblGSR) begin DOUT_B_out = D_INIT; end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) || (CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) && cas_out_mux_sel_b) begin if (REG_CAS_B_BIN == REG_CAS_B_TRUE) begin DOUT_B_out = CAS_IN_DOUT_B_reg; end else begin DOUT_B_out = CAS_IN_DOUT_B_in; end end else if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin DOUT_B_out = DOUT_B_reg; end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin DOUT_B_out = ram_data_b_ecc; end else if (data_B_enable) begin if (OREG_B_BIN == OREG_B_TRUE) begin DOUT_B_out = ram_data_b_reg; end else begin DOUT_B_out = ram_data_b_lat; end end else begin DOUT_B_out = D_INIT; end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_A_async) begin if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin `else always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin `endif DBITERR_A_reg <= 1'b0; SBITERR_A_reg <= 1'b0; end else if ((~a_sleep && ~shut_down && data_A_enable) && (((OREG_A_BIN == OREG_A_TRUE) && (RDACCESS_A_reg || RDACCESS_A_ecc_reg)) || ((OREG_A_BIN == OREG_A_FALSE) && (RDACCESS_A_lat || RDACCESS_A_ecc_reg)))) begin if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_ECC_CE_A_in) begin DBITERR_A_reg <= DBITERR_A_ecc; SBITERR_A_reg <= SBITERR_A_ecc; end end end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_A_async) begin if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin `else always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin `endif DOUT_A_reg <= D_INIT; end else if (~shut_down && data_A_enable) begin if (USE_EXT_CE_A_BIN == USE_EXT_CE_A_TRUE) begin if (OREG_ECC_CE_A_in) begin if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin DOUT_A_reg <= ram_data_a_ecc; end else if (OREG_A_BIN == OREG_A_TRUE) begin DOUT_A_reg <= ram_data_a_reg; end else begin DOUT_A_reg <= ram_data_a_lat; end end end else if (((OREG_A_BIN == OREG_A_TRUE) && (RDACCESS_A_reg || RDACCESS_A_ecc_reg)) || ((OREG_A_BIN == OREG_A_FALSE) && (RDACCESS_A_lat || RDACCESS_A_ecc_reg))) begin if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin DOUT_A_reg <= ram_data_a_ecc; end else if (OREG_A_BIN == OREG_A_TRUE) begin DOUT_A_reg <= ram_data_a_reg; end else begin DOUT_A_reg <= ram_data_a_lat; end end end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_A_async) begin if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin `else always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin `endif RDACCESS_A_ecc_reg <= 1'b0; end else begin if (OREG_A_BIN == OREG_A_TRUE) begin if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_CE_A_in) begin RDACCESS_A_ecc_reg <= RDACCESS_A_reg; end end else begin RDACCESS_A_ecc_reg <= RDACCESS_A_lat; end end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_B_async) begin if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin `else always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin `endif DBITERR_B_reg <= 1'b0; SBITERR_B_reg <= 1'b0; end else if ((~a_sleep && ~shut_down && data_B_enable) && (((OREG_B_BIN == OREG_B_TRUE) && (RDACCESS_B_reg || RDACCESS_B_ecc_reg)) || ((OREG_B_BIN == OREG_B_FALSE) && (RDACCESS_B_lat || RDACCESS_B_ecc_reg)))) begin if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_ECC_CE_B_in) begin DBITERR_B_reg <= DBITERR_B_ecc; SBITERR_B_reg <= SBITERR_B_ecc; end end end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_B_async) begin if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin `else always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin `endif DOUT_B_reg <= D_INIT; end else if (~shut_down && data_B_enable) begin if (USE_EXT_CE_B_BIN == USE_EXT_CE_B_TRUE) begin if (OREG_ECC_CE_B_in) begin if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin DOUT_B_reg <= ram_data_b_ecc; end else if (OREG_B_BIN == OREG_B_TRUE) begin DOUT_B_reg <= ram_data_b_reg; end else begin DOUT_B_reg <= ram_data_b_lat; end end end else if (((OREG_B_BIN == OREG_B_TRUE) && (RDACCESS_B_reg || RDACCESS_B_ecc_reg)) || ((OREG_B_BIN == OREG_B_FALSE) && (RDACCESS_B_lat || RDACCESS_B_ecc_reg))) begin if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin DOUT_B_reg <= ram_data_b_ecc; end else if (OREG_B_BIN == OREG_B_TRUE) begin DOUT_B_reg <= ram_data_b_reg; end else begin DOUT_B_reg <= ram_data_b_lat; end end end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_B_async) begin if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin `else always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin `endif RDACCESS_B_ecc_reg <= 1'b0; end else begin if (OREG_B_BIN == OREG_B_TRUE) begin if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_CE_B_in) begin RDACCESS_B_ecc_reg <= RDACCESS_B_reg; end end else begin RDACCESS_B_ecc_reg <= RDACCESS_B_lat; end end end // ram oreg `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_A_async) begin if (RST_A_async || RST_A_in || shut_down || a_sleep || glblGSR) begin `else always @ (posedge CLK_in or posedge RST_A_async or shut_down or glblGSR) begin if (RST_A_in || shut_down || a_sleep || glblGSR) begin `endif RDACCESS_A_reg <= 1'b0; end else begin RDACCESS_A_reg <= RDACCESS_A_lat; end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_A_async) begin if (RST_A_async || RST_A_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_A_BIN == OREG_A_FALSE)) begin `else always @ (posedge CLK_in or posedge RST_A_async or shut_down or glblGSR) begin if (RST_A_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_A_BIN == OREG_A_FALSE)) begin `endif ram_data_a_reg <= D_INIT; end else if (USE_EXT_CE_A_BIN == USE_EXT_CE_A_TRUE) begin if (OREG_CE_A_in) begin ram_data_a_reg = ram_data_a_lat; end end else if (ram_ce_a_int || RDACCESS_A_reg) begin ram_data_a_reg = ram_data_a_lat; end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_B_async) begin if (RST_B_async || RST_B_in || shut_down || a_sleep || glblGSR) begin `else always @ (posedge CLK_in or posedge RST_B_async or shut_down or glblGSR) begin if (RST_B_in || shut_down || a_sleep || glblGSR) begin `endif RDACCESS_B_reg <= 1'b0; end else begin RDACCESS_B_reg <= RDACCESS_B_lat; end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_B_async) begin if (RST_B_async || RST_B_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_B_BIN == OREG_B_FALSE)) begin `else always @ (posedge CLK_in or posedge RST_B_async or shut_down or glblGSR) begin if (RST_B_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_B_BIN == OREG_B_FALSE)) begin `endif ram_data_b_reg <= D_INIT; end else if (USE_EXT_CE_B_BIN == USE_EXT_CE_B_TRUE) begin if (OREG_CE_B_in) begin ram_data_b_reg = ram_data_b_lat; end end else if (ram_ce_b_int || RDACCESS_B_reg) begin ram_data_b_reg = ram_data_b_lat; end end reg [15:1] ram_ce_a_fifo_in = 15'b0; always @ (*) begin ram_ce_a_fifo_in = 15'b0; ram_ce_a_fifo_in[AUTO_SLEEP_LATENCY_BIN] = &(~(ADDR_A_int[22:12] ^ SELF_ADDR_A_REG) | SELF_MASK_A_REG) && EN_A_int; end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin ram_ce_a_fifo <= 15'b0; end else begin ram_ce_a_fifo <= {1'b0, ram_ce_a_fifo[15:2]} | ram_ce_a_fifo_in; end end always @ (*) begin if (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE) begin ram_ce_a_pre = &(~(ADDR_A_int[22:12] ^ SELF_ADDR_A_REG) | SELF_MASK_A_REG) && EN_A_int; end else begin ram_ce_a_pre = ram_ce_a_fifo[1]; end end always @ (*) begin if (a_sleep || SLEEP_in || auto_sleep) begin ram_ce_a_int = 1'b0; end else begin ram_ce_a_int = ram_ce_a_pre; end end reg [15:1] ram_ce_b_fifo_in = 15'b0; always @ (*) begin ram_ce_b_fifo_in = 15'b0; ram_ce_b_fifo_in[AUTO_SLEEP_LATENCY_BIN] = &(~(ADDR_B_int[22:12] ^ SELF_ADDR_B_REG) | SELF_MASK_B_REG) && EN_B_int; end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin ram_ce_b_fifo <= 15'b0; end else begin ram_ce_b_fifo <= {1'b0, ram_ce_b_fifo[15:2]} | ram_ce_b_fifo_in; end end always @ (*) begin if (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE) begin ram_ce_b_pre = &(~(ADDR_B_int[22:12] ^ SELF_ADDR_B_REG) | SELF_MASK_B_REG) && EN_B_int; end else begin ram_ce_b_pre = ram_ce_b_fifo[1]; end end always @ (*) begin if (a_sleep || SLEEP_in || auto_sleep) begin ram_ce_b_int = 1'b0; end else begin ram_ce_b_int = ram_ce_b_pre; end end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || ~RDB_WR_A_int || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin ram_bwe_a <= 72'h00; end else if (ram_ce_a_int) begin if (EN_ECC_WR_A_BIN == EN_ECC_WR_A_TRUE) begin ram_bwe_a <= 72'hFFFFFFFFFFFFFFFFFF; end else if (BWE_MODE_A_BIN == BWE_MODE_A_PARITY_INTERLEAVED) begin ram_bwe_a <= {BWE_A_int[7:0], {8{BWE_A_int[7]}}, {8{BWE_A_int[6]}}, {8{BWE_A_int[5]}}, {8{BWE_A_int[4]}}, {8{BWE_A_int[3]}}, {8{BWE_A_int[2]}}, {8{BWE_A_int[1]}}, {8{BWE_A_int[0]}}}; end else begin ram_bwe_a <= {{8{BWE_A_int[8]}}, {8{BWE_A_int[7]}}, {8{BWE_A_int[6]}}, {8{BWE_A_int[5]}}, {8{BWE_A_int[4]}}, {8{BWE_A_int[3]}}, {8{BWE_A_int[2]}}, {8{BWE_A_int[1]}}, {8{BWE_A_int[0]}}}; end end end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || ~RDB_WR_B_int || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin ram_bwe_b <= 72'b0; end else if (ram_ce_b_int) begin if (EN_ECC_WR_B_BIN == EN_ECC_WR_B_TRUE) begin ram_bwe_b <= 72'hFFFFFFFFFFFFFFFFFF; end else if (BWE_MODE_B_BIN == BWE_MODE_B_PARITY_INTERLEAVED) begin ram_bwe_b <= {BWE_B_int[7:0], {8{BWE_B_int[7]}}, {8{BWE_B_int[6]}}, {8{BWE_B_int[5]}}, {8{BWE_B_int[4]}}, {8{BWE_B_int[3]}}, {8{BWE_B_int[2]}}, {8{BWE_B_int[1]}}, {8{BWE_B_int[0]}}}; end else begin ram_bwe_b <= {{8{BWE_B_int[8]}}, {8{BWE_B_int[7]}}, {8{BWE_B_int[6]}}, {8{BWE_B_int[5]}}, {8{BWE_B_int[4]}}, {8{BWE_B_int[3]}}, {8{BWE_B_int[2]}}, {8{BWE_B_int[1]}}, {8{BWE_B_int[0]}}}; end end end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin ram_addr_a <= 12'b0; end else if (ram_ce_a_int) begin ram_addr_a <= ADDR_A_int[11:0]; end end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin ram_addr_b <= 12'b0; end else if (ram_ce_b_int) begin ram_addr_b <= ADDR_B_int[11:0]; end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_A_async) begin if (glblGSR || (RST_A_async || RST_A_in) || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin `else always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin if (glblGSR || RST_A_in || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin `endif ram_ce_a <= 1'b0; end else begin ram_ce_a <= ram_ce_a_int; end end `ifdef XIL_XECLIB always @ (posedge CLK_in or posedge RST_B_async) begin if (glblGSR || (RST_B_async || RST_B_in) || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin `else always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin if (glblGSR || RST_B_in || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin `endif ram_ce_b <= 1'b0; end else begin ram_ce_b <= ram_ce_b_int; end end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in || ~ram_ce_a_int) begin ram_we_a <= 1'b0; end else begin ram_we_a <= RDB_WR_A_int; if (RDB_WR_A_int) ram_we_a_event <= ~ram_we_a_event; end end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in || ~ram_ce_b_int) begin ram_we_b <= 1'b0; end else begin ram_we_b <= RDB_WR_B_int; if (RDB_WR_B_int) ram_we_b_event <= ~ram_we_b_event; end end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin ram_data_a <= D_INIT; end else if (RDB_WR_A_int && ram_ce_a_int) begin if (EN_ECC_WR_A_BIN == EN_ECC_WR_A_TRUE) begin ram_data_a[63:0] <= {DIN_A_int[63], DIN_A_int[62] ^ (INJECT_DBITERR_A_int), DIN_A_int[61:31], DIN_A_int[30] ^ (INJECT_DBITERR_A_int || INJECT_SBITERR_A_int), DIN_A_int[29:0]}; ram_data_a[71:64] <= fn_ecc(encode, DIN_A_int[63:0], DIN_A_int[71:64]); end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin ram_data_a[63:0] <= {DIN_A_int[63], DIN_A_int[62] ^ (INJECT_DBITERR_A_int), DIN_A_int[61:31], DIN_A_int[30] ^ (INJECT_DBITERR_A_int || INJECT_SBITERR_A_int), DIN_A_int[29:0]}; ram_data_a[71:64] <= DIN_A_int[71:64]; end else begin ram_data_a <= DIN_A_int; end end end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin ram_data_b <= D_INIT; end else if (RDB_WR_B_int && ram_ce_b_int) begin if (EN_ECC_WR_B_BIN == EN_ECC_WR_B_TRUE) begin ram_data_b[63:0] <= {DIN_B_int[63], DIN_B_int[62] ^ (INJECT_DBITERR_B_int), DIN_B_int[61:31], DIN_B_int[30] ^ (INJECT_DBITERR_B_int || INJECT_SBITERR_B_int), DIN_B_int[29:0]}; ram_data_b[71:64] <= fn_ecc(encode, DIN_B_int[63:0], DIN_B_int[71:64]); end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin ram_data_b[63:0] <= {DIN_B_int[63], DIN_B_int[62] ^ (INJECT_DBITERR_B_int), DIN_B_int[61:31], DIN_B_int[30] ^ (INJECT_DBITERR_B_int || INJECT_SBITERR_B_int), DIN_B_int[29:0]}; ram_data_b[71:64] <= DIN_B_int[71:64]; end else begin ram_data_b <= DIN_B_int; end end end // ram always @ (*) begin if ((auto_sleep || SLEEP_in || SHUTDOWN_in || DEEPSLEEP_in) || (((OREG_A_BIN == OREG_A_TRUE) || (OREG_ECC_A_BIN == OREG_ECC_A_TRUE )) && (a_sleep || shut_down)))begin RDACCESS_A_lat <= 1'b0; end else if ((ram_ce_a_int === 1'b1) && (RDB_WR_A_int === 1'b0)) begin RDACCESS_A_lat <= 1'b1; end else begin RDACCESS_A_lat <= 1'b0; end end always @ (*) begin if ((auto_sleep || SLEEP_in || SHUTDOWN_in || DEEPSLEEP_in) || (((OREG_B_BIN == OREG_B_TRUE) || (OREG_ECC_B_BIN == OREG_ECC_B_TRUE )) && (a_sleep || shut_down)))begin RDACCESS_B_lat <= 1'b0; end else if ((ram_ce_b_int === 1'b1) && (RDB_WR_B_int === 1'b0)) begin RDACCESS_B_lat <= 1'b1; end else begin RDACCESS_B_lat <= 1'b0; end end `ifndef XIL_XECLIB // always @ (posedge INIT_RAM or posedge glblGSR) begin always @ (posedge INIT_RAM) begin for (wa=0;wa<mem_depth;wa=wa+1) begin mem[wa] <= D_INIT; end end always @ (posedge shut_down) begin for (wa=0;wa<mem_depth;wa=wa+1) begin mem[wa] <= D_UNDEF; end end `endif always @ (*) begin if (RST_A_sync || RST_A_async || glblGSR || a_sleep || shut_down) begin ram_data_a_lat = D_INIT; end else if (ram_ce_a && ~ram_we_a) begin ram_data_a_lat = ram_data_a_out; end end always @ (*) begin if (RST_B_sync || RST_B_async || glblGSR || a_sleep || shut_down) begin ram_data_b_lat = D_INIT; end else if (ram_ce_b && ~ram_we_b) begin ram_data_b_lat = ram_data_b_out; end end `ifdef XIL_XECLIB always @ (posedge RST_A_async or posedge RST_B_async or posedge CLK_in) begin `else always @ (ram_we_a or ram_we_b or ram_ce_a or ram_ce_b or a_sleep or shut_down or ram_addr_a or ram_addr_b or ram_data_a or ram_data_b or ram_bwe_a or ram_bwe_b or ram_we_a_event or ram_we_b_event or posedge RST_A_async or posedge RST_B_async or posedge RST_A_sync or posedge RST_B_sync or glblGSR) begin `endif if (RST_A_async || RST_A_sync || shut_down || glblGSR) begin ram_data_a_out = D_INIT; end if (ram_we_a && ~shut_down && ~a_sleep && ~glblGSR) begin mem [ram_addr_a] = (ram_data_a & ram_bwe_a) | (mem [ram_addr_a] & ~ram_bwe_a); end if (ram_ce_a && ~ram_we_a && ~RST_A_in && ~shut_down && ~a_sleep && ~glblGSR) begin ram_data_a_out = mem[ram_addr_a]; end if (RST_B_async || RST_B_sync || shut_down || glblGSR) begin ram_data_b_out = D_INIT; end if (ram_we_b && ~shut_down && ~a_sleep && ~glblGSR) begin mem [ram_addr_b] = (ram_data_b & ram_bwe_b) | (mem [ram_addr_b] & ~ram_bwe_b); end if (ram_ce_b && ~ram_we_b && ~RST_B_in && ~shut_down && ~a_sleep && ~glblGSR) begin ram_data_b_out = mem[ram_addr_b]; end end // ecc correction task ecc_cor; output [71:0] data_cor; output sbiterr; output dbiterr; input [71:0] data; reg [7:0] synd_rd; reg [7:0] synd_ecc; reg decode; begin decode = 1'b0; synd_rd = fn_ecc(decode, data[63:0], data[71:64]); synd_ecc = synd_rd ^ data[71:64]; sbiterr = (|synd_ecc && synd_ecc[7]); dbiterr = (|synd_ecc && ~synd_ecc[7]); if (sbiterr) begin data_cor = fn_cor_bit(synd_ecc[6:0],data[63:0],data[71:64]); end else begin data_cor = data; end end endtask always @ (*) begin if (a_sleep || shut_down || glblGSR || (EN_ECC_RD_A_BIN == EN_ECC_RD_A_FALSE)) begin ram_data_a_ecc <= D_INIT; end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin if (OREG_A_BIN == OREG_A_TRUE) begin ecc_cor(ram_data_a_ecc, SBITERR_A_ecc, DBITERR_A_ecc, ram_data_a_reg); end else begin ecc_cor(ram_data_a_ecc, SBITERR_A_ecc, DBITERR_A_ecc, ram_data_a_lat); end end end always @ (*) begin if (a_sleep || shut_down || glblGSR || (EN_ECC_RD_B_BIN == EN_ECC_RD_B_FALSE)) begin ram_data_b_ecc <= D_INIT; end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin if (OREG_B_BIN == OREG_B_TRUE) begin ecc_cor(ram_data_b_ecc, SBITERR_B_ecc, DBITERR_B_ecc, ram_data_b_reg); end else begin ecc_cor(ram_data_b_ecc, SBITERR_B_ecc, DBITERR_B_ecc, ram_data_b_lat); end end end // sleep, deepsleep, shutdown `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR) begin wake_count <= 0; end else if (((wake_count > 0) && (~(auto_sleep || SLEEP_in || DEEPSLEEP_in || SHUTDOWN_in))) || (~(SHUTDOWN_in || DEEPSLEEP_in) && (wake_count > 2)) || (~SHUTDOWN_in && (wake_count > 3))) begin wake_count <= wake_count - 1; end else if (SHUTDOWN_in) begin wake_count <= 9; end else if (DEEPSLEEP_in && (wake_count <= 3)) begin wake_count <= 3; end else if (SLEEP_in && (wake_count <= 2)) begin wake_count <= 2; end else if (auto_sleep && (wake_count <= 1)) begin wake_count <= 1; end end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || (~auto_sleep && wake_count == 1)) begin a_sleep <= 1'b0; end else if (DEEPSLEEP_in || SLEEP_in || auto_sleep) begin a_sleep <= 1'b1; end end `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || (wake_count == 1)) begin shut_down <= 1'b0; end else if (SHUTDOWN_in) begin shut_down <= 1'b1; end end assign auto_sleep = auto_sleep_A && auto_sleep_B && ~auto_wake_up_A && ~auto_wake_up_B; assign auto_wake_up_A = ram_ce_a_fifo[3]; `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin auto_sleep_A <= 1'b0; end else if (auto_wake_up_A && auto_sleep_A) begin auto_sleep_A <= 1'b0; end else if (~|ram_ce_a_fifo && ~auto_sleep_A) begin auto_sleep_A <= 1'b1; end end assign auto_wake_up_B = ram_ce_b_fifo[3]; `ifdef XIL_XECLIB always @ (posedge CLK_in) begin `else always @ (posedge CLK_in or glblGSR) begin `endif if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin auto_sleep_B <= 1'b0; end else if (auto_wake_up_B && auto_sleep_B) begin auto_sleep_B <= 1'b0; end else if (~|ram_ce_b_fifo && ~auto_sleep_B) begin auto_sleep_B <= 1'b1; end end // end behavioral model `ifndef XIL_XECLIB `ifdef XIL_TIMING wire clk_en_n; wire clk_en_p; assign clk_en_n = IS_CLK_INVERTED_REG; assign clk_en_p = ~IS_CLK_INVERTED_REG; `endif specify (ADDR_A *> CAS_OUT_ADDR_A) = (0:0:0, 0:0:0); (ADDR_B *> CAS_OUT_ADDR_B) = (0:0:0, 0:0:0); (BWE_A *> CAS_OUT_BWE_A) = (0:0:0, 0:0:0); (BWE_B *> CAS_OUT_BWE_B) = (0:0:0, 0:0:0); (CAS_IN_ADDR_A *> CAS_OUT_ADDR_A) = (0:0:0, 0:0:0); (CAS_IN_ADDR_B *> CAS_OUT_ADDR_B) = (0:0:0, 0:0:0); (CAS_IN_BWE_A *> CAS_OUT_BWE_A) = (0:0:0, 0:0:0); (CAS_IN_BWE_B *> CAS_OUT_BWE_B) = (0:0:0, 0:0:0); (CAS_IN_DBITERR_A => CAS_OUT_DBITERR_A) = (0:0:0, 0:0:0); (CAS_IN_DBITERR_A => DBITERR_A) = (0:0:0, 0:0:0); (CAS_IN_DBITERR_B => CAS_OUT_DBITERR_B) = (0:0:0, 0:0:0); (CAS_IN_DBITERR_B => DBITERR_B) = (0:0:0, 0:0:0); (CAS_IN_DIN_A *> CAS_OUT_DIN_A) = (0:0:0, 0:0:0); (CAS_IN_DIN_B *> CAS_OUT_DIN_B) = (0:0:0, 0:0:0); (CAS_IN_DOUT_A *> CAS_OUT_DOUT_A) = (0:0:0, 0:0:0); (CAS_IN_DOUT_A *> DOUT_A) = (0:0:0, 0:0:0); (CAS_IN_DOUT_B *> CAS_OUT_DOUT_B) = (0:0:0, 0:0:0); (CAS_IN_DOUT_B *> DOUT_B) = (0:0:0, 0:0:0); (CAS_IN_EN_A => CAS_OUT_EN_A) = (0:0:0, 0:0:0); (CAS_IN_EN_B => CAS_OUT_EN_B) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_A *> CAS_OUT_DOUT_A) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_A *> DOUT_A) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_A => CAS_OUT_DBITERR_A) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_A => CAS_OUT_RDACCESS_A) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_A => CAS_OUT_SBITERR_A) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_A => DBITERR_A) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_A => RDACCESS_A) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_A => SBITERR_A) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_B *> CAS_OUT_DOUT_B) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_B *> DOUT_B) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_B => CAS_OUT_DBITERR_B) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_B => CAS_OUT_RDACCESS_B) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_B => CAS_OUT_SBITERR_B) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_B => DBITERR_B) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_B => RDACCESS_B) = (0:0:0, 0:0:0); (CAS_IN_RDACCESS_B => SBITERR_B) = (0:0:0, 0:0:0); (CAS_IN_RDB_WR_A => CAS_OUT_RDB_WR_A) = (0:0:0, 0:0:0); (CAS_IN_RDB_WR_B => CAS_OUT_RDB_WR_B) = (0:0:0, 0:0:0); (CAS_IN_SBITERR_A => CAS_OUT_SBITERR_A) = (0:0:0, 0:0:0); (CAS_IN_SBITERR_A => SBITERR_A) = (0:0:0, 0:0:0); (CAS_IN_SBITERR_B => CAS_OUT_SBITERR_B) = (0:0:0, 0:0:0); (CAS_IN_SBITERR_B => SBITERR_B) = (0:0:0, 0:0:0); (CLK *> CAS_OUT_ADDR_A) = (100:100:100, 100:100:100); (CLK *> CAS_OUT_ADDR_B) = (100:100:100, 100:100:100); (CLK *> CAS_OUT_BWE_A) = (100:100:100, 100:100:100); (CLK *> CAS_OUT_BWE_B) = (100:100:100, 100:100:100); (CLK *> CAS_OUT_DIN_A) = (100:100:100, 100:100:100); (CLK *> CAS_OUT_DIN_B) = (100:100:100, 100:100:100); (CLK *> CAS_OUT_DOUT_A) = (100:100:100, 100:100:100); (CLK *> CAS_OUT_DOUT_B) = (100:100:100, 100:100:100); (CLK *> DOUT_A) = (100:100:100, 100:100:100); (CLK *> DOUT_B) = (100:100:100, 100:100:100); (CLK => CAS_OUT_DBITERR_A) = (100:100:100, 100:100:100); (CLK => CAS_OUT_DBITERR_B) = (100:100:100, 100:100:100); (CLK => CAS_OUT_EN_A) = (100:100:100, 100:100:100); (CLK => CAS_OUT_EN_B) = (100:100:100, 100:100:100); (CLK => CAS_OUT_RDACCESS_A) = (100:100:100, 100:100:100); (CLK => CAS_OUT_RDACCESS_B) = (100:100:100, 100:100:100); (CLK => CAS_OUT_RDB_WR_A) = (100:100:100, 100:100:100); (CLK => CAS_OUT_RDB_WR_B) = (100:100:100, 100:100:100); (CLK => CAS_OUT_SBITERR_A) = (100:100:100, 100:100:100); (CLK => CAS_OUT_SBITERR_B) = (100:100:100, 100:100:100); (CLK => DBITERR_A) = (100:100:100, 100:100:100); (CLK => DBITERR_B) = (100:100:100, 100:100:100); (CLK => RDACCESS_A) = (100:100:100, 100:100:100); (CLK => RDACCESS_B) = (100:100:100, 100:100:100); (CLK => SBITERR_A) = (100:100:100, 100:100:100); (CLK => SBITERR_B) = (100:100:100, 100:100:100); (DIN_A *> CAS_OUT_DIN_A) = (0:0:0, 0:0:0); (DIN_B *> CAS_OUT_DIN_B) = (0:0:0, 0:0:0); (EN_A => CAS_OUT_EN_A) = (0:0:0, 0:0:0); (EN_B => CAS_OUT_EN_B) = (0:0:0, 0:0:0); (RDB_WR_A => CAS_OUT_RDB_WR_A) = (0:0:0, 0:0:0); (RDB_WR_B => CAS_OUT_RDB_WR_B) = (0:0:0, 0:0:0); (negedge RST_A *> (CAS_OUT_DOUT_A +: 0)) = (100:100:100, 100:100:100); (negedge RST_A *> (DOUT_A +: 0)) = (100:100:100, 100:100:100); (negedge RST_A => (CAS_OUT_DBITERR_A +: 0)) = (100:100:100, 100:100:100); (negedge RST_A => (CAS_OUT_RDACCESS_A +: 0)) = (100:100:100, 100:100:100); (negedge RST_A => (CAS_OUT_SBITERR_A +: 0)) = (100:100:100, 100:100:100); (negedge RST_A => (DBITERR_A +: 0)) = (100:100:100, 100:100:100); (negedge RST_A => (RDACCESS_A +: 0)) = (100:100:100, 100:100:100); (negedge RST_A => (SBITERR_A +: 0)) = (100:100:100, 100:100:100); (negedge RST_B *> (CAS_OUT_DOUT_B +: 0)) = (100:100:100, 100:100:100); (negedge RST_B *> (DOUT_B +: 0)) = (100:100:100, 100:100:100); (negedge RST_B => (CAS_OUT_DBITERR_B +: 0)) = (100:100:100, 100:100:100); (negedge RST_B => (CAS_OUT_RDACCESS_B +: 0)) = (100:100:100, 100:100:100); (negedge RST_B => (CAS_OUT_SBITERR_B +: 0)) = (100:100:100, 100:100:100); (negedge RST_B => (DBITERR_B +: 0)) = (100:100:100, 100:100:100); (negedge RST_B => (RDACCESS_B +: 0)) = (100:100:100, 100:100:100); (negedge RST_B => (SBITERR_B +: 0)) = (100:100:100, 100:100:100); (posedge RST_A *> (CAS_OUT_DOUT_A +: 0)) = (100:100:100, 100:100:100); (posedge RST_A *> (DOUT_A +: 0)) = (100:100:100, 100:100:100); (posedge RST_A => (CAS_OUT_DBITERR_A +: 0)) = (100:100:100, 100:100:100); (posedge RST_A => (CAS_OUT_RDACCESS_A +: 0)) = (100:100:100, 100:100:100); (posedge RST_A => (CAS_OUT_SBITERR_A +: 0)) = (100:100:100, 100:100:100); (posedge RST_A => (DBITERR_A +: 0)) = (100:100:100, 100:100:100); (posedge RST_A => (RDACCESS_A +: 0)) = (100:100:100, 100:100:100); (posedge RST_A => (SBITERR_A +: 0)) = (100:100:100, 100:100:100); (posedge RST_B *> (CAS_OUT_DOUT_B +: 0)) = (100:100:100, 100:100:100); (posedge RST_B *> (DOUT_B +: 0)) = (100:100:100, 100:100:100); (posedge RST_B => (CAS_OUT_DBITERR_B +: 0)) = (100:100:100, 100:100:100); (posedge RST_B => (CAS_OUT_RDACCESS_B +: 0)) = (100:100:100, 100:100:100); (posedge RST_B => (CAS_OUT_SBITERR_B +: 0)) = (100:100:100, 100:100:100); (posedge RST_B => (DBITERR_B +: 0)) = (100:100:100, 100:100:100); (posedge RST_B => (RDACCESS_B +: 0)) = (100:100:100, 100:100:100); (posedge RST_B => (SBITERR_B +: 0)) = (100:100:100, 100:100:100); `ifdef XIL_TIMING $period (negedge CLK, 0:0:0, notifier); $period (posedge CLK, 0:0:0, notifier); $recrem (negedge RST_A, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_A_delay, CLK_delay); $recrem (negedge RST_A, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_A_delay, CLK_delay); $recrem (negedge RST_B, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_B_delay, CLK_delay); $recrem (negedge RST_B, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_B_delay, CLK_delay); $recrem (posedge RST_A, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_A_delay, CLK_delay); $recrem (posedge RST_A, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_A_delay, CLK_delay); $recrem (posedge RST_B, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_B_delay, CLK_delay); $recrem (posedge RST_B, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_B_delay, CLK_delay); $setuphold (negedge CLK, negedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_A_delay); $setuphold (negedge CLK, negedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_B_delay); $setuphold (negedge CLK, negedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_A_delay); $setuphold (negedge CLK, negedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_B_delay); $setuphold (negedge CLK, negedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_A_delay); $setuphold (negedge CLK, negedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_B_delay); $setuphold (negedge CLK, negedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_A_delay); $setuphold (negedge CLK, negedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_B_delay); $setuphold (negedge CLK, negedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_A_delay); $setuphold (negedge CLK, negedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_B_delay); $setuphold (negedge CLK, negedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_A_delay); $setuphold (negedge CLK, negedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_B_delay); $setuphold (negedge CLK, negedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_A_delay); $setuphold (negedge CLK, negedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_B_delay); $setuphold (negedge CLK, negedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_A_delay); $setuphold (negedge CLK, negedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_B_delay); $setuphold (negedge CLK, negedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_A_delay); $setuphold (negedge CLK, negedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_B_delay); $setuphold (negedge CLK, negedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_A_delay); $setuphold (negedge CLK, negedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_B_delay); $setuphold (negedge CLK, negedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_A_delay); $setuphold (negedge CLK, negedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_B_delay); $setuphold (negedge CLK, negedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_A_delay); $setuphold (negedge CLK, negedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_B_delay); $setuphold (negedge CLK, negedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_A_delay); $setuphold (negedge CLK, negedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_B_delay); $setuphold (negedge CLK, negedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_A_delay); $setuphold (negedge CLK, negedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_B_delay); $setuphold (negedge CLK, negedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_A_delay); $setuphold (negedge CLK, negedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_B_delay); $setuphold (negedge CLK, negedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_A_delay); $setuphold (negedge CLK, negedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_B_delay); $setuphold (negedge CLK, negedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_A_delay); $setuphold (negedge CLK, negedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_B_delay); $setuphold (negedge CLK, negedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_A_delay); $setuphold (negedge CLK, negedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_B_delay); $setuphold (negedge CLK, negedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_A_delay); $setuphold (negedge CLK, negedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_B_delay); $setuphold (negedge CLK, negedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, SLEEP_delay); $setuphold (negedge CLK, posedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_A_delay); $setuphold (negedge CLK, posedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_B_delay); $setuphold (negedge CLK, posedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_A_delay); $setuphold (negedge CLK, posedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_B_delay); $setuphold (negedge CLK, posedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_A_delay); $setuphold (negedge CLK, posedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_B_delay); $setuphold (negedge CLK, posedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_A_delay); $setuphold (negedge CLK, posedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_B_delay); $setuphold (negedge CLK, posedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_A_delay); $setuphold (negedge CLK, posedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_B_delay); $setuphold (negedge CLK, posedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_A_delay); $setuphold (negedge CLK, posedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_B_delay); $setuphold (negedge CLK, posedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_A_delay); $setuphold (negedge CLK, posedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_B_delay); $setuphold (negedge CLK, posedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_A_delay); $setuphold (negedge CLK, posedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_B_delay); $setuphold (negedge CLK, posedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_A_delay); $setuphold (negedge CLK, posedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_B_delay); $setuphold (negedge CLK, posedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_A_delay); $setuphold (negedge CLK, posedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_B_delay); $setuphold (negedge CLK, posedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_A_delay); $setuphold (negedge CLK, posedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_B_delay); $setuphold (negedge CLK, posedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_A_delay); $setuphold (negedge CLK, posedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_B_delay); $setuphold (negedge CLK, posedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_A_delay); $setuphold (negedge CLK, posedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_B_delay); $setuphold (negedge CLK, posedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_A_delay); $setuphold (negedge CLK, posedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_B_delay); $setuphold (negedge CLK, posedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_A_delay); $setuphold (negedge CLK, posedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_B_delay); $setuphold (negedge CLK, posedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_A_delay); $setuphold (negedge CLK, posedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_B_delay); $setuphold (negedge CLK, posedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_A_delay); $setuphold (negedge CLK, posedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_B_delay); $setuphold (negedge CLK, posedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_A_delay); $setuphold (negedge CLK, posedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_B_delay); $setuphold (negedge CLK, posedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_A_delay); $setuphold (negedge CLK, posedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_B_delay); $setuphold (negedge CLK, posedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, SLEEP_delay); $setuphold (posedge CLK, negedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_A_delay); $setuphold (posedge CLK, negedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_B_delay); $setuphold (posedge CLK, negedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_A_delay); $setuphold (posedge CLK, negedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_B_delay); $setuphold (posedge CLK, negedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_A_delay); $setuphold (posedge CLK, negedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_B_delay); $setuphold (posedge CLK, negedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_A_delay); $setuphold (posedge CLK, negedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_B_delay); $setuphold (posedge CLK, negedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_A_delay); $setuphold (posedge CLK, negedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_B_delay); $setuphold (posedge CLK, negedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_A_delay); $setuphold (posedge CLK, negedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_B_delay); $setuphold (posedge CLK, negedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_A_delay); $setuphold (posedge CLK, negedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_B_delay); $setuphold (posedge CLK, negedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_A_delay); $setuphold (posedge CLK, negedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_B_delay); $setuphold (posedge CLK, negedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_A_delay); $setuphold (posedge CLK, negedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_B_delay); $setuphold (posedge CLK, negedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_A_delay); $setuphold (posedge CLK, negedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_B_delay); $setuphold (posedge CLK, negedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_A_delay); $setuphold (posedge CLK, negedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_B_delay); $setuphold (posedge CLK, negedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_A_delay); $setuphold (posedge CLK, negedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_B_delay); $setuphold (posedge CLK, negedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_A_delay); $setuphold (posedge CLK, negedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_B_delay); $setuphold (posedge CLK, negedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_A_delay); $setuphold (posedge CLK, negedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_B_delay); $setuphold (posedge CLK, negedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_A_delay); $setuphold (posedge CLK, negedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_B_delay); $setuphold (posedge CLK, negedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_A_delay); $setuphold (posedge CLK, negedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_B_delay); $setuphold (posedge CLK, negedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_A_delay); $setuphold (posedge CLK, negedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_B_delay); $setuphold (posedge CLK, negedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_A_delay); $setuphold (posedge CLK, negedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_B_delay); $setuphold (posedge CLK, negedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_A_delay); $setuphold (posedge CLK, negedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_B_delay); $setuphold (posedge CLK, negedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, SLEEP_delay); $setuphold (posedge CLK, posedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_A_delay); $setuphold (posedge CLK, posedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_B_delay); $setuphold (posedge CLK, posedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_A_delay); $setuphold (posedge CLK, posedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_B_delay); $setuphold (posedge CLK, posedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_A_delay); $setuphold (posedge CLK, posedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_B_delay); $setuphold (posedge CLK, posedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_A_delay); $setuphold (posedge CLK, posedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_B_delay); $setuphold (posedge CLK, posedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_A_delay); $setuphold (posedge CLK, posedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_B_delay); $setuphold (posedge CLK, posedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_A_delay); $setuphold (posedge CLK, posedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_B_delay); $setuphold (posedge CLK, posedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_A_delay); $setuphold (posedge CLK, posedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_B_delay); $setuphold (posedge CLK, posedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_A_delay); $setuphold (posedge CLK, posedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_B_delay); $setuphold (posedge CLK, posedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_A_delay); $setuphold (posedge CLK, posedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_B_delay); $setuphold (posedge CLK, posedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_A_delay); $setuphold (posedge CLK, posedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_B_delay); $setuphold (posedge CLK, posedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_A_delay); $setuphold (posedge CLK, posedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_B_delay); $setuphold (posedge CLK, posedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_A_delay); $setuphold (posedge CLK, posedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_B_delay); $setuphold (posedge CLK, posedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_A_delay); $setuphold (posedge CLK, posedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_B_delay); $setuphold (posedge CLK, posedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_A_delay); $setuphold (posedge CLK, posedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_B_delay); $setuphold (posedge CLK, posedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_A_delay); $setuphold (posedge CLK, posedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_B_delay); $setuphold (posedge CLK, posedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_A_delay); $setuphold (posedge CLK, posedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_B_delay); $setuphold (posedge CLK, posedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_A_delay); $setuphold (posedge CLK, posedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_B_delay); $setuphold (posedge CLK, posedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_A_delay); $setuphold (posedge CLK, posedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_B_delay); $setuphold (posedge CLK, posedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_A_delay); $setuphold (posedge CLK, posedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_B_delay); $setuphold (posedge CLK, posedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, SLEEP_delay); $width (negedge CLK, 0:0:0, 0, notifier); $width (negedge RST_A, 0:0:0, 0, notifier); $width (negedge RST_B, 0:0:0, 0, notifier); $width (posedge CLK, 0:0:0, 0, notifier); $width (posedge RST_A, 0:0:0, 0, notifier); $width (posedge RST_B, 0:0:0, 0, notifier); `endif specparam PATHPULSE$ = 0; endspecify `endif endmodule `endcelldefine

// ========== Copyright Header Begin ========================================== // // OpenSPARC T1 Processor File: pcx_buf_pm_even.v // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. // // The above named program is free software; you can redistribute it and/or // modify it under the terms of the GNU General Public // License version 2 as published by the Free Software Foundation. // // The above named program is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU // General Public License for more details. // // You should have received a copy of the GNU General Public // License along with this work; if not, write to the Free Software // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. // // ========== Copyright Header End ============================================ //////////////////////////////////////////////////////////////////////// /* // Description: datapath portion of CPX */ //////////////////////////////////////////////////////////////////////// // Global header file includes //////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////// // Local header file includes / local defines //////////////////////////////////////////////////////////////////////// `include "sys.h" `include "iop.h" module pcx_buf_pm_even(/*AUTOARG*/ // Outputs arbpc0_pcxdp_grant_pa, arbpc0_pcxdp_q0_hold_pa_l, arbpc0_pcxdp_qsel0_pa, arbpc0_pcxdp_qsel1_pa_l, arbpc0_pcxdp_shift_px, arbpc2_pcxdp_grant_pa, arbpc2_pcxdp_q0_hold_pa_l, arbpc2_pcxdp_qsel0_pa, arbpc2_pcxdp_qsel1_pa_l, arbpc2_pcxdp_shift_px, // Inputs arbpc0_pcxdp_grant_arbbf_pa, arbpc0_pcxdp_q0_hold_arbbf_pa_l, arbpc0_pcxdp_qsel0_arbbf_pa, arbpc0_pcxdp_qsel1_arbbf_pa_l, arbpc0_pcxdp_shift_arbbf_px, arbpc2_pcxdp_grant_arbbf_pa, arbpc2_pcxdp_q0_hold_arbbf_pa_l, arbpc2_pcxdp_qsel0_arbbf_pa, arbpc2_pcxdp_qsel1_arbbf_pa_l, arbpc2_pcxdp_shift_arbbf_px ); output arbpc0_pcxdp_grant_pa ; output arbpc0_pcxdp_q0_hold_pa_l ; output arbpc0_pcxdp_qsel0_pa ; output arbpc0_pcxdp_qsel1_pa_l ; output arbpc0_pcxdp_shift_px ; output arbpc2_pcxdp_grant_pa ; output arbpc2_pcxdp_q0_hold_pa_l ; output arbpc2_pcxdp_qsel0_pa ; output arbpc2_pcxdp_qsel1_pa_l ; output arbpc2_pcxdp_shift_px ; input arbpc0_pcxdp_grant_arbbf_pa; input arbpc0_pcxdp_q0_hold_arbbf_pa_l; input arbpc0_pcxdp_qsel0_arbbf_pa; input arbpc0_pcxdp_qsel1_arbbf_pa_l; input arbpc0_pcxdp_shift_arbbf_px; input arbpc2_pcxdp_grant_arbbf_pa; input arbpc2_pcxdp_q0_hold_arbbf_pa_l; input arbpc2_pcxdp_qsel0_arbbf_pa; input arbpc2_pcxdp_qsel1_arbbf_pa_l; input arbpc2_pcxdp_shift_arbbf_px; assign arbpc0_pcxdp_grant_pa = arbpc0_pcxdp_grant_arbbf_pa; assign arbpc0_pcxdp_q0_hold_pa_l = arbpc0_pcxdp_q0_hold_arbbf_pa_l; assign arbpc0_pcxdp_qsel0_pa = arbpc0_pcxdp_qsel0_arbbf_pa; assign arbpc0_pcxdp_qsel1_pa_l = arbpc0_pcxdp_qsel1_arbbf_pa_l; assign arbpc0_pcxdp_shift_px = arbpc0_pcxdp_shift_arbbf_px; assign arbpc2_pcxdp_grant_pa = arbpc2_pcxdp_grant_arbbf_pa; assign arbpc2_pcxdp_q0_hold_pa_l = arbpc2_pcxdp_q0_hold_arbbf_pa_l; assign arbpc2_pcxdp_qsel0_pa = arbpc2_pcxdp_qsel0_arbbf_pa; assign arbpc2_pcxdp_qsel1_pa_l = arbpc2_pcxdp_qsel1_arbbf_pa_l; assign arbpc2_pcxdp_shift_px = arbpc2_pcxdp_shift_arbbf_px; endmodule

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HD__A222OI_BLACKBOX_V `define SKY130_FD_SC_HD__A222OI_BLACKBOX_V /** * a222oi: 2-input AND into all inputs of 3-input NOR. * * Y = !((A1 & A2) | (B1 & B2) | (C1 & C2)) * * Verilog stub definition (black box without power pins). * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hd__a222oi ( Y , A1, A2, B1, B2, C1, C2 ); output Y ; input A1; input A2; input B1; input B2; input C1; input C2; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; endmodule `default_nettype wire `endif // SKY130_FD_SC_HD__A222OI_BLACKBOX_V

// diseño de una fifo ciclica, para implementar en cada bloque de proyecto // ferney alberto beltran 2016 electrónica digital 1 universidad Nacional module fifo #( parameter adr_width = 4, parameter dat_width = 8 ) ( input clk, reset, input rd, wr, input [dat_width-1:0] data_in, output [dat_width-1:0] data_out, output empty, output full ); parameter depth = (1 << adr_width); //declaración de registros reg [dat_width-1:0] array_reg [depth-1:0];// register array FIFO reg [adr_width-1:0] w_ptr_reg, w_ptr_next; reg [adr_width-1:0] r_ptr_reg, r_ptr_next; reg full_reg, empty_reg, full_next, empty_next; wire wr_en; assign data_out = array_reg[r_ptr_reg]; assign wr_en = wr & ~full_reg; assign full = full_reg; assign empty = empty_reg; always @(posedge clk) begin if (wr_en) array_reg[w_ptr_reg] <= data_in; end // fifo control logic // register for read and write pointers always @(posedge clk, posedge reset) begin if (reset) begin w_ptr_reg <= 0; r_ptr_reg <= 0; full_reg <= 1'b0; empty_reg <= 1'b1; end else begin w_ptr_reg <= w_ptr_next; r_ptr_reg <= r_ptr_next; full_reg <= full_next; empty_reg <= empty_next; end end always @(posedge reset, posedge wr, posedge rd) begin if (reset) begin w_ptr_next = 0; r_ptr_next = 0; end else begin full_next = full_reg; empty_next = empty_reg; case ({wr, rd}) 2'b01: // read if (~empty_reg) // not empty begin r_ptr_next = r_ptr_reg + 1; full_next = 1'b0; if (r_ptr_next==w_ptr_reg) empty_next = 1'b1; end 2'b10: // write if (~full_reg) // not full begin w_ptr_next = w_ptr_reg + 1; empty_next = 1'b0; if (w_ptr_next==r_ptr_reg) full_next = 1'b1; end 2'b11: // write and read begin w_ptr_next = w_ptr_reg + 1; r_ptr_next = r_ptr_reg + 1; end endcase end end endmodule

//Test Bench for Register File `define N 16 `define K 4 module regfile_tb; reg clk; wire [`N-1:0] a,b; reg [`N-1:0] x; reg [`K-1:0] sa, sb, d; reg ld; regfile #(.n(`N), .k(`K)) r1 (clk, x, ld, d, sa, sb, a, b); initial begin clk = 0; end initial begin $monitor("time:%t\tld: %b\tsa: %d\tsb: %d\td %d\tx: %d\ta: %d\tb: %d", $time, ld, sa, sb, d, x, a, b); end initial begin // Load 10 into register 2 #0 begin $display("\nStarting test 1"); ld = 1; x = 16'd10; d = 3; sa = 3; sb = 3; end // Retrieve 10 from register 2 #2 begin $display("Reading register"); ld = 0; x = 0; d = 3; sa = 3;//4'b0010; sb = 3;//4'b0010; end #2 begin $display("Writing + Reading"); ld = 1; x = 16'd15; d = 1; sa = 3; sb = 3; end #2 begin $display("Reading both registers"); ld = 0; x = 0; d = 0; sa = 1; sb = 3; end #2 begin $display("Read again"); ld = 0; x = 0; d = 0; sa = 1; sb = 3; end #4 $finish; end //Simulate Clock always begin #1 clk = !clk; end endmodule

// // Generated by Bluespec Compiler (build 0fccbb13) // // // Ports: // Name I/O size props // RDY_reset O 1 // RDY_set_verbosity O 1 const // v_from_masters_0_awready O 1 reg // v_from_masters_0_wready O 1 reg // v_from_masters_0_bvalid O 1 reg // v_from_masters_0_bid O 4 reg // v_from_masters_0_bresp O 2 reg // v_from_masters_0_arready O 1 reg // v_from_masters_0_rvalid O 1 reg // v_from_masters_0_rid O 4 reg // v_from_masters_0_rdata O 64 reg // v_from_masters_0_rresp O 2 reg // v_from_masters_0_rlast O 1 reg // v_from_masters_1_awready O 1 reg // v_from_masters_1_wready O 1 reg // v_from_masters_1_bvalid O 1 reg // v_from_masters_1_bid O 4 reg // v_from_masters_1_bresp O 2 reg // v_from_masters_1_arready O 1 reg // v_from_masters_1_rvalid O 1 reg // v_from_masters_1_rid O 4 reg // v_from_masters_1_rdata O 64 reg // v_from_masters_1_rresp O 2 reg // v_from_masters_1_rlast O 1 reg // v_to_slaves_0_awvalid O 1 reg // v_to_slaves_0_awid O 4 reg // v_to_slaves_0_awaddr O 64 reg // v_to_slaves_0_awlen O 8 reg // v_to_slaves_0_awsize O 3 reg // v_to_slaves_0_awburst O 2 reg // v_to_slaves_0_awlock O 1 reg // v_to_slaves_0_awcache O 4 reg // v_to_slaves_0_awprot O 3 reg // v_to_slaves_0_awqos O 4 reg // v_to_slaves_0_awregion O 4 reg // v_to_slaves_0_wvalid O 1 reg // v_to_slaves_0_wdata O 64 reg // v_to_slaves_0_wstrb O 8 reg // v_to_slaves_0_wlast O 1 reg // v_to_slaves_0_bready O 1 reg // v_to_slaves_0_arvalid O 1 reg // v_to_slaves_0_arid O 4 reg // v_to_slaves_0_araddr O 64 reg // v_to_slaves_0_arlen O 8 reg // v_to_slaves_0_arsize O 3 reg // v_to_slaves_0_arburst O 2 reg // v_to_slaves_0_arlock O 1 reg // v_to_slaves_0_arcache O 4 reg // v_to_slaves_0_arprot O 3 reg // v_to_slaves_0_arqos O 4 reg // v_to_slaves_0_arregion O 4 reg // v_to_slaves_0_rready O 1 reg // v_to_slaves_1_awvalid O 1 reg // v_to_slaves_1_awid O 4 reg // v_to_slaves_1_awaddr O 64 reg // v_to_slaves_1_awlen O 8 reg // v_to_slaves_1_awsize O 3 reg // v_to_slaves_1_awburst O 2 reg // v_to_slaves_1_awlock O 1 reg // v_to_slaves_1_awcache O 4 reg // v_to_slaves_1_awprot O 3 reg // v_to_slaves_1_awqos O 4 reg // v_to_slaves_1_awregion O 4 reg // v_to_slaves_1_wvalid O 1 reg // v_to_slaves_1_wdata O 64 reg // v_to_slaves_1_wstrb O 8 reg // v_to_slaves_1_wlast O 1 reg // v_to_slaves_1_bready O 1 reg // v_to_slaves_1_arvalid O 1 reg // v_to_slaves_1_arid O 4 reg // v_to_slaves_1_araddr O 64 reg // v_to_slaves_1_arlen O 8 reg // v_to_slaves_1_arsize O 3 reg // v_to_slaves_1_arburst O 2 reg // v_to_slaves_1_arlock O 1 reg // v_to_slaves_1_arcache O 4 reg // v_to_slaves_1_arprot O 3 reg // v_to_slaves_1_arqos O 4 reg // v_to_slaves_1_arregion O 4 reg // v_to_slaves_1_rready O 1 reg // v_to_slaves_2_awvalid O 1 reg // v_to_slaves_2_awid O 4 reg // v_to_slaves_2_awaddr O 64 reg // v_to_slaves_2_awlen O 8 reg // v_to_slaves_2_awsize O 3 reg // v_to_slaves_2_awburst O 2 reg // v_to_slaves_2_awlock O 1 reg // v_to_slaves_2_awcache O 4 reg // v_to_slaves_2_awprot O 3 reg // v_to_slaves_2_awqos O 4 reg // v_to_slaves_2_awregion O 4 reg // v_to_slaves_2_wvalid O 1 reg // v_to_slaves_2_wdata O 64 reg // v_to_slaves_2_wstrb O 8 reg // v_to_slaves_2_wlast O 1 reg // v_to_slaves_2_bready O 1 reg // v_to_slaves_2_arvalid O 1 reg // v_to_slaves_2_arid O 4 reg // v_to_slaves_2_araddr O 64 reg // v_to_slaves_2_arlen O 8 reg // v_to_slaves_2_arsize O 3 reg // v_to_slaves_2_arburst O 2 reg // v_to_slaves_2_arlock O 1 reg // v_to_slaves_2_arcache O 4 reg // v_to_slaves_2_arprot O 3 reg // v_to_slaves_2_arqos O 4 reg // v_to_slaves_2_arregion O 4 reg // v_to_slaves_2_rready O 1 reg // CLK I 1 clock // RST_N I 1 reset // set_verbosity_verbosity I 4 reg // v_from_masters_0_awvalid I 1 // v_from_masters_0_awid I 4 reg // v_from_masters_0_awaddr I 64 reg // v_from_masters_0_awlen I 8 reg // v_from_masters_0_awsize I 3 reg // v_from_masters_0_awburst I 2 reg // v_from_masters_0_awlock I 1 reg // v_from_masters_0_awcache I 4 reg // v_from_masters_0_awprot I 3 reg // v_from_masters_0_awqos I 4 reg // v_from_masters_0_awregion I 4 reg // v_from_masters_0_wvalid I 1 // v_from_masters_0_wdata I 64 reg // v_from_masters_0_wstrb I 8 reg // v_from_masters_0_wlast I 1 reg // v_from_masters_0_bready I 1 // v_from_masters_0_arvalid I 1 // v_from_masters_0_arid I 4 reg // v_from_masters_0_araddr I 64 reg // v_from_masters_0_arlen I 8 reg // v_from_masters_0_arsize I 3 reg // v_from_masters_0_arburst I 2 reg // v_from_masters_0_arlock I 1 reg // v_from_masters_0_arcache I 4 reg // v_from_masters_0_arprot I 3 reg // v_from_masters_0_arqos I 4 reg // v_from_masters_0_arregion I 4 reg // v_from_masters_0_rready I 1 // v_from_masters_1_awvalid I 1 // v_from_masters_1_awid I 4 reg // v_from_masters_1_awaddr I 64 reg // v_from_masters_1_awlen I 8 reg // v_from_masters_1_awsize I 3 reg // v_from_masters_1_awburst I 2 reg // v_from_masters_1_awlock I 1 reg // v_from_masters_1_awcache I 4 reg // v_from_masters_1_awprot I 3 reg // v_from_masters_1_awqos I 4 reg // v_from_masters_1_awregion I 4 reg // v_from_masters_1_wvalid I 1 // v_from_masters_1_wdata I 64 reg // v_from_masters_1_wstrb I 8 reg // v_from_masters_1_wlast I 1 reg // v_from_masters_1_bready I 1 // v_from_masters_1_arvalid I 1 // v_from_masters_1_arid I 4 reg // v_from_masters_1_araddr I 64 reg // v_from_masters_1_arlen I 8 reg // v_from_masters_1_arsize I 3 reg // v_from_masters_1_arburst I 2 reg // v_from_masters_1_arlock I 1 reg // v_from_masters_1_arcache I 4 reg // v_from_masters_1_arprot I 3 reg // v_from_masters_1_arqos I 4 reg // v_from_masters_1_arregion I 4 reg // v_from_masters_1_rready I 1 // v_to_slaves_0_awready I 1 // v_to_slaves_0_wready I 1 // v_to_slaves_0_bvalid I 1 // v_to_slaves_0_bid I 4 reg // v_to_slaves_0_bresp I 2 reg // v_to_slaves_0_arready I 1 // v_to_slaves_0_rvalid I 1 // v_to_slaves_0_rid I 4 reg // v_to_slaves_0_rdata I 64 reg // v_to_slaves_0_rresp I 2 reg // v_to_slaves_0_rlast I 1 reg // v_to_slaves_1_awready I 1 // v_to_slaves_1_wready I 1 // v_to_slaves_1_bvalid I 1 // v_to_slaves_1_bid I 4 reg // v_to_slaves_1_bresp I 2 reg // v_to_slaves_1_arready I 1 // v_to_slaves_1_rvalid I 1 // v_to_slaves_1_rid I 4 reg // v_to_slaves_1_rdata I 64 reg // v_to_slaves_1_rresp I 2 reg // v_to_slaves_1_rlast I 1 reg // v_to_slaves_2_awready I 1 // v_to_slaves_2_wready I 1 // v_to_slaves_2_bvalid I 1 // v_to_slaves_2_bid I 4 reg // v_to_slaves_2_bresp I 2 reg // v_to_slaves_2_arready I 1 // v_to_slaves_2_rvalid I 1 // v_to_slaves_2_rid I 4 reg // v_to_slaves_2_rdata I 64 reg // v_to_slaves_2_rresp I 2 reg // v_to_slaves_2_rlast I 1 reg // EN_reset I 1 // EN_set_verbosity I 1 // // No combinational paths from inputs to outputs // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module mkFabric_2x3(CLK, RST_N, EN_reset, RDY_reset, set_verbosity_verbosity, EN_set_verbosity, RDY_set_verbosity, v_from_masters_0_awvalid, v_from_masters_0_awid, v_from_masters_0_awaddr, v_from_masters_0_awlen, v_from_masters_0_awsize, v_from_masters_0_awburst, v_from_masters_0_awlock, v_from_masters_0_awcache, v_from_masters_0_awprot, v_from_masters_0_awqos, v_from_masters_0_awregion, v_from_masters_0_awready, v_from_masters_0_wvalid, v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast, v_from_masters_0_wready, v_from_masters_0_bvalid, v_from_masters_0_bid, v_from_masters_0_bresp, v_from_masters_0_bready, v_from_masters_0_arvalid, v_from_masters_0_arid, v_from_masters_0_araddr, v_from_masters_0_arlen, v_from_masters_0_arsize, v_from_masters_0_arburst, v_from_masters_0_arlock, v_from_masters_0_arcache, v_from_masters_0_arprot, v_from_masters_0_arqos, v_from_masters_0_arregion, v_from_masters_0_arready, v_from_masters_0_rvalid, v_from_masters_0_rid, v_from_masters_0_rdata, v_from_masters_0_rresp, v_from_masters_0_rlast, v_from_masters_0_rready, v_from_masters_1_awvalid, v_from_masters_1_awid, v_from_masters_1_awaddr, v_from_masters_1_awlen, v_from_masters_1_awsize, v_from_masters_1_awburst, v_from_masters_1_awlock, v_from_masters_1_awcache, v_from_masters_1_awprot, v_from_masters_1_awqos, v_from_masters_1_awregion, v_from_masters_1_awready, v_from_masters_1_wvalid, v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast, v_from_masters_1_wready, v_from_masters_1_bvalid, v_from_masters_1_bid, v_from_masters_1_bresp, v_from_masters_1_bready, v_from_masters_1_arvalid, v_from_masters_1_arid, v_from_masters_1_araddr, v_from_masters_1_arlen, v_from_masters_1_arsize, v_from_masters_1_arburst, v_from_masters_1_arlock, v_from_masters_1_arcache, v_from_masters_1_arprot, v_from_masters_1_arqos, v_from_masters_1_arregion, v_from_masters_1_arready, v_from_masters_1_rvalid, v_from_masters_1_rid, v_from_masters_1_rdata, v_from_masters_1_rresp, v_from_masters_1_rlast, v_from_masters_1_rready, v_to_slaves_0_awvalid, v_to_slaves_0_awid, v_to_slaves_0_awaddr, v_to_slaves_0_awlen, v_to_slaves_0_awsize, v_to_slaves_0_awburst, v_to_slaves_0_awlock, v_to_slaves_0_awcache, v_to_slaves_0_awprot, v_to_slaves_0_awqos, v_to_slaves_0_awregion, v_to_slaves_0_awready, v_to_slaves_0_wvalid, v_to_slaves_0_wdata, v_to_slaves_0_wstrb, v_to_slaves_0_wlast, v_to_slaves_0_wready, v_to_slaves_0_bvalid, v_to_slaves_0_bid, v_to_slaves_0_bresp, v_to_slaves_0_bready, v_to_slaves_0_arvalid, v_to_slaves_0_arid, v_to_slaves_0_araddr, v_to_slaves_0_arlen, v_to_slaves_0_arsize, v_to_slaves_0_arburst, v_to_slaves_0_arlock, v_to_slaves_0_arcache, v_to_slaves_0_arprot, v_to_slaves_0_arqos, v_to_slaves_0_arregion, v_to_slaves_0_arready, v_to_slaves_0_rvalid, v_to_slaves_0_rid, v_to_slaves_0_rdata, v_to_slaves_0_rresp, v_to_slaves_0_rlast, v_to_slaves_0_rready, v_to_slaves_1_awvalid, v_to_slaves_1_awid, v_to_slaves_1_awaddr, v_to_slaves_1_awlen, v_to_slaves_1_awsize, v_to_slaves_1_awburst, v_to_slaves_1_awlock, v_to_slaves_1_awcache, v_to_slaves_1_awprot, v_to_slaves_1_awqos, v_to_slaves_1_awregion, v_to_slaves_1_awready, v_to_slaves_1_wvalid, v_to_slaves_1_wdata, v_to_slaves_1_wstrb, v_to_slaves_1_wlast, v_to_slaves_1_wready, v_to_slaves_1_bvalid, v_to_slaves_1_bid, v_to_slaves_1_bresp, v_to_slaves_1_bready, v_to_slaves_1_arvalid, v_to_slaves_1_arid, v_to_slaves_1_araddr, v_to_slaves_1_arlen, v_to_slaves_1_arsize, v_to_slaves_1_arburst, v_to_slaves_1_arlock, v_to_slaves_1_arcache, v_to_slaves_1_arprot, v_to_slaves_1_arqos, v_to_slaves_1_arregion, v_to_slaves_1_arready, v_to_slaves_1_rvalid, v_to_slaves_1_rid, v_to_slaves_1_rdata, v_to_slaves_1_rresp, v_to_slaves_1_rlast, v_to_slaves_1_rready, v_to_slaves_2_awvalid, v_to_slaves_2_awid, v_to_slaves_2_awaddr, v_to_slaves_2_awlen, v_to_slaves_2_awsize, v_to_slaves_2_awburst, v_to_slaves_2_awlock, v_to_slaves_2_awcache, v_to_slaves_2_awprot, v_to_slaves_2_awqos, v_to_slaves_2_awregion, v_to_slaves_2_awready, v_to_slaves_2_wvalid, v_to_slaves_2_wdata, v_to_slaves_2_wstrb, v_to_slaves_2_wlast, v_to_slaves_2_wready, v_to_slaves_2_bvalid, v_to_slaves_2_bid, v_to_slaves_2_bresp, v_to_slaves_2_bready, v_to_slaves_2_arvalid, v_to_slaves_2_arid, v_to_slaves_2_araddr, v_to_slaves_2_arlen, v_to_slaves_2_arsize, v_to_slaves_2_arburst, v_to_slaves_2_arlock, v_to_slaves_2_arcache, v_to_slaves_2_arprot, v_to_slaves_2_arqos, v_to_slaves_2_arregion, v_to_slaves_2_arready, v_to_slaves_2_rvalid, v_to_slaves_2_rid, v_to_slaves_2_rdata, v_to_slaves_2_rresp, v_to_slaves_2_rlast, v_to_slaves_2_rready); input CLK; input RST_N; // action method reset input EN_reset; output RDY_reset; // action method set_verbosity input [3 : 0] set_verbosity_verbosity; input EN_set_verbosity; output RDY_set_verbosity; // action method v_from_masters_0_m_awvalid input v_from_masters_0_awvalid; input [3 : 0] v_from_masters_0_awid; input [63 : 0] v_from_masters_0_awaddr; input [7 : 0] v_from_masters_0_awlen; input [2 : 0] v_from_masters_0_awsize; input [1 : 0] v_from_masters_0_awburst; input v_from_masters_0_awlock; input [3 : 0] v_from_masters_0_awcache; input [2 : 0] v_from_masters_0_awprot; input [3 : 0] v_from_masters_0_awqos; input [3 : 0] v_from_masters_0_awregion; // value method v_from_masters_0_m_awready output v_from_masters_0_awready; // action method v_from_masters_0_m_wvalid input v_from_masters_0_wvalid; input [63 : 0] v_from_masters_0_wdata; input [7 : 0] v_from_masters_0_wstrb; input v_from_masters_0_wlast; // value method v_from_masters_0_m_wready output v_from_masters_0_wready; // value method v_from_masters_0_m_bvalid output v_from_masters_0_bvalid; // value method v_from_masters_0_m_bid output [3 : 0] v_from_masters_0_bid; // value method v_from_masters_0_m_bresp output [1 : 0] v_from_masters_0_bresp; // value method v_from_masters_0_m_buser // action method v_from_masters_0_m_bready input v_from_masters_0_bready; // action method v_from_masters_0_m_arvalid input v_from_masters_0_arvalid; input [3 : 0] v_from_masters_0_arid; input [63 : 0] v_from_masters_0_araddr; input [7 : 0] v_from_masters_0_arlen; input [2 : 0] v_from_masters_0_arsize; input [1 : 0] v_from_masters_0_arburst; input v_from_masters_0_arlock; input [3 : 0] v_from_masters_0_arcache; input [2 : 0] v_from_masters_0_arprot; input [3 : 0] v_from_masters_0_arqos; input [3 : 0] v_from_masters_0_arregion; // value method v_from_masters_0_m_arready output v_from_masters_0_arready; // value method v_from_masters_0_m_rvalid output v_from_masters_0_rvalid; // value method v_from_masters_0_m_rid output [3 : 0] v_from_masters_0_rid; // value method v_from_masters_0_m_rdata output [63 : 0] v_from_masters_0_rdata; // value method v_from_masters_0_m_rresp output [1 : 0] v_from_masters_0_rresp; // value method v_from_masters_0_m_rlast output v_from_masters_0_rlast; // value method v_from_masters_0_m_ruser // action method v_from_masters_0_m_rready input v_from_masters_0_rready; // action method v_from_masters_1_m_awvalid input v_from_masters_1_awvalid; input [3 : 0] v_from_masters_1_awid; input [63 : 0] v_from_masters_1_awaddr; input [7 : 0] v_from_masters_1_awlen; input [2 : 0] v_from_masters_1_awsize; input [1 : 0] v_from_masters_1_awburst; input v_from_masters_1_awlock; input [3 : 0] v_from_masters_1_awcache; input [2 : 0] v_from_masters_1_awprot; input [3 : 0] v_from_masters_1_awqos; input [3 : 0] v_from_masters_1_awregion; // value method v_from_masters_1_m_awready output v_from_masters_1_awready; // action method v_from_masters_1_m_wvalid input v_from_masters_1_wvalid; input [63 : 0] v_from_masters_1_wdata; input [7 : 0] v_from_masters_1_wstrb; input v_from_masters_1_wlast; // value method v_from_masters_1_m_wready output v_from_masters_1_wready; // value method v_from_masters_1_m_bvalid output v_from_masters_1_bvalid; // value method v_from_masters_1_m_bid output [3 : 0] v_from_masters_1_bid; // value method v_from_masters_1_m_bresp output [1 : 0] v_from_masters_1_bresp; // value method v_from_masters_1_m_buser // action method v_from_masters_1_m_bready input v_from_masters_1_bready; // action method v_from_masters_1_m_arvalid input v_from_masters_1_arvalid; input [3 : 0] v_from_masters_1_arid; input [63 : 0] v_from_masters_1_araddr; input [7 : 0] v_from_masters_1_arlen; input [2 : 0] v_from_masters_1_arsize; input [1 : 0] v_from_masters_1_arburst; input v_from_masters_1_arlock; input [3 : 0] v_from_masters_1_arcache; input [2 : 0] v_from_masters_1_arprot; input [3 : 0] v_from_masters_1_arqos; input [3 : 0] v_from_masters_1_arregion; // value method v_from_masters_1_m_arready output v_from_masters_1_arready; // value method v_from_masters_1_m_rvalid output v_from_masters_1_rvalid; // value method v_from_masters_1_m_rid output [3 : 0] v_from_masters_1_rid; // value method v_from_masters_1_m_rdata output [63 : 0] v_from_masters_1_rdata; // value method v_from_masters_1_m_rresp output [1 : 0] v_from_masters_1_rresp; // value method v_from_masters_1_m_rlast output v_from_masters_1_rlast; // value method v_from_masters_1_m_ruser // action method v_from_masters_1_m_rready input v_from_masters_1_rready; // value method v_to_slaves_0_m_awvalid output v_to_slaves_0_awvalid; // value method v_to_slaves_0_m_awid output [3 : 0] v_to_slaves_0_awid; // value method v_to_slaves_0_m_awaddr output [63 : 0] v_to_slaves_0_awaddr; // value method v_to_slaves_0_m_awlen output [7 : 0] v_to_slaves_0_awlen; // value method v_to_slaves_0_m_awsize output [2 : 0] v_to_slaves_0_awsize; // value method v_to_slaves_0_m_awburst output [1 : 0] v_to_slaves_0_awburst; // value method v_to_slaves_0_m_awlock output v_to_slaves_0_awlock; // value method v_to_slaves_0_m_awcache output [3 : 0] v_to_slaves_0_awcache; // value method v_to_slaves_0_m_awprot output [2 : 0] v_to_slaves_0_awprot; // value method v_to_slaves_0_m_awqos output [3 : 0] v_to_slaves_0_awqos; // value method v_to_slaves_0_m_awregion output [3 : 0] v_to_slaves_0_awregion; // value method v_to_slaves_0_m_awuser // action method v_to_slaves_0_m_awready input v_to_slaves_0_awready; // value method v_to_slaves_0_m_wvalid output v_to_slaves_0_wvalid; // value method v_to_slaves_0_m_wdata output [63 : 0] v_to_slaves_0_wdata; // value method v_to_slaves_0_m_wstrb output [7 : 0] v_to_slaves_0_wstrb; // value method v_to_slaves_0_m_wlast output v_to_slaves_0_wlast; // value method v_to_slaves_0_m_wuser // action method v_to_slaves_0_m_wready input v_to_slaves_0_wready; // action method v_to_slaves_0_m_bvalid input v_to_slaves_0_bvalid; input [3 : 0] v_to_slaves_0_bid; input [1 : 0] v_to_slaves_0_bresp; // value method v_to_slaves_0_m_bready output v_to_slaves_0_bready; // value method v_to_slaves_0_m_arvalid output v_to_slaves_0_arvalid; // value method v_to_slaves_0_m_arid output [3 : 0] v_to_slaves_0_arid; // value method v_to_slaves_0_m_araddr output [63 : 0] v_to_slaves_0_araddr; // value method v_to_slaves_0_m_arlen output [7 : 0] v_to_slaves_0_arlen; // value method v_to_slaves_0_m_arsize output [2 : 0] v_to_slaves_0_arsize; // value method v_to_slaves_0_m_arburst output [1 : 0] v_to_slaves_0_arburst; // value method v_to_slaves_0_m_arlock output v_to_slaves_0_arlock; // value method v_to_slaves_0_m_arcache output [3 : 0] v_to_slaves_0_arcache; // value method v_to_slaves_0_m_arprot output [2 : 0] v_to_slaves_0_arprot; // value method v_to_slaves_0_m_arqos output [3 : 0] v_to_slaves_0_arqos; // value method v_to_slaves_0_m_arregion output [3 : 0] v_to_slaves_0_arregion; // value method v_to_slaves_0_m_aruser // action method v_to_slaves_0_m_arready input v_to_slaves_0_arready; // action method v_to_slaves_0_m_rvalid input v_to_slaves_0_rvalid; input [3 : 0] v_to_slaves_0_rid; input [63 : 0] v_to_slaves_0_rdata; input [1 : 0] v_to_slaves_0_rresp; input v_to_slaves_0_rlast; // value method v_to_slaves_0_m_rready output v_to_slaves_0_rready; // value method v_to_slaves_1_m_awvalid output v_to_slaves_1_awvalid; // value method v_to_slaves_1_m_awid output [3 : 0] v_to_slaves_1_awid; // value method v_to_slaves_1_m_awaddr output [63 : 0] v_to_slaves_1_awaddr; // value method v_to_slaves_1_m_awlen output [7 : 0] v_to_slaves_1_awlen; // value method v_to_slaves_1_m_awsize output [2 : 0] v_to_slaves_1_awsize; // value method v_to_slaves_1_m_awburst output [1 : 0] v_to_slaves_1_awburst; // value method v_to_slaves_1_m_awlock output v_to_slaves_1_awlock; // value method v_to_slaves_1_m_awcache output [3 : 0] v_to_slaves_1_awcache; // value method v_to_slaves_1_m_awprot output [2 : 0] v_to_slaves_1_awprot; // value method v_to_slaves_1_m_awqos output [3 : 0] v_to_slaves_1_awqos; // value method v_to_slaves_1_m_awregion output [3 : 0] v_to_slaves_1_awregion; // value method v_to_slaves_1_m_awuser // action method v_to_slaves_1_m_awready input v_to_slaves_1_awready; // value method v_to_slaves_1_m_wvalid output v_to_slaves_1_wvalid; // value method v_to_slaves_1_m_wdata output [63 : 0] v_to_slaves_1_wdata; // value method v_to_slaves_1_m_wstrb output [7 : 0] v_to_slaves_1_wstrb; // value method v_to_slaves_1_m_wlast output v_to_slaves_1_wlast; // value method v_to_slaves_1_m_wuser // action method v_to_slaves_1_m_wready input v_to_slaves_1_wready; // action method v_to_slaves_1_m_bvalid input v_to_slaves_1_bvalid; input [3 : 0] v_to_slaves_1_bid; input [1 : 0] v_to_slaves_1_bresp; // value method v_to_slaves_1_m_bready output v_to_slaves_1_bready; // value method v_to_slaves_1_m_arvalid output v_to_slaves_1_arvalid; // value method v_to_slaves_1_m_arid output [3 : 0] v_to_slaves_1_arid; // value method v_to_slaves_1_m_araddr output [63 : 0] v_to_slaves_1_araddr; // value method v_to_slaves_1_m_arlen output [7 : 0] v_to_slaves_1_arlen; // value method v_to_slaves_1_m_arsize output [2 : 0] v_to_slaves_1_arsize; // value method v_to_slaves_1_m_arburst output [1 : 0] v_to_slaves_1_arburst; // value method v_to_slaves_1_m_arlock output v_to_slaves_1_arlock; // value method v_to_slaves_1_m_arcache output [3 : 0] v_to_slaves_1_arcache; // value method v_to_slaves_1_m_arprot output [2 : 0] v_to_slaves_1_arprot; // value method v_to_slaves_1_m_arqos output [3 : 0] v_to_slaves_1_arqos; // value method v_to_slaves_1_m_arregion output [3 : 0] v_to_slaves_1_arregion; // value method v_to_slaves_1_m_aruser // action method v_to_slaves_1_m_arready input v_to_slaves_1_arready; // action method v_to_slaves_1_m_rvalid input v_to_slaves_1_rvalid; input [3 : 0] v_to_slaves_1_rid; input [63 : 0] v_to_slaves_1_rdata; input [1 : 0] v_to_slaves_1_rresp; input v_to_slaves_1_rlast; // value method v_to_slaves_1_m_rready output v_to_slaves_1_rready; // value method v_to_slaves_2_m_awvalid output v_to_slaves_2_awvalid; // value method v_to_slaves_2_m_awid output [3 : 0] v_to_slaves_2_awid; // value method v_to_slaves_2_m_awaddr output [63 : 0] v_to_slaves_2_awaddr; // value method v_to_slaves_2_m_awlen output [7 : 0] v_to_slaves_2_awlen; // value method v_to_slaves_2_m_awsize output [2 : 0] v_to_slaves_2_awsize; // value method v_to_slaves_2_m_awburst output [1 : 0] v_to_slaves_2_awburst; // value method v_to_slaves_2_m_awlock output v_to_slaves_2_awlock; // value method v_to_slaves_2_m_awcache output [3 : 0] v_to_slaves_2_awcache; // value method v_to_slaves_2_m_awprot output [2 : 0] v_to_slaves_2_awprot; // value method v_to_slaves_2_m_awqos output [3 : 0] v_to_slaves_2_awqos; // value method v_to_slaves_2_m_awregion output [3 : 0] v_to_slaves_2_awregion; // value method v_to_slaves_2_m_awuser // action method v_to_slaves_2_m_awready input v_to_slaves_2_awready; // value method v_to_slaves_2_m_wvalid output v_to_slaves_2_wvalid; // value method v_to_slaves_2_m_wdata output [63 : 0] v_to_slaves_2_wdata; // value method v_to_slaves_2_m_wstrb output [7 : 0] v_to_slaves_2_wstrb; // value method v_to_slaves_2_m_wlast output v_to_slaves_2_wlast; // value method v_to_slaves_2_m_wuser // action method v_to_slaves_2_m_wready input v_to_slaves_2_wready; // action method v_to_slaves_2_m_bvalid input v_to_slaves_2_bvalid; input [3 : 0] v_to_slaves_2_bid; input [1 : 0] v_to_slaves_2_bresp; // value method v_to_slaves_2_m_bready output v_to_slaves_2_bready; // value method v_to_slaves_2_m_arvalid output v_to_slaves_2_arvalid; // value method v_to_slaves_2_m_arid output [3 : 0] v_to_slaves_2_arid; // value method v_to_slaves_2_m_araddr output [63 : 0] v_to_slaves_2_araddr; // value method v_to_slaves_2_m_arlen output [7 : 0] v_to_slaves_2_arlen; // value method v_to_slaves_2_m_arsize output [2 : 0] v_to_slaves_2_arsize; // value method v_to_slaves_2_m_arburst output [1 : 0] v_to_slaves_2_arburst; // value method v_to_slaves_2_m_arlock output v_to_slaves_2_arlock; // value method v_to_slaves_2_m_arcache output [3 : 0] v_to_slaves_2_arcache; // value method v_to_slaves_2_m_arprot output [2 : 0] v_to_slaves_2_arprot; // value method v_to_slaves_2_m_arqos output [3 : 0] v_to_slaves_2_arqos; // value method v_to_slaves_2_m_arregion output [3 : 0] v_to_slaves_2_arregion; // value method v_to_slaves_2_m_aruser // action method v_to_slaves_2_m_arready input v_to_slaves_2_arready; // action method v_to_slaves_2_m_rvalid input v_to_slaves_2_rvalid; input [3 : 0] v_to_slaves_2_rid; input [63 : 0] v_to_slaves_2_rdata; input [1 : 0] v_to_slaves_2_rresp; input v_to_slaves_2_rlast; // value method v_to_slaves_2_m_rready output v_to_slaves_2_rready; // signals for module outputs wire [63 : 0] v_from_masters_0_rdata, v_from_masters_1_rdata, v_to_slaves_0_araddr, v_to_slaves_0_awaddr, v_to_slaves_0_wdata, v_to_slaves_1_araddr, v_to_slaves_1_awaddr, v_to_slaves_1_wdata, v_to_slaves_2_araddr, v_to_slaves_2_awaddr, v_to_slaves_2_wdata; wire [7 : 0] v_to_slaves_0_arlen, v_to_slaves_0_awlen, v_to_slaves_0_wstrb, v_to_slaves_1_arlen, v_to_slaves_1_awlen, v_to_slaves_1_wstrb, v_to_slaves_2_arlen, v_to_slaves_2_awlen, v_to_slaves_2_wstrb; wire [3 : 0] v_from_masters_0_bid, v_from_masters_0_rid, v_from_masters_1_bid, v_from_masters_1_rid, v_to_slaves_0_arcache, v_to_slaves_0_arid, v_to_slaves_0_arqos, v_to_slaves_0_arregion, v_to_slaves_0_awcache, v_to_slaves_0_awid, v_to_slaves_0_awqos, v_to_slaves_0_awregion, v_to_slaves_1_arcache, v_to_slaves_1_arid, v_to_slaves_1_arqos, v_to_slaves_1_arregion, v_to_slaves_1_awcache, v_to_slaves_1_awid, v_to_slaves_1_awqos, v_to_slaves_1_awregion, v_to_slaves_2_arcache, v_to_slaves_2_arid, v_to_slaves_2_arqos, v_to_slaves_2_arregion, v_to_slaves_2_awcache, v_to_slaves_2_awid, v_to_slaves_2_awqos, v_to_slaves_2_awregion; wire [2 : 0] v_to_slaves_0_arprot, v_to_slaves_0_arsize, v_to_slaves_0_awprot, v_to_slaves_0_awsize, v_to_slaves_1_arprot, v_to_slaves_1_arsize, v_to_slaves_1_awprot, v_to_slaves_1_awsize, v_to_slaves_2_arprot, v_to_slaves_2_arsize, v_to_slaves_2_awprot, v_to_slaves_2_awsize; wire [1 : 0] v_from_masters_0_bresp, v_from_masters_0_rresp, v_from_masters_1_bresp, v_from_masters_1_rresp, v_to_slaves_0_arburst, v_to_slaves_0_awburst, v_to_slaves_1_arburst, v_to_slaves_1_awburst, v_to_slaves_2_arburst, v_to_slaves_2_awburst; wire RDY_reset, RDY_set_verbosity, v_from_masters_0_arready, v_from_masters_0_awready, v_from_masters_0_bvalid, v_from_masters_0_rlast, v_from_masters_0_rvalid, v_from_masters_0_wready, v_from_masters_1_arready, v_from_masters_1_awready, v_from_masters_1_bvalid, v_from_masters_1_rlast, v_from_masters_1_rvalid, v_from_masters_1_wready, v_to_slaves_0_arlock, v_to_slaves_0_arvalid, v_to_slaves_0_awlock, v_to_slaves_0_awvalid, v_to_slaves_0_bready, v_to_slaves_0_rready, v_to_slaves_0_wlast, v_to_slaves_0_wvalid, v_to_slaves_1_arlock, v_to_slaves_1_arvalid, v_to_slaves_1_awlock, v_to_slaves_1_awvalid, v_to_slaves_1_bready, v_to_slaves_1_rready, v_to_slaves_1_wlast, v_to_slaves_1_wvalid, v_to_slaves_2_arlock, v_to_slaves_2_arvalid, v_to_slaves_2_awlock, v_to_slaves_2_awvalid, v_to_slaves_2_bready, v_to_slaves_2_rready, v_to_slaves_2_wlast, v_to_slaves_2_wvalid; // register fabric_cfg_verbosity reg [3 : 0] fabric_cfg_verbosity; wire [3 : 0] fabric_cfg_verbosity$D_IN; wire fabric_cfg_verbosity$EN; // register fabric_rg_reset reg fabric_rg_reset; wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; // register fabric_v_rg_r_beat_count_0 reg [7 : 0] fabric_v_rg_r_beat_count_0; reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; wire fabric_v_rg_r_beat_count_0$EN; // register fabric_v_rg_r_beat_count_1 reg [7 : 0] fabric_v_rg_r_beat_count_1; reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; wire fabric_v_rg_r_beat_count_1$EN; // register fabric_v_rg_r_beat_count_2 reg [7 : 0] fabric_v_rg_r_beat_count_2; reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; wire fabric_v_rg_r_beat_count_2$EN; // register fabric_v_rg_r_err_beat_count_0 reg [7 : 0] fabric_v_rg_r_err_beat_count_0; wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; wire fabric_v_rg_r_err_beat_count_0$EN; // register fabric_v_rg_r_err_beat_count_1 reg [7 : 0] fabric_v_rg_r_err_beat_count_1; wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; wire fabric_v_rg_r_err_beat_count_1$EN; // register fabric_v_rg_wd_beat_count_0 reg [7 : 0] fabric_v_rg_wd_beat_count_0; wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; wire fabric_v_rg_wd_beat_count_0$EN; // register fabric_v_rg_wd_beat_count_1 reg [7 : 0] fabric_v_rg_wd_beat_count_1; wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; wire fabric_v_rg_wd_beat_count_1$EN; // ports of submodule fabric_v_f_rd_err_info_0 wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; wire fabric_v_f_rd_err_info_0$CLR, fabric_v_f_rd_err_info_0$DEQ, fabric_v_f_rd_err_info_0$EMPTY_N, fabric_v_f_rd_err_info_0$ENQ; // ports of submodule fabric_v_f_rd_err_info_1 wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; wire fabric_v_f_rd_err_info_1$CLR, fabric_v_f_rd_err_info_1$DEQ, fabric_v_f_rd_err_info_1$EMPTY_N, fabric_v_f_rd_err_info_1$ENQ; // ports of submodule fabric_v_f_rd_mis_0 wire [9 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; wire fabric_v_f_rd_mis_0$CLR, fabric_v_f_rd_mis_0$DEQ, fabric_v_f_rd_mis_0$EMPTY_N, fabric_v_f_rd_mis_0$ENQ, fabric_v_f_rd_mis_0$FULL_N; // ports of submodule fabric_v_f_rd_mis_1 wire [9 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; wire fabric_v_f_rd_mis_1$CLR, fabric_v_f_rd_mis_1$DEQ, fabric_v_f_rd_mis_1$EMPTY_N, fabric_v_f_rd_mis_1$ENQ, fabric_v_f_rd_mis_1$FULL_N; // ports of submodule fabric_v_f_rd_mis_2 wire [9 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; wire fabric_v_f_rd_mis_2$CLR, fabric_v_f_rd_mis_2$DEQ, fabric_v_f_rd_mis_2$EMPTY_N, fabric_v_f_rd_mis_2$ENQ, fabric_v_f_rd_mis_2$FULL_N; // ports of submodule fabric_v_f_rd_sjs_0 reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; wire fabric_v_f_rd_sjs_0$CLR, fabric_v_f_rd_sjs_0$DEQ, fabric_v_f_rd_sjs_0$EMPTY_N, fabric_v_f_rd_sjs_0$ENQ, fabric_v_f_rd_sjs_0$FULL_N; // ports of submodule fabric_v_f_rd_sjs_1 reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; wire fabric_v_f_rd_sjs_1$CLR, fabric_v_f_rd_sjs_1$DEQ, fabric_v_f_rd_sjs_1$EMPTY_N, fabric_v_f_rd_sjs_1$ENQ, fabric_v_f_rd_sjs_1$FULL_N; // ports of submodule fabric_v_f_wd_tasks_0 reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; wire fabric_v_f_wd_tasks_0$CLR, fabric_v_f_wd_tasks_0$DEQ, fabric_v_f_wd_tasks_0$EMPTY_N, fabric_v_f_wd_tasks_0$ENQ, fabric_v_f_wd_tasks_0$FULL_N; // ports of submodule fabric_v_f_wd_tasks_1 reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; wire fabric_v_f_wd_tasks_1$CLR, fabric_v_f_wd_tasks_1$DEQ, fabric_v_f_wd_tasks_1$EMPTY_N, fabric_v_f_wd_tasks_1$ENQ, fabric_v_f_wd_tasks_1$FULL_N; // ports of submodule fabric_v_f_wr_err_info_0 wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; wire fabric_v_f_wr_err_info_0$CLR, fabric_v_f_wr_err_info_0$DEQ, fabric_v_f_wr_err_info_0$EMPTY_N, fabric_v_f_wr_err_info_0$ENQ; // ports of submodule fabric_v_f_wr_err_info_1 wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; wire fabric_v_f_wr_err_info_1$CLR, fabric_v_f_wr_err_info_1$DEQ, fabric_v_f_wr_err_info_1$EMPTY_N, fabric_v_f_wr_err_info_1$ENQ; // ports of submodule fabric_v_f_wr_mis_0 wire [1 : 0] fabric_v_f_wr_mis_0$D_IN, fabric_v_f_wr_mis_0$D_OUT; wire fabric_v_f_wr_mis_0$CLR, fabric_v_f_wr_mis_0$DEQ, fabric_v_f_wr_mis_0$EMPTY_N, fabric_v_f_wr_mis_0$ENQ, fabric_v_f_wr_mis_0$FULL_N; // ports of submodule fabric_v_f_wr_mis_1 wire [1 : 0] fabric_v_f_wr_mis_1$D_IN, fabric_v_f_wr_mis_1$D_OUT; wire fabric_v_f_wr_mis_1$CLR, fabric_v_f_wr_mis_1$DEQ, fabric_v_f_wr_mis_1$EMPTY_N, fabric_v_f_wr_mis_1$ENQ, fabric_v_f_wr_mis_1$FULL_N; // ports of submodule fabric_v_f_wr_mis_2 wire [1 : 0] fabric_v_f_wr_mis_2$D_IN, fabric_v_f_wr_mis_2$D_OUT; wire fabric_v_f_wr_mis_2$CLR, fabric_v_f_wr_mis_2$DEQ, fabric_v_f_wr_mis_2$EMPTY_N, fabric_v_f_wr_mis_2$ENQ, fabric_v_f_wr_mis_2$FULL_N; // ports of submodule fabric_v_f_wr_sjs_0 reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; wire fabric_v_f_wr_sjs_0$CLR, fabric_v_f_wr_sjs_0$DEQ, fabric_v_f_wr_sjs_0$EMPTY_N, fabric_v_f_wr_sjs_0$ENQ, fabric_v_f_wr_sjs_0$FULL_N; // ports of submodule fabric_v_f_wr_sjs_1 reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; wire fabric_v_f_wr_sjs_1$CLR, fabric_v_f_wr_sjs_1$DEQ, fabric_v_f_wr_sjs_1$EMPTY_N, fabric_v_f_wr_sjs_1$ENQ, fabric_v_f_wr_sjs_1$FULL_N; // ports of submodule fabric_xactors_from_masters_0_f_rd_addr wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, fabric_xactors_from_masters_0_f_rd_addr$D_OUT; wire fabric_xactors_from_masters_0_f_rd_addr$CLR, fabric_xactors_from_masters_0_f_rd_addr$DEQ, fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, fabric_xactors_from_masters_0_f_rd_addr$ENQ, fabric_xactors_from_masters_0_f_rd_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_0_f_rd_data reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; wire fabric_xactors_from_masters_0_f_rd_data$CLR, fabric_xactors_from_masters_0_f_rd_data$DEQ, fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, fabric_xactors_from_masters_0_f_rd_data$ENQ, fabric_xactors_from_masters_0_f_rd_data$FULL_N; // ports of submodule fabric_xactors_from_masters_0_f_wr_addr wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, fabric_xactors_from_masters_0_f_wr_addr$D_OUT; wire fabric_xactors_from_masters_0_f_wr_addr$CLR, fabric_xactors_from_masters_0_f_wr_addr$DEQ, fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, fabric_xactors_from_masters_0_f_wr_addr$ENQ, fabric_xactors_from_masters_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_0_f_wr_data wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, fabric_xactors_from_masters_0_f_wr_data$D_OUT; wire fabric_xactors_from_masters_0_f_wr_data$CLR, fabric_xactors_from_masters_0_f_wr_data$DEQ, fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, fabric_xactors_from_masters_0_f_wr_data$ENQ, fabric_xactors_from_masters_0_f_wr_data$FULL_N; // ports of submodule fabric_xactors_from_masters_0_f_wr_resp reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; wire fabric_xactors_from_masters_0_f_wr_resp$CLR, fabric_xactors_from_masters_0_f_wr_resp$DEQ, fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, fabric_xactors_from_masters_0_f_wr_resp$ENQ, fabric_xactors_from_masters_0_f_wr_resp$FULL_N; // ports of submodule fabric_xactors_from_masters_1_f_rd_addr wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, fabric_xactors_from_masters_1_f_rd_addr$D_OUT; wire fabric_xactors_from_masters_1_f_rd_addr$CLR, fabric_xactors_from_masters_1_f_rd_addr$DEQ, fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, fabric_xactors_from_masters_1_f_rd_addr$ENQ, fabric_xactors_from_masters_1_f_rd_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_1_f_rd_data reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; wire fabric_xactors_from_masters_1_f_rd_data$CLR, fabric_xactors_from_masters_1_f_rd_data$DEQ, fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, fabric_xactors_from_masters_1_f_rd_data$ENQ, fabric_xactors_from_masters_1_f_rd_data$FULL_N; // ports of submodule fabric_xactors_from_masters_1_f_wr_addr wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, fabric_xactors_from_masters_1_f_wr_addr$D_OUT; wire fabric_xactors_from_masters_1_f_wr_addr$CLR, fabric_xactors_from_masters_1_f_wr_addr$DEQ, fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, fabric_xactors_from_masters_1_f_wr_addr$ENQ, fabric_xactors_from_masters_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_from_masters_1_f_wr_data wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, fabric_xactors_from_masters_1_f_wr_data$D_OUT; wire fabric_xactors_from_masters_1_f_wr_data$CLR, fabric_xactors_from_masters_1_f_wr_data$DEQ, fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, fabric_xactors_from_masters_1_f_wr_data$ENQ, fabric_xactors_from_masters_1_f_wr_data$FULL_N; // ports of submodule fabric_xactors_from_masters_1_f_wr_resp reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; wire fabric_xactors_from_masters_1_f_wr_resp$CLR, fabric_xactors_from_masters_1_f_wr_resp$DEQ, fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, fabric_xactors_from_masters_1_f_wr_resp$ENQ, fabric_xactors_from_masters_1_f_wr_resp$FULL_N; // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, fabric_xactors_to_slaves_0_f_rd_addr$DEQ, fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, fabric_xactors_to_slaves_0_f_rd_addr$ENQ, fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_0_f_rd_data wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, fabric_xactors_to_slaves_0_f_rd_data$D_OUT; wire fabric_xactors_to_slaves_0_f_rd_data$CLR, fabric_xactors_to_slaves_0_f_rd_data$DEQ, fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, fabric_xactors_to_slaves_0_f_rd_data$ENQ, fabric_xactors_to_slaves_0_f_rd_data$FULL_N; // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, fabric_xactors_to_slaves_0_f_wr_addr$DEQ, fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, fabric_xactors_to_slaves_0_f_wr_addr$ENQ, fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_0_f_wr_data wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, fabric_xactors_to_slaves_0_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_0_f_wr_data$CLR, fabric_xactors_to_slaves_0_f_wr_data$DEQ, fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, fabric_xactors_to_slaves_0_f_wr_data$ENQ, fabric_xactors_to_slaves_0_f_wr_data$FULL_N; // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, fabric_xactors_to_slaves_0_f_wr_resp$DEQ, fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, fabric_xactors_to_slaves_0_f_wr_resp$ENQ, fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, fabric_xactors_to_slaves_1_f_rd_addr$DEQ, fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, fabric_xactors_to_slaves_1_f_rd_addr$ENQ, fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_1_f_rd_data wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, fabric_xactors_to_slaves_1_f_rd_data$D_OUT; wire fabric_xactors_to_slaves_1_f_rd_data$CLR, fabric_xactors_to_slaves_1_f_rd_data$DEQ, fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, fabric_xactors_to_slaves_1_f_rd_data$ENQ, fabric_xactors_to_slaves_1_f_rd_data$FULL_N; // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, fabric_xactors_to_slaves_1_f_wr_addr$DEQ, fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, fabric_xactors_to_slaves_1_f_wr_addr$ENQ, fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_1_f_wr_data wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, fabric_xactors_to_slaves_1_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_1_f_wr_data$CLR, fabric_xactors_to_slaves_1_f_wr_data$DEQ, fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, fabric_xactors_to_slaves_1_f_wr_data$ENQ, fabric_xactors_to_slaves_1_f_wr_data$FULL_N; // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, fabric_xactors_to_slaves_1_f_wr_resp$DEQ, fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, fabric_xactors_to_slaves_1_f_wr_resp$ENQ, fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, fabric_xactors_to_slaves_2_f_rd_addr$DEQ, fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, fabric_xactors_to_slaves_2_f_rd_addr$ENQ, fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_2_f_rd_data wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, fabric_xactors_to_slaves_2_f_rd_data$D_OUT; wire fabric_xactors_to_slaves_2_f_rd_data$CLR, fabric_xactors_to_slaves_2_f_rd_data$DEQ, fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, fabric_xactors_to_slaves_2_f_rd_data$ENQ, fabric_xactors_to_slaves_2_f_rd_data$FULL_N; // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, fabric_xactors_to_slaves_2_f_wr_addr$DEQ, fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, fabric_xactors_to_slaves_2_f_wr_addr$ENQ, fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; // ports of submodule fabric_xactors_to_slaves_2_f_wr_data wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, fabric_xactors_to_slaves_2_f_wr_data$D_OUT; wire fabric_xactors_to_slaves_2_f_wr_data$CLR, fabric_xactors_to_slaves_2_f_wr_data$DEQ, fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, fabric_xactors_to_slaves_2_f_wr_data$ENQ, fabric_xactors_to_slaves_2_f_wr_data$FULL_N; // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, fabric_xactors_to_slaves_2_f_wr_resp$DEQ, fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, fabric_xactors_to_slaves_2_f_wr_resp$ENQ, fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; // ports of submodule soc_map wire [63 : 0] soc_map$m_is_IO_addr_addr, soc_map$m_is_mem_addr_addr, soc_map$m_is_near_mem_IO_addr_addr, soc_map$m_near_mem_io_addr_base, soc_map$m_near_mem_io_addr_lim, soc_map$m_plic_addr_base, soc_map$m_plic_addr_lim; // rule scheduling signals wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, CAN_FIRE_RL_fabric_rl_reset, CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, CAN_FIRE_reset, CAN_FIRE_set_verbosity, CAN_FIRE_v_from_masters_0_m_arvalid, CAN_FIRE_v_from_masters_0_m_awvalid, CAN_FIRE_v_from_masters_0_m_bready, CAN_FIRE_v_from_masters_0_m_rready, CAN_FIRE_v_from_masters_0_m_wvalid, CAN_FIRE_v_from_masters_1_m_arvalid, CAN_FIRE_v_from_masters_1_m_awvalid, CAN_FIRE_v_from_masters_1_m_bready, CAN_FIRE_v_from_masters_1_m_rready, CAN_FIRE_v_from_masters_1_m_wvalid, CAN_FIRE_v_to_slaves_0_m_arready, CAN_FIRE_v_to_slaves_0_m_awready, CAN_FIRE_v_to_slaves_0_m_bvalid, CAN_FIRE_v_to_slaves_0_m_rvalid, CAN_FIRE_v_to_slaves_0_m_wready, CAN_FIRE_v_to_slaves_1_m_arready, CAN_FIRE_v_to_slaves_1_m_awready, CAN_FIRE_v_to_slaves_1_m_bvalid, CAN_FIRE_v_to_slaves_1_m_rvalid, CAN_FIRE_v_to_slaves_1_m_wready, CAN_FIRE_v_to_slaves_2_m_arready, CAN_FIRE_v_to_slaves_2_m_awready, CAN_FIRE_v_to_slaves_2_m_bvalid, CAN_FIRE_v_to_slaves_2_m_rvalid, CAN_FIRE_v_to_slaves_2_m_wready, WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, WILL_FIRE_RL_fabric_rl_reset, WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, WILL_FIRE_reset, WILL_FIRE_set_verbosity, WILL_FIRE_v_from_masters_0_m_arvalid, WILL_FIRE_v_from_masters_0_m_awvalid, WILL_FIRE_v_from_masters_0_m_bready, WILL_FIRE_v_from_masters_0_m_rready, WILL_FIRE_v_from_masters_0_m_wvalid, WILL_FIRE_v_from_masters_1_m_arvalid, WILL_FIRE_v_from_masters_1_m_awvalid, WILL_FIRE_v_from_masters_1_m_bready, WILL_FIRE_v_from_masters_1_m_rready, WILL_FIRE_v_from_masters_1_m_wvalid, WILL_FIRE_v_to_slaves_0_m_arready, WILL_FIRE_v_to_slaves_0_m_awready, WILL_FIRE_v_to_slaves_0_m_bvalid, WILL_FIRE_v_to_slaves_0_m_rvalid, WILL_FIRE_v_to_slaves_0_m_wready, WILL_FIRE_v_to_slaves_1_m_arready, WILL_FIRE_v_to_slaves_1_m_awready, WILL_FIRE_v_to_slaves_1_m_bvalid, WILL_FIRE_v_to_slaves_1_m_rvalid, WILL_FIRE_v_to_slaves_1_m_wready, WILL_FIRE_v_to_slaves_2_m_arready, WILL_FIRE_v_to_slaves_2_m_awready, WILL_FIRE_v_to_slaves_2_m_bvalid, WILL_FIRE_v_to_slaves_2_m_rvalid, WILL_FIRE_v_to_slaves_2_m_wready; // inputs to muxes for submodule ports wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; wire [9 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2, MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; // declarations used by system tasks // synopsys translate_off reg [31 : 0] v__h8466; reg [31 : 0] v__h8813; reg [31 : 0] v__h9160; reg [31 : 0] v__h9570; reg [31 : 0] v__h9911; reg [31 : 0] v__h10252; reg [31 : 0] v__h11228; reg [31 : 0] v__h11475; reg [31 : 0] v__h11829; reg [31 : 0] v__h12076; reg [31 : 0] v__h12433; reg [31 : 0] v__h12703; reg [31 : 0] v__h12973; reg [31 : 0] v__h13247; reg [31 : 0] v__h13491; reg [31 : 0] v__h13735; reg [31 : 0] v__h13969; reg [31 : 0] v__h14179; reg [31 : 0] v__h14579; reg [31 : 0] v__h14913; reg [31 : 0] v__h15247; reg [31 : 0] v__h15635; reg [31 : 0] v__h15945; reg [31 : 0] v__h16255; reg [31 : 0] v__h17211; reg [31 : 0] v__h17492; reg [31 : 0] v__h17860; reg [31 : 0] v__h18131; reg [31 : 0] v__h18499; reg [31 : 0] v__h18770; reg [31 : 0] v__h19118; reg [31 : 0] v__h19399; reg [31 : 0] v__h19722; reg [31 : 0] v__h19993; reg [31 : 0] v__h20316; reg [31 : 0] v__h20587; reg [31 : 0] v__h21067; reg [31 : 0] v__h21449; reg [31 : 0] v__h5786; reg [31 : 0] v__h5780; reg [31 : 0] v__h8460; reg [31 : 0] v__h8807; reg [31 : 0] v__h9154; reg [31 : 0] v__h9564; reg [31 : 0] v__h9905; reg [31 : 0] v__h10246; reg [31 : 0] v__h11222; reg [31 : 0] v__h11469; reg [31 : 0] v__h11823; reg [31 : 0] v__h12070; reg [31 : 0] v__h12427; reg [31 : 0] v__h12697; reg [31 : 0] v__h12967; reg [31 : 0] v__h13241; reg [31 : 0] v__h13485; reg [31 : 0] v__h13729; reg [31 : 0] v__h13963; reg [31 : 0] v__h14173; reg [31 : 0] v__h14573; reg [31 : 0] v__h14907; reg [31 : 0] v__h15241; reg [31 : 0] v__h15629; reg [31 : 0] v__h15939; reg [31 : 0] v__h16249; reg [31 : 0] v__h17205; reg [31 : 0] v__h17486; reg [31 : 0] v__h17854; reg [31 : 0] v__h18125; reg [31 : 0] v__h18493; reg [31 : 0] v__h18764; reg [31 : 0] v__h19112; reg [31 : 0] v__h19393; reg [31 : 0] v__h19716; reg [31 : 0] v__h19987; reg [31 : 0] v__h20310; reg [31 : 0] v__h20581; reg [31 : 0] v__h21061; reg [31 : 0] v__h21443; // synopsys translate_on // remaining internal signals reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; wire [7 : 0] x__h11377, x__h11978, x__h17375, x__h18024, x__h18663, x__h21004, x__h21386; wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403, IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438, IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473, x1_avValue_rresp__h17353, x1_avValue_rresp__h18002, x1_avValue_rresp__h18641; wire _dor1fabric_v_f_rd_mis_0$EN_deq, _dor1fabric_v_f_rd_mis_1$EN_deq, _dor1fabric_v_f_rd_mis_2$EN_deq, fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130, fabric_v_f_wd_tasks_1_i_notEmpty__53_AND_fabri_ETC___d159, fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387, fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422, fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457, fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522, fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540, fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146, fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175, fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286, fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291, fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22, fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29, fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336, fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341, fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83, fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88, soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19, soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284, soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334, soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81, soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26, soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289, soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339, soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86; // action method reset assign RDY_reset = !fabric_rg_reset ; assign CAN_FIRE_reset = !fabric_rg_reset ; assign WILL_FIRE_reset = EN_reset ; // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; assign CAN_FIRE_set_verbosity = 1'd1 ; assign WILL_FIRE_set_verbosity = EN_set_verbosity ; // action method v_from_masters_0_m_awvalid assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; // value method v_from_masters_0_m_awready assign v_from_masters_0_awready = fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; // action method v_from_masters_0_m_wvalid assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; // value method v_from_masters_0_m_wready assign v_from_masters_0_wready = fabric_xactors_from_masters_0_f_wr_data$FULL_N ; // value method v_from_masters_0_m_bvalid assign v_from_masters_0_bvalid = fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; // value method v_from_masters_0_m_bid assign v_from_masters_0_bid = fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; // value method v_from_masters_0_m_bresp assign v_from_masters_0_bresp = fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; // action method v_from_masters_0_m_bready assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; // action method v_from_masters_0_m_arvalid assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; // value method v_from_masters_0_m_arready assign v_from_masters_0_arready = fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; // value method v_from_masters_0_m_rvalid assign v_from_masters_0_rvalid = fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; // value method v_from_masters_0_m_rid assign v_from_masters_0_rid = fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; // value method v_from_masters_0_m_rdata assign v_from_masters_0_rdata = fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; // value method v_from_masters_0_m_rresp assign v_from_masters_0_rresp = fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; // value method v_from_masters_0_m_rlast assign v_from_masters_0_rlast = fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; // action method v_from_masters_0_m_rready assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; // action method v_from_masters_1_m_awvalid assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; // value method v_from_masters_1_m_awready assign v_from_masters_1_awready = fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; // action method v_from_masters_1_m_wvalid assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; // value method v_from_masters_1_m_wready assign v_from_masters_1_wready = fabric_xactors_from_masters_1_f_wr_data$FULL_N ; // value method v_from_masters_1_m_bvalid assign v_from_masters_1_bvalid = fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; // value method v_from_masters_1_m_bid assign v_from_masters_1_bid = fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; // value method v_from_masters_1_m_bresp assign v_from_masters_1_bresp = fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; // action method v_from_masters_1_m_bready assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; // action method v_from_masters_1_m_arvalid assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; // value method v_from_masters_1_m_arready assign v_from_masters_1_arready = fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; // value method v_from_masters_1_m_rvalid assign v_from_masters_1_rvalid = fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; // value method v_from_masters_1_m_rid assign v_from_masters_1_rid = fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; // value method v_from_masters_1_m_rdata assign v_from_masters_1_rdata = fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; // value method v_from_masters_1_m_rresp assign v_from_masters_1_rresp = fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; // value method v_from_masters_1_m_rlast assign v_from_masters_1_rlast = fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; // action method v_from_masters_1_m_rready assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; // value method v_to_slaves_0_m_awvalid assign v_to_slaves_0_awvalid = fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; // value method v_to_slaves_0_m_awid assign v_to_slaves_0_awid = fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; // value method v_to_slaves_0_m_awaddr assign v_to_slaves_0_awaddr = fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; // value method v_to_slaves_0_m_awlen assign v_to_slaves_0_awlen = fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; // value method v_to_slaves_0_m_awsize assign v_to_slaves_0_awsize = fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; // value method v_to_slaves_0_m_awburst assign v_to_slaves_0_awburst = fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; // value method v_to_slaves_0_m_awlock assign v_to_slaves_0_awlock = fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; // value method v_to_slaves_0_m_awcache assign v_to_slaves_0_awcache = fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; // value method v_to_slaves_0_m_awprot assign v_to_slaves_0_awprot = fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; // value method v_to_slaves_0_m_awqos assign v_to_slaves_0_awqos = fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; // value method v_to_slaves_0_m_awregion assign v_to_slaves_0_awregion = fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; // action method v_to_slaves_0_m_awready assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; // value method v_to_slaves_0_m_wvalid assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; // value method v_to_slaves_0_m_wdata assign v_to_slaves_0_wdata = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; // value method v_to_slaves_0_m_wstrb assign v_to_slaves_0_wstrb = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; // value method v_to_slaves_0_m_wlast assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; // action method v_to_slaves_0_m_wready assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; // action method v_to_slaves_0_m_bvalid assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; // value method v_to_slaves_0_m_bready assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; // value method v_to_slaves_0_m_arvalid assign v_to_slaves_0_arvalid = fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; // value method v_to_slaves_0_m_arid assign v_to_slaves_0_arid = fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; // value method v_to_slaves_0_m_araddr assign v_to_slaves_0_araddr = fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; // value method v_to_slaves_0_m_arlen assign v_to_slaves_0_arlen = fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; // value method v_to_slaves_0_m_arsize assign v_to_slaves_0_arsize = fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; // value method v_to_slaves_0_m_arburst assign v_to_slaves_0_arburst = fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; // value method v_to_slaves_0_m_arlock assign v_to_slaves_0_arlock = fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; // value method v_to_slaves_0_m_arcache assign v_to_slaves_0_arcache = fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; // value method v_to_slaves_0_m_arprot assign v_to_slaves_0_arprot = fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; // value method v_to_slaves_0_m_arqos assign v_to_slaves_0_arqos = fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; // value method v_to_slaves_0_m_arregion assign v_to_slaves_0_arregion = fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; // action method v_to_slaves_0_m_arready assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; // action method v_to_slaves_0_m_rvalid assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; // value method v_to_slaves_0_m_rready assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; // value method v_to_slaves_1_m_awvalid assign v_to_slaves_1_awvalid = fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; // value method v_to_slaves_1_m_awid assign v_to_slaves_1_awid = fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; // value method v_to_slaves_1_m_awaddr assign v_to_slaves_1_awaddr = fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; // value method v_to_slaves_1_m_awlen assign v_to_slaves_1_awlen = fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; // value method v_to_slaves_1_m_awsize assign v_to_slaves_1_awsize = fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; // value method v_to_slaves_1_m_awburst assign v_to_slaves_1_awburst = fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; // value method v_to_slaves_1_m_awlock assign v_to_slaves_1_awlock = fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; // value method v_to_slaves_1_m_awcache assign v_to_slaves_1_awcache = fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; // value method v_to_slaves_1_m_awprot assign v_to_slaves_1_awprot = fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; // value method v_to_slaves_1_m_awqos assign v_to_slaves_1_awqos = fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; // value method v_to_slaves_1_m_awregion assign v_to_slaves_1_awregion = fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; // action method v_to_slaves_1_m_awready assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; // value method v_to_slaves_1_m_wvalid assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; // value method v_to_slaves_1_m_wdata assign v_to_slaves_1_wdata = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; // value method v_to_slaves_1_m_wstrb assign v_to_slaves_1_wstrb = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; // value method v_to_slaves_1_m_wlast assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; // action method v_to_slaves_1_m_wready assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; // action method v_to_slaves_1_m_bvalid assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; // value method v_to_slaves_1_m_bready assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; // value method v_to_slaves_1_m_arvalid assign v_to_slaves_1_arvalid = fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; // value method v_to_slaves_1_m_arid assign v_to_slaves_1_arid = fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; // value method v_to_slaves_1_m_araddr assign v_to_slaves_1_araddr = fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; // value method v_to_slaves_1_m_arlen assign v_to_slaves_1_arlen = fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; // value method v_to_slaves_1_m_arsize assign v_to_slaves_1_arsize = fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; // value method v_to_slaves_1_m_arburst assign v_to_slaves_1_arburst = fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; // value method v_to_slaves_1_m_arlock assign v_to_slaves_1_arlock = fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; // value method v_to_slaves_1_m_arcache assign v_to_slaves_1_arcache = fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; // value method v_to_slaves_1_m_arprot assign v_to_slaves_1_arprot = fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; // value method v_to_slaves_1_m_arqos assign v_to_slaves_1_arqos = fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; // value method v_to_slaves_1_m_arregion assign v_to_slaves_1_arregion = fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; // action method v_to_slaves_1_m_arready assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; // action method v_to_slaves_1_m_rvalid assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; // value method v_to_slaves_1_m_rready assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; // value method v_to_slaves_2_m_awvalid assign v_to_slaves_2_awvalid = fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; // value method v_to_slaves_2_m_awid assign v_to_slaves_2_awid = fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; // value method v_to_slaves_2_m_awaddr assign v_to_slaves_2_awaddr = fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; // value method v_to_slaves_2_m_awlen assign v_to_slaves_2_awlen = fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; // value method v_to_slaves_2_m_awsize assign v_to_slaves_2_awsize = fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; // value method v_to_slaves_2_m_awburst assign v_to_slaves_2_awburst = fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; // value method v_to_slaves_2_m_awlock assign v_to_slaves_2_awlock = fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; // value method v_to_slaves_2_m_awcache assign v_to_slaves_2_awcache = fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; // value method v_to_slaves_2_m_awprot assign v_to_slaves_2_awprot = fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; // value method v_to_slaves_2_m_awqos assign v_to_slaves_2_awqos = fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; // value method v_to_slaves_2_m_awregion assign v_to_slaves_2_awregion = fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; // action method v_to_slaves_2_m_awready assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; // value method v_to_slaves_2_m_wvalid assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; // value method v_to_slaves_2_m_wdata assign v_to_slaves_2_wdata = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; // value method v_to_slaves_2_m_wstrb assign v_to_slaves_2_wstrb = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; // value method v_to_slaves_2_m_wlast assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; // action method v_to_slaves_2_m_wready assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; // action method v_to_slaves_2_m_bvalid assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; // value method v_to_slaves_2_m_bready assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; // value method v_to_slaves_2_m_arvalid assign v_to_slaves_2_arvalid = fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; // value method v_to_slaves_2_m_arid assign v_to_slaves_2_arid = fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; // value method v_to_slaves_2_m_araddr assign v_to_slaves_2_araddr = fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; // value method v_to_slaves_2_m_arlen assign v_to_slaves_2_arlen = fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; // value method v_to_slaves_2_m_arsize assign v_to_slaves_2_arsize = fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; // value method v_to_slaves_2_m_arburst assign v_to_slaves_2_arburst = fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; // value method v_to_slaves_2_m_arlock assign v_to_slaves_2_arlock = fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; // value method v_to_slaves_2_m_arcache assign v_to_slaves_2_arcache = fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; // value method v_to_slaves_2_m_arprot assign v_to_slaves_2_arprot = fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; // value method v_to_slaves_2_m_arqos assign v_to_slaves_2_arqos = fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; // value method v_to_slaves_2_m_arregion assign v_to_slaves_2_arregion = fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; // action method v_to_slaves_2_m_arready assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; // action method v_to_slaves_2_m_rvalid assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; // value method v_to_slaves_2_m_rready assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; // submodule fabric_v_f_rd_err_info_0 SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_rd_err_info_0$D_IN), .ENQ(fabric_v_f_rd_err_info_0$ENQ), .DEQ(fabric_v_f_rd_err_info_0$DEQ), .CLR(fabric_v_f_rd_err_info_0$CLR), .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), .FULL_N(), .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); // submodule fabric_v_f_rd_err_info_1 SizedFIFO #(.p1width(32'd12), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_rd_err_info_1$D_IN), .ENQ(fabric_v_f_rd_err_info_1$ENQ), .DEQ(fabric_v_f_rd_err_info_1$DEQ), .CLR(fabric_v_f_rd_err_info_1$CLR), .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), .FULL_N(), .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_0 SizedFIFO #(.p1width(32'd10), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_rd_mis_0$D_IN), .ENQ(fabric_v_f_rd_mis_0$ENQ), .DEQ(fabric_v_f_rd_mis_0$DEQ), .CLR(fabric_v_f_rd_mis_0$CLR), .D_OUT(fabric_v_f_rd_mis_0$D_OUT), .FULL_N(fabric_v_f_rd_mis_0$FULL_N), .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); // submodule fabric_v_f_rd_mis_1 SizedFIFO #(.p1width(32'd10), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_rd_mis_1$D_IN), .ENQ(fabric_v_f_rd_mis_1$ENQ), .DEQ(fabric_v_f_rd_mis_1$DEQ), .CLR(fabric_v_f_rd_mis_1$CLR), .D_OUT(fabric_v_f_rd_mis_1$D_OUT), .FULL_N(fabric_v_f_rd_mis_1$FULL_N), .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); // submodule fabric_v_f_rd_mis_2 SizedFIFO #(.p1width(32'd10), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_rd_mis_2$D_IN), .ENQ(fabric_v_f_rd_mis_2$ENQ), .DEQ(fabric_v_f_rd_mis_2$DEQ), .CLR(fabric_v_f_rd_mis_2$CLR), .D_OUT(fabric_v_f_rd_mis_2$D_OUT), .FULL_N(fabric_v_f_rd_mis_2$FULL_N), .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); // submodule fabric_v_f_rd_sjs_0 SizedFIFO #(.p1width(32'd2), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_rd_sjs_0$D_IN), .ENQ(fabric_v_f_rd_sjs_0$ENQ), .DEQ(fabric_v_f_rd_sjs_0$DEQ), .CLR(fabric_v_f_rd_sjs_0$CLR), .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); // submodule fabric_v_f_rd_sjs_1 SizedFIFO #(.p1width(32'd2), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_rd_sjs_1$D_IN), .ENQ(fabric_v_f_rd_sjs_1$ENQ), .DEQ(fabric_v_f_rd_sjs_1$DEQ), .CLR(fabric_v_f_rd_sjs_1$CLR), .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); // submodule fabric_v_f_wd_tasks_0 FIFO2 #(.width(32'd10), .guarded(1'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_wd_tasks_0$D_IN), .ENQ(fabric_v_f_wd_tasks_0$ENQ), .DEQ(fabric_v_f_wd_tasks_0$DEQ), .CLR(fabric_v_f_wd_tasks_0$CLR), .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); // submodule fabric_v_f_wd_tasks_1 FIFO2 #(.width(32'd10), .guarded(1'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_wd_tasks_1$D_IN), .ENQ(fabric_v_f_wd_tasks_1$ENQ), .DEQ(fabric_v_f_wd_tasks_1$DEQ), .CLR(fabric_v_f_wd_tasks_1$CLR), .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); // submodule fabric_v_f_wr_err_info_0 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_wr_err_info_0$D_IN), .ENQ(fabric_v_f_wr_err_info_0$ENQ), .DEQ(fabric_v_f_wr_err_info_0$DEQ), .CLR(fabric_v_f_wr_err_info_0$CLR), .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), .FULL_N(), .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); // submodule fabric_v_f_wr_err_info_1 SizedFIFO #(.p1width(32'd4), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_wr_err_info_1$D_IN), .ENQ(fabric_v_f_wr_err_info_1$ENQ), .DEQ(fabric_v_f_wr_err_info_1$DEQ), .CLR(fabric_v_f_wr_err_info_1$CLR), .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), .FULL_N(), .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_0 SizedFIFO #(.p1width(32'd2), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_wr_mis_0$D_IN), .ENQ(fabric_v_f_wr_mis_0$ENQ), .DEQ(fabric_v_f_wr_mis_0$DEQ), .CLR(fabric_v_f_wr_mis_0$CLR), .D_OUT(fabric_v_f_wr_mis_0$D_OUT), .FULL_N(fabric_v_f_wr_mis_0$FULL_N), .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); // submodule fabric_v_f_wr_mis_1 SizedFIFO #(.p1width(32'd2), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_wr_mis_1$D_IN), .ENQ(fabric_v_f_wr_mis_1$ENQ), .DEQ(fabric_v_f_wr_mis_1$DEQ), .CLR(fabric_v_f_wr_mis_1$CLR), .D_OUT(fabric_v_f_wr_mis_1$D_OUT), .FULL_N(fabric_v_f_wr_mis_1$FULL_N), .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); // submodule fabric_v_f_wr_mis_2 SizedFIFO #(.p1width(32'd2), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_wr_mis_2$D_IN), .ENQ(fabric_v_f_wr_mis_2$ENQ), .DEQ(fabric_v_f_wr_mis_2$DEQ), .CLR(fabric_v_f_wr_mis_2$CLR), .D_OUT(fabric_v_f_wr_mis_2$D_OUT), .FULL_N(fabric_v_f_wr_mis_2$FULL_N), .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); // submodule fabric_v_f_wr_sjs_0 SizedFIFO #(.p1width(32'd2), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_wr_sjs_0$D_IN), .ENQ(fabric_v_f_wr_sjs_0$ENQ), .DEQ(fabric_v_f_wr_sjs_0$DEQ), .CLR(fabric_v_f_wr_sjs_0$CLR), .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); // submodule fabric_v_f_wr_sjs_1 SizedFIFO #(.p1width(32'd2), .p2depth(32'd8), .p3cntr_width(32'd3), .guarded(1'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), .CLK(CLK), .D_IN(fabric_v_f_wr_sjs_1$D_IN), .ENQ(fabric_v_f_wr_sjs_1$ENQ), .DEQ(fabric_v_f_wr_sjs_1$DEQ), .CLR(fabric_v_f_wr_sjs_1$CLR), .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); // submodule fabric_xactors_from_masters_0_f_rd_addr FIFO2 #(.width(32'd97), .guarded(1'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_0_f_rd_data FIFO2 #(.width(32'd71), .guarded(1'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); // submodule fabric_xactors_from_masters_0_f_wr_addr FIFO2 #(.width(32'd97), .guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_0_f_wr_data FIFO2 #(.width(32'd73), .guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); // submodule fabric_xactors_from_masters_0_f_wr_resp FIFO2 #(.width(32'd6), .guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); // submodule fabric_xactors_from_masters_1_f_rd_addr FIFO2 #(.width(32'd97), .guarded(1'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_1_f_rd_data FIFO2 #(.width(32'd71), .guarded(1'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); // submodule fabric_xactors_from_masters_1_f_wr_addr FIFO2 #(.width(32'd97), .guarded(1'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_from_masters_1_f_wr_data FIFO2 #(.width(32'd73), .guarded(1'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); // submodule fabric_xactors_from_masters_1_f_wr_resp FIFO2 #(.width(32'd6), .guarded(1'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); // submodule fabric_xactors_to_slaves_0_f_rd_addr FIFO2 #(.width(32'd97), .guarded(1'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_0_f_rd_data FIFO2 #(.width(32'd71), .guarded(1'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); // submodule fabric_xactors_to_slaves_0_f_wr_addr FIFO2 #(.width(32'd97), .guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_0_f_wr_data FIFO2 #(.width(32'd73), .guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); // submodule fabric_xactors_to_slaves_0_f_wr_resp FIFO2 #(.width(32'd6), .guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); // submodule fabric_xactors_to_slaves_1_f_rd_addr FIFO2 #(.width(32'd97), .guarded(1'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_1_f_rd_data FIFO2 #(.width(32'd71), .guarded(1'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); // submodule fabric_xactors_to_slaves_1_f_wr_addr FIFO2 #(.width(32'd97), .guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_1_f_wr_data FIFO2 #(.width(32'd73), .guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); // submodule fabric_xactors_to_slaves_1_f_wr_resp FIFO2 #(.width(32'd6), .guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); // submodule fabric_xactors_to_slaves_2_f_rd_addr FIFO2 #(.width(32'd97), .guarded(1'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_2_f_rd_data FIFO2 #(.width(32'd71), .guarded(1'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); // submodule fabric_xactors_to_slaves_2_f_wr_addr FIFO2 #(.width(32'd97), .guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); // submodule fabric_xactors_to_slaves_2_f_wr_data FIFO2 #(.width(32'd73), .guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); // submodule fabric_xactors_to_slaves_2_f_wr_resp FIFO2 #(.width(32'd6), .guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), .CLK(CLK), .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); // submodule soc_map mkSoC_Map soc_map(.CLK(CLK), .RST_N(RST_N), .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), .m_near_mem_io_addr_size(), .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), .m_plic_addr_base(soc_map$m_plic_addr_base), .m_plic_addr_size(), .m_plic_addr_lim(soc_map$m_plic_addr_lim), .m_uart0_addr_base(), .m_uart0_addr_size(), .m_uart0_addr_lim(), .m_boot_rom_addr_base(), .m_boot_rom_addr_size(), .m_boot_rom_addr_lim(), .m_mem0_controller_addr_base(), .m_mem0_controller_addr_size(), .m_mem0_controller_addr_lim(), .m_tcm_addr_base(), .m_tcm_addr_size(), .m_tcm_addr_lim(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), .m_pc_reset_value(), .m_mtvec_reset_value(), .m_nmivec_reset_value()); // rule RL_fabric_rl_wr_xaction_master_to_slave assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && (!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 || !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) && (!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 || !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29) ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; // rule RL_fabric_rl_wr_xaction_master_to_slave_1 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && fabric_v_f_wr_mis_1$FULL_N && soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 && fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; // rule RL_fabric_rl_wr_xaction_master_to_slave_2 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && fabric_v_f_wd_tasks_0$FULL_N && fabric_v_f_wr_sjs_0$FULL_N && fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && fabric_v_f_wr_mis_2$FULL_N && (!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 || !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) && soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 && fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; // rule RL_fabric_rl_wr_xaction_master_to_slave_3 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && fabric_v_f_wr_mis_0$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && (!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 || !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && (!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 || !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; // rule RL_fabric_rl_wr_xaction_master_to_slave_4 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && fabric_v_f_wr_mis_1$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 && fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; // rule RL_fabric_rl_wr_xaction_master_to_slave_5 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && fabric_v_f_wr_mis_2$FULL_N && fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && fabric_v_f_wd_tasks_1$FULL_N && fabric_v_f_wr_sjs_1$FULL_N && (!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 || !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 && fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; // rule RL_fabric_rl_wr_xaction_master_to_slave_data assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && fabric_v_f_wd_tasks_1_i_notEmpty__53_AND_fabri_ETC___d159 ; assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; // rule RL_fabric_rl_wr_resp_slave_to_master assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && fabric_xactors_from_masters_0_f_wr_resp$FULL_N && fabric_v_f_wr_mis_0$D_OUT == 2'd0 && fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; // rule RL_fabric_rl_wr_resp_slave_to_master_1 assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = fabric_v_f_wr_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_wr_resp$FULL_N && fabric_v_f_wr_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && fabric_v_f_wr_mis_1$D_OUT == 2'd0 && fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; // rule RL_fabric_rl_wr_resp_slave_to_master_2 assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = fabric_v_f_wr_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_wr_resp$FULL_N && fabric_v_f_wr_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && fabric_v_f_wr_mis_2$D_OUT == 2'd0 && fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; // rule RL_fabric_rl_wr_resp_slave_to_master_3 assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = fabric_v_f_wr_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && fabric_v_f_wr_mis_0$D_OUT == 2'd1 && fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; // rule RL_fabric_rl_wr_resp_slave_to_master_4 assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = fabric_v_f_wr_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && fabric_v_f_wr_mis_1$D_OUT == 2'd1 && fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; // rule RL_fabric_rl_wr_resp_slave_to_master_5 assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = fabric_v_f_wr_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && fabric_v_f_wr_mis_2$D_OUT == 2'd1 && fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; // rule RL_fabric_rl_wr_resp_err_to_master assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = fabric_v_f_wr_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_wr_resp$FULL_N && fabric_v_f_wr_err_info_0$EMPTY_N && fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; // rule RL_fabric_rl_wr_resp_err_to_master_1 assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = fabric_v_f_wr_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_wr_resp$FULL_N && fabric_v_f_wr_err_info_1$EMPTY_N && fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; // rule RL_fabric_rl_rd_xaction_master_to_slave assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && fabric_v_f_rd_mis_0$FULL_N && fabric_v_f_rd_sjs_0$FULL_N && (!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 || !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286) && (!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289 || !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291) ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; // rule RL_fabric_rl_rd_xaction_master_to_slave_1 assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_0$FULL_N && fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && fabric_v_f_rd_mis_1$FULL_N && soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 && fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; // rule RL_fabric_rl_rd_xaction_master_to_slave_2 assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_0$FULL_N && fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && fabric_v_f_rd_mis_2$FULL_N && (!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 || !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286) && soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289 && fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; // rule RL_fabric_rl_rd_xaction_master_to_slave_3 assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && fabric_v_f_rd_mis_0$FULL_N && fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_1$FULL_N && (!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 || !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336) && (!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339 || !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341) ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; // rule RL_fabric_rl_rd_xaction_master_to_slave_4 assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && fabric_v_f_rd_mis_1$FULL_N && fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_1$FULL_N && soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 && fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; // rule RL_fabric_rl_rd_xaction_master_to_slave_5 assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && fabric_v_f_rd_mis_2$FULL_N && fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && fabric_v_f_rd_sjs_1$FULL_N && (!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 || !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336) && soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339 && fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341 ; assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; // rule RL_fabric_rl_rd_resp_slave_to_master assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_sjs_0$EMPTY_N && fabric_v_f_rd_mis_0$D_OUT[9:8] == 2'd0 && fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; // rule RL_fabric_rl_rd_resp_slave_to_master_1 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && fabric_v_f_rd_sjs_0$EMPTY_N && fabric_v_f_rd_mis_1$D_OUT[9:8] == 2'd0 && fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; // rule RL_fabric_rl_rd_resp_slave_to_master_2 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && fabric_v_f_rd_sjs_0$EMPTY_N && fabric_v_f_rd_mis_2$D_OUT[9:8] == 2'd0 && fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; // rule RL_fabric_rl_rd_resp_slave_to_master_3 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = fabric_v_f_rd_mis_0$EMPTY_N && fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && fabric_v_f_rd_sjs_1$EMPTY_N && fabric_v_f_rd_mis_0$D_OUT[9:8] == 2'd1 && fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; // rule RL_fabric_rl_rd_resp_slave_to_master_4 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = fabric_v_f_rd_mis_1$EMPTY_N && fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && fabric_v_f_rd_sjs_1$EMPTY_N && fabric_v_f_rd_mis_1$D_OUT[9:8] == 2'd1 && fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; // rule RL_fabric_rl_rd_resp_slave_to_master_5 assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = fabric_v_f_rd_mis_2$EMPTY_N && fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && fabric_v_f_rd_sjs_1$EMPTY_N && fabric_v_f_rd_mis_2$D_OUT[9:8] == 2'd1 && fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; // rule RL_fabric_rl_rd_resp_err_to_master assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = fabric_v_f_rd_sjs_0$EMPTY_N && fabric_xactors_from_masters_0_f_rd_data$FULL_N && fabric_v_f_rd_err_info_0$EMPTY_N && fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; // rule RL_fabric_rl_rd_resp_err_to_master_1 assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = fabric_v_f_rd_sjs_1$EMPTY_N && fabric_xactors_from_masters_1_f_rd_data$FULL_N && fabric_v_f_rd_err_info_1$EMPTY_N && fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; // rule RL_fabric_rl_reset assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; // inputs to muxes for submodule ports assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = { 2'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = { 2'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ? 8'd0 : x__h17375 ; assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ? 8'd0 : x__h18024 ; assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ? 8'd0 : x__h18663 ; assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 ? 8'd0 : x__h11377 ; assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 ? 8'd0 : x__h11978 ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403, fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438, fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473, fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = { fabric_v_f_rd_err_info_0$D_OUT[3:0], 66'd3, fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 } ; assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = { fabric_v_f_rd_err_info_1$D_OUT[3:0], 66'd3, fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 } ; assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; // register fabric_cfg_verbosity assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; assign fabric_cfg_verbosity$EN = EN_set_verbosity ; // register fabric_rg_reset assign fabric_rg_reset$D_IN = !fabric_rg_reset ; assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; // register fabric_v_rg_r_beat_count_0 always@(fabric_rg_reset or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) case (1'b1) fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: fabric_v_rg_r_beat_count_0$D_IN = MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: fabric_v_rg_r_beat_count_0$D_IN = MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; default: fabric_v_rg_r_beat_count_0$D_IN = 8'b10101010 /* unspecified value */ ; endcase assign fabric_v_rg_r_beat_count_0$EN = WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || fabric_rg_reset ; // register fabric_v_rg_r_beat_count_1 always@(fabric_rg_reset or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) case (1'b1) fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: fabric_v_rg_r_beat_count_1$D_IN = MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: fabric_v_rg_r_beat_count_1$D_IN = MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; default: fabric_v_rg_r_beat_count_1$D_IN = 8'b10101010 /* unspecified value */ ; endcase assign fabric_v_rg_r_beat_count_1$EN = WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || fabric_rg_reset ; // register fabric_v_rg_r_beat_count_2 always@(fabric_rg_reset or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) case (1'b1) fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_v_rg_r_beat_count_2$D_IN = MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_v_rg_r_beat_count_2$D_IN = MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; default: fabric_v_rg_r_beat_count_2$D_IN = 8'b10101010 /* unspecified value */ ; endcase assign fabric_v_rg_r_beat_count_2$EN = WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || fabric_rg_reset ; // register fabric_v_rg_r_err_beat_count_0 assign fabric_v_rg_r_err_beat_count_0$D_IN = fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ? 8'd0 : x__h21004 ; assign fabric_v_rg_r_err_beat_count_0$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; // register fabric_v_rg_r_err_beat_count_1 assign fabric_v_rg_r_err_beat_count_1$D_IN = fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ? 8'd0 : x__h21386 ; assign fabric_v_rg_r_err_beat_count_1$EN = CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; // register fabric_v_rg_wd_beat_count_0 assign fabric_v_rg_wd_beat_count_0$D_IN = fabric_rg_reset ? 8'd0 : MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; assign fabric_v_rg_wd_beat_count_0$EN = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || fabric_rg_reset ; // register fabric_v_rg_wd_beat_count_1 assign fabric_v_rg_wd_beat_count_1$D_IN = fabric_rg_reset ? 8'd0 : MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; assign fabric_v_rg_wd_beat_count_1$EN = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || fabric_rg_reset ; // submodule fabric_v_f_rd_err_info_0 assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ; assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ; assign fabric_v_f_rd_err_info_0$DEQ = WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_err_info_1 assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ; assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ; assign fabric_v_f_rd_err_info_1$DEQ = WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_0 assign fabric_v_f_rd_mis_0$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; assign fabric_v_f_rd_mis_0$DEQ = _dor1fabric_v_f_rd_mis_0$EN_deq && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ; assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_1 assign fabric_v_f_rd_mis_1$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; assign fabric_v_f_rd_mis_1$DEQ = _dor1fabric_v_f_rd_mis_1$EN_deq && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ; assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_mis_2 assign fabric_v_f_rd_mis_2$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; assign fabric_v_f_rd_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; assign fabric_v_f_rd_mis_2$DEQ = _dor1fabric_v_f_rd_mis_2$EN_deq && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ; assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_0 always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: fabric_v_f_rd_sjs_0$D_IN = 2'd0; WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: fabric_v_f_rd_sjs_0$D_IN = 2'd1; WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: fabric_v_f_rd_sjs_0$D_IN = 2'd2; default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; endcase end assign fabric_v_f_rd_sjs_0$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; assign fabric_v_f_rd_sjs_0$DEQ = WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_rd_sjs_1 always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: fabric_v_f_rd_sjs_1$D_IN = 2'd0; WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: fabric_v_f_rd_sjs_1$D_IN = 2'd1; WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: fabric_v_f_rd_sjs_1$D_IN = 2'd2; default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; endcase end assign fabric_v_f_rd_sjs_1$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; assign fabric_v_f_rd_sjs_1$DEQ = WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_wd_tasks_0 always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; default: fabric_v_f_wd_tasks_0$D_IN = 10'b1010101010 /* unspecified value */ ; endcase end assign fabric_v_f_wd_tasks_0$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; assign fabric_v_f_wd_tasks_0$DEQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 ; assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_wd_tasks_1 always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; default: fabric_v_f_wd_tasks_1$D_IN = 10'b1010101010 /* unspecified value */ ; endcase end assign fabric_v_f_wd_tasks_1$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; assign fabric_v_f_wd_tasks_1$DEQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 ; assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_wr_err_info_0 assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ; assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ; assign fabric_v_f_wr_err_info_0$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_wr_err_info_1 assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ; assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ; assign fabric_v_f_wr_err_info_1$DEQ = CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_wr_mis_0 assign fabric_v_f_wr_mis_0$D_IN = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? 2'd0 : 2'd1 ; assign fabric_v_f_wr_mis_0$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; assign fabric_v_f_wr_mis_0$DEQ = WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_wr_mis_1 assign fabric_v_f_wr_mis_1$D_IN = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? 2'd0 : 2'd1 ; assign fabric_v_f_wr_mis_1$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; assign fabric_v_f_wr_mis_1$DEQ = WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; // submodule fabric_v_f_wr_mis_2 assign fabric_v_f_wr_mis_2$D_IN = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? 2'd0 : 2'd1 ; assign fabric_v_f_wr_mis_2$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; assign fabric_v_f_wr_mis_2$DEQ = WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; // submodule fabric_v_f_wr_sjs_0 always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: fabric_v_f_wr_sjs_0$D_IN = 2'd0; WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: fabric_v_f_wr_sjs_0$D_IN = 2'd1; WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: fabric_v_f_wr_sjs_0$D_IN = 2'd2; default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; endcase end assign fabric_v_f_wr_sjs_0$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; assign fabric_v_f_wr_sjs_0$DEQ = WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; // submodule fabric_v_f_wr_sjs_1 always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: fabric_v_f_wr_sjs_1$D_IN = 2'd0; WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: fabric_v_f_wr_sjs_1$D_IN = 2'd1; WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: fabric_v_f_wr_sjs_1$D_IN = 2'd2; default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; endcase end assign fabric_v_f_wr_sjs_1$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; assign fabric_v_f_wr_sjs_1$DEQ = WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_rd_addr assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = { v_from_masters_0_arid, v_from_masters_0_araddr, v_from_masters_0_arlen, v_from_masters_0_arsize, v_from_masters_0_arburst, v_from_masters_0_arlock, v_from_masters_0_arcache, v_from_masters_0_arprot, v_from_masters_0_arqos, v_from_masters_0_arregion } ; assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = v_from_masters_0_arvalid && fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_rd_data always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; default: fabric_xactors_from_masters_0_f_rd_data$D_IN = 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign fabric_xactors_from_masters_0_f_rd_data$ENQ = WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; assign fabric_xactors_from_masters_0_f_rd_data$DEQ = v_from_masters_0_rready && fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_wr_addr assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = { v_from_masters_0_awid, v_from_masters_0_awaddr, v_from_masters_0_awlen, v_from_masters_0_awsize, v_from_masters_0_awburst, v_from_masters_0_awlock, v_from_masters_0_awcache, v_from_masters_0_awprot, v_from_masters_0_awqos, v_from_masters_0_awregion } ; assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = v_from_masters_0_awvalid && fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_wr_data assign fabric_xactors_from_masters_0_f_wr_data$D_IN = { v_from_masters_0_wdata, v_from_masters_0_wstrb, v_from_masters_0_wlast } ; assign fabric_xactors_from_masters_0_f_wr_data$ENQ = v_from_masters_0_wvalid && fabric_xactors_from_masters_0_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_0_f_wr_data$DEQ = CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_wr_resp always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: fabric_xactors_from_masters_0_f_wr_resp$D_IN = fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: fabric_xactors_from_masters_0_f_wr_resp$D_IN = fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_wr_resp$D_IN = fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: fabric_xactors_from_masters_0_f_wr_resp$D_IN = MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = 6'b101010 /* unspecified value */ ; endcase end assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = v_from_masters_0_bready && fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_rd_addr assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = { v_from_masters_1_arid, v_from_masters_1_araddr, v_from_masters_1_arlen, v_from_masters_1_arsize, v_from_masters_1_arburst, v_from_masters_1_arlock, v_from_masters_1_arcache, v_from_masters_1_arprot, v_from_masters_1_arqos, v_from_masters_1_arregion } ; assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = v_from_masters_1_arvalid && fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_rd_data always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; default: fabric_xactors_from_masters_1_f_rd_data$D_IN = 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign fabric_xactors_from_masters_1_f_rd_data$ENQ = WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; assign fabric_xactors_from_masters_1_f_rd_data$DEQ = v_from_masters_1_rready && fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_wr_addr assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = { v_from_masters_1_awid, v_from_masters_1_awaddr, v_from_masters_1_awlen, v_from_masters_1_awsize, v_from_masters_1_awburst, v_from_masters_1_awlock, v_from_masters_1_awcache, v_from_masters_1_awprot, v_from_masters_1_awqos, v_from_masters_1_awregion } ; assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = v_from_masters_1_awvalid && fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_wr_data assign fabric_xactors_from_masters_1_f_wr_data$D_IN = { v_from_masters_1_wdata, v_from_masters_1_wstrb, v_from_masters_1_wlast } ; assign fabric_xactors_from_masters_1_f_wr_data$ENQ = v_from_masters_1_wvalid && fabric_xactors_from_masters_1_f_wr_data$FULL_N ; assign fabric_xactors_from_masters_1_f_wr_data$DEQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ; assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_wr_resp always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: fabric_xactors_from_masters_1_f_wr_resp$D_IN = fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: fabric_xactors_from_masters_1_f_wr_resp$D_IN = fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_wr_resp$D_IN = fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: fabric_xactors_from_masters_1_f_wr_resp$D_IN = MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = 6'b101010 /* unspecified value */ ; endcase end assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = v_from_masters_1_bready && fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_0_f_rd_addr assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? fabric_xactors_from_masters_0_f_rd_addr$D_OUT : fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && v_to_slaves_0_arready ; assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_0_f_rd_data assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = { v_to_slaves_0_rid, v_to_slaves_0_rdata, v_to_slaves_0_rresp, v_to_slaves_0_rlast } ; assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = v_to_slaves_0_rvalid && fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_0_f_wr_addr assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? fabric_xactors_from_masters_0_f_wr_addr$D_OUT : fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && v_to_slaves_0_awready ; assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_0_f_wr_data assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && v_to_slaves_0_wready ; assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_0_f_wr_resp assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = v_to_slaves_0_bvalid && fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_1_f_rd_addr assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? fabric_xactors_from_masters_0_f_rd_addr$D_OUT : fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && v_to_slaves_1_arready ; assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_1_f_rd_data assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = { v_to_slaves_1_rid, v_to_slaves_1_rdata, v_to_slaves_1_rresp, v_to_slaves_1_rlast } ; assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = v_to_slaves_1_rvalid && fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_1_f_wr_addr assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? fabric_xactors_from_masters_0_f_wr_addr$D_OUT : fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && v_to_slaves_1_awready ; assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_1_f_wr_data assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && v_to_slaves_1_wready ; assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_1_f_wr_resp assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = v_to_slaves_1_bvalid && fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_2_f_rd_addr assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? fabric_xactors_from_masters_0_f_rd_addr$D_OUT : fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && v_to_slaves_2_arready ; assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_2_f_rd_data assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = { v_to_slaves_2_rid, v_to_slaves_2_rdata, v_to_slaves_2_rresp, v_to_slaves_2_rlast } ; assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = v_to_slaves_2_rvalid && fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_2_f_wr_addr assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? fabric_xactors_from_masters_0_f_wr_addr$D_OUT : fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && v_to_slaves_2_awready ; assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_2_f_wr_data assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? fabric_xactors_from_masters_0_f_wr_data$D_OUT : fabric_xactors_from_masters_1_f_wr_data$D_OUT ; assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && v_to_slaves_2_wready ; assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; // submodule fabric_xactors_to_slaves_2_f_wr_resp assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = v_to_slaves_2_bvalid && fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals assign IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403 = fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ? x1_avValue_rresp__h17353 : fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; assign IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438 = fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ? x1_avValue_rresp__h18002 : fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; assign IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473 = fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ? x1_avValue_rresp__h18641 : fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; assign _dor1fabric_v_f_rd_mis_0$EN_deq = WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; assign _dor1fabric_v_f_rd_mis_1$EN_deq = WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; assign _dor1fabric_v_f_rd_mis_2$EN_deq = WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 = fabric_v_f_wd_tasks_0$EMPTY_N && CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; assign fabric_v_f_wd_tasks_1_i_notEmpty__53_AND_fabri_ETC___d159 = fabric_v_f_wd_tasks_1$EMPTY_N && CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; assign fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 = fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; assign fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 = fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; assign fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 = fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 = fabric_v_rg_r_err_beat_count_0 == fabric_v_f_rd_err_info_0$D_OUT[11:4] ; assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 = fabric_v_rg_r_err_beat_count_1 == fabric_v_f_rd_err_info_1$D_OUT[11:4] ; assign fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 = fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; assign fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 = fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_near_mem_io_addr_lim ; assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291 = fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_near_mem_io_addr_lim ; assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 = fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_near_mem_io_addr_lim ; assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341 = fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < soc_map$m_near_mem_io_addr_lim ; assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 = fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < soc_map$m_plic_addr_lim ; assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 = soc_map$m_near_mem_io_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 = soc_map$m_near_mem_io_addr_base <= fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 = soc_map$m_near_mem_io_addr_base <= fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 = soc_map$m_near_mem_io_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 = soc_map$m_plic_addr_base <= fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289 = soc_map$m_plic_addr_base <= fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339 = soc_map$m_plic_addr_base <= fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 = soc_map$m_plic_addr_base <= fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; assign x1_avValue_rresp__h17353 = (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? 2'b10 : fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; assign x1_avValue_rresp__h18002 = (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? 2'b10 : fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; assign x1_avValue_rresp__h18641 = (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? 2'b10 : fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; assign x__h11377 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; assign x__h11978 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; assign x__h17375 = fabric_v_rg_r_beat_count_0 + 8'd1 ; assign x__h18024 = fabric_v_rg_r_beat_count_1 + 8'd1 ; assign x__h18663 = fabric_v_rg_r_beat_count_2 + 8'd1 ; assign x__h21004 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; assign x__h21386 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; always@(fabric_v_f_wd_tasks_0$D_OUT or fabric_xactors_to_slaves_0_f_wr_data$FULL_N or fabric_xactors_to_slaves_1_f_wr_data$FULL_N or fabric_xactors_to_slaves_2_f_wr_data$FULL_N) begin case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) 2'd0: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = fabric_xactors_to_slaves_0_f_wr_data$FULL_N; 2'd1: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = fabric_xactors_to_slaves_1_f_wr_data$FULL_N; 2'd2: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = fabric_xactors_to_slaves_2_f_wr_data$FULL_N; 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; endcase end always@(fabric_v_f_wd_tasks_1$D_OUT or fabric_xactors_to_slaves_0_f_wr_data$FULL_N or fabric_xactors_to_slaves_1_f_wr_data$FULL_N or fabric_xactors_to_slaves_2_f_wr_data$FULL_N) begin case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) 2'd0: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = fabric_xactors_to_slaves_0_f_wr_data$FULL_N; 2'd1: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = fabric_xactors_to_slaves_1_f_wr_data$FULL_N; 2'd2: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = fabric_xactors_to_slaves_2_f_wr_data$FULL_N; 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; endcase end // handling of inlined registers always@(posedge CLK) begin if (RST_N == `BSV_RESET_VALUE) begin fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; end else begin if (fabric_cfg_verbosity$EN) fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY fabric_cfg_verbosity$D_IN; if (fabric_rg_reset$EN) fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; if (fabric_v_rg_r_beat_count_0$EN) fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY fabric_v_rg_r_beat_count_0$D_IN; if (fabric_v_rg_r_beat_count_1$EN) fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY fabric_v_rg_r_beat_count_1$D_IN; if (fabric_v_rg_r_beat_count_2$EN) fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY fabric_v_rg_r_beat_count_2$D_IN; if (fabric_v_rg_r_err_beat_count_0$EN) fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY fabric_v_rg_r_err_beat_count_0$D_IN; if (fabric_v_rg_r_err_beat_count_1$EN) fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY fabric_v_rg_r_err_beat_count_1$D_IN; if (fabric_v_rg_wd_beat_count_0$EN) fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY fabric_v_rg_wd_beat_count_0$D_IN; if (fabric_v_rg_wd_beat_count_1$EN) fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY fabric_v_rg_wd_beat_count_1$D_IN; end end // synopsys translate_off `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS initial begin fabric_cfg_verbosity = 4'hA; fabric_rg_reset = 1'h0; fabric_v_rg_r_beat_count_0 = 8'hAA; fabric_v_rg_r_beat_count_1 = 8'hAA; fabric_v_rg_r_beat_count_2 = 8'hAA; fabric_v_rg_r_err_beat_count_0 = 8'hAA; fabric_v_rg_r_err_beat_count_1 = 8'hAA; fabric_v_rg_wd_beat_count_0 = 8'hAA; fabric_v_rg_wd_beat_count_1 = 8'hAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on // handling of system tasks // synopsys translate_off always@(negedge CLK) begin #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) begin v__h8466 = $stime; #0; end v__h8460 = v__h8466 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", v__h8460, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) begin v__h8813 = $stime; #0; end v__h8807 = v__h8813 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", v__h8807, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) begin v__h9160 = $stime; #0; end v__h9154 = v__h9160 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", v__h9154, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) begin v__h9570 = $stime; #0; end v__h9564 = v__h9570 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", v__h9564, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) begin v__h9911 = $stime; #0; end v__h9905 = v__h9911 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", v__h9905, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) begin v__h10252 = $stime; #0; end v__h10246 = v__h10252 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", v__h10246, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_cfg_verbosity != 4'd0) begin v__h11228 = $stime; #0; end v__h11222 = v__h11228 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d", v__h11222, $signed(32'd0), fabric_v_f_wd_tasks_0$D_OUT[9:8], fabric_v_rg_wd_beat_count_0, fabric_v_f_wd_tasks_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_cfg_verbosity != 4'd0) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_cfg_verbosity != 4'd0) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_cfg_verbosity != 4'd0 && fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_cfg_verbosity != 4'd0 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_cfg_verbosity != 4'd0) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) begin v__h11475 = $stime; #0; end v__h11469 = v__h11475 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", v__h11469, $signed(32'd0), fabric_v_f_wd_tasks_0$D_OUT[9:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $display(" WLAST not set on final data beat (awlen = %0d)", fabric_v_f_wd_tasks_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 && !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_cfg_verbosity != 4'd0) begin v__h11829 = $stime; #0; end v__h11823 = v__h11829 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d", v__h11823, $signed(32'd1), fabric_v_f_wd_tasks_1$D_OUT[9:8], fabric_v_rg_wd_beat_count_1, fabric_v_f_wd_tasks_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_cfg_verbosity != 4'd0 && fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_cfg_verbosity != 4'd0 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) begin v__h12076 = $stime; #0; end v__h12070 = v__h12076 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", v__h12070, $signed(32'd1), fabric_v_f_wd_tasks_1$D_OUT[9:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $display(" WLAST not set on final data beat (awlen = %0d)", fabric_v_f_wd_tasks_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 && !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) begin v__h12433 = $stime; #0; end v__h12427 = v__h12433 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", v__h12427, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) begin v__h12703 = $stime; #0; end v__h12697 = v__h12703 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", v__h12697, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) begin v__h12973 = $stime; #0; end v__h12967 = v__h12973 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", v__h12967, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) begin v__h13247 = $stime; #0; end v__h13241 = v__h13247 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", v__h13241, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) begin v__h13491 = $stime; #0; end v__h13485 = v__h13491 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", v__h13485, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) begin v__h13735 = $stime; #0; end v__h13729 = v__h13735 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", v__h13729, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && fabric_cfg_verbosity != 4'd0) begin v__h13969 = $stime; #0; end v__h13963 = v__h13969 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", v__h13963, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) begin v__h14179 = $stime; #0; end v__h14173 = v__h14179 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", v__h14173, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) begin v__h14579 = $stime; #0; end v__h14573 = v__h14579 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", v__h14573, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) begin v__h14913 = $stime; #0; end v__h14907 = v__h14913 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", v__h14907, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) begin v__h15247 = $stime; #0; end v__h15241 = v__h15247 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", v__h15241, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) begin v__h15635 = $stime; #0; end v__h15629 = v__h15635 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", v__h15629, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) begin v__h15945 = $stime; #0; end v__h15939 = v__h15945 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", v__h15939, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) begin v__h16255 = $stime; #0; end v__h16249 = v__h16255 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", v__h16249, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin v__h17211 = $stime; #0; end v__h17205 = v__h17211 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", v__h17205, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $display(" RLAST not set on final data beat (arlen = %0d)", fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) begin v__h17492 = $stime; #0; end v__h17486 = v__h17492 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", v__h17486, $signed(32'd0), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin v__h17860 = $stime; #0; end v__h17854 = v__h17860 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", v__h17854, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $display(" RLAST not set on final data beat (arlen = %0d)", fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) begin v__h18131 = $stime; #0; end v__h18125 = v__h18131 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", v__h18125, $signed(32'd0), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin v__h18499 = $stime; #0; end v__h18493 = v__h18499 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", v__h18493, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $display(" RLAST not set on final data beat (arlen = %0d)", fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) begin v__h18770 = $stime; #0; end v__h18764 = v__h18770 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", v__h18764, $signed(32'd0), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) begin v__h19118 = $stime; #0; end v__h19112 = v__h19118 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", v__h19112, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $display(" RLAST not set on final data beat (arlen = %0d)", fabric_v_f_rd_mis_0$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) begin v__h19399 = $stime; #0; end v__h19393 = v__h19399 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", v__h19393, $signed(32'd1), $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0 && fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0 && !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) begin v__h19722 = $stime; #0; end v__h19716 = v__h19722 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", v__h19716, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $display(" RLAST not set on final data beat (arlen = %0d)", fabric_v_f_rd_mis_1$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) begin v__h19993 = $stime; #0; end v__h19987 = v__h19993 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", v__h19987, $signed(32'd1), $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0 && fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0 && !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) begin v__h20316 = $stime; #0; end v__h20310 = v__h20316 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", v__h20310, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $display(" RLAST not set on final data beat (arlen = %0d)", fabric_v_f_rd_mis_2$D_OUT[7:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 2'b10); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) begin v__h20587 = $stime; #0; end v__h20581 = v__h20587 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", v__h20581, $signed(32'd1), $signed(32'd2)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0 && fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0 && !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0) begin v__h21067 = $stime; #0; end v__h21061 = v__h21067 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", v__h21061, $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0 && fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0 && !fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) begin v__h21449 = $stime; #0; end v__h21443 = v__h21449 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", v__h21443, $signed(32'd1)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(" r: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 64'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 2'b11); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0 && fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0 && !fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && fabric_cfg_verbosity != 4'd0) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0) begin v__h5786 = $stime; #0; end v__h5780 = v__h5786 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0) $display("%0d: %m.rl_reset", v__h5780); end // synopsys translate_on endmodule // mkFabric_2x3

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_MS__SDFRTN_1_V `define SKY130_FD_SC_MS__SDFRTN_1_V /** * sdfrtn: Scan delay flop, inverted reset, inverted clock, * single output. * * Verilog wrapper for sdfrtn with size of 1 units. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_ms__sdfrtn.v" `ifdef USE_POWER_PINS /*********************************************************/ `celldefine module sky130_fd_sc_ms__sdfrtn_1 ( Q , CLK_N , D , SCD , SCE , RESET_B, VPWR , VGND , VPB , VNB ); output Q ; input CLK_N ; input D ; input SCD ; input SCE ; input RESET_B; input VPWR ; input VGND ; input VPB ; input VNB ; sky130_fd_sc_ms__sdfrtn base ( .Q(Q), .CLK_N(CLK_N), .D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule `endcelldefine /*********************************************************/ `else // If not USE_POWER_PINS /*********************************************************/ `celldefine module sky130_fd_sc_ms__sdfrtn_1 ( Q , CLK_N , D , SCD , SCE , RESET_B ); output Q ; input CLK_N ; input D ; input SCD ; input SCE ; input RESET_B; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; sky130_fd_sc_ms__sdfrtn base ( .Q(Q), .CLK_N(CLK_N), .D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B) ); endmodule `endcelldefine /*********************************************************/ `endif // USE_POWER_PINS `default_nettype wire `endif // SKY130_FD_SC_MS__SDFRTN_1_V

/****************************************************************************** This Source Code Form is subject to the terms of the Open Hardware Description License, v. 1.0. If a copy of the OHDL was not distributed with this file, You can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt Description: Branch prediction module Generates a predicted flag output and compares that to the real flag when it comes back in the following pipeline stage. Signals are deliberately not named after the pipeline stage they belong to, in order to keep this module generic. Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Copyright (C) 2016 Alexey Baturo <baturo.alexey@gmail.com> ******************************************************************************/ `include "mor1kx-defines.v" module mor1kx_branch_prediction #( parameter FEATURE_BRANCH_PREDICTOR = "NONE" ) ( input clk, input rst, // Signals belonging to the stage where the branch is predicted. input op_bf_i, // from decode stage, brn is bf input op_bnf_i, // from decode stage, brn is bnf input [9:0] immjbr_upper_i, // from decode stage, imm output predicted_flag_o, // to decode-execute stage, flag we predict to be // Signals belonging to the stage where the branch is resolved. input prev_op_brcond_i, // from decode-execute stage, prev brn was cond input prev_predicted_flag_i, // from decode-execute, prev predicted flag input flag_i, // from execute-ctrl stage, real flag we got input padv_decode_i, // is decode stage stalled input execute_bf_i, // prev insn was bf input execute_bnf_i, // prev insn was bnf // Branch misprediction indicator output branch_mispredict_o // to decode-execute stage, was brn mispredicted or not ); // Compare the real flag with the previously predicted flag and signal a // misprediction in case of a mismatch. assign branch_mispredict_o = prev_op_brcond_i & (flag_i != prev_predicted_flag_i); generate if (FEATURE_BRANCH_PREDICTOR=="SAT_COUNTER") begin : branch_predictor_saturation_counter mor1kx_branch_predictor_saturation_counter mor1kx_branch_predictor_saturation_counter ( // Outputs .predicted_flag_o (predicted_flag_o), // Inputs .clk (clk), .rst (rst), .flag_i (flag_i), .execute_op_bf_i (execute_bf_i), .execute_op_bnf_i (execute_bnf_i), .op_bf_i (op_bf_i), .op_bnf_i (op_bnf_i), .prev_op_brcond_i (prev_op_brcond_i), .branch_mispredict_i (branch_mispredict_o)); end else if (FEATURE_BRANCH_PREDICTOR=="SIMPLE") begin : branch_predictor_simple mor1kx_branch_predictor_simple mor1kx_branch_predictor_simple ( // Outputs .predicted_flag_o (predicted_flag_o), // Inputs .op_bf_i (op_bf_i), .op_bnf_i (op_bnf_i), .immjbr_upper_i (immjbr_upper_i)); end else begin initial begin $display("Error: FEATURE_PREDICTOR_TYPE, %s, not valid", FEATURE_BRANCH_PREDICTOR); $finish(); end end endgenerate endmodule

module fir_inj (x_in,clk,y,p_desc0_p_O_FD,p_desc1_p_O_FD,p_desc2_p_O_FD,p_desc3_p_O_FD,p_desc4_p_O_FD,p_desc5_p_O_FD,p_desc6_p_O_FD,p_desc7_p_O_FD,p_desc8_p_O_FD,p_desc9_p_O_FD,p_desc10_p_O_FD,p_desc11_p_O_FD,p_desc12_p_O_FD,p_desc13_p_O_FD,p_desc14_p_O_FD,p_desc15_p_O_FD,p_desc16_p_O_FD,p_desc17_p_O_FD,p_desc18_p_O_FD,p_desc19_p_O_FD,p_desc20_p_O_FD,p_desc21_p_O_FD,p_desc22_p_O_FD,p_desc23_p_O_FD,p_desc24_p_O_FD,p_desc25_p_O_FD,p_desc26_p_O_FD,p_desc27_p_O_FD,p_desc28_p_O_FD,p_desc29_p_O_FD,p_desc30_p_O_FD,p_desc31_p_O_FD,p_desc32_p_O_FD,p_x_14_pipe_0_Z_p_O_FD,p_x_14_pipe_9_Z_p_O_FD,p_x_14_pipe_10_Z_p_O_FD,p_x_14_pipe_11_Z_p_O_FD,p_x_14_pipe_12_Z_p_O_FD,p_x_14_pipe_13_Z_p_O_FD,p_x_14_pipe_14_Z_p_O_FD,p_x_14_pipe_15_Z_p_O_FD,p_x_14_pipe_16_Z_p_O_FD,p_x_14_pipe_17_Z_p_O_FD,p_x_9_pipe_1_Z_p_O_FD,p_x_9_pipe_2_Z_p_O_FD,p_x_9_pipe_3_Z_p_O_FD,p_x_9_pipe_4_Z_p_O_FD,p_x_9_pipe_5_Z_p_O_FD,p_x_9_pipe_6_Z_p_O_FD,p_x_9_pipe_7_Z_p_O_FD,p_x_9_pipe_8_Z_p_O_FD,p_x_15_pipe_0_0_15_Z_p_O_FD,p_x_15_pipe_0_0_16_Z_p_O_FD,p_x_15_pipe_0_0_17_Z_p_O_FD,p_x_15_pipe_0_0_18_Z_p_O_FD,p_x_15_pipe_0_0_19_Z_p_O_FD,p_x_15_pipe_0_0_20_Z_p_O_FD,p_x_15_pipe_0_0_21_Z_p_O_FD,p_x_15_pipe_0_0_22_Z_p_O_FD,p_x_15_pipe_0_0_23_Z_p_O_FD,p_x_15_pipe_0_0_24_Z_p_O_FD,p_x_15_pipe_0_0_25_Z_p_O_FD,p_x_15_pipe_0_0_26_Z_p_O_FD,p_x_15_pipe_0_0_27_Z_p_O_FD,p_x_15_pipe_0_0_28_Z_p_O_FD,p_x_15_pipe_0_0_29_Z_p_O_FD,p_x_16_pipe_0_0_0_Z_p_O_FD,p_x_16_pipe_0_0_1_Z_p_O_FD,p_x_16_pipe_0_0_2_Z_p_O_FD,p_x_16_pipe_0_0_3_Z_p_O_FD,p_x_16_pipe_0_0_4_Z_p_O_FD,p_x_16_pipe_0_0_5_Z_p_O_FD,p_x_16_pipe_0_0_6_Z_p_O_FD,p_x_16_pipe_0_0_7_Z_p_O_FD,p_x_16_pipe_0_0_8_Z_p_O_FD,p_x_16_pipe_0_0_9_Z_p_O_FD,p_x_16_pipe_0_0_10_Z_p_O_FD,p_x_16_pipe_0_0_11_Z_p_O_FD,p_x_16_pipe_0_0_12_Z_p_O_FD,p_x_16_pipe_0_0_13_Z_p_O_FD,p_x_16_pipe_0_0_14_Z_p_O_FD,p_desc33_p_O_FD,p_desc34_p_O_FD,p_desc35_p_O_FD,p_desc36_p_O_FD,p_desc37_p_O_FD,p_desc38_p_O_FD,p_desc39_p_O_FD,p_desc40_p_O_FD,p_desc41_p_O_FD,p_desc42_p_O_FD,p_desc43_p_O_FD,p_desc44_p_O_FD,p_desc45_p_O_FD,p_desc46_p_O_FD,p_desc47_p_O_FD,p_desc48_p_O_FD,p_desc49_p_O_FD,p_desc50_p_O_FD,p_desc51_p_O_FD,p_desc52_p_O_FD,p_desc53_p_O_FD,p_desc54_p_O_FD,p_desc55_p_O_FD,p_desc56_p_O_FD); input [7:0] x_in ; input clk ; output [7:0] y ; wire clk ; wire [7:0] x_0 ; wire [15:4] un1_x_1 ; wire [15:5] un1_x_2 ; wire [15:4] un1_x_3 ; wire [7:0] x_4 ; wire [15:2] un1_x_4 ; wire [14:0] un84_sop_0_0_0_0_5 ; wire [7:0] x_7 ; wire [7:0] x_8 ; wire x_9 ; wire [7:0] x_12 ; wire [7:0] x_13 ; wire [9:0] un84_sop_0_0_0_0_0 ; wire [9:0] un84_sop_0_0_0_0_1 ; wire [15:4] un1_x_14_0_0 ; wire [15:5] un1_x_13_0_0 ; wire [15:4] un1_x_12_0_0 ; wire [14:7] un1_x_11_0_0 ; wire [14:0] un84_sop_0_0_0_10_0 ; wire [15:8] un1_x_10_0_0 ; wire [15:5] un1_x_9_0 ; wire [15:4] un1_x_8_0 ; wire [15:2] un1_x_7_0 ; wire [15:1] un1_x_6_0 ; wire [14:0] un84_sop_0_0_0_5_0 ; wire [47:11] P_uc ; wire [29:0] ACOUT ; wire [3:0] CARRYOUT ; wire [47:0] PCOUT ; wire [47:11] P_uc_0 ; wire [29:0] ACOUT_0 ; wire [3:0] CARRYOUT_0 ; wire [47:0] PCOUT_0 ; wire [47:11] P_uc_1 ; wire [29:0] ACOUT_1 ; wire [17:0] BCOUT_1 ; wire [3:0] CARRYOUT_1 ; wire [47:0] PCOUT_1 ; wire [47:12] P_uc_2 ; wire [29:0] ACOUT_2 ; wire [3:0] CARRYOUT_2 ; wire [47:0] PCOUT_2 ; wire [47:12] P_uc_3 ; wire [29:0] ACOUT_3 ; wire [3:0] CARRYOUT_3 ; wire [47:0] PCOUT_3 ; wire [47:12] P_uc_4 ; wire [29:0] ACOUT_4 ; wire [3:0] CARRYOUT_4 ; wire [47:0] PCOUT_4 ; wire [47:12] P_uc_5 ; wire [29:0] ACOUT_5 ; wire [3:0] CARRYOUT_5 ; wire [47:0] PCOUT_5 ; wire [47:12] P_uc_6 ; wire [29:0] ACOUT_6 ; wire [3:0] CARRYOUT_6 ; wire [47:0] PCOUT_6 ; wire [47:14] P_uc_7 ; wire [29:0] ACOUT_7 ; wire [3:0] CARRYOUT_7 ; wire [47:0] PCOUT_7 ; wire [47:14] P_uc_8 ; wire [29:0] ACOUT_8 ; wire [3:0] CARRYOUT_8 ; wire [47:0] PCOUT_8 ; wire [47:15] P_uc_9 ; wire [29:0] ACOUT_9 ; wire [17:0] BCOUT_9 ; wire [3:0] CARRYOUT_9 ; wire [47:0] PCOUT_9 ; wire [7:0] x_10_0 ; wire [7:7] x_10_1 ; wire [7:7] x_10_2 ; wire [7:7] x_10_3 ; wire [7:7] x_10_4 ; wire [7:7] x_10_5 ; wire [7:7] x_10_6 ; wire [7:7] x_10_7 ; wire [7:7] x_10_8 ; wire [7:7] x_10_9 ; wire [7:7] x_10_10 ; wire [7:0] x_9_0 ; wire [7:7] x_9_1 ; wire [7:7] x_9_2 ; wire [7:7] x_9_3 ; wire [7:7] x_9_4 ; wire [7:7] x_9_5 ; wire [7:7] x_9_6 ; wire [7:7] x_9_7 ; wire [7:7] x_9_8 ; wire [7:7] x_9_9 ; wire [7:7] x_9_10 ; wire [7:0] x_6_0 ; wire [7:7] x_6_1 ; wire [7:7] x_6_2 ; wire [7:7] x_6_3 ; wire [7:7] x_6_4 ; wire [7:7] x_6_5 ; wire [7:7] x_6_6 ; wire [7:7] x_6_7 ; wire [7:7] x_6_8 ; wire [7:7] x_6_9 ; wire [7:7] x_6_10 ; wire [7:0] x_5_0 ; wire [7:7] x_5_1 ; wire [7:7] x_5_2 ; wire [7:7] x_5_3 ; wire [7:7] x_5_4 ; wire [7:7] x_5_5 ; wire [7:7] x_5_6 ; wire [7:7] x_5_7 ; wire [7:7] x_5_8 ; wire [7:7] x_5_9 ; wire [7:7] x_5_10 ; wire [7:0] x_4_0 ; wire [7:7] x_4_1 ; wire [7:7] x_4_2 ; wire [7:7] x_4_3 ; wire [7:7] x_4_4 ; wire [7:7] x_4_5 ; wire [7:7] x_4_6 ; wire [7:7] x_4_7 ; wire [7:7] x_4_8 ; wire [7:7] x_4_9 ; wire [7:7] x_4_10 ; wire [7:0] x_3_0 ; wire [7:7] x_3_1 ; wire [7:7] x_3_2 ; wire [7:7] x_3_3 ; wire [7:7] x_3_4 ; wire [7:7] x_3_5 ; wire [7:7] x_3_6 ; wire [7:7] x_3_7 ; wire [7:7] x_3_8 ; wire [7:7] x_3_9 ; wire [7:7] x_3_10 ; wire [7:0] x_2_0 ; wire [7:7] x_2_1 ; wire [7:7] x_2_2 ; wire [7:7] x_2_3 ; wire [7:7] x_2_4 ; wire [7:7] x_2_5 ; wire [7:7] x_2_6 ; wire [7:7] x_2_7 ; wire [7:7] x_2_8 ; wire [7:7] x_2_9 ; wire [7:7] x_2_10 ; wire [7:0] x_1_0 ; wire [7:7] x_1_1 ; wire [7:7] x_1_2 ; wire [7:7] x_1_3 ; wire [7:7] x_1_4 ; wire [7:7] x_1_5 ; wire [7:7] x_1_6 ; wire [7:7] x_1_7 ; wire [7:7] x_1_8 ; wire [7:7] x_1_9 ; wire [7:7] x_1_10 ; wire [7:0] x_0_0 ; wire [7:7] x_0_1 ; wire [7:7] x_0_2 ; wire [7:7] x_0_3 ; wire [7:7] x_0_4 ; wire [7:7] x_0_5 ; wire [7:7] x_0_6 ; wire [7:7] x_0_7 ; wire [7:7] x_0_8 ; wire [7:7] x_0_9 ; wire [7:7] x_0_10 ; wire [14:3] un84_sop_0_0_0_1_6_8 ; wire [14:0] un84_sop_1_7 ; wire [14:0] un84_sop_0_0_0_0_11_7 ; wire [14:0] un84_sop_1_4 ; wire [10:2] un1_x_10_4 ; wire [14:0] un84_sop_0_0_0_1_6_4 ; wire [14:0] un84_sop_0_0_0_0_11_6 ; wire [14:0] un84_sop_0_0_0_0_8 ; wire [14:0] un84_sop_0_0_0_1_6_6 ; wire [14:0] un84_sop_1_6 ; wire [14:7] un1_x_15_0_0_0 ; wire [14:7] un1_x_11_0_0_0 ; wire [14:7] un1_x_16_0_0_0 ; wire x_12_6_tmp_d_array_0 ; wire x_12_5_tmp_d_array_0 ; wire x_12_4_tmp_d_array_0 ; wire x_12_3_tmp_d_array_0 ; wire x_12_2_tmp_d_array_0 ; wire x_12_1_tmp_d_array_0 ; wire x_12_0_tmp_d_array_0 ; wire x_12_tmp_d_array_0 ; wire x_7_6_tmp_d_array_0 ; wire x_7_5_tmp_d_array_0 ; wire x_7_4_tmp_d_array_0 ; wire x_7_3_tmp_d_array_0 ; wire x_7_2_tmp_d_array_0 ; wire x_7_1_tmp_d_array_0 ; wire x_7_0_tmp_d_array_0 ; wire x_7_tmp_d_array_0 ; wire x_4_6_tmp_d_array_0 ; wire x_4_5_tmp_d_array_0 ; wire x_4_4_tmp_d_array_0 ; wire x_4_3_tmp_d_array_0 ; wire x_4_2_tmp_d_array_0 ; wire x_4_1_tmp_d_array_0 ; wire x_4_0_tmp_d_array_0 ; wire x_4_tmp_d_array_0 ; wire [4:4] un1_x_14_0_0_0 ; wire [5:5] un1_x_9_0_0 ; wire [4:4] un1_x_3_0 ; wire VCC ; wire GND ; wire un84_sop_1_s_7 ; wire un84_sop_1_s_8 ; wire un84_sop_1_s_9 ; wire un84_sop_1_s_10 ; wire un84_sop_1_s_11 ; wire un84_sop_1_s_12 ; wire un84_sop_1_s_13 ; wire un84_sop_1_s_14 ; wire un1_x_10_s_2_sf ; wire un1_x_10_axb_3 ; wire CARRYCASCOUT ; wire OVERFLOW ; wire MULTSIGNOUT ; wire PATTERNBDETECT ; wire PATTERNDETECT ; wire UNDERFLOW ; wire CARRYCASCOUT_0 ; wire OVERFLOW_0 ; wire MULTSIGNOUT_0 ; wire PATTERNBDETECT_0 ; wire PATTERNDETECT_0 ; wire UNDERFLOW_0 ; wire CARRYCASCOUT_1 ; wire OVERFLOW_1 ; wire MULTSIGNOUT_1 ; wire PATTERNBDETECT_1 ; wire PATTERNDETECT_1 ; wire UNDERFLOW_1 ; wire CARRYCASCOUT_2 ; wire OVERFLOW_2 ; wire MULTSIGNOUT_2 ; wire PATTERNBDETECT_2 ; wire PATTERNDETECT_2 ; wire UNDERFLOW_2 ; wire CARRYCASCOUT_3 ; wire OVERFLOW_3 ; wire MULTSIGNOUT_3 ; wire PATTERNBDETECT_3 ; wire PATTERNDETECT_3 ; wire UNDERFLOW_3 ; wire CARRYCASCOUT_4 ; wire OVERFLOW_4 ; wire MULTSIGNOUT_4 ; wire PATTERNBDETECT_4 ; wire PATTERNDETECT_4 ; wire UNDERFLOW_4 ; wire CARRYCASCOUT_5 ; wire OVERFLOW_5 ; wire MULTSIGNOUT_5 ; wire PATTERNBDETECT_5 ; wire PATTERNDETECT_5 ; wire UNDERFLOW_5 ; wire CARRYCASCOUT_6 ; wire OVERFLOW_6 ; wire MULTSIGNOUT_6 ; wire PATTERNBDETECT_6 ; wire PATTERNDETECT_6 ; wire UNDERFLOW_6 ; wire CARRYCASCOUT_7 ; wire OVERFLOW_7 ; wire MULTSIGNOUT_7 ; wire PATTERNBDETECT_7 ; wire PATTERNDETECT_7 ; wire UNDERFLOW_7 ; wire CARRYCASCOUT_8 ; wire OVERFLOW_8 ; wire MULTSIGNOUT_8 ; wire PATTERNBDETECT_8 ; wire PATTERNDETECT_8 ; wire UNDERFLOW_8 ; wire CARRYCASCOUT_9 ; wire OVERFLOW_9 ; wire MULTSIGNOUT_9 ; wire PATTERNBDETECT_9 ; wire PATTERNDETECT_9 ; wire UNDERFLOW_9 ; wire un84_sop_1_6_0_axb_1_lut6_2_O5 ; wire un84_sop_1_6_0_o5_2 ; wire un84_sop_1_6_0_o5_3 ; wire un84_sop_1_6_0_o5_4 ; wire un84_sop_1_6_0_o5_5 ; wire un84_sop_1_6_0_o5_6 ; wire un84_sop_1_6_0_o5_7 ; wire un84_sop_1_6_0_o5_8 ; wire un84_sop_1_6_0_o5_9 ; wire un84_sop_1_6_0_o5_10 ; wire un84_sop_1_6_0_o5_11 ; wire un84_sop_0_0_0_1_6_8_axb_2_lut6_2_O5 ; wire un84_sop_0_0_0_1_6_8_o5_3 ; wire un84_sop_0_0_0_1_6_8_o5_4 ; wire un84_sop_0_0_0_1_6_8_o5_5 ; wire un84_sop_0_0_0_1_6_8_o5_6 ; wire un84_sop_0_0_0_1_6_8_o5_7 ; wire un84_sop_0_0_0_6_6_0_axb_1_lut6_2_O5 ; wire un84_sop_0_0_0_6_6_0_o5_2 ; wire un84_sop_0_0_0_6_6_0_o5_3 ; wire un84_sop_0_0_0_6_6_0_o5_4 ; wire un84_sop_0_0_0_6_6_0_o5_5 ; wire un84_sop_0_0_0_6_6_0_o5_6 ; wire un84_sop_0_0_0_6_6_0_o5_7 ; wire un84_sop_0_0_0_6_6_0_o5_8 ; wire un84_sop_0_0_0_6_6_0_o5_9 ; wire un84_sop_0_0_0_6_6_0_o5_10 ; wire un84_sop_0_0_0_6_6_0_o5_11 ; wire un84_sop_0_0_0_6_6_0_o5_12 ; wire un84_sop_0_0_0_11_0_o5_2 ; wire un84_sop_0_0_0_11_0_o5_3 ; wire un84_sop_0_0_0_11_0_o5_4 ; wire un84_sop_0_0_0_11_0_o5_5 ; wire un84_sop_0_0_0_11_0_o5_6 ; wire un84_sop_0_0_0_11_0_o5_7 ; wire un84_sop_0_0_0_11_0_o5_8 ; wire un84_sop_0_0_0_11_0_o5_9 ; wire un84_sop_0_0_0_11_0_o5_10 ; wire un84_sop_0_0_0_11_0_o5_11 ; wire un84_sop_0_0_0_11_0_o5_12 ; wire un84_sop_0_0_0_11_6_0_axb_1_lut6_2_O5 ; wire un84_sop_0_0_0_11_6_0_o5_2 ; wire un84_sop_0_0_0_11_6_0_o5_3 ; wire un84_sop_0_0_0_11_6_0_o5_4 ; wire un84_sop_0_0_0_11_6_0_o5_5 ; wire un84_sop_0_0_0_11_6_0_o5_6 ; wire un84_sop_0_0_0_11_6_0_o5_7 ; wire un84_sop_0_0_0_11_6_0_o5_8 ; wire un84_sop_0_0_0_11_6_0_o5_9 ; wire un84_sop_0_0_0_11_6_0_o5_10 ; wire un84_sop_0_0_0_11_6_0_o5_11 ; wire un84_sop_0_0_0_11_6_0_cry_0 ; wire un84_sop_0_0_0_11_6_0_axb_1 ; wire un84_sop_0_0_0_11_6_0_cry_1 ; wire un84_sop_0_0_0_11_6_0_axb_2 ; wire un84_sop_0_0_0_11_6_0_cry_2 ; wire un84_sop_0_0_0_11_6_0_axb_3 ; wire un84_sop_0_0_0_11_6_0_cry_3 ; wire un84_sop_0_0_0_11_6_0_axb_4 ; wire un84_sop_0_0_0_11_6_0_cry_4 ; wire un84_sop_0_0_0_11_6_0_axb_5 ; wire un84_sop_0_0_0_11_6_0_cry_5 ; wire un84_sop_0_0_0_11_6_0_axb_6 ; wire un84_sop_0_0_0_11_6_0_cry_6 ; wire un84_sop_0_0_0_11_6_0_axb_7 ; wire un84_sop_0_0_0_11_6_0_cry_7 ; wire un84_sop_0_0_0_11_6_0_axb_8 ; wire un84_sop_0_0_0_11_6_0_cry_8 ; wire un84_sop_0_0_0_11_6_0_axb_9 ; wire un84_sop_0_0_0_11_6_0_cry_9 ; wire un84_sop_0_0_0_11_6_0_axb_10 ; wire un84_sop_0_0_0_11_6_0_cry_10 ; wire un84_sop_0_0_0_11_6_0_axb_11 ; wire un84_sop_0_0_0_11_6_0_cry_11 ; wire un84_sop_0_0_0_11_6_0_axb_12 ; wire un84_sop_0_0_0_11_6_0_cry_12 ; wire un84_sop_0_0_0_11_6_0_axb_13 ; wire un84_sop_0_0_0_11_0_axb_0 ; wire un84_sop_0_0_0_11_0_cry_0 ; wire un84_sop_0_0_0_11_0_axb_1 ; wire un84_sop_0_0_0_11_0_cry_1 ; wire un84_sop_0_0_0_11_0_cry_2_RNO ; wire un84_sop_0_0_0_11_0_axb_2 ; wire un84_sop_0_0_0_11_0_cry_2 ; wire un84_sop_0_0_0_11_0_axb_3 ; wire un84_sop_0_0_0_11_0_cry_3 ; wire un84_sop_0_0_0_11_0_axb_4 ; wire un84_sop_0_0_0_11_0_cry_4 ; wire un84_sop_0_0_0_11_0_axb_5 ; wire un84_sop_0_0_0_11_0_cry_5 ; wire un84_sop_0_0_0_11_0_axb_6 ; wire un84_sop_0_0_0_11_0_cry_6 ; wire un84_sop_0_0_0_11_0_axb_7 ; wire un84_sop_0_0_0_11_0_cry_7 ; wire un84_sop_0_0_0_11_0_axb_8 ; wire un84_sop_0_0_0_11_0_cry_8 ; wire un84_sop_0_0_0_11_0_axb_9 ; wire un84_sop_0_0_0_11_0_cry_9 ; wire un84_sop_0_0_0_11_0_axb_10 ; wire un84_sop_0_0_0_11_0_cry_10 ; wire un84_sop_0_0_0_11_0_axb_11 ; wire un84_sop_0_0_0_11_0_cry_11 ; wire un84_sop_0_0_0_11_0_axb_12 ; wire un84_sop_0_0_0_11_0_cry_12 ; wire un84_sop_0_0_0_11_0_axb_13 ; wire un84_sop_0_0_0_11_0_cry_13 ; wire un84_sop_0_0_0_11_0_axb_14 ; wire un84_sop_0_0_0_6_6_0_cry_0 ; wire un84_sop_0_0_0_6_6_0_axb_1 ; wire un84_sop_0_0_0_6_6_0_cry_1 ; wire un84_sop_0_0_0_6_6_0_axb_2 ; wire un84_sop_0_0_0_6_6_0_cry_2 ; wire un84_sop_0_0_0_6_6_0_axb_3 ; wire un84_sop_0_0_0_6_6_0_cry_3 ; wire un84_sop_0_0_0_6_6_0_axb_4 ; wire un84_sop_0_0_0_6_6_0_cry_4 ; wire un84_sop_0_0_0_6_6_0_axb_5 ; wire un84_sop_0_0_0_6_6_0_cry_5 ; wire un84_sop_0_0_0_6_6_0_axb_6 ; wire un84_sop_0_0_0_6_6_0_cry_6 ; wire un84_sop_0_0_0_6_6_0_axb_7 ; wire un84_sop_0_0_0_6_6_0_cry_7 ; wire un84_sop_0_0_0_6_6_0_axb_8 ; wire un84_sop_0_0_0_6_6_0_cry_8 ; wire un84_sop_0_0_0_6_6_0_axb_9 ; wire un84_sop_0_0_0_6_6_0_cry_9 ; wire un84_sop_0_0_0_6_6_0_axb_10 ; wire un84_sop_0_0_0_6_6_0_cry_10 ; wire un84_sop_0_0_0_6_6_0_axb_11 ; wire un84_sop_0_0_0_6_6_0_cry_11 ; wire un84_sop_0_0_0_6_6_0_axb_12 ; wire un84_sop_0_0_0_6_6_0_cry_12 ; wire un84_sop_0_0_0_6_6_0_axb_13 ; wire un84_sop_0_0_0_6_6_0_cry_13 ; wire un84_sop_0_0_0_6_6_0_axb_14 ; wire un84_sop_0_0_0_1_6_8_cry_0 ; wire un84_sop_0_0_0_1_6_8_axb_1 ; wire un84_sop_0_0_0_1_6_8_cry_1 ; wire un84_sop_0_0_0_1_6_8_axb_2 ; wire un84_sop_0_0_0_1_6_8_cry_2 ; wire un84_sop_0_0_0_1_6_8_axb_3 ; wire un84_sop_0_0_0_1_6_8_cry_3 ; wire un84_sop_0_0_0_1_6_8_axb_4 ; wire un84_sop_0_0_0_1_6_8_cry_4 ; wire un84_sop_0_0_0_1_6_8_axb_5 ; wire un84_sop_0_0_0_1_6_8_cry_5 ; wire un84_sop_0_0_0_1_6_8_axb_6 ; wire un84_sop_0_0_0_1_6_8_cry_6 ; wire un84_sop_0_0_0_1_6_8_axb_7 ; wire un84_sop_0_0_0_1_6_8_cry_7 ; wire un84_sop_0_0_0_1_6_8_axb_8 ; wire un84_sop_0_0_0_1_6_8_cry_8 ; wire un84_sop_0_0_0_1_6_8_axb_9 ; wire un84_sop_0_0_0_1_6_8_cry_9 ; wire un84_sop_0_0_0_1_6_8_axb_10 ; wire un84_sop_0_0_0_1_6_8_cry_10 ; wire un84_sop_0_0_0_1_6_8_axb_11 ; wire un84_sop_1_6_0_cry_0 ; wire un84_sop_1_6_0_axb_1 ; wire un84_sop_1_6_0_cry_1 ; wire un84_sop_1_6_0_axb_2 ; wire un84_sop_1_6_0_cry_2 ; wire un84_sop_1_6_0_axb_3 ; wire un84_sop_1_6_0_cry_3 ; wire un84_sop_1_6_0_axb_4 ; wire un84_sop_1_6_0_cry_4 ; wire un84_sop_1_6_0_axb_5 ; wire un84_sop_1_6_0_cry_5 ; wire un84_sop_1_6_0_axb_6 ; wire un84_sop_1_6_0_cry_6 ; wire un84_sop_1_6_0_axb_7 ; wire un84_sop_1_6_0_cry_7 ; wire un84_sop_1_6_0_axb_8 ; wire un84_sop_1_6_0_cry_8 ; wire un84_sop_1_6_0_axb_9 ; wire un84_sop_1_6_0_cry_9 ; wire un84_sop_1_6_0_axb_10 ; wire un84_sop_1_6_0_cry_10 ; wire un84_sop_1_6_0_axb_11 ; wire un84_sop_1_6_0_cry_11 ; wire un84_sop_1_6_0_axb_12 ; wire un84_sop_1_6_0_cry_12 ; wire un84_sop_1_6_0_axb_13 ; wire un1_x_10_cry_3 ; wire un1_x_10_axb_4 ; wire un1_x_10_cry_4 ; wire un1_x_10_axb_5 ; wire un1_x_10_cry_5 ; wire un1_x_10_axb_6 ; wire un1_x_10_cry_6 ; wire un1_x_10_axb_7 ; wire un1_x_10_cry_7 ; wire un1_x_10_axb_8 ; wire un1_x_10_cry_8 ; wire un1_x_10_axb_9 ; wire un1_x_10_cry_9 ; wire un1_x_10_axb_10 ; wire un1_x_10_cry_10 ; wire un1_x_10_axb_11 ; wire un84_sop_0_0_0_1_6_4_cry_0 ; wire un84_sop_0_0_0_1_6_4_axb_1 ; wire un84_sop_0_0_0_1_6_4_cry_1 ; wire un84_sop_0_0_0_1_6_4_axb_2 ; wire un84_sop_0_0_0_1_6_4_cry_2 ; wire un84_sop_0_0_0_1_6_4_axb_3 ; wire un84_sop_0_0_0_1_6_4_cry_3 ; wire un84_sop_0_0_0_1_6_4_axb_4 ; wire un84_sop_0_0_0_1_6_4_cry_4 ; wire un84_sop_0_0_0_1_6_4_axb_5 ; wire un84_sop_0_0_0_1_6_4_cry_5 ; wire un84_sop_0_0_0_1_6_4_axb_6 ; wire un84_sop_0_0_0_1_6_4_cry_6 ; wire un84_sop_0_0_0_1_6_4_axb_7 ; wire un84_sop_0_0_0_1_6_4_cry_7 ; wire un84_sop_0_0_0_1_6_4_axb_8 ; wire un84_sop_0_0_0_1_6_4_cry_8 ; wire un84_sop_0_0_0_1_6_4_axb_9 ; wire un84_sop_0_0_0_1_6_4_cry_9 ; wire un84_sop_0_0_0_1_6_4_axb_10 ; wire un84_sop_0_0_0_1_6_4_cry_10 ; wire un84_sop_0_0_0_1_6_4_axb_11 ; wire un84_sop_0_0_0_1_6_4_cry_11 ; wire un84_sop_0_0_0_1_6_4_axb_12 ; wire un84_sop_0_0_0_1_6_4_cry_12 ; wire un84_sop_0_0_0_1_6_4_axb_13 ; wire un84_sop_0_0_0_1_6_4_cry_13 ; wire un84_sop_0_0_0_1_6_4_axb_14 ; wire un84_sop_0_0_0_1_6_cry_0 ; wire un84_sop_0_0_0_1_6_axb_1 ; wire un84_sop_0_0_0_1_6_cry_1 ; wire un84_sop_0_0_0_1_6_axb_2 ; wire un84_sop_0_0_0_1_6_cry_2 ; wire un84_sop_0_0_0_1_6_axb_3 ; wire un84_sop_0_0_0_1_6_cry_3 ; wire un84_sop_0_0_0_1_6_axb_4 ; wire un84_sop_0_0_0_1_6_cry_4 ; wire un84_sop_0_0_0_1_6_axb_5 ; wire un84_sop_0_0_0_1_6_cry_5 ; wire un84_sop_0_0_0_1_6_axb_6 ; wire un84_sop_0_0_0_1_6_cry_6 ; wire un84_sop_0_0_0_1_6_axb_7 ; wire un84_sop_0_0_0_1_6_cry_7 ; wire un84_sop_0_0_0_1_6_axb_8 ; wire un84_sop_0_0_0_1_6_cry_8 ; wire un84_sop_0_0_0_1_6_axb_9 ; wire un84_sop_0_0_0_1_6_cry_9 ; wire un84_sop_0_0_0_1_6_axb_10 ; wire un84_sop_0_0_0_1_6_cry_10 ; wire un84_sop_0_0_0_1_6_axb_11 ; wire un84_sop_0_0_0_1_6_cry_11 ; wire un84_sop_0_0_0_1_6_axb_12 ; wire un84_sop_0_0_0_1_6_cry_12 ; wire un84_sop_0_0_0_1_6_axb_13 ; wire un84_sop_0_0_0_1_6_cry_13 ; wire un84_sop_0_0_0_1_6_axb_14 ; wire un1_x_0_0_c4 ; wire un1_x_10_5_c5 ; wire un84_sop_1_7_cry_0 ; wire un84_sop_1_7_axb_1 ; wire un84_sop_1_7_cry_1 ; wire un84_sop_1_7_axb_2 ; wire un84_sop_1_7_cry_2 ; wire un84_sop_1_7_axb_3 ; wire un84_sop_1_7_cry_3 ; wire un84_sop_1_7_axb_4 ; wire un84_sop_1_7_cry_4 ; wire un84_sop_1_7_axb_5 ; wire un84_sop_1_7_cry_5 ; wire un84_sop_1_7_axb_6 ; wire un84_sop_1_7_cry_6 ; wire un84_sop_1_7_axb_7 ; wire un84_sop_1_7_cry_7 ; wire un84_sop_1_7_axb_8 ; wire un84_sop_1_7_cry_8 ; wire un84_sop_1_7_axb_9 ; wire un84_sop_1_7_cry_9 ; wire un84_sop_1_7_axb_10 ; wire un84_sop_1_7_cry_10 ; wire un84_sop_1_7_axb_11 ; wire un84_sop_1_7_cry_11 ; wire un84_sop_1_7_axb_12 ; wire un84_sop_1_7_cry_12 ; wire un84_sop_1_7_axb_13 ; wire un84_sop_1_7_cry_13 ; wire un84_sop_1_7_axb_14 ; wire un84_sop_0_0_0_0_11_7_cry_0 ; wire un84_sop_0_0_0_0_11_7_axb_1 ; wire un84_sop_0_0_0_0_11_7_cry_1 ; wire un84_sop_0_0_0_0_11_7_axb_2 ; wire un84_sop_0_0_0_0_11_7_cry_2 ; wire un84_sop_0_0_0_0_11_7_axb_3 ; wire un84_sop_0_0_0_0_11_7_cry_3 ; wire un84_sop_0_0_0_0_11_7_axb_4 ; wire un84_sop_0_0_0_0_11_7_cry_4 ; wire un84_sop_0_0_0_0_11_7_axb_5 ; wire un84_sop_0_0_0_0_11_7_cry_5 ; wire un84_sop_0_0_0_0_11_7_axb_6 ; wire un84_sop_0_0_0_0_11_7_cry_6 ; wire un84_sop_0_0_0_0_11_7_axb_7 ; wire un84_sop_0_0_0_0_11_7_cry_7 ; wire un84_sop_0_0_0_0_11_7_axb_8 ; wire un84_sop_0_0_0_0_11_7_cry_8 ; wire un84_sop_0_0_0_0_11_7_axb_9 ; wire un84_sop_0_0_0_0_11_7_cry_9 ; wire un84_sop_0_0_0_0_11_7_axb_10 ; wire un84_sop_1_4_cry_0 ; wire un84_sop_1_4_axb_1 ; wire un84_sop_1_4_cry_1 ; wire un84_sop_1_4_axb_2 ; wire un84_sop_1_4_cry_2 ; wire un84_sop_1_4_axb_3 ; wire un84_sop_1_4_cry_3 ; wire un84_sop_1_4_axb_4 ; wire un84_sop_1_4_cry_4 ; wire un84_sop_1_4_axb_5 ; wire un84_sop_1_4_cry_5 ; wire un84_sop_1_4_axb_6 ; wire un84_sop_1_4_cry_6 ; wire un84_sop_1_4_axb_7 ; wire un84_sop_1_4_cry_7 ; wire un84_sop_1_4_axb_8 ; wire un84_sop_1_4_cry_8 ; wire un84_sop_1_4_axb_9 ; wire un84_sop_1_4_cry_9 ; wire un84_sop_1_4_axb_10 ; wire un84_sop_1_4_cry_10 ; wire un84_sop_1_4_axb_11 ; wire un84_sop_1_4_cry_11 ; wire un84_sop_1_4_axb_12 ; wire un84_sop_1_4_cry_12 ; wire un84_sop_1_4_axb_13 ; wire un84_sop_1_4_cry_13 ; wire un84_sop_1_4_axb_14 ; wire un84_sop_1_axb_0 ; wire un84_sop_1_cry_0 ; wire un84_sop_1_axb_1 ; wire un84_sop_1_cry_1 ; wire un84_sop_1_axb_2 ; wire un84_sop_1_cry_2 ; wire un84_sop_1_axb_3 ; wire un84_sop_1_cry_3 ; wire un84_sop_1_axb_4 ; wire un84_sop_1_cry_4 ; wire un84_sop_1_axb_5 ; wire un84_sop_1_cry_5 ; wire un84_sop_1_axb_6 ; wire un84_sop_1_cry_6 ; wire un84_sop_1_axb_7 ; wire un84_sop_1_cry_7 ; wire un84_sop_1_axb_8 ; wire un84_sop_1_cry_8 ; wire un84_sop_1_axb_9 ; wire un84_sop_1_cry_9 ; wire un84_sop_1_axb_10 ; wire un84_sop_1_cry_10 ; wire un84_sop_1_axb_11 ; wire un84_sop_1_cry_11 ; wire un84_sop_1_axb_12 ; wire un84_sop_1_cry_12 ; wire un84_sop_1_axb_13 ; wire un84_sop_1_cry_13 ; wire un84_sop_1_axb_14 ; wire un1_x_10_4_cry_1 ; wire un1_x_10_4_axb_2 ; wire un1_x_10_4_cry_2 ; wire un1_x_10_4_axb_3 ; wire un1_x_10_4_cry_3 ; wire un1_x_10_4_axb_4 ; wire un1_x_10_4_cry_4 ; wire un1_x_10_4_axb_5 ; wire un1_x_10_4_cry_5 ; wire un1_x_10_4_axb_6 ; wire un1_x_10_4_cry_6 ; wire un1_x_10_4_axb_7 ; wire un1_x_10_4_cry_7 ; wire un1_x_15_0_axb_0 ; wire un1_x_15_0_cry_0 ; wire un1_x_15_0_axb_1 ; wire un1_x_15_0_cry_1 ; wire un1_x_15_0_axb_2 ; wire un1_x_15_0_cry_2 ; wire un1_x_15_0_axb_3 ; wire un1_x_15_0_cry_3 ; wire un1_x_15_0_axb_4 ; wire un1_x_15_0_cry_4 ; wire un1_x_15_0_axb_5 ; wire un1_x_15_0_cry_5 ; wire un1_x_15_0_axb_6 ; wire un1_x_15_0_cry_6 ; wire un1_x_15_0_axb_7 ; wire un1_x_15_0_cry_7 ; wire un1_x_15_0_axb_8 ; wire un1_x_11_0_axb_0 ; wire un1_x_11_0_cry_0 ; wire un1_x_11_0_axb_1 ; wire un1_x_11_0_cry_1 ; wire un1_x_11_0_axb_2 ; wire un1_x_11_0_cry_2 ; wire un1_x_11_0_axb_3 ; wire un1_x_11_0_cry_3 ; wire un1_x_11_0_axb_4 ; wire un1_x_11_0_cry_4 ; wire un1_x_11_0_axb_5 ; wire un1_x_11_0_cry_5 ; wire un1_x_11_0_axb_6 ; wire un1_x_11_0_cry_6 ; wire un1_x_11_0_axb_7 ; wire un1_x_11_0_cry_7 ; wire un1_x_11_0_axb_8 ; wire un1_x_16_0_axb_0 ; wire un1_x_16_0_cry_0 ; wire un1_x_16_0_axb_1 ; wire un1_x_16_0_cry_1 ; wire un1_x_16_0_axb_2 ; wire un1_x_16_0_cry_2 ; wire un1_x_16_0_axb_3 ; wire un1_x_16_0_cry_3 ; wire un1_x_16_0_axb_4 ; wire un1_x_16_0_cry_4 ; wire un1_x_16_0_axb_5 ; wire un1_x_16_0_cry_5 ; wire un1_x_16_0_axb_6 ; wire un1_x_16_0_cry_6 ; wire un1_x_16_0_axb_7 ; wire un1_x_16_0_cry_7 ; wire un1_x_16_0_axb_8 ; wire un84_sop_0_0_0_1_cry_0 ; wire un84_sop_0_0_0_1_axb_1 ; wire un84_sop_0_0_0_1_cry_1 ; wire un84_sop_0_0_0_1_axb_2 ; wire un84_sop_0_0_0_1_cry_2 ; wire un84_sop_0_0_0_1_axb_3 ; wire un84_sop_0_0_0_1_cry_3 ; wire un84_sop_0_0_0_1_axb_4 ; wire un84_sop_0_0_0_1_cry_4 ; wire un84_sop_0_0_0_1_axb_5 ; wire un84_sop_0_0_0_1_cry_5 ; wire un84_sop_0_0_0_1_axb_6 ; wire un84_sop_0_0_0_1_cry_6 ; wire un84_sop_0_0_0_1_axb_7 ; wire un84_sop_0_0_0_1_cry_7 ; wire un84_sop_0_0_0_1_axb_8 ; wire un84_sop_0_0_0_1_cry_8 ; wire un84_sop_0_0_0_1_axb_9 ; wire un1_x_10_4_cry_1_sf ; wire un84_sop_0_0_0_0_11_7_axb_0_ci ; wire un84_sop_0_0_0_11_0_cry_0_cy ; wire un84_sop_0_0_0_11_6_0_cry_0_cy ; wire un84_sop_0_0_0_6_6_0_cry_0_cy ; wire un84_sop_1_6_0_cry_0_cy ; wire un84_sop_0_0_0_6_0_axb_0_0 ; wire un84_sop_0_0_0_6_0_axb_0_1 ; wire un84_sop_1_6_0_axb_0_0 ; wire un1_x_10_4_s_8_false ; wire x_4_x_4_1Q_Q31 ; wire x_4_0_x_4_1Q_Q31 ; wire x_4_1_x_4_1Q_Q31 ; wire x_4_2_x_4_1Q_Q31 ; wire x_4_3_x_4_1Q_Q31 ; wire x_4_4_x_4_1Q_Q31 ; wire x_4_5_x_4_1Q_Q31 ; wire x_4_6_x_4_1Q_Q31 ; wire x_7_x_7_1Q_Q31 ; wire x_7_0_x_7_1Q_Q31 ; wire x_7_1_x_7_1Q_Q31 ; wire x_7_2_x_7_1Q_Q31 ; wire x_7_3_x_7_1Q_Q31 ; wire x_7_4_x_7_1Q_Q31 ; wire x_7_5_x_7_1Q_Q31 ; wire x_7_6_x_7_1Q_Q31 ; wire x_12_x_4_1Q_Q31 ; wire x_12_0_x_4_1Q_Q31 ; wire x_12_1_x_4_1Q_Q31 ; wire x_12_2_x_4_1Q_Q31 ; wire x_12_3_x_4_1Q_Q31 ; wire x_12_4_x_4_1Q_Q31 ; wire x_12_5_x_4_1Q_Q31 ; wire x_12_6_x_7_1Q_Q31 ; input p_desc0_p_O_FD ; input p_desc1_p_O_FD ; input p_desc2_p_O_FD ; input p_desc3_p_O_FD ; input p_desc4_p_O_FD ; input p_desc5_p_O_FD ; input p_desc6_p_O_FD ; input p_desc7_p_O_FD ; input p_desc8_p_O_FD ; input p_desc9_p_O_FD ; input p_desc10_p_O_FD ; input p_desc11_p_O_FD ; input p_desc12_p_O_FD ; input p_desc13_p_O_FD ; input p_desc14_p_O_FD ; input p_desc15_p_O_FD ; input p_desc16_p_O_FD ; input p_desc17_p_O_FD ; input p_desc18_p_O_FD ; input p_desc19_p_O_FD ; input p_desc20_p_O_FD ; input p_desc21_p_O_FD ; input p_desc22_p_O_FD ; input p_desc23_p_O_FD ; input p_desc24_p_O_FD ; input p_desc25_p_O_FD ; input p_desc26_p_O_FD ; input p_desc27_p_O_FD ; input p_desc28_p_O_FD ; input p_desc29_p_O_FD ; input p_desc30_p_O_FD ; input p_desc31_p_O_FD ; input p_desc32_p_O_FD ; input p_x_14_pipe_0_Z_p_O_FD ; input p_x_14_pipe_9_Z_p_O_FD ; input p_x_14_pipe_10_Z_p_O_FD ; input p_x_14_pipe_11_Z_p_O_FD ; input p_x_14_pipe_12_Z_p_O_FD ; input p_x_14_pipe_13_Z_p_O_FD ; input p_x_14_pipe_14_Z_p_O_FD ; input p_x_14_pipe_15_Z_p_O_FD ; input p_x_14_pipe_16_Z_p_O_FD ; input p_x_14_pipe_17_Z_p_O_FD ; input p_x_9_pipe_1_Z_p_O_FD ; input p_x_9_pipe_2_Z_p_O_FD ; input p_x_9_pipe_3_Z_p_O_FD ; input p_x_9_pipe_4_Z_p_O_FD ; input p_x_9_pipe_5_Z_p_O_FD ; input p_x_9_pipe_6_Z_p_O_FD ; input p_x_9_pipe_7_Z_p_O_FD ; input p_x_9_pipe_8_Z_p_O_FD ; input p_x_15_pipe_0_0_15_Z_p_O_FD ; input p_x_15_pipe_0_0_16_Z_p_O_FD ; input p_x_15_pipe_0_0_17_Z_p_O_FD ; input p_x_15_pipe_0_0_18_Z_p_O_FD ; input p_x_15_pipe_0_0_19_Z_p_O_FD ; input p_x_15_pipe_0_0_20_Z_p_O_FD ; input p_x_15_pipe_0_0_21_Z_p_O_FD ; input p_x_15_pipe_0_0_22_Z_p_O_FD ; input p_x_15_pipe_0_0_23_Z_p_O_FD ; input p_x_15_pipe_0_0_24_Z_p_O_FD ; input p_x_15_pipe_0_0_25_Z_p_O_FD ; input p_x_15_pipe_0_0_26_Z_p_O_FD ; input p_x_15_pipe_0_0_27_Z_p_O_FD ; input p_x_15_pipe_0_0_28_Z_p_O_FD ; input p_x_15_pipe_0_0_29_Z_p_O_FD ; input p_x_16_pipe_0_0_0_Z_p_O_FD ; input p_x_16_pipe_0_0_1_Z_p_O_FD ; input p_x_16_pipe_0_0_2_Z_p_O_FD ; input p_x_16_pipe_0_0_3_Z_p_O_FD ; input p_x_16_pipe_0_0_4_Z_p_O_FD ; input p_x_16_pipe_0_0_5_Z_p_O_FD ; input p_x_16_pipe_0_0_6_Z_p_O_FD ; input p_x_16_pipe_0_0_7_Z_p_O_FD ; input p_x_16_pipe_0_0_8_Z_p_O_FD ; input p_x_16_pipe_0_0_9_Z_p_O_FD ; input p_x_16_pipe_0_0_10_Z_p_O_FD ; input p_x_16_pipe_0_0_11_Z_p_O_FD ; input p_x_16_pipe_0_0_12_Z_p_O_FD ; input p_x_16_pipe_0_0_13_Z_p_O_FD ; input p_x_16_pipe_0_0_14_Z_p_O_FD ; input p_desc33_p_O_FD ; input p_desc34_p_O_FD ; input p_desc35_p_O_FD ; input p_desc36_p_O_FD ; input p_desc37_p_O_FD ; input p_desc38_p_O_FD ; input p_desc39_p_O_FD ; input p_desc40_p_O_FD ; input p_desc41_p_O_FD ; input p_desc42_p_O_FD ; input p_desc43_p_O_FD ; input p_desc44_p_O_FD ; input p_desc45_p_O_FD ; input p_desc46_p_O_FD ; input p_desc47_p_O_FD ; input p_desc48_p_O_FD ; input p_desc49_p_O_FD ; input p_desc50_p_O_FD ; input p_desc51_p_O_FD ; input p_desc52_p_O_FD ; input p_desc53_p_O_FD ; input p_desc54_p_O_FD ; input p_desc55_p_O_FD ; input p_desc56_p_O_FD ; // instances GND GND_cZ(.G(GND)); VCC VCC_cZ(.P(VCC)); SRLC32E x_12_6_x_7_1Q(.Q(x_12_6_tmp_d_array_0),.Q31(x_12_6_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_9),.CLK(clk),.CE(VCC)); SRLC32E x_12_5_x_4_1Q(.Q(x_12_5_tmp_d_array_0),.Q31(x_12_5_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[1:1]),.CLK(clk),.CE(VCC)); SRLC32E x_12_4_x_4_1Q(.Q(x_12_4_tmp_d_array_0),.Q31(x_12_4_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[2:2]),.CLK(clk),.CE(VCC)); SRLC32E x_12_3_x_4_1Q(.Q(x_12_3_tmp_d_array_0),.Q31(x_12_3_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[3:3]),.CLK(clk),.CE(VCC)); SRLC32E x_12_2_x_4_1Q(.Q(x_12_2_tmp_d_array_0),.Q31(x_12_2_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[4:4]),.CLK(clk),.CE(VCC)); SRLC32E x_12_1_x_4_1Q(.Q(x_12_1_tmp_d_array_0),.Q31(x_12_1_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[5:5]),.CLK(clk),.CE(VCC)); SRLC32E x_12_0_x_4_1Q(.Q(x_12_0_tmp_d_array_0),.Q31(x_12_0_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[6:6]),.CLK(clk),.CE(VCC)); SRLC32E x_12_x_4_1Q(.Q(x_12_tmp_d_array_0),.Q31(x_12_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[7:7]),.CLK(clk),.CE(VCC)); SRLC32E x_7_6_x_7_1Q(.Q(x_7_6_tmp_d_array_0),.Q31(x_7_6_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[0:0]),.CLK(clk),.CE(VCC)); SRLC32E x_7_5_x_7_1Q(.Q(x_7_5_tmp_d_array_0),.Q31(x_7_5_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[1:1]),.CLK(clk),.CE(VCC)); SRLC32E x_7_4_x_7_1Q(.Q(x_7_4_tmp_d_array_0),.Q31(x_7_4_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[2:2]),.CLK(clk),.CE(VCC)); SRLC32E x_7_3_x_7_1Q(.Q(x_7_3_tmp_d_array_0),.Q31(x_7_3_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[3:3]),.CLK(clk),.CE(VCC)); SRLC32E x_7_2_x_7_1Q(.Q(x_7_2_tmp_d_array_0),.Q31(x_7_2_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[4:4]),.CLK(clk),.CE(VCC)); SRLC32E x_7_1_x_7_1Q(.Q(x_7_1_tmp_d_array_0),.Q31(x_7_1_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[5:5]),.CLK(clk),.CE(VCC)); SRLC32E x_7_0_x_7_1Q(.Q(x_7_0_tmp_d_array_0),.Q31(x_7_0_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[6:6]),.CLK(clk),.CE(VCC)); SRLC32E x_7_x_7_1Q(.Q(x_7_tmp_d_array_0),.Q31(x_7_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[7:7]),.CLK(clk),.CE(VCC)); SRLC32E x_4_6_x_4_1Q(.Q(x_4_6_tmp_d_array_0),.Q31(x_4_6_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[0:0]),.CLK(clk),.CE(VCC)); SRLC32E x_4_5_x_4_1Q(.Q(x_4_5_tmp_d_array_0),.Q31(x_4_5_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[1:1]),.CLK(clk),.CE(VCC)); SRLC32E x_4_4_x_4_1Q(.Q(x_4_4_tmp_d_array_0),.Q31(x_4_4_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[2:2]),.CLK(clk),.CE(VCC)); SRLC32E x_4_3_x_4_1Q(.Q(x_4_3_tmp_d_array_0),.Q31(x_4_3_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[3:3]),.CLK(clk),.CE(VCC)); SRLC32E x_4_2_x_4_1Q(.Q(x_4_2_tmp_d_array_0),.Q31(x_4_2_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[4:4]),.CLK(clk),.CE(VCC)); SRLC32E x_4_1_x_4_1Q(.Q(x_4_1_tmp_d_array_0),.Q31(x_4_1_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[5:5]),.CLK(clk),.CE(VCC)); SRLC32E x_4_0_x_4_1Q(.Q(x_4_0_tmp_d_array_0),.Q31(x_4_0_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[6:6]),.CLK(clk),.CE(VCC)); SRLC32E x_4_x_4_1Q(.Q(x_4_tmp_d_array_0),.Q31(x_4_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[7:7]),.CLK(clk),.CE(VCC)); LUT1 un1_x_10_4_s_8_false_cZ(.I0(GND),.O(un1_x_10_4_s_8_false)); defparam un1_x_10_4_s_8_false_cZ.INIT=2'h0; LUT3 un84_sop_1_6_0_s_0_lut(.I0(un1_x_1[4:4]),.I1(un1_x_2[5:5]),.I2(un1_x_3[4:4]),.O(un84_sop_1_6[0:0])); defparam un84_sop_1_6_0_s_0_lut.INIT=8'h96; LUT3 un84_sop_0_0_0_11_6_0_s_0_lut(.I0(un1_x_12_0_0[4:4]),.I1(un1_x_13_0_0[5:5]),.I2(un1_x_14_0_0[4:4]),.O(un84_sop_0_0_0_0_11_6[0:0])); defparam un84_sop_0_0_0_11_6_0_s_0_lut.INIT=8'h96; LUT3 un84_sop_0_0_0_6_6_0_s_0_lut(.I0(un1_x_7_0[2:2]),.I1(un1_x_8_0[4:4]),.I2(un1_x_9_0[5:5]),.O(un84_sop_0_0_0_1_6_6[0:0])); defparam un84_sop_0_0_0_6_6_0_s_0_lut.INIT=8'h96; LUT2 un84_sop_0_0_0_6_0_axb_0_0_cZ(.I0(un1_x_12_0_0[4:4]),.I1(un1_x_13_0_0[5:5]),.O(un84_sop_0_0_0_6_0_axb_0_0)); defparam un84_sop_0_0_0_6_0_axb_0_0_cZ.INIT=4'h6; LUT3 un84_sop_0_0_0_11_6_0_axb_12_cZ(.I0(un1_x_12_0_0[15:15]),.I1(un1_x_13_0_0[15:15]),.I2(un1_x_14_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_axb_12)); defparam un84_sop_0_0_0_11_6_0_axb_12_cZ.INIT=8'h7E; LUT2 un84_sop_0_0_0_6_0_axb_0_1_cZ(.I0(un1_x_7_0[2:2]),.I1(un1_x_8_0[4:4]),.O(un84_sop_0_0_0_6_0_axb_0_1)); defparam un84_sop_0_0_0_6_0_axb_0_1_cZ.INIT=4'h6; LUT4 un84_sop_0_0_0_6_6_0_axb_12_cZ(.I0(un1_x_7_0[13:13]),.I1(un1_x_7_0[14:14]),.I2(un1_x_8_0[15:15]),.I3(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_12)); defparam un84_sop_0_0_0_6_6_0_axb_12_cZ.INIT=16'h399C; LUT4 un84_sop_0_0_0_6_6_0_axb_13_cZ(.I0(un1_x_7_0[14:14]),.I1(un1_x_7_0[15:15]),.I2(un1_x_8_0[15:15]),.I3(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_13)); defparam un84_sop_0_0_0_6_6_0_axb_13_cZ.INIT=16'h399C; LUT2 un84_sop_0_0_0_1_6_8_axb_0(.I0(un84_sop_0_0_0_10_0[3:3]),.I1(x_4[0:0]),.O(un84_sop_0_0_0_1_6_8[3:3])); defparam un84_sop_0_0_0_1_6_8_axb_0.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_8_axb_1_cZ(.I0(un84_sop_0_0_0_10_0[4:4]),.I1(x_4[1:1]),.O(un84_sop_0_0_0_1_6_8_axb_1)); defparam un84_sop_0_0_0_1_6_8_axb_1_cZ.INIT=4'h6; LUT4 un84_sop_0_0_0_1_6_8_axb_9_cZ(.I0(un84_sop_0_0_0_10_0[11:11]),.I1(un84_sop_0_0_0_10_0[12:12]),.I2(x_4[6:6]),.I3(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_9)); defparam un84_sop_0_0_0_1_6_8_axb_9_cZ.INIT=16'h366C; LUT2 un84_sop_0_0_0_1_6_8_axb_10_cZ(.I0(un84_sop_0_0_0_10_0[13:13]),.I1(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_10)); defparam un84_sop_0_0_0_1_6_8_axb_10_cZ.INIT=4'h6; LUT2 un84_sop_1_6_0_axb_0_0_cZ(.I0(un1_x_1[4:4]),.I1(un1_x_2[5:5]),.O(un84_sop_1_6_0_axb_0_0)); defparam un84_sop_1_6_0_axb_0_0_cZ.INIT=4'h6; LUT3 un84_sop_1_6_0_axb_12_cZ(.I0(un1_x_1[15:15]),.I1(un1_x_2[15:15]),.I2(un1_x_3[15:15]),.O(un84_sop_1_6_0_axb_12)); defparam un84_sop_1_6_0_axb_12_cZ.INIT=8'h7E; LUT3 un1_x_10_axb_4_cZ(.I0(un1_x_10_4[4:4]),.I1(x_8[0:0]),.I2(x_8[1:1]),.O(un1_x_10_axb_4)); defparam un1_x_10_axb_4_cZ.INIT=8'h96; LUT4 un1_x_10_axb_5_cZ(.I0(un1_x_10_4[5:5]),.I1(x_8[0:0]),.I2(x_8[1:1]),.I3(x_8[2:2]),.O(un1_x_10_axb_5)); defparam un1_x_10_axb_5_cZ.INIT=16'hA956; LUT3 un1_x_10_axb_8_cZ(.I0(un1_x_10_4[8:8]),.I1(un1_x_10_5_c5),.I2(x_8[5:5]),.O(un1_x_10_axb_8)); defparam un1_x_10_axb_8_cZ.INIT=8'h69; LUT4 un1_x_10_axb_9_cZ(.I0(un1_x_10_5_c5),.I1(x_8[5:5]),.I2(x_8[6:6]),.I3(x_8[7:7]),.O(un1_x_10_axb_9)); defparam un1_x_10_axb_9_cZ.INIT=16'hD22D; LUT3 un1_x_10_axb_10_cZ(.I0(un1_x_10_5_c5),.I1(x_8[5:5]),.I2(x_8[6:6]),.O(un1_x_10_axb_10)); defparam un1_x_10_axb_10_cZ.INIT=8'hFD; LUT2 un84_sop_0_0_0_1_6_4_axb_0(.I0(un1_x_6_0[1:1]),.I1(un84_sop_0_0_0_10_0[0:0]),.O(un84_sop_0_0_0_1_6_4[0:0])); defparam un84_sop_0_0_0_1_6_4_axb_0.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_4_axb_1_cZ(.I0(un1_x_6_0[2:2]),.I1(un84_sop_0_0_0_10_0[1:1]),.O(un84_sop_0_0_0_1_6_4_axb_1)); defparam un84_sop_0_0_0_1_6_4_axb_1_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_4_axb_2_cZ(.I0(un1_x_6_0[3:3]),.I1(un84_sop_0_0_0_10_0[2:2]),.O(un84_sop_0_0_0_1_6_4_axb_2)); defparam un84_sop_0_0_0_1_6_4_axb_2_cZ.INIT=4'h6; LUT3 un84_sop_0_0_0_1_6_4_axb_3_cZ(.I0(un1_x_6_0[4:4]),.I1(un84_sop_0_0_0_10_0[3:3]),.I2(x_4[0:0]),.O(un84_sop_0_0_0_1_6_4_axb_3)); defparam un84_sop_0_0_0_1_6_4_axb_3_cZ.INIT=8'h96; LUT2 un84_sop_0_0_0_1_6_4_axb_4_cZ(.I0(un1_x_6_0[5:5]),.I1(un84_sop_0_0_0_1_6_8[4:4]),.O(un84_sop_0_0_0_1_6_4_axb_4)); defparam un84_sop_0_0_0_1_6_4_axb_4_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_4_axb_5_cZ(.I0(un1_x_6_0[6:6]),.I1(un84_sop_0_0_0_1_6_8[5:5]),.O(un84_sop_0_0_0_1_6_4_axb_5)); defparam un84_sop_0_0_0_1_6_4_axb_5_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_4_axb_6_cZ(.I0(un1_x_6_0[7:7]),.I1(un84_sop_0_0_0_1_6_8[6:6]),.O(un84_sop_0_0_0_1_6_4_axb_6)); defparam un84_sop_0_0_0_1_6_4_axb_6_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_4_axb_7_cZ(.I0(un1_x_6_0[8:8]),.I1(un84_sop_0_0_0_1_6_8[7:7]),.O(un84_sop_0_0_0_1_6_4_axb_7)); defparam un84_sop_0_0_0_1_6_4_axb_7_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_4_axb_8_cZ(.I0(un1_x_6_0[9:9]),.I1(un84_sop_0_0_0_1_6_8[8:8]),.O(un84_sop_0_0_0_1_6_4_axb_8)); defparam un84_sop_0_0_0_1_6_4_axb_8_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_4_axb_9_cZ(.I0(un1_x_6_0[10:10]),.I1(un84_sop_0_0_0_1_6_8[9:9]),.O(un84_sop_0_0_0_1_6_4_axb_9)); defparam un84_sop_0_0_0_1_6_4_axb_9_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_4_axb_10_cZ(.I0(un1_x_6_0[11:11]),.I1(un84_sop_0_0_0_1_6_8[10:10]),.O(un84_sop_0_0_0_1_6_4_axb_10)); defparam un84_sop_0_0_0_1_6_4_axb_10_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_4_axb_11_cZ(.I0(un1_x_6_0[12:12]),.I1(un84_sop_0_0_0_1_6_8[11:11]),.O(un84_sop_0_0_0_1_6_4_axb_11)); defparam un84_sop_0_0_0_1_6_4_axb_11_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_4_axb_12_cZ(.I0(un1_x_6_0[13:13]),.I1(un84_sop_0_0_0_1_6_8[12:12]),.O(un84_sop_0_0_0_1_6_4_axb_12)); defparam un84_sop_0_0_0_1_6_4_axb_12_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_4_axb_13_cZ(.I0(un1_x_6_0[14:14]),.I1(un84_sop_0_0_0_1_6_8[13:13]),.O(un84_sop_0_0_0_1_6_4_axb_13)); defparam un84_sop_0_0_0_1_6_4_axb_13_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_1_cZ(.I0(un1_x_4[3:3]),.I1(un84_sop_0_0_0_0_5[1:1]),.O(un84_sop_1_7_axb_1)); defparam un84_sop_1_7_axb_1_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_2_cZ(.I0(un1_x_4[4:4]),.I1(un84_sop_0_0_0_0_5[2:2]),.O(un84_sop_1_7_axb_2)); defparam un84_sop_1_7_axb_2_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_3_cZ(.I0(un1_x_4[5:5]),.I1(un84_sop_0_0_0_0_5[3:3]),.O(un84_sop_1_7_axb_3)); defparam un84_sop_1_7_axb_3_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_4_cZ(.I0(un1_x_4[6:6]),.I1(un84_sop_0_0_0_0_5[4:4]),.O(un84_sop_1_7_axb_4)); defparam un84_sop_1_7_axb_4_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_5_cZ(.I0(un1_x_4[7:7]),.I1(un84_sop_0_0_0_0_5[5:5]),.O(un84_sop_1_7_axb_5)); defparam un84_sop_1_7_axb_5_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_6_cZ(.I0(un1_x_4[8:8]),.I1(un84_sop_0_0_0_0_5[6:6]),.O(un84_sop_1_7_axb_6)); defparam un84_sop_1_7_axb_6_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_7_cZ(.I0(un1_x_4[9:9]),.I1(un84_sop_0_0_0_0_5[7:7]),.O(un84_sop_1_7_axb_7)); defparam un84_sop_1_7_axb_7_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_8_cZ(.I0(un1_x_4[10:10]),.I1(un84_sop_0_0_0_0_5[8:8]),.O(un84_sop_1_7_axb_8)); defparam un84_sop_1_7_axb_8_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_9_cZ(.I0(un1_x_4[11:11]),.I1(un84_sop_0_0_0_0_5[9:9]),.O(un84_sop_1_7_axb_9)); defparam un84_sop_1_7_axb_9_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_10_cZ(.I0(un1_x_4[12:12]),.I1(un84_sop_0_0_0_0_5[10:10]),.O(un84_sop_1_7_axb_10)); defparam un84_sop_1_7_axb_10_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_11_cZ(.I0(un1_x_4[13:13]),.I1(un84_sop_0_0_0_0_5[11:11]),.O(un84_sop_1_7_axb_11)); defparam un84_sop_1_7_axb_11_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_12_cZ(.I0(un1_x_4[14:14]),.I1(un84_sop_0_0_0_0_5[12:12]),.O(un84_sop_1_7_axb_12)); defparam un84_sop_1_7_axb_12_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_13_cZ(.I0(un1_x_4[15:15]),.I1(un84_sop_0_0_0_0_5[13:13]),.O(un84_sop_1_7_axb_13)); defparam un84_sop_1_7_axb_13_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_0_11_7_axb_0(.I0(un84_sop_0_0_0_0_0[0:0]),.I1(x_9),.O(un84_sop_0_0_0_0_11_7[0:0])); defparam un84_sop_0_0_0_0_11_7_axb_0.INIT=4'h6; LUT2 un84_sop_0_0_0_0_11_7_axb_1_cZ(.I0(un1_x_11_0_0[7:7]),.I1(un84_sop_0_0_0_0_0[1:1]),.O(un84_sop_0_0_0_0_11_7_axb_1)); defparam un84_sop_0_0_0_0_11_7_axb_1_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_0_11_7_axb_2_cZ(.I0(un1_x_11_0_0[8:8]),.I1(un84_sop_0_0_0_0_0[2:2]),.O(un84_sop_0_0_0_0_11_7_axb_2)); defparam un84_sop_0_0_0_0_11_7_axb_2_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_0_11_7_axb_3_cZ(.I0(un1_x_11_0_0[9:9]),.I1(un84_sop_0_0_0_0_0[3:3]),.O(un84_sop_0_0_0_0_11_7_axb_3)); defparam un84_sop_0_0_0_0_11_7_axb_3_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_0_11_7_axb_4_cZ(.I0(un1_x_11_0_0[10:10]),.I1(un84_sop_0_0_0_0_0[4:4]),.O(un84_sop_0_0_0_0_11_7_axb_4)); defparam un84_sop_0_0_0_0_11_7_axb_4_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_0_11_7_axb_5_cZ(.I0(un1_x_11_0_0[11:11]),.I1(un84_sop_0_0_0_0_0[5:5]),.O(un84_sop_0_0_0_0_11_7_axb_5)); defparam un84_sop_0_0_0_0_11_7_axb_5_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_0_11_7_axb_6_cZ(.I0(un1_x_11_0_0[12:12]),.I1(un84_sop_0_0_0_0_0[6:6]),.O(un84_sop_0_0_0_0_11_7_axb_6)); defparam un84_sop_0_0_0_0_11_7_axb_6_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_0_11_7_axb_7_cZ(.I0(un1_x_11_0_0[13:13]),.I1(un84_sop_0_0_0_0_0[7:7]),.O(un84_sop_0_0_0_0_11_7_axb_7)); defparam un84_sop_0_0_0_0_11_7_axb_7_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_0_11_7_axb_8_cZ(.I0(un1_x_11_0_0[14:14]),.I1(un84_sop_0_0_0_0_0[8:8]),.O(un84_sop_0_0_0_0_11_7_axb_8)); defparam un84_sop_0_0_0_0_11_7_axb_8_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_0_11_7_axb_9_cZ(.I0(un1_x_11_0_0[14:14]),.I1(un84_sop_0_0_0_0_0[9:9]),.O(un84_sop_0_0_0_0_11_7_axb_9)); defparam un84_sop_0_0_0_0_11_7_axb_9_cZ.INIT=4'h6; LUT3 un84_sop_1_4_cry_0_RNO(.I0(un1_x_4[2:2]),.I1(un84_sop_0_0_0_0_5[0:0]),.I2(x_0[0:0]),.O(un84_sop_1_4[0:0])); defparam un84_sop_1_4_cry_0_RNO.INIT=8'h96; LUT3 un84_sop_1_4_axb_1_cZ(.I0(un84_sop_1_7[1:1]),.I1(x_0[0:0]),.I2(x_0[1:1]),.O(un84_sop_1_4_axb_1)); defparam un84_sop_1_4_axb_1_cZ.INIT=8'h96; LUT4 un84_sop_1_4_axb_2_cZ(.I0(un84_sop_1_7[2:2]),.I1(x_0[0:0]),.I2(x_0[1:1]),.I3(x_0[2:2]),.O(un84_sop_1_4_axb_2)); defparam un84_sop_1_4_axb_2_cZ.INIT=16'hA956; LUT4 un84_sop_1_4_axb_5_cZ(.I0(un1_x_0_0_c4),.I1(un84_sop_1_7[5:5]),.I2(x_0[4:4]),.I3(x_0[5:5]),.O(un84_sop_1_4_axb_5)); defparam un84_sop_1_4_axb_5_cZ.INIT=16'hC639; LUT4 un84_sop_1_axb_0_cZ(.I0(un1_x_4[2:2]),.I1(un84_sop_0_0_0_0_5[0:0]),.I2(un84_sop_1_6[0:0]),.I3(x_0[0:0]),.O(un84_sop_1_axb_0)); defparam un84_sop_1_axb_0_cZ.INIT=16'h6996; LUT2 un84_sop_1_axb_1_cZ(.I0(un84_sop_1_4[1:1]),.I1(un84_sop_1_6[1:1]),.O(un84_sop_1_axb_1)); defparam un84_sop_1_axb_1_cZ.INIT=4'h6; LUT2 un84_sop_1_axb_2_cZ(.I0(un84_sop_1_4[2:2]),.I1(un84_sop_1_6[2:2]),.O(un84_sop_1_axb_2)); defparam un84_sop_1_axb_2_cZ.INIT=4'h6; LUT2 un84_sop_1_axb_3_cZ(.I0(un84_sop_1_4[3:3]),.I1(un84_sop_1_6[3:3]),.O(un84_sop_1_axb_3)); defparam un84_sop_1_axb_3_cZ.INIT=4'h6; LUT2 un84_sop_1_axb_4_cZ(.I0(un84_sop_1_4[4:4]),.I1(un84_sop_1_6[4:4]),.O(un84_sop_1_axb_4)); defparam un84_sop_1_axb_4_cZ.INIT=4'h6; LUT2 un84_sop_1_axb_5_cZ(.I0(un84_sop_1_4[5:5]),.I1(un84_sop_1_6[5:5]),.O(un84_sop_1_axb_5)); defparam un84_sop_1_axb_5_cZ.INIT=4'h6; LUT2 un84_sop_1_axb_6_cZ(.I0(un84_sop_1_4[6:6]),.I1(un84_sop_1_6[6:6]),.O(un84_sop_1_axb_6)); defparam un84_sop_1_axb_6_cZ.INIT=4'h6; LUT2 un1_x_10_4_cry_1_RNO(.I0(x_8[0:0]),.I1(x_8[1:1]),.O(un1_x_10_4_cry_1_sf)); defparam un1_x_10_4_cry_1_RNO.INIT=4'h6; LUT2 un1_x_10_4_axb_2_cZ(.I0(x_8[1:1]),.I1(x_8[2:2]),.O(un1_x_10_4_axb_2)); defparam un1_x_10_4_axb_2_cZ.INIT=4'h6; LUT2 un1_x_10_4_axb_3_cZ(.I0(x_8[2:2]),.I1(x_8[3:3]),.O(un1_x_10_4_axb_3)); defparam un1_x_10_4_axb_3_cZ.INIT=4'h6; LUT2 un1_x_10_4_axb_4_cZ(.I0(x_8[3:3]),.I1(x_8[4:4]),.O(un1_x_10_4_axb_4)); defparam un1_x_10_4_axb_4_cZ.INIT=4'h6; LUT2 un1_x_10_4_axb_5_cZ(.I0(x_8[4:4]),.I1(x_8[5:5]),.O(un1_x_10_4_axb_5)); defparam un1_x_10_4_axb_5_cZ.INIT=4'h6; LUT2 un1_x_10_4_axb_6_cZ(.I0(x_8[5:5]),.I1(x_8[6:6]),.O(un1_x_10_4_axb_6)); defparam un1_x_10_4_axb_6_cZ.INIT=4'h6; LUT2 un1_x_10_4_axb_7_cZ(.I0(x_8[6:6]),.I1(x_8[7:7]),.O(un1_x_10_4_axb_7)); defparam un1_x_10_4_axb_7_cZ.INIT=4'h6; LUT1 un1_x_15_0_axb_0_cZ(.I0(x_12[0:0]),.O(un1_x_15_0_axb_0)); defparam un1_x_15_0_axb_0_cZ.INIT=2'h1; LUT1 un1_x_15_0_axb_1_cZ(.I0(x_12[1:1]),.O(un1_x_15_0_axb_1)); defparam un1_x_15_0_axb_1_cZ.INIT=2'h1; LUT1 un1_x_15_0_axb_2_cZ(.I0(x_12[2:2]),.O(un1_x_15_0_axb_2)); defparam un1_x_15_0_axb_2_cZ.INIT=2'h1; LUT1 un1_x_15_0_axb_3_cZ(.I0(x_12[3:3]),.O(un1_x_15_0_axb_3)); defparam un1_x_15_0_axb_3_cZ.INIT=2'h1; LUT1 un1_x_15_0_axb_4_cZ(.I0(x_12[4:4]),.O(un1_x_15_0_axb_4)); defparam un1_x_15_0_axb_4_cZ.INIT=2'h1; LUT1 un1_x_15_0_axb_5_cZ(.I0(x_12[5:5]),.O(un1_x_15_0_axb_5)); defparam un1_x_15_0_axb_5_cZ.INIT=2'h1; LUT1 un1_x_15_0_axb_6_cZ(.I0(x_12[6:6]),.O(un1_x_15_0_axb_6)); defparam un1_x_15_0_axb_6_cZ.INIT=2'h1; LUT1 un1_x_15_0_axb_7_cZ(.I0(x_12[7:7]),.O(un1_x_15_0_axb_7)); defparam un1_x_15_0_axb_7_cZ.INIT=2'h1; LUT1 un1_x_11_0_axb_0_cZ(.I0(x_8[0:0]),.O(un1_x_11_0_axb_0)); defparam un1_x_11_0_axb_0_cZ.INIT=2'h1; LUT1 un1_x_16_0_axb_0_cZ(.I0(x_13[0:0]),.O(un1_x_16_0_axb_0)); defparam un1_x_16_0_axb_0_cZ.INIT=2'h1; LUT1 un1_x_16_0_axb_1_cZ(.I0(x_13[1:1]),.O(un1_x_16_0_axb_1)); defparam un1_x_16_0_axb_1_cZ.INIT=2'h1; LUT1 un1_x_16_0_axb_2_cZ(.I0(x_13[2:2]),.O(un1_x_16_0_axb_2)); defparam un1_x_16_0_axb_2_cZ.INIT=2'h1; LUT1 un1_x_16_0_axb_3_cZ(.I0(x_13[3:3]),.O(un1_x_16_0_axb_3)); defparam un1_x_16_0_axb_3_cZ.INIT=2'h1; LUT1 un1_x_16_0_axb_4_cZ(.I0(x_13[4:4]),.O(un1_x_16_0_axb_4)); defparam un1_x_16_0_axb_4_cZ.INIT=2'h1; LUT1 un1_x_16_0_axb_5_cZ(.I0(x_13[5:5]),.O(un1_x_16_0_axb_5)); defparam un1_x_16_0_axb_5_cZ.INIT=2'h1; LUT1 un1_x_16_0_axb_6_cZ(.I0(x_13[6:6]),.O(un1_x_16_0_axb_6)); defparam un1_x_16_0_axb_6_cZ.INIT=2'h1; LUT1 un1_x_16_0_axb_7_cZ(.I0(x_13[7:7]),.O(un1_x_16_0_axb_7)); defparam un1_x_16_0_axb_7_cZ.INIT=2'h1; LUT2 un84_sop_0_0_0_0_11_7_axb_0_ci_cZ(.I0(un84_sop_0_0_0_0_0[0:0]),.I1(x_9),.O(un84_sop_0_0_0_0_11_7_axb_0_ci)); defparam un84_sop_0_0_0_0_11_7_axb_0_ci_cZ.INIT=4'h6; LUT1 un84_sop_0_0_0_11_6_0_cry_0_thru(.I0(un1_x_14_0_0[4:4]),.O(un1_x_14_0_0_0[4:4])); defparam un84_sop_0_0_0_11_6_0_cry_0_thru.INIT=2'h2; LUT1 un84_sop_0_0_0_6_6_0_cry_0_thru(.I0(un1_x_9_0[5:5]),.O(un1_x_9_0_0[5:5])); defparam un84_sop_0_0_0_6_6_0_cry_0_thru.INIT=2'h2; LUT1 un84_sop_1_6_0_cry_0_thru(.I0(un1_x_3[4:4]),.O(un1_x_3_0[4:4])); defparam un84_sop_1_6_0_cry_0_thru.INIT=2'h2; p_O_FD desc0(.Q(x_0[0:0]),.D(x_in[0:0]),.C(clk),.E(p_desc0_p_O_FD)); p_O_FD desc1(.Q(x_0[1:1]),.D(x_in[1:1]),.C(clk),.E(p_desc1_p_O_FD)); p_O_FD desc2(.Q(x_0[2:2]),.D(x_in[2:2]),.C(clk),.E(p_desc2_p_O_FD)); p_O_FD desc3(.Q(x_0[3:3]),.D(x_in[3:3]),.C(clk),.E(p_desc3_p_O_FD)); p_O_FD desc4(.Q(x_0[4:4]),.D(x_in[4:4]),.C(clk),.E(p_desc4_p_O_FD)); p_O_FD desc5(.Q(x_0[5:5]),.D(x_in[5:5]),.C(clk),.E(p_desc5_p_O_FD)); p_O_FD desc6(.Q(x_0[6:6]),.D(x_in[6:6]),.C(clk),.E(p_desc6_p_O_FD)); p_O_FD desc7(.Q(x_0[7:7]),.D(x_in[7:7]),.C(clk),.E(p_desc7_p_O_FD)); p_O_FD desc8(.Q(y[7:7]),.D(un84_sop_1_s_14),.C(clk),.E(p_desc8_p_O_FD)); p_O_FD desc9(.Q(y[0:0]),.D(un84_sop_1_s_7),.C(clk),.E(p_desc9_p_O_FD)); p_O_FD desc10(.Q(y[1:1]),.D(un84_sop_1_s_8),.C(clk),.E(p_desc10_p_O_FD)); p_O_FD desc11(.Q(y[2:2]),.D(un84_sop_1_s_9),.C(clk),.E(p_desc11_p_O_FD)); p_O_FD desc12(.Q(y[3:3]),.D(un84_sop_1_s_10),.C(clk),.E(p_desc12_p_O_FD)); p_O_FD desc13(.Q(y[4:4]),.D(un84_sop_1_s_11),.C(clk),.E(p_desc13_p_O_FD)); p_O_FD desc14(.Q(y[5:5]),.D(un84_sop_1_s_12),.C(clk),.E(p_desc14_p_O_FD)); p_O_FD desc15(.Q(y[6:6]),.D(un84_sop_1_s_13),.C(clk),.E(p_desc15_p_O_FD)); p_O_FD desc16(.Q(x_8[7:7]),.D(x_7[7:7]),.C(clk),.E(p_desc16_p_O_FD)); p_O_FD desc17(.Q(x_8[6:6]),.D(x_7[6:6]),.C(clk),.E(p_desc17_p_O_FD)); p_O_FD desc18(.Q(x_8[5:5]),.D(x_7[5:5]),.C(clk),.E(p_desc18_p_O_FD)); p_O_FD desc19(.Q(x_8[4:4]),.D(x_7[4:4]),.C(clk),.E(p_desc19_p_O_FD)); p_O_FD desc20(.Q(x_8[3:3]),.D(x_7[3:3]),.C(clk),.E(p_desc20_p_O_FD)); p_O_FD desc21(.Q(x_8[2:2]),.D(x_7[2:2]),.C(clk),.E(p_desc21_p_O_FD)); p_O_FD desc22(.Q(x_8[1:1]),.D(x_7[1:1]),.C(clk),.E(p_desc22_p_O_FD)); p_O_FD desc23(.Q(x_8[0:0]),.D(x_7[0:0]),.C(clk),.E(p_desc23_p_O_FD)); p_O_FD desc24(.Q(x_9),.D(x_8[0:0]),.C(clk),.E(p_desc24_p_O_FD)); p_O_FD desc25(.Q(x_13[7:7]),.D(x_12[7:7]),.C(clk),.E(p_desc25_p_O_FD)); p_O_FD desc26(.Q(x_13[6:6]),.D(x_12[6:6]),.C(clk),.E(p_desc26_p_O_FD)); p_O_FD desc27(.Q(x_13[5:5]),.D(x_12[5:5]),.C(clk),.E(p_desc27_p_O_FD)); p_O_FD desc28(.Q(x_13[4:4]),.D(x_12[4:4]),.C(clk),.E(p_desc28_p_O_FD)); p_O_FD desc29(.Q(x_13[3:3]),.D(x_12[3:3]),.C(clk),.E(p_desc29_p_O_FD)); p_O_FD desc30(.Q(x_13[2:2]),.D(x_12[2:2]),.C(clk),.E(p_desc30_p_O_FD)); p_O_FD desc31(.Q(x_13[1:1]),.D(x_12[1:1]),.C(clk),.E(p_desc31_p_O_FD)); p_O_FD desc32(.Q(x_13[0:0]),.D(x_12[0:0]),.C(clk),.E(p_desc32_p_O_FD)); p_O_FD x_14_pipe_0_Z(.Q(un84_sop_0_0_0_0_0[0:0]),.D(un84_sop_0_0_0_0_1[0:0]),.C(clk),.E(p_x_14_pipe_0_Z_p_O_FD)); p_O_FD x_14_pipe_9_Z(.Q(un84_sop_0_0_0_0_0[1:1]),.D(un84_sop_0_0_0_0_1[1:1]),.C(clk),.E(p_x_14_pipe_9_Z_p_O_FD)); p_O_FD x_14_pipe_10_Z(.Q(un84_sop_0_0_0_0_0[2:2]),.D(un84_sop_0_0_0_0_1[2:2]),.C(clk),.E(p_x_14_pipe_10_Z_p_O_FD)); p_O_FD x_14_pipe_11_Z(.Q(un84_sop_0_0_0_0_0[3:3]),.D(un84_sop_0_0_0_0_1[3:3]),.C(clk),.E(p_x_14_pipe_11_Z_p_O_FD)); p_O_FD x_14_pipe_12_Z(.Q(un84_sop_0_0_0_0_0[4:4]),.D(un84_sop_0_0_0_0_1[4:4]),.C(clk),.E(p_x_14_pipe_12_Z_p_O_FD)); p_O_FD x_14_pipe_13_Z(.Q(un84_sop_0_0_0_0_0[5:5]),.D(un84_sop_0_0_0_0_1[5:5]),.C(clk),.E(p_x_14_pipe_13_Z_p_O_FD)); p_O_FD x_14_pipe_14_Z(.Q(un84_sop_0_0_0_0_0[6:6]),.D(un84_sop_0_0_0_0_1[6:6]),.C(clk),.E(p_x_14_pipe_14_Z_p_O_FD)); p_O_FD x_14_pipe_15_Z(.Q(un84_sop_0_0_0_0_0[7:7]),.D(un84_sop_0_0_0_0_1[7:7]),.C(clk),.E(p_x_14_pipe_15_Z_p_O_FD)); p_O_FD x_14_pipe_16_Z(.Q(un84_sop_0_0_0_0_0[8:8]),.D(un84_sop_0_0_0_0_1[8:8]),.C(clk),.E(p_x_14_pipe_16_Z_p_O_FD)); p_O_FD x_14_pipe_17_Z(.Q(un84_sop_0_0_0_0_0[9:9]),.D(un84_sop_0_0_0_0_1[9:9]),.C(clk),.E(p_x_14_pipe_17_Z_p_O_FD)); p_O_FD x_9_pipe_1_Z(.Q(un1_x_11_0_0[7:7]),.D(un1_x_11_0_0_0[7:7]),.C(clk),.E(p_x_9_pipe_1_Z_p_O_FD)); p_O_FD x_9_pipe_2_Z(.Q(un1_x_11_0_0[8:8]),.D(un1_x_11_0_0_0[8:8]),.C(clk),.E(p_x_9_pipe_2_Z_p_O_FD)); p_O_FD x_9_pipe_3_Z(.Q(un1_x_11_0_0[9:9]),.D(un1_x_11_0_0_0[9:9]),.C(clk),.E(p_x_9_pipe_3_Z_p_O_FD)); p_O_FD x_9_pipe_4_Z(.Q(un1_x_11_0_0[10:10]),.D(un1_x_11_0_0_0[10:10]),.C(clk),.E(p_x_9_pipe_4_Z_p_O_FD)); p_O_FD x_9_pipe_5_Z(.Q(un1_x_11_0_0[11:11]),.D(un1_x_11_0_0_0[11:11]),.C(clk),.E(p_x_9_pipe_5_Z_p_O_FD)); p_O_FD x_9_pipe_6_Z(.Q(un1_x_11_0_0[12:12]),.D(un1_x_11_0_0_0[12:12]),.C(clk),.E(p_x_9_pipe_6_Z_p_O_FD)); p_O_FD x_9_pipe_7_Z(.Q(un1_x_11_0_0[13:13]),.D(un1_x_11_0_0_0[13:13]),.C(clk),.E(p_x_9_pipe_7_Z_p_O_FD)); p_O_FD x_9_pipe_8_Z(.Q(un1_x_11_0_0[14:14]),.D(un1_x_11_0_0_0[14:14]),.C(clk),.E(p_x_9_pipe_8_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_15_Z(.Q(un84_sop_0_0_0_10_0[0:0]),.D(un84_sop_0_0_0_0_8[0:0]),.C(clk),.E(p_x_15_pipe_0_0_15_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_16_Z(.Q(un84_sop_0_0_0_10_0[1:1]),.D(un84_sop_0_0_0_0_8[1:1]),.C(clk),.E(p_x_15_pipe_0_0_16_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_17_Z(.Q(un84_sop_0_0_0_10_0[2:2]),.D(un84_sop_0_0_0_0_8[2:2]),.C(clk),.E(p_x_15_pipe_0_0_17_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_18_Z(.Q(un84_sop_0_0_0_10_0[3:3]),.D(un84_sop_0_0_0_0_8[3:3]),.C(clk),.E(p_x_15_pipe_0_0_18_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_19_Z(.Q(un84_sop_0_0_0_10_0[4:4]),.D(un84_sop_0_0_0_0_8[4:4]),.C(clk),.E(p_x_15_pipe_0_0_19_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_20_Z(.Q(un84_sop_0_0_0_10_0[5:5]),.D(un84_sop_0_0_0_0_8[5:5]),.C(clk),.E(p_x_15_pipe_0_0_20_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_21_Z(.Q(un84_sop_0_0_0_10_0[6:6]),.D(un84_sop_0_0_0_0_8[6:6]),.C(clk),.E(p_x_15_pipe_0_0_21_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_22_Z(.Q(un84_sop_0_0_0_10_0[7:7]),.D(un84_sop_0_0_0_0_8[7:7]),.C(clk),.E(p_x_15_pipe_0_0_22_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_23_Z(.Q(un84_sop_0_0_0_10_0[8:8]),.D(un84_sop_0_0_0_0_8[8:8]),.C(clk),.E(p_x_15_pipe_0_0_23_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_24_Z(.Q(un84_sop_0_0_0_10_0[9:9]),.D(un84_sop_0_0_0_0_8[9:9]),.C(clk),.E(p_x_15_pipe_0_0_24_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_25_Z(.Q(un84_sop_0_0_0_10_0[10:10]),.D(un84_sop_0_0_0_0_8[10:10]),.C(clk),.E(p_x_15_pipe_0_0_25_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_26_Z(.Q(un84_sop_0_0_0_10_0[11:11]),.D(un84_sop_0_0_0_0_8[11:11]),.C(clk),.E(p_x_15_pipe_0_0_26_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_27_Z(.Q(un84_sop_0_0_0_10_0[12:12]),.D(un84_sop_0_0_0_0_8[12:12]),.C(clk),.E(p_x_15_pipe_0_0_27_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_28_Z(.Q(un84_sop_0_0_0_10_0[13:13]),.D(un84_sop_0_0_0_0_8[13:13]),.C(clk),.E(p_x_15_pipe_0_0_28_Z_p_O_FD)); p_O_FD x_15_pipe_0_0_29_Z(.Q(un84_sop_0_0_0_10_0[14:14]),.D(un84_sop_0_0_0_0_8[14:14]),.C(clk),.E(p_x_15_pipe_0_0_29_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_0_Z(.Q(un84_sop_0_0_0_0_5[0:0]),.D(un84_sop_0_0_0_5_0[0:0]),.C(clk),.E(p_x_16_pipe_0_0_0_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_1_Z(.Q(un84_sop_0_0_0_0_5[1:1]),.D(un84_sop_0_0_0_5_0[1:1]),.C(clk),.E(p_x_16_pipe_0_0_1_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_2_Z(.Q(un84_sop_0_0_0_0_5[2:2]),.D(un84_sop_0_0_0_5_0[2:2]),.C(clk),.E(p_x_16_pipe_0_0_2_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_3_Z(.Q(un84_sop_0_0_0_0_5[3:3]),.D(un84_sop_0_0_0_5_0[3:3]),.C(clk),.E(p_x_16_pipe_0_0_3_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_4_Z(.Q(un84_sop_0_0_0_0_5[4:4]),.D(un84_sop_0_0_0_5_0[4:4]),.C(clk),.E(p_x_16_pipe_0_0_4_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_5_Z(.Q(un84_sop_0_0_0_0_5[5:5]),.D(un84_sop_0_0_0_5_0[5:5]),.C(clk),.E(p_x_16_pipe_0_0_5_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_6_Z(.Q(un84_sop_0_0_0_0_5[6:6]),.D(un84_sop_0_0_0_5_0[6:6]),.C(clk),.E(p_x_16_pipe_0_0_6_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_7_Z(.Q(un84_sop_0_0_0_0_5[7:7]),.D(un84_sop_0_0_0_5_0[7:7]),.C(clk),.E(p_x_16_pipe_0_0_7_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_8_Z(.Q(un84_sop_0_0_0_0_5[8:8]),.D(un84_sop_0_0_0_5_0[8:8]),.C(clk),.E(p_x_16_pipe_0_0_8_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_9_Z(.Q(un84_sop_0_0_0_0_5[9:9]),.D(un84_sop_0_0_0_5_0[9:9]),.C(clk),.E(p_x_16_pipe_0_0_9_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_10_Z(.Q(un84_sop_0_0_0_0_5[10:10]),.D(un84_sop_0_0_0_5_0[10:10]),.C(clk),.E(p_x_16_pipe_0_0_10_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_11_Z(.Q(un84_sop_0_0_0_0_5[11:11]),.D(un84_sop_0_0_0_5_0[11:11]),.C(clk),.E(p_x_16_pipe_0_0_11_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_12_Z(.Q(un84_sop_0_0_0_0_5[12:12]),.D(un84_sop_0_0_0_5_0[12:12]),.C(clk),.E(p_x_16_pipe_0_0_12_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_13_Z(.Q(un84_sop_0_0_0_0_5[13:13]),.D(un84_sop_0_0_0_5_0[13:13]),.C(clk),.E(p_x_16_pipe_0_0_13_Z_p_O_FD)); p_O_FD x_16_pipe_0_0_14_Z(.Q(un84_sop_0_0_0_0_5[14:14]),.D(un84_sop_0_0_0_5_0[14:14]),.C(clk),.E(p_x_16_pipe_0_0_14_Z_p_O_FD)); p_O_FD desc33(.Q(x_4[7:7]),.D(x_4_tmp_d_array_0),.C(clk),.E(p_desc33_p_O_FD)); p_O_FD desc34(.Q(x_4[6:6]),.D(x_4_0_tmp_d_array_0),.C(clk),.E(p_desc34_p_O_FD)); p_O_FD desc35(.Q(x_4[5:5]),.D(x_4_1_tmp_d_array_0),.C(clk),.E(p_desc35_p_O_FD)); p_O_FD desc36(.Q(x_4[4:4]),.D(x_4_2_tmp_d_array_0),.C(clk),.E(p_desc36_p_O_FD)); p_O_FD desc37(.Q(x_4[3:3]),.D(x_4_3_tmp_d_array_0),.C(clk),.E(p_desc37_p_O_FD)); p_O_FD desc38(.Q(x_4[2:2]),.D(x_4_4_tmp_d_array_0),.C(clk),.E(p_desc38_p_O_FD)); p_O_FD desc39(.Q(x_4[1:1]),.D(x_4_5_tmp_d_array_0),.C(clk),.E(p_desc39_p_O_FD)); p_O_FD desc40(.Q(x_4[0:0]),.D(x_4_6_tmp_d_array_0),.C(clk),.E(p_desc40_p_O_FD)); p_O_FD desc41(.Q(x_7[7:7]),.D(x_7_tmp_d_array_0),.C(clk),.E(p_desc41_p_O_FD)); p_O_FD desc42(.Q(x_7[6:6]),.D(x_7_0_tmp_d_array_0),.C(clk),.E(p_desc42_p_O_FD)); p_O_FD desc43(.Q(x_7[5:5]),.D(x_7_1_tmp_d_array_0),.C(clk),.E(p_desc43_p_O_FD)); p_O_FD desc44(.Q(x_7[4:4]),.D(x_7_2_tmp_d_array_0),.C(clk),.E(p_desc44_p_O_FD)); p_O_FD desc45(.Q(x_7[3:3]),.D(x_7_3_tmp_d_array_0),.C(clk),.E(p_desc45_p_O_FD)); p_O_FD desc46(.Q(x_7[2:2]),.D(x_7_4_tmp_d_array_0),.C(clk),.E(p_desc46_p_O_FD)); p_O_FD desc47(.Q(x_7[1:1]),.D(x_7_5_tmp_d_array_0),.C(clk),.E(p_desc47_p_O_FD)); p_O_FD desc48(.Q(x_7[0:0]),.D(x_7_6_tmp_d_array_0),.C(clk),.E(p_desc48_p_O_FD)); p_O_FD desc49(.Q(x_12[7:7]),.D(x_12_tmp_d_array_0),.C(clk),.E(p_desc49_p_O_FD)); p_O_FD desc50(.Q(x_12[6:6]),.D(x_12_0_tmp_d_array_0),.C(clk),.E(p_desc50_p_O_FD)); p_O_FD desc51(.Q(x_12[5:5]),.D(x_12_1_tmp_d_array_0),.C(clk),.E(p_desc51_p_O_FD)); p_O_FD desc52(.Q(x_12[4:4]),.D(x_12_2_tmp_d_array_0),.C(clk),.E(p_desc52_p_O_FD)); p_O_FD desc53(.Q(x_12[3:3]),.D(x_12_3_tmp_d_array_0),.C(clk),.E(p_desc53_p_O_FD)); p_O_FD desc54(.Q(x_12[2:2]),.D(x_12_4_tmp_d_array_0),.C(clk),.E(p_desc54_p_O_FD)); p_O_FD desc55(.Q(x_12[1:1]),.D(x_12_5_tmp_d_array_0),.C(clk),.E(p_desc55_p_O_FD)); p_O_FD desc56(.Q(x_12[0:0]),.D(x_12_6_tmp_d_array_0),.C(clk),.E(p_desc56_p_O_FD)); MUXCY_L un84_sop_1_6_0_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(un1_x_3_0[4:4]),.LO(un84_sop_1_6_0_cry_0_cy)); MUXCY_L un84_sop_0_0_0_6_6_0_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(un1_x_9_0_0[5:5]),.LO(un84_sop_0_0_0_6_6_0_cry_0_cy)); MUXCY_L un84_sop_0_0_0_11_6_0_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(un1_x_14_0_0_0[4:4]),.LO(un84_sop_0_0_0_11_6_0_cry_0_cy)); LUT3 un84_sop_0_0_0_11_0_cry_2_RNO_cZ(.I0(x_8[1:1]),.I1(x_8[0:0]),.I2(un84_sop_0_0_0_0_11_7[1:1]),.O(un84_sop_0_0_0_11_0_cry_2_RNO)); defparam un84_sop_0_0_0_11_0_cry_2_RNO_cZ.INIT=8'h60; LUT6 un84_sop_0_0_0_11_6_0_axb_8_cZ(.I0(un1_x_12_0_0[11:11]),.I1(un1_x_12_0_0[12:12]),.I2(un1_x_13_0_0[12:12]),.I3(un1_x_13_0_0[13:13]),.I4(un1_x_14_0_0[11:11]),.I5(un1_x_14_0_0[12:12]),.O(un84_sop_0_0_0_11_6_0_axb_8)); defparam un84_sop_0_0_0_11_6_0_axb_8_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_11_6_0_axb_3_cZ(.I0(un1_x_12_0_0[6:6]),.I1(un1_x_12_0_0[7:7]),.I2(un1_x_13_0_0[7:7]),.I3(un1_x_13_0_0[8:8]),.I4(un1_x_14_0_0[6:6]),.I5(un1_x_14_0_0[7:7]),.O(un84_sop_0_0_0_11_6_0_axb_3)); defparam un84_sop_0_0_0_11_6_0_axb_3_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_11_6_0_axb_4_cZ(.I0(un1_x_12_0_0[7:7]),.I1(un1_x_12_0_0[8:8]),.I2(un1_x_13_0_0[8:8]),.I3(un1_x_13_0_0[9:9]),.I4(un1_x_14_0_0[7:7]),.I5(un1_x_14_0_0[8:8]),.O(un84_sop_0_0_0_11_6_0_axb_4)); defparam un84_sop_0_0_0_11_6_0_axb_4_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_11_6_0_axb_9_cZ(.I0(un1_x_12_0_0[12:12]),.I1(un1_x_12_0_0[13:13]),.I2(un1_x_13_0_0[13:13]),.I3(un1_x_13_0_0[14:14]),.I4(un1_x_14_0_0[12:12]),.I5(un1_x_14_0_0[13:13]),.O(un84_sop_0_0_0_11_6_0_axb_9)); defparam un84_sop_0_0_0_11_6_0_axb_9_cZ.INIT=64'h36C96C93C936936C; LUT5 un84_sop_0_0_0_11_6_0_axb_11_cZ(.I0(un1_x_12_0_0[14:14]),.I1(un1_x_14_0_0[14:14]),.I2(un1_x_12_0_0[15:15]),.I3(un1_x_14_0_0[15:15]),.I4(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_axb_11)); defparam un84_sop_0_0_0_11_6_0_axb_11_cZ.INIT=32'h1EE18778; LUT6 un84_sop_1_6_0_axb_4_cZ(.I0(un1_x_1[7:7]),.I1(un1_x_1[8:8]),.I2(un1_x_2[8:8]),.I3(un1_x_2[9:9]),.I4(un1_x_3[7:7]),.I5(un1_x_3[8:8]),.O(un84_sop_1_6_0_axb_4)); defparam un84_sop_1_6_0_axb_4_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_11_6_0_axb_10_cZ(.I0(un1_x_12_0_0[13:13]),.I1(un1_x_12_0_0[14:14]),.I2(un1_x_13_0_0[14:14]),.I3(un1_x_14_0_0[13:13]),.I4(un1_x_14_0_0[14:14]),.I5(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_axb_10)); defparam un84_sop_0_0_0_11_6_0_axb_10_cZ.INIT=64'h366CC993C993366C; LUT6 un84_sop_0_0_0_11_6_0_axb_2_cZ(.I0(un1_x_12_0_0[5:5]),.I1(un1_x_12_0_0[6:6]),.I2(un1_x_13_0_0[6:6]),.I3(un1_x_13_0_0[7:7]),.I4(un1_x_14_0_0[5:5]),.I5(un1_x_14_0_0[6:6]),.O(un84_sop_0_0_0_11_6_0_axb_2)); defparam un84_sop_0_0_0_11_6_0_axb_2_cZ.INIT=64'h36C96C93C936936C; LUT6_L un84_sop_0_0_0_11_0_axb_5_cZ(.I0(un84_sop_0_0_0_0_11_7[4:4]),.I1(un84_sop_0_0_0_0_11_7[5:5]),.I2(un84_sop_0_0_0_0_11_6[4:4]),.I3(un84_sop_0_0_0_0_11_6[5:5]),.I4(un1_x_10_0_0[8:8]),.I5(un1_x_10_0_0[9:9]),.LO(un84_sop_0_0_0_11_0_axb_5)); defparam un84_sop_0_0_0_11_0_axb_5_cZ.INIT=64'h36C96C93C936936C; LUT6_L un84_sop_0_0_0_11_0_axb_6_cZ(.I0(un84_sop_0_0_0_0_11_7[5:5]),.I1(un84_sop_0_0_0_0_11_7[6:6]),.I2(un84_sop_0_0_0_0_11_6[5:5]),.I3(un84_sop_0_0_0_0_11_6[6:6]),.I4(un1_x_10_0_0[9:9]),.I5(un1_x_10_0_0[10:10]),.LO(un84_sop_0_0_0_11_0_axb_6)); defparam un84_sop_0_0_0_11_0_axb_6_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_11_6_0_axb_6_cZ(.I0(un1_x_12_0_0[9:9]),.I1(un1_x_12_0_0[10:10]),.I2(un1_x_13_0_0[10:10]),.I3(un1_x_13_0_0[11:11]),.I4(un1_x_14_0_0[9:9]),.I5(un1_x_14_0_0[10:10]),.O(un84_sop_0_0_0_11_6_0_axb_6)); defparam un84_sop_0_0_0_11_6_0_axb_6_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_11_6_0_axb_7_cZ(.I0(un1_x_12_0_0[10:10]),.I1(un1_x_12_0_0[11:11]),.I2(un1_x_13_0_0[11:11]),.I3(un1_x_13_0_0[12:12]),.I4(un1_x_14_0_0[10:10]),.I5(un1_x_14_0_0[11:11]),.O(un84_sop_0_0_0_11_6_0_axb_7)); defparam un84_sop_0_0_0_11_6_0_axb_7_cZ.INIT=64'h36C96C93C936936C; LUT6_L un84_sop_0_0_0_11_0_axb_10_cZ(.I0(un84_sop_0_0_0_0_11_7[9:9]),.I1(un84_sop_0_0_0_0_11_7[14:14]),.I2(un84_sop_0_0_0_0_11_6[9:9]),.I3(un84_sop_0_0_0_0_11_6[10:10]),.I4(un1_x_10_0_0[13:13]),.I5(un1_x_10_0_0[14:14]),.LO(un84_sop_0_0_0_11_0_axb_10)); defparam un84_sop_0_0_0_11_0_axb_10_cZ.INIT=64'h36C96C93C936936C; LUT4_L un84_sop_0_0_0_11_0_axb_12_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[11:11]),.I2(un84_sop_0_0_0_0_11_6[12:12]),.I3(un1_x_10_0_0[15:15]),.LO(un84_sop_0_0_0_11_0_axb_12)); defparam un84_sop_0_0_0_11_0_axb_12_cZ.INIT=16'h4BD2; LUT4_L un84_sop_0_0_0_11_0_axb_13_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[14:14]),.I2(un84_sop_0_0_0_0_11_6[12:12]),.I3(un1_x_10_0_0[15:15]),.LO(un84_sop_0_0_0_11_0_axb_13)); defparam un84_sop_0_0_0_11_0_axb_13_cZ.INIT=16'h63C6; LUT3 un84_sop_0_0_0_11_6_0_axb_13_cZ(.I0(un1_x_12_0_0[15:15]),.I1(un1_x_14_0_0[15:15]),.I2(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_axb_13)); defparam un84_sop_0_0_0_11_6_0_axb_13_cZ.INIT=8'h7E; LUT6_L un84_sop_0_0_0_11_0_axb_3_cZ(.I0(un84_sop_0_0_0_0_11_7[2:2]),.I1(un84_sop_0_0_0_0_11_7[3:3]),.I2(un84_sop_0_0_0_0_11_6[2:2]),.I3(un1_x_10_s_2_sf),.I4(un1_x_10_axb_3),.I5(un84_sop_0_0_0_0_11_6[3:3]),.LO(un84_sop_0_0_0_11_0_axb_3)); defparam un84_sop_0_0_0_11_0_axb_3_cZ.INIT=64'h366CC993C993366C; LUT6_L un84_sop_0_0_0_11_0_axb_4_cZ(.I0(un84_sop_0_0_0_0_11_7[3:3]),.I1(un84_sop_0_0_0_0_11_7[4:4]),.I2(un1_x_10_axb_3),.I3(un84_sop_0_0_0_0_11_6[3:3]),.I4(un84_sop_0_0_0_0_11_6[4:4]),.I5(un1_x_10_0_0[8:8]),.LO(un84_sop_0_0_0_11_0_axb_4)); defparam un84_sop_0_0_0_11_0_axb_4_cZ.INIT=64'h366CC993C993366C; LUT6 un84_sop_0_0_0_6_6_0_axb_5_cZ(.I0(un1_x_7_0[6:6]),.I1(un1_x_7_0[7:7]),.I2(un1_x_8_0[8:8]),.I3(un1_x_8_0[9:9]),.I4(un1_x_9_0[9:9]),.I5(un1_x_9_0[10:10]),.O(un84_sop_0_0_0_6_6_0_axb_5)); defparam un84_sop_0_0_0_6_6_0_axb_5_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_6_6_0_axb_6_cZ(.I0(un1_x_7_0[7:7]),.I1(un1_x_7_0[8:8]),.I2(un1_x_8_0[9:9]),.I3(un1_x_8_0[10:10]),.I4(un1_x_9_0[10:10]),.I5(un1_x_9_0[11:11]),.O(un84_sop_0_0_0_6_6_0_axb_6)); defparam un84_sop_0_0_0_6_6_0_axb_6_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_6_6_0_axb_10_cZ(.I0(un1_x_7_0[11:11]),.I1(un1_x_7_0[12:12]),.I2(un1_x_8_0[13:13]),.I3(un1_x_8_0[14:14]),.I4(un1_x_9_0[14:14]),.I5(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_10)); defparam un84_sop_0_0_0_6_6_0_axb_10_cZ.INIT=64'h36C96C93C936936C; LUT5 un84_sop_0_0_0_6_6_0_axb_11_cZ(.I0(un1_x_7_0[12:12]),.I1(un1_x_7_0[13:13]),.I2(un1_x_8_0[14:14]),.I3(un1_x_8_0[15:15]),.I4(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_11)); defparam un84_sop_0_0_0_6_6_0_axb_11_cZ.INIT=32'h36C9936C; LUT6 un84_sop_0_0_0_1_6_8_axb_3_cZ(.I0(un84_sop_0_0_0_10_0[5:5]),.I1(un84_sop_0_0_0_10_0[6:6]),.I2(x_4[1:1]),.I3(x_4[0:0]),.I4(x_4[2:2]),.I5(x_4[3:3]),.O(un84_sop_0_0_0_1_6_8_axb_3)); defparam un84_sop_0_0_0_1_6_8_axb_3_cZ.INIT=64'h3C6969C3C396963C; LUT6 un84_sop_0_0_0_1_6_8_axb_4_cZ(.I0(un84_sop_0_0_0_10_0[6:6]),.I1(un84_sop_0_0_0_10_0[7:7]),.I2(x_4[1:1]),.I3(x_4[2:2]),.I4(x_4[3:3]),.I5(x_4[4:4]),.O(un84_sop_0_0_0_1_6_8_axb_4)); defparam un84_sop_0_0_0_1_6_8_axb_4_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_1_6_8_axb_5_cZ(.I0(un84_sop_0_0_0_10_0[7:7]),.I1(un84_sop_0_0_0_10_0[8:8]),.I2(x_4[2:2]),.I3(x_4[3:3]),.I4(x_4[4:4]),.I5(x_4[5:5]),.O(un84_sop_0_0_0_1_6_8_axb_5)); defparam un84_sop_0_0_0_1_6_8_axb_5_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_1_6_8_axb_6_cZ(.I0(un84_sop_0_0_0_10_0[8:8]),.I1(un84_sop_0_0_0_10_0[9:9]),.I2(x_4[6:6]),.I3(x_4[3:3]),.I4(x_4[4:4]),.I5(x_4[5:5]),.O(un84_sop_0_0_0_1_6_8_axb_6)); defparam un84_sop_0_0_0_1_6_8_axb_6_cZ.INIT=64'h3C69C39669C3963C; LUT6 un84_sop_0_0_0_1_6_8_axb_7_cZ(.I0(un84_sop_0_0_0_10_0[9:9]),.I1(un84_sop_0_0_0_10_0[10:10]),.I2(x_4[6:6]),.I3(x_4[4:4]),.I4(x_4[5:5]),.I5(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_7)); defparam un84_sop_0_0_0_1_6_8_axb_7_cZ.INIT=64'h366CC993C993366C; LUT5 un84_sop_0_0_0_1_6_8_axb_8_cZ(.I0(un84_sop_0_0_0_10_0[11:11]),.I1(un84_sop_0_0_0_10_0[10:10]),.I2(x_4[6:6]),.I3(x_4[5:5]),.I4(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_8)); defparam un84_sop_0_0_0_1_6_8_axb_8_cZ.INIT=32'h5A69965A; LUT6 un84_sop_0_0_0_11_6_0_axb_5_cZ(.I0(un1_x_12_0_0[8:8]),.I1(un1_x_12_0_0[9:9]),.I2(un1_x_13_0_0[9:9]),.I3(un1_x_13_0_0[10:10]),.I4(un1_x_14_0_0[8:8]),.I5(un1_x_14_0_0[9:9]),.O(un84_sop_0_0_0_11_6_0_axb_5)); defparam un84_sop_0_0_0_11_6_0_axb_5_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_1_6_0_axb_2_cZ(.I0(un1_x_1[5:5]),.I1(un1_x_1[6:6]),.I2(un1_x_2[6:6]),.I3(un1_x_2[7:7]),.I4(un1_x_3[5:5]),.I5(un1_x_3[6:6]),.O(un84_sop_1_6_0_axb_2)); defparam un84_sop_1_6_0_axb_2_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_1_6_0_axb_3_cZ(.I0(un1_x_1[6:6]),.I1(un1_x_1[7:7]),.I2(un1_x_2[7:7]),.I3(un1_x_2[8:8]),.I4(un1_x_3[6:6]),.I5(un1_x_3[7:7]),.O(un84_sop_1_6_0_axb_3)); defparam un84_sop_1_6_0_axb_3_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_1_6_0_axb_5_cZ(.I0(un1_x_1[8:8]),.I1(un1_x_1[9:9]),.I2(un1_x_2[9:9]),.I3(un1_x_2[10:10]),.I4(un1_x_3[8:8]),.I5(un1_x_3[9:9]),.O(un84_sop_1_6_0_axb_5)); defparam un84_sop_1_6_0_axb_5_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_1_6_0_axb_6_cZ(.I0(un1_x_1[9:9]),.I1(un1_x_1[10:10]),.I2(un1_x_2[10:10]),.I3(un1_x_2[11:11]),.I4(un1_x_3[9:9]),.I5(un1_x_3[10:10]),.O(un84_sop_1_6_0_axb_6)); defparam un84_sop_1_6_0_axb_6_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_1_6_0_axb_7_cZ(.I0(un1_x_1[10:10]),.I1(un1_x_1[11:11]),.I2(un1_x_2[11:11]),.I3(un1_x_2[12:12]),.I4(un1_x_3[10:10]),.I5(un1_x_3[11:11]),.O(un84_sop_1_6_0_axb_7)); defparam un84_sop_1_6_0_axb_7_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_1_6_0_axb_8_cZ(.I0(un1_x_1[11:11]),.I1(un1_x_1[12:12]),.I2(un1_x_2[12:12]),.I3(un1_x_2[13:13]),.I4(un1_x_3[11:11]),.I5(un1_x_3[12:12]),.O(un84_sop_1_6_0_axb_8)); defparam un84_sop_1_6_0_axb_8_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_1_6_0_axb_9_cZ(.I0(un1_x_1[12:12]),.I1(un1_x_1[13:13]),.I2(un1_x_2[13:13]),.I3(un1_x_2[14:14]),.I4(un1_x_3[12:12]),.I5(un1_x_3[13:13]),.O(un84_sop_1_6_0_axb_9)); defparam un84_sop_1_6_0_axb_9_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_1_6_0_axb_10_cZ(.I0(un1_x_1[13:13]),.I1(un1_x_1[14:14]),.I2(un1_x_2[14:14]),.I3(un1_x_3[13:13]),.I4(un1_x_3[14:14]),.I5(un1_x_2[15:15]),.O(un84_sop_1_6_0_axb_10)); defparam un84_sop_1_6_0_axb_10_cZ.INIT=64'h366CC993C993366C; LUT5 un84_sop_1_6_0_axb_11_cZ(.I0(un1_x_1[14:14]),.I1(un1_x_3[14:14]),.I2(un1_x_1[15:15]),.I3(un1_x_3[15:15]),.I4(un1_x_2[15:15]),.O(un84_sop_1_6_0_axb_11)); defparam un84_sop_1_6_0_axb_11_cZ.INIT=32'h1EE18778; LUT3 un84_sop_1_6_0_axb_13_cZ(.I0(un1_x_1[15:15]),.I1(un1_x_3[15:15]),.I2(un1_x_2[15:15]),.O(un84_sop_1_6_0_axb_13)); defparam un84_sop_1_6_0_axb_13_cZ.INIT=8'h7E; LUT6_L un84_sop_0_0_0_11_0_axb_7_cZ(.I0(un84_sop_0_0_0_0_11_7[6:6]),.I1(un84_sop_0_0_0_0_11_7[7:7]),.I2(un84_sop_0_0_0_0_11_6[6:6]),.I3(un84_sop_0_0_0_0_11_6[7:7]),.I4(un1_x_10_0_0[10:10]),.I5(un1_x_10_0_0[11:11]),.LO(un84_sop_0_0_0_11_0_axb_7)); defparam un84_sop_0_0_0_11_0_axb_7_cZ.INIT=64'h36C96C93C936936C; LUT6_L un84_sop_0_0_0_11_0_axb_8_cZ(.I0(un84_sop_0_0_0_0_11_7[7:7]),.I1(un84_sop_0_0_0_0_11_7[8:8]),.I2(un84_sop_0_0_0_0_11_6[7:7]),.I3(un84_sop_0_0_0_0_11_6[8:8]),.I4(un1_x_10_0_0[11:11]),.I5(un1_x_10_0_0[12:12]),.LO(un84_sop_0_0_0_11_0_axb_8)); defparam un84_sop_0_0_0_11_0_axb_8_cZ.INIT=64'h36C96C93C936936C; LUT6_L un84_sop_0_0_0_11_0_axb_9_cZ(.I0(un84_sop_0_0_0_0_11_7[8:8]),.I1(un84_sop_0_0_0_0_11_7[9:9]),.I2(un84_sop_0_0_0_0_11_6[8:8]),.I3(un84_sop_0_0_0_0_11_6[9:9]),.I4(un1_x_10_0_0[12:12]),.I5(un1_x_10_0_0[13:13]),.LO(un84_sop_0_0_0_11_0_axb_9)); defparam un84_sop_0_0_0_11_0_axb_9_cZ.INIT=64'h36C96C93C936936C; LUT4_L un84_sop_0_0_0_11_0_axb_1_cZ(.I0(x_8[1:1]),.I1(x_8[0:0]),.I2(un84_sop_0_0_0_0_11_7[1:1]),.I3(un84_sop_0_0_0_0_11_6[1:1]),.LO(un84_sop_0_0_0_11_0_axb_1)); defparam un84_sop_0_0_0_11_0_axb_1_cZ.INIT=16'h6996; LUT5_L un84_sop_0_0_0_11_0_axb_11_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[10:10]),.I2(un84_sop_0_0_0_0_11_6[11:11]),.I3(un1_x_10_0_0[14:14]),.I4(un1_x_10_0_0[15:15]),.LO(un84_sop_0_0_0_11_0_axb_11)); defparam un84_sop_0_0_0_11_0_axb_11_cZ.INIT=32'h4B2DB4D2; LUT3 un84_sop_0_0_0_1_6_axb_0(.I0(un84_sop_0_0_0_10_0[0:0]),.I1(un1_x_6_0[1:1]),.I2(un84_sop_0_0_0_1_6_6[0:0]),.O(un84_sop_0_0_0_5_0[0:0])); defparam un84_sop_0_0_0_1_6_axb_0.INIT=8'h96; LUT6 un84_sop_1_4_axb_4_cZ(.I0(x_0[3:3]),.I1(x_0[2:2]),.I2(x_0[1:1]),.I3(x_0[0:0]),.I4(x_0[4:4]),.I5(un84_sop_1_7[4:4]),.O(un84_sop_1_4_axb_4)); defparam un84_sop_1_4_axb_4_cZ.INIT=64'hFFFE00010001FFFE; LUT6 un84_sop_0_0_0_6_6_0_axb_2_cZ(.I0(un1_x_7_0[3:3]),.I1(un1_x_7_0[4:4]),.I2(un1_x_8_0[5:5]),.I3(un1_x_8_0[6:6]),.I4(un1_x_9_0[6:6]),.I5(un1_x_9_0[7:7]),.O(un84_sop_0_0_0_6_6_0_axb_2)); defparam un84_sop_0_0_0_6_6_0_axb_2_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_6_6_0_axb_3_cZ(.I0(un1_x_7_0[4:4]),.I1(un1_x_7_0[5:5]),.I2(un1_x_8_0[6:6]),.I3(un1_x_8_0[7:7]),.I4(un1_x_9_0[7:7]),.I5(un1_x_9_0[8:8]),.O(un84_sop_0_0_0_6_6_0_axb_3)); defparam un84_sop_0_0_0_6_6_0_axb_3_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_6_6_0_axb_4_cZ(.I0(un1_x_7_0[5:5]),.I1(un1_x_7_0[6:6]),.I2(un1_x_8_0[7:7]),.I3(un1_x_8_0[8:8]),.I4(un1_x_9_0[8:8]),.I5(un1_x_9_0[9:9]),.O(un84_sop_0_0_0_6_6_0_axb_4)); defparam un84_sop_0_0_0_6_6_0_axb_4_cZ.INIT=64'h36C96C93C936936C; LUT6_L un84_sop_0_0_0_11_6_0_s_2_RNIGK751(.I0(x_8[1:1]),.I1(x_8[0:0]),.I2(un84_sop_0_0_0_0_11_7[1:1]),.I3(un84_sop_0_0_0_0_11_7[2:2]),.I4(un84_sop_0_0_0_0_11_6[2:2]),.I5(un1_x_10_s_2_sf),.LO(un84_sop_0_0_0_11_0_axb_2)); defparam un84_sop_0_0_0_11_6_0_s_2_RNIGK751.INIT=64'h9F60609F609F9F60; LUT6 un84_sop_0_0_0_6_6_0_axb_7_cZ(.I0(un1_x_7_0[8:8]),.I1(un1_x_7_0[9:9]),.I2(un1_x_8_0[10:10]),.I3(un1_x_8_0[11:11]),.I4(un1_x_9_0[11:11]),.I5(un1_x_9_0[12:12]),.O(un84_sop_0_0_0_6_6_0_axb_7)); defparam un84_sop_0_0_0_6_6_0_axb_7_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_6_6_0_axb_8_cZ(.I0(un1_x_7_0[9:9]),.I1(un1_x_7_0[10:10]),.I2(un1_x_8_0[11:11]),.I3(un1_x_8_0[12:12]),.I4(un1_x_9_0[12:12]),.I5(un1_x_9_0[13:13]),.O(un84_sop_0_0_0_6_6_0_axb_8)); defparam un84_sop_0_0_0_6_6_0_axb_8_cZ.INIT=64'h36C96C93C936936C; LUT6 un84_sop_0_0_0_6_6_0_axb_9_cZ(.I0(un1_x_7_0[10:10]),.I1(un1_x_7_0[11:11]),.I2(un1_x_8_0[12:12]),.I3(un1_x_8_0[13:13]),.I4(un1_x_9_0[13:13]),.I5(un1_x_9_0[14:14]),.O(un84_sop_0_0_0_6_6_0_axb_9)); defparam un84_sop_0_0_0_6_6_0_axb_9_cZ.INIT=64'h36C96C93C936936C; LUT4 un1_x_10_axb_11_cZ(.I0(x_8[6:6]),.I1(x_8[7:7]),.I2(x_8[5:5]),.I3(un1_x_10_5_c5),.O(un1_x_10_axb_11)); defparam un1_x_10_axb_11_cZ.INIT=16'hFEFF; LUT3_L un84_sop_0_0_0_11_0_axb_14_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[14:14]),.I2(un1_x_10_0_0[15:15]),.LO(un84_sop_0_0_0_11_0_axb_14)); defparam un84_sop_0_0_0_11_0_axb_14_cZ.INIT=8'h7E; LUT3 un84_sop_0_0_0_6_6_0_axb_14_cZ(.I0(un1_x_7_0[15:15]),.I1(un1_x_8_0[15:15]),.I2(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_14)); defparam un84_sop_0_0_0_6_6_0_axb_14_cZ.INIT=8'h7E; MUXCY_L un84_sop_0_0_0_11_0_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(un84_sop_0_0_0_0_11_7_axb_0_ci),.LO(un84_sop_0_0_0_11_0_cry_0_cy)); LUT1 un1_x_10_4_s_2_RNI13H1(.I0(un1_x_10_4[2:2]),.O(un1_x_10_s_2_sf)); defparam un1_x_10_4_s_2_RNI13H1.INIT=2'h2; LUT2_L un84_sop_0_0_0_1_axb_9_cZ(.I0(un1_x_16_0_0_0[14:14]),.I1(un1_x_15_0_0_0[14:14]),.LO(un84_sop_0_0_0_1_axb_9)); defparam un84_sop_0_0_0_1_axb_9_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_axb_8_cZ(.I0(un1_x_16_0_0_0[14:14]),.I1(un1_x_15_0_0_0[14:14]),.LO(un84_sop_0_0_0_1_axb_8)); defparam un84_sop_0_0_0_1_axb_8_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_axb_7_cZ(.I0(un1_x_16_0_0_0[13:13]),.I1(un1_x_15_0_0_0[13:13]),.LO(un84_sop_0_0_0_1_axb_7)); defparam un84_sop_0_0_0_1_axb_7_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_axb_6_cZ(.I0(un1_x_16_0_0_0[12:12]),.I1(un1_x_15_0_0_0[12:12]),.LO(un84_sop_0_0_0_1_axb_6)); defparam un84_sop_0_0_0_1_axb_6_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_axb_5_cZ(.I0(un1_x_16_0_0_0[11:11]),.I1(un1_x_15_0_0_0[11:11]),.LO(un84_sop_0_0_0_1_axb_5)); defparam un84_sop_0_0_0_1_axb_5_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_axb_4_cZ(.I0(un1_x_16_0_0_0[10:10]),.I1(un1_x_15_0_0_0[10:10]),.LO(un84_sop_0_0_0_1_axb_4)); defparam un84_sop_0_0_0_1_axb_4_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_axb_3_cZ(.I0(un1_x_16_0_0_0[9:9]),.I1(un1_x_15_0_0_0[9:9]),.LO(un84_sop_0_0_0_1_axb_3)); defparam un84_sop_0_0_0_1_axb_3_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_axb_2_cZ(.I0(un1_x_16_0_0_0[8:8]),.I1(un1_x_15_0_0_0[8:8]),.LO(un84_sop_0_0_0_1_axb_2)); defparam un84_sop_0_0_0_1_axb_2_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_axb_1_cZ(.I0(un1_x_16_0_0_0[7:7]),.I1(un1_x_15_0_0_0[7:7]),.LO(un84_sop_0_0_0_1_axb_1)); defparam un84_sop_0_0_0_1_axb_1_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_1_axb_0(.I0(x_12[0:0]),.I1(x_13[0:0]),.O(un84_sop_0_0_0_0_1[0:0])); defparam un84_sop_0_0_0_1_axb_0.INIT=4'h6; LUT1 un1_x_16_0_axb_8_cZ(.I0(x_13[7:7]),.O(un1_x_16_0_axb_8)); defparam un1_x_16_0_axb_8_cZ.INIT=2'h1; LUT1_L un1_x_11_0_axb_8_cZ(.I0(x_8[7:7]),.LO(un1_x_11_0_axb_8)); defparam un1_x_11_0_axb_8_cZ.INIT=2'h1; LUT1_L un1_x_11_0_axb_7_cZ(.I0(x_8[7:7]),.LO(un1_x_11_0_axb_7)); defparam un1_x_11_0_axb_7_cZ.INIT=2'h1; LUT1_L un1_x_11_0_axb_6_cZ(.I0(x_8[6:6]),.LO(un1_x_11_0_axb_6)); defparam un1_x_11_0_axb_6_cZ.INIT=2'h1; LUT1_L un1_x_11_0_axb_5_cZ(.I0(x_8[5:5]),.LO(un1_x_11_0_axb_5)); defparam un1_x_11_0_axb_5_cZ.INIT=2'h1; LUT1_L un1_x_11_0_axb_4_cZ(.I0(x_8[4:4]),.LO(un1_x_11_0_axb_4)); defparam un1_x_11_0_axb_4_cZ.INIT=2'h1; LUT1_L un1_x_11_0_axb_3_cZ(.I0(x_8[3:3]),.LO(un1_x_11_0_axb_3)); defparam un1_x_11_0_axb_3_cZ.INIT=2'h1; LUT1_L un1_x_11_0_axb_2_cZ(.I0(x_8[2:2]),.LO(un1_x_11_0_axb_2)); defparam un1_x_11_0_axb_2_cZ.INIT=2'h1; LUT1_L un1_x_11_0_axb_1_cZ(.I0(x_8[1:1]),.LO(un1_x_11_0_axb_1)); defparam un1_x_11_0_axb_1_cZ.INIT=2'h1; LUT1 un1_x_15_0_axb_8_cZ(.I0(x_12[7:7]),.O(un1_x_15_0_axb_8)); defparam un1_x_15_0_axb_8_cZ.INIT=2'h1; LUT1 un1_x_10_4_axb_10(.I0(x_8[7:7]),.O(un1_x_10_4[10:10])); defparam un1_x_10_4_axb_10.INIT=2'h2; LUT1 un1_x_10_4_axb_9(.I0(x_8[7:7]),.O(un1_x_10_4[9:9])); defparam un1_x_10_4_axb_9.INIT=2'h2; LUT2_L un84_sop_1_axb_14_cZ(.I0(un84_sop_1_6[14:14]),.I1(un84_sop_1_4[14:14]),.LO(un84_sop_1_axb_14)); defparam un84_sop_1_axb_14_cZ.INIT=4'h6; LUT2_L un84_sop_1_axb_13_cZ(.I0(un84_sop_1_6[14:14]),.I1(un84_sop_1_4[13:13]),.LO(un84_sop_1_axb_13)); defparam un84_sop_1_axb_13_cZ.INIT=4'h6; LUT2_L un84_sop_1_axb_12_cZ(.I0(un84_sop_1_6[12:12]),.I1(un84_sop_1_4[12:12]),.LO(un84_sop_1_axb_12)); defparam un84_sop_1_axb_12_cZ.INIT=4'h6; LUT2_L un84_sop_1_axb_11_cZ(.I0(un84_sop_1_6[11:11]),.I1(un84_sop_1_4[11:11]),.LO(un84_sop_1_axb_11)); defparam un84_sop_1_axb_11_cZ.INIT=4'h6; LUT2_L un84_sop_1_axb_10_cZ(.I0(un84_sop_1_6[10:10]),.I1(un84_sop_1_4[10:10]),.LO(un84_sop_1_axb_10)); defparam un84_sop_1_axb_10_cZ.INIT=4'h6; LUT2_L un84_sop_1_axb_9_cZ(.I0(un84_sop_1_6[9:9]),.I1(un84_sop_1_4[9:9]),.LO(un84_sop_1_axb_9)); defparam un84_sop_1_axb_9_cZ.INIT=4'h6; LUT2_L un84_sop_1_axb_8_cZ(.I0(un84_sop_1_6[8:8]),.I1(un84_sop_1_4[8:8]),.LO(un84_sop_1_axb_8)); defparam un84_sop_1_axb_8_cZ.INIT=4'h6; LUT2_L un84_sop_1_axb_7_cZ(.I0(un84_sop_1_6[7:7]),.I1(un84_sop_1_4[7:7]),.LO(un84_sop_1_axb_7)); defparam un84_sop_1_axb_7_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_0_11_7_axb_10_cZ(.I0(un1_x_11_0_0[14:14]),.I1(un84_sop_0_0_0_0_0[9:9]),.O(un84_sop_0_0_0_0_11_7_axb_10)); defparam un84_sop_0_0_0_0_11_7_axb_10_cZ.INIT=4'h6; LUT2 un84_sop_1_7_axb_14_cZ(.I0(un84_sop_0_0_0_0_5[14:14]),.I1(un1_x_4[15:15]),.O(un84_sop_1_7_axb_14)); defparam un84_sop_1_7_axb_14_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_14_cZ(.I0(un84_sop_0_0_0_1_6_6[14:14]),.I1(un84_sop_0_0_0_1_6_4[14:14]),.LO(un84_sop_0_0_0_1_6_axb_14)); defparam un84_sop_0_0_0_1_6_axb_14_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_13_cZ(.I0(un84_sop_0_0_0_1_6_6[13:13]),.I1(un84_sop_0_0_0_1_6_4[13:13]),.LO(un84_sop_0_0_0_1_6_axb_13)); defparam un84_sop_0_0_0_1_6_axb_13_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_12_cZ(.I0(un84_sop_0_0_0_1_6_6[12:12]),.I1(un84_sop_0_0_0_1_6_4[12:12]),.LO(un84_sop_0_0_0_1_6_axb_12)); defparam un84_sop_0_0_0_1_6_axb_12_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_11_cZ(.I0(un84_sop_0_0_0_1_6_6[11:11]),.I1(un84_sop_0_0_0_1_6_4[11:11]),.LO(un84_sop_0_0_0_1_6_axb_11)); defparam un84_sop_0_0_0_1_6_axb_11_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_10_cZ(.I0(un84_sop_0_0_0_1_6_6[10:10]),.I1(un84_sop_0_0_0_1_6_4[10:10]),.LO(un84_sop_0_0_0_1_6_axb_10)); defparam un84_sop_0_0_0_1_6_axb_10_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_9_cZ(.I0(un84_sop_0_0_0_1_6_6[9:9]),.I1(un84_sop_0_0_0_1_6_4[9:9]),.LO(un84_sop_0_0_0_1_6_axb_9)); defparam un84_sop_0_0_0_1_6_axb_9_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_8_cZ(.I0(un84_sop_0_0_0_1_6_6[8:8]),.I1(un84_sop_0_0_0_1_6_4[8:8]),.LO(un84_sop_0_0_0_1_6_axb_8)); defparam un84_sop_0_0_0_1_6_axb_8_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_7_cZ(.I0(un84_sop_0_0_0_1_6_6[7:7]),.I1(un84_sop_0_0_0_1_6_4[7:7]),.LO(un84_sop_0_0_0_1_6_axb_7)); defparam un84_sop_0_0_0_1_6_axb_7_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_6_cZ(.I0(un84_sop_0_0_0_1_6_6[6:6]),.I1(un84_sop_0_0_0_1_6_4[6:6]),.LO(un84_sop_0_0_0_1_6_axb_6)); defparam un84_sop_0_0_0_1_6_axb_6_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_5_cZ(.I0(un84_sop_0_0_0_1_6_6[5:5]),.I1(un84_sop_0_0_0_1_6_4[5:5]),.LO(un84_sop_0_0_0_1_6_axb_5)); defparam un84_sop_0_0_0_1_6_axb_5_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_4_cZ(.I0(un84_sop_0_0_0_1_6_6[4:4]),.I1(un84_sop_0_0_0_1_6_4[4:4]),.LO(un84_sop_0_0_0_1_6_axb_4)); defparam un84_sop_0_0_0_1_6_axb_4_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_3_cZ(.I0(un84_sop_0_0_0_1_6_4[3:3]),.I1(un84_sop_0_0_0_1_6_6[3:3]),.LO(un84_sop_0_0_0_1_6_axb_3)); defparam un84_sop_0_0_0_1_6_axb_3_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_2_cZ(.I0(un84_sop_0_0_0_1_6_4[2:2]),.I1(un84_sop_0_0_0_1_6_6[2:2]),.LO(un84_sop_0_0_0_1_6_axb_2)); defparam un84_sop_0_0_0_1_6_axb_2_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_1_6_axb_1_cZ(.I0(un84_sop_0_0_0_1_6_4[1:1]),.I1(un84_sop_0_0_0_1_6_6[1:1]),.LO(un84_sop_0_0_0_1_6_axb_1)); defparam un84_sop_0_0_0_1_6_axb_1_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_4_axb_14_cZ(.I0(un1_x_6_0[15:15]),.I1(un84_sop_0_0_0_1_6_8[14:14]),.O(un84_sop_0_0_0_1_6_4_axb_14)); defparam un84_sop_0_0_0_1_6_4_axb_14_cZ.INIT=4'h6; LUT2 un1_x_10_axb_3_cZ(.I0(x_8[0:0]),.I1(un1_x_10_4[3:3]),.O(un1_x_10_axb_3)); defparam un1_x_10_axb_3_cZ.INIT=4'h6; LUT2 un84_sop_0_0_0_1_6_8_axb_11_cZ(.I0(un84_sop_0_0_0_10_0[14:14]),.I1(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_11)); defparam un84_sop_0_0_0_1_6_8_axb_11_cZ.INIT=4'h6; LUT2_L un84_sop_0_0_0_11_0_axb_0_cZ(.I0(x_8[0:0]),.I1(un84_sop_0_0_0_0_11_6[0:0]),.LO(un84_sop_0_0_0_11_0_axb_0)); defparam un84_sop_0_0_0_11_0_axb_0_cZ.INIT=4'h6; LUT4 un1_x_0_0_ac0_5(.I0(x_0[3:3]),.I1(x_0[2:2]),.I2(x_0[1:1]),.I3(x_0[0:0]),.O(un1_x_0_0_c4)); defparam un1_x_0_0_ac0_5.INIT=16'h0001; LUT3 un84_sop_0_0_0_11_6_0_o5_11_cZ(.I0(un1_x_12_0_0[15:15]),.I1(un1_x_14_0_0[15:15]),.I2(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_o5_11)); defparam un84_sop_0_0_0_11_6_0_o5_11_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_6_0_o5_10_cZ(.I0(un1_x_12_0_0[14:14]),.I1(un1_x_14_0_0[14:14]),.I2(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_o5_10)); defparam un84_sop_0_0_0_11_6_0_o5_10_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_6_0_o5_9_cZ(.I0(un1_x_12_0_0[13:13]),.I1(un1_x_13_0_0[14:14]),.I2(un1_x_14_0_0[13:13]),.O(un84_sop_0_0_0_11_6_0_o5_9)); defparam un84_sop_0_0_0_11_6_0_o5_9_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_6_0_o5_8_cZ(.I0(un1_x_12_0_0[12:12]),.I1(un1_x_13_0_0[13:13]),.I2(un1_x_14_0_0[12:12]),.O(un84_sop_0_0_0_11_6_0_o5_8)); defparam un84_sop_0_0_0_11_6_0_o5_8_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_6_0_o5_7_cZ(.I0(un1_x_12_0_0[11:11]),.I1(un1_x_13_0_0[12:12]),.I2(un1_x_14_0_0[11:11]),.O(un84_sop_0_0_0_11_6_0_o5_7)); defparam un84_sop_0_0_0_11_6_0_o5_7_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_6_0_o5_6_cZ(.I0(un1_x_12_0_0[10:10]),.I1(un1_x_13_0_0[11:11]),.I2(un1_x_14_0_0[10:10]),.O(un84_sop_0_0_0_11_6_0_o5_6)); defparam un84_sop_0_0_0_11_6_0_o5_6_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_6_0_o5_5_cZ(.I0(un1_x_12_0_0[9:9]),.I1(un1_x_13_0_0[10:10]),.I2(un1_x_14_0_0[9:9]),.O(un84_sop_0_0_0_11_6_0_o5_5)); defparam un84_sop_0_0_0_11_6_0_o5_5_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_6_0_o5_4_cZ(.I0(un1_x_12_0_0[8:8]),.I1(un1_x_13_0_0[9:9]),.I2(un1_x_14_0_0[8:8]),.O(un84_sop_0_0_0_11_6_0_o5_4)); defparam un84_sop_0_0_0_11_6_0_o5_4_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_6_0_o5_3_cZ(.I0(un1_x_12_0_0[7:7]),.I1(un1_x_13_0_0[8:8]),.I2(un1_x_14_0_0[7:7]),.O(un84_sop_0_0_0_11_6_0_o5_3)); defparam un84_sop_0_0_0_11_6_0_o5_3_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_6_0_o5_2_cZ(.I0(un1_x_12_0_0[6:6]),.I1(un1_x_13_0_0[7:7]),.I2(un1_x_14_0_0[6:6]),.O(un84_sop_0_0_0_11_6_0_o5_2)); defparam un84_sop_0_0_0_11_6_0_o5_2_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_0_o5_12_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[12:12]),.I2(un1_x_10_0_0[15:15]),.O(un84_sop_0_0_0_11_0_o5_12)); defparam un84_sop_0_0_0_11_0_o5_12_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_0_o5_11_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[11:11]),.I2(un1_x_10_0_0[15:15]),.O(un84_sop_0_0_0_11_0_o5_11)); defparam un84_sop_0_0_0_11_0_o5_11_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_0_o5_10_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[10:10]),.I2(un1_x_10_0_0[14:14]),.O(un84_sop_0_0_0_11_0_o5_10)); defparam un84_sop_0_0_0_11_0_o5_10_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_0_o5_9_cZ(.I0(un84_sop_0_0_0_0_11_7[9:9]),.I1(un84_sop_0_0_0_0_11_6[9:9]),.I2(un1_x_10_0_0[13:13]),.O(un84_sop_0_0_0_11_0_o5_9)); defparam un84_sop_0_0_0_11_0_o5_9_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_0_o5_8_cZ(.I0(un84_sop_0_0_0_0_11_7[8:8]),.I1(un84_sop_0_0_0_0_11_6[8:8]),.I2(un1_x_10_0_0[12:12]),.O(un84_sop_0_0_0_11_0_o5_8)); defparam un84_sop_0_0_0_11_0_o5_8_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_0_o5_7_cZ(.I0(un84_sop_0_0_0_0_11_7[7:7]),.I1(un84_sop_0_0_0_0_11_6[7:7]),.I2(un1_x_10_0_0[11:11]),.O(un84_sop_0_0_0_11_0_o5_7)); defparam un84_sop_0_0_0_11_0_o5_7_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_0_o5_6_cZ(.I0(un84_sop_0_0_0_0_11_7[6:6]),.I1(un84_sop_0_0_0_0_11_6[6:6]),.I2(un1_x_10_0_0[10:10]),.O(un84_sop_0_0_0_11_0_o5_6)); defparam un84_sop_0_0_0_11_0_o5_6_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_0_o5_5_cZ(.I0(un84_sop_0_0_0_0_11_7[5:5]),.I1(un84_sop_0_0_0_0_11_6[5:5]),.I2(un1_x_10_0_0[9:9]),.O(un84_sop_0_0_0_11_0_o5_5)); defparam un84_sop_0_0_0_11_0_o5_5_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_0_o5_4_cZ(.I0(un84_sop_0_0_0_0_11_7[4:4]),.I1(un84_sop_0_0_0_0_11_6[4:4]),.I2(un1_x_10_0_0[8:8]),.O(un84_sop_0_0_0_11_0_o5_4)); defparam un84_sop_0_0_0_11_0_o5_4_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_0_o5_3_cZ(.I0(un84_sop_0_0_0_0_11_7[3:3]),.I1(un1_x_10_axb_3),.I2(un84_sop_0_0_0_0_11_6[3:3]),.O(un84_sop_0_0_0_11_0_o5_3)); defparam un84_sop_0_0_0_11_0_o5_3_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_11_0_o5_2_cZ(.I0(un84_sop_0_0_0_0_11_7[2:2]),.I1(un84_sop_0_0_0_0_11_6[2:2]),.I2(un1_x_10_s_2_sf),.O(un84_sop_0_0_0_11_0_o5_2)); defparam un84_sop_0_0_0_11_0_o5_2_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_6_6_0_o5_12_cZ(.I0(un1_x_7_0[14:14]),.I1(un1_x_8_0[15:15]),.I2(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_o5_12)); defparam un84_sop_0_0_0_6_6_0_o5_12_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_6_6_0_o5_11_cZ(.I0(un1_x_7_0[13:13]),.I1(un1_x_8_0[15:15]),.I2(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_o5_11)); defparam un84_sop_0_0_0_6_6_0_o5_11_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_6_6_0_o5_10_cZ(.I0(un1_x_7_0[12:12]),.I1(un1_x_8_0[14:14]),.I2(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_o5_10)); defparam un84_sop_0_0_0_6_6_0_o5_10_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_6_6_0_o5_9_cZ(.I0(un1_x_7_0[11:11]),.I1(un1_x_8_0[13:13]),.I2(un1_x_9_0[14:14]),.O(un84_sop_0_0_0_6_6_0_o5_9)); defparam un84_sop_0_0_0_6_6_0_o5_9_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_6_6_0_o5_8_cZ(.I0(un1_x_7_0[10:10]),.I1(un1_x_8_0[12:12]),.I2(un1_x_9_0[13:13]),.O(un84_sop_0_0_0_6_6_0_o5_8)); defparam un84_sop_0_0_0_6_6_0_o5_8_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_6_6_0_o5_7_cZ(.I0(un1_x_7_0[9:9]),.I1(un1_x_8_0[11:11]),.I2(un1_x_9_0[12:12]),.O(un84_sop_0_0_0_6_6_0_o5_7)); defparam un84_sop_0_0_0_6_6_0_o5_7_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_6_6_0_o5_6_cZ(.I0(un1_x_7_0[8:8]),.I1(un1_x_8_0[10:10]),.I2(un1_x_9_0[11:11]),.O(un84_sop_0_0_0_6_6_0_o5_6)); defparam un84_sop_0_0_0_6_6_0_o5_6_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_6_6_0_o5_5_cZ(.I0(un1_x_7_0[7:7]),.I1(un1_x_8_0[9:9]),.I2(un1_x_9_0[10:10]),.O(un84_sop_0_0_0_6_6_0_o5_5)); defparam un84_sop_0_0_0_6_6_0_o5_5_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_6_6_0_o5_4_cZ(.I0(un1_x_7_0[6:6]),.I1(un1_x_8_0[8:8]),.I2(un1_x_9_0[9:9]),.O(un84_sop_0_0_0_6_6_0_o5_4)); defparam un84_sop_0_0_0_6_6_0_o5_4_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_6_6_0_o5_3_cZ(.I0(un1_x_7_0[5:5]),.I1(un1_x_8_0[7:7]),.I2(un1_x_9_0[8:8]),.O(un84_sop_0_0_0_6_6_0_o5_3)); defparam un84_sop_0_0_0_6_6_0_o5_3_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_6_6_0_o5_2_cZ(.I0(un1_x_7_0[4:4]),.I1(un1_x_8_0[6:6]),.I2(un1_x_9_0[7:7]),.O(un84_sop_0_0_0_6_6_0_o5_2)); defparam un84_sop_0_0_0_6_6_0_o5_2_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_1_6_8_o5_7_cZ(.I0(un84_sop_0_0_0_10_0[10:10]),.I1(x_4[5:5]),.I2(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_o5_7)); defparam un84_sop_0_0_0_1_6_8_o5_7_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_1_6_8_o5_6_cZ(.I0(un84_sop_0_0_0_10_0[9:9]),.I1(x_4[6:6]),.I2(x_4[4:4]),.O(un84_sop_0_0_0_1_6_8_o5_6)); defparam un84_sop_0_0_0_1_6_8_o5_6_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_1_6_8_o5_5_cZ(.I0(un84_sop_0_0_0_10_0[8:8]),.I1(x_4[3:3]),.I2(x_4[5:5]),.O(un84_sop_0_0_0_1_6_8_o5_5)); defparam un84_sop_0_0_0_1_6_8_o5_5_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_1_6_8_o5_4_cZ(.I0(un84_sop_0_0_0_10_0[7:7]),.I1(x_4[2:2]),.I2(x_4[4:4]),.O(un84_sop_0_0_0_1_6_8_o5_4)); defparam un84_sop_0_0_0_1_6_8_o5_4_cZ.INIT=8'hE8; LUT3 un84_sop_0_0_0_1_6_8_o5_3_cZ(.I0(un84_sop_0_0_0_10_0[6:6]),.I1(x_4[1:1]),.I2(x_4[3:3]),.O(un84_sop_0_0_0_1_6_8_o5_3)); defparam un84_sop_0_0_0_1_6_8_o5_3_cZ.INIT=8'hE8; LUT3 un84_sop_1_6_0_o5_11_cZ(.I0(un1_x_1[15:15]),.I1(un1_x_3[15:15]),.I2(un1_x_2[15:15]),.O(un84_sop_1_6_0_o5_11)); defparam un84_sop_1_6_0_o5_11_cZ.INIT=8'hE8; LUT3 un84_sop_1_6_0_o5_10_cZ(.I0(un1_x_1[14:14]),.I1(un1_x_3[14:14]),.I2(un1_x_2[15:15]),.O(un84_sop_1_6_0_o5_10)); defparam un84_sop_1_6_0_o5_10_cZ.INIT=8'hE8; LUT3 un84_sop_1_6_0_o5_9_cZ(.I0(un1_x_1[13:13]),.I1(un1_x_2[14:14]),.I2(un1_x_3[13:13]),.O(un84_sop_1_6_0_o5_9)); defparam un84_sop_1_6_0_o5_9_cZ.INIT=8'hE8; LUT3 un84_sop_1_6_0_o5_8_cZ(.I0(un1_x_1[12:12]),.I1(un1_x_2[13:13]),.I2(un1_x_3[12:12]),.O(un84_sop_1_6_0_o5_8)); defparam un84_sop_1_6_0_o5_8_cZ.INIT=8'hE8; LUT3 un84_sop_1_6_0_o5_7_cZ(.I0(un1_x_1[11:11]),.I1(un1_x_2[12:12]),.I2(un1_x_3[11:11]),.O(un84_sop_1_6_0_o5_7)); defparam un84_sop_1_6_0_o5_7_cZ.INIT=8'hE8; LUT3 un84_sop_1_6_0_o5_6_cZ(.I0(un1_x_1[10:10]),.I1(un1_x_2[11:11]),.I2(un1_x_3[10:10]),.O(un84_sop_1_6_0_o5_6)); defparam un84_sop_1_6_0_o5_6_cZ.INIT=8'hE8; LUT3 un84_sop_1_6_0_o5_5_cZ(.I0(un1_x_1[9:9]),.I1(un1_x_2[10:10]),.I2(un1_x_3[9:9]),.O(un84_sop_1_6_0_o5_5)); defparam un84_sop_1_6_0_o5_5_cZ.INIT=8'hE8; LUT3 un84_sop_1_6_0_o5_4_cZ(.I0(un1_x_1[8:8]),.I1(un1_x_2[9:9]),.I2(un1_x_3[8:8]),.O(un84_sop_1_6_0_o5_4)); defparam un84_sop_1_6_0_o5_4_cZ.INIT=8'hE8; LUT3 un84_sop_1_6_0_o5_3_cZ(.I0(un1_x_1[7:7]),.I1(un1_x_2[8:8]),.I2(un1_x_3[7:7]),.O(un84_sop_1_6_0_o5_3)); defparam un84_sop_1_6_0_o5_3_cZ.INIT=8'hE8; LUT3 un84_sop_1_6_0_o5_2_cZ(.I0(un1_x_1[6:6]),.I1(un1_x_2[7:7]),.I2(un1_x_3[6:6]),.O(un84_sop_1_6_0_o5_2)); defparam un84_sop_1_6_0_o5_2_cZ.INIT=8'hE8; LUT5 un84_sop_1_4_axb_3_cZ(.I0(x_0[3:3]),.I1(x_0[2:2]),.I2(x_0[1:1]),.I3(x_0[0:0]),.I4(un84_sop_1_7[3:3]),.O(un84_sop_1_4_axb_3)); defparam un84_sop_1_4_axb_3_cZ.INIT=32'hAAA95556; LUT5 un1_x_10_5_ac0_7(.I0(x_8[4:4]),.I1(x_8[3:3]),.I2(x_8[2:2]),.I3(x_8[1:1]),.I4(x_8[0:0]),.O(un1_x_10_5_c5)); defparam un1_x_10_5_ac0_7.INIT=32'h00000001; LUT5 un1_x_10_axb_6_cZ(.I0(x_8[3:3]),.I1(x_8[2:2]),.I2(x_8[1:1]),.I3(x_8[0:0]),.I4(un1_x_10_4[6:6]),.O(un1_x_10_axb_6)); defparam un1_x_10_axb_6_cZ.INIT=32'hAAA95556; LUT6 un1_x_10_axb_7_cZ(.I0(x_8[4:4]),.I1(x_8[3:3]),.I2(x_8[2:2]),.I3(x_8[1:1]),.I4(x_8[0:0]),.I5(un1_x_10_4[7:7]),.O(un1_x_10_axb_7)); defparam un1_x_10_axb_7_cZ.INIT=64'hAAAAAAA955555556; LUT5 un84_sop_1_4_axb_6_cZ(.I0(x_0[6:6]),.I1(x_0[5:5]),.I2(x_0[4:4]),.I3(un1_x_0_0_c4),.I4(un84_sop_1_7[6:6]),.O(un84_sop_1_4_axb_6)); defparam un84_sop_1_4_axb_6_cZ.INIT=32'hA9AA5655; LUT6 un84_sop_1_4_axb_7_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[7:7]),.O(un84_sop_1_4_axb_7)); defparam un84_sop_1_4_axb_7_cZ.INIT=64'hAAA9AAAA55565555; LUT6 un84_sop_1_4_axb_14_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[14:14]),.O(un84_sop_1_4_axb_14)); defparam un84_sop_1_4_axb_14_cZ.INIT=64'hAAABAAAA55545555; LUT6 un84_sop_1_4_axb_13_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[13:13]),.O(un84_sop_1_4_axb_13)); defparam un84_sop_1_4_axb_13_cZ.INIT=64'hAAABAAAA55545555; LUT6 un84_sop_1_4_axb_12_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[12:12]),.O(un84_sop_1_4_axb_12)); defparam un84_sop_1_4_axb_12_cZ.INIT=64'hAAABAAAA55545555; LUT6 un84_sop_1_4_axb_11_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[11:11]),.O(un84_sop_1_4_axb_11)); defparam un84_sop_1_4_axb_11_cZ.INIT=64'hAAABAAAA55545555; LUT6 un84_sop_1_4_axb_10_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[10:10]),.O(un84_sop_1_4_axb_10)); defparam un84_sop_1_4_axb_10_cZ.INIT=64'hAAABAAAA55545555; LUT6 un84_sop_1_4_axb_9_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[9:9]),.O(un84_sop_1_4_axb_9)); defparam un84_sop_1_4_axb_9_cZ.INIT=64'hAAABAAAA55545555; LUT6 un84_sop_1_4_axb_8_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[8:8]),.O(un84_sop_1_4_axb_8)); defparam un84_sop_1_4_axb_8_cZ.INIT=64'hAAABAAAA55545555; LUT2 x_16_pipe_0_0_0_RNI0KBH(.I0(un84_sop_0_0_0_0_5[0:0]),.I1(un1_x_4[2:2]),.O(un84_sop_1_7[0:0])); defparam x_16_pipe_0_0_0_RNI0KBH.INIT=4'h6; XORCY un84_sop_0_0_0_1_s_9(.LI(un84_sop_0_0_0_1_axb_9),.CI(un84_sop_0_0_0_1_cry_8),.O(un84_sop_0_0_0_0_1[9:9])); XORCY un84_sop_0_0_0_1_s_8(.LI(un84_sop_0_0_0_1_axb_8),.CI(un84_sop_0_0_0_1_cry_7),.O(un84_sop_0_0_0_0_1[8:8])); MUXCY_L un84_sop_0_0_0_1_cry_8_cZ(.DI(un1_x_15_0_0_0[14:14]),.CI(un84_sop_0_0_0_1_cry_7),.S(un84_sop_0_0_0_1_axb_8),.LO(un84_sop_0_0_0_1_cry_8)); XORCY un84_sop_0_0_0_1_s_7(.LI(un84_sop_0_0_0_1_axb_7),.CI(un84_sop_0_0_0_1_cry_6),.O(un84_sop_0_0_0_0_1[7:7])); MUXCY_L un84_sop_0_0_0_1_cry_7_cZ(.DI(un1_x_15_0_0_0[13:13]),.CI(un84_sop_0_0_0_1_cry_6),.S(un84_sop_0_0_0_1_axb_7),.LO(un84_sop_0_0_0_1_cry_7)); XORCY un84_sop_0_0_0_1_s_6(.LI(un84_sop_0_0_0_1_axb_6),.CI(un84_sop_0_0_0_1_cry_5),.O(un84_sop_0_0_0_0_1[6:6])); MUXCY_L un84_sop_0_0_0_1_cry_6_cZ(.DI(un1_x_15_0_0_0[12:12]),.CI(un84_sop_0_0_0_1_cry_5),.S(un84_sop_0_0_0_1_axb_6),.LO(un84_sop_0_0_0_1_cry_6)); XORCY un84_sop_0_0_0_1_s_5(.LI(un84_sop_0_0_0_1_axb_5),.CI(un84_sop_0_0_0_1_cry_4),.O(un84_sop_0_0_0_0_1[5:5])); MUXCY_L un84_sop_0_0_0_1_cry_5_cZ(.DI(un1_x_15_0_0_0[11:11]),.CI(un84_sop_0_0_0_1_cry_4),.S(un84_sop_0_0_0_1_axb_5),.LO(un84_sop_0_0_0_1_cry_5)); XORCY un84_sop_0_0_0_1_s_4(.LI(un84_sop_0_0_0_1_axb_4),.CI(un84_sop_0_0_0_1_cry_3),.O(un84_sop_0_0_0_0_1[4:4])); MUXCY_L un84_sop_0_0_0_1_cry_4_cZ(.DI(un1_x_15_0_0_0[10:10]),.CI(un84_sop_0_0_0_1_cry_3),.S(un84_sop_0_0_0_1_axb_4),.LO(un84_sop_0_0_0_1_cry_4)); XORCY un84_sop_0_0_0_1_s_3(.LI(un84_sop_0_0_0_1_axb_3),.CI(un84_sop_0_0_0_1_cry_2),.O(un84_sop_0_0_0_0_1[3:3])); MUXCY_L un84_sop_0_0_0_1_cry_3_cZ(.DI(un1_x_15_0_0_0[9:9]),.CI(un84_sop_0_0_0_1_cry_2),.S(un84_sop_0_0_0_1_axb_3),.LO(un84_sop_0_0_0_1_cry_3)); XORCY un84_sop_0_0_0_1_s_2(.LI(un84_sop_0_0_0_1_axb_2),.CI(un84_sop_0_0_0_1_cry_1),.O(un84_sop_0_0_0_0_1[2:2])); MUXCY_L un84_sop_0_0_0_1_cry_2_cZ(.DI(un1_x_15_0_0_0[8:8]),.CI(un84_sop_0_0_0_1_cry_1),.S(un84_sop_0_0_0_1_axb_2),.LO(un84_sop_0_0_0_1_cry_2)); XORCY un84_sop_0_0_0_1_s_1(.LI(un84_sop_0_0_0_1_axb_1),.CI(un84_sop_0_0_0_1_cry_0),.O(un84_sop_0_0_0_0_1[1:1])); MUXCY_L un84_sop_0_0_0_1_cry_1_cZ(.DI(un1_x_15_0_0_0[7:7]),.CI(un84_sop_0_0_0_1_cry_0),.S(un84_sop_0_0_0_1_axb_1),.LO(un84_sop_0_0_0_1_cry_1)); MUXCY_L un84_sop_0_0_0_1_cry_0_cZ(.DI(x_13[0:0]),.CI(GND),.S(un84_sop_0_0_0_0_1[0:0]),.LO(un84_sop_0_0_0_1_cry_0)); XORCY un1_x_16_0_s_8(.LI(un1_x_16_0_axb_8),.CI(un1_x_16_0_cry_7),.O(un1_x_16_0_0_0[14:14])); XORCY un1_x_16_0_s_7(.LI(un1_x_16_0_axb_7),.CI(un1_x_16_0_cry_6),.O(un1_x_16_0_0_0[13:13])); MUXCY_L un1_x_16_0_cry_7_cZ(.DI(GND),.CI(un1_x_16_0_cry_6),.S(un1_x_16_0_axb_7),.LO(un1_x_16_0_cry_7)); XORCY un1_x_16_0_s_6(.LI(un1_x_16_0_axb_6),.CI(un1_x_16_0_cry_5),.O(un1_x_16_0_0_0[12:12])); MUXCY_L un1_x_16_0_cry_6_cZ(.DI(GND),.CI(un1_x_16_0_cry_5),.S(un1_x_16_0_axb_6),.LO(un1_x_16_0_cry_6)); XORCY un1_x_16_0_s_5(.LI(un1_x_16_0_axb_5),.CI(un1_x_16_0_cry_4),.O(un1_x_16_0_0_0[11:11])); MUXCY_L un1_x_16_0_cry_5_cZ(.DI(GND),.CI(un1_x_16_0_cry_4),.S(un1_x_16_0_axb_5),.LO(un1_x_16_0_cry_5)); XORCY un1_x_16_0_s_4(.LI(un1_x_16_0_axb_4),.CI(un1_x_16_0_cry_3),.O(un1_x_16_0_0_0[10:10])); MUXCY_L un1_x_16_0_cry_4_cZ(.DI(GND),.CI(un1_x_16_0_cry_3),.S(un1_x_16_0_axb_4),.LO(un1_x_16_0_cry_4)); XORCY un1_x_16_0_s_3(.LI(un1_x_16_0_axb_3),.CI(un1_x_16_0_cry_2),.O(un1_x_16_0_0_0[9:9])); MUXCY_L un1_x_16_0_cry_3_cZ(.DI(GND),.CI(un1_x_16_0_cry_2),.S(un1_x_16_0_axb_3),.LO(un1_x_16_0_cry_3)); XORCY un1_x_16_0_s_2(.LI(un1_x_16_0_axb_2),.CI(un1_x_16_0_cry_1),.O(un1_x_16_0_0_0[8:8])); MUXCY_L un1_x_16_0_cry_2_cZ(.DI(GND),.CI(un1_x_16_0_cry_1),.S(un1_x_16_0_axb_2),.LO(un1_x_16_0_cry_2)); XORCY un1_x_16_0_s_1(.LI(un1_x_16_0_axb_1),.CI(un1_x_16_0_cry_0),.O(un1_x_16_0_0_0[7:7])); MUXCY_L un1_x_16_0_cry_1_cZ(.DI(GND),.CI(un1_x_16_0_cry_0),.S(un1_x_16_0_axb_1),.LO(un1_x_16_0_cry_1)); MUXCY_L un1_x_16_0_cry_0_cZ(.DI(GND),.CI(VCC),.S(un1_x_16_0_axb_0),.LO(un1_x_16_0_cry_0)); XORCY un1_x_11_0_s_8(.LI(un1_x_11_0_axb_8),.CI(un1_x_11_0_cry_7),.O(un1_x_11_0_0_0[14:14])); XORCY un1_x_11_0_s_7(.LI(un1_x_11_0_axb_7),.CI(un1_x_11_0_cry_6),.O(un1_x_11_0_0_0[13:13])); MUXCY_L un1_x_11_0_cry_7_cZ(.DI(GND),.CI(un1_x_11_0_cry_6),.S(un1_x_11_0_axb_7),.LO(un1_x_11_0_cry_7)); XORCY un1_x_11_0_s_6(.LI(un1_x_11_0_axb_6),.CI(un1_x_11_0_cry_5),.O(un1_x_11_0_0_0[12:12])); MUXCY_L un1_x_11_0_cry_6_cZ(.DI(GND),.CI(un1_x_11_0_cry_5),.S(un1_x_11_0_axb_6),.LO(un1_x_11_0_cry_6)); XORCY un1_x_11_0_s_5(.LI(un1_x_11_0_axb_5),.CI(un1_x_11_0_cry_4),.O(un1_x_11_0_0_0[11:11])); MUXCY_L un1_x_11_0_cry_5_cZ(.DI(GND),.CI(un1_x_11_0_cry_4),.S(un1_x_11_0_axb_5),.LO(un1_x_11_0_cry_5)); XORCY un1_x_11_0_s_4(.LI(un1_x_11_0_axb_4),.CI(un1_x_11_0_cry_3),.O(un1_x_11_0_0_0[10:10])); MUXCY_L un1_x_11_0_cry_4_cZ(.DI(GND),.CI(un1_x_11_0_cry_3),.S(un1_x_11_0_axb_4),.LO(un1_x_11_0_cry_4)); XORCY un1_x_11_0_s_3(.LI(un1_x_11_0_axb_3),.CI(un1_x_11_0_cry_2),.O(un1_x_11_0_0_0[9:9])); MUXCY_L un1_x_11_0_cry_3_cZ(.DI(GND),.CI(un1_x_11_0_cry_2),.S(un1_x_11_0_axb_3),.LO(un1_x_11_0_cry_3)); XORCY un1_x_11_0_s_2(.LI(un1_x_11_0_axb_2),.CI(un1_x_11_0_cry_1),.O(un1_x_11_0_0_0[8:8])); MUXCY_L un1_x_11_0_cry_2_cZ(.DI(GND),.CI(un1_x_11_0_cry_1),.S(un1_x_11_0_axb_2),.LO(un1_x_11_0_cry_2)); XORCY un1_x_11_0_s_1(.LI(un1_x_11_0_axb_1),.CI(un1_x_11_0_cry_0),.O(un1_x_11_0_0_0[7:7])); MUXCY_L un1_x_11_0_cry_1_cZ(.DI(GND),.CI(un1_x_11_0_cry_0),.S(un1_x_11_0_axb_1),.LO(un1_x_11_0_cry_1)); MUXCY_L un1_x_11_0_cry_0_cZ(.DI(GND),.CI(VCC),.S(un1_x_11_0_axb_0),.LO(un1_x_11_0_cry_0)); XORCY un1_x_15_0_s_8(.LI(un1_x_15_0_axb_8),.CI(un1_x_15_0_cry_7),.O(un1_x_15_0_0_0[14:14])); XORCY un1_x_15_0_s_7(.LI(un1_x_15_0_axb_7),.CI(un1_x_15_0_cry_6),.O(un1_x_15_0_0_0[13:13])); MUXCY_L un1_x_15_0_cry_7_cZ(.DI(GND),.CI(un1_x_15_0_cry_6),.S(un1_x_15_0_axb_7),.LO(un1_x_15_0_cry_7)); XORCY un1_x_15_0_s_6(.LI(un1_x_15_0_axb_6),.CI(un1_x_15_0_cry_5),.O(un1_x_15_0_0_0[12:12])); MUXCY_L un1_x_15_0_cry_6_cZ(.DI(GND),.CI(un1_x_15_0_cry_5),.S(un1_x_15_0_axb_6),.LO(un1_x_15_0_cry_6)); XORCY un1_x_15_0_s_5(.LI(un1_x_15_0_axb_5),.CI(un1_x_15_0_cry_4),.O(un1_x_15_0_0_0[11:11])); MUXCY_L un1_x_15_0_cry_5_cZ(.DI(GND),.CI(un1_x_15_0_cry_4),.S(un1_x_15_0_axb_5),.LO(un1_x_15_0_cry_5)); XORCY un1_x_15_0_s_4(.LI(un1_x_15_0_axb_4),.CI(un1_x_15_0_cry_3),.O(un1_x_15_0_0_0[10:10])); MUXCY_L un1_x_15_0_cry_4_cZ(.DI(GND),.CI(un1_x_15_0_cry_3),.S(un1_x_15_0_axb_4),.LO(un1_x_15_0_cry_4)); XORCY un1_x_15_0_s_3(.LI(un1_x_15_0_axb_3),.CI(un1_x_15_0_cry_2),.O(un1_x_15_0_0_0[9:9])); MUXCY_L un1_x_15_0_cry_3_cZ(.DI(GND),.CI(un1_x_15_0_cry_2),.S(un1_x_15_0_axb_3),.LO(un1_x_15_0_cry_3)); XORCY un1_x_15_0_s_2(.LI(un1_x_15_0_axb_2),.CI(un1_x_15_0_cry_1),.O(un1_x_15_0_0_0[8:8])); MUXCY_L un1_x_15_0_cry_2_cZ(.DI(GND),.CI(un1_x_15_0_cry_1),.S(un1_x_15_0_axb_2),.LO(un1_x_15_0_cry_2)); XORCY un1_x_15_0_s_1(.LI(un1_x_15_0_axb_1),.CI(un1_x_15_0_cry_0),.O(un1_x_15_0_0_0[7:7])); MUXCY_L un1_x_15_0_cry_1_cZ(.DI(GND),.CI(un1_x_15_0_cry_0),.S(un1_x_15_0_axb_1),.LO(un1_x_15_0_cry_1)); MUXCY_L un1_x_15_0_cry_0_cZ(.DI(GND),.CI(VCC),.S(un1_x_15_0_axb_0),.LO(un1_x_15_0_cry_0)); XORCY un1_x_10_4_s_8(.LI(un1_x_10_4_s_8_false),.CI(un1_x_10_4_cry_7),.O(un1_x_10_4[8:8])); XORCY un1_x_10_4_s_7(.LI(un1_x_10_4_axb_7),.CI(un1_x_10_4_cry_6),.O(un1_x_10_4[7:7])); MUXCY_L un1_x_10_4_cry_7_cZ(.DI(x_8[6:6]),.CI(un1_x_10_4_cry_6),.S(un1_x_10_4_axb_7),.LO(un1_x_10_4_cry_7)); XORCY un1_x_10_4_s_6(.LI(un1_x_10_4_axb_6),.CI(un1_x_10_4_cry_5),.O(un1_x_10_4[6:6])); MUXCY_L un1_x_10_4_cry_6_cZ(.DI(x_8[5:5]),.CI(un1_x_10_4_cry_5),.S(un1_x_10_4_axb_6),.LO(un1_x_10_4_cry_6)); XORCY un1_x_10_4_s_5(.LI(un1_x_10_4_axb_5),.CI(un1_x_10_4_cry_4),.O(un1_x_10_4[5:5])); MUXCY_L un1_x_10_4_cry_5_cZ(.DI(x_8[4:4]),.CI(un1_x_10_4_cry_4),.S(un1_x_10_4_axb_5),.LO(un1_x_10_4_cry_5)); XORCY un1_x_10_4_s_4(.LI(un1_x_10_4_axb_4),.CI(un1_x_10_4_cry_3),.O(un1_x_10_4[4:4])); MUXCY_L un1_x_10_4_cry_4_cZ(.DI(x_8[3:3]),.CI(un1_x_10_4_cry_3),.S(un1_x_10_4_axb_4),.LO(un1_x_10_4_cry_4)); XORCY un1_x_10_4_s_3(.LI(un1_x_10_4_axb_3),.CI(un1_x_10_4_cry_2),.O(un1_x_10_4[3:3])); MUXCY_L un1_x_10_4_cry_3_cZ(.DI(x_8[2:2]),.CI(un1_x_10_4_cry_2),.S(un1_x_10_4_axb_3),.LO(un1_x_10_4_cry_3)); XORCY un1_x_10_4_s_2(.LI(un1_x_10_4_axb_2),.CI(un1_x_10_4_cry_1),.O(un1_x_10_4[2:2])); MUXCY_L un1_x_10_4_cry_2_cZ(.DI(x_8[1:1]),.CI(un1_x_10_4_cry_1),.S(un1_x_10_4_axb_2),.LO(un1_x_10_4_cry_2)); MUXCY_L un1_x_10_4_cry_1_cZ(.DI(x_8[0:0]),.CI(GND),.S(un1_x_10_4_cry_1_sf),.LO(un1_x_10_4_cry_1)); XORCY un84_sop_1_s_14_cZ(.LI(un84_sop_1_axb_14),.CI(un84_sop_1_cry_13),.O(un84_sop_1_s_14)); XORCY un84_sop_1_s_13_cZ(.LI(un84_sop_1_axb_13),.CI(un84_sop_1_cry_12),.O(un84_sop_1_s_13)); MUXCY_L un84_sop_1_cry_13_cZ(.DI(un84_sop_1_4[13:13]),.CI(un84_sop_1_cry_12),.S(un84_sop_1_axb_13),.LO(un84_sop_1_cry_13)); XORCY un84_sop_1_s_12_cZ(.LI(un84_sop_1_axb_12),.CI(un84_sop_1_cry_11),.O(un84_sop_1_s_12)); MUXCY_L un84_sop_1_cry_12_cZ(.DI(un84_sop_1_4[12:12]),.CI(un84_sop_1_cry_11),.S(un84_sop_1_axb_12),.LO(un84_sop_1_cry_12)); XORCY un84_sop_1_s_11_cZ(.LI(un84_sop_1_axb_11),.CI(un84_sop_1_cry_10),.O(un84_sop_1_s_11)); MUXCY_L un84_sop_1_cry_11_cZ(.DI(un84_sop_1_4[11:11]),.CI(un84_sop_1_cry_10),.S(un84_sop_1_axb_11),.LO(un84_sop_1_cry_11)); XORCY un84_sop_1_s_10_cZ(.LI(un84_sop_1_axb_10),.CI(un84_sop_1_cry_9),.O(un84_sop_1_s_10)); MUXCY_L un84_sop_1_cry_10_cZ(.DI(un84_sop_1_4[10:10]),.CI(un84_sop_1_cry_9),.S(un84_sop_1_axb_10),.LO(un84_sop_1_cry_10)); XORCY un84_sop_1_s_9_cZ(.LI(un84_sop_1_axb_9),.CI(un84_sop_1_cry_8),.O(un84_sop_1_s_9)); MUXCY_L un84_sop_1_cry_9_cZ(.DI(un84_sop_1_4[9:9]),.CI(un84_sop_1_cry_8),.S(un84_sop_1_axb_9),.LO(un84_sop_1_cry_9)); XORCY un84_sop_1_s_8_cZ(.LI(un84_sop_1_axb_8),.CI(un84_sop_1_cry_7),.O(un84_sop_1_s_8)); MUXCY_L un84_sop_1_cry_8_cZ(.DI(un84_sop_1_4[8:8]),.CI(un84_sop_1_cry_7),.S(un84_sop_1_axb_8),.LO(un84_sop_1_cry_8)); XORCY un84_sop_1_s_7_cZ(.LI(un84_sop_1_axb_7),.CI(un84_sop_1_cry_6),.O(un84_sop_1_s_7)); MUXCY_L un84_sop_1_cry_7_cZ(.DI(un84_sop_1_4[7:7]),.CI(un84_sop_1_cry_6),.S(un84_sop_1_axb_7),.LO(un84_sop_1_cry_7)); MUXCY_L un84_sop_1_cry_6_cZ(.DI(un84_sop_1_4[6:6]),.CI(un84_sop_1_cry_5),.S(un84_sop_1_axb_6),.LO(un84_sop_1_cry_6)); MUXCY_L un84_sop_1_cry_5_cZ(.DI(un84_sop_1_4[5:5]),.CI(un84_sop_1_cry_4),.S(un84_sop_1_axb_5),.LO(un84_sop_1_cry_5)); MUXCY_L un84_sop_1_cry_4_cZ(.DI(un84_sop_1_4[4:4]),.CI(un84_sop_1_cry_3),.S(un84_sop_1_axb_4),.LO(un84_sop_1_cry_4)); MUXCY_L un84_sop_1_cry_3_cZ(.DI(un84_sop_1_4[3:3]),.CI(un84_sop_1_cry_2),.S(un84_sop_1_axb_3),.LO(un84_sop_1_cry_3)); MUXCY_L un84_sop_1_cry_2_cZ(.DI(un84_sop_1_4[2:2]),.CI(un84_sop_1_cry_1),.S(un84_sop_1_axb_2),.LO(un84_sop_1_cry_2)); MUXCY_L un84_sop_1_cry_1_cZ(.DI(un84_sop_1_4[1:1]),.CI(un84_sop_1_cry_0),.S(un84_sop_1_axb_1),.LO(un84_sop_1_cry_1)); MUXCY_L un84_sop_1_cry_0_cZ(.DI(un84_sop_1_6[0:0]),.CI(GND),.S(un84_sop_1_axb_0),.LO(un84_sop_1_cry_0)); XORCY un84_sop_1_4_s_14(.LI(un84_sop_1_4_axb_14),.CI(un84_sop_1_4_cry_13),.O(un84_sop_1_4[14:14])); XORCY un84_sop_1_4_s_13(.LI(un84_sop_1_4_axb_13),.CI(un84_sop_1_4_cry_12),.O(un84_sop_1_4[13:13])); MUXCY_L un84_sop_1_4_cry_13_cZ(.DI(un84_sop_1_7[13:13]),.CI(un84_sop_1_4_cry_12),.S(un84_sop_1_4_axb_13),.LO(un84_sop_1_4_cry_13)); XORCY un84_sop_1_4_s_12(.LI(un84_sop_1_4_axb_12),.CI(un84_sop_1_4_cry_11),.O(un84_sop_1_4[12:12])); MUXCY_L un84_sop_1_4_cry_12_cZ(.DI(un84_sop_1_7[12:12]),.CI(un84_sop_1_4_cry_11),.S(un84_sop_1_4_axb_12),.LO(un84_sop_1_4_cry_12)); XORCY un84_sop_1_4_s_11(.LI(un84_sop_1_4_axb_11),.CI(un84_sop_1_4_cry_10),.O(un84_sop_1_4[11:11])); MUXCY_L un84_sop_1_4_cry_11_cZ(.DI(un84_sop_1_7[11:11]),.CI(un84_sop_1_4_cry_10),.S(un84_sop_1_4_axb_11),.LO(un84_sop_1_4_cry_11)); XORCY un84_sop_1_4_s_10(.LI(un84_sop_1_4_axb_10),.CI(un84_sop_1_4_cry_9),.O(un84_sop_1_4[10:10])); MUXCY_L un84_sop_1_4_cry_10_cZ(.DI(un84_sop_1_7[10:10]),.CI(un84_sop_1_4_cry_9),.S(un84_sop_1_4_axb_10),.LO(un84_sop_1_4_cry_10)); XORCY un84_sop_1_4_s_9(.LI(un84_sop_1_4_axb_9),.CI(un84_sop_1_4_cry_8),.O(un84_sop_1_4[9:9])); MUXCY_L un84_sop_1_4_cry_9_cZ(.DI(un84_sop_1_7[9:9]),.CI(un84_sop_1_4_cry_8),.S(un84_sop_1_4_axb_9),.LO(un84_sop_1_4_cry_9)); XORCY un84_sop_1_4_s_8(.LI(un84_sop_1_4_axb_8),.CI(un84_sop_1_4_cry_7),.O(un84_sop_1_4[8:8])); MUXCY_L un84_sop_1_4_cry_8_cZ(.DI(un84_sop_1_7[8:8]),.CI(un84_sop_1_4_cry_7),.S(un84_sop_1_4_axb_8),.LO(un84_sop_1_4_cry_8)); XORCY un84_sop_1_4_s_7(.LI(un84_sop_1_4_axb_7),.CI(un84_sop_1_4_cry_6),.O(un84_sop_1_4[7:7])); MUXCY_L un84_sop_1_4_cry_7_cZ(.DI(un84_sop_1_7[7:7]),.CI(un84_sop_1_4_cry_6),.S(un84_sop_1_4_axb_7),.LO(un84_sop_1_4_cry_7)); XORCY un84_sop_1_4_s_6(.LI(un84_sop_1_4_axb_6),.CI(un84_sop_1_4_cry_5),.O(un84_sop_1_4[6:6])); MUXCY_L un84_sop_1_4_cry_6_cZ(.DI(un84_sop_1_7[6:6]),.CI(un84_sop_1_4_cry_5),.S(un84_sop_1_4_axb_6),.LO(un84_sop_1_4_cry_6)); XORCY un84_sop_1_4_s_5(.LI(un84_sop_1_4_axb_5),.CI(un84_sop_1_4_cry_4),.O(un84_sop_1_4[5:5])); MUXCY_L un84_sop_1_4_cry_5_cZ(.DI(un84_sop_1_7[5:5]),.CI(un84_sop_1_4_cry_4),.S(un84_sop_1_4_axb_5),.LO(un84_sop_1_4_cry_5)); XORCY un84_sop_1_4_s_4(.LI(un84_sop_1_4_axb_4),.CI(un84_sop_1_4_cry_3),.O(un84_sop_1_4[4:4])); MUXCY_L un84_sop_1_4_cry_4_cZ(.DI(un84_sop_1_7[4:4]),.CI(un84_sop_1_4_cry_3),.S(un84_sop_1_4_axb_4),.LO(un84_sop_1_4_cry_4)); XORCY un84_sop_1_4_s_3(.LI(un84_sop_1_4_axb_3),.CI(un84_sop_1_4_cry_2),.O(un84_sop_1_4[3:3])); MUXCY_L un84_sop_1_4_cry_3_cZ(.DI(un84_sop_1_7[3:3]),.CI(un84_sop_1_4_cry_2),.S(un84_sop_1_4_axb_3),.LO(un84_sop_1_4_cry_3)); XORCY un84_sop_1_4_s_2(.LI(un84_sop_1_4_axb_2),.CI(un84_sop_1_4_cry_1),.O(un84_sop_1_4[2:2])); MUXCY_L un84_sop_1_4_cry_2_cZ(.DI(un84_sop_1_7[2:2]),.CI(un84_sop_1_4_cry_1),.S(un84_sop_1_4_axb_2),.LO(un84_sop_1_4_cry_2)); XORCY un84_sop_1_4_s_1(.LI(un84_sop_1_4_axb_1),.CI(un84_sop_1_4_cry_0),.O(un84_sop_1_4[1:1])); MUXCY_L un84_sop_1_4_cry_1_cZ(.DI(un84_sop_1_7[1:1]),.CI(un84_sop_1_4_cry_0),.S(un84_sop_1_4_axb_1),.LO(un84_sop_1_4_cry_1)); MUXCY_L un84_sop_1_4_cry_0_cZ(.DI(un84_sop_1_7[0:0]),.CI(GND),.S(un84_sop_1_4[0:0]),.LO(un84_sop_1_4_cry_0)); XORCY un84_sop_0_0_0_0_11_7_s_10(.LI(un84_sop_0_0_0_0_11_7_axb_10),.CI(un84_sop_0_0_0_0_11_7_cry_9),.O(un84_sop_0_0_0_0_11_7[14:14])); XORCY un84_sop_0_0_0_0_11_7_s_9(.LI(un84_sop_0_0_0_0_11_7_axb_9),.CI(un84_sop_0_0_0_0_11_7_cry_8),.O(un84_sop_0_0_0_0_11_7[9:9])); MUXCY_L un84_sop_0_0_0_0_11_7_cry_9_cZ(.DI(un84_sop_0_0_0_0_0[9:9]),.CI(un84_sop_0_0_0_0_11_7_cry_8),.S(un84_sop_0_0_0_0_11_7_axb_9),.LO(un84_sop_0_0_0_0_11_7_cry_9)); XORCY un84_sop_0_0_0_0_11_7_s_8(.LI(un84_sop_0_0_0_0_11_7_axb_8),.CI(un84_sop_0_0_0_0_11_7_cry_7),.O(un84_sop_0_0_0_0_11_7[8:8])); MUXCY_L un84_sop_0_0_0_0_11_7_cry_8_cZ(.DI(un84_sop_0_0_0_0_0[8:8]),.CI(un84_sop_0_0_0_0_11_7_cry_7),.S(un84_sop_0_0_0_0_11_7_axb_8),.LO(un84_sop_0_0_0_0_11_7_cry_8)); XORCY un84_sop_0_0_0_0_11_7_s_7(.LI(un84_sop_0_0_0_0_11_7_axb_7),.CI(un84_sop_0_0_0_0_11_7_cry_6),.O(un84_sop_0_0_0_0_11_7[7:7])); MUXCY_L un84_sop_0_0_0_0_11_7_cry_7_cZ(.DI(un84_sop_0_0_0_0_0[7:7]),.CI(un84_sop_0_0_0_0_11_7_cry_6),.S(un84_sop_0_0_0_0_11_7_axb_7),.LO(un84_sop_0_0_0_0_11_7_cry_7)); XORCY un84_sop_0_0_0_0_11_7_s_6(.LI(un84_sop_0_0_0_0_11_7_axb_6),.CI(un84_sop_0_0_0_0_11_7_cry_5),.O(un84_sop_0_0_0_0_11_7[6:6])); MUXCY_L un84_sop_0_0_0_0_11_7_cry_6_cZ(.DI(un84_sop_0_0_0_0_0[6:6]),.CI(un84_sop_0_0_0_0_11_7_cry_5),.S(un84_sop_0_0_0_0_11_7_axb_6),.LO(un84_sop_0_0_0_0_11_7_cry_6)); XORCY un84_sop_0_0_0_0_11_7_s_5(.LI(un84_sop_0_0_0_0_11_7_axb_5),.CI(un84_sop_0_0_0_0_11_7_cry_4),.O(un84_sop_0_0_0_0_11_7[5:5])); MUXCY_L un84_sop_0_0_0_0_11_7_cry_5_cZ(.DI(un84_sop_0_0_0_0_0[5:5]),.CI(un84_sop_0_0_0_0_11_7_cry_4),.S(un84_sop_0_0_0_0_11_7_axb_5),.LO(un84_sop_0_0_0_0_11_7_cry_5)); XORCY un84_sop_0_0_0_0_11_7_s_4(.LI(un84_sop_0_0_0_0_11_7_axb_4),.CI(un84_sop_0_0_0_0_11_7_cry_3),.O(un84_sop_0_0_0_0_11_7[4:4])); MUXCY_L un84_sop_0_0_0_0_11_7_cry_4_cZ(.DI(un84_sop_0_0_0_0_0[4:4]),.CI(un84_sop_0_0_0_0_11_7_cry_3),.S(un84_sop_0_0_0_0_11_7_axb_4),.LO(un84_sop_0_0_0_0_11_7_cry_4)); XORCY un84_sop_0_0_0_0_11_7_s_3(.LI(un84_sop_0_0_0_0_11_7_axb_3),.CI(un84_sop_0_0_0_0_11_7_cry_2),.O(un84_sop_0_0_0_0_11_7[3:3])); MUXCY_L un84_sop_0_0_0_0_11_7_cry_3_cZ(.DI(un84_sop_0_0_0_0_0[3:3]),.CI(un84_sop_0_0_0_0_11_7_cry_2),.S(un84_sop_0_0_0_0_11_7_axb_3),.LO(un84_sop_0_0_0_0_11_7_cry_3)); XORCY un84_sop_0_0_0_0_11_7_s_2(.LI(un84_sop_0_0_0_0_11_7_axb_2),.CI(un84_sop_0_0_0_0_11_7_cry_1),.O(un84_sop_0_0_0_0_11_7[2:2])); MUXCY_L un84_sop_0_0_0_0_11_7_cry_2_cZ(.DI(un84_sop_0_0_0_0_0[2:2]),.CI(un84_sop_0_0_0_0_11_7_cry_1),.S(un84_sop_0_0_0_0_11_7_axb_2),.LO(un84_sop_0_0_0_0_11_7_cry_2)); XORCY un84_sop_0_0_0_0_11_7_s_1(.LI(un84_sop_0_0_0_0_11_7_axb_1),.CI(un84_sop_0_0_0_0_11_7_cry_0),.O(un84_sop_0_0_0_0_11_7[1:1])); MUXCY_L un84_sop_0_0_0_0_11_7_cry_1_cZ(.DI(un84_sop_0_0_0_0_0[1:1]),.CI(un84_sop_0_0_0_0_11_7_cry_0),.S(un84_sop_0_0_0_0_11_7_axb_1),.LO(un84_sop_0_0_0_0_11_7_cry_1)); MUXCY_L un84_sop_0_0_0_0_11_7_cry_0_cZ(.DI(un84_sop_0_0_0_0_0[0:0]),.CI(GND),.S(un84_sop_0_0_0_0_11_7[0:0]),.LO(un84_sop_0_0_0_0_11_7_cry_0)); XORCY un84_sop_1_7_s_14(.LI(un84_sop_1_7_axb_14),.CI(un84_sop_1_7_cry_13),.O(un84_sop_1_7[14:14])); XORCY un84_sop_1_7_s_13(.LI(un84_sop_1_7_axb_13),.CI(un84_sop_1_7_cry_12),.O(un84_sop_1_7[13:13])); MUXCY_L un84_sop_1_7_cry_13_cZ(.DI(un84_sop_0_0_0_0_5[13:13]),.CI(un84_sop_1_7_cry_12),.S(un84_sop_1_7_axb_13),.LO(un84_sop_1_7_cry_13)); XORCY un84_sop_1_7_s_12(.LI(un84_sop_1_7_axb_12),.CI(un84_sop_1_7_cry_11),.O(un84_sop_1_7[12:12])); MUXCY_L un84_sop_1_7_cry_12_cZ(.DI(un84_sop_0_0_0_0_5[12:12]),.CI(un84_sop_1_7_cry_11),.S(un84_sop_1_7_axb_12),.LO(un84_sop_1_7_cry_12)); XORCY un84_sop_1_7_s_11(.LI(un84_sop_1_7_axb_11),.CI(un84_sop_1_7_cry_10),.O(un84_sop_1_7[11:11])); MUXCY_L un84_sop_1_7_cry_11_cZ(.DI(un84_sop_0_0_0_0_5[11:11]),.CI(un84_sop_1_7_cry_10),.S(un84_sop_1_7_axb_11),.LO(un84_sop_1_7_cry_11)); XORCY un84_sop_1_7_s_10(.LI(un84_sop_1_7_axb_10),.CI(un84_sop_1_7_cry_9),.O(un84_sop_1_7[10:10])); MUXCY_L un84_sop_1_7_cry_10_cZ(.DI(un84_sop_0_0_0_0_5[10:10]),.CI(un84_sop_1_7_cry_9),.S(un84_sop_1_7_axb_10),.LO(un84_sop_1_7_cry_10)); XORCY un84_sop_1_7_s_9(.LI(un84_sop_1_7_axb_9),.CI(un84_sop_1_7_cry_8),.O(un84_sop_1_7[9:9])); MUXCY_L un84_sop_1_7_cry_9_cZ(.DI(un84_sop_0_0_0_0_5[9:9]),.CI(un84_sop_1_7_cry_8),.S(un84_sop_1_7_axb_9),.LO(un84_sop_1_7_cry_9)); XORCY un84_sop_1_7_s_8(.LI(un84_sop_1_7_axb_8),.CI(un84_sop_1_7_cry_7),.O(un84_sop_1_7[8:8])); MUXCY_L un84_sop_1_7_cry_8_cZ(.DI(un84_sop_0_0_0_0_5[8:8]),.CI(un84_sop_1_7_cry_7),.S(un84_sop_1_7_axb_8),.LO(un84_sop_1_7_cry_8)); XORCY un84_sop_1_7_s_7(.LI(un84_sop_1_7_axb_7),.CI(un84_sop_1_7_cry_6),.O(un84_sop_1_7[7:7])); MUXCY_L un84_sop_1_7_cry_7_cZ(.DI(un84_sop_0_0_0_0_5[7:7]),.CI(un84_sop_1_7_cry_6),.S(un84_sop_1_7_axb_7),.LO(un84_sop_1_7_cry_7)); XORCY un84_sop_1_7_s_6(.LI(un84_sop_1_7_axb_6),.CI(un84_sop_1_7_cry_5),.O(un84_sop_1_7[6:6])); MUXCY_L un84_sop_1_7_cry_6_cZ(.DI(un84_sop_0_0_0_0_5[6:6]),.CI(un84_sop_1_7_cry_5),.S(un84_sop_1_7_axb_6),.LO(un84_sop_1_7_cry_6)); XORCY un84_sop_1_7_s_5(.LI(un84_sop_1_7_axb_5),.CI(un84_sop_1_7_cry_4),.O(un84_sop_1_7[5:5])); MUXCY_L un84_sop_1_7_cry_5_cZ(.DI(un84_sop_0_0_0_0_5[5:5]),.CI(un84_sop_1_7_cry_4),.S(un84_sop_1_7_axb_5),.LO(un84_sop_1_7_cry_5)); XORCY un84_sop_1_7_s_4(.LI(un84_sop_1_7_axb_4),.CI(un84_sop_1_7_cry_3),.O(un84_sop_1_7[4:4])); MUXCY_L un84_sop_1_7_cry_4_cZ(.DI(un84_sop_0_0_0_0_5[4:4]),.CI(un84_sop_1_7_cry_3),.S(un84_sop_1_7_axb_4),.LO(un84_sop_1_7_cry_4)); XORCY un84_sop_1_7_s_3(.LI(un84_sop_1_7_axb_3),.CI(un84_sop_1_7_cry_2),.O(un84_sop_1_7[3:3])); MUXCY_L un84_sop_1_7_cry_3_cZ(.DI(un84_sop_0_0_0_0_5[3:3]),.CI(un84_sop_1_7_cry_2),.S(un84_sop_1_7_axb_3),.LO(un84_sop_1_7_cry_3)); XORCY un84_sop_1_7_s_2(.LI(un84_sop_1_7_axb_2),.CI(un84_sop_1_7_cry_1),.O(un84_sop_1_7[2:2])); MUXCY_L un84_sop_1_7_cry_2_cZ(.DI(un84_sop_0_0_0_0_5[2:2]),.CI(un84_sop_1_7_cry_1),.S(un84_sop_1_7_axb_2),.LO(un84_sop_1_7_cry_2)); XORCY un84_sop_1_7_s_1(.LI(un84_sop_1_7_axb_1),.CI(un84_sop_1_7_cry_0),.O(un84_sop_1_7[1:1])); MUXCY_L un84_sop_1_7_cry_1_cZ(.DI(un84_sop_0_0_0_0_5[1:1]),.CI(un84_sop_1_7_cry_0),.S(un84_sop_1_7_axb_1),.LO(un84_sop_1_7_cry_1)); MUXCY_L un84_sop_1_7_cry_0_cZ(.DI(un84_sop_0_0_0_0_5[0:0]),.CI(GND),.S(un84_sop_1_7[0:0]),.LO(un84_sop_1_7_cry_0)); XORCY un84_sop_0_0_0_1_6_s_14(.LI(un84_sop_0_0_0_1_6_axb_14),.CI(un84_sop_0_0_0_1_6_cry_13),.O(un84_sop_0_0_0_5_0[14:14])); XORCY un84_sop_0_0_0_1_6_s_13(.LI(un84_sop_0_0_0_1_6_axb_13),.CI(un84_sop_0_0_0_1_6_cry_12),.O(un84_sop_0_0_0_5_0[13:13])); MUXCY_L un84_sop_0_0_0_1_6_cry_13_cZ(.DI(un84_sop_0_0_0_1_6_4[13:13]),.CI(un84_sop_0_0_0_1_6_cry_12),.S(un84_sop_0_0_0_1_6_axb_13),.LO(un84_sop_0_0_0_1_6_cry_13)); XORCY un84_sop_0_0_0_1_6_s_12(.LI(un84_sop_0_0_0_1_6_axb_12),.CI(un84_sop_0_0_0_1_6_cry_11),.O(un84_sop_0_0_0_5_0[12:12])); MUXCY_L un84_sop_0_0_0_1_6_cry_12_cZ(.DI(un84_sop_0_0_0_1_6_4[12:12]),.CI(un84_sop_0_0_0_1_6_cry_11),.S(un84_sop_0_0_0_1_6_axb_12),.LO(un84_sop_0_0_0_1_6_cry_12)); XORCY un84_sop_0_0_0_1_6_s_11(.LI(un84_sop_0_0_0_1_6_axb_11),.CI(un84_sop_0_0_0_1_6_cry_10),.O(un84_sop_0_0_0_5_0[11:11])); MUXCY_L un84_sop_0_0_0_1_6_cry_11_cZ(.DI(un84_sop_0_0_0_1_6_4[11:11]),.CI(un84_sop_0_0_0_1_6_cry_10),.S(un84_sop_0_0_0_1_6_axb_11),.LO(un84_sop_0_0_0_1_6_cry_11)); XORCY un84_sop_0_0_0_1_6_s_10(.LI(un84_sop_0_0_0_1_6_axb_10),.CI(un84_sop_0_0_0_1_6_cry_9),.O(un84_sop_0_0_0_5_0[10:10])); MUXCY_L un84_sop_0_0_0_1_6_cry_10_cZ(.DI(un84_sop_0_0_0_1_6_4[10:10]),.CI(un84_sop_0_0_0_1_6_cry_9),.S(un84_sop_0_0_0_1_6_axb_10),.LO(un84_sop_0_0_0_1_6_cry_10)); XORCY un84_sop_0_0_0_1_6_s_9(.LI(un84_sop_0_0_0_1_6_axb_9),.CI(un84_sop_0_0_0_1_6_cry_8),.O(un84_sop_0_0_0_5_0[9:9])); MUXCY_L un84_sop_0_0_0_1_6_cry_9_cZ(.DI(un84_sop_0_0_0_1_6_4[9:9]),.CI(un84_sop_0_0_0_1_6_cry_8),.S(un84_sop_0_0_0_1_6_axb_9),.LO(un84_sop_0_0_0_1_6_cry_9)); XORCY un84_sop_0_0_0_1_6_s_8(.LI(un84_sop_0_0_0_1_6_axb_8),.CI(un84_sop_0_0_0_1_6_cry_7),.O(un84_sop_0_0_0_5_0[8:8])); MUXCY_L un84_sop_0_0_0_1_6_cry_8_cZ(.DI(un84_sop_0_0_0_1_6_4[8:8]),.CI(un84_sop_0_0_0_1_6_cry_7),.S(un84_sop_0_0_0_1_6_axb_8),.LO(un84_sop_0_0_0_1_6_cry_8)); XORCY un84_sop_0_0_0_1_6_s_7(.LI(un84_sop_0_0_0_1_6_axb_7),.CI(un84_sop_0_0_0_1_6_cry_6),.O(un84_sop_0_0_0_5_0[7:7])); MUXCY_L un84_sop_0_0_0_1_6_cry_7_cZ(.DI(un84_sop_0_0_0_1_6_4[7:7]),.CI(un84_sop_0_0_0_1_6_cry_6),.S(un84_sop_0_0_0_1_6_axb_7),.LO(un84_sop_0_0_0_1_6_cry_7)); XORCY un84_sop_0_0_0_1_6_s_6(.LI(un84_sop_0_0_0_1_6_axb_6),.CI(un84_sop_0_0_0_1_6_cry_5),.O(un84_sop_0_0_0_5_0[6:6])); MUXCY_L un84_sop_0_0_0_1_6_cry_6_cZ(.DI(un84_sop_0_0_0_1_6_4[6:6]),.CI(un84_sop_0_0_0_1_6_cry_5),.S(un84_sop_0_0_0_1_6_axb_6),.LO(un84_sop_0_0_0_1_6_cry_6)); XORCY un84_sop_0_0_0_1_6_s_5(.LI(un84_sop_0_0_0_1_6_axb_5),.CI(un84_sop_0_0_0_1_6_cry_4),.O(un84_sop_0_0_0_5_0[5:5])); MUXCY_L un84_sop_0_0_0_1_6_cry_5_cZ(.DI(un84_sop_0_0_0_1_6_4[5:5]),.CI(un84_sop_0_0_0_1_6_cry_4),.S(un84_sop_0_0_0_1_6_axb_5),.LO(un84_sop_0_0_0_1_6_cry_5)); XORCY un84_sop_0_0_0_1_6_s_4(.LI(un84_sop_0_0_0_1_6_axb_4),.CI(un84_sop_0_0_0_1_6_cry_3),.O(un84_sop_0_0_0_5_0[4:4])); MUXCY_L un84_sop_0_0_0_1_6_cry_4_cZ(.DI(un84_sop_0_0_0_1_6_4[4:4]),.CI(un84_sop_0_0_0_1_6_cry_3),.S(un84_sop_0_0_0_1_6_axb_4),.LO(un84_sop_0_0_0_1_6_cry_4)); XORCY un84_sop_0_0_0_1_6_s_3(.LI(un84_sop_0_0_0_1_6_axb_3),.CI(un84_sop_0_0_0_1_6_cry_2),.O(un84_sop_0_0_0_5_0[3:3])); MUXCY_L un84_sop_0_0_0_1_6_cry_3_cZ(.DI(un84_sop_0_0_0_1_6_4[3:3]),.CI(un84_sop_0_0_0_1_6_cry_2),.S(un84_sop_0_0_0_1_6_axb_3),.LO(un84_sop_0_0_0_1_6_cry_3)); XORCY un84_sop_0_0_0_1_6_s_2(.LI(un84_sop_0_0_0_1_6_axb_2),.CI(un84_sop_0_0_0_1_6_cry_1),.O(un84_sop_0_0_0_5_0[2:2])); MUXCY_L un84_sop_0_0_0_1_6_cry_2_cZ(.DI(un84_sop_0_0_0_1_6_4[2:2]),.CI(un84_sop_0_0_0_1_6_cry_1),.S(un84_sop_0_0_0_1_6_axb_2),.LO(un84_sop_0_0_0_1_6_cry_2)); XORCY un84_sop_0_0_0_1_6_s_1(.LI(un84_sop_0_0_0_1_6_axb_1),.CI(un84_sop_0_0_0_1_6_cry_0),.O(un84_sop_0_0_0_5_0[1:1])); MUXCY_L un84_sop_0_0_0_1_6_cry_1_cZ(.DI(un84_sop_0_0_0_1_6_4[1:1]),.CI(un84_sop_0_0_0_1_6_cry_0),.S(un84_sop_0_0_0_1_6_axb_1),.LO(un84_sop_0_0_0_1_6_cry_1)); MUXCY_L un84_sop_0_0_0_1_6_cry_0_cZ(.DI(un84_sop_0_0_0_1_6_6[0:0]),.CI(GND),.S(un84_sop_0_0_0_5_0[0:0]),.LO(un84_sop_0_0_0_1_6_cry_0)); XORCY un84_sop_0_0_0_1_6_4_s_14(.LI(un84_sop_0_0_0_1_6_4_axb_14),.CI(un84_sop_0_0_0_1_6_4_cry_13),.O(un84_sop_0_0_0_1_6_4[14:14])); XORCY un84_sop_0_0_0_1_6_4_s_13(.LI(un84_sop_0_0_0_1_6_4_axb_13),.CI(un84_sop_0_0_0_1_6_4_cry_12),.O(un84_sop_0_0_0_1_6_4[13:13])); MUXCY_L un84_sop_0_0_0_1_6_4_cry_13_cZ(.DI(un84_sop_0_0_0_1_6_8[13:13]),.CI(un84_sop_0_0_0_1_6_4_cry_12),.S(un84_sop_0_0_0_1_6_4_axb_13),.LO(un84_sop_0_0_0_1_6_4_cry_13)); XORCY un84_sop_0_0_0_1_6_4_s_12(.LI(un84_sop_0_0_0_1_6_4_axb_12),.CI(un84_sop_0_0_0_1_6_4_cry_11),.O(un84_sop_0_0_0_1_6_4[12:12])); MUXCY_L un84_sop_0_0_0_1_6_4_cry_12_cZ(.DI(un84_sop_0_0_0_1_6_8[12:12]),.CI(un84_sop_0_0_0_1_6_4_cry_11),.S(un84_sop_0_0_0_1_6_4_axb_12),.LO(un84_sop_0_0_0_1_6_4_cry_12)); XORCY un84_sop_0_0_0_1_6_4_s_11(.LI(un84_sop_0_0_0_1_6_4_axb_11),.CI(un84_sop_0_0_0_1_6_4_cry_10),.O(un84_sop_0_0_0_1_6_4[11:11])); MUXCY_L un84_sop_0_0_0_1_6_4_cry_11_cZ(.DI(un84_sop_0_0_0_1_6_8[11:11]),.CI(un84_sop_0_0_0_1_6_4_cry_10),.S(un84_sop_0_0_0_1_6_4_axb_11),.LO(un84_sop_0_0_0_1_6_4_cry_11)); XORCY un84_sop_0_0_0_1_6_4_s_10(.LI(un84_sop_0_0_0_1_6_4_axb_10),.CI(un84_sop_0_0_0_1_6_4_cry_9),.O(un84_sop_0_0_0_1_6_4[10:10])); MUXCY_L un84_sop_0_0_0_1_6_4_cry_10_cZ(.DI(un84_sop_0_0_0_1_6_8[10:10]),.CI(un84_sop_0_0_0_1_6_4_cry_9),.S(un84_sop_0_0_0_1_6_4_axb_10),.LO(un84_sop_0_0_0_1_6_4_cry_10)); XORCY un84_sop_0_0_0_1_6_4_s_9(.LI(un84_sop_0_0_0_1_6_4_axb_9),.CI(un84_sop_0_0_0_1_6_4_cry_8),.O(un84_sop_0_0_0_1_6_4[9:9])); MUXCY_L un84_sop_0_0_0_1_6_4_cry_9_cZ(.DI(un84_sop_0_0_0_1_6_8[9:9]),.CI(un84_sop_0_0_0_1_6_4_cry_8),.S(un84_sop_0_0_0_1_6_4_axb_9),.LO(un84_sop_0_0_0_1_6_4_cry_9)); XORCY un84_sop_0_0_0_1_6_4_s_8(.LI(un84_sop_0_0_0_1_6_4_axb_8),.CI(un84_sop_0_0_0_1_6_4_cry_7),.O(un84_sop_0_0_0_1_6_4[8:8])); MUXCY_L un84_sop_0_0_0_1_6_4_cry_8_cZ(.DI(un84_sop_0_0_0_1_6_8[8:8]),.CI(un84_sop_0_0_0_1_6_4_cry_7),.S(un84_sop_0_0_0_1_6_4_axb_8),.LO(un84_sop_0_0_0_1_6_4_cry_8)); XORCY un84_sop_0_0_0_1_6_4_s_7(.LI(un84_sop_0_0_0_1_6_4_axb_7),.CI(un84_sop_0_0_0_1_6_4_cry_6),.O(un84_sop_0_0_0_1_6_4[7:7])); MUXCY_L un84_sop_0_0_0_1_6_4_cry_7_cZ(.DI(un84_sop_0_0_0_1_6_8[7:7]),.CI(un84_sop_0_0_0_1_6_4_cry_6),.S(un84_sop_0_0_0_1_6_4_axb_7),.LO(un84_sop_0_0_0_1_6_4_cry_7)); XORCY un84_sop_0_0_0_1_6_4_s_6(.LI(un84_sop_0_0_0_1_6_4_axb_6),.CI(un84_sop_0_0_0_1_6_4_cry_5),.O(un84_sop_0_0_0_1_6_4[6:6])); MUXCY_L un84_sop_0_0_0_1_6_4_cry_6_cZ(.DI(un84_sop_0_0_0_1_6_8[6:6]),.CI(un84_sop_0_0_0_1_6_4_cry_5),.S(un84_sop_0_0_0_1_6_4_axb_6),.LO(un84_sop_0_0_0_1_6_4_cry_6)); XORCY un84_sop_0_0_0_1_6_4_s_5(.LI(un84_sop_0_0_0_1_6_4_axb_5),.CI(un84_sop_0_0_0_1_6_4_cry_4),.O(un84_sop_0_0_0_1_6_4[5:5])); MUXCY_L un84_sop_0_0_0_1_6_4_cry_5_cZ(.DI(un84_sop_0_0_0_1_6_8[5:5]),.CI(un84_sop_0_0_0_1_6_4_cry_4),.S(un84_sop_0_0_0_1_6_4_axb_5),.LO(un84_sop_0_0_0_1_6_4_cry_5)); XORCY un84_sop_0_0_0_1_6_4_s_4(.LI(un84_sop_0_0_0_1_6_4_axb_4),.CI(un84_sop_0_0_0_1_6_4_cry_3),.O(un84_sop_0_0_0_1_6_4[4:4])); MUXCY_L un84_sop_0_0_0_1_6_4_cry_4_cZ(.DI(un84_sop_0_0_0_1_6_8[4:4]),.CI(un84_sop_0_0_0_1_6_4_cry_3),.S(un84_sop_0_0_0_1_6_4_axb_4),.LO(un84_sop_0_0_0_1_6_4_cry_4)); XORCY un84_sop_0_0_0_1_6_4_s_3(.LI(un84_sop_0_0_0_1_6_4_axb_3),.CI(un84_sop_0_0_0_1_6_4_cry_2),.O(un84_sop_0_0_0_1_6_4[3:3])); MUXCY_L un84_sop_0_0_0_1_6_4_cry_3_cZ(.DI(un1_x_6_0[4:4]),.CI(un84_sop_0_0_0_1_6_4_cry_2),.S(un84_sop_0_0_0_1_6_4_axb_3),.LO(un84_sop_0_0_0_1_6_4_cry_3)); XORCY un84_sop_0_0_0_1_6_4_s_2(.LI(un84_sop_0_0_0_1_6_4_axb_2),.CI(un84_sop_0_0_0_1_6_4_cry_1),.O(un84_sop_0_0_0_1_6_4[2:2])); MUXCY_L un84_sop_0_0_0_1_6_4_cry_2_cZ(.DI(un1_x_6_0[3:3]),.CI(un84_sop_0_0_0_1_6_4_cry_1),.S(un84_sop_0_0_0_1_6_4_axb_2),.LO(un84_sop_0_0_0_1_6_4_cry_2)); XORCY un84_sop_0_0_0_1_6_4_s_1(.LI(un84_sop_0_0_0_1_6_4_axb_1),.CI(un84_sop_0_0_0_1_6_4_cry_0),.O(un84_sop_0_0_0_1_6_4[1:1])); MUXCY_L un84_sop_0_0_0_1_6_4_cry_1_cZ(.DI(un1_x_6_0[2:2]),.CI(un84_sop_0_0_0_1_6_4_cry_0),.S(un84_sop_0_0_0_1_6_4_axb_1),.LO(un84_sop_0_0_0_1_6_4_cry_1)); MUXCY_L un84_sop_0_0_0_1_6_4_cry_0_cZ(.DI(un1_x_6_0[1:1]),.CI(GND),.S(un84_sop_0_0_0_1_6_4[0:0]),.LO(un84_sop_0_0_0_1_6_4_cry_0)); XORCY un1_x_10_s_11(.LI(un1_x_10_axb_11),.CI(un1_x_10_cry_10),.O(un1_x_10_0_0[15:15])); XORCY un1_x_10_s_10(.LI(un1_x_10_axb_10),.CI(un1_x_10_cry_9),.O(un1_x_10_0_0[14:14])); MUXCY_L un1_x_10_cry_10_cZ(.DI(un1_x_10_4[10:10]),.CI(un1_x_10_cry_9),.S(un1_x_10_axb_10),.LO(un1_x_10_cry_10)); XORCY un1_x_10_s_9(.LI(un1_x_10_axb_9),.CI(un1_x_10_cry_8),.O(un1_x_10_0_0[13:13])); MUXCY_L un1_x_10_cry_9_cZ(.DI(un1_x_10_4[9:9]),.CI(un1_x_10_cry_8),.S(un1_x_10_axb_9),.LO(un1_x_10_cry_9)); XORCY un1_x_10_s_8(.LI(un1_x_10_axb_8),.CI(un1_x_10_cry_7),.O(un1_x_10_0_0[12:12])); MUXCY_L un1_x_10_cry_8_cZ(.DI(un1_x_10_4[8:8]),.CI(un1_x_10_cry_7),.S(un1_x_10_axb_8),.LO(un1_x_10_cry_8)); XORCY un1_x_10_s_7(.LI(un1_x_10_axb_7),.CI(un1_x_10_cry_6),.O(un1_x_10_0_0[11:11])); MUXCY_L un1_x_10_cry_7_cZ(.DI(un1_x_10_4[7:7]),.CI(un1_x_10_cry_6),.S(un1_x_10_axb_7),.LO(un1_x_10_cry_7)); XORCY un1_x_10_s_6(.LI(un1_x_10_axb_6),.CI(un1_x_10_cry_5),.O(un1_x_10_0_0[10:10])); MUXCY_L un1_x_10_cry_6_cZ(.DI(un1_x_10_4[6:6]),.CI(un1_x_10_cry_5),.S(un1_x_10_axb_6),.LO(un1_x_10_cry_6)); XORCY un1_x_10_s_5(.LI(un1_x_10_axb_5),.CI(un1_x_10_cry_4),.O(un1_x_10_0_0[9:9])); MUXCY_L un1_x_10_cry_5_cZ(.DI(un1_x_10_4[5:5]),.CI(un1_x_10_cry_4),.S(un1_x_10_axb_5),.LO(un1_x_10_cry_5)); XORCY un1_x_10_s_4(.LI(un1_x_10_axb_4),.CI(un1_x_10_cry_3),.O(un1_x_10_0_0[8:8])); MUXCY_L un1_x_10_cry_4_cZ(.DI(un1_x_10_4[4:4]),.CI(un1_x_10_cry_3),.S(un1_x_10_axb_4),.LO(un1_x_10_cry_4)); MUXCY_L un1_x_10_cry_3_cZ(.DI(un1_x_10_4[3:3]),.CI(GND),.S(un1_x_10_axb_3),.LO(un1_x_10_cry_3)); XORCY un84_sop_1_6_0_s_13(.LI(un84_sop_1_6_0_axb_13),.CI(un84_sop_1_6_0_cry_12),.O(un84_sop_1_6[14:14])); XORCY un84_sop_1_6_0_s_12(.LI(un84_sop_1_6_0_axb_12),.CI(un84_sop_1_6_0_cry_11),.O(un84_sop_1_6[12:12])); MUXCY_L un84_sop_1_6_0_cry_12_cZ(.DI(un84_sop_1_6_0_o5_11),.CI(un84_sop_1_6_0_cry_11),.S(un84_sop_1_6_0_axb_12),.LO(un84_sop_1_6_0_cry_12)); XORCY un84_sop_1_6_0_s_11(.LI(un84_sop_1_6_0_axb_11),.CI(un84_sop_1_6_0_cry_10),.O(un84_sop_1_6[11:11])); MUXCY_L un84_sop_1_6_0_cry_11_cZ(.DI(un84_sop_1_6_0_o5_10),.CI(un84_sop_1_6_0_cry_10),.S(un84_sop_1_6_0_axb_11),.LO(un84_sop_1_6_0_cry_11)); XORCY un84_sop_1_6_0_s_10(.LI(un84_sop_1_6_0_axb_10),.CI(un84_sop_1_6_0_cry_9),.O(un84_sop_1_6[10:10])); MUXCY_L un84_sop_1_6_0_cry_10_cZ(.DI(un84_sop_1_6_0_o5_9),.CI(un84_sop_1_6_0_cry_9),.S(un84_sop_1_6_0_axb_10),.LO(un84_sop_1_6_0_cry_10)); XORCY un84_sop_1_6_0_s_9(.LI(un84_sop_1_6_0_axb_9),.CI(un84_sop_1_6_0_cry_8),.O(un84_sop_1_6[9:9])); MUXCY_L un84_sop_1_6_0_cry_9_cZ(.DI(un84_sop_1_6_0_o5_8),.CI(un84_sop_1_6_0_cry_8),.S(un84_sop_1_6_0_axb_9),.LO(un84_sop_1_6_0_cry_9)); XORCY un84_sop_1_6_0_s_8(.LI(un84_sop_1_6_0_axb_8),.CI(un84_sop_1_6_0_cry_7),.O(un84_sop_1_6[8:8])); MUXCY_L un84_sop_1_6_0_cry_8_cZ(.DI(un84_sop_1_6_0_o5_7),.CI(un84_sop_1_6_0_cry_7),.S(un84_sop_1_6_0_axb_8),.LO(un84_sop_1_6_0_cry_8)); XORCY un84_sop_1_6_0_s_7(.LI(un84_sop_1_6_0_axb_7),.CI(un84_sop_1_6_0_cry_6),.O(un84_sop_1_6[7:7])); MUXCY_L un84_sop_1_6_0_cry_7_cZ(.DI(un84_sop_1_6_0_o5_6),.CI(un84_sop_1_6_0_cry_6),.S(un84_sop_1_6_0_axb_7),.LO(un84_sop_1_6_0_cry_7)); XORCY un84_sop_1_6_0_s_6(.LI(un84_sop_1_6_0_axb_6),.CI(un84_sop_1_6_0_cry_5),.O(un84_sop_1_6[6:6])); MUXCY_L un84_sop_1_6_0_cry_6_cZ(.DI(un84_sop_1_6_0_o5_5),.CI(un84_sop_1_6_0_cry_5),.S(un84_sop_1_6_0_axb_6),.LO(un84_sop_1_6_0_cry_6)); XORCY un84_sop_1_6_0_s_5(.LI(un84_sop_1_6_0_axb_5),.CI(un84_sop_1_6_0_cry_4),.O(un84_sop_1_6[5:5])); MUXCY_L un84_sop_1_6_0_cry_5_cZ(.DI(un84_sop_1_6_0_o5_4),.CI(un84_sop_1_6_0_cry_4),.S(un84_sop_1_6_0_axb_5),.LO(un84_sop_1_6_0_cry_5)); XORCY un84_sop_1_6_0_s_4(.LI(un84_sop_1_6_0_axb_4),.CI(un84_sop_1_6_0_cry_3),.O(un84_sop_1_6[4:4])); MUXCY_L un84_sop_1_6_0_cry_4_cZ(.DI(un84_sop_1_6_0_o5_3),.CI(un84_sop_1_6_0_cry_3),.S(un84_sop_1_6_0_axb_4),.LO(un84_sop_1_6_0_cry_4)); XORCY un84_sop_1_6_0_s_3(.LI(un84_sop_1_6_0_axb_3),.CI(un84_sop_1_6_0_cry_2),.O(un84_sop_1_6[3:3])); MUXCY_L un84_sop_1_6_0_cry_3_cZ(.DI(un84_sop_1_6_0_o5_2),.CI(un84_sop_1_6_0_cry_2),.S(un84_sop_1_6_0_axb_3),.LO(un84_sop_1_6_0_cry_3)); XORCY un84_sop_1_6_0_s_2(.LI(un84_sop_1_6_0_axb_2),.CI(un84_sop_1_6_0_cry_1),.O(un84_sop_1_6[2:2])); MUXCY_L un84_sop_1_6_0_cry_2_cZ(.DI(un84_sop_1_6_0_axb_1_lut6_2_O5),.CI(un84_sop_1_6_0_cry_1),.S(un84_sop_1_6_0_axb_2),.LO(un84_sop_1_6_0_cry_2)); XORCY un84_sop_1_6_0_s_1(.LI(un84_sop_1_6_0_axb_1),.CI(un84_sop_1_6_0_cry_0),.O(un84_sop_1_6[1:1])); MUXCY_L un84_sop_1_6_0_cry_1_cZ(.DI(GND),.CI(un84_sop_1_6_0_cry_0),.S(un84_sop_1_6_0_axb_1),.LO(un84_sop_1_6_0_cry_1)); MUXCY_L un84_sop_1_6_0_cry_0_cZ(.DI(un1_x_2[5:5]),.CI(un84_sop_1_6_0_cry_0_cy),.S(un84_sop_1_6_0_axb_0_0),.LO(un84_sop_1_6_0_cry_0)); XORCY un84_sop_0_0_0_1_6_8_s_11(.LI(un84_sop_0_0_0_1_6_8_axb_11),.CI(un84_sop_0_0_0_1_6_8_cry_10),.O(un84_sop_0_0_0_1_6_8[14:14])); XORCY un84_sop_0_0_0_1_6_8_s_10(.LI(un84_sop_0_0_0_1_6_8_axb_10),.CI(un84_sop_0_0_0_1_6_8_cry_9),.O(un84_sop_0_0_0_1_6_8[13:13])); MUXCY_L un84_sop_0_0_0_1_6_8_cry_10_cZ(.DI(un84_sop_0_0_0_10_0[13:13]),.CI(un84_sop_0_0_0_1_6_8_cry_9),.S(un84_sop_0_0_0_1_6_8_axb_10),.LO(un84_sop_0_0_0_1_6_8_cry_10)); XORCY un84_sop_0_0_0_1_6_8_s_9(.LI(un84_sop_0_0_0_1_6_8_axb_9),.CI(un84_sop_0_0_0_1_6_8_cry_8),.O(un84_sop_0_0_0_1_6_8[12:12])); MUXCY_L un84_sop_0_0_0_1_6_8_cry_9_cZ(.DI(un84_sop_0_0_0_10_0[12:12]),.CI(un84_sop_0_0_0_1_6_8_cry_8),.S(un84_sop_0_0_0_1_6_8_axb_9),.LO(un84_sop_0_0_0_1_6_8_cry_9)); XORCY un84_sop_0_0_0_1_6_8_s_8(.LI(un84_sop_0_0_0_1_6_8_axb_8),.CI(un84_sop_0_0_0_1_6_8_cry_7),.O(un84_sop_0_0_0_1_6_8[11:11])); MUXCY_L un84_sop_0_0_0_1_6_8_cry_8_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_7),.CI(un84_sop_0_0_0_1_6_8_cry_7),.S(un84_sop_0_0_0_1_6_8_axb_8),.LO(un84_sop_0_0_0_1_6_8_cry_8)); XORCY un84_sop_0_0_0_1_6_8_s_7(.LI(un84_sop_0_0_0_1_6_8_axb_7),.CI(un84_sop_0_0_0_1_6_8_cry_6),.O(un84_sop_0_0_0_1_6_8[10:10])); MUXCY_L un84_sop_0_0_0_1_6_8_cry_7_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_6),.CI(un84_sop_0_0_0_1_6_8_cry_6),.S(un84_sop_0_0_0_1_6_8_axb_7),.LO(un84_sop_0_0_0_1_6_8_cry_7)); XORCY un84_sop_0_0_0_1_6_8_s_6(.LI(un84_sop_0_0_0_1_6_8_axb_6),.CI(un84_sop_0_0_0_1_6_8_cry_5),.O(un84_sop_0_0_0_1_6_8[9:9])); MUXCY_L un84_sop_0_0_0_1_6_8_cry_6_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_5),.CI(un84_sop_0_0_0_1_6_8_cry_5),.S(un84_sop_0_0_0_1_6_8_axb_6),.LO(un84_sop_0_0_0_1_6_8_cry_6)); XORCY un84_sop_0_0_0_1_6_8_s_5(.LI(un84_sop_0_0_0_1_6_8_axb_5),.CI(un84_sop_0_0_0_1_6_8_cry_4),.O(un84_sop_0_0_0_1_6_8[8:8])); MUXCY_L un84_sop_0_0_0_1_6_8_cry_5_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_4),.CI(un84_sop_0_0_0_1_6_8_cry_4),.S(un84_sop_0_0_0_1_6_8_axb_5),.LO(un84_sop_0_0_0_1_6_8_cry_5)); XORCY un84_sop_0_0_0_1_6_8_s_4(.LI(un84_sop_0_0_0_1_6_8_axb_4),.CI(un84_sop_0_0_0_1_6_8_cry_3),.O(un84_sop_0_0_0_1_6_8[7:7])); MUXCY_L un84_sop_0_0_0_1_6_8_cry_4_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_3),.CI(un84_sop_0_0_0_1_6_8_cry_3),.S(un84_sop_0_0_0_1_6_8_axb_4),.LO(un84_sop_0_0_0_1_6_8_cry_4)); XORCY un84_sop_0_0_0_1_6_8_s_3(.LI(un84_sop_0_0_0_1_6_8_axb_3),.CI(un84_sop_0_0_0_1_6_8_cry_2),.O(un84_sop_0_0_0_1_6_8[6:6])); MUXCY_L un84_sop_0_0_0_1_6_8_cry_3_cZ(.DI(un84_sop_0_0_0_1_6_8_axb_2_lut6_2_O5),.CI(un84_sop_0_0_0_1_6_8_cry_2),.S(un84_sop_0_0_0_1_6_8_axb_3),.LO(un84_sop_0_0_0_1_6_8_cry_3)); XORCY un84_sop_0_0_0_1_6_8_s_2(.LI(un84_sop_0_0_0_1_6_8_axb_2),.CI(un84_sop_0_0_0_1_6_8_cry_1),.O(un84_sop_0_0_0_1_6_8[5:5])); MUXCY_L un84_sop_0_0_0_1_6_8_cry_2_cZ(.DI(GND),.CI(un84_sop_0_0_0_1_6_8_cry_1),.S(un84_sop_0_0_0_1_6_8_axb_2),.LO(un84_sop_0_0_0_1_6_8_cry_2)); XORCY un84_sop_0_0_0_1_6_8_s_1(.LI(un84_sop_0_0_0_1_6_8_axb_1),.CI(un84_sop_0_0_0_1_6_8_cry_0),.O(un84_sop_0_0_0_1_6_8[4:4])); MUXCY_L un84_sop_0_0_0_1_6_8_cry_1_cZ(.DI(un84_sop_0_0_0_10_0[4:4]),.CI(un84_sop_0_0_0_1_6_8_cry_0),.S(un84_sop_0_0_0_1_6_8_axb_1),.LO(un84_sop_0_0_0_1_6_8_cry_1)); MUXCY_L un84_sop_0_0_0_1_6_8_cry_0_cZ(.DI(un84_sop_0_0_0_10_0[3:3]),.CI(GND),.S(un84_sop_0_0_0_1_6_8[3:3]),.LO(un84_sop_0_0_0_1_6_8_cry_0)); XORCY un84_sop_0_0_0_6_6_0_s_14(.LI(un84_sop_0_0_0_6_6_0_axb_14),.CI(un84_sop_0_0_0_6_6_0_cry_13),.O(un84_sop_0_0_0_1_6_6[14:14])); XORCY un84_sop_0_0_0_6_6_0_s_13(.LI(un84_sop_0_0_0_6_6_0_axb_13),.CI(un84_sop_0_0_0_6_6_0_cry_12),.O(un84_sop_0_0_0_1_6_6[13:13])); MUXCY_L un84_sop_0_0_0_6_6_0_cry_13_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_12),.CI(un84_sop_0_0_0_6_6_0_cry_12),.S(un84_sop_0_0_0_6_6_0_axb_13),.LO(un84_sop_0_0_0_6_6_0_cry_13)); XORCY un84_sop_0_0_0_6_6_0_s_12(.LI(un84_sop_0_0_0_6_6_0_axb_12),.CI(un84_sop_0_0_0_6_6_0_cry_11),.O(un84_sop_0_0_0_1_6_6[12:12])); MUXCY_L un84_sop_0_0_0_6_6_0_cry_12_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_11),.CI(un84_sop_0_0_0_6_6_0_cry_11),.S(un84_sop_0_0_0_6_6_0_axb_12),.LO(un84_sop_0_0_0_6_6_0_cry_12)); XORCY un84_sop_0_0_0_6_6_0_s_11(.LI(un84_sop_0_0_0_6_6_0_axb_11),.CI(un84_sop_0_0_0_6_6_0_cry_10),.O(un84_sop_0_0_0_1_6_6[11:11])); MUXCY_L un84_sop_0_0_0_6_6_0_cry_11_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_10),.CI(un84_sop_0_0_0_6_6_0_cry_10),.S(un84_sop_0_0_0_6_6_0_axb_11),.LO(un84_sop_0_0_0_6_6_0_cry_11)); XORCY un84_sop_0_0_0_6_6_0_s_10(.LI(un84_sop_0_0_0_6_6_0_axb_10),.CI(un84_sop_0_0_0_6_6_0_cry_9),.O(un84_sop_0_0_0_1_6_6[10:10])); MUXCY_L un84_sop_0_0_0_6_6_0_cry_10_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_9),.CI(un84_sop_0_0_0_6_6_0_cry_9),.S(un84_sop_0_0_0_6_6_0_axb_10),.LO(un84_sop_0_0_0_6_6_0_cry_10)); XORCY un84_sop_0_0_0_6_6_0_s_9(.LI(un84_sop_0_0_0_6_6_0_axb_9),.CI(un84_sop_0_0_0_6_6_0_cry_8),.O(un84_sop_0_0_0_1_6_6[9:9])); MUXCY_L un84_sop_0_0_0_6_6_0_cry_9_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_8),.CI(un84_sop_0_0_0_6_6_0_cry_8),.S(un84_sop_0_0_0_6_6_0_axb_9),.LO(un84_sop_0_0_0_6_6_0_cry_9)); XORCY un84_sop_0_0_0_6_6_0_s_8(.LI(un84_sop_0_0_0_6_6_0_axb_8),.CI(un84_sop_0_0_0_6_6_0_cry_7),.O(un84_sop_0_0_0_1_6_6[8:8])); MUXCY_L un84_sop_0_0_0_6_6_0_cry_8_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_7),.CI(un84_sop_0_0_0_6_6_0_cry_7),.S(un84_sop_0_0_0_6_6_0_axb_8),.LO(un84_sop_0_0_0_6_6_0_cry_8)); XORCY un84_sop_0_0_0_6_6_0_s_7(.LI(un84_sop_0_0_0_6_6_0_axb_7),.CI(un84_sop_0_0_0_6_6_0_cry_6),.O(un84_sop_0_0_0_1_6_6[7:7])); MUXCY_L un84_sop_0_0_0_6_6_0_cry_7_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_6),.CI(un84_sop_0_0_0_6_6_0_cry_6),.S(un84_sop_0_0_0_6_6_0_axb_7),.LO(un84_sop_0_0_0_6_6_0_cry_7)); XORCY un84_sop_0_0_0_6_6_0_s_6(.LI(un84_sop_0_0_0_6_6_0_axb_6),.CI(un84_sop_0_0_0_6_6_0_cry_5),.O(un84_sop_0_0_0_1_6_6[6:6])); MUXCY_L un84_sop_0_0_0_6_6_0_cry_6_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_5),.CI(un84_sop_0_0_0_6_6_0_cry_5),.S(un84_sop_0_0_0_6_6_0_axb_6),.LO(un84_sop_0_0_0_6_6_0_cry_6)); XORCY un84_sop_0_0_0_6_6_0_s_5(.LI(un84_sop_0_0_0_6_6_0_axb_5),.CI(un84_sop_0_0_0_6_6_0_cry_4),.O(un84_sop_0_0_0_1_6_6[5:5])); MUXCY_L un84_sop_0_0_0_6_6_0_cry_5_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_4),.CI(un84_sop_0_0_0_6_6_0_cry_4),.S(un84_sop_0_0_0_6_6_0_axb_5),.LO(un84_sop_0_0_0_6_6_0_cry_5)); XORCY un84_sop_0_0_0_6_6_0_s_4(.LI(un84_sop_0_0_0_6_6_0_axb_4),.CI(un84_sop_0_0_0_6_6_0_cry_3),.O(un84_sop_0_0_0_1_6_6[4:4])); MUXCY_L un84_sop_0_0_0_6_6_0_cry_4_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_3),.CI(un84_sop_0_0_0_6_6_0_cry_3),.S(un84_sop_0_0_0_6_6_0_axb_4),.LO(un84_sop_0_0_0_6_6_0_cry_4)); XORCY un84_sop_0_0_0_6_6_0_s_3(.LI(un84_sop_0_0_0_6_6_0_axb_3),.CI(un84_sop_0_0_0_6_6_0_cry_2),.O(un84_sop_0_0_0_1_6_6[3:3])); MUXCY_L un84_sop_0_0_0_6_6_0_cry_3_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_2),.CI(un84_sop_0_0_0_6_6_0_cry_2),.S(un84_sop_0_0_0_6_6_0_axb_3),.LO(un84_sop_0_0_0_6_6_0_cry_3)); XORCY un84_sop_0_0_0_6_6_0_s_2(.LI(un84_sop_0_0_0_6_6_0_axb_2),.CI(un84_sop_0_0_0_6_6_0_cry_1),.O(un84_sop_0_0_0_1_6_6[2:2])); MUXCY_L un84_sop_0_0_0_6_6_0_cry_2_cZ(.DI(un84_sop_0_0_0_6_6_0_axb_1_lut6_2_O5),.CI(un84_sop_0_0_0_6_6_0_cry_1),.S(un84_sop_0_0_0_6_6_0_axb_2),.LO(un84_sop_0_0_0_6_6_0_cry_2)); XORCY un84_sop_0_0_0_6_6_0_s_1(.LI(un84_sop_0_0_0_6_6_0_axb_1),.CI(un84_sop_0_0_0_6_6_0_cry_0),.O(un84_sop_0_0_0_1_6_6[1:1])); MUXCY_L un84_sop_0_0_0_6_6_0_cry_1_cZ(.DI(GND),.CI(un84_sop_0_0_0_6_6_0_cry_0),.S(un84_sop_0_0_0_6_6_0_axb_1),.LO(un84_sop_0_0_0_6_6_0_cry_1)); MUXCY_L un84_sop_0_0_0_6_6_0_cry_0_cZ(.DI(un1_x_8_0[4:4]),.CI(un84_sop_0_0_0_6_6_0_cry_0_cy),.S(un84_sop_0_0_0_6_0_axb_0_1),.LO(un84_sop_0_0_0_6_6_0_cry_0)); XORCY un84_sop_0_0_0_11_0_s_14(.LI(un84_sop_0_0_0_11_0_axb_14),.CI(un84_sop_0_0_0_11_0_cry_13),.O(un84_sop_0_0_0_0_8[14:14])); XORCY un84_sop_0_0_0_11_0_s_13(.LI(un84_sop_0_0_0_11_0_axb_13),.CI(un84_sop_0_0_0_11_0_cry_12),.O(un84_sop_0_0_0_0_8[13:13])); MUXCY_L un84_sop_0_0_0_11_0_cry_13_cZ(.DI(un84_sop_0_0_0_11_0_o5_12),.CI(un84_sop_0_0_0_11_0_cry_12),.S(un84_sop_0_0_0_11_0_axb_13),.LO(un84_sop_0_0_0_11_0_cry_13)); XORCY un84_sop_0_0_0_11_0_s_12(.LI(un84_sop_0_0_0_11_0_axb_12),.CI(un84_sop_0_0_0_11_0_cry_11),.O(un84_sop_0_0_0_0_8[12:12])); MUXCY_L un84_sop_0_0_0_11_0_cry_12_cZ(.DI(un84_sop_0_0_0_11_0_o5_11),.CI(un84_sop_0_0_0_11_0_cry_11),.S(un84_sop_0_0_0_11_0_axb_12),.LO(un84_sop_0_0_0_11_0_cry_12)); XORCY un84_sop_0_0_0_11_0_s_11(.LI(un84_sop_0_0_0_11_0_axb_11),.CI(un84_sop_0_0_0_11_0_cry_10),.O(un84_sop_0_0_0_0_8[11:11])); MUXCY_L un84_sop_0_0_0_11_0_cry_11_cZ(.DI(un84_sop_0_0_0_11_0_o5_10),.CI(un84_sop_0_0_0_11_0_cry_10),.S(un84_sop_0_0_0_11_0_axb_11),.LO(un84_sop_0_0_0_11_0_cry_11)); XORCY un84_sop_0_0_0_11_0_s_10(.LI(un84_sop_0_0_0_11_0_axb_10),.CI(un84_sop_0_0_0_11_0_cry_9),.O(un84_sop_0_0_0_0_8[10:10])); MUXCY_L un84_sop_0_0_0_11_0_cry_10_cZ(.DI(un84_sop_0_0_0_11_0_o5_9),.CI(un84_sop_0_0_0_11_0_cry_9),.S(un84_sop_0_0_0_11_0_axb_10),.LO(un84_sop_0_0_0_11_0_cry_10)); XORCY un84_sop_0_0_0_11_0_s_9(.LI(un84_sop_0_0_0_11_0_axb_9),.CI(un84_sop_0_0_0_11_0_cry_8),.O(un84_sop_0_0_0_0_8[9:9])); MUXCY_L un84_sop_0_0_0_11_0_cry_9_cZ(.DI(un84_sop_0_0_0_11_0_o5_8),.CI(un84_sop_0_0_0_11_0_cry_8),.S(un84_sop_0_0_0_11_0_axb_9),.LO(un84_sop_0_0_0_11_0_cry_9)); XORCY un84_sop_0_0_0_11_0_s_8(.LI(un84_sop_0_0_0_11_0_axb_8),.CI(un84_sop_0_0_0_11_0_cry_7),.O(un84_sop_0_0_0_0_8[8:8])); MUXCY_L un84_sop_0_0_0_11_0_cry_8_cZ(.DI(un84_sop_0_0_0_11_0_o5_7),.CI(un84_sop_0_0_0_11_0_cry_7),.S(un84_sop_0_0_0_11_0_axb_8),.LO(un84_sop_0_0_0_11_0_cry_8)); XORCY un84_sop_0_0_0_11_0_s_7(.LI(un84_sop_0_0_0_11_0_axb_7),.CI(un84_sop_0_0_0_11_0_cry_6),.O(un84_sop_0_0_0_0_8[7:7])); MUXCY_L un84_sop_0_0_0_11_0_cry_7_cZ(.DI(un84_sop_0_0_0_11_0_o5_6),.CI(un84_sop_0_0_0_11_0_cry_6),.S(un84_sop_0_0_0_11_0_axb_7),.LO(un84_sop_0_0_0_11_0_cry_7)); XORCY un84_sop_0_0_0_11_0_s_6(.LI(un84_sop_0_0_0_11_0_axb_6),.CI(un84_sop_0_0_0_11_0_cry_5),.O(un84_sop_0_0_0_0_8[6:6])); MUXCY_L un84_sop_0_0_0_11_0_cry_6_cZ(.DI(un84_sop_0_0_0_11_0_o5_5),.CI(un84_sop_0_0_0_11_0_cry_5),.S(un84_sop_0_0_0_11_0_axb_6),.LO(un84_sop_0_0_0_11_0_cry_6)); XORCY un84_sop_0_0_0_11_0_s_5(.LI(un84_sop_0_0_0_11_0_axb_5),.CI(un84_sop_0_0_0_11_0_cry_4),.O(un84_sop_0_0_0_0_8[5:5])); MUXCY_L un84_sop_0_0_0_11_0_cry_5_cZ(.DI(un84_sop_0_0_0_11_0_o5_4),.CI(un84_sop_0_0_0_11_0_cry_4),.S(un84_sop_0_0_0_11_0_axb_5),.LO(un84_sop_0_0_0_11_0_cry_5)); XORCY un84_sop_0_0_0_11_0_s_4(.LI(un84_sop_0_0_0_11_0_axb_4),.CI(un84_sop_0_0_0_11_0_cry_3),.O(un84_sop_0_0_0_0_8[4:4])); MUXCY_L un84_sop_0_0_0_11_0_cry_4_cZ(.DI(un84_sop_0_0_0_11_0_o5_3),.CI(un84_sop_0_0_0_11_0_cry_3),.S(un84_sop_0_0_0_11_0_axb_4),.LO(un84_sop_0_0_0_11_0_cry_4)); XORCY un84_sop_0_0_0_11_0_s_3(.LI(un84_sop_0_0_0_11_0_axb_3),.CI(un84_sop_0_0_0_11_0_cry_2),.O(un84_sop_0_0_0_0_8[3:3])); MUXCY_L un84_sop_0_0_0_11_0_cry_3_cZ(.DI(un84_sop_0_0_0_11_0_o5_2),.CI(un84_sop_0_0_0_11_0_cry_2),.S(un84_sop_0_0_0_11_0_axb_3),.LO(un84_sop_0_0_0_11_0_cry_3)); XORCY un84_sop_0_0_0_11_0_s_2(.LI(un84_sop_0_0_0_11_0_axb_2),.CI(un84_sop_0_0_0_11_0_cry_1),.O(un84_sop_0_0_0_0_8[2:2])); MUXCY_L un84_sop_0_0_0_11_0_cry_2_cZ(.DI(un84_sop_0_0_0_11_0_cry_2_RNO),.CI(un84_sop_0_0_0_11_0_cry_1),.S(un84_sop_0_0_0_11_0_axb_2),.LO(un84_sop_0_0_0_11_0_cry_2)); XORCY un84_sop_0_0_0_11_0_s_1(.LI(un84_sop_0_0_0_11_0_axb_1),.CI(un84_sop_0_0_0_11_0_cry_0),.O(un84_sop_0_0_0_0_8[1:1])); MUXCY_L un84_sop_0_0_0_11_0_cry_1_cZ(.DI(un84_sop_0_0_0_0_11_6[1:1]),.CI(un84_sop_0_0_0_11_0_cry_0),.S(un84_sop_0_0_0_11_0_axb_1),.LO(un84_sop_0_0_0_11_0_cry_1)); XORCY un84_sop_0_0_0_11_0_s_0(.LI(un84_sop_0_0_0_11_0_axb_0),.CI(un84_sop_0_0_0_11_0_cry_0_cy),.O(un84_sop_0_0_0_0_8[0:0])); MUXCY_L un84_sop_0_0_0_11_0_cry_0_cZ(.DI(un84_sop_0_0_0_0_11_6[0:0]),.CI(un84_sop_0_0_0_11_0_cry_0_cy),.S(un84_sop_0_0_0_11_0_axb_0),.LO(un84_sop_0_0_0_11_0_cry_0)); XORCY un84_sop_0_0_0_11_6_0_s_13(.LI(un84_sop_0_0_0_11_6_0_axb_13),.CI(un84_sop_0_0_0_11_6_0_cry_12),.O(un84_sop_0_0_0_0_11_6[14:14])); XORCY un84_sop_0_0_0_11_6_0_s_12(.LI(un84_sop_0_0_0_11_6_0_axb_12),.CI(un84_sop_0_0_0_11_6_0_cry_11),.O(un84_sop_0_0_0_0_11_6[12:12])); MUXCY_L un84_sop_0_0_0_11_6_0_cry_12_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_11),.CI(un84_sop_0_0_0_11_6_0_cry_11),.S(un84_sop_0_0_0_11_6_0_axb_12),.LO(un84_sop_0_0_0_11_6_0_cry_12)); XORCY un84_sop_0_0_0_11_6_0_s_11(.LI(un84_sop_0_0_0_11_6_0_axb_11),.CI(un84_sop_0_0_0_11_6_0_cry_10),.O(un84_sop_0_0_0_0_11_6[11:11])); MUXCY_L un84_sop_0_0_0_11_6_0_cry_11_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_10),.CI(un84_sop_0_0_0_11_6_0_cry_10),.S(un84_sop_0_0_0_11_6_0_axb_11),.LO(un84_sop_0_0_0_11_6_0_cry_11)); XORCY un84_sop_0_0_0_11_6_0_s_10(.LI(un84_sop_0_0_0_11_6_0_axb_10),.CI(un84_sop_0_0_0_11_6_0_cry_9),.O(un84_sop_0_0_0_0_11_6[10:10])); MUXCY_L un84_sop_0_0_0_11_6_0_cry_10_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_9),.CI(un84_sop_0_0_0_11_6_0_cry_9),.S(un84_sop_0_0_0_11_6_0_axb_10),.LO(un84_sop_0_0_0_11_6_0_cry_10)); XORCY un84_sop_0_0_0_11_6_0_s_9(.LI(un84_sop_0_0_0_11_6_0_axb_9),.CI(un84_sop_0_0_0_11_6_0_cry_8),.O(un84_sop_0_0_0_0_11_6[9:9])); MUXCY_L un84_sop_0_0_0_11_6_0_cry_9_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_8),.CI(un84_sop_0_0_0_11_6_0_cry_8),.S(un84_sop_0_0_0_11_6_0_axb_9),.LO(un84_sop_0_0_0_11_6_0_cry_9)); XORCY un84_sop_0_0_0_11_6_0_s_8(.LI(un84_sop_0_0_0_11_6_0_axb_8),.CI(un84_sop_0_0_0_11_6_0_cry_7),.O(un84_sop_0_0_0_0_11_6[8:8])); MUXCY_L un84_sop_0_0_0_11_6_0_cry_8_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_7),.CI(un84_sop_0_0_0_11_6_0_cry_7),.S(un84_sop_0_0_0_11_6_0_axb_8),.LO(un84_sop_0_0_0_11_6_0_cry_8)); XORCY un84_sop_0_0_0_11_6_0_s_7(.LI(un84_sop_0_0_0_11_6_0_axb_7),.CI(un84_sop_0_0_0_11_6_0_cry_6),.O(un84_sop_0_0_0_0_11_6[7:7])); MUXCY_L un84_sop_0_0_0_11_6_0_cry_7_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_6),.CI(un84_sop_0_0_0_11_6_0_cry_6),.S(un84_sop_0_0_0_11_6_0_axb_7),.LO(un84_sop_0_0_0_11_6_0_cry_7)); XORCY un84_sop_0_0_0_11_6_0_s_6(.LI(un84_sop_0_0_0_11_6_0_axb_6),.CI(un84_sop_0_0_0_11_6_0_cry_5),.O(un84_sop_0_0_0_0_11_6[6:6])); MUXCY_L un84_sop_0_0_0_11_6_0_cry_6_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_5),.CI(un84_sop_0_0_0_11_6_0_cry_5),.S(un84_sop_0_0_0_11_6_0_axb_6),.LO(un84_sop_0_0_0_11_6_0_cry_6)); XORCY un84_sop_0_0_0_11_6_0_s_5(.LI(un84_sop_0_0_0_11_6_0_axb_5),.CI(un84_sop_0_0_0_11_6_0_cry_4),.O(un84_sop_0_0_0_0_11_6[5:5])); MUXCY_L un84_sop_0_0_0_11_6_0_cry_5_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_4),.CI(un84_sop_0_0_0_11_6_0_cry_4),.S(un84_sop_0_0_0_11_6_0_axb_5),.LO(un84_sop_0_0_0_11_6_0_cry_5)); XORCY un84_sop_0_0_0_11_6_0_s_4(.LI(un84_sop_0_0_0_11_6_0_axb_4),.CI(un84_sop_0_0_0_11_6_0_cry_3),.O(un84_sop_0_0_0_0_11_6[4:4])); MUXCY_L un84_sop_0_0_0_11_6_0_cry_4_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_3),.CI(un84_sop_0_0_0_11_6_0_cry_3),.S(un84_sop_0_0_0_11_6_0_axb_4),.LO(un84_sop_0_0_0_11_6_0_cry_4)); XORCY un84_sop_0_0_0_11_6_0_s_3(.LI(un84_sop_0_0_0_11_6_0_axb_3),.CI(un84_sop_0_0_0_11_6_0_cry_2),.O(un84_sop_0_0_0_0_11_6[3:3])); MUXCY_L un84_sop_0_0_0_11_6_0_cry_3_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_2),.CI(un84_sop_0_0_0_11_6_0_cry_2),.S(un84_sop_0_0_0_11_6_0_axb_3),.LO(un84_sop_0_0_0_11_6_0_cry_3)); XORCY un84_sop_0_0_0_11_6_0_s_2(.LI(un84_sop_0_0_0_11_6_0_axb_2),.CI(un84_sop_0_0_0_11_6_0_cry_1),.O(un84_sop_0_0_0_0_11_6[2:2])); MUXCY_L un84_sop_0_0_0_11_6_0_cry_2_cZ(.DI(un84_sop_0_0_0_11_6_0_axb_1_lut6_2_O5),.CI(un84_sop_0_0_0_11_6_0_cry_1),.S(un84_sop_0_0_0_11_6_0_axb_2),.LO(un84_sop_0_0_0_11_6_0_cry_2)); XORCY un84_sop_0_0_0_11_6_0_s_1(.LI(un84_sop_0_0_0_11_6_0_axb_1),.CI(un84_sop_0_0_0_11_6_0_cry_0),.O(un84_sop_0_0_0_0_11_6[1:1])); MUXCY_L un84_sop_0_0_0_11_6_0_cry_1_cZ(.DI(GND),.CI(un84_sop_0_0_0_11_6_0_cry_0),.S(un84_sop_0_0_0_11_6_0_axb_1),.LO(un84_sop_0_0_0_11_6_0_cry_1)); MUXCY_L un84_sop_0_0_0_11_6_0_cry_0_cZ(.DI(un1_x_13_0_0[5:5]),.CI(un84_sop_0_0_0_11_6_0_cry_0_cy),.S(un84_sop_0_0_0_6_0_axb_0_0),.LO(un84_sop_0_0_0_11_6_0_cry_0)); DSP48E1 desc57(.ACOUT(ACOUT[29:0]),.BCOUT({x_0_10[7:7],x_0_9[7:7],x_0_8[7:7],x_0_7[7:7],x_0_6[7:7],x_0_5[7:7],x_0_4[7:7],x_0_3[7:7],x_0_2[7:7],x_0_1[7:7],x_0_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT),.CARRYOUT(CARRYOUT[3:0]),.MULTSIGNOUT(MULTSIGNOUT),.OVERFLOW(OVERFLOW),.P({P_uc[47:12],un1_x_1[15:4]}),.PATTERNBDETECT(PATTERNBDETECT),.PATTERNDETECT(PATTERNDETECT),.PCOUT(PCOUT[47:0]),.UNDERFLOW(UNDERFLOW),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND)); defparam desc57.ACASCREG=0; defparam desc57.ADREG=0; defparam desc57.ALUMODEREG=0; defparam desc57.AREG=0; defparam desc57.AUTORESET_PATDET="NO_RESET"; defparam desc57.A_INPUT="DIRECT"; defparam desc57.BCASCREG=1; defparam desc57.BREG=1; defparam desc57.B_INPUT="DIRECT"; defparam desc57.CARRYINREG=0; defparam desc57.CARRYINSELREG=0; defparam desc57.CREG=1; defparam desc57.DREG=0; defparam desc57.INMODEREG=0; defparam desc57.MREG=0; defparam desc57.OPMODEREG=0; defparam desc57.PREG=1; defparam desc57.USE_DPORT="FALSE"; defparam desc57.USE_MULT="MULTIPLY"; defparam desc57.USE_SIMD="ONE48"; DSP48E1 desc58(.ACOUT(ACOUT_0[29:0]),.BCOUT({x_9_10[7:7],x_9_9[7:7],x_9_8[7:7],x_9_7[7:7],x_9_6[7:7],x_9_5[7:7],x_9_4[7:7],x_9_3[7:7],x_9_2[7:7],x_9_1[7:7],x_9_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_0),.CARRYOUT(CARRYOUT_0[3:0]),.MULTSIGNOUT(MULTSIGNOUT_0),.OVERFLOW(OVERFLOW_0),.P({P_uc_0[47:12],un1_x_12_0_0[15:4]}),.PATTERNBDETECT(PATTERNBDETECT_0),.PATTERNDETECT(PATTERNDETECT_0),.PCOUT(PCOUT_0[47:0]),.UNDERFLOW(UNDERFLOW_0),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(VCC),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(VCC),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND)); defparam desc58.ACASCREG=2; defparam desc58.ADREG=0; defparam desc58.ALUMODEREG=0; defparam desc58.AREG=2; defparam desc58.AUTORESET_PATDET="NO_RESET"; defparam desc58.A_INPUT="DIRECT"; defparam desc58.BCASCREG=2; defparam desc58.BREG=2; defparam desc58.B_INPUT="DIRECT"; defparam desc58.CARRYINREG=0; defparam desc58.CARRYINSELREG=0; defparam desc58.CREG=1; defparam desc58.DREG=0; defparam desc58.INMODEREG=0; defparam desc58.MREG=0; defparam desc58.OPMODEREG=0; defparam desc58.PREG=1; defparam desc58.USE_DPORT="FALSE"; defparam desc58.USE_MULT="MULTIPLY"; defparam desc58.USE_SIMD="ONE48"; DSP48E1 desc59(.ACOUT(ACOUT_1[29:0]),.BCOUT(BCOUT_1[17:0]),.CARRYCASCOUT(CARRYCASCOUT_1),.CARRYOUT(CARRYOUT_1[3:0]),.MULTSIGNOUT(MULTSIGNOUT_1),.OVERFLOW(OVERFLOW_1),.P({P_uc_1[47:12],un1_x_14_0_0[15:4]}),.PATTERNBDETECT(PATTERNBDETECT_1),.PATTERNDETECT(PATTERNDETECT_1),.PCOUT(PCOUT_1[47:0]),.UNDERFLOW(UNDERFLOW_1),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_10_10[7:7],x_10_9[7:7],x_10_8[7:7],x_10_7[7:7],x_10_6[7:7],x_10_5[7:7],x_10_4[7:7],x_10_3[7:7],x_10_2[7:7],x_10_1[7:7],x_10_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND)); defparam desc59.ACASCREG=0; defparam desc59.ADREG=0; defparam desc59.ALUMODEREG=0; defparam desc59.AREG=0; defparam desc59.AUTORESET_PATDET="NO_RESET"; defparam desc59.A_INPUT="DIRECT"; defparam desc59.BCASCREG=1; defparam desc59.BREG=1; defparam desc59.B_INPUT="CASCADE"; defparam desc59.CARRYINREG=0; defparam desc59.CARRYINSELREG=0; defparam desc59.CREG=1; defparam desc59.DREG=0; defparam desc59.INMODEREG=0; defparam desc59.MREG=0; defparam desc59.OPMODEREG=0; defparam desc59.PREG=1; defparam desc59.USE_DPORT="FALSE"; defparam desc59.USE_MULT="MULTIPLY"; defparam desc59.USE_SIMD="ONE48"; DSP48E1 desc60(.ACOUT(ACOUT_2[29:0]),.BCOUT({x_2_10[7:7],x_2_9[7:7],x_2_8[7:7],x_2_7[7:7],x_2_6[7:7],x_2_5[7:7],x_2_4[7:7],x_2_3[7:7],x_2_2[7:7],x_2_1[7:7],x_2_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_2),.CARRYOUT(CARRYOUT_2[3:0]),.MULTSIGNOUT(MULTSIGNOUT_2),.OVERFLOW(OVERFLOW_2),.P({P_uc_2[47:12],un1_x_3[15:4]}),.PATTERNBDETECT(PATTERNBDETECT_2),.PATTERNDETECT(PATTERNDETECT_2),.PCOUT(PCOUT_2[47:0]),.UNDERFLOW(UNDERFLOW_2),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_1_10[7:7],x_1_9[7:7],x_1_8[7:7],x_1_7[7:7],x_1_6[7:7],x_1_5[7:7],x_1_4[7:7],x_1_3[7:7],x_1_2[7:7],x_1_1[7:7],x_1_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND)); defparam desc60.ACASCREG=0; defparam desc60.ADREG=0; defparam desc60.ALUMODEREG=0; defparam desc60.AREG=0; defparam desc60.AUTORESET_PATDET="NO_RESET"; defparam desc60.A_INPUT="DIRECT"; defparam desc60.BCASCREG=1; defparam desc60.BREG=1; defparam desc60.B_INPUT="CASCADE"; defparam desc60.CARRYINREG=0; defparam desc60.CARRYINSELREG=0; defparam desc60.CREG=1; defparam desc60.DREG=0; defparam desc60.INMODEREG=0; defparam desc60.MREG=0; defparam desc60.OPMODEREG=0; defparam desc60.PREG=1; defparam desc60.USE_DPORT="FALSE"; defparam desc60.USE_MULT="MULTIPLY"; defparam desc60.USE_SIMD="ONE48"; DSP48E1 desc61(.ACOUT(ACOUT_3[29:0]),.BCOUT({x_6_10[7:7],x_6_9[7:7],x_6_8[7:7],x_6_7[7:7],x_6_6[7:7],x_6_5[7:7],x_6_4[7:7],x_6_3[7:7],x_6_2[7:7],x_6_1[7:7],x_6_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_3),.CARRYOUT(CARRYOUT_3[3:0]),.MULTSIGNOUT(MULTSIGNOUT_3),.OVERFLOW(OVERFLOW_3),.P({P_uc_3[47:12],un1_x_8_0[15:4]}),.PATTERNBDETECT(PATTERNBDETECT_3),.PATTERNDETECT(PATTERNDETECT_3),.PCOUT(PCOUT_3[47:0]),.UNDERFLOW(UNDERFLOW_3),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_5_10[7:7],x_5_9[7:7],x_5_8[7:7],x_5_7[7:7],x_5_6[7:7],x_5_5[7:7],x_5_4[7:7],x_5_3[7:7],x_5_2[7:7],x_5_1[7:7],x_5_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND)); defparam desc61.ACASCREG=0; defparam desc61.ADREG=0; defparam desc61.ALUMODEREG=0; defparam desc61.AREG=0; defparam desc61.AUTORESET_PATDET="NO_RESET"; defparam desc61.A_INPUT="DIRECT"; defparam desc61.BCASCREG=1; defparam desc61.BREG=1; defparam desc61.B_INPUT="CASCADE"; defparam desc61.CARRYINREG=0; defparam desc61.CARRYINSELREG=0; defparam desc61.CREG=1; defparam desc61.DREG=0; defparam desc61.INMODEREG=0; defparam desc61.MREG=0; defparam desc61.OPMODEREG=0; defparam desc61.PREG=1; defparam desc61.USE_DPORT="FALSE"; defparam desc61.USE_MULT="MULTIPLY"; defparam desc61.USE_SIMD="ONE48"; DSP48E1 desc62(.ACOUT(ACOUT_4[29:0]),.BCOUT({x_4_10[7:7],x_4_9[7:7],x_4_8[7:7],x_4_7[7:7],x_4_6[7:7],x_4_5[7:7],x_4_4[7:7],x_4_3[7:7],x_4_2[7:7],x_4_1[7:7],x_4_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_4),.CARRYOUT(CARRYOUT_4[3:0]),.MULTSIGNOUT(MULTSIGNOUT_4),.OVERFLOW(OVERFLOW_4),.P({P_uc_4[47:15],un1_x_6_0[15:1]}),.PATTERNBDETECT(PATTERNBDETECT_4),.PATTERNDETECT(PATTERNDETECT_4),.PCOUT(PCOUT_4[47:0]),.UNDERFLOW(UNDERFLOW_4),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,GND,VCC,GND,GND,GND}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_3_10[7:7],x_3_9[7:7],x_3_8[7:7],x_3_7[7:7],x_3_6[7:7],x_3_5[7:7],x_3_4[7:7],x_3_3[7:7],x_3_2[7:7],x_3_1[7:7],x_3_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND)); defparam desc62.ACASCREG=0; defparam desc62.ADREG=0; defparam desc62.ALUMODEREG=0; defparam desc62.AREG=0; defparam desc62.AUTORESET_PATDET="NO_RESET"; defparam desc62.A_INPUT="DIRECT"; defparam desc62.BCASCREG=1; defparam desc62.BREG=1; defparam desc62.B_INPUT="CASCADE"; defparam desc62.CARRYINREG=0; defparam desc62.CARRYINSELREG=0; defparam desc62.CREG=1; defparam desc62.DREG=0; defparam desc62.INMODEREG=0; defparam desc62.MREG=0; defparam desc62.OPMODEREG=0; defparam desc62.PREG=1; defparam desc62.USE_DPORT="FALSE"; defparam desc62.USE_MULT="MULTIPLY"; defparam desc62.USE_SIMD="ONE48"; DSP48E1 desc63(.ACOUT(ACOUT_5[29:0]),.BCOUT({x_3_10[7:7],x_3_9[7:7],x_3_8[7:7],x_3_7[7:7],x_3_6[7:7],x_3_5[7:7],x_3_4[7:7],x_3_3[7:7],x_3_2[7:7],x_3_1[7:7],x_3_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_5),.CARRYOUT(CARRYOUT_5[3:0]),.MULTSIGNOUT(MULTSIGNOUT_5),.OVERFLOW(OVERFLOW_5),.P({P_uc_5[47:15],P_uc_4[14:14],un1_x_4[15:2]}),.PATTERNBDETECT(PATTERNBDETECT_5),.PATTERNDETECT(PATTERNDETECT_5),.PCOUT(PCOUT_5[47:0]),.UNDERFLOW(UNDERFLOW_5),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,GND,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_2_10[7:7],x_2_9[7:7],x_2_8[7:7],x_2_7[7:7],x_2_6[7:7],x_2_5[7:7],x_2_4[7:7],x_2_3[7:7],x_2_2[7:7],x_2_1[7:7],x_2_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND)); defparam desc63.ACASCREG=0; defparam desc63.ADREG=0; defparam desc63.ALUMODEREG=0; defparam desc63.AREG=0; defparam desc63.AUTORESET_PATDET="NO_RESET"; defparam desc63.A_INPUT="DIRECT"; defparam desc63.BCASCREG=1; defparam desc63.BREG=1; defparam desc63.B_INPUT="CASCADE"; defparam desc63.CARRYINREG=0; defparam desc63.CARRYINSELREG=0; defparam desc63.CREG=1; defparam desc63.DREG=0; defparam desc63.INMODEREG=0; defparam desc63.MREG=0; defparam desc63.OPMODEREG=0; defparam desc63.PREG=1; defparam desc63.USE_DPORT="FALSE"; defparam desc63.USE_MULT="MULTIPLY"; defparam desc63.USE_SIMD="ONE48"; DSP48E1 desc64(.ACOUT(ACOUT_6[29:0]),.BCOUT({x_5_10[7:7],x_5_9[7:7],x_5_8[7:7],x_5_7[7:7],x_5_6[7:7],x_5_5[7:7],x_5_4[7:7],x_5_3[7:7],x_5_2[7:7],x_5_1[7:7],x_5_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_6),.CARRYOUT(CARRYOUT_6[3:0]),.MULTSIGNOUT(MULTSIGNOUT_6),.OVERFLOW(OVERFLOW_6),.P({P_uc_6[47:15],P_uc_5[14:14],un1_x_7_0[15:2]}),.PATTERNBDETECT(PATTERNBDETECT_6),.PATTERNDETECT(PATTERNDETECT_6),.PCOUT(PCOUT_6[47:0]),.UNDERFLOW(UNDERFLOW_6),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,GND,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_4_10[7:7],x_4_9[7:7],x_4_8[7:7],x_4_7[7:7],x_4_6[7:7],x_4_5[7:7],x_4_4[7:7],x_4_3[7:7],x_4_2[7:7],x_4_1[7:7],x_4_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND)); defparam desc64.ACASCREG=0; defparam desc64.ADREG=0; defparam desc64.ALUMODEREG=0; defparam desc64.AREG=0; defparam desc64.AUTORESET_PATDET="NO_RESET"; defparam desc64.A_INPUT="DIRECT"; defparam desc64.BCASCREG=1; defparam desc64.BREG=1; defparam desc64.B_INPUT="CASCADE"; defparam desc64.CARRYINREG=0; defparam desc64.CARRYINSELREG=0; defparam desc64.CREG=1; defparam desc64.DREG=0; defparam desc64.INMODEREG=0; defparam desc64.MREG=0; defparam desc64.OPMODEREG=0; defparam desc64.PREG=1; defparam desc64.USE_DPORT="FALSE"; defparam desc64.USE_MULT="MULTIPLY"; defparam desc64.USE_SIMD="ONE48"; DSP48E1 desc65(.ACOUT(ACOUT_7[29:0]),.BCOUT({x_10_10[7:7],x_10_9[7:7],x_10_8[7:7],x_10_7[7:7],x_10_6[7:7],x_10_5[7:7],x_10_4[7:7],x_10_3[7:7],x_10_2[7:7],x_10_1[7:7],x_10_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_7),.CARRYOUT(CARRYOUT_7[3:0]),.MULTSIGNOUT(MULTSIGNOUT_7),.OVERFLOW(OVERFLOW_7),.P({P_uc_7[47:15],P_uc_6[14:14],P_uc_4[13:12],P_uc[11:11],un1_x_13_0_0[15:5]}),.PATTERNBDETECT(PATTERNBDETECT_7),.PATTERNDETECT(PATTERNDETECT_7),.PCOUT(PCOUT_7[47:0]),.UNDERFLOW(UNDERFLOW_7),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_9_10[7:7],x_9_9[7:7],x_9_8[7:7],x_9_7[7:7],x_9_6[7:7],x_9_5[7:7],x_9_4[7:7],x_9_3[7:7],x_9_2[7:7],x_9_1[7:7],x_9_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND)); defparam desc65.ACASCREG=0; defparam desc65.ADREG=0; defparam desc65.ALUMODEREG=0; defparam desc65.AREG=0; defparam desc65.AUTORESET_PATDET="NO_RESET"; defparam desc65.A_INPUT="DIRECT"; defparam desc65.BCASCREG=1; defparam desc65.BREG=1; defparam desc65.B_INPUT="CASCADE"; defparam desc65.CARRYINREG=0; defparam desc65.CARRYINSELREG=0; defparam desc65.CREG=1; defparam desc65.DREG=0; defparam desc65.INMODEREG=0; defparam desc65.MREG=0; defparam desc65.OPMODEREG=0; defparam desc65.PREG=1; defparam desc65.USE_DPORT="FALSE"; defparam desc65.USE_MULT="MULTIPLY"; defparam desc65.USE_SIMD="ONE48"; DSP48E1 desc66(.ACOUT(ACOUT_8[29:0]),.BCOUT({x_1_10[7:7],x_1_9[7:7],x_1_8[7:7],x_1_7[7:7],x_1_6[7:7],x_1_5[7:7],x_1_4[7:7],x_1_3[7:7],x_1_2[7:7],x_1_1[7:7],x_1_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_8),.CARRYOUT(CARRYOUT_8[3:0]),.MULTSIGNOUT(MULTSIGNOUT_8),.OVERFLOW(OVERFLOW_8),.P({P_uc_8[47:15],P_uc_7[14:14],P_uc_5[13:12],P_uc_0[11:11],un1_x_2[15:5]}),.PATTERNBDETECT(PATTERNBDETECT_8),.PATTERNDETECT(PATTERNDETECT_8),.PCOUT(PCOUT_8[47:0]),.UNDERFLOW(UNDERFLOW_8),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_0_10[7:7],x_0_9[7:7],x_0_8[7:7],x_0_7[7:7],x_0_6[7:7],x_0_5[7:7],x_0_4[7:7],x_0_3[7:7],x_0_2[7:7],x_0_1[7:7],x_0_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND)); defparam desc66.ACASCREG=0; defparam desc66.ADREG=0; defparam desc66.ALUMODEREG=0; defparam desc66.AREG=0; defparam desc66.AUTORESET_PATDET="NO_RESET"; defparam desc66.A_INPUT="DIRECT"; defparam desc66.BCASCREG=1; defparam desc66.BREG=1; defparam desc66.B_INPUT="CASCADE"; defparam desc66.CARRYINREG=0; defparam desc66.CARRYINSELREG=0; defparam desc66.CREG=1; defparam desc66.DREG=0; defparam desc66.INMODEREG=0; defparam desc66.MREG=0; defparam desc66.OPMODEREG=0; defparam desc66.PREG=1; defparam desc66.USE_DPORT="FALSE"; defparam desc66.USE_MULT="MULTIPLY"; defparam desc66.USE_SIMD="ONE48"; DSP48E1 desc67(.ACOUT(ACOUT_9[29:0]),.BCOUT(BCOUT_9[17:0]),.CARRYCASCOUT(CARRYCASCOUT_9),.CARRYOUT(CARRYOUT_9[3:0]),.MULTSIGNOUT(MULTSIGNOUT_9),.OVERFLOW(OVERFLOW_9),.P({P_uc_9[47:15],P_uc_8[14:14],P_uc_6[13:12],P_uc_1[11:11],un1_x_9_0[15:5]}),.PATTERNBDETECT(PATTERNBDETECT_9),.PATTERNDETECT(PATTERNDETECT_9),.PCOUT(PCOUT_9[47:0]),.UNDERFLOW(UNDERFLOW_9),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_6_10[7:7],x_6_9[7:7],x_6_8[7:7],x_6_7[7:7],x_6_6[7:7],x_6_5[7:7],x_6_4[7:7],x_6_3[7:7],x_6_2[7:7],x_6_1[7:7],x_6_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND)); defparam desc67.ACASCREG=0; defparam desc67.ADREG=0; defparam desc67.ALUMODEREG=0; defparam desc67.AREG=0; defparam desc67.AUTORESET_PATDET="NO_RESET"; defparam desc67.A_INPUT="DIRECT"; defparam desc67.BCASCREG=1; defparam desc67.BREG=1; defparam desc67.B_INPUT="CASCADE"; defparam desc67.CARRYINREG=0; defparam desc67.CARRYINSELREG=0; defparam desc67.CREG=1; defparam desc67.DREG=0; defparam desc67.INMODEREG=0; defparam desc67.MREG=0; defparam desc67.OPMODEREG=0; defparam desc67.PREG=1; defparam desc67.USE_DPORT="FALSE"; defparam desc67.USE_MULT="MULTIPLY"; defparam desc67.USE_SIMD="ONE48"; LUT3 un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o6(.I0(un1_x_12_0_0[5:5]),.I1(un1_x_13_0_0[6:6]),.I2(un1_x_14_0_0[5:5]),.O(un84_sop_0_0_0_11_6_0_axb_1)); defparam un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o6.INIT=8'h96; LUT3 un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o5(.I0(un1_x_12_0_0[5:5]),.I1(un1_x_13_0_0[6:6]),.I2(un1_x_14_0_0[5:5]),.O(un84_sop_0_0_0_11_6_0_axb_1_lut6_2_O5)); defparam un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o5.INIT=8'hE8; LUT3 un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o6(.I0(un1_x_7_0[3:3]),.I1(un1_x_8_0[5:5]),.I2(un1_x_9_0[6:6]),.O(un84_sop_0_0_0_6_6_0_axb_1)); defparam un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o6.INIT=8'h96; LUT3 un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o5(.I0(un1_x_7_0[3:3]),.I1(un1_x_8_0[5:5]),.I2(un1_x_9_0[6:6]),.O(un84_sop_0_0_0_6_6_0_axb_1_lut6_2_O5)); defparam un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o5.INIT=8'hE8; LUT3 un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o6(.I0(un84_sop_0_0_0_10_0[5:5]),.I1(x_4[0:0]),.I2(x_4[2:2]),.O(un84_sop_0_0_0_1_6_8_axb_2)); defparam un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o6.INIT=8'h96; LUT3 un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o5(.I0(un84_sop_0_0_0_10_0[5:5]),.I1(x_4[0:0]),.I2(x_4[2:2]),.O(un84_sop_0_0_0_1_6_8_axb_2_lut6_2_O5)); defparam un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o5.INIT=8'hE8; LUT3 un84_sop_1_6_0_axb_1_lut6_2_o6(.I0(un1_x_1[5:5]),.I1(un1_x_2[6:6]),.I2(un1_x_3[5:5]),.O(un84_sop_1_6_0_axb_1)); defparam un84_sop_1_6_0_axb_1_lut6_2_o6.INIT=8'h96; LUT3 un84_sop_1_6_0_axb_1_lut6_2_o5(.I0(un1_x_1[5:5]),.I1(un1_x_2[6:6]),.I2(un1_x_3[5:5]),.O(un84_sop_1_6_0_axb_1_lut6_2_O5)); defparam un84_sop_1_6_0_axb_1_lut6_2_o5.INIT=8'hE8; endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_wrcal.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Write calibration logic to align DQS to correct CK edge //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ **$Date: 2011/06/02 08:35:09 $ **$Author: **$Revision: **$Source: ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v4_0_ddr_phy_wrcal # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter CLK_PERIOD = 2500, parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps ) ( input clk, input rst, // Calibration status, control signals input wrcal_start, input wrcal_rd_wait, input wrcal_sanity_chk, input dqsfound_retry_done, input phy_rddata_en, output dqsfound_retry, output wrcal_read_req, output reg wrcal_act_req, output reg wrcal_done, output reg wrcal_pat_err, output reg wrcal_prech_req, output reg temp_wrcal_done, output reg wrcal_sanity_chk_done, input prech_done, // Captured data in resync clock domain input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Write level values of Phaser_Out coarse and fine // delay taps required to load Phaser_Out register input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt, input [6*DQS_WIDTH-1:0] wl_po_fine_cnt, input wrlvl_byte_done, output reg wrlvl_byte_redo, output reg early1_data, output reg early2_data, // DQ IDELAY output reg idelay_ld, output reg wrcal_pat_resume, // to phy_init for write output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt, output phy_if_reset, // Debug Port output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, output [99:0] dbg_phy_wrcal ); // Length of calibration sequence (in # of words) //localparam CAL_PAT_LEN = 8; // Read data shift register length localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2; // # of reads for reliable read capture localparam NUM_READS = 2; // # of cycles to wait after changing RDEN count value localparam RDEN_WAIT_CNT = 12; localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6; localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44; localparam CAL2_IDLE = 4'h0; localparam CAL2_READ_WAIT = 4'h1; localparam CAL2_NEXT_DQS = 4'h2; localparam CAL2_WRLVL_WAIT = 4'h3; localparam CAL2_IFIFO_RESET = 4'h4; localparam CAL2_DQ_IDEL_DEC = 4'h5; localparam CAL2_DONE = 4'h6; localparam CAL2_SANITY_WAIT = 4'h7; localparam CAL2_ERR = 4'h8; integer i,j,k,l,m,p,q,d; reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1]; reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w; reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1]; reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w; reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */; reg [4:0] not_empty_wait_cnt; reg [3:0] tap_inc_wait_cnt; reg cal2_done_r; reg cal2_done_r1; reg cal2_prech_req_r; reg [3:0] cal2_state_r; reg [3:0] cal2_state_r1; reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1]; reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1]; reg cal2_if_reset; reg wrcal_pat_resume_r; reg wrcal_pat_resume_r1; reg wrcal_pat_resume_r2; reg wrcal_pat_resume_r3; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; reg pat_data_match_r; reg pat1_data_match_r; reg pat1_data_match_r1; reg pat2_data_match_r; reg pat_data_match_valid_r; wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0]; wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0]; reg [DRAM_WIDTH-1:0] pat_match_fall0_r; reg pat_match_fall0_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall1_r; reg pat_match_fall1_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall2_r; reg pat_match_fall2_and_r; reg [DRAM_WIDTH-1:0] pat_match_fall3_r; reg pat_match_fall3_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise0_r; reg pat_match_rise0_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise1_r; reg pat_match_rise1_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise2_r; reg pat_match_rise2_and_r; reg [DRAM_WIDTH-1:0] pat_match_rise3_r; reg pat_match_rise3_and_r; reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; reg [DRAM_WIDTH-1:0] pat2_match_rise0_r; reg [DRAM_WIDTH-1:0] pat2_match_rise1_r; reg [DRAM_WIDTH-1:0] pat2_match_fall0_r; reg [DRAM_WIDTH-1:0] pat2_match_fall1_r; reg pat1_match_rise0_and_r; reg pat1_match_rise1_and_r; reg pat1_match_fall0_and_r; reg pat1_match_fall1_and_r; reg pat2_match_rise0_and_r; reg pat2_match_rise1_and_r; reg pat2_match_fall0_and_r; reg pat2_match_fall1_and_r; reg early1_data_match_r; reg early1_data_match_r1; reg [DRAM_WIDTH-1:0] early1_match_fall0_r; reg early1_match_fall0_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall1_r; reg early1_match_fall1_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall2_r; reg early1_match_fall2_and_r; reg [DRAM_WIDTH-1:0] early1_match_fall3_r; reg early1_match_fall3_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise0_r; reg early1_match_rise0_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise1_r; reg early1_match_rise1_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise2_r; reg early1_match_rise2_and_r; reg [DRAM_WIDTH-1:0] early1_match_rise3_r; reg early1_match_rise3_and_r; reg early2_data_match_r; reg [DRAM_WIDTH-1:0] early2_match_fall0_r; reg early2_match_fall0_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall1_r; reg early2_match_fall1_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall2_r; reg early2_match_fall2_and_r; reg [DRAM_WIDTH-1:0] early2_match_fall3_r; reg early2_match_fall3_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise0_r; reg early2_match_rise0_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise1_r; reg early2_match_rise1_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise2_r; reg early2_match_rise2_and_r; reg [DRAM_WIDTH-1:0] early2_match_rise3_r; reg early2_match_rise3_and_r; wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0]; wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0]; wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0]; wire [DQ_WIDTH-1:0] rd_data_rise0; wire [DQ_WIDTH-1:0] rd_data_fall0; wire [DQ_WIDTH-1:0] rd_data_rise1; wire [DQ_WIDTH-1:0] rd_data_fall1; wire [DQ_WIDTH-1:0] rd_data_rise2; wire [DQ_WIDTH-1:0] rd_data_fall2; wire [DQ_WIDTH-1:0] rd_data_rise3; wire [DQ_WIDTH-1:0] rd_data_fall3; reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; reg rd_active_posedge_r; reg rd_active_r; reg rd_active_r1; reg rd_active_r2; reg rd_active_r3; reg rd_active_r4; reg rd_active_r5; reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; reg wrlvl_byte_done_r; reg idelay_ld_done; reg pat1_detect; reg early1_detect; reg wrcal_sanity_chk_r; reg wrcal_sanity_chk_err; //*************************************************************************** // Debug //*************************************************************************** always @(*) begin for (d = 0; d < DQS_WIDTH; d = d + 1) begin po_fine_tap_cnt_w[(6*d)+:6] = po_fine_tap_cnt[d]; po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d]; end end assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w; assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w; generate if (nCK_PER_CLK == 4) begin: match_data_4 assign dbg_phy_wrcal[0] = pat_data_match_r; end else begin:match_data_2 assign dbg_phy_wrcal[0] = 1'b0; end endgenerate assign dbg_phy_wrcal[4:1] = cal2_state_r1[3:0]; assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err; assign dbg_phy_wrcal[6] = wrcal_start; assign dbg_phy_wrcal[7] = wrcal_done; assign dbg_phy_wrcal[8] = pat_data_match_valid_r; assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r; assign dbg_phy_wrcal[17+:5] = not_empty_wait_cnt; assign dbg_phy_wrcal[22] = early1_data; assign dbg_phy_wrcal[23] = early2_data; assign dbg_phy_wrcal[24+:8] = mux_rd_rise0_r; assign dbg_phy_wrcal[32+:8] = mux_rd_fall0_r; assign dbg_phy_wrcal[40+:8] = mux_rd_rise1_r; assign dbg_phy_wrcal[48+:8] = mux_rd_fall1_r; generate if (nCK_PER_CLK == 4) begin: mux_data_4 assign dbg_phy_wrcal[56+:8] = mux_rd_rise2_r; assign dbg_phy_wrcal[64+:8] = mux_rd_fall2_r; assign dbg_phy_wrcal[72+:8] = mux_rd_rise3_r; assign dbg_phy_wrcal[80+:8] = mux_rd_fall3_r; end else begin: mux_data_2 assign dbg_phy_wrcal[56+:8] = {8{1'b0}}; assign dbg_phy_wrcal[64+:8] = {8{1'b0}}; assign dbg_phy_wrcal[72+:8] = {8{1'b0}}; assign dbg_phy_wrcal[80+:8] = {8{1'b0}}; end endgenerate assign dbg_phy_wrcal[88] = early1_data_match_r; assign dbg_phy_wrcal[89] = early2_data_match_r; assign dbg_phy_wrcal[90] = wrcal_sanity_chk_r & pat_data_match_valid_r; assign dbg_phy_wrcal[91] = wrcal_sanity_chk_r; assign dbg_phy_wrcal[92] = wrcal_sanity_chk_done; assign dqsfound_retry = 1'b0; assign wrcal_read_req = 1'b0; assign phy_if_reset = cal2_if_reset; //************************************************************************** // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 // coarse delay //************************************************************************** always @(posedge clk) begin po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r; wrlvl_byte_done_r <= #TCQ wrlvl_byte_done; wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk; end //*************************************************************************** // Data mux to route appropriate byte to calibration logic - i.e. calibration // is done sequentially, one byte (or DQS group) at a time //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_rd_data_div4 assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2 assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; end endgenerate //************************************************************************** // Final Phaser OUT coarse and fine delay taps after write calibration // Sum of taps used during write leveling taps and write calibration //************************************************************************** always @(*) begin for (m = 0; m < DQS_WIDTH; m = m + 1) begin wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3]; wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6]; end end always @(posedge clk) begin if (rst) begin for (p = 0; p < DQS_WIDTH; p = p + 1) begin po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}}; po_fine_tap_cnt[p] <= #TCQ {6{1'b0}}; end end else if (cal2_done_r && ~cal2_done_r1) begin for (q = 0; q < DQS_WIDTH; q = q + 1) begin po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i]; po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i]; end end end always @(posedge clk) begin rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r; end // Register outputs for improved timing. // NOTE: Will need to change when per-bit DQ deskew is supported. // Currenly all bits in DQS group are checked in aggregate generate genvar mux_i; if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4 for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2 for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end end endgenerate //*************************************************************************** // generate request to PHY_INIT logic to issue precharged. Required when // calibration can take a long time (during which there are only constant // reads present on this bus). In this case need to issue perioidic // precharges to avoid tRAS violation. This signal must meet the following // requirements: (1) only transition from 0->1 when prech is first needed, // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted //*************************************************************************** always @(posedge clk) if (rst) wrcal_prech_req <= #TCQ 1'b0; else // Combine requests from all stages here wrcal_prech_req <= #TCQ cal2_prech_req_r; //*************************************************************************** // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES // NOTE: Written using discrete flops, but SRL can be used if the matching // logic does the comparison sequentially, rather than parallel //*************************************************************************** generate genvar rd_i; if (nCK_PER_CLK == 4) begin: gen_sr_div4 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; end end end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr always @(posedge clk) begin sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; end end end endgenerate //*************************************************************************** // Write calibration: // During write leveling DQS is aligned to the nearest CK edge that may not // be the correct CK edge. Write calibration is required to align the DQS to // the correct CK edge that clocks the write command. // The Phaser_Out coarse delay line is adjusted if required to add a memory // clock cycle of delay in order to read back the expected pattern. //*************************************************************************** always @(posedge clk) begin rd_active_r <= #TCQ phy_rddata_en; rd_active_r1 <= #TCQ rd_active_r; rd_active_r2 <= #TCQ rd_active_r1; rd_active_r3 <= #TCQ rd_active_r2; rd_active_r4 <= #TCQ rd_active_r3; rd_active_r5 <= #TCQ rd_active_r4; end //***************************************************************** // Expected data pattern when properly received by read capture // logic: // Based on pattern of ({rise,fall}) = // 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 // Each nibble will look like: // bit3: 1, 0, 1, 0, 0, 1, 1, 0 // bit2: 1, 0, 0, 1, 1, 0, 0, 1 // bit1: 1, 0, 1, 0, 0, 1, 0, 1 // bit0: 1, 0, 0, 1, 1, 0, 1, 0 // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN // and the actual training pattern contents change //***************************************************************** generate if (nCK_PER_CLK == 4) begin: gen_pat_div4 // FF00AA5555AA9966 assign pat_rise0[3] = 1'b1; assign pat_fall0[3] = 1'b0; assign pat_rise1[3] = 1'b1; assign pat_fall1[3] = 1'b0; assign pat_rise2[3] = 1'b0; assign pat_fall2[3] = 1'b1; assign pat_rise3[3] = 1'b1; assign pat_fall3[3] = 1'b0; assign pat_rise0[2] = 1'b1; assign pat_fall0[2] = 1'b0; assign pat_rise1[2] = 1'b0; assign pat_fall1[2] = 1'b1; assign pat_rise2[2] = 1'b1; assign pat_fall2[2] = 1'b0; assign pat_rise3[2] = 1'b0; assign pat_fall3[2] = 1'b1; assign pat_rise0[1] = 1'b1; assign pat_fall0[1] = 1'b0; assign pat_rise1[1] = 1'b1; assign pat_fall1[1] = 1'b0; assign pat_rise2[1] = 1'b0; assign pat_fall2[1] = 1'b1; assign pat_rise3[1] = 1'b0; assign pat_fall3[1] = 1'b1; assign pat_rise0[0] = 1'b1; assign pat_fall0[0] = 1'b0; assign pat_rise1[0] = 1'b0; assign pat_fall1[0] = 1'b1; assign pat_rise2[0] = 1'b1; assign pat_fall2[0] = 1'b0; assign pat_rise3[0] = 1'b1; assign pat_fall3[0] = 1'b0; // Pattern to distinguish between early write and incorrect read // BB11EE4444EEDD88 assign early_rise0[3] = 1'b1; assign early_fall0[3] = 1'b0; assign early_rise1[3] = 1'b1; assign early_fall1[3] = 1'b0; assign early_rise2[3] = 1'b0; assign early_fall2[3] = 1'b1; assign early_rise3[3] = 1'b1; assign early_fall3[3] = 1'b1; assign early_rise0[2] = 1'b0; assign early_fall0[2] = 1'b0; assign early_rise1[2] = 1'b1; assign early_fall1[2] = 1'b1; assign early_rise2[2] = 1'b1; assign early_fall2[2] = 1'b1; assign early_rise3[2] = 1'b1; assign early_fall3[2] = 1'b0; assign early_rise0[1] = 1'b1; assign early_fall0[1] = 1'b0; assign early_rise1[1] = 1'b1; assign early_fall1[1] = 1'b0; assign early_rise2[1] = 1'b0; assign early_fall2[1] = 1'b1; assign early_rise3[1] = 1'b0; assign early_fall3[1] = 1'b0; assign early_rise0[0] = 1'b1; assign early_fall0[0] = 1'b1; assign early_rise1[0] = 1'b0; assign early_fall1[0] = 1'b0; assign early_rise2[0] = 1'b0; assign early_fall2[0] = 1'b0; assign early_rise3[0] = 1'b1; assign early_fall3[0] = 1'b0; end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 // First cycle pattern FF00AA55 assign pat1_rise0[3] = 1'b1; assign pat1_fall0[3] = 1'b0; assign pat1_rise1[3] = 1'b1; assign pat1_fall1[3] = 1'b0; assign pat1_rise0[2] = 1'b1; assign pat1_fall0[2] = 1'b0; assign pat1_rise1[2] = 1'b0; assign pat1_fall1[2] = 1'b1; assign pat1_rise0[1] = 1'b1; assign pat1_fall0[1] = 1'b0; assign pat1_rise1[1] = 1'b1; assign pat1_fall1[1] = 1'b0; assign pat1_rise0[0] = 1'b1; assign pat1_fall0[0] = 1'b0; assign pat1_rise1[0] = 1'b0; assign pat1_fall1[0] = 1'b1; // Second cycle pattern 55AA9966 assign pat2_rise0[3] = 1'b0; assign pat2_fall0[3] = 1'b1; assign pat2_rise1[3] = 1'b1; assign pat2_fall1[3] = 1'b0; assign pat2_rise0[2] = 1'b1; assign pat2_fall0[2] = 1'b0; assign pat2_rise1[2] = 1'b0; assign pat2_fall1[2] = 1'b1; assign pat2_rise0[1] = 1'b0; assign pat2_fall0[1] = 1'b1; assign pat2_rise1[1] = 1'b0; assign pat2_fall1[1] = 1'b1; assign pat2_rise0[0] = 1'b1; assign pat2_fall0[0] = 1'b0; assign pat2_rise1[0] = 1'b1; assign pat2_fall1[0] = 1'b0; //Pattern to distinguish between early write and incorrect read // First cycle pattern AA5555AA assign early1_rise0[3] = 2'b1; assign early1_fall0[3] = 2'b0; assign early1_rise1[3] = 2'b0; assign early1_fall1[3] = 2'b1; assign early1_rise0[2] = 2'b0; assign early1_fall0[2] = 2'b1; assign early1_rise1[2] = 2'b1; assign early1_fall1[2] = 2'b0; assign early1_rise0[1] = 2'b1; assign early1_fall0[1] = 2'b0; assign early1_rise1[1] = 2'b0; assign early1_fall1[1] = 2'b1; assign early1_rise0[0] = 2'b0; assign early1_fall0[0] = 2'b1; assign early1_rise1[0] = 2'b1; assign early1_fall1[0] = 2'b0; // Second cycle pattern 9966BB11 assign early2_rise0[3] = 2'b1; assign early2_fall0[3] = 2'b0; assign early2_rise1[3] = 2'b1; assign early2_fall1[3] = 2'b0; assign early2_rise0[2] = 2'b0; assign early2_fall0[2] = 2'b1; assign early2_rise1[2] = 2'b0; assign early2_fall1[2] = 2'b0; assign early2_rise0[1] = 2'b0; assign early2_fall0[1] = 2'b1; assign early2_rise1[1] = 2'b1; assign early2_fall1[1] = 2'b0; assign early2_rise0[0] = 2'b1; assign early2_fall0[0] = 2'b0; assign early2_rise1[0] = 2'b1; assign early2_fall1[0] = 2'b1; end endgenerate // Each bit of each byte is compared to expected pattern. // This was done to prevent (and "drastically decrease") the chance that // invalid data clocked in when the DQ bus is tri-state (along with a // combination of the correct data) will resemble the expected data // pattern. A better fix for this is to change the training pattern and/or // make the pattern longer. generate genvar pt_i; if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4]) pat_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4]) pat_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4]) pat_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4]) pat_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4]) pat_match_rise2_r[pt_i] <= #TCQ 1'b1; else pat_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4]) pat_match_fall2_r[pt_i] <= #TCQ 1'b1; else pat_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4]) pat_match_rise3_r[pt_i] <= #TCQ 1'b1; else pat_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4]) pat_match_fall3_r[pt_i] <= #TCQ 1'b1; else pat_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4]) early1_match_rise0_r[pt_i] <= #TCQ 1'b1; else early1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4]) early1_match_fall0_r[pt_i] <= #TCQ 1'b1; else early1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4]) early1_match_rise1_r[pt_i] <= #TCQ 1'b1; else early1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4]) early1_match_fall1_r[pt_i] <= #TCQ 1'b1; else early1_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4]) early1_match_rise2_r[pt_i] <= #TCQ 1'b1; else early1_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4]) early1_match_fall2_r[pt_i] <= #TCQ 1'b1; else early1_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == early_rise0[pt_i%4]) early1_match_rise3_r[pt_i] <= #TCQ 1'b1; else early1_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == early_fall0[pt_i%4]) early1_match_fall3_r[pt_i] <= #TCQ 1'b1; else early1_match_fall3_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4]) early2_match_rise0_r[pt_i] <= #TCQ 1'b1; else early2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4]) early2_match_fall0_r[pt_i] <= #TCQ 1'b1; else early2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4]) early2_match_rise1_r[pt_i] <= #TCQ 1'b1; else early2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4]) early2_match_fall1_r[pt_i] <= #TCQ 1'b1; else early2_match_fall1_r[pt_i] <= #TCQ 1'b0; if (sr_rise2_r[pt_i] == early_rise0[pt_i%4]) early2_match_rise2_r[pt_i] <= #TCQ 1'b1; else early2_match_rise2_r[pt_i] <= #TCQ 1'b0; if (sr_fall2_r[pt_i] == early_fall0[pt_i%4]) early2_match_fall2_r[pt_i] <= #TCQ 1'b1; else early2_match_fall2_r[pt_i] <= #TCQ 1'b0; if (sr_rise3_r[pt_i] == early_rise1[pt_i%4]) early2_match_rise3_r[pt_i] <= #TCQ 1'b1; else early2_match_rise3_r[pt_i] <= #TCQ 1'b0; if (sr_fall3_r[pt_i] == early_fall1[pt_i%4]) early2_match_fall3_r[pt_i] <= #TCQ 1'b1; else early2_match_fall3_r[pt_i] <= #TCQ 1'b0; end end always @(posedge clk) begin pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r; pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r; pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r; pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r; pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r; pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r; pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r; pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r; pat_data_match_r <= #TCQ (pat_match_rise0_and_r && pat_match_fall0_and_r && pat_match_rise1_and_r && pat_match_fall1_and_r && pat_match_rise2_and_r && pat_match_fall2_and_r && pat_match_rise3_and_r && pat_match_fall3_and_r); pat_data_match_valid_r <= #TCQ rd_active_r3; end always @(posedge clk) begin early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r; early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r; early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r; early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r; early1_data_match_r <= #TCQ (early1_match_rise0_and_r && early1_match_fall0_and_r && early1_match_rise1_and_r && early1_match_fall1_and_r && early1_match_rise2_and_r && early1_match_fall2_and_r && early1_match_rise3_and_r && early1_match_fall3_and_r); end always @(posedge clk) begin early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r; early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r; early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r; early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r; early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r; early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r; early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r; early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r; early2_data_match_r <= #TCQ (early2_match_rise0_and_r && early2_match_fall0_and_r && early2_match_rise1_and_r && early2_match_fall1_and_r && early2_match_rise2_and_r && early2_match_fall2_and_r && early2_match_rise3_and_r && early2_match_fall3_and_r); end end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4]) pat2_match_rise0_r[pt_i] <= #TCQ 1'b1; else pat2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4]) pat2_match_fall0_r[pt_i] <= #TCQ 1'b1; else pat2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4]) pat2_match_rise1_r[pt_i] <= #TCQ 1'b1; else pat2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4]) pat2_match_fall1_r[pt_i] <= #TCQ 1'b1; else pat2_match_fall1_r[pt_i] <= #TCQ 1'b0; end always @(posedge clk) begin if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4]) early1_match_rise0_r[pt_i] <= #TCQ 1'b1; else early1_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4]) early1_match_fall0_r[pt_i] <= #TCQ 1'b1; else early1_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4]) early1_match_rise1_r[pt_i] <= #TCQ 1'b1; else early1_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4]) early1_match_fall1_r[pt_i] <= #TCQ 1'b1; else early1_match_fall1_r[pt_i] <= #TCQ 1'b0; end // early2 in this case does not mean 2 cycles early but // the second cycle of read data in 2:1 mode always @(posedge clk) begin if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4]) early2_match_rise0_r[pt_i] <= #TCQ 1'b1; else early2_match_rise0_r[pt_i] <= #TCQ 1'b0; if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4]) early2_match_fall0_r[pt_i] <= #TCQ 1'b1; else early2_match_fall0_r[pt_i] <= #TCQ 1'b0; if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4]) early2_match_rise1_r[pt_i] <= #TCQ 1'b1; else early2_match_rise1_r[pt_i] <= #TCQ 1'b0; if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4]) early2_match_fall1_r[pt_i] <= #TCQ 1'b1; else early2_match_fall1_r[pt_i] <= #TCQ 1'b0; end end always @(posedge clk) begin pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && pat1_match_fall0_and_r && pat1_match_rise1_and_r && pat1_match_fall1_and_r); pat1_data_match_r1 <= #TCQ pat1_data_match_r; pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3; pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3; pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3; pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3; pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r && pat2_match_fall0_and_r && pat2_match_rise1_and_r && pat2_match_fall1_and_r); // For 2:1 mode, read valid is asserted for 2 clock cycles - // here we generate a "match valid" pulse that is only 1 clock // cycle wide that is simulatenous when the match calculation // is complete pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5; end always @(posedge clk) begin early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; early1_data_match_r <= #TCQ (early1_match_rise0_and_r && early1_match_fall0_and_r && early1_match_rise1_and_r && early1_match_fall1_and_r); early1_data_match_r1 <= #TCQ early1_data_match_r; early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3; early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3; early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3; early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3; early2_data_match_r <= #TCQ (early2_match_rise0_and_r && early2_match_fall0_and_r && early2_match_rise1_and_r && early2_match_fall1_and_r); end end endgenerate // Need to delay it by 3 cycles in order to wait for Phaser_Out // coarse delay to take effect before issuing a write command always @(posedge clk) begin wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r; wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1; wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2; end always @(posedge clk) begin if (rst) tap_inc_wait_cnt <= #TCQ 'd0; else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) || (cal2_state_r == CAL2_IFIFO_RESET) || (cal2_state_r == CAL2_SANITY_WAIT)) tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1; else tap_inc_wait_cnt <= #TCQ 'd0; end always @(posedge clk) begin if (rst) not_empty_wait_cnt <= #TCQ 'd0; else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait) not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1; else not_empty_wait_cnt <= #TCQ 'd0; end always @(posedge clk) cal2_state_r1 <= #TCQ cal2_state_r; //***************************************************************** // Write Calibration state machine //***************************************************************** // when calibrating, check to see if the expected pattern is received. // Otherwise delay DQS to align to correct CK edge. // NOTES: // 1. An error condition can occur due to two reasons: // a. If the matching logic does not receive the expected data // pattern. However, the error may be "recoverable" because // the write calibration is still in progress. If an error is // found the write calibration logic delays DQS by an additional // clock cycle and restarts the pattern detection process. // By design, if the write path timing is incorrect, the correct // data pattern will never be detected. // b. Valid data not found even after incrementing Phaser_Out // coarse delay line. always @(posedge clk) begin if (rst) begin wrcal_dqs_cnt_r <= #TCQ 'b0; cal2_done_r <= #TCQ 1'b0; cal2_prech_req_r <= #TCQ 1'b0; cal2_state_r <= #TCQ CAL2_IDLE; wrcal_pat_err <= #TCQ 1'b0; wrcal_pat_resume_r <= #TCQ 1'b0; wrcal_act_req <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; temp_wrcal_done <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b0; early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b0; idelay_ld <= #TCQ 1'b0; idelay_ld_done <= #TCQ 1'b0; pat1_detect <= #TCQ 1'b0; early1_detect <= #TCQ 1'b0; wrcal_sanity_chk_done <= #TCQ 1'b0; wrcal_sanity_chk_err <= #TCQ 1'b0; end else begin cal2_prech_req_r <= #TCQ 1'b0; case (cal2_state_r) CAL2_IDLE: begin wrcal_pat_err <= #TCQ 1'b0; if (wrcal_start) begin cal2_if_reset <= #TCQ 1'b0; if (SIM_CAL_OPTION == "SKIP_CAL") // If skip write calibration, then proceed to end. cal2_state_r <= #TCQ CAL2_DONE; else cal2_state_r <= #TCQ CAL2_READ_WAIT; end end // General wait state to wait for read data to be output by the // IN_FIFO CAL2_READ_WAIT: begin wrcal_pat_resume_r <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; // Wait until read data is received, and pattern matching // calculation is complete. NOTE: Need to add a timeout here // in case for some reason data is never received (or rather // the PHASER_IN and IN_FIFO think they never receives data) if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin if (pat_data_match_r) // If found data match, then move on to next DQS group cal2_state_r <= #TCQ CAL2_NEXT_DQS; else begin if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_ERR; // If writes are one or two cycles early then redo // write leveling for the byte else if (early1_data_match_r) begin early1_data <= #TCQ 1'b1; early2_data <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; end else if (early2_data_match_r) begin early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b1; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; // Read late due to incorrect MPR idelay value // Decrement Idelay to '0'for the current byte end else if (~idelay_ld_done) begin cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; idelay_ld <= #TCQ 1'b1; end else cal2_state_r <= #TCQ CAL2_ERR; end end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin if ((pat1_data_match_r1 && pat2_data_match_r) || (pat1_detect && pat2_data_match_r)) // If found data match, then move on to next DQS group cal2_state_r <= #TCQ CAL2_NEXT_DQS; else if (pat1_data_match_r1 && ~pat2_data_match_r) begin cal2_state_r <= #TCQ CAL2_READ_WAIT; pat1_detect <= #TCQ 1'b1; end else begin // If writes are one or two cycles early then redo // write leveling for the byte if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_ERR; else if ((early1_data_match_r1 && early2_data_match_r) || (early1_detect && early2_data_match_r)) begin early1_data <= #TCQ 1'b1; early2_data <= #TCQ 1'b0; wrlvl_byte_redo <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; end else if (early1_data_match_r1 && ~early2_data_match_r) begin early1_detect <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_READ_WAIT; // Read late due to incorrect MPR idelay value // Decrement Idelay to '0'for the current byte end else if (~idelay_ld_done) begin cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; idelay_ld <= #TCQ 1'b1; end else cal2_state_r <= #TCQ CAL2_ERR; end end else if (not_empty_wait_cnt == 'd31) cal2_state_r <= #TCQ CAL2_ERR; end CAL2_WRLVL_WAIT: begin early1_detect <= #TCQ 1'b0; if (wrlvl_byte_done && ~wrlvl_byte_done_r) wrlvl_byte_redo <= #TCQ 1'b0; if (wrlvl_byte_done) begin if (rd_active_r1 && ~rd_active_r) begin cal2_state_r <= #TCQ CAL2_IFIFO_RESET; cal2_if_reset <= #TCQ 1'b1; early1_data <= #TCQ 1'b0; early2_data <= #TCQ 1'b0; end end end CAL2_DQ_IDEL_DEC: begin if (tap_inc_wait_cnt == 'd4) begin idelay_ld <= #TCQ 1'b0; cal2_state_r <= #TCQ CAL2_IFIFO_RESET; cal2_if_reset <= #TCQ 1'b1; idelay_ld_done <= #TCQ 1'b1; end end CAL2_IFIFO_RESET: begin if (tap_inc_wait_cnt == 'd15) begin cal2_if_reset <= #TCQ 1'b0; if (wrcal_sanity_chk_r) cal2_state_r <= #TCQ CAL2_DONE; else if (idelay_ld_done) begin wrcal_pat_resume_r <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_READ_WAIT; end else cal2_state_r <= #TCQ CAL2_IDLE; end end // Final processing for current DQS group. Move on to next group CAL2_NEXT_DQS: begin // At this point, we've just found the correct pattern for the // current DQS group. // Request bank/row precharge, and wait for its completion. Always // precharge after each DQS group to avoid tRAS(max) violation //verilint STARC-2.2.3.3 off if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin cal2_prech_req_r <= #TCQ 1'b0; wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; cal2_state_r <= #TCQ CAL2_SANITY_WAIT; end else cal2_prech_req_r <= #TCQ 1'b1; idelay_ld_done <= #TCQ 1'b0; pat1_detect <= #TCQ 1'b0; if (prech_done) if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) || (wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin // If either FAST_CAL is enabled and first DQS group is // finished, or if the last DQS group was just finished, // then end of write calibration if (wrcal_sanity_chk_r) begin cal2_if_reset <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_IFIFO_RESET; end else cal2_state_r <= #TCQ CAL2_DONE; end else begin // Continue to next DQS group wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; cal2_state_r <= #TCQ CAL2_READ_WAIT; end end //verilint STARC-2.2.3.3 on CAL2_SANITY_WAIT: begin if (tap_inc_wait_cnt == 'd15) begin cal2_state_r <= #TCQ CAL2_READ_WAIT; wrcal_pat_resume_r <= #TCQ 1'b1; end end // Finished with read enable calibration CAL2_DONE: begin if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin cal2_done_r <= #TCQ 1'b0; wrcal_dqs_cnt_r <= #TCQ 'd0; cal2_state_r <= #TCQ CAL2_IDLE; end else cal2_done_r <= #TCQ 1'b1; cal2_prech_req_r <= #TCQ 1'b0; cal2_if_reset <= #TCQ 1'b0; if (wrcal_sanity_chk_r) wrcal_sanity_chk_done <= #TCQ 1'b1; end // Assert error signal indicating that writes timing is incorrect CAL2_ERR: begin wrcal_pat_resume_r <= #TCQ 1'b0; if (wrcal_sanity_chk_r) wrcal_sanity_chk_err <= #TCQ 1'b1; else wrcal_pat_err <= #TCQ 1'b1; cal2_state_r <= #TCQ CAL2_ERR; end endcase end end // Delay assertion of wrcal_done for write calibration by a few cycles after // we've reached CAL2_DONE always @(posedge clk) if (rst) cal2_done_r1 <= #TCQ 1'b0; else cal2_done_r1 <= #TCQ cal2_done_r; always @(posedge clk) if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r)) wrcal_done <= #TCQ 1'b0; else if (cal2_done_r) wrcal_done <= #TCQ 1'b1; endmodule

// Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Wed Aug 31 18:10:14 2016" module carads( clk, rst_n_key, echo1, echo2, switch1, switch2, key1, uart_rx, to_sr, led7, led6, voice, sda, scl, MotorA, MotorB, ServoPPM, uart_tx, clkout, MotorPWM, led5, num, sel, testICC ); input wire clk; input wire rst_n_key; input wire echo1; input wire echo2; input wire switch1; input wire switch2; input wire key1; input wire uart_rx; output wire to_sr; output wire led7; output wire led6; output wire voice; inout wire sda; output wire scl; output wire MotorA; output wire MotorB; output wire ServoPPM; output wire uart_tx; output wire clkout; output wire MotorPWM; output wire led5; output wire [6:0] num; output wire [3:0] sel; output wire testICC; wire [6:0] num_ALTERA_SYNTHESIZED; wire [3:0] sel_ALTERA_SYNTHESIZED; wire [9:0] SYNTHESIZED_WIRE_1; wire [15:0] SYNTHESIZED_WIRE_2; wire [15:0] SYNTHESIZED_WIRE_3; wire [9:0] SYNTHESIZED_WIRE_4; wire [15:0] angle_control; wire [13:0] distance; reg rst_n_inside; wire rst_n; assign rst_n = rst_n_key && rst_n_inside; reg[15:0]autoResetCnt; always@(posedge clk) begin if(autoResetCnt<10000) begin rst_n_inside <= 1; autoResetCnt = autoResetCnt + 1; end else if(autoResetCnt>=10000 && autoResetCnt < 60000) begin autoResetCnt = autoResetCnt + 1; rst_n_inside <= 0; end else if(autoResetCnt >= 60000) rst_n_inside = 1; else autoResetCnt = 0; end transtop b2v_inst( .clk(clk), .rst_n(rst_n), .echo1(echo1), .echo2(echo2), .clkout(to_sr), .distance(distance), .speed(SYNTHESIZED_WIRE_1)); mainlogic b2v_inst1( .rst_n(rst_n), .switch1(switch1), .switch2(switch2), .clk(clk), .distance(distance), .speed(SYNTHESIZED_WIRE_1), .triangle(SYNTHESIZED_WIRE_2), .led1(led7), .led2(led6), .voice(voice), .out_num(SYNTHESIZED_WIRE_4), .speed_control(SYNTHESIZED_WIRE_3), .angle_control(angle_control)); top b2v_inst2( .clk(clk), .rst_n(rst_n), .key1(key1), .uart_rx(uart_rx), .sda(sda), .speed_control(SYNTHESIZED_WIRE_3), .scl(scl), .MotorPWM(MotorPWM), .MotorA(MotorA), .MotorB(MotorB), .ServoPPM(ServoPPM), .clkOut(clkout), .uart_tx(uart_tx), .newControlDataW(led5), .accXdata(SYNTHESIZED_WIRE_2), .angle_control(angle_control), .testICC(testICC) ); shumaguan b2v_inst9( .clk(clk), .rst_n(rst_n), .distance(distance), .num(num), .sel(sel) ); endmodule

module ADT7310P32S16 ( (* intersynth_port="Reset_n_i" *) input Reset_n_i, (* intersynth_port="Clk_i" *) input Clk_i, (* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *) input Enable_i, (* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *) output CpuIntr_o, (* intersynth_port="Outputs_o", intersynth_conntype="Bit" *) output ADT7310CS_n_o, (* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *) input[7:0] SPI_Data_i, (* intersynth_port="SPI_Write", intersynth_conntype="Bit" *) output SPI_Write_o, (* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *) output SPI_ReadNext_o, (* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *) output[7:0] SPI_Data_o, (* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *) input SPI_FIFOFull_i, (* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *) input SPI_FIFOEmpty_i, (* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *) input SPI_Transmission_i, (* intersynth_param="SPICounterPreset_i", intersynth_conntype="Word" *) input[15:0] SPICounterPreset_i, (* intersynth_param="Threshold_i", intersynth_conntype="Word" *) input[15:0] Threshold_i, (* intersynth_param="PeriodCounterPresetH_i", intersynth_conntype="Word" *) input[15:0] PeriodCounterPresetH_i, (* intersynth_param="PeriodCounterPresetL_i", intersynth_conntype="Word" *) input[15:0] PeriodCounterPresetL_i, (* intersynth_param="SensorValue_o", intersynth_conntype="Word" *) output[15:0] SensorValue_o, (* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *) output SPI_CPOL_o, (* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *) output SPI_CPHA_o, (* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *) output SPI_LSBFE_o ); /* constant value for dynamic signal */ assign SPI_CPOL_o = 1'b1; /* constant value for dynamic signal */ assign SPI_CPHA_o = 1'b1; /* constant value for dynamic signal */ assign SPI_LSBFE_o = 1'b0; (* keep *) wire SPIFSM_Start_s; (* keep *) wire SPIFSM_Done_s; (* keep *) wire [7:0] SPIFSM_Byte0_s; (* keep *) wire [7:0] SPIFSM_Byte1_s; SPIFSM #( .SPPRWidth (4), .SPRWidth (4), .DataWidth (8) ) SPIFSM_1 ( .Reset_n_i (Reset_n_i), .Clk_i (Clk_i), // FSM control .Start_i (SPIFSM_Start_s), .Done_o (SPIFSM_Done_s), .Byte0_o (SPIFSM_Byte0_s), .Byte1_o (SPIFSM_Byte1_s), // to/from SPI_Master .SPI_Transmission_i (SPI_Transmission_i), .SPI_Write_o (SPI_Write_o), .SPI_ReadNext_o (SPI_ReadNext_o), .SPI_Data_o (SPI_Data_o), .SPI_Data_i (SPI_Data_i), .SPI_FIFOFull_i (SPI_FIFOFull_i), .SPI_FIFOEmpty_i (SPI_FIFOEmpty_i), // to ADT7310 .ADT7310CS_n_o (ADT7310CS_n_o), // parameters .ParamCounterPreset_i(SPICounterPreset_i) ); SensorFSM #( .DataWidth (8) ) SensorFSM_1 ( .Reset_n_i (Reset_n_i), .Clk_i (Clk_i), .Enable_i (Enable_i), .CpuIntr_o (CpuIntr_o), .SensorValue_o (SensorValue_o), .MeasureFSM_Start_o (SPIFSM_Start_s), .MeasureFSM_Done_i (SPIFSM_Done_s), .MeasureFSM_Byte0_i (SPIFSM_Byte0_s), .MeasureFSM_Byte1_i (SPIFSM_Byte1_s), // parameters .ParamThreshold_i (Threshold_i), .ParamCounterPreset_i({PeriodCounterPresetH_i, PeriodCounterPresetL_i}) ); endmodule

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:58:55 05/17/2016 // Design Name: // Module Name: escritor_lector_rtc // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module escritor_lector_rtc( input clk,reset, input [7:0]port_id,in_dato, input write_strobe,read_strobe, output reg_a_d,reg_cs,reg_rd,reg_wr, output reg[7:0]out_dato, output flag_done, inout [7:0]dato ); reg en_funcion; reg [7:0]addr_RAM,dato_escribir; wire [7:0]dato_leido; reg [7:0]next_out_dato; reg [7:0]reg_addr_RAM, reg_dato_escribir,reg_dato_leido; reg reg_escribir_leer,escribir_leer; wire direccion_dato; /// I/O Datos Driver_bus_bidireccional instance_driver_bus_bidireccional ( .in_flag_escritura(~reg_wr), .in_flag_lectura(~reg_rd), .in_direccion_dato(direccion_dato), .in_dato(dato_escribir), .out_reg_dato(dato_leido), .addr_RAM(addr_RAM), .dato(dato) ); //Generador de señales de control signal_control_rtc_generator instance_signal_control_rtc_generator ( .clk(clk), .reset(reset), .in_escribir_leer(escribir_leer), .en_funcion(en_funcion), .reg_a_d(reg_a_d), .reg_cs(reg_cs), .reg_wr(reg_wr), .reg_rd(reg_rd), .out_direccion_dato(direccion_dato), .flag_done(flag_done) ); // logica secuencial always@(negedge clk , posedge reset) begin if (reset)begin addr_RAM <= 8'h0; dato_escribir <= 8'h0; escribir_leer <= 1'b0; out_dato <= 8'b0; end else begin addr_RAM <= reg_addr_RAM; dato_escribir <= reg_dato_escribir; escribir_leer <= reg_escribir_leer; out_dato <= next_out_dato; end end // logica combinacional para port_id always@* begin if (~reg_rd) next_out_dato = dato_leido; next_out_dato = out_dato; if ( write_strobe == 1'b1 || read_strobe == 1'b1) begin // inicio de secuencia de lectura_escritura rtc if(port_id == 8'h0E) en_funcion = 1'b1; else en_funcion = 1'b0; case (port_id) 8'h00: begin //actualiza direccion reg_addr_RAM = in_dato; reg_dato_escribir = dato_escribir; reg_escribir_leer = escribir_leer; end 8'h01: begin // actualiza dato reg_dato_escribir = in_dato; reg_addr_RAM = addr_RAM; reg_escribir_leer = escribir_leer; end 8'h0E: begin // inicia secuancia de rtc reg_addr_RAM = addr_RAM; reg_dato_escribir = dato_escribir; reg_escribir_leer = in_dato[0]; end default: begin reg_addr_RAM = addr_RAM; reg_dato_escribir = dato_escribir; reg_escribir_leer = escribir_leer; end endcase end else begin reg_addr_RAM = addr_RAM; reg_dato_escribir = dato_escribir; reg_escribir_leer = escribir_leer; en_funcion = 1'b0; end end endmodule

// megafunction wizard: %ROM: 1-PORT%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: Test.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 9.0 Build 132 02/25/2009 SJ Full Version // ************************************************************ //Copyright (C) 1991-2009 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. module Test ( address, clock, q); input [0:0] address; input clock; output [15:0] q; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" // Retrieval info: PRIVATE: AclrByte NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" // Retrieval info: PRIVATE: JTAG_ID STRING "test" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "test.mif" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: SingleClock NUMERIC "1" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" // Retrieval info: PRIVATE: WidthAddr NUMERIC "1" // Retrieval info: PRIVATE: WidthData NUMERIC "16" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: INIT_FILE STRING "test.mif" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=test" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1" // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "1" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: address 0 0 1 0 INPUT NODEFVAL address[0..0] // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] // Retrieval info: CONNECT: @address_a 0 0 1 0 address 0 0 1 0 // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL Test.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL Test.inc TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL Test.cmp TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL Test.bsf TRUE FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL Test_inst.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL Test_bb.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL Test_waveforms.html TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL Test_wave*.jpg FALSE // Retrieval info: LIB_FILE: altera_mf

/* Copyright (c) 2014 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ // Language: Verilog 2001 `timescale 1 ns / 1 ps module test_axis_async_frame_fifo_64; // Inputs reg input_clk = 0; reg input_rst = 0; reg output_clk = 0; reg output_rst = 0; reg [7:0] current_test = 0; reg [63:0] input_axis_tdata = 0; reg [7:0] input_axis_tkeep = 0; reg input_axis_tvalid = 0; reg input_axis_tlast = 0; reg input_axis_tuser = 0; reg output_axis_tready = 0; // Outputs wire input_axis_tready; wire [63:0] output_axis_tdata; wire [7:0] output_axis_tkeep; wire output_axis_tvalid; wire output_axis_tlast; initial begin // myhdl integration $from_myhdl(input_clk, input_rst, output_clk, output_rst, current_test, input_axis_tdata, input_axis_tkeep, input_axis_tvalid, input_axis_tlast, input_axis_tuser, output_axis_tready); $to_myhdl(input_axis_tready, output_axis_tdata, output_axis_tkeep, output_axis_tvalid, output_axis_tlast); // dump file $dumpfile("test_axis_async_frame_fifo_64.lxt"); $dumpvars(0, test_axis_async_frame_fifo_64); end axis_async_frame_fifo_64 #( .ADDR_WIDTH(6), .DATA_WIDTH(64), .DROP_WHEN_FULL(0) ) UUT ( // AXI input .input_clk(input_clk), .input_rst(input_rst), .input_axis_tdata(input_axis_tdata), .input_axis_tkeep(input_axis_tkeep), .input_axis_tvalid(input_axis_tvalid), .input_axis_tready(input_axis_tready), .input_axis_tlast(input_axis_tlast), .input_axis_tuser(input_axis_tuser), // AXI output .output_clk(output_clk), .output_rst(output_rst), .output_axis_tdata(output_axis_tdata), .output_axis_tkeep(output_axis_tkeep), .output_axis_tvalid(output_axis_tvalid), .output_axis_tready(output_axis_tready), .output_axis_tlast(output_axis_tlast) ); endmodule

///////////////////////////////////////////////////////////// // Created by: Synopsys DC Ultra(TM) in wire load mode // Version : L-2016.03-SP3 // Date : Sun Nov 13 08:44:16 2016 ///////////////////////////////////////////////////////////// module CORDIC_Arch2v1_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic, ack_cordic, operation, data_in, shift_region_flag, ready_cordic, data_output, beg_add_subt, ack_add_subt, add_subt_dataA, add_subt_dataB, result_add_subt, op_add_subt, ready_add_subt ); input [63:0] data_in; input [1:0] shift_region_flag; output [63:0] data_output; output [63:0] add_subt_dataA; output [63:0] add_subt_dataB; input [63:0] result_add_subt; input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt; output ready_cordic, beg_add_subt, ack_add_subt, op_add_subt; wire d_ff1_operation_out, sel_mux_1_reg, d_ff3_sign_out, sel_mux_3_reg, data_output2_63_, cordic_FSM_state_next_1_, n564, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366; wire [1:0] d_ff1_shift_region_flag_out; wire [1:0] cont_var_out; wire [3:0] cont_iter_out; wire [63:0] d_ff1_Z; wire [63:0] d_ff_Xn; wire [63:0] d_ff_Yn; wire [63:0] d_ff_Zn; wire [63:0] d_ff2_X; wire [63:0] d_ff2_Y; wire [63:0] d_ff2_Z; wire [63:0] d_ff3_sh_x_out; wire [63:0] d_ff3_sh_y_out; wire [56:0] d_ff3_LUT_out; wire [1:0] sel_mux_2_reg; wire [62:0] sign_inv_out; wire [3:0] cordic_FSM_state_reg; DFFRXLTS cont_iter_count_reg_3_ ( .D(n1338), .CK(clk), .RN(n2342), .Q( cont_iter_out[3]), .QN(n1478) ); DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n1333), .CK(clk), .RN(n2341), .Q(d_ff1_Z[0]) ); DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n1332), .CK(clk), .RN(n2350), .Q(d_ff1_Z[1]) ); DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n1331), .CK(clk), .RN(n2345), .Q(d_ff1_Z[2]) ); DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n1330), .CK(clk), .RN(n1488), .Q(d_ff1_Z[3]) ); DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n1329), .CK(clk), .RN(n2346), .Q(d_ff1_Z[4]) ); DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n1328), .CK(clk), .RN(n2340), .Q(d_ff1_Z[5]) ); DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n1327), .CK(clk), .RN(n2349), .Q(d_ff1_Z[6]) ); DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n1326), .CK(clk), .RN(n2346), .Q(d_ff1_Z[7]) ); DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n1325), .CK(clk), .RN(n2344), .Q(d_ff1_Z[8]) ); DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n1324), .CK(clk), .RN(n2344), .Q(d_ff1_Z[9]) ); DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n1323), .CK(clk), .RN(n2340), .Q(d_ff1_Z[10]) ); DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n1322), .CK(clk), .RN(n1488), .Q(d_ff1_Z[11]) ); DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n1321), .CK(clk), .RN(n2348), .Q(d_ff1_Z[12]) ); DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n1320), .CK(clk), .RN(n2348), .Q(d_ff1_Z[13]) ); DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n1319), .CK(clk), .RN(n2348), .Q(d_ff1_Z[14]) ); DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n1318), .CK(clk), .RN(n2348), .Q(d_ff1_Z[15]) ); DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n1317), .CK(clk), .RN(n2348), .Q(d_ff1_Z[16]) ); DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n1316), .CK(clk), .RN(n2355), .Q(d_ff1_Z[17]) ); DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n1315), .CK(clk), .RN(n2353), .Q(d_ff1_Z[18]) ); DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n1314), .CK(clk), .RN(n2352), .Q(d_ff1_Z[19]) ); DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n1313), .CK(clk), .RN(n2351), .Q(d_ff1_Z[20]) ); DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n1312), .CK(clk), .RN(n2357), .Q(d_ff1_Z[21]) ); DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n1311), .CK(clk), .RN(n2340), .Q(d_ff1_Z[22]) ); DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n1310), .CK(clk), .RN(n2346), .Q(d_ff1_Z[23]) ); DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n1309), .CK(clk), .RN(n1489), .Q(d_ff1_Z[24]) ); DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n1308), .CK(clk), .RN(n2345), .Q(d_ff1_Z[25]) ); DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n1307), .CK(clk), .RN(n2345), .Q(d_ff1_Z[26]) ); DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n1306), .CK(clk), .RN(n2346), .Q(d_ff1_Z[27]) ); DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n1305), .CK(clk), .RN(n2349), .Q(d_ff1_Z[28]) ); DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n1304), .CK(clk), .RN(n2345), .Q(d_ff1_Z[29]) ); DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n1303), .CK(clk), .RN(n1489), .Q(d_ff1_Z[30]) ); DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n1302), .CK(clk), .RN(n1488), .Q(d_ff1_Z[31]) ); DFFRXLTS reg_Z0_Q_reg_32_ ( .D(n1301), .CK(clk), .RN(n2346), .Q(d_ff1_Z[32]) ); DFFRXLTS reg_Z0_Q_reg_33_ ( .D(n1300), .CK(clk), .RN(n2344), .Q(d_ff1_Z[33]) ); DFFRXLTS reg_Z0_Q_reg_34_ ( .D(n1299), .CK(clk), .RN(n2346), .Q(d_ff1_Z[34]) ); DFFRXLTS reg_Z0_Q_reg_35_ ( .D(n1298), .CK(clk), .RN(n2346), .Q(d_ff1_Z[35]) ); DFFRXLTS reg_Z0_Q_reg_36_ ( .D(n1297), .CK(clk), .RN(n2345), .Q(d_ff1_Z[36]) ); DFFRXLTS reg_Z0_Q_reg_37_ ( .D(n1296), .CK(clk), .RN(n2344), .Q(d_ff1_Z[37]) ); DFFRXLTS reg_Z0_Q_reg_38_ ( .D(n1295), .CK(clk), .RN(n1488), .Q(d_ff1_Z[38]) ); DFFRXLTS reg_Z0_Q_reg_39_ ( .D(n1294), .CK(clk), .RN(n2340), .Q(d_ff1_Z[39]) ); DFFRXLTS reg_Z0_Q_reg_40_ ( .D(n1293), .CK(clk), .RN(n2347), .Q(d_ff1_Z[40]) ); DFFRXLTS reg_Z0_Q_reg_41_ ( .D(n1292), .CK(clk), .RN(n2349), .Q(d_ff1_Z[41]) ); DFFRXLTS reg_Z0_Q_reg_42_ ( .D(n1291), .CK(clk), .RN(n2345), .Q(d_ff1_Z[42]) ); DFFRXLTS reg_Z0_Q_reg_43_ ( .D(n1290), .CK(clk), .RN(n2344), .Q(d_ff1_Z[43]) ); DFFRXLTS reg_Z0_Q_reg_44_ ( .D(n1289), .CK(clk), .RN(n2340), .Q(d_ff1_Z[44]) ); DFFRXLTS reg_Z0_Q_reg_45_ ( .D(n1288), .CK(clk), .RN(n2349), .Q(d_ff1_Z[45]) ); DFFRXLTS reg_Z0_Q_reg_46_ ( .D(n1287), .CK(clk), .RN(n2347), .Q(d_ff1_Z[46]) ); DFFRXLTS reg_Z0_Q_reg_47_ ( .D(n1286), .CK(clk), .RN(n1489), .Q(d_ff1_Z[47]) ); DFFRXLTS reg_Z0_Q_reg_48_ ( .D(n1285), .CK(clk), .RN(n2349), .Q(d_ff1_Z[48]) ); DFFRXLTS reg_Z0_Q_reg_49_ ( .D(n1284), .CK(clk), .RN(n2344), .Q(d_ff1_Z[49]) ); DFFRXLTS reg_Z0_Q_reg_50_ ( .D(n1283), .CK(clk), .RN(n2344), .Q(d_ff1_Z[50]) ); DFFRXLTS reg_Z0_Q_reg_51_ ( .D(n1282), .CK(clk), .RN(n2347), .Q(d_ff1_Z[51]) ); DFFRXLTS reg_Z0_Q_reg_52_ ( .D(n1281), .CK(clk), .RN(n1488), .Q(d_ff1_Z[52]) ); DFFRXLTS reg_Z0_Q_reg_53_ ( .D(n1280), .CK(clk), .RN(n2349), .Q(d_ff1_Z[53]) ); DFFRXLTS reg_Z0_Q_reg_54_ ( .D(n1279), .CK(clk), .RN(n2347), .Q(d_ff1_Z[54]) ); DFFRXLTS reg_Z0_Q_reg_55_ ( .D(n1278), .CK(clk), .RN(n2340), .Q(d_ff1_Z[55]) ); DFFRXLTS reg_Z0_Q_reg_56_ ( .D(n1277), .CK(clk), .RN(n2347), .Q(d_ff1_Z[56]) ); DFFRXLTS reg_Z0_Q_reg_57_ ( .D(n1276), .CK(clk), .RN(n1489), .Q(d_ff1_Z[57]) ); DFFRXLTS reg_Z0_Q_reg_58_ ( .D(n1275), .CK(clk), .RN(n2340), .Q(d_ff1_Z[58]) ); DFFRXLTS reg_Z0_Q_reg_59_ ( .D(n1274), .CK(clk), .RN(n2345), .Q(d_ff1_Z[59]) ); DFFRXLTS reg_Z0_Q_reg_60_ ( .D(n1273), .CK(clk), .RN(n2344), .Q(d_ff1_Z[60]) ); DFFRXLTS reg_Z0_Q_reg_61_ ( .D(n1272), .CK(clk), .RN(n2347), .Q(d_ff1_Z[61]) ); DFFRXLTS reg_Z0_Q_reg_62_ ( .D(n1271), .CK(clk), .RN(n1509), .Q(d_ff1_Z[62]) ); DFFRXLTS reg_Z0_Q_reg_63_ ( .D(n1270), .CK(clk), .RN(n1508), .Q(d_ff1_Z[63]) ); DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n1265), .CK(clk), .RN(n2343), .Q(d_ff_Zn[0]) ); DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n1264), .CK(clk), .RN(n2341), .Q(d_ff_Zn[1]) ); DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n1263), .CK(clk), .RN(n2342), .Q(d_ff_Zn[2]) ); DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n1262), .CK(clk), .RN(n2339), .Q(d_ff_Zn[3]) ); DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n1261), .CK(clk), .RN(n2339), .Q(d_ff_Zn[4]) ); DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n1260), .CK(clk), .RN(n1509), .Q(d_ff_Zn[5]) ); DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n1259), .CK(clk), .RN(n1508), .Q(d_ff_Zn[6]) ); DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n1258), .CK(clk), .RN(n2341), .Q(d_ff_Zn[7]) ); DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n1257), .CK(clk), .RN(n2350), .Q(d_ff_Zn[8]) ); DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n1256), .CK(clk), .RN(n2343), .Q(d_ff_Zn[9]) ); DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n1255), .CK(clk), .RN(n2342), .Q( d_ff_Zn[10]) ); DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n1254), .CK(clk), .RN(n2339), .Q( d_ff_Zn[11]) ); DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n1253), .CK(clk), .RN(n1509), .Q( d_ff_Zn[12]) ); DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n1252), .CK(clk), .RN(n1508), .Q( d_ff_Zn[13]) ); DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n1251), .CK(clk), .RN(n2350), .Q( d_ff_Zn[14]) ); DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n1250), .CK(clk), .RN(n1509), .Q( d_ff_Zn[15]) ); DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n2357), .Q( d_ff_Zn[16]) ); DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n1248), .CK(clk), .RN(n1508), .Q( d_ff_Zn[17]) ); DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n1247), .CK(clk), .RN(n2343), .Q( d_ff_Zn[18]) ); DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n1246), .CK(clk), .RN(n2341), .Q( d_ff_Zn[19]) ); DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n1245), .CK(clk), .RN(n2339), .Q( d_ff_Zn[20]) ); DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n1244), .CK(clk), .RN(n2350), .Q( d_ff_Zn[21]) ); DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n1243), .CK(clk), .RN(n2343), .Q( d_ff_Zn[22]) ); DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n1242), .CK(clk), .RN(n2342), .Q( d_ff_Zn[23]) ); DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n1241), .CK(clk), .RN(n2345), .Q( d_ff_Zn[24]) ); DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n1240), .CK(clk), .RN(n1489), .Q( d_ff_Zn[25]) ); DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n1239), .CK(clk), .RN(n2349), .Q( d_ff_Zn[26]) ); DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n1238), .CK(clk), .RN(n2349), .Q( d_ff_Zn[27]) ); DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n1237), .CK(clk), .RN(n2340), .Q( d_ff_Zn[28]) ); DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n1236), .CK(clk), .RN(n2345), .Q( d_ff_Zn[29]) ); DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n1235), .CK(clk), .RN(n1488), .Q( d_ff_Zn[30]) ); DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n1234), .CK(clk), .RN(n2346), .Q( d_ff_Zn[31]) ); DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(n1233), .CK(clk), .RN(n2347), .Q( d_ff_Zn[32]) ); DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(n1232), .CK(clk), .RN(n2347), .Q( d_ff_Zn[33]) ); DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(n1231), .CK(clk), .RN(n1509), .Q( d_ff_Zn[34]) ); DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(n1230), .CK(clk), .RN(n2335), .Q( d_ff_Zn[35]) ); DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(n1229), .CK(clk), .RN(n1494), .Q( d_ff_Zn[36]) ); DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(n1228), .CK(clk), .RN(n1506), .Q( d_ff_Zn[37]) ); DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(n1227), .CK(clk), .RN(n1501), .Q( d_ff_Zn[38]) ); DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(n1226), .CK(clk), .RN(n1493), .Q( d_ff_Zn[39]) ); DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(n1225), .CK(clk), .RN(n2354), .Q( d_ff_Zn[40]) ); DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(n1224), .CK(clk), .RN(n2340), .Q( d_ff_Zn[41]) ); DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(n1223), .CK(clk), .RN(n2345), .Q( d_ff_Zn[42]) ); DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(n1222), .CK(clk), .RN(n2366), .Q( d_ff_Zn[43]) ); DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(n1221), .CK(clk), .RN(n2341), .Q( d_ff_Zn[44]) ); DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(n1220), .CK(clk), .RN(n2350), .Q( d_ff_Zn[45]) ); DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(n1219), .CK(clk), .RN(n2343), .Q( d_ff_Zn[46]) ); DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(n1218), .CK(clk), .RN(n2342), .Q( d_ff_Zn[47]) ); DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(n1217), .CK(clk), .RN(n2339), .Q( d_ff_Zn[48]) ); DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(n1216), .CK(clk), .RN(n1509), .Q( d_ff_Zn[49]) ); DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(n1215), .CK(clk), .RN(n1508), .Q( d_ff_Zn[50]) ); DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(n1214), .CK(clk), .RN(n2341), .Q( d_ff_Zn[51]) ); DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(n1213), .CK(clk), .RN(n2350), .Q( d_ff_Zn[52]) ); DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(n1212), .CK(clk), .RN(n2343), .Q( d_ff_Zn[53]) ); DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(n1211), .CK(clk), .RN(n2337), .Q( d_ff_Zn[54]) ); DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(n1210), .CK(clk), .RN(n2336), .Q( d_ff_Zn[55]) ); DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(n1209), .CK(clk), .RN(n2356), .Q( d_ff_Zn[56]) ); DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(n1208), .CK(clk), .RN(n2338), .Q( d_ff_Zn[57]) ); DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(n1207), .CK(clk), .RN(n2337), .Q( d_ff_Zn[58]) ); DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(n1206), .CK(clk), .RN(n2336), .Q( d_ff_Zn[59]) ); DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(n1205), .CK(clk), .RN(n2356), .Q( d_ff_Zn[60]) ); DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(n1204), .CK(clk), .RN(n2338), .Q( d_ff_Zn[61]) ); DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(n1203), .CK(clk), .RN(n2337), .Q( d_ff_Zn[62]) ); DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(n1202), .CK(clk), .RN(n2336), .Q( d_ff_Zn[63]) ); DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n1201), .CK(clk), .RN(n2356), .Q(d_ff_Yn[0]), .QN(n2239) ); DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n1200), .CK(clk), .RN(n2338), .Q(d_ff_Yn[1]), .QN(n2240) ); DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n1199), .CK(clk), .RN(n2337), .Q(d_ff_Yn[2]), .QN(n2241) ); DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n1198), .CK(clk), .RN(n2336), .Q(d_ff_Yn[3]), .QN(n2242) ); DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n1197), .CK(clk), .RN(n2356), .Q(d_ff_Yn[4]), .QN(n2243) ); DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n1196), .CK(clk), .RN(n2338), .Q(d_ff_Yn[5]), .QN(n2244) ); DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n1195), .CK(clk), .RN(n2337), .Q(d_ff_Yn[6]), .QN(n2245) ); DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n1194), .CK(clk), .RN(n2336), .Q(d_ff_Yn[7]), .QN(n2246) ); DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n1193), .CK(clk), .RN(n2356), .Q(d_ff_Yn[8]), .QN(n2247) ); DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n1192), .CK(clk), .RN(n2338), .Q(d_ff_Yn[9]), .QN(n2248) ); DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n1191), .CK(clk), .RN(n2337), .Q( d_ff_Yn[10]), .QN(n2249) ); DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n1190), .CK(clk), .RN(n2336), .Q( d_ff_Yn[11]), .QN(n2250) ); DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n1189), .CK(clk), .RN(n2356), .Q( d_ff_Yn[12]), .QN(n2251) ); DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n1188), .CK(clk), .RN(n2338), .Q( d_ff_Yn[13]), .QN(n2252) ); DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(n1187), .CK(clk), .RN(n2337), .Q( d_ff_Yn[14]), .QN(n2253) ); DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n1186), .CK(clk), .RN(n2336), .Q( d_ff_Yn[15]), .QN(n2254) ); DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n1185), .CK(clk), .RN(n2356), .Q( d_ff_Yn[16]), .QN(n2255) ); DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n1184), .CK(clk), .RN(n2338), .Q( d_ff_Yn[17]), .QN(n2256) ); DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n1183), .CK(clk), .RN(n2337), .Q( d_ff_Yn[18]), .QN(n2257) ); DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n1182), .CK(clk), .RN(n2336), .Q( d_ff_Yn[19]), .QN(n2258) ); DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n1181), .CK(clk), .RN(n2317), .Q( d_ff_Yn[20]), .QN(n2259) ); DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n1180), .CK(clk), .RN(n2314), .Q( d_ff_Yn[21]), .QN(n2260) ); DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n1179), .CK(clk), .RN(n2333), .Q( d_ff_Yn[22]), .QN(n2261) ); DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(n1178), .CK(clk), .RN(n2334), .Q( d_ff_Yn[23]), .QN(n2262) ); DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(n1177), .CK(clk), .RN(n2335), .Q( d_ff_Yn[24]), .QN(n2263) ); DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n1176), .CK(clk), .RN(n2315), .Q( d_ff_Yn[25]), .QN(n2264) ); DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n1175), .CK(clk), .RN(n2316), .Q( d_ff_Yn[26]), .QN(n2265) ); DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n1174), .CK(clk), .RN(n1513), .Q( d_ff_Yn[27]), .QN(n2266) ); DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(n1173), .CK(clk), .RN(n1514), .Q( d_ff_Yn[28]), .QN(n2267) ); DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(n1172), .CK(clk), .RN(n2317), .Q( d_ff_Yn[29]), .QN(n2268) ); DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(n1171), .CK(clk), .RN(n2314), .Q( d_ff_Yn[30]), .QN(n2269) ); DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(n1170), .CK(clk), .RN(n2333), .Q( d_ff_Yn[31]), .QN(n2270) ); DFFRXLTS d_ff4_Yn_Q_reg_32_ ( .D(n1169), .CK(clk), .RN(n2334), .Q( d_ff_Yn[32]), .QN(n2271) ); DFFRXLTS d_ff4_Yn_Q_reg_33_ ( .D(n1168), .CK(clk), .RN(n2335), .Q( d_ff_Yn[33]), .QN(n2272) ); DFFRXLTS d_ff4_Yn_Q_reg_34_ ( .D(n1167), .CK(clk), .RN(n2315), .Q( d_ff_Yn[34]), .QN(n2273) ); DFFRXLTS d_ff4_Yn_Q_reg_35_ ( .D(n1166), .CK(clk), .RN(n2316), .Q( d_ff_Yn[35]), .QN(n2274) ); DFFRXLTS d_ff4_Yn_Q_reg_36_ ( .D(n1165), .CK(clk), .RN(n1513), .Q( d_ff_Yn[36]), .QN(n2275) ); DFFRXLTS d_ff4_Yn_Q_reg_37_ ( .D(n1164), .CK(clk), .RN(n1514), .Q( d_ff_Yn[37]), .QN(n2276) ); DFFRXLTS d_ff4_Yn_Q_reg_38_ ( .D(n1163), .CK(clk), .RN(n2317), .Q( d_ff_Yn[38]), .QN(n2277) ); DFFRXLTS d_ff4_Yn_Q_reg_39_ ( .D(n1162), .CK(clk), .RN(n2314), .Q( d_ff_Yn[39]), .QN(n2278) ); DFFRXLTS d_ff4_Yn_Q_reg_40_ ( .D(n1161), .CK(clk), .RN(n2333), .Q( d_ff_Yn[40]), .QN(n2279) ); DFFRXLTS d_ff4_Yn_Q_reg_41_ ( .D(n1160), .CK(clk), .RN(n2334), .Q( d_ff_Yn[41]), .QN(n2280) ); DFFRXLTS d_ff4_Yn_Q_reg_42_ ( .D(n1159), .CK(clk), .RN(n2335), .Q( d_ff_Yn[42]), .QN(n2281) ); DFFRXLTS d_ff4_Yn_Q_reg_43_ ( .D(n1158), .CK(clk), .RN(n2315), .Q( d_ff_Yn[43]), .QN(n2282) ); DFFRXLTS d_ff4_Yn_Q_reg_44_ ( .D(n1157), .CK(clk), .RN(n2316), .Q( d_ff_Yn[44]), .QN(n2283) ); DFFRXLTS d_ff4_Yn_Q_reg_45_ ( .D(n1156), .CK(clk), .RN(n1513), .Q( d_ff_Yn[45]), .QN(n2284) ); DFFRXLTS d_ff4_Yn_Q_reg_46_ ( .D(n1155), .CK(clk), .RN(n1514), .Q( d_ff_Yn[46]), .QN(n2285) ); DFFRXLTS d_ff4_Yn_Q_reg_47_ ( .D(n1154), .CK(clk), .RN(n2317), .Q( d_ff_Yn[47]), .QN(n2286) ); DFFRXLTS d_ff4_Yn_Q_reg_48_ ( .D(n1153), .CK(clk), .RN(n2314), .Q( d_ff_Yn[48]), .QN(n2287) ); DFFRXLTS d_ff4_Yn_Q_reg_49_ ( .D(n1152), .CK(clk), .RN(n2333), .Q( d_ff_Yn[49]), .QN(n2288) ); DFFRXLTS d_ff4_Yn_Q_reg_50_ ( .D(n1151), .CK(clk), .RN(n2304), .Q( d_ff_Yn[50]), .QN(n2289) ); DFFRXLTS d_ff4_Yn_Q_reg_51_ ( .D(n1150), .CK(clk), .RN(n2342), .Q( d_ff_Yn[51]), .QN(n2290) ); DFFRXLTS d_ff4_Yn_Q_reg_52_ ( .D(n1149), .CK(clk), .RN(n1507), .Q( d_ff_Yn[52]) ); DFFRXLTS d_ff4_Yn_Q_reg_53_ ( .D(n1148), .CK(clk), .RN(n2356), .Q( d_ff_Yn[53]) ); DFFRXLTS d_ff4_Yn_Q_reg_54_ ( .D(n1147), .CK(clk), .RN(n2336), .Q( d_ff_Yn[54]), .QN(n2291) ); DFFRXLTS d_ff4_Yn_Q_reg_55_ ( .D(n1146), .CK(clk), .RN(n2357), .Q( d_ff_Yn[55]) ); DFFRXLTS d_ff4_Yn_Q_reg_56_ ( .D(n1145), .CK(clk), .RN(n2351), .Q( d_ff_Yn[56]) ); DFFRXLTS d_ff4_Yn_Q_reg_57_ ( .D(n1144), .CK(clk), .RN(n2352), .Q( d_ff_Yn[57]) ); DFFRXLTS d_ff4_Yn_Q_reg_58_ ( .D(n1143), .CK(clk), .RN(n2353), .Q( d_ff_Yn[58]) ); DFFRXLTS d_ff4_Yn_Q_reg_59_ ( .D(n1142), .CK(clk), .RN(n2348), .Q( d_ff_Yn[59]) ); DFFRXLTS d_ff4_Yn_Q_reg_60_ ( .D(n1141), .CK(clk), .RN(n2357), .Q( d_ff_Yn[60]) ); DFFRXLTS d_ff4_Yn_Q_reg_61_ ( .D(n1140), .CK(clk), .RN(n2351), .Q( d_ff_Yn[61]) ); DFFRXLTS d_ff4_Yn_Q_reg_62_ ( .D(n1139), .CK(clk), .RN(n2352), .Q( d_ff_Yn[62]) ); DFFRXLTS d_ff4_Yn_Q_reg_63_ ( .D(n1138), .CK(clk), .RN(n2353), .Q( d_ff_Yn[63]), .QN(n2292) ); DFFRXLTS d_ff5_Q_reg_0_ ( .D(n1073), .CK(clk), .RN(n2358), .Q( sign_inv_out[0]) ); DFFRXLTS d_ff5_Q_reg_1_ ( .D(n1071), .CK(clk), .RN(n2358), .Q( sign_inv_out[1]) ); DFFRXLTS d_ff5_Q_reg_2_ ( .D(n1069), .CK(clk), .RN(n2358), .Q( sign_inv_out[2]) ); DFFRXLTS d_ff5_Q_reg_3_ ( .D(n1067), .CK(clk), .RN(n2358), .Q( sign_inv_out[3]) ); DFFRXLTS d_ff5_Q_reg_4_ ( .D(n1065), .CK(clk), .RN(n2362), .Q( sign_inv_out[4]) ); DFFRXLTS d_ff5_Q_reg_5_ ( .D(n1063), .CK(clk), .RN(n2363), .Q( sign_inv_out[5]) ); DFFRXLTS d_ff5_Q_reg_6_ ( .D(n1061), .CK(clk), .RN(n2359), .Q( sign_inv_out[6]) ); DFFRXLTS d_ff5_Q_reg_10_ ( .D(n1053), .CK(clk), .RN(n2365), .Q( sign_inv_out[10]) ); DFFRXLTS d_ff5_Q_reg_11_ ( .D(n1051), .CK(clk), .RN(n2361), .Q( sign_inv_out[11]) ); DFFRXLTS d_ff5_Q_reg_12_ ( .D(n1049), .CK(clk), .RN(n2360), .Q( sign_inv_out[12]) ); DFFRXLTS d_ff5_Q_reg_13_ ( .D(n1047), .CK(clk), .RN(n2359), .Q( sign_inv_out[13]) ); DFFRXLTS d_ff5_Q_reg_14_ ( .D(n1045), .CK(clk), .RN(n2362), .Q( sign_inv_out[14]) ); DFFRXLTS d_ff5_Q_reg_15_ ( .D(n1043), .CK(clk), .RN(n2363), .Q( sign_inv_out[15]) ); DFFRXLTS d_ff5_Q_reg_16_ ( .D(n1041), .CK(clk), .RN(n2359), .Q( sign_inv_out[16]) ); DFFRXLTS d_ff5_Q_reg_17_ ( .D(n1039), .CK(clk), .RN(n2359), .Q( sign_inv_out[17]) ); DFFRXLTS d_ff5_Q_reg_18_ ( .D(n1037), .CK(clk), .RN(n2362), .Q( sign_inv_out[18]) ); DFFRXLTS d_ff5_Q_reg_19_ ( .D(n1035), .CK(clk), .RN(n2363), .Q( sign_inv_out[19]) ); DFFRXLTS d_ff5_Q_reg_20_ ( .D(n1033), .CK(clk), .RN(n2360), .Q( sign_inv_out[20]) ); DFFRXLTS d_ff5_Q_reg_21_ ( .D(n1031), .CK(clk), .RN(n2361), .Q( sign_inv_out[21]) ); DFFRXLTS d_ff5_Q_reg_22_ ( .D(n1029), .CK(clk), .RN(n1507), .Q( sign_inv_out[22]) ); DFFRXLTS d_ff5_Q_reg_23_ ( .D(n1027), .CK(clk), .RN(n1506), .Q( sign_inv_out[23]) ); DFFRXLTS d_ff5_Q_reg_24_ ( .D(n1025), .CK(clk), .RN(n2308), .Q( sign_inv_out[24]) ); DFFRXLTS d_ff5_Q_reg_25_ ( .D(n1023), .CK(clk), .RN(n2360), .Q( sign_inv_out[25]) ); DFFRXLTS d_ff5_Q_reg_26_ ( .D(n1021), .CK(clk), .RN(n2361), .Q( sign_inv_out[26]) ); DFFRXLTS d_ff5_Q_reg_27_ ( .D(n1019), .CK(clk), .RN(n1507), .Q( sign_inv_out[27]) ); DFFRXLTS d_ff5_Q_reg_28_ ( .D(n1017), .CK(clk), .RN(n2337), .Q( sign_inv_out[28]) ); DFFRXLTS d_ff5_Q_reg_29_ ( .D(n1015), .CK(clk), .RN(n2356), .Q( sign_inv_out[29]) ); DFFRXLTS d_ff5_Q_reg_30_ ( .D(n1013), .CK(clk), .RN(n1488), .Q( sign_inv_out[30]) ); DFFRXLTS d_ff5_Q_reg_31_ ( .D(n1011), .CK(clk), .RN(n2348), .Q( sign_inv_out[31]) ); DFFRXLTS d_ff5_Q_reg_32_ ( .D(n1009), .CK(clk), .RN(n1489), .Q( sign_inv_out[32]) ); DFFRXLTS d_ff5_Q_reg_33_ ( .D(n1007), .CK(clk), .RN(n1510), .Q( sign_inv_out[33]) ); DFFRXLTS d_ff5_Q_reg_34_ ( .D(n1005), .CK(clk), .RN(n1510), .Q( sign_inv_out[34]) ); DFFRXLTS d_ff5_Q_reg_35_ ( .D(n1003), .CK(clk), .RN(n2353), .Q( sign_inv_out[35]) ); DFFRXLTS d_ff5_Q_reg_36_ ( .D(n1001), .CK(clk), .RN(n2351), .Q( sign_inv_out[36]) ); DFFRXLTS d_ff5_Q_reg_40_ ( .D(n993), .CK(clk), .RN(n1502), .Q( sign_inv_out[40]) ); DFFRXLTS d_ff5_Q_reg_41_ ( .D(n991), .CK(clk), .RN(n1502), .Q( sign_inv_out[41]) ); DFFRXLTS d_ff5_Q_reg_42_ ( .D(n989), .CK(clk), .RN(n2329), .Q( sign_inv_out[42]) ); DFFRXLTS d_ff5_Q_reg_43_ ( .D(n987), .CK(clk), .RN(n1502), .Q( sign_inv_out[43]) ); DFFRXLTS d_ff5_Q_reg_44_ ( .D(n985), .CK(clk), .RN(n2351), .Q( sign_inv_out[44]) ); DFFRXLTS d_ff5_Q_reg_45_ ( .D(n983), .CK(clk), .RN(n1510), .Q( sign_inv_out[45]) ); DFFRXLTS d_ff5_Q_reg_46_ ( .D(n981), .CK(clk), .RN(n2353), .Q( sign_inv_out[46]) ); DFFRXLTS d_ff5_Q_reg_47_ ( .D(n979), .CK(clk), .RN(n1507), .Q( sign_inv_out[47]) ); DFFRXLTS d_ff5_Q_reg_48_ ( .D(n977), .CK(clk), .RN(n1510), .Q( sign_inv_out[48]) ); DFFRXLTS d_ff5_Q_reg_49_ ( .D(n975), .CK(clk), .RN(n2334), .Q( sign_inv_out[49]) ); DFFRXLTS d_ff5_Q_reg_50_ ( .D(n973), .CK(clk), .RN(n1510), .Q( sign_inv_out[50]) ); DFFRXLTS d_ff5_Q_reg_51_ ( .D(n971), .CK(clk), .RN(n2355), .Q( sign_inv_out[51]) ); DFFRXLTS d_ff5_Q_reg_52_ ( .D(n969), .CK(clk), .RN(n2353), .Q( sign_inv_out[52]) ); DFFRXLTS d_ff5_Q_reg_53_ ( .D(n967), .CK(clk), .RN(n2352), .Q( sign_inv_out[53]) ); DFFRXLTS d_ff5_Q_reg_54_ ( .D(n965), .CK(clk), .RN(n2366), .Q( sign_inv_out[54]) ); DFFRXLTS d_ff5_Q_reg_55_ ( .D(n963), .CK(clk), .RN(n1502), .Q( sign_inv_out[55]) ); DFFRXLTS d_ff5_Q_reg_56_ ( .D(n961), .CK(clk), .RN(n1508), .Q( sign_inv_out[56]) ); DFFRXLTS d_ff5_Q_reg_57_ ( .D(n959), .CK(clk), .RN(n2355), .Q( sign_inv_out[57]) ); DFFRXLTS d_ff5_Q_reg_58_ ( .D(n957), .CK(clk), .RN(n2353), .Q( sign_inv_out[58]) ); DFFRXLTS d_ff5_Q_reg_59_ ( .D(n955), .CK(clk), .RN(n2351), .Q( sign_inv_out[59]) ); DFFRXLTS d_ff5_Q_reg_60_ ( .D(n953), .CK(clk), .RN(n2312), .Q( sign_inv_out[60]) ); DFFRXLTS d_ff5_Q_reg_61_ ( .D(n951), .CK(clk), .RN(n2313), .Q( sign_inv_out[61]) ); DFFRXLTS d_ff5_Q_reg_62_ ( .D(n949), .CK(clk), .RN(n2296), .Q( sign_inv_out[62]) ); DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n945), .CK(clk), .RN(n2294), .Q( d_ff3_LUT_out[0]) ); DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n944), .CK(clk), .RN(n2312), .Q( d_ff3_LUT_out[1]) ); DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n943), .CK(clk), .RN(n2296), .Q( d_ff3_LUT_out[2]) ); DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n941), .CK(clk), .RN(n2327), .Q( d_ff3_LUT_out[4]) ); DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n940), .CK(clk), .RN(n2309), .Q( d_ff3_LUT_out[5]) ); DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n939), .CK(clk), .RN(n2329), .Q( d_ff3_LUT_out[6]) ); DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n938), .CK(clk), .RN(n2328), .Q( d_ff3_LUT_out[7]) ); DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n937), .CK(clk), .RN(n2310), .QN(n1517) ); DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n936), .CK(clk), .RN(n2311), .Q( d_ff3_LUT_out[9]) ); DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n935), .CK(clk), .RN(n2309), .Q( d_ff3_LUT_out[10]) ); DFFRXLTS reg_LUT_Q_reg_11_ ( .D(n934), .CK(clk), .RN(n1511), .Q( d_ff3_LUT_out[11]) ); DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n933), .CK(clk), .RN(n2330), .Q( d_ff3_LUT_out[12]) ); DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n932), .CK(clk), .RN(n2327), .Q( d_ff3_LUT_out[13]) ); DFFRXLTS reg_LUT_Q_reg_14_ ( .D(n931), .CK(clk), .RN(n2329), .Q( d_ff3_LUT_out[14]) ); DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n929), .CK(clk), .RN(n2311), .Q( d_ff3_LUT_out[16]) ); DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n928), .CK(clk), .RN(n2328), .Q( d_ff3_LUT_out[17]) ); DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n927), .CK(clk), .RN(n2309), .Q( d_ff3_LUT_out[18]) ); DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n926), .CK(clk), .RN(n2328), .QN(n1515) ); DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n925), .CK(clk), .RN(n2310), .Q( d_ff3_LUT_out[20]) ); DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n924), .CK(clk), .RN(n2311), .Q( d_ff3_LUT_out[21]) ); DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n923), .CK(clk), .RN(n2309), .Q( d_ff3_LUT_out[22]) ); DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n922), .CK(clk), .RN(n1511), .Q( d_ff3_LUT_out[23]) ); DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n921), .CK(clk), .RN(n2330), .Q( d_ff3_LUT_out[24]) ); DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n920), .CK(clk), .RN(n2327), .Q( d_ff3_LUT_out[25]) ); DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n919), .CK(clk), .RN(n2329), .Q( d_ff3_LUT_out[26]) ); DFFRXLTS reg_LUT_Q_reg_27_ ( .D(n918), .CK(clk), .RN(n1511), .Q( d_ff3_LUT_out[27]) ); DFFRXLTS reg_LUT_Q_reg_28_ ( .D(n917), .CK(clk), .RN(n2330), .Q( d_ff3_LUT_out[28]) ); DFFRXLTS reg_LUT_Q_reg_29_ ( .D(n916), .CK(clk), .RN(n2327), .Q( d_ff3_LUT_out[29]) ); DFFRXLTS reg_LUT_Q_reg_30_ ( .D(n915), .CK(clk), .RN(n2329), .Q( d_ff3_LUT_out[30]) ); DFFRXLTS reg_LUT_Q_reg_31_ ( .D(n914), .CK(clk), .RN(n1511), .Q( d_ff3_LUT_out[31]) ); DFFRXLTS reg_LUT_Q_reg_32_ ( .D(n913), .CK(clk), .RN(n2330), .Q( d_ff3_LUT_out[32]) ); DFFRXLTS reg_LUT_Q_reg_33_ ( .D(n912), .CK(clk), .RN(n2361), .Q( d_ff3_LUT_out[33]) ); DFFRXLTS reg_LUT_Q_reg_34_ ( .D(n911), .CK(clk), .RN(n2364), .Q( d_ff3_LUT_out[34]) ); DFFRXLTS reg_LUT_Q_reg_35_ ( .D(n910), .CK(clk), .RN(n2360), .Q( d_ff3_LUT_out[35]) ); DFFRXLTS reg_LUT_Q_reg_36_ ( .D(n909), .CK(clk), .RN(n2365), .Q( d_ff3_LUT_out[36]) ); DFFRXLTS reg_LUT_Q_reg_37_ ( .D(n908), .CK(clk), .RN(n2308), .Q( d_ff3_LUT_out[37]) ); DFFRXLTS reg_LUT_Q_reg_38_ ( .D(n907), .CK(clk), .RN(n1507), .Q( d_ff3_LUT_out[38]) ); DFFRXLTS reg_LUT_Q_reg_39_ ( .D(n906), .CK(clk), .RN(n1506), .Q( d_ff3_LUT_out[39]) ); DFFRXLTS reg_LUT_Q_reg_40_ ( .D(n905), .CK(clk), .RN(n2361), .Q( d_ff3_LUT_out[40]) ); DFFRXLTS reg_LUT_Q_reg_41_ ( .D(n904), .CK(clk), .RN(n2364), .QN(n1516) ); DFFRXLTS reg_LUT_Q_reg_42_ ( .D(n903), .CK(clk), .RN(n2360), .Q( d_ff3_LUT_out[42]) ); DFFRXLTS reg_LUT_Q_reg_43_ ( .D(n902), .CK(clk), .RN(n2322), .Q( d_ff3_LUT_out[43]) ); DFFRXLTS reg_LUT_Q_reg_44_ ( .D(n901), .CK(clk), .RN(n2306), .Q( d_ff3_LUT_out[44]) ); DFFRXLTS reg_LUT_Q_reg_45_ ( .D(n900), .CK(clk), .RN(n2303), .Q( d_ff3_LUT_out[45]) ); DFFRXLTS reg_LUT_Q_reg_46_ ( .D(n899), .CK(clk), .RN(n2307), .Q( d_ff3_LUT_out[46]) ); DFFRXLTS reg_LUT_Q_reg_47_ ( .D(n898), .CK(clk), .RN(n2322), .Q( d_ff3_LUT_out[47]) ); DFFRXLTS reg_LUT_Q_reg_49_ ( .D(n896), .CK(clk), .RN(n2306), .Q( d_ff3_LUT_out[49]) ); DFFRXLTS reg_LUT_Q_reg_50_ ( .D(n895), .CK(clk), .RN(n2303), .Q( d_ff3_LUT_out[50]) ); DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n894), .CK(clk), .RN(n2307), .Q( d_ff3_LUT_out[52]) ); DFFRXLTS reg_LUT_Q_reg_53_ ( .D(n893), .CK(clk), .RN(n2307), .Q( d_ff3_LUT_out[53]), .QN(n2293) ); DFFRXLTS reg_LUT_Q_reg_54_ ( .D(n892), .CK(clk), .RN(n2322), .Q( d_ff3_LUT_out[54]) ); DFFRXLTS reg_LUT_Q_reg_55_ ( .D(n891), .CK(clk), .RN(n2306), .Q( d_ff3_LUT_out[55]) ); DFFRXLTS reg_LUT_Q_reg_56_ ( .D(n890), .CK(clk), .RN(n2303), .Q( d_ff3_LUT_out[56]) ); DFFRXLTS reg_shift_y_Q_reg_52_ ( .D(n709), .CK(clk), .RN(n2307), .Q( d_ff3_sh_y_out[52]) ); DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(n708), .CK(clk), .RN(n2322), .Q( d_ff3_sh_y_out[53]) ); DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(n707), .CK(clk), .RN(n2306), .Q( d_ff3_sh_y_out[54]) ); DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(n706), .CK(clk), .RN(n2303), .Q( d_ff3_sh_y_out[55]) ); DFFRXLTS reg_shift_y_Q_reg_56_ ( .D(n705), .CK(clk), .RN(n2307), .Q( d_ff3_sh_y_out[56]) ); DFFRXLTS reg_shift_y_Q_reg_57_ ( .D(n704), .CK(clk), .RN(n2322), .Q( d_ff3_sh_y_out[57]) ); DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(n703), .CK(clk), .RN(n2306), .Q( d_ff3_sh_y_out[58]) ); DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(n702), .CK(clk), .RN(n2305), .Q( d_ff3_sh_y_out[59]) ); DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(n701), .CK(clk), .RN(n2305), .Q( d_ff3_sh_y_out[60]) ); DFFRXLTS reg_shift_y_Q_reg_61_ ( .D(n700), .CK(clk), .RN(n2305), .Q( d_ff3_sh_y_out[61]) ); DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(n699), .CK(clk), .RN(n2305), .Q( d_ff3_sh_y_out[62]) ); DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(n581), .CK(clk), .RN(n2305), .Q( d_ff3_sh_x_out[52]) ); DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(n580), .CK(clk), .RN(n2305), .Q( d_ff3_sh_x_out[53]) ); DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(n579), .CK(clk), .RN(n2305), .Q( d_ff3_sh_x_out[54]) ); DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(n578), .CK(clk), .RN(n2305), .Q( d_ff3_sh_x_out[55]) ); DFFRXLTS reg_shift_x_Q_reg_56_ ( .D(n577), .CK(clk), .RN(n2305), .Q( d_ff3_sh_x_out[56]) ); DFFRXLTS reg_shift_x_Q_reg_57_ ( .D(n576), .CK(clk), .RN(n2305), .Q( d_ff3_sh_x_out[57]) ); DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(n575), .CK(clk), .RN(n2332), .Q( d_ff3_sh_x_out[58]) ); DFFRXLTS reg_shift_x_Q_reg_59_ ( .D(n574), .CK(clk), .RN(n2331), .Q( d_ff3_sh_x_out[59]) ); DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(n573), .CK(clk), .RN(n2304), .Q( d_ff3_sh_x_out[60]) ); DFFRXLTS reg_shift_x_Q_reg_61_ ( .D(n572), .CK(clk), .RN(n2332), .Q( d_ff3_sh_x_out[61]) ); DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(n571), .CK(clk), .RN(n2331), .Q( d_ff3_sh_x_out[62]) ); DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n889), .CK(clk), .RN(n2304), .Q( d_ff2_Z[0]) ); DFFRXLTS reg_val_muxZ_2stage_Q_reg_47_ ( .D(n842), .CK(clk), .RN(n2319), .Q( d_ff2_Z[47]) ); DFFRXLTS reg_val_muxZ_2stage_Q_reg_48_ ( .D(n841), .CK(clk), .RN(n2318), .Q( d_ff2_Z[48]) ); DFFRXLTS reg_val_muxZ_2stage_Q_reg_49_ ( .D(n840), .CK(clk), .RN(n2299), .Q( d_ff2_Z[49]) ); DFFRXLTS reg_val_muxZ_2stage_Q_reg_50_ ( .D(n839), .CK(clk), .RN(n2298), .Q( d_ff2_Z[50]) ); DFFRXLTS reg_val_muxZ_2stage_Q_reg_51_ ( .D(n838), .CK(clk), .RN(n2319), .Q( d_ff2_Z[51]) ); DFFRXLTS reg_val_muxZ_2stage_Q_reg_52_ ( .D(n837), .CK(clk), .RN(n2318), .Q( d_ff2_Z[52]) ); DFFRXLTS reg_val_muxZ_2stage_Q_reg_53_ ( .D(n836), .CK(clk), .RN(n2299), .Q( d_ff2_Z[53]) ); DFFRXLTS reg_val_muxZ_2stage_Q_reg_54_ ( .D(n835), .CK(clk), .RN(n2298), .Q( d_ff2_Z[54]) ); DFFRXLTS reg_val_muxZ_2stage_Q_reg_55_ ( .D(n834), .CK(clk), .RN(n2319), .Q( d_ff2_Z[55]) ); DFFRXLTS reg_val_muxZ_2stage_Q_reg_56_ ( .D(n833), .CK(clk), .RN(n2318), .Q( d_ff2_Z[56]) ); DFFRXLTS reg_val_muxZ_2stage_Q_reg_58_ ( .D(n831), .CK(clk), .RN(n2298), .Q( d_ff2_Z[58]) ); DFFRXLTS reg_val_muxZ_2stage_Q_reg_60_ ( .D(n829), .CK(clk), .RN(n2318), .Q( d_ff2_Z[60]) ); DFFRX1TS reg_sign_Q_reg_0_ ( .D(n825), .CK(clk), .RN(n2297), .Q( d_ff3_sign_out) ); DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n823), .CK(clk), .RN(n2297), .Q( d_ff3_sh_y_out[0]) ); DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n821), .CK(clk), .RN(n2297), .Q( d_ff3_sh_y_out[1]) ); DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n819), .CK(clk), .RN(n2297), .Q( d_ff3_sh_y_out[2]) ); DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n817), .CK(clk), .RN(n2297), .Q( d_ff3_sh_y_out[3]) ); DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n815), .CK(clk), .RN(n2313), .Q( d_ff3_sh_y_out[4]) ); DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n813), .CK(clk), .RN(n2294), .Q( d_ff3_sh_y_out[5]) ); DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n811), .CK(clk), .RN(n2296), .Q( d_ff3_sh_y_out[6]) ); DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n809), .CK(clk), .RN(n2313), .Q( d_ff3_sh_y_out[7]) ); DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n807), .CK(clk), .RN(n2294), .Q( d_ff3_sh_y_out[8]) ); DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n805), .CK(clk), .RN(n2312), .Q( d_ff3_sh_y_out[9]) ); DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n803), .CK(clk), .RN(n2313), .Q( d_ff3_sh_y_out[10]) ); DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n801), .CK(clk), .RN(n2294), .Q( d_ff3_sh_y_out[11]) ); DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n799), .CK(clk), .RN(n2296), .Q( d_ff3_sh_y_out[12]) ); DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n797), .CK(clk), .RN(n2312), .Q( d_ff3_sh_y_out[13]) ); DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n795), .CK(clk), .RN(n2294), .Q( d_ff3_sh_y_out[14]) ); DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n793), .CK(clk), .RN(n2312), .Q( d_ff3_sh_y_out[15]) ); DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n791), .CK(clk), .RN(n2296), .Q( d_ff3_sh_y_out[16]) ); DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n789), .CK(clk), .RN(n2313), .Q( d_ff3_sh_y_out[17]) ); DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n787), .CK(clk), .RN(n2294), .Q( d_ff3_sh_y_out[18]) ); DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n785), .CK(clk), .RN(n2332), .Q( d_ff3_sh_y_out[19]) ); DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n783), .CK(clk), .RN(n2304), .Q( d_ff3_sh_y_out[20]) ); DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n781), .CK(clk), .RN(n2331), .Q( d_ff3_sh_y_out[21]) ); DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n779), .CK(clk), .RN(n2304), .Q( d_ff3_sh_y_out[22]) ); DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n777), .CK(clk), .RN(n2331), .Q( d_ff3_sh_y_out[23]) ); DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n775), .CK(clk), .RN(n2332), .Q( d_ff3_sh_y_out[24]) ); DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n773), .CK(clk), .RN(n2304), .Q( d_ff3_sh_y_out[25]) ); DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n771), .CK(clk), .RN(n2331), .Q( d_ff3_sh_y_out[26]) ); DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n769), .CK(clk), .RN(n2332), .Q( d_ff3_sh_y_out[27]) ); DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n767), .CK(clk), .RN(n2330), .Q( d_ff3_sh_y_out[28]) ); DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n765), .CK(clk), .RN(n2327), .Q( d_ff3_sh_y_out[29]) ); DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n763), .CK(clk), .RN(n2329), .Q( d_ff3_sh_y_out[30]) ); DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n761), .CK(clk), .RN(n2330), .Q( d_ff3_sh_y_out[31]) ); DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(n759), .CK(clk), .RN(n2327), .Q( d_ff3_sh_y_out[32]) ); DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(n757), .CK(clk), .RN(n1511), .Q( d_ff3_sh_y_out[33]) ); DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(n755), .CK(clk), .RN(n2310), .Q( d_ff3_sh_y_out[34]) ); DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(n753), .CK(clk), .RN(n2311), .Q( d_ff3_sh_y_out[35]) ); DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(n751), .CK(clk), .RN(n1511), .Q( d_ff3_sh_y_out[36]) ); DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(n749), .CK(clk), .RN(n2328), .Q( d_ff3_sh_y_out[37]) ); DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(n747), .CK(clk), .RN(n1511), .Q( d_ff3_sh_y_out[38]) ); DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(n745), .CK(clk), .RN(n2328), .Q( d_ff3_sh_y_out[39]) ); DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(n743), .CK(clk), .RN(n2310), .Q( d_ff3_sh_y_out[40]) ); DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(n741), .CK(clk), .RN(n2311), .Q( d_ff3_sh_y_out[41]) ); DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(n739), .CK(clk), .RN(n2330), .Q( d_ff3_sh_y_out[42]) ); DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(n737), .CK(clk), .RN(n2329), .Q( d_ff3_sh_y_out[43]) ); DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(n735), .CK(clk), .RN(n2328), .Q( d_ff3_sh_y_out[44]) ); DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(n733), .CK(clk), .RN(n2310), .Q( d_ff3_sh_y_out[45]) ); DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(n731), .CK(clk), .RN(n2311), .Q( d_ff3_sh_y_out[46]) ); DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(n729), .CK(clk), .RN(n2309), .Q( d_ff3_sh_y_out[47]) ); DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(n727), .CK(clk), .RN(n1494), .Q( d_ff3_sh_y_out[48]) ); DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(n725), .CK(clk), .RN(n2302), .Q( d_ff3_sh_y_out[49]) ); DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(n723), .CK(clk), .RN(n2320), .Q( d_ff3_sh_y_out[50]) ); DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(n721), .CK(clk), .RN(n1494), .Q( d_ff3_sh_y_out[51]) ); DFFRXLTS reg_val_muxY_2stage_Q_reg_56_ ( .D(n716), .CK(clk), .RN(n2320), .Q( d_ff2_Y[56]) ); DFFRXLTS reg_val_muxY_2stage_Q_reg_58_ ( .D(n714), .CK(clk), .RN(n2320), .Q( d_ff2_Y[58]) ); DFFRXLTS reg_val_muxY_2stage_Q_reg_60_ ( .D(n712), .CK(clk), .RN(n2326), .Q( d_ff2_Y[60]) ); DFFRXLTS reg_val_muxY_2stage_Q_reg_62_ ( .D(n710), .CK(clk), .RN(n2324), .Q( d_ff2_Y[62]), .QN(n2237) ); DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(n697), .CK(clk), .RN(n2326), .Q( d_ff3_sh_y_out[63]) ); DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n695), .CK(clk), .RN(n2324), .Q( d_ff3_sh_x_out[0]) ); DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n693), .CK(clk), .RN(n2301), .Q( d_ff3_sh_x_out[1]) ); DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n691), .CK(clk), .RN(n1494), .Q( d_ff3_sh_x_out[2]) ); DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n689), .CK(clk), .RN(n1494), .Q( d_ff3_sh_x_out[3]) ); DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n687), .CK(clk), .RN(n2302), .Q( d_ff3_sh_x_out[4]) ); DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n685), .CK(clk), .RN(n2323), .Q( d_ff3_sh_x_out[5]) ); DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n683), .CK(clk), .RN(n2323), .Q( d_ff3_sh_x_out[6]) ); DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n681), .CK(clk), .RN(n2323), .Q( d_ff3_sh_x_out[7]) ); DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n679), .CK(clk), .RN(n2323), .Q( d_ff3_sh_x_out[8]) ); DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n677), .CK(clk), .RN(n2307), .Q( d_ff3_sh_x_out[9]) ); DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n675), .CK(clk), .RN(n2322), .Q( d_ff3_sh_x_out[10]) ); DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n673), .CK(clk), .RN(n2306), .Q( d_ff3_sh_x_out[11]) ); DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n671), .CK(clk), .RN(n2322), .Q( d_ff3_sh_x_out[12]) ); DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n669), .CK(clk), .RN(n2306), .Q( d_ff3_sh_x_out[13]) ); DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n667), .CK(clk), .RN(n2303), .Q( d_ff3_sh_x_out[14]) ); DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n665), .CK(clk), .RN(n2307), .Q( d_ff3_sh_x_out[15]) ); DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n663), .CK(clk), .RN(n2322), .Q( d_ff3_sh_x_out[16]) ); DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n661), .CK(clk), .RN(n2306), .Q( d_ff3_sh_x_out[17]) ); DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n659), .CK(clk), .RN(n2303), .Q( d_ff3_sh_x_out[18]) ); DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n657), .CK(clk), .RN(n2325), .Q( d_ff3_sh_x_out[19]) ); DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n655), .CK(clk), .RN(n2301), .Q( d_ff3_sh_x_out[20]) ); DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n653), .CK(clk), .RN(n2325), .Q( d_ff3_sh_x_out[21]) ); DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n2301), .Q( d_ff3_sh_x_out[22]) ); DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n2325), .Q( d_ff3_sh_x_out[23]) ); DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n647), .CK(clk), .RN(n2298), .Q( d_ff3_sh_x_out[24]) ); DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n645), .CK(clk), .RN(n2319), .Q( d_ff3_sh_x_out[25]) ); DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n643), .CK(clk), .RN(n2318), .Q( d_ff3_sh_x_out[26]) ); DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n641), .CK(clk), .RN(n2299), .Q( d_ff3_sh_x_out[27]) ); DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n639), .CK(clk), .RN(n2298), .Q( d_ff3_sh_x_out[28]) ); DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n637), .CK(clk), .RN(n2319), .Q( d_ff3_sh_x_out[29]) ); DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n635), .CK(clk), .RN(n2318), .Q( d_ff3_sh_x_out[30]) ); DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n633), .CK(clk), .RN(n2299), .Q( d_ff3_sh_x_out[31]) ); DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(n631), .CK(clk), .RN(n2298), .Q( d_ff3_sh_x_out[32]) ); DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(n629), .CK(clk), .RN(n2319), .Q( d_ff3_sh_x_out[33]) ); DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(n627), .CK(clk), .RN(n1514), .Q( d_ff3_sh_x_out[34]) ); DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(n625), .CK(clk), .RN(n2314), .Q( d_ff3_sh_x_out[35]) ); DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(n623), .CK(clk), .RN(n2334), .Q( d_ff3_sh_x_out[36]) ); DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(n621), .CK(clk), .RN(n2315), .Q( d_ff3_sh_x_out[37]) ); DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(n619), .CK(clk), .RN(n1513), .Q( d_ff3_sh_x_out[38]) ); DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(n617), .CK(clk), .RN(n2315), .Q( d_ff3_sh_x_out[39]) ); DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(n615), .CK(clk), .RN(n1513), .Q( d_ff3_sh_x_out[40]) ); DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(n613), .CK(clk), .RN(n2314), .Q( d_ff3_sh_x_out[41]) ); DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(n611), .CK(clk), .RN(n2334), .Q( d_ff3_sh_x_out[42]) ); DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(n609), .CK(clk), .RN(n2315), .Q( d_ff3_sh_x_out[43]) ); DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(n607), .CK(clk), .RN(n1513), .Q( d_ff3_sh_x_out[44]) ); DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(n605), .CK(clk), .RN(n2317), .Q( d_ff3_sh_x_out[45]) ); DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(n603), .CK(clk), .RN(n2333), .Q( d_ff3_sh_x_out[46]) ); DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(n601), .CK(clk), .RN(n2335), .Q( d_ff3_sh_x_out[47]) ); DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(n599), .CK(clk), .RN(n2316), .Q( d_ff3_sh_x_out[48]) ); DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(n597), .CK(clk), .RN(n2317), .Q( d_ff3_sh_x_out[49]) ); DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(n595), .CK(clk), .RN(n2316), .Q( d_ff3_sh_x_out[50]) ); DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(n593), .CK(clk), .RN(n1514), .Q( d_ff3_sh_x_out[51]) ); DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(n569), .CK(clk), .RN(n2331), .Q( d_ff3_sh_x_out[63]) ); DFFRX2TS cont_var_count_reg_0_ ( .D(n1337), .CK(clk), .RN(n1509), .Q( cont_var_out[0]), .QN(n2231) ); DFFRX1TS reg_ch_mux_2_Q_reg_0_ ( .D(n1267), .CK(clk), .RN(n2339), .Q( sel_mux_2_reg[0]), .QN(n2230) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_53_ ( .D(n591), .CK(clk), .RN(n2314), .Q( d_ff2_X[53]), .QN(n2228) ); DFFRX2TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(clk), .RN(n564), .Q(cordic_FSM_state_reg[1]), .QN(n2222) ); DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n1072), .CK(clk), .RN(n2358), .Q( data_output[0]) ); DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n1070), .CK(clk), .RN(n2358), .Q( data_output[1]) ); DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n1068), .CK(clk), .RN(n2358), .Q( data_output[2]) ); DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n1066), .CK(clk), .RN(n2363), .Q( data_output[3]) ); DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n1064), .CK(clk), .RN(n2363), .Q( data_output[4]) ); DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n1062), .CK(clk), .RN(n2362), .Q( data_output[5]) ); DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n1060), .CK(clk), .RN(n2359), .Q( data_output[6]) ); DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n1058), .CK(clk), .RN(n2365), .Q( data_output[7]) ); DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n1056), .CK(clk), .RN(n2364), .Q( data_output[8]) ); DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n1054), .CK(clk), .RN(n2361), .Q( data_output[9]) ); DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n1052), .CK(clk), .RN(n2365), .Q( data_output[10]) ); DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n1050), .CK(clk), .RN(n2364), .Q( data_output[11]) ); DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n1048), .CK(clk), .RN(n2361), .Q( data_output[12]) ); DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n1046), .CK(clk), .RN(n2363), .Q( data_output[13]) ); DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n1044), .CK(clk), .RN(n2362), .Q( data_output[14]) ); DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n1042), .CK(clk), .RN(n2359), .Q( data_output[15]) ); DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n1040), .CK(clk), .RN(n2362), .Q( data_output[16]) ); DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n1038), .CK(clk), .RN(n2359), .Q( data_output[17]) ); DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n1036), .CK(clk), .RN(n2363), .Q( data_output[18]) ); DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n1034), .CK(clk), .RN(n2362), .Q( data_output[19]) ); DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n1032), .CK(clk), .RN(n2365), .Q( data_output[20]) ); DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n1030), .CK(clk), .RN(n2360), .Q( data_output[21]) ); DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n1028), .CK(clk), .RN(n2308), .Q( data_output[22]) ); DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n1026), .CK(clk), .RN(n1506), .Q( data_output[23]) ); DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n1024), .CK(clk), .RN(n1507), .Q( data_output[24]) ); DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n1022), .CK(clk), .RN(n2308), .Q( data_output[25]) ); DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n1020), .CK(clk), .RN(n2360), .Q( data_output[26]) ); DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n1018), .CK(clk), .RN(n2308), .Q( data_output[27]) ); DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n1016), .CK(clk), .RN(n2337), .Q( data_output[28]) ); DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n1014), .CK(clk), .RN(n2338), .Q( data_output[29]) ); DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n1012), .CK(clk), .RN(n1488), .Q( data_output[30]) ); DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n1010), .CK(clk), .RN(n2355), .Q( data_output[31]) ); DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(n1008), .CK(clk), .RN(n1501), .Q( data_output[32]) ); DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(n1006), .CK(clk), .RN(n2351), .Q( data_output[33]) ); DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(n1004), .CK(clk), .RN(n2352), .Q( data_output[34]) ); DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(n1002), .CK(clk), .RN(n2353), .Q( data_output[35]) ); DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(n1000), .CK(clk), .RN(n2355), .Q( data_output[36]) ); DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(n998), .CK(clk), .RN(n2350), .Q( data_output[37]) ); DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(n996), .CK(clk), .RN(n2350), .Q( data_output[38]) ); DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(n994), .CK(clk), .RN(n2341), .Q( data_output[39]) ); DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(n992), .CK(clk), .RN(n1502), .Q( data_output[40]) ); DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(n990), .CK(clk), .RN(n1502), .Q( data_output[41]) ); DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(n988), .CK(clk), .RN(n2327), .Q( data_output[42]) ); DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(n986), .CK(clk), .RN(n2353), .Q( data_output[43]) ); DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(n984), .CK(clk), .RN(n2355), .Q( data_output[44]) ); DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(n982), .CK(clk), .RN(n1510), .Q( data_output[45]) ); DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(n980), .CK(clk), .RN(n2357), .Q( data_output[46]) ); DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(n978), .CK(clk), .RN(n1502), .Q( data_output[47]) ); DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(n976), .CK(clk), .RN(n1493), .Q( data_output[48]) ); DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(n974), .CK(clk), .RN(n1489), .Q( data_output[49]) ); DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(n972), .CK(clk), .RN(n2357), .Q( data_output[50]) ); DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(n970), .CK(clk), .RN(n2351), .Q( data_output[51]) ); DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(n968), .CK(clk), .RN(n2352), .Q( data_output[52]) ); DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(n966), .CK(clk), .RN(n2343), .Q( data_output[53]) ); DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(n964), .CK(clk), .RN(n1502), .Q( data_output[54]) ); DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(n962), .CK(clk), .RN(n2339), .Q( data_output[55]) ); DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(n960), .CK(clk), .RN(n1489), .Q( data_output[56]) ); DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(n958), .CK(clk), .RN(n2357), .Q( data_output[57]) ); DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(n956), .CK(clk), .RN(n2351), .Q( data_output[58]) ); DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(n954), .CK(clk), .RN(n2356), .Q( data_output[59]) ); DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(n952), .CK(clk), .RN(n2296), .Q( data_output[60]) ); DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(n950), .CK(clk), .RN(n2294), .Q( data_output[61]) ); DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(n948), .CK(clk), .RN(n2313), .Q( data_output[62]) ); DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(n946), .CK(clk), .RN(n2296), .Q( data_output[63]) ); DFFRX2TS reg_val_muxX_2stage_Q_reg_55_ ( .D(n589), .CK(clk), .RN(n2317), .Q( d_ff2_X[55]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_59_ ( .D(n585), .CK(clk), .RN(n2294), .Q( d_ff2_X[59]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_57_ ( .D(n587), .CK(clk), .RN(n2313), .Q( d_ff2_X[57]) ); DFFRX4TS cordic_FSM_state_reg_reg_3_ ( .D(n1345), .CK(clk), .RN(n564), .Q( cordic_FSM_state_reg[3]), .QN(n2229) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_61_ ( .D(n583), .CK(clk), .RN(n2296), .Q( d_ff2_X[61]) ); DFFRX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n1266), .CK(clk), .RN(n2342), .Q( sel_mux_2_reg[1]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_54_ ( .D(n590), .CK(clk), .RN(n2334), .Q( d_ff2_X[54]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_56_ ( .D(n588), .CK(clk), .RN(n2335), .Q( d_ff2_X[56]), .QN(n1481) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_53_ ( .D(n719), .CK(clk), .RN(n2301), .Q( d_ff2_Y[53]), .QN(n1480) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_54_ ( .D(n718), .CK(clk), .RN(n1493), .Q( d_ff2_Y[54]) ); DFFRX1TS reg_ch_mux_1_Q_reg_0_ ( .D(n1268), .CK(clk), .RN(n2343), .Q( sel_mux_1_reg) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_63_ ( .D(n826), .CK(clk), .RN(n2299), .Q( d_ff2_Z[63]) ); DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n1335), .CK(clk), .RN(n2350), .Q( d_ff1_shift_region_flag_out[0]), .QN(n2238) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_62_ ( .D(n582), .CK(clk), .RN(n2323), .Q( d_ff2_X[62]) ); DFFRX1TS reg_ch_mux_3_Q_reg_0_ ( .D(n1269), .CK(clk), .RN(n1508), .Q( sel_mux_3_reg) ); DFFRX1TS cont_var_count_reg_1_ ( .D(n1342), .CK(clk), .RN(n1510), .Q( cont_var_out[1]), .QN(n1482) ); DFFRX1TS reg_operation_Q_reg_0_ ( .D(n1336), .CK(clk), .RN(n2341), .Q( d_ff1_operation_out), .QN(n2224) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_63_ ( .D(n698), .CK(clk), .RN(n2300), .Q( d_ff2_Y[63]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_51_ ( .D(n722), .CK(clk), .RN(n2300), .Q( d_ff2_Y[51]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_50_ ( .D(n724), .CK(clk), .RN(n2324), .Q( d_ff2_Y[50]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_49_ ( .D(n726), .CK(clk), .RN(n2326), .Q( d_ff2_Y[49]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_48_ ( .D(n728), .CK(clk), .RN(n2328), .Q( d_ff2_Y[48]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_47_ ( .D(n730), .CK(clk), .RN(n2309), .Q( d_ff2_Y[47]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_46_ ( .D(n732), .CK(clk), .RN(n2311), .Q( d_ff2_Y[46]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_45_ ( .D(n734), .CK(clk), .RN(n2310), .Q( d_ff2_Y[45]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_44_ ( .D(n736), .CK(clk), .RN(n2328), .Q( d_ff2_Y[44]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_43_ ( .D(n738), .CK(clk), .RN(n2330), .Q( d_ff2_Y[43]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_42_ ( .D(n740), .CK(clk), .RN(n1511), .Q( d_ff2_Y[42]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_41_ ( .D(n742), .CK(clk), .RN(n2309), .Q( d_ff2_Y[41]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_40_ ( .D(n744), .CK(clk), .RN(n2311), .Q( d_ff2_Y[40]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_39_ ( .D(n746), .CK(clk), .RN(n2310), .Q( d_ff2_Y[39]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_38_ ( .D(n748), .CK(clk), .RN(n2311), .Q( d_ff2_Y[38]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_37_ ( .D(n750), .CK(clk), .RN(n2329), .Q( d_ff2_Y[37]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_36_ ( .D(n752), .CK(clk), .RN(n2309), .Q( d_ff2_Y[36]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_35_ ( .D(n754), .CK(clk), .RN(n2309), .Q( d_ff2_Y[35]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_34_ ( .D(n756), .CK(clk), .RN(n2328), .Q( d_ff2_Y[34]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_33_ ( .D(n758), .CK(clk), .RN(n2310), .Q( d_ff2_Y[33]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_32_ ( .D(n760), .CK(clk), .RN(n2311), .Q( d_ff2_Y[32]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n762), .CK(clk), .RN(n2310), .Q( d_ff2_Y[31]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n764), .CK(clk), .RN(n2309), .Q( d_ff2_Y[30]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n766), .CK(clk), .RN(n2328), .Q( d_ff2_Y[29]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n768), .CK(clk), .RN(n2332), .Q( d_ff2_Y[28]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n770), .CK(clk), .RN(n2331), .Q( d_ff2_Y[27]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n772), .CK(clk), .RN(n2304), .Q( d_ff2_Y[26]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n774), .CK(clk), .RN(n2332), .Q( d_ff2_Y[25]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n776), .CK(clk), .RN(n2331), .Q( d_ff2_Y[24]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n778), .CK(clk), .RN(n2332), .Q( d_ff2_Y[23]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n780), .CK(clk), .RN(n2304), .Q( d_ff2_Y[22]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n782), .CK(clk), .RN(n2331), .Q( d_ff2_Y[21]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n784), .CK(clk), .RN(n2304), .Q( d_ff2_Y[20]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n786), .CK(clk), .RN(n2303), .Q( d_ff2_Y[19]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n788), .CK(clk), .RN(n2294), .Q( d_ff2_Y[18]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n790), .CK(clk), .RN(n2313), .Q( d_ff2_Y[17]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n792), .CK(clk), .RN(n2296), .Q( d_ff2_Y[16]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n794), .CK(clk), .RN(n2312), .Q( d_ff2_Y[15]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n796), .CK(clk), .RN(n2295), .Q( d_ff2_Y[14]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n798), .CK(clk), .RN(n2295), .Q( d_ff2_Y[13]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n800), .CK(clk), .RN(n2295), .Q( d_ff2_Y[12]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n802), .CK(clk), .RN(n2295), .Q( d_ff2_Y[11]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n804), .CK(clk), .RN(n2295), .Q( d_ff2_Y[10]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n806), .CK(clk), .RN(n2295), .Q( d_ff2_Y[9]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n808), .CK(clk), .RN(n2295), .Q( d_ff2_Y[8]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n810), .CK(clk), .RN(n2295), .Q( d_ff2_Y[7]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n812), .CK(clk), .RN(n2295), .Q( d_ff2_Y[6]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n814), .CK(clk), .RN(n2295), .Q( d_ff2_Y[5]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n816), .CK(clk), .RN(n2297), .Q( d_ff2_Y[4]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n818), .CK(clk), .RN(n2297), .Q( d_ff2_Y[3]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n820), .CK(clk), .RN(n2297), .Q( d_ff2_Y[2]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n822), .CK(clk), .RN(n2297), .Q( d_ff2_Y[1]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n824), .CK(clk), .RN(n2297), .Q( d_ff2_Y[0]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_49_ ( .D(n598), .CK(clk), .RN(n1513), .Q( d_ff2_X[49]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_48_ ( .D(n600), .CK(clk), .RN(n2315), .Q( d_ff2_X[48]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_46_ ( .D(n604), .CK(clk), .RN(n2314), .Q( d_ff2_X[46]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_45_ ( .D(n606), .CK(clk), .RN(n1514), .Q( d_ff2_X[45]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_43_ ( .D(n610), .CK(clk), .RN(n2335), .Q( d_ff2_X[43]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_42_ ( .D(n612), .CK(clk), .RN(n2333), .Q( d_ff2_X[42]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_41_ ( .D(n614), .CK(clk), .RN(n1514), .Q( d_ff2_X[41]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_39_ ( .D(n618), .CK(clk), .RN(n1514), .Q( d_ff2_X[39]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_36_ ( .D(n624), .CK(clk), .RN(n2333), .Q( d_ff2_X[36]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_35_ ( .D(n626), .CK(clk), .RN(n2317), .Q( d_ff2_X[35]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_34_ ( .D(n628), .CK(clk), .RN(n2318), .Q( d_ff2_X[34]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_32_ ( .D(n632), .CK(clk), .RN(n2319), .Q( d_ff2_X[32]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n634), .CK(clk), .RN(n2298), .Q( d_ff2_X[31]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n638), .CK(clk), .RN(n2319), .Q( d_ff2_X[29]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n640), .CK(clk), .RN(n2298), .Q( d_ff2_X[28]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n644), .CK(clk), .RN(n2299), .Q( d_ff2_X[26]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n648), .CK(clk), .RN(n1494), .Q( d_ff2_X[24]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n658), .CK(clk), .RN(n2321), .Q( d_ff2_X[19]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n668), .CK(clk), .RN(n2321), .Q( d_ff2_X[14]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n670), .CK(clk), .RN(n2321), .Q( d_ff2_X[13]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n674), .CK(clk), .RN(n2321), .Q( d_ff2_X[11]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n678), .CK(clk), .RN(n2323), .Q( d_ff2_X[9]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n680), .CK(clk), .RN(n2323), .Q( d_ff2_X[8]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n682), .CK(clk), .RN(n2323), .Q( d_ff2_X[7]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n684), .CK(clk), .RN(n2323), .Q( d_ff2_X[6]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n690), .CK(clk), .RN(n2302), .Q( d_ff2_X[3]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n696), .CK(clk), .RN(n2320), .Q( d_ff2_X[0]) ); DFFRX1TS d_ff4_Xn_Q_reg_60_ ( .D(n1077), .CK(clk), .RN(n2312), .Q( d_ff_Xn[60]) ); DFFRX1TS d_ff4_Xn_Q_reg_58_ ( .D(n1079), .CK(clk), .RN(n2357), .Q( d_ff_Xn[58]) ); DFFRX1TS d_ff4_Xn_Q_reg_56_ ( .D(n1081), .CK(clk), .RN(n1501), .Q( d_ff_Xn[56]) ); DFFRX1TS d_ff4_Xn_Q_reg_54_ ( .D(n1083), .CK(clk), .RN(n2342), .Q( d_ff_Xn[54]) ); DFFRX1TS d_ff4_Xn_Q_reg_53_ ( .D(n1084), .CK(clk), .RN(n2351), .Q( d_ff_Xn[53]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_47_ ( .D(n602), .CK(clk), .RN(n2334), .Q( d_ff2_X[47]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_44_ ( .D(n608), .CK(clk), .RN(n2316), .Q( d_ff2_X[44]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_40_ ( .D(n616), .CK(clk), .RN(n2316), .Q( d_ff2_X[40]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_38_ ( .D(n620), .CK(clk), .RN(n2316), .Q( d_ff2_X[38]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_37_ ( .D(n622), .CK(clk), .RN(n2335), .Q( d_ff2_X[37]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_33_ ( .D(n630), .CK(clk), .RN(n2299), .Q( d_ff2_X[33]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n636), .CK(clk), .RN(n2318), .Q( d_ff2_X[30]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n642), .CK(clk), .RN(n2318), .Q( d_ff2_X[27]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n646), .CK(clk), .RN(n2319), .Q( d_ff2_X[25]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n2325), .Q( d_ff2_X[23]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n2325), .Q( d_ff2_X[22]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n2302), .Q( d_ff2_X[21]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n656), .CK(clk), .RN(n2320), .Q( d_ff2_X[20]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n660), .CK(clk), .RN(n2321), .Q( d_ff2_X[18]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n662), .CK(clk), .RN(n2321), .Q( d_ff2_X[17]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n664), .CK(clk), .RN(n2321), .Q( d_ff2_X[16]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n666), .CK(clk), .RN(n2321), .Q( d_ff2_X[15]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n672), .CK(clk), .RN(n2321), .Q( d_ff2_X[12]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n676), .CK(clk), .RN(n2321), .Q( d_ff2_X[10]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n686), .CK(clk), .RN(n2323), .Q( d_ff2_X[5]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n688), .CK(clk), .RN(n2301), .Q( d_ff2_X[4]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n692), .CK(clk), .RN(n1494), .Q( d_ff2_X[2]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n694), .CK(clk), .RN(n2324), .Q( d_ff2_X[1]) ); DFFRX1TS d_ff4_Xn_Q_reg_63_ ( .D(n1074), .CK(clk), .RN(n2312), .Q( d_ff_Xn[63]) ); DFFRX1TS d_ff4_Xn_Q_reg_52_ ( .D(n1085), .CK(clk), .RN(n2352), .Q( d_ff_Xn[52]) ); DFFRX1TS d_ff4_Xn_Q_reg_51_ ( .D(n1086), .CK(clk), .RN(n2353), .Q( d_ff_Xn[51]) ); DFFRX1TS d_ff4_Xn_Q_reg_50_ ( .D(n1087), .CK(clk), .RN(n1494), .Q( d_ff_Xn[50]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_55_ ( .D(n717), .CK(clk), .RN(n2320), .Q( d_ff2_Y[55]), .QN(n2232) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_59_ ( .D(n713), .CK(clk), .RN(n2302), .Q( d_ff2_Y[59]), .QN(n2235) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_57_ ( .D(n715), .CK(clk), .RN(n2301), .Q( d_ff2_Y[57]), .QN(n2233) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_61_ ( .D(n711), .CK(clk), .RN(n2325), .Q( d_ff2_Y[61]), .QN(n2236) ); DFFRX1TS reg_LUT_Q_reg_3_ ( .D(n942), .CK(clk), .RN(n2327), .Q( d_ff3_LUT_out[3]) ); DFFRX1TS reg_LUT_Q_reg_48_ ( .D(n897), .CK(clk), .RN(n2307), .Q( d_ff3_LUT_out[48]) ); DFFRX4TS cont_iter_count_reg_2_ ( .D(n1339), .CK(clk), .RN(n2350), .Q( cont_iter_out[2]), .QN(n2227) ); DFFRX1TS d_ff4_Xn_Q_reg_47_ ( .D(n1090), .CK(clk), .RN(n2366), .Q( d_ff_Xn[47]) ); DFFRX1TS d_ff4_Xn_Q_reg_37_ ( .D(n1100), .CK(clk), .RN(n2354), .Q( d_ff_Xn[37]) ); DFFRX1TS d_ff4_Xn_Q_reg_38_ ( .D(n1099), .CK(clk), .RN(n2354), .Q( d_ff_Xn[38]) ); DFFRX1TS d_ff4_Xn_Q_reg_39_ ( .D(n1098), .CK(clk), .RN(n2354), .Q( d_ff_Xn[39]) ); DFFRX1TS d_ff4_Xn_Q_reg_40_ ( .D(n1097), .CK(clk), .RN(n2354), .Q( d_ff_Xn[40]) ); DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n1127), .CK(clk), .RN(n2365), .Q( d_ff_Xn[10]) ); DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n1128), .CK(clk), .RN(n2361), .Q(d_ff_Xn[9]) ); DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n1129), .CK(clk), .RN(n2360), .Q(d_ff_Xn[8]) ); DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n1130), .CK(clk), .RN(n1506), .Q(d_ff_Xn[7]) ); DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n1334), .CK(clk), .RN(n1508), .Q( d_ff1_shift_region_flag_out[1]), .QN(n2226) ); DFFRX1TS d_ff4_Xn_Q_reg_55_ ( .D(n1082), .CK(clk), .RN(n2366), .Q( d_ff_Xn[55]) ); DFFRX1TS d_ff4_Xn_Q_reg_57_ ( .D(n1080), .CK(clk), .RN(n1510), .Q( d_ff_Xn[57]) ); DFFRX1TS d_ff4_Xn_Q_reg_59_ ( .D(n1078), .CK(clk), .RN(n2352), .Q( d_ff_Xn[59]) ); DFFRX1TS d_ff4_Xn_Q_reg_61_ ( .D(n1076), .CK(clk), .RN(n2296), .Q( d_ff_Xn[61]) ); DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n1137), .CK(clk), .RN(n2348), .Q(d_ff_Xn[0]) ); DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n1134), .CK(clk), .RN(n2358), .Q(d_ff_Xn[3]) ); DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n1131), .CK(clk), .RN(n2362), .Q(d_ff_Xn[6]) ); DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n1126), .CK(clk), .RN(n2364), .Q( d_ff_Xn[11]) ); DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n1124), .CK(clk), .RN(n2308), .Q( d_ff_Xn[13]) ); DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n1123), .CK(clk), .RN(n2363), .Q( d_ff_Xn[14]) ); DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n1118), .CK(clk), .RN(n2359), .Q( d_ff_Xn[19]) ); DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n1113), .CK(clk), .RN(n1507), .Q( d_ff_Xn[24]) ); DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n1111), .CK(clk), .RN(n2364), .Q( d_ff_Xn[26]) ); DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n1109), .CK(clk), .RN(n2338), .Q( d_ff_Xn[28]) ); DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n1108), .CK(clk), .RN(n2336), .Q( d_ff_Xn[29]) ); DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n1106), .CK(clk), .RN(n1501), .Q( d_ff_Xn[31]) ); DFFRX1TS d_ff4_Xn_Q_reg_32_ ( .D(n1105), .CK(clk), .RN(n2320), .Q( d_ff_Xn[32]) ); DFFRX1TS d_ff4_Xn_Q_reg_34_ ( .D(n1103), .CK(clk), .RN(n2357), .Q( d_ff_Xn[34]) ); DFFRX1TS d_ff4_Xn_Q_reg_35_ ( .D(n1102), .CK(clk), .RN(n2355), .Q( d_ff_Xn[35]) ); DFFRX1TS d_ff4_Xn_Q_reg_36_ ( .D(n1101), .CK(clk), .RN(n2352), .Q( d_ff_Xn[36]) ); DFFRX1TS d_ff4_Xn_Q_reg_41_ ( .D(n1096), .CK(clk), .RN(n1501), .Q( d_ff_Xn[41]) ); DFFRX1TS d_ff4_Xn_Q_reg_42_ ( .D(n1095), .CK(clk), .RN(n2325), .Q( d_ff_Xn[42]) ); DFFRX1TS d_ff4_Xn_Q_reg_43_ ( .D(n1094), .CK(clk), .RN(n1501), .Q( d_ff_Xn[43]) ); DFFRX1TS d_ff4_Xn_Q_reg_45_ ( .D(n1092), .CK(clk), .RN(n2357), .Q( d_ff_Xn[45]) ); DFFRX1TS d_ff4_Xn_Q_reg_46_ ( .D(n1091), .CK(clk), .RN(n2355), .Q( d_ff_Xn[46]) ); DFFRX1TS d_ff4_Xn_Q_reg_48_ ( .D(n1089), .CK(clk), .RN(n2301), .Q( d_ff_Xn[48]) ); DFFRX1TS d_ff4_Xn_Q_reg_49_ ( .D(n1088), .CK(clk), .RN(n1501), .Q( d_ff_Xn[49]) ); DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n1136), .CK(clk), .RN(n2358), .Q(d_ff_Xn[1]) ); DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n1135), .CK(clk), .RN(n2358), .Q(d_ff_Xn[2]) ); DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n1133), .CK(clk), .RN(n2363), .Q(d_ff_Xn[4]) ); DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n1132), .CK(clk), .RN(n2359), .Q(d_ff_Xn[5]) ); DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n1125), .CK(clk), .RN(n1506), .Q( d_ff_Xn[12]) ); DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n1122), .CK(clk), .RN(n2359), .Q( d_ff_Xn[15]) ); DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n1121), .CK(clk), .RN(n2362), .Q( d_ff_Xn[16]) ); DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n1120), .CK(clk), .RN(n2362), .Q( d_ff_Xn[17]) ); DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n1119), .CK(clk), .RN(n2363), .Q( d_ff_Xn[18]) ); DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n1117), .CK(clk), .RN(n2365), .Q( d_ff_Xn[20]) ); DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n1116), .CK(clk), .RN(n2364), .Q( d_ff_Xn[21]) ); DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n1115), .CK(clk), .RN(n1506), .Q( d_ff_Xn[22]) ); DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n1114), .CK(clk), .RN(n2308), .Q( d_ff_Xn[23]) ); DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n1112), .CK(clk), .RN(n2365), .Q( d_ff_Xn[25]) ); DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n1110), .CK(clk), .RN(n1506), .Q( d_ff_Xn[27]) ); DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n1107), .CK(clk), .RN(n2338), .Q( d_ff_Xn[30]) ); DFFRX1TS d_ff4_Xn_Q_reg_33_ ( .D(n1104), .CK(clk), .RN(n1501), .Q( d_ff_Xn[33]) ); DFFRX1TS d_ff4_Xn_Q_reg_44_ ( .D(n1093), .CK(clk), .RN(n2352), .Q( d_ff_Xn[44]) ); DFFRX1TS d_ff4_Xn_Q_reg_62_ ( .D(n1075), .CK(clk), .RN(n2312), .Q( d_ff_Xn[62]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_50_ ( .D(n596), .CK(clk), .RN(n2315), .Q( d_ff2_X[50]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_51_ ( .D(n594), .CK(clk), .RN(n1513), .Q( d_ff2_X[51]) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_63_ ( .D(n570), .CK(clk), .RN(n2312), .Q( d_ff2_X[63]) ); DFFRX1TS reg_val_muxY_2stage_Q_reg_52_ ( .D(n720), .CK(clk), .RN(n2300), .Q( d_ff2_Y[52]), .QN(n2234) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_58_ ( .D(n586), .CK(clk), .RN(n2313), .Q( d_ff2_X[58]), .QN(n1483) ); DFFRX1TS reg_val_muxX_2stage_Q_reg_60_ ( .D(n584), .CK(clk), .RN(n2294), .Q( d_ff2_X[60]), .QN(n1485) ); DFFRX1TS reg_LUT_Q_reg_15_ ( .D(n930), .CK(clk), .RN(n2310), .Q( d_ff3_LUT_out[15]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_57_ ( .D(n832), .CK(clk), .RN(n2299), .Q( d_ff2_Z[57]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_59_ ( .D(n830), .CK(clk), .RN(n2319), .Q( d_ff2_Z[59]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_61_ ( .D(n828), .CK(clk), .RN(n2299), .Q( d_ff2_Z[61]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_62_ ( .D(n827), .CK(clk), .RN(n2298), .Q( d_ff2_Z[62]) ); DFFRX1TS d_ff5_Q_reg_63_ ( .D(n947), .CK(clk), .RN(n2313), .Q( data_output2_63_) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n888), .CK(clk), .RN(n2332), .Q( d_ff2_Z[1]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n887), .CK(clk), .RN(n2331), .Q( d_ff2_Z[2]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n886), .CK(clk), .RN(n2304), .Q( d_ff2_Z[3]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n885), .CK(clk), .RN(n2332), .Q( d_ff2_Z[4]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n884), .CK(clk), .RN(n2303), .Q( d_ff2_Z[5]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n883), .CK(clk), .RN(n2307), .Q( d_ff2_Z[6]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n882), .CK(clk), .RN(n2322), .Q( d_ff2_Z[7]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n881), .CK(clk), .RN(n2306), .Q( d_ff2_Z[8]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n880), .CK(clk), .RN(n2303), .Q( d_ff2_Z[9]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n879), .CK(clk), .RN(n2307), .Q( d_ff2_Z[10]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n878), .CK(clk), .RN(n2322), .Q( d_ff2_Z[11]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n877), .CK(clk), .RN(n2306), .Q( d_ff2_Z[12]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n876), .CK(clk), .RN(n2303), .Q( d_ff2_Z[13]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n875), .CK(clk), .RN(n1493), .Q( d_ff2_Z[14]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n874), .CK(clk), .RN(n2300), .Q( d_ff2_Z[15]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n873), .CK(clk), .RN(n2320), .Q( d_ff2_Z[16]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n872), .CK(clk), .RN(n2326), .Q( d_ff2_Z[17]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n871), .CK(clk), .RN(n2324), .Q( d_ff2_Z[18]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n870), .CK(clk), .RN(n2320), .Q( d_ff2_Z[19]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n869), .CK(clk), .RN(n2325), .Q( d_ff2_Z[20]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n868), .CK(clk), .RN(n1493), .Q( d_ff2_Z[21]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n867), .CK(clk), .RN(n2300), .Q( d_ff2_Z[22]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n866), .CK(clk), .RN(n2302), .Q( d_ff2_Z[23]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n865), .CK(clk), .RN(n2325), .Q( d_ff2_Z[24]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n864), .CK(clk), .RN(n1493), .Q( d_ff2_Z[25]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n863), .CK(clk), .RN(n2300), .Q( d_ff2_Z[26]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n862), .CK(clk), .RN(n2324), .Q( d_ff2_Z[27]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n861), .CK(clk), .RN(n2301), .Q( d_ff2_Z[28]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n860), .CK(clk), .RN(n2326), .Q( d_ff2_Z[29]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n859), .CK(clk), .RN(n2302), .Q( d_ff2_Z[30]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n858), .CK(clk), .RN(n2302), .Q( d_ff2_Z[31]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_32_ ( .D(n857), .CK(clk), .RN(n2325), .Q( d_ff2_Z[32]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_33_ ( .D(n856), .CK(clk), .RN(n2324), .Q( d_ff2_Z[33]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_34_ ( .D(n855), .CK(clk), .RN(n2324), .Q( d_ff2_Z[34]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_35_ ( .D(n854), .CK(clk), .RN(n2301), .Q( d_ff2_Z[35]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_36_ ( .D(n853), .CK(clk), .RN(n2326), .Q( d_ff2_Z[36]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_37_ ( .D(n852), .CK(clk), .RN(n2326), .Q( d_ff2_Z[37]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_38_ ( .D(n851), .CK(clk), .RN(n1493), .Q( d_ff2_Z[38]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_39_ ( .D(n850), .CK(clk), .RN(n2300), .Q( d_ff2_Z[39]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_40_ ( .D(n849), .CK(clk), .RN(n2326), .Q( d_ff2_Z[40]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_41_ ( .D(n848), .CK(clk), .RN(n2320), .Q( d_ff2_Z[41]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_42_ ( .D(n847), .CK(clk), .RN(n1493), .Q( d_ff2_Z[42]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_43_ ( .D(n846), .CK(clk), .RN(n2300), .Q( d_ff2_Z[43]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_44_ ( .D(n845), .CK(clk), .RN(n2318), .Q( d_ff2_Z[44]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_45_ ( .D(n844), .CK(clk), .RN(n2299), .Q( d_ff2_Z[45]) ); DFFRX1TS reg_val_muxZ_2stage_Q_reg_46_ ( .D(n843), .CK(clk), .RN(n2298), .Q( d_ff2_Z[46]) ); DFFRX2TS cordic_FSM_state_reg_reg_2_ ( .D(n1344), .CK(clk), .RN(n564), .Q( cordic_FSM_state_reg[2]), .QN(n2225) ); DFFRX1TS cont_iter_count_reg_1_ ( .D(n1340), .CK(clk), .RN(n1509), .Q(n1477), .QN(n1479) ); DFFRXLTS d_ff5_Q_reg_37_ ( .D(n999), .CK(clk), .RN(n2354), .Q( sign_inv_out[37]) ); DFFRXLTS d_ff5_Q_reg_38_ ( .D(n997), .CK(clk), .RN(n2354), .Q( sign_inv_out[38]) ); DFFRXLTS d_ff5_Q_reg_39_ ( .D(n995), .CK(clk), .RN(n2354), .Q( sign_inv_out[39]) ); DFFRXLTS d_ff5_Q_reg_9_ ( .D(n1055), .CK(clk), .RN(n2308), .Q( sign_inv_out[9]) ); DFFRXLTS d_ff5_Q_reg_8_ ( .D(n1057), .CK(clk), .RN(n2364), .Q( sign_inv_out[8]) ); DFFRXLTS d_ff5_Q_reg_7_ ( .D(n1059), .CK(clk), .RN(n1507), .Q( sign_inv_out[7]) ); DFFRX4TS cont_iter_count_reg_0_ ( .D(n1341), .CK(clk), .RN(n2339), .Q( cont_iter_out[0]), .QN(n1484) ); DFFRX2TS reg_val_muxX_2stage_Q_reg_52_ ( .D(n592), .CK(clk), .RN(n2333), .Q( d_ff2_X[52]) ); DFFRX2TS cordic_FSM_state_reg_reg_0_ ( .D(n1343), .CK(clk), .RN(n564), .Q( cordic_FSM_state_reg[0]), .QN(n2223) ); AOI222X1TS U1472 ( .A0(n1844), .A1(d_ff2_Z[60]), .B0(n1736), .B1(d_ff1_Z[60]), .C0(d_ff_Zn[60]), .C1(n1842), .Y(n1826) ); AOI222X1TS U1473 ( .A0(n1837), .A1(d_ff2_Z[56]), .B0(n1736), .B1(d_ff1_Z[56]), .C0(d_ff_Zn[56]), .C1(n1842), .Y(n1832) ); AOI222X1TS U1474 ( .A0(n1844), .A1(d_ff2_Z[58]), .B0(n1683), .B1(d_ff1_Z[58]), .C0(d_ff_Zn[58]), .C1(n1840), .Y(n1830) ); AOI32X1TS U1475 ( .A0(n2064), .A1(n2089), .A2(n2195), .B0(d_ff3_LUT_out[0]), .B1(n2044), .Y(n2024) ); AOI222X1TS U1476 ( .A0(n1837), .A1(d_ff2_Z[55]), .B0(n1821), .B1(d_ff1_Z[55]), .C0(d_ff_Zn[55]), .C1(n1840), .Y(n1838) ); AOI222X1TS U1477 ( .A0(n1837), .A1(d_ff2_Z[52]), .B0(n1719), .B1(d_ff1_Z[52]), .C0(d_ff_Zn[52]), .C1(n1817), .Y(n1706) ); AOI222X1TS U1478 ( .A0(n1837), .A1(d_ff2_Z[53]), .B0(n1719), .B1(d_ff1_Z[53]), .C0(d_ff_Zn[53]), .C1(n1817), .Y(n1704) ); AOI222X1TS U1479 ( .A0(d_ff2_Z[54]), .A1(n1789), .B0(d_ff2_Y[54]), .B1(n1497), .C0(d_ff2_X[54]), .C1(n1889), .Y(n1790) ); AOI222X1TS U1480 ( .A0(d_ff2_Z[51]), .A1(n1789), .B0(d_ff2_Y[51]), .B1(n1497), .C0(d_ff2_X[51]), .C1(n1889), .Y(n1788) ); AOI222X1TS U1481 ( .A0(d_ff2_Z[0]), .A1(n1789), .B0(d_ff2_Y[0]), .B1(n1887), .C0(d_ff2_X[0]), .C1(n1889), .Y(n1785) ); AOI222X1TS U1482 ( .A0(d_ff2_Z[47]), .A1(n1789), .B0(d_ff2_Y[47]), .B1(n1782), .C0(d_ff2_X[47]), .C1(n1889), .Y(n1783) ); AOI222X1TS U1483 ( .A0(d_ff2_Z[48]), .A1(n1789), .B0(d_ff2_Y[48]), .B1(n1871), .C0(d_ff2_X[48]), .C1(n1889), .Y(n1787) ); AOI222X1TS U1484 ( .A0(d_ff2_Z[49]), .A1(n1789), .B0(d_ff2_Y[49]), .B1(n1871), .C0(d_ff2_X[49]), .C1(n1889), .Y(n1784) ); AOI222X1TS U1485 ( .A0(d_ff2_Z[50]), .A1(n1789), .B0(d_ff2_Y[50]), .B1(n1871), .C0(d_ff2_X[50]), .C1(n1889), .Y(n1786) ); AOI222X1TS U1486 ( .A0(d_ff3_LUT_out[50]), .A1(n1892), .B0(n1887), .B1( d_ff3_sh_x_out[50]), .C0(n1886), .C1(d_ff3_sh_y_out[50]), .Y(n1888) ); AOI222X1TS U1487 ( .A0(d_ff3_LUT_out[47]), .A1(n1892), .B0(n1887), .B1( d_ff3_sh_x_out[47]), .C0(n1886), .C1(d_ff3_sh_y_out[47]), .Y(n1884) ); AOI222X1TS U1488 ( .A0(d_ff3_LUT_out[43]), .A1(n1892), .B0(n1887), .B1( d_ff3_sh_x_out[43]), .C0(n1886), .C1(d_ff3_sh_y_out[43]), .Y(n1883) ); AOI222X1TS U1489 ( .A0(d_ff3_LUT_out[45]), .A1(n1892), .B0(n1887), .B1( d_ff3_sh_x_out[45]), .C0(n1886), .C1(d_ff3_sh_y_out[45]), .Y(n1882) ); AOI222X1TS U1490 ( .A0(d_ff3_LUT_out[55]), .A1(n1892), .B0( d_ff3_sh_y_out[55]), .B1(n1889), .C0(d_ff3_sh_x_out[55]), .C1(n1806), .Y(n1890) ); AOI222X1TS U1491 ( .A0(d_ff3_LUT_out[54]), .A1(n1892), .B0(n1887), .B1( d_ff3_sh_x_out[54]), .C0(n1889), .C1(d_ff3_sh_y_out[54]), .Y(n1885) ); AOI222X1TS U1492 ( .A0(d_ff3_LUT_out[1]), .A1(n1873), .B0(n1893), .B1( d_ff3_sh_x_out[1]), .C0(n1894), .C1(d_ff3_sh_y_out[1]), .Y(n1864) ); AOI222X1TS U1493 ( .A0(d_ff3_LUT_out[6]), .A1(n1873), .B0(n1498), .B1( d_ff3_sh_x_out[6]), .C0(n1894), .C1(d_ff3_sh_y_out[6]), .Y(n1869) ); AOI222X1TS U1494 ( .A0(d_ff3_LUT_out[7]), .A1(n1873), .B0(n1782), .B1( d_ff3_sh_x_out[7]), .C0(n1894), .C1(d_ff3_sh_y_out[7]), .Y(n1872) ); AOI222X1TS U1495 ( .A0(d_ff3_LUT_out[5]), .A1(n1873), .B0(n1893), .B1( d_ff3_sh_x_out[5]), .C0(n1894), .C1(d_ff3_sh_y_out[5]), .Y(n1870) ); AOI222X1TS U1496 ( .A0(d_ff3_LUT_out[0]), .A1(n1873), .B0(n1498), .B1( d_ff3_sh_x_out[0]), .C0(n1894), .C1(d_ff3_sh_y_out[0]), .Y(n1862) ); AOI222X1TS U1497 ( .A0(d_ff3_LUT_out[9]), .A1(n1873), .B0(n1782), .B1( d_ff3_sh_x_out[9]), .C0(n1867), .C1(d_ff3_sh_y_out[9]), .Y(n1868) ); AOI222X1TS U1498 ( .A0(d_ff3_LUT_out[39]), .A1(n1881), .B0(n1852), .B1( d_ff3_sh_x_out[39]), .C0(n1886), .C1(d_ff3_sh_y_out[39]), .Y(n1849) ); AOI222X1TS U1499 ( .A0(d_ff3_LUT_out[27]), .A1(n1814), .B0(n1813), .B1( d_ff3_sh_x_out[27]), .C0(n1812), .C1(d_ff3_sh_y_out[27]), .Y(n1815) ); AOI222X1TS U1500 ( .A0(d_ff3_LUT_out[25]), .A1(n1814), .B0(n1813), .B1( d_ff3_sh_x_out[25]), .C0(n1812), .C1(d_ff3_sh_y_out[25]), .Y(n1808) ); AOI222X1TS U1501 ( .A0(d_ff3_LUT_out[29]), .A1(n1814), .B0(n1813), .B1( d_ff3_sh_x_out[29]), .C0(n1851), .C1(d_ff3_sh_y_out[29]), .Y(n1767) ); AOI222X1TS U1502 ( .A0(d_ff3_LUT_out[33]), .A1(n1881), .B0(n1852), .B1( d_ff3_sh_x_out[33]), .C0(n1851), .C1(d_ff3_sh_y_out[33]), .Y(n1853) ); AOI222X1TS U1503 ( .A0(d_ff3_LUT_out[26]), .A1(n1814), .B0(n1813), .B1( d_ff3_sh_x_out[26]), .C0(n1812), .C1(d_ff3_sh_y_out[26]), .Y(n1805) ); AOI222X1TS U1504 ( .A0(d_ff2_Z[9]), .A1(n1881), .B0(d_ff2_Y[9]), .B1(n1854), .C0(d_ff2_X[9]), .C1(n1910), .Y(n1855) ); AOI222X1TS U1505 ( .A0(d_ff3_LUT_out[14]), .A1(n1810), .B0(n1498), .B1( d_ff3_sh_x_out[14]), .C0(n1867), .C1(d_ff3_sh_y_out[14]), .Y(n1796) ); AOI222X1TS U1506 ( .A0(d_ff3_LUT_out[11]), .A1(n1810), .B0(n1893), .B1( d_ff3_sh_x_out[11]), .C0(n1867), .C1(d_ff3_sh_y_out[11]), .Y(n1811) ); INVX2TS U1507 ( .A(n1906), .Y(n1727) ); NAND2X1TS U1508 ( .A(n2139), .B(n2138), .Y(n2142) ); CMPR32X2TS U1509 ( .A(d_ff2_Y[54]), .B(n1491), .C(n1534), .CO(n1550), .S( n1535) ); CMPR32X2TS U1510 ( .A(n1491), .B(d_ff2_X[54]), .C(n2193), .CO(n2197), .S( n2194) ); INVX4TS U1511 ( .A(cont_iter_out[0]), .Y(n2188) ); NOR2X1TS U1512 ( .A(sel_mux_1_reg), .B(n2187), .Y(n1664) ); AOI31XLTS U1513 ( .A0(n1505), .A1(n1678), .A2(n2227), .B0(n1937), .Y(n1679) ); NAND2BX1TS U1514 ( .AN(n2050), .B(n2083), .Y(n2079) ); NAND2X2TS U1515 ( .A(n2141), .B(n2127), .Y(n2144) ); AO22XLTS U1516 ( .A0(n2221), .A1(n2140), .B0(n2152), .B1(d_ff3_sh_y_out[56]), .Y(n705) ); AO22XLTS U1517 ( .A0(n2204), .A1(n2199), .B0(n2220), .B1(d_ff3_sh_x_out[56]), .Y(n577) ); AOI222X1TS U1518 ( .A0(n2187), .A1(d_ff2_Z[3]), .B0(n1821), .B1(d_ff1_Z[3]), .C0(d_ff_Zn[3]), .C1(n2118), .Y(n1737) ); AOI222X1TS U1519 ( .A0(n2187), .A1(d_ff2_Z[4]), .B0(n1821), .B1(d_ff1_Z[4]), .C0(d_ff_Zn[4]), .C1(n2118), .Y(n1741) ); AO22XLTS U1520 ( .A0(n2119), .A1(d_ff2_Y[42]), .B0(n2117), .B1( d_ff3_sh_y_out[42]), .Y(n739) ); AO22XLTS U1521 ( .A0(n2119), .A1(d_ff2_Y[40]), .B0(n2117), .B1( d_ff3_sh_y_out[40]), .Y(n743) ); AO22XLTS U1522 ( .A0(n2110), .A1(d_ff2_Y[18]), .B0(n2109), .B1( d_ff3_sh_y_out[18]), .Y(n787) ); AO22XLTS U1523 ( .A0(n2110), .A1(d_ff2_Y[23]), .B0(n2109), .B1( d_ff3_sh_y_out[23]), .Y(n777) ); AO22XLTS U1524 ( .A0(n2115), .A1(d_ff2_Y[38]), .B0(n2117), .B1( d_ff3_sh_y_out[38]), .Y(n747) ); AO22XLTS U1525 ( .A0(n2115), .A1(d_ff2_Y[37]), .B0(n2117), .B1( d_ff3_sh_y_out[37]), .Y(n749) ); AO22XLTS U1526 ( .A0(n2115), .A1(d_ff2_Y[36]), .B0(n2117), .B1( d_ff3_sh_y_out[36]), .Y(n751) ); AO22XLTS U1527 ( .A0(n2115), .A1(d_ff2_Y[35]), .B0(n2117), .B1( d_ff3_sh_y_out[35]), .Y(n753) ); AOI222X1TS U1528 ( .A0(n2187), .A1(d_ff2_Z[5]), .B0(n1736), .B1(d_ff1_Z[5]), .C0(d_ff_Zn[5]), .C1(n2118), .Y(n1686) ); AO22XLTS U1529 ( .A0(n2104), .A1(d_ff2_Y[2]), .B0(n2103), .B1( d_ff3_sh_y_out[2]), .Y(n819) ); AO22XLTS U1530 ( .A0(n2110), .A1(d_ff2_Y[24]), .B0(n2109), .B1( d_ff3_sh_y_out[24]), .Y(n775) ); AO22XLTS U1531 ( .A0(n2104), .A1(d_ff2_Y[4]), .B0(n2103), .B1( d_ff3_sh_y_out[4]), .Y(n815) ); AO22XLTS U1532 ( .A0(n2110), .A1(d_ff2_Y[22]), .B0(n2109), .B1( d_ff3_sh_y_out[22]), .Y(n779) ); AO22XLTS U1533 ( .A0(n2110), .A1(d_ff2_Y[21]), .B0(n2109), .B1( d_ff3_sh_y_out[21]), .Y(n781) ); AO22XLTS U1534 ( .A0(n2221), .A1(d_ff2_Y[20]), .B0(n2109), .B1( d_ff3_sh_y_out[20]), .Y(n783) ); AO22XLTS U1535 ( .A0(n2115), .A1(d_ff2_Y[16]), .B0(n2109), .B1( d_ff3_sh_y_out[16]), .Y(n791) ); AO22XLTS U1536 ( .A0(n2107), .A1(d_ff2_Y[17]), .B0(n2109), .B1( d_ff3_sh_y_out[17]), .Y(n789) ); AO22XLTS U1537 ( .A0(n2206), .A1(n2080), .B0(n2103), .B1(d_ff3_LUT_out[37]), .Y(n908) ); AO22XLTS U1538 ( .A0(n2104), .A1(n2101), .B0(n2103), .B1(d_ff3_LUT_out[56]), .Y(n890) ); AO22XLTS U1539 ( .A0(d_ff_Yn[46]), .A1(n2186), .B0(d_ff2_Y[46]), .B1(n2218), .Y(n732) ); AO22XLTS U1540 ( .A0(d_ff_Yn[47]), .A1(n2186), .B0(d_ff2_Y[47]), .B1(n2218), .Y(n730) ); AO22XLTS U1541 ( .A0(n2104), .A1(n2077), .B0(n2103), .B1(d_ff3_LUT_out[24]), .Y(n921) ); AO22XLTS U1542 ( .A0(d_ff_Yn[48]), .A1(n2186), .B0(d_ff2_Y[48]), .B1(n2218), .Y(n728) ); AO22XLTS U1543 ( .A0(d_ff_Yn[50]), .A1(n2186), .B0(d_ff2_Y[50]), .B1(n2155), .Y(n724) ); AO22XLTS U1544 ( .A0(d_ff_Yn[49]), .A1(n2186), .B0(d_ff2_Y[49]), .B1(n2218), .Y(n726) ); AO22XLTS U1545 ( .A0(n2204), .A1(n2192), .B0(n2220), .B1(d_ff3_sh_x_out[53]), .Y(n580) ); AO22XLTS U1546 ( .A0(d_ff_Yn[22]), .A1(n2114), .B0(d_ff2_Y[22]), .B1(n2111), .Y(n780) ); AO22XLTS U1547 ( .A0(d_ff_Yn[21]), .A1(n2114), .B0(d_ff2_Y[21]), .B1(n2111), .Y(n782) ); AO22XLTS U1548 ( .A0(d_ff_Yn[23]), .A1(n2172), .B0(d_ff2_Y[23]), .B1(n2111), .Y(n778) ); AO22XLTS U1549 ( .A0(d_ff_Yn[24]), .A1(n2172), .B0(d_ff2_Y[24]), .B1(n2111), .Y(n776) ); AO22XLTS U1550 ( .A0(d_ff_Yn[25]), .A1(n2172), .B0(d_ff2_Y[25]), .B1(n2111), .Y(n774) ); AO22XLTS U1551 ( .A0(n2110), .A1(d_ff2_Y[28]), .B0(n2113), .B1( d_ff3_sh_y_out[28]), .Y(n767) ); AO22XLTS U1552 ( .A0(n2119), .A1(d_ff2_Y[30]), .B0(n2113), .B1( d_ff3_sh_y_out[30]), .Y(n763) ); AO22XLTS U1553 ( .A0(n2115), .A1(d_ff2_Y[31]), .B0(n2113), .B1( d_ff3_sh_y_out[31]), .Y(n761) ); AO22XLTS U1554 ( .A0(n2115), .A1(d_ff2_Y[32]), .B0(n2113), .B1( d_ff3_sh_y_out[32]), .Y(n759) ); AO22XLTS U1555 ( .A0(n2115), .A1(d_ff2_Y[34]), .B0(n2113), .B1( d_ff3_sh_y_out[34]), .Y(n755) ); INVX3TS U1556 ( .A(n2185), .Y(n1739) ); INVX3TS U1557 ( .A(n2131), .Y(n1819) ); NAND3X1TS U1558 ( .A(cont_iter_out[2]), .B(n2076), .C(n1496), .Y(n2071) ); INVX3TS U1559 ( .A(n2131), .Y(n1835) ); INVX3TS U1560 ( .A(n2131), .Y(n1817) ); NOR2X1TS U1561 ( .A(n2089), .B(d_ff3_LUT_out[55]), .Y(n1700) ); AOI222X1TS U1562 ( .A0(d_ff3_LUT_out[3]), .A1(n1873), .B0(n1498), .B1( d_ff3_sh_x_out[3]), .C0(n1894), .C1(d_ff3_sh_y_out[3]), .Y(n1865) ); AO22XLTS U1563 ( .A0(d_ff_Xn[4]), .A1(n2168), .B0(d_ff2_X[4]), .B1(n2155), .Y(n688) ); AO22XLTS U1564 ( .A0(d_ff_Xn[10]), .A1(n2168), .B0(d_ff2_X[10]), .B1(n2155), .Y(n676) ); AO22XLTS U1565 ( .A0(d_ff_Yn[29]), .A1(n2112), .B0(d_ff2_Y[29]), .B1(n2111), .Y(n766) ); AO22XLTS U1566 ( .A0(d_ff_Xn[5]), .A1(n2168), .B0(d_ff2_X[5]), .B1(n2155), .Y(n686) ); AO22XLTS U1567 ( .A0(d_ff_Xn[2]), .A1(n2168), .B0(d_ff2_X[2]), .B1(n2155), .Y(n692) ); AO22XLTS U1568 ( .A0(d_ff_Yn[32]), .A1(n2112), .B0(d_ff2_Y[32]), .B1(n2116), .Y(n760) ); AO22XLTS U1569 ( .A0(d_ff_Xn[44]), .A1(n2168), .B0(d_ff2_X[44]), .B1(n2218), .Y(n608) ); AO22XLTS U1570 ( .A0(d_ff_Yn[27]), .A1(n2112), .B0(d_ff2_Y[27]), .B1(n2111), .Y(n770) ); AO22XLTS U1571 ( .A0(d_ff_Yn[35]), .A1(n2114), .B0(d_ff2_Y[35]), .B1(n2116), .Y(n754) ); AO22XLTS U1572 ( .A0(d_ff_Xn[12]), .A1(n2168), .B0(d_ff2_X[12]), .B1(n2155), .Y(n672) ); AO22XLTS U1573 ( .A0(d_ff_Yn[33]), .A1(n2114), .B0(d_ff2_Y[33]), .B1(n2116), .Y(n758) ); AO22XLTS U1574 ( .A0(d_ff_Yn[31]), .A1(n2112), .B0(d_ff2_Y[31]), .B1(n2116), .Y(n762) ); AO22XLTS U1575 ( .A0(d_ff_Yn[30]), .A1(n2112), .B0(d_ff2_Y[30]), .B1(n2111), .Y(n764) ); AO22XLTS U1576 ( .A0(d_ff_Yn[28]), .A1(n2112), .B0(d_ff2_Y[28]), .B1(n2111), .Y(n768) ); AO22XLTS U1577 ( .A0(d_ff_Yn[26]), .A1(n2112), .B0(d_ff2_Y[26]), .B1(n2111), .Y(n772) ); AO22XLTS U1578 ( .A0(d_ff_Yn[34]), .A1(n2114), .B0(d_ff2_Y[34]), .B1(n2116), .Y(n756) ); AO22X1TS U1579 ( .A0(n2101), .A1(n2231), .B0(n1476), .B1(n1989), .Y(n1900) ); AOI222X1TS U1580 ( .A0(d_ff3_LUT_out[15]), .A1(n1810), .B0(n1498), .B1( d_ff3_sh_x_out[15]), .C0(n1867), .C1(d_ff3_sh_y_out[15]), .Y(n1803) ); INVX2TS U1581 ( .A(n2153), .Y(n2213) ); INVX2TS U1582 ( .A(n2153), .Y(n2076) ); INVX1TS U1583 ( .A(n2082), .Y(n2054) ); INVX3TS U1584 ( .A(n2153), .Y(n2065) ); INVX3TS U1585 ( .A(n2153), .Y(n2089) ); NAND2XLTS U1586 ( .A(sel_mux_2_reg[1]), .B(n2366), .Y(n1545) ); NAND2X1TS U1587 ( .A(n2040), .B(n2188), .Y(n2037) ); CLKBUFX3TS U1588 ( .A(n1950), .Y(n1940) ); BUFX3TS U1589 ( .A(n1560), .Y(n1475) ); INVX3TS U1590 ( .A(n2176), .Y(n2187) ); INVX3TS U1591 ( .A(n1880), .Y(n1776) ); INVX3TS U1592 ( .A(n1880), .Y(n1852) ); NOR2X4TS U1593 ( .A(sel_mux_3_reg), .B(n1605), .Y(n1555) ); OR3X2TS U1594 ( .A(n2225), .B(n2229), .C(n1929), .Y(n2008) ); CLKINVX2TS U1595 ( .A(n1519), .Y(n2211) ); NAND3X2TS U1596 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[3]), .C(n1932), .Y(n1605) ); OAI211X4TS U1597 ( .A0(n2032), .A1(n1682), .B0(n1681), .C0(n1680), .Y(n934) ); INVX2TS U1598 ( .A(n2188), .Y(n2100) ); BUFX3TS U1599 ( .A(n1792), .Y(n1881) ); BUFX3TS U1600 ( .A(n1860), .Y(n1877) ); INVX2TS U1601 ( .A(cordic_FSM_state_reg[2]), .Y(n1486) ); NAND4BXLTS U1602 ( .AN(ack_cordic), .B(n1512), .C(cordic_FSM_state_reg[2]), .D(n2222), .Y(n1934) ); NAND2X1TS U1603 ( .A(n2208), .B(n1485), .Y(n2210) ); NAND2X1TS U1604 ( .A(n2202), .B(n1483), .Y(n2205) ); NAND2X1TS U1605 ( .A(n1481), .B(n2198), .Y(n2200) ); NAND2X1TS U1606 ( .A(n2147), .B(n2146), .Y(n2150) ); AO22XLTS U1607 ( .A0(n2006), .A1(result_add_subt[62]), .B0(n2005), .B1( d_ff_Xn[62]), .Y(n1075) ); AO22XLTS U1608 ( .A0(n2001), .A1(result_add_subt[44]), .B0(n1999), .B1( d_ff_Xn[44]), .Y(n1093) ); AO22XLTS U1609 ( .A0(n1998), .A1(result_add_subt[33]), .B0(n1997), .B1( d_ff_Xn[33]), .Y(n1104) ); AO22XLTS U1610 ( .A0(n1998), .A1(result_add_subt[30]), .B0(n1997), .B1( d_ff_Xn[30]), .Y(n1107) ); AO22XLTS U1611 ( .A0(n1996), .A1(result_add_subt[27]), .B0(n1995), .B1( d_ff_Xn[27]), .Y(n1110) ); AO22XLTS U1612 ( .A0(n1996), .A1(result_add_subt[23]), .B0(n1995), .B1( d_ff_Xn[23]), .Y(n1114) ); AO22XLTS U1613 ( .A0(n1996), .A1(result_add_subt[22]), .B0(n1995), .B1( d_ff_Xn[22]), .Y(n1115) ); AO22XLTS U1614 ( .A0(n1996), .A1(result_add_subt[21]), .B0(n1995), .B1( d_ff_Xn[21]), .Y(n1116) ); AO22XLTS U1615 ( .A0(n1996), .A1(result_add_subt[20]), .B0(n1995), .B1( d_ff_Xn[20]), .Y(n1117) ); AO22XLTS U1616 ( .A0(n1994), .A1(result_add_subt[18]), .B0(n1993), .B1( d_ff_Xn[18]), .Y(n1119) ); AO22XLTS U1617 ( .A0(n1994), .A1(result_add_subt[17]), .B0(n1993), .B1( d_ff_Xn[17]), .Y(n1120) ); AO22XLTS U1618 ( .A0(n1994), .A1(result_add_subt[16]), .B0(n1993), .B1( d_ff_Xn[16]), .Y(n1121) ); AO22XLTS U1619 ( .A0(n1994), .A1(result_add_subt[15]), .B0(n1993), .B1( d_ff_Xn[15]), .Y(n1122) ); AO22XLTS U1620 ( .A0(n1992), .A1(result_add_subt[4]), .B0(n2000), .B1( d_ff_Xn[4]), .Y(n1133) ); AO22XLTS U1621 ( .A0(n1992), .A1(result_add_subt[2]), .B0(n2000), .B1( d_ff_Xn[2]), .Y(n1135) ); AO22XLTS U1622 ( .A0(n1992), .A1(result_add_subt[1]), .B0(n2004), .B1( d_ff_Xn[1]), .Y(n1136) ); AO22XLTS U1623 ( .A0(n2001), .A1(result_add_subt[49]), .B0(n2002), .B1( d_ff_Xn[49]), .Y(n1088) ); AO22XLTS U1624 ( .A0(n2001), .A1(result_add_subt[48]), .B0(n1999), .B1( d_ff_Xn[48]), .Y(n1089) ); AO22XLTS U1625 ( .A0(n2001), .A1(result_add_subt[46]), .B0(n1999), .B1( d_ff_Xn[46]), .Y(n1091) ); AO22XLTS U1626 ( .A0(n2001), .A1(result_add_subt[45]), .B0(n1999), .B1( d_ff_Xn[45]), .Y(n1092) ); AO22XLTS U1627 ( .A0(n2001), .A1(result_add_subt[43]), .B0(n1999), .B1( d_ff_Xn[43]), .Y(n1094) ); AO22XLTS U1628 ( .A0(n2001), .A1(result_add_subt[42]), .B0(n1999), .B1( d_ff_Xn[42]), .Y(n1095) ); AO22XLTS U1629 ( .A0(n2001), .A1(result_add_subt[41]), .B0(n1999), .B1( d_ff_Xn[41]), .Y(n1096) ); AO22XLTS U1630 ( .A0(n1998), .A1(result_add_subt[36]), .B0(n1997), .B1( d_ff_Xn[36]), .Y(n1101) ); AO22XLTS U1631 ( .A0(n1998), .A1(result_add_subt[35]), .B0(n1997), .B1( d_ff_Xn[35]), .Y(n1102) ); AO22XLTS U1632 ( .A0(n1998), .A1(result_add_subt[34]), .B0(n1997), .B1( d_ff_Xn[34]), .Y(n1103) ); AO22XLTS U1633 ( .A0(n1998), .A1(result_add_subt[32]), .B0(n1997), .B1( d_ff_Xn[32]), .Y(n1105) ); AO22XLTS U1634 ( .A0(n1998), .A1(result_add_subt[31]), .B0(n1997), .B1( d_ff_Xn[31]), .Y(n1106) ); AO22XLTS U1635 ( .A0(n1996), .A1(result_add_subt[29]), .B0(n1997), .B1( d_ff_Xn[29]), .Y(n1108) ); AO22XLTS U1636 ( .A0(n1996), .A1(result_add_subt[28]), .B0(n1995), .B1( d_ff_Xn[28]), .Y(n1109) ); AO22XLTS U1637 ( .A0(n1996), .A1(result_add_subt[26]), .B0(n1995), .B1( d_ff_Xn[26]), .Y(n1111) ); AO22XLTS U1638 ( .A0(n1996), .A1(result_add_subt[24]), .B0(n1995), .B1( d_ff_Xn[24]), .Y(n1113) ); AO22XLTS U1639 ( .A0(n1994), .A1(result_add_subt[19]), .B0(n1995), .B1( d_ff_Xn[19]), .Y(n1118) ); AO22XLTS U1640 ( .A0(n1994), .A1(result_add_subt[14]), .B0(n1993), .B1( d_ff_Xn[14]), .Y(n1123) ); AO22XLTS U1641 ( .A0(n1994), .A1(result_add_subt[13]), .B0(n1993), .B1( d_ff_Xn[13]), .Y(n1124) ); AO22XLTS U1642 ( .A0(n1994), .A1(result_add_subt[11]), .B0(n1993), .B1( d_ff_Xn[11]), .Y(n1126) ); AO22XLTS U1643 ( .A0(n1992), .A1(result_add_subt[6]), .B0(n2000), .B1( d_ff_Xn[6]), .Y(n1131) ); AO22XLTS U1644 ( .A0(n1992), .A1(result_add_subt[3]), .B0(n2000), .B1( d_ff_Xn[3]), .Y(n1134) ); AO22XLTS U1645 ( .A0(n1992), .A1(result_add_subt[0]), .B0(n2005), .B1( d_ff_Xn[0]), .Y(n1137) ); AO22XLTS U1646 ( .A0(n2006), .A1(result_add_subt[61]), .B0(n2005), .B1( d_ff_Xn[61]), .Y(n1076) ); AO22XLTS U1647 ( .A0(n2003), .A1(result_add_subt[59]), .B0(n2005), .B1( d_ff_Xn[59]), .Y(n1078) ); AO22XLTS U1648 ( .A0(n2003), .A1(result_add_subt[57]), .B0(n2002), .B1( d_ff_Xn[57]), .Y(n1080) ); AO22XLTS U1649 ( .A0(n2003), .A1(result_add_subt[55]), .B0(n2002), .B1( d_ff_Xn[55]), .Y(n1082) ); AO22XLTS U1650 ( .A0(n1992), .A1(result_add_subt[7]), .B0(n2000), .B1( d_ff_Xn[7]), .Y(n1130) ); AO22XLTS U1651 ( .A0(n1992), .A1(result_add_subt[8]), .B0(n2000), .B1( d_ff_Xn[8]), .Y(n1129) ); AO22XLTS U1652 ( .A0(n1992), .A1(result_add_subt[9]), .B0(n1993), .B1( d_ff_Xn[9]), .Y(n1128) ); AO22XLTS U1653 ( .A0(n1994), .A1(result_add_subt[10]), .B0(n1993), .B1( d_ff_Xn[10]), .Y(n1127) ); AO22XLTS U1654 ( .A0(n2001), .A1(result_add_subt[40]), .B0(n1999), .B1( d_ff_Xn[40]), .Y(n1097) ); AO22XLTS U1655 ( .A0(n2001), .A1(result_add_subt[47]), .B0(n1999), .B1( d_ff_Xn[47]), .Y(n1090) ); AO22XLTS U1656 ( .A0(n2003), .A1(result_add_subt[50]), .B0(n2002), .B1( d_ff_Xn[50]), .Y(n1087) ); AO22XLTS U1657 ( .A0(n2003), .A1(result_add_subt[52]), .B0(n2002), .B1( d_ff_Xn[52]), .Y(n1085) ); AO22XLTS U1658 ( .A0(n2003), .A1(result_add_subt[53]), .B0(n2002), .B1( d_ff_Xn[53]), .Y(n1084) ); AO22XLTS U1659 ( .A0(n2003), .A1(result_add_subt[54]), .B0(n2002), .B1( d_ff_Xn[54]), .Y(n1083) ); AO22XLTS U1660 ( .A0(n2003), .A1(result_add_subt[56]), .B0(n2002), .B1( d_ff_Xn[56]), .Y(n1081) ); AO22XLTS U1661 ( .A0(n2006), .A1(result_add_subt[60]), .B0(n2005), .B1( d_ff_Xn[60]), .Y(n1077) ); AO22XLTS U1662 ( .A0(d_ff2_X[62]), .A1(n2187), .B0(d_ff_Xn[62]), .B1(n2186), .Y(n582) ); AO22XLTS U1663 ( .A0(d_ff_Xn[52]), .A1(n2175), .B0(d_ff2_X[52]), .B1(n2174), .Y(n592) ); CLKINVX3TS U1664 ( .A(n1880), .Y(n1813) ); BUFX3TS U1665 ( .A(n1727), .Y(n1770) ); OR2X2TS U1666 ( .A(n1991), .B(n1990), .Y(n2004) ); AOI32X1TS U1667 ( .A0(n2231), .A1(n2101), .A2(n1482), .B0(n1989), .B1(n1476), .Y(n1991) ); BUFX3TS U1668 ( .A(n2120), .Y(n2170) ); CLKAND2X2TS U1669 ( .A(n2197), .B(d_ff2_X[55]), .Y(n2196) ); INVX2TS U1670 ( .A(d_ff_Yn[62]), .Y(n2132) ); INVX2TS U1671 ( .A(d_ff_Yn[61]), .Y(n2130) ); INVX2TS U1672 ( .A(d_ff_Yn[60]), .Y(n2129) ); INVX2TS U1673 ( .A(d_ff_Yn[59]), .Y(n2128) ); INVX2TS U1674 ( .A(d_ff_Yn[58]), .Y(n2126) ); INVX2TS U1675 ( .A(d_ff_Yn[56]), .Y(n2124) ); INVX2TS U1676 ( .A(d_ff_Yn[55]), .Y(n2123) ); INVX2TS U1677 ( .A(d_ff_Yn[53]), .Y(n2122) ); INVX2TS U1678 ( .A(d_ff_Yn[52]), .Y(n2121) ); INVX2TS U1679 ( .A(n1957), .Y(n1966) ); OAI21XLTS U1680 ( .A0(n1480), .A1(n1860), .B0(n1856), .Y(add_subt_dataA[53]) ); OAI21XLTS U1681 ( .A0(n2232), .A1(n1860), .B0(n1523), .Y(add_subt_dataA[55]) ); OAI21XLTS U1682 ( .A0(n2138), .A1(n1860), .B0(n1859), .Y(add_subt_dataA[56]) ); OAI21XLTS U1683 ( .A0(n2233), .A1(n1877), .B0(n1875), .Y(add_subt_dataA[57]) ); OAI21XLTS U1684 ( .A0(n2127), .A1(n1877), .B0(n1857), .Y(add_subt_dataA[58]) ); OAI21XLTS U1685 ( .A0(n2235), .A1(n1880), .B0(n1879), .Y(add_subt_dataA[59]) ); OAI21XLTS U1686 ( .A0(n2146), .A1(n1877), .B0(n1858), .Y(add_subt_dataA[60]) ); OAI21XLTS U1687 ( .A0(n2236), .A1(n1877), .B0(n1876), .Y(add_subt_dataA[61]) ); AOI222X1TS U1688 ( .A0(d_ff2_Z[63]), .A1(n1873), .B0(d_ff2_Y[63]), .B1(n1497), .C0(d_ff2_X[63]), .C1(n1889), .Y(n1874) ); OAI21XLTS U1689 ( .A0(n1938), .A1(n2078), .B0(n1658), .Y(n1340) ); AOI32X1TS U1690 ( .A0(n1928), .A1(n1927), .A2(n1926), .B0(n2223), .B1(n1927), .Y(n1344) ); NAND4XLTS U1691 ( .A(n1512), .B(n2225), .C(n2101), .D(n1925), .Y(n1926) ); NAND4BXLTS U1692 ( .AN(n1935), .B(n1938), .C(n1934), .D(n1933), .Y(n1343) ); OAI31X1TS U1693 ( .A0(n1932), .A1(n1931), .A2(n2229), .B0(n2223), .Y(n1933) ); NAND3BXLTS U1694 ( .AN(n2085), .B(n2045), .C(n2072), .Y(n930) ); AOI2BB2XLTS U1695 ( .B0(n1485), .B1(n1844), .A0N(d_ff_Xn[60]), .A1N(n2185), .Y(n584) ); AOI2BB2XLTS U1696 ( .B0(n1483), .B1(n2105), .A0N(d_ff_Xn[58]), .A1N(n2181), .Y(n586) ); AO22XLTS U1697 ( .A0(d_ff_Xn[63]), .A1(n2219), .B0(d_ff2_X[63]), .B1(n2218), .Y(n570) ); AO22XLTS U1698 ( .A0(d_ff_Xn[51]), .A1(n2172), .B0(d_ff2_X[51]), .B1(n2174), .Y(n594) ); AO22XLTS U1699 ( .A0(d_ff_Xn[50]), .A1(n2172), .B0(d_ff2_X[50]), .B1(n2174), .Y(n596) ); AO22XLTS U1700 ( .A0(n1996), .A1(result_add_subt[25]), .B0(n1995), .B1( d_ff_Xn[25]), .Y(n1112) ); AO22XLTS U1701 ( .A0(n1994), .A1(result_add_subt[12]), .B0(n1993), .B1( d_ff_Xn[12]), .Y(n1125) ); AO22XLTS U1702 ( .A0(n1992), .A1(result_add_subt[5]), .B0(n2000), .B1( d_ff_Xn[5]), .Y(n1132) ); AO22XLTS U1703 ( .A0(n1952), .A1(d_ff1_shift_region_flag_out[1]), .B0(n1955), .B1(shift_region_flag[1]), .Y(n1334) ); OAI21XLTS U1704 ( .A0(n2246), .A1(n1645), .B0(n1638), .Y(n1059) ); OAI21XLTS U1705 ( .A0(n2247), .A1(n1645), .B0(n1644), .Y(n1057) ); OAI21XLTS U1706 ( .A0(n2248), .A1(n1645), .B0(n1636), .Y(n1055) ); OAI21XLTS U1707 ( .A0(n2278), .A1(n1604), .B0(n1586), .Y(n995) ); AO22XLTS U1708 ( .A0(n1998), .A1(result_add_subt[39]), .B0(n1999), .B1( d_ff_Xn[39]), .Y(n1098) ); AO22XLTS U1709 ( .A0(n1998), .A1(result_add_subt[38]), .B0(n1997), .B1( d_ff_Xn[38]), .Y(n1099) ); OAI21XLTS U1710 ( .A0(n2276), .A1(n1604), .B0(n1583), .Y(n999) ); AO22XLTS U1711 ( .A0(n1998), .A1(result_add_subt[37]), .B0(n1997), .B1( d_ff_Xn[37]), .Y(n1100) ); NAND2BXLTS U1712 ( .AN(d_ff3_LUT_out[48]), .B(n2152), .Y(n897) ); NOR2XLTS U1713 ( .A(n2049), .B(n1571), .Y(n1572) ); AO22XLTS U1714 ( .A0(n2003), .A1(result_add_subt[51]), .B0(n2002), .B1( d_ff_Xn[51]), .Y(n1086) ); AO22XLTS U1715 ( .A0(n2006), .A1(result_add_subt[63]), .B0(n2005), .B1( d_ff_Xn[63]), .Y(n1074) ); AO22XLTS U1716 ( .A0(d_ff_Xn[1]), .A1(n2219), .B0(d_ff2_X[1]), .B1(n2155), .Y(n694) ); AO22XLTS U1717 ( .A0(d_ff_Xn[15]), .A1(n2168), .B0(d_ff2_X[15]), .B1(n2160), .Y(n666) ); AO22XLTS U1718 ( .A0(d_ff_Xn[16]), .A1(n2172), .B0(d_ff2_X[16]), .B1(n2160), .Y(n664) ); AO22XLTS U1719 ( .A0(d_ff_Xn[17]), .A1(n2172), .B0(d_ff2_X[17]), .B1(n2160), .Y(n662) ); AO22XLTS U1720 ( .A0(d_ff_Xn[18]), .A1(n2172), .B0(d_ff2_X[18]), .B1(n2160), .Y(n660) ); AO22XLTS U1721 ( .A0(d_ff_Xn[20]), .A1(n2172), .B0(d_ff2_X[20]), .B1(n2160), .Y(n656) ); AO22XLTS U1722 ( .A0(d_ff_Xn[21]), .A1(n2164), .B0(d_ff2_X[21]), .B1(n2160), .Y(n654) ); AO22XLTS U1723 ( .A0(d_ff_Xn[22]), .A1(n2164), .B0(d_ff2_X[22]), .B1(n2160), .Y(n652) ); AO22XLTS U1724 ( .A0(d_ff_Xn[23]), .A1(n2164), .B0(d_ff2_X[23]), .B1(n2160), .Y(n650) ); AO22XLTS U1725 ( .A0(d_ff_Xn[25]), .A1(n2164), .B0(d_ff2_X[25]), .B1(n2160), .Y(n646) ); AO22XLTS U1726 ( .A0(d_ff_Xn[27]), .A1(n2164), .B0(d_ff2_X[27]), .B1(n2160), .Y(n642) ); AO22XLTS U1727 ( .A0(d_ff_Xn[30]), .A1(n2164), .B0(d_ff2_X[30]), .B1(n2174), .Y(n636) ); AO22XLTS U1728 ( .A0(d_ff_Xn[33]), .A1(n2168), .B0(d_ff2_X[33]), .B1(n2174), .Y(n630) ); AO22XLTS U1729 ( .A0(d_ff_Xn[37]), .A1(n2164), .B0(d_ff2_X[37]), .B1(n2174), .Y(n622) ); AO22XLTS U1730 ( .A0(d_ff_Xn[38]), .A1(n2168), .B0(d_ff2_X[38]), .B1(n2174), .Y(n620) ); AO22XLTS U1731 ( .A0(d_ff_Xn[40]), .A1(n2168), .B0(d_ff2_X[40]), .B1(n2174), .Y(n616) ); AO22XLTS U1732 ( .A0(d_ff_Xn[47]), .A1(n2172), .B0(d_ff2_X[47]), .B1(n2174), .Y(n602) ); AO22XLTS U1733 ( .A0(n2003), .A1(result_add_subt[58]), .B0(n2002), .B1( d_ff_Xn[58]), .Y(n1079) ); AO22XLTS U1734 ( .A0(d_ff_Yn[0]), .A1(n2118), .B0(d_ff2_Y[0]), .B1(n2187), .Y(n824) ); AO22XLTS U1735 ( .A0(d_ff_Yn[1]), .A1(n2175), .B0(d_ff2_Y[1]), .B1(n2105), .Y(n822) ); AO22XLTS U1736 ( .A0(d_ff_Yn[2]), .A1(n2175), .B0(d_ff2_Y[2]), .B1(n1844), .Y(n820) ); AO22XLTS U1737 ( .A0(d_ff_Yn[3]), .A1(n2112), .B0(d_ff2_Y[3]), .B1(n2183), .Y(n818) ); AO22XLTS U1738 ( .A0(d_ff_Yn[4]), .A1(n2112), .B0(d_ff2_Y[4]), .B1(n2105), .Y(n816) ); AO22XLTS U1739 ( .A0(d_ff_Yn[5]), .A1(n2112), .B0(d_ff2_Y[5]), .B1(n1844), .Y(n814) ); AO22XLTS U1740 ( .A0(d_ff_Yn[6]), .A1(n2118), .B0(d_ff2_Y[6]), .B1(n2105), .Y(n812) ); AO22XLTS U1741 ( .A0(d_ff_Yn[7]), .A1(n2118), .B0(d_ff2_Y[7]), .B1(n1844), .Y(n810) ); AO22XLTS U1742 ( .A0(d_ff_Yn[8]), .A1(n2118), .B0(d_ff2_Y[8]), .B1(n2183), .Y(n808) ); AO22XLTS U1743 ( .A0(d_ff_Yn[9]), .A1(n2175), .B0(d_ff2_Y[9]), .B1(n2105), .Y(n806) ); AO22XLTS U1744 ( .A0(d_ff_Yn[10]), .A1(n2175), .B0(d_ff2_Y[10]), .B1(n1844), .Y(n804) ); AO22XLTS U1745 ( .A0(d_ff_Yn[11]), .A1(n2175), .B0(d_ff2_Y[11]), .B1(n1717), .Y(n802) ); AO22XLTS U1746 ( .A0(d_ff_Yn[12]), .A1(n2175), .B0(d_ff2_Y[12]), .B1(n2108), .Y(n800) ); AO22XLTS U1747 ( .A0(d_ff_Yn[13]), .A1(n2175), .B0(d_ff2_Y[13]), .B1(n1833), .Y(n798) ); AO22XLTS U1748 ( .A0(d_ff_Yn[14]), .A1(n2175), .B0(d_ff2_Y[14]), .B1(n1717), .Y(n796) ); AO22XLTS U1749 ( .A0(d_ff_Yn[15]), .A1(n2175), .B0(d_ff2_Y[15]), .B1(n2108), .Y(n794) ); AO22XLTS U1750 ( .A0(d_ff_Yn[16]), .A1(n2114), .B0(d_ff2_Y[16]), .B1(n1833), .Y(n792) ); AO22XLTS U1751 ( .A0(d_ff_Yn[17]), .A1(n2114), .B0(d_ff2_Y[17]), .B1(n1717), .Y(n790) ); AO22XLTS U1752 ( .A0(d_ff_Yn[18]), .A1(n2114), .B0(d_ff2_Y[18]), .B1(n2108), .Y(n788) ); AO22XLTS U1753 ( .A0(d_ff_Yn[19]), .A1(n2114), .B0(d_ff2_Y[19]), .B1(n1833), .Y(n786) ); AO22XLTS U1754 ( .A0(d_ff_Yn[20]), .A1(n2114), .B0(d_ff2_Y[20]), .B1(n1717), .Y(n784) ); AO22XLTS U1755 ( .A0(d_ff_Yn[36]), .A1(n2219), .B0(d_ff2_Y[36]), .B1(n2116), .Y(n752) ); AO22XLTS U1756 ( .A0(d_ff_Yn[37]), .A1(n2219), .B0(d_ff2_Y[37]), .B1(n2116), .Y(n750) ); AO22XLTS U1757 ( .A0(d_ff_Yn[38]), .A1(n2219), .B0(d_ff2_Y[38]), .B1(n2116), .Y(n748) ); AO22XLTS U1758 ( .A0(d_ff_Yn[39]), .A1(n2219), .B0(d_ff2_Y[39]), .B1(n2116), .Y(n746) ); AO22XLTS U1759 ( .A0(d_ff_Yn[40]), .A1(n2219), .B0(d_ff2_Y[40]), .B1(n2116), .Y(n744) ); AO22XLTS U1760 ( .A0(d_ff_Yn[41]), .A1(n2118), .B0(d_ff2_Y[41]), .B1(n2218), .Y(n742) ); AO22XLTS U1761 ( .A0(d_ff_Yn[42]), .A1(n2164), .B0(d_ff2_Y[42]), .B1(n2218), .Y(n740) ); AO22XLTS U1762 ( .A0(d_ff_Yn[43]), .A1(n2164), .B0(d_ff2_Y[43]), .B1(n2174), .Y(n738) ); AO22XLTS U1763 ( .A0(d_ff_Yn[44]), .A1(n2164), .B0(d_ff2_Y[44]), .B1(n2218), .Y(n736) ); AO22XLTS U1764 ( .A0(d_ff_Yn[45]), .A1(n2118), .B0(d_ff2_Y[45]), .B1(n2218), .Y(n734) ); AO22XLTS U1765 ( .A0(d_ff_Yn[51]), .A1(n2219), .B0(d_ff2_Y[51]), .B1(n2155), .Y(n722) ); AO22XLTS U1766 ( .A0(d_ff_Yn[63]), .A1(n2219), .B0(d_ff2_Y[63]), .B1(n2155), .Y(n698) ); AO22XLTS U1767 ( .A0(n1950), .A1(d_ff1_operation_out), .B0(n1955), .B1( operation), .Y(n1336) ); NAND3XLTS U1768 ( .A(n1544), .B(sel_mux_3_reg), .C(n2366), .Y(n1543) ); NAND3XLTS U1769 ( .A(cordic_FSM_state_reg[3]), .B(n1932), .C(n2223), .Y( n1544) ); AO22XLTS U1770 ( .A0(n1944), .A1(d_ff1_shift_region_flag_out[0]), .B0(n1955), .B1(shift_region_flag[0]), .Y(n1335) ); AOI222X1TS U1771 ( .A0(n2183), .A1(d_ff2_Z[63]), .B0(n1736), .B1(d_ff1_Z[63]), .C0(d_ff_Zn[63]), .C1(n1840), .Y(n1822) ); NAND3XLTS U1772 ( .A(n1542), .B(sel_mux_1_reg), .C(n2366), .Y(n1541) ); NAND3XLTS U1773 ( .A(cordic_FSM_state_reg[0]), .B(n1932), .C(n2229), .Y( n1542) ); AO22XLTS U1774 ( .A0(d_ff_Yn[54]), .A1(n2219), .B0(d_ff2_Y[54]), .B1(n2155), .Y(n718) ); AOI2BB2XLTS U1775 ( .B0(n1481), .B1(n2183), .A0N(d_ff_Xn[56]), .A1N(n2185), .Y(n588) ); OAI32X1TS U1776 ( .A0(n1899), .A1(n1476), .A2(n1482), .B0(n1902), .B1(n1545), .Y(n1266) ); AO22XLTS U1777 ( .A0(n2022), .A1(n1537), .B0(n2021), .B1(data_output[63]), .Y(n946) ); AO22XLTS U1778 ( .A0(n2022), .A1(sign_inv_out[62]), .B0(n2021), .B1( data_output[62]), .Y(n948) ); AO22XLTS U1779 ( .A0(n2022), .A1(sign_inv_out[61]), .B0(n2021), .B1( data_output[61]), .Y(n950) ); AO22XLTS U1780 ( .A0(n2022), .A1(sign_inv_out[60]), .B0(n2021), .B1( data_output[60]), .Y(n952) ); AO22XLTS U1781 ( .A0(n2020), .A1(sign_inv_out[59]), .B0(n2021), .B1( data_output[59]), .Y(n954) ); AO22XLTS U1782 ( .A0(n2020), .A1(sign_inv_out[58]), .B0(n2019), .B1( data_output[58]), .Y(n956) ); AO22XLTS U1783 ( .A0(n2020), .A1(sign_inv_out[57]), .B0(n2019), .B1( data_output[57]), .Y(n958) ); AO22XLTS U1784 ( .A0(n2020), .A1(sign_inv_out[56]), .B0(n2019), .B1( data_output[56]), .Y(n960) ); AO22XLTS U1785 ( .A0(n2020), .A1(sign_inv_out[55]), .B0(n2019), .B1( data_output[55]), .Y(n962) ); AO22XLTS U1786 ( .A0(n2020), .A1(sign_inv_out[54]), .B0(n2019), .B1( data_output[54]), .Y(n964) ); AO22XLTS U1787 ( .A0(n2020), .A1(sign_inv_out[53]), .B0(n2019), .B1( data_output[53]), .Y(n966) ); AO22XLTS U1788 ( .A0(n2020), .A1(sign_inv_out[52]), .B0(n2019), .B1( data_output[52]), .Y(n968) ); AO22XLTS U1789 ( .A0(n2020), .A1(sign_inv_out[51]), .B0(n2019), .B1( data_output[51]), .Y(n970) ); AO22XLTS U1790 ( .A0(n2020), .A1(sign_inv_out[50]), .B0(n2019), .B1( data_output[50]), .Y(n972) ); AO22XLTS U1791 ( .A0(n2017), .A1(sign_inv_out[49]), .B0(n2019), .B1( data_output[49]), .Y(n974) ); AO22XLTS U1792 ( .A0(n2017), .A1(sign_inv_out[48]), .B0(n2015), .B1( data_output[48]), .Y(n976) ); AO22XLTS U1793 ( .A0(n2017), .A1(sign_inv_out[47]), .B0(n2015), .B1( data_output[47]), .Y(n978) ); AO22XLTS U1794 ( .A0(n2017), .A1(sign_inv_out[46]), .B0(n2015), .B1( data_output[46]), .Y(n980) ); AO22XLTS U1795 ( .A0(n2017), .A1(sign_inv_out[45]), .B0(n2015), .B1( data_output[45]), .Y(n982) ); AO22XLTS U1796 ( .A0(n2017), .A1(sign_inv_out[44]), .B0(n2015), .B1( data_output[44]), .Y(n984) ); AO22XLTS U1797 ( .A0(n2017), .A1(sign_inv_out[43]), .B0(n2015), .B1( data_output[43]), .Y(n986) ); AO22XLTS U1798 ( .A0(n2017), .A1(sign_inv_out[42]), .B0(n2015), .B1( data_output[42]), .Y(n988) ); AO22XLTS U1799 ( .A0(n2017), .A1(sign_inv_out[41]), .B0(n2015), .B1( data_output[41]), .Y(n990) ); AO22XLTS U1800 ( .A0(n2017), .A1(sign_inv_out[40]), .B0(n2015), .B1( data_output[40]), .Y(n992) ); AO22XLTS U1801 ( .A0(n2014), .A1(sign_inv_out[39]), .B0(n2015), .B1( data_output[39]), .Y(n994) ); AO22XLTS U1802 ( .A0(n2014), .A1(sign_inv_out[38]), .B0(n2013), .B1( data_output[38]), .Y(n996) ); AO22XLTS U1803 ( .A0(n2014), .A1(sign_inv_out[37]), .B0(n2013), .B1( data_output[37]), .Y(n998) ); AO22XLTS U1804 ( .A0(n2014), .A1(sign_inv_out[36]), .B0(n2013), .B1( data_output[36]), .Y(n1000) ); AO22XLTS U1805 ( .A0(n2014), .A1(sign_inv_out[35]), .B0(n2013), .B1( data_output[35]), .Y(n1002) ); AO22XLTS U1806 ( .A0(n2014), .A1(sign_inv_out[34]), .B0(n2013), .B1( data_output[34]), .Y(n1004) ); AO22XLTS U1807 ( .A0(n2014), .A1(sign_inv_out[33]), .B0(n2013), .B1( data_output[33]), .Y(n1006) ); AO22XLTS U1808 ( .A0(n2014), .A1(sign_inv_out[32]), .B0(n2013), .B1( data_output[32]), .Y(n1008) ); AO22XLTS U1809 ( .A0(n2014), .A1(sign_inv_out[31]), .B0(n2013), .B1( data_output[31]), .Y(n1010) ); AO22XLTS U1810 ( .A0(n2014), .A1(sign_inv_out[30]), .B0(n2013), .B1( data_output[30]), .Y(n1012) ); AO22XLTS U1811 ( .A0(n2011), .A1(sign_inv_out[29]), .B0(n2013), .B1( data_output[29]), .Y(n1014) ); AO22XLTS U1812 ( .A0(n2011), .A1(sign_inv_out[28]), .B0(n2012), .B1( data_output[28]), .Y(n1016) ); AO22XLTS U1813 ( .A0(n2011), .A1(sign_inv_out[27]), .B0(n2012), .B1( data_output[27]), .Y(n1018) ); AO22XLTS U1814 ( .A0(n2011), .A1(sign_inv_out[26]), .B0(n2012), .B1( data_output[26]), .Y(n1020) ); AO22XLTS U1815 ( .A0(n2011), .A1(sign_inv_out[25]), .B0(n2012), .B1( data_output[25]), .Y(n1022) ); AO22XLTS U1816 ( .A0(n2011), .A1(sign_inv_out[24]), .B0(n2012), .B1( data_output[24]), .Y(n1024) ); AO22XLTS U1817 ( .A0(n2011), .A1(sign_inv_out[23]), .B0(n2012), .B1( data_output[23]), .Y(n1026) ); AO22XLTS U1818 ( .A0(n2011), .A1(sign_inv_out[22]), .B0(n2010), .B1( data_output[22]), .Y(n1028) ); AO22XLTS U1819 ( .A0(n2011), .A1(sign_inv_out[21]), .B0(n2010), .B1( data_output[21]), .Y(n1030) ); AO22XLTS U1820 ( .A0(n2011), .A1(sign_inv_out[20]), .B0(n2016), .B1( data_output[20]), .Y(n1032) ); AO22XLTS U1821 ( .A0(n2009), .A1(sign_inv_out[19]), .B0(n2016), .B1( data_output[19]), .Y(n1034) ); AO22XLTS U1822 ( .A0(n2009), .A1(sign_inv_out[18]), .B0(n2018), .B1( data_output[18]), .Y(n1036) ); AO22XLTS U1823 ( .A0(n2009), .A1(sign_inv_out[17]), .B0(n2008), .B1( data_output[17]), .Y(n1038) ); AO22XLTS U1824 ( .A0(n2009), .A1(sign_inv_out[16]), .B0(n2021), .B1( data_output[16]), .Y(n1040) ); AO22XLTS U1825 ( .A0(n2009), .A1(sign_inv_out[15]), .B0(n2008), .B1( data_output[15]), .Y(n1042) ); AO22XLTS U1826 ( .A0(n2009), .A1(sign_inv_out[14]), .B0(n2008), .B1( data_output[14]), .Y(n1044) ); AO22XLTS U1827 ( .A0(n2009), .A1(sign_inv_out[13]), .B0(n2008), .B1( data_output[13]), .Y(n1046) ); AO22XLTS U1828 ( .A0(n2009), .A1(sign_inv_out[12]), .B0(n2021), .B1( data_output[12]), .Y(n1048) ); AO22XLTS U1829 ( .A0(n2009), .A1(sign_inv_out[11]), .B0(n2008), .B1( data_output[11]), .Y(n1050) ); AO22XLTS U1830 ( .A0(n2009), .A1(sign_inv_out[10]), .B0(n2008), .B1( data_output[10]), .Y(n1052) ); AO22XLTS U1831 ( .A0(n2007), .A1(sign_inv_out[9]), .B0(n2018), .B1( data_output[9]), .Y(n1054) ); AO22XLTS U1832 ( .A0(n2007), .A1(sign_inv_out[8]), .B0(n2010), .B1( data_output[8]), .Y(n1056) ); AO22XLTS U1833 ( .A0(n2007), .A1(sign_inv_out[7]), .B0(n2010), .B1( data_output[7]), .Y(n1058) ); AO22XLTS U1834 ( .A0(n2007), .A1(sign_inv_out[6]), .B0(n2010), .B1( data_output[6]), .Y(n1060) ); AO22XLTS U1835 ( .A0(n2007), .A1(sign_inv_out[5]), .B0(n2010), .B1( data_output[5]), .Y(n1062) ); AO22XLTS U1836 ( .A0(n2007), .A1(sign_inv_out[4]), .B0(n2010), .B1( data_output[4]), .Y(n1064) ); AO22XLTS U1837 ( .A0(n2007), .A1(sign_inv_out[3]), .B0(n2010), .B1( data_output[3]), .Y(n1066) ); AO22XLTS U1838 ( .A0(n2007), .A1(sign_inv_out[2]), .B0(n2010), .B1( data_output[2]), .Y(n1068) ); AO22XLTS U1839 ( .A0(n2007), .A1(sign_inv_out[1]), .B0(n2012), .B1( data_output[1]), .Y(n1070) ); AO22XLTS U1840 ( .A0(n2007), .A1(sign_inv_out[0]), .B0(n2018), .B1( data_output[0]), .Y(n1072) ); NAND3XLTS U1841 ( .A(n1533), .B(n2091), .C(n1575), .Y( cordic_FSM_state_next_1_) ); NOR3XLTS U1842 ( .A(n2213), .B(n1908), .C(n1576), .Y(n1337) ); AOI31XLTS U1843 ( .A0(ack_add_subt), .A1(n2101), .A2(n1482), .B0( cont_var_out[0]), .Y(n1576) ); AO22XLTS U1844 ( .A0(n2221), .A1(d_ff2_X[63]), .B0(n2220), .B1( d_ff3_sh_x_out[63]), .Y(n569) ); AO22XLTS U1845 ( .A0(n2204), .A1(d_ff2_X[51]), .B0(n2173), .B1( d_ff3_sh_x_out[51]), .Y(n593) ); AO22XLTS U1846 ( .A0(n2204), .A1(d_ff2_X[50]), .B0(n2173), .B1( d_ff3_sh_x_out[50]), .Y(n595) ); AO22XLTS U1847 ( .A0(n2204), .A1(d_ff2_X[49]), .B0(n2173), .B1( d_ff3_sh_x_out[49]), .Y(n597) ); AO22XLTS U1848 ( .A0(n2204), .A1(d_ff2_X[48]), .B0(n2173), .B1( d_ff3_sh_x_out[48]), .Y(n599) ); AO22XLTS U1849 ( .A0(n2204), .A1(d_ff2_X[47]), .B0(n2173), .B1( d_ff3_sh_x_out[47]), .Y(n601) ); AO22XLTS U1850 ( .A0(n2204), .A1(d_ff2_X[46]), .B0(n2173), .B1( d_ff3_sh_x_out[46]), .Y(n603) ); AO22XLTS U1851 ( .A0(n2169), .A1(d_ff2_X[45]), .B0(n2173), .B1( d_ff3_sh_x_out[45]), .Y(n605) ); AO22XLTS U1852 ( .A0(n2169), .A1(d_ff2_X[44]), .B0(n2173), .B1( d_ff3_sh_x_out[44]), .Y(n607) ); AO22XLTS U1853 ( .A0(n2169), .A1(d_ff2_X[43]), .B0(n2173), .B1( d_ff3_sh_x_out[43]), .Y(n609) ); AO22XLTS U1854 ( .A0(n2169), .A1(d_ff2_X[42]), .B0(n2173), .B1( d_ff3_sh_x_out[42]), .Y(n611) ); AO22XLTS U1855 ( .A0(n2169), .A1(d_ff2_X[41]), .B0(n2165), .B1( d_ff3_sh_x_out[41]), .Y(n613) ); AO22XLTS U1856 ( .A0(n2169), .A1(d_ff2_X[40]), .B0(n2165), .B1( d_ff3_sh_x_out[40]), .Y(n615) ); AO22XLTS U1857 ( .A0(n2169), .A1(d_ff2_X[39]), .B0(n2165), .B1( d_ff3_sh_x_out[39]), .Y(n617) ); AO22XLTS U1858 ( .A0(n2169), .A1(d_ff2_X[38]), .B0(n2165), .B1( d_ff3_sh_x_out[38]), .Y(n619) ); AO22XLTS U1859 ( .A0(n2169), .A1(d_ff2_X[37]), .B0(n2165), .B1( d_ff3_sh_x_out[37]), .Y(n621) ); AO22XLTS U1860 ( .A0(n2169), .A1(d_ff2_X[36]), .B0(n2165), .B1( d_ff3_sh_x_out[36]), .Y(n623) ); AO22XLTS U1861 ( .A0(n2162), .A1(d_ff2_X[35]), .B0(n2165), .B1( d_ff3_sh_x_out[35]), .Y(n625) ); AO22XLTS U1862 ( .A0(n2162), .A1(d_ff2_X[34]), .B0(n2165), .B1( d_ff3_sh_x_out[34]), .Y(n627) ); AO22XLTS U1863 ( .A0(n2162), .A1(d_ff2_X[33]), .B0(n2165), .B1( d_ff3_sh_x_out[33]), .Y(n629) ); AO22XLTS U1864 ( .A0(n2162), .A1(d_ff2_X[32]), .B0(n2165), .B1( d_ff3_sh_x_out[32]), .Y(n631) ); AO22XLTS U1865 ( .A0(n2162), .A1(d_ff2_X[31]), .B0(n2161), .B1( d_ff3_sh_x_out[31]), .Y(n633) ); AO22XLTS U1866 ( .A0(n2162), .A1(d_ff2_X[30]), .B0(n2161), .B1( d_ff3_sh_x_out[30]), .Y(n635) ); AO22XLTS U1867 ( .A0(n2162), .A1(d_ff2_X[29]), .B0(n2161), .B1( d_ff3_sh_x_out[29]), .Y(n637) ); AO22XLTS U1868 ( .A0(n2162), .A1(d_ff2_X[28]), .B0(n2161), .B1( d_ff3_sh_x_out[28]), .Y(n639) ); AO22XLTS U1869 ( .A0(n2162), .A1(d_ff2_X[27]), .B0(n2161), .B1( d_ff3_sh_x_out[27]), .Y(n641) ); AO22XLTS U1870 ( .A0(n2162), .A1(d_ff2_X[26]), .B0(n2161), .B1( d_ff3_sh_x_out[26]), .Y(n643) ); AO22XLTS U1871 ( .A0(n2159), .A1(d_ff2_X[25]), .B0(n2161), .B1( d_ff3_sh_x_out[25]), .Y(n645) ); AO22XLTS U1872 ( .A0(n2159), .A1(d_ff2_X[24]), .B0(n2161), .B1( d_ff3_sh_x_out[24]), .Y(n647) ); AO22XLTS U1873 ( .A0(n2159), .A1(d_ff2_X[23]), .B0(n2161), .B1( d_ff3_sh_x_out[23]), .Y(n649) ); AO22XLTS U1874 ( .A0(n2159), .A1(d_ff2_X[22]), .B0(n2215), .B1( d_ff3_sh_x_out[22]), .Y(n651) ); AO22XLTS U1875 ( .A0(n2159), .A1(d_ff2_X[21]), .B0(n2215), .B1( d_ff3_sh_x_out[21]), .Y(n653) ); AO22XLTS U1876 ( .A0(n2159), .A1(d_ff2_X[20]), .B0(n2215), .B1( d_ff3_sh_x_out[20]), .Y(n655) ); AO22XLTS U1877 ( .A0(n2159), .A1(d_ff2_X[19]), .B0(n2158), .B1( d_ff3_sh_x_out[19]), .Y(n657) ); AO22XLTS U1878 ( .A0(n2159), .A1(d_ff2_X[18]), .B0(n2215), .B1( d_ff3_sh_x_out[18]), .Y(n659) ); AO22XLTS U1879 ( .A0(n2159), .A1(d_ff2_X[17]), .B0(n2215), .B1( d_ff3_sh_x_out[17]), .Y(n661) ); AO22XLTS U1880 ( .A0(n2157), .A1(d_ff2_X[16]), .B0(n2215), .B1( d_ff3_sh_x_out[16]), .Y(n663) ); AO22XLTS U1881 ( .A0(n2157), .A1(d_ff2_X[15]), .B0(n2171), .B1( d_ff3_sh_x_out[15]), .Y(n665) ); AO22XLTS U1882 ( .A0(n2157), .A1(d_ff2_X[14]), .B0(n2158), .B1( d_ff3_sh_x_out[14]), .Y(n667) ); AO22XLTS U1883 ( .A0(n2157), .A1(d_ff2_X[13]), .B0(n2158), .B1( d_ff3_sh_x_out[13]), .Y(n669) ); AO22XLTS U1884 ( .A0(n2159), .A1(d_ff2_X[12]), .B0(n2156), .B1( d_ff3_sh_x_out[12]), .Y(n671) ); AO22XLTS U1885 ( .A0(n2157), .A1(d_ff2_X[11]), .B0(n2154), .B1( d_ff3_sh_x_out[11]), .Y(n673) ); AO22XLTS U1886 ( .A0(n2157), .A1(d_ff2_X[10]), .B0(n2156), .B1( d_ff3_sh_x_out[10]), .Y(n675) ); AO22XLTS U1887 ( .A0(n2157), .A1(d_ff2_X[9]), .B0(n2154), .B1( d_ff3_sh_x_out[9]), .Y(n677) ); AO22XLTS U1888 ( .A0(n2157), .A1(d_ff2_X[8]), .B0(n2154), .B1( d_ff3_sh_x_out[8]), .Y(n679) ); AO22XLTS U1889 ( .A0(n2157), .A1(d_ff2_X[7]), .B0(n2153), .B1( d_ff3_sh_x_out[7]), .Y(n681) ); AO22XLTS U1890 ( .A0(n2157), .A1(d_ff2_X[6]), .B0(n2153), .B1( d_ff3_sh_x_out[6]), .Y(n683) ); AO22XLTS U1891 ( .A0(n2217), .A1(d_ff2_X[5]), .B0(n2152), .B1( d_ff3_sh_x_out[5]), .Y(n685) ); AO22XLTS U1892 ( .A0(n2217), .A1(d_ff2_X[4]), .B0(n2152), .B1( d_ff3_sh_x_out[4]), .Y(n687) ); AO22XLTS U1893 ( .A0(n2217), .A1(d_ff2_X[3]), .B0(n2154), .B1( d_ff3_sh_x_out[3]), .Y(n689) ); AO22XLTS U1894 ( .A0(n2217), .A1(d_ff2_X[2]), .B0(n2152), .B1( d_ff3_sh_x_out[2]), .Y(n691) ); AO22XLTS U1895 ( .A0(n2217), .A1(d_ff2_X[1]), .B0(n2152), .B1( d_ff3_sh_x_out[1]), .Y(n693) ); AO22XLTS U1896 ( .A0(n2217), .A1(d_ff2_X[0]), .B0(n2152), .B1( d_ff3_sh_x_out[0]), .Y(n695) ); AO22XLTS U1897 ( .A0(n2217), .A1(d_ff2_Y[63]), .B0(n2156), .B1( d_ff3_sh_y_out[63]), .Y(n697) ); AO22XLTS U1898 ( .A0(n2221), .A1(d_ff2_Y[51]), .B0(n2171), .B1( d_ff3_sh_y_out[51]), .Y(n721) ); AO22XLTS U1899 ( .A0(n2221), .A1(d_ff2_Y[50]), .B0(n1519), .B1( d_ff3_sh_y_out[50]), .Y(n723) ); AO22XLTS U1900 ( .A0(n2119), .A1(d_ff2_Y[49]), .B0(n2161), .B1( d_ff3_sh_y_out[49]), .Y(n725) ); AO22XLTS U1901 ( .A0(n2119), .A1(d_ff2_Y[48]), .B0(n2220), .B1( d_ff3_sh_y_out[48]), .Y(n727) ); AO22XLTS U1902 ( .A0(n2119), .A1(d_ff2_Y[47]), .B0(n2220), .B1( d_ff3_sh_y_out[47]), .Y(n729) ); AO22XLTS U1903 ( .A0(n2119), .A1(d_ff2_Y[46]), .B0(n2220), .B1( d_ff3_sh_y_out[46]), .Y(n731) ); AO22XLTS U1904 ( .A0(n2119), .A1(d_ff2_Y[45]), .B0(n2220), .B1( d_ff3_sh_y_out[45]), .Y(n733) ); AO22XLTS U1905 ( .A0(n2221), .A1(d_ff2_Y[44]), .B0(n2117), .B1( d_ff3_sh_y_out[44]), .Y(n735) ); AO22XLTS U1906 ( .A0(n2119), .A1(d_ff2_Y[43]), .B0(n2117), .B1( d_ff3_sh_y_out[43]), .Y(n737) ); AO22XLTS U1907 ( .A0(n2119), .A1(d_ff2_Y[41]), .B0(n2117), .B1( d_ff3_sh_y_out[41]), .Y(n741) ); AO22XLTS U1908 ( .A0(n2115), .A1(d_ff2_Y[39]), .B0(n2117), .B1( d_ff3_sh_y_out[39]), .Y(n745) ); AO22XLTS U1909 ( .A0(n2115), .A1(d_ff2_Y[33]), .B0(n2113), .B1( d_ff3_sh_y_out[33]), .Y(n757) ); AO22XLTS U1910 ( .A0(n2110), .A1(d_ff2_Y[29]), .B0(n2113), .B1( d_ff3_sh_y_out[29]), .Y(n765) ); AO22XLTS U1911 ( .A0(n2110), .A1(d_ff2_Y[27]), .B0(n2113), .B1( d_ff3_sh_y_out[27]), .Y(n769) ); AO22XLTS U1912 ( .A0(n2110), .A1(d_ff2_Y[26]), .B0(n2113), .B1( d_ff3_sh_y_out[26]), .Y(n771) ); AO22XLTS U1913 ( .A0(n2110), .A1(d_ff2_Y[25]), .B0(n2113), .B1( d_ff3_sh_y_out[25]), .Y(n773) ); AO22XLTS U1914 ( .A0(n2107), .A1(d_ff2_Y[19]), .B0(n2109), .B1( d_ff3_sh_y_out[19]), .Y(n785) ); AO22XLTS U1915 ( .A0(n2107), .A1(d_ff2_Y[15]), .B0(n2109), .B1( d_ff3_sh_y_out[15]), .Y(n793) ); AO22XLTS U1916 ( .A0(n2107), .A1(d_ff2_Y[14]), .B0(n1519), .B1( d_ff3_sh_y_out[14]), .Y(n795) ); AO22XLTS U1917 ( .A0(n2107), .A1(d_ff2_Y[13]), .B0(n1519), .B1( d_ff3_sh_y_out[13]), .Y(n797) ); AO22XLTS U1918 ( .A0(n2107), .A1(d_ff2_Y[12]), .B0(n1519), .B1( d_ff3_sh_y_out[12]), .Y(n799) ); AO22XLTS U1919 ( .A0(n2107), .A1(d_ff2_Y[11]), .B0(n1519), .B1( d_ff3_sh_y_out[11]), .Y(n801) ); AO22XLTS U1920 ( .A0(n2107), .A1(d_ff2_Y[10]), .B0(n1519), .B1( d_ff3_sh_y_out[10]), .Y(n803) ); AO22XLTS U1921 ( .A0(n2104), .A1(d_ff2_Y[9]), .B0(n2156), .B1( d_ff3_sh_y_out[9]), .Y(n805) ); AO22XLTS U1922 ( .A0(n2107), .A1(d_ff2_Y[8]), .B0(n2044), .B1( d_ff3_sh_y_out[8]), .Y(n807) ); AO22XLTS U1923 ( .A0(n2104), .A1(d_ff2_Y[7]), .B0(n2171), .B1( d_ff3_sh_y_out[7]), .Y(n809) ); AO22XLTS U1924 ( .A0(n2107), .A1(d_ff2_Y[6]), .B0(n2167), .B1( d_ff3_sh_y_out[6]), .Y(n811) ); AO22XLTS U1925 ( .A0(n2104), .A1(d_ff2_Y[5]), .B0(n2163), .B1( d_ff3_sh_y_out[5]), .Y(n813) ); AO22XLTS U1926 ( .A0(n2104), .A1(d_ff2_Y[3]), .B0(n2103), .B1( d_ff3_sh_y_out[3]), .Y(n817) ); AO22XLTS U1927 ( .A0(n2104), .A1(d_ff2_Y[1]), .B0(n2103), .B1( d_ff3_sh_y_out[1]), .Y(n821) ); AO22XLTS U1928 ( .A0(n2104), .A1(d_ff2_Y[0]), .B0(n2103), .B1( d_ff3_sh_y_out[0]), .Y(n823) ); AO22XLTS U1929 ( .A0(n1519), .A1(d_ff3_sign_out), .B0(n2206), .B1( d_ff2_Z[63]), .Y(n825) ); AO22XLTS U1930 ( .A0(n2217), .A1(n2216), .B0(n2215), .B1(d_ff3_sh_x_out[62]), .Y(n571) ); AOI2BB2XLTS U1931 ( .B0(n2213), .B1(n2212), .A0N(d_ff3_sh_x_out[61]), .A1N( n2211), .Y(n572) ); AO22XLTS U1932 ( .A0(n2221), .A1(n2209), .B0(n2220), .B1(d_ff3_sh_x_out[60]), .Y(n573) ); OAI21XLTS U1933 ( .A0(n2208), .A1(n1485), .B0(n2210), .Y(n2209) ); AOI2BB2XLTS U1934 ( .B0(n2213), .B1(n2207), .A0N(d_ff3_sh_x_out[59]), .A1N( n2206), .Y(n574) ); AO22XLTS U1935 ( .A0(n2204), .A1(n2203), .B0(n2220), .B1(d_ff3_sh_x_out[58]), .Y(n575) ); OAI21XLTS U1936 ( .A0(n2202), .A1(n1483), .B0(n2205), .Y(n2203) ); AOI2BB2XLTS U1937 ( .B0(n2076), .B1(n2201), .A0N(d_ff3_sh_x_out[57]), .A1N( n2206), .Y(n576) ); AO22XLTS U1938 ( .A0(n2204), .A1(n2194), .B0(n2220), .B1(d_ff3_sh_x_out[54]), .Y(n579) ); AOI2BB2XLTS U1939 ( .B0(n2076), .B1(n2189), .A0N(d_ff3_sh_x_out[52]), .A1N( n2206), .Y(n581) ); AO22X1TS U1940 ( .A0(n2217), .A1(n1521), .B0(n2153), .B1(d_ff3_sh_y_out[62]), .Y(n699) ); AOI2BB2XLTS U1941 ( .B0(n2076), .B1(n2151), .A0N(d_ff3_sh_y_out[61]), .A1N( n2206), .Y(n700) ); AO22XLTS U1942 ( .A0(n2217), .A1(n2148), .B0(n2156), .B1(d_ff3_sh_y_out[60]), .Y(n701) ); OAI21XLTS U1943 ( .A0(n2147), .A1(n2146), .B0(n2150), .Y(n2148) ); AOI2BB2XLTS U1944 ( .B0(n2089), .B1(n2145), .A0N(d_ff3_sh_y_out[59]), .A1N( n2206), .Y(n702) ); AO22XLTS U1945 ( .A0(n2221), .A1(n1539), .B0(n2152), .B1(d_ff3_sh_y_out[58]), .Y(n703) ); OAI21XLTS U1946 ( .A0(n2141), .A1(n2127), .B0(n2144), .Y(n1539) ); AOI2BB2XLTS U1947 ( .B0(n2213), .B1(n2143), .A0N(d_ff3_sh_y_out[57]), .A1N( n2206), .Y(n704) ); OAI21XLTS U1948 ( .A0(n2139), .A1(n2138), .B0(n2142), .Y(n2140) ); OAI21XLTS U1949 ( .A0(n1682), .A1(n1552), .B0(n1551), .Y(n706) ); AO22XLTS U1950 ( .A0(n2221), .A1(n1535), .B0(n2153), .B1(d_ff3_sh_y_out[54]), .Y(n707) ); AO22XLTS U1951 ( .A0(n2221), .A1(n2137), .B0(n1519), .B1(d_ff3_sh_y_out[53]), .Y(n708) ); AOI2BB2XLTS U1952 ( .B0(n2089), .B1(n2134), .A0N(d_ff3_sh_y_out[52]), .A1N( n2206), .Y(n709) ); AOI31XLTS U1953 ( .A0(n2052), .A1(n2101), .A2(n2037), .B0(n1700), .Y(n891) ); OAI21XLTS U1954 ( .A0(n2087), .A1(n2036), .B0(n1554), .Y(n892) ); OAI32X1TS U1955 ( .A0(n2044), .A1(n2064), .A2(n1699), .B0(n2089), .B1(n2293), .Y(n893) ); AO22XLTS U1956 ( .A0(n2206), .A1(cont_iter_out[0]), .B0(n2103), .B1( d_ff3_LUT_out[52]), .Y(n894) ); AO21XLTS U1957 ( .A0(d_ff3_LUT_out[49]), .A1(n2103), .B0(n2096), .Y(n896) ); AO21XLTS U1958 ( .A0(d_ff3_LUT_out[47]), .A1(n2095), .B0(n2094), .Y(n898) ); AO21XLTS U1959 ( .A0(d_ff3_LUT_out[46]), .A1(n2095), .B0(n2096), .Y(n899) ); AO21XLTS U1960 ( .A0(d_ff3_LUT_out[44]), .A1(n2095), .B0(n2096), .Y(n901) ); AO21XLTS U1961 ( .A0(d_ff3_LUT_out[43]), .A1(n2095), .B0(n2092), .Y(n902) ); AO21XLTS U1962 ( .A0(d_ff3_LUT_out[42]), .A1(n2095), .B0(n2094), .Y(n903) ); NAND2BXLTS U1963 ( .AN(n2085), .B(n2084), .Y(n906) ); AO21XLTS U1964 ( .A0(d_ff3_LUT_out[34]), .A1(n2095), .B0(n2092), .Y(n911) ); AOI2BB2XLTS U1965 ( .B0(n2075), .B1(n2088), .A0N(n2097), .A1N( d_ff3_LUT_out[31]), .Y(n914) ); AO21XLTS U1966 ( .A0(d_ff3_LUT_out[30]), .A1(n2095), .B0(n2074), .Y(n915) ); NAND4XLTS U1967 ( .A(n2073), .B(n2072), .C(n2071), .D(n2070), .Y(n916) ); NAND4XLTS U1968 ( .A(n2069), .B(n2072), .C(n2068), .D(n2067), .Y(n918) ); NAND3XLTS U1969 ( .A(n2068), .B(n2062), .C(n2061), .Y(n920) ); AOI2BB2XLTS U1970 ( .B0(n2058), .B1(n2057), .A0N(n2097), .A1N( d_ff3_LUT_out[23]), .Y(n922) ); AOI2BB2XLTS U1971 ( .B0(n2052), .B1(n2057), .A0N(n2097), .A1N( d_ff3_LUT_out[21]), .Y(n924) ); AOI2BB2XLTS U1972 ( .B0(n2089), .B1(n2090), .A0N(d_ff3_LUT_out[20]), .A1N( n2211), .Y(n925) ); AO21XLTS U1973 ( .A0(d_ff3_LUT_out[16]), .A1(n2095), .B0(n2046), .Y(n929) ); OAI211XLTS U1974 ( .A0(n1682), .A1(n1496), .B0(n2071), .C0(n1562), .Y(n931) ); AOI2BB2XLTS U1975 ( .B0(n2041), .B1(n2096), .A0N(n2097), .A1N( d_ff3_LUT_out[13]), .Y(n932) ); AOI211XLTS U1976 ( .A0(d_ff3_LUT_out[11]), .A1(n2087), .B0(n2085), .C0(n2035), .Y(n1681) ); AOI2BB2XLTS U1977 ( .B0(n2075), .B1(n2037), .A0N(n2097), .A1N( d_ff3_LUT_out[10]), .Y(n935) ); NAND4BXLTS U1978 ( .AN(n2035), .B(n2047), .C(n2034), .D(n2033), .Y(n936) ); NAND3XLTS U1979 ( .A(n2089), .B(n2064), .C(n2195), .Y(n2034) ); NAND3XLTS U1980 ( .A(n2073), .B(n2072), .C(n2030), .Y(n939) ); AO21XLTS U1981 ( .A0(d_ff3_LUT_out[4]), .A1(n2095), .B0(n2074), .Y(n941) ); AO21XLTS U1982 ( .A0(d_ff3_LUT_out[2]), .A1(n2095), .B0(n2026), .Y(n943) ); AOI31XLTS U1983 ( .A0(n2195), .A1(n1490), .A2(n2025), .B0(n2091), .Y(n2026) ); OAI211XLTS U1984 ( .A0(n2073), .A1(n2078), .B0(n2047), .C0(n1570), .Y(n944) ); NAND3XLTS U1985 ( .A(n2024), .B(n2068), .C(n2023), .Y(n945) ); OAI21XLTS U1986 ( .A0(n2132), .A1(n1475), .B0(n1561), .Y(n949) ); OAI21XLTS U1987 ( .A0(n2130), .A1(n1560), .B0(n1557), .Y(n951) ); OAI21XLTS U1988 ( .A0(n2129), .A1(n1475), .B0(n1559), .Y(n953) ); OAI21XLTS U1989 ( .A0(n2128), .A1(n1657), .B0(n1653), .Y(n955) ); OAI21XLTS U1990 ( .A0(n2125), .A1(n1657), .B0(n1649), .Y(n959) ); OAI21XLTS U1991 ( .A0(n2124), .A1(n1657), .B0(n1651), .Y(n961) ); OAI21XLTS U1992 ( .A0(n2123), .A1(n1657), .B0(n1648), .Y(n963) ); OAI21XLTS U1993 ( .A0(n2291), .A1(n1657), .B0(n1646), .Y(n965) ); OAI21XLTS U1994 ( .A0(n2122), .A1(n1657), .B0(n1656), .Y(n967) ); OAI21XLTS U1995 ( .A0(n2121), .A1(n1657), .B0(n1647), .Y(n969) ); OAI21XLTS U1996 ( .A0(n2289), .A1(n1657), .B0(n1633), .Y(n973) ); OAI21XLTS U1997 ( .A0(n2288), .A1(n1599), .B0(n1580), .Y(n975) ); OAI21XLTS U1998 ( .A0(n2287), .A1(n1599), .B0(n1590), .Y(n977) ); OAI21XLTS U1999 ( .A0(n2286), .A1(n1599), .B0(n1578), .Y(n979) ); OAI21XLTS U2000 ( .A0(n2285), .A1(n1599), .B0(n1589), .Y(n981) ); OAI21XLTS U2001 ( .A0(n2284), .A1(n1599), .B0(n1584), .Y(n983) ); OAI21XLTS U2002 ( .A0(n2283), .A1(n1599), .B0(n1581), .Y(n985) ); OAI21XLTS U2003 ( .A0(n2282), .A1(n1599), .B0(n1592), .Y(n987) ); OAI21XLTS U2004 ( .A0(n2281), .A1(n1599), .B0(n1595), .Y(n989) ); OAI21XLTS U2005 ( .A0(n2280), .A1(n1599), .B0(n1579), .Y(n991) ); OAI21XLTS U2006 ( .A0(n2279), .A1(n1599), .B0(n1598), .Y(n993) ); OAI21XLTS U2007 ( .A0(n2275), .A1(n1604), .B0(n1593), .Y(n1001) ); OAI21XLTS U2008 ( .A0(n2274), .A1(n1604), .B0(n1582), .Y(n1003) ); OAI21XLTS U2009 ( .A0(n2273), .A1(n1604), .B0(n1603), .Y(n1005) ); OAI21XLTS U2010 ( .A0(n2272), .A1(n1604), .B0(n1600), .Y(n1007) ); OAI21XLTS U2011 ( .A0(n2271), .A1(n1604), .B0(n1587), .Y(n1009) ); OAI21XLTS U2012 ( .A0(n2270), .A1(n1604), .B0(n1588), .Y(n1011) ); OAI21XLTS U2013 ( .A0(n2269), .A1(n1604), .B0(n1591), .Y(n1013) ); OAI21XLTS U2014 ( .A0(n2268), .A1(n1624), .B0(n1594), .Y(n1015) ); OAI21XLTS U2015 ( .A0(n2267), .A1(n1624), .B0(n1596), .Y(n1017) ); OAI21XLTS U2016 ( .A0(n2266), .A1(n1624), .B0(n1608), .Y(n1019) ); OAI21XLTS U2017 ( .A0(n2265), .A1(n1624), .B0(n1613), .Y(n1021) ); OAI21XLTS U2018 ( .A0(n2263), .A1(n1624), .B0(n1620), .Y(n1025) ); OAI21XLTS U2019 ( .A0(n2262), .A1(n1624), .B0(n1609), .Y(n1027) ); OAI21XLTS U2020 ( .A0(n2261), .A1(n1624), .B0(n1623), .Y(n1029) ); OAI21XLTS U2021 ( .A0(n2260), .A1(n1624), .B0(n1606), .Y(n1031) ); OAI21XLTS U2022 ( .A0(n2259), .A1(n1624), .B0(n1610), .Y(n1033) ); OAI21XLTS U2023 ( .A0(n2258), .A1(n1629), .B0(n1607), .Y(n1035) ); OAI21XLTS U2024 ( .A0(n2257), .A1(n1629), .B0(n1628), .Y(n1037) ); OAI21XLTS U2025 ( .A0(n2256), .A1(n1629), .B0(n1612), .Y(n1039) ); OAI21XLTS U2026 ( .A0(n2255), .A1(n1629), .B0(n1625), .Y(n1041) ); OAI21XLTS U2027 ( .A0(n2254), .A1(n1629), .B0(n1614), .Y(n1043) ); OAI21XLTS U2028 ( .A0(n2253), .A1(n1629), .B0(n1615), .Y(n1045) ); OAI21XLTS U2029 ( .A0(n2252), .A1(n1629), .B0(n1617), .Y(n1047) ); OAI21XLTS U2030 ( .A0(n2250), .A1(n1629), .B0(n1611), .Y(n1051) ); OAI21XLTS U2031 ( .A0(n2249), .A1(n1629), .B0(n1621), .Y(n1053) ); OAI21XLTS U2032 ( .A0(n2245), .A1(n1645), .B0(n1639), .Y(n1061) ); OAI21XLTS U2033 ( .A0(n2243), .A1(n1645), .B0(n1634), .Y(n1065) ); OAI21XLTS U2034 ( .A0(n2242), .A1(n1645), .B0(n1641), .Y(n1067) ); OAI21XLTS U2035 ( .A0(n2241), .A1(n1645), .B0(n1632), .Y(n1069) ); OAI21XLTS U2036 ( .A0(n2240), .A1(n1645), .B0(n1630), .Y(n1071) ); OAI21XLTS U2037 ( .A0(n2239), .A1(n1645), .B0(n1637), .Y(n1073) ); AO22XLTS U2038 ( .A0(n1973), .A1(result_add_subt[63]), .B0(n1972), .B1( d_ff_Zn[63]), .Y(n1202) ); AO22XLTS U2039 ( .A0(n1973), .A1(result_add_subt[62]), .B0(n1972), .B1( d_ff_Zn[62]), .Y(n1203) ); AO22XLTS U2040 ( .A0(n1973), .A1(result_add_subt[61]), .B0(n1972), .B1( d_ff_Zn[61]), .Y(n1204) ); AO22XLTS U2041 ( .A0(n1973), .A1(result_add_subt[60]), .B0(n1972), .B1( d_ff_Zn[60]), .Y(n1205) ); AO22XLTS U2042 ( .A0(n1970), .A1(result_add_subt[59]), .B0(n1972), .B1( d_ff_Zn[59]), .Y(n1206) ); AO22XLTS U2043 ( .A0(n1970), .A1(result_add_subt[58]), .B0(n1969), .B1( d_ff_Zn[58]), .Y(n1207) ); AO22XLTS U2044 ( .A0(n1970), .A1(result_add_subt[57]), .B0(n1969), .B1( d_ff_Zn[57]), .Y(n1208) ); AO22XLTS U2045 ( .A0(n1970), .A1(result_add_subt[56]), .B0(n1969), .B1( d_ff_Zn[56]), .Y(n1209) ); AO22XLTS U2046 ( .A0(n1970), .A1(result_add_subt[55]), .B0(n1969), .B1( d_ff_Zn[55]), .Y(n1210) ); AO22XLTS U2047 ( .A0(n1970), .A1(result_add_subt[54]), .B0(n1969), .B1( d_ff_Zn[54]), .Y(n1211) ); AO22XLTS U2048 ( .A0(n1970), .A1(result_add_subt[53]), .B0(n1969), .B1( d_ff_Zn[53]), .Y(n1212) ); AO22XLTS U2049 ( .A0(n1970), .A1(result_add_subt[52]), .B0(n1969), .B1( d_ff_Zn[52]), .Y(n1213) ); AO22XLTS U2050 ( .A0(n1970), .A1(result_add_subt[51]), .B0(n1969), .B1( d_ff_Zn[51]), .Y(n1214) ); AO22XLTS U2051 ( .A0(n1970), .A1(result_add_subt[50]), .B0(n1969), .B1( d_ff_Zn[50]), .Y(n1215) ); AO22XLTS U2052 ( .A0(n1968), .A1(result_add_subt[49]), .B0(n1969), .B1( d_ff_Zn[49]), .Y(n1216) ); AO22XLTS U2053 ( .A0(n1968), .A1(result_add_subt[48]), .B0(n1972), .B1( d_ff_Zn[48]), .Y(n1217) ); AO22XLTS U2054 ( .A0(n1968), .A1(result_add_subt[47]), .B0(n1967), .B1( d_ff_Zn[47]), .Y(n1218) ); AO22XLTS U2055 ( .A0(n1968), .A1(result_add_subt[46]), .B0(n1967), .B1( d_ff_Zn[46]), .Y(n1219) ); AO22XLTS U2056 ( .A0(n1968), .A1(result_add_subt[45]), .B0(n1967), .B1( d_ff_Zn[45]), .Y(n1220) ); AO22XLTS U2057 ( .A0(n1968), .A1(result_add_subt[44]), .B0(n1967), .B1( d_ff_Zn[44]), .Y(n1221) ); AO22XLTS U2058 ( .A0(n1968), .A1(result_add_subt[43]), .B0(n1966), .B1( d_ff_Zn[43]), .Y(n1222) ); AO22XLTS U2059 ( .A0(n1968), .A1(result_add_subt[42]), .B0(n1966), .B1( d_ff_Zn[42]), .Y(n1223) ); AO22XLTS U2060 ( .A0(n1968), .A1(result_add_subt[41]), .B0(n1966), .B1( d_ff_Zn[41]), .Y(n1224) ); AO22XLTS U2061 ( .A0(n1968), .A1(result_add_subt[40]), .B0(n1966), .B1( d_ff_Zn[40]), .Y(n1225) ); AO22XLTS U2062 ( .A0(n1965), .A1(result_add_subt[39]), .B0(n1966), .B1( d_ff_Zn[39]), .Y(n1226) ); AO22XLTS U2063 ( .A0(n1965), .A1(result_add_subt[38]), .B0(n1964), .B1( d_ff_Zn[38]), .Y(n1227) ); AO22XLTS U2064 ( .A0(n1965), .A1(result_add_subt[37]), .B0(n1964), .B1( d_ff_Zn[37]), .Y(n1228) ); AO22XLTS U2065 ( .A0(n1965), .A1(result_add_subt[36]), .B0(n1964), .B1( d_ff_Zn[36]), .Y(n1229) ); AO22XLTS U2066 ( .A0(n1965), .A1(result_add_subt[35]), .B0(n1964), .B1( d_ff_Zn[35]), .Y(n1230) ); AO22XLTS U2067 ( .A0(n1965), .A1(result_add_subt[34]), .B0(n1964), .B1( d_ff_Zn[34]), .Y(n1231) ); AO22XLTS U2068 ( .A0(n1965), .A1(result_add_subt[33]), .B0(n1964), .B1( d_ff_Zn[33]), .Y(n1232) ); AO22XLTS U2069 ( .A0(n1965), .A1(result_add_subt[32]), .B0(n1964), .B1( d_ff_Zn[32]), .Y(n1233) ); AO22XLTS U2070 ( .A0(n1965), .A1(result_add_subt[31]), .B0(n1964), .B1( d_ff_Zn[31]), .Y(n1234) ); AO22XLTS U2071 ( .A0(n1965), .A1(result_add_subt[30]), .B0(n1964), .B1( d_ff_Zn[30]), .Y(n1235) ); AO22XLTS U2072 ( .A0(n1963), .A1(result_add_subt[29]), .B0(n1964), .B1( d_ff_Zn[29]), .Y(n1236) ); AO22XLTS U2073 ( .A0(n1963), .A1(result_add_subt[28]), .B0(n1962), .B1( d_ff_Zn[28]), .Y(n1237) ); AO22XLTS U2074 ( .A0(n1963), .A1(result_add_subt[27]), .B0(n1962), .B1( d_ff_Zn[27]), .Y(n1238) ); AO22XLTS U2075 ( .A0(n1963), .A1(result_add_subt[26]), .B0(n1962), .B1( d_ff_Zn[26]), .Y(n1239) ); AO22XLTS U2076 ( .A0(n1963), .A1(result_add_subt[25]), .B0(n1962), .B1( d_ff_Zn[25]), .Y(n1240) ); AO22XLTS U2077 ( .A0(n1963), .A1(result_add_subt[24]), .B0(n1962), .B1( d_ff_Zn[24]), .Y(n1241) ); AO22XLTS U2078 ( .A0(n1963), .A1(result_add_subt[23]), .B0(n1962), .B1( d_ff_Zn[23]), .Y(n1242) ); AO22XLTS U2079 ( .A0(n1963), .A1(result_add_subt[22]), .B0(n1962), .B1( d_ff_Zn[22]), .Y(n1243) ); AO22XLTS U2080 ( .A0(n1963), .A1(result_add_subt[21]), .B0(n1962), .B1( d_ff_Zn[21]), .Y(n1244) ); AO22XLTS U2081 ( .A0(n1963), .A1(result_add_subt[20]), .B0(n1962), .B1( d_ff_Zn[20]), .Y(n1245) ); AO22XLTS U2082 ( .A0(n1961), .A1(result_add_subt[19]), .B0(n1962), .B1( d_ff_Zn[19]), .Y(n1246) ); AO22XLTS U2083 ( .A0(n1961), .A1(result_add_subt[18]), .B0(n1960), .B1( d_ff_Zn[18]), .Y(n1247) ); AO22XLTS U2084 ( .A0(n1961), .A1(result_add_subt[17]), .B0(n1960), .B1( d_ff_Zn[17]), .Y(n1248) ); AO22XLTS U2085 ( .A0(n1961), .A1(result_add_subt[16]), .B0(n1960), .B1( d_ff_Zn[16]), .Y(n1249) ); AO22XLTS U2086 ( .A0(n1961), .A1(result_add_subt[15]), .B0(n1960), .B1( d_ff_Zn[15]), .Y(n1250) ); AO22XLTS U2087 ( .A0(n1961), .A1(result_add_subt[14]), .B0(n1960), .B1( d_ff_Zn[14]), .Y(n1251) ); AO22XLTS U2088 ( .A0(n1961), .A1(result_add_subt[13]), .B0(n1960), .B1( d_ff_Zn[13]), .Y(n1252) ); AO22XLTS U2089 ( .A0(n1961), .A1(result_add_subt[12]), .B0(n1960), .B1( d_ff_Zn[12]), .Y(n1253) ); AO22XLTS U2090 ( .A0(n1961), .A1(result_add_subt[11]), .B0(n1960), .B1( d_ff_Zn[11]), .Y(n1254) ); AO22XLTS U2091 ( .A0(n1961), .A1(result_add_subt[10]), .B0(n1960), .B1( d_ff_Zn[10]), .Y(n1255) ); AO22XLTS U2092 ( .A0(n1959), .A1(result_add_subt[9]), .B0(n1960), .B1( d_ff_Zn[9]), .Y(n1256) ); AO22XLTS U2093 ( .A0(n1959), .A1(result_add_subt[8]), .B0(n1958), .B1( d_ff_Zn[8]), .Y(n1257) ); AO22XLTS U2094 ( .A0(n1959), .A1(result_add_subt[7]), .B0(n1958), .B1( d_ff_Zn[7]), .Y(n1258) ); AO22XLTS U2095 ( .A0(n1959), .A1(result_add_subt[6]), .B0(n1958), .B1( d_ff_Zn[6]), .Y(n1259) ); AO22XLTS U2096 ( .A0(n1959), .A1(result_add_subt[5]), .B0(n1958), .B1( d_ff_Zn[5]), .Y(n1260) ); AO22XLTS U2097 ( .A0(n1959), .A1(result_add_subt[4]), .B0(n1958), .B1( d_ff_Zn[4]), .Y(n1261) ); AO22XLTS U2098 ( .A0(n1959), .A1(result_add_subt[3]), .B0(n1958), .B1( d_ff_Zn[3]), .Y(n1262) ); AO22XLTS U2099 ( .A0(n1959), .A1(result_add_subt[2]), .B0(n1958), .B1( d_ff_Zn[2]), .Y(n1263) ); AO22XLTS U2100 ( .A0(n1959), .A1(result_add_subt[1]), .B0(n1971), .B1( d_ff_Zn[1]), .Y(n1264) ); AO22XLTS U2101 ( .A0(n1959), .A1(result_add_subt[0]), .B0(n1971), .B1( d_ff_Zn[0]), .Y(n1265) ); AO22XLTS U2102 ( .A0(n1955), .A1(data_in[63]), .B0(n1954), .B1(d_ff1_Z[63]), .Y(n1270) ); AO22XLTS U2103 ( .A0(n1953), .A1(data_in[62]), .B0(n1952), .B1(d_ff1_Z[62]), .Y(n1271) ); AO22XLTS U2104 ( .A0(n1953), .A1(data_in[61]), .B0(n1951), .B1(d_ff1_Z[61]), .Y(n1272) ); AO22XLTS U2105 ( .A0(n1953), .A1(data_in[60]), .B0(n1951), .B1(d_ff1_Z[60]), .Y(n1273) ); AO22XLTS U2106 ( .A0(n1953), .A1(data_in[59]), .B0(n1950), .B1(d_ff1_Z[59]), .Y(n1274) ); AO22XLTS U2107 ( .A0(n1949), .A1(data_in[58]), .B0(n1950), .B1(d_ff1_Z[58]), .Y(n1275) ); AO22XLTS U2108 ( .A0(n1949), .A1(data_in[57]), .B0(n1940), .B1(d_ff1_Z[57]), .Y(n1276) ); AO22XLTS U2109 ( .A0(n1949), .A1(data_in[56]), .B0(n1940), .B1(d_ff1_Z[56]), .Y(n1277) ); AO22XLTS U2110 ( .A0(n1949), .A1(data_in[55]), .B0(n1950), .B1(d_ff1_Z[55]), .Y(n1278) ); AO22XLTS U2111 ( .A0(n1949), .A1(data_in[54]), .B0(n1952), .B1(d_ff1_Z[54]), .Y(n1279) ); AO22XLTS U2112 ( .A0(n1948), .A1(data_in[53]), .B0(n1952), .B1(d_ff1_Z[53]), .Y(n1280) ); AO22XLTS U2113 ( .A0(n1948), .A1(data_in[52]), .B0(n1952), .B1(d_ff1_Z[52]), .Y(n1281) ); AO22XLTS U2114 ( .A0(n1948), .A1(data_in[51]), .B0(n1947), .B1(d_ff1_Z[51]), .Y(n1282) ); AO22XLTS U2115 ( .A0(n1948), .A1(data_in[50]), .B0(n1947), .B1(d_ff1_Z[50]), .Y(n1283) ); AO22XLTS U2116 ( .A0(n1946), .A1(data_in[49]), .B0(n1947), .B1(d_ff1_Z[49]), .Y(n1284) ); AO22XLTS U2117 ( .A0(n1946), .A1(data_in[48]), .B0(n1947), .B1(d_ff1_Z[48]), .Y(n1285) ); AO22XLTS U2118 ( .A0(n1946), .A1(data_in[47]), .B0(n1947), .B1(d_ff1_Z[47]), .Y(n1286) ); AO22XLTS U2119 ( .A0(n1946), .A1(data_in[46]), .B0(n1947), .B1(d_ff1_Z[46]), .Y(n1287) ); AO22XLTS U2120 ( .A0(n1946), .A1(data_in[45]), .B0(n1947), .B1(d_ff1_Z[45]), .Y(n1288) ); AO22XLTS U2121 ( .A0(n1946), .A1(data_in[44]), .B0(n1947), .B1(d_ff1_Z[44]), .Y(n1289) ); AO22XLTS U2122 ( .A0(n1949), .A1(data_in[43]), .B0(n1947), .B1(d_ff1_Z[43]), .Y(n1290) ); AO22XLTS U2123 ( .A0(n1949), .A1(data_in[42]), .B0(n1947), .B1(d_ff1_Z[42]), .Y(n1291) ); AO22XLTS U2124 ( .A0(n1949), .A1(data_in[41]), .B0(n1945), .B1(d_ff1_Z[41]), .Y(n1292) ); AO22XLTS U2125 ( .A0(n1949), .A1(data_in[40]), .B0(n1945), .B1(d_ff1_Z[40]), .Y(n1293) ); AO22XLTS U2126 ( .A0(n1949), .A1(data_in[39]), .B0(n1945), .B1(d_ff1_Z[39]), .Y(n1294) ); AO22XLTS U2127 ( .A0(n1948), .A1(data_in[38]), .B0(n1945), .B1(d_ff1_Z[38]), .Y(n1295) ); AO22XLTS U2128 ( .A0(n1948), .A1(data_in[37]), .B0(n1945), .B1(d_ff1_Z[37]), .Y(n1296) ); AO22XLTS U2129 ( .A0(n1948), .A1(data_in[36]), .B0(n1945), .B1(d_ff1_Z[36]), .Y(n1297) ); AO22XLTS U2130 ( .A0(n1948), .A1(data_in[35]), .B0(n1945), .B1(d_ff1_Z[35]), .Y(n1298) ); AO22XLTS U2131 ( .A0(n1948), .A1(data_in[34]), .B0(n1945), .B1(d_ff1_Z[34]), .Y(n1299) ); AO22XLTS U2132 ( .A0(n1943), .A1(data_in[33]), .B0(n1945), .B1(d_ff1_Z[33]), .Y(n1300) ); AO22XLTS U2133 ( .A0(n1943), .A1(data_in[32]), .B0(n1945), .B1(d_ff1_Z[32]), .Y(n1301) ); AO22XLTS U2134 ( .A0(n1943), .A1(data_in[31]), .B0(n1954), .B1(d_ff1_Z[31]), .Y(n1302) ); AO22XLTS U2135 ( .A0(n1943), .A1(data_in[30]), .B0(n1954), .B1(d_ff1_Z[30]), .Y(n1303) ); AO22XLTS U2136 ( .A0(n1955), .A1(data_in[29]), .B0(n1954), .B1(d_ff1_Z[29]), .Y(n1304) ); AO22XLTS U2137 ( .A0(n1955), .A1(data_in[28]), .B0(n1954), .B1(d_ff1_Z[28]), .Y(n1305) ); AO22XLTS U2138 ( .A0(n1955), .A1(data_in[27]), .B0(n1954), .B1(d_ff1_Z[27]), .Y(n1306) ); AO22XLTS U2139 ( .A0(n1955), .A1(data_in[26]), .B0(n1954), .B1(d_ff1_Z[26]), .Y(n1307) ); AO22XLTS U2140 ( .A0(n1942), .A1(data_in[25]), .B0(n1954), .B1(d_ff1_Z[25]), .Y(n1308) ); AO22XLTS U2141 ( .A0(n1946), .A1(data_in[24]), .B0(n1954), .B1(d_ff1_Z[24]), .Y(n1309) ); AO22XLTS U2142 ( .A0(n1946), .A1(data_in[23]), .B0(n1954), .B1(d_ff1_Z[23]), .Y(n1310) ); AO22XLTS U2143 ( .A0(n1946), .A1(data_in[22]), .B0(n1941), .B1(d_ff1_Z[22]), .Y(n1311) ); AO22XLTS U2144 ( .A0(n1946), .A1(data_in[21]), .B0(n1941), .B1(d_ff1_Z[21]), .Y(n1312) ); AO22XLTS U2145 ( .A0(n1943), .A1(data_in[20]), .B0(n1941), .B1(d_ff1_Z[20]), .Y(n1313) ); AO22XLTS U2146 ( .A0(n1943), .A1(data_in[19]), .B0(n1941), .B1(d_ff1_Z[19]), .Y(n1314) ); AO22XLTS U2147 ( .A0(n1943), .A1(data_in[18]), .B0(n1941), .B1(d_ff1_Z[18]), .Y(n1315) ); AO22XLTS U2148 ( .A0(n1943), .A1(data_in[17]), .B0(n1941), .B1(d_ff1_Z[17]), .Y(n1316) ); AO22XLTS U2149 ( .A0(n1943), .A1(data_in[16]), .B0(n1941), .B1(d_ff1_Z[16]), .Y(n1317) ); AO22XLTS U2150 ( .A0(n1943), .A1(data_in[15]), .B0(n1941), .B1(d_ff1_Z[15]), .Y(n1318) ); AO22XLTS U2151 ( .A0(n1942), .A1(data_in[14]), .B0(n1941), .B1(d_ff1_Z[14]), .Y(n1319) ); AO22XLTS U2152 ( .A0(n1942), .A1(data_in[13]), .B0(n1941), .B1(d_ff1_Z[13]), .Y(n1320) ); AO22XLTS U2153 ( .A0(n1942), .A1(data_in[12]), .B0(n1940), .B1(d_ff1_Z[12]), .Y(n1321) ); AO22XLTS U2154 ( .A0(n1942), .A1(data_in[11]), .B0(n1940), .B1(d_ff1_Z[11]), .Y(n1322) ); AO22XLTS U2155 ( .A0(n1953), .A1(data_in[10]), .B0(n1940), .B1(d_ff1_Z[10]), .Y(n1323) ); AO22XLTS U2156 ( .A0(n1953), .A1(data_in[9]), .B0(n1940), .B1(d_ff1_Z[9]), .Y(n1324) ); AO22XLTS U2157 ( .A0(n1953), .A1(data_in[8]), .B0(n1940), .B1(d_ff1_Z[8]), .Y(n1325) ); AO22XLTS U2158 ( .A0(n1953), .A1(data_in[7]), .B0(n1939), .B1(d_ff1_Z[7]), .Y(n1326) ); AO22XLTS U2159 ( .A0(n1953), .A1(data_in[6]), .B0(n1939), .B1(d_ff1_Z[6]), .Y(n1327) ); AO22XLTS U2160 ( .A0(n1953), .A1(data_in[5]), .B0(n1939), .B1(d_ff1_Z[5]), .Y(n1328) ); AO22XLTS U2161 ( .A0(n1948), .A1(data_in[4]), .B0(n1939), .B1(d_ff1_Z[4]), .Y(n1329) ); AO22XLTS U2162 ( .A0(n1942), .A1(data_in[3]), .B0(n1939), .B1(d_ff1_Z[3]), .Y(n1330) ); AO22XLTS U2163 ( .A0(n1942), .A1(data_in[2]), .B0(n1939), .B1(d_ff1_Z[2]), .Y(n1331) ); AO22XLTS U2164 ( .A0(n1942), .A1(data_in[1]), .B0(n1939), .B1(d_ff1_Z[1]), .Y(n1332) ); AO22XLTS U2165 ( .A0(n1942), .A1(data_in[0]), .B0(n1952), .B1(d_ff1_Z[0]), .Y(n1333) ); NOR3X6TS U2166 ( .A(n1503), .B(n1491), .C(n1676), .Y(n1476) ); INVX2TS U2167 ( .A(n1504), .Y(n2195) ); INVX2TS U2168 ( .A(n1877), .Y(n1806) ); CLKBUFX2TS U2169 ( .A(cont_iter_out[3]), .Y(n2049) ); BUFX3TS U2170 ( .A(n2120), .Y(n2176) ); CLKBUFX2TS U2171 ( .A(n1518), .Y(n1526) ); BUFX3TS U2172 ( .A(n1518), .Y(n1525) ); BUFX3TS U2173 ( .A(n1518), .Y(n1527) ); CLKINVX3TS U2174 ( .A(n1524), .Y(n2345) ); CLKINVX3TS U2175 ( .A(n1524), .Y(n2340) ); INVX2TS U2176 ( .A(n1524), .Y(n2344) ); INVX2TS U2177 ( .A(n1524), .Y(n2346) ); INVX2TS U2178 ( .A(n2340), .Y(n1487) ); INVX2TS U2179 ( .A(n1487), .Y(n1488) ); INVX2TS U2180 ( .A(n1487), .Y(n1489) ); INVX2TS U2181 ( .A(n2100), .Y(n1490) ); INVX2TS U2182 ( .A(cont_iter_out[2]), .Y(n1491) ); CLKINVX3TS U2183 ( .A(n1529), .Y(n2320) ); CLKINVX3TS U2184 ( .A(n1529), .Y(n2325) ); CLKINVX3TS U2185 ( .A(n1529), .Y(n2301) ); INVX2TS U2186 ( .A(n1529), .Y(n2300) ); INVX2TS U2187 ( .A(n2301), .Y(n1492) ); INVX2TS U2188 ( .A(n1492), .Y(n1493) ); INVX2TS U2189 ( .A(n1492), .Y(n1494) ); INVX2TS U2190 ( .A(n1477), .Y(n1495) ); CLKINVX3TS U2191 ( .A(n1499), .Y(n1496) ); INVX2TS U2192 ( .A(n1880), .Y(n1497) ); INVX2TS U2193 ( .A(n1880), .Y(n1498) ); INVX2TS U2194 ( .A(n1479), .Y(n1499) ); INVX2TS U2195 ( .A(n1479), .Y(n1500) ); INVX2TS U2196 ( .A(n1487), .Y(n1501) ); INVX2TS U2197 ( .A(n1487), .Y(n1502) ); INVX2TS U2198 ( .A(n2049), .Y(n1503) ); INVX2TS U2199 ( .A(n1503), .Y(n1504) ); INVX2TS U2200 ( .A(n1503), .Y(n1505) ); AOI211X1TS U2201 ( .A0(n1476), .A1(n1486), .B0(n1896), .C0(n1932), .Y(n1898) ); NOR2X4TS U2202 ( .A(cordic_FSM_state_reg[2]), .B(n2222), .Y(n1932) ); OAI21XLTS U2203 ( .A0(n2237), .A1(n1877), .B0(n1861), .Y(add_subt_dataA[62]) ); AOI222X1TS U2204 ( .A0(d_ff2_Z[46]), .A1(n1792), .B0(d_ff2_Y[46]), .B1(n1497), .C0(d_ff2_X[46]), .C1(n1780), .Y(n1769) ); AOI222X1TS U2205 ( .A0(d_ff2_Z[45]), .A1(n1789), .B0(d_ff2_Y[45]), .B1(n1871), .C0(d_ff2_X[45]), .C1(n1780), .Y(n1778) ); AOI222X1TS U2206 ( .A0(d_ff2_Z[44]), .A1(n1789), .B0(d_ff2_Y[44]), .B1(n1893), .C0(d_ff2_X[44]), .C1(n1780), .Y(n1771) ); AOI222X1TS U2207 ( .A0(d_ff2_Z[43]), .A1(n1727), .B0(d_ff2_Y[43]), .B1(n1782), .C0(d_ff2_X[43]), .C1(n1780), .Y(n1779) ); AOI222X1TS U2208 ( .A0(d_ff2_Z[42]), .A1(n1792), .B0(d_ff2_Y[42]), .B1(n1871), .C0(d_ff2_X[42]), .C1(n1780), .Y(n1772) ); AOI222X1TS U2209 ( .A0(d_ff2_Z[41]), .A1(n1892), .B0(d_ff2_Y[41]), .B1(n1893), .C0(d_ff2_X[41]), .C1(n1780), .Y(n1768) ); AOI222X1TS U2210 ( .A0(d_ff2_Z[40]), .A1(n1727), .B0(d_ff2_Y[40]), .B1(n1782), .C0(d_ff2_X[40]), .C1(n1780), .Y(n1775) ); AOI222X1TS U2211 ( .A0(d_ff2_Z[39]), .A1(n1789), .B0(d_ff2_Y[39]), .B1(n1893), .C0(d_ff2_X[39]), .C1(n1780), .Y(n1781) ); AOI222X1TS U2212 ( .A0(d_ff2_Z[38]), .A1(n1773), .B0(d_ff2_Y[38]), .B1(n1782), .C0(d_ff2_X[38]), .C1(n1780), .Y(n1774) ); AOI222X1TS U2213 ( .A0(d_ff2_Z[37]), .A1(n1727), .B0(d_ff2_Y[37]), .B1(n1776), .C0(d_ff2_X[37]), .C1(n1780), .Y(n1777) ); AOI222X1TS U2214 ( .A0(d_ff2_Z[36]), .A1(n1773), .B0(d_ff2_Y[36]), .B1(n1893), .C0(d_ff2_X[36]), .C1(n1730), .Y(n1746) ); AOI222X1TS U2215 ( .A0(d_ff2_Z[35]), .A1(n1892), .B0(d_ff2_Y[35]), .B1(n1782), .C0(d_ff2_X[35]), .C1(n1730), .Y(n1749) ); AOI222X1TS U2216 ( .A0(d_ff2_Z[34]), .A1(n1727), .B0(d_ff2_Y[34]), .B1(n1776), .C0(d_ff2_X[34]), .C1(n1910), .Y(n1751) ); AOI222X1TS U2217 ( .A0(d_ff2_Z[33]), .A1(n1727), .B0(d_ff2_Y[33]), .B1(n1776), .C0(d_ff2_X[33]), .C1(n1730), .Y(n1743) ); AOI222X1TS U2218 ( .A0(d_ff2_Z[32]), .A1(n1773), .B0(d_ff2_Y[32]), .B1(n1776), .C0(d_ff2_X[32]), .C1(n1909), .Y(n1748) ); AOI222X1TS U2219 ( .A0(d_ff2_Z[31]), .A1(n1773), .B0(d_ff2_Y[31]), .B1(n1776), .C0(d_ff2_X[31]), .C1(n1730), .Y(n1755) ); AOI222X1TS U2220 ( .A0(d_ff2_Z[30]), .A1(n1773), .B0(d_ff2_Y[30]), .B1(n1776), .C0(d_ff2_X[30]), .C1(n1910), .Y(n1745) ); AOI222X1TS U2221 ( .A0(d_ff2_Z[29]), .A1(n1727), .B0(d_ff2_Y[29]), .B1(n1776), .C0(d_ff2_X[29]), .C1(n1730), .Y(n1747) ); AOI222X1TS U2222 ( .A0(d_ff2_Z[28]), .A1(n1773), .B0(d_ff2_Y[28]), .B1(n1776), .C0(d_ff2_X[28]), .C1(n1909), .Y(n1756) ); AOI222X1TS U2223 ( .A0(d_ff2_Z[27]), .A1(n1770), .B0(d_ff2_Y[27]), .B1(n1776), .C0(d_ff2_X[27]), .C1(n1910), .Y(n1731) ); AOI222X1TS U2224 ( .A0(d_ff2_Z[26]), .A1(n1773), .B0(d_ff2_Y[26]), .B1(n1920), .C0(d_ff2_X[26]), .C1(n1752), .Y(n1750) ); AOI222X1TS U2225 ( .A0(d_ff2_Z[25]), .A1(n1773), .B0(d_ff2_Y[25]), .B1(n1920), .C0(d_ff2_X[25]), .C1(n1752), .Y(n1742) ); AOI222X1TS U2226 ( .A0(d_ff2_Z[24]), .A1(n1773), .B0(d_ff2_Y[24]), .B1(n1920), .C0(d_ff2_X[24]), .C1(n1752), .Y(n1754) ); AOI222X1TS U2227 ( .A0(d_ff2_Z[23]), .A1(n1727), .B0(d_ff2_Y[23]), .B1(n1920), .C0(d_ff2_X[23]), .C1(n1752), .Y(n1728) ); AOI222X1TS U2228 ( .A0(d_ff2_Z[22]), .A1(n1792), .B0(d_ff2_Y[22]), .B1(n1920), .C0(d_ff2_X[22]), .C1(n1752), .Y(n1726) ); AOI222X1TS U2229 ( .A0(d_ff2_Z[21]), .A1(n1770), .B0(d_ff2_Y[21]), .B1(n1776), .C0(d_ff2_X[21]), .C1(n1752), .Y(n1732) ); AOI222X1TS U2230 ( .A0(d_ff2_Z[20]), .A1(n1773), .B0(d_ff2_Y[20]), .B1(n1920), .C0(d_ff2_X[20]), .C1(n1752), .Y(n1744) ); AOI222X1TS U2231 ( .A0(d_ff2_Z[19]), .A1(n1734), .B0(d_ff2_Y[19]), .B1(n1920), .C0(d_ff2_X[19]), .C1(n1752), .Y(n1735) ); AOI222X1TS U2232 ( .A0(d_ff2_Z[18]), .A1(n1770), .B0(d_ff2_Y[18]), .B1(n1920), .C0(d_ff2_X[18]), .C1(n1752), .Y(n1729) ); AOI222X1TS U2233 ( .A0(d_ff2_Z[15]), .A1(n1770), .B0(d_ff2_Y[15]), .B1(n1920), .C0(d_ff2_X[15]), .C1(n1910), .Y(n1691) ); AOI222X1TS U2234 ( .A0(d_ff2_Z[14]), .A1(n1727), .B0(d_ff2_Y[14]), .B1(n1920), .C0(d_ff2_X[14]), .C1(n1909), .Y(n1695) ); AOI222X1TS U2235 ( .A0(d_ff2_Z[5]), .A1(n1911), .B0(d_ff2_Y[5]), .B1(n1753), .C0(d_ff2_X[5]), .C1(n1910), .Y(n1692) ); AOI222X1TS U2236 ( .A0(d_ff2_Z[4]), .A1(n1911), .B0(d_ff2_Y[4]), .B1(n1806), .C0(d_ff2_X[4]), .C1(n1909), .Y(n1697) ); AOI222X1TS U2237 ( .A0(d_ff2_Z[3]), .A1(n1734), .B0(d_ff2_Y[3]), .B1(n1753), .C0(d_ff2_X[3]), .C1(n1694), .Y(n1565) ); AOI222X1TS U2238 ( .A0(d_ff2_Z[2]), .A1(n1911), .B0(d_ff2_Y[2]), .B1(n1806), .C0(d_ff2_X[2]), .C1(n1909), .Y(n1698) ); AOI222X1TS U2239 ( .A0(d_ff2_Z[1]), .A1(n1734), .B0(d_ff2_Y[1]), .B1(n1753), .C0(d_ff2_X[1]), .C1(n1730), .Y(n1689) ); AOI222X4TS U2240 ( .A0(n2187), .A1(d_ff2_Z[0]), .B0(n1817), .B1(d_ff_Zn[0]), .C0(n1821), .C1(d_ff1_Z[0]), .Y(n1757) ); INVX1TS U2241 ( .A(beg_add_subt), .Y(n1897) ); OAI21XLTS U2242 ( .A0(n2292), .A1(n1560), .B0(n1556), .Y(n947) ); OAI32X1TS U2243 ( .A0(n1902), .A1(n1901), .A2(n2230), .B0(n1900), .B1(n1899), .Y(n1267) ); BUFX3TS U2244 ( .A(n1527), .Y(n1901) ); NOR4X1TS U2245 ( .A(cordic_FSM_state_reg[1]), .B(n2223), .C(n2225), .D(n2229), .Y(ready_cordic) ); OAI32X1TS U2246 ( .A0(cordic_FSM_state_reg[2]), .A1(beg_fsm_cordic), .A2( n1930), .B0(n1929), .B1(n2225), .Y(n1935) ); OAI21X2TS U2247 ( .A0(n1571), .A1(n2080), .B0(n2065), .Y(n2060) ); NOR2X2TS U2248 ( .A(n1676), .B(n2080), .Y(n1937) ); OAI21X2TS U2249 ( .A0(n1678), .A1(n1563), .B0(n2065), .Y(n2048) ); NOR2X2TS U2250 ( .A(n2100), .B(n1499), .Y(n1678) ); OAI211XLTS U2251 ( .A0(n1569), .A1(n2087), .B0(n2023), .C0(n1564), .Y(n938) ); OAI211XLTS U2252 ( .A0(n2076), .A1(n1515), .B0(n2062), .C0(n2023), .Y(n926) ); OAI21X2TS U2253 ( .A0(n2051), .A1(n2039), .B0(n2089), .Y(n2023) ); CLKINVX3TS U2254 ( .A(n1860), .Y(n1920) ); NOR2X2TS U2255 ( .A(n2100), .B(n1496), .Y(n1699) ); CLKINVX3TS U2256 ( .A(n1525), .Y(n2319) ); CLKINVX3TS U2257 ( .A(n1525), .Y(n2297) ); CLKINVX3TS U2258 ( .A(n1525), .Y(n2298) ); CLKINVX3TS U2259 ( .A(n1525), .Y(n2299) ); CLKINVX3TS U2260 ( .A(n1525), .Y(n2318) ); AOI222X4TS U2261 ( .A0(n1911), .A1(d_ff3_LUT_out[44]), .B0(n1887), .B1( d_ff3_sh_x_out[44]), .C0(n1886), .C1(d_ff3_sh_y_out[44]), .Y(n1764) ); AOI222X4TS U2262 ( .A0(n1911), .A1(d_ff3_LUT_out[52]), .B0(n1887), .B1( d_ff3_sh_x_out[52]), .C0(n1886), .C1(d_ff3_sh_y_out[52]), .Y(n1761) ); AOI222X4TS U2263 ( .A0(n1911), .A1(d_ff3_LUT_out[49]), .B0(n1887), .B1( d_ff3_sh_x_out[49]), .C0(n1886), .C1(d_ff3_sh_y_out[49]), .Y(n1760) ); AOI222X4TS U2264 ( .A0(n1911), .A1(d_ff3_LUT_out[46]), .B0(n1887), .B1( d_ff3_sh_x_out[46]), .C0(n1886), .C1(d_ff3_sh_y_out[46]), .Y(n1758) ); CLKINVX3TS U2265 ( .A(n2185), .Y(n1842) ); CLKINVX3TS U2266 ( .A(n2185), .Y(n1840) ); CLKINVX3TS U2267 ( .A(n2106), .Y(n1724) ); CLKINVX3TS U2268 ( .A(n2106), .Y(n1717) ); CLKINVX3TS U2269 ( .A(n2106), .Y(n1833) ); CLKINVX3TS U2270 ( .A(n2106), .Y(n2108) ); OAI33X1TS U2271 ( .A0(d_ff1_shift_region_flag_out[1]), .A1( d_ff1_operation_out), .A2(n2238), .B0(n2226), .B1(n2224), .B2( d_ff1_shift_region_flag_out[0]), .Y(n1536) ); CLKINVX3TS U2272 ( .A(n1527), .Y(n2294) ); CLKINVX3TS U2273 ( .A(n1527), .Y(n2296) ); CLKINVX3TS U2274 ( .A(n1527), .Y(n2312) ); CLKINVX3TS U2275 ( .A(n1527), .Y(n2295) ); CLKINVX3TS U2276 ( .A(n1527), .Y(n2313) ); CLKBUFX3TS U2277 ( .A(n1492), .Y(n1524) ); CLKINVX3TS U2278 ( .A(n1518), .Y(n2305) ); CLKINVX3TS U2279 ( .A(n1518), .Y(n2304) ); CLKINVX3TS U2280 ( .A(n1518), .Y(n2332) ); CLKINVX3TS U2281 ( .A(n1518), .Y(n2331) ); CLKINVX3TS U2282 ( .A(n1526), .Y(n2358) ); CLKINVX3TS U2283 ( .A(n1526), .Y(n2363) ); CLKINVX3TS U2284 ( .A(n1526), .Y(n2362) ); CLKINVX3TS U2285 ( .A(n1526), .Y(n2359) ); INVX2TS U2286 ( .A(n1901), .Y(n1506) ); INVX2TS U2287 ( .A(n1487), .Y(n1507) ); INVX2TS U2288 ( .A(n1527), .Y(n1508) ); INVX2TS U2289 ( .A(n1527), .Y(n1509) ); CLKINVX3TS U2290 ( .A(n1492), .Y(n2356) ); INVX2TS U2291 ( .A(n1525), .Y(n1510) ); CLKINVX3TS U2292 ( .A(n1492), .Y(n2357) ); CLKINVX3TS U2293 ( .A(n1487), .Y(n2351) ); CLKINVX3TS U2294 ( .A(n1492), .Y(n2352) ); CLKINVX3TS U2295 ( .A(n1487), .Y(n2353) ); BUFX3TS U2296 ( .A(n1525), .Y(n1529) ); CLKINVX3TS U2297 ( .A(n1901), .Y(n2321) ); CLKINVX3TS U2298 ( .A(n1901), .Y(n2307) ); CLKINVX3TS U2299 ( .A(n1901), .Y(n2303) ); CLKINVX3TS U2300 ( .A(n1901), .Y(n2306) ); CLKINVX3TS U2301 ( .A(n1901), .Y(n2322) ); INVX2TS U2302 ( .A(n1530), .Y(n1511) ); CLKINVX3TS U2303 ( .A(n1530), .Y(n2328) ); CLKINVX3TS U2304 ( .A(n1530), .Y(n2309) ); CLKINVX3TS U2305 ( .A(n1530), .Y(n2310) ); CLKINVX3TS U2306 ( .A(n1530), .Y(n2311) ); BUFX3TS U2307 ( .A(n1527), .Y(n1530) ); CLKINVX3TS U2308 ( .A(n1525), .Y(n2323) ); CLKINVX3TS U2309 ( .A(n1529), .Y(n2336) ); CLKINVX3TS U2310 ( .A(n1524), .Y(n2337) ); CLKINVX3TS U2311 ( .A(n1487), .Y(n2338) ); NOR2X2TS U2312 ( .A(n1504), .B(n2227), .Y(n2055) ); CLKINVX3TS U2313 ( .A(n1530), .Y(n2350) ); AOI32X4TS U2314 ( .A0(n2195), .A1(n2213), .A2(n1552), .B0(d_ff3_sh_y_out[55]), .B1(n2087), .Y(n1551) ); OAI21XLTS U2315 ( .A0(n2065), .A1(d_ff3_LUT_out[1]), .B0(n2029), .Y(n1570) ); OAI21XLTS U2316 ( .A0(n2213), .A1(d_ff3_LUT_out[6]), .B0(n2029), .Y(n2030) ); OAI21XLTS U2317 ( .A0(n2065), .A1(d_ff3_LUT_out[7]), .B0(n2048), .Y(n1564) ); OAI21XLTS U2318 ( .A0(n2065), .A1(d_ff3_LUT_out[14]), .B0(n2060), .Y(n1562) ); AOI32X4TS U2319 ( .A0(n2100), .A1(n2076), .A2(n1553), .B0(d_ff3_LUT_out[54]), .B1(n2087), .Y(n1554) ); OAI32X4TS U2320 ( .A0(n2044), .A1(n2043), .A2(n2054), .B0(n2076), .B1( d_ff3_LUT_out[9]), .Y(n2033) ); OAI32X4TS U2321 ( .A0(n2044), .A1(n1937), .A2(n2042), .B0(d_ff3_LUT_out[26]), .B1(n2213), .Y(n1538) ); NOR2X2TS U2322 ( .A(n1679), .B(n2152), .Y(n2085) ); NOR2X1TS U2323 ( .A(d_ff2_Y[61]), .B(n2150), .Y(n2149) ); OAI211XLTS U2324 ( .A0(n1682), .A1(n2025), .B0(n1577), .C0(n1680), .Y(n912) ); OAI211XLTS U2325 ( .A0(n1574), .A1(n2073), .B0(n1680), .C0(n1573), .Y(n942) ); OAI21X2TS U2326 ( .A0(n2040), .A1(n2050), .B0(n2089), .Y(n1680) ); NOR2X2TS U2327 ( .A(d_ff2_Y[57]), .B(n2142), .Y(n2141) ); NOR2X2TS U2328 ( .A(d_ff2_Y[59]), .B(n2144), .Y(n2147) ); NOR2XLTS U2329 ( .A(n1476), .B(n2066), .Y(n2058) ); AOI222X4TS U2330 ( .A0(n1837), .A1(d_ff2_Z[54]), .B0(n1821), .B1(d_ff1_Z[54]), .C0(d_ff_Zn[54]), .C1(n1835), .Y(n1836) ); AOI222X4TS U2331 ( .A0(n1837), .A1(d_ff2_Z[47]), .B0(n1719), .B1(d_ff1_Z[47]), .C0(d_ff_Zn[47]), .C1(n1817), .Y(n1714) ); AOI222X4TS U2332 ( .A0(n1837), .A1(d_ff2_Z[49]), .B0(n1719), .B1(d_ff1_Z[49]), .C0(d_ff_Zn[49]), .C1(n1817), .Y(n1712) ); AOI222X4TS U2333 ( .A0(n1837), .A1(d_ff2_Z[50]), .B0(n1719), .B1(d_ff1_Z[50]), .C0(d_ff_Zn[50]), .C1(n1835), .Y(n1711) ); AOI222X4TS U2334 ( .A0(n1837), .A1(d_ff2_Z[51]), .B0(n1719), .B1(d_ff1_Z[51]), .C0(d_ff_Zn[51]), .C1(n1835), .Y(n1710) ); AOI222X4TS U2335 ( .A0(n1837), .A1(d_ff2_Z[48]), .B0(n1719), .B1(d_ff1_Z[48]), .C0(d_ff_Zn[48]), .C1(n1835), .Y(n1705) ); CLKINVX3TS U2336 ( .A(n2102), .Y(n1837) ); CLKINVX3TS U2337 ( .A(n2102), .Y(n1844) ); CLKINVX3TS U2338 ( .A(n2102), .Y(n2183) ); CLKINVX3TS U2339 ( .A(n2102), .Y(n2105) ); AOI222X4TS U2340 ( .A0(d_ff2_Z[6]), .A1(n1734), .B0(d_ff2_Y[6]), .B1(n1854), .C0(d_ff2_X[6]), .C1(n1567), .Y(n1568) ); AOI222X4TS U2341 ( .A0(d_ff2_Z[7]), .A1(n1734), .B0(d_ff2_Y[7]), .B1(n1854), .C0(d_ff2_X[7]), .C1(n1694), .Y(n1566) ); AOI222X4TS U2342 ( .A0(d_ff2_Z[8]), .A1(n1734), .B0(d_ff2_Y[8]), .B1(n1854), .C0(d_ff2_X[8]), .C1(n1694), .Y(n1701) ); AOI222X4TS U2343 ( .A0(d_ff2_Z[10]), .A1(n1734), .B0(d_ff2_Y[10]), .B1(n1854), .C0(d_ff2_X[10]), .C1(n1730), .Y(n1688) ); AOI222X4TS U2344 ( .A0(d_ff2_Z[11]), .A1(n1770), .B0(d_ff2_Y[11]), .B1(n1854), .C0(d_ff2_X[11]), .C1(n1909), .Y(n1696) ); AOI222X4TS U2345 ( .A0(d_ff2_Z[12]), .A1(n1734), .B0(d_ff2_Y[12]), .B1(n1854), .C0(d_ff2_X[12]), .C1(n1910), .Y(n1693) ); AOI222X4TS U2346 ( .A0(d_ff2_Z[13]), .A1(n1734), .B0(d_ff2_Y[13]), .B1(n1854), .C0(d_ff2_X[13]), .C1(n1730), .Y(n1690) ); AOI222X4TS U2347 ( .A0(d_ff2_Z[16]), .A1(n1770), .B0(d_ff2_Y[16]), .B1(n1854), .C0(d_ff2_X[16]), .C1(n1730), .Y(n1687) ); AOI222X4TS U2348 ( .A0(d_ff2_Z[17]), .A1(n1734), .B0(d_ff2_Y[17]), .B1(n1854), .C0(d_ff2_X[17]), .C1(n1752), .Y(n1733) ); OAI21XLTS U2349 ( .A0(n1989), .A1(n1544), .B0(n1543), .Y(n1269) ); OAI21XLTS U2350 ( .A0(n2093), .A1(n1542), .B0(n1541), .Y(n1268) ); CLKBUFX2TS U2351 ( .A(cordic_FSM_state_reg[3]), .Y(n1512) ); NOR4X2TS U2352 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]), .C(n2225), .D(n2222), .Y(n1902) ); OAI21X2TS U2353 ( .A0(n2049), .A1(n2032), .B0(n2065), .Y(n2086) ); INVX2TS U2354 ( .A(n1528), .Y(n1513) ); INVX2TS U2355 ( .A(n1528), .Y(n1514) ); BUFX3TS U2356 ( .A(n1527), .Y(n1528) ); NOR4X4TS U2357 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[1]), .C(n2223), .D(n2229), .Y(ack_add_subt) ); BUFX3TS U2358 ( .A(n1770), .Y(n1792) ); BUFX3TS U2359 ( .A(n1694), .Y(n1916) ); BUFX3TS U2360 ( .A(n1567), .Y(n1694) ); BUFX3TS U2361 ( .A(n1683), .Y(n1736) ); BUFX3TS U2362 ( .A(n1664), .Y(n1683) ); AND3X2TS U2363 ( .A(n1896), .B(n2225), .C(n2229), .Y(n1518) ); OR4X2TS U2364 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[1]), .C(n2223), .D(n1486), .Y(n1519) ); OR2X1TS U2365 ( .A(n1550), .B(d_ff2_Y[55]), .Y(n1549) ); OAI21XLTS U2366 ( .A0(n2065), .A1(d_ff3_LUT_out[25]), .B0(n2060), .Y(n2061) ); INVX2TS U2367 ( .A(d_ff_Yn[57]), .Y(n2125) ); OAI211XLTS U2368 ( .A0(n2188), .A1(n1938), .B0(n1500), .C0(n1952), .Y(n1658) ); OAI21XLTS U2369 ( .A0(n2126), .A1(n1657), .B0(n1650), .Y(n957) ); OAI21XLTS U2370 ( .A0(n2290), .A1(n1657), .B0(n1635), .Y(n971) ); OAI21XLTS U2371 ( .A0(n2277), .A1(n1604), .B0(n1585), .Y(n997) ); OAI21XLTS U2372 ( .A0(n2264), .A1(n1624), .B0(n1616), .Y(n1023) ); OAI21XLTS U2373 ( .A0(n2251), .A1(n1629), .B0(n1618), .Y(n1049) ); OAI21XLTS U2374 ( .A0(n2244), .A1(n1645), .B0(n1631), .Y(n1063) ); OAI21XLTS U2375 ( .A0(n2234), .A1(n1860), .B0(n1522), .Y(add_subt_dataA[52]) ); BUFX3TS U2376 ( .A(n2154), .Y(n2215) ); INVX2TS U2377 ( .A(n2215), .Y(n2217) ); NOR2X2TS U2378 ( .A(d_ff2_Y[52]), .B(n2188), .Y(n2136) ); NAND2X1TS U2379 ( .A(d_ff2_Y[53]), .B(n1495), .Y(n1520) ); AOI22X1TS U2380 ( .A0(n1500), .A1(n1480), .B0(n2136), .B1(n1520), .Y(n1534) ); AOI22X1TS U2381 ( .A0(n1550), .A1(d_ff2_Y[55]), .B0(n1503), .B1(n1549), .Y( n2139) ); INVX2TS U2382 ( .A(d_ff2_Y[56]), .Y(n2138) ); INVX2TS U2383 ( .A(d_ff2_Y[58]), .Y(n2127) ); INVX2TS U2384 ( .A(d_ff2_Y[60]), .Y(n2146) ); XOR2X1TS U2385 ( .A(d_ff2_Y[62]), .B(n2149), .Y(n1521) ); BUFX3TS U2386 ( .A(n1519), .Y(n2156) ); BUFX3TS U2387 ( .A(n2156), .Y(n2044) ); BUFX3TS U2388 ( .A(n2044), .Y(n2153) ); OR2X2TS U2389 ( .A(sel_mux_2_reg[1]), .B(n2230), .Y(n1860) ); NAND2X1TS U2390 ( .A(n2230), .B(sel_mux_2_reg[1]), .Y(n1906) ); BUFX3TS U2391 ( .A(n1881), .Y(n1878) ); NOR2X1TS U2392 ( .A(sel_mux_2_reg[0]), .B(sel_mux_2_reg[1]), .Y(n1567) ); BUFX3TS U2393 ( .A(n1909), .Y(n1919) ); AOI22X1TS U2394 ( .A0(n1878), .A1(d_ff2_Z[52]), .B0(d_ff2_X[52]), .B1(n1919), .Y(n1522) ); AOI22X1TS U2395 ( .A0(d_ff2_X[55]), .A1(n1916), .B0(d_ff2_Z[55]), .B1(n1878), .Y(n1523) ); NOR2X2TS U2396 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[1]), .Y(n1896) ); INVX2TS U2397 ( .A(n1524), .Y(n2308) ); INVX2TS U2398 ( .A(n1529), .Y(n2302) ); INVX2TS U2399 ( .A(n1901), .Y(n2339) ); INVX2TS U2400 ( .A(n1901), .Y(n2342) ); INVX2TS U2401 ( .A(n1524), .Y(n2347) ); INVX2TS U2402 ( .A(n1492), .Y(n2348) ); INVX2TS U2403 ( .A(n1524), .Y(n2349) ); INVX2TS U2404 ( .A(n1901), .Y(n2341) ); INVX2TS U2405 ( .A(n1528), .Y(n2333) ); INVX2TS U2406 ( .A(n1528), .Y(n2334) ); INVX2TS U2407 ( .A(n1528), .Y(n2335) ); INVX2TS U2408 ( .A(n1528), .Y(n2317) ); INVX2TS U2409 ( .A(n1529), .Y(n2324) ); INVX2TS U2410 ( .A(n1529), .Y(n2354) ); INVX2TS U2411 ( .A(n1492), .Y(n2355) ); INVX2TS U2412 ( .A(n1529), .Y(n2365) ); INVX2TS U2413 ( .A(n1525), .Y(n2364) ); INVX2TS U2414 ( .A(n1530), .Y(n2361) ); INVX2TS U2415 ( .A(n1528), .Y(n2360) ); INVX2TS U2416 ( .A(n1525), .Y(n2343) ); INVX2TS U2417 ( .A(n1528), .Y(n2314) ); INVX2TS U2418 ( .A(n1528), .Y(n2315) ); INVX2TS U2419 ( .A(n1528), .Y(n2316) ); INVX2TS U2420 ( .A(n1530), .Y(n2329) ); INVX2TS U2421 ( .A(n1530), .Y(n2330) ); INVX2TS U2422 ( .A(n1529), .Y(n2326) ); INVX2TS U2423 ( .A(n1530), .Y(n2327) ); INVX2TS U2424 ( .A(n1526), .Y(n2366) ); NAND2X1TS U2425 ( .A(n2229), .B(n2222), .Y(n1930) ); INVX2TS U2426 ( .A(n1930), .Y(n1532) ); AOI21X1TS U2427 ( .A0(cordic_FSM_state_reg[3]), .A1(cordic_FSM_state_reg[2]), .B0(n2222), .Y(n1531) ); AOI32X1TS U2428 ( .A0(beg_fsm_cordic), .A1(cordic_FSM_state_reg[0]), .A2( n1532), .B0(n2223), .B1(n1531), .Y(n1533) ); BUFX3TS U2429 ( .A(n2156), .Y(n2154) ); BUFX3TS U2430 ( .A(n2154), .Y(n2091) ); INVX2TS U2431 ( .A(ack_add_subt), .Y(n1575) ); BUFX3TS U2432 ( .A(n2154), .Y(n2171) ); INVX2TS U2433 ( .A(n2171), .Y(n2221) ); AND3X2TS U2434 ( .A(cordic_FSM_state_reg[2]), .B(n1896), .C(n2229), .Y(n2120) ); NAND2X1TS U2435 ( .A(n2170), .B(sel_mux_1_reg), .Y(n2181) ); BUFX3TS U2436 ( .A(n2182), .Y(n2166) ); OA22X1TS U2437 ( .A0(n2106), .A1(d_ff2_X[19]), .B0(d_ff_Xn[19]), .B1(n2166), .Y(n658) ); BUFX3TS U2438 ( .A(n2182), .Y(n2177) ); OA22X1TS U2439 ( .A0(n2176), .A1(d_ff2_X[36]), .B0(d_ff_Xn[36]), .B1(n2177), .Y(n624) ); CLKBUFX2TS U2440 ( .A(n2176), .Y(n2102) ); OA22X1TS U2441 ( .A0(n2102), .A1(d_ff2_X[48]), .B0(d_ff_Xn[48]), .B1(n2177), .Y(n600) ); OA22X1TS U2442 ( .A0(n2120), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n2166), .Y(n638) ); CLKBUFX2TS U2443 ( .A(n2176), .Y(n2106) ); OA22X1TS U2444 ( .A0(n2106), .A1(d_ff2_X[49]), .B0(d_ff_Xn[49]), .B1(n2177), .Y(n598) ); OA22X1TS U2445 ( .A0(n2120), .A1(d_ff2_X[26]), .B0(d_ff_Xn[26]), .B1(n2166), .Y(n644) ); OA22X1TS U2446 ( .A0(n2120), .A1(d_ff2_X[31]), .B0(d_ff_Xn[31]), .B1(n2166), .Y(n634) ); OA22X1TS U2447 ( .A0(n2120), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n2166), .Y(n640) ); OA22X1TS U2448 ( .A0(n2120), .A1(d_ff2_X[24]), .B0(d_ff_Xn[24]), .B1(n2166), .Y(n648) ); BUFX3TS U2449 ( .A(n2181), .Y(n2180) ); BUFX3TS U2450 ( .A(n2180), .Y(n2185) ); OA22X1TS U2451 ( .A0(n2120), .A1(d_ff2_X[14]), .B0(d_ff_Xn[14]), .B1(n2185), .Y(n668) ); OA22X1TS U2452 ( .A0(n2176), .A1(d_ff2_X[13]), .B0(d_ff_Xn[13]), .B1(n2185), .Y(n670) ); CLKBUFX2TS U2453 ( .A(n2120), .Y(n2178) ); BUFX3TS U2454 ( .A(n2181), .Y(n2182) ); BUFX3TS U2455 ( .A(n2182), .Y(n2131) ); OA22X1TS U2456 ( .A0(n2178), .A1(d_ff2_X[0]), .B0(d_ff_Xn[0]), .B1(n2131), .Y(n696) ); INVX2TS U2457 ( .A(n1896), .Y(n1929) ); CLKBUFX2TS U2458 ( .A(n2008), .Y(n2018) ); INVX2TS U2459 ( .A(n2018), .Y(n2022) ); XOR2X1TS U2460 ( .A(data_output2_63_), .B(n1536), .Y(n1537) ); CLKBUFX2TS U2461 ( .A(n2008), .Y(n2016) ); CLKBUFX2TS U2462 ( .A(n2016), .Y(n2021) ); NAND2X2TS U2463 ( .A(n2100), .B(n1499), .Y(n1676) ); INVX2TS U2464 ( .A(n2055), .Y(n2080) ); NAND3X1TS U2465 ( .A(n2055), .B(n2188), .C(n1495), .Y(n1569) ); INVX2TS U2466 ( .A(n1569), .Y(n2042) ); OAI211X4TS U2467 ( .A0(n1505), .A1(n1496), .B0(n2076), .C0(n2080), .Y(n2053) ); NAND2X1TS U2468 ( .A(n1538), .B(n2053), .Y(n919) ); BUFX3TS U2469 ( .A(n2154), .Y(n2152) ); INVX2TS U2470 ( .A(n1476), .Y(n2101) ); XNOR2X1TS U2471 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out), .Y(n1540) ); CLKXOR2X2TS U2472 ( .A(d_ff1_shift_region_flag_out[0]), .B(n1540), .Y(n1989) ); NAND4X1TS U2473 ( .A(cordic_FSM_state_reg[3]), .B(n1896), .C(ready_add_subt), .D(n2225), .Y(n1990) ); NOR2X2TS U2474 ( .A(n1900), .B(n1990), .Y(n1974) ); BUFX3TS U2475 ( .A(n1974), .Y(n1979) ); BUFX3TS U2476 ( .A(n1979), .Y(n1987) ); OAI2BB2XLTS U2477 ( .B0(n1987), .B1(n2129), .A0N(n1979), .A1N( result_add_subt[60]), .Y(n1141) ); OAI2BB2XLTS U2478 ( .B0(n1987), .B1(n2128), .A0N(n1976), .A1N( result_add_subt[59]), .Y(n1142) ); OAI2BB2XLTS U2479 ( .B0(n1987), .B1(n2130), .A0N(n1976), .A1N( result_add_subt[61]), .Y(n1140) ); OAI2BB2XLTS U2480 ( .B0(n1987), .B1(n2132), .A0N(n1976), .A1N( result_add_subt[62]), .Y(n1139) ); INVX2TS U2481 ( .A(rst), .Y(n564) ); NOR4X1TS U2482 ( .A(cordic_FSM_state_reg[3]), .B(n2223), .C(n1486), .D(n2222), .Y(beg_add_subt) ); NOR3X2TS U2483 ( .A(n1505), .B(cont_iter_out[2]), .C(n1500), .Y(n2040) ); INVX2TS U2484 ( .A(n2037), .Y(n2093) ); INVX2TS U2485 ( .A(n1902), .Y(n1899) ); NAND2X2TS U2486 ( .A(n2100), .B(n1496), .Y(n2078) ); INVX2TS U2487 ( .A(n2078), .Y(n2064) ); NOR2X2TS U2488 ( .A(d_ff2_X[52]), .B(n2188), .Y(n2191) ); NAND2X1TS U2489 ( .A(d_ff2_X[53]), .B(n1495), .Y(n1546) ); AOI22X1TS U2490 ( .A0(n1499), .A1(n2228), .B0(n2191), .B1(n1546), .Y(n2193) ); AOI2BB1X1TS U2491 ( .A0N(n2197), .A1N(d_ff2_X[55]), .B0(n2196), .Y(n1548) ); BUFX3TS U2492 ( .A(n2154), .Y(n2087) ); NOR2X2TS U2493 ( .A(n2087), .B(n1478), .Y(n2027) ); AOI22X1TS U2494 ( .A0(n1548), .A1(n2027), .B0(d_ff3_sh_x_out[55]), .B1(n2091), .Y(n1547) ); OAI31X1TS U2495 ( .A0(n2049), .A1(n1548), .A2(n2087), .B0(n1547), .Y(n578) ); INVX2TS U2496 ( .A(n2027), .Y(n1682) ); OAI2BB1X1TS U2497 ( .A0N(d_ff2_Y[55]), .A1N(n1550), .B0(n1549), .Y(n1552) ); NAND2X1TS U2498 ( .A(n2227), .B(n1676), .Y(n2036) ); NOR2XLTS U2499 ( .A(n2227), .B(n1496), .Y(n1553) ); NAND2BX1TS U2500 ( .AN(n1605), .B(sel_mux_3_reg), .Y(n1560) ); CLKBUFX2TS U2501 ( .A(n1605), .Y(n1640) ); BUFX3TS U2502 ( .A(n1640), .Y(n1652) ); AOI22X1TS U2503 ( .A0(d_ff_Xn[63]), .A1(n1555), .B0(data_output2_63_), .B1( n1652), .Y(n1556) ); AOI22X1TS U2504 ( .A0(d_ff_Xn[61]), .A1(n1555), .B0(sign_inv_out[61]), .B1( n1652), .Y(n1557) ); INVX2TS U2505 ( .A(n2180), .Y(n2118) ); AOI222X1TS U2506 ( .A0(n2187), .A1(d_ff2_Z[6]), .B0(n1683), .B1(d_ff1_Z[6]), .C0(d_ff_Zn[6]), .C1(n2118), .Y(n1558) ); INVX2TS U2507 ( .A(n1558), .Y(n883) ); AOI22X1TS U2508 ( .A0(d_ff_Xn[60]), .A1(n1555), .B0(sign_inv_out[60]), .B1( n1652), .Y(n1559) ); AOI22X1TS U2509 ( .A0(d_ff_Xn[62]), .A1(n1555), .B0(sign_inv_out[62]), .B1( n1652), .Y(n1561) ); NAND2X2TS U2510 ( .A(n1499), .B(n2227), .Y(n2025) ); NOR2X2TS U2511 ( .A(n1504), .B(n2025), .Y(n2099) ); NAND2X1TS U2512 ( .A(n2100), .B(n2099), .Y(n2082) ); OAI21X2TS U2513 ( .A0(n1500), .A1(n2080), .B0(n2082), .Y(n2038) ); NAND2X1TS U2514 ( .A(n2065), .B(n2038), .Y(n2062) ); NAND2X2TS U2515 ( .A(n2099), .B(n2188), .Y(n2088) ); INVX2TS U2516 ( .A(n2088), .Y(n2051) ); NAND2X1TS U2517 ( .A(n1505), .B(n2227), .Y(n1563) ); OAI32X4TS U2518 ( .A0(n1500), .A1(n2100), .A2(n1563), .B0(n2080), .B1(n1496), .Y(n2039) ); INVX2TS U2519 ( .A(n1699), .Y(n1571) ); BUFX3TS U2520 ( .A(n1770), .Y(n1734) ); INVX2TS U2521 ( .A(n1565), .Y(add_subt_dataA[3]) ); INVX2TS U2522 ( .A(n1880), .Y(n1854) ); INVX2TS U2523 ( .A(n1566), .Y(add_subt_dataA[7]) ); INVX2TS U2524 ( .A(n1568), .Y(add_subt_dataA[6]) ); NAND2X2TS U2525 ( .A(cont_iter_out[2]), .B(n2027), .Y(n2073) ); NAND2X1TS U2526 ( .A(n2065), .B(n2039), .Y(n2047) ); NAND2X1TS U2527 ( .A(n2082), .B(n1569), .Y(n2050) ); NOR2X1TS U2528 ( .A(n2087), .B(n2050), .Y(n2031) ); OAI31X1TS U2529 ( .A0(n1505), .A1(cont_iter_out[2]), .A2(n2078), .B0(n2031), .Y(n2029) ); INVX2TS U2530 ( .A(n1678), .Y(n1574) ); OAI22X1TS U2531 ( .A0(n2076), .A1(d_ff3_LUT_out[3]), .B0(n1572), .B1(n2048), .Y(n1573) ); NOR3X2TS U2532 ( .A(n1476), .B(n2231), .C(n1575), .Y(n1908) ); INVX2TS U2533 ( .A(n2073), .Y(n2063) ); AOI21X1TS U2534 ( .A0(d_ff3_LUT_out[33]), .A1(n2091), .B0(n2063), .Y(n1577) ); BUFX3TS U2535 ( .A(n1475), .Y(n1599) ); BUFX3TS U2536 ( .A(n1555), .Y(n1597) ); BUFX3TS U2537 ( .A(n1605), .Y(n1654) ); AOI22X1TS U2538 ( .A0(d_ff_Xn[47]), .A1(n1597), .B0(sign_inv_out[47]), .B1( n1654), .Y(n1578) ); BUFX3TS U2539 ( .A(n1605), .Y(n1601) ); AOI22X1TS U2540 ( .A0(d_ff_Xn[41]), .A1(n1597), .B0(sign_inv_out[41]), .B1( n1601), .Y(n1579) ); AOI22X1TS U2541 ( .A0(d_ff_Xn[49]), .A1(n1597), .B0(sign_inv_out[49]), .B1( n1654), .Y(n1580) ); AOI22X1TS U2542 ( .A0(d_ff_Xn[44]), .A1(n1597), .B0(sign_inv_out[44]), .B1( n1654), .Y(n1581) ); BUFX3TS U2543 ( .A(n1475), .Y(n1604) ); BUFX3TS U2544 ( .A(n1555), .Y(n1602) ); AOI22X1TS U2545 ( .A0(d_ff_Xn[35]), .A1(n1602), .B0(sign_inv_out[35]), .B1( n1601), .Y(n1582) ); AOI22X1TS U2546 ( .A0(d_ff_Xn[37]), .A1(n1602), .B0(sign_inv_out[37]), .B1( n1601), .Y(n1583) ); AOI22X1TS U2547 ( .A0(d_ff_Xn[45]), .A1(n1597), .B0(sign_inv_out[45]), .B1( n1654), .Y(n1584) ); AOI22X1TS U2548 ( .A0(d_ff_Xn[38]), .A1(n1602), .B0(sign_inv_out[38]), .B1( n1601), .Y(n1585) ); AOI22X1TS U2549 ( .A0(d_ff_Xn[39]), .A1(n1602), .B0(sign_inv_out[39]), .B1( n1601), .Y(n1586) ); BUFX3TS U2550 ( .A(n1605), .Y(n1619) ); AOI22X1TS U2551 ( .A0(d_ff_Xn[32]), .A1(n1602), .B0(sign_inv_out[32]), .B1( n1619), .Y(n1587) ); AOI22X1TS U2552 ( .A0(d_ff_Xn[31]), .A1(n1602), .B0(sign_inv_out[31]), .B1( n1619), .Y(n1588) ); AOI22X1TS U2553 ( .A0(d_ff_Xn[46]), .A1(n1597), .B0(sign_inv_out[46]), .B1( n1654), .Y(n1589) ); AOI22X1TS U2554 ( .A0(d_ff_Xn[48]), .A1(n1597), .B0(sign_inv_out[48]), .B1( n1654), .Y(n1590) ); AOI22X1TS U2555 ( .A0(d_ff_Xn[30]), .A1(n1602), .B0(sign_inv_out[30]), .B1( n1619), .Y(n1591) ); AOI22X1TS U2556 ( .A0(d_ff_Xn[43]), .A1(n1597), .B0(sign_inv_out[43]), .B1( n1601), .Y(n1592) ); AOI22X1TS U2557 ( .A0(d_ff_Xn[36]), .A1(n1602), .B0(sign_inv_out[36]), .B1( n1601), .Y(n1593) ); BUFX3TS U2558 ( .A(n1475), .Y(n1624) ); BUFX3TS U2559 ( .A(n1555), .Y(n1622) ); AOI22X1TS U2560 ( .A0(d_ff_Xn[29]), .A1(n1622), .B0(sign_inv_out[29]), .B1( n1619), .Y(n1594) ); AOI22X1TS U2561 ( .A0(d_ff_Xn[42]), .A1(n1597), .B0(sign_inv_out[42]), .B1( n1601), .Y(n1595) ); AOI22X1TS U2562 ( .A0(d_ff_Xn[28]), .A1(n1622), .B0(sign_inv_out[28]), .B1( n1619), .Y(n1596) ); AOI22X1TS U2563 ( .A0(d_ff_Xn[40]), .A1(n1597), .B0(sign_inv_out[40]), .B1( n1601), .Y(n1598) ); AOI22X1TS U2564 ( .A0(d_ff_Xn[33]), .A1(n1602), .B0(sign_inv_out[33]), .B1( n1619), .Y(n1600) ); AOI22X1TS U2565 ( .A0(d_ff_Xn[34]), .A1(n1602), .B0(sign_inv_out[34]), .B1( n1601), .Y(n1603) ); BUFX3TS U2566 ( .A(n1605), .Y(n1626) ); AOI22X1TS U2567 ( .A0(d_ff_Xn[21]), .A1(n1622), .B0(sign_inv_out[21]), .B1( n1626), .Y(n1606) ); BUFX3TS U2568 ( .A(n1475), .Y(n1629) ); BUFX3TS U2569 ( .A(n1555), .Y(n1627) ); AOI22X1TS U2570 ( .A0(d_ff_Xn[19]), .A1(n1627), .B0(sign_inv_out[19]), .B1( n1626), .Y(n1607) ); AOI22X1TS U2571 ( .A0(d_ff_Xn[27]), .A1(n1622), .B0(sign_inv_out[27]), .B1( n1619), .Y(n1608) ); AOI22X1TS U2572 ( .A0(d_ff_Xn[23]), .A1(n1622), .B0(sign_inv_out[23]), .B1( n1626), .Y(n1609) ); AOI22X1TS U2573 ( .A0(d_ff_Xn[20]), .A1(n1622), .B0(sign_inv_out[20]), .B1( n1626), .Y(n1610) ); BUFX3TS U2574 ( .A(n1640), .Y(n1642) ); AOI22X1TS U2575 ( .A0(d_ff_Xn[11]), .A1(n1627), .B0(sign_inv_out[11]), .B1( n1642), .Y(n1611) ); AOI22X1TS U2576 ( .A0(d_ff_Xn[17]), .A1(n1627), .B0(sign_inv_out[17]), .B1( n1626), .Y(n1612) ); AOI22X1TS U2577 ( .A0(d_ff_Xn[26]), .A1(n1622), .B0(sign_inv_out[26]), .B1( n1619), .Y(n1613) ); AOI22X1TS U2578 ( .A0(d_ff_Xn[15]), .A1(n1627), .B0(sign_inv_out[15]), .B1( n1626), .Y(n1614) ); AOI22X1TS U2579 ( .A0(d_ff_Xn[14]), .A1(n1627), .B0(sign_inv_out[14]), .B1( n1626), .Y(n1615) ); AOI22X1TS U2580 ( .A0(d_ff_Xn[25]), .A1(n1622), .B0(sign_inv_out[25]), .B1( n1619), .Y(n1616) ); AOI22X1TS U2581 ( .A0(d_ff_Xn[13]), .A1(n1627), .B0(sign_inv_out[13]), .B1( n1642), .Y(n1617) ); AOI22X1TS U2582 ( .A0(d_ff_Xn[12]), .A1(n1627), .B0(sign_inv_out[12]), .B1( n1642), .Y(n1618) ); AOI22X1TS U2583 ( .A0(d_ff_Xn[24]), .A1(n1622), .B0(sign_inv_out[24]), .B1( n1619), .Y(n1620) ); AOI22X1TS U2584 ( .A0(d_ff_Xn[10]), .A1(n1627), .B0(sign_inv_out[10]), .B1( n1642), .Y(n1621) ); AOI22X1TS U2585 ( .A0(d_ff_Xn[22]), .A1(n1622), .B0(sign_inv_out[22]), .B1( n1626), .Y(n1623) ); AOI22X1TS U2586 ( .A0(d_ff_Xn[16]), .A1(n1627), .B0(sign_inv_out[16]), .B1( n1626), .Y(n1625) ); AOI22X1TS U2587 ( .A0(d_ff_Xn[18]), .A1(n1627), .B0(sign_inv_out[18]), .B1( n1626), .Y(n1628) ); BUFX3TS U2588 ( .A(n1475), .Y(n1645) ); BUFX3TS U2589 ( .A(n1555), .Y(n1643) ); AOI22X1TS U2590 ( .A0(d_ff_Xn[1]), .A1(n1643), .B0(sign_inv_out[1]), .B1( n1640), .Y(n1630) ); AOI22X1TS U2591 ( .A0(d_ff_Xn[5]), .A1(n1643), .B0(sign_inv_out[5]), .B1( n1642), .Y(n1631) ); AOI22X1TS U2592 ( .A0(d_ff_Xn[2]), .A1(n1643), .B0(sign_inv_out[2]), .B1( n1640), .Y(n1632) ); BUFX3TS U2593 ( .A(n1475), .Y(n1657) ); BUFX3TS U2594 ( .A(n1555), .Y(n1655) ); AOI22X1TS U2595 ( .A0(d_ff_Xn[50]), .A1(n1655), .B0(sign_inv_out[50]), .B1( n1654), .Y(n1633) ); AOI22X1TS U2596 ( .A0(d_ff_Xn[4]), .A1(n1643), .B0(sign_inv_out[4]), .B1( n1642), .Y(n1634) ); AOI22X1TS U2597 ( .A0(d_ff_Xn[51]), .A1(n1655), .B0(sign_inv_out[51]), .B1( n1654), .Y(n1635) ); AOI22X1TS U2598 ( .A0(d_ff_Xn[9]), .A1(n1643), .B0(sign_inv_out[9]), .B1( n1642), .Y(n1636) ); AOI22X1TS U2599 ( .A0(d_ff_Xn[0]), .A1(n1643), .B0(sign_inv_out[0]), .B1( n1640), .Y(n1637) ); AOI22X1TS U2600 ( .A0(d_ff_Xn[7]), .A1(n1643), .B0(sign_inv_out[7]), .B1( n1642), .Y(n1638) ); AOI22X1TS U2601 ( .A0(d_ff_Xn[6]), .A1(n1643), .B0(sign_inv_out[6]), .B1( n1642), .Y(n1639) ); AOI22X1TS U2602 ( .A0(d_ff_Xn[3]), .A1(n1643), .B0(sign_inv_out[3]), .B1( n1640), .Y(n1641) ); AOI22X1TS U2603 ( .A0(d_ff_Xn[8]), .A1(n1643), .B0(sign_inv_out[8]), .B1( n1642), .Y(n1644) ); AOI22X1TS U2604 ( .A0(d_ff_Xn[54]), .A1(n1655), .B0(sign_inv_out[54]), .B1( n1652), .Y(n1646) ); AOI22X1TS U2605 ( .A0(d_ff_Xn[52]), .A1(n1655), .B0(sign_inv_out[52]), .B1( n1654), .Y(n1647) ); AOI22X1TS U2606 ( .A0(d_ff_Xn[55]), .A1(n1655), .B0(sign_inv_out[55]), .B1( n1652), .Y(n1648) ); AOI22X1TS U2607 ( .A0(d_ff_Xn[57]), .A1(n1655), .B0(sign_inv_out[57]), .B1( n1652), .Y(n1649) ); AOI22X1TS U2608 ( .A0(d_ff_Xn[58]), .A1(n1655), .B0(sign_inv_out[58]), .B1( n1652), .Y(n1650) ); AOI22X1TS U2609 ( .A0(d_ff_Xn[56]), .A1(n1655), .B0(sign_inv_out[56]), .B1( n1652), .Y(n1651) ); AOI22X1TS U2610 ( .A0(d_ff_Xn[59]), .A1(n1655), .B0(sign_inv_out[59]), .B1( n1652), .Y(n1653) ); AOI22X1TS U2611 ( .A0(d_ff_Xn[53]), .A1(n1655), .B0(sign_inv_out[53]), .B1( n1654), .Y(n1656) ); NAND2X1TS U2612 ( .A(cont_var_out[1]), .B(n2231), .Y(n1925) ); NOR2X1TS U2613 ( .A(n1476), .B(n1925), .Y(n1956) ); NAND2X2TS U2614 ( .A(ack_add_subt), .B(n1956), .Y(n1938) ); NAND3X1TS U2615 ( .A(n1932), .B(n2223), .C(n2229), .Y(n1951) ); BUFX3TS U2616 ( .A(n1951), .Y(n1950) ); BUFX3TS U2617 ( .A(n1950), .Y(n1952) ); AOI222X1TS U2618 ( .A0(n1833), .A1(d_ff2_Z[8]), .B0(n1683), .B1(d_ff1_Z[8]), .C0(d_ff_Zn[8]), .C1(n1739), .Y(n1659) ); INVX2TS U2619 ( .A(n1659), .Y(n881) ); AOI222X1TS U2620 ( .A0(n1717), .A1(d_ff2_Z[10]), .B0(n1683), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n1739), .Y(n1660) ); INVX2TS U2621 ( .A(n1660), .Y(n879) ); AOI222X1TS U2622 ( .A0(n2108), .A1(d_ff2_Z[11]), .B0(n1683), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n1739), .Y(n1661) ); INVX2TS U2623 ( .A(n1661), .Y(n878) ); AOI222X1TS U2624 ( .A0(n1833), .A1(d_ff2_Z[9]), .B0(n1683), .B1(d_ff1_Z[9]), .C0(d_ff_Zn[9]), .C1(n1739), .Y(n1662) ); INVX2TS U2625 ( .A(n1662), .Y(n880) ); AOI222X1TS U2626 ( .A0(n1717), .A1(d_ff2_Z[7]), .B0(n1683), .B1(d_ff1_Z[7]), .C0(d_ff_Zn[7]), .C1(n1739), .Y(n1663) ); INVX2TS U2627 ( .A(n1663), .Y(n882) ); BUFX3TS U2628 ( .A(n1664), .Y(n1674) ); AOI222X1TS U2629 ( .A0(n2108), .A1(d_ff2_Z[25]), .B0(n1674), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n1817), .Y(n1665) ); INVX2TS U2630 ( .A(n1665), .Y(n864) ); AOI222X1TS U2631 ( .A0(n1724), .A1(d_ff2_Z[24]), .B0(n1674), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n1819), .Y(n1666) ); INVX2TS U2632 ( .A(n1666), .Y(n865) ); AOI222X1TS U2633 ( .A0(n1724), .A1(d_ff2_Z[27]), .B0(n1674), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n1835), .Y(n1667) ); INVX2TS U2634 ( .A(n1667), .Y(n862) ); AOI222X1TS U2635 ( .A0(n1833), .A1(d_ff2_Z[32]), .B0(n1674), .B1(d_ff1_Z[32]), .C0(d_ff_Zn[32]), .C1(n1817), .Y(n1668) ); INVX2TS U2636 ( .A(n1668), .Y(n857) ); AOI222X1TS U2637 ( .A0(n1724), .A1(d_ff2_Z[26]), .B0(n1674), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n1835), .Y(n1669) ); INVX2TS U2638 ( .A(n1669), .Y(n863) ); AOI222X1TS U2639 ( .A0(n1717), .A1(d_ff2_Z[30]), .B0(n1674), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n1817), .Y(n1670) ); INVX2TS U2640 ( .A(n1670), .Y(n859) ); AOI222X1TS U2641 ( .A0(n2108), .A1(d_ff2_Z[33]), .B0(n1674), .B1(d_ff1_Z[33]), .C0(d_ff_Zn[33]), .C1(n1835), .Y(n1671) ); INVX2TS U2642 ( .A(n1671), .Y(n856) ); AOI222X1TS U2643 ( .A0(n1833), .A1(d_ff2_Z[29]), .B0(n1674), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n1817), .Y(n1672) ); INVX2TS U2644 ( .A(n1672), .Y(n860) ); AOI222X1TS U2645 ( .A0(n1717), .A1(d_ff2_Z[28]), .B0(n1674), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n1835), .Y(n1673) ); INVX2TS U2646 ( .A(n1673), .Y(n861) ); AOI222X1TS U2647 ( .A0(n2108), .A1(d_ff2_Z[31]), .B0(n1674), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n1817), .Y(n1675) ); INVX2TS U2648 ( .A(n1675), .Y(n858) ); OAI211XLTS U2649 ( .A0(n1676), .A1(n1938), .B0(cont_iter_out[2]), .C0(n1952), .Y(n1677) ); OAI31X1TS U2650 ( .A0(n1938), .A1(n1490), .A2(n2025), .B0(n1677), .Y(n1339) ); NAND2X1TS U2651 ( .A(n2064), .B(n2227), .Y(n2032) ); NOR3X1TS U2652 ( .A(cont_iter_out[0]), .B(n2025), .C(n1682), .Y(n2035) ); AOI222X1TS U2653 ( .A0(n2108), .A1(d_ff2_Z[13]), .B0(n1736), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n1739), .Y(n1684) ); INVX2TS U2654 ( .A(n1684), .Y(n876) ); AOI222X1TS U2655 ( .A0(n1833), .A1(d_ff2_Z[12]), .B0(n1736), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n1739), .Y(n1685) ); INVX2TS U2656 ( .A(n1685), .Y(n877) ); INVX2TS U2657 ( .A(n1686), .Y(n884) ); BUFX3TS U2658 ( .A(n1694), .Y(n1730) ); INVX2TS U2659 ( .A(n1687), .Y(add_subt_dataA[16]) ); INVX2TS U2660 ( .A(n1688), .Y(add_subt_dataA[10]) ); INVX2TS U2661 ( .A(n1689), .Y(add_subt_dataA[1]) ); INVX2TS U2662 ( .A(n1690), .Y(add_subt_dataA[13]) ); INVX2TS U2663 ( .A(n1860), .Y(n1753) ); BUFX3TS U2664 ( .A(n1694), .Y(n1910) ); INVX2TS U2665 ( .A(n1691), .Y(add_subt_dataA[15]) ); BUFX3TS U2666 ( .A(n1770), .Y(n1911) ); INVX2TS U2667 ( .A(n1692), .Y(add_subt_dataA[5]) ); INVX2TS U2668 ( .A(n1693), .Y(add_subt_dataA[12]) ); BUFX3TS U2669 ( .A(n1694), .Y(n1909) ); INVX2TS U2670 ( .A(n1695), .Y(add_subt_dataA[14]) ); INVX2TS U2671 ( .A(n1696), .Y(add_subt_dataA[11]) ); INVX2TS U2672 ( .A(n1697), .Y(add_subt_dataA[4]) ); INVX2TS U2673 ( .A(n1698), .Y(add_subt_dataA[2]) ); AOI211X1TS U2674 ( .A0(n1699), .A1(n2195), .B0(n2086), .C0(n2038), .Y(n2052) ); INVX2TS U2675 ( .A(n1701), .Y(add_subt_dataA[8]) ); BUFX3TS U2676 ( .A(n1736), .Y(n1723) ); AOI222X1TS U2677 ( .A0(n1724), .A1(d_ff2_Z[21]), .B0(n1723), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n1819), .Y(n1702) ); INVX2TS U2678 ( .A(n1702), .Y(n868) ); BUFX3TS U2679 ( .A(n1736), .Y(n1719) ); AOI222X1TS U2680 ( .A0(n2183), .A1(d_ff2_Z[44]), .B0(n1719), .B1(d_ff1_Z[44]), .C0(d_ff_Zn[44]), .C1(n1840), .Y(n1703) ); INVX2TS U2681 ( .A(n1703), .Y(n845) ); INVX2TS U2682 ( .A(n1704), .Y(n836) ); INVX2TS U2683 ( .A(n1705), .Y(n841) ); INVX2TS U2684 ( .A(n1706), .Y(n837) ); AOI222X1TS U2685 ( .A0(n1724), .A1(d_ff2_Z[23]), .B0(n1723), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n1819), .Y(n1707) ); INVX2TS U2686 ( .A(n1707), .Y(n866) ); AOI222X1TS U2687 ( .A0(n1717), .A1(d_ff2_Z[15]), .B0(n1723), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n1739), .Y(n1708) ); INVX2TS U2688 ( .A(n1708), .Y(n874) ); AOI222X1TS U2689 ( .A0(n2105), .A1(d_ff2_Z[45]), .B0(n1719), .B1(d_ff1_Z[45]), .C0(d_ff_Zn[45]), .C1(n1842), .Y(n1709) ); INVX2TS U2690 ( .A(n1709), .Y(n844) ); INVX2TS U2691 ( .A(n1710), .Y(n838) ); INVX2TS U2692 ( .A(n1711), .Y(n839) ); INVX2TS U2693 ( .A(n1712), .Y(n840) ); AOI222X1TS U2694 ( .A0(n1724), .A1(d_ff2_Z[19]), .B0(n1723), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n1819), .Y(n1713) ); INVX2TS U2695 ( .A(n1713), .Y(n870) ); INVX2TS U2696 ( .A(n1714), .Y(n842) ); AOI222X1TS U2697 ( .A0(n2108), .A1(d_ff2_Z[14]), .B0(n1723), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n1739), .Y(n1715) ); INVX2TS U2698 ( .A(n1715), .Y(n875) ); AOI222X1TS U2699 ( .A0(n1724), .A1(d_ff2_Z[17]), .B0(n1723), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n1819), .Y(n1716) ); INVX2TS U2700 ( .A(n1716), .Y(n872) ); AOI222X1TS U2701 ( .A0(n1833), .A1(d_ff2_Z[16]), .B0(n1723), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n1819), .Y(n1718) ); INVX2TS U2702 ( .A(n1718), .Y(n873) ); AOI222X1TS U2703 ( .A0(n1844), .A1(d_ff2_Z[46]), .B0(n1719), .B1(d_ff1_Z[46]), .C0(d_ff_Zn[46]), .C1(n1835), .Y(n1720) ); INVX2TS U2704 ( .A(n1720), .Y(n843) ); AOI222X1TS U2705 ( .A0(n1724), .A1(d_ff2_Z[22]), .B0(n1723), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n1819), .Y(n1721) ); INVX2TS U2706 ( .A(n1721), .Y(n867) ); AOI222X1TS U2707 ( .A0(n1724), .A1(d_ff2_Z[18]), .B0(n1723), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n1819), .Y(n1722) ); INVX2TS U2708 ( .A(n1722), .Y(n871) ); AOI222X1TS U2709 ( .A0(n1724), .A1(d_ff2_Z[20]), .B0(n1723), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n1819), .Y(n1725) ); INVX2TS U2710 ( .A(n1725), .Y(n869) ); BUFX3TS U2711 ( .A(n1730), .Y(n1752) ); INVX2TS U2712 ( .A(n1726), .Y(add_subt_dataA[22]) ); INVX2TS U2713 ( .A(n1728), .Y(add_subt_dataA[23]) ); INVX2TS U2714 ( .A(n1729), .Y(add_subt_dataA[18]) ); BUFX3TS U2715 ( .A(n1877), .Y(n1880) ); INVX2TS U2716 ( .A(n1731), .Y(add_subt_dataA[27]) ); INVX2TS U2717 ( .A(n1732), .Y(add_subt_dataA[21]) ); INVX2TS U2718 ( .A(n1733), .Y(add_subt_dataA[17]) ); INVX2TS U2719 ( .A(n1735), .Y(add_subt_dataA[19]) ); BUFX3TS U2720 ( .A(n1736), .Y(n1821) ); INVX2TS U2721 ( .A(n1737), .Y(n886) ); AOI222X1TS U2722 ( .A0(n2187), .A1(d_ff2_Z[1]), .B0(n1821), .B1(d_ff1_Z[1]), .C0(d_ff_Zn[1]), .C1(n1840), .Y(n1738) ); INVX2TS U2723 ( .A(n1738), .Y(n888) ); AOI222X1TS U2724 ( .A0(n2187), .A1(d_ff2_Z[2]), .B0(n1821), .B1(d_ff1_Z[2]), .C0(d_ff_Zn[2]), .C1(n1739), .Y(n1740) ); INVX2TS U2725 ( .A(n1740), .Y(n887) ); INVX2TS U2726 ( .A(n1741), .Y(n885) ); BUFX3TS U2727 ( .A(n1792), .Y(n1773) ); INVX2TS U2728 ( .A(n1742), .Y(add_subt_dataA[25]) ); INVX2TS U2729 ( .A(n1743), .Y(add_subt_dataA[33]) ); INVX2TS U2730 ( .A(n1744), .Y(add_subt_dataA[20]) ); INVX2TS U2731 ( .A(n1745), .Y(add_subt_dataA[30]) ); INVX2TS U2732 ( .A(n1877), .Y(n1782) ); INVX2TS U2733 ( .A(n1746), .Y(add_subt_dataA[36]) ); INVX2TS U2734 ( .A(n1747), .Y(add_subt_dataA[29]) ); INVX2TS U2735 ( .A(n1748), .Y(add_subt_dataA[32]) ); INVX2TS U2736 ( .A(n1749), .Y(add_subt_dataA[35]) ); INVX2TS U2737 ( .A(n1750), .Y(add_subt_dataA[26]) ); INVX2TS U2738 ( .A(n1751), .Y(add_subt_dataA[34]) ); INVX2TS U2739 ( .A(n1754), .Y(add_subt_dataA[24]) ); INVX2TS U2740 ( .A(n1755), .Y(add_subt_dataA[31]) ); INVX2TS U2741 ( .A(n1756), .Y(add_subt_dataA[28]) ); INVX2TS U2742 ( .A(n1757), .Y(n889) ); INVX2TS U2743 ( .A(n1880), .Y(n1887) ); BUFX3TS U2744 ( .A(n1910), .Y(n1886) ); INVX2TS U2745 ( .A(n1758), .Y(add_subt_dataB[46]) ); BUFX3TS U2746 ( .A(n1910), .Y(n1851) ); AOI222X1TS U2747 ( .A0(d_ff3_LUT_out[36]), .A1(n1792), .B0(n1852), .B1( d_ff3_sh_x_out[36]), .C0(n1851), .C1(d_ff3_sh_y_out[36]), .Y(n1759) ); INVX2TS U2748 ( .A(n1759), .Y(add_subt_dataB[36]) ); INVX2TS U2749 ( .A(n1760), .Y(add_subt_dataB[49]) ); INVX2TS U2750 ( .A(n1761), .Y(add_subt_dataB[52]) ); AOI222X1TS U2751 ( .A0(d_ff3_LUT_out[35]), .A1(n1792), .B0(n1813), .B1( d_ff3_sh_x_out[35]), .C0(n1851), .C1(d_ff3_sh_y_out[35]), .Y(n1762) ); INVX2TS U2752 ( .A(n1762), .Y(add_subt_dataB[35]) ); AOI222X1TS U2753 ( .A0(n1911), .A1(d_ff3_LUT_out[37]), .B0(n1852), .B1( d_ff3_sh_x_out[37]), .C0(n1851), .C1(d_ff3_sh_y_out[37]), .Y(n1763) ); INVX2TS U2754 ( .A(n1763), .Y(add_subt_dataB[37]) ); INVX2TS U2755 ( .A(n1764), .Y(add_subt_dataB[44]) ); AOI222X1TS U2756 ( .A0(d_ff3_LUT_out[34]), .A1(n1792), .B0(n1852), .B1( d_ff3_sh_x_out[34]), .C0(n1851), .C1(d_ff3_sh_y_out[34]), .Y(n1765) ); INVX2TS U2757 ( .A(n1765), .Y(add_subt_dataB[34]) ); BUFX3TS U2758 ( .A(n1792), .Y(n1814) ); AOI222X1TS U2759 ( .A0(d_ff3_LUT_out[30]), .A1(n1814), .B0(n1813), .B1( d_ff3_sh_x_out[30]), .C0(n1851), .C1(d_ff3_sh_y_out[30]), .Y(n1766) ); INVX2TS U2760 ( .A(n1766), .Y(add_subt_dataB[30]) ); INVX2TS U2761 ( .A(n1767), .Y(add_subt_dataB[29]) ); BUFX3TS U2762 ( .A(n1909), .Y(n1780) ); INVX2TS U2763 ( .A(n1768), .Y(add_subt_dataA[41]) ); INVX2TS U2764 ( .A(n1769), .Y(add_subt_dataA[46]) ); BUFX3TS U2765 ( .A(n1770), .Y(n1789) ); INVX2TS U2766 ( .A(n1771), .Y(add_subt_dataA[44]) ); INVX2TS U2767 ( .A(n1877), .Y(n1893) ); INVX2TS U2768 ( .A(n1772), .Y(add_subt_dataA[42]) ); INVX2TS U2769 ( .A(n1774), .Y(add_subt_dataA[38]) ); INVX2TS U2770 ( .A(n1775), .Y(add_subt_dataA[40]) ); INVX2TS U2771 ( .A(n1777), .Y(add_subt_dataA[37]) ); INVX2TS U2772 ( .A(n1778), .Y(add_subt_dataA[45]) ); INVX2TS U2773 ( .A(n1779), .Y(add_subt_dataA[43]) ); INVX2TS U2774 ( .A(n1781), .Y(add_subt_dataA[39]) ); BUFX3TS U2775 ( .A(n1909), .Y(n1889) ); INVX2TS U2776 ( .A(n1783), .Y(add_subt_dataA[47]) ); INVX2TS U2777 ( .A(n1784), .Y(add_subt_dataA[49]) ); INVX2TS U2778 ( .A(n1785), .Y(add_subt_dataA[0]) ); INVX2TS U2779 ( .A(n1786), .Y(add_subt_dataA[50]) ); INVX2TS U2780 ( .A(n1787), .Y(add_subt_dataA[48]) ); INVX2TS U2781 ( .A(n1788), .Y(add_subt_dataA[51]) ); INVX2TS U2782 ( .A(n1790), .Y(add_subt_dataA[54]) ); BUFX3TS U2783 ( .A(n1694), .Y(n1812) ); AOI222X1TS U2784 ( .A0(n1911), .A1(d_ff3_LUT_out[20]), .B0(n1497), .B1( d_ff3_sh_x_out[20]), .C0(n1812), .C1(d_ff3_sh_y_out[20]), .Y(n1791) ); INVX2TS U2785 ( .A(n1791), .Y(add_subt_dataB[20]) ); BUFX3TS U2786 ( .A(n1792), .Y(n1810) ); BUFX3TS U2787 ( .A(n1694), .Y(n1867) ); AOI222X1TS U2788 ( .A0(d_ff3_LUT_out[18]), .A1(n1810), .B0(n1497), .B1( d_ff3_sh_x_out[18]), .C0(n1867), .C1(d_ff3_sh_y_out[18]), .Y(n1793) ); INVX2TS U2789 ( .A(n1793), .Y(add_subt_dataB[18]) ); AOI222X1TS U2790 ( .A0(d_ff3_LUT_out[22]), .A1(n1814), .B0(n1813), .B1( d_ff3_sh_x_out[22]), .C0(n1812), .C1(d_ff3_sh_y_out[22]), .Y(n1794) ); INVX2TS U2791 ( .A(n1794), .Y(add_subt_dataB[22]) ); AOI222X1TS U2792 ( .A0(d_ff3_LUT_out[16]), .A1(n1810), .B0(n1782), .B1( d_ff3_sh_x_out[16]), .C0(n1867), .C1(d_ff3_sh_y_out[16]), .Y(n1795) ); INVX2TS U2793 ( .A(n1795), .Y(add_subt_dataB[16]) ); INVX2TS U2794 ( .A(n1796), .Y(add_subt_dataB[14]) ); AOI222X1TS U2795 ( .A0(d_ff3_LUT_out[21]), .A1(n1810), .B0(n1893), .B1( d_ff3_sh_x_out[21]), .C0(n1812), .C1(d_ff3_sh_y_out[21]), .Y(n1797) ); INVX2TS U2796 ( .A(n1797), .Y(add_subt_dataB[21]) ); AOI222X1TS U2797 ( .A0(d_ff3_LUT_out[12]), .A1(n1810), .B0(n1498), .B1( d_ff3_sh_x_out[12]), .C0(n1867), .C1(d_ff3_sh_y_out[12]), .Y(n1798) ); INVX2TS U2798 ( .A(n1798), .Y(add_subt_dataB[12]) ); AOI222X1TS U2799 ( .A0(d_ff3_LUT_out[10]), .A1(n1810), .B0(n1498), .B1( d_ff3_sh_x_out[10]), .C0(n1867), .C1(d_ff3_sh_y_out[10]), .Y(n1799) ); INVX2TS U2800 ( .A(n1799), .Y(add_subt_dataB[10]) ); AOI222X1TS U2801 ( .A0(d_ff3_LUT_out[28]), .A1(n1814), .B0(n1813), .B1( d_ff3_sh_x_out[28]), .C0(n1812), .C1(d_ff3_sh_y_out[28]), .Y(n1800) ); INVX2TS U2802 ( .A(n1800), .Y(add_subt_dataB[28]) ); AOI222X1TS U2803 ( .A0(d_ff3_LUT_out[13]), .A1(n1810), .B0(n1782), .B1( d_ff3_sh_x_out[13]), .C0(n1867), .C1(d_ff3_sh_y_out[13]), .Y(n1801) ); INVX2TS U2804 ( .A(n1801), .Y(add_subt_dataB[13]) ); AOI222X1TS U2805 ( .A0(d_ff3_LUT_out[24]), .A1(n1814), .B0(n1813), .B1( d_ff3_sh_x_out[24]), .C0(n1812), .C1(d_ff3_sh_y_out[24]), .Y(n1802) ); INVX2TS U2806 ( .A(n1802), .Y(add_subt_dataB[24]) ); INVX2TS U2807 ( .A(n1803), .Y(add_subt_dataB[15]) ); AOI222X1TS U2808 ( .A0(d_ff3_LUT_out[31]), .A1(n1814), .B0(n1852), .B1( d_ff3_sh_x_out[31]), .C0(n1812), .C1(d_ff3_sh_y_out[31]), .Y(n1804) ); INVX2TS U2809 ( .A(n1804), .Y(add_subt_dataB[31]) ); INVX2TS U2810 ( .A(n1805), .Y(add_subt_dataB[26]) ); AOI222X1TS U2811 ( .A0(d_ff3_LUT_out[17]), .A1(n1810), .B0(n1893), .B1( d_ff3_sh_x_out[17]), .C0(n1867), .C1(d_ff3_sh_y_out[17]), .Y(n1807) ); INVX2TS U2812 ( .A(n1807), .Y(add_subt_dataB[17]) ); INVX2TS U2813 ( .A(n1808), .Y(add_subt_dataB[25]) ); AOI222X1TS U2814 ( .A0(d_ff3_LUT_out[23]), .A1(n1814), .B0(n1813), .B1( d_ff3_sh_x_out[23]), .C0(n1812), .C1(d_ff3_sh_y_out[23]), .Y(n1809) ); INVX2TS U2815 ( .A(n1809), .Y(add_subt_dataB[23]) ); INVX2TS U2816 ( .A(n1877), .Y(n1871) ); INVX2TS U2817 ( .A(n1811), .Y(add_subt_dataB[11]) ); INVX2TS U2818 ( .A(n1815), .Y(add_subt_dataB[27]) ); BUFX3TS U2819 ( .A(n1821), .Y(n1843) ); AOI222X1TS U2820 ( .A0(n2183), .A1(d_ff2_Z[41]), .B0(n1843), .B1(d_ff1_Z[41]), .C0(d_ff_Zn[41]), .C1(n1842), .Y(n1816) ); INVX2TS U2821 ( .A(n1816), .Y(n848) ); AOI222X1TS U2822 ( .A0(n1833), .A1(d_ff2_Z[34]), .B0(n1843), .B1(d_ff1_Z[34]), .C0(d_ff_Zn[34]), .C1(n1835), .Y(n1818) ); INVX2TS U2823 ( .A(n1818), .Y(n855) ); AOI222X1TS U2824 ( .A0(n1717), .A1(d_ff2_Z[35]), .B0(n1843), .B1(d_ff1_Z[35]), .C0(d_ff_Zn[35]), .C1(n1819), .Y(n1820) ); INVX2TS U2825 ( .A(n1820), .Y(n854) ); INVX2TS U2826 ( .A(n1822), .Y(n826) ); AOI222X1TS U2827 ( .A0(n2105), .A1(d_ff2_Z[40]), .B0(n1843), .B1(d_ff1_Z[40]), .C0(d_ff_Zn[40]), .C1(n1840), .Y(n1823) ); INVX2TS U2828 ( .A(n1823), .Y(n849) ); AOI222X1TS U2829 ( .A0(n1844), .A1(d_ff2_Z[37]), .B0(n1843), .B1(d_ff1_Z[37]), .C0(d_ff_Zn[37]), .C1(n1842), .Y(n1824) ); INVX2TS U2830 ( .A(n1824), .Y(n852) ); AOI222X1TS U2831 ( .A0(n2105), .A1(d_ff2_Z[61]), .B0(n1736), .B1(d_ff1_Z[61]), .C0(d_ff_Zn[61]), .C1(n1842), .Y(n1825) ); INVX2TS U2832 ( .A(n1825), .Y(n828) ); INVX2TS U2833 ( .A(n1826), .Y(n829) ); AOI222X1TS U2834 ( .A0(n2183), .A1(d_ff2_Z[57]), .B0(n1683), .B1(d_ff1_Z[57]), .C0(d_ff_Zn[57]), .C1(n1840), .Y(n1827) ); INVX2TS U2835 ( .A(n1827), .Y(n832) ); AOI222X1TS U2836 ( .A0(n2105), .A1(d_ff2_Z[62]), .B0(n1683), .B1(d_ff1_Z[62]), .C0(d_ff_Zn[62]), .C1(n1842), .Y(n1828) ); INVX2TS U2837 ( .A(n1828), .Y(n827) ); AOI222X1TS U2838 ( .A0(n2183), .A1(d_ff2_Z[38]), .B0(n1843), .B1(d_ff1_Z[38]), .C0(d_ff_Zn[38]), .C1(n1840), .Y(n1829) ); INVX2TS U2839 ( .A(n1829), .Y(n851) ); INVX2TS U2840 ( .A(n1830), .Y(n831) ); AOI222X1TS U2841 ( .A0(n2105), .A1(d_ff2_Z[43]), .B0(n1843), .B1(d_ff1_Z[43]), .C0(d_ff_Zn[43]), .C1(n1842), .Y(n1831) ); INVX2TS U2842 ( .A(n1831), .Y(n846) ); INVX2TS U2843 ( .A(n1832), .Y(n833) ); AOI222X1TS U2844 ( .A0(n2108), .A1(d_ff2_Z[36]), .B0(n1843), .B1(d_ff1_Z[36]), .C0(d_ff_Zn[36]), .C1(n1840), .Y(n1834) ); INVX2TS U2845 ( .A(n1834), .Y(n853) ); INVX2TS U2846 ( .A(n1836), .Y(n835) ); INVX2TS U2847 ( .A(n1838), .Y(n834) ); AOI222X1TS U2848 ( .A0(n1844), .A1(d_ff2_Z[42]), .B0(n1843), .B1(d_ff1_Z[42]), .C0(d_ff_Zn[42]), .C1(n1842), .Y(n1839) ); INVX2TS U2849 ( .A(n1839), .Y(n847) ); AOI222X1TS U2850 ( .A0(n2183), .A1(d_ff2_Z[59]), .B0(n1821), .B1(d_ff1_Z[59]), .C0(d_ff_Zn[59]), .C1(n1842), .Y(n1841) ); INVX2TS U2851 ( .A(n1841), .Y(n830) ); AOI222X1TS U2852 ( .A0(n2183), .A1(d_ff2_Z[39]), .B0(n1843), .B1(d_ff1_Z[39]), .C0(d_ff_Zn[39]), .C1(n1840), .Y(n1845) ); INVX2TS U2853 ( .A(n1845), .Y(n850) ); AOI222X1TS U2854 ( .A0(d_ff3_LUT_out[38]), .A1(n1881), .B0(n1852), .B1( d_ff3_sh_x_out[38]), .C0(n1851), .C1(d_ff3_sh_y_out[38]), .Y(n1846) ); INVX2TS U2855 ( .A(n1846), .Y(add_subt_dataB[38]) ); AOI222X1TS U2856 ( .A0(d_ff3_LUT_out[42]), .A1(n1881), .B0(n1852), .B1( d_ff3_sh_x_out[42]), .C0(n1886), .C1(d_ff3_sh_y_out[42]), .Y(n1847) ); INVX2TS U2857 ( .A(n1847), .Y(add_subt_dataB[42]) ); AOI222X1TS U2858 ( .A0(d_ff3_LUT_out[32]), .A1(n1881), .B0(n1852), .B1( d_ff3_sh_x_out[32]), .C0(n1851), .C1(d_ff3_sh_y_out[32]), .Y(n1848) ); INVX2TS U2859 ( .A(n1848), .Y(add_subt_dataB[32]) ); INVX2TS U2860 ( .A(n1849), .Y(add_subt_dataB[39]) ); AOI222X1TS U2861 ( .A0(d_ff3_LUT_out[40]), .A1(n1881), .B0(n1852), .B1( d_ff3_sh_x_out[40]), .C0(n1851), .C1(d_ff3_sh_y_out[40]), .Y(n1850) ); INVX2TS U2862 ( .A(n1850), .Y(add_subt_dataB[40]) ); INVX2TS U2863 ( .A(n1853), .Y(add_subt_dataB[33]) ); INVX2TS U2864 ( .A(n1855), .Y(add_subt_dataA[9]) ); AOI22X1TS U2865 ( .A0(n1878), .A1(d_ff2_Z[53]), .B0(d_ff2_X[53]), .B1(n1919), .Y(n1856) ); AOI22X1TS U2866 ( .A0(d_ff2_X[58]), .A1(n1916), .B0(d_ff2_Z[58]), .B1(n1878), .Y(n1857) ); AOI22X1TS U2867 ( .A0(d_ff2_X[60]), .A1(n1919), .B0(d_ff2_Z[60]), .B1(n1878), .Y(n1858) ); AOI22X1TS U2868 ( .A0(d_ff2_X[56]), .A1(n1916), .B0(d_ff2_Z[56]), .B1(n1878), .Y(n1859) ); AOI22X1TS U2869 ( .A0(d_ff2_X[62]), .A1(n1919), .B0(d_ff2_Z[62]), .B1(n1878), .Y(n1861) ); BUFX3TS U2870 ( .A(n1881), .Y(n1873) ); BUFX3TS U2871 ( .A(n1916), .Y(n1894) ); INVX2TS U2872 ( .A(n1862), .Y(add_subt_dataB[0]) ); AOI222X1TS U2873 ( .A0(d_ff3_LUT_out[4]), .A1(n1873), .B0(n1871), .B1( d_ff3_sh_x_out[4]), .C0(n1894), .C1(d_ff3_sh_y_out[4]), .Y(n1863) ); INVX2TS U2874 ( .A(n1863), .Y(add_subt_dataB[4]) ); INVX2TS U2875 ( .A(n1864), .Y(add_subt_dataB[1]) ); INVX2TS U2876 ( .A(n1865), .Y(add_subt_dataB[3]) ); AOI222X1TS U2877 ( .A0(d_ff3_LUT_out[2]), .A1(n1873), .B0(n1871), .B1( d_ff3_sh_x_out[2]), .C0(n1894), .C1(d_ff3_sh_y_out[2]), .Y(n1866) ); INVX2TS U2878 ( .A(n1866), .Y(add_subt_dataB[2]) ); INVX2TS U2879 ( .A(n1868), .Y(add_subt_dataB[9]) ); INVX2TS U2880 ( .A(n1869), .Y(add_subt_dataB[6]) ); INVX2TS U2881 ( .A(n1870), .Y(add_subt_dataB[5]) ); INVX2TS U2882 ( .A(n1872), .Y(add_subt_dataB[7]) ); INVX2TS U2883 ( .A(n1874), .Y(add_subt_dataA[63]) ); AOI22X1TS U2884 ( .A0(d_ff2_X[57]), .A1(n1916), .B0(d_ff2_Z[57]), .B1(n1878), .Y(n1875) ); AOI22X1TS U2885 ( .A0(d_ff2_X[61]), .A1(n1916), .B0(d_ff2_Z[61]), .B1(n1878), .Y(n1876) ); AOI22X1TS U2886 ( .A0(d_ff2_X[59]), .A1(n1919), .B0(d_ff2_Z[59]), .B1(n1878), .Y(n1879) ); BUFX3TS U2887 ( .A(n1881), .Y(n1892) ); INVX2TS U2888 ( .A(n1882), .Y(add_subt_dataB[45]) ); INVX2TS U2889 ( .A(n1883), .Y(add_subt_dataB[43]) ); INVX2TS U2890 ( .A(n1884), .Y(add_subt_dataB[47]) ); INVX2TS U2891 ( .A(n1885), .Y(add_subt_dataB[54]) ); INVX2TS U2892 ( .A(n1888), .Y(add_subt_dataB[50]) ); INVX2TS U2893 ( .A(n1890), .Y(add_subt_dataB[55]) ); AOI222X1TS U2894 ( .A0(d_ff3_sh_y_out[53]), .A1(n1894), .B0( d_ff3_sh_x_out[53]), .B1(n1871), .C0(n1892), .C1(d_ff3_LUT_out[53]), .Y(n1891) ); INVX2TS U2895 ( .A(n1891), .Y(add_subt_dataB[53]) ); AOI222X1TS U2896 ( .A0(d_ff3_sh_y_out[56]), .A1(n1894), .B0( d_ff3_sh_x_out[56]), .B1(n1871), .C0(n1892), .C1(d_ff3_LUT_out[56]), .Y(n1895) ); INVX2TS U2897 ( .A(n1895), .Y(add_subt_dataB[56]) ); OAI211XLTS U2898 ( .A0(n1898), .A1(n2229), .B0(n1897), .C0(n1934), .Y(n1345) ); AOI22X1TS U2899 ( .A0(n1806), .A1(d_ff3_sh_x_out[8]), .B0(n1919), .B1( d_ff3_sh_y_out[8]), .Y(n1903) ); OAI21XLTS U2900 ( .A0(n1517), .A1(n1906), .B0(n1903), .Y(add_subt_dataB[8]) ); AOI22X1TS U2901 ( .A0(n1753), .A1(d_ff3_sh_x_out[19]), .B0(n1919), .B1( d_ff3_sh_y_out[19]), .Y(n1904) ); OAI21XLTS U2902 ( .A0(n1515), .A1(n1906), .B0(n1904), .Y(add_subt_dataB[19]) ); AOI22X1TS U2903 ( .A0(n1806), .A1(d_ff3_sh_x_out[41]), .B0(n1919), .B1( d_ff3_sh_y_out[41]), .Y(n1905) ); OAI21XLTS U2904 ( .A0(n1516), .A1(n1906), .B0(n1905), .Y(add_subt_dataB[41]) ); INVX2TS U2905 ( .A(n1908), .Y(n1907) ); AOI221XLTS U2906 ( .A0(cont_var_out[1]), .A1(n1908), .B0(n1482), .B1(n1907), .C0(n2089), .Y(n1342) ); AO22XLTS U2907 ( .A0(n1753), .A1(d_ff3_sh_x_out[63]), .B0(n1909), .B1( d_ff3_sh_y_out[63]), .Y(add_subt_dataB[63]) ); AO22XLTS U2908 ( .A0(d_ff3_sh_y_out[62]), .A1(n1910), .B0(d_ff3_sh_x_out[62]), .B1(n1806), .Y(add_subt_dataB[62]) ); AOI22X1TS U2909 ( .A0(d_ff3_sh_y_out[61]), .A1(n1694), .B0( d_ff3_sh_x_out[61]), .B1(n1806), .Y(n1912) ); NAND2X2TS U2910 ( .A(d_ff3_LUT_out[48]), .B(n1911), .Y(n1921) ); NAND2X1TS U2911 ( .A(n1912), .B(n1921), .Y(add_subt_dataB[61]) ); AOI22X1TS U2912 ( .A0(d_ff3_sh_y_out[60]), .A1(n1916), .B0( d_ff3_sh_x_out[60]), .B1(n1753), .Y(n1913) ); NAND2X1TS U2913 ( .A(n1913), .B(n1921), .Y(add_subt_dataB[60]) ); AOI22X1TS U2914 ( .A0(d_ff3_sh_y_out[59]), .A1(n1916), .B0( d_ff3_sh_x_out[59]), .B1(n1806), .Y(n1914) ); NAND2X1TS U2915 ( .A(n1914), .B(n1921), .Y(add_subt_dataB[59]) ); AOI22X1TS U2916 ( .A0(d_ff3_sh_y_out[58]), .A1(n1916), .B0( d_ff3_sh_x_out[58]), .B1(n1753), .Y(n1915) ); NAND2X1TS U2917 ( .A(n1915), .B(n1921), .Y(add_subt_dataB[58]) ); AOI22X1TS U2918 ( .A0(d_ff3_sh_y_out[57]), .A1(n1916), .B0( d_ff3_sh_x_out[57]), .B1(n1753), .Y(n1917) ); NAND2X1TS U2919 ( .A(n1917), .B(n1921), .Y(add_subt_dataB[57]) ); AOI22X1TS U2920 ( .A0(n1753), .A1(d_ff3_sh_x_out[51]), .B0(n1919), .B1( d_ff3_sh_y_out[51]), .Y(n1918) ); NAND2X1TS U2921 ( .A(n1918), .B(n1921), .Y(add_subt_dataB[51]) ); AOI22X1TS U2922 ( .A0(n1806), .A1(d_ff3_sh_x_out[48]), .B0(n1919), .B1( d_ff3_sh_y_out[48]), .Y(n1922) ); NAND2X1TS U2923 ( .A(n1922), .B(n1921), .Y(add_subt_dataB[48]) ); AOI2BB2XLTS U2924 ( .B0(d_ff3_sign_out), .B1(n2231), .A0N(n2231), .A1N( d_ff3_sign_out), .Y(op_add_subt) ); INVX2TS U2925 ( .A(n1932), .Y(n1928) ); NOR2XLTS U2926 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[3]), .Y(n1924) ); AOI31XLTS U2927 ( .A0(cordic_FSM_state_reg[0]), .A1(cordic_FSM_state_reg[3]), .A2(ack_cordic), .B0(cordic_FSM_state_reg[1]), .Y(n1923) ); OAI21X1TS U2928 ( .A0(n1924), .A1(n1923), .B0(cordic_FSM_state_reg[2]), .Y( n1927) ); CLKAND2X2TS U2929 ( .A(ready_add_subt), .B(n2225), .Y(n1931) ); NAND2X1TS U2930 ( .A(n1952), .B(n1938), .Y(n1936) ); AOI22X1TS U2931 ( .A0(cont_iter_out[0]), .A1(n1936), .B0(n1938), .B1(n1490), .Y(n1341) ); INVX2TS U2932 ( .A(n1952), .Y(n1942) ); INVX2TS U2933 ( .A(n1937), .Y(n2057) ); OAI22X1TS U2934 ( .A0(n1942), .A1(n1503), .B0(n1938), .B1(n2057), .Y(n1338) ); INVX2TS U2935 ( .A(n1950), .Y(n1955) ); CLKBUFX2TS U2936 ( .A(n1950), .Y(n1944) ); CLKBUFX2TS U2937 ( .A(n1940), .Y(n1939) ); INVX2TS U2938 ( .A(n1944), .Y(n1948) ); INVX2TS U2939 ( .A(n1944), .Y(n1953) ); BUFX3TS U2940 ( .A(n1940), .Y(n1941) ); INVX2TS U2941 ( .A(n1944), .Y(n1943) ); INVX2TS U2942 ( .A(n1950), .Y(n1946) ); BUFX3TS U2943 ( .A(n1940), .Y(n1954) ); BUFX3TS U2944 ( .A(n1944), .Y(n1945) ); INVX2TS U2945 ( .A(n1944), .Y(n1949) ); BUFX3TS U2946 ( .A(n1950), .Y(n1947) ); NOR2BX1TS U2947 ( .AN(n1956), .B(n1990), .Y(n1957) ); BUFX3TS U2948 ( .A(n1966), .Y(n1958) ); INVX2TS U2949 ( .A(n1958), .Y(n1959) ); BUFX3TS U2950 ( .A(n1966), .Y(n1971) ); BUFX3TS U2951 ( .A(n1971), .Y(n1960) ); INVX2TS U2952 ( .A(n1971), .Y(n1961) ); BUFX3TS U2953 ( .A(n1971), .Y(n1962) ); INVX2TS U2954 ( .A(n1971), .Y(n1963) ); CLKBUFX2TS U2955 ( .A(n1966), .Y(n1967) ); BUFX3TS U2956 ( .A(n1967), .Y(n1964) ); INVX2TS U2957 ( .A(n1971), .Y(n1965) ); INVX2TS U2958 ( .A(n1966), .Y(n1968) ); CLKBUFX2TS U2959 ( .A(n1967), .Y(n1972) ); BUFX3TS U2960 ( .A(n1967), .Y(n1969) ); INVX2TS U2961 ( .A(n1971), .Y(n1970) ); INVX2TS U2962 ( .A(n1971), .Y(n1973) ); BUFX3TS U2963 ( .A(n1974), .Y(n1977) ); OAI2BB2XLTS U2964 ( .B0(n1977), .B1(n2239), .A0N(n1979), .A1N( result_add_subt[0]), .Y(n1201) ); BUFX3TS U2965 ( .A(n1979), .Y(n1975) ); OAI2BB2XLTS U2966 ( .B0(n1975), .B1(n2240), .A0N(n1979), .A1N( result_add_subt[1]), .Y(n1200) ); OAI2BB2XLTS U2967 ( .B0(n1977), .B1(n2241), .A0N(n1979), .A1N( result_add_subt[2]), .Y(n1199) ); BUFX3TS U2968 ( .A(n1979), .Y(n1986) ); OAI2BB2XLTS U2969 ( .B0(n1975), .B1(n2242), .A0N(n1986), .A1N( result_add_subt[3]), .Y(n1198) ); OAI2BB2XLTS U2970 ( .B0(n1975), .B1(n2243), .A0N(n1986), .A1N( result_add_subt[4]), .Y(n1197) ); BUFX3TS U2971 ( .A(n1974), .Y(n1984) ); OAI2BB2XLTS U2972 ( .B0(n1977), .B1(n2244), .A0N(n1984), .A1N( result_add_subt[5]), .Y(n1196) ); OAI2BB2XLTS U2973 ( .B0(n1977), .B1(n2245), .A0N(n1986), .A1N( result_add_subt[6]), .Y(n1195) ); OAI2BB2XLTS U2974 ( .B0(n1975), .B1(n2246), .A0N(n1986), .A1N( result_add_subt[7]), .Y(n1194) ); BUFX3TS U2975 ( .A(n1979), .Y(n1983) ); OAI2BB2XLTS U2976 ( .B0(n1975), .B1(n2247), .A0N(n1983), .A1N( result_add_subt[8]), .Y(n1193) ); CLKBUFX2TS U2977 ( .A(n1979), .Y(n1976) ); BUFX3TS U2978 ( .A(n1976), .Y(n1978) ); OAI2BB2XLTS U2979 ( .B0(n1978), .B1(n2248), .A0N(n1984), .A1N( result_add_subt[9]), .Y(n1192) ); OAI2BB2XLTS U2980 ( .B0(n1978), .B1(n2249), .A0N(n1983), .A1N( result_add_subt[10]), .Y(n1191) ); BUFX3TS U2981 ( .A(n1974), .Y(n1981) ); OAI2BB2XLTS U2982 ( .B0(n1975), .B1(n2250), .A0N(n1981), .A1N( result_add_subt[11]), .Y(n1190) ); OAI2BB2XLTS U2983 ( .B0(n1975), .B1(n2251), .A0N(n1983), .A1N( result_add_subt[12]), .Y(n1189) ); OAI2BB2XLTS U2984 ( .B0(n1978), .B1(n2252), .A0N(n1981), .A1N( result_add_subt[13]), .Y(n1188) ); OAI2BB2XLTS U2985 ( .B0(n1975), .B1(n2253), .A0N(n1983), .A1N( result_add_subt[14]), .Y(n1187) ); OAI2BB2XLTS U2986 ( .B0(n1975), .B1(n2254), .A0N(n1981), .A1N( result_add_subt[15]), .Y(n1186) ); BUFX3TS U2987 ( .A(n1974), .Y(n1980) ); OAI2BB2XLTS U2988 ( .B0(n1978), .B1(n2255), .A0N(n1980), .A1N( result_add_subt[16]), .Y(n1185) ); OAI2BB2XLTS U2989 ( .B0(n1978), .B1(n2256), .A0N(n1981), .A1N( result_add_subt[17]), .Y(n1184) ); OAI2BB2XLTS U2990 ( .B0(n1975), .B1(n2257), .A0N(n1980), .A1N( result_add_subt[18]), .Y(n1183) ); OAI2BB2XLTS U2991 ( .B0(n1978), .B1(n2258), .A0N(n1983), .A1N( result_add_subt[19]), .Y(n1182) ); OAI2BB2XLTS U2992 ( .B0(n1978), .B1(n2259), .A0N(n1977), .A1N( result_add_subt[20]), .Y(n1181) ); OAI2BB2XLTS U2993 ( .B0(n1978), .B1(n2260), .A0N(n1981), .A1N( result_add_subt[21]), .Y(n1180) ); OAI2BB2XLTS U2994 ( .B0(n1978), .B1(n2261), .A0N(n1977), .A1N( result_add_subt[22]), .Y(n1179) ); BUFX3TS U2995 ( .A(n1976), .Y(n1988) ); OAI2BB2XLTS U2996 ( .B0(n1988), .B1(n2262), .A0N(n1980), .A1N( result_add_subt[23]), .Y(n1178) ); OAI2BB2XLTS U2997 ( .B0(n1988), .B1(n2263), .A0N(n1977), .A1N( result_add_subt[24]), .Y(n1177) ); OAI2BB2XLTS U2998 ( .B0(n1988), .B1(n2264), .A0N(n1980), .A1N( result_add_subt[25]), .Y(n1176) ); OAI2BB2XLTS U2999 ( .B0(n1988), .B1(n2265), .A0N(n1980), .A1N( result_add_subt[26]), .Y(n1175) ); OAI2BB2XLTS U3000 ( .B0(n1988), .B1(n2266), .A0N(n1977), .A1N( result_add_subt[27]), .Y(n1174) ); OAI2BB2XLTS U3001 ( .B0(n1988), .B1(n2267), .A0N(n1977), .A1N( result_add_subt[28]), .Y(n1173) ); OAI2BB2XLTS U3002 ( .B0(n1988), .B1(n2268), .A0N(n1980), .A1N( result_add_subt[29]), .Y(n1172) ); OAI2BB2XLTS U3003 ( .B0(n1988), .B1(n2269), .A0N(n1977), .A1N( result_add_subt[30]), .Y(n1171) ); OAI2BB2XLTS U3004 ( .B0(n1978), .B1(n2270), .A0N(n1980), .A1N( result_add_subt[31]), .Y(n1170) ); OAI2BB2XLTS U3005 ( .B0(n1988), .B1(n2271), .A0N(n1981), .A1N( result_add_subt[32]), .Y(n1169) ); BUFX3TS U3006 ( .A(n1976), .Y(n1982) ); OAI2BB2XLTS U3007 ( .B0(n1982), .B1(n2272), .A0N(n1980), .A1N( result_add_subt[33]), .Y(n1168) ); OAI2BB2XLTS U3008 ( .B0(n1982), .B1(n2273), .A0N(n1980), .A1N( result_add_subt[34]), .Y(n1167) ); OAI2BB2XLTS U3009 ( .B0(n1982), .B1(n2274), .A0N(n1981), .A1N( result_add_subt[35]), .Y(n1166) ); OAI2BB2XLTS U3010 ( .B0(n1982), .B1(n2275), .A0N(n1980), .A1N( result_add_subt[36]), .Y(n1165) ); OAI2BB2XLTS U3011 ( .B0(n1982), .B1(n2276), .A0N(n1981), .A1N( result_add_subt[37]), .Y(n1164) ); OAI2BB2XLTS U3012 ( .B0(n1982), .B1(n2277), .A0N(n1983), .A1N( result_add_subt[38]), .Y(n1163) ); OAI2BB2XLTS U3013 ( .B0(n1982), .B1(n2278), .A0N(n1983), .A1N( result_add_subt[39]), .Y(n1162) ); OAI2BB2XLTS U3014 ( .B0(n1982), .B1(n2279), .A0N(n1981), .A1N( result_add_subt[40]), .Y(n1161) ); OAI2BB2XLTS U3015 ( .B0(n1982), .B1(n2280), .A0N(n1983), .A1N( result_add_subt[41]), .Y(n1160) ); OAI2BB2XLTS U3016 ( .B0(n1982), .B1(n2281), .A0N(n1981), .A1N( result_add_subt[42]), .Y(n1159) ); BUFX3TS U3017 ( .A(n1976), .Y(n1985) ); OAI2BB2XLTS U3018 ( .B0(n1985), .B1(n2282), .A0N(n1983), .A1N( result_add_subt[43]), .Y(n1158) ); OAI2BB2XLTS U3019 ( .B0(n1985), .B1(n2283), .A0N(n1984), .A1N( result_add_subt[44]), .Y(n1157) ); OAI2BB2XLTS U3020 ( .B0(n1985), .B1(n2284), .A0N(n1983), .A1N( result_add_subt[45]), .Y(n1156) ); OAI2BB2XLTS U3021 ( .B0(n1985), .B1(n2285), .A0N(n1984), .A1N( result_add_subt[46]), .Y(n1155) ); OAI2BB2XLTS U3022 ( .B0(n1985), .B1(n2286), .A0N(n1984), .A1N( result_add_subt[47]), .Y(n1154) ); OAI2BB2XLTS U3023 ( .B0(n1985), .B1(n2287), .A0N(n1984), .A1N( result_add_subt[48]), .Y(n1153) ); OAI2BB2XLTS U3024 ( .B0(n1985), .B1(n2288), .A0N(n1984), .A1N( result_add_subt[49]), .Y(n1152) ); OAI2BB2XLTS U3025 ( .B0(n1985), .B1(n2289), .A0N(n1984), .A1N( result_add_subt[50]), .Y(n1151) ); OAI2BB2XLTS U3026 ( .B0(n1985), .B1(n2290), .A0N(n1984), .A1N( result_add_subt[51]), .Y(n1150) ); OAI2BB2XLTS U3027 ( .B0(n1985), .B1(n2121), .A0N(n1984), .A1N( result_add_subt[52]), .Y(n1149) ); OAI2BB2XLTS U3028 ( .B0(n1987), .B1(n2122), .A0N(n1986), .A1N( result_add_subt[53]), .Y(n1148) ); OAI2BB2XLTS U3029 ( .B0(n1987), .B1(n2291), .A0N(n1986), .A1N( result_add_subt[54]), .Y(n1147) ); OAI2BB2XLTS U3030 ( .B0(n1987), .B1(n2123), .A0N(n1986), .A1N( result_add_subt[55]), .Y(n1146) ); OAI2BB2XLTS U3031 ( .B0(n1987), .B1(n2124), .A0N(n1986), .A1N( result_add_subt[56]), .Y(n1145) ); OAI2BB2XLTS U3032 ( .B0(n1987), .B1(n2125), .A0N(n1986), .A1N( result_add_subt[57]), .Y(n1144) ); OAI2BB2XLTS U3033 ( .B0(n1987), .B1(n2126), .A0N(n1986), .A1N( result_add_subt[58]), .Y(n1143) ); OAI2BB2XLTS U3034 ( .B0(n1988), .B1(n2292), .A0N(n1979), .A1N( result_add_subt[63]), .Y(n1138) ); BUFX3TS U3035 ( .A(n2004), .Y(n2000) ); INVX2TS U3036 ( .A(n2000), .Y(n1992) ); BUFX3TS U3037 ( .A(n2004), .Y(n2005) ); BUFX3TS U3038 ( .A(n2005), .Y(n1993) ); INVX2TS U3039 ( .A(n2004), .Y(n1994) ); BUFX3TS U3040 ( .A(n2000), .Y(n1995) ); INVX2TS U3041 ( .A(n2004), .Y(n1996) ); BUFX3TS U3042 ( .A(n2004), .Y(n1997) ); INVX2TS U3043 ( .A(n2004), .Y(n1998) ); BUFX3TS U3044 ( .A(n2005), .Y(n1999) ); INVX2TS U3045 ( .A(n2005), .Y(n2001) ); BUFX3TS U3046 ( .A(n2000), .Y(n2002) ); INVX2TS U3047 ( .A(n2005), .Y(n2003) ); INVX2TS U3048 ( .A(n2004), .Y(n2006) ); BUFX3TS U3049 ( .A(n2008), .Y(n2010) ); INVX2TS U3050 ( .A(n2010), .Y(n2007) ); BUFX3TS U3051 ( .A(n2008), .Y(n2012) ); INVX2TS U3052 ( .A(n2012), .Y(n2009) ); INVX2TS U3053 ( .A(n2012), .Y(n2011) ); BUFX3TS U3054 ( .A(n2016), .Y(n2013) ); INVX2TS U3055 ( .A(n2012), .Y(n2014) ); BUFX3TS U3056 ( .A(n2016), .Y(n2015) ); INVX2TS U3057 ( .A(n2018), .Y(n2017) ); BUFX3TS U3058 ( .A(n2016), .Y(n2019) ); INVX2TS U3059 ( .A(n2018), .Y(n2020) ); NAND3X1TS U3060 ( .A(cont_iter_out[2]), .B(n1499), .C(n2027), .Y(n2068) ); BUFX3TS U3061 ( .A(n2156), .Y(n2095) ); AOI21X2TS U3062 ( .A0(cont_iter_out[2]), .A1(n1499), .B0(n1505), .Y(n2090) ); AOI31X1TS U3063 ( .A0(n2090), .A1(n2088), .A2(n2037), .B0(n2091), .Y(n2074) ); AOI22X1TS U3064 ( .A0(n2027), .A1(n2227), .B0(n2091), .B1(d_ff3_LUT_out[5]), .Y(n2028) ); NAND2X1TS U3065 ( .A(n2028), .B(n2062), .Y(n940) ); NAND2X1TS U3066 ( .A(n2065), .B(n2051), .Y(n2072) ); AOI22X1TS U3067 ( .A0(n1517), .A1(n2087), .B0(n2053), .B1(n2031), .Y(n937) ); INVX2TS U3068 ( .A(n2032), .Y(n2043) ); AOI211X1TS U3069 ( .A0(n1505), .A1(n2036), .B0(n2153), .C0(n2038), .Y(n2075) ); INVX2TS U3070 ( .A(n2215), .Y(n2097) ); AOI211X1TS U3071 ( .A0(n2100), .A1(n1496), .B0(n1505), .C0(cont_iter_out[2]), .Y(n2059) ); NAND2X1TS U3072 ( .A(n2097), .B(n2059), .Y(n2098) ); OA21XLTS U3073 ( .A0(n2211), .A1(d_ff3_LUT_out[12]), .B0(n2098), .Y(n933) ); NOR3X1TS U3074 ( .A(n2043), .B(n2039), .C(n2038), .Y(n2041) ); NOR2X2TS U3075 ( .A(n2040), .B(n2152), .Y(n2096) ); OAI32X1TS U3076 ( .A0(n2044), .A1(n2043), .A2(n2042), .B0(d_ff3_LUT_out[15]), .B1(n2213), .Y(n2045) ); AOI21X1TS U3077 ( .A0(n2090), .A1(n2078), .B0(n2091), .Y(n2046) ); BUFX3TS U3078 ( .A(n2156), .Y(n2158) ); OAI2BB1X1TS U3079 ( .A0N(d_ff3_LUT_out[17]), .A1N(n2158), .B0(n2047), .Y( n928) ); AOI211X1TS U3080 ( .A0(cont_iter_out[2]), .A1(n2049), .B0(n2093), .C0(n2048), .Y(n2083) ); OA22X1TS U3081 ( .A0(n2051), .A1(n2079), .B0(n2097), .B1(d_ff3_LUT_out[18]), .Y(n927) ); OAI2BB1X1TS U3082 ( .A0N(d_ff3_LUT_out[22]), .A1N(n2158), .B0(n2053), .Y( n923) ); AOI211X1TS U3083 ( .A0(n2055), .A1(n2064), .B0(n2060), .C0(n2054), .Y(n2056) ); INVX2TS U3084 ( .A(n2056), .Y(n2066) ); INVX2TS U3085 ( .A(n2156), .Y(n2104) ); NAND2X1TS U3086 ( .A(n2059), .B(n2088), .Y(n2077) ); CLKBUFX2TS U3087 ( .A(n2154), .Y(n2163) ); CLKBUFX2TS U3088 ( .A(n2163), .Y(n2167) ); BUFX3TS U3089 ( .A(n2167), .Y(n2103) ); NAND2X1TS U3090 ( .A(n2064), .B(n2063), .Y(n2069) ); OAI22X1TS U3091 ( .A0(n1476), .A1(n2066), .B0(n2213), .B1(d_ff3_LUT_out[27]), .Y(n2067) ); OAI2BB1X1TS U3092 ( .A0N(d_ff3_LUT_out[28]), .A1N(n2158), .B0(n2086), .Y( n917) ); NAND2X1TS U3093 ( .A(d_ff3_LUT_out[29]), .B(n2091), .Y(n2070) ); OAI21X1TS U3094 ( .A0(n2093), .A1(n2077), .B0(n2213), .Y(n2081) ); OAI2BB1X1TS U3095 ( .A0N(d_ff3_LUT_out[32]), .A1N(n2158), .B0(n2081), .Y( n913) ); AOI31X1TS U3096 ( .A0(n2090), .A1(n2078), .A2(n2088), .B0(n2091), .Y(n2092) ); OA21XLTS U3097 ( .A0(n2211), .A1(d_ff3_LUT_out[35]), .B0(n2079), .Y(n910) ); OAI2BB1X1TS U3098 ( .A0N(d_ff3_LUT_out[36]), .A1N(n2158), .B0(n2086), .Y( n909) ); INVX2TS U3099 ( .A(n2044), .Y(n2206) ); OAI2BB1X1TS U3100 ( .A0N(d_ff3_LUT_out[38]), .A1N(n2158), .B0(n2081), .Y( n907) ); OAI2BB2XLTS U3101 ( .B0(n2097), .B1(d_ff3_LUT_out[39]), .A0N(n2083), .A1N( n2082), .Y(n2084) ); OAI2BB1X1TS U3102 ( .A0N(d_ff3_LUT_out[40]), .A1N(n2158), .B0(n2086), .Y( n905) ); AOI32X1TS U3103 ( .A0(n2090), .A1(n2076), .A2(n2088), .B0(n1516), .B1(n2087), .Y(n904) ); AOI31X1TS U3104 ( .A0(n2195), .A1(n1484), .A2(n2227), .B0(n2091), .Y(n2094) ); OA22X1TS U3105 ( .A0(n2093), .A1(n2098), .B0(n2097), .B1(d_ff3_LUT_out[45]), .Y(n900) ); OA22X1TS U3106 ( .A0(n2099), .A1(n2098), .B0(n2097), .B1(d_ff3_LUT_out[50]), .Y(n895) ); INVX2TS U3107 ( .A(n2180), .Y(n2175) ); INVX2TS U3108 ( .A(n2180), .Y(n2112) ); INVX2TS U3109 ( .A(n2171), .Y(n2107) ); BUFX3TS U3110 ( .A(n2167), .Y(n2109) ); INVX2TS U3111 ( .A(n2182), .Y(n2114) ); INVX2TS U3112 ( .A(n2171), .Y(n2115) ); INVX2TS U3113 ( .A(n2171), .Y(n2110) ); INVX2TS U3114 ( .A(n2178), .Y(n2111) ); INVX2TS U3115 ( .A(n2182), .Y(n2172) ); BUFX3TS U3116 ( .A(n2171), .Y(n2113) ); INVX2TS U3117 ( .A(n2171), .Y(n2119) ); INVX2TS U3118 ( .A(n2178), .Y(n2116) ); BUFX3TS U3119 ( .A(n2167), .Y(n2117) ); CLKBUFX2TS U3120 ( .A(n2180), .Y(n2179) ); INVX2TS U3121 ( .A(n2179), .Y(n2219) ); INVX2TS U3122 ( .A(n2178), .Y(n2218) ); INVX2TS U3123 ( .A(n2179), .Y(n2164) ); INVX2TS U3124 ( .A(n2176), .Y(n2174) ); BUFX3TS U3125 ( .A(n2167), .Y(n2220) ); INVX2TS U3126 ( .A(n2179), .Y(n2186) ); BUFX3TS U3127 ( .A(n2163), .Y(n2161) ); INVX2TS U3128 ( .A(n2178), .Y(n2155) ); BUFX3TS U3129 ( .A(n2120), .Y(n2184) ); BUFX3TS U3130 ( .A(n2184), .Y(n2133) ); OAI22X1TS U3131 ( .A0(n2133), .A1(n2234), .B0(n2121), .B1(n2180), .Y(n720) ); OAI22X1TS U3132 ( .A0(n2133), .A1(n1480), .B0(n2122), .B1(n2185), .Y(n719) ); OAI22X1TS U3133 ( .A0(n2133), .A1(n2232), .B0(n2123), .B1(n2185), .Y(n717) ); OAI22X1TS U3134 ( .A0(n2133), .A1(n2138), .B0(n2124), .B1(n2182), .Y(n716) ); OAI22X1TS U3135 ( .A0(n2133), .A1(n2233), .B0(n2125), .B1(n2131), .Y(n715) ); OAI22X1TS U3136 ( .A0(n2133), .A1(n2127), .B0(n2126), .B1(n2131), .Y(n714) ); OAI22X1TS U3137 ( .A0(n2133), .A1(n2235), .B0(n2128), .B1(n2131), .Y(n713) ); OAI22X1TS U3138 ( .A0(n2133), .A1(n2146), .B0(n2129), .B1(n2131), .Y(n712) ); OAI22X1TS U3139 ( .A0(n2133), .A1(n2236), .B0(n2130), .B1(n2131), .Y(n711) ); OAI22X1TS U3140 ( .A0(n2133), .A1(n2237), .B0(n2132), .B1(n2131), .Y(n710) ); AOI21X1TS U3141 ( .A0(d_ff2_Y[52]), .A1(n2188), .B0(n2136), .Y(n2134) ); AOI22X1TS U3142 ( .A0(n1477), .A1(n1480), .B0(d_ff2_Y[53]), .B1(n1496), .Y( n2135) ); XNOR2X1TS U3143 ( .A(n2136), .B(n2135), .Y(n2137) ); AOI21X1TS U3144 ( .A0(d_ff2_Y[57]), .A1(n2142), .B0(n2141), .Y(n2143) ); AOI21X1TS U3145 ( .A0(d_ff2_Y[59]), .A1(n2144), .B0(n2147), .Y(n2145) ); AOI21X1TS U3146 ( .A0(d_ff2_Y[61]), .A1(n2150), .B0(n2149), .Y(n2151) ); INVX2TS U3147 ( .A(n2182), .Y(n2168) ); OA22X1TS U3148 ( .A0(n2184), .A1(d_ff2_X[3]), .B0(d_ff_Xn[3]), .B1(n2180), .Y(n690) ); OA22X1TS U3149 ( .A0(n2184), .A1(d_ff2_X[6]), .B0(d_ff_Xn[6]), .B1(n2182), .Y(n684) ); INVX2TS U3150 ( .A(n2215), .Y(n2157) ); OA22X1TS U3151 ( .A0(n2184), .A1(d_ff2_X[7]), .B0(d_ff_Xn[7]), .B1(n2180), .Y(n682) ); OA22X1TS U3152 ( .A0(n2184), .A1(d_ff2_X[8]), .B0(d_ff_Xn[8]), .B1(n2182), .Y(n680) ); OA22X1TS U3153 ( .A0(n2184), .A1(d_ff2_X[9]), .B0(d_ff_Xn[9]), .B1(n2179), .Y(n678) ); OA22X1TS U3154 ( .A0(n2102), .A1(d_ff2_X[11]), .B0(d_ff_Xn[11]), .B1(n2179), .Y(n674) ); INVX2TS U3155 ( .A(n2163), .Y(n2159) ); INVX2TS U3156 ( .A(n2176), .Y(n2160) ); INVX2TS U3157 ( .A(n2163), .Y(n2162) ); OA22X1TS U3158 ( .A0(n2170), .A1(d_ff2_X[32]), .B0(d_ff_Xn[32]), .B1(n2166), .Y(n632) ); BUFX3TS U3159 ( .A(n2167), .Y(n2165) ); OA22X1TS U3160 ( .A0(n2170), .A1(d_ff2_X[34]), .B0(d_ff_Xn[34]), .B1(n2166), .Y(n628) ); OA22X1TS U3161 ( .A0(n2170), .A1(d_ff2_X[35]), .B0(d_ff_Xn[35]), .B1(n2166), .Y(n626) ); INVX2TS U3162 ( .A(n2163), .Y(n2169) ); OA22X1TS U3163 ( .A0(n2170), .A1(d_ff2_X[39]), .B0(d_ff_Xn[39]), .B1(n2177), .Y(n618) ); OA22X1TS U3164 ( .A0(n2170), .A1(d_ff2_X[41]), .B0(d_ff_Xn[41]), .B1(n2177), .Y(n614) ); OA22X1TS U3165 ( .A0(n2170), .A1(d_ff2_X[42]), .B0(d_ff_Xn[42]), .B1(n2166), .Y(n612) ); BUFX3TS U3166 ( .A(n2167), .Y(n2173) ); OA22X1TS U3167 ( .A0(n2170), .A1(d_ff2_X[43]), .B0(d_ff_Xn[43]), .B1(n2177), .Y(n610) ); OA22X1TS U3168 ( .A0(n2170), .A1(d_ff2_X[45]), .B0(d_ff_Xn[45]), .B1(n2177), .Y(n606) ); OA22X1TS U3169 ( .A0(n2170), .A1(d_ff2_X[46]), .B0(d_ff_Xn[46]), .B1(n2177), .Y(n604) ); INVX2TS U3170 ( .A(n2171), .Y(n2204) ); OA22X1TS U3171 ( .A0(n2176), .A1(d_ff2_X[53]), .B0(d_ff_Xn[53]), .B1(n2177), .Y(n591) ); OA22X1TS U3172 ( .A0(n2178), .A1(d_ff2_X[54]), .B0(d_ff_Xn[54]), .B1(n2177), .Y(n590) ); OA22X1TS U3173 ( .A0(d_ff_Xn[55]), .A1(n2179), .B0(d_ff2_X[55]), .B1(n2184), .Y(n589) ); OA22X1TS U3174 ( .A0(d_ff_Xn[57]), .A1(n2180), .B0(d_ff2_X[57]), .B1(n2184), .Y(n587) ); OA22X1TS U3175 ( .A0(d_ff_Xn[59]), .A1(n2182), .B0(d_ff2_X[59]), .B1(n2184), .Y(n585) ); OA22X1TS U3176 ( .A0(d_ff_Xn[61]), .A1(n2185), .B0(d_ff2_X[61]), .B1(n2184), .Y(n583) ); AOI21X1TS U3177 ( .A0(d_ff2_X[52]), .A1(n1484), .B0(n2191), .Y(n2189) ); AOI22X1TS U3178 ( .A0(n1500), .A1(n2228), .B0(d_ff2_X[53]), .B1(n1496), .Y( n2190) ); XNOR2X1TS U3179 ( .A(n2191), .B(n2190), .Y(n2192) ); OAI22X1TS U3180 ( .A0(n2197), .A1(d_ff2_X[55]), .B0(n2196), .B1(n2195), .Y( n2198) ); OAI21XLTS U3181 ( .A0(n2198), .A1(n1481), .B0(n2200), .Y(n2199) ); NOR2X2TS U3182 ( .A(d_ff2_X[57]), .B(n2200), .Y(n2202) ); AOI21X1TS U3183 ( .A0(d_ff2_X[57]), .A1(n2200), .B0(n2202), .Y(n2201) ); NOR2X2TS U3184 ( .A(d_ff2_X[59]), .B(n2205), .Y(n2208) ); AOI21X1TS U3185 ( .A0(d_ff2_X[59]), .A1(n2205), .B0(n2208), .Y(n2207) ); NOR2X1TS U3186 ( .A(d_ff2_X[61]), .B(n2210), .Y(n2214) ); AOI21X1TS U3187 ( .A0(d_ff2_X[61]), .A1(n2210), .B0(n2214), .Y(n2212) ); XOR2X1TS U3188 ( .A(d_ff2_X[62]), .B(n2214), .Y(n2216) ); initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk10.tcl_syn.sdf"); endmodule

// MBT 9/6/2014 // // BSG Front Side Bus // // This is a *full duplex* front side bus // that allows output and input traffic // to proceed independently, from nodes // into the bsg out assembler; and from // bsg in assembler to nodes. // // It is designed to interoperate with // the "MURN ring protocol" and nodes, // per UCSC's rnswitch, but without // research features and implementing // full duplex channels instead of a ring // for performance reasons. // // The parameter nodes_p indicates how // many items are to be chained on the fsb. // // bsg_fsb itself does not limit the maximum number // of nodes; however the bsg_fsb_murn_gateway uses // the RingPacketType data structure, which currently // limits us to 4 bits of id's, or 16 nodes. // `ifndef FSB_LEGACY `include "bsg_defines.v" module bsg_fsb #(parameter `BSG_INV_PARAM( width_p ) ,parameter `BSG_INV_PARAM(nodes_p ) // bit vector of master nodes , parameter enabled_at_start_vec_p = (nodes_p) ' (0) , parameter snoop_vec_p = (nodes_p) ' (0) , parameter id_width_p = `BSG_SAFE_CLOG2(nodes_p) ) (input clk_i , input reset_i // from assembler , input asm_v_i , input [width_p-1:0] asm_data_i , output asm_yumi_o // to asm , output asm_v_o , output [width_p-1:0] asm_data_o , input asm_ready_i // into nodes , output [nodes_p-1:0] node_v_o , output [width_p-1:0] node_data_o [nodes_p-1:0] , input [nodes_p-1:0] node_ready_i // into nodes (control) , output [nodes_p-1:0] node_en_r_o , output [nodes_p-1:0] node_reset_r_o // unsupported // , output [nodes_p-1:0] node_powerup_o // out of nodes , input [nodes_p-1:0] node_v_i , input [width_p-1:0] node_data_i [nodes_p-1:0] , output [nodes_p-1:0] node_yumi_o ); genvar i; // index is node this channel goes out of wire [nodes_p-1:0] in_hop_v; wire [width_p-1:0] in_hop_data [nodes_p-1:0]; wire [nodes_p-1:0] in_hop_ready; // index is node this channel goes in to wire [nodes_p-1:0] out_hop_v; wire [width_p-1:0] out_hop_data [nodes_p-1:0]; wire [nodes_p-1:0] out_hop_ready; assign out_hop_v [nodes_p-1] = 1'b0; assign out_hop_data[nodes_p-1] = { (width_p) {1'b0} }; wire to_asm_ready; assign asm_yumi_o = to_asm_ready & asm_v_i; // make sure packets fall off of the end. assign in_hop_ready[nodes_p-1] = 1'b1; for (i = 0; i < nodes_p; i++) begin : fsb_node wire node_ready_int, node_v_int, node_en_r_int; wire [width_p-1:0] node_data_o_int; // m1 = minus 1 wire [width_p-1:0] out_hop_data_m1; wire in_hop_ready_m1, out_hop_v_m1; if (i == 0) begin assign to_asm_ready = in_hop_ready_m1; assign asm_v_o = out_hop_v_m1; assign asm_data_o = out_hop_data_m1; end else begin assign in_hop_ready[i-1] = in_hop_ready_m1; assign out_hop_v[i-1] = out_hop_v_m1; assign out_hop_data[i-1] = out_hop_data_m1; end // note: for critical path optimization, these hops // can be wrapped in an additional loop that // instantiates multiple of these nodes, each of which // handles a subset of data bus. // create a chain of hops going in from assembler bsg_front_side_bus_hop_in #(.width_p(width_p) ,. fan_out_p(2) ) hopin (.clk_i(clk_i) ,.reset_i(reset_i) // (i==0) ? 0: avoid vcs complaint of negative index. ,.ready_o(in_hop_ready_m1) ,.v_i ((i==0) ? asm_v_i : in_hop_v [(i==0) ? i: i-1]) ,.data_i ((i==0) ? asm_data_i : in_hop_data [(i==0) ? i: i-1]) ,.v_o ({node_v_int , in_hop_v [i]}) ,.data_o ({node_data_o_int , in_hop_data [i]}) // 1=local node, 0 is next node // note: the node does valid->ready // but should be located nearby so it's okay ,.ready_i({node_ready_int, in_hop_ready[i]}) ); // create a chain of hops going out to assembler bsg_front_side_bus_hop_out #(.width_p(width_p)) hopout (.clk_i(clk_i) ,.reset_i(reset_i) // we can't transmit data unless the node is enabled ,.v_i ({node_en_r_int & node_v_i [i], out_hop_v [i]}) ,.data_i ({node_data_i [i], out_hop_data[i]}) ,.ready_o(out_hop_ready[i]) ,.yumi_o (node_yumi_o [i]) // (i==0) ? 0: avoid vcs complaint of negative index. ,.v_o (out_hop_v_m1) ,.data_o (out_hop_data_m1) ,.ready_i((i==0) ? asm_ready_i : out_hop_ready[(i==0) ? 0:i-1]) ); bsg_fsb_murn_gateway #(.width_p(width_p) ,.id_width_p( id_width_p ) ,.id_p(i) ,.enabled_at_start_p(enabled_at_start_vec_p[i]) ,.snoop_p(snoop_vec_p[i]) ) murn_gateway (.clk_i (clk_i) ,.reset_i (reset_i) // from gateway ,.v_i (node_v_int) ,.data_i (node_data_o_int) ,.ready_o (node_ready_int) // to node // updated valid bit based on enable // and filtering out switch command packets ,.ready_i (node_ready_i [i]) ,.v_o (node_v_o [i]) ,.node_en_r_o (node_en_r_int ) ,.node_reset_r_o(node_reset_r_o[i]) ); // avoid lint warnings assign node_data_o[i] = node_data_o_int; assign node_en_r_o[i] = node_en_r_int; // synopsys translate_off always @(negedge node_reset_r_o[i]) begin $display(" __ _ _"); $display(" / _| | | | | "); $display(" | |_ ___ | |__ _ __ ___ ___ ___ | |_ "); $display(" | _| / __| | '_ \\ | '__| / _ \\ / __| / _ \\ | __|"); $display(" | | \\__ \\ | |_) | | | | __/ \\__ \\ | __/ | |_ "); $display(" |_| |___/ |_.__/ |_| \\___| |___/ \\___| \\__|"); $display("## reset low on FSB in module %m, node %2d, time = ",i,$stime); end always @(posedge node_en_r_o[i]) begin $display(" __ _ _ _ "); $display(" / _| | | | | | | "); $display(" | |_ ___ | |__ ___ _ __ __ _ | |__ | | ___ "); $display(" | _| / __| | '_ \\ / _ \\ | '_ \\ / _` | | '_ \\ | | / _ \\ "); $display(" | | \\__ \\ | |_) | | __/ | | | | | (_| | | |_) | | | | __/ "); $display(" |_| |___/ |_.__/ \\___| |_| |_| \\__,_| |_.__/ |_| \\___| "); $display("## enable high on FSB in module %m, node %2d, time = ",i, $stime); end // synopsys translate_on end endmodule `BSG_ABSTRACT_MODULE(bsg_fsb) `else module bsg_fsb #(parameter `BSG_INV_PARAM( width_p ) ,parameter `BSG_INV_PARAM(nodes_p ) // bit vector of master nodes , parameter enabled_at_start_vec_p = (nodes_p) ' (0) , parameter snoop_vec_p = (nodes_p) ' (0) ) (input clk_i , input reset_i // from assembler , input asm_v_i , input [width_p-1:0] asm_data_i , output asm_yumi_o // to asm , output asm_v_o , output [width_p-1:0] asm_data_o , input asm_ready_i // into nodes , output [nodes_p-1:0] node_v_o , output [width_p-1:0] node_data_o [nodes_p-1:0] , input [nodes_p-1:0] node_ready_i // into nodes (control) , output [nodes_p-1:0] node_en_r_o , output [nodes_p-1:0] node_reset_r_o // unsupported // , output [nodes_p-1:0] node_powerup_o // out of nodes , input [nodes_p-1:0] node_v_i , input [width_p-1:0] node_data_i [nodes_p-1:0] , output [nodes_p-1:0] node_yumi_o ); genvar i; // index is node this channel goes out of wire [nodes_p-1:0] in_hop_v; wire [width_p-1:0] in_hop_data [nodes_p-1:0]; wire [nodes_p-1:0] in_hop_ready; // index is node this channel goes in to wire [nodes_p-1:0] out_hop_v; wire [width_p-1:0] out_hop_data [nodes_p-1:0]; wire [nodes_p-1:0] out_hop_ready; assign out_hop_v [nodes_p-1] = 1'b0; assign out_hop_data[nodes_p-1] = { (width_p) {1'b0} }; wire to_asm_ready; assign asm_yumi_o = to_asm_ready & asm_v_i; // make sure packets fall off of the end. assign in_hop_ready[nodes_p-1] = 1'b1; for (i = 0; i < nodes_p; i++) begin : fsb_node wire node_ready_int, node_v_int, node_en_r_int; wire [width_p-1:0] node_data_o_int; // m1 = minus 1 wire [width_p-1:0] out_hop_data_m1; wire in_hop_ready_m1, out_hop_v_m1; if (i == 0) begin assign to_asm_ready = in_hop_ready_m1; assign asm_v_o = out_hop_v_m1; assign asm_data_o = out_hop_data_m1; end else begin assign in_hop_ready[i-1] = in_hop_ready_m1; assign out_hop_v[i-1] = out_hop_v_m1; assign out_hop_data[i-1] = out_hop_data_m1; end // note: for critical path optimization, these hops // can be wrapped in an additional loop that // instantiates multiple of these nodes, each of which // handles a subset of data bus. // create a chain of hops going in from assembler bsg_front_side_bus_hop_in #(.width_p(width_p) ,. fan_out_p(2) ) hopin (.clk_i(clk_i) ,.reset_i(reset_i) // (i==0) ? 0: avoid vcs complaint of negative index. ,.ready_o(in_hop_ready_m1) ,.v_i ((i==0) ? asm_v_i : in_hop_v [(i==0) ? i: i-1]) ,.data_i ((i==0) ? asm_data_i : in_hop_data [(i==0) ? i: i-1]) ,.v_o ({node_v_int , in_hop_v [i]}) ,.data_o ({node_data_o_int , in_hop_data [i]}) // 1=local node, 0 is next node // note: the node does valid->ready // but should be located nearby so it's okay ,.ready_i({node_ready_int, in_hop_ready[i]}) ); // create a chain of hops going out to assembler bsg_front_side_bus_hop_out #(.width_p(width_p)) hopout (.clk_i(clk_i) ,.reset_i(reset_i) // we can't transmit data unless the node is enabled ,.v_i ({node_en_r_int & node_v_i [i], out_hop_v [i]}) ,.data_i ({node_data_i [i], out_hop_data[i]}) ,.ready_o(out_hop_ready[i]) ,.yumi_o (node_yumi_o [i]) // (i==0) ? 0: avoid vcs complaint of negative index. ,.v_o (out_hop_v_m1) ,.data_o (out_hop_data_m1) ,.ready_i((i==0) ? asm_ready_i : out_hop_ready[(i==0) ? 0:i-1]) ); bsg_fsb_murn_gateway #(.width_p(width_p) ,.id_p(i) ,.enabled_at_start_p(enabled_at_start_vec_p[i]) ,.snoop_p(snoop_vec_p[i]) ) murn_gateway (.clk_i (clk_i) ,.reset_i (reset_i) // from gateway ,.v_i (node_v_int) ,.data_i (node_data_o_int) ,.ready_o (node_ready_int) // to node // updated valid bit based on enable // and filtering out switch command packets ,.ready_i (node_ready_i [i]) ,.v_o (node_v_o [i]) ,.node_en_r_o (node_en_r_int ) ,.node_reset_r_o(node_reset_r_o[i]) ); // avoid lint warnings assign node_data_o[i] = node_data_o_int; assign node_en_r_o[i] = node_en_r_int; // synopsys translate_off always @(negedge node_reset_r_o[i]) begin $display(" __ _ _"); $display(" / _| | | | | "); $display(" | |_ ___ | |__ _ __ ___ ___ ___ | |_ "); $display(" | _| / __| | '_ \\ | '__| / _ \\ / __| / _ \\ | __|"); $display(" | | \\__ \\ | |_) | | | | __/ \\__ \\ | __/ | |_ "); $display(" |_| |___/ |_.__/ |_| \\___| |___/ \\___| \\__|"); $display("## reset low on FSB in module %m, node %2d, time = ",i,$stime); end always @(posedge node_en_r_o[i]) begin $display(" __ _ _ _ "); $display(" / _| | | | | | | "); $display(" | |_ ___ | |__ ___ _ __ __ _ | |__ | | ___ "); $display(" | _| / __| | '_ \\ / _ \\ | '_ \\ / _` | | '_ \\ | | / _ \\ "); $display(" | | \\__ \\ | |_) | | __/ | | | | | (_| | | |_) | | | | __/ "); $display(" |_| |___/ |_.__/ \\___| |_| |_| \\__,_| |_.__/ |_| \\___| "); $display("## enable high on FSB in module %m, node %2d, time = ",i, $stime); end // synopsys translate_on end endmodule `BSG_ABSTRACT_MODULE(bsg_fsb) `endif

module HeadFieldExtractor ( input wire[63:0] din_data, input wire din_last, output wire din_ready, input wire din_valid, output wire[63:0] dout_data, output wire dout_last, input wire dout_ready, output wire dout_valid, output wire[63:0] headers_data, output wire headers_last, input wire headers_ready, output wire headers_valid ); assign din_ready = 1'bx; assign dout_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; assign dout_last = 1'bx; assign dout_valid = 1'bx; assign headers_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; assign headers_last = 1'bx; assign headers_valid = 1'bx; endmodule module PatternMatch ( input wire[63:0] din_data, input wire din_last, output wire din_ready, input wire din_valid, output wire[63:0] match_data, output wire match_last, input wire match_ready, output wire match_valid ); assign din_ready = 1'bx; assign match_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; assign match_last = 1'bx; assign match_valid = 1'bx; endmodule module Filter ( input wire[31:0] cfg_ar_addr, input wire[2:0] cfg_ar_prot, output wire cfg_ar_ready, input wire cfg_ar_valid, input wire[31:0] cfg_aw_addr, input wire[2:0] cfg_aw_prot, output wire cfg_aw_ready, input wire cfg_aw_valid, input wire cfg_b_ready, output wire[1:0] cfg_b_resp, output wire cfg_b_valid, output wire[63:0] cfg_r_data, input wire cfg_r_ready, output wire[1:0] cfg_r_resp, output wire cfg_r_valid, input wire[63:0] cfg_w_data, output wire cfg_w_ready, input wire[7:0] cfg_w_strb, input wire cfg_w_valid, input wire[63:0] din_data, input wire din_last, output wire din_ready, input wire din_valid, output wire[63:0] dout_data, output wire dout_last, input wire dout_ready, output wire dout_valid, input wire[63:0] headers_data, input wire headers_last, output wire headers_ready, input wire headers_valid, input wire[63:0] patternMatch_data, input wire patternMatch_last, output wire patternMatch_ready, input wire patternMatch_valid ); assign cfg_ar_ready = 1'bx; assign cfg_aw_ready = 1'bx; assign cfg_b_resp = 2'bxx; assign cfg_b_valid = 1'bx; assign cfg_r_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; assign cfg_r_resp = 2'bxx; assign cfg_r_valid = 1'bx; assign cfg_w_ready = 1'bx; assign din_ready = 1'bx; assign dout_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; assign dout_last = 1'bx; assign dout_valid = 1'bx; assign headers_ready = 1'bx; assign patternMatch_ready = 1'bx; endmodule module Exporter ( input wire[63:0] din_data, input wire din_last, output wire din_ready, input wire din_valid, output wire[63:0] dout_data, output wire dout_last, input wire dout_ready, output wire dout_valid ); assign din_ready = 1'bx; assign dout_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; assign dout_last = 1'bx; assign dout_valid = 1'bx; endmodule // // Stream duplicator for AxiStream interfaces // // :see: :class:`hwtLib.handshaked.splitCopy.HsSplitCopy` // // .. hwt-autodoc:: // module AxiSSplitCopy #( parameter DATA_WIDTH = 64, parameter DEST_WIDTH = 0, parameter ID_WIDTH = 0, parameter INTF_CLS = "<class 'hwtLib.amba.axis.AxiStream'>", parameter IS_BIGENDIAN = 0, parameter OUTPUTS = 2, parameter USER_WIDTH = 0, parameter USE_KEEP = 0, parameter USE_STRB = 0 ) ( input wire[63:0] dataIn_data, input wire dataIn_last, output reg dataIn_ready, input wire dataIn_valid, output wire[63:0] dataOut_0_data, output wire dataOut_0_last, input wire dataOut_0_ready, output reg dataOut_0_valid, output wire[63:0] dataOut_1_data, output wire dataOut_1_last, input wire dataOut_1_ready, output reg dataOut_1_valid ); always @(dataOut_0_ready, dataOut_1_ready) begin: assig_process_dataIn_ready dataIn_ready = dataOut_0_ready & dataOut_1_ready; end assign dataOut_0_data = dataIn_data; assign dataOut_0_last = dataIn_last; always @(dataIn_valid, dataOut_1_ready) begin: assig_process_dataOut_0_valid dataOut_0_valid = dataIn_valid & dataOut_1_ready; end assign dataOut_1_data = dataIn_data; assign dataOut_1_last = dataIn_last; always @(dataIn_valid, dataOut_0_ready) begin: assig_process_dataOut_1_valid dataOut_1_valid = dataIn_valid & dataOut_0_ready; end generate if (DATA_WIDTH != 64) $error("%m Generated only for this param value"); endgenerate generate if (DEST_WIDTH != 0) $error("%m Generated only for this param value"); endgenerate generate if (ID_WIDTH != 0) $error("%m Generated only for this param value"); endgenerate generate if (INTF_CLS != "<class 'hwtLib.amba.axis.AxiStream'>") $error("%m Generated only for this param value"); endgenerate generate if (IS_BIGENDIAN != 0) $error("%m Generated only for this param value"); endgenerate generate if (OUTPUTS != 2) $error("%m Generated only for this param value"); endgenerate generate if (USER_WIDTH != 0) $error("%m Generated only for this param value"); endgenerate generate if (USE_KEEP != 0) $error("%m Generated only for this param value"); endgenerate generate if (USE_STRB != 0) $error("%m Generated only for this param value"); endgenerate endmodule // // This unit has actually no functionality it is just example // of hierarchical design. // // .. hwt-autodoc:: // module NetFilter #( parameter DATA_WIDTH = 64 ) ( input wire[31:0] cfg_ar_addr, input wire[2:0] cfg_ar_prot, output wire cfg_ar_ready, input wire cfg_ar_valid, input wire[31:0] cfg_aw_addr, input wire[2:0] cfg_aw_prot, output wire cfg_aw_ready, input wire cfg_aw_valid, input wire cfg_b_ready, output wire[1:0] cfg_b_resp, output wire cfg_b_valid, output wire[63:0] cfg_r_data, input wire cfg_r_ready, output wire[1:0] cfg_r_resp, output wire cfg_r_valid, input wire[63:0] cfg_w_data, output wire cfg_w_ready, input wire[7:0] cfg_w_strb, input wire cfg_w_valid, input wire clk, input wire[63:0] din_data, input wire din_last, output wire din_ready, input wire din_valid, output wire[63:0] export_data, output wire export_last, input wire export_ready, output wire export_valid, input wire rst_n ); wire[63:0] sig_exporter_din_data; wire sig_exporter_din_last; wire sig_exporter_din_ready; wire sig_exporter_din_valid; wire[63:0] sig_exporter_dout_data; wire sig_exporter_dout_last; wire sig_exporter_dout_ready; wire sig_exporter_dout_valid; wire[31:0] sig_filter_cfg_ar_addr; wire[2:0] sig_filter_cfg_ar_prot; wire sig_filter_cfg_ar_ready; wire sig_filter_cfg_ar_valid; wire[31:0] sig_filter_cfg_aw_addr; wire[2:0] sig_filter_cfg_aw_prot; wire sig_filter_cfg_aw_ready; wire sig_filter_cfg_aw_valid; wire sig_filter_cfg_b_ready; wire[1:0] sig_filter_cfg_b_resp; wire sig_filter_cfg_b_valid; wire[63:0] sig_filter_cfg_r_data; wire sig_filter_cfg_r_ready; wire[1:0] sig_filter_cfg_r_resp; wire sig_filter_cfg_r_valid; wire[63:0] sig_filter_cfg_w_data; wire sig_filter_cfg_w_ready; wire[7:0] sig_filter_cfg_w_strb; wire sig_filter_cfg_w_valid; wire[63:0] sig_filter_din_data; wire sig_filter_din_last; wire sig_filter_din_ready; wire sig_filter_din_valid; wire[63:0] sig_filter_dout_data; wire sig_filter_dout_last; wire sig_filter_dout_ready; wire sig_filter_dout_valid; wire[63:0] sig_filter_headers_data; wire sig_filter_headers_last; wire sig_filter_headers_ready; wire sig_filter_headers_valid; wire[63:0] sig_filter_patternMatch_data; wire sig_filter_patternMatch_last; wire sig_filter_patternMatch_ready; wire sig_filter_patternMatch_valid; wire[63:0] sig_gen_dout_splitCopy_0_dataIn_data; wire sig_gen_dout_splitCopy_0_dataIn_last; wire sig_gen_dout_splitCopy_0_dataIn_ready; wire sig_gen_dout_splitCopy_0_dataIn_valid; wire[63:0] sig_gen_dout_splitCopy_0_dataOut_0_data; wire sig_gen_dout_splitCopy_0_dataOut_0_last; wire sig_gen_dout_splitCopy_0_dataOut_0_ready; wire sig_gen_dout_splitCopy_0_dataOut_0_valid; wire[63:0] sig_gen_dout_splitCopy_0_dataOut_1_data; wire sig_gen_dout_splitCopy_0_dataOut_1_last; wire sig_gen_dout_splitCopy_0_dataOut_1_ready; wire sig_gen_dout_splitCopy_0_dataOut_1_valid; wire[63:0] sig_hfe_din_data; wire sig_hfe_din_last; wire sig_hfe_din_ready; wire sig_hfe_din_valid; wire[63:0] sig_hfe_dout_data; wire sig_hfe_dout_last; wire sig_hfe_dout_ready; wire sig_hfe_dout_valid; wire[63:0] sig_hfe_headers_data; wire sig_hfe_headers_last; wire sig_hfe_headers_ready; wire sig_hfe_headers_valid; wire[63:0] sig_patternMatch_din_data; wire sig_patternMatch_din_last; wire sig_patternMatch_din_ready; wire sig_patternMatch_din_valid; wire[63:0] sig_patternMatch_match_data; wire sig_patternMatch_match_last; wire sig_patternMatch_match_ready; wire sig_patternMatch_match_valid; Exporter exporter_inst ( .din_data(sig_exporter_din_data), .din_last(sig_exporter_din_last), .din_ready(sig_exporter_din_ready), .din_valid(sig_exporter_din_valid), .dout_data(sig_exporter_dout_data), .dout_last(sig_exporter_dout_last), .dout_ready(sig_exporter_dout_ready), .dout_valid(sig_exporter_dout_valid) ); Filter filter_inst ( .cfg_ar_addr(sig_filter_cfg_ar_addr), .cfg_ar_prot(sig_filter_cfg_ar_prot), .cfg_ar_ready(sig_filter_cfg_ar_ready), .cfg_ar_valid(sig_filter_cfg_ar_valid), .cfg_aw_addr(sig_filter_cfg_aw_addr), .cfg_aw_prot(sig_filter_cfg_aw_prot), .cfg_aw_ready(sig_filter_cfg_aw_ready), .cfg_aw_valid(sig_filter_cfg_aw_valid), .cfg_b_ready(sig_filter_cfg_b_ready), .cfg_b_resp(sig_filter_cfg_b_resp), .cfg_b_valid(sig_filter_cfg_b_valid), .cfg_r_data(sig_filter_cfg_r_data), .cfg_r_ready(sig_filter_cfg_r_ready), .cfg_r_resp(sig_filter_cfg_r_resp), .cfg_r_valid(sig_filter_cfg_r_valid), .cfg_w_data(sig_filter_cfg_w_data), .cfg_w_ready(sig_filter_cfg_w_ready), .cfg_w_strb(sig_filter_cfg_w_strb), .cfg_w_valid(sig_filter_cfg_w_valid), .din_data(sig_filter_din_data), .din_last(sig_filter_din_last), .din_ready(sig_filter_din_ready), .din_valid(sig_filter_din_valid), .dout_data(sig_filter_dout_data), .dout_last(sig_filter_dout_last), .dout_ready(sig_filter_dout_ready), .dout_valid(sig_filter_dout_valid), .headers_data(sig_filter_headers_data), .headers_last(sig_filter_headers_last), .headers_ready(sig_filter_headers_ready), .headers_valid(sig_filter_headers_valid), .patternMatch_data(sig_filter_patternMatch_data), .patternMatch_last(sig_filter_patternMatch_last), .patternMatch_ready(sig_filter_patternMatch_ready), .patternMatch_valid(sig_filter_patternMatch_valid) ); AxiSSplitCopy #( .DATA_WIDTH(64), .DEST_WIDTH(0), .ID_WIDTH(0), .INTF_CLS("<class 'hwtLib.amba.axis.AxiStream'>"), .IS_BIGENDIAN(0), .OUTPUTS(2), .USER_WIDTH(0), .USE_KEEP(0), .USE_STRB(0) ) gen_dout_splitCopy_0_inst ( .dataIn_data(sig_gen_dout_splitCopy_0_dataIn_data), .dataIn_last(sig_gen_dout_splitCopy_0_dataIn_last), .dataIn_ready(sig_gen_dout_splitCopy_0_dataIn_ready), .dataIn_valid(sig_gen_dout_splitCopy_0_dataIn_valid), .dataOut_0_data(sig_gen_dout_splitCopy_0_dataOut_0_data), .dataOut_0_last(sig_gen_dout_splitCopy_0_dataOut_0_last), .dataOut_0_ready(sig_gen_dout_splitCopy_0_dataOut_0_ready), .dataOut_0_valid(sig_gen_dout_splitCopy_0_dataOut_0_valid), .dataOut_1_data(sig_gen_dout_splitCopy_0_dataOut_1_data), .dataOut_1_last(sig_gen_dout_splitCopy_0_dataOut_1_last), .dataOut_1_ready(sig_gen_dout_splitCopy_0_dataOut_1_ready), .dataOut_1_valid(sig_gen_dout_splitCopy_0_dataOut_1_valid) ); HeadFieldExtractor hfe_inst ( .din_data(sig_hfe_din_data), .din_last(sig_hfe_din_last), .din_ready(sig_hfe_din_ready), .din_valid(sig_hfe_din_valid), .dout_data(sig_hfe_dout_data), .dout_last(sig_hfe_dout_last), .dout_ready(sig_hfe_dout_ready), .dout_valid(sig_hfe_dout_valid), .headers_data(sig_hfe_headers_data), .headers_last(sig_hfe_headers_last), .headers_ready(sig_hfe_headers_ready), .headers_valid(sig_hfe_headers_valid) ); PatternMatch patternMatch_inst ( .din_data(sig_patternMatch_din_data), .din_last(sig_patternMatch_din_last), .din_ready(sig_patternMatch_din_ready), .din_valid(sig_patternMatch_din_valid), .match_data(sig_patternMatch_match_data), .match_last(sig_patternMatch_match_last), .match_ready(sig_patternMatch_match_ready), .match_valid(sig_patternMatch_match_valid) ); assign cfg_ar_ready = sig_filter_cfg_ar_ready; assign cfg_aw_ready = sig_filter_cfg_aw_ready; assign cfg_b_resp = sig_filter_cfg_b_resp; assign cfg_b_valid = sig_filter_cfg_b_valid; assign cfg_r_data = sig_filter_cfg_r_data; assign cfg_r_resp = sig_filter_cfg_r_resp; assign cfg_r_valid = sig_filter_cfg_r_valid; assign cfg_w_ready = sig_filter_cfg_w_ready; assign din_ready = sig_hfe_din_ready; assign export_data = sig_exporter_dout_data; assign export_last = sig_exporter_dout_last; assign export_valid = sig_exporter_dout_valid; assign sig_exporter_din_data = sig_filter_dout_data; assign sig_exporter_din_last = sig_filter_dout_last; assign sig_exporter_din_valid = sig_filter_dout_valid; assign sig_exporter_dout_ready = export_ready; assign sig_filter_cfg_ar_addr = cfg_ar_addr; assign sig_filter_cfg_ar_prot = cfg_ar_prot; assign sig_filter_cfg_ar_valid = cfg_ar_valid; assign sig_filter_cfg_aw_addr = cfg_aw_addr; assign sig_filter_cfg_aw_prot = cfg_aw_prot; assign sig_filter_cfg_aw_valid = cfg_aw_valid; assign sig_filter_cfg_b_ready = cfg_b_ready; assign sig_filter_cfg_r_ready = cfg_r_ready; assign sig_filter_cfg_w_data = cfg_w_data; assign sig_filter_cfg_w_strb = cfg_w_strb; assign sig_filter_cfg_w_valid = cfg_w_valid; assign sig_filter_din_data = sig_gen_dout_splitCopy_0_dataOut_1_data; assign sig_filter_din_last = sig_gen_dout_splitCopy_0_dataOut_1_last; assign sig_filter_din_valid = sig_gen_dout_splitCopy_0_dataOut_1_valid; assign sig_filter_dout_ready = sig_exporter_din_ready; assign sig_filter_headers_data = sig_hfe_headers_data; assign sig_filter_headers_last = sig_hfe_headers_last; assign sig_filter_headers_valid = sig_hfe_headers_valid; assign sig_filter_patternMatch_data = sig_patternMatch_match_data; assign sig_filter_patternMatch_last = sig_patternMatch_match_last; assign sig_filter_patternMatch_valid = sig_patternMatch_match_valid; assign sig_gen_dout_splitCopy_0_dataIn_data = sig_hfe_dout_data; assign sig_gen_dout_splitCopy_0_dataIn_last = sig_hfe_dout_last; assign sig_gen_dout_splitCopy_0_dataIn_valid = sig_hfe_dout_valid; assign sig_gen_dout_splitCopy_0_dataOut_0_ready = sig_patternMatch_din_ready; assign sig_gen_dout_splitCopy_0_dataOut_1_ready = sig_filter_din_ready; assign sig_hfe_din_data = din_data; assign sig_hfe_din_last = din_last; assign sig_hfe_din_valid = din_valid; assign sig_hfe_dout_ready = sig_gen_dout_splitCopy_0_dataIn_ready; assign sig_hfe_headers_ready = sig_filter_headers_ready; assign sig_patternMatch_din_data = sig_gen_dout_splitCopy_0_dataOut_0_data; assign sig_patternMatch_din_last = sig_gen_dout_splitCopy_0_dataOut_0_last; assign sig_patternMatch_din_valid = sig_gen_dout_splitCopy_0_dataOut_0_valid; assign sig_patternMatch_match_ready = sig_filter_patternMatch_ready; generate if (DATA_WIDTH != 64) $error("%m Generated only for this param value"); endgenerate endmodule

(************************************************************************) (* * The Coq Proof Assistant / The Coq Development Team *) (* v * INRIA, CNRS and contributors - Copyright 1999-2019 *) (* <O___,, * (see CREDITS file for the list of authors) *) (* \VV/ **************************************************************) (* // * This file is distributed under the terms of the *) (* * GNU Lesser General Public License Version 2.1 *) (* * (see LICENSE file for the text of the license) *) (************************************************************************) (** * MSetRBT : Implementation of MSetInterface via Red-Black trees *) (** Initial author: Andrew W. Appel, 2011. Extra modifications by: Pierre Letouzey The design decisions behind this implementation are described here: - Efficient Verified Red-Black Trees, by Andrew W. Appel, September 2011. http://www.cs.princeton.edu/~appel/papers/redblack.pdf Additional suggested reading: - Red-Black Trees in a Functional Setting by Chris Okasaki. Journal of Functional Programming, 9(4):471-477, July 1999. http://www.eecs.usma.edu/webs/people/okasaki/jfp99redblack.pdf - Red-black trees with types, by Stefan Kahrs. Journal of Functional Programming, 11(4), 425-432, 2001. - Functors for Proofs and Programs, by J.-C. Filliatre and P. Letouzey. ESOP'04: European Symposium on Programming, pp. 370-384, 2004. http://www.lri.fr/~filliatr/ftp/publis/fpp.ps.gz *) Require MSetGenTree. Require Import Bool List BinPos Pnat Setoid SetoidList PeanoNat. Local Open Scope list_scope. (* For nicer extraction, we create induction principles only when needed *) Local Unset Elimination Schemes. (** An extra function not (yet?) in MSetInterface.S *) Module Type MSetRemoveMin (Import M:MSetInterface.S). Parameter remove_min : t -> option (elt * t). Axiom remove_min_spec1 : forall s k s', remove_min s = Some (k,s') -> min_elt s = Some k /\ remove k s [=] s'. Axiom remove_min_spec2 : forall s, remove_min s = None -> Empty s. End MSetRemoveMin. (** The type of color annotation. *) Inductive color := Red | Black. Module Color. Definition t := color. End Color. (** * Ops : the pure functions *) Module Ops (X:Orders.OrderedType) <: MSetInterface.Ops X. (** ** Generic trees instantiated with color *) (** We reuse a generic definition of trees where the information parameter is a color. Functions like mem or fold are also provided by this generic functor. *) Include MSetGenTree.Ops X Color. Definition t := tree. Local Notation Rd := (Node Red). Local Notation Bk := (Node Black). (** ** Basic tree *) Definition singleton (k: elt) : tree := Bk Leaf k Leaf. (** ** Changing root color *) Definition makeBlack t := match t with | Leaf => Leaf | Node _ a x b => Bk a x b end. Definition makeRed t := match t with | Leaf => Leaf | Node _ a x b => Rd a x b end. (** ** Balancing *) (** We adapt when one side is not a true red-black tree. Both sides have the same black depth. *) Definition lbal l k r := match l with | Rd (Rd a x b) y c => Rd (Bk a x b) y (Bk c k r) | Rd a x (Rd b y c) => Rd (Bk a x b) y (Bk c k r) | _ => Bk l k r end. Definition rbal l k r := match r with | Rd (Rd b y c) z d => Rd (Bk l k b) y (Bk c z d) | Rd b y (Rd c z d) => Rd (Bk l k b) y (Bk c z d) | _ => Bk l k r end. (** A variant of [rbal], with reverse pattern order. Is it really useful ? Should we always use it ? *) Definition rbal' l k r := match r with | Rd b y (Rd c z d) => Rd (Bk l k b) y (Bk c z d) | Rd (Rd b y c) z d => Rd (Bk l k b) y (Bk c z d) | _ => Bk l k r end. (** Balancing with different black depth. One side is almost a red-black tree, while the other is a true red-black tree, but with black depth + 1. Used in deletion. *) Definition lbalS l k r := match l with | Rd a x b => Rd (Bk a x b) k r | _ => match r with | Bk a y b => rbal' l k (Rd a y b) | Rd (Bk a y b) z c => Rd (Bk l k a) y (rbal' b z (makeRed c)) | _ => Rd l k r (* impossible *) end end. Definition rbalS l k r := match r with | Rd b y c => Rd l k (Bk b y c) | _ => match l with | Bk a x b => lbal (Rd a x b) k r | Rd a x (Bk b y c) => Rd (lbal (makeRed a) x b) y (Bk c k r) | _ => Rd l k r (* impossible *) end end. (** ** Insertion *) Fixpoint ins x s := match s with | Leaf => Rd Leaf x Leaf | Node c l y r => match X.compare x y with | Eq => s | Lt => match c with | Red => Rd (ins x l) y r | Black => lbal (ins x l) y r end | Gt => match c with | Red => Rd l y (ins x r) | Black => rbal l y (ins x r) end end end. Definition add x s := makeBlack (ins x s). (** ** Deletion *) Fixpoint append (l:tree) : tree -> tree := match l with | Leaf => fun r => r | Node lc ll lx lr => fix append_l (r:tree) : tree := match r with | Leaf => l | Node rc rl rx rr => match lc, rc with | Red, Red => let lrl := append lr rl in match lrl with | Rd lr' x rl' => Rd (Rd ll lx lr') x (Rd rl' rx rr) | _ => Rd ll lx (Rd lrl rx rr) end | Black, Black => let lrl := append lr rl in match lrl with | Rd lr' x rl' => Rd (Bk ll lx lr') x (Bk rl' rx rr) | _ => lbalS ll lx (Bk lrl rx rr) end | Black, Red => Rd (append_l rl) rx rr | Red, Black => Rd ll lx (append lr r) end end end. Fixpoint del x t := match t with | Leaf => Leaf | Node _ a y b => match X.compare x y with | Eq => append a b | Lt => match a with | Bk _ _ _ => lbalS (del x a) y b | _ => Rd (del x a) y b end | Gt => match b with | Bk _ _ _ => rbalS a y (del x b) | _ => Rd a y (del x b) end end end. Definition remove x t := makeBlack (del x t). (** ** Removing minimal element *) Fixpoint delmin l x r : (elt * tree) := match l with | Leaf => (x,r) | Node lc ll lx lr => let (k,l') := delmin ll lx lr in match lc with | Black => (k, lbalS l' x r) | Red => (k, Rd l' x r) end end. Definition remove_min t : option (elt * tree) := match t with | Leaf => None | Node _ l x r => let (k,t) := delmin l x r in Some (k, makeBlack t) end. (** ** Tree-ification We rebuild a tree of size [if pred then n-1 else n] as soon as the list [l] has enough elements *) Definition bogus : tree * list elt := (Leaf, nil). Notation treeify_t := (list elt -> tree * list elt). Definition treeify_zero : treeify_t := fun acc => (Leaf,acc). Definition treeify_one : treeify_t := fun acc => match acc with | x::acc => (Rd Leaf x Leaf, acc) | _ => bogus end. Definition treeify_cont (f g : treeify_t) : treeify_t := fun acc => match f acc with | (l, x::acc) => match g acc with | (r, acc) => (Bk l x r, acc) end | _ => bogus end. Fixpoint treeify_aux (pred:bool)(n: positive) : treeify_t := match n with | xH => if pred then treeify_zero else treeify_one | xO n => treeify_cont (treeify_aux pred n) (treeify_aux true n) | xI n => treeify_cont (treeify_aux false n) (treeify_aux pred n) end. Fixpoint plength_aux (l:list elt)(p:positive) := match l with | nil => p | _::l => plength_aux l (Pos.succ p) end. Definition plength l := plength_aux l 1. Definition treeify (l:list elt) := fst (treeify_aux true (plength l) l). (** ** Filtering *) Fixpoint filter_aux (f: elt -> bool) s acc := match s with | Leaf => acc | Node _ l k r => let acc := filter_aux f r acc in if f k then filter_aux f l (k::acc) else filter_aux f l acc end. Definition filter (f: elt -> bool) (s: t) : t := treeify (filter_aux f s nil). Fixpoint partition_aux (f: elt -> bool) s acc1 acc2 := match s with | Leaf => (acc1,acc2) | Node _ sl k sr => let (acc1, acc2) := partition_aux f sr acc1 acc2 in if f k then partition_aux f sl (k::acc1) acc2 else partition_aux f sl acc1 (k::acc2) end. Definition partition (f: elt -> bool) (s:t) : t*t := let (ok,ko) := partition_aux f s nil nil in (treeify ok, treeify ko). (** ** Union, intersection, difference *) (** union of the elements of [l1] and [l2] into a third [acc] list. *) Fixpoint union_list l1 : list elt -> list elt -> list elt := match l1 with | nil => @rev_append _ | x::l1' => fix union_l1 l2 acc := match l2 with | nil => rev_append l1 acc | y::l2' => match X.compare x y with | Eq => union_list l1' l2' (x::acc) | Lt => union_l1 l2' (y::acc) | Gt => union_list l1' l2 (x::acc) end end end. Definition linear_union s1 s2 := treeify (union_list (rev_elements s1) (rev_elements s2) nil). Fixpoint inter_list l1 : list elt -> list elt -> list elt := match l1 with | nil => fun _ acc => acc | x::l1' => fix inter_l1 l2 acc := match l2 with | nil => acc | y::l2' => match X.compare x y with | Eq => inter_list l1' l2' (x::acc) | Lt => inter_l1 l2' acc | Gt => inter_list l1' l2 acc end end end. Definition linear_inter s1 s2 := treeify (inter_list (rev_elements s1) (rev_elements s2) nil). Fixpoint diff_list l1 : list elt -> list elt -> list elt := match l1 with | nil => fun _ acc => acc | x::l1' => fix diff_l1 l2 acc := match l2 with | nil => rev_append l1 acc | y::l2' => match X.compare x y with | Eq => diff_list l1' l2' acc | Lt => diff_l1 l2' acc | Gt => diff_list l1' l2 (x::acc) end end end. Definition linear_diff s1 s2 := treeify (diff_list (rev_elements s1) (rev_elements s2) nil). (** [compare_height] returns: - [Lt] if [height s2] is at least twice [height s1]; - [Gt] if [height s1] is at least twice [height s2]; - [Eq] if heights are approximately equal. Warning: this is not an equivalence relation! but who cares.... *) Definition skip_red t := match t with | Rd t' _ _ => t' | _ => t end. Definition skip_black t := match skip_red t with | Bk t' _ _ => t' | t' => t' end. Fixpoint compare_height (s1x s1 s2 s2x: tree) : comparison := match skip_red s1x, skip_red s1, skip_red s2, skip_red s2x with | Node _ s1x' _ _, Node _ s1' _ _, Node _ s2' _ _, Node _ s2x' _ _ => compare_height (skip_black s1x') s1' s2' (skip_black s2x') | _, Leaf, _, Node _ _ _ _ => Lt | Node _ _ _ _, _, Leaf, _ => Gt | Node _ s1x' _ _, Node _ s1' _ _, Node _ s2' _ _, Leaf => compare_height (skip_black s1x') s1' s2' Leaf | Leaf, Node _ s1' _ _, Node _ s2' _ _, Node _ s2x' _ _ => compare_height Leaf s1' s2' (skip_black s2x') | _, _, _, _ => Eq end. (** When one tree is quite smaller than the other, we simply adds repeatively all its elements in the big one. For trees of comparable height, we rather use [linear_union]. *) Definition union (t1 t2: t) : t := match compare_height t1 t1 t2 t2 with | Lt => fold add t1 t2 | Gt => fold add t2 t1 | Eq => linear_union t1 t2 end. Definition diff (t1 t2: t) : t := match compare_height t1 t1 t2 t2 with | Lt => filter (fun k => negb (mem k t2)) t1 | Gt => fold remove t2 t1 | Eq => linear_diff t1 t2 end. Definition inter (t1 t2: t) : t := match compare_height t1 t1 t2 t2 with | Lt => filter (fun k => mem k t2) t1 | Gt => filter (fun k => mem k t1) t2 | Eq => linear_inter t1 t2 end. End Ops. (** * MakeRaw : the pure functions and their specifications *) Module Type MakeRaw (X:Orders.OrderedType) <: MSetInterface.RawSets X. Include Ops X. (** Generic definition of binary-search-trees and proofs of specifications for generic functions such as mem or fold. *) Include MSetGenTree.Props X Color. Local Notation Rd := (Node Red). Local Notation Bk := (Node Black). Local Hint Immediate MX.eq_sym : core. Local Hint Unfold In lt_tree gt_tree Ok : core. Local Hint Constructors InT bst : core. Local Hint Resolve MX.eq_refl MX.eq_trans MX.lt_trans ok : core. Local Hint Resolve lt_leaf gt_leaf lt_tree_node gt_tree_node : core. Local Hint Resolve lt_tree_not_in lt_tree_trans gt_tree_not_in gt_tree_trans : core. Local Hint Resolve elements_spec2 : core. (** ** Singleton set *) Lemma singleton_spec x y : InT y (singleton x) <-> X.eq y x. Proof. unfold singleton; intuition_in. Qed. Instance singleton_ok x : Ok (singleton x). Proof. unfold singleton; auto. Qed. (** ** makeBlack, MakeRed *) Lemma makeBlack_spec s x : InT x (makeBlack s) <-> InT x s. Proof. destruct s; simpl; intuition_in. Qed. Lemma makeRed_spec s x : InT x (makeRed s) <-> InT x s. Proof. destruct s; simpl; intuition_in. Qed. Instance makeBlack_ok s `{Ok s} : Ok (makeBlack s). Proof. destruct s; simpl; ok. Qed. Instance makeRed_ok s `{Ok s} : Ok (makeRed s). Proof. destruct s; simpl; ok. Qed. (** ** Generic handling for red-matching and red-red-matching *) Definition isblack t := match t with Bk _ _ _ => True | _ => False end. Definition notblack t := match t with Bk _ _ _ => False | _ => True end. Definition notred t := match t with Rd _ _ _ => False | _ => True end. Definition rcase {A} f g t : A := match t with | Rd a x b => f a x b | _ => g t end. Inductive rspec {A} f g : tree -> A -> Prop := | rred a x b : rspec f g (Rd a x b) (f a x b) | relse t : notred t -> rspec f g t (g t). Fact rmatch {A} f g t : rspec (A:=A) f g t (rcase f g t). Proof. destruct t as [|[|] l x r]; simpl; now constructor. Qed. Definition rrcase {A} f g t : A := match t with | Rd (Rd a x b) y c => f a x b y c | Rd a x (Rd b y c) => f a x b y c | _ => g t end. Notation notredred := (rrcase (fun _ _ _ _ _ => False) (fun _ => True)). Inductive rrspec {A} f g : tree -> A -> Prop := | rrleft a x b y c : rrspec f g (Rd (Rd a x b) y c) (f a x b y c) | rrright a x b y c : rrspec f g (Rd a x (Rd b y c)) (f a x b y c) | rrelse t : notredred t -> rrspec f g t (g t). Fact rrmatch {A} f g t : rrspec (A:=A) f g t (rrcase f g t). Proof. destruct t as [|[|] l x r]; simpl; try now constructor. destruct l as [|[|] ll lx lr], r as [|[|] rl rx rr]; now constructor. Qed. Definition rrcase' {A} f g t : A := match t with | Rd a x (Rd b y c) => f a x b y c | Rd (Rd a x b) y c => f a x b y c | _ => g t end. Fact rrmatch' {A} f g t : rrspec (A:=A) f g t (rrcase' f g t). Proof. destruct t as [|[|] l x r]; simpl; try now constructor. destruct l as [|[|] ll lx lr], r as [|[|] rl rx rr]; now constructor. Qed. (** Balancing operations are instances of generic match *) Fact lbal_match l k r : rrspec (fun a x b y c => Rd (Bk a x b) y (Bk c k r)) (fun l => Bk l k r) l (lbal l k r). Proof. exact (rrmatch _ _ _). Qed. Fact rbal_match l k r : rrspec (fun a x b y c => Rd (Bk l k a) x (Bk b y c)) (fun r => Bk l k r) r (rbal l k r). Proof. exact (rrmatch _ _ _). Qed. Fact rbal'_match l k r : rrspec (fun a x b y c => Rd (Bk l k a) x (Bk b y c)) (fun r => Bk l k r) r (rbal' l k r). Proof. exact (rrmatch' _ _ _). Qed. Fact lbalS_match l x r : rspec (fun a y b => Rd (Bk a y b) x r) (fun l => match r with | Bk a y b => rbal' l x (Rd a y b) | Rd (Bk a y b) z c => Rd (Bk l x a) y (rbal' b z (makeRed c)) | _ => Rd l x r end) l (lbalS l x r). Proof. exact (rmatch _ _ _). Qed. Fact rbalS_match l x r : rspec (fun a y b => Rd l x (Bk a y b)) (fun r => match l with | Bk a y b => lbal (Rd a y b) x r | Rd a y (Bk b z c) => Rd (lbal (makeRed a) y b) z (Bk c x r) | _ => Rd l x r end) r (rbalS l x r). Proof. exact (rmatch _ _ _). Qed. (** ** Balancing for insertion *) Lemma lbal_spec l x r y : InT y (lbal l x r) <-> X.eq y x \/ InT y l \/ InT y r. Proof. case lbal_match; intuition_in. Qed. Instance lbal_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) : Ok (lbal l x r). Proof. destruct (lbal_match l x r); ok. Qed. Lemma rbal_spec l x r y : InT y (rbal l x r) <-> X.eq y x \/ InT y l \/ InT y r. Proof. case rbal_match; intuition_in. Qed. Instance rbal_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) : Ok (rbal l x r). Proof. destruct (rbal_match l x r); ok. Qed. Lemma rbal'_spec l x r y : InT y (rbal' l x r) <-> X.eq y x \/ InT y l \/ InT y r. Proof. case rbal'_match; intuition_in. Qed. Instance rbal'_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) : Ok (rbal' l x r). Proof. destruct (rbal'_match l x r); ok. Qed. Hint Rewrite In_node_iff In_leaf_iff makeRed_spec makeBlack_spec lbal_spec rbal_spec rbal'_spec : rb. Ltac descolor := destruct_all Color.t. Ltac destree t := destruct t as [|[|] ? ? ?]. Ltac autorew := autorewrite with rb. Tactic Notation "autorew" "in" ident(H) := autorewrite with rb in H. (** ** Insertion *) Lemma ins_spec : forall s x y, InT y (ins x s) <-> X.eq y x \/ InT y s. Proof. induct s x. - intuition_in. - intuition_in. setoid_replace y with x; eauto. - descolor; autorew; rewrite IHl; intuition_in. - descolor; autorew; rewrite IHr; intuition_in. Qed. Hint Rewrite ins_spec : rb. Instance ins_ok s x `{Ok s} : Ok (ins x s). Proof. induct s x; auto; descolor; (apply lbal_ok || apply rbal_ok || ok); auto; intros y; autorew; intuition; order. Qed. Lemma add_spec' s x y : InT y (add x s) <-> X.eq y x \/ InT y s. Proof. unfold add. now autorew. Qed. Hint Rewrite add_spec' : rb. Lemma add_spec s x y `{Ok s} : InT y (add x s) <-> X.eq y x \/ InT y s. Proof. apply add_spec'. Qed. Instance add_ok s x `{Ok s} : Ok (add x s). Proof. unfold add; auto_tc. Qed. (** ** Balancing for deletion *) Lemma lbalS_spec l x r y : InT y (lbalS l x r) <-> X.eq y x \/ InT y l \/ InT y r. Proof. case lbalS_match. - intros; autorew; intuition_in. - clear l. intros l _. destruct r as [|[|] rl rx rr]. * autorew. intuition_in. * destree rl; autorew; intuition_in. * autorew. intuition_in. Qed. Instance lbalS_ok l x r : forall `(Ok l, Ok r, lt_tree x l, gt_tree x r), Ok (lbalS l x r). Proof. case lbalS_match; intros. - ok. - destruct r as [|[|] rl rx rr]. * ok. * destruct rl as [|[|] rll rlx rlr]; intros; ok. + apply rbal'_ok; ok. intros w; autorew; auto. + intros w; autorew. destruct 1 as [Hw|[Hw|Hw]]; try rewrite Hw; eauto. * ok. autorew. apply rbal'_ok; ok. Qed. Lemma rbalS_spec l x r y : InT y (rbalS l x r) <-> X.eq y x \/ InT y l \/ InT y r. Proof. case rbalS_match. - intros; autorew; intuition_in. - intros t _. destruct l as [|[|] ll lx lr]. * autorew. intuition_in. * destruct lr as [|[|] lrl lrx lrr]; autorew; intuition_in. * autorew. intuition_in. Qed. Instance rbalS_ok l x r : forall `(Ok l, Ok r, lt_tree x l, gt_tree x r), Ok (rbalS l x r). Proof. case rbalS_match; intros. - ok. - destruct l as [|[|] ll lx lr]. * ok. * destruct lr as [|[|] lrl lrx lrr]; intros; ok. + apply lbal_ok; ok. intros w; autorew; auto. + intros w; autorew. destruct 1 as [Hw|[Hw|Hw]]; try rewrite Hw; eauto. * ok. apply lbal_ok; ok. Qed. Hint Rewrite lbalS_spec rbalS_spec : rb. (** ** Append for deletion *) Ltac append_tac l r := induction l as [| lc ll _ lx lr IHlr]; [intro r; simpl |induction r as [| rc rl IHrl rx rr _]; [simpl |destruct lc, rc; [specialize (IHlr rl); clear IHrl |simpl; assert (Hr:notred (Bk rl rx rr)) by (simpl; trivial); set (r:=Bk rl rx rr) in *; clearbody r; clear IHrl rl rx rr; specialize (IHlr r) |change (append _ _) with (Rd (append (Bk ll lx lr) rl) rx rr); assert (Hl:notred (Bk ll lx lr)) by (simpl; trivial); set (l:=Bk ll lx lr) in *; clearbody l; clear IHlr ll lx lr |specialize (IHlr rl); clear IHrl]]]. Fact append_rr_match ll lx lr rl rx rr : rspec (fun a x b => Rd (Rd ll lx a) x (Rd b rx rr)) (fun t => Rd ll lx (Rd t rx rr)) (append lr rl) (append (Rd ll lx lr) (Rd rl rx rr)). Proof. exact (rmatch _ _ _). Qed. Fact append_bb_match ll lx lr rl rx rr : rspec (fun a x b => Rd (Bk ll lx a) x (Bk b rx rr)) (fun t => lbalS ll lx (Bk t rx rr)) (append lr rl) (append (Bk ll lx lr) (Bk rl rx rr)). Proof. exact (rmatch _ _ _). Qed. Lemma append_spec l r x : InT x (append l r) <-> InT x l \/ InT x r. Proof. revert r. append_tac l r; autorew; try tauto. - (* Red / Red *) revert IHlr; case append_rr_match; [intros a y b | intros t Ht]; autorew; tauto. - (* Black / Black *) revert IHlr; case append_bb_match; [intros a y b | intros t Ht]; autorew; tauto. Qed. Hint Rewrite append_spec : rb. Lemma append_ok : forall x l r `{Ok l, Ok r}, lt_tree x l -> gt_tree x r -> Ok (append l r). Proof. append_tac l r. - (* Leaf / _ *) trivial. - (* _ / Leaf *) trivial. - (* Red / Red *) intros; inv. assert (IH : Ok (append lr rl)) by (apply IHlr; eauto). clear IHlr. assert (X.lt lx rx) by (transitivity x; eauto). assert (G : gt_tree lx (append lr rl)). { intros w. autorew. destruct 1; [|transitivity x]; eauto. } assert (L : lt_tree rx (append lr rl)). { intros w. autorew. destruct 1; [transitivity x|]; eauto. } revert IH G L; case append_rr_match; intros; ok. - (* Red / Black *) intros; ok. intros w; autorew; destruct 1; eauto. - (* Black / Red *) intros; ok. intros w; autorew; destruct 1; eauto. - (* Black / Black *) intros; inv. assert (IH : Ok (append lr rl)) by (apply IHlr; eauto). clear IHlr. assert (X.lt lx rx) by (transitivity x; eauto). assert (G : gt_tree lx (append lr rl)). { intros w. autorew. destruct 1; [|transitivity x]; eauto. } assert (L : lt_tree rx (append lr rl)). { intros w. autorew. destruct 1; [transitivity x|]; eauto. } revert IH G L; case append_bb_match; intros; ok. apply lbalS_ok; ok. Qed. (** ** Deletion *) Lemma del_spec : forall s x y `{Ok s}, InT y (del x s) <-> InT y s /\ ~X.eq y x. Proof. induct s x. - intuition_in. - autorew; intuition_in. assert (X.lt y x') by eauto. order. assert (X.lt x' y) by eauto. order. order. - destruct l as [|[|] ll lx lr]; autorew; rewrite ?IHl by trivial; intuition_in; order. - destruct r as [|[|] rl rx rr]; autorew; rewrite ?IHr by trivial; intuition_in; order. Qed. Hint Rewrite del_spec : rb. Instance del_ok s x `{Ok s} : Ok (del x s). Proof. induct s x. - trivial. - eapply append_ok; eauto. - assert (lt_tree x' (del x l)). { intro w. autorew; trivial. destruct 1. eauto. } destruct l as [|[|] ll lx lr]; auto_tc. - assert (gt_tree x' (del x r)). { intro w. autorew; trivial. destruct 1. eauto. } destruct r as [|[|] rl rx rr]; auto_tc. Qed. Lemma remove_spec s x y `{Ok s} : InT y (remove x s) <-> InT y s /\ ~X.eq y x. Proof. unfold remove. now autorew. Qed. Hint Rewrite remove_spec : rb. Instance remove_ok s x `{Ok s} : Ok (remove x s). Proof. unfold remove; auto_tc. Qed. (** ** Removing the minimal element *) Lemma delmin_spec l y r c x s' `{O : Ok (Node c l y r)} : delmin l y r = (x,s') -> min_elt (Node c l y r) = Some x /\ del x (Node c l y r) = s'. Proof. revert y r c x s' O. induction l as [|lc ll IH ly lr _]. - simpl. intros y r _ x s' _. injection 1; intros; subst. now rewrite MX.compare_refl. - intros y r c x s' O. simpl delmin. specialize (IH ly lr). destruct delmin as (x0,s0). destruct (IH lc x0 s0); clear IH; [ok|trivial|]. remember (Node lc ll ly lr) as l. simpl min_elt in *. intros E. replace x0 with x in * by (destruct lc; now injection E). split. * subst l; intuition. * assert (X.lt x y). { inversion_clear O. assert (InT x l) by now apply min_elt_spec1. auto. } simpl. case X.compare_spec; try order. destruct lc; injection E; subst l s0; auto. Qed. Lemma remove_min_spec1 s x s' `{Ok s}: remove_min s = Some (x,s') -> min_elt s = Some x /\ remove x s = s'. Proof. unfold remove_min. destruct s as [|c l y r]; try easy. generalize (delmin_spec l y r c). destruct delmin as (x0,s0). intros D. destruct (D x0 s0) as (->,<-); auto. fold (remove x0 (Node c l y r)). inversion_clear 1; auto. Qed. Lemma remove_min_spec2 s : remove_min s = None -> Empty s. Proof. unfold remove_min. destruct s as [|c l y r]. - easy. - now destruct delmin. Qed. Lemma remove_min_ok (s:t) `{Ok s}: match remove_min s with | Some (_,s') => Ok s' | None => True end. Proof. generalize (remove_min_spec1 s). destruct remove_min as [(x0,s0)|]; auto. intros R. destruct (R x0 s0); auto. subst s0. auto_tc. Qed. (** ** Treeify *) Notation ifpred p n := (if p then pred n else n%nat). Definition treeify_invariant size (f:treeify_t) := forall acc, size <= length acc -> let (t,acc') := f acc in cardinal t = size /\ acc = elements t ++ acc'. Lemma treeify_zero_spec : treeify_invariant 0 treeify_zero. Proof. intro. simpl. auto. Qed. Lemma treeify_one_spec : treeify_invariant 1 treeify_one. Proof. intros [|x acc]; simpl; auto; inversion 1. Qed. Lemma treeify_cont_spec f g size1 size2 size : treeify_invariant size1 f -> treeify_invariant size2 g -> size = S (size1 + size2) -> treeify_invariant size (treeify_cont f g). Proof. intros Hf Hg EQ acc LE. unfold treeify_cont. specialize (Hf acc). destruct (f acc) as (t1,acc1). destruct Hf as (Hf1,Hf2). { transitivity size; trivial. subst. auto with arith. } destruct acc1 as [|x acc1]. { exfalso. revert LE. apply Nat.lt_nge. subst. rewrite app_nil_r, <- elements_cardinal; auto with arith. } specialize (Hg acc1). destruct (g acc1) as (t2,acc2). destruct Hg as (Hg1,Hg2). { revert LE. subst. rewrite app_length, <- elements_cardinal. simpl. rewrite Nat.add_succ_r, <- Nat.succ_le_mono. apply Nat.add_le_mono_l. } rewrite elements_node, app_ass. now subst. Qed. Lemma treeify_aux_spec n (p:bool) : treeify_invariant (ifpred p (Pos.to_nat n)) (treeify_aux p n). Proof. revert p. induction n as [n|n|]; intros p; simpl treeify_aux. - eapply treeify_cont_spec; [ apply (IHn false) | apply (IHn p) | ]. rewrite Pos2Nat.inj_xI. assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H. destruct p; simpl; intros; rewrite Nat.add_0_r; trivial. now rewrite <- Nat.add_succ_r, Nat.succ_pred; trivial. - eapply treeify_cont_spec; [ apply (IHn p) | apply (IHn true) | ]. rewrite Pos2Nat.inj_xO. assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H. rewrite <- Nat.add_succ_r, Nat.succ_pred by trivial. destruct p; simpl; intros; rewrite Nat.add_0_r; trivial. symmetry. now apply Nat.add_pred_l. - destruct p; [ apply treeify_zero_spec | apply treeify_one_spec ]. Qed. Lemma plength_aux_spec l p : Pos.to_nat (plength_aux l p) = length l + Pos.to_nat p. Proof. revert p. induction l; trivial. simpl plength_aux. intros. now rewrite IHl, Pos2Nat.inj_succ, Nat.add_succ_r. Qed. Lemma plength_spec l : Pos.to_nat (plength l) = S (length l). Proof. unfold plength. rewrite plength_aux_spec. apply Nat.add_1_r. Qed. Lemma treeify_elements l : elements (treeify l) = l. Proof. assert (H := treeify_aux_spec (plength l) true l). unfold treeify. destruct treeify_aux as (t,acc); simpl in *. destruct H as (H,H'). { now rewrite plength_spec. } subst l. rewrite plength_spec, app_length, <- elements_cardinal in *. destruct acc. * now rewrite app_nil_r. * exfalso. revert H. simpl. rewrite Nat.add_succ_r, Nat.add_comm. apply Nat.succ_add_discr. Qed. Lemma treeify_spec x l : InT x (treeify l) <-> InA X.eq x l. Proof. intros. now rewrite <- elements_spec1, treeify_elements. Qed. Lemma treeify_ok l : sort X.lt l -> Ok (treeify l). Proof. intros. apply elements_sort_ok. rewrite treeify_elements; auto. Qed. (** ** Filter *) #[deprecated(since="8.11",note="Lemma filter_app has been moved to module List.")] Notation filter_app := List.filter_app. Lemma filter_aux_elements s f acc : filter_aux f s acc = List.filter f (elements s) ++ acc. Proof. revert acc. induction s as [|c l IHl x r IHr]; trivial. intros acc. rewrite elements_node, List.filter_app. simpl. destruct (f x); now rewrite IHl, IHr, app_ass. Qed. Lemma filter_elements s f : elements (filter f s) = List.filter f (elements s). Proof. unfold filter. now rewrite treeify_elements, filter_aux_elements, app_nil_r. Qed. Lemma filter_spec s x f : Proper (X.eq==>Logic.eq) f -> (InT x (filter f s) <-> InT x s /\ f x = true). Proof. intros Hf. rewrite <- elements_spec1, filter_elements, filter_InA, elements_spec1; now auto_tc. Qed. Instance filter_ok s f `(Ok s) : Ok (filter f s). Proof. apply elements_sort_ok. rewrite filter_elements. apply filter_sort with X.eq; auto_tc. Qed. (** ** Partition *) Lemma partition_aux_spec s f acc1 acc2 : partition_aux f s acc1 acc2 = (filter_aux f s acc1, filter_aux (fun x => negb (f x)) s acc2). Proof. revert acc1 acc2. induction s as [ | c l Hl x r Hr ]; simpl. - trivial. - intros acc1 acc2. destruct (f x); simpl; now rewrite Hr, Hl. Qed. Lemma partition_spec s f : partition f s = (filter f s, filter (fun x => negb (f x)) s). Proof. unfold partition, filter. now rewrite partition_aux_spec. Qed. Lemma partition_spec1 s f : Proper (X.eq==>Logic.eq) f -> Equal (fst (partition f s)) (filter f s). Proof. now rewrite partition_spec. Qed. Lemma partition_spec2 s f : Proper (X.eq==>Logic.eq) f -> Equal (snd (partition f s)) (filter (fun x => negb (f x)) s). Proof. now rewrite partition_spec. Qed. Instance partition_ok1 s f `(Ok s) : Ok (fst (partition f s)). Proof. rewrite partition_spec; now apply filter_ok. Qed. Instance partition_ok2 s f `(Ok s) : Ok (snd (partition f s)). Proof. rewrite partition_spec; now apply filter_ok. Qed. (** ** An invariant for binary list functions with accumulator. *) Ltac inA := rewrite ?InA_app_iff, ?InA_cons, ?InA_nil, ?InA_rev in *; auto_tc. Record INV l1 l2 acc : Prop := { l1_sorted : sort X.lt (rev l1); l2_sorted : sort X.lt (rev l2); acc_sorted : sort X.lt acc; l1_lt_acc x y : InA X.eq x l1 -> InA X.eq y acc -> X.lt x y; l2_lt_acc x y : InA X.eq x l2 -> InA X.eq y acc -> X.lt x y}. Local Hint Resolve l1_sorted l2_sorted acc_sorted : core. Lemma INV_init s1 s2 `(Ok s1, Ok s2) : INV (rev_elements s1) (rev_elements s2) nil. Proof. rewrite !rev_elements_rev. split; rewrite ?rev_involutive; auto; intros; now inA. Qed. Lemma INV_sym l1 l2 acc : INV l1 l2 acc -> INV l2 l1 acc. Proof. destruct 1; now split. Qed. Lemma INV_drop x1 l1 l2 acc : INV (x1 :: l1) l2 acc -> INV l1 l2 acc. Proof. intros (l1s,l2s,accs,l1a,l2a). simpl in *. destruct (sorted_app_inv _ _ l1s) as (U & V & W); auto. split; auto. Qed. Lemma INV_eq x1 x2 l1 l2 acc : INV (x1 :: l1) (x2 :: l2) acc -> X.eq x1 x2 -> INV l1 l2 (x1 :: acc). Proof. intros (U,V,W,X,Y) EQ. simpl in *. destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto. destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto. split; auto. - constructor; auto. apply InA_InfA with X.eq; auto_tc. - intros x y; inA; intros Hx [Hy|Hy]. + apply U3; inA. + apply X; inA. - intros x y; inA; intros Hx [Hy|Hy]. + rewrite Hy, EQ; apply V3; inA. + apply Y; inA. Qed. Lemma INV_lt x1 x2 l1 l2 acc : INV (x1 :: l1) (x2 :: l2) acc -> X.lt x1 x2 -> INV (x1 :: l1) l2 (x2 :: acc). Proof. intros (U,V,W,X,Y) EQ. simpl in *. destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto. destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto. split; auto. - constructor; auto. apply InA_InfA with X.eq; auto_tc. - intros x y; inA; intros Hx [Hy|Hy]. + rewrite Hy; clear Hy. destruct Hx; [order|]. transitivity x1; auto. apply U3; inA. + apply X; inA. - intros x y; inA; intros Hx [Hy|Hy]. + rewrite Hy. apply V3; inA. + apply Y; inA. Qed. Lemma INV_rev l1 l2 acc : INV l1 l2 acc -> Sorted X.lt (rev_append l1 acc). Proof. intros. rewrite rev_append_rev. apply SortA_app with X.eq; eauto with *. intros x y. inA. eapply @l1_lt_acc; eauto. Qed. (** ** union *) Lemma union_list_ok l1 l2 acc : INV l1 l2 acc -> sort X.lt (union_list l1 l2 acc). Proof. revert l2 acc. induction l1 as [|x1 l1 IH1]; [intro l2|induction l2 as [|x2 l2 IH2]]; intros acc inv. - eapply INV_rev, INV_sym; eauto. - eapply INV_rev; eauto. - simpl. case X.compare_spec; intro C. * apply IH1. eapply INV_eq; eauto. * apply (IH2 (x2::acc)). eapply INV_lt; eauto. * apply IH1. eapply INV_sym, INV_lt; eauto. now apply INV_sym. Qed. Instance linear_union_ok s1 s2 `(Ok s1, Ok s2) : Ok (linear_union s1 s2). Proof. unfold linear_union. now apply treeify_ok, union_list_ok, INV_init. Qed. Instance fold_add_ok s1 s2 `(Ok s1, Ok s2) : Ok (fold add s1 s2). Proof. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *. induction (rev (elements s1)); simpl; unfold flip in *; auto_tc. Qed. Instance union_ok s1 s2 `(Ok s1, Ok s2) : Ok (union s1 s2). Proof. unfold union. destruct compare_height; auto_tc. Qed. Lemma union_list_spec x l1 l2 acc : InA X.eq x (union_list l1 l2 acc) <-> InA X.eq x l1 \/ InA X.eq x l2 \/ InA X.eq x acc. Proof. revert l2 acc. induction l1 as [|x1 l1 IH1]. - intros l2 acc; simpl. rewrite rev_append_rev. inA. tauto. - induction l2 as [|x2 l2 IH2]; intros acc; simpl. * rewrite rev_append_rev. inA. tauto. * case X.compare_spec; intro C. + rewrite IH1, !InA_cons, C; tauto. + rewrite (IH2 (x2::acc)), !InA_cons. tauto. + rewrite IH1, !InA_cons; tauto. Qed. Lemma linear_union_spec s1 s2 x : InT x (linear_union s1 s2) <-> InT x s1 \/ InT x s2. Proof. unfold linear_union. rewrite treeify_spec, union_list_spec, !rev_elements_rev. rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc. tauto. Qed. Lemma fold_add_spec s1 s2 x : InT x (fold add s1 s2) <-> InT x s1 \/ InT x s2. Proof. rewrite fold_spec, <- fold_left_rev_right. rewrite <- (elements_spec1 s1), <- InA_rev by auto_tc. unfold elt in *. induction (rev (elements s1)); simpl. - rewrite InA_nil. tauto. - unfold flip. rewrite add_spec', IHl, InA_cons. tauto. Qed. Lemma union_spec' s1 s2 x : InT x (union s1 s2) <-> InT x s1 \/ InT x s2. Proof. unfold union. destruct compare_height. - apply linear_union_spec. - apply fold_add_spec. - rewrite fold_add_spec. tauto. Qed. Lemma union_spec : forall s1 s2 y `{Ok s1, Ok s2}, (InT y (union s1 s2) <-> InT y s1 \/ InT y s2). Proof. intros; apply union_spec'. Qed. (** ** inter *) Lemma inter_list_ok l1 l2 acc : INV l1 l2 acc -> sort X.lt (inter_list l1 l2 acc). Proof. revert l2 acc. induction l1 as [|x1 l1 IH1]; [|induction l2 as [|x2 l2 IH2]]; simpl. - eauto. - eauto. - intros acc inv. case X.compare_spec; intro C. * apply IH1. eapply INV_eq; eauto. * apply (IH2 acc). eapply INV_sym, INV_drop, INV_sym; eauto. * apply IH1. eapply INV_drop; eauto. Qed. Instance linear_inter_ok s1 s2 `(Ok s1, Ok s2) : Ok (linear_inter s1 s2). Proof. unfold linear_inter. now apply treeify_ok, inter_list_ok, INV_init. Qed. Instance inter_ok s1 s2 `(Ok s1, Ok s2) : Ok (inter s1 s2). Proof. unfold inter. destruct compare_height; auto_tc. Qed. Lemma inter_list_spec x l1 l2 acc : sort X.lt (rev l1) -> sort X.lt (rev l2) -> (InA X.eq x (inter_list l1 l2 acc) <-> (InA X.eq x l1 /\ InA X.eq x l2) \/ InA X.eq x acc). Proof. revert l2 acc. induction l1 as [|x1 l1 IH1]. - intros l2 acc; simpl. inA. tauto. - induction l2 as [|x2 l2 IH2]; intros acc. * simpl. inA. tauto. * simpl. intros U V. destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto. destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto. case X.compare_spec; intro C. + rewrite IH1, !InA_cons, C; tauto. + rewrite (IH2 acc); auto. inA. intuition; try order. assert (X.lt x x1) by (apply U3; inA). order. + rewrite IH1; auto. inA. intuition; try order. assert (X.lt x x2) by (apply V3; inA). order. Qed. Lemma linear_inter_spec s1 s2 x `(Ok s1, Ok s2) : InT x (linear_inter s1 s2) <-> InT x s1 /\ InT x s2. Proof. unfold linear_inter. rewrite !rev_elements_rev, treeify_spec, inter_list_spec by (rewrite rev_involutive; auto_tc). rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc. tauto. Qed. Local Instance mem_proper s `(Ok s) : Proper (X.eq ==> Logic.eq) (fun k => mem k s). Proof. intros x y EQ. apply Bool.eq_iff_eq_true; rewrite !mem_spec; auto. now rewrite EQ. Qed. Lemma inter_spec s1 s2 y `{Ok s1, Ok s2} : InT y (inter s1 s2) <-> InT y s1 /\ InT y s2. Proof. unfold inter. destruct compare_height. - now apply linear_inter_spec. - rewrite filter_spec, mem_spec by auto_tc; tauto. - rewrite filter_spec, mem_spec by auto_tc; tauto. Qed. (** ** difference *) Lemma diff_list_ok l1 l2 acc : INV l1 l2 acc -> sort X.lt (diff_list l1 l2 acc). Proof. revert l2 acc. induction l1 as [|x1 l1 IH1]; [intro l2|induction l2 as [|x2 l2 IH2]]; intros acc inv. - eauto. - unfold diff_list. eapply INV_rev; eauto. - simpl. case X.compare_spec; intro C. * apply IH1. eapply INV_drop, INV_sym, INV_drop, INV_sym; eauto. * apply (IH2 acc). eapply INV_sym, INV_drop, INV_sym; eauto. * apply IH1. eapply INV_sym, INV_lt; eauto. now apply INV_sym. Qed. Instance diff_inter_ok s1 s2 `(Ok s1, Ok s2) : Ok (linear_diff s1 s2). Proof. unfold linear_inter. now apply treeify_ok, diff_list_ok, INV_init. Qed. Instance fold_remove_ok s1 s2 `(Ok s2) : Ok (fold remove s1 s2). Proof. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *. induction (rev (elements s1)); simpl; unfold flip in *; auto_tc. Qed. Instance diff_ok s1 s2 `(Ok s1, Ok s2) : Ok (diff s1 s2). Proof. unfold diff. destruct compare_height; auto_tc. Qed. Lemma diff_list_spec x l1 l2 acc : sort X.lt (rev l1) -> sort X.lt (rev l2) -> (InA X.eq x (diff_list l1 l2 acc) <-> (InA X.eq x l1 /\ ~InA X.eq x l2) \/ InA X.eq x acc). Proof. revert l2 acc. induction l1 as [|x1 l1 IH1]. - intros l2 acc; simpl. inA. tauto. - induction l2 as [|x2 l2 IH2]; intros acc. * intros; simpl. rewrite rev_append_rev. inA. tauto. * simpl. intros U V. destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto. destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto. case X.compare_spec; intro C. + rewrite IH1; auto. f_equiv. inA. intuition; try order. assert (X.lt x x1) by (apply U3; inA). order. + rewrite (IH2 acc); auto. f_equiv. inA. intuition; try order. assert (X.lt x x1) by (apply U3; inA). order. + rewrite IH1; auto. inA. intuition; try order. left; split; auto. destruct 1. order. assert (X.lt x x2) by (apply V3; inA). order. Qed. Lemma linear_diff_spec s1 s2 x `(Ok s1, Ok s2) : InT x (linear_diff s1 s2) <-> InT x s1 /\ ~InT x s2. Proof. unfold linear_diff. rewrite !rev_elements_rev, treeify_spec, diff_list_spec by (rewrite rev_involutive; auto_tc). rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc. tauto. Qed. Lemma fold_remove_spec s1 s2 x `(Ok s2) : InT x (fold remove s1 s2) <-> InT x s2 /\ ~InT x s1. Proof. rewrite fold_spec, <- fold_left_rev_right. rewrite <- (elements_spec1 s1), <- InA_rev by auto_tc. unfold elt in *. induction (rev (elements s1)); simpl; intros. - rewrite InA_nil. intuition. - unfold flip in *. rewrite remove_spec, IHl, InA_cons. tauto. clear IHl. induction l; simpl; auto_tc. Qed. Lemma diff_spec s1 s2 y `{Ok s1, Ok s2} : InT y (diff s1 s2) <-> InT y s1 /\ ~InT y s2. Proof. unfold diff. destruct compare_height. - now apply linear_diff_spec. - rewrite filter_spec, Bool.negb_true_iff, <- Bool.not_true_iff_false, mem_spec; intuition. intros x1 x2 EQ. f_equal. now apply mem_proper. - now apply fold_remove_spec. Qed. End MakeRaw. (** * Balancing properties We now prove that all operations preserve a red-black invariant, and that trees have hence a logarithmic depth. *) Module BalanceProps(X:Orders.OrderedType)(Import M : MakeRaw X). Local Notation Rd := (Node Red). Local Notation Bk := (Node Black). Import M.MX. (** ** Red-Black invariants *) (** In a red-black tree : - a red node has no red children - the black depth at each node is the same along all paths. The black depth is here an argument of the predicate. *) Inductive rbt : nat -> tree -> Prop := | RB_Leaf : rbt 0 Leaf | RB_Rd n l k r : notred l -> notred r -> rbt n l -> rbt n r -> rbt n (Rd l k r) | RB_Bk n l k r : rbt n l -> rbt n r -> rbt (S n) (Bk l k r). (** A red-red tree is almost a red-black tree, except that it has a _red_ root node which _may_ have red children. Note that a red-red tree is hence non-empty, and all its strict subtrees are red-black. *) Inductive rrt (n:nat) : tree -> Prop := | RR_Rd l k r : rbt n l -> rbt n r -> rrt n (Rd l k r). (** An almost-red-black tree is almost a red-black tree, except that it's permitted to have two red nodes in a row at the very root (only). We implement this notion by saying that a quasi-red-black tree is either a red-black tree or a red-red tree. *) Inductive arbt (n:nat)(t:tree) : Prop := | ARB_RB : rbt n t -> arbt n t | ARB_RR : rrt n t -> arbt n t. (** The main exported invariant : being a red-black tree for some black depth. *) Class Rbt (t:tree) := RBT : exists d, rbt d t. (** ** Basic tactics and results about red-black *) Scheme rbt_ind := Induction for rbt Sort Prop. Local Hint Constructors rbt rrt arbt : core. Local Hint Extern 0 (notred _) => (exact I) : core. Ltac invrb := intros; invtree rrt; invtree rbt; try contradiction. Ltac desarb := match goal with H:arbt _ _ |- _ => destruct H end. Ltac nonzero n := destruct n as [|n]; [try split; invrb|]. Lemma rr_nrr_rb n t : rrt n t -> notredred t -> rbt n t. Proof. destruct 1 as [l x r Hl Hr]. destruct l, r; descolor; invrb; auto. Qed. Local Hint Resolve rr_nrr_rb : core. Lemma arb_nrr_rb n t : arbt n t -> notredred t -> rbt n t. Proof. destruct 1; auto. Qed. Lemma arb_nr_rb n t : arbt n t -> notred t -> rbt n t. Proof. destruct 1; destruct t; descolor; invrb; auto. Qed. Local Hint Resolve arb_nrr_rb arb_nr_rb : core. (** ** A Red-Black tree has indeed a logarithmic depth *) Definition redcarac s := rcase (fun _ _ _ => 1) (fun _ => 0) s. Lemma rb_maxdepth s n : rbt n s -> maxdepth s <= 2*n + redcarac s. Proof. induction 1. - simpl; auto. - replace (redcarac l) with 0 in * by now destree l. replace (redcarac r) with 0 in * by now destree r. simpl maxdepth. simpl redcarac. rewrite Nat.add_succ_r, <- Nat.succ_le_mono. now apply Nat.max_lub. - simpl. rewrite <- Nat.succ_le_mono. apply Nat.max_lub; eapply Nat.le_trans; eauto; [destree l | destree r]; simpl; rewrite !Nat.add_0_r, ?Nat.add_1_r; auto with arith. Qed. Lemma rb_mindepth s n : rbt n s -> n + redcarac s <= mindepth s. Proof. induction 1; simpl. - trivial. - rewrite Nat.add_succ_r. apply -> Nat.succ_le_mono. replace (redcarac l) with 0 in * by now destree l. replace (redcarac r) with 0 in * by now destree r. now apply Nat.min_glb. - apply -> Nat.succ_le_mono. rewrite Nat.add_0_r. apply Nat.min_glb; eauto with arith. Qed. Lemma maxdepth_upperbound s : Rbt s -> maxdepth s <= 2 * Nat.log2 (S (cardinal s)). Proof. intros (n,H). eapply Nat.le_trans; [eapply rb_maxdepth; eauto|]. transitivity (2*(n+redcarac s)). - rewrite Nat.mul_add_distr_l. apply Nat.add_le_mono_l. rewrite <- Nat.mul_1_l at 1. apply Nat.mul_le_mono_r. auto with arith. - apply Nat.mul_le_mono_l. transitivity (mindepth s). + now apply rb_mindepth. + apply mindepth_log_cardinal. Qed. Lemma maxdepth_lowerbound s : s<>Leaf -> Nat.log2 (cardinal s) < maxdepth s. Proof. apply maxdepth_log_cardinal. Qed. (** ** Singleton *) Lemma singleton_rb x : Rbt (singleton x). Proof. unfold singleton. exists 1; auto. Qed. (** ** [makeBlack] and [makeRed] *) Lemma makeBlack_rb n t : arbt n t -> Rbt (makeBlack t). Proof. destruct t as [|[|] l x r]. - exists 0; auto. - destruct 1; invrb; exists (S n); simpl; auto. - exists n; auto. Qed. Lemma makeRed_rr t n : rbt (S n) t -> notred t -> rrt n (makeRed t). Proof. destruct t as [|[|] l x r]; invrb; simpl; auto. Qed. (** ** Balancing *) Lemma lbal_rb n l k r : arbt n l -> rbt n r -> rbt (S n) (lbal l k r). Proof. case lbal_match; intros; desarb; invrb; auto. Qed. Lemma rbal_rb n l k r : rbt n l -> arbt n r -> rbt (S n) (rbal l k r). Proof. case rbal_match; intros; desarb; invrb; auto. Qed. Lemma rbal'_rb n l k r : rbt n l -> arbt n r -> rbt (S n) (rbal' l k r). Proof. case rbal'_match; intros; desarb; invrb; auto. Qed. Lemma lbalS_rb n l x r : arbt n l -> rbt (S n) r -> notred r -> rbt (S n) (lbalS l x r). Proof. intros Hl Hr Hr'. destruct r as [|[|] rl rx rr]; invrb. clear Hr'. revert Hl. case lbalS_match. - destruct 1; invrb; auto. - intros. apply rbal'_rb; auto. Qed. Lemma lbalS_arb n l x r : arbt n l -> rbt (S n) r -> arbt (S n) (lbalS l x r). Proof. case lbalS_match. - destruct 1; invrb; auto. - clear l. intros l Hl Hl' Hr. destruct r as [|[|] rl rx rr]; invrb. * destruct rl as [|[|] rll rlx rlr]; invrb. right; auto using rbal'_rb, makeRed_rr. * left; apply rbal'_rb; auto. Qed. Lemma rbalS_rb n l x r : rbt (S n) l -> notred l -> arbt n r -> rbt (S n) (rbalS l x r). Proof. intros Hl Hl' Hr. destruct l as [|[|] ll lx lr]; invrb. clear Hl'. revert Hr. case rbalS_match. - destruct 1; invrb; auto. - intros. apply lbal_rb; auto. Qed. Lemma rbalS_arb n l x r : rbt (S n) l -> arbt n r -> arbt (S n) (rbalS l x r). Proof. case rbalS_match. - destruct 2; invrb; auto. - clear r. intros r Hr Hr' Hl. destruct l as [|[|] ll lx lr]; invrb. * destruct lr as [|[|] lrl lrx lrr]; invrb. right; auto using lbal_rb, makeRed_rr. * left; apply lbal_rb; auto. Qed. (** ** Insertion *) (** The next lemmas combine simultaneous results about rbt and arbt. A first solution here: statement with [if ... then ... else] *) Definition ifred s (A B:Prop) := rcase (fun _ _ _ => A) (fun _ => B) s. Lemma ifred_notred s A B : notred s -> (ifred s A B <-> B). Proof. destruct s; descolor; simpl; intuition. Qed. Lemma ifred_or s A B : ifred s A B -> A\/B. Proof. destruct s; descolor; simpl; intuition. Qed. Lemma ins_rr_rb x s n : rbt n s -> ifred s (rrt n (ins x s)) (rbt n (ins x s)). Proof. induction 1 as [ | n l k r | n l k r Hl IHl Hr IHr ]. - simpl; auto. - simpl. rewrite ifred_notred in * by trivial. elim_compare x k; auto. - rewrite ifred_notred by trivial. unfold ins; fold ins. (* simpl is too much here ... *) elim_compare x k. * auto. * apply lbal_rb; trivial. apply ifred_or in IHl; intuition. * apply rbal_rb; trivial. apply ifred_or in IHr; intuition. Qed. Lemma ins_arb x s n : rbt n s -> arbt n (ins x s). Proof. intros H. apply (ins_rr_rb x), ifred_or in H. intuition. Qed. Instance add_rb x s : Rbt s -> Rbt (add x s). Proof. intros (n,H). unfold add. now apply (makeBlack_rb n), ins_arb. Qed. (** ** Deletion *) (** A second approach here: statement with ... /\ ... *) Lemma append_arb_rb n l r : rbt n l -> rbt n r -> (arbt n (append l r)) /\ (notred l -> notred r -> rbt n (append l r)). Proof. revert r n. append_tac l r. - split; auto. - split; auto. - (* Red / Red *) intros n. invrb. case (IHlr n); auto; clear IHlr. case append_rr_match. + intros a x b _ H; split; invrb. assert (rbt n (Rd a x b)) by auto. invrb. auto. + split; invrb; auto. - (* Red / Black *) split; invrb. destruct (IHlr n) as (_,IH); auto. - (* Black / Red *) split; invrb. destruct (IHrl n) as (_,IH); auto. - (* Black / Black *) nonzero n. invrb. destruct (IHlr n) as (IH,_); auto; clear IHlr. revert IH. case append_bb_match. + intros a x b IH; split; destruct IH; invrb; auto. + split; [left | invrb]; auto using lbalS_rb. Qed. (** A third approach : Lemma ... with ... *) Lemma del_arb s x n : rbt (S n) s -> isblack s -> arbt n (del x s) with del_rb s x n : rbt n s -> notblack s -> rbt n (del x s). Proof. { revert n. induct s x; try destruct c; try contradiction; invrb. - apply append_arb_rb; assumption. - assert (IHl' := del_rb l x). clear IHr del_arb del_rb. destruct l as [|[|] ll lx lr]; auto. nonzero n. apply lbalS_arb; auto. - assert (IHr' := del_rb r x). clear IHl del_arb del_rb. destruct r as [|[|] rl rx rr]; auto. nonzero n. apply rbalS_arb; auto. } { revert n. induct s x; try assumption; try destruct c; try contradiction; invrb. - apply append_arb_rb; assumption. - assert (IHl' := del_arb l x). clear IHr del_arb del_rb. destruct l as [|[|] ll lx lr]; auto. nonzero n. destruct n as [|n]; [invrb|]; apply lbalS_rb; auto. - assert (IHr' := del_arb r x). clear IHl del_arb del_rb. destruct r as [|[|] rl rx rr]; auto. nonzero n. apply rbalS_rb; auto. } Qed. Instance remove_rb s x : Rbt s -> Rbt (remove x s). Proof. intros (n,H). unfold remove. destruct s as [|[|] l y r]. - apply (makeBlack_rb n). auto. - apply (makeBlack_rb n). left. apply del_rb; simpl; auto. - nonzero n. apply (makeBlack_rb n). apply del_arb; simpl; auto. Qed. (** ** Treeify *) Definition treeify_rb_invariant size depth (f:treeify_t) := forall acc, size <= length acc -> rbt depth (fst (f acc)) /\ size + length (snd (f acc)) = length acc. Lemma treeify_zero_rb : treeify_rb_invariant 0 0 treeify_zero. Proof. intros acc _; simpl; auto. Qed. Lemma treeify_one_rb : treeify_rb_invariant 1 0 treeify_one. Proof. intros [|x acc]; simpl; auto; inversion 1. Qed. Lemma treeify_cont_rb f g size1 size2 size d : treeify_rb_invariant size1 d f -> treeify_rb_invariant size2 d g -> size = S (size1 + size2) -> treeify_rb_invariant size (S d) (treeify_cont f g). Proof. intros Hf Hg H acc Hacc. unfold treeify_cont. specialize (Hf acc). destruct (f acc) as (l, acc1). simpl in *. destruct Hf as (Hf1, Hf2). { subst. eauto with arith. } destruct acc1 as [|x acc2]; simpl in *. - exfalso. revert Hacc. apply Nat.lt_nge. rewrite H, <- Hf2. auto with arith. - specialize (Hg acc2). destruct (g acc2) as (r, acc3). simpl in *. destruct Hg as (Hg1, Hg2). { revert Hacc. rewrite H, <- Hf2, Nat.add_succ_r, <- Nat.succ_le_mono. apply Nat.add_le_mono_l. } split; auto. now rewrite H, <- Hf2, <- Hg2, Nat.add_succ_r, Nat.add_assoc. Qed. Lemma treeify_aux_rb n : exists d, forall (b:bool), treeify_rb_invariant (ifpred b (Pos.to_nat n)) d (treeify_aux b n). Proof. induction n as [n (d,IHn)|n (d,IHn)| ]. - exists (S d). intros b. eapply treeify_cont_rb; [ apply (IHn false) | apply (IHn b) | ]. rewrite Pos2Nat.inj_xI. assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H. destruct b; simpl; intros; rewrite Nat.add_0_r; trivial. now rewrite <- Nat.add_succ_r, Nat.succ_pred; trivial. - exists (S d). intros b. eapply treeify_cont_rb; [ apply (IHn b) | apply (IHn true) | ]. rewrite Pos2Nat.inj_xO. assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H. rewrite <- Nat.add_succ_r, Nat.succ_pred by trivial. destruct b; simpl; intros; rewrite Nat.add_0_r; trivial. symmetry. now apply Nat.add_pred_l. - exists 0; destruct b; [ apply treeify_zero_rb | apply treeify_one_rb ]. Qed. (** The black depth of [treeify l] is actually a log2, but we don't need to mention that. *) Instance treeify_rb l : Rbt (treeify l). Proof. unfold treeify. destruct (treeify_aux_rb (plength l)) as (d,H). exists d. apply H. now rewrite plength_spec. Qed. (** ** Filtering *) Instance filter_rb f s : Rbt (filter f s). Proof. unfold filter; auto_tc. Qed. Instance partition_rb1 f s : Rbt (fst (partition f s)). Proof. unfold partition. destruct partition_aux. simpl. auto_tc. Qed. Instance partition_rb2 f s : Rbt (snd (partition f s)). Proof. unfold partition. destruct partition_aux. simpl. auto_tc. Qed. (** ** Union, intersection, difference *) Instance fold_add_rb s1 s2 : Rbt s2 -> Rbt (fold add s1 s2). Proof. intros. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *. induction (rev (elements s1)); simpl; unfold flip in *; auto_tc. Qed. Instance fold_remove_rb s1 s2 : Rbt s2 -> Rbt (fold remove s1 s2). Proof. intros. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *. induction (rev (elements s1)); simpl; unfold flip in *; auto_tc. Qed. Lemma union_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (union s1 s2). Proof. intros. unfold union, linear_union. destruct compare_height; auto_tc. Qed. Lemma inter_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (inter s1 s2). Proof. intros. unfold inter, linear_inter. destruct compare_height; auto_tc. Qed. Lemma diff_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (diff s1 s2). Proof. intros. unfold diff, linear_diff. destruct compare_height; auto_tc. Qed. End BalanceProps. (** * Final Encapsulation Now, in order to really provide a functor implementing [S], we need to encapsulate everything into a type of binary search trees. They also happen to be well-balanced, but this has no influence on the correctness of operations, so we won't state this here, see [BalanceProps] if you need more than just the MSet interface. *) Module Type MSetInterface_S_Ext := MSetInterface.S <+ MSetRemoveMin. Module Make (X: Orders.OrderedType) <: MSetInterface_S_Ext with Module E := X. Module Raw. Include MakeRaw X. End Raw. Include MSetInterface.Raw2Sets X Raw. Definition opt_ok (x:option (elt * Raw.t)) := match x with Some (_,s) => Raw.Ok s | None => True end. Definition mk_opt_t (x: option (elt * Raw.t))(P: opt_ok x) : option (elt * t) := match x as o return opt_ok o -> option (elt * t) with | Some (k,s') => fun P : Raw.Ok s' => Some (k, Mkt s') | None => fun _ => None end P. Definition remove_min s : option (elt * t) := mk_opt_t (Raw.remove_min (this s)) (Raw.remove_min_ok s). Lemma remove_min_spec1 s x s' : remove_min s = Some (x,s') -> min_elt s = Some x /\ Equal (remove x s) s'. Proof. destruct s as (s,Hs). unfold remove_min, mk_opt_t, min_elt, remove, Equal, In; simpl. generalize (fun x s' => @Raw.remove_min_spec1 s x s' Hs). set (P := Raw.remove_min_ok s). clearbody P. destruct (Raw.remove_min s) as [(x0,s0)|]; try easy. intros H [= -> <-]. simpl. destruct (H x s0); auto. subst; intuition. Qed. Lemma remove_min_spec2 s : remove_min s = None -> Empty s. Proof. destruct s as (s,Hs). unfold remove_min, mk_opt_t, Empty, In; simpl. generalize (Raw.remove_min_spec2 s). set (P := Raw.remove_min_ok s). clearbody P. destruct (Raw.remove_min s) as [(x0,s0)|]; now intuition. Qed. End Make.

//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: P.20131013 // \ \ Application: netgen // / / Filename: barrel_shifter_synthesis.v // /___/ /\ Timestamp: Sun May 03 00:34:43 2015 // \ \ / \ // \___\/\___\ // // Command : -intstyle ise -tm barrel_shifter_synthesis -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim barrel_shifter.ngc barrel_shifter_synthesis.v // Device : xc6slx16-2-csg324 // Input file : barrel_shifter.ngc // Output file : D:\Projects\Xilinx\Shifter\netgen\synthesis\barrel_shifter_synthesis.v // # of Modules : 1 // Design Name : barrel_shifter // Xilinx : D:\Xilinx\14.7\ISE_DS\ISE\ // // Purpose: // This verilog netlist is a verification model and uses simulation // primitives which may not represent the true implementation of the // device, however the netlist is functionally correct and should not // be modified. This file cannot be synthesized and should only be used // with supported simulation tools. // // Reference: // Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 // //////////////////////////////////////////////////////////////////////////////// `timescale 1 ns/1 ps module barrel_shifter_synthesis ( rotate, sra, ain, bin, yout ); input rotate; input sra; input [15 : 0] ain; input [4 : 0] bin; output [15 : 0] yout; wire ain_0_IBUF_0; wire ain_14_IBUF_1; wire ain_1_IBUF_2; wire ain_13_IBUF_3; wire ain_2_IBUF_4; wire ain_12_IBUF_5; wire ain_3_IBUF_6; wire ain_11_IBUF_7; wire ain_4_IBUF_8; wire ain_10_IBUF_9; wire ain_5_IBUF_10; wire ain_9_IBUF_11; wire ain_6_IBUF_12; wire ain_8_IBUF_13; wire ain_7_IBUF_14; wire ain_15_IBUF_15; wire bin_4_IBUF_16; wire bin_3_IBUF_17; wire bin_2_IBUF_18; wire bin_1_IBUF_19; wire bin_0_IBUF_20; wire rotate_IBUF_21; wire sra_IBUF_22; wire yout_15_OBUF_25; wire yout_14_OBUF_26; wire yout_13_OBUF_27; wire yout_12_OBUF_28; wire yout_11_OBUF_29; wire yout_10_OBUF_30; wire yout_9_OBUF_31; wire yout_8_OBUF_32; wire yout_7_OBUF_33; wire yout_6_OBUF_34; wire yout_5_OBUF_35; wire yout_4_OBUF_36; wire yout_3_OBUF_37; wire yout_2_OBUF_38; wire yout_1_OBUF_39; wire yout_0_OBUF_40; wire \b<3>_mmx_out29 ; wire \b<3>_mmx_out27 ; wire \b<3>_mmx_out25 ; wire \b<3>_mmx_out24 ; wire \b<3>_mmx_out23 ; wire \b<3>_mmx_out22 ; wire \b<2>_mmx_out15 ; wire \b<3>_mmx_out14 ; wire \b<2>_mmx_out14 ; wire \b<2>_mmx_out13 ; wire \b<3>_mmx_out12 ; wire \b<2>_mmx_out12 ; wire \b<3>_mmx_out11 ; wire \b<2>_mmx_out11 ; wire \b<2>_mmx_out10 ; wire \b<2>_mmx_out9 ; wire \b<3>_mmx_out7 ; wire \b<2>_mmx_out8 ; wire \b<3>_mmx_out5 ; wire \b<3>_mmx_out3 ; wire \b<2>_mmx_out ; wire \b<2>111 ; wire Mmux_yout201; wire Mmux_yout141; wire Mmux_yout121; wire Mmux_yout111_66; wire Mmux_yout61; wire Mmux_yout122_68; wire Mmux_yout191_69; wire Mmux_yout71; wire Mmux_yout1221; wire Mmux_yout51; wire Mmux_yout1811; wire Mmux_yout1411; wire Mmux_yout1311; wire Mmux_yout1711; wire Mmux_yout1222; wire Mmux_yout52; wire Mmux_yout1511; wire Mmux_yout1611_80; wire Mmux_yout114_81; wire \b<2>151 ; wire Mmux_yout1112; wire Mmux_yout1224; wire Mmux_yout911; wire Mmux_yout14111_86; wire Mmux_yout14112_87; wire Mmux_yout13111_88; wire Mmux_yout13112_89; wire Mmux_yout15111_90; wire Mmux_yout15112_91; wire Mmux_yout3; wire Mmux_yout31_93; wire Mmux_yout32_94; wire N2; wire Mmux_yout1141_96; wire Mmux_yout1211_97; wire Mmux_yout1212_98; wire Mmux_yout1213_99; wire \b<2>2 ; wire Mmux_yout17111_101; wire Mmux_yout17112_102; wire N4; wire Mmux_yout18111_104; wire Mmux_yout18112_105; wire N6; wire Mmux_yout11; wire Mmux_yout112_108; wire Mmux_yout113_109; wire N8; wire N10; wire N12; wire N14; wire N15; wire N16; wire N17; wire [3 : 2] b; LUT2 #( .INIT ( 4'h6 )) \Mmux_b<3>11 ( .I0(bin_3_IBUF_17), .I1(bin_4_IBUF_16), .O(b[3]) ); LUT2 #( .INIT ( 4'h6 )) \Mmux_b<2>11 ( .I0(bin_2_IBUF_18), .I1(bin_4_IBUF_16), .O(b[2]) ); LUT3 #( .INIT ( 8'hE4 )) Mmux_yout202 ( .I0(bin_0_IBUF_20), .I1(Mmux_yout191_69), .I2(Mmux_yout201), .O(yout_9_OBUF_31) ); LUT3 #( .INIT ( 8'hE4 )) Mmux_yout72 ( .I0(bin_0_IBUF_20), .I1(Mmux_yout61), .I2(Mmux_yout71), .O(yout_13_OBUF_27) ); LUT3 #( .INIT ( 8'hE4 )) Mmux_yout81 ( .I0(bin_0_IBUF_20), .I1(Mmux_yout71), .I2(Mmux_yout111_66), .O(yout_14_OBUF_26) ); LUT3 #( .INIT ( 8'hE4 )) Mmux_yout41 ( .I0(bin_0_IBUF_20), .I1(Mmux_yout201), .I2(Mmux_yout51), .O(yout_10_OBUF_30) ); LUT3 #( .INIT ( 8'hE4 )) Mmux_yout62 ( .I0(bin_0_IBUF_20), .I1(Mmux_yout52), .I2(Mmux_yout61), .O(yout_12_OBUF_28) ); LUT3 #( .INIT ( 8'hE4 )) Mmux_yout53 ( .I0(bin_0_IBUF_20), .I1(Mmux_yout51), .I2(Mmux_yout52), .O(yout_11_OBUF_29) ); LUT5 #( .INIT ( 32'hFD5DA808 )) Mmux_yout1911 ( .I0(bin_1_IBUF_19), .I1(\b<2>_mmx_out8 ), .I2(bin_4_IBUF_16), .I3(\b<2>_mmx_out9 ), .I4(Mmux_yout1711), .O(Mmux_yout191_69) ); LUT5 #( .INIT ( 32'hFD5DA808 )) Mmux_yout2011 ( .I0(bin_1_IBUF_19), .I1(\b<2>_mmx_out10 ), .I2(bin_4_IBUF_16), .I3(\b<2>_mmx_out11 ), .I4(Mmux_yout1811), .O(Mmux_yout201) ); LUT5 #( .INIT ( 32'hFBEA5140 )) Mmux_yout711 ( .I0(bin_1_IBUF_19), .I1(bin_4_IBUF_16), .I2(\b<2>_mmx_out15 ), .I3(\b<2>_mmx_out14 ), .I4(Mmux_yout114_81), .O(Mmux_yout71) ); LUT5 #( .INIT ( 32'hFBEA5140 )) Mmux_yout611 ( .I0(bin_1_IBUF_19), .I1(bin_4_IBUF_16), .I2(\b<2>_mmx_out13 ), .I3(\b<2>_mmx_out12 ), .I4(Mmux_yout1112), .O(Mmux_yout61) ); LUT3 #( .INIT ( 8'h40 )) Mmux_yout9111 ( .I0(rotate_IBUF_21), .I1(ain_15_IBUF_15), .I2(sra_IBUF_22), .O(Mmux_yout911) ); LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \b<2>311 ( .I0(b[2]), .I1(b[3]), .I2(ain_6_IBUF_12), .I3(ain_14_IBUF_1), .I4(ain_10_IBUF_9), .I5(ain_2_IBUF_4), .O(\b<2>_mmx_out ) ); LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) Mmux_yout12211 ( .I0(b[3]), .I1(bin_2_IBUF_18), .I2(ain_1_IBUF_2), .I3(ain_5_IBUF_10), .I4(ain_13_IBUF_3), .I5(ain_9_IBUF_11), .O(Mmux_yout1221) ); LUT5 #( .INIT ( 32'hFD5DA808 )) Mmux_yout131 ( .I0(bin_0_IBUF_20), .I1(Mmux_yout1224), .I2(bin_1_IBUF_19), .I3(Mmux_yout1311), .I4(Mmux_yout121), .O(yout_2_OBUF_38) ); LUT5 #( .INIT ( 32'hFBEA5140 )) Mmux_yout142 ( .I0(bin_0_IBUF_20), .I1(bin_1_IBUF_19), .I2(Mmux_yout1311), .I3(Mmux_yout1224), .I4(Mmux_yout141), .O(yout_3_OBUF_37) ); LUT5 #( .INIT ( 32'hFD5DA808 )) Mmux_yout151 ( .I0(bin_0_IBUF_20), .I1(Mmux_yout1311), .I2(bin_1_IBUF_19), .I3(Mmux_yout1511), .I4(Mmux_yout141), .O(yout_4_OBUF_36) ); LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) Mmux_yout161 ( .I0(bin_0_IBUF_20), .I1(bin_1_IBUF_19), .I2(Mmux_yout1411), .I3(Mmux_yout1611_80), .I4(Mmux_yout1511), .I5(Mmux_yout1311), .O(yout_5_OBUF_35) ); LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) Mmux_yout171 ( .I0(bin_0_IBUF_20), .I1(bin_1_IBUF_19), .I2(Mmux_yout1511), .I3(Mmux_yout1711), .I4(Mmux_yout1611_80), .I5(Mmux_yout1411), .O(yout_6_OBUF_34) ); LUT5 #( .INIT ( 32'hFBEA5140 )) Mmux_yout191 ( .I0(bin_0_IBUF_20), .I1(bin_1_IBUF_19), .I2(Mmux_yout1811), .I3(Mmux_yout1611_80), .I4(Mmux_yout191_69), .O(yout_8_OBUF_32) ); LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) Mmux_yout181 ( .I0(bin_0_IBUF_20), .I1(bin_1_IBUF_19), .I2(Mmux_yout1611_80), .I3(Mmux_yout1811), .I4(Mmux_yout1711), .I5(Mmux_yout1511), .O(yout_7_OBUF_33) ); LUT6 #( .INIT ( 64'hFD5D5D5DA8080808 )) \b<2>31 ( .I0(b[2]), .I1(ain_4_IBUF_8), .I2(b[3]), .I3(ain_12_IBUF_5), .I4(rotate_IBUF_21), .I5(\b<3>_mmx_out11 ), .O(\b<2>_mmx_out11 ) ); LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \b<2>1511 ( .I0(b[2]), .I1(b[3]), .I2(ain_10_IBUF_9), .I3(ain_2_IBUF_4), .I4(ain_6_IBUF_12), .I5(ain_14_IBUF_1), .O(\b<2>151 ) ); LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) Mmux_yout511 ( .I0(bin_1_IBUF_19), .I1(bin_4_IBUF_16), .I2(\b<2>_mmx_out12 ), .I3(\b<2>_mmx_out13 ), .I4(\b<2>_mmx_out9 ), .I5(\b<2>_mmx_out8 ), .O(Mmux_yout51) ); LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) Mmux_yout521 ( .I0(bin_1_IBUF_19), .I1(bin_4_IBUF_16), .I2(\b<2>_mmx_out14 ), .I3(\b<2>_mmx_out15 ), .I4(\b<2>_mmx_out11 ), .I5(\b<2>_mmx_out10 ), .O(Mmux_yout52) ); LUT5 #( .INIT ( 32'hA8202020 )) Mmux_yout31 ( .I0(bin_1_IBUF_19), .I1(bin_4_IBUF_16), .I2(\b<2>_mmx_out ), .I3(\b<2>151 ), .I4(rotate_IBUF_21), .O(Mmux_yout3) ); LUT6 #( .INIT ( 64'hFD5D5D5DA8080808 )) Mmux_yout33 ( .I0(bin_2_IBUF_18), .I1(\b<3>_mmx_out23 ), .I2(bin_4_IBUF_16), .I3(\b<2>111 ), .I4(rotate_IBUF_21), .I5(Mmux_yout31_93), .O(Mmux_yout32_94) ); LUT5 #( .INIT ( 32'hEEFE4454 )) Mmux_yout34 ( .I0(bin_0_IBUF_20), .I1(Mmux_yout3), .I2(Mmux_yout32_94), .I3(bin_1_IBUF_19), .I4(Mmux_yout122_68), .O(yout_0_OBUF_40) ); LUT6 #( .INIT ( 64'hEFABABAB45010101 )) Mmux_yout122 ( .I0(bin_1_IBUF_19), .I1(bin_4_IBUF_16), .I2(N2), .I3(rotate_IBUF_21), .I4(Mmux_yout1221), .I5(Mmux_yout1224), .O(Mmux_yout122_68) ); LUT6 #( .INIT ( 64'hA8AAA88820222000 )) Mmux_yout1141 ( .I0(rotate_IBUF_21), .I1(b[2]), .I2(ain_8_IBUF_13), .I3(b[3]), .I4(ain_0_IBUF_0), .I5(\b<3>_mmx_out23 ), .O(Mmux_yout1141_96) ); LUT4 #( .INIT ( 16'hE444 )) Mmux_yout1213 ( .I0(bin_4_IBUF_16), .I1(\b<2>_mmx_out ), .I2(\b<2>151 ), .I3(rotate_IBUF_21), .O(Mmux_yout1213_99) ); LUT4 #( .INIT ( 16'hFDA8 )) Mmux_yout1214 ( .I0(bin_1_IBUF_19), .I1(Mmux_yout1211_97), .I2(Mmux_yout1212_98), .I3(Mmux_yout1213_99), .O(Mmux_yout121) ); LUT4 #( .INIT ( 16'hFE54 )) Mmux_yout1413 ( .I0(bin_1_IBUF_19), .I1(Mmux_yout1211_97), .I2(Mmux_yout1212_98), .I3(Mmux_yout1411), .O(Mmux_yout141) ); LUT6 #( .INIT ( 64'hA8A0282088800800 )) \b<2>21 ( .I0(rotate_IBUF_21), .I1(b[2]), .I2(b[3]), .I3(ain_0_IBUF_0), .I4(ain_8_IBUF_13), .I5(ain_4_IBUF_8), .O(\b<2>2 ) ); LUT6 #( .INIT ( 64'hDDD55D5588800800 )) Mmux_yout17112 ( .I0(b[3]), .I1(rotate_IBUF_21), .I2(b[2]), .I3(ain_13_IBUF_3), .I4(ain_9_IBUF_11), .I5(Mmux_yout17111_101), .O(Mmux_yout17112_102) ); LUT2 #( .INIT ( 4'h8 )) \b<2>5_SW0 ( .I0(rotate_IBUF_21), .I1(ain_13_IBUF_3), .O(N4) ); LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \b<2>5 ( .I0(b[3]), .I1(b[2]), .I2(ain_1_IBUF_2), .I3(N4), .I4(ain_5_IBUF_10), .I5(ain_9_IBUF_11), .O(\b<2>_mmx_out13 ) ); LUT6 #( .INIT ( 64'hDDD55D5588800800 )) Mmux_yout18112 ( .I0(b[3]), .I1(rotate_IBUF_21), .I2(b[2]), .I3(ain_14_IBUF_1), .I4(ain_10_IBUF_9), .I5(Mmux_yout18111_104), .O(Mmux_yout18112_105) ); LUT6 #( .INIT ( 64'hEFEA454045404540 )) \b<2>29 ( .I0(b[3]), .I1(ain_3_IBUF_6), .I2(b[2]), .I3(ain_7_IBUF_14), .I4(N6), .I5(rotate_IBUF_21), .O(\b<2>_mmx_out9 ) ); LUT6 #( .INIT ( 64'hFFF7DDD5AAA28880 )) Mmux_yout115 ( .I0(bin_0_IBUF_20), .I1(bin_1_IBUF_19), .I2(Mmux_yout112_108), .I3(Mmux_yout113_109), .I4(Mmux_yout114_81), .I5(Mmux_yout111_66), .O(yout_15_OBUF_25) ); LUT2 #( .INIT ( 4'h8 )) \b<2>7_SW0 ( .I0(rotate_IBUF_21), .I1(ain_14_IBUF_1), .O(N8) ); LUT6 #( .INIT ( 64'hFD75B931EC64A820 )) \b<2>7 ( .I0(b[3]), .I1(b[2]), .I2(ain_2_IBUF_4), .I3(N8), .I4(ain_6_IBUF_12), .I5(ain_10_IBUF_9), .O(\b<2>_mmx_out15 ) ); LUT5 #( .INIT ( 32'hFD5DA808 )) Mmux_yout111 ( .I0(bin_1_IBUF_19), .I1(N10), .I2(bin_4_IBUF_16), .I3(Mmux_yout1221), .I4(Mmux_yout1112), .O(Mmux_yout111_66) ); LUT5 #( .INIT ( 32'hFBEA5140 )) Mmux_yout1611 ( .I0(bin_2_IBUF_18), .I1(bin_4_IBUF_16), .I2(\b<3>_mmx_out24 ), .I3(\b<3>_mmx_out22 ), .I4(N12), .O(Mmux_yout1611_80) ); IBUF ain_15_IBUF ( .I(ain[15]), .O(ain_15_IBUF_15) ); IBUF ain_14_IBUF ( .I(ain[14]), .O(ain_14_IBUF_1) ); IBUF ain_13_IBUF ( .I(ain[13]), .O(ain_13_IBUF_3) ); IBUF ain_12_IBUF ( .I(ain[12]), .O(ain_12_IBUF_5) ); IBUF ain_11_IBUF ( .I(ain[11]), .O(ain_11_IBUF_7) ); IBUF ain_10_IBUF ( .I(ain[10]), .O(ain_10_IBUF_9) ); IBUF ain_9_IBUF ( .I(ain[9]), .O(ain_9_IBUF_11) ); IBUF ain_8_IBUF ( .I(ain[8]), .O(ain_8_IBUF_13) ); IBUF ain_7_IBUF ( .I(ain[7]), .O(ain_7_IBUF_14) ); IBUF ain_6_IBUF ( .I(ain[6]), .O(ain_6_IBUF_12) ); IBUF ain_5_IBUF ( .I(ain[5]), .O(ain_5_IBUF_10) ); IBUF ain_4_IBUF ( .I(ain[4]), .O(ain_4_IBUF_8) ); IBUF ain_3_IBUF ( .I(ain[3]), .O(ain_3_IBUF_6) ); IBUF ain_2_IBUF ( .I(ain[2]), .O(ain_2_IBUF_4) ); IBUF ain_1_IBUF ( .I(ain[1]), .O(ain_1_IBUF_2) ); IBUF ain_0_IBUF ( .I(ain[0]), .O(ain_0_IBUF_0) ); IBUF bin_4_IBUF ( .I(bin[4]), .O(bin_4_IBUF_16) ); IBUF bin_3_IBUF ( .I(bin[3]), .O(bin_3_IBUF_17) ); IBUF bin_2_IBUF ( .I(bin[2]), .O(bin_2_IBUF_18) ); IBUF bin_1_IBUF ( .I(bin[1]), .O(bin_1_IBUF_19) ); IBUF bin_0_IBUF ( .I(bin[0]), .O(bin_0_IBUF_20) ); IBUF rotate_IBUF ( .I(rotate), .O(rotate_IBUF_21) ); IBUF sra_IBUF ( .I(sra), .O(sra_IBUF_22) ); OBUF yout_15_OBUF ( .I(yout_15_OBUF_25), .O(yout[15]) ); OBUF yout_14_OBUF ( .I(yout_14_OBUF_26), .O(yout[14]) ); OBUF yout_13_OBUF ( .I(yout_13_OBUF_27), .O(yout[13]) ); OBUF yout_12_OBUF ( .I(yout_12_OBUF_28), .O(yout[12]) ); OBUF yout_11_OBUF ( .I(yout_11_OBUF_29), .O(yout[11]) ); OBUF yout_10_OBUF ( .I(yout_10_OBUF_30), .O(yout[10]) ); OBUF yout_9_OBUF ( .I(yout_9_OBUF_31), .O(yout[9]) ); OBUF yout_8_OBUF ( .I(yout_8_OBUF_32), .O(yout[8]) ); OBUF yout_7_OBUF ( .I(yout_7_OBUF_33), .O(yout[7]) ); OBUF yout_6_OBUF ( .I(yout_6_OBUF_34), .O(yout[6]) ); OBUF yout_5_OBUF ( .I(yout_5_OBUF_35), .O(yout[5]) ); OBUF yout_4_OBUF ( .I(yout_4_OBUF_36), .O(yout[4]) ); OBUF yout_3_OBUF ( .I(yout_3_OBUF_37), .O(yout[3]) ); OBUF yout_2_OBUF ( .I(yout_2_OBUF_38), .O(yout[2]) ); OBUF yout_1_OBUF ( .I(yout_1_OBUF_39), .O(yout[1]) ); OBUF yout_0_OBUF ( .I(yout_0_OBUF_40), .O(yout[0]) ); LUT6 #( .INIT ( 64'hF7D5D5D5A2808080 )) \b<3>151 ( .I0(b[3]), .I1(rotate_IBUF_21), .I2(ain_0_IBUF_0), .I3(ain_15_IBUF_15), .I4(sra_IBUF_22), .I5(ain_8_IBUF_13), .O(\b<3>_mmx_out22 ) ); LUT6 #( .INIT ( 64'hF7D5D5D5A2808080 )) \b<3>181 ( .I0(b[3]), .I1(rotate_IBUF_21), .I2(ain_1_IBUF_2), .I3(ain_15_IBUF_15), .I4(sra_IBUF_22), .I5(ain_9_IBUF_11), .O(\b<3>_mmx_out25 ) ); LUT6 #( .INIT ( 64'hF7D5D5D5A2808080 )) \b<3>201 ( .I0(b[3]), .I1(rotate_IBUF_21), .I2(ain_2_IBUF_4), .I3(ain_15_IBUF_15), .I4(sra_IBUF_22), .I5(ain_10_IBUF_9), .O(\b<3>_mmx_out27 ) ); LUT6 #( .INIT ( 64'hF7D5D5D5A2808080 )) \b<3>221 ( .I0(b[3]), .I1(rotate_IBUF_21), .I2(ain_3_IBUF_6), .I3(ain_15_IBUF_15), .I4(sra_IBUF_22), .I5(ain_11_IBUF_7), .O(\b<3>_mmx_out29 ) ); LUT6 #( .INIT ( 64'hF7D5D5D5A2808080 )) \b<3>231 ( .I0(b[3]), .I1(rotate_IBUF_21), .I2(ain_5_IBUF_10), .I3(ain_15_IBUF_15), .I4(sra_IBUF_22), .I5(ain_13_IBUF_3), .O(\b<3>_mmx_out3 ) ); LUT6 #( .INIT ( 64'hF7D5D5D5A2808080 )) \b<3>251 ( .I0(b[3]), .I1(rotate_IBUF_21), .I2(ain_6_IBUF_12), .I3(ain_15_IBUF_15), .I4(sra_IBUF_22), .I5(ain_14_IBUF_1), .O(\b<3>_mmx_out5 ) ); LUT6 #( .INIT ( 64'hF7D5A280A280A280 )) \b<3>41 ( .I0(rotate_IBUF_21), .I1(b[3]), .I2(ain_9_IBUF_11), .I3(ain_1_IBUF_2), .I4(ain_15_IBUF_15), .I5(sra_IBUF_22), .O(\b<3>_mmx_out12 ) ); LUT6 #( .INIT ( 64'hF7D5A280A280A280 )) \b<3>61 ( .I0(rotate_IBUF_21), .I1(b[3]), .I2(ain_10_IBUF_9), .I3(ain_2_IBUF_4), .I4(ain_15_IBUF_15), .I5(sra_IBUF_22), .O(\b<3>_mmx_out14 ) ); LUT5 #( .INIT ( 32'hB391A280 )) Mmux_yout14112 ( .I0(bin_3_IBUF_17), .I1(bin_4_IBUF_16), .I2(ain_2_IBUF_4), .I3(ain_14_IBUF_1), .I4(ain_6_IBUF_12), .O(Mmux_yout14112_87) ); LUT6 #( .INIT ( 64'hFED4D4D4BA909090 )) Mmux_yout14113 ( .I0(bin_4_IBUF_16), .I1(bin_2_IBUF_18), .I2(Mmux_yout14112_87), .I3(rotate_IBUF_21), .I4(Mmux_yout14111_86), .I5(\b<3>_mmx_out27 ), .O(Mmux_yout1411) ); LUT5 #( .INIT ( 32'hB391A280 )) Mmux_yout13112 ( .I0(bin_3_IBUF_17), .I1(bin_4_IBUF_16), .I2(ain_1_IBUF_2), .I3(ain_13_IBUF_3), .I4(ain_5_IBUF_10), .O(Mmux_yout13112_89) ); LUT6 #( .INIT ( 64'hFED4D4D4BA909090 )) Mmux_yout13113 ( .I0(bin_4_IBUF_16), .I1(bin_2_IBUF_18), .I2(Mmux_yout13112_89), .I3(rotate_IBUF_21), .I4(Mmux_yout13111_88), .I5(\b<3>_mmx_out25 ), .O(Mmux_yout1311) ); LUT5 #( .INIT ( 32'hB391A280 )) Mmux_yout15112 ( .I0(bin_3_IBUF_17), .I1(bin_4_IBUF_16), .I2(ain_3_IBUF_6), .I3(ain_15_IBUF_15), .I4(ain_7_IBUF_14), .O(Mmux_yout15112_91) ); LUT6 #( .INIT ( 64'hFED4D4D4BA909090 )) Mmux_yout15113 ( .I0(bin_4_IBUF_16), .I1(bin_2_IBUF_18), .I2(Mmux_yout15112_91), .I3(rotate_IBUF_21), .I4(Mmux_yout15111_90), .I5(\b<3>_mmx_out29 ), .O(Mmux_yout1511) ); LUT6 #( .INIT ( 64'h082A193B4C6E5D7F )) Mmux_yout122_SW0 ( .I0(bin_2_IBUF_18), .I1(b[3]), .I2(ain_13_IBUF_3), .I3(ain_5_IBUF_10), .I4(ain_1_IBUF_2), .I5(ain_9_IBUF_11), .O(N2) ); LUT6 #( .INIT ( 64'hFD75FD75FD75A820 )) Mmux_yout1142 ( .I0(bin_4_IBUF_16), .I1(bin_2_IBUF_18), .I2(\b<3>_mmx_out11 ), .I3(\b<2>111 ), .I4(Mmux_yout911), .I5(Mmux_yout1141_96), .O(Mmux_yout114_81) ); LUT5 #( .INIT ( 32'h62224000 )) Mmux_yout1211 ( .I0(bin_2_IBUF_18), .I1(bin_4_IBUF_16), .I2(\b<2>111 ), .I3(rotate_IBUF_21), .I4(\b<3>_mmx_out22 ), .O(Mmux_yout1211_97) ); LUT5 #( .INIT ( 32'hFBEA5140 )) Mmux_yout17113 ( .I0(bin_4_IBUF_16), .I1(bin_2_IBUF_18), .I2(\b<3>_mmx_out3 ), .I3(\b<3>_mmx_out25 ), .I4(Mmux_yout17112_102), .O(Mmux_yout1711) ); LUT5 #( .INIT ( 32'hFBEA5140 )) Mmux_yout18113 ( .I0(bin_4_IBUF_16), .I1(bin_2_IBUF_18), .I2(\b<3>_mmx_out5 ), .I3(\b<3>_mmx_out27 ), .I4(Mmux_yout18112_105), .O(Mmux_yout1811) ); LUT6 #( .INIT ( 64'hAAA00A0088800800 )) Mmux_yout112 ( .I0(bin_2_IBUF_18), .I1(bin_4_IBUF_16), .I2(bin_3_IBUF_17), .I3(ain_6_IBUF_12), .I4(ain_14_IBUF_1), .I5(rotate_IBUF_21), .O(Mmux_yout11) ); LUT6 #( .INIT ( 64'h5551151144400400 )) Mmux_yout114 ( .I0(bin_2_IBUF_18), .I1(bin_4_IBUF_16), .I2(bin_3_IBUF_17), .I3(ain_2_IBUF_4), .I4(ain_10_IBUF_9), .I5(\b<3>_mmx_out14 ), .O(Mmux_yout113_109) ); LUT6 #( .INIT ( 64'hF7D5D5D5A2808080 )) Mmux_yout111_SW0 ( .I0(bin_2_IBUF_18), .I1(rotate_IBUF_21), .I2(Mmux_yout1222), .I3(ain_15_IBUF_15), .I4(sra_IBUF_22), .I5(\b<3>_mmx_out12 ), .O(N10) ); LUT6 #( .INIT ( 64'hDF8FDD858A8A8880 )) Mmux_yout1611_SW0 ( .I0(bin_3_IBUF_17), .I1(ain_4_IBUF_8), .I2(bin_4_IBUF_16), .I3(rotate_IBUF_21), .I4(Mmux_yout911), .I5(ain_12_IBUF_5), .O(N12) ); LUT5 #( .INIT ( 32'hF6909090 )) \b<3>171 ( .I0(bin_3_IBUF_17), .I1(bin_4_IBUF_16), .I2(ain_0_IBUF_0), .I3(rotate_IBUF_21), .I4(ain_8_IBUF_13), .O(\b<3>_mmx_out24 ) ); LUT4 #( .INIT ( 16'hF690 )) \b<3>161 ( .I0(bin_3_IBUF_17), .I1(bin_4_IBUF_16), .I2(ain_4_IBUF_8), .I3(ain_12_IBUF_5), .O(\b<3>_mmx_out23 ) ); LUT4 #( .INIT ( 16'hF690 )) \b<2>281 ( .I0(bin_2_IBUF_18), .I1(bin_4_IBUF_16), .I2(\b<3>_mmx_out29 ), .I3(\b<3>_mmx_out7 ), .O(\b<2>_mmx_out8 ) ); LUT4 #( .INIT ( 16'hF690 )) \b<2>61 ( .I0(bin_2_IBUF_18), .I1(bin_4_IBUF_16), .I2(\b<3>_mmx_out5 ), .I3(\b<3>_mmx_out14 ), .O(\b<2>_mmx_out14 ) ); LUT4 #( .INIT ( 16'hF690 )) \b<2>41 ( .I0(bin_2_IBUF_18), .I1(bin_4_IBUF_16), .I2(\b<3>_mmx_out3 ), .I3(\b<3>_mmx_out12 ), .O(\b<2>_mmx_out12 ) ); LUT4 #( .INIT ( 16'hF690 )) \b<2>1111 ( .I0(bin_3_IBUF_17), .I1(bin_4_IBUF_16), .I2(ain_12_IBUF_5), .I3(ain_4_IBUF_8), .O(\b<2>111 ) ); LUT6 #( .INIT ( 64'hFFF7DDD5AAA28880 )) Mmux_yout123 ( .I0(bin_0_IBUF_20), .I1(bin_1_IBUF_19), .I2(Mmux_yout1211_97), .I3(Mmux_yout1212_98), .I4(Mmux_yout1213_99), .I5(Mmux_yout122_68), .O(yout_1_OBUF_39) ); LUT6 #( .INIT ( 64'hBEAABE8282AA8282 )) \b<3>271 ( .I0(ain_15_IBUF_15), .I1(bin_3_IBUF_17), .I2(bin_4_IBUF_16), .I3(rotate_IBUF_21), .I4(sra_IBUF_22), .I5(ain_7_IBUF_14), .O(\b<3>_mmx_out7 ) ); LUT4 #( .INIT ( 16'hF690 )) Mmux_yout17111 ( .I0(bin_2_IBUF_18), .I1(bin_4_IBUF_16), .I2(ain_5_IBUF_10), .I3(ain_1_IBUF_2), .O(Mmux_yout17111_101) ); LUT4 #( .INIT ( 16'hF690 )) Mmux_yout18111 ( .I0(bin_2_IBUF_18), .I1(bin_4_IBUF_16), .I2(ain_6_IBUF_12), .I3(ain_2_IBUF_4), .O(Mmux_yout18111_104) ); LUT4 #( .INIT ( 16'hF690 )) \b<2>29_SW0 ( .I0(bin_2_IBUF_18), .I1(bin_4_IBUF_16), .I2(ain_15_IBUF_15), .I3(ain_11_IBUF_7), .O(N6) ); LUT5 #( .INIT ( 32'hE0EE2022 )) Mmux_yout32 ( .I0(ain_0_IBUF_0), .I1(bin_3_IBUF_17), .I2(rotate_IBUF_21), .I3(bin_4_IBUF_16), .I4(ain_8_IBUF_13), .O(Mmux_yout31_93) ); LUT6 #( .INIT ( 64'h9989988811011000 )) Mmux_yout1212 ( .I0(bin_2_IBUF_18), .I1(bin_4_IBUF_16), .I2(bin_3_IBUF_17), .I3(ain_12_IBUF_5), .I4(ain_4_IBUF_8), .I5(\b<3>_mmx_out24 ), .O(Mmux_yout1212_98) ); LUT6 #( .INIT ( 64'h7E5A3C1866422400 )) Mmux_yout14111 ( .I0(bin_3_IBUF_17), .I1(bin_4_IBUF_16), .I2(bin_2_IBUF_18), .I3(ain_6_IBUF_12), .I4(ain_10_IBUF_9), .I5(ain_14_IBUF_1), .O(Mmux_yout14111_86) ); LUT6 #( .INIT ( 64'h7E5A3C1866422400 )) Mmux_yout13111 ( .I0(bin_3_IBUF_17), .I1(bin_4_IBUF_16), .I2(bin_2_IBUF_18), .I3(ain_5_IBUF_10), .I4(ain_9_IBUF_11), .I5(ain_13_IBUF_3), .O(Mmux_yout13111_88) ); LUT6 #( .INIT ( 64'h7E5A3C1866422400 )) Mmux_yout15111 ( .I0(bin_3_IBUF_17), .I1(bin_4_IBUF_16), .I2(bin_2_IBUF_18), .I3(ain_7_IBUF_14), .I4(ain_11_IBUF_7), .I5(ain_15_IBUF_15), .O(Mmux_yout15111_90) ); LUT6 #( .INIT ( 64'hFFFFFFFFEAAB2AA8 )) \b<2>22 ( .I0(Mmux_yout911), .I1(bin_2_IBUF_18), .I2(bin_4_IBUF_16), .I3(bin_3_IBUF_17), .I4(ain_12_IBUF_5), .I5(\b<2>2 ), .O(\b<2>_mmx_out10 ) ); LUT4 #( .INIT ( 16'hF690 )) \b<3>31 ( .I0(bin_3_IBUF_17), .I1(bin_4_IBUF_16), .I2(ain_8_IBUF_13), .I3(ain_0_IBUF_0), .O(\b<3>_mmx_out11 ) ); LUT4 #( .INIT ( 16'hF690 )) Mmux_yout12221 ( .I0(bin_3_IBUF_17), .I1(bin_4_IBUF_16), .I2(ain_5_IBUF_10), .I3(ain_13_IBUF_3), .O(Mmux_yout1222) ); LUT6 #( .INIT ( 64'hAABAAAAAAAAAAAAA )) Mmux_yout113 ( .I0(Mmux_yout11), .I1(bin_4_IBUF_16), .I2(bin_2_IBUF_18), .I3(rotate_IBUF_21), .I4(ain_15_IBUF_15), .I5(sra_IBUF_22), .O(Mmux_yout112_108) ); MUXF7 Mmux_yout12243 ( .I0(N14), .I1(N15), .S(bin_2_IBUF_18), .O(Mmux_yout1224) ); LUT5 #( .INIT ( 32'hBE0E8202 )) Mmux_yout12243_F ( .I0(ain_3_IBUF_6), .I1(b[3]), .I2(bin_4_IBUF_16), .I3(rotate_IBUF_21), .I4(ain_11_IBUF_7), .O(N14) ); LUT5 #( .INIT ( 32'hBE0E8202 )) Mmux_yout12243_G ( .I0(ain_7_IBUF_14), .I1(b[3]), .I2(bin_4_IBUF_16), .I3(rotate_IBUF_21), .I4(ain_15_IBUF_15), .O(N15) ); MUXF7 Mmux_yout11123 ( .I0(N16), .I1(N17), .S(bin_2_IBUF_18), .O(Mmux_yout1112) ); LUT6 #( .INIT ( 64'hF7D5D5D5A2808080 )) Mmux_yout11123_F ( .I0(bin_4_IBUF_16), .I1(bin_3_IBUF_17), .I2(ain_7_IBUF_14), .I3(ain_15_IBUF_15), .I4(rotate_IBUF_21), .I5(\b<3>_mmx_out7 ), .O(N16) ); LUT6 #( .INIT ( 64'hFD75FD75FC30A820 )) Mmux_yout11123_G ( .I0(bin_4_IBUF_16), .I1(bin_3_IBUF_17), .I2(ain_3_IBUF_6), .I3(ain_11_IBUF_7), .I4(rotate_IBUF_21), .I5(Mmux_yout911), .O(N17) ); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif

// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 // Date : Tue Oct 17 18:54:09 2017 // Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_led_controller_0_0_stub.v // Design : ip_design_led_controller_0_0 // Purpose : Stub declaration of top-level module interface // Device : xc7z020clg484-1 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "led_controller_v1_0,Vivado 2017.3" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(LEDs_out, s00_axi_awaddr, s00_axi_awprot, s00_axi_awvalid, s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid, s00_axi_wready, s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr, s00_axi_arprot, s00_axi_arvalid, s00_axi_arready, s00_axi_rdata, s00_axi_rresp, s00_axi_rvalid, s00_axi_rready, s00_axi_aclk, s00_axi_aresetn) /* synthesis syn_black_box black_box_pad_pin="LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */; output [7:0]LEDs_out; input [3:0]s00_axi_awaddr; input [2:0]s00_axi_awprot; input s00_axi_awvalid; output s00_axi_awready; input [31:0]s00_axi_wdata; input [3:0]s00_axi_wstrb; input s00_axi_wvalid; output s00_axi_wready; output [1:0]s00_axi_bresp; output s00_axi_bvalid; input s00_axi_bready; input [3:0]s00_axi_araddr; input [2:0]s00_axi_arprot; input s00_axi_arvalid; output s00_axi_arready; output [31:0]s00_axi_rdata; output [1:0]s00_axi_rresp; output s00_axi_rvalid; input s00_axi_rready; input s00_axi_aclk; input s00_axi_aresetn; endmodule

/* ========================================================================================================================= | Verilog module for driving a half-bridge (HB) conveter topology in digital current mode control. | | | | Theory of operation: This module is very similar to a duty cycle mode controlled HB. | | In a nutshell, the high side FET is turned on. The inductor current rises, and a comparator | | on the board itself flips when the inductor current reaches a preset reference. This is accomplished | | by using high-side current sense resistor and some isolation circuitry. When the comparator (cmp) flips high, | | a flag is set. The high side is then turned off, a counter clocks the dead time, and the low side FET | | is turned on for the remainder of the switching period. | | | | Inputs/Outputs: | | clk: FPGA system clock input. | | cmp: The high-side current sense comparator input. | | DT: Dead time in sysclk ticks. | | MaxCount: the length of a switching period in sysclk ticks. | | High: Hide side MOSFET gate drive signal. | | Low: Low side MOSFET gate drive signal. | ========================================================================================================================= */ `timescale 1ns/1ps `define minDuty 10 `define offTime 5 module PeakCurrentHB(clk, cmp, DT, MaxCount, High, Low); //Inputs and outputs input clk, cmp; input [7:0] DT, MaxCount; output reg High, Low; //Internal variables reg [7:0] Counter = 0; reg [7:0] DTCount = 0; reg [7:0] MaxDuty = 0; reg Flag; //Wires wire [7:0] Counter_Next, DTCount_Next, MaxDuty_Next; wire High_Next, Low_Next, Flag_Next; //For simulation purposes only initial begin High = 0; Low = 1; end //Sequential Code always @ (posedge(clk)) begin Counter <= Counter_Next; High <= High_Next; Low <= Low_Next; Flag <= Flag_Next; MaxDuty <= MaxDuty_Next; end //Clock the dead time counter on the flag edge always @ (negedge(High)) begin DTCount <= DTCount_Next; end //Combinatorial Code assign Flag_Next = (Counter == 8'b00000000)?0:(cmp || Flag); assign Counter_Next = (Counter < MaxCount)?(Counter+1):0; assign High_Next = (Counter >= DT) && (!Flag) && (Counter < MaxDuty); assign Low_Next = ((Flag) && (Counter > DTCount)) || ((!High) && (Counter > MaxDuty) && (Counter >= DTCount)); assign DTCount_Next = Counter + DT; assign MaxDuty_Next = (MaxCount >> 1) - 1; endmodule

`include "mem_beh.v" `include "regfile_beh.v" `include "components.v" `include "control_units.v" `include "alu_beh.v" `include "mux2to1_beh.v" module kustar; reg clock, clear; wire [31:0] MuxtoPC, PCtoMux, MuxtoMem, MemtoInstReg, SigntoShift, ShifttoMux, MemdatatoMux, MuxtoWriteData; wire [31:0] RegtoA, RegtoB, AtoMux, BtoMux, AMuxtoALU, BMuxtoALU, ALUtoALUOut, ALUOuttoMux , ShifttoConcat, ConcattoMux; wire Zero; wire [5:0] Op ; wire [4:0] Rs, Rt, MuxtoWriteReg; wire [15:0] AddrorConst ; wire PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, ALUSrcA, RegWrite, RegDst; wire [1:0] PCSource, ALUOp, ALUSrcB; wire [2:0] ALUcontrol; reg [31:0] four; reg yesItAlwaysTure; reg yesItAlwyasFalse; reg [31:0] unused; single_register PC (MuxtoPC, PCtoMux, clock, clear, (Zero&PCWriteCond)|PCWrite); mux2to1 PostPCMux (PCtoMux, ALUOuttoMux, MuxtoMem, IorD); mem Memory (MuxtoMem, RegtoB, MemtoInstReg, MemWrite, MemRead, clock); single_register InstReg (MemtoInstReg, {Op[5:0], Rs[4:0], Rt[4:0], AddrorConst[15:0]}, clock, clear, IRWrite); single_register MemDataReg (MemtoInstReg, MemdatatoMux, clock, clear, MemRead); mux2to1for5bit WriteRegMux (Rt, AddrorConst[15:11], MuxtoWriteReg, RegDst); mux2to1 PreWriteDataMux (ALUOuttoMux, MemdatatoMux, MuxtoWriteData, MemtoReg); registerfile Registers (Rs, RegtoA, Rt, RegtoB, MuxtoWriteReg, MuxtoWriteData, clock, yesItAlwyasFalse, RegWrite); signextd SignExtend (AddrorConst, SigntoShift); shiftleft2 ShiftSign (SigntoShift, ShifttoMux); mux2to1 AMux (PCtoMux, RegtoA, AMuxtoALU, ALUSrcA); mux4to1 BMux (RegtoB, four, SigntoShift, ShifttoMux, BMuxtoALU, ALUSrcB); ALU YesThisIsALU (AMuxtoALU, BMuxtoALU, ALUcontrol, ALUtoALUOut, Zero); single_register ALUOut (ALUtoALUOut, ALUOuttoMux, clock, clear, yesItAlwaysTure); shiftleft2 PCShift ({Op[5:0], Rs[4:0], Rt[4:0], AddrorConst[15:0]}, ShifttoConcat); concatenate4to28 PCConcat (ShifttoConcat, PCtoMux, ConcattoMux); mux4to1 PCMux (ALUtoALUOut, ALUOuttoMux, ConcattoMux, unused, MuxtoPC, PCSource); mcu YesThisIsMCU (clock, clear, Op, PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, PCSource, ALUOp, ALUSrcB, ALUSrcA, RegWrite, RegDst); acu YesThisIsACU (AddrorConst[5:0], ALUOp, ALUcontrol); /* module acu(funct, ALUOp, ALUcontrol); input [5:0] funct; input [1:0] ALUOp; output [2:0] ALUcontrol; ------------------------------------------------------- module mcu(clk, clr, OP, PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, PCSource, ALUOp, ALUSrcB, ALUSrcA, RegWrite, RegDst); input clk, clr; input [5:0] OP; output PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, ALUSrcA, RegWrite, RegDst; output [1:0] PCSource, ALUOp, ALUSrcB; ------------------------------------------------------------- // concatenate pcin[31-28] with datain[27-0] to form a jump address module concatenate4to28(datain, pcin, pcout); input [31:0] datain, pcin; output [31:0] pcout; ------------------------------------------------------------- module ALU(inputA, inputB, ALUop, result, zero); input [31:0] inputA, inputB; input [2:0] ALUop; output [31:0] result; output zero; --------------------------------------------------------------- module mux4to1(datain0, datain1, datain2, datain3, dataout, select); input [31:0] datain0, datain1, datain2, datain3; input[1:0] select; output [31:0] dataout; ------------------------------------------- module shiftleft2(datain, dataout); input [31:0] datain; output [31:0] dataout; ----------------------------------------------------------- module signextd(datain, dataout); input [15:0] datain; output [31:0] dataout; ------------------------------------------------------------ module registerfile(ADDA, DATAA, ADDB, DATAB, ADDC, DATAC, clk, clr, WE); input [4:0] ADDA,ADDB, ADDC; input [31:0] DATAC; input clk, clr, WE; output [31:0] DATAA, DATAB; --------------------------------------------- module single_register(datain, dataout, clk, clr, WE); input [31:0] datain; output [31:0] dataout; input clk, clr, WE; ---------------- module mem(addr,datain,dataout, MemWrite, MemRead, clk); input clk; input [31:0] addr, datain; output [31:0] dataout; input MemWrite, MemRead; ------------------------------ module mux2to1(datain0,datain1, dataout, select); input [31:0] datain0, datain1; input select; output [31:0] dataout; */ initial forever #50 clock = ~clock; initial begin four = 4; yesItAlwaysTure = 1; yesItAlwyasFalse = 0; clock = 0; clear = 1; /* we may not connect clear to register file and memory because we don't want our initial data get cleared*/ #10 clear = 0; end initial #10000 $stop; endmodule

// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 // Date : Sun Apr 09 07:03:52 2017 // Host : GILAMONSTER running 64-bit major release (build 9200) // Command : write_verilog -force -mode funcsim // C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0_1/system_ov7670_controller_0_0_sim_netlist.v // Design : system_ov7670_controller_0_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7z020clg484-1 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* CHECK_LICENSE_TYPE = "system_ov7670_controller_0_0,ov7670_controller,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_controller,Vivado 2016.4" *) (* NotValidForBitStream *) module system_ov7670_controller_0_0 (clk, resend, config_finished, sioc, siod, reset, pwdn, xclk); (* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk; input resend; output config_finished; output sioc; inout siod; (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset; output pwdn; output xclk; wire \<const0> ; wire \<const1> ; wire clk; wire config_finished; wire resend; wire sioc; wire siod; wire xclk; assign pwdn = \<const0> ; assign reset = \<const1> ; GND GND (.G(\<const0> )); system_ov7670_controller_0_0_ov7670_controller U0 (.clk(clk), .config_finished(config_finished), .resend(resend), .sioc(sioc), .siod(siod), .xclk(xclk)); VCC VCC (.P(\<const1> )); endmodule (* ORIG_REF_NAME = "i2c_sender" *) module system_ov7670_controller_0_0_i2c_sender (E, sioc, p_0_in, \busy_sr_reg[1]_0 , siod, \busy_sr_reg[31]_0 , clk, p_1_in, DOADO, \busy_sr_reg[31]_1 ); output [0:0]E; output sioc; output p_0_in; output \busy_sr_reg[1]_0 ; output siod; input \busy_sr_reg[31]_0 ; input clk; input [0:0]p_1_in; input [15:0]DOADO; input [0:0]\busy_sr_reg[31]_1 ; wire [15:0]DOADO; wire [0:0]E; wire busy_sr0; wire \busy_sr[0]_i_3_n_0 ; wire \busy_sr[0]_i_5_n_0 ; wire \busy_sr[10]_i_1_n_0 ; wire \busy_sr[11]_i_1_n_0 ; wire \busy_sr[12]_i_1_n_0 ; wire \busy_sr[13]_i_1_n_0 ; wire \busy_sr[14]_i_1_n_0 ; wire \busy_sr[15]_i_1_n_0 ; wire \busy_sr[16]_i_1_n_0 ; wire \busy_sr[17]_i_1_n_0 ; wire \busy_sr[18]_i_1_n_0 ; wire \busy_sr[19]_i_1_n_0 ; wire \busy_sr[1]_i_1_n_0 ; wire \busy_sr[20]_i_1_n_0 ; wire \busy_sr[21]_i_1_n_0 ; wire \busy_sr[22]_i_1_n_0 ; wire \busy_sr[23]_i_1_n_0 ; wire \busy_sr[24]_i_1_n_0 ; wire \busy_sr[25]_i_1_n_0 ; wire \busy_sr[26]_i_1_n_0 ; wire \busy_sr[27]_i_1_n_0 ; wire \busy_sr[28]_i_1_n_0 ; wire \busy_sr[29]_i_1_n_0 ; wire \busy_sr[2]_i_1_n_0 ; wire \busy_sr[30]_i_1_n_0 ; wire \busy_sr[31]_i_1_n_0 ; wire \busy_sr[31]_i_2_n_0 ; wire \busy_sr[3]_i_1_n_0 ; wire \busy_sr[4]_i_1_n_0 ; wire \busy_sr[5]_i_1_n_0 ; wire \busy_sr[6]_i_1_n_0 ; wire \busy_sr[7]_i_1_n_0 ; wire \busy_sr[8]_i_1_n_0 ; wire \busy_sr[9]_i_1_n_0 ; wire \busy_sr_reg[1]_0 ; wire \busy_sr_reg[31]_0 ; wire [0:0]\busy_sr_reg[31]_1 ; wire \busy_sr_reg_n_0_[0] ; wire \busy_sr_reg_n_0_[10] ; wire \busy_sr_reg_n_0_[11] ; wire \busy_sr_reg_n_0_[12] ; wire \busy_sr_reg_n_0_[13] ; wire \busy_sr_reg_n_0_[14] ; wire \busy_sr_reg_n_0_[15] ; wire \busy_sr_reg_n_0_[16] ; wire \busy_sr_reg_n_0_[17] ; wire \busy_sr_reg_n_0_[18] ; wire \busy_sr_reg_n_0_[1] ; wire \busy_sr_reg_n_0_[21] ; wire \busy_sr_reg_n_0_[22] ; wire \busy_sr_reg_n_0_[23] ; wire \busy_sr_reg_n_0_[24] ; wire \busy_sr_reg_n_0_[25] ; wire \busy_sr_reg_n_0_[26] ; wire \busy_sr_reg_n_0_[27] ; wire \busy_sr_reg_n_0_[28] ; wire \busy_sr_reg_n_0_[29] ; wire \busy_sr_reg_n_0_[2] ; wire \busy_sr_reg_n_0_[30] ; wire \busy_sr_reg_n_0_[3] ; wire \busy_sr_reg_n_0_[4] ; wire \busy_sr_reg_n_0_[5] ; wire \busy_sr_reg_n_0_[6] ; wire \busy_sr_reg_n_0_[7] ; wire \busy_sr_reg_n_0_[8] ; wire \busy_sr_reg_n_0_[9] ; wire clk; wire \data_sr[10]_i_1_n_0 ; wire \data_sr[12]_i_1_n_0 ; wire \data_sr[13]_i_1_n_0 ; wire \data_sr[14]_i_1_n_0 ; wire \data_sr[15]_i_1_n_0 ; wire \data_sr[16]_i_1_n_0 ; wire \data_sr[17]_i_1_n_0 ; wire \data_sr[18]_i_1_n_0 ; wire \data_sr[19]_i_1_n_0 ; wire \data_sr[22]_i_1_n_0 ; wire \data_sr[27]_i_1_n_0 ; wire \data_sr[30]_i_1_n_0 ; wire \data_sr[31]_i_1_n_0 ; wire \data_sr[31]_i_2_n_0 ; wire \data_sr[3]_i_1_n_0 ; wire \data_sr[4]_i_1_n_0 ; wire \data_sr[5]_i_1_n_0 ; wire \data_sr[6]_i_1_n_0 ; wire \data_sr[7]_i_1_n_0 ; wire \data_sr[8]_i_1_n_0 ; wire \data_sr[9]_i_1_n_0 ; wire \data_sr_reg_n_0_[10] ; wire \data_sr_reg_n_0_[11] ; wire \data_sr_reg_n_0_[12] ; wire \data_sr_reg_n_0_[13] ; wire \data_sr_reg_n_0_[14] ; wire \data_sr_reg_n_0_[15] ; wire \data_sr_reg_n_0_[16] ; wire \data_sr_reg_n_0_[17] ; wire \data_sr_reg_n_0_[18] ; wire \data_sr_reg_n_0_[19] ; wire \data_sr_reg_n_0_[1] ; wire \data_sr_reg_n_0_[20] ; wire \data_sr_reg_n_0_[21] ; wire \data_sr_reg_n_0_[22] ; wire \data_sr_reg_n_0_[23] ; wire \data_sr_reg_n_0_[24] ; wire \data_sr_reg_n_0_[25] ; wire \data_sr_reg_n_0_[26] ; wire \data_sr_reg_n_0_[27] ; wire \data_sr_reg_n_0_[28] ; wire \data_sr_reg_n_0_[29] ; wire \data_sr_reg_n_0_[2] ; wire \data_sr_reg_n_0_[30] ; wire \data_sr_reg_n_0_[31] ; wire \data_sr_reg_n_0_[3] ; wire \data_sr_reg_n_0_[4] ; wire \data_sr_reg_n_0_[5] ; wire \data_sr_reg_n_0_[6] ; wire \data_sr_reg_n_0_[7] ; wire \data_sr_reg_n_0_[8] ; wire \data_sr_reg_n_0_[9] ; wire [7:6]divider_reg__0; wire [5:0]divider_reg__1; wire p_0_in; wire [7:0]p_0_in__0; wire [0:0]p_1_in; wire [1:0]p_1_in_0; wire sioc; wire sioc_i_1_n_0; wire sioc_i_2_n_0; wire sioc_i_3_n_0; wire sioc_i_4_n_0; wire sioc_i_5_n_0; wire siod; wire siod_INST_0_i_1_n_0; LUT6 #( .INIT(64'h4000FFFF40004000)) \busy_sr[0]_i_1 (.I0(\busy_sr[0]_i_3_n_0 ), .I1(divider_reg__0[6]), .I2(divider_reg__0[7]), .I3(p_0_in), .I4(\busy_sr_reg[1]_0 ), .I5(p_1_in), .O(busy_sr0)); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \busy_sr[0]_i_3 (.I0(divider_reg__1[4]), .I1(divider_reg__1[2]), .I2(divider_reg__1[0]), .I3(divider_reg__1[1]), .I4(divider_reg__1[3]), .I5(divider_reg__1[5]), .O(\busy_sr[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( .INIT(32'hFFFFFFFE)) \busy_sr[0]_i_4 (.I0(divider_reg__1[2]), .I1(divider_reg__1[3]), .I2(divider_reg__1[0]), .I3(divider_reg__1[1]), .I4(\busy_sr[0]_i_5_n_0 ), .O(\busy_sr_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT4 #( .INIT(16'hFFFE)) \busy_sr[0]_i_5 (.I0(divider_reg__1[5]), .I1(divider_reg__1[4]), .I2(divider_reg__0[7]), .I3(divider_reg__0[6]), .O(\busy_sr[0]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT2 #( .INIT(4'h8)) \busy_sr[10]_i_1 (.I0(\busy_sr_reg_n_0_[9] ), .I1(p_0_in), .O(\busy_sr[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT2 #( .INIT(4'h8)) \busy_sr[11]_i_1 (.I0(\busy_sr_reg_n_0_[10] ), .I1(p_0_in), .O(\busy_sr[11]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT2 #( .INIT(4'h8)) \busy_sr[12]_i_1 (.I0(\busy_sr_reg_n_0_[11] ), .I1(p_0_in), .O(\busy_sr[12]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT2 #( .INIT(4'h8)) \busy_sr[13]_i_1 (.I0(\busy_sr_reg_n_0_[12] ), .I1(p_0_in), .O(\busy_sr[13]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT2 #( .INIT(4'h8)) \busy_sr[14]_i_1 (.I0(\busy_sr_reg_n_0_[13] ), .I1(p_0_in), .O(\busy_sr[14]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT2 #( .INIT(4'h8)) \busy_sr[15]_i_1 (.I0(\busy_sr_reg_n_0_[14] ), .I1(p_0_in), .O(\busy_sr[15]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT2 #( .INIT(4'h8)) \busy_sr[16]_i_1 (.I0(\busy_sr_reg_n_0_[15] ), .I1(p_0_in), .O(\busy_sr[16]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT2 #( .INIT(4'h8)) \busy_sr[17]_i_1 (.I0(\busy_sr_reg_n_0_[16] ), .I1(p_0_in), .O(\busy_sr[17]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT2 #( .INIT(4'h8)) \busy_sr[18]_i_1 (.I0(\busy_sr_reg_n_0_[17] ), .I1(p_0_in), .O(\busy_sr[18]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT2 #( .INIT(4'h8)) \busy_sr[19]_i_1 (.I0(\busy_sr_reg_n_0_[18] ), .I1(p_0_in), .O(\busy_sr[19]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h8)) \busy_sr[1]_i_1 (.I0(\busy_sr_reg_n_0_[0] ), .I1(p_0_in), .O(\busy_sr[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT2 #( .INIT(4'h8)) \busy_sr[20]_i_1 (.I0(p_1_in_0[0]), .I1(p_0_in), .O(\busy_sr[20]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT2 #( .INIT(4'h8)) \busy_sr[21]_i_1 (.I0(p_1_in_0[1]), .I1(p_0_in), .O(\busy_sr[21]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT2 #( .INIT(4'h8)) \busy_sr[22]_i_1 (.I0(\busy_sr_reg_n_0_[21] ), .I1(p_0_in), .O(\busy_sr[22]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT2 #( .INIT(4'h8)) \busy_sr[23]_i_1 (.I0(\busy_sr_reg_n_0_[22] ), .I1(p_0_in), .O(\busy_sr[23]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT2 #( .INIT(4'h8)) \busy_sr[24]_i_1 (.I0(\busy_sr_reg_n_0_[23] ), .I1(p_0_in), .O(\busy_sr[24]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT2 #( .INIT(4'h8)) \busy_sr[25]_i_1 (.I0(\busy_sr_reg_n_0_[24] ), .I1(p_0_in), .O(\busy_sr[25]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT2 #( .INIT(4'h8)) \busy_sr[26]_i_1 (.I0(\busy_sr_reg_n_0_[25] ), .I1(p_0_in), .O(\busy_sr[26]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT2 #( .INIT(4'h8)) \busy_sr[27]_i_1 (.I0(\busy_sr_reg_n_0_[26] ), .I1(p_0_in), .O(\busy_sr[27]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT2 #( .INIT(4'h8)) \busy_sr[28]_i_1 (.I0(\busy_sr_reg_n_0_[27] ), .I1(p_0_in), .O(\busy_sr[28]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT2 #( .INIT(4'h8)) \busy_sr[29]_i_1 (.I0(\busy_sr_reg_n_0_[28] ), .I1(p_0_in), .O(\busy_sr[29]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT2 #( .INIT(4'h8)) \busy_sr[2]_i_1 (.I0(\busy_sr_reg_n_0_[1] ), .I1(p_0_in), .O(\busy_sr[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT2 #( .INIT(4'h8)) \busy_sr[30]_i_1 (.I0(\busy_sr_reg_n_0_[29] ), .I1(p_0_in), .O(\busy_sr[30]_i_1_n_0 )); LUT6 #( .INIT(64'h22222222A2222222)) \busy_sr[31]_i_1 (.I0(p_1_in), .I1(\busy_sr_reg[1]_0 ), .I2(p_0_in), .I3(divider_reg__0[7]), .I4(divider_reg__0[6]), .I5(\busy_sr[0]_i_3_n_0 ), .O(\busy_sr[31]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT2 #( .INIT(4'h8)) \busy_sr[31]_i_2 (.I0(p_0_in), .I1(\busy_sr_reg_n_0_[30] ), .O(\busy_sr[31]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT2 #( .INIT(4'h8)) \busy_sr[3]_i_1 (.I0(\busy_sr_reg_n_0_[2] ), .I1(p_0_in), .O(\busy_sr[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT2 #( .INIT(4'h8)) \busy_sr[4]_i_1 (.I0(\busy_sr_reg_n_0_[3] ), .I1(p_0_in), .O(\busy_sr[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT2 #( .INIT(4'h8)) \busy_sr[5]_i_1 (.I0(\busy_sr_reg_n_0_[4] ), .I1(p_0_in), .O(\busy_sr[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT2 #( .INIT(4'h8)) \busy_sr[6]_i_1 (.I0(\busy_sr_reg_n_0_[5] ), .I1(p_0_in), .O(\busy_sr[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT2 #( .INIT(4'h8)) \busy_sr[7]_i_1 (.I0(\busy_sr_reg_n_0_[6] ), .I1(p_0_in), .O(\busy_sr[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT2 #( .INIT(4'h8)) \busy_sr[8]_i_1 (.I0(\busy_sr_reg_n_0_[7] ), .I1(p_0_in), .O(\busy_sr[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT2 #( .INIT(4'h8)) \busy_sr[9]_i_1 (.I0(\busy_sr_reg_n_0_[8] ), .I1(p_0_in), .O(\busy_sr[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \busy_sr_reg[0] (.C(clk), .CE(busy_sr0), .D(p_1_in), .Q(\busy_sr_reg_n_0_[0] ), .R(1'b0)); FDSE #( .INIT(1'b0)) \busy_sr_reg[10] (.C(clk), .CE(busy_sr0), .D(\busy_sr[10]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[10] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[11] (.C(clk), .CE(busy_sr0), .D(\busy_sr[11]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[11] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[12] (.C(clk), .CE(busy_sr0), .D(\busy_sr[12]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[12] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[13] (.C(clk), .CE(busy_sr0), .D(\busy_sr[13]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[13] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[14] (.C(clk), .CE(busy_sr0), .D(\busy_sr[14]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[14] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[15] (.C(clk), .CE(busy_sr0), .D(\busy_sr[15]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[15] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[16] (.C(clk), .CE(busy_sr0), .D(\busy_sr[16]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[16] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[17] (.C(clk), .CE(busy_sr0), .D(\busy_sr[17]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[17] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[18] (.C(clk), .CE(busy_sr0), .D(\busy_sr[18]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[18] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[19] (.C(clk), .CE(busy_sr0), .D(\busy_sr[19]_i_1_n_0 ), .Q(p_1_in_0[0]), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[1] (.C(clk), .CE(busy_sr0), .D(\busy_sr[1]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[1] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[20] (.C(clk), .CE(busy_sr0), .D(\busy_sr[20]_i_1_n_0 ), .Q(p_1_in_0[1]), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[21] (.C(clk), .CE(busy_sr0), .D(\busy_sr[21]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[21] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[22] (.C(clk), .CE(busy_sr0), .D(\busy_sr[22]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[22] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[23] (.C(clk), .CE(busy_sr0), .D(\busy_sr[23]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[23] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[24] (.C(clk), .CE(busy_sr0), .D(\busy_sr[24]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[24] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[25] (.C(clk), .CE(busy_sr0), .D(\busy_sr[25]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[25] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[26] (.C(clk), .CE(busy_sr0), .D(\busy_sr[26]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[26] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[27] (.C(clk), .CE(busy_sr0), .D(\busy_sr[27]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[27] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[28] (.C(clk), .CE(busy_sr0), .D(\busy_sr[28]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[28] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[29] (.C(clk), .CE(busy_sr0), .D(\busy_sr[29]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[29] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[2] (.C(clk), .CE(busy_sr0), .D(\busy_sr[2]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[2] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[30] (.C(clk), .CE(busy_sr0), .D(\busy_sr[30]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[30] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[31] (.C(clk), .CE(busy_sr0), .D(\busy_sr[31]_i_2_n_0 ), .Q(p_0_in), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[3] (.C(clk), .CE(busy_sr0), .D(\busy_sr[3]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[3] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[4] (.C(clk), .CE(busy_sr0), .D(\busy_sr[4]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[4] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[5] (.C(clk), .CE(busy_sr0), .D(\busy_sr[5]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[5] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[6] (.C(clk), .CE(busy_sr0), .D(\busy_sr[6]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[6] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[7] (.C(clk), .CE(busy_sr0), .D(\busy_sr[7]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[7] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[8] (.C(clk), .CE(busy_sr0), .D(\busy_sr[8]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[8] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[9] (.C(clk), .CE(busy_sr0), .D(\busy_sr[9]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[9] ), .S(\busy_sr[31]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT3 #( .INIT(8'hB8)) \data_sr[10]_i_1 (.I0(\data_sr_reg_n_0_[9] ), .I1(p_0_in), .I2(DOADO[7]), .O(\data_sr[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT3 #( .INIT(8'hB8)) \data_sr[12]_i_1 (.I0(\data_sr_reg_n_0_[11] ), .I1(p_0_in), .I2(DOADO[8]), .O(\data_sr[12]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT3 #( .INIT(8'hB8)) \data_sr[13]_i_1 (.I0(\data_sr_reg_n_0_[12] ), .I1(p_0_in), .I2(DOADO[9]), .O(\data_sr[13]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT3 #( .INIT(8'hB8)) \data_sr[14]_i_1 (.I0(\data_sr_reg_n_0_[13] ), .I1(p_0_in), .I2(DOADO[10]), .O(\data_sr[14]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT3 #( .INIT(8'hB8)) \data_sr[15]_i_1 (.I0(\data_sr_reg_n_0_[14] ), .I1(p_0_in), .I2(DOADO[11]), .O(\data_sr[15]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT3 #( .INIT(8'hB8)) \data_sr[16]_i_1 (.I0(\data_sr_reg_n_0_[15] ), .I1(p_0_in), .I2(DOADO[12]), .O(\data_sr[16]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT3 #( .INIT(8'hB8)) \data_sr[17]_i_1 (.I0(\data_sr_reg_n_0_[16] ), .I1(p_0_in), .I2(DOADO[13]), .O(\data_sr[17]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT3 #( .INIT(8'hB8)) \data_sr[18]_i_1 (.I0(\data_sr_reg_n_0_[17] ), .I1(p_0_in), .I2(DOADO[14]), .O(\data_sr[18]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT3 #( .INIT(8'hB8)) \data_sr[19]_i_1 (.I0(\data_sr_reg_n_0_[18] ), .I1(p_0_in), .I2(DOADO[15]), .O(\data_sr[19]_i_1_n_0 )); LUT6 #( .INIT(64'hCFCFCFCFAACAAAAA)) \data_sr[22]_i_1 (.I0(\data_sr_reg_n_0_[22] ), .I1(\data_sr_reg_n_0_[21] ), .I2(p_0_in), .I3(\data_sr[31]_i_2_n_0 ), .I4(divider_reg__0[7]), .I5(\busy_sr_reg[31]_0 ), .O(\data_sr[22]_i_1_n_0 )); LUT6 #( .INIT(64'hCFCFCFCFAACAAAAA)) \data_sr[27]_i_1 (.I0(\data_sr_reg_n_0_[27] ), .I1(\data_sr_reg_n_0_[26] ), .I2(p_0_in), .I3(\data_sr[31]_i_2_n_0 ), .I4(divider_reg__0[7]), .I5(\busy_sr_reg[31]_0 ), .O(\data_sr[27]_i_1_n_0 )); LUT3 #( .INIT(8'h02)) \data_sr[30]_i_1 (.I0(p_1_in), .I1(\busy_sr_reg[1]_0 ), .I2(p_0_in), .O(\data_sr[30]_i_1_n_0 )); LUT6 #( .INIT(64'hCFCFCFCFAACAAAAA)) \data_sr[31]_i_1 (.I0(\data_sr_reg_n_0_[31] ), .I1(\data_sr_reg_n_0_[30] ), .I2(p_0_in), .I3(\data_sr[31]_i_2_n_0 ), .I4(divider_reg__0[7]), .I5(\busy_sr_reg[31]_0 ), .O(\data_sr[31]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT2 #( .INIT(4'hB)) \data_sr[31]_i_2 (.I0(\busy_sr[0]_i_3_n_0 ), .I1(divider_reg__0[6]), .O(\data_sr[31]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT3 #( .INIT(8'hB8)) \data_sr[3]_i_1 (.I0(\data_sr_reg_n_0_[2] ), .I1(p_0_in), .I2(DOADO[0]), .O(\data_sr[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT3 #( .INIT(8'hB8)) \data_sr[4]_i_1 (.I0(\data_sr_reg_n_0_[3] ), .I1(p_0_in), .I2(DOADO[1]), .O(\data_sr[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT3 #( .INIT(8'hB8)) \data_sr[5]_i_1 (.I0(\data_sr_reg_n_0_[4] ), .I1(p_0_in), .I2(DOADO[2]), .O(\data_sr[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT3 #( .INIT(8'hB8)) \data_sr[6]_i_1 (.I0(\data_sr_reg_n_0_[5] ), .I1(p_0_in), .I2(DOADO[3]), .O(\data_sr[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT3 #( .INIT(8'hB8)) \data_sr[7]_i_1 (.I0(\data_sr_reg_n_0_[6] ), .I1(p_0_in), .I2(DOADO[4]), .O(\data_sr[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT3 #( .INIT(8'hB8)) \data_sr[8]_i_1 (.I0(\data_sr_reg_n_0_[7] ), .I1(p_0_in), .I2(DOADO[5]), .O(\data_sr[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT3 #( .INIT(8'hB8)) \data_sr[9]_i_1 (.I0(\data_sr_reg_n_0_[8] ), .I1(p_0_in), .I2(DOADO[6]), .O(\data_sr[9]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[10] (.C(clk), .CE(busy_sr0), .D(\data_sr[10]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[11] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[10] ), .Q(\data_sr_reg_n_0_[11] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[12] (.C(clk), .CE(busy_sr0), .D(\data_sr[12]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[13] (.C(clk), .CE(busy_sr0), .D(\data_sr[13]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[14] (.C(clk), .CE(busy_sr0), .D(\data_sr[14]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[15] (.C(clk), .CE(busy_sr0), .D(\data_sr[15]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[15] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[16] (.C(clk), .CE(busy_sr0), .D(\data_sr[16]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[16] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[17] (.C(clk), .CE(busy_sr0), .D(\data_sr[17]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[17] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[18] (.C(clk), .CE(busy_sr0), .D(\data_sr[18]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[18] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[19] (.C(clk), .CE(busy_sr0), .D(\data_sr[19]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[19] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[1] (.C(clk), .CE(busy_sr0), .D(p_0_in), .Q(\data_sr_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[20] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[19] ), .Q(\data_sr_reg_n_0_[20] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[21] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[20] ), .Q(\data_sr_reg_n_0_[21] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[22] (.C(clk), .CE(1'b1), .D(\data_sr[22]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[22] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[23] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[22] ), .Q(\data_sr_reg_n_0_[23] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[24] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[23] ), .Q(\data_sr_reg_n_0_[24] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[25] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[24] ), .Q(\data_sr_reg_n_0_[25] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[26] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[25] ), .Q(\data_sr_reg_n_0_[26] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[27] (.C(clk), .CE(1'b1), .D(\data_sr[27]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[27] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[28] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[27] ), .Q(\data_sr_reg_n_0_[28] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[29] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[28] ), .Q(\data_sr_reg_n_0_[29] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[2] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[1] ), .Q(\data_sr_reg_n_0_[2] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[30] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[29] ), .Q(\data_sr_reg_n_0_[30] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[31] (.C(clk), .CE(1'b1), .D(\data_sr[31]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[31] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[3] (.C(clk), .CE(busy_sr0), .D(\data_sr[3]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[4] (.C(clk), .CE(busy_sr0), .D(\data_sr[4]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[5] (.C(clk), .CE(busy_sr0), .D(\data_sr[5]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[6] (.C(clk), .CE(busy_sr0), .D(\data_sr[6]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[7] (.C(clk), .CE(busy_sr0), .D(\data_sr[7]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[8] (.C(clk), .CE(busy_sr0), .D(\data_sr[8]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[9] (.C(clk), .CE(busy_sr0), .D(\data_sr[9]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[9] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT1 #( .INIT(2'h1)) \divider[0]_i_1 (.I0(divider_reg__1[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT2 #( .INIT(4'h6)) \divider[1]_i_1 (.I0(divider_reg__1[0]), .I1(divider_reg__1[1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT3 #( .INIT(8'h78)) \divider[2]_i_1 (.I0(divider_reg__1[1]), .I1(divider_reg__1[0]), .I2(divider_reg__1[2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT4 #( .INIT(16'h7F80)) \divider[3]_i_1 (.I0(divider_reg__1[2]), .I1(divider_reg__1[0]), .I2(divider_reg__1[1]), .I3(divider_reg__1[3]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT5 #( .INIT(32'h7FFF8000)) \divider[4]_i_1 (.I0(divider_reg__1[3]), .I1(divider_reg__1[1]), .I2(divider_reg__1[0]), .I3(divider_reg__1[2]), .I4(divider_reg__1[4]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \divider[5]_i_1 (.I0(divider_reg__1[4]), .I1(divider_reg__1[2]), .I2(divider_reg__1[0]), .I3(divider_reg__1[1]), .I4(divider_reg__1[3]), .I5(divider_reg__1[5]), .O(p_0_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT2 #( .INIT(4'h9)) \divider[6]_i_1 (.I0(\busy_sr[0]_i_3_n_0 ), .I1(divider_reg__0[6]), .O(p_0_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT3 #( .INIT(8'hD2)) \divider[7]_i_2 (.I0(divider_reg__0[6]), .I1(\busy_sr[0]_i_3_n_0 ), .I2(divider_reg__0[7]), .O(p_0_in__0[7])); FDRE #( .INIT(1'b1)) \divider_reg[0] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[0]), .Q(divider_reg__1[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[1] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[1]), .Q(divider_reg__1[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[2] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[2]), .Q(divider_reg__1[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[3] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[3]), .Q(divider_reg__1[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[4] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[4]), .Q(divider_reg__1[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[5] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[5]), .Q(divider_reg__1[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[6] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[6]), .Q(divider_reg__0[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[7] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[7]), .Q(divider_reg__0[7]), .R(1'b0)); LUT6 #( .INIT(64'hFCFCFFF8FFFFFFFF)) sioc_i_1 (.I0(\busy_sr_reg_n_0_[0] ), .I1(sioc_i_2_n_0), .I2(sioc_i_3_n_0), .I3(\busy_sr_reg_n_0_[1] ), .I4(sioc_i_4_n_0), .I5(p_0_in), .O(sioc_i_1_n_0)); LUT2 #( .INIT(4'h6)) sioc_i_2 (.I0(divider_reg__0[6]), .I1(divider_reg__0[7]), .O(sioc_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT4 #( .INIT(16'hA222)) sioc_i_3 (.I0(sioc_i_5_n_0), .I1(\busy_sr_reg_n_0_[30] ), .I2(divider_reg__0[6]), .I3(p_0_in), .O(sioc_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT4 #( .INIT(16'h7FFF)) sioc_i_4 (.I0(\busy_sr_reg_n_0_[29] ), .I1(\busy_sr_reg_n_0_[2] ), .I2(p_0_in), .I3(\busy_sr_reg_n_0_[30] ), .O(sioc_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT4 #( .INIT(16'h0001)) sioc_i_5 (.I0(\busy_sr_reg_n_0_[0] ), .I1(\busy_sr_reg_n_0_[1] ), .I2(\busy_sr_reg_n_0_[29] ), .I3(\busy_sr_reg_n_0_[2] ), .O(sioc_i_5_n_0)); FDRE sioc_reg (.C(clk), .CE(1'b1), .D(sioc_i_1_n_0), .Q(sioc), .R(1'b0)); LUT2 #( .INIT(4'h8)) siod_INST_0 (.I0(\data_sr_reg_n_0_[31] ), .I1(siod_INST_0_i_1_n_0), .O(siod)); LUT6 #( .INIT(64'hB0BBB0BB0000B0BB)) siod_INST_0_i_1 (.I0(\busy_sr_reg_n_0_[28] ), .I1(\busy_sr_reg_n_0_[29] ), .I2(p_1_in_0[0]), .I3(p_1_in_0[1]), .I4(\busy_sr_reg_n_0_[11] ), .I5(\busy_sr_reg_n_0_[10] ), .O(siod_INST_0_i_1_n_0)); FDRE taken_reg (.C(clk), .CE(1'b1), .D(\busy_sr_reg[31]_0 ), .Q(E), .R(1'b0)); endmodule (* ORIG_REF_NAME = "ov7670_controller" *) module system_ov7670_controller_0_0_ov7670_controller (config_finished, siod, xclk, sioc, resend, clk); output config_finished; output siod; output xclk; output sioc; input resend; input clk; wire Inst_i2c_sender_n_3; wire Inst_ov7670_registers_n_16; wire Inst_ov7670_registers_n_18; wire clk; wire config_finished; wire p_0_in; wire [0:0]p_1_in; wire resend; wire sioc; wire siod; wire [15:0]sreg_reg; wire sys_clk_i_1_n_0; wire taken; wire xclk; system_ov7670_controller_0_0_i2c_sender Inst_i2c_sender (.DOADO(sreg_reg), .E(taken), .\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3), .\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18), .\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16), .clk(clk), .p_0_in(p_0_in), .p_1_in(p_1_in), .sioc(sioc), .siod(siod)); system_ov7670_controller_0_0_ov7670_registers Inst_ov7670_registers (.DOADO(sreg_reg), .E(taken), .clk(clk), .config_finished(config_finished), .\divider_reg[2] (Inst_i2c_sender_n_3), .\divider_reg[7] (Inst_ov7670_registers_n_16), .p_0_in(p_0_in), .p_1_in(p_1_in), .resend(resend), .taken_reg(Inst_ov7670_registers_n_18)); LUT1 #( .INIT(2'h1)) sys_clk_i_1 (.I0(xclk), .O(sys_clk_i_1_n_0)); FDRE #( .INIT(1'b0)) sys_clk_reg (.C(clk), .CE(1'b1), .D(sys_clk_i_1_n_0), .Q(xclk), .R(1'b0)); endmodule (* ORIG_REF_NAME = "ov7670_registers" *) module system_ov7670_controller_0_0_ov7670_registers (DOADO, \divider_reg[7] , config_finished, taken_reg, p_1_in, clk, \divider_reg[2] , p_0_in, resend, E); output [15:0]DOADO; output [0:0]\divider_reg[7] ; output config_finished; output taken_reg; output [0:0]p_1_in; input clk; input \divider_reg[2] ; input p_0_in; input resend; input [0:0]E; wire [15:0]DOADO; wire [0:0]E; wire [7:0]address; wire [7:0]address_reg__0; wire \address_rep[0]_i_1_n_0 ; wire \address_rep[1]_i_1_n_0 ; wire \address_rep[2]_i_1_n_0 ; wire \address_rep[3]_i_1_n_0 ; wire \address_rep[4]_i_1_n_0 ; wire \address_rep[5]_i_1_n_0 ; wire \address_rep[6]_i_1_n_0 ; wire \address_rep[7]_i_1_n_0 ; wire \address_rep[7]_i_2_n_0 ; wire clk; wire config_finished; wire config_finished_INST_0_i_1_n_0; wire config_finished_INST_0_i_2_n_0; wire config_finished_INST_0_i_3_n_0; wire config_finished_INST_0_i_4_n_0; wire \divider_reg[2] ; wire [0:0]\divider_reg[7] ; wire p_0_in; wire [0:0]p_1_in; wire resend; wire taken_reg; wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED; wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED; wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED; (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[0] (.C(clk), .CE(E), .D(\address_rep[0]_i_1_n_0 ), .Q(address_reg__0[0]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[1] (.C(clk), .CE(E), .D(\address_rep[1]_i_1_n_0 ), .Q(address_reg__0[1]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[2] (.C(clk), .CE(E), .D(\address_rep[2]_i_1_n_0 ), .Q(address_reg__0[2]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[3] (.C(clk), .CE(E), .D(\address_rep[3]_i_1_n_0 ), .Q(address_reg__0[3]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[4] (.C(clk), .CE(E), .D(\address_rep[4]_i_1_n_0 ), .Q(address_reg__0[4]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[5] (.C(clk), .CE(E), .D(\address_rep[5]_i_1_n_0 ), .Q(address_reg__0[5]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[6] (.C(clk), .CE(E), .D(\address_rep[6]_i_1_n_0 ), .Q(address_reg__0[6]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[7] (.C(clk), .CE(E), .D(\address_rep[7]_i_1_n_0 ), .Q(address_reg__0[7]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[0] (.C(clk), .CE(E), .D(\address_rep[0]_i_1_n_0 ), .Q(address[0]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[1] (.C(clk), .CE(E), .D(\address_rep[1]_i_1_n_0 ), .Q(address[1]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[2] (.C(clk), .CE(E), .D(\address_rep[2]_i_1_n_0 ), .Q(address[2]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[3] (.C(clk), .CE(E), .D(\address_rep[3]_i_1_n_0 ), .Q(address[3]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[4] (.C(clk), .CE(E), .D(\address_rep[4]_i_1_n_0 ), .Q(address[4]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[5] (.C(clk), .CE(E), .D(\address_rep[5]_i_1_n_0 ), .Q(address[5]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[6] (.C(clk), .CE(E), .D(\address_rep[6]_i_1_n_0 ), .Q(address[6]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[7] (.C(clk), .CE(E), .D(\address_rep[7]_i_1_n_0 ), .Q(address[7]), .R(resend)); LUT1 #( .INIT(2'h1)) \address_rep[0]_i_1 (.I0(address_reg__0[0]), .O(\address_rep[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT2 #( .INIT(4'h6)) \address_rep[1]_i_1 (.I0(address_reg__0[0]), .I1(address_reg__0[1]), .O(\address_rep[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT3 #( .INIT(8'h78)) \address_rep[2]_i_1 (.I0(address_reg__0[1]), .I1(address_reg__0[0]), .I2(address_reg__0[2]), .O(\address_rep[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT4 #( .INIT(16'h7F80)) \address_rep[3]_i_1 (.I0(address_reg__0[2]), .I1(address_reg__0[0]), .I2(address_reg__0[1]), .I3(address_reg__0[3]), .O(\address_rep[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT5 #( .INIT(32'h7FFF8000)) \address_rep[4]_i_1 (.I0(address_reg__0[3]), .I1(address_reg__0[1]), .I2(address_reg__0[0]), .I3(address_reg__0[2]), .I4(address_reg__0[4]), .O(\address_rep[4]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \address_rep[5]_i_1 (.I0(address_reg__0[4]), .I1(address_reg__0[2]), .I2(address_reg__0[0]), .I3(address_reg__0[1]), .I4(address_reg__0[3]), .I5(address_reg__0[5]), .O(\address_rep[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT2 #( .INIT(4'h9)) \address_rep[6]_i_1 (.I0(\address_rep[7]_i_2_n_0 ), .I1(address_reg__0[6]), .O(\address_rep[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT3 #( .INIT(8'hD2)) \address_rep[7]_i_1 (.I0(address_reg__0[6]), .I1(\address_rep[7]_i_2_n_0 ), .I2(address_reg__0[7]), .O(\address_rep[7]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \address_rep[7]_i_2 (.I0(address_reg__0[4]), .I1(address_reg__0[2]), .I2(address_reg__0[0]), .I3(address_reg__0[1]), .I4(address_reg__0[3]), .I5(address_reg__0[5]), .O(\address_rep[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT5 #( .INIT(32'h0000FFFE)) \busy_sr[0]_i_2 (.I0(config_finished_INST_0_i_4_n_0), .I1(config_finished_INST_0_i_3_n_0), .I2(config_finished_INST_0_i_2_n_0), .I3(config_finished_INST_0_i_1_n_0), .I4(p_0_in), .O(p_1_in)); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT4 #( .INIT(16'h0001)) config_finished_INST_0 (.I0(config_finished_INST_0_i_1_n_0), .I1(config_finished_INST_0_i_2_n_0), .I2(config_finished_INST_0_i_3_n_0), .I3(config_finished_INST_0_i_4_n_0), .O(config_finished)); LUT4 #( .INIT(16'h7FFF)) config_finished_INST_0_i_1 (.I0(DOADO[5]), .I1(DOADO[4]), .I2(DOADO[7]), .I3(DOADO[6]), .O(config_finished_INST_0_i_1_n_0)); LUT4 #( .INIT(16'h7FFF)) config_finished_INST_0_i_2 (.I0(DOADO[1]), .I1(DOADO[0]), .I2(DOADO[3]), .I3(DOADO[2]), .O(config_finished_INST_0_i_2_n_0)); LUT4 #( .INIT(16'h7FFF)) config_finished_INST_0_i_3 (.I0(DOADO[13]), .I1(DOADO[12]), .I2(DOADO[15]), .I3(DOADO[14]), .O(config_finished_INST_0_i_3_n_0)); LUT4 #( .INIT(16'h7FFF)) config_finished_INST_0_i_4 (.I0(DOADO[9]), .I1(DOADO[8]), .I2(DOADO[11]), .I3(DOADO[10]), .O(config_finished_INST_0_i_4_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFE0000)) \divider[7]_i_1 (.I0(config_finished_INST_0_i_1_n_0), .I1(config_finished_INST_0_i_2_n_0), .I2(config_finished_INST_0_i_3_n_0), .I3(config_finished_INST_0_i_4_n_0), .I4(\divider_reg[2] ), .I5(p_0_in), .O(\divider_reg[7] )); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "4096" *) (* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *) (* bram_addr_begin = "0" *) (* bram_addr_end = "1023" *) (* bram_slice_begin = "0" *) (* bram_slice_end = "15" *) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280), .INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440), .INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907), .INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100), .INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(18'h00000), .INIT_B(18'h00000), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(18), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(18), .WRITE_WIDTH_B(0)) sreg_reg (.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}), .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .CLKARDCLK(clk), .CLKBWRCLK(1'b0), .DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .DIPADIP({1'b0,1'b0}), .DIPBDIP({1'b1,1'b1}), .DOADO(DOADO), .DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]), .DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]), .DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]), .ENARDEN(1'b1), .ENBWREN(1'b0), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({1'b0,1'b0}), .WEBWE({1'b0,1'b0,1'b0,1'b0})); LUT6 #( .INIT(64'h0000000055555554)) taken_i_1 (.I0(p_0_in), .I1(config_finished_INST_0_i_1_n_0), .I2(config_finished_INST_0_i_2_n_0), .I3(config_finished_INST_0_i_3_n_0), .I4(config_finished_INST_0_i_4_n_0), .I5(\divider_reg[2] ), .O(taken_reg)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif

module fifo_tb(); // Declarations/*{{{*/ // Slave side reg s_aclk; reg s_aresetn; reg s_axis_tvalid; wire s_axis_tready; reg [63:0] s_axis_tdata; reg [7:0] s_axis_tkeep; reg s_axis_tlast; // Master side reg m_aclk; wire m_aresetn; wire m_axis_tvalid; reg m_axis_tready; wire [63:0] m_axis_tdata; wire [7:0] m_axis_tkeep; wire m_axis_tlast; wire axis_overflow; wire axis_underflow; /*}}}*/ // FIFO module/*{{{*/ FIFO F0 ( .m_aclk(m_aclk), // input m_aclk .s_aclk(s_aclk), // input s_aclk .s_aresetn(s_aresetn), // input s_aresetn .s_axis_tvalid(s_axis_tvalid), // input s_axis_tvalid .s_axis_tready(s_axis_tready), // output s_axis_tready .s_axis_tdata(s_axis_tdata), // input [63 : 0] s_axis_tdata .s_axis_tkeep(s_axis_tkeep), // input [7 : 0] s_axis_tkeep .s_axis_tlast(s_axis_tlast), // input s_axis_tlast .m_axis_tvalid(m_axis_tvalid), // output m_axis_tvalid .m_axis_tready(m_axis_tready), // input m_axis_tready .m_axis_tdata(m_axis_tdata), // output [63 : 0] m_axis_tdata .m_axis_tkeep(m_axis_tkeep), // output [7 : 0] m_axis_tkeep .m_axis_tlast(m_axis_tlast), // output m_axis_tlast .axis_overflow(axis_overflow), // output axis_overflow .axis_underflow(axis_underflow) // output axis_underflow ); /*}}}*/ // This is to ensure we simulate our reads from the slave end of the FIFO only // when there is valid data to be read from the queue to avoid underflows. always @(m_axis_tvalid) begin m_axis_tready <= m_axis_tvalid; end // Testbench initialization/*{{{*/ initial begin s_aclk <= 1'b0; m_aclk <= 1'b0; s_aresetn <= 1'b0; s_axis_tvalid <= 1'b0; m_axis_tready <= 1'b0; s_axis_tdata <= 64'b0; s_axis_tkeep <= 8'b0; s_axis_tlast <= 1'b0; end /*}}}*/ // Master domain clock initial begin forever begin #10 s_aclk <= ~s_aclk; end end // Slave domain clock initial begin forever begin #5 m_aclk <= ~m_aclk; end end // Test bench stimuli/*{{{*/ initial begin #10 s_aresetn <= 1'b1; // Slave will be ready 3 s_aclk ticks after reset // Test writing a single data slice to the slave specifying valid bytes with tkeep #60 s_axis_tvalid <= 1'b1; // Wait until slave is ready to avoid overflow s_axis_tdata <= 64'hFFFFFFFFFFFFFFFF; s_axis_tkeep <= 8'hCF; s_axis_tlast <= 1'b1; #20 s_axis_tvalid <= 1'b0; // Keep the valid signal asserted for at least 1 clock s_axis_tdata <= 64'b0; s_axis_tkeep <= 8'b0; s_axis_tlast <= 1'b0; // Test writing multiple data slices to the slave specifying valid bytes with tkeep and last slice with tlast #20 s_axis_tvalid <= 1'b1; // Wait until slave is ready to avoid overflow s_axis_tdata <= 64'h1111111111111111; s_axis_tkeep <= 8'hFF; #20 s_axis_tdata <= 64'h2222222222222222; s_axis_tkeep <= 8'hFF; #20 s_axis_tdata <= 64'h3333333333333333; s_axis_tkeep <= 8'hFF; #20 s_axis_tdata <= 64'h4444444444444444; s_axis_tkeep <= 8'hFF; s_axis_tlast <= 1'b1; #20 s_axis_tvalid <= 1'b0; s_axis_tdata <= 64'b0; s_axis_tkeep <= 8'b0; s_axis_tlast <= 1'b0; end /*}}}*/ endmodule

`timescale 1ns / 1ps /* Group Members: Kevin Ingram and Warren Seto Lab Name: Traffic Light Controller (Lab 3) Project Name: eng312_proj3 Design Name: Traffic_Test_D_eng312_proj3.v Design Description: Verilog Test Bench to Implement Test D (11 AM) */ module Traffic_Test; // Inputs reg NS_VEHICLE_DETECT; reg EW_VEHICLE_DETECT; // Outputs wire NS_RED; wire NS_YELLOW; wire NS_GREEN; wire EW_RED; wire EW_YELLOW; wire EW_GREEN; // Clock reg clk; // Counters wire[4:0] count1; wire[3:0] count2; wire[1:0] count3; // Counter Modules nsCounter clock1(clk, count1); // Count a total of 32 seconds ewCounter clock2(clk, count2); // Counts a total of 16 seconds yellowCounter clock3(clk, count3); // Counts a total of 4 seconds // Main Traffic Module Traffic CORE (count1, count2, count3, NS_VEHICLE_DETECT, EW_VEHICLE_DETECT, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN); initial begin clk = 0; NS_VEHICLE_DETECT = 0; EW_VEHICLE_DETECT = 1; $display(" NS | EW "); $display(" (Time) | R Y G R Y G "); $monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN); #1000 $finish; end always begin #1 clk = ~clk; end always @ (clk) begin if ($time % 6 == 0) begin NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT; end if ($time % 15 == 0) begin EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT; end end endmodule

// Code generated by Icestudio 0.8.1w202112300112 `default_nettype none //---- Top entity module main #( parameter v771499 = "v771499.list" ) ( input vclk, output [3:0] v894180, output [0:0] vinit ); localparam p0 = v771499; wire [0:7] w1; wire [0:3] w2; wire [0:7] w3; wire w4; assign v894180 = w2; assign w4 = vclk; v6809d2 #( .v9298ae(p0) ) v60d27e ( .v6d8c97(w1), .vc4e0ba(w3), .v6dda25(w4) ); vda0861 vf2b781 ( .vffb58f(w1) ); v6bdcd9 v78e5a8 ( .v2cc41f(w2), .vcc8c7c(w3) ); assign vinit = 1'b0; endmodule //---- Top entity module v6809d2 #( parameter v9298ae = "v9298ae.list" ) ( input v6dda25, input [7:0] v6d8c97, output [7:0] vc4e0ba ); localparam p3 = v9298ae; wire w0; wire w1; wire w2; wire w4; wire w5; wire w6; wire w7; wire [0:7] w8; wire [0:7] w9; wire w10; wire [0:31] w11; wire [0:31] w12; wire [0:31] w13; wire [0:31] w14; wire [0:31] w15; wire [0:3] w16; wire w17; wire w18; wire w19; assign w4 = v6dda25; assign w5 = v6dda25; assign w6 = v6dda25; assign w7 = v6dda25; assign vc4e0ba = w8; assign w9 = v6d8c97; assign w1 = w0; assign w5 = w4; assign w6 = w4; assign w6 = w5; assign w7 = w4; assign w7 = w5; assign w7 = w6; assign w12 = w11; vf1cffe v468719 ( .ve9ba68(w0), .v79476f(w1), .v6dda25(w4), .v27dec4(w10), .v9231ba(w11), .vfc9252(w13), .va0e119(w14), .ve17e80(w16) ); vd30ca9 v16f275 ( .v9fb85f(w0) ); v893ac6 #( .vba98fe(p3) ) vc59f55 ( .v6dda25(w5), .v5d7e06(w11), .v9a5b8a(w15) ); ve4c3a8 v29c9ed ( .v5c832d(w12), .v4642b6(w17), .vd02149(w18), .vafdfa0(w19) ); vf68661 v66eb94 ( .v6dda25(w7), .vfeb41a(w8), .vf837fe(w13), .ve9e5a1(w16), .ve146f6(w19) ); v145d1e v3f3e01 ( .vc74a9c(w9), .vb76294(w14), .vb79ed5(w15), .v6287a6(w17), .v19f646(w18) ); v04e061 vb15d38 ( .v4642b6(w2), .vd6bebe(w6) ); v3676a0 vd1c5e9 ( .v0e28cb(w2), .vcbab45(w10) ); endmodule //--------------------------------------------------- //-- Generic-comp-clk //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Generic component with clk input //--------------------------------------------------- //---- Top entity module vf1cffe ( input v6dda25, input v27dec4, input [31:0] va0e119, input v79476f, input ve9ba68, output [31:0] v9231ba, output [31:0] vfc9252, output [3:0] ve17e80, output v8d2eee ); wire w0; wire [0:31] w1; wire w2; wire w3; wire [0:31] w4; wire [0:31] w5; wire [0:3] w6; wire w7; wire w8; assign w0 = v27dec4; assign w1 = va0e119; assign w2 = v79476f; assign w3 = ve9ba68; assign v9231ba = w4; assign vfc9252 = w5; assign ve17e80 = w6; assign v8d2eee = w7; assign w8 = v6dda25; vf1cffe_v172245 v172245 ( .reset(w0), .mem_rdata(w1), .mem_rbusy(w2), .mem_wbusy(w3), .mem_addr(w4), .mem_wdata(w5), .mem_wmask(w6), .mem_rstrb(w7), .clk(w8) ); endmodule //--------------------------------------------------- //-- RV32I //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- RV32I //--------------------------------------------------- module vf1cffe_v172245 ( input clk, input reset, input [31:0] mem_rdata, input mem_rbusy, input mem_wbusy, output [31:0] mem_addr, output [31:0] mem_wdata, output [3:0] mem_wmask, output mem_rstrb ); localparam RESET_ADDR = 0; parameter ADDR_WIDTH = 24; localparam ADDR_PAD = {(32-ADDR_WIDTH){1'b0}}; // 32-bits padding for addrs /***************************************************************************/ // Instruction decoding. /***************************************************************************/ // Extracts rd,rs1,rs2,funct3,imm and opcode from instruction. // Reference: Table page 104 of: // https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf // The destination register wire [4:0] rdId = instr[11:7]; // The ALU function, decoded in 1-hot form (doing so reduces LUT count) // It is used as follows: funct3Is[val] <=> funct3 == val (* onehot *) wire [7:0] funct3Is = 8'b00000001 << instr[14:12]; // The five immediate formats, see RiscV reference (link above), Fig. 2.4 p. 12 wire [31:0] Uimm = { instr[31], instr[30:12], {12{1'b0}}}; wire [31:0] Iimm = {{21{instr[31]}}, instr[30:20]}; /* verilator lint_off UNUSED */ // MSBs of SBJimms are not used by addr adder. wire [31:0] Simm = {{21{instr[31]}}, instr[30:25],instr[11:7]}; wire [31:0] Bimm = {{20{instr[31]}}, instr[7],instr[30:25],instr[11:8],1'b0}; wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12],instr[20],instr[30:21],1'b0}; /* verilator lint_on UNUSED */ // Base RISC-V (RV32I) has only 10 different instructions ! wire isLoad = (instr[6:2] == 5'b00000); // rd <- mem[rs1+Iimm] wire isALUimm = (instr[6:2] == 5'b00100); // rd <- rs1 OP Iimm wire isAUIPC = (instr[6:2] == 5'b00101); // rd <- PC + Uimm wire isStore = (instr[6:2] == 5'b01000); // mem[rs1+Simm] <- rs2 wire isALUreg = (instr[6:2] == 5'b01100); // rd <- rs1 OP rs2 wire isLUI = (instr[6:2] == 5'b01101); // rd <- Uimm wire isBranch = (instr[6:2] == 5'b11000); // if(rs1 OP rs2) PC<-PC+Bimm wire isJALR = (instr[6:2] == 5'b11001); // rd <- PC+4; PC<-rs1+Iimm wire isJAL = (instr[6:2] == 5'b11011); // rd <- PC+4; PC<-PC+Jimm wire isSYSTEM = (instr[6:2] == 5'b11100); // rd <- cycles wire isALU = isALUimm | isALUreg; /***************************************************************************/ // The register file. /***************************************************************************/ reg [31:0] rs1; reg [31:0] rs2; reg [31:0] registerFile [31:0]; always @(posedge clk) begin if (writeBack) if (rdId != 0) registerFile[rdId] <= writeBackData; end /***************************************************************************/ // The ALU. Does operations and tests combinatorially, except shifts. /***************************************************************************/ // First ALU source, always rs1 wire [31:0] aluIn1 = rs1; // Second ALU source, depends on opcode: // ALUreg, Branch: rs2 // ALUimm, Load, JALR: Iimm wire [31:0] aluIn2 = isALUreg | isBranch ? rs2 : Iimm; reg [31:0] aluReg; // The internal register of the ALU, used by shift. reg [4:0] aluShamt; // Current shift amount. wire aluBusy = |aluShamt; // ALU is busy if shift amount is non-zero. wire aluWr; // ALU write strobe, starts shifting. // The adder is used by both arithmetic instructions and JALR. wire [31:0] aluPlus = aluIn1 + aluIn2; // Use a single 33 bits subtract to do subtraction and all comparisons // (trick borrowed from swapforth/J1) wire [32:0] aluMinus = {1'b1, ~aluIn2} + {1'b0,aluIn1} + 33'b1; wire LT = (aluIn1[31] ^ aluIn2[31]) ? aluIn1[31] : aluMinus[32]; wire LTU = aluMinus[32]; wire EQ = (aluMinus[31:0] == 0); // Notes: // - instr[30] is 1 for SUB and 0 for ADD // - for SUB, need to test also instr[5] to discriminate ADDI: // (1 for ADD/SUB, 0 for ADDI, and Iimm used by ADDI overlaps bit 30 !) // - instr[30] is 1 for SRA (do sign extension) and 0 for SRL wire [31:0] aluOut = (funct3Is[0] ? instr[30] & instr[5] ? aluMinus[31:0] : aluPlus : 32'b0) | (funct3Is[2] ? {31'b0, LT} : 32'b0) | (funct3Is[3] ? {31'b0, LTU} : 32'b0) | (funct3Is[4] ? aluIn1 ^ aluIn2 : 32'b0) | (funct3Is[6] ? aluIn1 | aluIn2 : 32'b0) | (funct3Is[7] ? aluIn1 & aluIn2 : 32'b0) | (funct3IsShift ? aluReg : 32'b0) ; wire funct3IsShift = funct3Is[1] | funct3Is[5]; always @(posedge clk) begin if(aluWr) begin if (funct3IsShift) begin // SLL, SRA, SRL aluReg <= aluIn1; aluShamt <= aluIn2[4:0]; end end // Compact form of: // funct3=001 -> SLL (aluReg <= aluReg << 1) // funct3=101 & instr[30] -> SRA (aluReg <= {aluReg[31], aluReg[31:1]}) // funct3=101 & !instr[30] -> SRL (aluReg <= {1'b0, aluReg[31:1]}) if (|aluShamt) begin aluShamt <= aluShamt - 1; aluReg <= funct3Is[1] ? aluReg << 1 : // SLL {instr[30] & aluReg[31], aluReg[31:1]}; // SRA,SRL end end /***************************************************************************/ // The predicate for conditional branches. /***************************************************************************/ wire predicate = funct3Is[0] & EQ | // BEQ funct3Is[1] & !EQ | // BNE funct3Is[4] & LT | // BLT funct3Is[5] & !LT | // BGE funct3Is[6] & LTU | // BLTU funct3Is[7] & !LTU ; // BGEU /***************************************************************************/ // Program counter and branch target computation. /***************************************************************************/ reg [ADDR_WIDTH-1:0] PC; // The program counter. reg [31:2] instr; // Latched instruction. Note that bits 0 and 1 are // ignored (not used in RV32I base instr set). wire [ADDR_WIDTH-1:0] PCplus4 = PC + 4; // An adder used to compute branch address, JAL address and AUIPC. // branch->PC+Bimm AUIPC->PC+Uimm JAL->PC+Jimm // Equivalent to PCplusImm = PC + (isJAL ? Jimm : isAUIPC ? Uimm : Bimm) wire [ADDR_WIDTH-1:0] PCplusImm = PC + ( instr[3] ? Jimm[ADDR_WIDTH-1:0] : instr[4] ? Uimm[ADDR_WIDTH-1:0] : Bimm[ADDR_WIDTH-1:0] ); // A separate adder to compute the destination of load/store. // testing instr[5] is equivalent to testing isStore in this context. wire [ADDR_WIDTH-1:0] loadstore_addr = rs1[ADDR_WIDTH-1:0] + (instr[5] ? Simm[ADDR_WIDTH-1:0] : Iimm[ADDR_WIDTH-1:0]); assign mem_addr = {ADDR_PAD, state[WAIT_INSTR_bit] | state[FETCH_INSTR_bit] ? PC : loadstore_addr }; /***************************************************************************/ // The value written back to the register file. /***************************************************************************/ wire [31:0] writeBackData = /* verilator lint_off WIDTH */ (isSYSTEM ? cycles : 32'b0) | // SYSTEM /* verilator lint_on WIDTH */ (isLUI ? Uimm : 32'b0) | // LUI (isALU ? aluOut : 32'b0) | // ALUreg, ALUimm (isAUIPC ? {ADDR_PAD,PCplusImm} : 32'b0) | // AUIPC (isJALR | isJAL ? {ADDR_PAD,PCplus4 } : 32'b0) | // JAL, JALR (isLoad ? LOAD_data : 32'b0); // Load /***************************************************************************/ // LOAD/STORE /***************************************************************************/ // All memory accesses are aligned on 32 bits boundary. For this // reason, we need some circuitry that does unaligned halfword // and byte load/store, based on: // - funct3[1:0]: 00->byte 01->halfword 10->word // - mem_addr[1:0]: indicates which byte/halfword is accessed wire mem_byteAccess = instr[13:12] == 2'b00; // funct3[1:0] == 2'b00; wire mem_halfwordAccess = instr[13:12] == 2'b01; // funct3[1:0] == 2'b01; // LOAD, in addition to funct3[1:0], LOAD depends on: // - funct3[2] (instr[14]): 0->do sign expansion 1->no sign expansion wire LOAD_sign = !instr[14] & (mem_byteAccess ? LOAD_byte[7] : LOAD_halfword[15]); wire [31:0] LOAD_data = mem_byteAccess ? {{24{LOAD_sign}}, LOAD_byte} : mem_halfwordAccess ? {{16{LOAD_sign}}, LOAD_halfword} : mem_rdata ; wire [15:0] LOAD_halfword = loadstore_addr[1] ? mem_rdata[31:16] : mem_rdata[15:0]; wire [7:0] LOAD_byte = loadstore_addr[0] ? LOAD_halfword[15:8] : LOAD_halfword[7:0]; // STORE assign mem_wdata[ 7: 0] = rs2[7:0]; assign mem_wdata[15: 8] = loadstore_addr[0] ? rs2[7:0] : rs2[15: 8]; assign mem_wdata[23:16] = loadstore_addr[1] ? rs2[7:0] : rs2[23:16]; assign mem_wdata[31:24] = loadstore_addr[0] ? rs2[7:0] : loadstore_addr[1] ? rs2[15:8] : rs2[31:24]; // The memory write mask: // 1111 if writing a word // 0011 or 1100 if writing a halfword // (depending on loadstore_addr[1]) // 0001, 0010, 0100 or 1000 if writing a byte // (depending on loadstore_addr[1:0]) wire [3:0] STORE_wmask = mem_byteAccess ? (loadstore_addr[1] ? (loadstore_addr[0] ? 4'b1000 : 4'b0100) : (loadstore_addr[0] ? 4'b0010 : 4'b0001) ) : mem_halfwordAccess ? (loadstore_addr[1] ? 4'b1100 : 4'b0011) : 4'b1111; /*************************************************************************/ // And, last but not least, the state machine. /*************************************************************************/ localparam FETCH_INSTR_bit = 0; localparam WAIT_INSTR_bit = 1; localparam EXECUTE_bit = 2; localparam WAIT_ALU_OR_MEM_bit = 3; localparam NB_STATES = 4; localparam FETCH_INSTR = 1 << FETCH_INSTR_bit; localparam WAIT_INSTR = 1 << WAIT_INSTR_bit; localparam EXECUTE = 1 << EXECUTE_bit; localparam WAIT_ALU_OR_MEM = 1 << WAIT_ALU_OR_MEM_bit; (* onehot *) reg [NB_STATES-1:0] state; // The signals (internal and external) that are determined // combinatorially from state and other signals. // register write-back enable. wire writeBack = ~(isBranch | isStore ) & (state[EXECUTE_bit] | state[WAIT_ALU_OR_MEM_bit]); // The memory-read signal. assign mem_rstrb = state[EXECUTE_bit] & isLoad | state[FETCH_INSTR_bit]; // The mask for memory-write. assign mem_wmask = {4{state[EXECUTE_bit] & isStore}} & STORE_wmask; // aluWr starts computation (shifts) in the ALU. assign aluWr = state[EXECUTE_bit] & isALU; wire jumpToPCplusImm = isJAL | (isBranch & predicate); `ifdef NRV_IS_IO_ADDR wire needToWait = isLoad | isStore & `NRV_IS_IO_ADDR(mem_addr) | isALU & funct3IsShift; `else wire needToWait = isLoad | isStore | isALU & funct3IsShift; `endif always @(posedge clk) begin if(!reset) begin state <= WAIT_ALU_OR_MEM; // Just waiting for !mem_wbusy PC <= RESET_ADDR[ADDR_WIDTH-1:0]; end else // See note [1] at the end of this file. (* parallel_case *) case(1'b1) state[WAIT_INSTR_bit]: begin if(!mem_rbusy) begin // may be high when executing from SPI flash rs1 <= registerFile[mem_rdata[19:15]]; rs2 <= registerFile[mem_rdata[24:20]]; instr <= mem_rdata[31:2]; // Bits 0 and 1 are ignored (see state <= EXECUTE; // also the declaration of instr). end end state[EXECUTE_bit]: begin PC <= isJALR ? {aluPlus[ADDR_WIDTH-1:1],1'b0} : jumpToPCplusImm ? PCplusImm : PCplus4; state <= needToWait ? WAIT_ALU_OR_MEM : FETCH_INSTR; end state[WAIT_ALU_OR_MEM_bit]: begin if(!aluBusy & !mem_rbusy & !mem_wbusy) state <= FETCH_INSTR; end default: begin // FETCH_INSTR state <= WAIT_INSTR; end endcase end /***************************************************************************/ // Cycle counter /***************************************************************************/ `ifdef NRV_COUNTER_WIDTH reg [`NRV_COUNTER_WIDTH-1:0] cycles; `else reg [31:0] cycles; `endif always @(posedge clk) cycles <= cycles + 1; `ifdef BENCH initial begin cycles = 0; aluShamt = 0; registerFile[0] = 0; end `endif /*****************************************************************************/ // Notes: // // [1] About the "reverse case" statement, also used in Claire Wolf's picorv32: // It is just a cleaner way of writing a series of cascaded if() statements, // To understand it, think about the case statement *in general* as follows: // case (expr) // val_1: statement_1 // val_2: statement_2 // ... val_n: statement_n // endcase // The first statement_i such that expr == val_i is executed. // Now if expr is 1'b1: // case (1'b1) // cond_1: statement_1 // cond_2: statement_2 // ... cond_n: statement_n // endcase // It is *exactly the same thing*, the first statement_i such that // expr == cond_i is executed (that is, such that 1'b1 == cond_i, // in other words, such that cond_i is true) // More on this: // https://stackoverflow.com/questions/15418636/case-statement-in-verilog // // [2] state uses 1-hot encoding (at any time, state has only one bit set to 1). // It uses a larger number of bits (one bit per state), but often results in // a both more compact (fewer LUTs) and faster state machine. endmodule //---- Top entity module vd30ca9 ( output v9fb85f ); wire w0; assign v9fb85f = w0; vd30ca9_vb2eccd vb2eccd ( .q(w0) ); endmodule //--------------------------------------------------- //-- bit-0 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Constant bit 0 //--------------------------------------------------- module vd30ca9_vb2eccd ( output q ); //-- Constant bit-0 assign q = 1'b0; endmodule //---- Top entity module v893ac6 #( parameter vba98fe = "vba98fe.list" ) ( input v6dda25, input [31:0] v5d7e06, output [31:0] v9a5b8a ); localparam p6 = vba98fe; wire w0; wire [0:31] w1; wire w2; wire [0:31] w3; wire [0:9] w4; wire [0:31] w5; wire w7; wire [0:31] w8; wire [0:31] w9; assign w7 = v6dda25; assign v9a5b8a = w8; assign w9 = v5d7e06; vd30ca9 vc98086 ( .v9fb85f(w0) ); vd30ca9 v30628d ( .v9fb85f(w2) ); v2c97f6 v773b48 ( .v7c9bd8(w3) ); v675d07 #( .v5a4ee6(p6) ) vdbacf7 ( .v23dc54(w2), .v6f4b70(w3), .vb261ad(w4), .v922e3d(w7), .vddff9f(w8) ); v794b6d va8ea8d ( .vef1612(w4), .ve841af(w5) ); vaaf5c4 ve8e400 ( .v712289(w0), .v51eedb(w1), .v4f6beb(w9) ); vaaf5c4 v677471 ( .v4f6beb(w1), .v51eedb(w5) ); endmodule //--------------------------------------------------- //-- Generic-comp-clk //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Generic component with clk input //--------------------------------------------------- //---- Top entity module v2c97f6 #( parameter vfffc23 = 0 ) ( output [31:0] v7c9bd8 ); localparam p0 = vfffc23; wire [0:31] w1; assign v7c9bd8 = w1; v959751 #( .vc5c8ea(p0) ) v9f49e7 ( .vbc97e4(w1) ); endmodule //--------------------------------------------------- //-- 32bits-Value_0 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- 32bits constant value: 0 //--------------------------------------------------- //---- Top entity module v959751 #( parameter vc5c8ea = 0 ) ( output [31:0] vbc97e4 ); localparam p0 = vc5c8ea; wire [0:31] w1; assign vbc97e4 = w1; v959751_v465065 #( .VALUE(p0) ) v465065 ( .k(w1) ); endmodule //--------------------------------------------------- //-- 32-bits-gen-constant //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Generic: 32-bits generic constant //--------------------------------------------------- module v959751_v465065 #( parameter VALUE = 0 ) ( output [31:0] k ); assign k = VALUE; endmodule //---- Top entity module v675d07 #( parameter v5a4ee6 = "v5a4ee6.list" ) ( input v922e3d, input [9:0] vb261ad, input [31:0] v6f4b70, input v23dc54, output [31:0] vddff9f ); localparam p2 = v5a4ee6; wire w0; wire w1; wire [0:9] w3; wire [0:31] w4; wire [0:31] w5; assign w0 = v922e3d; assign w1 = v23dc54; assign w3 = vb261ad; assign vddff9f = w4; assign w5 = v6f4b70; v675d07_vbaa912 #( .ROMF(p2) ) vbaa912 ( .clk(w0), .wr(w1), .addr(w3), .data_out(w4), .data_in(w5) ); endmodule //--------------------------------------------------- //-- Memory-1Kx32 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Smem 1kx32: Synchronous memory: 1024 words of 32 bits //--------------------------------------------------- module v675d07_vbaa912 #( parameter ROMF = 0 ) ( input clk, input [9:0] addr, input [31:0] data_in, input wr, output [31:0] data_out ); //-- Address with localparam ADDR_WIDTH = 10; //-- Data with localparam DATA_WIDTH = 32; //-- Size of the memory localparam SIZE = 1 << ADDR_WIDTH; //-- Memory itself reg [DATA_WIDTH-1:0] mem[0:SIZE-1]; //-- The data_out is a registered output (not a wire) reg data_out; //-- Reading port: Synchronous always @(posedge clk) begin data_out <= mem[addr]; end //-- Writing port: Synchronous always @(posedge clk) begin if (wr) mem[addr] <= data_in; end //-- Init the memory initial begin if (ROMF) $readmemh(ROMF, mem, 0, SIZE-1); end endmodule //---- Top entity module v794b6d ( input [31:0] ve841af, output [21:0] v51fb1f, output [9:0] vef1612 ); wire [0:31] w0; wire [0:9] w1; wire [0:21] w2; assign w0 = ve841af; assign vef1612 = w1; assign v51fb1f = w2; v794b6d_v9a2a06 v9a2a06 ( .i(w0), .o0(w1), .o1(w2) ); endmodule //--------------------------------------------------- //-- Bus32-Split-22-10 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus32-Split-22-10: Split the 32-bits bus into two buses of 22 and 10 wires //--------------------------------------------------- module v794b6d_v9a2a06 ( input [31:0] i, output [21:0] o1, output [9:0] o0 ); assign o1 = i[31:10]; assign o0 = i[9:0]; endmodule //---- Top entity module vaaf5c4 ( input v712289, input [31:0] v4f6beb, output [31:0] v51eedb, output v7e4f0f ); wire [0:31] w0; wire w1; wire w2; wire [0:30] w3; wire [0:31] w4; assign w0 = v4f6beb; assign v7e4f0f = w1; assign w2 = v712289; assign v51eedb = w4; vecd30a vd4273f ( .ve841af(w0), .v8d1a42(w1), .v11ef80(w3) ); v51b3c0 v9b7810 ( .v411a12(w2), .vd40455(w3), .v7d0a31(w4) ); endmodule //--------------------------------------------------- //-- SR1-32bits //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- SR1-32bits: Shift a 32-bit value one bit right. MSB is filled with the input in //--------------------------------------------------- //---- Top entity module vecd30a ( input [31:0] ve841af, output [30:0] v11ef80, output v8d1a42 ); wire [0:31] w0; wire w1; wire [0:30] w2; assign w0 = ve841af; assign v8d1a42 = w1; assign v11ef80 = w2; vecd30a_v9a2a06 v9a2a06 ( .i(w0), .o0(w1), .o1(w2) ); endmodule //--------------------------------------------------- //-- Bus32-Split-31-1 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus32-Split-31-1: Split the 32-bits bus into two buses of 31 and 1 wires //--------------------------------------------------- module vecd30a_v9a2a06 ( input [31:0] i, output [30:0] o1, output o0 ); assign o1 = i[31:1]; assign o0 = i[0]; endmodule //---- Top entity module v51b3c0 ( input v411a12, input [30:0] vd40455, output [31:0] v7d0a31 ); wire [0:31] w0; wire [0:30] w1; wire w2; assign v7d0a31 = w0; assign w1 = vd40455; assign w2 = v411a12; v51b3c0_v9a2a06 v9a2a06 ( .o(w0), .i0(w1), .i1(w2) ); endmodule //--------------------------------------------------- //-- Bus32-Join-1-31 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus32-Join-1-31: Join the two buses into an 32-bits Bus //--------------------------------------------------- module v51b3c0_v9a2a06 ( input i1, input [30:0] i0, output [31:0] o ); assign o = {i1, i0}; endmodule //---- Top entity module ve4c3a8 #( parameter v389bd1 = 5'h1F ) ( input [31:0] v5c832d, output v4642b6, output vafdfa0, output vd02149 ); localparam p8 = v389bd1; wire w0; wire w1; wire w2; wire [0:14] w3; wire [0:4] w4; wire [0:4] w5; wire [0:4] w6; wire [0:4] w7; wire [0:2] w9; wire [0:31] w10; wire [0:31] w11; wire w12; wire w13; wire w14; wire w15; wire w16; assign w10 = v5c832d; assign w11 = v5c832d; assign v4642b6 = w12; assign vafdfa0 = w13; assign vd02149 = w14; assign w2 = w1; assign w6 = w4; assign w11 = w10; assign w16 = w15; v3676a0 v8f98d9 ( .vcbab45(w0), .v0e28cb(w1) ); vba518e v72db53 ( .v0e28cb(w0), .vcbab45(w13), .v3ca442(w16) ); vba518e v97a3cf ( .v3ca442(w2), .vcbab45(w14), .v0e28cb(w15) ); v9a2795 v666bdb ( .vda577d(w1), .vdee7c7(w9) ); va7b832 ve316c5 ( .v29a212(w3), .ve841af(w10) ); vef0f91 v3ffece ( .vcbe66f(w3), .vfa86aa(w4) ); v1cc648 v736214 ( .vfad888(w4), .vd80e4f(w5), .v4642b6(w12) ); v108a6d v2a89b0 ( .v6ece80(w5) ); v1cc648 v01ba64 ( .vd80e4f(w6), .vfad888(w7), .v4642b6(w15) ); v3693fc #( .vc5c8ea(p8) ) v006a39 ( .vc8d3b9(w7) ); ve500df vfe8608 ( .vbb2522(w9), .ve841af(w11) ); endmodule //--------------------------------------------------- //-- Generic-comp //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Componente genérico //--------------------------------------------------- //---- Top entity module v3676a0 ( input v0e28cb, output vcbab45 ); wire w0; wire w1; assign w0 = v0e28cb; assign vcbab45 = w1; v3676a0_vd54ca1 vd54ca1 ( .a(w0), .q(w1) ); endmodule //--------------------------------------------------- //-- NOT //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- NOT gate (Verilog implementation) //--------------------------------------------------- module v3676a0_vd54ca1 ( input a, output q ); //-- NOT Gate assign q = ~a; endmodule //---- Top entity module vba518e ( input v0e28cb, input v3ca442, output vcbab45 ); wire w0; wire w1; wire w2; assign w0 = v0e28cb; assign w1 = v3ca442; assign vcbab45 = w2; vba518e_vf4938a vf4938a ( .a(w0), .b(w1), .c(w2) ); endmodule //--------------------------------------------------- //-- AND2 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Two bits input And gate //--------------------------------------------------- module vba518e_vf4938a ( input a, input b, output c ); //-- AND gate //-- Verilog implementation assign c = a & b; endmodule //---- Top entity module v9a2795 ( input [2:0] vdee7c7, output vda577d, output v3f8943, output v64d863 ); wire w0; wire w1; wire [0:2] w2; wire w3; assign v3f8943 = w0; assign v64d863 = w1; assign w2 = vdee7c7; assign vda577d = w3; v9a2795_v9a2a06 v9a2a06 ( .o1(w0), .o0(w1), .i(w2), .o2(w3) ); endmodule //--------------------------------------------------- //-- Bus3-Split-all //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus3-Split-all: Split the 3-bits bus into three wires //--------------------------------------------------- module v9a2795_v9a2a06 ( input [2:0] i, output o2, output o1, output o0 ); assign o2 = i[2]; assign o1 = i[1]; assign o0 = i[0]; endmodule //---- Top entity module va7b832 ( input [31:0] ve841af, output [16:0] v62a8c1, output [14:0] v29a212 ); wire [0:31] w0; wire [0:14] w1; wire [0:16] w2; assign w0 = ve841af; assign v29a212 = w1; assign v62a8c1 = w2; va7b832_v9a2a06 v9a2a06 ( .i(w0), .o0(w1), .o1(w2) ); endmodule //--------------------------------------------------- //-- Bus32-Split-17-15 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus32-Split-17-15: Split the 32-bits bus into two buses of 17 and 15 wires //--------------------------------------------------- module va7b832_v9a2a06 ( input [31:0] i, output [16:0] o1, output [14:0] o0 ); assign o1 = i[31:15]; assign o0 = i[14:0]; endmodule //---- Top entity module vef0f91 ( input [14:0] vcbe66f, output [4:0] vfa86aa, output [9:0] vbdb2c8 ); wire [0:14] w0; wire [0:9] w1; wire [0:4] w2; assign w0 = vcbe66f; assign vbdb2c8 = w1; assign vfa86aa = w2; vef0f91_v9a2a06 v9a2a06 ( .i(w0), .o0(w1), .o1(w2) ); endmodule //--------------------------------------------------- //-- Bus15-Split-7-8 CLONE //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus15-Split-7-8: Split the 15-bits bus into two buses of 7 and 8 bits //--------------------------------------------------- module vef0f91_v9a2a06 ( input [14:0] i, output [4:0] o1, output [9:0] o0 ); assign o1 = i[14:10]; assign o0 = i[9:0]; endmodule //---- Top entity module v1cc648 ( input [4:0] vd80e4f, input [4:0] vfad888, output v4642b6 ); wire w0; wire [0:4] w1; wire [0:4] w2; wire w3; wire w4; wire w5; wire [0:3] w6; wire w7; wire [0:3] w8; assign v4642b6 = w0; assign w1 = vfad888; assign w2 = vd80e4f; v23b15b vc1b29d ( .v4642b6(w3), .v27dec4(w5), .v6848e9(w7) ); v91f34c vf38386 ( .v427dd1(w1), .v53baa6(w7), .v479af4(w8) ); v91f34c v83c3c9 ( .v427dd1(w2), .v53baa6(w5), .v479af4(w6) ); v438230 v577a36 ( .v4642b6(w4), .v693354(w6), .v5369cd(w8) ); vba518e v707c6e ( .vcbab45(w0), .v0e28cb(w3), .v3ca442(w4) ); endmodule //--------------------------------------------------- //-- comp2-5bits //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Comp2-5bit: Comparator of two 5-bit numbers //--------------------------------------------------- //---- Top entity module v23b15b ( input v27dec4, input v6848e9, output v4642b6 ); wire w0; wire w1; wire w2; wire w3; assign w1 = v27dec4; assign v4642b6 = w2; assign w3 = v6848e9; vd12401 v955b2b ( .vcbab45(w0), .v0e28cb(w1), .v3ca442(w3) ); v3676a0 vf92936 ( .v0e28cb(w0), .vcbab45(w2) ); endmodule //--------------------------------------------------- //-- comp2-1bit //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Comp2-1bit: Comparator of two 1-bit numbers //--------------------------------------------------- //---- Top entity module vd12401 ( input v0e28cb, input v3ca442, output vcbab45 ); wire w0; wire w1; wire w2; assign w0 = v0e28cb; assign w1 = v3ca442; assign vcbab45 = w2; vd12401_vf4938a vf4938a ( .a(w0), .b(w1), .c(w2) ); endmodule //--------------------------------------------------- //-- XOR2 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- XOR gate: two bits input xor gate //--------------------------------------------------- module vd12401_vf4938a ( input a, input b, output c ); //-- XOR gate //-- Verilog implementation assign c = a ^ b; endmodule //---- Top entity module v91f34c ( input [4:0] v427dd1, output v53baa6, output [3:0] v479af4 ); wire [0:3] w0; wire [0:4] w1; wire w2; assign v479af4 = w0; assign w1 = v427dd1; assign v53baa6 = w2; v91f34c_v9a2a06 v9a2a06 ( .o0(w0), .i(w1), .o1(w2) ); endmodule //--------------------------------------------------- //-- Bus5-Split-1-4 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus5-Split-1-4: Split the 5-bits bus into two buses of 1 and 4 bits //--------------------------------------------------- module v91f34c_v9a2a06 ( input [4:0] i, output o1, output [3:0] o0 ); assign o1 = i[4]; assign o0 = i[3:0]; endmodule //---- Top entity module v438230 ( input [3:0] v693354, input [3:0] v5369cd, output v4642b6 ); wire w0; wire [0:3] w1; wire [0:3] w2; wire w3; wire w4; wire w5; wire w6; wire w7; wire w8; wire w9; wire w10; wire w11; wire w12; wire w13; wire w14; assign v4642b6 = w0; assign w1 = v693354; assign w2 = v5369cd; v23b15b v09a5a5 ( .v4642b6(w3), .v27dec4(w12), .v6848e9(w14) ); v23b15b vc1b29d ( .v4642b6(w4), .v27dec4(w11), .v6848e9(w13) ); v23b15b vcd27ce ( .v4642b6(w5), .v27dec4(w9), .v6848e9(w10) ); vc4f23a vea9c80 ( .v985fcb(w1), .v4f1fd3(w7), .vda577d(w9), .v3f8943(w11), .v64d863(w12) ); vc4f23a va7dcdc ( .v985fcb(w2), .v4f1fd3(w8), .vda577d(w10), .v3f8943(w13), .v64d863(w14) ); v23b15b va0849c ( .v4642b6(w6), .v27dec4(w7), .v6848e9(w8) ); veffd42 v6e3e65 ( .vcbab45(w0), .v3ca442(w3), .v0e28cb(w4), .v033bf6(w5), .v9eb652(w6) ); endmodule //--------------------------------------------------- //-- comp2-4bits //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Comp2-4bit: Comparator of two 4-bit numbers //--------------------------------------------------- //---- Top entity module vc4f23a ( input [3:0] v985fcb, output v4f1fd3, output vda577d, output v3f8943, output v64d863 ); wire w0; wire w1; wire w2; wire w3; wire [0:3] w4; assign v3f8943 = w0; assign v64d863 = w1; assign vda577d = w2; assign v4f1fd3 = w3; assign w4 = v985fcb; vc4f23a_v9a2a06 v9a2a06 ( .o1(w0), .o0(w1), .o2(w2), .o3(w3), .i(w4) ); endmodule //--------------------------------------------------- //-- Bus4-Split-all //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus4-Split-all: Split the 4-bits bus into its wires //--------------------------------------------------- module vc4f23a_v9a2a06 ( input [3:0] i, output o3, output o2, output o1, output o0 ); assign o3 = i[3]; assign o2 = i[2]; assign o1 = i[1]; assign o0 = i[0]; endmodule //---- Top entity module veffd42 ( input v9eb652, input v033bf6, input v0e28cb, input v3ca442, output vcbab45 ); wire w0; wire w1; wire w2; wire w3; wire w4; wire w5; wire w6; assign w0 = v3ca442; assign w1 = v9eb652; assign w2 = v033bf6; assign w3 = v0e28cb; assign vcbab45 = w4; vba518e vf3ef0f ( .v3ca442(w0), .v0e28cb(w3), .vcbab45(w6) ); vba518e vdcc53d ( .v0e28cb(w1), .v3ca442(w2), .vcbab45(w5) ); vba518e v17ac22 ( .vcbab45(w4), .v0e28cb(w5), .v3ca442(w6) ); endmodule //--------------------------------------------------- //-- AND4 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Three bits input And gate //--------------------------------------------------- //---- Top entity module v108a6d #( parameter vfffc23 = 0 ) ( output [4:0] v6ece80 ); localparam p0 = vfffc23; wire [0:4] w1; assign v6ece80 = w1; v3693fc #( .vc5c8ea(p0) ) ve88537 ( .vc8d3b9(w1) ); endmodule //--------------------------------------------------- //-- 5bits-Value_0 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- 5bits constant value: 0 //--------------------------------------------------- //---- Top entity module v3693fc #( parameter vc5c8ea = 0 ) ( output [4:0] vc8d3b9 ); localparam p0 = vc5c8ea; wire [0:4] w1; assign vc8d3b9 = w1; v3693fc_v465065 #( .VALUE(p0) ) v465065 ( .k(w1) ); endmodule //--------------------------------------------------- //-- 5-bits-gen-constant //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Generic: 5-bits generic constant (0-31) //--------------------------------------------------- module v3693fc_v465065 #( parameter VALUE = 0 ) ( output [4:0] k ); assign k = VALUE; endmodule //---- Top entity module ve500df ( input [31:0] ve841af, output [28:0] vfc82fb, output [2:0] vbb2522 ); wire [0:31] w0; wire [0:2] w1; wire [0:28] w2; assign w0 = ve841af; assign vbb2522 = w1; assign vfc82fb = w2; ve500df_v9a2a06 v9a2a06 ( .i(w0), .o0(w1), .o1(w2) ); endmodule //--------------------------------------------------- //-- Bus32-Split-29-3 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus32-Split-29-3: Split the 29-bits bus into two buses of 29 and 3 wires //--------------------------------------------------- module ve500df_v9a2a06 ( input [31:0] i, output [28:0] o1, output [2:0] o0 ); assign o1 = i[31:3]; assign o0 = i[2:0]; endmodule //---- Top entity module vf68661 ( input v6dda25, input [31:0] vf837fe, input [3:0] ve9e5a1, input ve146f6, output [7:0] vfeb41a ); wire w0; wire [0:7] w1; wire w2; wire [0:7] w3; wire w4; wire [0:31] w5; wire [0:3] w6; wire w7; assign vfeb41a = w3; assign w4 = v6dda25; assign w5 = vf837fe; assign w6 = ve9e5a1; assign w7 = ve146f6; vf61fa3 v8cf02b ( .vcbab45(w0), .vaf45b8(w6) ); vba518e v7c2c65 ( .v0e28cb(w0), .vcbab45(w2), .v3ca442(w7) ); v468a05 v4dcb81 ( .vc6471a(w1), .ve841af(w5) ); v857d2e v415624 ( .vec26ff(w1), .vccca56(w2), .v19a59f(w3), .v6dda25(w4) ); endmodule //--------------------------------------------------- //-- Generic-comp-clk //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Generic component with clk input //--------------------------------------------------- //---- Top entity module vf61fa3 ( input [3:0] vaf45b8, output vcbab45 ); wire w0; wire [0:3] w1; wire w2; wire w3; wire w4; wire w5; assign vcbab45 = w0; assign w1 = vaf45b8; vc4f23a v5f4674 ( .v985fcb(w1), .v4f1fd3(w2), .vda577d(w3), .v3f8943(w4), .v64d863(w5) ); vf49321 vea932e ( .vcbab45(w0), .ve86251(w2), .v0e28cb(w3), .v3ca442(w4), .v8b2684(w5) ); endmodule //--------------------------------------------------- //-- OR-BUS4 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- OR-BUS4: OR gate with 4-bits bus input //--------------------------------------------------- //---- Top entity module vf49321 ( input ve86251, input v0e28cb, input v3ca442, input v8b2684, output vcbab45 ); wire w0; wire w1; wire w2; wire w3; wire w4; wire w5; wire w6; assign w0 = ve86251; assign w1 = v0e28cb; assign w3 = v3ca442; assign vcbab45 = w5; assign w6 = v8b2684; v873425 v1edc96 ( .v0e28cb(w0), .v3ca442(w1), .vcbab45(w2) ); v873425 v5591ec ( .v0e28cb(w2), .v3ca442(w3), .vcbab45(w4) ); v873425 vdba9a4 ( .v0e28cb(w4), .vcbab45(w5), .v3ca442(w6) ); endmodule //--------------------------------------------------- //-- OR4 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- OR4: Four bits input OR gate //--------------------------------------------------- //---- Top entity module v873425 ( input v0e28cb, input v3ca442, output vcbab45 ); wire w0; wire w1; wire w2; assign w0 = v0e28cb; assign w1 = v3ca442; assign vcbab45 = w2; v873425_vf4938a vf4938a ( .a(w0), .b(w1), .c(w2) ); endmodule //--------------------------------------------------- //-- OR2 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- OR2: Two bits input OR gate //--------------------------------------------------- module v873425_vf4938a ( input a, input b, output c ); //-- OR Gate //-- Verilog implementation assign c = a | b; endmodule //---- Top entity module v468a05 ( input [31:0] ve841af, output [7:0] vdd0469, output [7:0] v4ba85d, output [7:0] vf93ecb, output [7:0] vc6471a ); wire [0:31] w0; wire [0:7] w1; wire [0:7] w2; wire [0:7] w3; wire [0:7] w4; assign w0 = ve841af; assign vc6471a = w1; assign vf93ecb = w2; assign v4ba85d = w3; assign vdd0469 = w4; v468a05_v9a2a06 v9a2a06 ( .i(w0), .o0(w1), .o1(w2), .o2(w3), .o3(w4) ); endmodule //--------------------------------------------------- //-- Bus32-Split-quarter //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus32-Split-quarter: Split the 32-bits bus into four buses of 8 wires //--------------------------------------------------- module v468a05_v9a2a06 ( input [31:0] i, output [7:0] o3, output [7:0] o2, output [7:0] o1, output [7:0] o0 ); assign o3 = i[32:24]; assign o2 = i[23:16]; assign o1 = i[15:8]; assign o0 = i[7:0]; endmodule //---- Top entity module v857d2e ( input v6dda25, input [7:0] vec26ff, input vccca56, output [7:0] v19a59f ); wire [0:7] w0; wire [0:7] w1; wire [0:3] w2; wire [0:3] w3; wire [0:3] w4; wire [0:3] w5; wire w6; wire w7; wire w8; wire w9; assign w0 = vec26ff; assign v19a59f = w1; assign w6 = v6dda25; assign w7 = v6dda25; assign w8 = vccca56; assign w9 = vccca56; assign w7 = w6; assign w9 = w8; v6bdcd9 v8e04d7 ( .vcc8c7c(w0), .v651522(w2), .v2cc41f(w4) ); vafb28f vdbcc53 ( .va9ac17(w1), .v515fe7(w3), .v3c88fc(w5) ); v370cd6 v732df5 ( .v2856c0(w2), .v7891f9(w3), .v6dda25(w6), .vccca56(w8) ); v370cd6 v21c6af ( .v2856c0(w4), .v7891f9(w5), .v6dda25(w7), .vccca56(w9) ); endmodule //--------------------------------------------------- //-- Reg-x08 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Reg-x08: 8-bits register //--------------------------------------------------- //---- Top entity module v6bdcd9 ( input [7:0] vcc8c7c, output [3:0] v651522, output [3:0] v2cc41f ); wire [0:3] w0; wire [0:3] w1; wire [0:7] w2; assign v651522 = w0; assign v2cc41f = w1; assign w2 = vcc8c7c; v6bdcd9_v9a2a06 v9a2a06 ( .o1(w0), .o0(w1), .i(w2) ); endmodule //--------------------------------------------------- //-- Bus8-Split-half //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus8-Split-half: Split the 8-bits bus into two buses of the same size //--------------------------------------------------- module v6bdcd9_v9a2a06 ( input [7:0] i, output [3:0] o1, output [3:0] o0 ); assign o1 = i[7:4]; assign o0 = i[3:0]; endmodule //---- Top entity module vafb28f ( input [3:0] v515fe7, input [3:0] v3c88fc, output [7:0] va9ac17 ); wire [0:7] w0; wire [0:3] w1; wire [0:3] w2; assign va9ac17 = w0; assign w1 = v515fe7; assign w2 = v3c88fc; vafb28f_v9a2a06 v9a2a06 ( .o(w0), .i1(w1), .i0(w2) ); endmodule //--------------------------------------------------- //-- Bus8-Join-half //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus8-Join-half: Join the two same halves into an 8-bits Bus //--------------------------------------------------- module vafb28f_v9a2a06 ( input [3:0] i1, input [3:0] i0, output [7:0] o ); assign o = {i1, i0}; endmodule //---- Top entity module v370cd6 ( input v6dda25, input [3:0] v2856c0, input vccca56, output [3:0] v7891f9 ); wire w0; wire w1; wire w2; wire w3; wire w4; wire w5; wire [0:3] w6; wire [0:3] w7; wire w8; wire w9; wire w10; wire w11; wire w12; wire w13; wire w14; wire w15; wire w16; wire w17; assign w6 = v2856c0; assign v7891f9 = w7; assign w10 = v6dda25; assign w11 = v6dda25; assign w12 = v6dda25; assign w13 = v6dda25; assign w14 = vccca56; assign w15 = vccca56; assign w16 = vccca56; assign w17 = vccca56; assign w11 = w10; assign w12 = w10; assign w12 = w11; assign w13 = w10; assign w13 = w11; assign w13 = w12; assign w15 = w14; assign w16 = w14; assign w16 = w15; assign w17 = w14; assign w17 = w15; assign w17 = w16; v22cb98 v1ba30c ( .v27dec4(w0), .v4642b6(w2), .ve4a668(w12), .vd793aa(w16) ); v22cb98 v38f79d ( .v27dec4(w1), .v4642b6(w3), .ve4a668(w13), .vd793aa(w17) ); v22cb98 v009467 ( .v27dec4(w4), .v4642b6(w5), .ve4a668(w11), .vd793aa(w15) ); vc4f23a vf2e2c0 ( .v3f8943(w0), .v64d863(w1), .vda577d(w4), .v985fcb(w6), .v4f1fd3(w8) ); v84f0a1 v947047 ( .vee8a83(w2), .v03aaf0(w3), .vf8041d(w5), .v11bca5(w7), .vd84a57(w9) ); v22cb98 v3a0f4c ( .v27dec4(w8), .v4642b6(w9), .ve4a668(w10), .vd793aa(w14) ); endmodule //--------------------------------------------------- //-- Reg-x04 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Reg-x04: 4-bits register //--------------------------------------------------- //---- Top entity module v22cb98 #( parameter v5462c0 = 0 ) ( input ve4a668, input v27dec4, input vd793aa, output v4642b6 ); localparam p1 = v5462c0; wire w0; wire w2; wire w3; wire w4; wire w5; wire w6; assign w2 = ve4a668; assign w3 = v27dec4; assign v4642b6 = w5; assign w6 = vd793aa; assign w5 = w4; va40d2f v9ff767 ( .v030ad0(w0), .vb192d0(w3), .v27dec4(w4), .v2d3366(w6) ); v053dc2 #( .v71e305(p1) ) v89c757 ( .vf54559(w0), .va4102a(w2), .ve8318d(w4) ); endmodule //--------------------------------------------------- //-- 1-bit-reg //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Reg: 1-Bit register //--------------------------------------------------- //---- Top entity module va40d2f ( input v27dec4, input vb192d0, input v2d3366, output v030ad0 ); wire w0; wire w1; wire w2; wire w3; assign v030ad0 = w0; assign w1 = v2d3366; assign w2 = v27dec4; assign w3 = vb192d0; vd0c4e5 v0f3fef ( .v030ad0(w0), .v2d3366(w1), .vb192d0(w2), .v27dec4(w3) ); endmodule //--------------------------------------------------- //-- MuxF-2-1 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- 2-to-1 Multplexer (1-bit channels). Fippled version //--------------------------------------------------- //---- Top entity module vd0c4e5 ( input v27dec4, input vb192d0, input v2d3366, output v030ad0 ); wire w0; wire w1; wire w2; wire w3; wire w4; wire w5; wire w6; wire w7; assign v030ad0 = w0; assign w2 = v2d3366; assign w3 = v2d3366; assign w6 = v27dec4; assign w7 = vb192d0; assign w3 = w2; v873425 vaaee1f ( .vcbab45(w0), .v0e28cb(w1), .v3ca442(w4) ); vba518e v569873 ( .vcbab45(w1), .v3ca442(w2), .v0e28cb(w6) ); v3676a0 v1f00ae ( .v0e28cb(w3), .vcbab45(w5) ); vba518e vc8527f ( .vcbab45(w4), .v3ca442(w5), .v0e28cb(w7) ); endmodule //--------------------------------------------------- //-- Mux-2-1 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- 2-to-1 Multplexer (1-bit channels) //--------------------------------------------------- //---- Top entity module v053dc2 #( parameter v71e305 = 0 ) ( input va4102a, input vf54559, output ve8318d ); localparam p2 = v71e305; wire w0; wire w1; wire w3; assign w0 = va4102a; assign ve8318d = w1; assign w3 = vf54559; v053dc2_vb8adf8 #( .INI(p2) ) vb8adf8 ( .clk(w0), .q(w1), .d(w3) ); endmodule //--------------------------------------------------- //-- DFF //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- D Flip-flop (verilog implementation) //--------------------------------------------------- module v053dc2_vb8adf8 #( parameter INI = 0 ) ( input clk, input d, output q ); //-- Initial value reg q = INI; //-- Capture the input data //-- on the rising edge of //-- the system clock always @(posedge clk) q <= d; endmodule //---- Top entity module v84f0a1 ( input vd84a57, input vf8041d, input vee8a83, input v03aaf0, output [3:0] v11bca5 ); wire w0; wire w1; wire w2; wire w3; wire [0:3] w4; assign w0 = vee8a83; assign w1 = v03aaf0; assign w2 = vf8041d; assign w3 = vd84a57; assign v11bca5 = w4; v84f0a1_v9a2a06 v9a2a06 ( .i1(w0), .i0(w1), .i2(w2), .i3(w3), .o(w4) ); endmodule //--------------------------------------------------- //-- Bus4-Join-all //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus4-Join-all: Join all the wires into a 4-bits Bus //--------------------------------------------------- module v84f0a1_v9a2a06 ( input i3, input i2, input i1, input i0, output [3:0] o ); assign o = {i3, i2, i1, i0}; endmodule //---- Top entity module v145d1e ( input [31:0] vb79ed5, input [7:0] vc74a9c, input v6287a6, input v19f646, output [31:0] vb76294 ); wire [0:31] w0; wire [0:31] w1; wire [0:7] w2; wire [0:7] w3; wire [0:7] w4; wire [0:31] w5; wire [0:31] w6; wire [0:31] w7; wire [0:7] w8; wire w9; wire w10; assign w6 = vb79ed5; assign vb76294 = w7; assign w8 = vc74a9c; assign w9 = v6287a6; assign w10 = v19f646; assign w3 = w2; assign w4 = w2; assign w4 = w3; v15006c v7f618a ( .v3d79e8(w0), .v53354a(w6), .vd99bd0(w7), .v2d3366(w9) ); v15006c vf576d8 ( .vd99bd0(w0), .v53354a(w1), .v3d79e8(w5), .v2d3366(w10) ); v78e0a3 v9e8b5c ( .v7d0a31(w1), .v6127ee(w2), .v12d067(w3), .vea9d11(w4), .v29bdec(w8) ); vda0861 vfb1ecd ( .vffb58f(w2) ); v2c97f6 v1dbb84 ( .v7c9bd8(w5) ); endmodule //--------------------------------------------------- //-- Generic-comp //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Componente genérico //--------------------------------------------------- //---- Top entity module v15006c ( input [31:0] v53354a, input [31:0] v3d79e8, input v2d3366, output [31:0] vd99bd0 ); wire [0:7] w0; wire [0:7] w1; wire [0:7] w2; wire [0:31] w3; wire [0:31] w4; wire [0:31] w5; wire [0:7] w6; wire [0:7] w7; wire [0:7] w8; wire w9; wire w10; wire w11; wire w12; wire [0:7] w13; wire [0:7] w14; wire [0:7] w15; wire [0:7] w16; wire [0:7] w17; wire [0:7] w18; assign vd99bd0 = w3; assign w4 = v3d79e8; assign w5 = v53354a; assign w9 = v2d3366; assign w10 = v2d3366; assign w11 = v2d3366; assign w12 = v2d3366; assign w10 = w9; assign w11 = w9; assign w11 = w10; assign w12 = w9; assign w12 = w10; assign w12 = w11; v1bbb5b v41cfb0 ( .v9d2a6a(w0), .v2d3366(w12), .v2a1cbe(w17), .v9d7ae8(w18) ); v1bbb5b vf7893e ( .v9d2a6a(w1), .v2d3366(w11), .v2a1cbe(w15), .v9d7ae8(w16) ); v1bbb5b v40a6d4 ( .v9d2a6a(w2), .v2d3366(w10), .v2a1cbe(w13), .v9d7ae8(w14) ); v78e0a3 v2e8dfc ( .v29bdec(w0), .vea9d11(w1), .v6127ee(w2), .v7d0a31(w3), .v12d067(w6) ); v468a05 v95e147 ( .ve841af(w5), .vdd0469(w7), .v4ba85d(w13), .vf93ecb(w15), .vc6471a(w17) ); v468a05 v44f594 ( .ve841af(w4), .vdd0469(w8), .v4ba85d(w14), .vf93ecb(w16), .vc6471a(w18) ); v1bbb5b v68fd67 ( .v9d2a6a(w6), .v2a1cbe(w7), .v9d7ae8(w8), .v2d3366(w9) ); endmodule //--------------------------------------------------- //-- 32-bits-Mux-2-1 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- 2-to-1 Multplexer (32-bit channels) //--------------------------------------------------- //---- Top entity module v1bbb5b ( input [7:0] v2a1cbe, input [7:0] v9d7ae8, input v2d3366, output [7:0] v9d2a6a ); wire [0:3] w0; wire [0:7] w1; wire [0:7] w2; wire [0:7] w3; wire [0:3] w4; wire [0:3] w5; wire [0:3] w6; wire [0:3] w7; wire w8; wire w9; wire [0:3] w10; assign v9d2a6a = w1; assign w2 = v2a1cbe; assign w3 = v9d7ae8; assign w8 = v2d3366; assign w9 = v2d3366; assign w9 = w8; v952eda v54aed2 ( .v6833fd(w0), .v54ac99(w7), .v2d3366(w9), .ve2616d(w10) ); vafb28f v117a88 ( .v3c88fc(w0), .va9ac17(w1), .v515fe7(w4) ); v6bdcd9 v9f32ae ( .vcc8c7c(w2), .v651522(w5), .v2cc41f(w7) ); v6bdcd9 v9881c7 ( .vcc8c7c(w3), .v651522(w6), .v2cc41f(w10) ); v952eda v34a43a ( .v6833fd(w4), .v54ac99(w5), .ve2616d(w6), .v2d3366(w8) ); endmodule //--------------------------------------------------- //-- 8-bits-Mux-2-1 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- 2-to-1 Multplexer (8-bit channels) //--------------------------------------------------- //---- Top entity module v952eda ( input [3:0] v54ac99, input [3:0] ve2616d, input v2d3366, output [3:0] v6833fd ); wire w0; wire w1; wire w2; wire [0:3] w3; wire w4; wire [0:3] w5; wire [0:3] w6; wire w7; wire w8; wire w9; wire w10; wire w11; wire w12; wire w13; wire w14; wire w15; wire w16; wire w17; wire w18; assign v6833fd = w3; assign w5 = ve2616d; assign w6 = v54ac99; assign w9 = v2d3366; assign w10 = v2d3366; assign w11 = v2d3366; assign w12 = v2d3366; assign w10 = w9; assign w11 = w9; assign w11 = w10; assign w12 = w9; assign w12 = w10; assign w12 = w11; vd0c4e5 v6d94c9 ( .v030ad0(w0), .v2d3366(w11), .v27dec4(w15), .vb192d0(w17) ); vd0c4e5 vebe465 ( .v030ad0(w1), .v2d3366(w12), .v27dec4(w16), .vb192d0(w18) ); vd0c4e5 ve1c21f ( .v030ad0(w2), .v2d3366(w10), .v27dec4(w13), .vb192d0(w14) ); v84f0a1 va44bdf ( .vee8a83(w0), .v03aaf0(w1), .vf8041d(w2), .v11bca5(w3), .vd84a57(w4) ); vd0c4e5 v2ebff3 ( .v030ad0(w4), .v27dec4(w7), .vb192d0(w8), .v2d3366(w9) ); vc4f23a v3c3a57 ( .v985fcb(w5), .v4f1fd3(w8), .vda577d(w14), .v3f8943(w17), .v64d863(w18) ); vc4f23a vd6d480 ( .v985fcb(w6), .v4f1fd3(w7), .vda577d(w13), .v3f8943(w15), .v64d863(w16) ); endmodule //--------------------------------------------------- //-- 4-bits-Mux-2-1 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- 2-to-1 Multplexer (4-bit channels) //--------------------------------------------------- //---- Top entity module v78e0a3 ( input [7:0] v12d067, input [7:0] v6127ee, input [7:0] vea9d11, input [7:0] v29bdec, output [31:0] v7d0a31 ); wire [0:31] w0; wire [0:7] w1; wire [0:7] w2; wire [0:7] w3; wire [0:7] w4; assign v7d0a31 = w0; assign w1 = v29bdec; assign w2 = vea9d11; assign w3 = v6127ee; assign w4 = v12d067; v78e0a3_v9a2a06 v9a2a06 ( .o(w0), .i0(w1), .i1(w2), .i2(w3), .i3(w4) ); endmodule //--------------------------------------------------- //-- Bus32-Join-quarter //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus32-Join-quarter: Join the four buses into an 32-bits Bus //--------------------------------------------------- module v78e0a3_v9a2a06 ( input [7:0] i3, input [7:0] i2, input [7:0] i1, input [7:0] i0, output [31:0] o ); assign o = {i3, i2, i1, i0}; endmodule //---- Top entity module vda0861 #( parameter vfffc23 = 0 ) ( output [7:0] vffb58f ); localparam p0 = vfffc23; wire [0:7] w1; assign vffb58f = w1; vffc517 #( .vc5c8ea(p0) ) v778577 ( .va0aeac(w1) ); endmodule //--------------------------------------------------- //-- 8bits-Value_0 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- 8bits constant value: 0 //--------------------------------------------------- //---- Top entity module vffc517 #( parameter vc5c8ea = 0 ) ( output [7:0] va0aeac ); localparam p0 = vc5c8ea; wire [0:7] w1; assign va0aeac = w1; vffc517_v465065 #( .VALUE(p0) ) v465065 ( .k(w1) ); endmodule //--------------------------------------------------- //-- 8-bits-gen-constant //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Generic: 8-bits generic constant (0-255) //--------------------------------------------------- module vffc517_v465065 #( parameter VALUE = 0 ) ( output [7:0] k ); assign k = VALUE; endmodule //---- Top entity module v04e061 #( parameter v001ed5 = 1 ) ( input vd6bebe, output v4642b6, output [4:0] vb385cd, output vd9f5b6 ); localparam p1 = v001ed5; wire w0; wire w2; wire w3; wire w4; wire w5; wire w6; wire w7; wire [0:4] w8; wire w9; wire w10; wire w11; wire [0:4] w12; assign v4642b6 = w2; assign vd9f5b6 = w6; assign vb385cd = w8; assign w9 = vd6bebe; assign w10 = vd6bebe; assign w4 = w2; assign w5 = w3; assign w10 = w9; assign w11 = w2; assign w11 = w4; v144728 #( .v573b2a(p1) ) v04fe70 ( .v27dec4(w0), .v4642b6(w2), .v92a149(w3), .v6dda25(w9) ); vd30ca9 v8af589 ( .v9fb85f(w0) ); vba518e ve66489 ( .v0e28cb(w5), .vcbab45(w6), .v3ca442(w11) ); vaf1249 ve31e7c ( .ve37344(w3), .ve556f1(w7), .v6dda25(w10), .va1c800(w12) ); vd30ca9 va31481 ( .v9fb85f(w7) ); v51353d vabd391 ( .v427380(w4), .v81cd93(w8), .v083523(w12) ); endmodule //--------------------------------------------------- //-- start-5-bits //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- start-5-bit: 32 cycles width pulse //--------------------------------------------------- //---- Top entity module v144728 #( parameter v573b2a = 0 ) ( input v6dda25, input v27dec4, input v92a149, output v4642b6 ); localparam p0 = v573b2a; wire w1; wire w2; wire w3; wire w4; wire w5; wire w6; wire w7; wire w8; wire w9; assign w5 = v6dda25; assign v4642b6 = w6; assign w8 = v27dec4; assign w9 = v92a149; assign w7 = w6; v053dc2 #( .v71e305(p0) ) v24b497 ( .vf54559(w1), .va4102a(w5), .ve8318d(w6) ); vd0c4e5 vda4b54 ( .v030ad0(w1), .v27dec4(w2), .vb192d0(w3), .v2d3366(w8) ); vfebcfe v2141a0 ( .v9fb85f(w2) ); vd0c4e5 v75d8ff ( .v030ad0(w3), .v27dec4(w4), .vb192d0(w7), .v2d3366(w9) ); vd30ca9 va595cf ( .v9fb85f(w4) ); endmodule //--------------------------------------------------- //-- RS-FF-set //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- RS-FF-set. RS Flip-flop with priority set //--------------------------------------------------- //---- Top entity module vfebcfe ( output v9fb85f ); wire w0; assign v9fb85f = w0; vfebcfe_vb2eccd vb2eccd ( .q(w0) ); endmodule //--------------------------------------------------- //-- bit-1 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Constant bit 1 //--------------------------------------------------- module vfebcfe_vb2eccd ( output q ); //-- Constant bit-1 assign q = 1'b1; endmodule //---- Top entity module vaf1249 ( input v6dda25, input ve556f1, output [4:0] va1c800, output ve37344 ); wire w0; wire [0:4] w1; wire [0:4] w2; wire w3; wire [0:4] w4; wire w5; assign w0 = ve556f1; assign w3 = v6dda25; assign va1c800 = w4; assign ve37344 = w5; assign w4 = w1; v6ed669 vad9b51 ( .v782748(w0), .vcc30ea(w1), .v35dd11(w2), .v6dda25(w3) ); vd0bb30 v1e9706 ( .vd03823(w1), .vb4c454(w2), .v4642b6(w5) ); endmodule //--------------------------------------------------- //-- syscounter-rst-5bits //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- 5-bits Syscounter with reset //--------------------------------------------------- //---- Top entity module v6ed669 ( input v6dda25, input v782748, input [4:0] v35dd11, output [4:0] vcc30ea ); wire [0:4] w0; wire [0:3] w1; wire w2; wire [0:3] w3; wire w4; wire [0:4] w5; wire w6; wire w7; wire w8; wire w9; assign w0 = v35dd11; assign vcc30ea = w5; assign w6 = v6dda25; assign w7 = v6dda25; assign w8 = v782748; assign w9 = v782748; assign w7 = w6; assign w9 = w8; v2be0f8 v8aa818 ( .vf354ee(w2), .v4642b6(w4), .vd53b77(w6), .v27dec4(w8) ); v5c75f6 vbdef88 ( .v4de61b(w1), .v50034e(w3), .v6dda25(w7), .v782748(w9) ); v91f34c v122992 ( .v427dd1(w0), .v479af4(w1), .v53baa6(w2) ); vcdce79 v93fefd ( .v167ed7(w3), .vee8a83(w4), .v6a2e9e(w5) ); endmodule //--------------------------------------------------- //-- DFF-rst-x05 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- DFF-rst-x05: Five D flip-flops in paralell with reset //--------------------------------------------------- //---- Top entity module v2be0f8 #( parameter vbd3217 = 0 ) ( input vd53b77, input v27dec4, input vf354ee, output v4642b6 ); localparam p5 = vbd3217; wire w0; wire w1; wire w2; wire w3; wire w4; wire w6; assign w2 = v27dec4; assign w3 = vf354ee; assign v4642b6 = w4; assign w6 = vd53b77; v3676a0 v7539bf ( .vcbab45(w1), .v0e28cb(w2) ); vba518e vfe8158 ( .vcbab45(w0), .v0e28cb(w1), .v3ca442(w3) ); v053dc2 #( .v71e305(p5) ) vd104a4 ( .vf54559(w0), .ve8318d(w4), .va4102a(w6) ); endmodule //--------------------------------------------------- //-- DFF-rst-x01 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- DFF-rst-x01: D Flip flop with reset input. When rst=1, the DFF is 0 //--------------------------------------------------- //---- Top entity module v5c75f6 ( input v6dda25, input v782748, input [3:0] v4de61b, output [3:0] v50034e ); wire w0; wire w1; wire w2; wire w3; wire w4; wire w5; wire [0:3] w6; wire [0:3] w7; wire w8; wire w9; wire w10; wire w11; wire w12; wire w13; wire w14; wire w15; wire w16; wire w17; assign w6 = v4de61b; assign v50034e = w7; assign w10 = v6dda25; assign w11 = v6dda25; assign w12 = v6dda25; assign w13 = v6dda25; assign w14 = v782748; assign w15 = v782748; assign w16 = v782748; assign w17 = v782748; assign w11 = w10; assign w12 = w10; assign w12 = w11; assign w13 = w10; assign w13 = w11; assign w13 = w12; assign w15 = w14; assign w16 = w14; assign w16 = w15; assign w17 = w14; assign w17 = w15; assign w17 = w16; vc4f23a v4b1225 ( .v3f8943(w2), .v64d863(w3), .vda577d(w4), .v985fcb(w6), .v4f1fd3(w8) ); v84f0a1 v6491fd ( .v03aaf0(w0), .vee8a83(w1), .vf8041d(w5), .v11bca5(w7), .vd84a57(w9) ); v2be0f8 v10a04f ( .v4642b6(w0), .vf354ee(w3), .vd53b77(w13), .v27dec4(w17) ); v2be0f8 v7d9648 ( .v4642b6(w1), .vf354ee(w2), .vd53b77(w12), .v27dec4(w16) ); v2be0f8 v004b14 ( .vf354ee(w4), .v4642b6(w5), .vd53b77(w11), .v27dec4(w15) ); v2be0f8 v8aa818 ( .vf354ee(w8), .v4642b6(w9), .vd53b77(w10), .v27dec4(w14) ); endmodule //--------------------------------------------------- //-- DFF-rst-x04 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- DFF-rst-x04: Three D flip-flops in paralell with reset //--------------------------------------------------- //---- Top entity module vcdce79 ( input vee8a83, input [3:0] v167ed7, output [4:0] v6a2e9e ); wire [0:4] w0; wire w1; wire [0:3] w2; assign v6a2e9e = w0; assign w1 = vee8a83; assign w2 = v167ed7; vcdce79_v9a2a06 v9a2a06 ( .o(w0), .i1(w1), .i0(w2) ); endmodule //--------------------------------------------------- //-- Bus5-Join-1-4 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus5-Join-1-4: Join the two buses of 1 and 4 bits into a 5-bits Bus //--------------------------------------------------- module vcdce79_v9a2a06 ( input i1, input [3:0] i0, output [4:0] o ); assign o = {i1, i0}; endmodule //---- Top entity module vd0bb30 #( parameter v6c5139 = 1 ) ( input [4:0] vd03823, output v4642b6, output [4:0] vb4c454 ); localparam p1 = v6c5139; wire w0; wire [0:4] w2; wire [0:4] w3; assign v4642b6 = w0; assign w2 = vd03823; assign vb4c454 = w3; va17f79 #( .vd73390(p1) ) vc288d0 ( .v4642b6(w0), .va6f14e(w2), .v919f01(w3) ); endmodule //--------------------------------------------------- //-- Inc1-5bits //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Inc1-5bit: Increment a 5-bits number by one //--------------------------------------------------- //---- Top entity module va17f79 #( parameter vd73390 = 0 ) ( input [4:0] va6f14e, output v4642b6, output [4:0] v919f01 ); localparam p1 = vd73390; wire w0; wire [0:4] w2; wire [0:4] w3; wire [0:4] w4; assign v4642b6 = w0; assign w3 = va6f14e; assign v919f01 = w4; v0cfc7a v530cb5 ( .v4642b6(w0), .v225d34(w2), .vbb6b94(w3), .vae8b91(w4) ); v3693fc #( .vc5c8ea(p1) ) v809c3c ( .vc8d3b9(w2) ); endmodule //--------------------------------------------------- //-- AdderK-5bits //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- AdderK-5bit: Adder of 5-bit operand and 5-bit constant //--------------------------------------------------- //---- Top entity module v0cfc7a ( input [4:0] v225d34, input [4:0] vbb6b94, output v4642b6, output [4:0] vae8b91 ); wire w0; wire w1; wire [0:4] w2; wire [0:4] w3; wire [0:4] w4; wire w5; wire [0:3] w6; wire w7; wire [0:3] w8; wire w9; wire [0:3] w10; assign w2 = vbb6b94; assign w3 = v225d34; assign vae8b91 = w4; assign v4642b6 = w5; vad119b vb8ad86 ( .v0ef266(w0), .v8e8a67(w1), .v4642b6(w5), .v27dec4(w7), .v82de4f(w9) ); v91f34c v144430 ( .v427dd1(w2), .v53baa6(w9), .v479af4(w10) ); v91f34c v09d2c7 ( .v427dd1(w3), .v53baa6(w7), .v479af4(w8) ); v25966b vd35762 ( .v4642b6(w0), .v817794(w6), .v0550b6(w8), .v24708e(w10) ); vcdce79 v758283 ( .vee8a83(w1), .v6a2e9e(w4), .v167ed7(w6) ); endmodule //--------------------------------------------------- //-- Adder-5bits //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Adder-5bits: Adder of two operands of 5 bits //--------------------------------------------------- //---- Top entity module vad119b ( input v27dec4, input v82de4f, input v0ef266, output v4642b6, output v8e8a67 ); wire w0; wire w1; wire w2; wire w3; wire w4; wire w5; wire w6; wire w7; wire w8; wire w9; wire w10; wire w11; assign v8e8a67 = w1; assign v4642b6 = w5; assign w6 = v27dec4; assign w7 = v27dec4; assign w8 = v82de4f; assign w9 = v82de4f; assign w10 = v0ef266; assign w11 = v0ef266; assign w2 = w0; assign w7 = w6; assign w9 = w8; assign w11 = w10; vd12401 v2e3d9f ( .vcbab45(w0), .v0e28cb(w7), .v3ca442(w9) ); vd12401 vb50462 ( .v0e28cb(w0), .vcbab45(w1), .v3ca442(w11) ); vba518e v4882f4 ( .v3ca442(w2), .vcbab45(w3), .v0e28cb(w10) ); vba518e v8fcf41 ( .vcbab45(w4), .v0e28cb(w6), .v3ca442(w8) ); v873425 vc5b8b9 ( .v3ca442(w3), .v0e28cb(w4), .vcbab45(w5) ); endmodule //--------------------------------------------------- //-- AdderC-1bit //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- AdderC-1bit: Adder of two operands of 1 bit plus the carry in //--------------------------------------------------- //---- Top entity module v25966b ( input [3:0] v0550b6, input [3:0] v24708e, output v4642b6, output [3:0] v817794 ); wire w0; wire w1; wire w2; wire w3; wire w4; wire [0:3] w5; wire [0:3] w6; wire [0:3] w7; wire w8; wire w9; wire w10; wire w11; wire w12; wire w13; wire w14; wire w15; wire w16; wire w17; wire w18; assign w5 = v24708e; assign w6 = v0550b6; assign v817794 = w7; assign v4642b6 = w9; v1ea21d vdbe125 ( .v4642b6(w0), .v8e8a67(w2), .v27dec4(w15), .v82de4f(w18) ); vad119b vb8ad86 ( .v0ef266(w0), .v8e8a67(w1), .v4642b6(w3), .v27dec4(w14), .v82de4f(w17) ); vad119b v5d29b2 ( .v0ef266(w3), .v8e8a67(w4), .v4642b6(w8), .v27dec4(w12), .v82de4f(w16) ); vc4f23a vf4a6ff ( .v985fcb(w5), .v4f1fd3(w13), .vda577d(w16), .v3f8943(w17), .v64d863(w18) ); vc4f23a v9d4632 ( .v985fcb(w6), .v4f1fd3(w11), .vda577d(w12), .v3f8943(w14), .v64d863(w15) ); v84f0a1 v140dbf ( .vee8a83(w1), .v03aaf0(w2), .vf8041d(w4), .v11bca5(w7), .vd84a57(w10) ); vad119b v5c5937 ( .v0ef266(w8), .v4642b6(w9), .v8e8a67(w10), .v27dec4(w11), .v82de4f(w13) ); endmodule //--------------------------------------------------- //-- Adder-4bits //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Adder-4bits: Adder of two operands of 4 bits //--------------------------------------------------- //---- Top entity module v1ea21d ( input v27dec4, input v82de4f, output v4642b6, output v8e8a67 ); wire w0; wire w1; wire w2; wire w3; wire w4; assign w0 = v82de4f; assign w1 = v27dec4; assign v4642b6 = w3; assign v8e8a67 = w4; vad119b vb820a1 ( .v82de4f(w0), .v27dec4(w1), .v0ef266(w2), .v4642b6(w3), .v8e8a67(w4) ); vd30ca9 v23ebb6 ( .v9fb85f(w2) ); endmodule //--------------------------------------------------- //-- Adder-1bit //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Adder-1bit: Adder of two operands of 1 bit //--------------------------------------------------- //---- Top entity module v51353d ( input [4:0] v083523, input v427380, output [4:0] v81cd93 ); wire w0; wire w1; wire w2; wire w3; wire w4; wire w5; wire w6; wire w7; wire [0:4] w8; wire w9; wire [0:4] w10; wire w11; wire w12; wire w13; wire w14; wire w15; wire w16; assign w1 = v427380; assign w2 = v427380; assign w6 = v427380; assign w8 = v083523; assign v81cd93 = w10; assign w13 = v427380; assign w14 = v427380; assign w2 = w1; assign w6 = w1; assign w6 = w2; assign w13 = w1; assign w13 = w2; assign w13 = w6; assign w14 = w1; assign w14 = w2; assign w14 = w6; assign w14 = w13; vba518e v984c00 ( .v0e28cb(w0), .v3ca442(w2), .vcbab45(w3) ); vba518e v63c547 ( .v3ca442(w1), .vcbab45(w4), .v0e28cb(w9) ); vba518e v017827 ( .v0e28cb(w5), .v3ca442(w6), .vcbab45(w7) ); v60f5a9 v3aadcd ( .v3f8943(w0), .vda577d(w5), .v427dd1(w8), .v64d863(w9), .v53baa6(w11), .v4f1fd3(w12) ); v36cddd v6e87bf ( .vee8a83(w3), .v03aaf0(w4), .vf8041d(w7), .v6a2e9e(w10), .vd84a57(w15), .v684b0d(w16) ); vba518e vd994d2 ( .v0e28cb(w12), .v3ca442(w13), .vcbab45(w15) ); vba518e v0bd924 ( .v0e28cb(w11), .v3ca442(w14), .vcbab45(w16) ); endmodule //--------------------------------------------------- //-- AND-Busen-5 //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- AND-Busen-5: Enable a 5-bits bus. When the enable signal is 0, the output is 0 //--------------------------------------------------- //---- Top entity module v60f5a9 ( input [4:0] v427dd1, output v53baa6, output v4f1fd3, output vda577d, output v3f8943, output v64d863 ); wire w0; wire w1; wire w2; wire w3; wire w4; wire [0:4] w5; assign v3f8943 = w0; assign v64d863 = w1; assign vda577d = w2; assign v4f1fd3 = w3; assign v53baa6 = w4; assign w5 = v427dd1; v60f5a9_v9a2a06 v9a2a06 ( .o1(w0), .o0(w1), .o2(w2), .o3(w3), .o4(w4), .i(w5) ); endmodule //--------------------------------------------------- //-- Bus5-Split-all //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus5-Split-all: Split the 5-bits bus into its wires //--------------------------------------------------- module v60f5a9_v9a2a06 ( input [4:0] i, output o4, output o3, output o2, output o1, output o0 ); assign o4 = i[4]; assign o3 = i[3]; assign o2 = i[2]; assign o1 = i[1]; assign o0 = i[0]; endmodule //---- Top entity module v36cddd ( input v684b0d, input vd84a57, input vf8041d, input vee8a83, input v03aaf0, output [4:0] v6a2e9e ); wire w0; wire w1; wire [0:4] w2; wire w3; wire w4; wire w5; assign w0 = vee8a83; assign w1 = v03aaf0; assign v6a2e9e = w2; assign w3 = vf8041d; assign w4 = vd84a57; assign w5 = v684b0d; v36cddd_v9a2a06 v9a2a06 ( .i1(w0), .i0(w1), .o(w2), .i2(w3), .i3(w4), .i4(w5) ); endmodule //--------------------------------------------------- //-- Bus5-Join-all //-- - - - - - - - - - - - - - - - - - - - - - - - -- //-- Bus5-Join-all: Join all the wires into a 5-bits Bus //--------------------------------------------------- module v36cddd_v9a2a06 ( input i4, input i3, input i2, input i1, input i0, output [4:0] o ); assign o = {i4, i3, i2, i1, i0}; endmodule

/****************************************************************************** * License Agreement * * * * Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. * * All rights reserved. * * * * Any megafunction design, and related net list (encrypted or decrypted), * * support information, device programming or simulation file, and any other * * associated documentation or information provided by Altera or a partner * * under Altera's Megafunction Partnership Program may be used only to * * program PLD devices (but not masked PLD devices) from Altera. Any other * * use of such megafunction design, net list, support information, device * * programming or simulation file, or any other related documentation or * * information is prohibited for any other purpose, including, but not * * limited to modification, reverse engineering, de-compiling, or use with * * any other silicon devices, unless such use is explicitly licensed under * * a separate agreement with Altera or a megafunction partner. Title to * * the intellectual property, including patents, copyrights, trademarks, * * trade secrets, or maskworks, embodied in any such megafunction design, * * net list, support information, device programming or simulation file, or * * any other related documentation or information provided by Altera or a * * megafunction partner, remains with Altera, the megafunction partner, or * * their respective licensors. No other licenses, including any licenses * * needed under any third party's intellectual property, are provided herein.* * Copying or modifying any file, or portion thereof, to which this notice * * is attached violates this copyright. * * * * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS * * IN THIS FILE. * * * * This agreement shall be governed in all respects by the laws of the State * * of California and by the laws of the United States of America. * * * ******************************************************************************/ /****************************************************************************** * * * This module read and write data to the 16x2 Character LCD on the DE2 * * Board. * * * ******************************************************************************/ module altera_up_character_lcd_communication ( // Inputs clk, reset, data_in, enable, rs, rw, display_on, back_light_on, // Bidirectionals LCD_DATA, // Outputs LCD_ON, LCD_BLON, LCD_EN, LCD_RS, LCD_RW, data_out, transfer_complete ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ // Timing info for minimum wait between consecutive communications // if using a 50MHz Clk parameter CLOCK_CYCLES_FOR_IDLE_STATE = 7'h7F; // Minimum 2500 ns parameter IC = 7; // Number of bits for idle counter parameter IDLE_COUNTER_INCREMENT = 7'h01; parameter CLOCK_CYCLES_FOR_OPERATION_STATE = 3; // Minimum 40 ns parameter CLOCK_CYCLES_FOR_ENABLE_STATE = 15; // Minimum 230 ns parameter CLOCK_CYCLES_FOR_HOLD_STATE = 1; // Minimum 10 ns parameter SC = 4; // Number of bits for states counter parameter COUNTER_INCREMENT = 4'h1; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input [ 7: 0] data_in; input rs; input rw; input enable; input display_on; input back_light_on; // Bidirectionals inout [ 7: 0] LCD_DATA; // Outputs output reg LCD_ON; output reg LCD_BLON; output reg LCD_EN; output reg LCD_RS; output reg LCD_RW; output reg [ 7: 0] data_out; // Stores data read from the LCD output reg transfer_complete; // Indicates the end of the transfer /***************************************************************************** * Constant Declarations * *****************************************************************************/ // states parameter LCD_STATE_4_IDLE = 3'h4, LCD_STATE_0_OPERATION = 3'h0, LCD_STATE_1_ENABLE = 3'h1, LCD_STATE_2_HOLD = 3'h2, LCD_STATE_3_END = 3'h3; /***************************************************************************** * Internal Wires and Registers Declarations * *****************************************************************************/ // Internal Wires // Internal Registers reg [ 7: 0] data_to_lcd; reg [IC: 1] idle_counter; reg [SC: 1] state_0_counter; reg [SC: 1] state_1_counter; reg [SC: 1] state_2_counter; // State Machine Registers reg [ 2: 0] ns_lcd; reg [ 2: 0] s_lcd; /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ always @(posedge clk) begin if (reset) s_lcd <= LCD_STATE_4_IDLE; else s_lcd <= ns_lcd; end always @(*) begin ns_lcd = LCD_STATE_4_IDLE; case (s_lcd) LCD_STATE_4_IDLE: begin if ((idle_counter == CLOCK_CYCLES_FOR_IDLE_STATE) & enable) ns_lcd = LCD_STATE_0_OPERATION; else ns_lcd = LCD_STATE_4_IDLE; end LCD_STATE_0_OPERATION: begin if (state_0_counter == CLOCK_CYCLES_FOR_OPERATION_STATE) ns_lcd = LCD_STATE_1_ENABLE; else ns_lcd = LCD_STATE_0_OPERATION; end LCD_STATE_1_ENABLE: begin if (state_1_counter == CLOCK_CYCLES_FOR_ENABLE_STATE) ns_lcd = LCD_STATE_2_HOLD; else ns_lcd = LCD_STATE_1_ENABLE; end LCD_STATE_2_HOLD: begin if (state_2_counter == CLOCK_CYCLES_FOR_HOLD_STATE) ns_lcd = LCD_STATE_3_END; else ns_lcd = LCD_STATE_2_HOLD; end LCD_STATE_3_END: begin if (enable == 1'b0) ns_lcd = LCD_STATE_4_IDLE; else ns_lcd = LCD_STATE_3_END; end default: begin ns_lcd = LCD_STATE_4_IDLE; end endcase end /***************************************************************************** * Sequential Logic * *****************************************************************************/ always @(posedge clk) begin if (reset) begin LCD_ON <= 1'b0; LCD_BLON <= 1'b0; end else begin LCD_ON <= display_on; LCD_BLON <= back_light_on; end end always @(posedge clk) begin if (reset) begin LCD_EN <= 1'b0; LCD_RS <= 1'b0; LCD_RW <= 1'b0; data_out <= 8'h00; transfer_complete <= 1'b0; end else begin if (s_lcd == LCD_STATE_1_ENABLE) LCD_EN <= 1'b1; else LCD_EN <= 1'b0; if (s_lcd == LCD_STATE_4_IDLE) begin LCD_RS <= rs; LCD_RW <= rw; data_to_lcd <= data_in; end if (s_lcd == LCD_STATE_1_ENABLE) data_out <= LCD_DATA; if (s_lcd == LCD_STATE_3_END) transfer_complete <= 1'b1; else transfer_complete <= 1'b0; end end always @(posedge clk) begin if (reset) idle_counter <= {IC{1'b0}}; else if (s_lcd == LCD_STATE_4_IDLE) idle_counter <= idle_counter + IDLE_COUNTER_INCREMENT; else idle_counter <= {IC{1'b0}}; end always @(posedge clk) begin if (reset) begin state_0_counter <= {SC{1'b0}}; state_1_counter <= {SC{1'b0}}; state_2_counter <= {SC{1'b0}}; end else begin if (s_lcd == LCD_STATE_0_OPERATION) state_0_counter <= state_0_counter + COUNTER_INCREMENT; else state_0_counter <= {SC{1'b0}}; if (s_lcd == LCD_STATE_1_ENABLE) state_1_counter <= state_1_counter + COUNTER_INCREMENT; else state_1_counter <= {SC{1'b0}}; if (s_lcd == LCD_STATE_2_HOLD) state_2_counter <= state_2_counter + COUNTER_INCREMENT; else state_2_counter <= {SC{1'b0}}; end end /***************************************************************************** * Combinational Logic * *****************************************************************************/ assign LCD_DATA = (((s_lcd == LCD_STATE_1_ENABLE) || (s_lcd == LCD_STATE_2_HOLD)) && (LCD_RW == 1'b0)) ? data_to_lcd : 8'hzz; /***************************************************************************** * Internal Modules * *****************************************************************************/ endmodule

//----------------------------------------------------------------- // // The original verilog code provided by Clifford E. Cummings, // Sunburst Design, Inc. // // Email: <cliffc@sunburst-design.com> // Web: www.sunburst-design.com // //---------------------------------------------------------------- module small_async_fifo #( parameter DSIZE = 8, parameter ASIZE = 3, parameter ALMOST_FULL_SIZE = 5, parameter ALMOST_EMPTY_SIZE = 3 ) ( //wr interface output wfull, output w_almost_full, input [DSIZE-1:0] wdata, input winc, wclk, wrst_n, //rd interface output [DSIZE-1:0] rdata, output rempty, output r_almost_empty, input rinc, rclk, rrst_n ); wire [ASIZE-1:0] waddr, raddr; wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr; sync_r2w #(ASIZE) sync_r2w (.wq2_rptr(wq2_rptr), .rptr(rptr), .wclk(wclk), .wrst_n(wrst_n)); sync_w2r #(ASIZE) sync_w2r (.rq2_wptr(rq2_wptr), .wptr(wptr), .rclk(rclk), .rrst_n(rrst_n)); fifo_mem #(DSIZE, ASIZE) fifo_mem (.rdata(rdata), .wdata(wdata), .waddr(waddr), .raddr(raddr), .wclken(winc), .wfull(wfull), .wclk(wclk)); rptr_empty #(.ADDRSIZE(ASIZE), .ALMOST_EMPTY_SIZE(ALMOST_EMPTY_SIZE)) rptr_empty (.rempty(rempty), .r_almost_empty(r_almost_empty), .raddr(raddr), .rptr(rptr), .rq2_wptr(rq2_wptr), .rinc(rinc), .rclk(rclk), .rrst_n(rrst_n)); wptr_full #(.ADDRSIZE(ASIZE), .ALMOST_FULL_SIZE(ALMOST_FULL_SIZE)) wptr_full (.wfull(wfull), .w_almost_full(w_almost_full), .waddr(waddr), .wptr(wptr), .wq2_rptr(wq2_rptr), .winc(winc), .wclk(wclk), .wrst_n(wrst_n)); endmodule // small_async_fifo module sync_r2w #(parameter ADDRSIZE = 3) (output reg [ADDRSIZE:0] wq2_rptr, input [ADDRSIZE:0] rptr, input wclk, wrst_n); reg [ADDRSIZE:0] wq1_rptr; always @(posedge wclk or negedge wrst_n) if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0; else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr}; endmodule // sync_r2w module sync_w2r #(parameter ADDRSIZE = 3) (output reg [ADDRSIZE:0] rq2_wptr, input [ADDRSIZE:0] wptr, input rclk, rrst_n); reg [ADDRSIZE:0] rq1_wptr; always @(posedge rclk or negedge rrst_n) if (!rrst_n) {rq2_wptr,rq1_wptr} <= 0; else {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr}; endmodule // sync_w2r module rptr_empty #(parameter ADDRSIZE = 3, parameter ALMOST_EMPTY_SIZE=3) (output reg rempty, output reg r_almost_empty, output [ADDRSIZE-1:0] raddr, output reg [ADDRSIZE :0] rptr, input [ADDRSIZE :0] rq2_wptr, input rinc, rclk, rrst_n); reg [ADDRSIZE:0] rbin; wire [ADDRSIZE:0] rgraynext, rbinnext; reg [ADDRSIZE :0] rq2_wptr_bin; integer i; //------------------ // GRAYSTYLE2 pointer //------------------ always @(posedge rclk or negedge rrst_n) if (!rrst_n) {rbin, rptr} <= 0; else {rbin, rptr} <= {rbinnext, rgraynext}; // Memory read-address pointer (okay to use binary to address memory) assign raddr = rbin[ADDRSIZE-1:0]; assign rbinnext = rbin + (rinc & ~rempty); assign rgraynext = (rbinnext>>1) ^ rbinnext; //-------------------------------------------------------------- // FIFO empty when the next rptr == synchronized wptr or on reset //-------------------------------------------------------------- wire rempty_val = (rgraynext == rq2_wptr); // Gray code to Binary code conversion always @(rq2_wptr) for (i=0; i<(ADDRSIZE+1); i=i+1) rq2_wptr_bin[i] = ^ (rq2_wptr >> i); wire [ADDRSIZE:0] subtract = (rbinnext + ALMOST_EMPTY_SIZE)-rq2_wptr_bin; wire r_almost_empty_val = ~subtract[ADDRSIZE]; always @(posedge rclk or negedge rrst_n) if (!rrst_n) begin rempty <= 1'b1; r_almost_empty <= 1'b 1; end else begin rempty <= rempty_val; r_almost_empty <= r_almost_empty_val; end endmodule // rptr_empty module wptr_full #(parameter ADDRSIZE = 3, parameter ALMOST_FULL_SIZE=5 ) (output reg wfull, output reg w_almost_full, output [ADDRSIZE-1:0] waddr, output reg [ADDRSIZE :0] wptr, input [ADDRSIZE :0] wq2_rptr, input winc, wclk, wrst_n); reg [ADDRSIZE:0] wbin; wire [ADDRSIZE:0] wgraynext, wbinnext; reg [ADDRSIZE :0] wq2_rptr_bin; integer i; // GRAYSTYLE2 pointer always @(posedge wclk or negedge wrst_n) if (!wrst_n) {wbin, wptr} <= 0; else {wbin, wptr} <= {wbinnext, wgraynext}; // Memory write-address pointer (okay to use binary to address memory) assign waddr = wbin[ADDRSIZE-1:0]; assign wbinnext = wbin + (winc & ~wfull); assign wgraynext = (wbinnext>>1) ^ wbinnext; //----------------------------------------------------------------- // Simplified version of the three necessary full-tests: // assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) && // (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) && // (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0])); //----------------------------------------------------------------- wire wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]}); // Gray code to Binary code conversion always @(wq2_rptr) for (i=0; i<(ADDRSIZE+1); i=i+1) wq2_rptr_bin[i] = ^ (wq2_rptr >> i); wire [ADDRSIZE :0] subtract = wbinnext - wq2_rptr_bin - ALMOST_FULL_SIZE; wire w_almost_full_val = ~subtract[ADDRSIZE]; always @(posedge wclk or negedge wrst_n) if (!wrst_n) begin wfull <= 1'b0; w_almost_full <= 1'b 0; end else begin wfull <= wfull_val; w_almost_full <= w_almost_full_val; end endmodule // wptr_full module fifo_mem #(parameter DATASIZE = 8, // Memory data word width parameter ADDRSIZE = 3) // Number of mem address bits (output [DATASIZE-1:0] rdata, input [DATASIZE-1:0] wdata, input [ADDRSIZE-1:0] waddr, raddr, input wclken, wfull, wclk); // RTL Verilog memory model localparam DEPTH = 1<<ADDRSIZE; reg [DATASIZE-1:0] mem [0:DEPTH-1]; assign rdata = mem[raddr]; always @(posedge wclk) if (wclken && !wfull) mem[waddr] <= wdata; endmodule // fifo_mem

// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:axi_register_slice:2.1 // IP Revision: 9 `timescale 1ns/1ps (* DowngradeIPIdentifiedWarnings = "yes" *) module block_design_m01_regslice_0 ( aclk, aresetn, s_axi_awaddr, s_axi_awprot, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready ); (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) input wire aclk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input wire aresetn; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input wire [31 : 0] s_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input wire [2 : 0] s_axi_awprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input wire s_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output wire s_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input wire [31 : 0] s_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input wire [3 : 0] s_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input wire s_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output wire s_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output wire [1 : 0] s_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output wire s_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input wire s_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input wire [31 : 0] s_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input wire [2 : 0] s_axi_arprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input wire s_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output wire s_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output wire [31 : 0] s_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output wire [1 : 0] s_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output wire s_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input wire s_axi_rready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output wire [31 : 0] m_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output wire [2 : 0] m_axi_awprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output wire m_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input wire m_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output wire [31 : 0] m_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output wire [3 : 0] m_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output wire m_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input wire m_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input wire [1 : 0] m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input wire m_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output wire m_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output wire [31 : 0] m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output wire [2 : 0] m_axi_arprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output wire m_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input wire m_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input wire [31 : 0] m_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input wire [1 : 0] m_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input wire m_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output wire m_axi_rready; axi_register_slice_v2_1_9_axi_register_slice #( .C_FAMILY("zynq"), .C_AXI_PROTOCOL(2), .C_AXI_ID_WIDTH(1), .C_AXI_ADDR_WIDTH(32), .C_AXI_DATA_WIDTH(32), .C_AXI_SUPPORTS_USER_SIGNALS(0), .C_AXI_AWUSER_WIDTH(1), .C_AXI_ARUSER_WIDTH(1), .C_AXI_WUSER_WIDTH(1), .C_AXI_RUSER_WIDTH(1), .C_AXI_BUSER_WIDTH(1), .C_REG_CONFIG_AW(7), .C_REG_CONFIG_W(7), .C_REG_CONFIG_B(7), .C_REG_CONFIG_AR(7), .C_REG_CONFIG_R(7) ) inst ( .aclk(aclk), .aresetn(aresetn), .s_axi_awid(1'H0), .s_axi_awaddr(s_axi_awaddr), .s_axi_awlen(8'H00), .s_axi_awsize(3'H0), .s_axi_awburst(2'H1), .s_axi_awlock(1'H0), .s_axi_awcache(4'H0), .s_axi_awprot(s_axi_awprot), .s_axi_awregion(4'H0), .s_axi_awqos(4'H0), .s_axi_awuser(1'H0), .s_axi_awvalid(s_axi_awvalid), .s_axi_awready(s_axi_awready), .s_axi_wid(1'H0), .s_axi_wdata(s_axi_wdata), .s_axi_wstrb(s_axi_wstrb), .s_axi_wlast(1'H1), .s_axi_wuser(1'H0), .s_axi_wvalid(s_axi_wvalid), .s_axi_wready(s_axi_wready), .s_axi_bid(), .s_axi_bresp(s_axi_bresp), .s_axi_buser(), .s_axi_bvalid(s_axi_bvalid), .s_axi_bready(s_axi_bready), .s_axi_arid(1'H0), .s_axi_araddr(s_axi_araddr), .s_axi_arlen(8'H00), .s_axi_arsize(3'H0), .s_axi_arburst(2'H1), .s_axi_arlock(1'H0), .s_axi_arcache(4'H0), .s_axi_arprot(s_axi_arprot), .s_axi_arregion(4'H0), .s_axi_arqos(4'H0), .s_axi_aruser(1'H0), .s_axi_arvalid(s_axi_arvalid), .s_axi_arready(s_axi_arready), .s_axi_rid(), .s_axi_rdata(s_axi_rdata), .s_axi_rresp(s_axi_rresp), .s_axi_rlast(), .s_axi_ruser(), .s_axi_rvalid(s_axi_rvalid), .s_axi_rready(s_axi_rready), .m_axi_awid(), .m_axi_awaddr(m_axi_awaddr), .m_axi_awlen(), .m_axi_awsize(), .m_axi_awburst(), .m_axi_awlock(), .m_axi_awcache(), .m_axi_awprot(m_axi_awprot), .m_axi_awregion(), .m_axi_awqos(), .m_axi_awuser(), .m_axi_awvalid(m_axi_awvalid), .m_axi_awready(m_axi_awready), .m_axi_wid(), .m_axi_wdata(m_axi_wdata), .m_axi_wstrb(m_axi_wstrb), .m_axi_wlast(), .m_axi_wuser(), .m_axi_wvalid(m_axi_wvalid), .m_axi_wready(m_axi_wready), .m_axi_bid(1'H0), .m_axi_bresp(m_axi_bresp), .m_axi_buser(1'H0), .m_axi_bvalid(m_axi_bvalid), .m_axi_bready(m_axi_bready), .m_axi_arid(), .m_axi_araddr(m_axi_araddr), .m_axi_arlen(), .m_axi_arsize(), .m_axi_arburst(), .m_axi_arlock(), .m_axi_arcache(), .m_axi_arprot(m_axi_arprot), .m_axi_arregion(), .m_axi_arqos(), .m_axi_aruser(), .m_axi_arvalid(m_axi_arvalid), .m_axi_arready(m_axi_arready), .m_axi_rid(1'H0), .m_axi_rdata(m_axi_rdata), .m_axi_rresp(m_axi_rresp), .m_axi_rlast(1'H1), .m_axi_ruser(1'H0), .m_axi_rvalid(m_axi_rvalid), .m_axi_rready(m_axi_rready) ); endmodule

/////////////////////////////////////////////////////////////////////////////// // // Copyright (C) 2014 Francis Bruno, All Rights Reserved // // This program is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License as published by the Free // Software Foundation; either version 3 of the License, or (at your option) // any later version. // // This program is distributed in the hope that it will be useful, but // WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY // or FITNESS FOR A PARTICULAR PURPOSE. // See the GNU General Public License for more details. // // You should have received a copy of the GNU General Public License along with // this program; if not, see <http://www.gnu.org/licenses>. // // This code is available under licenses for commercial use. Please contact // Francis Bruno for more information. // // http://www.gplgpu.com // http://www.asicsolutions.com // // Title : Drawing Engine Data Path // File : ded_top.v // Author : Frank Bruno // Created : 30-Dec-2008 // RCS File : $Source:$ // Status : $Id:$ // // /////////////////////////////////////////////////////////////////////////////// // // Description : // This is the Drawing Engine Data path 2D only // ////////////////////////////////////////////////////////////////////////////// // // Modules Instantiated: // /////////////////////////////////////////////////////////////////////////////// // // Modification History: // // $Log:$ // /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// `timescale 1ns / 10ps module ded_top #(parameter BYTES = 16) ( // Global Signals input de_clk, // Drawing Engine Clock de_rstn, // Drawing Engine Reset // Host/ XY Windows input hb_clk, // host bus clock hb_rstn, // host bus reset input [12:2] hb_adr, // host bus lower address bits input hb_we, // host bus write strobe input hb_xyw_csn, // chip select for XY window // DEX related input dx_mem_req, // memory request dx_mem_rd, // memory read dx_line_actv_2, // line command active signal dx_blt_actv_2, // bit blt active signal input dx_pc_ld, // load pixel cache input [31:0] dx_clpx_bus_2, // clipping X values input dx_rstn_wad, // load cache write address input dx_ld_rad, // load cache read address input dx_ld_rad_e, // load cache read address input dx_sol_2, // start of line flag dx_eol_2, // end of line flag input dx_ld_msk, // load mask.{ld_start,ld_end, // ld_lftclp,ld_rhtclp} input [9:0] dx_xalu, // lower four bits of the X alu. input [15:0] srcx, // lower five bits from the destination X input [15:0] srcy, // lower five bits from the destination X input [15:0] dsty, // lower five bits from the destination Y input [15:0] dx_dstx, // Current X for blts and xfers. input dx_fg_bgn, // fore/back ground bit for line pat. input clip, // Clip indicator. PIPED SIGNAL input [4:0] xpat_ofs, // X off set for patterns. input [4:0] ypat_ofs, // Y off set for patterns. input [15:0] real_dstx, // X destination. input [15:0] real_dsty, // Y destination. input ld_initial, // load the initial color value. input pc_msk_last, // Mask the last pixel for nolast input last_pixel, // Last Pixel from Jim (Not Clean) input ld_wcnt, input [3:0] fx_1, input rmw, // Memory Controller Inputs input mclock, // memory controller clock input mc_popen, // memory controller pop enable input mc_push, // push data into fifo from MC. mc_eop, // end of page cycle pulse, from MC mc_eop4, // end of page cycle pulse, from MC input de_pc_pop, // Pop from PC // Level 2 Registers input [3:0] de_pln_msk_2, // Plane mask bits input dr_solid_2, // solid mode bit dr_trnsp_2, // transparent mode bit input [1:0] stpl_2, // stipple mode bit 01 = planar, 10 = packed input [1:0] dr_apat_2, // area mode bits 01 = 8x8, 10 = 32x32 input [1:0] dr_clp_2, // lower two bits of the clipping register input [31:0] fore_2, // foreground register output input [31:0] back_2, // background register output input dr_sen_2, // Source enable bits input y_clip_2, // Inside the Y clipping boundries input ps8_2, // pixel size equals eight ps16_2, // pixel size equals sixteen ps32_2, // pixel size equals thirty-two input [1:0] bc_lvl_2, // Y page request limit input hb_write, input [27:0] dorg_2, // Destination origin. input [27:0] sorg_2, // Source origin. input [27:0] z_org, // Z origin input [11:0] dptch_2, // destination pitch. input [11:0] sptch_2, // source pitch. input [11:0] z_ptch, // Z pitch input [1:0] ps_2, // Pixel size to MC input [3:0] bsrcr_2, // Source blending function. input [2:0] bdstr_2, // Destination blending function. input blend_en_2, // Blending enable. input [1:0] blend_reg_en_2,// Select blending registers or alpha from FB input [7:0] bsrc_alpha_2, // Source alpha data. input [7:0] bdst_alpha_2, // Destination alpha data. input [3:0] rop_2, // Raster operation. input [31:0] kcol_2, // Key Color. input [2:0] key_ctrl_2, // Key control. input [2:0] frst8_2, // used to be in dex // Memory Controller Outputs output [BYTES-1:0] mc_pixel_msk, // pixel mask data output output [(BYTES<<3)-1:0] mc_fb_out, // frame buffer data output output [(BYTES<<2)-1:0] mc_fb_a, // frame buffer data output output pc_mc_busy, // gated MC busy for Jim output [31:0] de_mc_address, // Line/ Blt linear address output de_mc_read, output de_mc_rmw, output [3:0] de_mc_wcnt, output de_pc_empty, output pc_empty, // Host Bus output [31:0] hb_dout, // Host read back data. // ded_ca_top memory interface `ifdef BYTE16 output [3:0] ca_enable, `elsif BYTE8 output [1:0] ca_enable, `else output ca_enable, `endif output [4:0] hb_ram_addr, output [4:0] ca_ram_addr0, output [4:0] ca_ram_addr1, input [(BYTES*8)-1:0] hb_dout_ram, input [(BYTES<<3)-1:0] ca_dout0, input [(BYTES<<3)-1:0] ca_dout1, // Drawing Engine output pc_dirty, // data is left in the pixel cache output clip_ind, // Clipping indicator. output stpl_pk_4, // packed stipple bit, level four output pc_mc_rdy, // Ready signal from PC to DX output pipe_pending, // There is something in the PC or pipe output line_actv_4, output [1:0] ps_4, output [3:0] bsrcr_4, // Source blending function. output [2:0] bdstr_4, // Destination blending function. output blend_en_4, // Blending enable. output [1:0] blend_reg_en_4, // Blending register enables output [7:0] bsrc_alpha_4, // Source alpha data. output [7:0] bdst_alpha_4, // Destination alpha data. output [3:0] rop_4, // Raster operation. output [31:0] kcol_4, // Key Color. output [2:0] key_ctrl_4, // Key control. //////////////////////////////////////////////////////// // 3D Interface. output pc_busy_3d, input valid_3d, input fg_bgn_3d, input msk_last_3d, input [15:0] x_out_3d, input [15:0] y_out_3d, input last_3d, input [31:0] pixel_3d, input [31:0] z_3d, input [4:0] z_ctrl, input active_3d_2, input [7:0] alpha_3d, output pc_last, output [4:0] z_ctrl_4, output [31:0] z_address_4, output [(BYTES*8)-1:0] z_out ); wire [(BYTES<<3)-1:0] de_pc_data; wire [(BYTES<<2)-1:0] de_pc_a; wire [BYTES-1:0] de_pc_mask; wire [1:0] clp_4; wire [31:0] fore_4; // foreground register output wire [31:0] back_4; // foreground register output /************************************************************************/ /* CREATE INTERNAL WIRE BUSSES */ /************************************************************************/ wire [(BYTES<<3)-1:0] ca_din; /* Data into cache. */ wire [BYTES-1:0] cx_sel; /* color expand selector. */ wire [BYTES-1:0] trns_msk; /* transparentcy mask. */ wire [9:0] ca_rad; /* Cache read address. */ wire [7:0] ca_wr_en; /* Cache write enables. */ wire [1:0] apat_4; wire [2:0] psize_4; wire [1:0] stpl_4; wire [8:0] x_bitmask; /* muxed input bitmask to texel cache */ wire [8:0] y_bitmask; /* muxed input bitmask to texel cache */ wire ca_src_2 = dr_sen_2; reg xyw_csn_d; `ifdef BYTE16 wire [2:0] ca_mc_addr; `elsif BYTE8 wire [3:0] ca_mc_addr; `else wire [4:0] ca_mc_addr; `endif wire sol_3; wire ps32_4; wire ps16_4; wire ps8_4; wire solid_4; wire blt_actv_4; wire trnsp_4; wire eol_4; wire pc_busy; wire [3:0] mask_4; wire rad_flg_2, rad_flg_3; wire [2:0] strt_wrd_2; wire [3:0] strt_byt_2; wire [2:0] strt_bit_2; wire [2:0] strt_wrd_3; wire [3:0] strt_byt_3; wire [2:0] strt_bit_3; wire [2:0] strt_wrd_4; wire [3:0] strt_byt_4; wire [2:0] strt_bit_4; wire [6:0] lft_enc_2; wire [6:0] rht_enc_2; wire [11:0] clp_min_2; // left clipping pointer wire [11:0] clp_max_2; // right clipping pointer wire [3:0] cmin_enc_2; wire [3:0] cmax_enc_2; wire [6:0] lft_enc_4; wire [6:0] rht_enc_4; wire [11:0] clp_min_4; // left clipping pointer wire [11:0] clp_max_4; // right clipping pointer wire [3:0] cmin_enc_4; wire [3:0] cmax_enc_4; wire y_clip_4; wire sol_4; wire [13:0] x_bus_4; wire mc_read_3; wire rst_wad_flg_2, rst_wad_flg_3; wire [2:0] frst8_4; wire mc_acken; assign stpl_pk_4 = stpl_4[1]; assign pc_mc_rdy = ~pc_busy; /****************************************************************/ /* DATAPATH CACHE CONTROLLER */ /****************************************************************/ ded_cactrl #(.BYTES (BYTES)) U_CACTRL ( .de_clk (de_clk), .de_rstn (de_rstn), .mc_read_4 (mc_read_3), .mc_push (mc_push), .mclock (mclock), //.mc_popen (mc_popen & blt_actv_4 & ~solid_4), .mc_popen (mc_popen), .mc_acken (mc_acken), .irst_wad (dx_rstn_wad), .ld_rad (dx_ld_rad), .ld_rad_e (dx_ld_rad_e), .x_adr (dx_xalu), .srcx (srcx[8:0]), .dsty (dsty[4:0]), .dstx (dx_dstx[6:0]), .lt_actv_4 (line_actv_4), .stpl_2 (stpl_2), .stpl_4 (stpl_4), .apat_2 (dr_apat_2), .apat_4 (apat_4), .ps8_2 (ps8_2), .ps16_2 (ps16_2), .ps32_2 (ps32_2), .psize_4 (psize_4), //.mc_eop (mc_eop & blt_actv_4 & ~solid_4), .mc_eop (mc_eop), .eol_4 (eol_4), .ofset (srcx[2:0]), .frst8_4 (frst8_4), .sol_3 (sol_3), //.mem_req (dx_mem_req & dx_blt_actv_2), .mem_req (dx_mem_req), .mem_rd (dx_mem_rd), .xpat_ofs (xpat_ofs), .ypat_ofs (ypat_ofs), .ca_src_2 (ca_src_2), .rad_flg_2 (rad_flg_2), .strt_wrd_3 (strt_wrd_3), .strt_byt_3 (strt_byt_3), .strt_bit_3 (strt_bit_3), .strt_wrd_4 (strt_wrd_4), .strt_byt_4 (strt_byt_4), .strt_bit_4 (strt_bit_4), .rst_wad_flg_3 (rst_wad_flg_3), .rad_flg_3 (rad_flg_3), .strt_wrd_2 (strt_wrd_2), .strt_byt_2 (strt_byt_2), .strt_bit_2 (strt_bit_2), .rst_wad_flg_2 (rst_wad_flg_2), .ca_rad (ca_rad), .ca_mc_addr (ca_mc_addr) ); /****************************************************************/ /* DATAPATH DATA CACHE */ /****************************************************************/ ded_ca_top #(.BYTES (BYTES)) U_CA_TOP ( .mclock (mclock), .mc_push (mc_push), .mc_addr (ca_mc_addr), .hclock (hb_clk), .hb_we (hb_we & ~hb_xyw_csn), // fixme??? is this needed .hb_addr (hb_adr[6:2]), .hb_dout_ram (hb_dout_ram), `ifdef BYTE16 .rad (ca_rad[9:7]), `elsif BYTE8 .rad (ca_rad[9:6]), `else .rad (ca_rad[9:5]), `endif .ca_enable (ca_enable), .hb_dout (hb_dout), .hb_ram_addr (hb_ram_addr), .ca_ram_addr0 (ca_ram_addr0), .ca_ram_addr1 (ca_ram_addr1) ); // always @ (posedge hb_clk) xyw_csn_d <= hb_xyw_csn; /****************************************************************/ /* DATAPATH FUNNEL SHIFTER */ /* DATAPATH COLOR SELECTOR */ /* (grouped for synthesis) */ /****************************************************************/ ded_funcol #(.BYTES (BYTES)) U_FUNCOL ( .mclock (mclock), .stpl_4 (stpl_4), .apat_4 (apat_4), .ps32_4 (ps32_4), .ps16_4 (ps16_4), .ps8_4 (ps8_4), .lt_actv_4 (line_actv_4), .fore_4 (fore_4), .back_4 (back_4), .solid_4 (solid_4), .pc_col (de_pc_data), `ifdef BYTE16 .rad (ca_rad[6:0]), `elsif BYTE8 .rad (ca_rad[5:0]), `else .rad (ca_rad[4:0]), `endif .bsd0 (ca_dout0), .bsd1 (ca_dout1), .col_dat (mc_fb_out), .trns_msk (trns_msk), .cx_sel (cx_sel) ); /****************************************************************/ /* MASK GENERATOR */ /****************************************************************/ ded_mskgen #(.BYTES (BYTES)) U_MSKGEN ( .de_clk (de_clk), .de_rstn (de_rstn), .mclock (mclock), .mc_acken (mc_acken), .mc_popen (mc_popen), .ld_msk (dx_ld_msk), .line_actv_4 (line_actv_4), .blt_actv_4 (blt_actv_4), .clp_4 (clp_4), .mem_req (dx_mem_req), .mem_rd (dx_mem_rd), .pc_msk_in (de_pc_mask), .clpx_bus_2 (dx_clpx_bus_2), .x_bus (dx_dstx), .xalu_bus (dx_xalu[6:0]), .trnsp_4 (trnsp_4), .trns_msk_in (trns_msk), .ps16_2 (ps16_2), .ps32_2 (ps32_2), .mc_eop (mc_eop), .mask_4 (mask_4), .lft_enc_4 (lft_enc_4), .rht_enc_4 (rht_enc_4), .clp_min_4 (clp_min_4), .clp_max_4 (clp_max_4), .cmin_enc_4 (cmin_enc_4), .cmax_enc_4 (cmax_enc_4), .y_clip_4 (y_clip_4), .sol_4 (sol_4), .eol_4 (eol_4), .x_count_4 (x_bus_4), .mc_eop4 (mc_eop4), .pixel_msk (mc_pixel_msk), .clip_ind (clip_ind), .lft_enc_2 (lft_enc_2), .rht_enc_2 (rht_enc_2), .clp_min_2 (clp_min_2), .clp_max_2 (clp_max_2), .cmin_enc_2 (cmin_enc_2), .cmax_enc_2 (cmax_enc_2) ); /****************************************************************/ /* LINE PIXEL CACHE */ /****************************************************************/ ded_pix_cache #(.BYTES (BYTES)) U_PIX ( .de_clk (de_clk), .mc_clk (mclock), // .de_rstn (de_rstn), .de_rstn (hb_rstn), .dorg_2 (dorg_2), .sorg_2 (sorg_2), .dptch_2 (dptch_2), .sptch_2 (sptch_2), .ld_wcnt (ld_wcnt), .fx_1 (fx_1), .rmw (rmw), .ps8_2 (ps8_2), .ps16_2 (ps16_2), .ps32_2 (ps32_2), .fore_2 (fore_2), .back_2 (back_2), .solid_2 (dr_solid_2), .dr_trnsp_2 (dr_trnsp_2), // 2D Interface. .dx_pc_ld (dx_pc_ld), .dx_clip (clip), .dx_real_dstx (real_dstx), .dx_real_dsty (real_dsty), .dx_pc_msk_last (pc_msk_last), .dx_fg_bgn (dx_fg_bgn), .dx_last_pixel (last_pixel), // 3D Interface. `ifdef CORE_3D .valid_3d (valid_3d), .fg_bgn_3d (fg_bgn_3d), .x_out_3d (x_out_3d), .y_out_3d (y_out_3d), .pc_msk_last_3d (msk_last_3d), .pc_last_3d (last_3d), .pixel_3d (pixel_3d), .z_3d (z_3d), .alpha_3d (alpha_3d), .z_op (z_ctrl[2:0]), .z_en (z_ctrl[3]), .z_ro (z_ctrl[4]), .zorg_2 (z_org), .zptch_2 (z_ptch), .active_3d_2 (active_3d_2), `else .valid_3d (1'b0), .fg_bgn_3d (1'b0), .x_out_3d (16'h0), .y_out_3d (16'h0), .pc_msk_last_3d (1'b0), .pc_last_3d (1'b0), .pixel_3d (32'h0), .alpha_3d (8'h0), .z_op (3'b0), .z_en (1'b0), .z_ro (1'b0), .zorg_2 (28'b0), .zptch_2 (12'b0), .active_3d_2 (1'b0), `endif // .de_pc_pop (de_pc_pop), .mc_popen (mc_popen), .srcx (srcx), .srcy (srcy), .dstx (dx_dstx), .dsty (dsty), .imem_rd (dx_mem_rd), .dx_mem_req (dx_mem_req), .mask_2 (de_pln_msk_2), .stpl_2 (stpl_2), .dr_apat_2 (dr_apat_2), .dr_clp_2 (dr_clp_2), .rad_flg_2 (rad_flg_2), .strt_wrd_2 (strt_wrd_2), .strt_byt_2 (strt_byt_2), .strt_bit_2 (strt_bit_2), .ps_2 (ps_2), .bsrcr_2 (bsrcr_2), .bdstr_2 (bdstr_2), .blend_en_2 (blend_en_2), .blend_reg_en_2 (blend_reg_en_2), .bsrc_alpha_2 (bsrc_alpha_2), .bdst_alpha_2 (bdst_alpha_2), .rop_2 (rop_2), .kcol_2 (kcol_2), .key_ctrl_2 (key_ctrl_2), .lft_enc_2 (lft_enc_2), .rht_enc_2 (rht_enc_2), .clp_min_2 (clp_min_2), .clp_max_2 (clp_max_2), .cmin_enc_2 (cmin_enc_2), .cmax_enc_2 (cmax_enc_2), .y_clip_2 (y_clip_2), .sol_2 (dx_sol_2), .eol_2 (dx_eol_2), .rst_wad_flg_2 (rst_wad_flg_2), .frst8_2 (frst8_2), .rad_flg_3 (rad_flg_3), .strt_wrd_3 (strt_wrd_3), .strt_byt_3 (strt_byt_3), .strt_bit_3 (strt_bit_3), .strt_wrd_4 (strt_wrd_4), .strt_byt_4 (strt_byt_4), .strt_bit_4 (strt_bit_4), .px_a (mc_fb_a), .px_col (de_pc_data), .px_msk_color (de_pc_mask), .de_mc_address (de_mc_address), .de_mc_read (de_mc_read), .de_mc_rmw (de_mc_rmw), .de_mc_wcnt (de_mc_wcnt), .pc_dirty (pc_dirty), .de_pc_empty (de_pc_empty), .pc_pending (pipe_pending), .pc_busy (pc_busy), .pc_busy_3d (pc_busy_3d), .fore_4 (fore_4), .back_4 (back_4), .blt_actv_4 (blt_actv_4), .stpl_4 (stpl_4), .ps8_4 (ps8_4), .ps16_4 (ps16_4), .ps32_4 (ps32_4), .trnsp_4 (trnsp_4), .solid_4 (solid_4), .clp_4 (clp_4), .line_actv_4 (line_actv_4), .apat_4 (apat_4), .mask_4 (mask_4), .ps_4 (ps_4), .bsrcr_4 (bsrcr_4), .bdstr_4 (bdstr_4), .blend_en_4 (blend_en_4), .blend_reg_en_4 (blend_reg_en_4), .bsrc_alpha_4 (bsrc_alpha_4), .bdst_alpha_4 (bdst_alpha_4), .rop_4 (rop_4), .kcol_4 (kcol_4), .key_ctrl_4 (key_ctrl_4), .lft_enc_4 (lft_enc_4), .rht_enc_4 (rht_enc_4), .clp_min_4 (clp_min_4), .clp_max_4 (clp_max_4), .cmin_enc_4 (cmin_enc_4), .cmax_enc_4 (cmax_enc_4), .y_clip_4 (y_clip_4), .sol_4 (sol_4), .eol_4 (eol_4), .x_bus_4 (x_bus_4), .rst_wad_flg_3 (rst_wad_flg_3), .mc_read_3 (mc_read_3), .sol_3 (sol_3), .mc_acken (mc_acken), .frst8_4 (frst8_4), .pc_empty (pc_empty), .pc_last (pc_last), .z_en_4 (z_ctrl_4[3]), .z_ro_4 (z_ctrl_4[4]), .z_op_4 (z_ctrl_4[2:0]), .z_address_4 (z_address_4), .z_out (z_out) ); assign pc_mc_busy = pc_busy; assign psize_4 = {ps32_4,ps16_4,ps8_4}; // Needed for cactrl endmodule

/************************************************************************** * * File Name: MT48LC4M16A2.V * Version: 2.1 * Date: June 6th, 2002 * Model: BUS Functional * Simulator: Model Technology * * Dependencies: None * * Email: modelsupport@micron.com * Company: Micron Technology, Inc. * Model: MT48LC4M16A2 (1Meg x 16 x 4 Banks) * * Description: Micron 64Mb SDRAM Verilog model * * Limitation: - Doesn't check for 4096 cycle refresh * * Note: - Set simulator resolution to "ps" accuracy * - Set Debug = 0 to disable $display messages * * Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY * WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR * A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. * * Copyright © 2001 Micron Semiconductor Products, Inc. * All rights researved * * Rev Author Date Changes * --- -------------------------- --------------------------------------- * 2.1 SH 06/06/2002 - Typo in bank multiplex * Micron Technology Inc. * * 2.0 SH 04/30/2002 - Second release * Micron Technology Inc. * **************************************************************************/ `timescale 1ns / 1ps module mt48lc4m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm); parameter addr_bits = 12; parameter data_bits = 16; parameter col_bits = 8; parameter mem_sizes = 1048575; inout [data_bits - 1 : 0] Dq; input [addr_bits - 1 : 0] Addr; input [1 : 0] Ba; input Clk; input Cke; input Cs_n; input Ras_n; input Cas_n; input We_n; input [1 : 0] Dqm; reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes]; reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes]; reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes]; reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes]; reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr; reg [addr_bits - 1 : 0] Mode_reg; reg [data_bits - 1 : 0] Dq_reg, Dq_dqm; reg [col_bits - 1 : 0] Col_temp, Burst_counter; reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks) reg Auto_precharge [0 : 3]; // RW Auto Precharge (Bank) reg Read_precharge [0 : 3]; // R Auto Precharge reg Write_precharge [0 : 3]; // W Auto Precharge reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge reg [1 : 0] RW_interrupt_bank; // RW Interrupt Bank integer RW_interrupt_counter [0 : 3]; // RW Interrupt Counter integer Count_precharge [0 : 3]; // RW Auto Precharge Counter reg Data_in_enable; reg Data_out_enable; reg [1 : 0] Bank, Prev_bank; reg [addr_bits - 1 : 0] Row; reg [col_bits - 1 : 0] Col, Col_brst; // Internal system clock reg CkeZ, Sys_clk; // Commands Decode wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n; wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n; wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n; wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n; wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n; wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n; wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n; // Burst Length Decode wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0]; wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0]; wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0]; wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; wire Burst_length_f = Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; // CAS Latency Decode wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4]; wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4]; // Write Burst Mode wire Write_burst_mode = Mode_reg[9]; wire Debug = 1'b1; // Debug messages : 1 = On wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ assign Dq = Dq_reg; // DQ buffer // Commands Operation `define ACT 0 `define NOP 1 `define READ 2 `define WRITE 3 `define PRECH 4 `define A_REF 5 `define BST 6 `define LMR 7 // Timing Parameters for -7E PC133 CL2 parameter tAC = 5.4; parameter tHZ = 5.4; parameter tOH = 3.0; parameter tMRD = 2.0; // 2 Clk Cycles parameter tRAS = 37.0; parameter tRC = 60.0; parameter tRCD = 15.0; parameter tRFC = 66.0; parameter tRP = 15.0; parameter tRRD = 14.0; parameter tWRa = 7.0; // A2 Version - Auto precharge mode (1 Clk + 7 ns) parameter tWRm = 14.0; // A2 Version - Manual precharge mode (14 ns) // Timing Check variable time MRD_chk; time WR_chkm [0 : 3]; time RFC_chk, RRD_chk; time RC_chk0, RC_chk1, RC_chk2, RC_chk3; time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; time RP_chk0, RP_chk1, RP_chk2, RP_chk3; initial begin Dq_reg = {data_bits{1'bz}}; Data_in_enable = 0; Data_out_enable = 0; Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1; Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0; WR_chkm[0] = 0; WR_chkm[1] = 0; WR_chkm[2] = 0; WR_chkm[3] = 0; RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0; RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0; MRD_chk = 0; RFC_chk = 0; RRD_chk = 0; RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0; RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0; RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0; RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0; $timeformat (-9, 1, " ns", 12); end // System clock generator always begin @ (posedge Clk) begin Sys_clk = CkeZ; CkeZ = Cke; end @ (negedge Clk) begin Sys_clk = 1'b0; end end always @ (posedge Sys_clk) begin // Internal Commamd Pipelined Command[0] = Command[1]; Command[1] = Command[2]; Command[2] = Command[3]; Command[3] = `NOP; Col_addr[0] = Col_addr[1]; Col_addr[1] = Col_addr[2]; Col_addr[2] = Col_addr[3]; Col_addr[3] = {col_bits{1'b0}}; Bank_addr[0] = Bank_addr[1]; Bank_addr[1] = Bank_addr[2]; Bank_addr[2] = Bank_addr[3]; Bank_addr[3] = 2'b0; Bank_precharge[0] = Bank_precharge[1]; Bank_precharge[1] = Bank_precharge[2]; Bank_precharge[2] = Bank_precharge[3]; Bank_precharge[3] = 2'b0; A10_precharge[0] = A10_precharge[1]; A10_precharge[1] = A10_precharge[2]; A10_precharge[2] = A10_precharge[3]; A10_precharge[3] = 1'b0; // Dqm pipeline for Read Dqm_reg0 = Dqm_reg1; Dqm_reg1 = Dqm; // Read or Write with Auto Precharge Counter if (Auto_precharge[0] === 1'b1) begin Count_precharge[0] = Count_precharge[0] + 1; end if (Auto_precharge[1] === 1'b1) begin Count_precharge[1] = Count_precharge[1] + 1; end if (Auto_precharge[2] === 1'b1) begin Count_precharge[2] = Count_precharge[2] + 1; end if (Auto_precharge[3] === 1'b1) begin Count_precharge[3] = Count_precharge[3] + 1; end // Read or Write Interrupt Counter if (RW_interrupt_write[0] === 1'b1) begin RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1; end if (RW_interrupt_write[1] === 1'b1) begin RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1; end if (RW_interrupt_write[2] === 1'b1) begin RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1; end if (RW_interrupt_write[3] === 1'b1) begin RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1; end // tMRD Counter MRD_chk = MRD_chk + 1; // Auto Refresh if (Aref_enable === 1'b1) begin if (Debug) begin $display ("%m : at time %t AREF : Auto Refresh", $time); end // Auto Refresh to Auto Refresh if ($time - RFC_chk < tRFC) begin $display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $time); end // Precharge to Auto Refresh if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin $display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time); end // Precharge to Refresh if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin $display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time); end // Load Mode Register to Auto Refresh if (MRD_chk < tMRD) begin $display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time); end // Record Current tRFC time RFC_chk = $time; end // Load Mode Register if (Mode_reg_enable === 1'b1) begin // Register Mode Mode_reg = Addr; // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode if (Debug) begin $display ("%m : at time %t LMR : Load Mode Register", $time); // CAS Latency case (Addr[6 : 4]) 3'b010 : $display ("%m : CAS Latency = 2"); 3'b011 : $display ("%m : CAS Latency = 3"); default : $display ("%m : CAS Latency = Reserved"); endcase // Burst Length case (Addr[2 : 0]) 3'b000 : $display ("%m : Burst Length = 1"); 3'b001 : $display ("%m : Burst Length = 2"); 3'b010 : $display ("%m : Burst Length = 4"); 3'b011 : $display ("%m : Burst Length = 8"); 3'b111 : $display ("%m : Burst Length = Full"); default : $display ("%m : Burst Length = Reserved"); endcase // Burst Type if (Addr[3] === 1'b0) begin $display ("%m : Burst Type = Sequential"); end else if (Addr[3] === 1'b1) begin $display ("%m : Burst Type = Interleaved"); end else begin $display ("%m : Burst Type = Reserved"); end // Write Burst Mode if (Addr[9] === 1'b0) begin $display ("%m : Write Burst Mode = Programmed Burst Length"); end else if (Addr[9] === 1'b1) begin $display ("%m : Write Burst Mode = Single Location Access"); end else begin $display ("%m : Write Burst Mode = Reserved"); end end // Precharge to Load Mode Register if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin $display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time); end // Precharge to Load Mode Register if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin $display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time); end // Auto Refresh to Load Mode Register if ($time - RFC_chk < tRFC) begin $display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $time); end // Load Mode Register to Load Mode Register if (MRD_chk < tMRD) begin $display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time); end // Reset MRD Counter MRD_chk = 0; end // Active Block (Latch Bank Address and Row Address) if (Active_enable === 1'b1) begin // Activate an open bank can corrupt data if ((Ba === 2'b00 && Act_b0 === 1'b1) || (Ba === 2'b01 && Act_b1 === 1'b1) || (Ba === 2'b10 && Act_b2 === 1'b1) || (Ba === 2'b11 && Act_b3 === 1'b1)) begin $display ("%m : at time %t ERROR: Bank already activated -- data can be corrupted", $time); end // Activate Bank 0 if (Ba === 2'b00 && Pc_b0 === 1'b1) begin // Debug Message if (Debug) begin $display ("%m : at time %t ACT : Bank = 0 Row = %d", $time, Addr); end // ACTIVE to ACTIVE command period if ($time - RC_chk0 < tRC) begin $display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time); end // Precharge to Activate Bank 0 if ($time - RP_chk0 < tRP) begin $display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time); end // Record variables Act_b0 = 1'b1; Pc_b0 = 1'b0; B0_row_addr = Addr [addr_bits - 1 : 0]; RAS_chk0 = $time; RC_chk0 = $time; RCD_chk0 = $time; end if (Ba == 2'b01 && Pc_b1 == 1'b1) begin // Debug Message if (Debug) begin $display ("%m : at time %t ACT : Bank = 1 Row = %d", $time, Addr); end // ACTIVE to ACTIVE command period if ($time - RC_chk1 < tRC) begin $display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time); end // Precharge to Activate Bank 1 if ($time - RP_chk1 < tRP) begin $display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time); end // Record variables Act_b1 = 1'b1; Pc_b1 = 1'b0; B1_row_addr = Addr [addr_bits - 1 : 0]; RAS_chk1 = $time; RC_chk1 = $time; RCD_chk1 = $time; end if (Ba == 2'b10 && Pc_b2 == 1'b1) begin // Debug Message if (Debug) begin $display ("%m : at time %t ACT : Bank = 2 Row = %d", $time, Addr); end // ACTIVE to ACTIVE command period if ($time - RC_chk2 < tRC) begin $display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time); end // Precharge to Activate Bank 2 if ($time - RP_chk2 < tRP) begin $display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time); end // Record variables Act_b2 = 1'b1; Pc_b2 = 1'b0; B2_row_addr = Addr [addr_bits - 1 : 0]; RAS_chk2 = $time; RC_chk2 = $time; RCD_chk2 = $time; end if (Ba == 2'b11 && Pc_b3 == 1'b1) begin // Debug Message if (Debug) begin $display ("%m : at time %t ACT : Bank = 3 Row = %d", $time, Addr); end // ACTIVE to ACTIVE command period if ($time - RC_chk3 < tRC) begin $display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time); end // Precharge to Activate Bank 3 if ($time - RP_chk3 < tRP) begin $display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time); end // Record variables Act_b3 = 1'b1; Pc_b3 = 1'b0; B3_row_addr = Addr [addr_bits - 1 : 0]; RAS_chk3 = $time; RC_chk3 = $time; RCD_chk3 = $time; end // Active Bank A to Active Bank B if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin $display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba); end // Auto Refresh to Activate if ($time - RFC_chk < tRFC) begin $display ("%m : at time %t ERROR: tRFC violation during Activate bank = %d", $time, Ba); end // Load Mode Register to Active if (MRD_chk < tMRD ) begin $display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba); end // Record variables for checking violation RRD_chk = $time; Prev_bank = Ba; end // Precharge Block if (Prech_enable == 1'b1) begin // Load Mode Register to Precharge if ($time - MRD_chk < tMRD) begin $display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time); end // Precharge Bank 0 if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin Act_b0 = 1'b0; Pc_b0 = 1'b1; RP_chk0 = $time; // Activate to Precharge if ($time - RAS_chk0 < tRAS) begin $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); end // tWR violation check for write if ($time - WR_chkm[0] < tWRm) begin $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); end end // Precharge Bank 1 if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin Act_b1 = 1'b0; Pc_b1 = 1'b1; RP_chk1 = $time; // Activate to Precharge if ($time - RAS_chk1 < tRAS) begin $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); end // tWR violation check for write if ($time - WR_chkm[1] < tWRm) begin $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); end end // Precharge Bank 2 if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin Act_b2 = 1'b0; Pc_b2 = 1'b1; RP_chk2 = $time; // Activate to Precharge if ($time - RAS_chk2 < tRAS) begin $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); end // tWR violation check for write if ($time - WR_chkm[2] < tWRm) begin $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); end end // Precharge Bank 3 if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin Act_b3 = 1'b0; Pc_b3 = 1'b1; RP_chk3 = $time; // Activate to Precharge if ($time - RAS_chk3 < tRAS) begin $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); end // tWR violation check for write if ($time - WR_chkm[3] < tWRm) begin $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); end end // Terminate a Write Immediately (if same bank or all banks) if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin Data_in_enable = 1'b0; end // Precharge Command Pipeline for Read if (Cas_latency_3 === 1'b1) begin Command[2] = `PRECH; Bank_precharge[2] = Ba; A10_precharge[2] = Addr[10]; end else if (Cas_latency_2 === 1'b1) begin Command[1] = `PRECH; Bank_precharge[1] = Ba; A10_precharge[1] = Addr[10]; end end // Burst terminate if (Burst_term === 1'b1) begin // Terminate a Write Immediately if (Data_in_enable == 1'b1) begin Data_in_enable = 1'b0; end // Terminate a Read Depend on CAS Latency if (Cas_latency_3 === 1'b1) begin Command[2] = `BST; end else if (Cas_latency_2 == 1'b1) begin Command[1] = `BST; end // Display debug message if (Debug) begin $display ("%m : at time %t BST : Burst Terminate",$time); end end // Read, Write, Column Latch if (Read_enable === 1'b1) begin // Check to see if bank is open (ACT) if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin $display("%m : at time %t ERROR: Bank is not Activated for Read", $time); end // Activate to Read or Write if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) || (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) || (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) || (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin $display("%m : at time %t ERROR: tRCD violation during Read", $time); end // CAS Latency pipeline if (Cas_latency_3 == 1'b1) begin Command[2] = `READ; Col_addr[2] = Addr; Bank_addr[2] = Ba; end else if (Cas_latency_2 == 1'b1) begin Command[1] = `READ; Col_addr[1] = Addr; Bank_addr[1] = Ba; end // Read interrupt Write (terminate Write immediately) if (Data_in_enable == 1'b1) begin Data_in_enable = 1'b0; // Interrupting a Write with Autoprecharge if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin RW_interrupt_write[RW_interrupt_bank] = 1'b1; RW_interrupt_counter[RW_interrupt_bank] = 0; // Display debug message if (Debug) begin $display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $time); end end end // Write with Auto Precharge if (Addr[10] == 1'b1) begin Auto_precharge[Ba] = 1'b1; Count_precharge[Ba] = 0; RW_interrupt_bank = Ba; Read_precharge[Ba] = 1'b1; end end // Write Command if (Write_enable == 1'b1) begin // Activate to Write if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin $display("%m : at time %t ERROR: Bank is not Activated for Write", $time); end // Activate to Read or Write if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) || (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) || (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) || (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin $display("%m : at time %t ERROR: tRCD violation during Read", $time); end // Latch Write command, Bank, and Column Command[0] = `WRITE; Col_addr[0] = Addr; Bank_addr[0] = Ba; // Write interrupt Write (terminate Write immediately) if (Data_in_enable == 1'b1) begin Data_in_enable = 1'b0; // Interrupting a Write with Autoprecharge if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin RW_interrupt_write[RW_interrupt_bank] = 1'b1; // Display debug message if (Debug) begin $display ("%m : at time %t NOTE : Read Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank); end end end // Write interrupt Read (terminate Read immediately) if (Data_out_enable == 1'b1) begin Data_out_enable = 1'b0; // Interrupting a Read with Autoprecharge if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin RW_interrupt_read[RW_interrupt_bank] = 1'b1; // Display debug message if (Debug) begin $display ("%m : at time %t NOTE : Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank); end end end // Write with Auto Precharge if (Addr[10] == 1'b1) begin Auto_precharge[Ba] = 1'b1; Count_precharge[Ba] = 0; RW_interrupt_bank = Ba; Write_precharge[Ba] = 1'b1; end end /* Write with Auto Precharge Calculation The device start internal precharge when: 1. Meet minimum tRAS requirement and 2. tWR cycle(s) after last valid data or 3. Interrupt by a Read or Write (with or without Auto Precharge) Note: Model is starting the internal precharge 1 cycle after they meet all the requirement but tRP will be compensate for the time after the 1 cycle. */ if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin if ((($time - RAS_chk0 >= tRAS) && // Case 1 (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 2 (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) || (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) || (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) || (RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin // Case 3 Auto_precharge[0] = 1'b0; Write_precharge[0] = 1'b0; RW_interrupt_write[0] = 1'b0; Pc_b0 = 1'b1; Act_b0 = 1'b0; RP_chk0 = $time + tWRa; if (Debug) begin $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); end end end if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin if ((($time - RAS_chk1 >= tRAS) && // Case 1 (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || // Case 2 (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) || (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) || (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) || (RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin // Case 3 Auto_precharge[1] = 1'b0; Write_precharge[1] = 1'b0; RW_interrupt_write[1] = 1'b0; Pc_b1 = 1'b1; Act_b1 = 1'b0; RP_chk1 = $time + tWRa; if (Debug) begin $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); end end end if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin if ((($time - RAS_chk2 >= tRAS) && // Case 1 (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || // Case 2 (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) || (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) || (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) || (RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin // Case 3 Auto_precharge[2] = 1'b0; Write_precharge[2] = 1'b0; RW_interrupt_write[2] = 1'b0; Pc_b2 = 1'b1; Act_b2 = 1'b0; RP_chk2 = $time + tWRa; if (Debug) begin $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); end end end if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin if ((($time - RAS_chk3 >= tRAS) && // Case 1 (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || // Case 2 (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) || (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) || (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) || (RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin // Case 3 Auto_precharge[3] = 1'b0; Write_precharge[3] = 1'b0; RW_interrupt_write[3] = 1'b0; Pc_b3 = 1'b1; Act_b3 = 1'b0; RP_chk3 = $time + tWRa; if (Debug) begin $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); end end end // Read with Auto Precharge Calculation // The device start internal precharge: // 1. Meet minimum tRAS requirement // and 2. CAS Latency - 1 cycles before last burst // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin if ((($time - RAS_chk0 >= tRAS) && // Case 1 ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 2 (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) || (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) || (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) || (RW_interrupt_read[0] == 1'b1)) begin // Case 3 Pc_b0 = 1'b1; Act_b0 = 1'b0; RP_chk0 = $time; Auto_precharge[0] = 1'b0; Read_precharge[0] = 1'b0; RW_interrupt_read[0] = 1'b0; if (Debug) begin $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); end end end if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin if ((($time - RAS_chk1 >= tRAS) && ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) || (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) || (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) || (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) || (RW_interrupt_read[1] == 1'b1)) begin Pc_b1 = 1'b1; Act_b1 = 1'b0; RP_chk1 = $time; Auto_precharge[1] = 1'b0; Read_precharge[1] = 1'b0; RW_interrupt_read[1] = 1'b0; if (Debug) begin $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); end end end if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin if ((($time - RAS_chk2 >= tRAS) && ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) || (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) || (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) || (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) || (RW_interrupt_read[2] == 1'b1)) begin Pc_b2 = 1'b1; Act_b2 = 1'b0; RP_chk2 = $time; Auto_precharge[2] = 1'b0; Read_precharge[2] = 1'b0; RW_interrupt_read[2] = 1'b0; if (Debug) begin $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); end end end if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin if ((($time - RAS_chk3 >= tRAS) && ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) || (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) || (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) || (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) || (RW_interrupt_read[3] == 1'b1)) begin Pc_b3 = 1'b1; Act_b3 = 1'b0; RP_chk3 = $time; Auto_precharge[3] = 1'b0; Read_precharge[3] = 1'b0; RW_interrupt_read[3] = 1'b0; if (Debug) begin $display("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); end end end // Internal Precharge or Bst if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin if (Data_out_enable == 1'b1) begin Data_out_enable = 1'b0; end end end else if (Command[0] == `BST) begin // BST terminate a read to current bank if (Data_out_enable == 1'b1) begin Data_out_enable = 1'b0; end end if (Data_out_enable == 1'b0) begin Dq_reg <= #tOH {data_bits{1'bz}}; end // Detect Read or Write command if (Command[0] == `READ) begin Bank = Bank_addr[0]; Col = Col_addr[0]; Col_brst = Col_addr[0]; case (Bank_addr[0]) 2'b00 : Row = B0_row_addr; 2'b01 : Row = B1_row_addr; 2'b10 : Row = B2_row_addr; 2'b11 : Row = B3_row_addr; endcase Burst_counter = 0; Data_in_enable = 1'b0; Data_out_enable = 1'b1; end else if (Command[0] == `WRITE) begin Bank = Bank_addr[0]; Col = Col_addr[0]; Col_brst = Col_addr[0]; case (Bank_addr[0]) 2'b00 : Row = B0_row_addr; 2'b01 : Row = B1_row_addr; 2'b10 : Row = B2_row_addr; 2'b11 : Row = B3_row_addr; endcase Burst_counter = 0; Data_in_enable = 1'b1; Data_out_enable = 1'b0; end // DQ buffer (Driver/Receiver) if (Data_in_enable == 1'b1) begin // Writing Data to Memory // Array buffer case (Bank) 2'b00 : Dq_dqm = Bank0 [{Row, Col}]; 2'b01 : Dq_dqm = Bank1 [{Row, Col}]; 2'b10 : Dq_dqm = Bank2 [{Row, Col}]; 2'b11 : Dq_dqm = Bank3 [{Row, Col}]; endcase // Dqm operation if (Dqm[0] == 1'b0) begin Dq_dqm [ 7 : 0] = Dq [ 7 : 0]; end if (Dqm[1] == 1'b0) begin Dq_dqm [15 : 8] = Dq [15 : 8]; end // Write to memory case (Bank) 2'b00 : Bank0 [{Row, Col}] = Dq_dqm; 2'b01 : Bank1 [{Row, Col}] = Dq_dqm; 2'b10 : Bank2 [{Row, Col}] = Dq_dqm; 2'b11 : Bank3 [{Row, Col}] = Dq_dqm; endcase // Display debug message if (Dqm !== 2'b11) begin // Record tWR for manual precharge WR_chkm [Bank] = $time; if (Debug) begin $display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq_dqm); end end else begin if (Debug) begin $display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); end end // Advance burst counter subroutine #tHZ Burst_decode; end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory // Array buffer case (Bank) 2'b00 : Dq_dqm = Bank0[{Row, Col}]; 2'b01 : Dq_dqm = Bank1[{Row, Col}]; 2'b10 : Dq_dqm = Bank2[{Row, Col}]; 2'b11 : Dq_dqm = Bank3[{Row, Col}]; endcase // Dqm operation if (Dqm_reg0 [0] == 1'b1) begin Dq_dqm [ 7 : 0] = 8'bz; end if (Dqm_reg0 [1] == 1'b1) begin Dq_dqm [15 : 8] = 8'bz; end // Display debug message if (Dqm_reg0 !== 2'b11) begin Dq_reg = #tAC Dq_dqm; if (Debug) begin $display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq_reg); end end else begin Dq_reg = #tHZ {data_bits{1'bz}}; if (Debug) begin $display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); end end // Advance burst counter subroutine Burst_decode; end end // Burst counter decode task Burst_decode; begin // Advance Burst Counter Burst_counter = Burst_counter + 1; // Burst Type if (Mode_reg[3] == 1'b0) begin // Sequential Burst Col_temp = Col + 1; end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst Col_temp[2] = Burst_counter[2] ^ Col_brst[2]; Col_temp[1] = Burst_counter[1] ^ Col_brst[1]; Col_temp[0] = Burst_counter[0] ^ Col_brst[0]; end // Burst Length if (Burst_length_2) begin // Burst Length = 2 Col [0] = Col_temp [0]; end else if (Burst_length_4) begin // Burst Length = 4 Col [1 : 0] = Col_temp [1 : 0]; end else if (Burst_length_8) begin // Burst Length = 8 Col [2 : 0] = Col_temp [2 : 0]; end else begin // Burst Length = FULL Col = Col_temp; end // Burst Read Single Write if (Write_burst_mode == 1'b1) begin Data_in_enable = 1'b0; end // Data Counter if (Burst_length_1 == 1'b1) begin if (Burst_counter >= 1) begin Data_in_enable = 1'b0; Data_out_enable = 1'b0; end end else if (Burst_length_2 == 1'b1) begin if (Burst_counter >= 2) begin Data_in_enable = 1'b0; Data_out_enable = 1'b0; end end else if (Burst_length_4 == 1'b1) begin if (Burst_counter >= 4) begin Data_in_enable = 1'b0; Data_out_enable = 1'b0; end end else if (Burst_length_8 == 1'b1) begin if (Burst_counter >= 8) begin Data_in_enable = 1'b0; Data_out_enable = 1'b0; end end end endtask // Timing Parameters for -7E (133 MHz @ CL2) specify specparam tAH = 0.8, // Addr, Ba Hold Time tAS = 1.5, // Addr, Ba Setup Time tCH = 2.5, // Clock High-Level Width tCL = 2.5, // Clock Low-Level Width tCK = 7.0, // Clock Cycle Time tDH = 0.8, // Data-in Hold Time tDS = 1.5, // Data-in Setup Time tCKH = 0.8, // CKE Hold Time tCKS = 1.5, // CKE Setup Time tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time $width (posedge Clk, tCH); $width (negedge Clk, tCL); $period (negedge Clk, tCK); $period (posedge Clk, tCK); $setuphold(posedge Clk, Cke, tCKS, tCKH); $setuphold(posedge Clk, Cs_n, tCMS, tCMH); $setuphold(posedge Clk, Cas_n, tCMS, tCMH); $setuphold(posedge Clk, Ras_n, tCMS, tCMH); $setuphold(posedge Clk, We_n, tCMS, tCMH); $setuphold(posedge Clk, Addr, tAS, tAH); $setuphold(posedge Clk, Ba, tAS, tAH); $setuphold(posedge Clk, Dqm, tCMS, tCMH); $setuphold(posedge Dq_chk, Dq, tDS, tDH); endspecify endmodule

//----------------------------------------------------------------------------- // // (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // // Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express // File : pcie3_7x_0_pipe_sync.v // Version : 3.0 //----------------------------------------------------------------------------// // Filename : pcie3_7x_0_pipe_sync.v // Description : PIPE Sync Module for 7 Series Transceiver // Version : 20.1 //------------------------------------------------------------------------------ // PCIE_TXSYNC_MODE : 0 = Manual TX sync (default). // : 1 = Auto TX sync. // PCIE_RXSYNC_MODE : 0 = Manual RX sync (default). // : 1 = Auto RX sync. //------------------------------------------------------------------------------ `timescale 1ns / 1ps //---------- PIPE Sync Module -------------------------------------------------- module pcie3_7x_0_pipe_sync # ( parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only parameter PCIE_RXBUF_EN = "TRUE", // PCIe TX buffer enable for Gen3 only parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode parameter PCIE_LANE = 1, // PCIe lane parameter PCIE_LINK_SPEED = 3, // PCIe link speed parameter BYPASS_TXDELAY_ALIGN = 0, // Bypass TX delay align parameter BYPASS_RXDELAY_ALIGN = 0 // Bypass RX delay align ) ( //---------- Input ------------------------------------- input SYNC_CLK, input SYNC_RST_N, input SYNC_SLAVE, input SYNC_GEN3, input SYNC_RATE_IDLE, input SYNC_MMCM_LOCK, input SYNC_RXELECIDLE, input SYNC_RXCDRLOCK, input SYNC_ACTIVE_LANE, input SYNC_TXSYNC_START, input SYNC_TXPHINITDONE, input SYNC_TXDLYSRESETDONE, input SYNC_TXPHALIGNDONE, input SYNC_TXSYNCDONE, input SYNC_RXSYNC_START, input SYNC_RXDLYSRESETDONE, input SYNC_RXPHALIGNDONE_M, input SYNC_RXPHALIGNDONE_S, input SYNC_RXSYNC_DONEM_IN, input SYNC_RXSYNCDONE, //---------- Output ------------------------------------ output SYNC_TXPHDLYRESET, output SYNC_TXPHALIGN, output SYNC_TXPHALIGNEN, output SYNC_TXPHINIT, output SYNC_TXDLYBYPASS, output SYNC_TXDLYSRESET, output SYNC_TXDLYEN, output SYNC_TXSYNC_DONE, output [ 5:0] SYNC_FSM_TX, output SYNC_RXPHALIGN, output SYNC_RXPHALIGNEN, output SYNC_RXDLYBYPASS, output SYNC_RXDLYSRESET, output SYNC_RXDLYEN, output SYNC_RXDDIEN, output SYNC_RXSYNC_DONEM_OUT, output SYNC_RXSYNC_DONE, output [ 6:0] SYNC_FSM_RX ); //---------- Input Register ---------------------------- (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg3; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg3; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg3; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg3; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg3; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg1; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg2; (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg2; //---------- Output Register --------------------------- reg txdlyen = 1'd0; reg txsync_done = 1'd0; reg [ 5:0] fsm_tx = 6'd0; reg rxdlyen = 1'd0; reg rxsync_done = 1'd0; reg [ 6:0] fsm_rx = 7'd0; //---------- FSM --------------------------------------- localparam FSM_TXSYNC_IDLE = 6'b000001; localparam FSM_MMCM_LOCK = 6'b000010; localparam FSM_TXSYNC_START = 6'b000100; localparam FSM_TXPHINITDONE = 6'b001000; // Manual TX sync only localparam FSM_TXSYNC_DONE1 = 6'b010000; localparam FSM_TXSYNC_DONE2 = 6'b100000; localparam FSM_RXSYNC_IDLE = 7'b0000001; localparam FSM_RXCDRLOCK = 7'b0000010; localparam FSM_RXSYNC_START = 7'b0000100; localparam FSM_RXSYNC_DONE1 = 7'b0001000; localparam FSM_RXSYNC_DONE2 = 7'b0010000; localparam FSM_RXSYNC_DONES = 7'b0100000; localparam FSM_RXSYNC_DONEM = 7'b1000000; //---------- Input FF ---------------------------------------------------------- always @ (posedge SYNC_CLK) begin if (!SYNC_RST_N) begin //---------- 1st Stage FF -------------------------- gen3_reg1 <= 1'd0; rate_idle_reg1 <= 1'd0; mmcm_lock_reg1 <= 1'd0; rxelecidle_reg1 <= 1'd0; rxcdrlock_reg1 <= 1'd0; txsync_start_reg1 <= 1'd0; txphinitdone_reg1 <= 1'd0; txdlysresetdone_reg1 <= 1'd0; txphaligndone_reg1 <= 1'd0; txsyncdone_reg1 <= 1'd0; rxsync_start_reg1 <= 1'd0; rxdlysresetdone_reg1 <= 1'd0; rxphaligndone_m_reg1 <= 1'd0; rxphaligndone_s_reg1 <= 1'd0; rxsync_donem_reg1 <= 1'd0; rxsyncdone_reg1 <= 1'd0; //---------- 2nd Stage FF -------------------------- gen3_reg2 <= 1'd0; rate_idle_reg2 <= 1'd0; mmcm_lock_reg2 <= 1'd0; rxelecidle_reg2 <= 1'd0; rxcdrlock_reg2 <= 1'd0; txsync_start_reg2 <= 1'd0; txphinitdone_reg2 <= 1'd0; txdlysresetdone_reg2 <= 1'd0; txphaligndone_reg2 <= 1'd0; txsyncdone_reg2 <= 1'd0; rxsync_start_reg2 <= 1'd0; rxdlysresetdone_reg2 <= 1'd0; rxphaligndone_m_reg2 <= 1'd0; rxphaligndone_s_reg2 <= 1'd0; rxsync_donem_reg2 <= 1'd0; rxsyncdone_reg2 <= 1'd0; //---------- 3rd Stage FF -------------------------- txsync_start_reg3 <= 1'd0; txphinitdone_reg3 <= 1'd0; txdlysresetdone_reg3 <= 1'd0; txphaligndone_reg3 <= 1'd0; txsyncdone_reg3 <= 1'd0; end else begin //---------- 1st Stage FF -------------------------- gen3_reg1 <= SYNC_GEN3; rate_idle_reg1 <= SYNC_RATE_IDLE; mmcm_lock_reg1 <= SYNC_MMCM_LOCK; rxelecidle_reg1 <= SYNC_RXELECIDLE; rxcdrlock_reg1 <= SYNC_RXCDRLOCK; txsync_start_reg1 <= SYNC_TXSYNC_START; txphinitdone_reg1 <= SYNC_TXPHINITDONE; txdlysresetdone_reg1 <= SYNC_TXDLYSRESETDONE; txphaligndone_reg1 <= SYNC_TXPHALIGNDONE; txsyncdone_reg1 <= SYNC_TXSYNCDONE; rxsync_start_reg1 <= SYNC_RXSYNC_START; rxdlysresetdone_reg1 <= SYNC_RXDLYSRESETDONE; rxphaligndone_m_reg1 <= SYNC_RXPHALIGNDONE_M; rxphaligndone_s_reg1 <= SYNC_RXPHALIGNDONE_S; rxsync_donem_reg1 <= SYNC_RXSYNC_DONEM_IN; rxsyncdone_reg1 <= SYNC_RXSYNCDONE; //---------- 2nd Stage FF -------------------------- gen3_reg2 <= gen3_reg1; rate_idle_reg2 <= rate_idle_reg1; mmcm_lock_reg2 <= mmcm_lock_reg1; rxelecidle_reg2 <= rxelecidle_reg1; rxcdrlock_reg2 <= rxcdrlock_reg1; txsync_start_reg2 <= txsync_start_reg1; txphinitdone_reg2 <= txphinitdone_reg1; txdlysresetdone_reg2 <= txdlysresetdone_reg1; txphaligndone_reg2 <= txphaligndone_reg1; txsyncdone_reg2 <= txsyncdone_reg1; rxsync_start_reg2 <= rxsync_start_reg1; rxdlysresetdone_reg2 <= rxdlysresetdone_reg1; rxphaligndone_m_reg2 <= rxphaligndone_m_reg1; rxphaligndone_s_reg2 <= rxphaligndone_s_reg1; rxsync_donem_reg2 <= rxsync_donem_reg1; rxsyncdone_reg2 <= rxsyncdone_reg1; //---------- 3rd Stage FF -------------------------- txsync_start_reg3 <= txsync_start_reg2; txphinitdone_reg3 <= txphinitdone_reg2; txdlysresetdone_reg3 <= txdlysresetdone_reg2; txphaligndone_reg3 <= txphaligndone_reg2; txsyncdone_reg3 <= txsyncdone_reg2; end end //---------- Generate TX Sync FSM ---------------------------------------------- generate if ((PCIE_LINK_SPEED == 3) || (PCIE_TXBUF_EN == "FALSE")) begin : txsync_fsm //---------- PIPE TX Sync FSM ---------------------------------------------- always @ (posedge SYNC_CLK) begin if (!SYNC_RST_N) begin fsm_tx <= FSM_TXSYNC_IDLE; txdlyen <= 1'd0; txsync_done <= 1'd0; end else begin case (fsm_tx) //---------- Idle State ------------------------ FSM_TXSYNC_IDLE : begin //---------- Exiting Reset or Rate Change -- if (txsync_start_reg2) begin fsm_tx <= FSM_MMCM_LOCK; txdlyen <= 1'd0; txsync_done <= 1'd0; end else begin fsm_tx <= FSM_TXSYNC_IDLE; txdlyen <= txdlyen; txsync_done <= txsync_done; end end //---------- Check MMCM Lock ------------------- FSM_MMCM_LOCK : begin fsm_tx <= (mmcm_lock_reg2 ? FSM_TXSYNC_START : FSM_MMCM_LOCK); txdlyen <= 1'd0; txsync_done <= 1'd0; end //---------- TX Delay Soft Reset --------------- FSM_TXSYNC_START : begin fsm_tx <= (((!txdlysresetdone_reg3 && txdlysresetdone_reg2) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START); txdlyen <= 1'd0; txsync_done <= 1'd0; end //---------- Wait for TX Phase Init Done (Manual Mode Only) FSM_TXPHINITDONE : begin fsm_tx <= (((!txphinitdone_reg3 && txphinitdone_reg2) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE); txdlyen <= 1'd0; txsync_done <= 1'd0; end //---------- Wait for TX Phase Alignment Done -- FSM_TXSYNC_DONE1 : begin if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE) fsm_tx <= ((!txsyncdone_reg3 && txsyncdone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1); else fsm_tx <= ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1); txdlyen <= 1'd0; txsync_done <= 1'd0; end //---------- Wait for Master TX Delay Alignment Done FSM_TXSYNC_DONE2 : begin if ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1)) begin fsm_tx <= FSM_TXSYNC_IDLE; txdlyen <= !SYNC_SLAVE; txsync_done <= 1'd1; end else begin fsm_tx <= FSM_TXSYNC_DONE2; txdlyen <= !SYNC_SLAVE; txsync_done <= 1'd0; end end //---------- Default State --------------------- default : begin fsm_tx <= FSM_TXSYNC_IDLE; txdlyen <= 1'd0; txsync_done <= 1'd0; end endcase end end end //---------- TX Sync FSM Default------------------------------------------------ else begin : txsync_fsm_disable //---------- Default ------------------------------------------------------- always @ (posedge SYNC_CLK) begin fsm_tx <= FSM_TXSYNC_IDLE; txdlyen <= 1'd0; txsync_done <= 1'd0; end end endgenerate //---------- Generate RX Sync FSM ---------------------------------------------- generate if ((PCIE_LINK_SPEED == 3) && (PCIE_RXBUF_EN == "FALSE")) begin : rxsync_fsm //---------- PIPE RX Sync FSM ---------------------------------------------- always @ (posedge SYNC_CLK) begin if (!SYNC_RST_N) begin fsm_rx <= FSM_RXSYNC_IDLE; rxdlyen <= 1'd0; rxsync_done <= 1'd0; end else begin case (fsm_rx) //---------- Idle State ------------------------ FSM_RXSYNC_IDLE : begin //---------- Exiting Rate Change ----------- if (rxsync_start_reg2) begin fsm_rx <= FSM_RXCDRLOCK; rxdlyen <= 1'd0; rxsync_done <= 1'd0; end //---------- Exiting Electrical Idle without Rate Change else if (gen3_reg2 && rate_idle_reg2 && ((rxelecidle_reg2 == 1'd1) && (rxelecidle_reg1 == 1'd0))) begin fsm_rx <= FSM_RXCDRLOCK; rxdlyen <= 1'd0; rxsync_done <= 1'd0; end //---------- Idle -------------------------- else begin fsm_rx <= FSM_RXSYNC_IDLE; rxdlyen <= rxelecidle_reg2 ? 1'd0 : rxdlyen; rxsync_done <= rxelecidle_reg2 ? 1'd0 : rxsync_done; end end //---------- Wait for RX Electrical Idle Exit and RX CDR Lock FSM_RXCDRLOCK : begin fsm_rx <= ((!rxelecidle_reg2 && rxcdrlock_reg2) ? FSM_RXSYNC_START : FSM_RXCDRLOCK); rxdlyen <= 1'd0; rxsync_done <= 1'd0; end //---------- Start RX Sync with RX Delay Soft Reset FSM_RXSYNC_START : begin fsm_rx <= ((!rxdlysresetdone_reg2 && rxdlysresetdone_reg1) ? FSM_RXSYNC_DONE1 : FSM_RXSYNC_START); rxdlyen <= 1'd0; rxsync_done <= 1'd0; end //---------- Wait for RX Phase Alignment Done -- FSM_RXSYNC_DONE1 : begin if (SYNC_SLAVE) begin fsm_rx <= ((!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1); rxdlyen <= 1'd0; rxsync_done <= 1'd0; end else begin fsm_rx <= ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1); rxdlyen <= 1'd0; rxsync_done <= 1'd0; end end //---------- Wait for Master RX Delay Alignment Done FSM_RXSYNC_DONE2 : begin if (SYNC_SLAVE) begin fsm_rx <= FSM_RXSYNC_IDLE; rxdlyen <= 1'd0; rxsync_done <= 1'd1; end else if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1)) begin fsm_rx <= ((PCIE_LANE == 1) ? FSM_RXSYNC_IDLE : FSM_RXSYNC_DONES); rxdlyen <= (PCIE_LANE == 1); rxsync_done <= (PCIE_LANE == 1); end else begin fsm_rx <= FSM_RXSYNC_DONE2; rxdlyen <= 1'd1; rxsync_done <= 1'd0; end end //---------- Wait for Slave RX Phase Alignment Done FSM_RXSYNC_DONES : begin if (!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) begin fsm_rx <= FSM_RXSYNC_DONEM; rxdlyen <= 1'd1; rxsync_done <= 1'd0; end else begin fsm_rx <= FSM_RXSYNC_DONES; rxdlyen <= 1'd0; rxsync_done <= 1'd0; end end //---------- Wait for Master RX Delay Alignment Done FSM_RXSYNC_DONEM : begin if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1)) begin fsm_rx <= FSM_RXSYNC_IDLE; rxdlyen <= 1'd1; rxsync_done <= 1'd1; end else begin fsm_rx <= FSM_RXSYNC_DONEM; rxdlyen <= 1'd1; rxsync_done <= 1'd0; end end //---------- Default State --------------------- default : begin fsm_rx <= FSM_RXSYNC_IDLE; rxdlyen <= 1'd0; rxsync_done <= 1'd0; end endcase end end end //---------- RX Sync FSM Default ----------------------------------------------- else begin : rxsync_fsm_disable //---------- Default ------------------------------------------------------- always @ (posedge SYNC_CLK) begin fsm_rx <= FSM_RXSYNC_IDLE; rxdlyen <= 1'd0; rxsync_done <= 1'd0; end end endgenerate //---------- PIPE Sync Output -------------------------------------------------- assign SYNC_TXPHALIGNEN = ((PCIE_TXSYNC_MODE == 1) || (!gen3_reg2 && (PCIE_TXBUF_EN == "TRUE"))) ? 1'd0 : 1'd1; assign SYNC_TXDLYBYPASS = 1'd0; //assign SYNC_TXDLYSRESET = !(((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0; assign SYNC_TXDLYSRESET = (fsm_tx == FSM_TXSYNC_START); assign SYNC_TXPHDLYRESET = (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0; assign SYNC_TXPHINIT = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXPHINITDONE); assign SYNC_TXPHALIGN = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXSYNC_DONE1); assign SYNC_TXDLYEN = PCIE_TXSYNC_MODE ? 1'd0 : txdlyen; assign SYNC_TXSYNC_DONE = txsync_done; assign SYNC_FSM_TX = fsm_tx; assign SYNC_RXPHALIGNEN = ((PCIE_RXSYNC_MODE == 1) || (!gen3_reg2) || (PCIE_RXBUF_EN == "TRUE")) ? 1'd0 : 1'd1; assign SYNC_RXDLYBYPASS = !gen3_reg2 || (PCIE_RXBUF_EN == "TRUE"); assign SYNC_RXDLYSRESET = (fsm_rx == FSM_RXSYNC_START); assign SYNC_RXPHALIGN = PCIE_RXSYNC_MODE ? 1'd0 : (!SYNC_SLAVE ? (fsm_rx == FSM_RXSYNC_DONE1) : (rxsync_donem_reg2 && (fsm_rx == FSM_RXSYNC_DONE1))); assign SYNC_RXDLYEN = PCIE_RXSYNC_MODE ? 1'd0 : rxdlyen; assign SYNC_RXDDIEN = gen3_reg2 && (PCIE_RXBUF_EN == "FALSE"); assign SYNC_RXSYNC_DONE = rxsync_done; assign SYNC_RXSYNC_DONEM_OUT = (fsm_rx == FSM_RXSYNC_DONES); assign SYNC_FSM_RX = fsm_rx; endmodule

// ============================================================================= // COPYRIGHT NOTICE // Copyright 2000-2001 (c) Lattice Semiconductor Corporation // ALL RIGHTS RESERVED // This confidential and proprietary software may be used only as authorised // by a licensing agreement from Lattice Semiconductor Corporation. // The entire notice above must be reproduced on all authorized copies and // copies may only be made to the extent permitted by a licensing agreement // from Lattice Semiconductor Corporation. // // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) // 5555 NE Moore Court 408-826-6000 (other locations) // Hillsboro, OR 97124 web : http://www.latticesemi.com/ // U.S.A email: techsupport@latticesemi.com // ============================================================================= // FILE DETAILS // Project : USERNAME // File : USERNAME.v // Title : // Dependencies : // Description : Top level for core. // ============================================================================= module pcie ( input wire sys_clk_250, // 250 Mhz Clock input wire sys_clk_125, // 125 Mhz Clock input wire rst_n, // asynchronous system reset. input wire inta_n, input wire [7:0] msi, input wire [15:0] vendor_id , input wire [15:0] device_id , input wire [7:0] rev_id , input wire [23:0] class_code , input wire [15:0] subsys_ven_id , input wire [15:0] subsys_id , input wire load_id , input wire force_lsm_active, // Force LSM Status Active input wire force_rec_ei, // Force Received Electrical Idle input wire force_phy_status, // Force PHY Connection Status input wire force_disable_scr,// Force Disable Scrambler to PCS input wire hl_snd_beacon, // HL req. to Send Beacon input wire hl_disable_scr, // HL req. to Disable Scrambling bit in TS1/TS2 input wire hl_gto_dis, // HL req a jump to Disable input wire hl_gto_det, // HL req a jump to detect input wire hl_gto_hrst, // HL req a jump to Hot reset input wire hl_gto_l0stx, // HL req a jump to TX L0s input wire hl_gto_l1, // HL req a jump to L1 input wire hl_gto_l2, // HL req a jump to L2 input wire hl_gto_l0stxfts, // HL req a jump to L0s TX FTS input wire hl_gto_lbk, // HL req a jump to Loopback input wire hl_gto_rcvry, // HL req a jump to recovery input wire hl_gto_cfg, // HL req a jump to CFG input wire no_pcie_train, // Disable the training process // Power Management Interface input wire [1:0] tx_dllp_val, // Req for Sending PM/Vendor type DLLP input wire [2:0] tx_pmtype, // Power Management Type input wire [23:0] tx_vsd_data, // Vendor Type DLLP contents // For VC Inputs input wire tx_req_vc0, // VC0 Request from User input wire [15:0] tx_data_vc0, // VC0 Input data from user logic input wire tx_st_vc0, // VC0 start of pkt from user logic. input wire tx_end_vc0, // VC0 End of pkt from user logic. input wire tx_nlfy_vc0, // VC0 End of nullified pkt from user logic. input wire ph_buf_status_vc0, // VC0 Indicate the Full/alm.Full status of the PH buffers input wire pd_buf_status_vc0, // VC0 Indicate PD Buffer has got space less than Max Pkt size input wire nph_buf_status_vc0, // VC0 For NPH input wire npd_buf_status_vc0, // VC0 For NPD input wire ph_processed_vc0, // VC0 TL has processed one TLP Header - PH Type input wire pd_processed_vc0, // VC0 TL has processed one TLP Data - PD TYPE input wire nph_processed_vc0, // VC0 For NPH input wire npd_processed_vc0, // VC0 For NPD input wire [7:0] pd_num_vc0, // VC0 For PD -- No. of Data processed input wire [7:0] npd_num_vc0, // VC0 For PD input wire [7:0] rxp_data, // CH0:PCI Express data from External Phy input wire rxp_data_k, // CH0:PCI Express Control from External Phy input wire rxp_valid, // CH0:Indicates a symbol lock and valid data on rx_data /rx_data_k input wire rxp_elec_idle, // CH0:Inidicates receiver detection of an electrical signal input wire [2:0] rxp_status, // CH0:Indicates receiver Staus/Error codes input wire phy_status, // Indicates PHY status info // From User logic // From User logic input wire cmpln_tout , // Completion time out. input wire cmpltr_abort_np , // Completor abort. input wire cmpltr_abort_p , // Completor abort. input wire unexp_cmpln , // Unexpexted completion. input wire ur_np_ext , // UR for NP type. input wire ur_p_ext , // UR for P type. input wire np_req_pend , // Non posted request is pending. input wire pme_status , // PME status to reg 044h. // User Loop back data input wire [15:0] tx_lbk_data, // TX User Master Loopback data input wire [1:0] tx_lbk_kcntl, // TX User Master Loopback control output wire tx_lbk_rdy, // TX loop back is ready to accept data output wire [15:0] rx_lbk_data, // RX User Master Loopback data output wire [1:0] rx_lbk_kcntl, // RX User Master Loopback control // Power Management/ Vendor specific DLLP output wire tx_dllp_sent, // Requested PM DLLP is sent output wire [2:0] rxdp_pmd_type, // PM DLLP type bits. output wire [23:0] rxdp_vsd_data , // Vendor specific DLLP data. output wire [1:0] rxdp_dllp_val, // PM/Vendor specific DLLP valid. output wire [7:0] txp_data, // CH0:PCI Express data to External Phy output wire txp_data_k, // CH0:PCI Express control to External Phy output wire txp_elec_idle, // CH0:Tells PHY to output Electrical Idle output wire txp_compliance, // CH0:Sets the PHY running disparity to -ve output wire rxp_polarity, // CH0:Tells PHY to do polarity inversion on the received data output wire txp_detect_rx_lb, // Tells PHY to begin receiver detection or begin Loopback output wire reset_n, // Async reset to the PHY output wire [1:0] power_down, // Tell sthe PHY to power Up or Down output wire phy_pol_compliance, // Polling compliance output wire [3:0] phy_ltssm_state, // Indicates the states of the ltssm output wire [2:0] phy_ltssm_substate, // sub-states of the ltssm_state output wire tx_rdy_vc0, // VC0 TX ready indicating signal output wire [8:0] tx_ca_ph_vc0, // VC0 Available credit for Posted Type Headers output wire [12:0] tx_ca_pd_vc0, // VC0 For Posted - Data output wire [8:0] tx_ca_nph_vc0, // VC0 For Non-posted - Header output wire [12:0] tx_ca_npd_vc0, // VC0 For Non-posted - Data output wire [8:0] tx_ca_cplh_vc0, // VC0 For Completion - Header output wire [12:0] tx_ca_cpld_vc0, // VC0 For Completion - Data output wire tx_ca_p_recheck_vc0, // output wire tx_ca_cpl_recheck_vc0, // output wire [15:0] rx_data_vc0, // VC0 Receive data output wire rx_st_vc0, // VC0 Receive data start output wire rx_end_vc0, // VC0 Receive data end output wire rx_us_req_vc0 , // VC0 unsupported req received output wire rx_malf_tlp_vc0 ,// VC0 malformed TLP in received data output wire [6:0] rx_bar_hit , // Bar hit output wire [2:0] mm_enable , // Multiple message enable bits of Register output wire msi_enable , // MSI enable bit of Register // From Config Registers output wire [7:0] bus_num , // Bus number output wire [4:0] dev_num , // Device number output wire [2:0] func_num , // Function number output wire [1:0] pm_power_state , // Power state bits of Register at 044h output wire pme_en , // PME_En at 044h output wire [5:0] cmd_reg_out , // Bits 10,8,6,2,1,0 From register 004h output wire [14:0] dev_cntl_out , // Divice control register at 060h output wire [7:0] lnk_cntl_out , // Link control register at 068h // To ASPM implementation outside the IP output wire tx_rbuf_empty, // Transmit retry buffer is empty output wire tx_dllp_pend, // DLPP is pending to be transmitted output wire rx_tlp_rcvd, // Received a TLP // Datal Link Control SM Status output wire dl_inactive, // Data Link Control SM is in INACTIVE state output wire dl_init, // INIT state output wire dl_active, // ACTIVE state output wire dl_up // Data Link Layer is UP ); pci_exp_x1_core_wrap u1_dut( // Clock and Reset .sys_clk_250 ( sys_clk_250 ) , .sys_clk_125 ( sys_clk_125 ) , .rst_n ( rst_n ), .inta_n ( inta_n ), .msi ( msi ), .vendor_id ( vendor_id ), .device_id ( device_id ), .rev_id ( rev_id ), .class_code ( class_code ), .subsys_ven_id ( subsys_ven_id ), .subsys_id ( subsys_id ), .load_id ( load_id ), // Inputs .force_lsm_active ( force_lsm_active ), .force_rec_ei ( force_rec_ei ), .force_phy_status ( force_phy_status ), .force_disable_scr ( force_disable_scr ), .hl_snd_beacon ( hl_snd_beacon ), .hl_disable_scr ( hl_disable_scr ), .hl_gto_dis ( hl_gto_dis ), .hl_gto_det ( hl_gto_det ), .hl_gto_hrst ( hl_gto_hrst ), .hl_gto_l0stx ( hl_gto_l0stx ), .hl_gto_l1 ( hl_gto_l1 ), .hl_gto_l2 ( hl_gto_l2 ), .hl_gto_l0stxfts ( hl_gto_l0stxfts ), .hl_gto_lbk ( hl_gto_lbk ), .hl_gto_rcvry ( hl_gto_rcvry ), .hl_gto_cfg ( hl_gto_cfg ), .no_pcie_train ( no_pcie_train ), // Power Management Interface .tx_dllp_val ( tx_dllp_val ), .tx_pmtype ( tx_pmtype ), .tx_vsd_data ( tx_vsd_data ), .tx_req_vc0 ( tx_req_vc0 ), .tx_data_vc0 ( tx_data_vc0 ), .tx_st_vc0 ( tx_st_vc0 ), .tx_end_vc0 ( tx_end_vc0 ), .tx_nlfy_vc0 ( tx_nlfy_vc0 ), .ph_buf_status_vc0 ( ph_buf_status_vc0 ), .pd_buf_status_vc0 ( pd_buf_status_vc0 ), .nph_buf_status_vc0 ( nph_buf_status_vc0 ), .npd_buf_status_vc0 ( npd_buf_status_vc0 ), .ph_processed_vc0 ( ph_processed_vc0 ), .pd_processed_vc0 ( pd_processed_vc0 ), .nph_processed_vc0 ( nph_processed_vc0 ), .npd_processed_vc0 ( npd_processed_vc0 ), .pd_num_vc0 ( pd_num_vc0 ), .npd_num_vc0 ( npd_num_vc0 ), // From External PHY (PIPE I/F) .rxp_data ( rxp_data ), .rxp_data_k ( rxp_data_k ), .rxp_valid ( rxp_valid ), .rxp_elec_idle ( rxp_elec_idle ), .rxp_status ( rxp_status ), .phy_status ( phy_status), // From User logic .cmpln_tout ( cmpln_tout ), .cmpltr_abort_np ( cmpltr_abort_np ), .cmpltr_abort_p ( cmpltr_abort_p ), .unexp_cmpln ( unexp_cmpln ), .ur_np_ext ( ur_np_ext ), .ur_p_ext ( ur_p_ext ), .np_req_pend ( np_req_pend ), .pme_status ( pme_status ), .tx_lbk_data ( tx_lbk_data ), .tx_lbk_kcntl ( tx_lbk_kcntl ), .tx_lbk_rdy ( tx_lbk_rdy ), .rx_lbk_data ( rx_lbk_data ), .rx_lbk_kcntl ( rx_lbk_kcntl ), // Power Management .tx_dllp_sent ( tx_dllp_sent ), .rxdp_pmd_type ( rxdp_pmd_type ), .rxdp_vsd_data ( rxdp_vsd_data ), .rxdp_dllp_val ( rxdp_dllp_val ), //-------- Outputs // To External PHY (PIPE I/F) .txp_data ( txp_data ), .txp_data_k ( txp_data_k ), .txp_elec_idle ( txp_elec_idle ), .txp_compliance ( txp_compliance ), .rxp_polarity ( rxp_polarity ), .txp_detect_rx_lb ( txp_detect_rx_lb ), .reset_n ( reset_n ), .power_down ( power_down ), // From TX User Interface .phy_pol_compliance ( phy_pol_compliance ), .phy_ltssm_state ( phy_ltssm_state ), .phy_ltssm_substate ( phy_ltssm_substate ), .tx_rdy_vc0 ( tx_rdy_vc0), .tx_ca_ph_vc0 ( tx_ca_ph_vc0), .tx_ca_pd_vc0 ( tx_ca_pd_vc0), .tx_ca_nph_vc0 ( tx_ca_nph_vc0), .tx_ca_npd_vc0 ( tx_ca_npd_vc0), .tx_ca_cplh_vc0 ( tx_ca_cplh_vc0), .tx_ca_cpld_vc0 ( tx_ca_cpld_vc0), .tx_ca_p_recheck_vc0 ( tx_ca_p_recheck_vc0 ), .tx_ca_cpl_recheck_vc0 ( tx_ca_cpl_recheck_vc0 ), .rx_data_vc0 ( rx_data_vc0), .rx_st_vc0 ( rx_st_vc0), .rx_end_vc0 ( rx_end_vc0), .rx_us_req_vc0 ( rx_us_req_vc0 ), .rx_malf_tlp_vc0 ( rx_malf_tlp_vc0 ), .rx_bar_hit ( rx_bar_hit ), .mm_enable ( mm_enable ), .msi_enable ( msi_enable ), // From Config Registers .bus_num ( bus_num ) , .dev_num ( dev_num ) , .func_num ( func_num ) , .pm_power_state ( pm_power_state ) , .pme_en ( pme_en ) , .cmd_reg_out ( cmd_reg_out ), .dev_cntl_out ( dev_cntl_out ), .lnk_cntl_out ( lnk_cntl_out ), // To ASPM implementation outside the IP .tx_rbuf_empty ( tx_rbuf_empty ), .tx_dllp_pend ( tx_dllp_pend ), .rx_tlp_rcvd ( rx_tlp_rcvd ), // Datal Link Control SM Status .dl_inactive ( dl_inactive ), .dl_init ( dl_init ), .dl_active ( dl_active ), .dl_up ( dl_up ) ); endmodule

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LS__O2BB2AI_BLACKBOX_V `define SKY130_FD_SC_LS__O2BB2AI_BLACKBOX_V /** * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND. * * Y = !(!(A1 & A2) & (B1 | B2)) * * Verilog stub definition (black box without power pins). * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_ls__o2bb2ai ( Y , A1_N, A2_N, B1 , B2 ); output Y ; input A1_N; input A2_N; input B1 ; input B2 ; // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; endmodule `default_nettype wire `endif // SKY130_FD_SC_LS__O2BB2AI_BLACKBOX_V

// `include "define.v" // `include "regfile.v" // `include "hilo_reg.v" // `include "BranchControl.v" // `include "HazardControl.v" // `include "ForwardControl.v" // `include "IF.v" // `include "IF_ID.v" // `include "ID.v" // `include "ID_EX.v" // `include "EX.v" // `include "ALU.v" // `include "decoder.v" // `include "EX_MEM.v" // `include "MEM.v" // `include "RM_ctrl.v" // `include "WM_ctrl.v" // `include "MEM_WB.v" // `include "utilities/dffe.v" // `include "utilities/mux2x1.v" // `include "utilities/mux4x1.v" module pipeline_CPU ( input clk, input rst, input[`RegDataWidth-1:0] data_from_mem, output[`MemAddrWidth-1:0] mem_addr, output[3:0] mem_byte_slct, output[`RegDataWidth-1:0] data_to_write_mem, output mem_we, output mem_re, input[`InstDataWidth-1:0] inst_from_rom, output[`InstAddrWidth-1:0] rom_addr, output rom_ce ); supply1 vcc; supply0 gnd; // Forwarding wire wire[1:0] FWA; wire[1:0] FWB; wire[1:0] FWhi; wire[1:0] FWlo; wire FWLS; wire[1:0] FW_br_A; wire[1:0] FW_br_B; // branch control wire wire[`InstAddrWidth-1:0] branch_address; wire is_branch; wire is_rst_IF_ID; // Hazard Control wire wire is_hold_IF; wire is_hold_IF_ID; wire is_zeros_ID_EX; wire[`InstAddrWidth-1:0] pc_plus4_IF; wire[`InstDataWidth-1:0] inst_ID; wire[`InstAddrWidth-1:0] pc_plus4_ID; IF inst_fetch(.clk (clk), .rst (rst), .is_hold (is_hold_IF), .is_branch(is_branch), .branch_address(branch_address), .ce(rom_ce), .pc(rom_addr), .pc_plus4(pc_plus4_IF) ); wire IF_ID_controlor; mux2x1 IF_ID_control( .in_0(rst), .in_1(vcc), .slct(is_rst_IF_ID), .out(IF_ID_controlor) ); IF_ID if_id_reg( .clk (clk), .rst (IF_ID_controlor), .is_hold (is_hold_IF_ID), .pc_plus4_IF(pc_plus4_IF), .inst_IF (inst_from_rom), .pc_plus4_ID(pc_plus4_ID), .inst_ID (inst_ID) ); wire[`RegAddrWidth-1:0] raddr_1_ID; wire[`RegDataWidth-1:0] rdata_1_ID; wire[`RegAddrWidth-1:0] raddr_2_ID; wire[`RegDataWidth-1:0] rdata_2_ID; wire[`RegDataWidth-1:0] shamt_ID; wire WriteReg_ID; wire MemOrAlu_ID; wire WriteMem_ID; wire ReadMem_ID; wire[`ALUTypeWidth-1:0] AluType_ID; wire[`ALUOpWidth-1:0] AluOp_ID; wire AluSrcA_ID; wire AluSrcB_ID; wire RegDes_ID; wire ImmSigned_ID; wire is_jal_ID; wire[`RegAddrWidth-1:0] rt_ID; wire[`RegAddrWidth-1:0] rd_ID; wire[`RegDataWidth-1:0] imm_signed_ID; wire[`RegDataWidth-1:0] imm_unsigned_ID; wire[`OpcodeWidth-1:0] opcode_ID; ID inst_decode( .rst(rst), .pc_plus4(pc_plus4_ID), .inst(inst_ID), .reg1_addr(raddr_1_ID), .reg2_addr(raddr_2_ID), .WriteReg(WriteReg_ID), .MemOrAlu(MemOrAlu_ID), .WriteMem(WriteMem_ID), .ReadMem(ReadMem_ID), .AluType(AluType_ID), .AluOp(AluOp_ID), .AluSrcA(AluSrcA_ID), .AluSrcB(AluSrcB_ID), .RegDes(RegDes_ID), .ImmSigned(ImmSigned_ID), .opcode(opcode_ID), .rt(rt_ID), .rd(rd_ID), .imm_signed(imm_signed_ID), .imm_unsigned(imm_unsigned_ID), .shamt(shamt_ID), .is_jal(is_jal_ID) ); wire[`RegAddrWidth-1:0] reg_write_addr; wire[`RegDataWidth-1:0] reg_write_data; wire reg_we; wire we_hi; wire[`RegDataWidth-1:0] hi_data_in; wire we_lo; wire[`RegDataWidth-1:0] lo_data_in; wire[`RegDataWidth-1:0] hi_data_out_ID; wire[`RegDataWidth-1:0] lo_data_out_ID; wire[`RegDataWidth-1:0] hi_data_to_EX; wire[`RegDataWidth-1:0] lo_data_to_EX; // force read regfile regfile regs( .clk(clk), .rst(rst), .waddr(reg_write_addr), .wdata(reg_write_data), .we(reg_we), .re1(vcc), .raddr_1(raddr_1_ID), .rdata_1(rdata_1_ID), .re2(vcc), .raddr_2(raddr_2_ID), .rdata_2(rdata_2_ID) ); hilo_reg hilo_regs( .clk(clk), .rst(rst), .we_hi(we_hi), .hi_data_in(hi_data_in), .we_lo(we_lo), .lo_data_in(lo_data_in), .hi_data_out(hi_data_out_ID), .lo_data_out(lo_data_out_ID) ); wire WriteReg_EX; wire MemOrAlu_EX; wire WriteMem_EX; wire ReadMem_EX; wire[`ALUTypeWidth-1:0] AluType_EX; wire[`ALUOpWidth-1:0] AluOp_EX; wire AluSrcA_EX; wire AluSrcB_EX; wire RegDes_EX; wire ImmSigned_EX; wire is_jal_EX; wire[`RegAddrWidth-1:0] rt_EX; wire[`RegAddrWidth-1:0] rd_EX; wire[`RegDataWidth-1:0] imm_signed_EX; wire[`RegDataWidth-1:0] imm_unsigned_EX; wire[`OpcodeWidth-1:0] opcode_EX; wire[`RegDataWidth-1:0] rdata_1_EX; wire[`RegDataWidth-1:0] rdata_2_EX; wire[`RegAddrWidth-1:0] raddr_1_EX; wire[`RegAddrWidth-1:0] raddr_2_EX; wire[`RegDataWidth-1:0] shamt_EX; wire[`InstAddrWidth-1:0] pc_plus4_EX; wire ID_EX_controlor; mux2x1 ID_EX_control( .in_0(rst), .in_1(vcc), .slct(is_zeros_ID_EX), .out(ID_EX_controlor) ); ID_EX id_ex_reg( .clk(clk), .rst(ID_EX_controlor), .is_hold(gnd), .rdata_1_ID(rdata_1_ID), .rdata_2_ID(rdata_2_ID), .raddr_1_ID(raddr_1_ID), .raddr_2_ID(raddr_2_ID), .shamt_ID(shamt_ID), .WriteReg_ID(WriteReg_ID), .MemOrAlu_ID(MemOrAlu_ID), .WriteMem_ID(WriteMem_ID), .ReadMem_ID(ReadMem_ID), .AluType_ID(AluType_ID), .AluOp_ID(AluOp_ID), .AluSrcA_ID(AluSrcA_ID), .AluSrcB_ID(AluSrcB_ID), .RegDes_ID(RegDes_ID), .ImmSigned_ID(ImmSigned_ID), .is_jal_ID(is_jal_ID), .rt_ID(rt_ID), .rd_ID(rd_ID), .imm_signed_ID(imm_signed_ID), .imm_unsigned_ID(imm_unsigned_ID), .opcode_ID(opcode_ID), .hi_ID(hi_data_out_ID), .lo_ID(lo_data_out_ID), .pc_plus4_ID(pc_plus4_ID), .rdata_1_EX(rdata_1_EX), .rdata_2_EX(rdata_2_EX), .raddr_1_EX(raddr_1_EX), .raddr_2_EX(raddr_2_EX), .shamt_EX(shamt_EX), .WriteReg_EX(WriteReg_EX), .MemOrAlu_EX(MemOrAlu_EX), .ReadMem_EX(ReadMem_EX), .WriteMem_EX(WriteMem_EX), .AluType_EX(AluType_EX), .AluOp_EX(AluOp_EX), .AluSrcA_EX(AluSrcA_EX), .AluSrcB_EX(AluSrcB_EX), .RegDes_EX(RegDes_EX), .ImmSigned_EX(ImmSigned_EX), .is_jal_EX(is_jal_EX), .rt_EX(rt_EX), .rd_EX(rd_EX), .imm_signed_EX(imm_signed_EX), .imm_unsigned_EX(imm_unsigned_EX), .opcode_EX(opcode_EX), .hi_EX(hi_data_to_EX), .lo_EX(lo_data_to_EX), .pc_plus4_EX(pc_plus4_EX) ); wire[`RegAddrWidth-1:0] target_EX; wire is_Overflow; wire[`RegDataWidth-1:0] data_out_EX; wire we_hi_EX; wire we_lo_EX; wire[`RegDataWidth-1:0] hi_EX; wire[`RegDataWidth-1:0] lo_EX; wire[`RegDataWidth-1:0] rdata_2_EX_out; wire[`RegDataWidth-1:0] hi_MEM; wire[`RegDataWidth-1:0] lo_MEM; wire[`RegDataWidth-1:0] data_from_ALU_MEM; EX execution( .rst(rst), .shamt(shamt_EX), .AluType_EX(AluType_EX), .AluOp_EX(AluOp_EX), .AluSrcA_EX(AluSrcA_EX), .AluSrcB_EX(AluSrcB_EX), .RegDes_EX(RegDes_EX), .ImmSigned_EX(ImmSigned_EX), .is_jal_EX(is_jal_EX), .rt_EX(rt_EX), .rd_EX(rd_EX), .imm_signed_EX(imm_signed_EX), .imm_unsigned_EX(imm_unsigned_EX), .hi(hi_data_to_EX), .lo(lo_data_to_EX), .rdata_1(rdata_1_EX), .rdata_2(rdata_2_EX), .pc_plus4_EX(pc_plus4_EX), // forwarding data in .data_out_MEM(data_from_ALU_MEM), .data_out_WB(reg_write_data), .hi_MEM(hi_MEM), .hi_WB(hi_data_in), .lo_MEM(lo_MEM), .lo_WB(lo_data_in), .FWA(FWA), .FWB(FWB), .FWhi(FWhi), .FWlo(FWlo), .target_EX(target_EX), .is_Overflow(is_Overflow), .data_out_EX(data_out_EX), .rdata_2_EX(rdata_2_EX_out), .hi_EX(hi_EX), .lo_EX(lo_EX), .we_hi(we_hi_EX), .we_lo(we_lo_EX) ); wire[`RegAddrWidth-1:0] target_MEM; wire we_hi_MEM; wire we_lo_MEM; wire[`RegDataWidth-1:0] rdata_2_MEM; wire[`RegAddrWidth-1:0] raddr_2_MEM; wire WriteReg_MEM; wire MemOrAlu_MEM; wire WriteMem_MEM; wire ReadMem_MEM; wire[`OpcodeWidth-1:0] opcode_MEM; EX_MEM ex_mem_reg( .clk(clk), .rst(rst), // set gnd temporarily .is_hold(gnd), .target_EX(target_EX), .data_out_EX(data_out_EX), .we_hi_EX(we_hi_EX), .we_lo_EX(we_lo_EX), .hi_EX(hi_EX), .lo_EX(lo_EX), .raddr_2_EX(raddr_2_EX), .rdata_2_EX(rdata_2_EX_out), .WriteReg_EX(WriteReg_EX), .MemOrAlu_EX(MemOrAlu_EX), .WriteMem_EX(WriteMem_EX), .ReadMem_EX(ReadMem_EX), .opcode_EX(opcode_EX), .target_MEM(target_MEM), .data_from_ALU_MEM(data_from_ALU_MEM), .we_hi_MEM(we_hi_MEM), .we_lo_MEM(we_lo_MEM), .hi_MEM(hi_MEM), .lo_MEM(lo_MEM), .raddr_2_MEM(raddr_2_MEM), .rdata_2_MEM(rdata_2_MEM), .WriteReg_MEM(WriteReg_MEM), .MemOrAlu_MEM(MemOrAlu_MEM), .WriteMem_MEM(WriteMem_MEM), .ReadMem_MEM(ReadMem_MEM), .opcode_MEM(opcode_MEM) ); wire[`RegDataWidth-1:0] MEM_data_MEM; // memory read/write MEM mem( .rst(rst), .FWLS(FWLS), .reg_data_2(rdata_2_MEM), .WB_data(reg_write_data), .raw_mem_data(data_from_mem), .ReadMem(ReadMem_MEM), .WriteMem(WriteMem_MEM), .mem_addr(data_from_ALU_MEM), .opcode(opcode_MEM), .data_to_write_mem(data_to_write_mem), .data_to_reg(MEM_data_MEM), .byte_slct(mem_byte_slct) ); assign mem_addr = data_from_ALU_MEM; assign mem_re = ReadMem_MEM; assign mem_we = WriteMem_MEM; wire[`RegDataWidth-1:0] ALU_data_WB; wire[`RegDataWidth-1:0] MEM_data_WB; MEM_WB mem_wb_reg( .clk(clk), .rst(rst), // set gnd temporarily .is_hold(gnd), .target_MEM(target_MEM), .ALU_data_MEM(data_from_ALU_MEM), .MEM_data_MEM(MEM_data_MEM), .we_hi_MEM(we_hi_MEM), .we_lo_MEM(we_lo_MEM), .hi_MEM(hi_MEM), .lo_MEM(lo_MEM), .WriteReg_MEM(WriteReg_MEM), .MemOrAlu_MEM(MemOrAlu_MEM), .target_WB(reg_write_addr), .ALU_data_WB(ALU_data_WB), .MEM_data_WB(MEM_data_WB), .we_hi_WB(we_hi), .we_lo_WB(we_lo), .hi_WB(hi_data_in), .lo_WB(lo_data_in), .WriteReg_WB(reg_we), .MemOrAlu_WB(MemOrAlu_WB) ); // See define.v // MemOrAlu // `define ALU 1'b1 // `define Mem 1'b0 mux2x1 #(.data_width(`RegDataWidth)) result_mux( .in_0(MEM_data_WB), .in_1(ALU_data_WB), .slct(MemOrAlu_WB), .out(reg_write_data) ); // Control center ForwardControl forwarding_handler( .rst(rst), .reg_data_1_addr_ID(raddr_1_ID), .reg_data_2_addr_ID(raddr_2_ID), .reg_data_1_addr_EX(raddr_1_EX), .reg_data_2_addr_EX(raddr_2_EX), .target_EX(target_EX), .WriteReg_EX(WriteReg_EX), .reg_data_2_addr_MEM(raddr_2_MEM), .target_MEM(target_MEM), .WriteReg_MEM(WriteReg_MEM), .MemOrAlu_MEM(MemOrAlu_MEM), .we_hi_MEM(we_hi_MEM), .we_lo_MEM(we_lo_MEM), .target_WB(reg_write_addr), .WriteReg_WB(reg_we), .we_hi_WB(we_hi), .we_lo_WB(we_lo), .FWA(FWA), .FWB(FWB), .FWhi(FWhi), .FWlo(FWlo), .FWLS(FWLS), .FW_br_A(FW_br_A), .FW_br_B(FW_br_B) ); BranchControl branch_handler( .rst(rst), .pc_plus4_ID(pc_plus4_ID), .inst_ID(inst_ID), .FW_br_A(FW_br_A), .FW_br_B(FW_br_B), .rdata_1_ID(rdata_1_ID), .rdata_2_ID(rdata_2_ID), .data_out_EX(data_out_EX), .data_from_ALU_MEM(data_from_ALU_MEM), .MEM_data_MEM(MEM_data_MEM), .branch_address(branch_address), .is_branch(is_branch), .is_rst_IF_ID(is_rst_IF_ID) ); HazardControl hazard_handler( .rst(rst), .ReadMem_EX(ReadMem_EX), .WriteMem_ID(WriteMem_ID), .raddr_1_ID(raddr_1_ID), .raddr_2_ID(raddr_2_ID), .target_EX(target_EX), .is_hold_IF(is_hold_IF), .is_hold_IF_ID(is_hold_IF_ID), .is_zeros_ID_EX(is_zeros_ID_EX) ); endmodule

/*============================================================================ This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point Arithmetic Package, Release 1, by John R. Hauser. Copyright 2019 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ `include "HardFloat_consts.vi" `include "HardFloat_specialize.vi" module mulAddRecF16_add ( input [(`floatControlWidth - 1):0] control, input int_mul, input [16:0] a, input [16:0] b, input [2:0] roundingMode, output [16:0] out, output [4:0] exceptionFlags, output [15:0] out_imul ); wire [16:0] recF16_1 = 'h08000; mulAddRecFN#(5, 11) mulAddRecFN( control, {int_mul, 2'b0}, a, recF16_1, b, roundingMode, out, exceptionFlags, out_imul); endmodule module mulAddRecF32_add ( input [(`floatControlWidth - 1):0] control, input int_mul, input [32:0] a, input [32:0] b, input [2:0] roundingMode, output [32:0] out, output [4:0] exceptionFlags, output [31:0] out_imul ); wire [32:0] recF32_1 = 33'h080000000; mulAddRecFN#(8, 24) mulAddRecFN( control, {int_mul, 2'b0}, a, recF32_1, b, roundingMode, out, exceptionFlags, out_imul); endmodule module mulAddRecF64_add ( input [(`floatControlWidth - 1):0] control, input int_mul, input [64:0] a, input [64:0] b, input [2:0] roundingMode, output [64:0] out, output [4:0] exceptionFlags, output [63:0] out_imul ); wire [64:0] recF64_1 = 65'h08000000000000000; mulAddRecFN#(11, 53) mulAddRecFN( control, {int_mul, 2'b0}, a, recF64_1, b, roundingMode, out, exceptionFlags, out_imul); endmodule module mulAddRecF128_add ( input [(`floatControlWidth - 1):0] control, input [128:0] a, input [128:0] b, input [2:0] roundingMode, output [128:0] out, output [4:0] exceptionFlags ); wire [127:0] out_imul; wire [128:0] recF128_1 = 129'h080000000000000000000000000000000; mulAddRecFN#(15, 113, 0) mulAddRecFN( control, 3'b0, a, recF128_1, b, roundingMode, out, exceptionFlags, out_imul ); endmodule module mulAddRecF16_mul ( input [(`floatControlWidth - 1):0] control, input int_mul, input [16:0] a, input [16:0] b, input [2:0] roundingMode, output [16:0] out, output [4:0] exceptionFlags, output [15:0] out_imul ); wire [16:0] zeroAddend = {a[16] ^ b[16], 16'b0}; mulAddRecFN#(5, 11) mulAddRecFN( control, {int_mul, 2'b0}, a, b, zeroAddend, roundingMode, out, exceptionFlags, out_imul ); endmodule module mulAddRecF32_mul ( input [(`floatControlWidth - 1):0] control, input int_mul, input [32:0] a, input [32:0] b, input [2:0] roundingMode, output [32:0] out, output [4:0] exceptionFlags, output [31:0] out_imul ); wire [32:0] zeroAddend = {a[32] ^ b[32], 32'b0}; mulAddRecFN#(8, 24) mulAddRecFN( control, {int_mul, 2'b0}, a, b, zeroAddend, roundingMode, out, exceptionFlags, out_imul ); endmodule module mulAddRecF64_mul ( input [(`floatControlWidth - 1):0] control, input int_mul, input [64:0] a, input [64:0] b, input [2:0] roundingMode, output [64:0] out, output [4:0] exceptionFlags, output [63:0] out_imul ); wire [64:0] zeroAddend = {a[64] ^ b[64], 64'b0}; mulAddRecFN#(11, 53) mulAddRecFN( control, {int_mul, 2'b0}, a, b, zeroAddend, roundingMode, out, exceptionFlags, out_imul ); endmodule module mulAddRecF128_mul ( input [(`floatControlWidth - 1):0] control, input [128:0] a, input [128:0] b, input [2:0] roundingMode, output [128:0] out, output [4:0] exceptionFlags ); wire [128:0] zeroAddend = {a[128] ^ b[128], 128'b0}; wire [127:0] out_imul; mulAddRecFN#(15, 113, 0) mulAddRecFN( control, 3'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags,out_imul ); endmodule module mulAddRecF16 ( input [(`floatControlWidth - 1):0] control, input int_mul, input [2:0] op, input [16:0] a, input [16:0] b, input [16:0] c, input [2:0] roundingMode, output [16:0] out, output [4:0] exceptionFlags, output [15:0] out_imul ); mulAddRecFN#(5, 11) mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags, out_imul); endmodule module mulAddRecF32 ( input [(`floatControlWidth - 1):0] control, input int_mul, input [2:0] op, input [32:0] a, input [32:0] b, input [32:0] c, input [2:0] roundingMode, output [32:0] out, output [4:0] exceptionFlags, output [31:0] out_imul ); mulAddRecFN#(8, 24) mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags, out_imul); endmodule module mulAddRecF64 ( input [(`floatControlWidth - 1):0] control, input int_mul, input [2:0] op, input [64:0] a, input [64:0] b, input [64:0] c, input [2:0] roundingMode, output [64:0] out, output [4:0] exceptionFlags, output [63:0] out_imul ); mulAddRecFN#(11, 53) mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags, out_imul); endmodule module mulAddRecF128 ( input [(`floatControlWidth - 1):0] control, input [2:0] op, input [128:0] a, input [128:0] b, input [128:0] c, input [2:0] roundingMode, output [128:0] out, output [4:0] exceptionFlags ); wire [127:0] out_imul; mulAddRecFN#(15, 113) mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags, out_imul); endmodule

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__DLYGATE4S50_PP_SYMBOL_V `define SKY130_FD_SC_LP__DLYGATE4S50_PP_SYMBOL_V /** * dlygate4s50: Delay Buffer 4-stage 0.50um length inner stage gates. * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_lp__dlygate4s50 ( //# {{data|Data Signals}} input A , output X , //# {{power|Power}} input VPB , input VPWR, input VGND, input VNB ); endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__DLYGATE4S50_PP_SYMBOL_V

//============================================================= // // Copyright (c) 2017 Simon Southwell. All rights reserved. // // Date: 11th August 2017 // // This code is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation, either version 3 of the License, or // (at your option) any later version. // // The code is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this code. If not, see <http://www.gnu.org/licenses/>. // // $Id: wb_mux.v,v 1.1 2017/08/22 09:16:05 simon Exp $ // $Source: /home/simon/CVS/src/cpu/mico32/HDL/rtl/wb_mux.v,v $ // //============================================================= `include "regs.vh" // Wishbone bus multiplexer, with high priority and low priority // bus master interfaces, muxed to a single interface. High // priority interface always wins when bus is inactive, but low // priority access is not interrupted if already started when // high prirority request asserted. module wb_mux (sys_clk, resetcpu, // High priority bus h_cyc, h_stb, h_we, h_sel, h_ack, h_adr, h_dat_o, h_dat_i, // Low priority bus l_cyc, l_stb, l_we, l_sel, l_ack, l_adr, l_dat_o, l_dat_i, // Muxed bus m_cyc, m_stb, m_we, m_sel, m_ack, m_adr, m_dat_o, m_dat_i ); input sys_clk; input resetcpu; input h_cyc; input h_stb; input h_we; input [3:0] h_sel; input [31:0] h_adr; input [31:0] h_dat_o; // An input, but matches name of LM32 interface output [31:0] h_dat_i; // An output, but matches name of LM32 interface output h_ack; input l_cyc; input l_stb; input l_we; input [3:0] l_sel; input [31:0] l_adr; input [31:0] l_dat_o; // An input, but matches name of LM32 interface output [31:0] l_dat_i; // An output, but matches name of LM32 interface output l_ack; output m_cyc; output m_stb; output m_we; output [3:0] m_sel; output [31:0] m_adr; output [31:0] m_dat_o; input [31:0] m_dat_i; input m_ack; reg active; reg h_owns_bus_reg; // Select high priority bus, if bus inactive and high priority bus // requesting, or (when active), it is the selected bus. wire sel_h = (h_cyc & ~active) | (h_owns_bus_reg & active); // Mux the outputs from the two busses assign m_cyc = h_cyc | l_cyc; assign m_stb = sel_h ? h_stb : l_stb; assign m_we = sel_h ? h_we : l_we; assign m_sel = sel_h ? h_sel : l_sel; assign m_adr = sel_h ? h_adr : l_adr; assign m_dat_o = sel_h ? h_dat_o : l_dat_o; // Route read data back to sources (regardless of bus selection) assign h_dat_i = m_dat_i; assign l_dat_i = m_dat_i; // Route ACK back to selected bus. // Using h_owns_bus_reg assumes there can be no ACK earlier than the // next cycle. If ACK can be in the same cycle as assertion of m_cyc, // then sel_h should be used, but this has slow timing and could, potentially, // create a timing loop, as ack would then be dependant on <x>_cyc. assign h_ack = h_owns_bus_reg & m_ack; assign l_ack = ~h_owns_bus_reg & m_ack; always @(posedge sys_clk or posedge resetcpu) begin if (resetcpu == 1'b1) begin active <= 1'b0; h_owns_bus_reg <= 1'b0; end else begin // Go active (and hold) if either bus requesting, clearing state on the returned ACK active <= (active | h_cyc | l_cyc) & ~m_ack; // Flag high priority bus ownership, and hold, or if that bus requesting and inactive. h_owns_bus_reg <= (active & h_owns_bus_reg) | (~active & h_cyc); end end endmodule

//------------------------------------------------------------------------- // COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License along // with this program; if not, write to the Free Software Foundation, Inc., // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. //------------------------------------------------------------------------- // Title : okWireIn_sync // Author : Caleb Fangmeier // Description : This is a simple wrapper of the okWireIn that syncronizes // the signals with another clock by means of a shallow fifo buffer. // // $Id$ //------------------------------------------------------------------------- `default_nettype none `timescale 1ns / 1ps module okWireIn_sync ( input wire clk, input wire okClk, input wire [112:0] okHE, input wire [7:0] ep_addr, output reg [31:0] ep_dataout ); wire [31:0] control_bus; wire [31:0] q_buff; wire rdempty; reg rdreq; always @( posedge clk ) begin if ( rdreq ) begin ep_dataout <= q_buff; end rdreq <= ~rdempty; end fifo32_shallow fifo32_shallow_inst ( .data ( control_bus ), .rdclk ( clk ), .rdreq ( rdreq ), .wrclk ( okClk ), .wrreq ( 1'b1 ), .q ( q_buff ), .rdempty ( rdempty ), .wrfull ( ) ); okWireIn control_wires( .okHE(okHE), .ep_addr(ep_addr), .ep_dataout(control_bus) ); endmodule

module pipeline( input Clk, output [31:0] PC_in,PC_out, output [2:0]PCSrc, //1 /*output[5:0] Op_IF, output[4:0] Rs_IF,Rt_IF,Rd_IF,Shamt_IF, output[5:0] Func_IF, */ //3 /*output[31:0] Branch_addr_EX,PC_Add_EX, output[2:0] Condition_EX, output Branch_EX, output[2:0]PC_write_EX, output[3:0]Mem_Write_Byte_en_EX,Rd_Write_Byte_en_EX, output MemWBSrc_EX,OverflowEn_EX, output[31:0] MemData_EX,WBData_EX, output Less_EX,Zero_EX,Overflow_EX, output[4:0]Rd_EX, output flash_ID,flash_EX, //4 output[31:0] MemData_Mem,Data_out, output[31:0] WBData_Mem, output MemWBSrc_Mem, output[3:0] Rd_Write_Byte_en_Mem, output[4:0] Rd_Mem, output [31:0] Immediate32_IF,ALU_OpA,ALU_OpB,ALU_out,RegShift, output [1:0] Rs_EX_Forward,Rt_EX_Forward, output [4:0]ShiftAmount */ output flash_ID,flash_EX, output [31:0] OperandA_ID,OperandB_ID, output [4:0] Rs_ID,Rt_ID,Rd_ID,Rd_EX,Rd_Mem, output [31:0] Immediate32_ID, output [2:0] MemDataSrc_ID, output ALUSrcA_ID,ALUSrcB_ID,Jump_ID, output [3:0] ALUOp_ID,Rd_Write_Byte_en_Mem,MemWriteEn,RdWriteEn, output [31:0] IR_IF,Shifter_out,Rd_in,MemData_EX,Data_out,WBData_EX, output [4:0]ShiftAmount, output [1:0] Rs_EX_Forward,Rt_EX_Forward, output [31:0] Immediate32_IF,ALU_OpA,ALU_OpB,ALU_out,RegShift ); //--------Harzard---------------------------------- //wire[2:0] PCSrc; //--------PC--------------------------------------- //wire[31:0] PC_in,PC_out; //--------PC+4------------------------------------- wire[31:0] PC_Add_IF; //--------InstruMemory----------------------------- wire[31:0] ins_data;//,IR_IF; //--------IF_ID Seg1------------------------------- wire stall_IF; wire flash_IF; wire[5:0] Op_IF; wire[4:0] Rs_IF,Rt_IF,Rd_IF,Shamt_IF; wire[5:0] Func_IF; //--------Controller------------------------------- wire RegDt0_IF,ID_RsRead_IF,ID_RtRead_IF; wire[1:0] Ex_top_IF; wire BranchSel_IF; wire OverflowEn_IF; wire[2:0] Condition_IF; wire Branch_IF; wire[2:0] PC_write_IF; wire[3:0] Mem_Write_Byte_en_IF,Rd_Write_Byte_en_IF,ALUOp_IF; wire MemWBSrc_IF; wire Jump_IF; wire ALUShiftSel_IF; wire[2:0] MemDataSrc_IF; wire ALUSrcA_IF,ALUSrcB_IF; //wire[3:0] ALUOp_IF; wire[1:0] RegDst_IF; wire ShiftAmountSrc_IF; wire[1:0] Shift_Op_IF; //---------Registers------------------------------- wire[31:0] Rs_out,Rt_out;//Rd_in //---------expansion------------------------------- //wire[31:0] Immediate32_IF; //---------ID_EX Seg2------------------------------ wire stall_ID;//flash_ID, wire[31:0]PC_Add_ID; wire OverflowEn_ID; wire[2:0] Condition_ID; wire Branch_ID,EX_RsRead_ID,EX_RtRead_ID; wire[2:0] PC_write_ID; wire[3:0] Mem_Write_Byte_en_ID,Rd_Write_Byte_en_ID; wire MemWBSrc_ID,ALUShiftSel_ID; //wire[2:0] MemDataSrc_ID; //wire ALUSrcA_ID,ALUSrcB_ID; //wire[3:0] ALUOp_ID; wire[1:0] RegDst_ID; wire ShiftAmountSrc_ID; wire[1:0] Shift_Op_ID; //wire[31:0] OperandA_ID,OperandB_ID; //wire[4:0] Rs_ID,Rt_ID,Rd_ID; //wire[31:0] Immediate32_ID; wire[4:0]Shamt_ID; //----------JUMP branch--------------------------- wire[31:0] Branch_addr_ID,Jump_Done; //----------Forward------------------------------- //wire[1:0] Rs_EX_Forward,Rt_EX_Forward; wire Rs_LoudUse_Forward,Rt_LoudUse_Forward; //----------After ALU and ID/EX mux--------------- wire[31:0] mux4one,mux4two,mux4three,mux8one; wire Zero,Less,Overflow,BranchSel_ID; //wire[31:0] ALU_out; //----------Shifter------------------------------- //wire[31:0] Shifter_out; //wire [4:0]ShiftAmount; //----------Ex_MEM Seg3-------------------------- wire stall_EX;//flash_EX wire OverflowEn_EX; wire[31:0] Branch_addr_EX,PC_Add_EX; wire[2:0] Condition_EX; wire Branch_EX,MemWBSrc_EX; wire[2:0]PC_write_EX; wire[3:0]Mem_Write_Byte_en_EX,Rd_Write_Byte_en_EX; //wire[31:0] WBData_EX;//MemData_EX, wire Less_EX,Zero_EX,Overflow_EX; //wire[4:0]Rd_EX; //----------Condition------------------------------ wire BranchValid; //wire[3:0] RdWriteEn;//,MemWriteEn; //----------DataMemory----------------------------- wire [31:0]Mem_data_shift; //----------MEM_WB Seg4--------------------------- wire stall_Mem,flash_Mem; wire[31:0] MemData_Mem; wire[31:0] WBData_Mem; wire MemWBSrc_Mem; //wire[3:0] Rd_Write_Byte_en_Mem; //wire[4:0] Rd_Mem; //-----------------------------------------------Hazard------------------------------------------------------- HazardControl hazard(BranchValid,Jump_ID,MemWBSrc_ID,ID_RsRead_IF,ID_RtRead_IF,Rs_IF,Rt_IF,Rt_ID, //output stall_IF,stall_ID,stall_EX,stall_Mem,flash_IF,flash_ID,flash_EX,flash_Mem,PCSrc); //-------------------------------------------------PC--------------------------------------------------------- wire[31:0] PC_Add_IF_in; Mux4_1 PC_selcet(PC_Add_IF,Jump_Done,Branch_addr_EX,mux4one,PCSrc,PC_in); PC pc(Clk,PC_in,PC_out); //------------------------------------------------PC+4--------------------------------------------------------- assign PC_Add_IF_in = PC_out + 4; //---------------------------------------------InstructMemory-------------------------------------------------- parameter ins_we = 4'b0000; assign ins_data = 0; InstruMemory instruct(ins_data,PC_out,ins_we,Clk,IR_IF); //----------------------------------------------IF_ID_Seg Seg1------------------------------------------------- IF_ID_Seg Seg1(Clk,stall_IF,flash_IF,PC_Add_IF_in,IR_IF,PC_Add_IF,Op_IF,Rs_IF,Rt_IF,Rd_IF,Shamt_IF,Func_IF); //----------------------------------------------Controller----------------------------------------------------- Controller controller(Op_IF,Rs_IF,Rt_IF,Rd_IF,Shamt_IF,Func_IF,RegDt0_IF,ID_RsRead_IF,ID_RtRead_IF,Ex_top_IF,BranchSel_IF, OverflowEn_IF,Condition_IF,Branch_IF,PC_write_IF,Mem_Write_Byte_en_IF,Rd_Write_Byte_en_IF,MemWBSrc_IF,Jump_IF, ALUShiftSel_IF,MemDataSrc_IF,ALUSrcA_IF,ALUSrcB_IF,ALUOp_IF,RegDst_IF,ShiftAmountSrc_IF,Shift_Op_IF); //----------------------------------------------Registers------------------------------------------------------ assign Rd_in = (MemWBSrc_Mem == 0)?WBData_Mem:MemData_Mem; MIPS_Register mipsregister(Rs_IF,((RegDt0_IF == 1'b1)?Rt_IF:5'b00000),Rd_Mem,Clk,Rd_Write_Byte_en_Mem,Rd_in,Rs_out,Rt_out); //--------------------------------------------expansion-------------------------------------------------------- NumExpansion expansion({Rd_IF[4:0],Shamt_IF[4:0],Func_IF[5:0]},Ex_top_IF,Immediate32_IF); //------------------------------------------ID_EX Seg2------------------------------------------------------- ID_EX_Seg seg2(Clk,stall_ID,flash_ID,PC_Add_IF,OverflowEn_IF,Condition_IF,Branch_IF,PC_write_IF, Mem_Write_Byte_en_IF,Rd_Write_Byte_en_IF,MemWBSrc_IF,Jump_IF,ALUShiftSel_IF,MemDataSrc_IF,ALUSrcA_IF,ALUSrcB_IF, ALUOp_IF,RegDst_IF,ShiftAmountSrc_IF,Shift_Op_IF,(Rs_LoudUse_Forward == 0)?Rs_out:Rd_in, (Rt_LoudUse_Forward == 0)?Rt_out:Rd_in,Rs_IF,Rt_IF,Rd_IF,Immediate32_IF,Shamt_IF,BranchSel_IF, {ID_RsRead_IF,ID_RtRead_IF}, //output PC_Add_ID,OverflowEn_ID,Condition_ID,Branch_ID,PC_write_ID,Mem_Write_Byte_en_ID,Rd_Write_Byte_en_ID, MemWBSrc_ID,Jump_ID,ALUShiftSel_ID,MemDataSrc_ID,ALUSrcA_ID,ALUSrcB_ID, ALUOp_ID,RegDst_ID,ShiftAmountSrc_ID,Shift_Op_ID,OperandA_ID,OperandB_ID,Rs_ID,Rt_ID,Rd_ID,Immediate32_ID,Shamt_ID, BranchSel_ID,{EX_RsRead_ID,EX_RtRead_ID} ); //----------------------------------------JUMP branch Module--------------------------------------------------- assign Branch_addr_ID = PC_Add_ID + {Immediate32_ID[29:0],2'b00}; assign Jump_Done = {PC_Add_ID[31:28],Rs_ID,Rt_ID,Immediate32_ID[15:0],2'b00}; //-----------------------------------------forward------------------------------------------------------------- Forward forward({EX_RsRead_ID,EX_RtRead_ID},Rt_ID,Rs_ID,Rd_EX,RdWriteEn,Rd_Mem,Rd_Write_Byte_en_Mem, //output Rs_EX_Forward,Rt_EX_Forward, //input Rt_IF,Rs_IF,{ID_RsRead_IF,ID_RtRead_IF}, //output Rs_LoudUse_Forward,Rt_LoudUse_Forward); //--------------------------------------after ALU and ID/EX Mux------------------------------------------------ Mux4_1 mux4_one(OperandA_ID,WBData_EX,Rd_in,0,Rs_EX_Forward,mux4one); Mux4_1 mux4_two(OperandB_ID,WBData_EX,Rd_in,0,Rt_EX_Forward,mux4two); Mux4_1 mux4_three(Rd_ID,Rt_ID,5'b11111,0,RegDst_ID,mux4three); MUX8_1_ALU mux8_one(MemDataSrc_ID,32'b0,mux4two,PC_Add_ID + 4,0,0,0,0,0,mux8one); //rt assign ALU_OpA = (ALUSrcA_ID == 0)?mux4one:0; assign ALU_OpB = (ALUSrcB_ID == 0)?mux4two:Immediate32_ID; ALU alu(ALU_OpA,ALU_OpB,ALUOp_ID,Zero,Less,Overflow,ALU_out); assign ShiftAmount = (ShiftAmountSrc_ID == 1)?mux4one[4:0]:Shamt_ID; //--------------------------------------------shifter----------------------------------------------------------- MIPS_Shifter shifter(mux4two,ShiftAmount,Shift_Op_ID,Shifter_out); //-----------------------------------------EX_MEM---Seg3-------------------------------------------------------- EX_MEM_Seg seg3(Clk,stall_EX,flash_EX,Branch_addr_ID,PC_Add_ID,Condition_ID,Branch_ID,PC_write_ID, Mem_Write_Byte_en_ID,Rd_Write_Byte_en_ID,MemWBSrc_ID,OverflowEn_ID, mux8one,((BranchSel_ID == 1'b0) ? ((ALUShiftSel_ID == 1'b0)?Shifter_out:ALU_out): mux8one),Less,Zero,Overflow,mux4three, //output Branch_addr_EX,PC_Add_EX,Condition_EX,Branch_EX,PC_write_EX,Mem_Write_Byte_en_EX, Rd_Write_Byte_en_EX,MemWBSrc_EX,OverflowEn_EX, MemData_EX,WBData_EX,Less_EX,Zero_EX,Overflow_EX,Rd_EX ); //----------------------------------------Condition-------------------------------------------------------------- Condition_Check condition_check(Condition_EX,PC_write_EX,WBData_EX[1:0],MemWBSrc_EX,OverflowEn_EX,Branch_EX,Overflow_EX,Mem_Write_Byte_en_EX,Rd_Write_Byte_en_EX,Less_EX,Zero_EX, //output BranchValid,RdWriteEn,MemWriteEn); //---------------------------------------DataMemory-------------------------------------------------------------- //wire [31:0] RegShift; Register_ShiftOutput regshift(MemData_EX,WBData_EX[1:0],{3'b101,PC_write_EX[2:0]},RegShift); DataMemory datamemory(RegShift,WBData_EX,MemWriteEn,Clk,Data_out); Memory_ShiftOutput memshift(Data_out,WBData_EX[1:0],{3'b100,PC_write_EX[2:0]},Mem_data_shift); //---------------------------------------DataMemoryWithCache----------------------------------------------------- //------------------------------You can choose one section from DataMemory or DataMemory with cache-------------- /*wire hit; wire [63:0] ReadRam; wire writeback; wire [7:0] readramn,writeramn; Register_ShiftOutput regshift(MemData_EX,WBData_EX[1:0],{3'b101,PC_write_EX[2:0]},RegShift); Cache DataMemorywithCache(RegShift,WBData_EX,MemWriteEn,Clk,Data_out,hit,ReadRam,writeback,readramn,writeramn); Memory_ShiftOutput memshift(Data_out,WBData_EX[1:0],{3'b100,PC_write_EX[2:0]},Mem_data_shift); */ //--------------------------------------MEM_WB---Seg4------------------------------------------------------------ MEM_WB_Seg seg4(Clk,stall_Mem,flash_Mem,Mem_data_shift,WBData_EX,MemWBSrc_EX,RdWriteEn,Rd_EX, //output MemData_Mem,WBData_Mem,MemWBSrc_Mem,Rd_Write_Byte_en_Mem,Rd_Mem); endmodule

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HDLL__XNOR2_PP_SYMBOL_V `define SKY130_FD_SC_HDLL__XNOR2_PP_SYMBOL_V /** * xnor2: 2-input exclusive NOR. * * Y = !(A ^ B) * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hdll__xnor2 ( //# {{data|Data Signals}} input A , input B , output Y , //# {{power|Power}} input VPB , input VPWR, input VGND, input VNB ); endmodule `default_nettype wire `endif // SKY130_FD_SC_HDLL__XNOR2_PP_SYMBOL_V

`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 17:25:47 05/08/2012 // Design Name: cls_spi // Module Name: G:/Projects/s6atlystest/cls_spi_tb.v // Project Name: s6atlystest // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: cls_spi // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module cls_spi_tb; // Inputs reg clock; reg reset; reg [31:0] data; reg miso; // Outputs wire ss; wire mosi; wire sclk; // Instantiate the Unit Under Test (UUT) cls_spi uut ( .clock(clock), .reset(reset), .data(data), .ss(ss), .mosi(mosi), .miso(miso), .sclk(sclk) ); initial begin // Initialize Inputs clock = 0; reset = 1; data = 32'h89ABCDEF; miso = 0; // Wait 100 ns for global reset to finish #100 reset = 0; end always begin #10 clock = !clock; end endmodule

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LS__DFXBP_TB_V `define SKY130_FD_SC_LS__DFXBP_TB_V /** * dfxbp: Delay flop, complementary outputs. * * Autogenerated test bench. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_ls__dfxbp.v" module top(); // Inputs are registered reg D; reg VPWR; reg VGND; reg VPB; reg VNB; // Outputs are wires wire Q; wire Q_N; initial begin // Initial state is x for all inputs. D = 1'bX; VGND = 1'bX; VNB = 1'bX; VPB = 1'bX; VPWR = 1'bX; #20 D = 1'b0; #40 VGND = 1'b0; #60 VNB = 1'b0; #80 VPB = 1'b0; #100 VPWR = 1'b0; #120 D = 1'b1; #140 VGND = 1'b1; #160 VNB = 1'b1; #180 VPB = 1'b1; #200 VPWR = 1'b1; #220 D = 1'b0; #240 VGND = 1'b0; #260 VNB = 1'b0; #280 VPB = 1'b0; #300 VPWR = 1'b0; #320 VPWR = 1'b1; #340 VPB = 1'b1; #360 VNB = 1'b1; #380 VGND = 1'b1; #400 D = 1'b1; #420 VPWR = 1'bx; #440 VPB = 1'bx; #460 VNB = 1'bx; #480 VGND = 1'bx; #500 D = 1'bx; end // Create a clock reg CLK; initial begin CLK = 1'b0; end always begin #5 CLK = ~CLK; end sky130_fd_sc_ls__dfxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK)); endmodule `default_nettype wire `endif // SKY130_FD_SC_LS__DFXBP_TB_V

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_MS__A2BB2OI_BEHAVIORAL_V `define SKY130_FD_SC_MS__A2BB2OI_BEHAVIORAL_V /** * a2bb2oi: 2-input AND, both inputs inverted, into first input, and * 2-input AND into 2nd input of 2-input NOR. * * Y = !((!A1 & !A2) | (B1 & B2)) * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none `celldefine module sky130_fd_sc_ms__a2bb2oi ( Y , A1_N, A2_N, B1 , B2 ); // Module ports output Y ; input A1_N; input A2_N; input B1 ; input B2 ; // Module supplies supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; // Local signals wire and0_out ; wire nor0_out ; wire nor1_out_Y; // Name Output Other arguments and and0 (and0_out , B1, B2 ); nor nor0 (nor0_out , A1_N, A2_N ); nor nor1 (nor1_out_Y, nor0_out, and0_out); buf buf0 (Y , nor1_out_Y ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_MS__A2BB2OI_BEHAVIORAL_V

// Single-bit clock-domain crossing synchronizer // // Notes: // A synchronizer is a device that takes an asynchronous // input and produces an output signal that transitions // synchronous to a sample clock // // The single-bit clock domain synchronizer safely // transfers the output from clock domain A to // clock domain B. Without the synchronizer, the // input of the receiving clock domain can go // metastable at the first register stage of the // sampling domain. A good synchronizer // removes the probability of input going metastable // by moving the input through register stages in // the target clock domain // // Mean Time Between Failures defines the probability // of the o/p of the sampling domain going metastable. // MTBF = 1/(freq of sampling * freq of data change *X) // Higher MTBF, the better // As freq of sampling increases, probability of metastability // is higher (lower MTBF) // // It is generally recommended that the output of the // launching clock domain is registered before synchronizing. // Consider the case where a signal is derived through some // combinational logic before getting transfered from clock // domain A to B. The probability of glitching after the // combinational logic is very high, which in turn increases // probability of metastability at the latching clock domain. // // The synchronizer may be used in different scenarios // - Case 1: Transfer from slow clock domain to fast // - Case 2: Transfer from fast clock domain to slow // - Case 3: Transfer b/w unrelated clocks with same frequency, // // Case 1 is the most straightforward. A CDC with >=2 stages is // sufficient. Case 2 is tricky because the launch data can // change multiple times before capturing in the latching domain. // In this situation, it is recommended that either the launch clock // hold the data for at-least 3 clock cycles of the latch // clock domain (open-loop solution) or hold the data until // the latch domain sends back an acknowledgment (closed-loop // solution). // module single_bit_cdc_synchronizer #( parameter NUM_STAGES = 3 // minimum 2 stages, recommended 3 stages // probability of metastability decreases // exponentially with #stages ) ( input clk, //latch clock input d_in, output q_out; ); reg[NUM_STAGES-1:0] r; assign q_out=r[NUM_STAGES-1]; integer i; always@(posedge latch_clk) begin for(i=1; i<NUM_STAGES; i=i+1) begin r[i] <= r[i-1]; end end endmodule

// Copyright (c) 2013, Simon Que // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // // Redistributions of source code must retain the above copyright notice, this // list of conditions and the following disclaimer. // Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution. // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. `timescale 1ns/1ps `include "spi_memory.vh" module SPIMemoryTest; // SPI interface. reg _select, sck, mosi; wire miso; // Memory interface. wire [`SPI_MEM_ADDR_WIDTH-1:0] addr; wire [`SPI_MEM_DATA_WIDTH-1:0] data_in; wire [`SPI_MEM_DATA_WIDTH-1:0] data_out; wire rd, wr; // Instantiate the Unit Under Test (UUT). SPIMemory spi_memory( ._select(_select), .sck(sck), .mosi(mosi), .miso(miso), .addr(addr), .data_in(data_in), .data_out(data_out), .rd(rd), .wr(wr) ); // Don't have actual memory, so just use the lower byte of address as the data // read from memory. assign data_in = rd ? addr[`SPI_MEM_DATA_WIDTH-1:0] : 'bx; initial begin _select = 0; sck = 0; mosi = 0; #1 _select = 1; // Perform some writes. #10 _select = 0; spi_transmit(8'hde); // Write to address 0x5ead. spi_transmit(8'had); spi_transmit(8'h01); // These are the data bytes written. spi_transmit(8'h02); spi_transmit(8'h04); spi_transmit(8'h08); _select = 1; #10 _select = 0; spi_transmit(8'hbe); // Write to address 0x3eef. spi_transmit(8'hef); spi_transmit(8'h11); // These are the data bytes written. spi_transmit(8'h22); spi_transmit(8'h44); spi_transmit(8'h88); _select = 1; // Perform some reads. #10 _select = 0; spi_transmit(8'h5a); // Read from address 0x5afe. spi_transmit(8'hfe); spi_transmit(8'h01); // These dummy data bytes should not show up. spi_transmit(8'h02); spi_transmit(8'h04); spi_transmit(8'h08); _select = 1; #10 _select = 0; spi_transmit(8'h7f); // Test wraparound during read. spi_transmit(8'hfe); spi_transmit(8'h11); // These dummy data bytes should not show up. spi_transmit(8'h22); spi_transmit(8'h44); spi_transmit(8'h88); _select = 1; #10 _select = 0; spi_transmit(8'hff); // Test wraparound during write. spi_transmit(8'hfe); spi_transmit(8'h11); // These dummy data bytes should not show up. spi_transmit(8'h22); spi_transmit(8'h44); spi_transmit(8'h88); _select = 1; end // Task to send a byte over SPI. task spi_transmit; input [`BYTE_WIDTH-1:0] data; integer i; begin sck = 0; #2 sck = 0; for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin mosi = data[`BYTE_WIDTH - 1 - i]; #1 sck = 1; #1 sck = 0; end #2 sck = 0; end endtask endmodule

(** * Auto: More Automation *) Require Import Coq.omega.Omega. Require Import Maps. Require Import Imp. (** Up to now, we've used the more manual part of Coq's tactic facilities. In this chapter, we'll learn more about some of Coq's powerful automation features: proof search via the [auto] tactic, automated forward reasoning via the [Ltac] hypothesis matching machinery, and deferred instantiation of existential variables using [eapply] and [eauto]. Using these features together with Ltac's scripting facilities will enable us to make our proofs startlingly short! Used properly, they can also make proofs more maintainable and robust to changes in underlying definitions. A deeper treatment of [auto] and [eauto] can be found in the [UseAuto] chapter. There's another major category of automation we haven't discussed much yet, namely built-in decision procedures for specific kinds of problems: [omega] is one example, but there are others. This topic will be deferred for a while longer. Our motivating example will be this proof, repeated with just a few small changes from the [Imp] chapter. We will simplify this proof in several stages. *) Ltac inv H := inversion H; subst; clear H. Theorem ceval_deterministic: forall c st st1 st2, c / st \\ st1 -> c / st \\ st2 -> st1 = st2. Proof. intros c st st1 st2 E1 E2; generalize dependent st2; induction E1; intros st2 E2; inv E2. - (* E_Skip *) reflexivity. - (* E_Ass *) reflexivity. - (* E_Seq *) assert (st' = st'0) as EQ1. { (* Proof of assertion *) apply IHE1_1; assumption. } subst st'0. apply IHE1_2. assumption. (* E_IfTrue *) - (* b evaluates to true *) apply IHE1. assumption. - (* b evaluates to false (contradiction) *) rewrite H in H5. inversion H5. (* E_IfFalse *) - (* b evaluates to true (contradiction) *) rewrite H in H5. inversion H5. - (* b evaluates to false *) apply IHE1. assumption. (* E_WhileEnd *) - (* b evaluates to false *) reflexivity. - (* b evaluates to true (contradiction) *) rewrite H in H2. inversion H2. (* E_WhileLoop *) - (* b evaluates to false (contradiction) *) rewrite H in H4. inversion H4. - (* b evaluates to true *) assert (st' = st'0) as EQ1. { (* Proof of assertion *) apply IHE1_1; assumption. } subst st'0. apply IHE1_2. assumption. Qed. (* ################################################################# *) (** * The [auto] Tactic *) (** Thus far, our proof scripts mostly apply relevant hypotheses or lemmas by name, and one at a time. *) Example auto_example_1 : forall (P Q R: Prop), (P -> Q) -> (Q -> R) -> P -> R. Proof. intros P Q R H1 H2 H3. apply H2. apply H1. assumption. Qed. (** The [auto] tactic frees us from this drudgery by _searching_ for a sequence of applications that will prove the goal *) Example auto_example_1' : forall (P Q R: Prop), (P -> Q) -> (Q -> R) -> P -> R. Proof. intros P Q R H1 H2 H3. auto. Qed. (** The [auto] tactic solves goals that are solvable by any combination of - [intros] and - [apply] (of hypotheses from the local context, by default). *) (** Using [auto] is always "safe" in the sense that it will never fail and will never change the proof state: either it completely solves the current goal, or it does nothing. *) (** Here is a more interesting example showing [auto]'s power: *) Example auto_example_2 : forall P Q R S T U : Prop, (P -> Q) -> (P -> R) -> (T -> R) -> (S -> T -> U) -> ((P->Q) -> (P->S)) -> T -> P -> U. Proof. auto. Qed. (** Proof search could, in principle, take an arbitrarily long time, so there are limits to how far [auto] will search by default. *) Example auto_example_3 : forall (P Q R S T U: Prop), (P -> Q) -> (Q -> R) -> (R -> S) -> (S -> T) -> (T -> U) -> P -> U. Proof. (* When it cannot solve the goal, [auto] does nothing *) auto. (* Optional argument says how deep to search (default is 5) *) auto 6. Qed. (** When searching for potential proofs of the current goal, [auto] considers the hypotheses in the current context together with a _hint database_ of other lemmas and constructors. Some common lemmas about equality and logical operators are installed in this hint database by default. *) Example auto_example_4 : forall P Q R : Prop, Q -> (Q -> R) -> P \/ (Q /\ R). Proof. auto. Qed. (** We can extend the hint database just for the purposes of one application of [auto] by writing [auto using ...]. *) Lemma le_antisym : forall n m: nat, (n <= m /\ m <= n) -> n = m. Proof. intros. omega. Qed. Example auto_example_6 : forall n m p : nat, (n <= p -> (n <= m /\ m <= n)) -> n <= p -> n = m. Proof. intros. auto. (* does nothing: auto doesn't destruct hypotheses! *) auto using le_antisym. Qed. (** Of course, in any given development there will probably be some specific constructors and lemmas that are used very often in proofs. We can add these to the global hint database by writing Hint Resolve T. at the top level, where [T] is a top-level theorem or a constructor of an inductively defined proposition (i.e., anything whose type is an implication). As a shorthand, we can write Hint Constructors c. to tell Coq to do a [Hint Resolve] for _all_ of the constructors from the inductive definition of [c]. It is also sometimes necessary to add Hint Unfold d. where [d] is a defined symbol, so that [auto] knows to expand uses of [d], thus enabling further possibilities for applying lemmas that it knows about. *) Hint Resolve le_antisym. Example auto_example_6' : forall n m p : nat, (n<= p -> (n <= m /\ m <= n)) -> n <= p -> n = m. Proof. intros. auto. (* picks up hint from database *) Qed. Definition is_fortytwo x := x = 42. Example auto_example_7: forall x, (x <= 42 /\ 42 <= x) -> is_fortytwo x. Proof. auto. (* does nothing *) Abort. Hint Unfold is_fortytwo. Example auto_example_7' : forall x, (x <= 42 /\ 42 <= x) -> is_fortytwo x. Proof. auto. Qed. (** Now let's take a first pass over [ceval_deterministic] to simplify the proof script. *) Theorem ceval_deterministic': forall c st st1 st2, c / st \\ st1 -> c / st \\ st2 -> st1 = st2. Proof. intros c st st1 st2 E1 E2. generalize dependent st2; induction E1; intros st2 E2; inv E2; auto. - (* E_Seq *) assert (st' = st'0) as EQ1 by auto. subst st'0. auto. - (* E_IfTrue *) + (* b evaluates to false (contradiction) *) rewrite H in H5. inversion H5. - (* E_IfFalse *) + (* b evaluates to true (contradiction) *) rewrite H in H5. inversion H5. - (* E_WhileEnd *) + (* b evaluates to true (contradiction) *) rewrite H in H2. inversion H2. (* E_WhileLoop *) - (* b evaluates to false (contradiction) *) rewrite H in H4. inversion H4. - (* b evaluates to true *) assert (st' = st'0) as EQ1 by auto. subst st'0. auto. Qed. (** When we are using a particular tactic many times in a proof, we can use a variant of the [Proof] command to make that tactic into a default within the proof. Saying [Proof with t] (where [t] is an arbitrary tactic) allows us to use [t1...] as a shorthand for [t1;t] within the proof. As an illustration, here is an alternate version of the previous proof, using [Proof with auto]. *) Theorem ceval_deterministic'_alt: forall c st st1 st2, c / st \\ st1 -> c / st \\ st2 -> st1 = st2. Proof with auto. intros c st st1 st2 E1 E2; generalize dependent st2; induction E1; intros st2 E2; inv E2... - (* E_Seq *) assert (st' = st'0) as EQ1... subst st'0... - (* E_IfTrue *) + (* b evaluates to false (contradiction) *) rewrite H in H5. inversion H5. - (* E_IfFalse *) + (* b evaluates to true (contradiction) *) rewrite H in H5. inversion H5. - (* E_WhileEnd *) + (* b evaluates to true (contradiction) *) rewrite H in H2. inversion H2. (* E_WhileLoop *) - (* b evaluates to false (contradiction) *) rewrite H in H4. inversion H4. - (* b evaluates to true *) assert (st' = st'0) as EQ1... subst st'0... Qed. (* ################################################################# *) (** * Searching For Hypotheses *) (** The proof has become simpler, but there is still an annoying amount of repetition. Let's start by tackling the contradiction cases. Each of them occurs in a situation where we have both H1: beval st b = false and H2: beval st b = true as hypotheses. The contradiction is evident, but demonstrating it is a little complicated: we have to locate the two hypotheses [H1] and [H2] and do a [rewrite] following by an [inversion]. We'd like to automate this process. (In fact, Coq has a built-in tactic [congruence] that will do the job in this case. But we'll ignore the existence of this tactic for now, in order to demonstrate how to build forward search tactics by hand.) As a first step, we can abstract out the piece of script in question by writing a little function in Coq's tactic programming language, Ltac. *) Ltac rwinv H1 H2 := rewrite H1 in H2; inv H2. Theorem ceval_deterministic'': forall c st st1 st2, c / st \\ st1 -> c / st \\ st2 -> st1 = st2. Proof. intros c st st1 st2 E1 E2. generalize dependent st2; induction E1; intros st2 E2; inv E2; auto. - (* E_Seq *) assert (st' = st'0) as EQ1 by auto. subst st'0. auto. - (* E_IfTrue *) + (* b evaluates to false (contradiction) *) rwinv H H5. - (* E_IfFalse *) + (* b evaluates to true (contradiction) *) rwinv H H5. - (* E_WhileEnd *) + (* b evaluates to true (contradiction) *) rwinv H H2. (* E_WhileLoop *) - (* b evaluates to false (contradiction) *) rwinv H H4. - (* b evaluates to true *) assert (st' = st'0) as EQ1 by auto. subst st'0. auto. Qed. (** That was is a bit better, but not much. We really want Coq to discover the relevant hypotheses for us. We can do this by using the [match goal] facility of Ltac. *) Ltac find_rwinv := match goal with H1: ?E = true, H2: ?E = false |- _ => rwinv H1 H2 end. (** The [match goal] tactic looks for two distinct hypotheses that have the form of equalities, with the same arbitrary expression [E] on the left and with conflicting boolean values on the right. If such hypotheses are found, it binds [H1] and [H2] to their names and applies the [rwinv] tactic to [H1] and [H2]. Adding this tactic to the ones that we invoke in each case of the induction handles all of the contradictory cases. *) Theorem ceval_deterministic''': forall c st st1 st2, c / st \\ st1 -> c / st \\ st2 -> st1 = st2. Proof. intros c st st1 st2 E1 E2. generalize dependent st2; induction E1; intros st2 E2; inv E2; try find_rwinv; auto. - (* E_Seq *) assert (st' = st'0) as EQ1 by auto. subst st'0. auto. - (* E_WhileLoop *) + (* b evaluates to true *) assert (st' = st'0) as EQ1 by auto. subst st'0. auto. Qed. (** Let's see about the remaining cases. Each of them involves applying a conditional hypothesis to extract an equality. Currently we have phrased these as assertions, so that we have to predict what the resulting equality will be (although we can then use [auto] to prove it). An alternative is to pick the relevant hypotheses to use and then rewrite with them, as follows: *) Theorem ceval_deterministic'''': forall c st st1 st2, c / st \\ st1 -> c / st \\ st2 -> st1 = st2. Proof. intros c st st1 st2 E1 E2. generalize dependent st2; induction E1; intros st2 E2; inv E2; try find_rwinv; auto. - (* E_Seq *) rewrite (IHE1_1 st'0 H1) in *. auto. - (* E_WhileLoop *) + (* b evaluates to true *) rewrite (IHE1_1 st'0 H3) in *. auto. Qed. (** Now we can automate the task of finding the relevant hypotheses to rewrite with. *) Ltac find_eqn := match goal with H1: forall x, ?P x -> ?L = ?R, H2: ?P ?X |- _ => rewrite (H1 X H2) in * end. (** The pattern [forall x, ?P x -> ?L = ?R] matches any hypothesis of the form "for all [x], _some property of [x]_ implies _some equality_." The property of [x] is bound to the pattern variable [P], and the left- and right-hand sides of the equality are bound to [L] and [R]. The name of this hypothesis is bound to [H1]. Then the pattern [?P ?X] matches any hypothesis that provides evidence that [P] holds for some concrete [X]. If both patterns succeed, we apply the [rewrite] tactic (instantiating the quantified [x] with [X] and providing [H2] as the required evidence for [P X]) in all hypotheses and the goal. One problem remains: in general, there may be several pairs of hypotheses that have the right general form, and it seems tricky to pick out the ones we actually need. A key trick is to realize that we can _try them all_! Here's how this works: - each execution of [match goal] will keep trying to find a valid pair of hypotheses until the tactic on the RHS of the match succeeds; if there are no such pairs, it fails; - [rewrite] will fail given a trivial equation of the form [X = X]; - we can wrap the whole thing in a [repeat], which will keep doing useful rewrites until only trivial ones are left. *) Theorem ceval_deterministic''''': forall c st st1 st2, c / st \\ st1 -> c / st \\ st2 -> st1 = st2. Proof. intros c st st1 st2 E1 E2. generalize dependent st2; induction E1; intros st2 E2; inv E2; try find_rwinv; repeat find_eqn; auto. Qed. (** The big payoff in this approach is that our proof script should be robust in the face of modest changes to our language. For example, we can add a [REPEAT] command to the language. *) Module Repeat. Inductive com : Type := | CSkip : com | CAsgn : id -> aexp -> com | CSeq : com -> com -> com | CIf : bexp -> com -> com -> com | CWhile : bexp -> com -> com | CRepeat : com -> bexp -> com. (** [REPEAT] behaves like [WHILE], except that the loop guard is checked _after_ each execution of the body, with the loop repeating as long as the guard stays _false_. Because of this, the body will always execute at least once. *) Notation "'SKIP'" := CSkip. Notation "c1 ; c2" := (CSeq c1 c2) (at level 80, right associativity). Notation "X '::=' a" := (CAsgn X a) (at level 60). Notation "'WHILE' b 'DO' c 'END'" := (CWhile b c) (at level 80, right associativity). Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" := (CIf e1 e2 e3) (at level 80, right associativity). Notation "'REPEAT' e1 'UNTIL' b2 'END'" := (CRepeat e1 b2) (at level 80, right associativity). Inductive ceval : state -> com -> state -> Prop := | E_Skip : forall st, ceval st SKIP st | E_Ass : forall st a1 n X, aeval st a1 = n -> ceval st (X ::= a1) (t_update st X n) | E_Seq : forall c1 c2 st st' st'', ceval st c1 st' -> ceval st' c2 st'' -> ceval st (c1 ; c2) st'' | E_IfTrue : forall st st' b1 c1 c2, beval st b1 = true -> ceval st c1 st' -> ceval st (IFB b1 THEN c1 ELSE c2 FI) st' | E_IfFalse : forall st st' b1 c1 c2, beval st b1 = false -> ceval st c2 st' -> ceval st (IFB b1 THEN c1 ELSE c2 FI) st' | E_WhileEnd : forall b1 st c1, beval st b1 = false -> ceval st (WHILE b1 DO c1 END) st | E_WhileLoop : forall st st' st'' b1 c1, beval st b1 = true -> ceval st c1 st' -> ceval st' (WHILE b1 DO c1 END) st'' -> ceval st (WHILE b1 DO c1 END) st'' | E_RepeatEnd : forall st st' b1 c1, ceval st c1 st' -> beval st' b1 = true -> ceval st (CRepeat c1 b1) st' | E_RepeatLoop : forall st st' st'' b1 c1, ceval st c1 st' -> beval st' b1 = false -> ceval st' (CRepeat c1 b1) st'' -> ceval st (CRepeat c1 b1) st''. Notation "c1 '/' st '\\' st'" := (ceval st c1 st') (at level 40, st at level 39). (** Our first attempt at the proof is disappointing: the [E_RepeatEnd] and [E_RepeatLoop] cases are not handled by our previous automation. *) Theorem ceval_deterministic: forall c st st1 st2, c / st \\ st1 -> c / st \\ st2 -> st1 = st2. Proof. intros c st st1 st2 E1 E2. generalize dependent st2; induction E1; intros st2 E2; inv E2; try find_rwinv; repeat find_eqn; auto. - (* E_RepeatEnd *) + (* b evaluates to false (contradiction) *) find_rwinv. (* oops: why didn't [find_rwinv] solve this for us already? answer: we did things in the wrong order. *) - (* E_RepeatLoop *) + (* b evaluates to true (contradiction) *) find_rwinv. Qed. (** To fix this, we just have to swap the invocations of [find_eqn] and [find_rwinv]. *) Theorem ceval_deterministic': forall c st st1 st2, c / st \\ st1 -> c / st \\ st2 -> st1 = st2. Proof. intros c st st1 st2 E1 E2. generalize dependent st2; induction E1; intros st2 E2; inv E2; repeat find_eqn; try find_rwinv; auto. Qed. End Repeat. (** These examples just give a flavor of what "hyper-automation" can achieve in Coq. The details of [match goal] are a bit tricky, and debugging scripts using it is, frankly, not very pleasant. But it is well worth adding at least simple uses to your proofs, both to avoid tedium and to "future proof" them. *) (* ----------------------------------------------------------------- *) (** *** [eapply] and [eauto] *) (** To close the chapter, we'll introduce one more convenient feature of Coq: its ability to delay instantiation of quantifiers. To motivate this feature, recall this example from the [Imp] chapter: *) Example ceval_example1: (X ::= ANum 2;; IFB BLe (AId X) (ANum 1) THEN Y ::= ANum 3 ELSE Z ::= ANum 4 FI) / empty_state \\ (t_update (t_update empty_state X 2) Z 4). Proof. (* We supply the intermediate state [st']... *) apply E_Seq with (t_update empty_state X 2). - apply E_Ass. reflexivity. - apply E_IfFalse. reflexivity. apply E_Ass. reflexivity. Qed. (** In the first step of the proof, we had to explicitly provide a longish expression to help Coq instantiate a "hidden" argument to the [E_Seq] constructor. This was needed because the definition of [E_Seq]... E_Seq : forall c1 c2 st st' st'', c1 / st \\ st' -> c2 / st' \\ st'' -> (c1 ;; c2) / st \\ st'' is quantified over a variable, [st'], that does not appear in its conclusion, so unifying its conclusion with the goal state doesn't help Coq find a suitable value for this variable. If we leave out the [with], this step fails ("Error: Unable to find an instance for the variable [st']"). What's silly about this error is that the appropriate value for [st'] will actually become obvious in the very next step, where we apply [E_Ass]. If Coq could just wait until we get to this step, there would be no need to give the value explicitly. This is exactly what the [eapply] tactic gives us: *) Example ceval'_example1: (X ::= ANum 2;; IFB BLe (AId X) (ANum 1) THEN Y ::= ANum 3 ELSE Z ::= ANum 4 FI) / empty_state \\ (t_update (t_update empty_state X 2) Z 4). Proof. eapply E_Seq. (* 1 *) - apply E_Ass. (* 2 *) reflexivity. (* 3 *) - (* 4 *) apply E_IfFalse. reflexivity. apply E_Ass. reflexivity. Qed. (** The tactic [eapply H] tactic behaves just like [apply H] except that, after it finishes unifying the goal state with the conclusion of [H], it does not bother to check whether all the variables that were introduced in the process have been given concrete values during unification. If you step through the proof above, you'll see that the goal state at position [1] mentions the _existential variable_ [?st'] in both of the generated subgoals. The next step (which gets us to position [2]) replaces [?st'] with a concrete value. This new value contains a new existential variable [?n], which is instantiated in its turn by the following [reflexivity] step, position [3]. When we start working on the second subgoal (position [4]), we observe that the occurrence of [?st'] in this subgoal has been replaced by the value that it was given during the first subgoal. *) (** Several of the tactics that we've seen so far, including [exists], [constructor], and [auto], have [e...] variants. For example, here's a proof using [eauto]: *) Hint Constructors ceval. Hint Transparent state. Hint Transparent total_map. Definition st12 := t_update (t_update empty_state X 1) Y 2. Definition st21 := t_update (t_update empty_state X 2) Y 1. Example auto_example_8 : exists s', (IFB (BLe (AId X) (AId Y)) THEN (Z ::= AMinus (AId Y) (AId X)) ELSE (Y ::= APlus (AId X) (AId Z)) FI) / st21 \\ s'. Proof. eauto. Qed. (** The [eauto] tactic works just like [auto], except that it uses [eapply] instead of [apply]. *) (** $Date: 2016-10-18 15:42:43 -0400 (Tue, 18 Oct 2016) $ *)

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_TB_V `define SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_TB_V /** * UDP_OUT :=x when VPWR!=1 or VGND!=0 * UDP_OUT :=UDP_IN when VPWR==1 and VGND==0 * * Autogenerated test bench. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_lp__udp_pwrgood_pp_pg_s.v" module top(); // Inputs are registered reg UDP_IN; reg VPWR; reg VGND; reg SLEEP; // Outputs are wires wire UDP_OUT; initial begin // Initial state is x for all inputs. SLEEP = 1'bX; UDP_IN = 1'bX; VGND = 1'bX; VPWR = 1'bX; #20 SLEEP = 1'b0; #40 UDP_IN = 1'b0; #60 VGND = 1'b0; #80 VPWR = 1'b0; #100 SLEEP = 1'b1; #120 UDP_IN = 1'b1; #140 VGND = 1'b1; #160 VPWR = 1'b1; #180 SLEEP = 1'b0; #200 UDP_IN = 1'b0; #220 VGND = 1'b0; #240 VPWR = 1'b0; #260 VPWR = 1'b1; #280 VGND = 1'b1; #300 UDP_IN = 1'b1; #320 SLEEP = 1'b1; #340 VPWR = 1'bx; #360 VGND = 1'bx; #380 UDP_IN = 1'bx; #400 SLEEP = 1'bx; end sky130_fd_sc_lp__udp_pwrgood_pp$PG$S dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .SLEEP(SLEEP), .UDP_OUT(UDP_OUT)); endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_TB_V

//------------------------------------------------------------------- //-- counter_tb.v //-- Banco de pruebas para el contador //------------------------------------------------------------------- //-- BQ August 2015. Written by Juan Gonzalez (Obijuan) //------------------------------------------------------------------- module counter_tb(); //-- Registro para generar la señal de reloj reg clk = 0; //-- Datos de salida del contador wire [26:0] data; //-- Registro para comprobar si el contador cuenta correctamente reg [26:0] counter_check = 1; //-- Instanciar el contador counter C1( .clk(clk), .data(data) ); //-- Generador de reloj. Periodo 2 unidades always #1 clk = ~clk; //-- Comprobacion del valor del contador //-- En cada flanco de bajada se comprueba la salida del contador //-- y se incrementa el valor esperado always @(negedge clk) begin if (counter_check != data) $display("-->ERROR!. Esperado: %d. Leido: %d",counter_check, data); counter_check <= counter_check + 1; end //-- Proceso al inicio initial begin //-- Fichero donde almacenar los resultados $dumpfile("counter_tb.vcd"); $dumpvars(0, counter_tb); //-- Comprobación del reset. # 0.5 if (data != 0) $display("ERROR! Contador NO está a 0!"); else $display("Contador inicializado. OK."); # 99 $display("FIN de la simulacion"); # 100 $finish; end endmodule

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HS__O41AI_FUNCTIONAL_V `define SKY130_FD_SC_HS__O41AI_FUNCTIONAL_V /** * o41ai: 4-input OR into 2-input NAND. * * Y = !((A1 | A2 | A3 | A4) & B1) * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import sub cells. `include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v" `celldefine module sky130_fd_sc_hs__o41ai ( VPWR, VGND, Y , A1 , A2 , A3 , A4 , B1 ); // Module ports input VPWR; input VGND; output Y ; input A1 ; input A2 ; input A3 ; input A4 ; input B1 ; // Local signals wire A4 or0_out ; wire nand0_out_Y ; wire u_vpwr_vgnd0_out_Y; // Name Output Other arguments or or0 (or0_out , A4, A3, A2, A1 ); nand nand0 (nand0_out_Y , B1, or0_out ); sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND); buf buf0 (Y , u_vpwr_vgnd0_out_Y ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HS__O41AI_FUNCTIONAL_V

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__DLXTP_FUNCTIONAL_PP_V `define SKY130_FD_SC_LP__DLXTP_FUNCTIONAL_PP_V /** * dlxtp: Delay latch, non-inverted enable, single output. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v" `celldefine module sky130_fd_sc_lp__dlxtp ( Q , D , GATE, VPWR, VGND, VPB , VNB ); // Module ports output Q ; input D ; input GATE; input VPWR; input VGND; input VPB ; input VNB ; // Local signals wire buf_Q ; wire GATE_delayed; wire D_delayed ; // Delay Name Output Other arguments sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND); buf buf0 (Q , buf_Q ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_LP__DLXTP_FUNCTIONAL_PP_V

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_MS__NAND4_FUNCTIONAL_PP_V `define SKY130_FD_SC_MS__NAND4_FUNCTIONAL_PP_V /** * nand4: 4-input NAND. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v" `celldefine module sky130_fd_sc_ms__nand4 ( Y , A , B , C , D , VPWR, VGND, VPB , VNB ); // Module ports output Y ; input A ; input B ; input C ; input D ; input VPWR; input VGND; input VPB ; input VNB ; // Local signals wire nand0_out_Y ; wire pwrgood_pp0_out_Y; // Name Output Other arguments nand nand0 (nand0_out_Y , D, C, B, A ); sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND); buf buf0 (Y , pwrgood_pp0_out_Y ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_MS__NAND4_FUNCTIONAL_PP_V

// MBT 7/7/16 // // bsg_channel_tunnel // // This module allows you to multiplex multiple streams over a shared // interconnect without having deadlock occur because of stream interleaving. // // There are three models for interleaving streams: // // a. Your stream is guaranteed to be sunk by the remote node without // dependence on external factors, and does not rely upon back pressure. // In this case you avoid deadlock but may have fairness issues. Here, you // attach directly to the shared interconnect (e.g. bsg_fsb). // // b. Your streams rely upon back pressure from the remote node. Here, you // can use multiple bsg_channel_tunnel modules, one for each stream. // This ensures that you do not deadlock, but it does not address unfairness // in the interconnect that may lead to starvation. // // c. Your stream rely upon back pressure from the remote node. In this // scenario, you use one bsg_channel_tunnel across multiple streams. // Within this group of streams, you will have round-robin fairness. // // Channel tunneling is like virtual channels except that it includes // credits as part of the channels, and it does not // require the virtual channels to demultiplex at every step. // // Finally, especially when crossing chip boundaries (and using case c), // we can aggregrate the FIFO space into a single // large FIFO which is more efficient per bit than many smaller FIFOs. // // 1. remote_credits_p typical set to 2X bandwidth delay product of link // // ASIC<->ASIC // // e.g. if the core frequency is 1000 MHz, and the off-chip frequency // is 300 MHz, and the off-chip link is 0.4 word/cycle, and the 1-way latency // in the core domain is 5 cycles, and the latency in the off-chip // domain is 10 cycles, then: // // one-way chip latency = 5 * 1 ns + 10 * 3.3 ns = 38.3 ns // bandwidth = 0.4 words / 3.33 ns = .133 words / ns // bandwidth * delay = .133 * 35 = 4.6 words // // * 2 ASICS = 9.2 words // * 2 (roundtrip) = 18.4 words // // ASIC<->FPGA // // note, if there is an FPGA in the loop, then latencies blow up. // suppose the FPGA runs at 300*.4 = 120 Mhz=8.3ns, and so the on-FPGA latency // is 38.3 * (8.3) = 314 ns. then one way latency is 352 ns, and buffering is // (.133 * (352))*2 = 93 words. // // 2. area grows as num_in_p * remote_credits_p // // // 3. area for all channels can be stored in a single place when using alternate // implementations of virtual fifos // `include "bsg_defines.v" module bsg_channel_tunnel #(parameter width_p = 1 , parameter `BSG_INV_PARAM(num_in_p) , parameter `BSG_INV_PARAM(remote_credits_p) , use_pseudo_large_fifo_p = 0 , harden_small_fifo_p = 0 , lg_remote_credits_lp = $clog2(remote_credits_p+1) , lg_credit_decimation_p = `BSG_MIN(lg_remote_credits_lp,4) , tag_width_lp = $clog2(num_in_p+1) , tagged_width_lp = tag_width_lp + width_p ) (input clk_i ,input reset_i // incoming multiplexed data ,input [tagged_width_lp-1:0] multi_data_i ,input multi_v_i ,output multi_yumi_o // outgoing multiplexed data , output [tagged_width_lp-1:0] multi_data_o , output multi_v_o , input multi_yumi_i // incoming demultiplexed data , input [num_in_p-1:0][width_p-1:0] data_i , input [num_in_p-1:0] v_i , output [num_in_p-1:0] yumi_o // outgoing demultiplexed data , output [num_in_p-1:0][width_p-1:0] data_o , output [num_in_p-1:0] v_o , input [num_in_p-1:0] yumi_i ); // synopsys translate_off initial assert(lg_credit_decimation_p <= lg_remote_credits_lp) else begin $error("%m bad params; insufficient remote credits 2^%d to allow for decimation factor 2^%d" ,lg_remote_credits_lp,lg_credit_decimation_p); $finish; end initial assert(width_p >= num_in_p*lg_remote_credits_lp) else begin $error("%m bad params; channel width (%d) must be at least wide enough to route back credits (%d)" ,width_p ,num_in_p*lg_remote_credits_lp); $finish; end // synopsys translate_on wire [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_local_return_data_oi; wire credit_local_return_v_oi; wire [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_remote_return_data_oi; wire credit_remote_return_yumi_io; bsg_channel_tunnel_out #(.width_p (width_p) ,.num_in_p (num_in_p) ,.remote_credits_p (remote_credits_p) ,.lg_credit_decimation_p(lg_credit_decimation_p) ) bcto (.clk_i ,.reset_i ,.data_i ,.v_i ,.yumi_o ,.data_o (multi_data_o ) ,.v_o(multi_v_o) ,.yumi_i (multi_yumi_i ) ,.credit_local_return_data_i (credit_local_return_data_oi ) ,.credit_local_return_v_i (credit_local_return_v_oi ) ,.credit_remote_return_data_i(credit_remote_return_data_oi) ,.credit_remote_return_yumi_o(credit_remote_return_yumi_io) ); bsg_channel_tunnel_in #(.width_p (width_p ) ,.num_in_p (num_in_p ) ,.remote_credits_p (remote_credits_p) ,.use_pseudo_large_fifo_p(use_pseudo_large_fifo_p) ,.harden_small_fifo_p (harden_small_fifo_p) ,.lg_credit_decimation_p(lg_credit_decimation_p) ) bcti (.clk_i ,.reset_i ,.data_i (multi_data_i ) ,.v_i (multi_v_i) ,.yumi_o (multi_yumi_o ) ,.data_o ,.v_o ,.yumi_i ,.credit_local_return_data_o (credit_local_return_data_oi ) ,.credit_local_return_v_o (credit_local_return_v_oi ) ,.credit_remote_return_data_o(credit_remote_return_data_oi) ,.credit_remote_return_yumi_i(credit_remote_return_yumi_io) ); endmodule `BSG_ABSTRACT_MODULE(bsg_channel_tunnel)

///////////////////////////////////////////////////////////// // Created by: Synopsys DC Ultra(TM) in wire load mode // Version : L-2016.03-SP3 // Date : Sun Mar 12 16:58:40 2017 ///////////////////////////////////////////////////////////// module Approx_adder_W32 ( add_sub, in1, in2, res ); input [31:0] in1; input [31:0] in2; output [32:0] res; input add_sub; wire n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, n365, n366, n367, n369, n370; OAI2BB1X2TS U43 ( .A0N(n264), .A1N(n274), .B0(n19), .Y(res[32]) ); XOR2X2TS U44 ( .A(n204), .B(n203), .Y(res[26]) ); XOR2X2TS U45 ( .A(n239), .B(n238), .Y(res[27]) ); XOR2X2TS U46 ( .A(n244), .B(n243), .Y(res[25]) ); XOR2X2TS U47 ( .A(n248), .B(n247), .Y(res[28]) ); NAND2X1TS U48 ( .A(n237), .B(n89), .Y(n238) ); NAND2X1TS U49 ( .A(n242), .B(n241), .Y(n243) ); NAND2X1TS U50 ( .A(n246), .B(n257), .Y(n247) ); NAND2X1TS U51 ( .A(n228), .B(n256), .Y(n229) ); NAND2X1TS U52 ( .A(n272), .B(n271), .Y(n273) ); NAND2XLTS U53 ( .A(n83), .B(n294), .Y(n295) ); NAND2XLTS U54 ( .A(n86), .B(n291), .Y(n292) ); NAND2XLTS U55 ( .A(n311), .B(n310), .Y(n313) ); NAND2XLTS U56 ( .A(n87), .B(n275), .Y(n276) ); NAND2X1TS U57 ( .A(n285), .B(n284), .Y(n286) ); NAND2X1TS U58 ( .A(n306), .B(n305), .Y(n307) ); NAND2XLTS U59 ( .A(n326), .B(n325), .Y(n327) ); NAND2XLTS U60 ( .A(n301), .B(n300), .Y(n302) ); NAND2X4TS U61 ( .A(n274), .B(n22), .Y(n77) ); OA21XLTS U62 ( .A0(n267), .A1(n271), .B0(n268), .Y(n19) ); OAI21X1TS U63 ( .A0(n308), .A1(n304), .B0(n305), .Y(n303) ); INVX6TS U64 ( .A(n45), .Y(n287) ); NOR2X1TS U65 ( .A(n231), .B(n233), .Y(n236) ); INVX2TS U66 ( .A(n289), .Y(n296) ); CLKBUFX2TS U67 ( .A(n297), .Y(n298) ); OR2X2TS U68 ( .A(n270), .B(n266), .Y(n79) ); NOR2X2TS U69 ( .A(n262), .B(in1[30]), .Y(n265) ); NAND2X2TS U70 ( .A(n263), .B(in1[31]), .Y(n268) ); NAND2X1TS U71 ( .A(n227), .B(in1[29]), .Y(n256) ); CLKMX2X2TS U72 ( .A(in2[30]), .B(n253), .S0(n252), .Y(n262) ); NAND2X2TS U73 ( .A(n219), .B(in1[28]), .Y(n257) ); NAND2X2TS U74 ( .A(n180), .B(in1[22]), .Y(n284) ); NAND2X1TS U75 ( .A(n181), .B(in1[23]), .Y(n280) ); OR2X2TS U76 ( .A(n168), .B(in1[20]), .Y(n83) ); NOR2X2TS U77 ( .A(n299), .B(n304), .Y(n160) ); NAND2X2TS U78 ( .A(n193), .B(in1[24]), .Y(n275) ); CLKMX2X4TS U79 ( .A(in2[29]), .B(n226), .S0(n225), .Y(n227) ); INVX2TS U80 ( .A(n291), .Y(n170) ); OR2X4TS U81 ( .A(n214), .B(in1[27]), .Y(n89) ); NAND2X2TS U82 ( .A(n157), .B(in1[18]), .Y(n305) ); NAND2X2TS U83 ( .A(n158), .B(in1[19]), .Y(n300) ); NOR2X2TS U84 ( .A(n251), .B(in2[30]), .Y(n249) ); CLKMX2X3TS U85 ( .A(in2[23]), .B(n175), .S0(n225), .Y(n181) ); OR2X2TS U86 ( .A(n142), .B(in1[16]), .Y(n82) ); NAND2X2TS U87 ( .A(n169), .B(in1[21]), .Y(n291) ); NOR2X1TS U88 ( .A(n224), .B(n223), .Y(n211) ); MX2X2TS U89 ( .A(in2[25]), .B(n189), .S0(add_sub), .Y(n194) ); MXI2X2TS U90 ( .A(n167), .B(n166), .S0(n225), .Y(n168) ); XOR2X1TS U91 ( .A(n174), .B(n173), .Y(n175) ); OR2X1TS U92 ( .A(n210), .B(in2[27]), .Y(n223) ); INVX4TS U93 ( .A(add_sub), .Y(n353) ); NOR3X2TS U94 ( .A(n176), .B(in2[22]), .C(n184), .Y(n174) ); INVX2TS U95 ( .A(n187), .Y(n153) ); NAND2X1TS U96 ( .A(n206), .B(n205), .Y(n210) ); INVX4TS U97 ( .A(n63), .Y(n61) ); INVX2TS U98 ( .A(in2[20]), .Y(n167) ); NOR2X2TS U99 ( .A(n176), .B(in2[20]), .Y(n163) ); CLKINVX2TS U100 ( .A(n128), .Y(n67) ); INVX2TS U101 ( .A(in2[26]), .Y(n205) ); NAND2X2TS U102 ( .A(n131), .B(in1[14]), .Y(n321) ); NAND2X4TS U103 ( .A(n127), .B(in1[12]), .Y(n330) ); NAND2X2TS U104 ( .A(n18), .B(in1[13]), .Y(n325) ); OR2X2TS U105 ( .A(in2[21]), .B(in2[20]), .Y(n184) ); NOR2X4TS U106 ( .A(in2[17]), .B(in2[16]), .Y(n162) ); XNOR2X2TS U107 ( .A(n112), .B(in2[11]), .Y(n113) ); NOR2X1TS U108 ( .A(in2[19]), .B(in2[18]), .Y(n161) ); OR2X6TS U109 ( .A(n104), .B(in1[8]), .Y(n84) ); CLKINVX6TS U110 ( .A(n346), .Y(n105) ); BUFX4TS U111 ( .A(add_sub), .Y(n252) ); NOR2X2TS U112 ( .A(in2[13]), .B(in2[12]), .Y(n133) ); XNOR2X2TS U113 ( .A(n111), .B(in2[10]), .Y(n93) ); OR2X4TS U114 ( .A(n115), .B(n116), .Y(n111) ); NAND2X6TS U115 ( .A(n52), .B(n350), .Y(n101) ); INVX4TS U116 ( .A(n54), .Y(n97) ); BUFX8TS U117 ( .A(add_sub), .Y(n225) ); INVX8TS U118 ( .A(add_sub), .Y(n94) ); INVX12TS U119 ( .A(in2[3]), .Y(n90) ); CLKINVX6TS U120 ( .A(in2[8]), .Y(n103) ); AND2X2TS U121 ( .A(n118), .B(n117), .Y(n119) ); NAND2X2TS U122 ( .A(in2[6]), .B(add_sub), .Y(n96) ); NOR2X1TS U123 ( .A(n176), .B(n184), .Y(n177) ); AOI21X2TS U124 ( .A0(n89), .A1(n216), .B0(n215), .Y(n217) ); NOR2X4TS U125 ( .A(n219), .B(in1[28]), .Y(n254) ); NOR2XLTS U126 ( .A(n11), .B(in2[2]), .Y(n364) ); OR2X2TS U127 ( .A(n193), .B(in1[24]), .Y(n87) ); OAI21X2TS U128 ( .A0(n220), .A1(n254), .B0(n257), .Y(n221) ); OA21XLTS U129 ( .A0(n336), .A1(n333), .B0(n334), .Y(n20) ); INVX2TS U130 ( .A(n298), .Y(n308) ); NAND2X1TS U131 ( .A(n209), .B(n232), .Y(n203) ); AND2X4TS U132 ( .A(n261), .B(n255), .Y(n9) ); AND2X2TS U133 ( .A(n94), .B(n95), .Y(n10) ); NAND2X2TS U134 ( .A(n92), .B(n352), .Y(n11) ); INVX2TS U135 ( .A(n275), .Y(n240) ); NOR2X4TS U136 ( .A(n227), .B(in1[29]), .Y(n258) ); NOR2X4TS U137 ( .A(n16), .B(n27), .Y(n29) ); INVX2TS U138 ( .A(n260), .Y(n220) ); NOR2X6TS U139 ( .A(n218), .B(n231), .Y(n255) ); INVX3TS U140 ( .A(n267), .Y(n269) ); INVX4TS U141 ( .A(n182), .Y(n46) ); INVX2TS U142 ( .A(n232), .Y(n216) ); NOR2X4TS U143 ( .A(n202), .B(in1[26]), .Y(n233) ); INVX2TS U144 ( .A(n254), .Y(n246) ); NOR2X4TS U145 ( .A(n258), .B(n254), .Y(n261) ); XNOR2X2TS U146 ( .A(n200), .B(in2[26]), .Y(n201) ); XOR2X2TS U147 ( .A(n177), .B(in2[22]), .Y(n178) ); MXI2X4TS U148 ( .A(n192), .B(n191), .S0(n225), .Y(n193) ); NAND2BX2TS U149 ( .AN(n153), .B(n162), .Y(n154) ); NAND2X4TS U150 ( .A(n269), .B(n268), .Y(n270) ); NAND2X4TS U151 ( .A(n209), .B(n89), .Y(n218) ); INVX2TS U152 ( .A(n183), .Y(n42) ); NOR2X4TS U153 ( .A(n196), .B(n195), .Y(n234) ); INVX4TS U154 ( .A(n233), .Y(n209) ); INVX2TS U155 ( .A(n36), .Y(n69) ); OAI21X2TS U156 ( .A0(n258), .A1(n257), .B0(n256), .Y(n259) ); INVX2TS U157 ( .A(n299), .Y(n301) ); INVX4TS U158 ( .A(n190), .Y(n242) ); INVX2TS U159 ( .A(n237), .Y(n215) ); MXI2X4TS U160 ( .A(n205), .B(n201), .S0(n252), .Y(n202) ); NAND2X4TS U161 ( .A(n147), .B(in1[17]), .Y(n310) ); INVX4TS U162 ( .A(n294), .Y(n290) ); MXI2X4TS U163 ( .A(n179), .B(n178), .S0(n252), .Y(n180) ); MX2X4TS U164 ( .A(in2[28]), .B(n212), .S0(n225), .Y(n219) ); NAND2X2TS U165 ( .A(n199), .B(n206), .Y(n200) ); NAND2X2TS U166 ( .A(n142), .B(in1[16]), .Y(n314) ); NOR2X4TS U167 ( .A(n149), .B(n153), .Y(n151) ); OR2X4TS U168 ( .A(n110), .B(in1[10]), .Y(n85) ); INVX6TS U169 ( .A(in2[10]), .Y(n117) ); INVX2TS U170 ( .A(in2[17]), .Y(n144) ); XNOR2X1TS U171 ( .A(n303), .B(n302), .Y(res[19]) ); NAND2X6TS U172 ( .A(n43), .B(n41), .Y(n47) ); XOR2X1TS U173 ( .A(n308), .B(n307), .Y(res[18]) ); NAND2X4TS U174 ( .A(n182), .B(n9), .Y(n71) ); OR2X4TS U175 ( .A(n213), .B(n254), .Y(n222) ); NOR2X4TS U176 ( .A(n16), .B(n79), .Y(n72) ); AND2X2TS U177 ( .A(n63), .B(n25), .Y(n24) ); AND2X2TS U178 ( .A(n270), .B(n272), .Y(n22) ); NOR2X1TS U179 ( .A(n267), .B(n265), .Y(n264) ); XOR2X1TS U180 ( .A(n20), .B(n332), .Y(res[12]) ); INVX2TS U181 ( .A(n231), .Y(n198) ); AND2X2TS U182 ( .A(n281), .B(n280), .Y(n23) ); XOR2X1TS U183 ( .A(n337), .B(n336), .Y(res[11]) ); NOR2X6TS U184 ( .A(n263), .B(in1[31]), .Y(n267) ); CLKAND2X2TS U185 ( .A(n271), .B(n265), .Y(n76) ); XNOR2X2TS U186 ( .A(n249), .B(in2[31]), .Y(n250) ); NOR2X4TS U187 ( .A(n194), .B(in1[25]), .Y(n190) ); NAND2X4TS U188 ( .A(n340), .B(n85), .Y(n37) ); MX2X2TS U189 ( .A(in2[27]), .B(n208), .S0(add_sub), .Y(n214) ); XOR2X1TS U190 ( .A(n345), .B(n13), .Y(res[9]) ); XNOR2X1TS U191 ( .A(n81), .B(in2[29]), .Y(n226) ); NAND2X4TS U192 ( .A(n320), .B(n321), .Y(n63) ); INVX4TS U193 ( .A(n333), .Y(n335) ); NAND2X4TS U194 ( .A(n114), .B(in1[11]), .Y(n334) ); NAND2X4TS U195 ( .A(n104), .B(in1[8]), .Y(n346) ); OAI21XLTS U196 ( .A0(n358), .A1(n353), .B0(n357), .Y(res[6]) ); OAI21XLTS U197 ( .A0(n366), .A1(n353), .B0(n365), .Y(res[3]) ); NAND3X6TS U198 ( .A(n35), .B(n32), .C(n30), .Y(n350) ); OAI21XLTS U199 ( .A0(n361), .A1(n353), .B0(n360), .Y(res[5]) ); OAI21XLTS U200 ( .A0(n363), .A1(n353), .B0(n362), .Y(res[2]) ); OAI21XLTS U201 ( .A0(n370), .A1(n353), .B0(n369), .Y(res[4]) ); OAI21XLTS U202 ( .A0(n355), .A1(n353), .B0(n354), .Y(res[1]) ); OR2X2TS U203 ( .A(in2[18]), .B(n148), .Y(n149) ); CLKINVX6TS U204 ( .A(n11), .Y(n12) ); OR2X1TS U205 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) ); OAI21X4TS U206 ( .A0(n279), .A1(n284), .B0(n280), .Y(n182) ); NOR2X4TS U207 ( .A(n181), .B(in1[23]), .Y(n279) ); NAND3X4TS U208 ( .A(n78), .B(n77), .C(n74), .Y(res[31]) ); MX2X6TS U209 ( .A(in2[13]), .B(n124), .S0(n225), .Y(n18) ); NOR2X4TS U210 ( .A(n61), .B(n60), .Y(n62) ); NAND4X4TS U211 ( .A(n352), .B(n92), .C(n91), .D(n90), .Y(n48) ); XNOR2X2TS U212 ( .A(n154), .B(in2[18]), .Y(n155) ); INVX12TS U213 ( .A(in2[7]), .Y(n49) ); XNOR2X4TS U214 ( .A(n115), .B(in2[8]), .Y(n102) ); AOI21X1TS U215 ( .A0(n347), .A1(n84), .B0(n105), .Y(n13) ); XOR2X2TS U216 ( .A(n134), .B(in2[12]), .Y(n125) ); NOR2X4TS U217 ( .A(n147), .B(in1[17]), .Y(n309) ); MX2X4TS U218 ( .A(in2[17]), .B(n146), .S0(n225), .Y(n147) ); AND4X8TS U219 ( .A(n90), .B(n95), .C(n91), .D(n92), .Y(n14) ); INVX12TS U220 ( .A(in2[6]), .Y(n95) ); INVX12TS U221 ( .A(n277), .Y(n40) ); NAND2X8TS U222 ( .A(n187), .B(n186), .Y(n224) ); NOR4X2TS U223 ( .A(n185), .B(n184), .C(in2[23]), .D(in2[22]), .Y(n186) ); AND2X4TS U224 ( .A(n183), .B(n9), .Y(n80) ); XOR2X1TS U225 ( .A(n176), .B(n167), .Y(n166) ); NOR2X4TS U226 ( .A(n10), .B(n59), .Y(n58) ); NAND2BX4TS U227 ( .AN(in2[29]), .B(n81), .Y(n251) ); NOR3X4TS U228 ( .A(n224), .B(in2[28]), .C(n223), .Y(n81) ); NOR2X2TS U229 ( .A(n99), .B(in2[7]), .Y(n31) ); NAND2X4TS U230 ( .A(n90), .B(n91), .Y(n99) ); XOR2X1TS U231 ( .A(n293), .B(n292), .Y(res[21]) ); AOI21X4TS U232 ( .A0(n296), .A1(n83), .B0(n290), .Y(n293) ); NAND2X4TS U233 ( .A(n168), .B(in1[20]), .Y(n294) ); NAND2BX4TS U234 ( .AN(n185), .B(n187), .Y(n176) ); NOR2X4TS U235 ( .A(in2[25]), .B(in2[24]), .Y(n206) ); OAI21X4TS U236 ( .A0(n234), .A1(n218), .B0(n217), .Y(n260) ); XOR2X2TS U237 ( .A(n163), .B(in2[21]), .Y(n165) ); MXI2X4TS U238 ( .A(n165), .B(n164), .S0(n353), .Y(n169) ); NAND2X4TS U239 ( .A(n86), .B(n83), .Y(n172) ); MX2X4TS U240 ( .A(in2[19]), .B(n152), .S0(add_sub), .Y(n158) ); NAND2X8TS U241 ( .A(n134), .B(n133), .Y(n139) ); NAND2X8TS U242 ( .A(n103), .B(n108), .Y(n116) ); NOR2X4TS U243 ( .A(n224), .B(n210), .Y(n207) ); XNOR2X4TS U244 ( .A(n188), .B(in2[25]), .Y(n189) ); NOR2X4TS U245 ( .A(n224), .B(in2[24]), .Y(n188) ); MXI2X4TS U246 ( .A(n103), .B(n102), .S0(n225), .Y(n104) ); NOR2X6TS U247 ( .A(n70), .B(n334), .Y(n68) ); NAND2X4TS U248 ( .A(n134), .B(n126), .Y(n123) ); INVX2TS U249 ( .A(in2[16]), .Y(n141) ); INVX2TS U250 ( .A(in2[18]), .Y(n156) ); INVX2TS U251 ( .A(in1[7]), .Y(n53) ); NAND2X2TS U252 ( .A(n109), .B(in1[9]), .Y(n342) ); NAND2X4TS U253 ( .A(n110), .B(in1[10]), .Y(n338) ); NOR2X2TS U254 ( .A(n131), .B(in1[14]), .Y(n320) ); NOR2X4TS U255 ( .A(n180), .B(in1[22]), .Y(n283) ); INVX4TS U256 ( .A(n71), .Y(n27) ); INVX2TS U257 ( .A(n116), .Y(n120) ); INVX2TS U258 ( .A(in2[11]), .Y(n118) ); INVX2TS U259 ( .A(n96), .Y(n57) ); OAI21X2TS U260 ( .A0(n96), .A1(n17), .B0(in1[6]), .Y(n59) ); INVX6TS U261 ( .A(in2[9]), .Y(n108) ); INVX2TS U262 ( .A(in2[12]), .Y(n126) ); INVX12TS U263 ( .A(in2[5]), .Y(n51) ); INVX8TS U264 ( .A(in2[4]), .Y(n50) ); CLKAND2X2TS U265 ( .A(n49), .B(add_sub), .Y(n15) ); NAND2X1TS U266 ( .A(n34), .B(in2[7]), .Y(n33) ); INVX2TS U267 ( .A(n99), .Y(n34) ); CLKINVX6TS U268 ( .A(n68), .Y(n28) ); INVX2TS U269 ( .A(n88), .Y(n60) ); XOR2X1TS U270 ( .A(n151), .B(n150), .Y(n152) ); INVX2TS U271 ( .A(in2[19]), .Y(n150) ); INVX2TS U272 ( .A(in2[21]), .Y(n164) ); INVX2TS U273 ( .A(n224), .Y(n199) ); INVX2TS U274 ( .A(n241), .Y(n195) ); NOR2X2TS U275 ( .A(n275), .B(n190), .Y(n196) ); INVX2TS U276 ( .A(n171), .Y(n44) ); INVX2TS U277 ( .A(n255), .Y(n213) ); NOR2X4TS U278 ( .A(n279), .B(n283), .Y(n183) ); INVX2TS U279 ( .A(n314), .Y(n143) ); NOR2X4TS U280 ( .A(n158), .B(in1[19]), .Y(n299) ); OR2X4TS U281 ( .A(n169), .B(in1[21]), .Y(n86) ); CLKBUFX2TS U282 ( .A(n288), .Y(n289) ); NAND2X2TS U283 ( .A(n194), .B(in1[25]), .Y(n241) ); NAND2X4TS U284 ( .A(n202), .B(in1[26]), .Y(n232) ); INVX2TS U285 ( .A(n234), .Y(n197) ); NAND2X2TS U286 ( .A(n214), .B(in1[27]), .Y(n237) ); NAND2X2TS U287 ( .A(n242), .B(n87), .Y(n231) ); OAI21X1TS U288 ( .A0(n234), .A1(n233), .B0(n232), .Y(n235) ); NAND2X1TS U289 ( .A(n270), .B(n271), .Y(n75) ); NOR2XLTS U290 ( .A(n48), .B(in2[4]), .Y(n359) ); NAND2X1TS U291 ( .A(n349), .B(n52), .Y(n351) ); NAND2X1TS U292 ( .A(n84), .B(n346), .Y(n348) ); NAND2X1TS U293 ( .A(n343), .B(n342), .Y(n345) ); INVX2TS U294 ( .A(n341), .Y(n343) ); NAND2X1TS U295 ( .A(n85), .B(n338), .Y(n339) ); NAND2X1TS U296 ( .A(n335), .B(n334), .Y(n337) ); NAND2X1TS U297 ( .A(n331), .B(n330), .Y(n332) ); INVX2TS U298 ( .A(n329), .Y(n331) ); OAI21XLTS U299 ( .A0(n20), .A1(n329), .B0(n330), .Y(n328) ); INVX2TS U300 ( .A(n324), .Y(n326) ); NAND2X1TS U301 ( .A(n322), .B(n321), .Y(n323) ); INVX2TS U302 ( .A(n320), .Y(n322) ); NAND2X1TS U303 ( .A(n88), .B(n317), .Y(n318) ); CLKBUFX2TS U304 ( .A(n64), .Y(n25) ); NAND2X1TS U305 ( .A(n82), .B(n314), .Y(n315) ); XOR2XLTS U306 ( .A(n313), .B(n312), .Y(res[17]) ); INVX2TS U307 ( .A(n309), .Y(n311) ); XNOR2X1TS U308 ( .A(n296), .B(n295), .Y(res[20]) ); XOR2X1TS U309 ( .A(n287), .B(n286), .Y(res[22]) ); INVX2TS U310 ( .A(n283), .Y(n285) ); XOR2X2TS U311 ( .A(n282), .B(n23), .Y(res[23]) ); INVX2TS U312 ( .A(n279), .Y(n281) ); INVX2TS U313 ( .A(n258), .Y(n228) ); OAI21X1TS U314 ( .A0(n270), .A1(n76), .B0(n75), .Y(n74) ); NAND3X2TS U315 ( .A(n73), .B(n72), .C(n71), .Y(n78) ); NAND2X4TS U316 ( .A(n100), .B(n367), .Y(n55) ); NAND3X6TS U317 ( .A(n335), .B(n38), .C(n129), .Y(n36) ); CLKINVX12TS U318 ( .A(n26), .Y(n134) ); XNOR2X2TS U319 ( .A(n139), .B(in2[14]), .Y(n130) ); BUFX8TS U320 ( .A(n278), .Y(n45) ); NOR2X4TS U321 ( .A(in2[8]), .B(n115), .Y(n106) ); INVX8TS U322 ( .A(n115), .Y(n122) ); XNOR2X1TS U323 ( .A(n277), .B(n276), .Y(res[24]) ); NOR2X4TS U324 ( .A(n109), .B(in1[9]), .Y(n341) ); INVX16TS U325 ( .A(in2[0]), .Y(n352) ); NAND2X4TS U326 ( .A(n262), .B(in1[30]), .Y(n271) ); NOR2X4TS U327 ( .A(n157), .B(in1[18]), .Y(n304) ); AO21X4TS U328 ( .A0(n260), .A1(n261), .B0(n259), .Y(n16) ); AND2X8TS U329 ( .A(n50), .B(n51), .Y(n17) ); INVX2TS U330 ( .A(n271), .Y(n266) ); AND4X8TS U331 ( .A(n50), .B(n352), .C(n51), .D(n49), .Y(n21) ); INVX2TS U332 ( .A(n265), .Y(n272) ); INVX2TS U333 ( .A(n38), .Y(n336) ); CLKINVX6TS U334 ( .A(n48), .Y(n367) ); NOR2X4TS U335 ( .A(n114), .B(in1[11]), .Y(n333) ); XOR2X2TS U336 ( .A(n187), .B(in2[16]), .Y(n140) ); NAND2X8TS U337 ( .A(n14), .B(n21), .Y(n115) ); INVX8TS U338 ( .A(n129), .Y(n70) ); NAND2X8TS U339 ( .A(n122), .B(n121), .Y(n26) ); NAND3X8TS U340 ( .A(n55), .B(n58), .C(n56), .Y(n54) ); NOR2X8TS U341 ( .A(n39), .B(n221), .Y(n230) ); AND2X8TS U342 ( .A(n36), .B(n28), .Y(n65) ); AOI21X4TS U343 ( .A0(n347), .A1(n84), .B0(n105), .Y(n344) ); NAND2X8TS U344 ( .A(n101), .B(n349), .Y(n347) ); NAND2X8TS U345 ( .A(n73), .B(n29), .Y(n274) ); NAND2X8TS U346 ( .A(n45), .B(n80), .Y(n73) ); OAI2BB1X4TS U347 ( .A0N(n31), .A1N(n12), .B0(n98), .Y(n30) ); NAND3BX4TS U348 ( .AN(n33), .B(n12), .C(n100), .Y(n32) ); NAND2BX4TS U349 ( .AN(n100), .B(n15), .Y(n35) ); NAND2X8TS U350 ( .A(n64), .B(n62), .Y(n138) ); NAND2X8TS U351 ( .A(n65), .B(n66), .Y(n64) ); NAND2X8TS U352 ( .A(n37), .B(n338), .Y(n38) ); OAI21X4TS U353 ( .A0(n344), .A1(n341), .B0(n342), .Y(n340) ); NOR2X8TS U354 ( .A(n40), .B(n222), .Y(n39) ); AOI21X4TS U355 ( .A0(n171), .A1(n172), .B0(n42), .Y(n41) ); NAND2BX4TS U356 ( .AN(n44), .B(n288), .Y(n43) ); OAI21X2TS U357 ( .A0(n288), .A1(n172), .B0(n171), .Y(n278) ); NAND2X8TS U358 ( .A(n47), .B(n46), .Y(n277) ); XOR2X4TS U359 ( .A(n123), .B(in2[13]), .Y(n124) ); MXI2X8TS U360 ( .A(n126), .B(n125), .S0(n225), .Y(n127) ); MXI2X4TS U361 ( .A(n132), .B(n130), .S0(n252), .Y(n131) ); NAND2X8TS U362 ( .A(n54), .B(n53), .Y(n52) ); NAND2BX4TS U363 ( .AN(n367), .B(n57), .Y(n56) ); NOR3XLTS U364 ( .A(n68), .B(n69), .C(n128), .Y(n319) ); AND2X8TS U365 ( .A(n67), .B(n321), .Y(n66) ); INVX16TS U366 ( .A(in2[1]), .Y(n92) ); INVX16TS U367 ( .A(in2[2]), .Y(n91) ); XNOR2X1TS U368 ( .A(n315), .B(n316), .Y(res[16]) ); XNOR2X1TS U369 ( .A(n348), .B(n347), .Y(res[8]) ); XNOR2X1TS U370 ( .A(n340), .B(n339), .Y(res[10]) ); XNOR2X2TS U371 ( .A(n274), .B(n273), .Y(res[30]) ); OR2X8TS U372 ( .A(n137), .B(in1[15]), .Y(n88) ); MX2X4TS U373 ( .A(in2[11]), .B(n113), .S0(n252), .Y(n114) ); MXI2X4TS U374 ( .A(n117), .B(n93), .S0(n252), .Y(n110) ); AND2X4TS U375 ( .A(n17), .B(n95), .Y(n100) ); NAND2X8TS U376 ( .A(n97), .B(in1[7]), .Y(n349) ); XOR2X1TS U377 ( .A(add_sub), .B(in2[7]), .Y(n98) ); XNOR2X4TS U378 ( .A(n106), .B(n108), .Y(n107) ); MXI2X4TS U379 ( .A(n108), .B(n107), .S0(n225), .Y(n109) ); NOR2X4TS U380 ( .A(n111), .B(in2[10]), .Y(n112) ); AND2X8TS U381 ( .A(n120), .B(n119), .Y(n121) ); NOR2X8TS U382 ( .A(n18), .B(in1[13]), .Y(n324) ); NOR2X8TS U383 ( .A(n127), .B(in1[12]), .Y(n329) ); NOR2X8TS U384 ( .A(n324), .B(n329), .Y(n129) ); OAI21X4TS U385 ( .A0(n324), .A1(n330), .B0(n325), .Y(n128) ); INVX2TS U386 ( .A(in2[14]), .Y(n132) ); NAND3X1TS U387 ( .A(n134), .B(n133), .C(n132), .Y(n135) ); XOR2X1TS U388 ( .A(n135), .B(in2[15]), .Y(n136) ); MX2X4TS U389 ( .A(in2[15]), .B(n136), .S0(n252), .Y(n137) ); NAND2X6TS U390 ( .A(n137), .B(in1[15]), .Y(n317) ); NAND2X8TS U391 ( .A(n138), .B(n317), .Y(n316) ); NOR3X8TS U392 ( .A(n139), .B(in2[15]), .C(in2[14]), .Y(n187) ); MXI2X2TS U393 ( .A(n141), .B(n140), .S0(n252), .Y(n142) ); AOI21X4TS U394 ( .A0(n316), .A1(n82), .B0(n143), .Y(n312) ); NOR2X2TS U395 ( .A(n153), .B(in2[16]), .Y(n145) ); XOR2X1TS U396 ( .A(n145), .B(n144), .Y(n146) ); OAI21X4TS U397 ( .A0(n312), .A1(n309), .B0(n310), .Y(n297) ); INVX2TS U398 ( .A(n162), .Y(n148) ); MXI2X4TS U399 ( .A(n156), .B(n155), .S0(n252), .Y(n157) ); OAI21X4TS U400 ( .A0(n299), .A1(n305), .B0(n300), .Y(n159) ); AOI21X4TS U401 ( .A0(n297), .A1(n160), .B0(n159), .Y(n288) ); NAND2X2TS U402 ( .A(n162), .B(n161), .Y(n185) ); AOI21X4TS U403 ( .A0(n86), .A1(n290), .B0(n170), .Y(n171) ); INVX2TS U404 ( .A(in2[23]), .Y(n173) ); INVX2TS U405 ( .A(in2[22]), .Y(n179) ); INVX2TS U406 ( .A(in2[24]), .Y(n192) ); XNOR2X4TS U407 ( .A(n224), .B(in2[24]), .Y(n191) ); AOI21X4TS U408 ( .A0(n277), .A1(n198), .B0(n197), .Y(n204) ); XNOR2X1TS U409 ( .A(n207), .B(in2[27]), .Y(n208) ); XNOR2X1TS U410 ( .A(n211), .B(in2[28]), .Y(n212) ); XOR2X4TS U411 ( .A(n230), .B(n229), .Y(res[29]) ); AOI21X4TS U412 ( .A0(n277), .A1(n236), .B0(n235), .Y(n239) ); AOI21X4TS U413 ( .A0(n277), .A1(n87), .B0(n240), .Y(n244) ); AOI21X4TS U414 ( .A0(n277), .A1(n255), .B0(n260), .Y(n248) ); MX2X4TS U415 ( .A(in2[31]), .B(n250), .S0(n252), .Y(n263) ); XOR2X1TS U416 ( .A(n251), .B(in2[30]), .Y(n253) ); OAI21X4TS U417 ( .A0(n287), .A1(n283), .B0(n284), .Y(n282) ); INVX2TS U418 ( .A(n304), .Y(n306) ); XNOR2X1TS U419 ( .A(n24), .B(n318), .Y(res[15]) ); XOR2XLTS U420 ( .A(n319), .B(n323), .Y(res[14]) ); XNOR2X1TS U421 ( .A(n328), .B(n327), .Y(res[13]) ); XNOR2X1TS U422 ( .A(n351), .B(n350), .Y(res[7]) ); XOR2X1TS U423 ( .A(n352), .B(in2[1]), .Y(n355) ); AOI21X1TS U424 ( .A0(n94), .A1(in2[1]), .B0(in1[1]), .Y(n354) ); NAND2X1TS U425 ( .A(n367), .B(n17), .Y(n356) ); XNOR2X1TS U426 ( .A(n356), .B(in2[6]), .Y(n358) ); AOI21X1TS U427 ( .A0(n94), .A1(in2[6]), .B0(in1[6]), .Y(n357) ); XOR2X1TS U428 ( .A(n359), .B(in2[5]), .Y(n361) ); AOI21X1TS U429 ( .A0(n94), .A1(in2[5]), .B0(in1[5]), .Y(n360) ); XNOR2X1TS U430 ( .A(n11), .B(in2[2]), .Y(n363) ); AOI21X1TS U431 ( .A0(n353), .A1(in2[2]), .B0(in1[2]), .Y(n362) ); XNOR2X1TS U432 ( .A(n364), .B(n90), .Y(n366) ); AOI21X1TS U433 ( .A0(n94), .A1(in2[3]), .B0(in1[3]), .Y(n365) ); XOR2X1TS U434 ( .A(n367), .B(in2[4]), .Y(n370) ); AOI21X1TS U435 ( .A0(n94), .A1(in2[4]), .B0(in1[4]), .Y(n369) ); initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_LOALPL7_syn.sdf"); endmodule

// Copyright 2008, 2009 by Jakub Bednarski // // This file is part of Minimig // // Minimig is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 3 of the License, or // (at your option) any later version. // // Minimig is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see <http://www.gnu.org/licenses/>. // // // // -- JB -- // // 2008-10-06 - initial version // 2008-10-08 - interrupt controller implemented, kickstart boots // 2008-10-09 - working identify device command implemented (hdtoolbox detects our drive) // - read command reads data from hardfile (fixed size and name, only one sector read size supported, workbench sees hardfile partition) // 2008-10-10 - multiple sector transfer supported: works ok, sequential transfers with direct spi read and 28MHz CPU from 400 to 520 KB/s // - arm firmare seekfile function very slow: seeking from start to 20MB takes 144 ms (some software improvements required) // 2008-10-30 - write support added // 2008-12-31 - added hdd enable // 2009-05-24 - clean-up & renaming // 2009-08-11 - hdd_ena enables Master & Slave drives // 2009-11-18 - changed sector buffer size // 2010-04-13 - changed sector buffer size // 2010-08-10 - improved BSY signal handling module gayle ( input clk, input clk7_en, input reset, input [23:1] address_in, input [15:0] data_in, output [15:0] data_out, input rd, input hwr, input lwr, input sel_ide, // $DAxxxx input sel_gayle, // $DExxxx output irq, output nrdy, // fifo is not ready for reading input [1:0] hdd_ena, // enables Master & Slave drives output hdd_cmd_req, output hdd_dat_req, input [2:0] hdd_addr, input [15:0] hdd_data_out, output [15:0] hdd_data_in, input hdd_wr, input hdd_status_wr, input hdd_data_wr, input hdd_data_rd, output hd_fwr, output hd_frd ); localparam VCC = 1'b1; localparam GND = 1'b0; //0xda2000 Data //0xda2004 Error | Feature //0xda2008 SectorCount //0xda200c SectorNumber //0xda2010 CylinderLow //0xda2014 CylinderHigh //0xda2018 Device/Head //0xda201c Status | Command //0xda3018 Control /* memory map: $DA0000 - $DA0FFFF : CS1 16-bit speed $DA1000 - $DA1FFFF : CS2 16-bit speed $DA2000 - $DA2FFFF : CS1 8-bit speed $DA3000 - $DA3FFFF : CS2 8-bit speed $DA4000 - $DA7FFFF : reserved $DA8000 - $DA8FFFF : IDE INTREQ state status register (not implemented as scsi.device doesn't use it) $DA9000 - $DA9FFFF : IDE INTREQ change status register (writing zeros resets selected bits, writing ones doesn't change anything) $DAA000 - $DAAFFFF : IDE INTENA register (r/w, only MSB matters) command class: PI (PIO In) PO (PIO Out) ND (No Data) Status: #6 - DRDY - Drive Ready #7 - BSY - Busy #3 - DRQ - Data Request #0 - ERR - Error INTRQ - Interrupt Request */ // address decoding signals wire sel_gayleid; // Gayle ID register select wire sel_tfr; // HDD task file registers select wire sel_fifo; // HDD data port select (FIFO buffer) wire sel_status; // HDD status register select wire sel_command; // HDD command register select wire sel_cs; // Gayle IDE CS wire sel_intreq; // Gayle interrupt request status register select wire sel_intena; // Gayle interrupt enable register select wire sel_cfg; // Gayle CFG // internal registers reg intena; // Gayle IDE interrupt enable bit reg intreq; // Gayle IDE interrupt request bit reg busy; // busy status (command processing state) reg pio_in; // pio in command type is being processed reg pio_out; // pio out command type is being processed reg error; // error status (command processing failed) reg [3:0] cfg; reg [1:0] cs; reg [5:0] cs_mask; reg dev; // drive select (Master/Slave) wire bsy; // busy wire drdy; // drive ready wire drq; // data request wire err; // error wire [7:0] status; // HDD status // FIFO control wire fifo_reset; wire [15:0] fifo_data_in; wire [15:0] fifo_data_out; wire fifo_rd; wire fifo_wr; wire fifo_full; wire fifo_empty; wire fifo_last; // last word of a sector is being read // gayle id reg reg [1:0] gayleid_cnt; // sequence counter wire gayleid; // output data (one bit wide) // hd leds assign hd_fwr = fifo_wr; assign hd_frd = fifo_rd; // HDD status register assign status = {bsy,drdy,2'b00,drq,2'b00,err}; // status debug reg [7:0] status_dbg /* synthesis syn_noprune */; always @ (posedge clk) status_dbg <= #1 status; // HDD status register bits assign bsy = busy & ~drq; assign drdy = ~(bsy|drq); assign err = error; // address decoding assign sel_gayleid = sel_gayle && address_in[15:12]==4'b0001 ? VCC : GND; // GAYLEID, $DE1xxx assign sel_tfr = sel_ide && address_in[15:14]==2'b00 && !address_in[12] ? VCC : GND; // $DA0xxx, $DA2xxx assign sel_status = rd && sel_tfr && address_in[4:2]==3'b111 ? VCC : GND; assign sel_command = hwr && sel_tfr && address_in[4:2]==3'b111 ? VCC : GND; assign sel_fifo = sel_tfr && address_in[4:2]==3'b000 ? VCC : GND; assign sel_cs = sel_ide && address_in[15:12]==4'b1000 ? VCC : GND; // GAYLE_CS_1200, $DA8xxx assign sel_intreq = sel_ide && address_in[15:12]==4'b1001 ? VCC : GND; // GAYLE_IRQ_1200, $DA9xxx assign sel_intena = sel_ide && address_in[15:12]==4'b1010 ? VCC : GND; // GAYLE_INT_1200, $DAAxxx assign sel_cfg = sel_ide && address_in[15:12]==4'b1011 ? VCC : GND; // GAYLE_CFG_1200, $DABxxx //===============================================================================================// // gayle cs always @ (posedge clk) begin if (clk7_en) begin if (reset) begin cs_mask <= #1 6'd0; cs <= #1 2'd0; end else if (hwr && sel_cs) begin cs_mask <= #1 data_in[15:10]; cs <= #1 data_in[9:8]; end end end // gayle cfg always @ (posedge clk) begin if (clk7_en) begin if (reset) cfg <= #1 4'd0; if (hwr && sel_cfg) begin cfg <= #1 data_in[15:12]; end end end // task file registers reg [7:0] tfr [7:0]; wire [2:0] tfr_sel; wire [7:0] tfr_in; wire [7:0] tfr_out; wire tfr_we; reg [7:0] sector_count; // sector counter wire sector_count_dec; // decrease sector counter always @(posedge clk) if (clk7_en) begin if (hwr && sel_tfr && address_in[4:2] == 3'b010) // sector count register loaded by the host sector_count <= data_in[15:8]; else if (sector_count_dec) sector_count <= sector_count - 8'd1; end assign sector_count_dec = pio_in & fifo_last & sel_fifo & rd; // task file register control assign tfr_we = busy ? hdd_wr : sel_tfr & hwr; assign tfr_sel = busy ? hdd_addr : address_in[4:2]; assign tfr_in = busy ? hdd_data_out[7:0] : data_in[15:8]; // input multiplexer for SPI host assign hdd_data_in = tfr_sel==0 ? fifo_data_out : {8'h00,tfr_out}; // task file registers always @(posedge clk) if (clk7_en) begin if (tfr_we) tfr[tfr_sel] <= tfr_in; end assign tfr_out = tfr[tfr_sel]; // master/slave drive select always @(posedge clk) if (clk7_en) begin if (reset) dev <= 0; else if (sel_tfr && address_in[4:2]==6 && hwr) dev <= data_in[12]; end // IDE interrupt enable register always @(posedge clk) if (clk7_en) begin if (reset) intena <= GND; else if (sel_intena && hwr) intena <= data_in[15]; end // gayle id register: reads 1->1->0->1 on MSB always @(posedge clk) if (clk7_en) begin if (sel_gayleid) if (hwr) // a write resets sequence counter gayleid_cnt <= 2'd0; else if (rd) gayleid_cnt <= gayleid_cnt + 2'd1; end assign gayleid = ~gayleid_cnt[1] | gayleid_cnt[0]; // Gayle ID output data // status register (write only from SPI host) // 7 - busy status (write zero to finish command processing: allow host access to task file registers) // 6 // 5 // 4 - intreq // 3 - drq enable for pio in (PI) command type // 2 - drq enable for pio out (PO) command type // 1 // 0 - error flag (remember about setting error task file register) // command busy status always @(posedge clk) if (clk7_en) begin if (reset) busy <= GND; else if (hdd_status_wr && hdd_data_out[7] || (sector_count_dec && sector_count == 8'h01)) // reset by SPI host (by clearing BSY status bit) busy <= GND; else if (sel_command) // set when the CPU writes command register busy <= VCC; end // IDE interrupt request register always @(posedge clk) if (clk7_en) begin if (reset) intreq <= GND; else if (busy && hdd_status_wr && hdd_data_out[4] && intena) // set by SPI host intreq <= VCC; else if (sel_intreq && hwr && !data_in[15]) // cleared by the CPU intreq <= GND; end assign irq = (~pio_in | drq) & intreq; // interrupt request line (INT2) // pio in command type always @(posedge clk) if (clk7_en) begin if (reset) pio_in <= GND; else if (drdy) // reset when processing of the current command ends pio_in <= GND; else if (busy && hdd_status_wr && hdd_data_out[3]) // set by SPI host pio_in <= VCC; end // pio out command type always @(posedge clk) if (clk7_en) begin if (reset) pio_out <= GND; else if (busy && hdd_status_wr && hdd_data_out[7]) // reset by SPI host when command processing completes pio_out <= GND; else if (busy && hdd_status_wr && hdd_data_out[2]) // set by SPI host pio_out <= VCC; end assign drq = (fifo_full & pio_in) | (~fifo_full & pio_out); // HDD data request status bit // error status always @(posedge clk) if (clk7_en) begin if (reset) error <= GND; else if (sel_command) // reset by the CPU when command register is written error <= GND; else if (busy && hdd_status_wr && hdd_data_out[0]) // set by SPI host error <= VCC; end assign hdd_cmd_req = bsy; // bsy is set when command register is written, tells the SPI host about new command assign hdd_dat_req = (fifo_full & pio_out); // the FIFO is full so SPI host may read it // FIFO in/out multiplexer assign fifo_reset = reset | sel_command; assign fifo_data_in = pio_in ? hdd_data_out : data_in; assign fifo_rd = pio_out ? hdd_data_rd : sel_fifo & rd; assign fifo_wr = pio_in ? hdd_data_wr : sel_fifo & hwr & lwr; //sector data buffer (FIFO) gayle_fifo SECBUF1 ( .clk(clk), .clk7_en(clk7_en), .reset(fifo_reset), .data_in(fifo_data_in), .data_out(fifo_data_out), .rd(fifo_rd), .wr(fifo_wr), .full(fifo_full), .empty(fifo_empty), .last(fifo_last) ); // fifo is not ready for reading assign nrdy = pio_in & sel_fifo & fifo_empty; //data_out multiplexer assign data_out = (sel_fifo && rd ? fifo_data_out : sel_status ? (!dev && hdd_ena[0]) || (dev && hdd_ena[1]) ? {status,8'h00} : 16'h00_00 : sel_tfr && rd ? {tfr_out,8'h00} : 16'h00_00) | (sel_cs && rd ? {(cs_mask[5] || intreq), cs_mask[4:0], cs, 8'h0} : 16'h00_00) | (sel_intreq && rd ? {intreq, 15'b000_0000_0000_0000} : 16'h00_00) | (sel_intena && rd ? {intena, 15'b000_0000_0000_0000} : 16'h00_00) | (sel_gayleid && rd ? {gayleid,15'b000_0000_0000_0000} : 16'h00_00) | (sel_cfg && rd ? {cfg, 12'b0000_0000_0000} : 16'h00_00); //===============================================================================================// endmodule

module qsys_serial_device#( parameter address_size=8)( // Qsys bus interface input rsi_MRST_reset, input csi_MCLK_clk, input [31:0] avs_ctrl_writedata, output reg[31:0] avs_ctrl_readdata, input [3:0] avs_ctrl_byteenable, input [7:0] avs_ctrl_address, input avs_ctrl_write, input avs_ctrl_read, input avs_ctrl_chipselect, output reg avs_ctrl_waitrequest, output reg avs_ctrl_readdatavalid, // Qsys serial interface output reg sdo, input sdi, output clk, output reg sle, input srdy ); reg [64:0] data_buffer; assign clk = csi_MCLK_clk; parameter initial_state = 8'd0; parameter bus_data_wait = initial_state+8'd1; parameter bus_data_ready = bus_data_wait+8'd1; parameter bus_transmit_start = bus_data_ready + 8'd1; parameter bus_transmit_ready = bus_transmit_start + 8'd64; parameter bus_transmit_finish = bus_transmit_ready + 8'd1; parameter bus_ready_wait = bus_transmit_finish + 8'd1; parameter bus_transmit_back = bus_ready_wait + 8'd1; parameter bus_data_read = bus_transmit_back + 8'd1; parameter bus_data_read_finish = bus_data_read + 8'd2; reg [7:0] state; reg [7:0] nextstate; always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset) begin if (rsi_MRST_reset) state <= initial_state; else state <= nextstate; end always@(state or srdy or avs_ctrl_write or avs_ctrl_read) begin case(state) initial_state: nextstate <= bus_data_wait; bus_data_wait: begin if(avs_ctrl_write == 1'b1 || avs_ctrl_read == 1'b1) begin if(avs_ctrl_chipselect == 1'b1) nextstate <= bus_data_ready; else nextstate <= bus_data_wait; end else nextstate <= bus_data_wait; end bus_data_ready: nextstate <= bus_transmit_start; bus_transmit_start: nextstate <= state + 1; bus_transmit_ready: nextstate <= bus_transmit_finish; bus_transmit_finish: nextstate <= bus_ready_wait; bus_ready_wait: begin if(srdy == 1'b1) nextstate <= bus_transmit_back; else nextstate <= bus_ready_wait; end bus_transmit_back: begin if(srdy == 1'b0) nextstate <= bus_data_read; else nextstate <= bus_transmit_back; end bus_data_read: nextstate <= state +1; bus_data_read_finish: nextstate <= bus_data_wait; default: nextstate <= state + 1; endcase end always@(posedge csi_MCLK_clk) begin if (state == bus_data_wait) begin data_buffer[63:32] <= avs_ctrl_address; if (avs_ctrl_write == 1'b1) begin data_buffer[64] <= 1'b1; //write data_buffer[31:0] <= avs_ctrl_writedata; end else if (avs_ctrl_read == 1'b1) begin data_buffer[64] <= 1'b0; //read data_buffer[31:0] <= 32'd0; end end else if (state >= bus_transmit_start && state <= bus_transmit_ready) begin integer i; for(i=0;i<64;i=i+1) data_buffer[i+1] <= data_buffer[i]; sdo <= data_buffer[64]; end else if (state == bus_transmit_back) begin integer i; for(i=0;i<64;i=i+1) data_buffer[i+1] <= data_buffer[i]; data_buffer[0]<= sdi; end end always@(posedge csi_MCLK_clk) begin if (state >= bus_data_ready && state < bus_transmit_ready) sle <= 1; else sle <= 0; end always@(state) begin if (state >= bus_data_ready && state <= bus_data_read) avs_ctrl_waitrequest = 1'b1; else avs_ctrl_waitrequest = 1'b0; end always@(posedge csi_MCLK_clk) begin if (state == bus_data_read ) avs_ctrl_readdatavalid <= 1'b1; else avs_ctrl_readdatavalid <= 1'b0; end always@(posedge csi_MCLK_clk) begin if (state == bus_data_read) begin avs_ctrl_readdata <= data_buffer[31:0]; end end endmodule

// DESCRIPTION: Verilator: Test symbol table scope map and general public // signal reflection // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. module t ( input wire CLK ); foo #(.WIDTH (1)) foo1 (.*); foo #(.WIDTH (7)) foo7 (.*); foo #(.WIDTH (8)) foo8 (.*); foo #(.WIDTH (32)) foo32 (.*); foo #(.WIDTH (33)) foo33 (.*); foo #(.WIDTH (40)) foo40 (.*); foo #(.WIDTH (41)) foo41 (.*); foo #(.WIDTH (64)) foo64 (.*); foo #(.WIDTH (65)) foo65 (.*); foo #(.WIDTH (96)) foo96 (.*); foo #(.WIDTH (97)) foo97 (.*); foo #(.WIDTH (128)) foo128 (.*); foo #(.WIDTH (256)) foo256 (.*); foo #(.WIDTH (1024)) foo1024 (.*); bar #(.WIDTH (1024)) bar1024 (.*); endmodule module foo #( parameter WIDTH = 32 ) ( input CLK ); logic [ ( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0 ] initial_value; logic [ WIDTH - 1 : 0 ] value_q /* verilator public */; integer i; initial begin initial_value = '1; for (i = 0; i < WIDTH / 8; i++) initial_value[ i * 8 +: 8 ] = i[ 7 : 0 ]; value_q = initial_value[ WIDTH - 1 : 0 ]; end always @(posedge CLK) value_q <= ~value_q; endmodule module bar #( parameter WIDTH = 32 ) ( input CLK ); foo #(.WIDTH (WIDTH)) foo (.*); endmodule

`timescale 1ns / 1ps /******************************************************************************* * Engineer: Robin zhang * Create Date: 2016.09.10 * Module Name: spi_slave *******************************************************************************/ module spi_slave_0_base( clk,sck,mosi,miso,ssel,rst_n,recived_status ); input clk; input rst_n; input sck,mosi,ssel; output miso; output recived_status; reg recived_status; reg[2:0] sckr; reg[2:0] sselr; reg[1:0] mosir; reg[2:0] bitcnt; reg[7:0] bytecnt; reg byte_received; // high when a byte has been received reg [7:0] byte_data_received; reg[7:0] received_memory; reg [7:0] byte_data_sent; reg [7:0] cnt; wire ssel_active; wire sck_risingedge; wire sck_fallingedge; wire ssel_startmessage; wire ssel_endmessage; wire mosi_data; /******************************************************************************* *detect the rising edge and falling edge of sck *******************************************************************************/ always @(posedge clk or negedge rst_n)begin if(!rst_n) sckr <= 3'h0; else sckr <= {sckr[1:0],sck}; end assign sck_risingedge = (sckr[2:1] == 2'b01) ? 1'b1 : 1'b0; assign sck_fallingedge = (sckr[2:1] == 2'b10) ? 1'b1 : 1'b0; /******************************************************************************* *detect starts at falling edge and stops at rising edge of ssel *******************************************************************************/ always @(posedge clk or negedge rst_n)begin if(!rst_n) sselr <= 3'h0; else sselr <= {sselr[1:0],ssel}; end assign ssel_active = (~sselr[1]) ? 1'b1 : 1'b0; // SSEL is active low assign ssel_startmessage = (sselr[2:1]==2'b10) ? 1'b1 : 1'b0; // message starts at falling edge assign ssel_endmessage = (sselr[2:1]==2'b01) ? 1'b1 : 1'b0; // message stops at rising edge /******************************************************************************* *read from mosi *******************************************************************************/ always @(posedge clk or negedge rst_n)begin if(!rst_n) mosir <= 2'h0; else mosir <={mosir[0],mosi}; end assign mosi_data = mosir[1]; /******************************************************************************* *SPI slave reveive in 8-bits format *******************************************************************************/ always @(posedge clk or negedge rst_n)begin if(!rst_n)begin bitcnt <= 3'b000; byte_data_received <= 8'h0; end else begin if(~ssel_active) bitcnt <= 3'b000; else begin if(sck_risingedge)begin bitcnt <= bitcnt + 3'b001; byte_data_received <= {byte_data_received[6:0], mosi_data}; end else begin bitcnt <= bitcnt; byte_data_received <= byte_data_received; end end end end always @(posedge clk or negedge rst_n) begin if(!rst_n) byte_received <= 1'b0; else byte_received <= ssel_active && sck_risingedge && (bitcnt==3'b111); end always @(posedge clk or negedge rst_n) begin if(!rst_n)begin bytecnt <= 8'h0; received_memory <= 8'h0; end else begin if(byte_received) begin bytecnt <= bytecnt + 1'b1; received_memory <= (byte_data_received == bytecnt) ? (received_memory + 1'b1) : received_memory; end else begin bytecnt <= bytecnt; received_memory <= received_memory; end end end /******************************************************************************* *SPI slave send date *******************************************************************************/ always @(posedge clk or negedge rst_n) begin if(!rst_n) cnt<= 8'h0; else begin if(byte_received) cnt<=cnt+8'h1; // count the messages else cnt<=cnt; end end always @(posedge clk or negedge rst_n) begin if(!rst_n) byte_data_sent <= 8'h0; else begin if(ssel_active && sck_fallingedge) begin if(bitcnt==3'b000) byte_data_sent <= cnt; // after that, we send 0s else byte_data_sent <= {byte_data_sent[6:0], 1'b0}; end else byte_data_sent <= byte_data_sent; end end assign miso = byte_data_sent[7]; // send MSB first always @(posedge clk or negedge rst_n) begin if(!rst_n) recived_status <= 1'b0; else recived_status <= (received_memory == 8'd64) ? 1'b1 : 1'b0; end endmodule

(** * Basics: Functional Programming in Coq *) (* [Admitted] is Coq's "escape hatch" that says accept this definition without proof. We use it to mark the 'holes' in the development that should be completed as part of your homework exercises. In practice, [Admitted] is useful when you're incrementally developing large proofs. *) Definition admit {T: Type} : T. Admitted. (* ###################################################################### *) (** * Introduction *) (** The functional programming style brings programming closer to simple, everyday mathematics: If a procedure or method has no side effects, then pretty much all you need to understand about it is how it maps inputs to outputs -- that is, you can think of it as just a concrete method for computing a mathematical function. This is one sense of the word "functional" in "functional programming." The direct connection between programs and simple mathematical objects supports both formal proofs of correctness and sound informal reasoning about program behavior. The other sense in which functional programming is "functional" is that it emphasizes the use of functions (or methods) as _first-class_ values -- i.e., values that can be passed as arguments to other functions, returned as results, stored in data structures, etc. The recognition that functions can be treated as data in this way enables a host of useful and powerful idioms. Other common features of functional languages include _algebraic data types_ and _pattern matching_, which make it easy to construct and manipulate rich data structures, and sophisticated _polymorphic type systems_ that support abstraction and code reuse. Coq shares all of these features. The first half of this chapter introduces the most essential elements of Coq's functional programming language. The second half introduces some basic _tactics_ that can be used to prove simple properties of Coq programs. *) (* ###################################################################### *) (** * Enumerated Types *) (** One unusual aspect of Coq is that its set of built-in features is _extremely_ small. For example, instead of providing the usual palette of atomic data types (booleans, integers, strings, etc.), Coq offers an extremely powerful mechanism for defining new data types from scratch -- so powerful that all these familiar types arise as instances. Naturally, the Coq distribution comes with an extensive standard library providing definitions of booleans, numbers, and many common data structures like lists and hash tables. But there is nothing magic or primitive about these library definitions: they are ordinary user code. To illustrate this, we will explicitly recapitulate all the definitions we need in this course, rather than just getting them implicitly from the library. To see how this mechanism works, let's start with a very simple example. *) (* ###################################################################### *) (** ** Days of the Week *) (** The following declaration tells Coq that we are defining a new set of data values -- a _type_. *) Inductive day : Type := | monday : day | tuesday : day | wednesday : day | thursday : day | friday : day | saturday : day | sunday : day. (** The type is called [day], and its members are [monday], [tuesday], etc. The second and following lines of the definition can be read "[monday] is a [day], [tuesday] is a [day], etc." Having defined [day], we can write functions that operate on days. *) Definition next_weekday (d:day) : day := match d with | monday => tuesday | tuesday => wednesday | wednesday => thursday | thursday => friday | friday => monday | saturday => monday | sunday => monday end. (** One thing to note is that the argument and return types of this function are explicitly declared. Like most functional programming languages, Coq can often figure out these types for itself when they are not given explicitly -- i.e., it performs some _type inference_ -- but we'll always include them to make reading easier. *) (** Having defined a function, we should check that it works on some examples. There are actually three different ways to do this in Coq. First, we can use the command [Eval compute] to evaluate a compound expression involving [next_weekday]. *) Eval compute in (next_weekday friday). (* ==> monday : day *) Eval compute in (next_weekday (next_weekday saturday)). (* ==> tuesday : day *) (** If you have a computer handy, this would be an excellent moment to fire up the Coq interpreter under your favorite IDE -- either CoqIde or Proof General -- and try this for yourself. Load this file ([Basics.v]) from the book's accompanying Coq sources, find the above example, submit it to Coq, and observe the result. *) (** The keyword [compute] tells Coq precisely how to evaluate the expression we give it. For the moment, [compute] is the only one we'll need; later on we'll see some alternatives that are sometimes useful. *) (** Second, we can record what we _expect_ the result to be in the form of a Coq example: *) Example test_next_weekday: (next_weekday (next_weekday saturday)) = tuesday. (** This declaration does two things: it makes an assertion (that the second weekday after [saturday] is [tuesday]), and it gives the assertion a name that can be used to refer to it later. *) (** Having made the assertion, we can also ask Coq to verify it, like this: *) Proof. simpl. reflexivity. Qed. (** The details are not important for now (we'll come back to them in a bit), but essentially this can be read as "The assertion we've just made can be proved by observing that both sides of the equality evaluate to the same thing, after some simplification." *) (** Third, we can ask Coq to _extract_, from our [Definition], a program in some other, more conventional, programming language (OCaml, Scheme, or Haskell) with a high-performance compiler. This facility is very interesting, since it gives us a way to construct _fully certified_ programs in mainstream languages. Indeed, this is one of the main uses for which Coq was developed. We'll come back to this topic in later chapters. More information can also be found in the Coq'Art book by Bertot and Casteran, as well as the Coq reference manual. *) (* ###################################################################### *) (** ** Booleans *) (** In a similar way, we can define the standard type [bool] of booleans, with members [true] and [false]. *) Inductive bool : Type := | true : bool | false : bool. (** Although we are rolling our own booleans here for the sake of building up everything from scratch, Coq does, of course, provide a default implementation of the booleans in its standard library, together with a multitude of useful functions and lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library documentation if you're interested.) Whenever possible, we'll name our own definitions and theorems so that they exactly coincide with the ones in the standard library. *) (** Functions over booleans can be defined in the same way as above: *) Definition negb (b:bool) : bool := match b with | true => false | false => true end. Definition andb (b1:bool) (b2:bool) : bool := match b1 with | true => b2 | false => false end. Definition orb (b1:bool) (b2:bool) : bool := match b1 with | true => true | false => b2 end. (** The last two illustrate the syntax for multi-argument function definitions. *) (** The following four "unit tests" constitute a complete specification -- a truth table -- for the [orb] function: *) Example test_orb1: (orb true false) = true. Proof. reflexivity. Qed. Example test_orb2: (orb false false) = false. Proof. reflexivity. Qed. Example test_orb3: (orb false true) = true. Proof. reflexivity. Qed. Example test_orb4: (orb true true) = true. Proof. reflexivity. Qed. (** (Note that we've dropped the [simpl] in the proofs. It's not actually needed because [reflexivity] automatically performs simplification.) *) (** _A note on notation_: In .v files, we use square brackets to delimit fragments of Coq code within comments; this convention, also used by the [coqdoc] documentation tool, keeps them visually separate from the surrounding text. In the html version of the files, these pieces of text appear in a [different font]. *) (** The values [Admitted] and [admit] can be used to fill a hole in an incomplete definition or proof. We'll use them in the following exercises. In general, your job in the exercises is to replace [admit] or [Admitted] with real definitions or proofs. *) (** **** Exercise: 1 star (nandb) *) (** Complete the definition of the following function, then make sure that the [Example] assertions below can each be verified by Coq. *) (** This function should return [true] if either or both of its inputs are [false]. *) Definition nandb (b1:bool) (b2:bool) : bool := negb (andb b1 b2). (** Remove "[Admitted.]" and fill in each proof with "[Proof. reflexivity. Qed.]" *) Example test_nandb1: (nandb true false) = true. Proof. reflexivity. Qed. Example test_nandb2: (nandb false false) = true. Proof. reflexivity. Qed. Example test_nandb3: (nandb false true) = true. Proof. reflexivity. Qed. Example test_nandb4: (nandb true true) = false. Proof. reflexivity. Qed. (** [] *) (** **** Exercise: 1 star (andb3) *) (** Do the same for the [andb3] function below. This function should return [true] when all of its inputs are [true], and [false] otherwise. *) Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool := andb (andb b1 b2) b3. Example test_andb31: (andb3 true true true) = true. Proof. reflexivity. Qed. Example test_andb32: (andb3 false true true) = false. Proof. reflexivity. Qed. Example test_andb33: (andb3 true false true) = false. Proof. reflexivity. Qed. Example test_andb34: (andb3 true true false) = false. Proof. reflexivity. Qed. (** [] *) (* ###################################################################### *) (** ** Function Types *) (** The [Check] command causes Coq to print the type of an expression. For example, the type of [negb true] is [bool]. *) Check true. (* ===> true : bool *) Check (negb true). (* ===> negb true : bool *) (** Functions like [negb] itself are also data values, just like [true] and [false]. Their types are called _function types_, and they are written with arrows. *) Check negb. (* ===> negb : bool -> bool *) (** The type of [negb], written [bool -> bool] and pronounced "[bool] arrow [bool]," can be read, "Given an input of type [bool], this function produces an output of type [bool]." Similarly, the type of [andb], written [bool -> bool -> bool], can be read, "Given two inputs, both of type [bool], this function produces an output of type [bool]." *) (* ###################################################################### *) (** ** Numbers *) (** _Technical digression_: Coq provides a fairly sophisticated _module system_, to aid in organizing large developments. In this course we won't need most of its features, but one is useful: If we enclose a collection of declarations between [Module X] and [End X] markers, then, in the remainder of the file after the [End], these definitions will be referred to by names like [X.foo] instead of just [foo]. Here, we use this feature to introduce the definition of the type [nat] in an inner module so that it does not shadow the one from the standard library. *) Module Playground1. (** The types we have defined so far are examples of "enumerated types": their definitions explicitly enumerate a finite set of elements. A more interesting way of defining a type is to give a collection of "inductive rules" describing its elements. For example, we can define the natural numbers as follows: *) Inductive nat : Type := | O : nat | S : nat -> nat. (** The clauses of this definition can be read: - [O] is a natural number (note that this is the letter "[O]," not the numeral "[0]"). - [S] is a "constructor" that takes a natural number and yields another one -- that is, if [n] is a natural number, then [S n] is too. Let's look at this in a little more detail. Every inductively defined set ([day], [nat], [bool], etc.) is actually a set of _expressions_. The definition of [nat] says how expressions in the set [nat] can be constructed: - the expression [O] belongs to the set [nat]; - if [n] is an expression belonging to the set [nat], then [S n] is also an expression belonging to the set [nat]; and - expressions formed in these two ways are the only ones belonging to the set [nat]. The same rules apply for our definitions of [day] and [bool]. The annotations we used for their constructors are analogous to the one for the [O] constructor, and indicate that each of those constructors doesn't take any arguments. *) (** These three conditions are the precise force of the [Inductive] declaration. They imply that the expression [O], the expression [S O], the expression [S (S O)], the expression [S (S (S O))], and so on all belong to the set [nat], while other expressions like [true], [andb true false], and [S (S false)] do not. We can write simple functions that pattern match on natural numbers just as we did above -- for example, the predecessor function: *) Definition pred (n : nat) : nat := match n with | O => O | S n' => n' end. (** The second branch can be read: "if [n] has the form [S n'] for some [n'], then return [n']." *) End Playground1. Definition minustwo (n : nat) : nat := match n with | O => O | S O => O | S (S n') => n' end. (** Because natural numbers are such a pervasive form of data, Coq provides a tiny bit of built-in magic for parsing and printing them: ordinary arabic numerals can be used as an alternative to the "unary" notation defined by the constructors [S] and [O]. Coq prints numbers in arabic form by default: *) Check (S (S (S (S O)))). Eval compute in (minustwo 4). (** The constructor [S] has the type [nat -> nat], just like the functions [minustwo] and [pred]: *) Check S. Check pred. Check minustwo. (** These are all things that can be applied to a number to yield a number. However, there is a fundamental difference: functions like [pred] and [minustwo] come with _computation rules_ -- e.g., the definition of [pred] says that [pred 2] can be simplified to [1] -- while the definition of [S] has no such behavior attached. Although it is like a function in the sense that it can be applied to an argument, it does not _do_ anything at all! *) (** For most function definitions over numbers, pure pattern matching is not enough: we also need recursion. For example, to check that a number [n] is even, we may need to recursively check whether [n-2] is even. To write such functions, we use the keyword [Fixpoint]. *) Fixpoint evenb (n:nat) : bool := match n with | O => true | S O => false | S (S n') => evenb n' end. (** We can define [oddb] by a similar [Fixpoint] declaration, but here is a simpler definition that will be a bit easier to work with: *) Definition oddb (n:nat) : bool := negb (evenb n). Example test_oddb1: (oddb (S O)) = true. Proof. reflexivity. Qed. Example test_oddb2: (oddb (S (S (S (S O))))) = false. Proof. reflexivity. Qed. (** Naturally, we can also define multi-argument functions by recursion. (Once again, we use a module to avoid polluting the namespace.) *) Module Playground2. Fixpoint plus (n : nat) (m : nat) : nat := match n with | O => m | S n' => S (plus n' m) end. (** Adding three to two now gives us five, as we'd expect. *) Eval compute in (plus (S (S (S O))) (S (S O))). (** The simplification that Coq performs to reach this conclusion can be visualized as follows: *) (* [plus (S (S (S O))) (S (S O))] ==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match] ==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match] ==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match] ==> [S (S (S (S (S O))))] by the first clause of the [match] *) (** As a notational convenience, if two or more arguments have the same type, they can be written together. In the following definition, [(n m : nat)] means just the same as if we had written [(n : nat) (m : nat)]. *) Fixpoint mult (n m : nat) : nat := match n with | O => O | S n' => plus m (mult n' m) end. Example test_mult1: (mult 3 3) = 9. Proof. reflexivity. Qed. (** You can match two expressions at once by putting a comma between them: *) Fixpoint minus (n m:nat) : nat := match n, m with | O , _ => O | S _ , O => n | S n', S m' => minus n' m' end. (** The _ in the first line is a _wildcard pattern_. Writing _ in a pattern is the same as writing some variable that doesn't get used on the right-hand side. This avoids the need to invent a bogus variable name. *) End Playground2. Fixpoint exp (base power : nat) : nat := match power with | O => S O | S p => mult base (exp base p) end. (** **** Exercise: 1 star (factorial) *) (** Recall the standard factorial function: << factorial(0) = 1 factorial(n) = n * factorial(n-1) (if n>0) >> Translate this into Coq. *) Fixpoint factorial (n:nat) : nat := match n with | O => 1 | S n' => mult n (factorial n') end. Example test_factorial1: (factorial 3) = 6. Proof. reflexivity. Qed. Example test_factorial2: (factorial 5) = (mult 10 12). Proof. reflexivity. Qed. (** [] *) (** We can make numerical expressions a little easier to read and write by introducing "notations" for addition, multiplication, and subtraction. *) Notation "x + y" := (plus x y) (at level 50, left associativity) : nat_scope. Notation "x - y" := (minus x y) (at level 50, left associativity) : nat_scope. Notation "x * y" := (mult x y) (at level 40, left associativity) : nat_scope. Check ((0 + 1) + 1). (** (The [level], [associativity], and [nat_scope] annotations control how these notations are treated by Coq's parser. The details are not important, but interested readers can refer to the "More on Notation" subsection in the "Advanced Material" section at the end of this chapter.) *) (** Note that these do not change the definitions we've already made: they are simply instructions to the Coq parser to accept [x + y] in place of [plus x y] and, conversely, to the Coq pretty-printer to display [plus x y] as [x + y]. *) (** When we say that Coq comes with nothing built-in, we really mean it: even equality testing for numbers is a user-defined operation! *) (** The [beq_nat] function tests [nat]ural numbers for [eq]uality, yielding a [b]oolean. Note the use of nested [match]es (we could also have used a simultaneous match, as we did in [minus].) *) Fixpoint beq_nat (n m : nat) : bool := match n with | O => match m with | O => true | S m' => false end | S n' => match m with | O => false | S m' => beq_nat n' m' end end. (** Similarly, the [ble_nat] function tests [nat]ural numbers for [l]ess-or-[e]qual, yielding a [b]oolean. *) Fixpoint ble_nat (n m : nat) : bool := match n with | O => true | S n' => match m with | O => false | S m' => ble_nat n' m' end end. Example test_ble_nat1: (ble_nat 2 2) = true. Proof. reflexivity. Qed. Example test_ble_nat2: (ble_nat 2 4) = true. Proof. reflexivity. Qed. Example test_ble_nat3: (ble_nat 4 2) = false. Proof. reflexivity. Qed. (** **** Exercise: 2 stars (blt_nat) *) (** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han, yielding a [b]oolean. Instead of making up a new [Fixpoint] for this one, define it in terms of a previously defined function. *) Definition blt_nat (n m : nat) : bool := ble_nat (S n) m. Example test_blt_nat1: (blt_nat 2 2) = false. Proof. reflexivity. Qed. Example test_blt_nat2: (blt_nat 2 4) = true. Proof. reflexivity. Qed. Example test_blt_nat3: (blt_nat 4 2) = false. Proof. reflexivity. Qed. (** [] *) (* ###################################################################### *) (** * Proof by Simplification *) (** Now that we've defined a few datatypes and functions, let's turn to the question of how to state and prove properties of their behavior. Actually, in a sense, we've already started doing this: each [Example] in the previous sections makes a precise claim about the behavior of some function on some particular inputs. The proofs of these claims were always the same: use [reflexivity] to check that both sides of the [=] simplify to identical values. (By the way, it will be useful later to know that [reflexivity] actually does somewhat more simplification than [simpl] does -- for example, it tries "unfolding" defined terms, replacing them with their right-hand sides. The reason for this difference is that, when reflexivity succeeds, the whole goal is finished and we don't need to look at whatever expanded expressions [reflexivity] has found; by contrast, [simpl] is used in situations where we may have to read and understand the new goal, so we would not want it blindly expanding definitions.) The same sort of "proof by simplification" can be used to prove more interesting properties as well. For example, the fact that [0] is a "neutral element" for [+] on the left can be proved just by observing that [0 + n] reduces to [n] no matter what [n] is, a fact that can be read directly off the definition of [plus].*) Theorem plus_O_n : forall n : nat, 0 + n = n. Proof. intros n. reflexivity. Qed. (** (_Note_: You may notice that the above statement looks different in the original source file and the final html output. In Coq files, we write the [forall] universal quantifier using the "_forall_" reserved identifier. This gets printed as an upside-down "A", the familiar symbol used in logic.) *) (** The form of this theorem and proof are almost exactly the same as the examples above; there are just a few differences. First, we've used the keyword [Theorem] instead of [Example]. Indeed, the difference is purely a matter of style; the keywords [Example] and [Theorem] (and a few others, including [Lemma], [Fact], and [Remark]) mean exactly the same thing to Coq. Secondly, we've added the quantifier [forall n:nat], so that our theorem talks about _all_ natural numbers [n]. In order to prove theorems of this form, we need to to be able to reason by _assuming_ the existence of an arbitrary natural number [n]. This is achieved in the proof by [intros n], which moves the quantifier from the goal to a "context" of current assumptions. In effect, we start the proof by saying "OK, suppose [n] is some arbitrary number." The keywords [intros], [simpl], and [reflexivity] are examples of _tactics_. A tactic is a command that is used between [Proof] and [Qed] to tell Coq how it should check the correctness of some claim we are making. We will see several more tactics in the rest of this lecture, and yet more in future lectures. *) (** We could try to prove a similar theorem about [plus] *) Theorem plus_n_O : forall n, n + 0 = n. (** However, unlike the previous proof, [simpl] doesn't do anything in this case *) Proof. simpl. (* Doesn't do anything! *) Abort. (** (Can you explain why this happens? Step through both proofs with Coq and notice how the goal and context change.) *) Theorem plus_1_l : forall n:nat, 1 + n = S n. Proof. intros n. reflexivity. Qed. Theorem mult_0_l : forall n:nat, 0 * n = 0. Proof. intros n. reflexivity. Qed. (** The [_l] suffix in the names of these theorems is pronounced "on the left." *) (* ###################################################################### *) (** * Proof by Rewriting *) (** Here is a slightly more interesting theorem: *) Theorem plus_id_example : forall n m:nat, n = m -> n + n = m + m. (** Instead of making a completely universal claim about all numbers [n] and [m], this theorem talks about a more specialized property that only holds when [n = m]. The arrow symbol is pronounced "implies." As before, we need to be able to reason by assuming the existence of some numbers [n] and [m]. We also need to assume the hypothesis [n = m]. The [intros] tactic will serve to move all three of these from the goal into assumptions in the current context. Since [n] and [m] are arbitrary numbers, we can't just use simplification to prove this theorem. Instead, we prove it by observing that, if we are assuming [n = m], then we can replace [n] with [m] in the goal statement and obtain an equality with the same expression on both sides. The tactic that tells Coq to perform this replacement is called [rewrite]. *) Proof. intros n m. (* move both quantifiers into the context *) intros H. (* move the hypothesis into the context *) rewrite -> H. (* Rewrite the goal using the hypothesis *) reflexivity. Qed. (** The first line of the proof moves the universally quantified variables [n] and [m] into the context. The second moves the hypothesis [n = m] into the context and gives it the (arbitrary) name [H]. The third tells Coq to rewrite the current goal ([n + n = m + m]) by replacing the/ left side of the equality hypothesis [H] with the right side. (The arrow symbol in the [rewrite] has nothing to do with implication: it tells Coq to apply the rewrite from left to right. To rewrite from right to left, you can use [rewrite <-]. Try making this change in the above proof and see what difference it makes in Coq's behavior.) *) (** **** Exercise: 1 star (plus_id_exercise) *) (** Remove "[Admitted.]" and fill in the proof. *) Theorem plus_id_exercise : forall n m o : nat, n = m -> m = o -> n + m = m + o. Proof. intros n m o H1 H2. rewrite H1. rewrite <- H2. reflexivity. Qed. (** [] *) (** As we've seen in earlier examples, the [Admitted] command tells Coq that we want to skip trying to prove this theorem and just accept it as a given. This can be useful for developing longer proofs, since we can state subsidiary facts that we believe will be useful for making some larger argument, use [Admitted] to accept them on faith for the moment, and continue thinking about the larger argument until we are sure it makes sense; then we can go back and fill in the proofs we skipped. Be careful, though: every time you say [Admitted] (or [admit]) you are leaving a door open for total nonsense to enter Coq's nice, rigorous, formally checked world! *) (** We can also use the [rewrite] tactic with a previously proved theorem instead of a hypothesis from the context. *) Theorem mult_0_plus : forall n m : nat, (0 + n) * m = n * m. Proof. intros n m. rewrite -> plus_O_n. reflexivity. Qed. (** **** Exercise: 2 stars (mult_S_1) *) Theorem mult_S_1 : forall n m : nat, m = S n -> m * (1 + n) = m * m. Proof. intros n m H. simpl. rewrite <- H. reflexivity. Qed. (** [] *) (* ###################################################################### *) (** * Proof by Case Analysis *) (** Of course, not everything can be proved by simple calculation: In general, unknown, hypothetical values (arbitrary numbers, booleans, lists, etc.) can block the calculation. For example, if we try to prove the following fact using the [simpl] tactic as above, we get stuck. *) Theorem plus_1_neq_0_firsttry : forall n : nat, beq_nat (n + 1) 0 = false. Proof. intros n. simpl. (* does nothing! *) Abort. (** The reason for this is that the definitions of both [beq_nat] and [+] begin by performing a [match] on their first argument. But here, the first argument to [+] is the unknown number [n] and the argument to [beq_nat] is the compound expression [n + 1]; neither can be simplified. What we need is to be able to consider the possible forms of [n] separately. If [n] is [O], then we can calculate the final result of [beq_nat (n + 1) 0] and check that it is, indeed, [false]. And if [n = S n'] for some [n'], then, although we don't know exactly what number [n + 1] yields, we can calculate that, at least, it will begin with one [S], and this is enough to calculate that, again, [beq_nat (n + 1) 0] will yield [false]. The tactic that tells Coq to consider, separately, the cases where [n = O] and where [n = S n'] is called [destruct]. *) Theorem plus_1_neq_0 : forall n : nat, beq_nat (n + 1) 0 = false. Proof. intros n. destruct n as [| n']. reflexivity. reflexivity. Qed. (** The [destruct] generates _two_ subgoals, which we must then prove, separately, in order to get Coq to accept the theorem as proved. (No special command is needed for moving from one subgoal to the other. When the first subgoal has been proved, it just disappears and we are left with the other "in focus.") In this proof, each of the subgoals is easily proved by a single use of [reflexivity]. The annotation "[as [| n']]" is called an _intro pattern_. It tells Coq what variable names to introduce in each subgoal. In general, what goes between the square brackets is a _list_ of lists of names, separated by [|]. Here, the first component is empty, since the [O] constructor is nullary (it doesn't carry any data). The second component gives a single name, [n'], since [S] is a unary constructor. The [destruct] tactic can be used with any inductively defined datatype. For example, we use it here to prove that boolean negation is involutive -- i.e., that negation is its own inverse. *) Theorem negb_involutive : forall b : bool, negb (negb b) = b. Proof. intros b. destruct b. reflexivity. reflexivity. Qed. (** Note that the [destruct] here has no [as] clause because none of the subcases of the [destruct] need to bind any variables, so there is no need to specify any names. (We could also have written [as [|]], or [as []].) In fact, we can omit the [as] clause from _any_ [destruct] and Coq will fill in variable names automatically. Although this is convenient, it is arguably bad style, since Coq often makes confusing choices of names when left to its own devices. *) (** **** Exercise: 1 star (zero_nbeq_plus_1) *) Theorem zero_nbeq_plus_1 : forall n : nat, beq_nat 0 (n + 1) = false. Proof. intros n. destruct n as [| n']. simpl. reflexivity. simpl. reflexivity. Qed. (** [] *) (* ###################################################################### *) (** * More Exercises *) (** **** Exercise: 2 stars (boolean_functions) *) (** Use the tactics you have learned so far to prove the following theorem about boolean functions. *) Theorem identity_fn_applied_twice : forall (f : bool -> bool), (forall (x : bool), f x = x) -> forall (b : bool), f (f b) = b. Proof. intros f H b. rewrite H. rewrite H. reflexivity. Qed. (** Now state and prove a theorem [negation_fn_applied_twice] similar to the previous one but where the second hypothesis says that the function [f] has the property that [f x = negb x].*) Theorem negation_fn_applied_twice : forall (f : bool -> bool), (forall (x : bool), f x = negb x) -> forall (b : bool), f (f b) = b. Proof. intros f H b. rewrite H. rewrite H. rewrite negb_involutive. reflexivity. Qed. (** [] *) (** **** Exercise: 2 stars (andb_eq_orb) *) (** Prove the following theorem. (You may want to first prove a subsidiary lemma or two. Alternatively, remember that you do not have to introduce all hypotheses at the same time.) *) Lemma andb_true : forall (b : bool), andb b true = true -> b = true. Proof. intros b H. destruct b. reflexivity. inversion H. Qed. Lemma orb_true : forall (b : bool), orb b true = true. Proof. intros b. destruct b; reflexivity. Qed. Lemma andb_true_b : forall (b : bool), andb b true = b. Proof. intros b. destruct b; reflexivity. Qed. Lemma orb_false_b : forall (b : bool), orb b false = b. Proof. intros b. destruct b; reflexivity. Qed. Theorem andb_false : forall (b : bool), andb b false = false. Proof. intros b. destruct b ; reflexivity. Qed. Theorem andb_eq_orb : forall (b c : bool), (andb b c = orb b c) -> b = c. Proof. intros b c H. destruct c. rewrite <- orb_true with (b := b). rewrite <- H. rewrite andb_true_b. reflexivity. rewrite <- andb_false with (b := b). rewrite H. rewrite orb_false_b. reflexivity. Qed. (** [] *) (** **** Exercise: 3 stars (binary) *) (** Consider a different, more efficient representation of natural numbers using a binary rather than unary system. That is, instead of saying that each natural number is either zero or the successor of a natural number, we can say that each binary number is either - zero, - twice a binary number, or - one more than twice a binary number. (a) First, write an inductive definition of the type [bin] corresponding to this description of binary numbers. (Hint: Recall that the definition of [nat] from class, Inductive nat : Type := | O : nat | S : nat -> nat. says nothing about what [O] and [S] "mean." It just says "[O] is in the set called [nat], and if [n] is in the set then so is [S n]." The interpretation of [O] as zero and [S] as successor/plus one comes from the way that we _use_ [nat] values, by writing functions to do things with them, proving things about them, and so on. Your definition of [bin] should be correspondingly simple; it is the functions you will write next that will give it mathematical meaning.) (b) Next, write an increment function [incr] for binary numbers, and a function [bin_to_nat] to convert binary numbers to unary numbers. (c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc. for your increment and binary-to-unary functions. Notice that incrementing a binary number and then converting it to unary should yield the same result as first converting it to unary and then incrementing. *) Inductive bin : Type := | Ob : bin | Tb : bin -> bin | STb : bin -> bin. Fixpoint incr (n: bin) : bin := match n with | Ob => STb Ob | Tb n => STb n | STb n => Tb (incr n) end. Fixpoint bin_to_nat (n : bin) : nat := match n with | Ob => O | Tb n => 2 * (bin_to_nat n) | STb n => 2 * (bin_to_nat n) + 1 end. Lemma plus_1_S : forall n : nat, n + 1 = S n. Proof. intros n. induction n. simpl. reflexivity. simpl. rewrite IHn. reflexivity. Qed. Lemma plus_O : forall n : nat, n + 0 = n. intros n. induction n. reflexivity. simpl. rewrite IHn. reflexivity. Qed. Lemma S_equal : forall n m : nat, S n = S m <-> n = m. Proof. intros n m. split. intros H. inversion H. reflexivity. intros H. rewrite H. reflexivity. Qed. Lemma S_equal_l : forall n m : nat, S n = S m -> n = m. Proof. intros n m H. inversion H. reflexivity. Qed. Lemma S_equal_r : forall n m : nat, n = m -> S n = S m. intros n m H. rewrite H. reflexivity. Qed. Lemma plus_SS : forall n m : nat, S n + S m = S (S (n + m)). Proof. intros n. induction n as [|n']. intros m. simpl. reflexivity. intros m. simpl. apply S_equal. rewrite <- IHn'. simpl. reflexivity. Qed. Theorem incr_bin_nat : forall n : bin, bin_to_nat (incr n) = S (bin_to_nat n). Proof. intros n. induction n as [| n' | n']. (* n = Ob *) simpl. reflexivity. (* n = Tb n' *) simpl. rewrite plus_1_S. reflexivity. (* n = STb n' *) simpl. rewrite IHn'. rewrite plus_1_S. rewrite plus_O. rewrite plus_O. rewrite plus_SS. reflexivity. Qed. (** [] *) (* ###################################################################### *) (** * More on Notation (Advanced) *) (** In general, sections marked Advanced are not needed to follow the rest of the book, except possibly other Advanced sections. On a first reading, you might want to skim these sections so that you know what's there for future reference. *) Notation "x + y" := (plus x y) (at level 50, left associativity) : nat_scope. Notation "x * y" := (mult x y) (at level 40, left associativity) : nat_scope. (** For each notation-symbol in Coq we can specify its _precedence level_ and its _associativity_. The precedence level n can be specified by the keywords [at level n] and it is helpful to disambiguate expressions containing different symbols. The associativity is helpful to disambiguate expressions containing more occurrences of the same symbol. For example, the parameters specified above for [+] and [*] say that the expression [1+2*3*4] is a shorthand for the expression [(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and _left_, _right_, or _no_ associativity. Each notation-symbol in Coq is also active in a _notation scope_. Coq tries to guess what scope you mean, so when you write [S(O*O)] it guesses [nat_scope], but when you write the cartesian product (tuple) type [bool*bool] it guesses [type_scope]. Occasionally you have to help it out with percent-notation by writing [(x*y)%nat], and sometimes in Coq's feedback to you it will use [%nat] to indicate what scope a notation is in. Notation scopes also apply to numeral notation (3,4,5, etc.), so you may sometimes see [0%nat] which means [O], or [0%Z] which means the Integer zero. *) (** * [Fixpoint] and Structural Recursion (Advanced) *) Fixpoint plus' (n : nat) (m : nat) : nat := match n with | O => m | S n' => S (plus' n' m) end. (** When Coq checks this definition, it notes that [plus'] is "decreasing on 1st argument." What this means is that we are performing a _structural recursion_ over the argument [n] -- i.e., that we make recursive calls only on strictly smaller values of [n]. This implies that all calls to [plus'] will eventually terminate. Coq demands that some argument of _every_ [Fixpoint] definition is "decreasing". This requirement is a fundamental feature of Coq's design: In particular, it guarantees that every function that can be defined in Coq will terminate on all inputs. However, because Coq's "decreasing analysis" is not very sophisticated, it is sometimes necessary to write functions in slightly unnatural ways. *) (** **** Exercise: 2 stars, optional (decreasing) *) (** To get a concrete sense of this, find a way to write a sensible [Fixpoint] definition (of a simple function on numbers, say) that _does_ terminate on all inputs, but that Coq will reject because of this restriction. *) (* FILL IN HERE *) (** [] *) (** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)

/* -*- tab-width: 4 -*- * * Electric(tm) VLSI Design System * * File: jtagController.v * * Copyright (c) 2005 Sun Microsystems and Static Free Software * * Electric(tm) is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 3 of the License, or * (at your option) any later version. * * Electric(tm) is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with Electric(tm); see the file COPYING. If not, write to * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, * Boston, Mass 02111-1307, USA. */ /* Verilog for cell testCell{sch} from Library jtag */ /* Created on Tue April 26, 2005 11:27:36 */ /* Last revised on Tue April 26, 2005 11:29:37 */ /* Written on Tue April 26, 2005 11:30:54 by Electric VLSI Design System, version 8.02l */ module redFour__NMOSwk_X_1_Delay_100(g, d, s); input g; input d; input s; supply0 gnd; rtranif1 #(100) NMOSfwk_0 (d, s, g); endmodule /* redFour__NMOSwk_X_1_Delay_100 */ module redFour__PMOSwk_X_0_833_Delay_100(g, d, s); input g; input d; input s; supply1 vdd; rtranif0 #(100) PMOSfwk_0 (d, s, g); endmodule /* redFour__PMOSwk_X_0_833_Delay_100 */ module scanChainFive__scanL(in, out); input in; output out; supply1 vdd; supply0 gnd; wire net_4, net_7; redFour__NMOSwk_X_1_Delay_100 NMOSwk_0(.g(out), .d(in), .s(net_7)); redFour__NMOSwk_X_1_Delay_100 NMOSwk_1(.g(out), .d(net_7), .s(gnd)); redFour__PMOSwk_X_0_833_Delay_100 PMOSwk_0(.g(out), .d(net_4), .s(vdd)); redFour__PMOSwk_X_0_833_Delay_100 PMOSwk_1(.g(out), .d(in), .s(net_4)); not (strong0, strong1) #(100) invV_0 (out, in); endmodule /* scanChainFive__scanL */ module redFour__NMOS_X_6_667_Delay_100(g, d, s); input g; input d; input s; supply0 gnd; tranif1 #(100) NMOSf_0 (d, s, g); endmodule /* redFour__NMOS_X_6_667_Delay_100 */ module redFour__PMOS_X_3_333_Delay_100(g, d, s); input g; input d; input s; supply1 vdd; tranif0 #(100) PMOSf_0 (d, s, g); endmodule /* redFour__PMOS_X_3_333_Delay_100 */ module scanChainFive__scanP(in, src, drn); input in; input src; output drn; supply1 vdd; supply0 gnd; wire net_1; redFour__NMOS_X_6_667_Delay_100 NMOS_0(.g(in), .d(drn), .s(src)); redFour__PMOS_X_3_333_Delay_100 PMOS_0(.g(net_1), .d(drn), .s(src)); not (strong0, strong1) #(0) inv_0 (net_1, in); endmodule /* scanChainFive__scanP */ module scanChainFive__scanRL(phi1, phi2, rd, sin, sout); input phi1; input phi2; input rd; input sin; output sout; supply1 vdd; supply0 gnd; wire net_0, net_2, net_3; scanChainFive__scanL foo1(.in(net_2), .out(net_3)); scanChainFive__scanL foo2(.in(net_0), .out(sout)); scanChainFive__scanP scanP_0(.in(rd), .src(vdd), .drn(net_0)); scanChainFive__scanP scanP_1(.in(phi1), .src(net_3), .drn(net_0)); scanChainFive__scanP scanP_2(.in(phi2), .src(sin), .drn(net_2)); endmodule /* scanChainFive__scanRL */ module jtag__BR(SDI, phi1, phi2, read, SDO); input SDI; input phi1; input phi2; input read; output SDO; supply1 vdd; supply0 gnd; scanChainFive__scanRL scanRL_0(.phi1(phi1), .phi2(phi2), .rd(read), .sin(SDI), .sout(SDO)); endmodule /* jtag__BR */ module scanChainFive__scanIRH(mclr, phi1, phi2, rd, sin, wr, dout, doutb, sout); input mclr; input phi1; input phi2; input rd; input sin; input wr; output dout; output doutb; output sout; supply1 vdd; supply0 gnd; wire net_2, net_4, net_6, net_7; scanChainFive__scanL foo1(.in(net_6), .out(net_7)); scanChainFive__scanL foo2(.in(net_2), .out(sout)); scanChainFive__scanL foo3(.in(net_4), .out(doutb)); not (strong0, strong1) #(100) invLT_0 (dout, doutb); scanChainFive__scanP scanP_0(.in(wr), .src(sout), .drn(net_4)); scanChainFive__scanP scanP_1(.in(rd), .src(gnd), .drn(net_2)); scanChainFive__scanP scanP_2(.in(mclr), .src(vdd), .drn(net_4)); scanChainFive__scanP scanP_3(.in(phi1), .src(net_7), .drn(net_2)); scanChainFive__scanP scanP_4(.in(phi2), .src(sin), .drn(net_6)); endmodule /* scanChainFive__scanIRH */ module scanChainFive__scanIRL(mclr, phi1, phi2, rd, sin, wr, dout, doutb, sout); input mclr; input phi1; input phi2; input rd; input sin; input wr; output dout; output doutb; output sout; supply1 vdd; supply0 gnd; wire net_2, net_3, net_4, net_6; scanChainFive__scanL foo1(.in(net_2), .out(net_3)); scanChainFive__scanL foo2(.in(net_4), .out(sout)); scanChainFive__scanL foo3(.in(net_6), .out(doutb)); not (strong0, strong1) #(100) invLT_0 (dout, doutb); scanChainFive__scanP scanP_0(.in(rd), .src(vdd), .drn(net_4)); scanChainFive__scanP scanP_1(.in(mclr), .src(vdd), .drn(net_6)); scanChainFive__scanP scanP_2(.in(wr), .src(sout), .drn(net_6)); scanChainFive__scanP scanP_3(.in(phi1), .src(net_3), .drn(net_4)); scanChainFive__scanP scanP_4(.in(phi2), .src(sin), .drn(net_2)); endmodule /* scanChainFive__scanIRL */ module jtag__IR(SDI, phi1, phi2, read, reset, write, IR, IRb, SDO); input SDI; input phi1; input phi2; input read; input reset; input write; output [8:1] IR; output [8:1] IRb; output SDO; supply1 vdd; supply0 gnd; wire net_1, net_2, net_3, net_4, net_5, net_6, net_7; scanChainFive__scanIRH scanIRH_0(.mclr(reset), .phi1(phi1), .phi2(phi2), .rd(read), .sin(net_1), .wr(write), .dout(IR[1]), .doutb(IRb[1]), .sout(SDO)); scanChainFive__scanIRL scanIRL_0(.mclr(reset), .phi1(phi1), .phi2(phi2), .rd(read), .sin(net_3), .wr(write), .dout(IR[7]), .doutb(IRb[7]), .sout(net_2)); scanChainFive__scanIRL scanIRL_1(.mclr(reset), .phi1(phi1), .phi2(phi2), .rd(read), .sin(net_5), .wr(write), .dout(IR[5]), .doutb(IRb[5]), .sout(net_4)); scanChainFive__scanIRL scanIRL_2(.mclr(reset), .phi1(phi1), .phi2(phi2), .rd(read), .sin(net_2), .wr(write), .dout(IR[6]), .doutb(IRb[6]), .sout(net_5)); scanChainFive__scanIRL scanIRL_3(.mclr(reset), .phi1(phi1), .phi2(phi2), .rd(read), .sin(net_7), .wr(write), .dout(IR[3]), .doutb(IRb[3]), .sout(net_6)); scanChainFive__scanIRL scanIRL_4(.mclr(reset), .phi1(phi1), .phi2(phi2), .rd(read), .sin(net_6), .wr(write), .dout(IR[2]), .doutb(IRb[2]), .sout(net_1)); scanChainFive__scanIRL scanIRL_5(.mclr(reset), .phi1(phi1), .phi2(phi2), .rd(read), .sin(net_4), .wr(write), .dout(IR[4]), .doutb(IRb[4]), .sout(net_7)); scanChainFive__scanIRL scanIRL_6(.mclr(reset), .phi1(phi1), .phi2(phi2), .rd(read), .sin(SDI), .wr(write), .dout(IR[8]), .doutb(IRb[8]), .sout(net_3)); endmodule /* jtag__IR */ module redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1(ina, inb, out); input ina; input inb; output out; supply1 vdd; supply0 gnd; nor (strong0, strong1) #(100) nor2_0 (out, ina, inb); endmodule /* redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1 */ module jtag__IRdecode(IR, IRb, Bypass, ExTest, SamplePreload, ScanPath); input [4:1] IR; input [4:1] IRb; output Bypass; output ExTest; output SamplePreload; output [12:0] ScanPath; supply1 vdd; supply0 gnd; wire H00, H01, H10, H11, L00, L01, L10, L11, net_19, net_21, net_23, net_25; wire net_26, net_27, net_28, net_29, net_30, net_31, net_32, net_33, net_34; wire net_35, net_36, net_37; not (strong0, strong1) #(100) inv_0 (Bypass, net_19); not (strong0, strong1) #(100) inv_1 (SamplePreload, net_21); not (strong0, strong1) #(100) inv_2 (ExTest, net_23); not (strong0, strong1) #(100) inv_3 (ScanPath[12], net_25); not (strong0, strong1) #(100) inv_4 (ScanPath[11], net_26); not (strong0, strong1) #(100) inv_5 (ScanPath[10], net_27); not (strong0, strong1) #(100) inv_6 (ScanPath[9], net_28); not (strong0, strong1) #(100) inv_7 (ScanPath[8], net_29); not (strong0, strong1) #(100) inv_8 (ScanPath[7], net_30); not (strong0, strong1) #(100) inv_9 (ScanPath[6], net_31); not (strong0, strong1) #(100) inv_10 (ScanPath[5], net_32); not (strong0, strong1) #(100) inv_11 (ScanPath[4], net_33); not (strong0, strong1) #(100) inv_12 (ScanPath[3], net_34); not (strong0, strong1) #(100) inv_13 (ScanPath[2], net_35); not (strong0, strong1) #(100) inv_14 (ScanPath[1], net_36); not (strong0, strong1) #(100) inv_15 (ScanPath[0], net_37); nand (strong0, strong1) #(100) nand2_0 (net_19, L11, H11); nand (strong0, strong1) #(100) nand2_1 (net_21, L10, H11); nand (strong0, strong1) #(100) nand2_2 (net_23, L01, H11); nand (strong0, strong1) #(100) nand2_3 (net_25, L00, H11); nand (strong0, strong1) #(100) nand2_4 (net_26, L11, H10); nand (strong0, strong1) #(100) nand2_5 (net_27, L10, H10); nand (strong0, strong1) #(100) nand2_6 (net_28, L01, H10); nand (strong0, strong1) #(100) nand2_7 (net_29, L00, H10); nand (strong0, strong1) #(100) nand2_8 (net_30, L11, H01); nand (strong0, strong1) #(100) nand2_9 (net_31, L10, H01); nand (strong0, strong1) #(100) nand2_10 (net_32, L01, H01); nand (strong0, strong1) #(100) nand2_11 (net_33, L00, H01); nand (strong0, strong1) #(100) nand2_12 (net_34, L11, H00); nand (strong0, strong1) #(100) nand2_13 (net_35, L10, H00); nand (strong0, strong1) #(100) nand2_14 (net_36, L01, H00); nand (strong0, strong1) #(100) nand2_15 (net_37, L00, H00); redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1 nor2n_0(.ina(IR[1]), .inb(IR[2]), .out(L00)); redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1 nor2n_1(.ina(IRb[1]), .inb(IR[2]), .out(L01)); redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1 nor2n_2(.ina(IR[1]), .inb(IRb[2]), .out(L10)); redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1 nor2n_3(.ina(IRb[1]), .inb(IRb[2]), .out(L11)); redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1 nor2n_4(.ina(IR[3]), .inb(IR[4]), .out(H00)); redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1 nor2n_5(.ina(IRb[3]), .inb(IR[4]), .out(H01)); redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1 nor2n_6(.ina(IR[3]), .inb(IRb[4]), .out(H10)); redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1 nor2n_7(.ina(IRb[3]), .inb(IRb[4]), .out(H11)); endmodule /* jtag__IRdecode */ module redFour__PMOSwk_X_0_222_Delay_100(g, d, s); input g; input d; input s; supply1 vdd; rtranif0 #(100) PMOSfwk_0 (d, s, g); endmodule /* redFour__PMOSwk_X_0_222_Delay_100 */ module jtag__clockGen(clk, phi1_fb, phi2_fb, phi1_out, phi2_out); input clk; input phi1_fb; input phi2_fb; output phi1_out; output phi2_out; supply1 vdd; supply0 gnd; wire net_0, net_1, net_3, net_4, net_6; not (strong0, strong1) #(100) inv_0 (phi2_out, net_3); not (strong0, strong1) #(100) inv_1 (phi1_out, net_6); not (strong0, strong1) #(100) inv_2 (net_4, clk); not (strong0, strong1) #(100) invLT_0 (net_0, phi1_fb); not (strong0, strong1) #(100) invLT_1 (net_1, phi2_fb); nand (strong0, strong1) #(100) nand2_0 (net_3, net_0, net_4); nand (strong0, strong1) #(100) nand2_1 (net_6, net_1, clk); endmodule /* jtag__clockGen */ module jtag__capture_ctl(capture, phi2, sel, out, phi1); input capture; input phi2; input sel; output out; input phi1; supply1 vdd; supply0 gnd; wire net_1, net_2, net_3, net_4; scanChainFive__scanL foo(.in(net_2), .out(net_3)); not (strong0, strong1) #(100) inv_0 (net_1, capture); not (strong0, strong1) #(100) inv_1 (out, net_4); nand (strong0, strong1) #(100) nand3_0 (net_4, sel, net_3, phi1); scanChainFive__scanP scanP_0(.in(phi2), .src(net_1), .drn(net_2)); endmodule /* jtag__capture_ctl */ module jtag__shift_ctl(phi1_fb, phi2_fb, sel, shift, phi1_out, phi2_out, phi1_in, phi2_in); input phi1_fb; input phi2_fb; input sel; input shift; output phi1_out; output phi2_out; input phi1_in; input phi2_in; supply1 vdd; supply0 gnd; wire net_1, net_2, net_3, net_4, net_7; jtag__clockGen clockGen_0(.clk(net_7), .phi1_fb(phi1_fb), .phi2_fb(phi2_fb), .phi1_out(phi1_out), .phi2_out(phi2_out)); scanChainFive__scanL foo(.in(net_2), .out(net_3)); not (strong0, strong1) #(100) inv_0 (net_7, net_4); not (strong0, strong1) #(100) inv_1 (net_1, shift); nand (strong0, strong1) #(100) nand3_0 (net_4, sel, net_3, phi1_in); scanChainFive__scanP scanP_0(.in(phi2_in), .src(net_1), .drn(net_2)); endmodule /* jtag__shift_ctl */ module jtag__update_ctl(sel, update, out, phi2); input sel; input update; output out; input phi2; supply1 vdd; supply0 gnd; wire net_1; not (strong0, strong1) #(100) inv_0 (out, net_1); nand (strong0, strong1) #(100) nand3_0 (net_1, sel, update, phi2); endmodule /* jtag__update_ctl */ module jtag__jtagIRControl(capture, phi1_fb, phi1_in, phi2_fb, phi2_in, shift, update, phi1_out, phi2_out, read, write); input capture; input phi1_fb; input phi1_in; input phi2_fb; input phi2_in; input shift; input update; output phi1_out; output phi2_out; output read; output write; supply1 vdd; supply0 gnd; jtag__capture_ctl capture__0(.capture(capture), .phi2(phi2_in), .sel(vdd), .out(read), .phi1(phi1_in)); jtag__shift_ctl shift_ct_0(.phi1_fb(phi1_fb), .phi2_fb(phi2_fb), .sel(vdd), .shift(shift), .phi1_out(phi1_out), .phi2_out(phi2_out), .phi1_in(phi1_in), .phi2_in(phi2_in)); jtag__update_ctl update_c_0(.sel(vdd), .update(update), .out(write), .phi2(phi2_in)); endmodule /* jtag__jtagIRControl */ module redFour__NMOS_X_8_Delay_100(g, d, s); input g; input d; input s; supply0 gnd; tranif1 #(100) NMOSf_0 (d, s, g); endmodule /* redFour__NMOS_X_8_Delay_100 */ module redFour__PMOS_X_4_Delay_100(g, d, s); input g; input d; input s; supply1 vdd; tranif0 #(100) PMOSf_0 (d, s, g); endmodule /* redFour__PMOS_X_4_Delay_100 */ module jtag__tsinvBig(Din, en, enb, Dout); input Din; input en; input enb; output Dout; supply1 vdd; supply0 gnd; wire net_13, net_14, net_22, net_23; redFour__NMOS_X_8_Delay_100 NMOS_0(.g(Din), .d(net_13), .s(gnd)); redFour__NMOS_X_8_Delay_100 NMOS_1(.g(en), .d(Dout), .s(net_13)); redFour__NMOS_X_8_Delay_100 NMOS_2(.g(en), .d(Dout), .s(net_23)); redFour__NMOS_X_8_Delay_100 NMOS_3(.g(Din), .d(net_23), .s(gnd)); redFour__PMOS_X_4_Delay_100 PMOS_0(.g(enb), .d(Dout), .s(net_14)); redFour__PMOS_X_4_Delay_100 PMOS_1(.g(Din), .d(net_14), .s(vdd)); redFour__PMOS_X_4_Delay_100 PMOS_2(.g(enb), .d(Dout), .s(net_22)); redFour__PMOS_X_4_Delay_100 PMOS_3(.g(Din), .d(net_22), .s(vdd)); endmodule /* jtag__tsinvBig */ module jtag__jtagScanControl(TDI, capture, phi1_fb, phi1_in, phi2_fb, phi2_in, sel, shift, update, TDO, phi1_out, phi2_out, read, write); input TDI; input capture; input phi1_fb; input phi1_in; input phi2_fb; input phi2_in; input sel; input shift; input update; output TDO; output phi1_out; output phi2_out; output read; output write; supply1 vdd; supply0 gnd; wire net_0, net_2; jtag__capture_ctl capture__0(.capture(capture), .phi2(phi2_in), .sel(sel), .out(read), .phi1(phi1_in)); not (strong0, strong1) #(100) inv_0 (net_2, sel); not (strong0, strong1) #(100) inv_1 (net_0, TDI); jtag__shift_ctl shift_ct_0(.phi1_fb(phi1_fb), .phi2_fb(phi2_fb), .sel(sel), .shift(shift), .phi1_out(phi1_out), .phi2_out(phi2_out), .phi1_in(phi1_in), .phi2_in(phi2_in)); jtag__tsinvBig tsinvBig_0(.Din(net_0), .en(sel), .enb(net_2), .Dout(TDO)); jtag__update_ctl update_c_0(.sel(sel), .update(update), .out(write), .phi2(phi2_in)); endmodule /* jtag__jtagScanControl */ module redFour__NMOS_X_5_667_Delay_100(g, d, s); input g; input d; input s; supply0 gnd; tranif1 #(100) NMOSf_0 (d, s, g); endmodule /* redFour__NMOS_X_5_667_Delay_100 */ module redFour__PMOS_X_2_833_Delay_100(g, d, s); input g; input d; input s; supply1 vdd; tranif0 #(100) PMOSf_0 (d, s, g); endmodule /* redFour__PMOS_X_2_833_Delay_100 */ module jtag__tsinv(Din, Dout, en, enb); input Din; input Dout; input en; input enb; supply1 vdd; supply0 gnd; wire net_1, net_2; redFour__NMOS_X_5_667_Delay_100 NMOS_0(.g(Din), .d(net_1), .s(gnd)); redFour__NMOS_X_5_667_Delay_100 NMOS_1(.g(en), .d(Dout), .s(net_1)); redFour__PMOS_X_2_833_Delay_100 PMOS_0(.g(Din), .d(net_2), .s(vdd)); redFour__PMOS_X_2_833_Delay_100 PMOS_1(.g(enb), .d(Dout), .s(net_2)); endmodule /* jtag__tsinv */ module jtag__mux2_phi2(Din0, Din1, phi2, sel, Dout); input Din0; input Din1; input phi2; input sel; output Dout; supply1 vdd; supply0 gnd; wire net_1, net_2, net_3, net_5, net_6; not (strong0, strong1) #(100) inv_0 (net_5, sel); not (strong0, strong1) #(100) inv_1 (net_1, net_6); not (strong0, strong1) #(100) inv_2 (Dout, net_3); scanChainFive__scanL scanL_0(.in(net_2), .out(net_3)); scanChainFive__scanP scanP_0(.in(phi2), .src(net_1), .drn(net_2)); jtag__tsinv tsinv_0(.Din(Din0), .Dout(net_6), .en(net_5), .enb(sel)); jtag__tsinv tsinv_1(.Din(Din1), .Dout(net_6), .en(sel), .enb(net_5)); endmodule /* jtag__mux2_phi2 */ module jtag__scanAmp1w1648(in, out); input in; output out; supply1 vdd; supply0 gnd; wire net_0; tranif1 nmos_0(gnd, net_0, in); tranif1 nmos_1(gnd, out, net_0); tranif0 pmos_0(net_0, vdd, in); tranif0 pmos_1(out, vdd, net_0); endmodule /* jtag__scanAmp1w1648 */ module redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1(ina, inb, out); input ina; input inb; output out; supply1 vdd; supply0 gnd; nand (strong0, strong1) #(100) nand2_0 (out, ina, inb); endmodule /* redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1 */ module redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1(ina, inb, out); input ina; input inb; output out; supply1 vdd; supply0 gnd; nand (strong0, strong1) #(100) nand2_0 (out, ina, inb); endmodule /* redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 */ module redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1(ina, inb, out); input ina; input inb; output out; supply1 vdd; supply0 gnd; nor (strong0, strong1) #(100) nor2_0 (out, ina, inb); endmodule /* redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 */ module orangeTSMC180nm__wire_R_26m_100_C_0_025f(a); input a; supply0 gnd; endmodule /* orangeTSMC180nm__wire_R_26m_100_C_0_025f */ module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100(a); input a; supply0 gnd; orangeTSMC180nm__wire_R_26m_100_C_0_025f wire_0(.a(a)); endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 */ module jtag__o2a(inAa, inAb, inOb, out); input inAa; input inAb; input inOb; output out; supply1 vdd; supply0 gnd; wire net_0; nor (strong0, strong1) #(100) nor2_0 (net_0, inAa, inAb); redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 nor2n_0(.ina(inOb), .inb(net_0), .out(out)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_0(.a(net_0)); endmodule /* jtag__o2a */ module orangeTSMC180nm__wire_R_26m_500_C_0_025f(a); input a; supply0 gnd; endmodule /* orangeTSMC180nm__wire_R_26m_500_C_0_025f */ module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500(a); input a; supply0 gnd; orangeTSMC180nm__wire_R_26m_500_C_0_025f wire_0(.a(a)); endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500 */ module jtag__slaveBit(din, phi2, slave); input din; input phi2; output slave; supply1 vdd; supply0 gnd; wire net_6, net_7; not (strong0, strong1) #(100) inv_0 (slave, net_7); scanChainFive__scanL scanL_0(.in(net_6), .out(net_7)); scanChainFive__scanP scanP_0(.in(phi2), .src(din), .drn(net_6)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500 wire180_0(.a(slave)); endmodule /* jtag__slaveBit */ module redFour__NMOS_X_1_667_Delay_100(g, d, s); input g; input d; input s; supply0 gnd; tranif1 #(100) NMOSf_0 (d, s, g); endmodule /* redFour__NMOS_X_1_667_Delay_100 */ module orangeTSMC180nm__wire_R_26m_750_C_0_025f(a); input a; supply0 gnd; endmodule /* orangeTSMC180nm__wire_R_26m_750_C_0_025f */ module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750(a); input a; supply0 gnd; orangeTSMC180nm__wire_R_26m_750_C_0_025f wire_0(.a(a)); endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 */ module orangeTSMC180nm__wire_R_26m_1000_C_0_025f(a); input a; supply0 gnd; endmodule /* orangeTSMC180nm__wire_R_26m_1000_C_0_025f */ module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000(a); input a; supply0 gnd; orangeTSMC180nm__wire_R_26m_1000_C_0_025f wire_0(.a(a)); endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 */ module jtag__stateBit(next, phi1, phi2, rst, master, slave, slaveBar); input next; input phi1; input phi2; input rst; output master; output slave; output slaveBar; supply1 vdd; supply0 gnd; wire net_12, net_13, net_14, net_17; redFour__NMOS_X_1_667_Delay_100 NMOS_0(.g(rst), .d(net_12), .s(gnd)); not (strong0, strong1) #(100) inv_0 (slave, slaveBar); not (strong0, strong1) #(100) inv_1 (slaveBar, net_17); not (strong0, strong1) #(100) inv_2 (master, net_13); scanChainFive__scanL scanL_0(.in(net_12), .out(net_13)); scanChainFive__scanL scanL_1(.in(net_14), .out(net_17)); scanChainFive__scanP scanP_0(.in(phi1), .src(next), .drn(net_12)); scanChainFive__scanP scanP_1(.in(phi2), .src(net_13), .drn(net_14)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 wire180_0(.a(master)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 wire180_1(.a(slave)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500 wire180_2(.a(slaveBar)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_3(.a(next)); endmodule /* jtag__stateBit */ module redFour__PMOS_X_1_5_Delay_100(g, d, s); input g; input d; input s; supply1 vdd; tranif0 #(100) PMOSf_0 (d, s, g); endmodule /* redFour__PMOS_X_1_5_Delay_100 */ module jtag__stateBitHI(next, phi1, phi2, rstb, master, slave, slaveBar); input next; input phi1; input phi2; input rstb; output master; output slave; output slaveBar; supply1 vdd; supply0 gnd; wire net_10, net_11, net_12, net_15; redFour__PMOS_X_1_5_Delay_100 PMOS_0(.g(rstb), .d(net_12), .s(vdd)); not (strong0, strong1) #(100) inv_0 (slave, slaveBar); not (strong0, strong1) #(100) inv_1 (slaveBar, net_15); not (strong0, strong1) #(100) inv_2 (master, net_10); scanChainFive__scanL scanL_0(.in(net_12), .out(net_10)); scanChainFive__scanL scanL_1(.in(net_11), .out(net_15)); scanChainFive__scanP scanP_0(.in(phi1), .src(next), .drn(net_12)); scanChainFive__scanP scanP_1(.in(phi2), .src(net_10), .drn(net_11)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 wire180_0(.a(slave)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500 wire180_1(.a(slaveBar)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_2(.a(next)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 wire180_3(.a(master)); endmodule /* jtag__stateBitHI */ module orangeTSMC180nm__wire_R_26m_675_C_0_025f(a); input a; supply0 gnd; endmodule /* orangeTSMC180nm__wire_R_26m_675_C_0_025f */ module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675(a); input a; supply0 gnd; orangeTSMC180nm__wire_R_26m_675_C_0_025f wire_0(.a(a)); endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675 */ module orangeTSMC180nm__wire_R_26m_1500_C_0_025f(a); input a; supply0 gnd; endmodule /* orangeTSMC180nm__wire_R_26m_1500_C_0_025f */ module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500(a); input a; supply0 gnd; orangeTSMC180nm__wire_R_26m_1500_C_0_025f wire_0(.a(a)); endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500 */ module jtag__tapCtlJKL(TMS, TRSTb, phi1, phi2, CapDR, CapIR, Idle, PauseDR, PauseIR, Reset, Reset_s, SelDR, SelIR, ShftDR, ShftIR, UpdDR, UpdIR, X1DR, X1IR, X2DR, X2IR); input TMS; input TRSTb; input phi1; input phi2; output CapDR; output CapIR; output Idle; output PauseDR; output PauseIR; output Reset; output Reset_s; output SelDR; output SelIR; output ShftDR; output ShftIR; output UpdDR; output UpdIR; output X1DR; output X1IR; output X2DR; output X2IR; supply1 vdd; supply0 gnd; wire net_0, net_2, net_4, net_6, net_12, net_13, net_14, net_15, net_16; wire net_17, net_18, net_19, net_20, net_22, net_23, net_24, net_25, net_26; wire net_28, net_29, net_31, net_32, net_34, net_40, net_43, net_44, net_48; wire net_50, net_52, net_54, net_55, net_56, net_58, net_59, net_60, net_64; wire net_67, net_68, net_70, net_71, net_72, net_74, net_75, net_76, net_79; wire net_80, rst, stateBit_1_slave, stateBit_5_slaveBar, stateBit_6_slaveBar; wire stateBit_9_slaveBar, stateBit_10_slaveBar, stateBit_11_slave; wire stateBit_12_slave; not (strong0, strong1) #(100) inv_0 (rst, TRSTb); not (strong0, strong1) #(100) inv_1 (net_24, net_12); redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1 nand2n_0(.ina(net_13), .inb(net_14), .out(net_0)); redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 nand2n_1(.ina(net_15), .inb(net_16), .out(net_4)); redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 nand2n_2(.ina(net_17), .inb(net_18), .out(net_2)); redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 nand2n_3(.ina(net_19), .inb(net_20), .out(net_6)); redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 nor2n_0(.ina(net_12), .inb(net_23), .out(net_22)); redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 nor2n_1(.ina(net_24), .inb(net_26), .out(net_25)); redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 nor2n_2(.ina(net_24), .inb(net_29), .out(net_28)); redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 nor2n_3(.ina(net_24), .inb(net_32), .out(net_31)); redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 nor2n_4(.ina(net_12), .inb(net_26), .out(net_34)); jtag__o2a o2a_0(.inAa(net_2), .inAb(net_43), .inOb(net_12), .out(net_40)); jtag__o2a o2a_1(.inAa(net_6), .inAb(net_0), .inOb(net_12), .out(net_44)); jtag__o2a o2a_2(.inAa(net_50), .inAb(net_0), .inOb(net_24), .out(net_48)); jtag__o2a o2a_3(.inAa(net_54), .inAb(net_55), .inOb(net_12), .out(net_52)); jtag__o2a o2a_4(.inAa(net_58), .inAb(net_59), .inOb(net_12), .out(net_56)); jtag__o2a o2a_5(.inAa(net_58), .inAb(net_43), .inOb(net_24), .out(net_60)); jtag__o2a o2a_6(.inAa(net_54), .inAb(net_67), .inOb(net_24), .out(net_64)); jtag__o2a o2a_7(.inAa(net_70), .inAb(net_71), .inOb(net_24), .out(net_68)); jtag__o2a o2a_8(.inAa(net_74), .inAb(net_75), .inOb(net_24), .out(net_72)); jtag__o2a o2a_9(.inAa(Reset_s), .inAb(net_79), .inOb(net_24), .out(net_76)); jtag__o2a o2a_10(.inAa(net_4), .inAb(net_67), .inOb(net_12), .out(net_80)); jtag__slaveBit slaveBit_0(.din(TMS), .phi2(phi2), .slave(net_12)); jtag__stateBit stateBit_0(.next(net_25), .phi1(phi1), .phi2(phi2), .rst(rst), .master(SelIR), .slave(net_79), .slaveBar(net_23)); jtag__stateBit stateBit_1(.next(net_48), .phi1(phi1), .phi2(phi2), .rst(rst), .master(SelDR), .slave(stateBit_1_slave), .slaveBar(net_26)); jtag__stateBit stateBit_2(.next(net_34), .phi1(phi1), .phi2(phi2), .rst(rst), .master(CapDR), .slave(net_75), .slaveBar(net_16)); jtag__stateBit stateBit_3(.next(net_22), .phi1(phi1), .phi2(phi2), .rst(rst), .master(CapIR), .slave(net_71), .slaveBar(net_18)); jtag__stateBit stateBit_4(.next(net_44), .phi1(phi1), .phi2(phi2), .rst(rst), .master(Idle), .slave(net_50), .slaveBar(net_20)); jtag__stateBit stateBit_5(.next(net_68), .phi1(phi1), .phi2(phi2), .rst(rst), .master(X1IR), .slave(net_58), .slaveBar(stateBit_5_slaveBar)); jtag__stateBit stateBit_6(.next(net_72), .phi1(phi1), .phi2(phi2), .rst(rst), .master(X1DR), .slave(net_54), .slaveBar(stateBit_6_slaveBar)); jtag__stateBit stateBit_7(.next(net_80), .phi1(phi1), .phi2(phi2), .rst(rst), .master(ShftDR), .slave(net_74), .slaveBar(net_15)); jtag__stateBit stateBit_8(.next(net_40), .phi1(phi1), .phi2(phi2), .rst(rst), .master(ShftIR), .slave(net_70), .slaveBar(net_17)); jtag__stateBit stateBit_9(.next(net_28), .phi1(phi1), .phi2(phi2), .rst(rst), .master(X2IR), .slave(net_43), .slaveBar(stateBit_9_slaveBar)); jtag__stateBit stateBit_10(.next(net_31), .phi1(phi1), .phi2(phi2), .rst(rst), .master(X2DR), .slave(net_67), .slaveBar(stateBit_10_slaveBar)); jtag__stateBit stateBit_11(.next(net_64), .phi1(phi1), .phi2(phi2), .rst(rst), .master(UpdDR), .slave(stateBit_11_slave), .slaveBar(net_14)); jtag__stateBit stateBit_12(.next(net_60), .phi1(phi1), .phi2(phi2), .rst(rst), .master(UpdIR), .slave(stateBit_12_slave), .slaveBar(net_13)); jtag__stateBit stateBit_13(.next(net_56), .phi1(phi1), .phi2(phi2), .rst(rst), .master(PauseIR), .slave(net_59), .slaveBar(net_29)); jtag__stateBit stateBit_14(.next(net_52), .phi1(phi1), .phi2(phi2), .rst(rst), .master(PauseDR), .slave(net_55), .slaveBar(net_32)); jtag__stateBitHI stateBit_15(.next(net_76), .phi1(phi1), .phi2(phi2), .rstb(TRSTb), .master(Reset), .slave(Reset_s), .slaveBar(net_19)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_0(.a(net_4)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_1(.a(net_2)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_2(.a(net_6)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675 wire180_3(.a(net_0)); orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500 wire180_4(.a(rst)); endmodule /* jtag__tapCtlJKL */ module jtag__jtagControl(TCK, TDI, TDIx, TMS, TRSTb, phi1_fb, phi2_fb, Cap, ExTest, SelBS, SelDR, Shft, TDOb, Upd, phi1, phi2); input TCK; input TDI; input TDIx; input TMS; input TRSTb; input phi1_fb; input phi2_fb; output Cap; output ExTest; output SelBS; output [12:0] SelDR; output Shft; output TDOb; output Upd; output phi1; output phi2; supply1 vdd; supply0 gnd; wire jtagScan_0_write, net_0, net_1, net_2, net_3, net_6, net_8, net_10; wire net_33, net_35, net_37, net_38, net_41, net_47, net_48, net_50, net_51; wire net_52, net_55, net_56, net_62, net_64, net_68, net_73, net_75, net_79; wire net_97, net_99, net_103, net_128, tapCtlJK_0_Idle, tapCtlJK_0_PauseDR; wire tapCtlJK_0_PauseIR, tapCtlJK_0_Reset, tapCtlJK_0_SelDR, tapCtlJK_0_SelIR; wire tapCtlJK_0_X1DR, tapCtlJK_0_X2DR, tapCtlJK_0_X2IR; wire [8:1] IR; wire [8:1] IRb; jtag__BR BR_0(.SDI(TDI), .phi1(net_68), .phi2(net_73), .read(net_99), .SDO(net_97)); jtag__IR IR_0(.SDI(TDI), .phi1(net_79), .phi2(net_75), .read(net_55), .reset(net_56), .write(net_103), .IR(IR[8:1]), .IRb(IRb[8:1]), .SDO(net_128)); jtag__IRdecode IRdecode_0(.IR(IR[4:1]), .IRb(IRb[4:1]), .Bypass(net_41), .ExTest(ExTest), .SamplePreload(net_47), .ScanPath(SelDR[12:0])); redFour__PMOSwk_X_0_222_Delay_100 PMOSwk_0(.g(gnd), .d(TDIx), .s(vdd)); jtag__clockGen clockGen_0(.clk(TCK), .phi1_fb(phi1_fb), .phi2_fb(phi2_fb), .phi1_out(net_10), .phi2_out(net_8)); not (strong0, strong1) #(100) inv_0 (net_0, net_3); not (strong0, strong1) #(100) inv_1 (SelBS, net_48); not (strong0, strong1) #(100) inv_2 (net_6, net_50); not (strong0, strong1) #(100) inv_3 (Cap, net_37); not (strong0, strong1) #(100) inv_4 (Shft, net_51); not (strong0, strong1) #(100) inv_5 (net_51, net_52); not (strong0, strong1) #(100) inv_6 (Upd, net_38); jtag__jtagIRControl jtagIRCo_0(.capture(net_62), .phi1_fb(net_79), .phi1_in(phi1), .phi2_fb(net_75), .phi2_in(phi2), .shift(net_2), .update(net_64), .phi1_out(net_79), .phi2_out(net_75), .read(net_55), .write(net_103)); jtag__jtagScanControl jtagScan_0(.TDI(net_97), .capture(Cap), .phi1_fb(net_68), .phi1_in(phi1), .phi2_fb(net_73), .phi2_in(phi2), .sel(net_41), .shift(Shft), .update(gnd), .TDO(TDIx), .phi1_out(net_68), .phi2_out(net_73), .read(net_99), .write(jtagScan_0_write)); jtag__mux2_phi2 mux2_phi_0(.Din0(TDIx), .Din1(net_128), .phi2(phi2), .sel(net_0), .Dout(net_50)); nand (strong0, strong1) #(100) nand2_0 (net_37, IR[8], net_35); nand (strong0, strong1) #(100) nand2_1 (net_38, IR[7], net_33); nor (strong0, strong1) #(100) nor2_0 (net_3, net_1, net_2); nor (strong0, strong1) #(100) nor2_1 (net_48, net_47, ExTest); jtag__scanAmp1w1648 scanAmp1_0(.in(net_6), .out(TDOb)); jtag__scanAmp1w1648 scanAmp1_1(.in(net_8), .out(phi2)); jtag__scanAmp1w1648 scanAmp1_2(.in(net_10), .out(phi1)); jtag__tapCtlJKL tapCtlJK_0(.TMS(TMS), .TRSTb(TRSTb), .phi1(phi1), .phi2(phi2), .CapDR(net_35), .CapIR(net_62), .Idle(tapCtlJK_0_Idle), .PauseDR(tapCtlJK_0_PauseDR), .PauseIR(tapCtlJK_0_PauseIR), .Reset(tapCtlJK_0_Reset), .Reset_s(net_56), .SelDR(tapCtlJK_0_SelDR), .SelIR(tapCtlJK_0_SelIR), .ShftDR(net_52), .ShftIR(net_2), .UpdDR(net_33), .UpdIR(net_64), .X1DR(tapCtlJK_0_X1DR), .X1IR(net_1), .X2DR(tapCtlJK_0_X2DR), .X2IR(tapCtlJK_0_X2IR)); endmodule /* jtag__jtagControl */ module jtag__JTAGamp(leaf, root); input [8:1] leaf; input [5:1] root; supply1 vdd; supply0 gnd; jtag__scanAmp1w1648 toLeaf_5_(.in(root[5]), .out(leaf[5])); jtag__scanAmp1w1648 toLeaf_4_(.in(root[4]), .out(leaf[4])); jtag__scanAmp1w1648 toLeaf_3_(.in(root[3]), .out(leaf[3])); jtag__scanAmp1w1648 toLeaf_2_(.in(root[2]), .out(leaf[2])); jtag__scanAmp1w1648 toLeaf_1_(.in(root[1]), .out(leaf[1])); endmodule /* jtag__JTAGamp */ module jtag__jtagScanCtlWBuf(TDI, cap, phi1, phi2, sel, shift, upd, TDO, leaf); input TDI; input cap; input phi1; input phi2; input sel; input shift; input upd; output TDO; input [8:1] leaf; supply1 vdd; supply0 gnd; wire [5:2] a; jtag__JTAGamp JTAGamp_0(.leaf(leaf[8:1]), .root({a[5], a[4], a[3], a[2], TDI})); jtag__jtagScanControl jtagScan_0(.TDI(leaf[8]), .capture(cap), .phi1_fb(leaf[6]), .phi1_in(phi1), .phi2_fb(leaf[7]), .phi2_in(phi2), .sel(sel), .shift(shift), .update(upd), .TDO(TDO), .phi1_out(a[3]), .phi2_out(a[2]), .read(a[5]), .write(a[4])); endmodule /* jtag__jtagScanCtlWBuf */ module jtag__jtagScanCtlGroup(TDI, capture, phi1_in, phi2_in, selBS, sel, shift, update, TDO, BS, leaf0, leaf1, leaf2, leaf3, leaf4, leaf5, leaf6, leaf7, leaf8, leaf9, leaf10, leaf11, leaf12); input TDI; input capture; input phi1_in; input phi2_in; input selBS; input [12:0] sel; input shift; input update; output TDO; input [8:1] BS; input [8:1] leaf0; input [8:1] leaf1; input [8:1] leaf2; input [8:1] leaf3; input [8:1] leaf4; input [8:1] leaf5; input [8:1] leaf6; input [8:1] leaf7; input [8:1] leaf8; input [8:1] leaf9; input [8:1] leaf10; input [8:1] leaf11; input [8:1] leaf12; supply1 vdd; supply0 gnd; jtag__jtagScanCtlWBuf jtagScan_1(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(sel[0]), .shift(shift), .upd(update), .TDO(TDO), .leaf(leaf0[8:1])); jtag__jtagScanCtlWBuf jtagScan_2(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(sel[10]), .shift(shift), .upd(update), .TDO(TDO), .leaf(leaf10[8:1])); jtag__jtagScanCtlWBuf jtagScan_3(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(sel[12]), .shift(shift), .upd(update), .TDO(TDO), .leaf(leaf12[8:1])); jtag__jtagScanCtlWBuf jtagScan_4(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(sel[11]), .shift(shift), .upd(update), .TDO(TDO), .leaf(leaf11[8:1])); jtag__jtagScanCtlWBuf jtagScan_5(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(sel[9]), .shift(shift), .upd(update), .TDO(TDO), .leaf(leaf9[8:1])); jtag__jtagScanCtlWBuf jtagScan_6(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(sel[8]), .shift(shift), .upd(update), .TDO(TDO), .leaf(leaf8[8:1])); jtag__jtagScanCtlWBuf jtagScan_7(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(sel[6]), .shift(shift), .upd(update), .TDO(TDO), .leaf(leaf6[8:1])); jtag__jtagScanCtlWBuf jtagScan_8(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(sel[5]), .shift(shift), .upd(update), .TDO(TDO), .leaf(leaf5[8:1])); jtag__jtagScanCtlWBuf jtagScan_9(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(sel[4]), .shift(shift), .upd(update), .TDO(TDO), .leaf(leaf4[8:1])); jtag__jtagScanCtlWBuf jtagScan_10(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(sel[3]), .shift(shift), .upd(update), .TDO(TDO), .leaf(leaf3[8:1])); jtag__jtagScanCtlWBuf jtagScan_11(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(sel[2]), .shift(shift), .upd(update), .TDO(TDO), .leaf(leaf2[8:1])); jtag__jtagScanCtlWBuf jtagScan_12(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(sel[1]), .shift(shift), .upd(update), .TDO(TDO), .leaf(leaf1[8:1])); jtag__jtagScanCtlWBuf jtagScan_13(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(sel[7]), .shift(shift), .upd(update), .TDO(TDO), .leaf(leaf7[8:1])); jtag__jtagScanCtlWBuf jtagScan_16(.TDI(TDI), .cap(capture), .phi1(phi1_in), .phi2(phi2_in), .sel(selBS), .shift(shift), .upd(update), .TDO(TDO), .leaf(BS[8:1])); endmodule /* jtag__jtagScanCtlGroup */ module jtag__jtagCentral_LEIGNORE_1(TCK, TDI, TMS, TRSTb, ExTest, TDOb, BS, leaf0, leaf1, leaf2, leaf3, leaf4, leaf5, leaf6, leaf7, leaf8, leaf9, leaf10, leaf11, leaf12); input TCK; input TDI; input TMS; input TRSTb; output ExTest; output TDOb; input [8:1] BS; input [8:1] leaf0; input [8:1] leaf1; input [8:1] leaf2; input [8:1] leaf3; input [8:1] leaf4; input [8:1] leaf5; input [8:1] leaf6; input [8:1] leaf7; input [8:1] leaf8; input [8:1] leaf9; input [8:1] leaf10; input [8:1] leaf11; input [8:1] leaf12; supply1 vdd; supply0 gnd; wire net_10, net_14, net_15, net_17, net_24, net_25, net_50; wire [0:12] net_6; jtag__jtagControl jtagCont_0(.TCK(TCK), .TDI(TDI), .TDIx(net_15), .TMS(TMS), .TRSTb(TRSTb), .phi1_fb(net_24), .phi2_fb(net_10), .Cap(net_25), .ExTest(ExTest), .SelBS(net_50), .SelDR({net_6[0], net_6[1], net_6[2], net_6[3], net_6[4], net_6[5], net_6[6], net_6[7], net_6[8], net_6[9], net_6[10], net_6[11], net_6[12]}), .Shft(net_17), .TDOb(TDOb), .Upd(net_14), .phi1(net_24), .phi2(net_10)); jtag__jtagScanCtlGroup jtagScan_0(.TDI(TDI), .capture(net_25), .phi1_in(net_24), .phi2_in(net_10), .selBS(net_50), .sel({net_6[0], net_6[1], net_6[2], net_6[3], net_6[4], net_6[5], net_6[6], net_6[7], net_6[8], net_6[9], net_6[10], net_6[11], net_6[12]}), .shift(net_17), .update(net_14), .TDO(net_15), .BS(BS[8:1]), .leaf0(leaf0[8:1]), .leaf1(leaf1[8:1]), .leaf2(leaf2[8:1]), .leaf3(leaf3[8:1]), .leaf4(leaf4[8:1]), .leaf5(leaf5[8:1]), .leaf6(leaf6[8:1]), .leaf7(leaf7[8:1]), .leaf8(leaf8[8:1]), .leaf9(leaf9[8:1]), .leaf10(leaf10[8:1]), .leaf11(leaf11[8:1]), .leaf12(leaf12[8:1])); endmodule /* jtag__jtagCentral_LEIGNORE_1 */ module scanFansFour__jtag_endcap(jtag); input [8:4] jtag; endmodule /* scanFansFour__jtag_endcap */ module testCell(TCK, TDI, TMS, TRSTb, TDOb); input TCK; input TDI; input TMS; input TRSTb; output TDOb; supply1 vdd; supply0 gnd; wire jtagCent_0_ExTest; wire [4:0] net_5; wire [4:0] net_6; wire [4:0] net_7; wire [4:0] net_8; wire [4:0] net_9; wire [4:0] net_10; wire [4:0] net_11; wire [4:0] net_12; wire [4:0] net_13; wire [4:0] net_14; wire [4:0] net_15; wire [4:0] net_16; wire [4:0] net_17; wire [4:0] net_18; jtag__jtagCentral_LEIGNORE_1 jtagCent_0(.TCK(TCK), .TDI(TDI), .TMS(TMS), .TRSTb(TRSTb), .ExTest(jtagCent_0_ExTest), .TDOb(TDOb), .BS({net_6[0], net_6[1], net_6[2], net_6[3], net_6[4], net_6[2], net_6[1], net_6[0]}), .leaf0({net_7[0], net_7[1], net_7[2], net_7[3], net_7[4], net_7[2], net_7[1], net_7[0]}), .leaf1({net_18[0], net_18[1], net_18[2], net_18[3], net_18[4], net_18[2], net_18[1], net_18[0]}), .leaf2({net_17[0], net_17[1], net_17[2], net_17[3], net_17[4], net_17[2], net_17[1], net_17[0]}), .leaf3({net_16[0], net_16[1], net_16[2], net_16[3], net_16[4], net_16[2], net_16[1], net_16[0]}), .leaf4({net_15[0], net_15[1], net_15[2], net_15[3], net_15[4], net_15[2], net_15[1], net_15[0]}), .leaf5({net_14[0], net_14[1], net_14[2], net_14[3], net_14[4], net_14[2], net_14[1], net_14[0]}), .leaf6({net_13[0], net_13[1], net_13[2], net_13[3], net_13[4], net_13[2], net_13[1], net_13[0]}), .leaf7({net_12[0], net_12[1], net_12[2], net_12[3], net_12[4], net_12[2], net_12[1], net_12[0]}), .leaf8({net_11[0], net_11[1], net_11[2], net_11[3], net_11[4], net_11[2], net_11[1], net_11[0]}), .leaf9({net_10[0], net_10[1], net_10[2], net_10[3], net_10[4], net_10[2], net_10[1], net_10[0]}), .leaf10({net_9[0], net_9[1], net_9[2], net_9[3], net_9[4], net_9[2], net_9[1], net_9[0]}), .leaf11({net_8[0], net_8[1], net_8[2], net_8[3], net_8[4], net_8[2], net_8[1], net_8[0]}), .leaf12({net_5[0], net_5[1], net_5[2], net_5[3], net_5[4], net_5[2], net_5[1], net_5[0]})); scanFansFour__jtag_endcap jtag_end_0(.jtag({net_5[0], net_5[1], net_5[2], net_5[4], net_5[3]})); scanFansFour__jtag_endcap jtag_end_1(.jtag({net_8[0], net_8[1], net_8[2], net_8[4], net_8[3]})); scanFansFour__jtag_endcap jtag_end_2(.jtag({net_9[0], net_9[1], net_9[2], net_9[4], net_9[3]})); scanFansFour__jtag_endcap jtag_end_3(.jtag({net_10[0], net_10[1], net_10[2], net_10[4], net_10[3]})); scanFansFour__jtag_endcap jtag_end_4(.jtag({net_11[0], net_11[1], net_11[2], net_11[4], net_11[3]})); scanFansFour__jtag_endcap jtag_end_5(.jtag({net_12[0], net_12[1], net_12[2], net_12[4], net_12[3]})); scanFansFour__jtag_endcap jtag_end_6(.jtag({net_13[0], net_13[1], net_13[2], net_13[4], net_13[3]})); scanFansFour__jtag_endcap jtag_end_7(.jtag({net_14[0], net_14[1], net_14[2], net_14[4], net_14[3]})); scanFansFour__jtag_endcap jtag_end_8(.jtag({net_15[0], net_15[1], net_15[2], net_15[4], net_15[3]})); scanFansFour__jtag_endcap jtag_end_9(.jtag({net_16[0], net_16[1], net_16[2], net_16[4], net_16[3]})); scanFansFour__jtag_endcap jtag_end_10(.jtag({net_17[0], net_17[1], net_17[2], net_17[4], net_17[3]})); scanFansFour__jtag_endcap jtag_end_11(.jtag({net_18[0], net_18[1], net_18[2], net_18[4], net_18[3]})); scanFansFour__jtag_endcap jtag_end_12(.jtag({net_7[0], net_7[1], net_7[2], net_7[4], net_7[3]})); scanFansFour__jtag_endcap jtag_end_13(.jtag({net_6[0], net_6[1], net_6[2], net_6[4], net_6[3]})); endmodule /* testCell */

`timescale 1ns/1ps `include "sata_defines.v" module tb_cocotb ( //Parameters //Registers/Wires input rst, //reset input clk, output linkup, //link is finished output sata_ready, output sata_busy, //input write_data_stb, //input read_data_stb, input [7:0] hard_drive_command, input execute_command_stb, input command_layer_reset, input [15:0] sector_count, input [47:0] sector_address, output d2h_interrupt, output d2h_notification, output [3:0] d2h_port_mult, output [7:0] d2h_device, output [47:0] d2h_lba, output [15:0] d2h_sector_count, output [7:0] d2h_status, output [7:0] d2h_error, input u2h_write_enable, output u2h_write_finished, input [23:0] u2h_write_count, input h2u_read_enable, output [23:0] h2u_read_total_count, output h2u_read_error, output h2u_read_busy, output u2h_read_error, output transport_layer_ready, output link_layer_ready, output phy_ready, input prim_scrambler_en, input data_scrambler_en, //Data Interface output tx_set_elec_idle, output rx_is_elec_idle, output hd_ready, input platform_ready, //Debug input hold, input single_rdwr ); reg [31:0] test_id = 0; wire [31:0] tx_dout; wire tx_is_k; wire tx_comm_reset; wire tx_comm_wake; wire tx_elec_idle; wire [31:0] rx_din; wire [3:0] rx_is_k; wire rx_elec_idle; wire comm_init_detect; wire comm_wake_detect; reg r_rst; reg r_write_data_stb; reg r_read_data_stb; reg r_command_layer_reset; reg [15:0] r_sector_count; reg [47:0] r_sector_address; reg r_prim_scrambler_en; reg r_data_scrambler_en; reg r_platform_ready; reg r_dout_count; reg r_hold; reg r_u2h_write_enable; reg [23:0] r_u2h_write_count; reg r_h2u_read_enable; reg [7:0] r_hard_drive_command; reg r_execute_command_stb; wire hd_read_from_host; wire [31:0] hd_data_from_host; wire hd_write_to_host; wire [31:0] hd_data_to_host; wire [31:0] user_dout; wire user_dout_ready; wire user_dout_activate; wire user_dout_stb; wire [23:0] user_dout_size; wire [31:0] user_din; wire user_din_stb; wire [1:0] user_din_ready; wire [1:0] user_din_activate; wire [23:0] user_din_size; wire dma_activate_stb; wire d2h_reg_stb; wire pio_setup_stb; wire d2h_data_stb; wire dma_setup_stb; wire set_device_bits_stb; wire [7:0] d2h_fis; wire i_rx_byte_is_aligned; //There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered always @ (*) r_rst = rst; //always @ (*) r_write_data_stb = write_data_stb; //always @ (*) r_read_data_stb = read_data_stb; always @ (*) r_command_layer_reset= command_layer_reset; always @ (*) r_sector_count = sector_count; always @ (*) r_sector_address = sector_address; always @ (*) r_prim_scrambler_en = prim_scrambler_en; always @ (*) r_data_scrambler_en = data_scrambler_en; always @ (*) r_platform_ready = platform_ready; always @ (*) r_hold = hold; always @ (*) r_u2h_write_enable = u2h_write_enable; always @ (*) r_u2h_write_count = u2h_write_count; always @ (*) r_h2u_read_enable = h2u_read_enable; always @ (*) r_hard_drive_command = hard_drive_command; always @ (*) r_execute_command_stb= execute_command_stb; //Submodules //User Generated Test Data test_in user_2_hd_generator( .clk (clk ), .rst (rst ), .enable (r_u2h_write_enable ), .finished (u2h_write_finished ), .write_count (r_u2h_write_count ), .ready (user_din_ready ), .activate (user_din_activate ), .fifo_data (user_din ), .fifo_size (user_din_size ), .strobe (user_din_stb ) ); //Module to process data from Hard Drive to User test_out hd_2_user_reader( .clk (clk ), .rst (rst ), .busy (h2u_read_busy ), .enable (r_h2u_read_enable ), .error (h2u_read_error ), .total_count (h2u_read_total_count ), .ready (user_dout_ready ), .activate (user_dout_activate ), .size (user_dout_size ), .data (user_dout ), .strobe (user_dout_stb ) ); //hd data reader core hd_data_reader user_2_hd_reader( .clk (clk ), .rst (rst ), .enable (r_u2h_write_enable ), .error (u2h_read_error ), .hd_read_from_host (hd_read_from_host ), .hd_data_from_host (hd_data_from_host ) ); //hd data writer core hd_data_writer hd_2_user_generator( .clk (clk ), .rst (rst ), .enable (r_h2u_read_enable ), .data (hd_data_to_host ), .strobe (hd_write_to_host ) ); sata_stack ss ( .rst (r_rst ), //reset .clk (clk ), //clock used to run the stack .command_layer_reset (r_command_layer_reset), .platform_ready (platform_ready ), //the underlying physical platform is .platform_error ( ), .linkup (linkup ), //link is finished .sata_ready (sata_ready ), .sata_busy (sata_busy ), .send_sync_escape (1'b0 ), .hard_drive_error ( ), .pio_data_ready ( ), //Host to Device Control // .write_data_stb (r_write_data_stb ), // .read_data_stb (r_read_data_stb ), .hard_drive_command (r_hard_drive_command ), .execute_command_stb (r_execute_command_stb), .user_features (16'h0000 ), .sector_count (r_sector_count ), .sector_address (r_sector_address ), .dma_activate_stb (dma_activate_stb ), .d2h_reg_stb (d2h_reg_stb ), .pio_setup_stb (pio_setup_stb ), .d2h_data_stb (d2h_data_stb ), .dma_setup_stb (dma_setup_stb ), .set_device_bits_stb (set_device_bits_stb ), .d2h_fis (d2h_fis ), .d2h_interrupt (d2h_interrupt ), .d2h_notification (d2h_notification ), .d2h_port_mult (d2h_port_mult ), .d2h_device (d2h_device ), .d2h_lba (d2h_lba ), .d2h_sector_count (d2h_sector_count ), .d2h_status (d2h_status ), .d2h_error (d2h_error ), //Data from host to the hard drive path .data_in_clk (clk ), .data_in_clk_valid (1'b1 ), .user_din (user_din ), //User Data Here .user_din_stb (user_din_stb ), //Strobe Each Data word in here .user_din_ready (user_din_ready ), //Using PPFIFO Ready Signal .user_din_activate (user_din_activate ), //Activate PPFIFO Channel .user_din_size (user_din_size ), //Find the size of the data to write to the device //Data from hard drive to host path .data_out_clk (clk ), .data_out_clk_valid (1'b1 ), .user_dout (user_dout ), .user_dout_ready (user_dout_ready ), .user_dout_activate (user_dout_activate ), .user_dout_stb (user_dout_stb ), .user_dout_size (user_dout_size ), .transport_layer_ready (transport_layer_ready), .link_layer_ready (link_layer_ready ), .phy_ready (phy_ready ), .phy_error (1'b0 ), .tx_dout (tx_dout ), .tx_is_k (tx_is_k ), .tx_comm_reset (tx_comm_reset ), .tx_comm_wake (tx_comm_wake ), .tx_elec_idle (tx_elec_idle ), .tx_oob_complete (1'b1 ), .rx_din (rx_din ), .rx_is_k (rx_is_k ), .rx_elec_idle (rx_elec_idle ), .rx_byte_is_aligned (i_rx_byte_is_aligned ), .comm_init_detect (comm_init_detect ), .comm_wake_detect (comm_wake_detect ), //.prim_scrambler_en (r_prim_scrambler_en ), .prim_scrambler_en (1'b1 ), //.data_scrambler_en (r_data_scrambler_en ) .data_scrambler_en (1'b1 ) ); faux_sata_hd fshd ( .rst (r_rst ), .clk (clk ), .tx_dout (rx_din ), .tx_is_k (rx_is_k ), .rx_din (tx_dout ), .rx_is_k ({3'b000, tx_is_k} ), .rx_is_elec_idle (tx_elec_idle ), .rx_byte_is_aligned (i_rx_byte_is_aligned ), .comm_reset_detect (tx_comm_reset ), .comm_wake_detect (tx_comm_wake ), .tx_comm_reset (comm_init_detect ), .tx_comm_wake (comm_wake_detect ), .hd_ready (hd_ready ), // .phy_ready (phy_ready ), //.dbg_data_scrambler_en (r_data_scrambler_en ), .dbg_data_scrambler_en (1'b1 ), .dbg_hold (r_hold ), .dbg_ll_write_start (1'b0 ), .dbg_ll_write_data (32'h0 ), .dbg_ll_write_size (0 ), .dbg_ll_write_hold (1'b0 ), .dbg_ll_write_abort (1'b0 ), .dbg_ll_read_ready (1'b0 ), .dbg_t_en (1'b0 ), .dbg_send_reg_stb (1'b0 ), .dbg_send_dma_act_stb (1'b0 ), .dbg_send_data_stb (1'b0 ), .dbg_send_pio_stb (1'b0 ), .dbg_send_dev_bits_stb (1'b0 ), .dbg_pio_transfer_count(16'h0000 ), .dbg_pio_direction (1'b0 ), .dbg_pio_e_status (8'h00 ), .dbg_d2h_interrupt (1'b0 ), .dbg_d2h_notification (1'b0 ), .dbg_d2h_status (8'b0 ), .dbg_d2h_error (8'b0 ), .dbg_d2h_port_mult (4'b0000 ), .dbg_d2h_device (8'h00 ), .dbg_d2h_lba (48'h000000000000 ), .dbg_d2h_sector_count (16'h0000 ), .dbg_cl_if_data (32'b0 ), .dbg_cl_if_ready (1'b0 ), .dbg_cl_if_size (24'h0 ), .dbg_cl_of_ready (2'b0 ), .dbg_cl_of_size (24'h0 ), .hd_read_from_host (hd_read_from_host ), .hd_data_from_host (hd_data_from_host ), .hd_write_to_host (hd_write_to_host ), .hd_data_to_host (hd_data_to_host ) ); //Asynchronous Logic //Synchronous Logic //Simulation Control initial begin $dumpfile ("design.vcd"); $dumpvars(0, tb_cocotb); end endmodule

/* Copyright (c) 2014-2020 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ // Language: Verilog 2001 `timescale 1ns / 1ps /* * AXI4-Stream ethernet frame receiver (AXI in, Ethernet frame out) */ module eth_axis_rx # ( // Width of AXI stream interfaces in bits parameter DATA_WIDTH = 8, // Propagate tkeep signal // If disabled, tkeep assumed to be 1'b1 parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) parameter KEEP_WIDTH = (DATA_WIDTH/8) ) ( input wire clk, input wire rst, /* * AXI input */ input wire [DATA_WIDTH-1:0] s_axis_tdata, input wire [KEEP_WIDTH-1:0] s_axis_tkeep, input wire s_axis_tvalid, output wire s_axis_tready, input wire s_axis_tlast, input wire s_axis_tuser, /* * Ethernet frame output */ output wire m_eth_hdr_valid, input wire m_eth_hdr_ready, output wire [47:0] m_eth_dest_mac, output wire [47:0] m_eth_src_mac, output wire [15:0] m_eth_type, output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata, output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep, output wire m_eth_payload_axis_tvalid, input wire m_eth_payload_axis_tready, output wire m_eth_payload_axis_tlast, output wire m_eth_payload_axis_tuser, /* * Status signals */ output wire busy, output wire error_header_early_termination ); parameter CYCLE_COUNT = (14+KEEP_WIDTH-1)/KEEP_WIDTH; parameter PTR_WIDTH = $clog2(CYCLE_COUNT); parameter OFFSET = 14 % KEEP_WIDTH; // bus width assertions initial begin if (KEEP_WIDTH * 8 != DATA_WIDTH) begin $error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)"); $finish; end end /* Ethernet frame Field Length Destination MAC address 6 octets Source MAC address 6 octets Ethertype 2 octets This module receives an Ethernet frame on an AXI stream interface, decodes and strips the headers, then produces the header fields in parallel along with the payload in a separate AXI stream. */ reg read_eth_header_reg = 1'b1, read_eth_header_next; reg read_eth_payload_reg = 1'b0, read_eth_payload_next; reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next; reg flush_save; reg transfer_in_save; reg s_axis_tready_reg = 1'b0, s_axis_tready_next; reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next; reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next; reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next; reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next; reg busy_reg = 1'b0; reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next; reg [DATA_WIDTH-1:0] save_axis_tdata_reg = 64'd0; reg [KEEP_WIDTH-1:0] save_axis_tkeep_reg = 8'd0; reg save_axis_tlast_reg = 1'b0; reg save_axis_tuser_reg = 1'b0; reg [DATA_WIDTH-1:0] shift_axis_tdata; reg [KEEP_WIDTH-1:0] shift_axis_tkeep; reg shift_axis_tvalid; reg shift_axis_tlast; reg shift_axis_tuser; reg shift_axis_input_tready; reg shift_axis_extra_cycle_reg = 1'b0; // internal datapath reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int; reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int; reg m_eth_payload_axis_tvalid_int; reg m_eth_payload_axis_tready_int_reg = 1'b0; reg m_eth_payload_axis_tlast_int; reg m_eth_payload_axis_tuser_int; wire m_eth_payload_axis_tready_int_early; assign s_axis_tready = s_axis_tready_reg; assign m_eth_hdr_valid = m_eth_hdr_valid_reg; assign m_eth_dest_mac = m_eth_dest_mac_reg; assign m_eth_src_mac = m_eth_src_mac_reg; assign m_eth_type = m_eth_type_reg; assign busy = busy_reg; assign error_header_early_termination = error_header_early_termination_reg; always @* begin if (OFFSET == 0) begin // passthrough if no overlap shift_axis_tdata = s_axis_tdata; shift_axis_tkeep = s_axis_tkeep; shift_axis_tvalid = s_axis_tvalid; shift_axis_tlast = s_axis_tlast; shift_axis_tuser = s_axis_tuser; shift_axis_input_tready = 1'b1; end else if (shift_axis_extra_cycle_reg) begin shift_axis_tdata = {s_axis_tdata, save_axis_tdata_reg} >> (OFFSET*8); shift_axis_tkeep = {{KEEP_WIDTH{1'b0}}, save_axis_tkeep_reg} >> OFFSET; shift_axis_tvalid = 1'b1; shift_axis_tlast = save_axis_tlast_reg; shift_axis_tuser = save_axis_tuser_reg; shift_axis_input_tready = flush_save; end else begin shift_axis_tdata = {s_axis_tdata, save_axis_tdata_reg} >> (OFFSET*8); shift_axis_tkeep = {s_axis_tkeep, save_axis_tkeep_reg} >> OFFSET; shift_axis_tvalid = s_axis_tvalid; shift_axis_tlast = (s_axis_tlast && ((s_axis_tkeep & ({KEEP_WIDTH{1'b1}} << OFFSET)) == 0)); shift_axis_tuser = (s_axis_tuser && ((s_axis_tkeep & ({KEEP_WIDTH{1'b1}} << OFFSET)) == 0)); shift_axis_input_tready = !(s_axis_tlast && s_axis_tready && s_axis_tvalid); end end always @* begin read_eth_header_next = read_eth_header_reg; read_eth_payload_next = read_eth_payload_reg; ptr_next = ptr_reg; s_axis_tready_next = m_eth_payload_axis_tready_int_early && shift_axis_input_tready && (!m_eth_hdr_valid || m_eth_hdr_ready); flush_save = 1'b0; transfer_in_save = 1'b0; m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready; m_eth_dest_mac_next = m_eth_dest_mac_reg; m_eth_src_mac_next = m_eth_src_mac_reg; m_eth_type_next = m_eth_type_reg; error_header_early_termination_next = 1'b0; m_eth_payload_axis_tdata_int = shift_axis_tdata; m_eth_payload_axis_tkeep_int = shift_axis_tkeep; m_eth_payload_axis_tvalid_int = 1'b0; m_eth_payload_axis_tlast_int = shift_axis_tlast; m_eth_payload_axis_tuser_int = shift_axis_tuser; if ((s_axis_tready && s_axis_tvalid) || (m_eth_payload_axis_tready_int_reg && shift_axis_extra_cycle_reg)) begin transfer_in_save = 1'b1; if (read_eth_header_reg) begin // word transfer in - store it ptr_next = ptr_reg + 1; `define _HEADER_FIELD_(offset, field) \ if (ptr_reg == offset/KEEP_WIDTH && (!KEEP_ENABLE || s_axis_tkeep[offset%KEEP_WIDTH])) begin \ field = s_axis_tdata[(offset%KEEP_WIDTH)*8 +: 8]; \ end `_HEADER_FIELD_(0, m_eth_dest_mac_next[5*8 +: 8]) `_HEADER_FIELD_(1, m_eth_dest_mac_next[4*8 +: 8]) `_HEADER_FIELD_(2, m_eth_dest_mac_next[3*8 +: 8]) `_HEADER_FIELD_(3, m_eth_dest_mac_next[2*8 +: 8]) `_HEADER_FIELD_(4, m_eth_dest_mac_next[1*8 +: 8]) `_HEADER_FIELD_(5, m_eth_dest_mac_next[0*8 +: 8]) `_HEADER_FIELD_(6, m_eth_src_mac_next[5*8 +: 8]) `_HEADER_FIELD_(7, m_eth_src_mac_next[4*8 +: 8]) `_HEADER_FIELD_(8, m_eth_src_mac_next[3*8 +: 8]) `_HEADER_FIELD_(9, m_eth_src_mac_next[2*8 +: 8]) `_HEADER_FIELD_(10, m_eth_src_mac_next[1*8 +: 8]) `_HEADER_FIELD_(11, m_eth_src_mac_next[0*8 +: 8]) `_HEADER_FIELD_(12, m_eth_type_next[1*8 +: 8]) `_HEADER_FIELD_(13, m_eth_type_next[0*8 +: 8]) if (ptr_reg == 13/KEEP_WIDTH && (!KEEP_ENABLE || s_axis_tkeep[13%KEEP_WIDTH])) begin if (!shift_axis_tlast) begin m_eth_hdr_valid_next = 1'b1; read_eth_header_next = 1'b0; read_eth_payload_next = 1'b1; end end `undef _HEADER_FIELD_ end if (read_eth_payload_reg) begin // transfer payload m_eth_payload_axis_tdata_int = shift_axis_tdata; m_eth_payload_axis_tkeep_int = shift_axis_tkeep; m_eth_payload_axis_tvalid_int = 1'b1; m_eth_payload_axis_tlast_int = shift_axis_tlast; m_eth_payload_axis_tuser_int = shift_axis_tuser; end if (shift_axis_tlast) begin if (read_eth_header_next) begin // don't have the whole header error_header_early_termination_next = 1'b1; end flush_save = 1'b1; ptr_next = 1'b0; read_eth_header_next = 1'b1; read_eth_payload_next = 1'b0; end end end always @(posedge clk) begin read_eth_header_reg <= read_eth_header_next; read_eth_payload_reg <= read_eth_payload_next; ptr_reg <= ptr_next; s_axis_tready_reg <= s_axis_tready_next; m_eth_hdr_valid_reg <= m_eth_hdr_valid_next; m_eth_dest_mac_reg <= m_eth_dest_mac_next; m_eth_src_mac_reg <= m_eth_src_mac_next; m_eth_type_reg <= m_eth_type_next; error_header_early_termination_reg <= error_header_early_termination_next; busy_reg <= (read_eth_payload_next || ptr_next != 0); if (transfer_in_save) begin save_axis_tdata_reg <= s_axis_tdata; save_axis_tkeep_reg <= s_axis_tkeep; save_axis_tuser_reg <= s_axis_tuser; end if (flush_save) begin save_axis_tlast_reg <= 1'b0; shift_axis_extra_cycle_reg <= 1'b0; end else if (transfer_in_save) begin save_axis_tlast_reg <= s_axis_tlast; shift_axis_extra_cycle_reg <= OFFSET ? s_axis_tlast && ((s_axis_tkeep & ({KEEP_WIDTH{1'b1}} << OFFSET)) != 0) : 1'b0; end if (rst) begin read_eth_header_reg <= 1'b1; read_eth_payload_reg <= 1'b0; ptr_reg <= 0; s_axis_tready_reg <= 1'b0; m_eth_hdr_valid_reg <= 1'b0; save_axis_tlast_reg <= 1'b0; shift_axis_extra_cycle_reg <= 1'b0; busy_reg <= 1'b0; error_header_early_termination_reg <= 1'b0; end end // output datapath logic reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next; reg m_eth_payload_axis_tlast_reg = 1'b0; reg m_eth_payload_axis_tuser_reg = 1'b0; reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next; reg temp_m_eth_payload_axis_tlast_reg = 1'b0; reg temp_m_eth_payload_axis_tuser_reg = 1'b0; // datapath control reg store_eth_payload_int_to_output; reg store_eth_payload_int_to_temp; reg store_eth_payload_axis_temp_to_output; assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg; assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? m_eth_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg; assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg; assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg; // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int)); always @* begin // transfer sink ready state to source m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg; temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg; store_eth_payload_int_to_output = 1'b0; store_eth_payload_int_to_temp = 1'b0; store_eth_payload_axis_temp_to_output = 1'b0; if (m_eth_payload_axis_tready_int_reg) begin // input is ready if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin // output is ready or currently not valid, transfer data to output m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int; store_eth_payload_int_to_output = 1'b1; end else begin // output is not ready, store input in temp temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int; store_eth_payload_int_to_temp = 1'b1; end end else if (m_eth_payload_axis_tready) begin // input is not ready, but output is ready m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg; temp_m_eth_payload_axis_tvalid_next = 1'b0; store_eth_payload_axis_temp_to_output = 1'b1; end end always @(posedge clk) begin if (rst) begin m_eth_payload_axis_tvalid_reg <= 1'b0; m_eth_payload_axis_tready_int_reg <= 1'b0; temp_m_eth_payload_axis_tvalid_reg <= 1'b0; end else begin m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next; m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early; temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next; end // datapath if (store_eth_payload_int_to_output) begin m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int; m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int; m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int; m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int; end else if (store_eth_payload_axis_temp_to_output) begin m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg; m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg; m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg; m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg; end if (store_eth_payload_int_to_temp) begin temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int; temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int; temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int; temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int; end end endmodule

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HS__EDFXBP_BEHAVIORAL_PP_V `define SKY130_FD_SC_HS__EDFXBP_BEHAVIORAL_PP_V /** * edfxbp: Delay flop with loopback enable, non-inverted clock, * complementary outputs. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import sub cells. `include "../u_edf_p_no_pg/sky130_fd_sc_hs__u_edf_p_no_pg.v" `celldefine module sky130_fd_sc_hs__edfxbp ( Q , Q_N , CLK , D , DE , VPWR, VGND ); // Module ports output Q ; output Q_N ; input CLK ; input D ; input DE ; input VPWR; input VGND; // Local signals wire buf_Q ; reg notifier ; wire D_delayed ; wire DE_delayed ; wire CLK_delayed; wire awake ; wire cond0 ; // Name Output Other arguments sky130_fd_sc_hs__u_edf_p_no_pg u_edf_p_no_pg0 (buf_Q , D_delayed, CLK_delayed, DE_delayed, notifier, VPWR, VGND); assign awake = ( VPWR === 1'b1 ); assign cond0 = ( awake && ( DE_delayed === 1'b1 ) ); buf buf0 (Q , buf_Q ); not not0 (Q_N , buf_Q ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HS__EDFXBP_BEHAVIORAL_PP_V

`include "e200_defines.v" module tb_top(); reg clk; reg lfextclk; reg rst_n; wire hfclkrst; wire hfclk = clk & (~hfclkrst); `define CPU_TOP u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.u_e200_cpu_top `define EXU `CPU_TOP.u_e200_cpu.u_e200_core.u_e200_exu `define ITCM `CPU_TOP.u_e200_srams.u_e200_itcm_ram.u_e200_itcm_gnrl_ram.u_sirv_sim_ram `define PC_WRITE_TOHOST `E200_PC_SIZE'h80000086 `define PC_EXT_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000a6 `define PC_SFT_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000be `define PC_TMR_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000d6 `define PC_AFTER_SETMTVEC `E200_PC_SIZE'h80000148 wire [`E200_XLEN-1:0] x3 = `EXU.u_e200_exu_regfile.rf_r[3]; wire [`E200_PC_SIZE-1:0] pc = `EXU.u_e200_exu_commit.alu_cmt_i_pc; reg [31:0] pc_write_to_host_cnt; reg [31:0] pc_write_to_host_cycle; reg [31:0] valid_ir_cycle; reg [31:0] cycle_count; reg pc_write_to_host_flag; always @(posedge hfclk or negedge rst_n) begin if(rst_n == 1'b0) begin pc_write_to_host_cnt <= 32'b0; pc_write_to_host_flag <= 1'b0; pc_write_to_host_cycle <= 32'b0; end else if (pc == `PC_WRITE_TOHOST) begin pc_write_to_host_cnt <= pc_write_to_host_cnt + 1'b1; pc_write_to_host_flag <= 1'b1; if (pc_write_to_host_flag == 1'b0) begin pc_write_to_host_cycle <= cycle_count; end end end always @(posedge hfclk or negedge rst_n) begin if(rst_n == 1'b0) begin cycle_count <= 32'b0; end else begin cycle_count <= cycle_count + 1'b1; end end wire i_valid = `EXU.i_valid; wire i_ready = `EXU.i_ready; always @(posedge hfclk or negedge rst_n) begin if(rst_n == 1'b0) begin valid_ir_cycle <= 32'b0; end else if(i_valid & i_ready & (pc_write_to_host_flag == 1'b0)) begin valid_ir_cycle <= valid_ir_cycle + 1'b1; end end // Randomly force the external interrupt `define EXT_IRQ u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.plic_ext_irq `define SFT_IRQ u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.clint_sft_irq `define TMR_IRQ u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.clint_tmr_irq `define U_CPU u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.u_e200_cpu_top.u_e200_cpu `define ITCM_BUS_ERR `U_CPU.u_e200_itcm_ctrl.chk_icb_rsp_err `define ITCM_BUS_READ `U_CPU.u_e200_itcm_ctrl.e2_icb_read_r `define STATUS_MIE `U_CPU.u_e200_core.u_e200_exu.u_e200_exu_commit.u_e200_exu_excp.status_mie_r wire stop_assert_irq = (pc_write_to_host_cnt > 32); reg tb_itcm_bus_err; reg tb_ext_irq; reg tb_tmr_irq; reg tb_sft_irq; initial begin tb_ext_irq = 1'b0; tb_tmr_irq = 1'b0; tb_sft_irq = 1'b0; end `ifdef ENABLE_TB_FORCE initial begin tb_itcm_bus_err = 1'b0; #100 @(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program forever begin repeat ($urandom_range(1, 20)) @(posedge clk) tb_itcm_bus_err = 1'b0; // Wait random times repeat ($urandom_range(1, 200)) @(posedge clk) tb_itcm_bus_err = 1'b1; // Wait random times if(stop_assert_irq) begin break; end end end initial begin force `EXT_IRQ = tb_ext_irq; force `SFT_IRQ = tb_sft_irq; force `TMR_IRQ = tb_tmr_irq; // We force the bus-error only when: // It is in common code, not in exception code, by checking MIE bit // It is in read operation, not write, otherwise the test cannot recover force `ITCM_BUS_ERR = tb_itcm_bus_err & `STATUS_MIE & `ITCM_BUS_READ ; end initial begin #100 @(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program forever begin repeat ($urandom_range(1, 200)) @(posedge clk) tb_ext_irq = 1'b0; // Wait random times tb_ext_irq = 1'b1; // assert the irq @((pc == `PC_EXT_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values tb_ext_irq = 1'b0; if(stop_assert_irq) begin break; end end end initial begin #100 @(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program forever begin repeat ($urandom_range(1, 200)) @(posedge clk) tb_sft_irq = 1'b0; // Wait random times tb_sft_irq = 1'b1; // assert the irq @((pc == `PC_SFT_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values tb_sft_irq = 1'b0; if(stop_assert_irq) begin break; end end end initial begin #100 @(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program forever begin repeat ($urandom_range(1, 200)) @(posedge clk) tb_tmr_irq = 1'b0; // Wait random times tb_tmr_irq = 1'b1; // assert the irq @((pc == `PC_TMR_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values tb_tmr_irq = 1'b0; if(stop_assert_irq) begin break; end end end `endif reg[8*300:1] testcase; integer dumpwave; initial begin $display("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"); if($value$plusargs("TESTCASE=%s",testcase))begin $display("TESTCASE=%s",testcase); end pc_write_to_host_flag <=0; clk <=0; lfextclk <=0; rst_n <=0; #120 rst_n <=1; @(pc_write_to_host_cnt == 32'd8) #10 rst_n <=1; `ifdef ENABLE_TB_FORCE @((~tb_tmr_irq) & (~tb_sft_irq) & (~tb_ext_irq)) #10 rst_n <=1;// Wait the interrupt to complete `endif $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~ Test Result Summary ~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~TESTCASE: %s ~~~~~~~~~~~~~", testcase); $display("~~~~~~~~~~~~~~Total cycle_count value: %d ~~~~~~~~~~~~~", cycle_count); $display("~~~~~~~~~~The valid Instruction Count: %d ~~~~~~~~~~~~~", valid_ir_cycle); $display("~~~~~The test ending reached at cycle: %d ~~~~~~~~~~~~~", pc_write_to_host_cycle); $display("~~~~~~~~~~~~~~~The final x3 Reg value: %d ~~~~~~~~~~~~~", x3); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); if (x3 == 1) begin $display("~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~ ##### ## #### #### ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~ # # # # # # ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~ # # # # #### #### ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~ ##### ###### # #~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~ # # # # # # #~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~ # # # #### #### ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); end else begin $display("~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~###### ## # # ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~# # # # # ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~##### # # # # ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~# ###### # # ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~# # # # # ~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~# # # # ######~~~~~~~~~~~~~~~~"); $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); end #10 $finish; end initial begin #10000000 $display("Time Out !!!"); $finish; end always begin #2 clk <= ~clk; end always begin #33 lfextclk <= ~lfextclk; end //initial begin // $value$plusargs("DUMPWAVE=%d",dumpwave); // if(dumpwave != 0)begin // // To add your waveform generation function // end //end integer i; reg [7:0] itcm_mem [0:(`E200_ITCM_RAM_DP*8)-1]; initial begin $readmemh({testcase, ".verilog"}, itcm_mem); for (i=0;i<(`E200_ITCM_RAM_DP);i=i+1) begin `ITCM.mem_r[i][00+7:00] = itcm_mem[i*8+0]; `ITCM.mem_r[i][08+7:08] = itcm_mem[i*8+1]; `ITCM.mem_r[i][16+7:16] = itcm_mem[i*8+2]; `ITCM.mem_r[i][24+7:24] = itcm_mem[i*8+3]; `ITCM.mem_r[i][32+7:32] = itcm_mem[i*8+4]; `ITCM.mem_r[i][40+7:40] = itcm_mem[i*8+5]; `ITCM.mem_r[i][48+7:48] = itcm_mem[i*8+6]; `ITCM.mem_r[i][56+7:56] = itcm_mem[i*8+7]; end $display("ITCM 0x00: %h", `ITCM.mem_r[8'h00]); $display("ITCM 0x01: %h", `ITCM.mem_r[8'h01]); $display("ITCM 0x02: %h", `ITCM.mem_r[8'h02]); $display("ITCM 0x03: %h", `ITCM.mem_r[8'h03]); $display("ITCM 0x04: %h", `ITCM.mem_r[8'h04]); $display("ITCM 0x05: %h", `ITCM.mem_r[8'h05]); $display("ITCM 0x06: %h", `ITCM.mem_r[8'h06]); $display("ITCM 0x07: %h", `ITCM.mem_r[8'h07]); $display("ITCM 0x16: %h", `ITCM.mem_r[8'h16]); $display("ITCM 0x20: %h", `ITCM.mem_r[8'h20]); end wire jtag_TDI = 1'b0; wire jtag_TDO; wire jtag_TCK = 1'b0; wire jtag_TMS = 1'b0; wire jtag_TRST = 1'b0; wire jtag_DRV_TDO = 1'b0; e200_fpga_soc_top u_e200_fpga_soc_top( .hfclk(hfclk), .hfclkrst(hfclkrst), .io_pads_jtag_TCK_i_ival (jtag_TCK), .io_pads_jtag_TCK_o_oval (), .io_pads_jtag_TCK_o_oe (), .io_pads_jtag_TCK_o_ie (), .io_pads_jtag_TCK_o_pue (), .io_pads_jtag_TCK_o_ds (), .io_pads_jtag_TMS_i_ival (jtag_TMS), .io_pads_jtag_TMS_o_oval (), .io_pads_jtag_TMS_o_oe (), .io_pads_jtag_TMS_o_ie (), .io_pads_jtag_TMS_o_pue (), .io_pads_jtag_TMS_o_ds (), .io_pads_jtag_TDI_i_ival (jtag_TDI), .io_pads_jtag_TDI_o_oval (), .io_pads_jtag_TDI_o_oe (), .io_pads_jtag_TDI_o_ie (), .io_pads_jtag_TDI_o_pue (), .io_pads_jtag_TDI_o_ds (), .io_pads_jtag_TDO_i_ival (1'b1), .io_pads_jtag_TDO_o_oval (jtag_TDO), .io_pads_jtag_TDO_o_oe (), .io_pads_jtag_TDO_o_ie (), .io_pads_jtag_TDO_o_pue (), .io_pads_jtag_TDO_o_ds (), .io_pads_jtag_TRST_n_i_ival (jtag_TRST), .io_pads_jtag_TRST_n_o_oval (), .io_pads_jtag_TRST_n_o_oe (), .io_pads_jtag_TRST_n_o_ie (), .io_pads_jtag_TRST_n_o_pue (), .io_pads_jtag_TRST_n_o_ds (), .io_pads_gpio_0_i_ival (1'b0), .io_pads_gpio_0_o_oval (), .io_pads_gpio_0_o_oe (), .io_pads_gpio_0_o_ie (), .io_pads_gpio_0_o_pue (), .io_pads_gpio_0_o_ds (), .io_pads_gpio_1_i_ival (1'b0), .io_pads_gpio_1_o_oval (), .io_pads_gpio_1_o_oe (), .io_pads_gpio_1_o_ie (), .io_pads_gpio_1_o_pue (), .io_pads_gpio_1_o_ds (), .io_pads_gpio_2_i_ival (1'b0), .io_pads_gpio_2_o_oval (), .io_pads_gpio_2_o_oe (), .io_pads_gpio_2_o_ie (), .io_pads_gpio_2_o_pue (), .io_pads_gpio_2_o_ds (), .io_pads_gpio_3_i_ival (1'b0), .io_pads_gpio_3_o_oval (), .io_pads_gpio_3_o_oe (), .io_pads_gpio_3_o_ie (), .io_pads_gpio_3_o_pue (), .io_pads_gpio_3_o_ds (), .io_pads_gpio_4_i_ival (1'b0), .io_pads_gpio_4_o_oval (), .io_pads_gpio_4_o_oe (), .io_pads_gpio_4_o_ie (), .io_pads_gpio_4_o_pue (), .io_pads_gpio_4_o_ds (), .io_pads_gpio_5_i_ival (1'b0), .io_pads_gpio_5_o_oval (), .io_pads_gpio_5_o_oe (), .io_pads_gpio_5_o_ie (), .io_pads_gpio_5_o_pue (), .io_pads_gpio_5_o_ds (), .io_pads_gpio_6_i_ival (1'b0), .io_pads_gpio_6_o_oval (), .io_pads_gpio_6_o_oe (), .io_pads_gpio_6_o_ie (), .io_pads_gpio_6_o_pue (), .io_pads_gpio_6_o_ds (), .io_pads_gpio_7_i_ival (1'b0), .io_pads_gpio_7_o_oval (), .io_pads_gpio_7_o_oe (), .io_pads_gpio_7_o_ie (), .io_pads_gpio_7_o_pue (), .io_pads_gpio_7_o_ds (), .io_pads_gpio_8_i_ival (1'b0), .io_pads_gpio_8_o_oval (), .io_pads_gpio_8_o_oe (), .io_pads_gpio_8_o_ie (), .io_pads_gpio_8_o_pue (), .io_pads_gpio_8_o_ds (), .io_pads_gpio_9_i_ival (1'b0), .io_pads_gpio_9_o_oval (), .io_pads_gpio_9_o_oe (), .io_pads_gpio_9_o_ie (), .io_pads_gpio_9_o_pue (), .io_pads_gpio_9_o_ds (), .io_pads_gpio_10_i_ival (1'b0), .io_pads_gpio_10_o_oval (), .io_pads_gpio_10_o_oe (), .io_pads_gpio_10_o_ie (), .io_pads_gpio_10_o_pue (), .io_pads_gpio_10_o_ds (), .io_pads_gpio_11_i_ival (1'b0), .io_pads_gpio_11_o_oval (), .io_pads_gpio_11_o_oe (), .io_pads_gpio_11_o_ie (), .io_pads_gpio_11_o_pue (), .io_pads_gpio_11_o_ds (), .io_pads_gpio_12_i_ival (1'b0), .io_pads_gpio_12_o_oval (), .io_pads_gpio_12_o_oe (), .io_pads_gpio_12_o_ie (), .io_pads_gpio_12_o_pue (), .io_pads_gpio_12_o_ds (), .io_pads_gpio_13_i_ival (1'b0), .io_pads_gpio_13_o_oval (), .io_pads_gpio_13_o_oe (), .io_pads_gpio_13_o_ie (), .io_pads_gpio_13_o_pue (), .io_pads_gpio_13_o_ds (), .io_pads_gpio_14_i_ival (1'b0), .io_pads_gpio_14_o_oval (), .io_pads_gpio_14_o_oe (), .io_pads_gpio_14_o_ie (), .io_pads_gpio_14_o_pue (), .io_pads_gpio_14_o_ds (), .io_pads_gpio_15_i_ival (1'b0), .io_pads_gpio_15_o_oval (), .io_pads_gpio_15_o_oe (), .io_pads_gpio_15_o_ie (), .io_pads_gpio_15_o_pue (), .io_pads_gpio_15_o_ds (), .io_pads_gpio_16_i_ival (1'b0), .io_pads_gpio_16_o_oval (), .io_pads_gpio_16_o_oe (), .io_pads_gpio_16_o_ie (), .io_pads_gpio_16_o_pue (), .io_pads_gpio_16_o_ds (), .io_pads_gpio_17_i_ival (1'b0), .io_pads_gpio_17_o_oval (), .io_pads_gpio_17_o_oe (), .io_pads_gpio_17_o_ie (), .io_pads_gpio_17_o_pue (), .io_pads_gpio_17_o_ds (), .io_pads_gpio_18_i_ival (1'b0), .io_pads_gpio_18_o_oval (), .io_pads_gpio_18_o_oe (), .io_pads_gpio_18_o_ie (), .io_pads_gpio_18_o_pue (), .io_pads_gpio_18_o_ds (), .io_pads_gpio_19_i_ival (1'b0), .io_pads_gpio_19_o_oval (), .io_pads_gpio_19_o_oe (), .io_pads_gpio_19_o_ie (), .io_pads_gpio_19_o_pue (), .io_pads_gpio_19_o_ds (), .io_pads_gpio_20_i_ival (1'b0), .io_pads_gpio_20_o_oval (), .io_pads_gpio_20_o_oe (), .io_pads_gpio_20_o_ie (), .io_pads_gpio_20_o_pue (), .io_pads_gpio_20_o_ds (), .io_pads_gpio_21_i_ival (1'b0), .io_pads_gpio_21_o_oval (), .io_pads_gpio_21_o_oe (), .io_pads_gpio_21_o_ie (), .io_pads_gpio_21_o_pue (), .io_pads_gpio_21_o_ds (), .io_pads_gpio_22_i_ival (1'b0), .io_pads_gpio_22_o_oval (), .io_pads_gpio_22_o_oe (), .io_pads_gpio_22_o_ie (), .io_pads_gpio_22_o_pue (), .io_pads_gpio_22_o_ds (), .io_pads_gpio_23_i_ival (1'b0), .io_pads_gpio_23_o_oval (), .io_pads_gpio_23_o_oe (), .io_pads_gpio_23_o_ie (), .io_pads_gpio_23_o_pue (), .io_pads_gpio_23_o_ds (), .io_pads_gpio_24_i_ival (1'b0), .io_pads_gpio_24_o_oval (), .io_pads_gpio_24_o_oe (), .io_pads_gpio_24_o_ie (), .io_pads_gpio_24_o_pue (), .io_pads_gpio_24_o_ds (), .io_pads_gpio_25_i_ival (1'b0), .io_pads_gpio_25_o_oval (), .io_pads_gpio_25_o_oe (), .io_pads_gpio_25_o_ie (), .io_pads_gpio_25_o_pue (), .io_pads_gpio_25_o_ds (), .io_pads_gpio_26_i_ival (1'b0), .io_pads_gpio_26_o_oval (), .io_pads_gpio_26_o_oe (), .io_pads_gpio_26_o_ie (), .io_pads_gpio_26_o_pue (), .io_pads_gpio_26_o_ds (), .io_pads_gpio_27_i_ival (1'b0), .io_pads_gpio_27_o_oval (), .io_pads_gpio_27_o_oe (), .io_pads_gpio_27_o_ie (), .io_pads_gpio_27_o_pue (), .io_pads_gpio_27_o_ds (), .io_pads_gpio_28_i_ival (1'b0), .io_pads_gpio_28_o_oval (), .io_pads_gpio_28_o_oe (), .io_pads_gpio_28_o_ie (), .io_pads_gpio_28_o_pue (), .io_pads_gpio_28_o_ds (), .io_pads_gpio_29_i_ival (1'b0), .io_pads_gpio_29_o_oval (), .io_pads_gpio_29_o_oe (), .io_pads_gpio_29_o_ie (), .io_pads_gpio_29_o_pue (), .io_pads_gpio_29_o_ds (), .io_pads_gpio_30_i_ival (1'b0), .io_pads_gpio_30_o_oval (), .io_pads_gpio_30_o_oe (), .io_pads_gpio_30_o_ie (), .io_pads_gpio_30_o_pue (), .io_pads_gpio_30_o_ds (), .io_pads_gpio_31_i_ival (1'b0), .io_pads_gpio_31_o_oval (), .io_pads_gpio_31_o_oe (), .io_pads_gpio_31_o_ie (), .io_pads_gpio_31_o_pue (), .io_pads_gpio_31_o_ds (), .io_pads_qspi_sck_i_ival (1'b1), .io_pads_qspi_sck_o_oval (), .io_pads_qspi_sck_o_oe (), .io_pads_qspi_sck_o_ie (), .io_pads_qspi_sck_o_pue (), .io_pads_qspi_sck_o_ds (), .io_pads_qspi_dq_0_i_ival (1'b1), .io_pads_qspi_dq_0_o_oval (), .io_pads_qspi_dq_0_o_oe (), .io_pads_qspi_dq_0_o_ie (), .io_pads_qspi_dq_0_o_pue (), .io_pads_qspi_dq_0_o_ds (), .io_pads_qspi_dq_1_i_ival (1'b1), .io_pads_qspi_dq_1_o_oval (), .io_pads_qspi_dq_1_o_oe (), .io_pads_qspi_dq_1_o_ie (), .io_pads_qspi_dq_1_o_pue (), .io_pads_qspi_dq_1_o_ds (), .io_pads_qspi_dq_2_i_ival (1'b1), .io_pads_qspi_dq_2_o_oval (), .io_pads_qspi_dq_2_o_oe (), .io_pads_qspi_dq_2_o_ie (), .io_pads_qspi_dq_2_o_pue (), .io_pads_qspi_dq_2_o_ds (), .io_pads_qspi_dq_3_i_ival (1'b1), .io_pads_qspi_dq_3_o_oval (), .io_pads_qspi_dq_3_o_oe (), .io_pads_qspi_dq_3_o_ie (), .io_pads_qspi_dq_3_o_pue (), .io_pads_qspi_dq_3_o_ds (), .io_pads_qspi_cs_0_i_ival (1'b1), .io_pads_qspi_cs_0_o_oval (), .io_pads_qspi_cs_0_o_oe (), .io_pads_qspi_cs_0_o_ie (), .io_pads_qspi_cs_0_o_pue (), .io_pads_qspi_cs_0_o_ds (), .io_pads_aon_erst_n_i_ival (rst_n),//This is the real reset, active low .io_pads_aon_erst_n_o_oval (), .io_pads_aon_erst_n_o_oe (), .io_pads_aon_erst_n_o_ie (), .io_pads_aon_erst_n_o_pue (), .io_pads_aon_erst_n_o_ds (), .io_pads_aon_lfextclk_i_ival (lfextclk), .io_pads_aon_lfextclk_o_oval (), .io_pads_aon_lfextclk_o_oe (), .io_pads_aon_lfextclk_o_ie (), .io_pads_aon_lfextclk_o_pue (), .io_pads_aon_lfextclk_o_ds (), .io_pads_aon_pmu_dwakeup_n_i_ival (1'b1), .io_pads_aon_pmu_dwakeup_n_o_oval (), .io_pads_aon_pmu_dwakeup_n_o_oe (), .io_pads_aon_pmu_dwakeup_n_o_ie (), .io_pads_aon_pmu_dwakeup_n_o_pue (), .io_pads_aon_pmu_dwakeup_n_o_ds (), .io_pads_aon_pmu_vddpaden_i_ival (1'b1), .io_pads_aon_pmu_vddpaden_o_oval (), .io_pads_aon_pmu_vddpaden_o_oe (), .io_pads_aon_pmu_vddpaden_o_ie (), .io_pads_aon_pmu_vddpaden_o_pue (), .io_pads_aon_pmu_vddpaden_o_ds () ); endmodule

// ========== Copyright Header Begin ========================================== // // OpenSPARC T1 Processor File: sparc_exu_byp.v // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. // // The above named program is free software; you can redistribute it and/or // modify it under the terms of the GNU General Public // License version 2 as published by the Free Software Foundation. // // The above named program is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU // General Public License for more details. // // You should have received a copy of the GNU General Public // License along with this work; if not, write to the Free Software // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. // // ========== Copyright Header End ============================================ //////////////////////////////////////////////////////////////////////// /* // Module Name: sparc_exu_byp // Description: This block includes the muxes for the bypassing for all // 3 register outputs. It also includes the pipeline registers // for the output of the ALU. All other operands come from // outside the bypass block. Rs1_data chooses between the normal // bypassing paths and the PC. Rs2_data chooses between the normal // bypassing paths and the immediate. */ //FPGA_SYN enables all FPGA related modifications `ifdef FPGA_SYN `define FPGA_SYN_CLK_EN `define FPGA_SYN_CLK_DFF `endif module sparc_exu_byp ( /*AUTOARG*/ // Outputs so, byp_alu_rs1_data_e, byp_alu_rs2_data_e_l, byp_alu_rs2_data_e, exu_lsu_rs3_data_e, exu_spu_rs3_data_e, exu_lsu_rs2_data_e, byp_alu_rcc_data_e, byp_irf_rd_data_w, exu_tlu_wsr_data_m, byp_irf_rd_data_w2, byp_ecc_rs3_data_e, byp_ecc_rcc_data_e, byp_ecl_rs2_31_e, byp_ecl_rs1_31_e, byp_ecl_rs1_63_e, byp_ecl_rs1_2_0_e, byp_ecl_rs2_3_0_e, byp_ecc_rs1_synd_d, byp_ecc_rs2_synd_d, byp_ecc_rs3_synd_d, // Inputs rclk, se, si, sehold, ecl_byp_rs1_mux2_sel_e, ecl_byp_rs1_mux2_sel_rf, ecl_byp_rs1_mux2_sel_ld, ecl_byp_rs1_mux2_sel_usemux1, ecl_byp_rs1_mux1_sel_m, ecl_byp_rs1_mux1_sel_w, ecl_byp_rs1_mux1_sel_w2, ecl_byp_rs1_mux1_sel_other, ecl_byp_rcc_mux2_sel_e, ecl_byp_rcc_mux2_sel_rf, ecl_byp_rcc_mux2_sel_ld, ecl_byp_rcc_mux2_sel_usemux1, ecl_byp_rcc_mux1_sel_m, ecl_byp_rcc_mux1_sel_w, ecl_byp_rcc_mux1_sel_w2, ecl_byp_rcc_mux1_sel_other, ecl_byp_rs2_mux2_sel_e, ecl_byp_rs2_mux2_sel_rf, ecl_byp_rs2_mux2_sel_ld, ecl_byp_rs2_mux2_sel_usemux1, ecl_byp_rs2_mux1_sel_m, ecl_byp_rs2_mux1_sel_w, ecl_byp_rs2_mux1_sel_w2, ecl_byp_rs2_mux1_sel_other, ecl_byp_rs3_mux2_sel_e, ecl_byp_rs3_mux2_sel_rf, ecl_byp_rs3_mux2_sel_ld, ecl_byp_rs3_mux2_sel_usemux1, ecl_byp_rs3_mux1_sel_m, ecl_byp_rs3_mux1_sel_w, ecl_byp_rs3_mux1_sel_w2, ecl_byp_rs3_mux1_sel_other, ecl_byp_rs3h_mux2_sel_e, ecl_byp_rs3h_mux2_sel_rf, ecl_byp_rs3h_mux2_sel_ld, ecl_byp_rs3h_mux2_sel_usemux1, ecl_byp_rs3h_mux1_sel_m, ecl_byp_rs3h_mux1_sel_w, ecl_byp_rs3h_mux1_sel_w2, ecl_byp_rs3h_mux1_sel_other, ecl_byp_rs1_longmux_sel_g2, ecl_byp_rs1_longmux_sel_w2, ecl_byp_rs1_longmux_sel_ldxa, ecl_byp_rs2_longmux_sel_g2, ecl_byp_rs2_longmux_sel_w2, ecl_byp_rs2_longmux_sel_ldxa, ecl_byp_rs3_longmux_sel_g2, ecl_byp_rs3_longmux_sel_w2, ecl_byp_rs3_longmux_sel_ldxa, ecl_byp_rs3h_longmux_sel_g2, ecl_byp_rs3h_longmux_sel_w2, ecl_byp_rs3h_longmux_sel_ldxa, ecl_byp_sel_load_m, ecl_byp_sel_pipe_m, ecl_byp_sel_ecc_m, ecl_byp_sel_muldiv_g, ecl_byp_sel_load_g, ecl_byp_sel_restore_g, ecl_byp_std_e_l, ecl_byp_ldxa_g, alu_byp_rd_data_e, ifu_exu_imm_data_d, irf_byp_rs1_data_d_l, irf_byp_rs2_data_d_l, irf_byp_rs3_data_d_l, irf_byp_rs3h_data_d_l, lsu_exu_dfill_data_g, lsu_exu_ldxa_data_g, div_byp_muldivout_g, ecc_byp_ecc_result_m, ecl_byp_ecc_mask_m_l, ifu_exu_pc_d, ecl_byp_3lsb_m, ecl_byp_restore_m, ecl_byp_sel_restore_m, ecl_byp_eclpr_e, div_byp_yreg_e, ifu_exu_pcver_e, tlu_exu_rsr_data_m, ffu_exu_rsr_data_m, ecl_byp_sel_yreg_e, ecl_byp_sel_eclpr_e, ecl_byp_sel_ifusr_e, ecl_byp_sel_alu_e, ecl_byp_sel_ifex_m, ecl_byp_sel_ffusr_m, ecl_byp_sel_tlusr_m ); input rclk; input se; // scan enable input si; input sehold; input ecl_byp_rs1_mux2_sel_e;// select lines for bypass muxes for rs1 input ecl_byp_rs1_mux2_sel_rf; input ecl_byp_rs1_mux2_sel_ld; input ecl_byp_rs1_mux2_sel_usemux1; input ecl_byp_rs1_mux1_sel_m; input ecl_byp_rs1_mux1_sel_w; input ecl_byp_rs1_mux1_sel_w2; input ecl_byp_rs1_mux1_sel_other; input ecl_byp_rcc_mux2_sel_e;// select lines for bypass muxes for reg condition code input ecl_byp_rcc_mux2_sel_rf; input ecl_byp_rcc_mux2_sel_ld; input ecl_byp_rcc_mux2_sel_usemux1; input ecl_byp_rcc_mux1_sel_m; input ecl_byp_rcc_mux1_sel_w; input ecl_byp_rcc_mux1_sel_w2; input ecl_byp_rcc_mux1_sel_other; input ecl_byp_rs2_mux2_sel_e;// select lines for bypass muxes for rs2 input ecl_byp_rs2_mux2_sel_rf; input ecl_byp_rs2_mux2_sel_ld; input ecl_byp_rs2_mux2_sel_usemux1; input ecl_byp_rs2_mux1_sel_m; input ecl_byp_rs2_mux1_sel_w; input ecl_byp_rs2_mux1_sel_w2; input ecl_byp_rs2_mux1_sel_other; input ecl_byp_rs3_mux2_sel_e;// select lines for bypass muxes for rs3 input ecl_byp_rs3_mux2_sel_rf; input ecl_byp_rs3_mux2_sel_ld; input ecl_byp_rs3_mux2_sel_usemux1; input ecl_byp_rs3_mux1_sel_m; input ecl_byp_rs3_mux1_sel_w; input ecl_byp_rs3_mux1_sel_w2; input ecl_byp_rs3_mux1_sel_other; input ecl_byp_rs3h_mux2_sel_e;// select lines for bypass muxes for rs3 double input ecl_byp_rs3h_mux2_sel_rf; input ecl_byp_rs3h_mux2_sel_ld; input ecl_byp_rs3h_mux2_sel_usemux1; input ecl_byp_rs3h_mux1_sel_m; input ecl_byp_rs3h_mux1_sel_w; input ecl_byp_rs3h_mux1_sel_w2; input ecl_byp_rs3h_mux1_sel_other; input ecl_byp_rs1_longmux_sel_g2; input ecl_byp_rs1_longmux_sel_w2; input ecl_byp_rs1_longmux_sel_ldxa; input ecl_byp_rs2_longmux_sel_g2; input ecl_byp_rs2_longmux_sel_w2; input ecl_byp_rs2_longmux_sel_ldxa; input ecl_byp_rs3_longmux_sel_g2; input ecl_byp_rs3_longmux_sel_w2; input ecl_byp_rs3_longmux_sel_ldxa; input ecl_byp_rs3h_longmux_sel_g2; input ecl_byp_rs3h_longmux_sel_w2; input ecl_byp_rs3h_longmux_sel_ldxa; input ecl_byp_sel_load_m; // m instruction uses load in w1 port input ecl_byp_sel_pipe_m; input ecl_byp_sel_ecc_m; input ecl_byp_sel_muldiv_g; input ecl_byp_sel_load_g; input ecl_byp_sel_restore_g; input ecl_byp_std_e_l; input ecl_byp_ldxa_g; input [63:0] alu_byp_rd_data_e; // data from alu for bypass input [31:0] ifu_exu_imm_data_d; // immediate input [71:0] irf_byp_rs1_data_d_l; // RF rs1_data input [71:0] irf_byp_rs2_data_d_l; // RF rs2_data input [71:0] irf_byp_rs3_data_d_l; // RF rs3_data input [31:0] irf_byp_rs3h_data_d_l;// RF rs3 double data input [63:0] lsu_exu_dfill_data_g; // load data input [63:0] lsu_exu_ldxa_data_g; input [63:0] div_byp_muldivout_g; input [63:0] ecc_byp_ecc_result_m;// result from ecc input [7:0] ecl_byp_ecc_mask_m_l; input [47:0] ifu_exu_pc_d; input [2:0] ecl_byp_3lsb_m; input ecl_byp_restore_m; input ecl_byp_sel_restore_m; input [7:0] ecl_byp_eclpr_e; input [31:0] div_byp_yreg_e; input [63:0] ifu_exu_pcver_e; input [63:0] tlu_exu_rsr_data_m; input [63:0] ffu_exu_rsr_data_m; input ecl_byp_sel_yreg_e; input ecl_byp_sel_eclpr_e; input ecl_byp_sel_ifusr_e; input ecl_byp_sel_alu_e; input ecl_byp_sel_ifex_m; input ecl_byp_sel_ffusr_m; input ecl_byp_sel_tlusr_m; output so; output [63:0] byp_alu_rs1_data_e; // rs1_data operand for alu output [63:0] byp_alu_rs2_data_e_l; // rs2_data operand for alu output [63:0] byp_alu_rs2_data_e; output [63:0] exu_lsu_rs3_data_e; // rs3_data operand for lsu output [63:0] exu_spu_rs3_data_e;// rs3 data for spu output [63:0] exu_lsu_rs2_data_e; output [63:0] byp_alu_rcc_data_e;// data for reg condition codes output [71:0] byp_irf_rd_data_w; output [63:0] exu_tlu_wsr_data_m; // data for writeback output [71:0] byp_irf_rd_data_w2; output [63:0] byp_ecc_rs3_data_e; output [63:0] byp_ecc_rcc_data_e; output byp_ecl_rs2_31_e; output byp_ecl_rs1_31_e; output byp_ecl_rs1_63_e; output [2:0] byp_ecl_rs1_2_0_e; output [3:0] byp_ecl_rs2_3_0_e; output [7:0] byp_ecc_rs1_synd_d; output [7:0] byp_ecc_rs2_synd_d; output [7:0] byp_ecc_rs3_synd_d; wire clk; wire sehold_clk; wire [63:0] irf_byp_rs1_data_d; // RF rs1_data wire [63:0] irf_byp_rs2_data_d; // RF rs2_data wire [63:0] irf_byp_rs3_data_d; // RF rs3_data wire [31:0] irf_byp_rs3h_data_d; // RF rs3_data double wire [63:0] byp_alu_rs1_data_d; // rs1 operand for alu wire [63:0] byp_alu_rcc_data_d; // rcc operand for alu wire [63:0] byp_alu_rs2_data_d; // rs2_data operand for alu wire [63:0] rd_data_e; // e stage rd_data wire [63:0] rd_data_m; // m stage non-load rd_data wire [63:0] full_rd_data_m; // m stage non-load rd_data including rdsr wire [63:0] rd_data_g; wire [63:0] byp_irf_rd_data_m;// m stage rd_data wire [63:0] rs1_data_btwn_mux; // intermediate net for rs1_data muxes wire [63:0] rcc_data_btwn_mux; // intermediate net for rs1_data muxes wire [63:0] rs2_data_btwn_mux; // intermediate net for rs2_data muxes wire [63:0] rs3_data_btwn_mux; // intermediate net for rs3_data muxes wire [31:0] rs3h_data_btwn_mux; // intermediate net for rs3h_data muxes wire [63:0] rs3_data_d; wire [63:0] rs3_data_e; wire [31:0] rs3h_data_d; wire [31:0] rs3h_data_e; wire [63:0] restore_rd_data; wire [63:0] restore_rd_data_next; wire [63:0] dfill_data_g; wire [63:0] dfill_data_g2; wire ecl_byp_std_e; wire [7:0] rd_synd_w_l; wire [7:0] rd_synd_w2_l; assign clk = rclk; `ifdef FPGA_SYN_CLK_EN `else clken_buf irf_write_clkbuf ( .rclk (clk), .enb_l (sehold), .tmb_l (~se), .clk (sehold_clk) ) ; `endif assign byp_ecc_rs1_synd_d[7:0] = ~irf_byp_rs1_data_d_l[71:64]; assign byp_ecc_rs2_synd_d[7:0] = ~irf_byp_rs2_data_d_l[71:64]; assign byp_ecc_rs3_synd_d[7:0] = ~irf_byp_rs3_data_d_l[71:64]; ///////////////////////////////////////// // Load returns go straight into a flop after mux with ldxa_data ///////////////////////////////////////// dp_mux2es #(64) dfill_data_mux (.dout(dfill_data_g[63:0]), .in0(lsu_exu_dfill_data_g[63:0]), .in1(lsu_exu_ldxa_data_g[63:0]), .sel(ecl_byp_ldxa_g)); dff_s #(64) dfill_data_dff (.din(dfill_data_g[63:0]), .clk(clk), .q(dfill_data_g2[63:0]), .se(se), .si(), .so()); ////////////////////////////////////////////////// // RD of PR or SR ////////////////////////////////////////////////// // Mux outputs for rdpr/rdsr mux4ds #(64) ifu_exu_sr_mux(.dout(rd_data_e[63:0]), .in0({32'b0, div_byp_yreg_e[31:0]}), .in1({56'b0, ecl_byp_eclpr_e[7:0]}), .in2(ifu_exu_pcver_e[63:0]), .in3(alu_byp_rd_data_e[63:0]), .sel0(ecl_byp_sel_yreg_e), .sel1(ecl_byp_sel_eclpr_e), .sel2(ecl_byp_sel_ifusr_e), .sel3(ecl_byp_sel_alu_e)); // mux in the rdsr data from ffu and tlu mux3ds #(64) sr_out_mux(.dout(full_rd_data_m[63:0]), .in0({rd_data_m[63:3], ecl_byp_3lsb_m[2:0]}), .in1(ffu_exu_rsr_data_m[63:0]), .in2(tlu_exu_rsr_data_m[63:0]), .sel0(ecl_byp_sel_ifex_m), .sel1(ecl_byp_sel_ffusr_m), .sel2(ecl_byp_sel_tlusr_m)); // Pipeline registers for rd_data dff_s #(64) dff_rd_data_e2m(.din(rd_data_e[63:0]), .clk(clk), .q(rd_data_m[63:0]), .se(se), .si(), .so()); dp_buffer #(64) wsr_data_buf(.dout(exu_tlu_wsr_data_m[63:0]), .in(rd_data_m[63:0])); // Flop for storing result from restore dp_mux2es #(64) restore_buf_mux(.dout(restore_rd_data_next[63:0]), .in0(restore_rd_data[63:0]), .in1(rd_data_m[63:0]), .sel(ecl_byp_restore_m)); dff_s #(64) dff_restore_buf(.din(restore_rd_data_next[63:0]), .q(restore_rd_data[63:0]), .clk(clk), .se(se), .si(), .so()); // Mux for rd_data_m between ALU and load data and ECC result and restore result mux4ds #(64) rd_data_m_mux(.dout(byp_irf_rd_data_m[63:0]), .in0(full_rd_data_m[63:0]), .in1(dfill_data_g2[63:0]), .in2(ecc_byp_ecc_result_m[63:0]), .in3(restore_rd_data[63:0]), .sel0(ecl_byp_sel_pipe_m), .sel1(ecl_byp_sel_load_m), .sel2(ecl_byp_sel_ecc_m), .sel3(ecl_byp_sel_restore_m)); `ifdef FPGA_SYN_CLK_DFF dffe_s #(64) dff_rd_data_m2w(.din(byp_irf_rd_data_m[63:0]), .en (~(sehold)), .clk(clk), .q(byp_irf_rd_data_w[63:0]), .se(se), .si(), .so()); `else dff_s #(64) dff_rd_data_m2w(.din(byp_irf_rd_data_m[63:0]), .clk(sehold_clk), .q(byp_irf_rd_data_w[63:0]), .se(se), .si(), .so()); `endif // W2 flop `ifdef FPGA_SYN_CLK_DFF dffe_s #(64) dff_rd_data_g2w(.din(rd_data_g[63:0]), .en (~(sehold)), .clk(clk), .q(byp_irf_rd_data_w2[63:0]), .se(se), .si(), .so()); `else dff_s #(64) dff_rd_data_g2w(.din(rd_data_g[63:0]), .clk(sehold_clk), .q(byp_irf_rd_data_w2[63:0]), .se(se), .si(), .so()); `endif // D-E pipeline registers for rs_data dff_s #(64) rs1_data_dff(.din(byp_alu_rs1_data_d[63:0]), .clk(clk), .q(byp_alu_rs1_data_e[63:0]), .se(se), .si(), .so()); dff_s #(64) rs2_data_dff(.din(byp_alu_rs2_data_d[63:0]), .clk(clk), .q(byp_alu_rs2_data_e[63:0]), .se(se), .si(), .so()); assign byp_alu_rs2_data_e_l[63:0] = ~byp_alu_rs2_data_e[63:0]; assign byp_ecl_rs2_31_e = byp_alu_rs2_data_e[31]; assign byp_ecl_rs1_63_e = byp_alu_rs1_data_e[63]; assign byp_ecl_rs1_31_e = byp_alu_rs1_data_e[31]; assign byp_ecl_rs1_2_0_e[2:0] = byp_alu_rs1_data_e[2:0]; assign byp_ecl_rs2_3_0_e[3:0] = byp_alu_rs2_data_e[3:0]; dff_s #(64) rs3_data_dff(.din(rs3_data_d[63:0]), .clk(clk), .q(rs3_data_e[63:0]), .se(se), .si(), .so()); dff_s #(32) rs3h_data_dff(.din(rs3h_data_d[31:0]), .clk(clk), .q(rs3h_data_e[31:0]), .se(se), .si(), .so()); dff_s #(64) rcc_data_dff(.din(byp_alu_rcc_data_d[63:0]), .clk(clk), .q(byp_alu_rcc_data_e[63:0]), .se(se), .si(), .so()); assign ecl_byp_std_e = ~ecl_byp_std_e_l; dp_mux2es #(64) rs2_data_out_mux(.dout(exu_lsu_rs2_data_e[63:0]), .in0(byp_alu_rs2_data_e[63:0]), .in1(rs3_data_e[63:0]), .sel(ecl_byp_std_e)); dp_mux2es #(64) rs3_data_out_mux(.dout(exu_lsu_rs3_data_e[63:0]), .in0(rs3_data_e[63:0]), .in1({32'b0,rs3h_data_e[31:0]}), .sel(ecl_byp_std_e)); // part of rs3 goes to spu. Buffer off to help timing/loading assign exu_spu_rs3_data_e[63:0] = rs3_data_e[63:0]; assign byp_ecc_rs3_data_e[63:0] = rs3_data_e[63:0]; assign byp_ecc_rcc_data_e[63:0] = byp_alu_rcc_data_e[63:0]; // Forwarding Muxes // Select lines are as follows: // mux1[M, W, W2, OTHER(optional)] // mux2[mux1, RF, E, LD] assign irf_byp_rs1_data_d[63:0] = ~irf_byp_rs1_data_d_l[63:0]; assign irf_byp_rs2_data_d[63:0] = ~irf_byp_rs2_data_d_l[63:0]; assign irf_byp_rs3_data_d[63:0] = ~irf_byp_rs3_data_d_l[63:0]; assign irf_byp_rs3h_data_d[31:0] = ~irf_byp_rs3h_data_d_l[31:0]; /* -----\/----- EXCLUDED -----\/----- // the w2 bypass path is either what is being written that cycle // or the load result that will be written next cycle. -----/\----- EXCLUDED -----/\----- */ wire [63:0] rs1_data_w2; wire [63:0] rs2_data_w2; wire [63:0] rs3_data_w2; wire [31:0] rs3h_data_w2; mux3ds #(64) rs1_w2_mux(.dout(rs1_data_w2[63:0]), .in0(byp_irf_rd_data_w2[63:0]), .in1(dfill_data_g2[63:0]), .in2(lsu_exu_ldxa_data_g[63:0]), .sel0(ecl_byp_rs1_longmux_sel_w2), .sel1(ecl_byp_rs1_longmux_sel_g2), .sel2(ecl_byp_rs1_longmux_sel_ldxa)); mux3ds #(64) rs2_w2_mux(.dout(rs2_data_w2[63:0]), .in0(byp_irf_rd_data_w2[63:0]), .in1(dfill_data_g2[63:0]), .in2(lsu_exu_ldxa_data_g[63:0]), .sel0(ecl_byp_rs2_longmux_sel_w2), .sel1(ecl_byp_rs2_longmux_sel_g2), .sel2(ecl_byp_rs2_longmux_sel_ldxa)); mux3ds #(64) rs3_w2_mux(.dout(rs3_data_w2[63:0]), .in0(byp_irf_rd_data_w2[63:0]), .in1(dfill_data_g2[63:0]), .in2(lsu_exu_ldxa_data_g[63:0]), .sel0(ecl_byp_rs3_longmux_sel_w2), .sel1(ecl_byp_rs3_longmux_sel_g2), .sel2(ecl_byp_rs3_longmux_sel_ldxa)); mux3ds #(32) rs3h_w2_mux(.dout(rs3h_data_w2[31:0]), .in0(byp_irf_rd_data_w2[31:0]), .in1(dfill_data_g2[31:0]), .in2(lsu_exu_ldxa_data_g[31:0]), .sel0(ecl_byp_rs3h_longmux_sel_w2), .sel1(ecl_byp_rs3h_longmux_sel_g2), .sel2(ecl_byp_rs3h_longmux_sel_ldxa)); // rs1_data muxes: RF and E are critical paths mux4ds #(64) mux_rs1_data_1(.dout(rs1_data_btwn_mux[63:0]), .in0(rd_data_m[63:0]), .in1(byp_irf_rd_data_w[63:0]), .in2(rs1_data_w2[63:0]), .in3({{16{ifu_exu_pc_d[47]}}, ifu_exu_pc_d[47:0]}), .sel0(ecl_byp_rs1_mux1_sel_m), .sel1(ecl_byp_rs1_mux1_sel_w), .sel2(ecl_byp_rs1_mux1_sel_w2), .sel3(ecl_byp_rs1_mux1_sel_other)); mux4ds #(64) mux_rs1_data_2(.dout(byp_alu_rs1_data_d[63:0]), .in0(rs1_data_btwn_mux[63:0]), .in1(irf_byp_rs1_data_d[63:0]), .in2(alu_byp_rd_data_e[63:0]), .in3(lsu_exu_dfill_data_g[63:0]), .sel0(ecl_byp_rs1_mux2_sel_usemux1), .sel1(ecl_byp_rs1_mux2_sel_rf), .sel2(ecl_byp_rs1_mux2_sel_e), .sel3(ecl_byp_rs1_mux2_sel_ld)); // rcc_data muxes: RF and E are critical paths mux4ds #(64) mux_rcc_data_1(.dout(rcc_data_btwn_mux[63:0]), .in0(rd_data_m[63:0]), .in1(byp_irf_rd_data_w[63:0]), .in2(rs1_data_w2[63:0]), .in3({64{1'b0}}), .sel0(ecl_byp_rcc_mux1_sel_m), .sel1(ecl_byp_rcc_mux1_sel_w), .sel2(ecl_byp_rcc_mux1_sel_w2), .sel3(ecl_byp_rcc_mux1_sel_other)); mux4ds #(64) mux_rcc_data_2(.dout(byp_alu_rcc_data_d[63:0]), .in0(rcc_data_btwn_mux[63:0]), .in1(irf_byp_rs1_data_d[63:0]), .in2(alu_byp_rd_data_e[63:0]), .in3(lsu_exu_dfill_data_g[63:0]), .sel0(ecl_byp_rcc_mux2_sel_usemux1), .sel1(ecl_byp_rcc_mux2_sel_rf), .sel2(ecl_byp_rcc_mux2_sel_e), .sel3(ecl_byp_rcc_mux2_sel_ld)); // rs2_data muxes: RF and E are critical paths, optional is imm mux4ds #(64) mux_rs2_data_1(.dout(rs2_data_btwn_mux[63:0]), .in0(rd_data_m[63:0]), .in1(byp_irf_rd_data_w[63:0]), .in2(rs2_data_w2[63:0]), .in3({{32{ifu_exu_imm_data_d[31]}}, ifu_exu_imm_data_d[31:0]}), .sel0(ecl_byp_rs2_mux1_sel_m), .sel1(ecl_byp_rs2_mux1_sel_w), .sel2(ecl_byp_rs2_mux1_sel_w2), .sel3(ecl_byp_rs2_mux1_sel_other)); mux4ds #(64) mux_rs2_data_2(.dout(byp_alu_rs2_data_d[63:0]), .in0(rs2_data_btwn_mux[63:0]), .in1(irf_byp_rs2_data_d[63:0]), .in2(alu_byp_rd_data_e[63:0]), .in3(lsu_exu_dfill_data_g[63:0]), .sel0(ecl_byp_rs2_mux2_sel_usemux1), .sel1(ecl_byp_rs2_mux2_sel_rf), .sel2(ecl_byp_rs2_mux2_sel_e), .sel3(ecl_byp_rs2_mux2_sel_ld)); // rs3_data muxes: RF and E are critical paths, no optional mux4ds #(64) mux_rs3_data_1(.dout(rs3_data_btwn_mux[63:0]), .in0(rd_data_m[63:0]), .in1(byp_irf_rd_data_w[63:0]), .in2(rs3_data_w2[63:0]), .in3({64{1'b0}}), .sel0(ecl_byp_rs3_mux1_sel_m), .sel1(ecl_byp_rs3_mux1_sel_w), .sel2(ecl_byp_rs3_mux1_sel_w2), .sel3(ecl_byp_rs3_mux1_sel_other)); mux4ds #(64) mux_rs3_data_2(.dout(rs3_data_d[63:0]), .in0(rs3_data_btwn_mux[63:0]), .in1(irf_byp_rs3_data_d[63:0]), .in2(alu_byp_rd_data_e[63:0]), .in3(lsu_exu_dfill_data_g[63:0]), .sel0(ecl_byp_rs3_mux2_sel_usemux1), .sel1(ecl_byp_rs3_mux2_sel_rf), .sel2(ecl_byp_rs3_mux2_sel_e), .sel3(ecl_byp_rs3_mux2_sel_ld)); // rs3_data muxes: RF and E are critical paths, no optional mux4ds #(32) mux_rs3h_data_1(.dout(rs3h_data_btwn_mux[31:0]), .in0(rd_data_m[31:0]), .in1(byp_irf_rd_data_w[31:0]), .in2(rs3h_data_w2[31:0]), .in3({32{1'b0}}), .sel0(ecl_byp_rs3h_mux1_sel_m), .sel1(ecl_byp_rs3h_mux1_sel_w), .sel2(ecl_byp_rs3h_mux1_sel_w2), .sel3(ecl_byp_rs3h_mux1_sel_other)); mux4ds #(32) mux_rs3h_data_2(.dout(rs3h_data_d[31:0]), .in0(rs3h_data_btwn_mux[31:0]), .in1(irf_byp_rs3h_data_d[31:0]), .in2(alu_byp_rd_data_e[31:0]), .in3(lsu_exu_dfill_data_g[31:0]), .sel0(ecl_byp_rs3h_mux2_sel_usemux1), .sel1(ecl_byp_rs3h_mux2_sel_rf), .sel2(ecl_byp_rs3h_mux2_sel_e), .sel3(ecl_byp_rs3h_mux2_sel_ld)); // ECC for W1 `ifdef FPGA_SYN_CLK_DFF sparc_exu_byp_eccgen w1_eccgen(.d(byp_irf_rd_data_m[63:0]), .msk(ecl_byp_ecc_mask_m_l[7:0]), .p(rd_synd_w_l[7:0]), .clk(clk), .se(se)); `else sparc_exu_byp_eccgen w1_eccgen(.d(byp_irf_rd_data_m[63:0]), .msk(ecl_byp_ecc_mask_m_l[7:0]), .p(rd_synd_w_l[7:0]), .clk(sehold_clk), .se(se)); `endif assign byp_irf_rd_data_w[71:64] = ~rd_synd_w_l[7:0]; //////////////////////// // G arbitration muxes and W2 ECC //////////////////////// mux3ds #(64) mux_w2_data(.dout(rd_data_g[63:0]), .in0(div_byp_muldivout_g[63:0]), .in1(dfill_data_g2[63:0]), .in2(restore_rd_data[63:0]), .sel0(ecl_byp_sel_muldiv_g), .sel1(ecl_byp_sel_load_g), .sel2(ecl_byp_sel_restore_g)); `ifdef FPGA_SYN_CLK_DFF sparc_exu_byp_eccgen w2_eccgen(.d(rd_data_g[63:0]), .msk(ecl_byp_ecc_mask_m_l[7:0]), .p(rd_synd_w2_l[7:0]), .clk(clk), .se(se)); `else sparc_exu_byp_eccgen w2_eccgen(.d(rd_data_g[63:0]), .msk(ecl_byp_ecc_mask_m_l[7:0]), .p(rd_synd_w2_l[7:0]), .clk(sehold_clk), .se(se)); `endif assign byp_irf_rd_data_w2[71:64] = ~rd_synd_w2_l[7:0]; endmodule // sparc_exu_byp

/* Copyright (c) 2020 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ // Language: Verilog 2001 `timescale 1ns / 1ps /* * FPGA core logic */ module fpga_core # ( parameter TARGET = "GENERIC" ) ( /* * Clock: 125MHz * Synchronous reset */ input wire clk, input wire clk90, input wire rst, /* * GPIO */ input wire [3:0] btn, input wire [17:0] sw, output wire [8:0] ledg, output wire [17:0] ledr, output wire [6:0] hex0, output wire [6:0] hex1, output wire [6:0] hex2, output wire [6:0] hex3, output wire [6:0] hex4, output wire [6:0] hex5, output wire [6:0] hex6, output wire [6:0] hex7, output wire [35:0] gpio, /* * Ethernet: 1000BASE-T RGMII */ input wire phy0_rx_clk, input wire [3:0] phy0_rxd, input wire phy0_rx_ctl, output wire phy0_tx_clk, output wire [3:0] phy0_txd, output wire phy0_tx_ctl, output wire phy0_reset_n, input wire phy0_int_n, input wire phy1_rx_clk, input wire [3:0] phy1_rxd, input wire phy1_rx_ctl, output wire phy1_tx_clk, output wire [3:0] phy1_txd, output wire phy1_tx_ctl, output wire phy1_reset_n, input wire phy1_int_n ); // AXI between MAC and Ethernet modules wire [7:0] rx_axis_tdata; wire rx_axis_tvalid; wire rx_axis_tready; wire rx_axis_tlast; wire rx_axis_tuser; wire [7:0] tx_axis_tdata; wire tx_axis_tvalid; wire tx_axis_tready; wire tx_axis_tlast; wire tx_axis_tuser; // Ethernet frame between Ethernet modules and UDP stack wire rx_eth_hdr_ready; wire rx_eth_hdr_valid; wire [47:0] rx_eth_dest_mac; wire [47:0] rx_eth_src_mac; wire [15:0] rx_eth_type; wire [7:0] rx_eth_payload_axis_tdata; wire rx_eth_payload_axis_tvalid; wire rx_eth_payload_axis_tready; wire rx_eth_payload_axis_tlast; wire rx_eth_payload_axis_tuser; wire tx_eth_hdr_ready; wire tx_eth_hdr_valid; wire [47:0] tx_eth_dest_mac; wire [47:0] tx_eth_src_mac; wire [15:0] tx_eth_type; wire [7:0] tx_eth_payload_axis_tdata; wire tx_eth_payload_axis_tvalid; wire tx_eth_payload_axis_tready; wire tx_eth_payload_axis_tlast; wire tx_eth_payload_axis_tuser; // IP frame connections wire rx_ip_hdr_valid; wire rx_ip_hdr_ready; wire [47:0] rx_ip_eth_dest_mac; wire [47:0] rx_ip_eth_src_mac; wire [15:0] rx_ip_eth_type; wire [3:0] rx_ip_version; wire [3:0] rx_ip_ihl; wire [5:0] rx_ip_dscp; wire [1:0] rx_ip_ecn; wire [15:0] rx_ip_length; wire [15:0] rx_ip_identification; wire [2:0] rx_ip_flags; wire [12:0] rx_ip_fragment_offset; wire [7:0] rx_ip_ttl; wire [7:0] rx_ip_protocol; wire [15:0] rx_ip_header_checksum; wire [31:0] rx_ip_source_ip; wire [31:0] rx_ip_dest_ip; wire [7:0] rx_ip_payload_axis_tdata; wire rx_ip_payload_axis_tvalid; wire rx_ip_payload_axis_tready; wire rx_ip_payload_axis_tlast; wire rx_ip_payload_axis_tuser; wire tx_ip_hdr_valid; wire tx_ip_hdr_ready; wire [5:0] tx_ip_dscp; wire [1:0] tx_ip_ecn; wire [15:0] tx_ip_length; wire [7:0] tx_ip_ttl; wire [7:0] tx_ip_protocol; wire [31:0] tx_ip_source_ip; wire [31:0] tx_ip_dest_ip; wire [7:0] tx_ip_payload_axis_tdata; wire tx_ip_payload_axis_tvalid; wire tx_ip_payload_axis_tready; wire tx_ip_payload_axis_tlast; wire tx_ip_payload_axis_tuser; // UDP frame connections wire rx_udp_hdr_valid; wire rx_udp_hdr_ready; wire [47:0] rx_udp_eth_dest_mac; wire [47:0] rx_udp_eth_src_mac; wire [15:0] rx_udp_eth_type; wire [3:0] rx_udp_ip_version; wire [3:0] rx_udp_ip_ihl; wire [5:0] rx_udp_ip_dscp; wire [1:0] rx_udp_ip_ecn; wire [15:0] rx_udp_ip_length; wire [15:0] rx_udp_ip_identification; wire [2:0] rx_udp_ip_flags; wire [12:0] rx_udp_ip_fragment_offset; wire [7:0] rx_udp_ip_ttl; wire [7:0] rx_udp_ip_protocol; wire [15:0] rx_udp_ip_header_checksum; wire [31:0] rx_udp_ip_source_ip; wire [31:0] rx_udp_ip_dest_ip; wire [15:0] rx_udp_source_port; wire [15:0] rx_udp_dest_port; wire [15:0] rx_udp_length; wire [15:0] rx_udp_checksum; wire [7:0] rx_udp_payload_axis_tdata; wire rx_udp_payload_axis_tvalid; wire rx_udp_payload_axis_tready; wire rx_udp_payload_axis_tlast; wire rx_udp_payload_axis_tuser; wire tx_udp_hdr_valid; wire tx_udp_hdr_ready; wire [5:0] tx_udp_ip_dscp; wire [1:0] tx_udp_ip_ecn; wire [7:0] tx_udp_ip_ttl; wire [31:0] tx_udp_ip_source_ip; wire [31:0] tx_udp_ip_dest_ip; wire [15:0] tx_udp_source_port; wire [15:0] tx_udp_dest_port; wire [15:0] tx_udp_length; wire [15:0] tx_udp_checksum; wire [7:0] tx_udp_payload_axis_tdata; wire tx_udp_payload_axis_tvalid; wire tx_udp_payload_axis_tready; wire tx_udp_payload_axis_tlast; wire tx_udp_payload_axis_tuser; wire [7:0] rx_fifo_udp_payload_axis_tdata; wire rx_fifo_udp_payload_axis_tvalid; wire rx_fifo_udp_payload_axis_tready; wire rx_fifo_udp_payload_axis_tlast; wire rx_fifo_udp_payload_axis_tuser; wire [7:0] tx_fifo_udp_payload_axis_tdata; wire tx_fifo_udp_payload_axis_tvalid; wire tx_fifo_udp_payload_axis_tready; wire tx_fifo_udp_payload_axis_tlast; wire tx_fifo_udp_payload_axis_tuser; // Configuration wire [47:0] local_mac = 48'h02_00_00_00_00_00; wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128}; wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1}; wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0}; // IP ports not used assign rx_ip_hdr_ready = 1; assign rx_ip_payload_axis_tready = 1; assign tx_ip_hdr_valid = 0; assign tx_ip_dscp = 0; assign tx_ip_ecn = 0; assign tx_ip_length = 0; assign tx_ip_ttl = 0; assign tx_ip_protocol = 0; assign tx_ip_source_ip = 0; assign tx_ip_dest_ip = 0; assign tx_ip_payload_axis_tdata = 0; assign tx_ip_payload_axis_tvalid = 0; assign tx_ip_payload_axis_tlast = 0; assign tx_ip_payload_axis_tuser = 0; // Loop back UDP wire match_cond = rx_udp_dest_port == 1234; wire no_match = !match_cond; reg match_cond_reg = 0; reg no_match_reg = 0; always @(posedge clk) begin if (rst) begin match_cond_reg <= 0; no_match_reg <= 0; end else begin if (rx_udp_payload_axis_tvalid) begin if ((!match_cond_reg && !no_match_reg) || (rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin match_cond_reg <= match_cond; no_match_reg <= no_match; end end else begin match_cond_reg <= 0; no_match_reg <= 0; end end end assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond; assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match; assign tx_udp_ip_dscp = 0; assign tx_udp_ip_ecn = 0; assign tx_udp_ip_ttl = 64; assign tx_udp_ip_source_ip = local_ip; assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip; assign tx_udp_source_port = rx_udp_dest_port; assign tx_udp_dest_port = rx_udp_source_port; assign tx_udp_length = rx_udp_length; assign tx_udp_checksum = 0; assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata; assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid; assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready; assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast; assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser; assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata; assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg; assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg; assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast; assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser; // Place first payload byte onto LEDs reg valid_last = 0; reg [7:0] led_reg = 0; always @(posedge clk) begin if (tx_udp_payload_axis_tvalid) begin if (!valid_last) begin led_reg <= tx_udp_payload_axis_tdata; valid_last <= 1'b1; end if (tx_udp_payload_axis_tlast) begin valid_last <= 1'b0; end end if (rst) begin led_reg <= 0; end end // place dest IP onto 7 segment displays reg [31:0] dest_ip_reg = 0; always @(posedge clk) begin if (tx_udp_hdr_valid) begin dest_ip_reg <= tx_udp_ip_dest_ip; end if (rst) begin dest_ip_reg <= 0; end end hex_display #( .INVERT(1) ) hex_display_0 ( .in(dest_ip_reg[3:0]), .enable(1), .out(hex0) ); hex_display #( .INVERT(1) ) hex_display_1 ( .in(dest_ip_reg[7:4]), .enable(1), .out(hex1) ); hex_display #( .INVERT(1) ) hex_display_2 ( .in(dest_ip_reg[11:8]), .enable(1), .out(hex2) ); hex_display #( .INVERT(1) ) hex_display_3 ( .in(dest_ip_reg[15:12]), .enable(1), .out(hex3) ); hex_display #( .INVERT(1) ) hex_display_4 ( .in(dest_ip_reg[19:16]), .enable(1), .out(hex4) ); hex_display #( .INVERT(1) ) hex_display_5 ( .in(dest_ip_reg[23:20]), .enable(1), .out(hex5) ); hex_display #( .INVERT(1) ) hex_display_6 ( .in(dest_ip_reg[27:24]), .enable(1), .out(hex6) ); hex_display #( .INVERT(1) ) hex_display_7 ( .in(dest_ip_reg[31:28]), .enable(1), .out(hex7) ); //assign led = sw; assign ledg = led_reg; assign ledr = sw; assign phy0_reset_n = ~rst; assign phy1_reset_n = ~rst; assign gpio = 0; eth_mac_1g_rgmii_fifo #( .TARGET(TARGET), .USE_CLK90("TRUE"), .ENABLE_PADDING(1), .MIN_FRAME_LENGTH(64), .TX_FIFO_DEPTH(4096), .TX_FRAME_FIFO(1), .RX_FIFO_DEPTH(4096), .RX_FRAME_FIFO(1) ) eth_mac_inst ( .gtx_clk(clk), .gtx_clk90(clk90), .gtx_rst(rst), .logic_clk(clk), .logic_rst(rst), .tx_axis_tdata(tx_axis_tdata), .tx_axis_tvalid(tx_axis_tvalid), .tx_axis_tready(tx_axis_tready), .tx_axis_tlast(tx_axis_tlast), .tx_axis_tuser(tx_axis_tuser), .rx_axis_tdata(rx_axis_tdata), .rx_axis_tvalid(rx_axis_tvalid), .rx_axis_tready(rx_axis_tready), .rx_axis_tlast(rx_axis_tlast), .rx_axis_tuser(rx_axis_tuser), .rgmii_rx_clk(phy0_rx_clk), .rgmii_rxd(phy0_rxd), .rgmii_rx_ctl(phy0_rx_ctl), .rgmii_tx_clk(phy0_tx_clk), .rgmii_txd(phy0_txd), .rgmii_tx_ctl(phy0_tx_ctl), .tx_fifo_overflow(), .tx_fifo_bad_frame(), .tx_fifo_good_frame(), .rx_error_bad_frame(), .rx_error_bad_fcs(), .rx_fifo_overflow(), .rx_fifo_bad_frame(), .rx_fifo_good_frame(), .speed(), .ifg_delay(12) ); eth_axis_rx eth_axis_rx_inst ( .clk(clk), .rst(rst), // AXI input .s_axis_tdata(rx_axis_tdata), .s_axis_tvalid(rx_axis_tvalid), .s_axis_tready(rx_axis_tready), .s_axis_tlast(rx_axis_tlast), .s_axis_tuser(rx_axis_tuser), // Ethernet frame output .m_eth_hdr_valid(rx_eth_hdr_valid), .m_eth_hdr_ready(rx_eth_hdr_ready), .m_eth_dest_mac(rx_eth_dest_mac), .m_eth_src_mac(rx_eth_src_mac), .m_eth_type(rx_eth_type), .m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), .m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), .m_eth_payload_axis_tready(rx_eth_payload_axis_tready), .m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), .m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), // Status signals .busy(), .error_header_early_termination() ); eth_axis_tx eth_axis_tx_inst ( .clk(clk), .rst(rst), // Ethernet frame input .s_eth_hdr_valid(tx_eth_hdr_valid), .s_eth_hdr_ready(tx_eth_hdr_ready), .s_eth_dest_mac(tx_eth_dest_mac), .s_eth_src_mac(tx_eth_src_mac), .s_eth_type(tx_eth_type), .s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), .s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), .s_eth_payload_axis_tready(tx_eth_payload_axis_tready), .s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), .s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), // AXI output .m_axis_tdata(tx_axis_tdata), .m_axis_tvalid(tx_axis_tvalid), .m_axis_tready(tx_axis_tready), .m_axis_tlast(tx_axis_tlast), .m_axis_tuser(tx_axis_tuser), // Status signals .busy() ); udp_complete udp_complete_inst ( .clk(clk), .rst(rst), // Ethernet frame input .s_eth_hdr_valid(rx_eth_hdr_valid), .s_eth_hdr_ready(rx_eth_hdr_ready), .s_eth_dest_mac(rx_eth_dest_mac), .s_eth_src_mac(rx_eth_src_mac), .s_eth_type(rx_eth_type), .s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), .s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), .s_eth_payload_axis_tready(rx_eth_payload_axis_tready), .s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), .s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), // Ethernet frame output .m_eth_hdr_valid(tx_eth_hdr_valid), .m_eth_hdr_ready(tx_eth_hdr_ready), .m_eth_dest_mac(tx_eth_dest_mac), .m_eth_src_mac(tx_eth_src_mac), .m_eth_type(tx_eth_type), .m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), .m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), .m_eth_payload_axis_tready(tx_eth_payload_axis_tready), .m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), .m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), // IP frame input .s_ip_hdr_valid(tx_ip_hdr_valid), .s_ip_hdr_ready(tx_ip_hdr_ready), .s_ip_dscp(tx_ip_dscp), .s_ip_ecn(tx_ip_ecn), .s_ip_length(tx_ip_length), .s_ip_ttl(tx_ip_ttl), .s_ip_protocol(tx_ip_protocol), .s_ip_source_ip(tx_ip_source_ip), .s_ip_dest_ip(tx_ip_dest_ip), .s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata), .s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid), .s_ip_payload_axis_tready(tx_ip_payload_axis_tready), .s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast), .s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser), // IP frame output .m_ip_hdr_valid(rx_ip_hdr_valid), .m_ip_hdr_ready(rx_ip_hdr_ready), .m_ip_eth_dest_mac(rx_ip_eth_dest_mac), .m_ip_eth_src_mac(rx_ip_eth_src_mac), .m_ip_eth_type(rx_ip_eth_type), .m_ip_version(rx_ip_version), .m_ip_ihl(rx_ip_ihl), .m_ip_dscp(rx_ip_dscp), .m_ip_ecn(rx_ip_ecn), .m_ip_length(rx_ip_length), .m_ip_identification(rx_ip_identification), .m_ip_flags(rx_ip_flags), .m_ip_fragment_offset(rx_ip_fragment_offset), .m_ip_ttl(rx_ip_ttl), .m_ip_protocol(rx_ip_protocol), .m_ip_header_checksum(rx_ip_header_checksum), .m_ip_source_ip(rx_ip_source_ip), .m_ip_dest_ip(rx_ip_dest_ip), .m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata), .m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid), .m_ip_payload_axis_tready(rx_ip_payload_axis_tready), .m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast), .m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser), // UDP frame input .s_udp_hdr_valid(tx_udp_hdr_valid), .s_udp_hdr_ready(tx_udp_hdr_ready), .s_udp_ip_dscp(tx_udp_ip_dscp), .s_udp_ip_ecn(tx_udp_ip_ecn), .s_udp_ip_ttl(tx_udp_ip_ttl), .s_udp_ip_source_ip(tx_udp_ip_source_ip), .s_udp_ip_dest_ip(tx_udp_ip_dest_ip), .s_udp_source_port(tx_udp_source_port), .s_udp_dest_port(tx_udp_dest_port), .s_udp_length(tx_udp_length), .s_udp_checksum(tx_udp_checksum), .s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata), .s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid), .s_udp_payload_axis_tready(tx_udp_payload_axis_tready), .s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast), .s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser), // UDP frame output .m_udp_hdr_valid(rx_udp_hdr_valid), .m_udp_hdr_ready(rx_udp_hdr_ready), .m_udp_eth_dest_mac(rx_udp_eth_dest_mac), .m_udp_eth_src_mac(rx_udp_eth_src_mac), .m_udp_eth_type(rx_udp_eth_type), .m_udp_ip_version(rx_udp_ip_version), .m_udp_ip_ihl(rx_udp_ip_ihl), .m_udp_ip_dscp(rx_udp_ip_dscp), .m_udp_ip_ecn(rx_udp_ip_ecn), .m_udp_ip_length(rx_udp_ip_length), .m_udp_ip_identification(rx_udp_ip_identification), .m_udp_ip_flags(rx_udp_ip_flags), .m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset), .m_udp_ip_ttl(rx_udp_ip_ttl), .m_udp_ip_protocol(rx_udp_ip_protocol), .m_udp_ip_header_checksum(rx_udp_ip_header_checksum), .m_udp_ip_source_ip(rx_udp_ip_source_ip), .m_udp_ip_dest_ip(rx_udp_ip_dest_ip), .m_udp_source_port(rx_udp_source_port), .m_udp_dest_port(rx_udp_dest_port), .m_udp_length(rx_udp_length), .m_udp_checksum(rx_udp_checksum), .m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata), .m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid), .m_udp_payload_axis_tready(rx_udp_payload_axis_tready), .m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast), .m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser), // Status signals .ip_rx_busy(), .ip_tx_busy(), .udp_rx_busy(), .udp_tx_busy(), .ip_rx_error_header_early_termination(), .ip_rx_error_payload_early_termination(), .ip_rx_error_invalid_header(), .ip_rx_error_invalid_checksum(), .ip_tx_error_payload_early_termination(), .ip_tx_error_arp_failed(), .udp_rx_error_header_early_termination(), .udp_rx_error_payload_early_termination(), .udp_tx_error_payload_early_termination(), // Configuration .local_mac(local_mac), .local_ip(local_ip), .gateway_ip(gateway_ip), .subnet_mask(subnet_mask), .clear_arp_cache(0) ); axis_fifo #( .DEPTH(8192), .DATA_WIDTH(8), .KEEP_ENABLE(0), .ID_ENABLE(0), .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), .FRAME_FIFO(0) ) udp_payload_fifo ( .clk(clk), .rst(rst), // AXI input .s_axis_tdata(rx_fifo_udp_payload_axis_tdata), .s_axis_tkeep(0), .s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid), .s_axis_tready(rx_fifo_udp_payload_axis_tready), .s_axis_tlast(rx_fifo_udp_payload_axis_tlast), .s_axis_tid(0), .s_axis_tdest(0), .s_axis_tuser(rx_fifo_udp_payload_axis_tuser), // AXI output .m_axis_tdata(tx_fifo_udp_payload_axis_tdata), .m_axis_tkeep(), .m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid), .m_axis_tready(tx_fifo_udp_payload_axis_tready), .m_axis_tlast(tx_fifo_udp_payload_axis_tlast), .m_axis_tid(), .m_axis_tdest(), .m_axis_tuser(tx_fifo_udp_payload_axis_tuser), // Status .status_overflow(), .status_bad_frame(), .status_good_frame() ); endmodule

// *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. // // All rights reserved. // // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // - Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in // the documentation and/or other materials provided with the // distribution. // - Neither the name of Analog Devices, Inc. nor the names of its // contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // - The use of this software may or may not infringe the patent rights // of one or more patent holders. This license does not release you // from the requirement that you obtain separate licenses from these // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. // // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY // RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** // *************************************************************************** // *************************************************************************** // This is the dac physical interface (drives samples from the low speed clock to the // dac clock domain. `timescale 1ns/100ps module axi_ad9144_if ( // jesd interface // tx_clk is (line-rate/40) tx_clk, tx_data, // dac interface dac_clk, dac_rst, dac_data_0_0, dac_data_0_1, dac_data_0_2, dac_data_0_3, dac_data_1_0, dac_data_1_1, dac_data_1_2, dac_data_1_3, dac_data_2_0, dac_data_2_1, dac_data_2_2, dac_data_2_3, dac_data_3_0, dac_data_3_1, dac_data_3_2, dac_data_3_3); // jesd interface // tx_clk is (line-rate/40) input tx_clk; output [255:0] tx_data; // dac interface output dac_clk; input dac_rst; input [15:0] dac_data_0_0; input [15:0] dac_data_0_1; input [15:0] dac_data_0_2; input [15:0] dac_data_0_3; input [15:0] dac_data_1_0; input [15:0] dac_data_1_1; input [15:0] dac_data_1_2; input [15:0] dac_data_1_3; input [15:0] dac_data_2_0; input [15:0] dac_data_2_1; input [15:0] dac_data_2_2; input [15:0] dac_data_2_3; input [15:0] dac_data_3_0; input [15:0] dac_data_3_1; input [15:0] dac_data_3_2; input [15:0] dac_data_3_3; // internal registers reg [255:0] tx_data = 'd0; // reorder data for the jesd links assign dac_clk = tx_clk; always @(posedge dac_clk) begin if (dac_rst == 1'b1) begin tx_data <= 256'd0; end else begin tx_data[255:248] <= dac_data_3_3[ 7: 0]; tx_data[247:240] <= dac_data_3_2[ 7: 0]; tx_data[239:232] <= dac_data_3_1[ 7: 0]; tx_data[231:224] <= dac_data_3_0[ 7: 0]; tx_data[223:216] <= dac_data_3_3[15: 8]; tx_data[215:208] <= dac_data_3_2[15: 8]; tx_data[207:200] <= dac_data_3_1[15: 8]; tx_data[199:192] <= dac_data_3_0[15: 8]; tx_data[191:184] <= dac_data_2_3[ 7: 0]; tx_data[183:176] <= dac_data_2_2[ 7: 0]; tx_data[175:168] <= dac_data_2_1[ 7: 0]; tx_data[167:160] <= dac_data_2_0[ 7: 0]; tx_data[159:152] <= dac_data_2_3[15: 8]; tx_data[151:144] <= dac_data_2_2[15: 8]; tx_data[143:136] <= dac_data_2_1[15: 8]; tx_data[135:128] <= dac_data_2_0[15: 8]; tx_data[127:120] <= dac_data_1_3[ 7: 0]; tx_data[119:112] <= dac_data_1_2[ 7: 0]; tx_data[111:104] <= dac_data_1_1[ 7: 0]; tx_data[103: 96] <= dac_data_1_0[ 7: 0]; tx_data[ 95: 88] <= dac_data_1_3[15: 8]; tx_data[ 87: 80] <= dac_data_1_2[15: 8]; tx_data[ 79: 72] <= dac_data_1_1[15: 8]; tx_data[ 71: 64] <= dac_data_1_0[15: 8]; tx_data[ 63: 56] <= dac_data_0_3[ 7: 0]; tx_data[ 55: 48] <= dac_data_0_2[ 7: 0]; tx_data[ 47: 40] <= dac_data_0_1[ 7: 0]; tx_data[ 39: 32] <= dac_data_0_0[ 7: 0]; tx_data[ 31: 24] <= dac_data_0_3[15: 8]; tx_data[ 23: 16] <= dac_data_0_2[15: 8]; tx_data[ 15: 8] <= dac_data_0_1[15: 8]; tx_data[ 7: 0] <= dac_data_0_0[15: 8]; end end endmodule // *************************************************************************** // ***************************************************************************

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__O21AI_FUNCTIONAL_PP_V `define SKY130_FD_SC_LP__O21AI_FUNCTIONAL_PP_V /** * o21ai: 2-input OR into first input of 2-input NAND. * * Y = !((A1 | A2) & B1) * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v" `celldefine module sky130_fd_sc_lp__o21ai ( Y , A1 , A2 , B1 , VPWR, VGND, VPB , VNB ); // Module ports output Y ; input A1 ; input A2 ; input B1 ; input VPWR; input VGND; input VPB ; input VNB ; // Local signals wire or0_out ; wire nand0_out_Y ; wire pwrgood_pp0_out_Y; // Name Output Other arguments or or0 (or0_out , A2, A1 ); nand nand0 (nand0_out_Y , B1, or0_out ); sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND); buf buf0 (Y , pwrgood_pp0_out_Y ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_LP__O21AI_FUNCTIONAL_PP_V

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Adam LLC // Engineer: Adam Michael // // Create Date: 15:07:21 09/17/2015 // Design Name: Manual Keypad Scanner and Encoder // Module Name: Lab2Part1Fall2015AJM ////////////////////////////////////////////////////////////////////////////////// module Lab2Part1Fall2015AJM(Rows, ClockIn, Load, Reset, RotateOnce, Columns, KeyNumberLEDs, ClockLocked); parameter LENGTH = 4; input [LENGTH-1:0] Rows; input ClockIn, Load, Reset, RotateOnce; output [LENGTH-1:0] Columns; output [LENGTH:0] KeyNumberLEDs; output ClockLocked; wire DebouncedShift, Rotate; Clock50MHz KeypadScanClock(ClockIn, Clock, ClockLocked); DebouncerWithoutLatch RotateOnceSwitch(RotateOnce, DebouncedRotate, Reset, Clock); ClockedOneShot RotateOnceUnit(DebouncedRotate, Rotate, Reset, Clock); ShiftReg4bits ColumnPattern(4'b1110, Clock, Load, Reset, Rotate, Columns); KeyEncoderAJM KeyMapUnit(Columns, Rows, KeyNumberLEDs); endmodule

// // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // // // // // Ports: // Name I/O size props // RDY_set_verbosity O 1 const // RDY_cpu_reset_server_request_put O 1 reg // cpu_reset_server_response_get O 1 reg // RDY_cpu_reset_server_response_get O 1 reg // cpu_imem_master_awvalid O 1 reg // cpu_imem_master_awid O 4 reg // cpu_imem_master_awaddr O 64 reg // cpu_imem_master_awlen O 8 reg // cpu_imem_master_awsize O 3 reg // cpu_imem_master_awburst O 2 reg // cpu_imem_master_awlock O 1 reg // cpu_imem_master_awcache O 4 reg // cpu_imem_master_awprot O 3 reg // cpu_imem_master_awqos O 4 reg // cpu_imem_master_awregion O 4 reg // cpu_imem_master_wvalid O 1 reg // cpu_imem_master_wdata O 64 reg // cpu_imem_master_wstrb O 8 reg // cpu_imem_master_wlast O 1 reg // cpu_imem_master_bready O 1 reg // cpu_imem_master_arvalid O 1 reg // cpu_imem_master_arid O 4 reg // cpu_imem_master_araddr O 64 reg // cpu_imem_master_arlen O 8 reg // cpu_imem_master_arsize O 3 reg // cpu_imem_master_arburst O 2 reg // cpu_imem_master_arlock O 1 reg // cpu_imem_master_arcache O 4 reg // cpu_imem_master_arprot O 3 reg // cpu_imem_master_arqos O 4 reg // cpu_imem_master_arregion O 4 reg // cpu_imem_master_rready O 1 reg // cpu_dmem_master_awvalid O 1 reg // cpu_dmem_master_awid O 4 reg // cpu_dmem_master_awaddr O 64 reg // cpu_dmem_master_awlen O 8 reg // cpu_dmem_master_awsize O 3 reg // cpu_dmem_master_awburst O 2 reg // cpu_dmem_master_awlock O 1 reg // cpu_dmem_master_awcache O 4 reg // cpu_dmem_master_awprot O 3 reg // cpu_dmem_master_awqos O 4 reg // cpu_dmem_master_awregion O 4 reg // cpu_dmem_master_wvalid O 1 reg // cpu_dmem_master_wdata O 64 reg // cpu_dmem_master_wstrb O 8 reg // cpu_dmem_master_wlast O 1 reg // cpu_dmem_master_bready O 1 reg // cpu_dmem_master_arvalid O 1 reg // cpu_dmem_master_arid O 4 reg // cpu_dmem_master_araddr O 64 reg // cpu_dmem_master_arlen O 8 reg // cpu_dmem_master_arsize O 3 reg // cpu_dmem_master_arburst O 2 reg // cpu_dmem_master_arlock O 1 reg // cpu_dmem_master_arcache O 4 reg // cpu_dmem_master_arprot O 3 reg // cpu_dmem_master_arqos O 4 reg // cpu_dmem_master_arregion O 4 reg // cpu_dmem_master_rready O 1 reg // RDY_set_watch_tohost O 1 const // CLK I 1 clock // RST_N I 1 reset // set_verbosity_verbosity I 4 reg // set_verbosity_logdelay I 64 reg // cpu_reset_server_request_put I 1 reg // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 // cpu_imem_master_bvalid I 1 // cpu_imem_master_bid I 4 reg // cpu_imem_master_bresp I 2 reg // cpu_imem_master_arready I 1 // cpu_imem_master_rvalid I 1 // cpu_imem_master_rid I 4 reg // cpu_imem_master_rdata I 64 reg // cpu_imem_master_rresp I 2 reg // cpu_imem_master_rlast I 1 reg // cpu_dmem_master_awready I 1 // cpu_dmem_master_wready I 1 // cpu_dmem_master_bvalid I 1 // cpu_dmem_master_bid I 4 reg // cpu_dmem_master_bresp I 2 reg // cpu_dmem_master_arready I 1 // cpu_dmem_master_rvalid I 1 // cpu_dmem_master_rid I 4 reg // cpu_dmem_master_rdata I 64 reg // cpu_dmem_master_rresp I 2 reg // cpu_dmem_master_rlast I 1 reg // core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 // nmi_req_set_not_clear I 1 // set_watch_tohost_watch_tohost I 1 unused // set_watch_tohost_tohost_addr I 64 unused // EN_set_verbosity I 1 // EN_cpu_reset_server_request_put I 1 // EN_set_watch_tohost I 1 unused // EN_cpu_reset_server_response_get I 1 // // No combinational paths from inputs to outputs // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module mkCore(CLK, RST_N, set_verbosity_verbosity, set_verbosity_logdelay, EN_set_verbosity, RDY_set_verbosity, cpu_reset_server_request_put, EN_cpu_reset_server_request_put, RDY_cpu_reset_server_request_put, EN_cpu_reset_server_response_get, cpu_reset_server_response_get, RDY_cpu_reset_server_response_get, cpu_imem_master_awvalid, cpu_imem_master_awid, cpu_imem_master_awaddr, cpu_imem_master_awlen, cpu_imem_master_awsize, cpu_imem_master_awburst, cpu_imem_master_awlock, cpu_imem_master_awcache, cpu_imem_master_awprot, cpu_imem_master_awqos, cpu_imem_master_awregion, cpu_imem_master_awready, cpu_imem_master_wvalid, cpu_imem_master_wdata, cpu_imem_master_wstrb, cpu_imem_master_wlast, cpu_imem_master_wready, cpu_imem_master_bvalid, cpu_imem_master_bid, cpu_imem_master_bresp, cpu_imem_master_bready, cpu_imem_master_arvalid, cpu_imem_master_arid, cpu_imem_master_araddr, cpu_imem_master_arlen, cpu_imem_master_arsize, cpu_imem_master_arburst, cpu_imem_master_arlock, cpu_imem_master_arcache, cpu_imem_master_arprot, cpu_imem_master_arqos, cpu_imem_master_arregion, cpu_imem_master_arready, cpu_imem_master_rvalid, cpu_imem_master_rid, cpu_imem_master_rdata, cpu_imem_master_rresp, cpu_imem_master_rlast, cpu_imem_master_rready, cpu_dmem_master_awvalid, cpu_dmem_master_awid, cpu_dmem_master_awaddr, cpu_dmem_master_awlen, cpu_dmem_master_awsize, cpu_dmem_master_awburst, cpu_dmem_master_awlock, cpu_dmem_master_awcache, cpu_dmem_master_awprot, cpu_dmem_master_awqos, cpu_dmem_master_awregion, cpu_dmem_master_awready, cpu_dmem_master_wvalid, cpu_dmem_master_wdata, cpu_dmem_master_wstrb, cpu_dmem_master_wlast, cpu_dmem_master_wready, cpu_dmem_master_bvalid, cpu_dmem_master_bid, cpu_dmem_master_bresp, cpu_dmem_master_bready, cpu_dmem_master_arvalid, cpu_dmem_master_arid, cpu_dmem_master_araddr, cpu_dmem_master_arlen, cpu_dmem_master_arsize, cpu_dmem_master_arburst, cpu_dmem_master_arlock, cpu_dmem_master_arcache, cpu_dmem_master_arprot, cpu_dmem_master_arqos, cpu_dmem_master_arregion, cpu_dmem_master_arready, cpu_dmem_master_rvalid, cpu_dmem_master_rid, cpu_dmem_master_rdata, cpu_dmem_master_rresp, cpu_dmem_master_rlast, cpu_dmem_master_rready, core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, nmi_req_set_not_clear, set_watch_tohost_watch_tohost, set_watch_tohost_tohost_addr, EN_set_watch_tohost, RDY_set_watch_tohost); input CLK; input RST_N; // action method set_verbosity input [3 : 0] set_verbosity_verbosity; input [63 : 0] set_verbosity_logdelay; input EN_set_verbosity; output RDY_set_verbosity; // action method cpu_reset_server_request_put input cpu_reset_server_request_put; input EN_cpu_reset_server_request_put; output RDY_cpu_reset_server_request_put; // actionvalue method cpu_reset_server_response_get input EN_cpu_reset_server_response_get; output cpu_reset_server_response_get; output RDY_cpu_reset_server_response_get; // value method cpu_imem_master_m_awvalid output cpu_imem_master_awvalid; // value method cpu_imem_master_m_awid output [3 : 0] cpu_imem_master_awid; // value method cpu_imem_master_m_awaddr output [63 : 0] cpu_imem_master_awaddr; // value method cpu_imem_master_m_awlen output [7 : 0] cpu_imem_master_awlen; // value method cpu_imem_master_m_awsize output [2 : 0] cpu_imem_master_awsize; // value method cpu_imem_master_m_awburst output [1 : 0] cpu_imem_master_awburst; // value method cpu_imem_master_m_awlock output cpu_imem_master_awlock; // value method cpu_imem_master_m_awcache output [3 : 0] cpu_imem_master_awcache; // value method cpu_imem_master_m_awprot output [2 : 0] cpu_imem_master_awprot; // value method cpu_imem_master_m_awqos output [3 : 0] cpu_imem_master_awqos; // value method cpu_imem_master_m_awregion output [3 : 0] cpu_imem_master_awregion; // value method cpu_imem_master_m_awuser // action method cpu_imem_master_m_awready input cpu_imem_master_awready; // value method cpu_imem_master_m_wvalid output cpu_imem_master_wvalid; // value method cpu_imem_master_m_wdata output [63 : 0] cpu_imem_master_wdata; // value method cpu_imem_master_m_wstrb output [7 : 0] cpu_imem_master_wstrb; // value method cpu_imem_master_m_wlast output cpu_imem_master_wlast; // value method cpu_imem_master_m_wuser // action method cpu_imem_master_m_wready input cpu_imem_master_wready; // action method cpu_imem_master_m_bvalid input cpu_imem_master_bvalid; input [3 : 0] cpu_imem_master_bid; input [1 : 0] cpu_imem_master_bresp; // value method cpu_imem_master_m_bready output cpu_imem_master_bready; // value method cpu_imem_master_m_arvalid output cpu_imem_master_arvalid; // value method cpu_imem_master_m_arid output [3 : 0] cpu_imem_master_arid; // value method cpu_imem_master_m_araddr output [63 : 0] cpu_imem_master_araddr; // value method cpu_imem_master_m_arlen output [7 : 0] cpu_imem_master_arlen; // value method cpu_imem_master_m_arsize output [2 : 0] cpu_imem_master_arsize; // value method cpu_imem_master_m_arburst output [1 : 0] cpu_imem_master_arburst; // value method cpu_imem_master_m_arlock output cpu_imem_master_arlock; // value method cpu_imem_master_m_arcache output [3 : 0] cpu_imem_master_arcache; // value method cpu_imem_master_m_arprot output [2 : 0] cpu_imem_master_arprot; // value method cpu_imem_master_m_arqos output [3 : 0] cpu_imem_master_arqos; // value method cpu_imem_master_m_arregion output [3 : 0] cpu_imem_master_arregion; // value method cpu_imem_master_m_aruser // action method cpu_imem_master_m_arready input cpu_imem_master_arready; // action method cpu_imem_master_m_rvalid input cpu_imem_master_rvalid; input [3 : 0] cpu_imem_master_rid; input [63 : 0] cpu_imem_master_rdata; input [1 : 0] cpu_imem_master_rresp; input cpu_imem_master_rlast; // value method cpu_imem_master_m_rready output cpu_imem_master_rready; // value method cpu_dmem_master_m_awvalid output cpu_dmem_master_awvalid; // value method cpu_dmem_master_m_awid output [3 : 0] cpu_dmem_master_awid; // value method cpu_dmem_master_m_awaddr output [63 : 0] cpu_dmem_master_awaddr; // value method cpu_dmem_master_m_awlen output [7 : 0] cpu_dmem_master_awlen; // value method cpu_dmem_master_m_awsize output [2 : 0] cpu_dmem_master_awsize; // value method cpu_dmem_master_m_awburst output [1 : 0] cpu_dmem_master_awburst; // value method cpu_dmem_master_m_awlock output cpu_dmem_master_awlock; // value method cpu_dmem_master_m_awcache output [3 : 0] cpu_dmem_master_awcache; // value method cpu_dmem_master_m_awprot output [2 : 0] cpu_dmem_master_awprot; // value method cpu_dmem_master_m_awqos output [3 : 0] cpu_dmem_master_awqos; // value method cpu_dmem_master_m_awregion output [3 : 0] cpu_dmem_master_awregion; // value method cpu_dmem_master_m_awuser // action method cpu_dmem_master_m_awready input cpu_dmem_master_awready; // value method cpu_dmem_master_m_wvalid output cpu_dmem_master_wvalid; // value method cpu_dmem_master_m_wdata output [63 : 0] cpu_dmem_master_wdata; // value method cpu_dmem_master_m_wstrb output [7 : 0] cpu_dmem_master_wstrb; // value method cpu_dmem_master_m_wlast output cpu_dmem_master_wlast; // value method cpu_dmem_master_m_wuser // action method cpu_dmem_master_m_wready input cpu_dmem_master_wready; // action method cpu_dmem_master_m_bvalid input cpu_dmem_master_bvalid; input [3 : 0] cpu_dmem_master_bid; input [1 : 0] cpu_dmem_master_bresp; // value method cpu_dmem_master_m_bready output cpu_dmem_master_bready; // value method cpu_dmem_master_m_arvalid output cpu_dmem_master_arvalid; // value method cpu_dmem_master_m_arid output [3 : 0] cpu_dmem_master_arid; // value method cpu_dmem_master_m_araddr output [63 : 0] cpu_dmem_master_araddr; // value method cpu_dmem_master_m_arlen output [7 : 0] cpu_dmem_master_arlen; // value method cpu_dmem_master_m_arsize output [2 : 0] cpu_dmem_master_arsize; // value method cpu_dmem_master_m_arburst output [1 : 0] cpu_dmem_master_arburst; // value method cpu_dmem_master_m_arlock output cpu_dmem_master_arlock; // value method cpu_dmem_master_m_arcache output [3 : 0] cpu_dmem_master_arcache; // value method cpu_dmem_master_m_arprot output [2 : 0] cpu_dmem_master_arprot; // value method cpu_dmem_master_m_arqos output [3 : 0] cpu_dmem_master_arqos; // value method cpu_dmem_master_m_arregion output [3 : 0] cpu_dmem_master_arregion; // value method cpu_dmem_master_m_aruser // action method cpu_dmem_master_m_arready input cpu_dmem_master_arready; // action method cpu_dmem_master_m_rvalid input cpu_dmem_master_rvalid; input [3 : 0] cpu_dmem_master_rid; input [63 : 0] cpu_dmem_master_rdata; input [1 : 0] cpu_dmem_master_rresp; input cpu_dmem_master_rlast; // value method cpu_dmem_master_m_rready output cpu_dmem_master_rready; // action method core_external_interrupt_sources_0_m_interrupt_req input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_1_m_interrupt_req input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_2_m_interrupt_req input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_3_m_interrupt_req input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_4_m_interrupt_req input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_5_m_interrupt_req input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_6_m_interrupt_req input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_7_m_interrupt_req input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_8_m_interrupt_req input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_9_m_interrupt_req input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_10_m_interrupt_req input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_11_m_interrupt_req input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_12_m_interrupt_req input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_13_m_interrupt_req input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_14_m_interrupt_req input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_15_m_interrupt_req input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; // action method nmi_req input nmi_req_set_not_clear; // action method set_watch_tohost input set_watch_tohost_watch_tohost; input [63 : 0] set_watch_tohost_tohost_addr; input EN_set_watch_tohost; output RDY_set_watch_tohost; // signals for module outputs wire [63 : 0] cpu_dmem_master_araddr, cpu_dmem_master_awaddr, cpu_dmem_master_wdata, cpu_imem_master_araddr, cpu_imem_master_awaddr, cpu_imem_master_wdata; wire [7 : 0] cpu_dmem_master_arlen, cpu_dmem_master_awlen, cpu_dmem_master_wstrb, cpu_imem_master_arlen, cpu_imem_master_awlen, cpu_imem_master_wstrb; wire [3 : 0] cpu_dmem_master_arcache, cpu_dmem_master_arid, cpu_dmem_master_arqos, cpu_dmem_master_arregion, cpu_dmem_master_awcache, cpu_dmem_master_awid, cpu_dmem_master_awqos, cpu_dmem_master_awregion, cpu_imem_master_arcache, cpu_imem_master_arid, cpu_imem_master_arqos, cpu_imem_master_arregion, cpu_imem_master_awcache, cpu_imem_master_awid, cpu_imem_master_awqos, cpu_imem_master_awregion; wire [2 : 0] cpu_dmem_master_arprot, cpu_dmem_master_arsize, cpu_dmem_master_awprot, cpu_dmem_master_awsize, cpu_imem_master_arprot, cpu_imem_master_arsize, cpu_imem_master_awprot, cpu_imem_master_awsize; wire [1 : 0] cpu_dmem_master_arburst, cpu_dmem_master_awburst, cpu_imem_master_arburst, cpu_imem_master_awburst; wire RDY_cpu_reset_server_request_put, RDY_cpu_reset_server_response_get, RDY_set_verbosity, RDY_set_watch_tohost, cpu_dmem_master_arlock, cpu_dmem_master_arvalid, cpu_dmem_master_awlock, cpu_dmem_master_awvalid, cpu_dmem_master_bready, cpu_dmem_master_rready, cpu_dmem_master_wlast, cpu_dmem_master_wvalid, cpu_imem_master_arlock, cpu_imem_master_arvalid, cpu_imem_master_awlock, cpu_imem_master_awvalid, cpu_imem_master_bready, cpu_imem_master_rready, cpu_imem_master_wlast, cpu_imem_master_wvalid, cpu_reset_server_response_get; // ports of submodule cpu wire [63 : 0] cpu$dmem_master_araddr, cpu$dmem_master_awaddr, cpu$dmem_master_rdata, cpu$dmem_master_wdata, cpu$imem_master_araddr, cpu$imem_master_awaddr, cpu$imem_master_rdata, cpu$imem_master_wdata, cpu$set_verbosity_logdelay, cpu$set_watch_tohost_tohost_addr; wire [7 : 0] cpu$dmem_master_arlen, cpu$dmem_master_awlen, cpu$dmem_master_wstrb, cpu$imem_master_arlen, cpu$imem_master_awlen, cpu$imem_master_wstrb; wire [3 : 0] cpu$dmem_master_arcache, cpu$dmem_master_arid, cpu$dmem_master_arqos, cpu$dmem_master_arregion, cpu$dmem_master_awcache, cpu$dmem_master_awid, cpu$dmem_master_awqos, cpu$dmem_master_awregion, cpu$dmem_master_bid, cpu$dmem_master_rid, cpu$imem_master_arcache, cpu$imem_master_arid, cpu$imem_master_arqos, cpu$imem_master_arregion, cpu$imem_master_awcache, cpu$imem_master_awid, cpu$imem_master_awqos, cpu$imem_master_awregion, cpu$imem_master_bid, cpu$imem_master_rid, cpu$set_verbosity_verbosity; wire [2 : 0] cpu$dmem_master_arprot, cpu$dmem_master_arsize, cpu$dmem_master_awprot, cpu$dmem_master_awsize, cpu$imem_master_arprot, cpu$imem_master_arsize, cpu$imem_master_awprot, cpu$imem_master_awsize; wire [1 : 0] cpu$dmem_master_arburst, cpu$dmem_master_awburst, cpu$dmem_master_bresp, cpu$dmem_master_rresp, cpu$imem_master_arburst, cpu$imem_master_awburst, cpu$imem_master_bresp, cpu$imem_master_rresp; wire cpu$EN_hart0_server_reset_request_put, cpu$EN_hart0_server_reset_response_get, cpu$EN_set_verbosity, cpu$EN_set_watch_tohost, cpu$RDY_hart0_server_reset_request_put, cpu$RDY_hart0_server_reset_response_get, cpu$dmem_master_arlock, cpu$dmem_master_arready, cpu$dmem_master_arvalid, cpu$dmem_master_awlock, cpu$dmem_master_awready, cpu$dmem_master_awvalid, cpu$dmem_master_bready, cpu$dmem_master_bvalid, cpu$dmem_master_rlast, cpu$dmem_master_rready, cpu$dmem_master_rvalid, cpu$dmem_master_wlast, cpu$dmem_master_wready, cpu$dmem_master_wvalid, cpu$hart0_server_reset_request_put, cpu$hart0_server_reset_response_get, cpu$imem_master_arlock, cpu$imem_master_arready, cpu$imem_master_arvalid, cpu$imem_master_awlock, cpu$imem_master_awready, cpu$imem_master_awvalid, cpu$imem_master_bready, cpu$imem_master_bvalid, cpu$imem_master_rlast, cpu$imem_master_rready, cpu$imem_master_rvalid, cpu$imem_master_wlast, cpu$imem_master_wready, cpu$imem_master_wvalid, cpu$m_external_interrupt_req_set_not_clear, cpu$nmi_req_set_not_clear, cpu$s_external_interrupt_req_set_not_clear, cpu$set_watch_tohost_watch_tohost, cpu$software_interrupt_req_set_not_clear, cpu$timer_interrupt_req_set_not_clear; // ports of submodule f_reset_reqs wire f_reset_reqs$CLR, f_reset_reqs$DEQ, f_reset_reqs$D_IN, f_reset_reqs$D_OUT, f_reset_reqs$EMPTY_N, f_reset_reqs$ENQ, f_reset_reqs$FULL_N; // ports of submodule f_reset_rsps wire f_reset_rsps$CLR, f_reset_rsps$DEQ, f_reset_rsps$D_IN, f_reset_rsps$D_OUT, f_reset_rsps$EMPTY_N, f_reset_rsps$ENQ, f_reset_rsps$FULL_N; // ports of submodule fabric_2x3 wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, fabric_2x3$v_from_masters_0_awaddr, fabric_2x3$v_from_masters_0_rdata, fabric_2x3$v_from_masters_0_wdata, fabric_2x3$v_from_masters_1_araddr, fabric_2x3$v_from_masters_1_awaddr, fabric_2x3$v_from_masters_1_wdata, fabric_2x3$v_to_slaves_0_araddr, fabric_2x3$v_to_slaves_0_awaddr, fabric_2x3$v_to_slaves_0_rdata, fabric_2x3$v_to_slaves_0_wdata, fabric_2x3$v_to_slaves_1_araddr, fabric_2x3$v_to_slaves_1_awaddr, fabric_2x3$v_to_slaves_1_rdata, fabric_2x3$v_to_slaves_1_wdata, fabric_2x3$v_to_slaves_2_araddr, fabric_2x3$v_to_slaves_2_awaddr, fabric_2x3$v_to_slaves_2_rdata, fabric_2x3$v_to_slaves_2_wdata; wire [7 : 0] fabric_2x3$v_from_masters_0_arlen, fabric_2x3$v_from_masters_0_awlen, fabric_2x3$v_from_masters_0_wstrb, fabric_2x3$v_from_masters_1_arlen, fabric_2x3$v_from_masters_1_awlen, fabric_2x3$v_from_masters_1_wstrb, fabric_2x3$v_to_slaves_0_arlen, fabric_2x3$v_to_slaves_0_awlen, fabric_2x3$v_to_slaves_0_wstrb, fabric_2x3$v_to_slaves_1_arlen, fabric_2x3$v_to_slaves_1_awlen, fabric_2x3$v_to_slaves_1_wstrb, fabric_2x3$v_to_slaves_2_arlen, fabric_2x3$v_to_slaves_2_awlen, fabric_2x3$v_to_slaves_2_wstrb; wire [3 : 0] fabric_2x3$set_verbosity_verbosity, fabric_2x3$v_from_masters_0_arcache, fabric_2x3$v_from_masters_0_arid, fabric_2x3$v_from_masters_0_arqos, fabric_2x3$v_from_masters_0_arregion, fabric_2x3$v_from_masters_0_awcache, fabric_2x3$v_from_masters_0_awid, fabric_2x3$v_from_masters_0_awqos, fabric_2x3$v_from_masters_0_awregion, fabric_2x3$v_from_masters_0_bid, fabric_2x3$v_from_masters_0_rid, fabric_2x3$v_from_masters_1_arcache, fabric_2x3$v_from_masters_1_arid, fabric_2x3$v_from_masters_1_arqos, fabric_2x3$v_from_masters_1_arregion, fabric_2x3$v_from_masters_1_awcache, fabric_2x3$v_from_masters_1_awid, fabric_2x3$v_from_masters_1_awqos, fabric_2x3$v_from_masters_1_awregion, fabric_2x3$v_to_slaves_0_arcache, fabric_2x3$v_to_slaves_0_arid, fabric_2x3$v_to_slaves_0_arqos, fabric_2x3$v_to_slaves_0_arregion, fabric_2x3$v_to_slaves_0_awcache, fabric_2x3$v_to_slaves_0_awid, fabric_2x3$v_to_slaves_0_awqos, fabric_2x3$v_to_slaves_0_awregion, fabric_2x3$v_to_slaves_0_bid, fabric_2x3$v_to_slaves_0_rid, fabric_2x3$v_to_slaves_1_arcache, fabric_2x3$v_to_slaves_1_arid, fabric_2x3$v_to_slaves_1_arqos, fabric_2x3$v_to_slaves_1_arregion, fabric_2x3$v_to_slaves_1_awcache, fabric_2x3$v_to_slaves_1_awid, fabric_2x3$v_to_slaves_1_awqos, fabric_2x3$v_to_slaves_1_awregion, fabric_2x3$v_to_slaves_1_bid, fabric_2x3$v_to_slaves_1_rid, fabric_2x3$v_to_slaves_2_arcache, fabric_2x3$v_to_slaves_2_arid, fabric_2x3$v_to_slaves_2_arqos, fabric_2x3$v_to_slaves_2_arregion, fabric_2x3$v_to_slaves_2_awcache, fabric_2x3$v_to_slaves_2_awid, fabric_2x3$v_to_slaves_2_awqos, fabric_2x3$v_to_slaves_2_awregion, fabric_2x3$v_to_slaves_2_bid, fabric_2x3$v_to_slaves_2_rid; wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, fabric_2x3$v_from_masters_0_arsize, fabric_2x3$v_from_masters_0_awprot, fabric_2x3$v_from_masters_0_awsize, fabric_2x3$v_from_masters_1_arprot, fabric_2x3$v_from_masters_1_arsize, fabric_2x3$v_from_masters_1_awprot, fabric_2x3$v_from_masters_1_awsize, fabric_2x3$v_to_slaves_0_arprot, fabric_2x3$v_to_slaves_0_arsize, fabric_2x3$v_to_slaves_0_awprot, fabric_2x3$v_to_slaves_0_awsize, fabric_2x3$v_to_slaves_1_arprot, fabric_2x3$v_to_slaves_1_arsize, fabric_2x3$v_to_slaves_1_awprot, fabric_2x3$v_to_slaves_1_awsize, fabric_2x3$v_to_slaves_2_arprot, fabric_2x3$v_to_slaves_2_arsize, fabric_2x3$v_to_slaves_2_awprot, fabric_2x3$v_to_slaves_2_awsize; wire [1 : 0] fabric_2x3$v_from_masters_0_arburst, fabric_2x3$v_from_masters_0_awburst, fabric_2x3$v_from_masters_0_bresp, fabric_2x3$v_from_masters_0_rresp, fabric_2x3$v_from_masters_1_arburst, fabric_2x3$v_from_masters_1_awburst, fabric_2x3$v_to_slaves_0_arburst, fabric_2x3$v_to_slaves_0_awburst, fabric_2x3$v_to_slaves_0_bresp, fabric_2x3$v_to_slaves_0_rresp, fabric_2x3$v_to_slaves_1_arburst, fabric_2x3$v_to_slaves_1_awburst, fabric_2x3$v_to_slaves_1_bresp, fabric_2x3$v_to_slaves_1_rresp, fabric_2x3$v_to_slaves_2_arburst, fabric_2x3$v_to_slaves_2_awburst, fabric_2x3$v_to_slaves_2_bresp, fabric_2x3$v_to_slaves_2_rresp; wire fabric_2x3$EN_reset, fabric_2x3$EN_set_verbosity, fabric_2x3$RDY_reset, fabric_2x3$v_from_masters_0_arlock, fabric_2x3$v_from_masters_0_arready, fabric_2x3$v_from_masters_0_arvalid, fabric_2x3$v_from_masters_0_awlock, fabric_2x3$v_from_masters_0_awready, fabric_2x3$v_from_masters_0_awvalid, fabric_2x3$v_from_masters_0_bready, fabric_2x3$v_from_masters_0_bvalid, fabric_2x3$v_from_masters_0_rlast, fabric_2x3$v_from_masters_0_rready, fabric_2x3$v_from_masters_0_rvalid, fabric_2x3$v_from_masters_0_wlast, fabric_2x3$v_from_masters_0_wready, fabric_2x3$v_from_masters_0_wvalid, fabric_2x3$v_from_masters_1_arlock, fabric_2x3$v_from_masters_1_arvalid, fabric_2x3$v_from_masters_1_awlock, fabric_2x3$v_from_masters_1_awvalid, fabric_2x3$v_from_masters_1_bready, fabric_2x3$v_from_masters_1_rready, fabric_2x3$v_from_masters_1_wlast, fabric_2x3$v_from_masters_1_wvalid, fabric_2x3$v_to_slaves_0_arlock, fabric_2x3$v_to_slaves_0_arready, fabric_2x3$v_to_slaves_0_arvalid, fabric_2x3$v_to_slaves_0_awlock, fabric_2x3$v_to_slaves_0_awready, fabric_2x3$v_to_slaves_0_awvalid, fabric_2x3$v_to_slaves_0_bready, fabric_2x3$v_to_slaves_0_bvalid, fabric_2x3$v_to_slaves_0_rlast, fabric_2x3$v_to_slaves_0_rready, fabric_2x3$v_to_slaves_0_rvalid, fabric_2x3$v_to_slaves_0_wlast, fabric_2x3$v_to_slaves_0_wready, fabric_2x3$v_to_slaves_0_wvalid, fabric_2x3$v_to_slaves_1_arlock, fabric_2x3$v_to_slaves_1_arready, fabric_2x3$v_to_slaves_1_arvalid, fabric_2x3$v_to_slaves_1_awlock, fabric_2x3$v_to_slaves_1_awready, fabric_2x3$v_to_slaves_1_awvalid, fabric_2x3$v_to_slaves_1_bready, fabric_2x3$v_to_slaves_1_bvalid, fabric_2x3$v_to_slaves_1_rlast, fabric_2x3$v_to_slaves_1_rready, fabric_2x3$v_to_slaves_1_rvalid, fabric_2x3$v_to_slaves_1_wlast, fabric_2x3$v_to_slaves_1_wready, fabric_2x3$v_to_slaves_1_wvalid, fabric_2x3$v_to_slaves_2_arlock, fabric_2x3$v_to_slaves_2_arready, fabric_2x3$v_to_slaves_2_arvalid, fabric_2x3$v_to_slaves_2_awlock, fabric_2x3$v_to_slaves_2_awready, fabric_2x3$v_to_slaves_2_awvalid, fabric_2x3$v_to_slaves_2_bready, fabric_2x3$v_to_slaves_2_bvalid, fabric_2x3$v_to_slaves_2_rlast, fabric_2x3$v_to_slaves_2_rready, fabric_2x3$v_to_slaves_2_rvalid, fabric_2x3$v_to_slaves_2_wlast, fabric_2x3$v_to_slaves_2_wready, fabric_2x3$v_to_slaves_2_wvalid; // ports of submodule near_mem_io wire [63 : 0] near_mem_io$axi4_slave_araddr, near_mem_io$axi4_slave_awaddr, near_mem_io$axi4_slave_rdata, near_mem_io$axi4_slave_wdata, near_mem_io$set_addr_map_addr_base, near_mem_io$set_addr_map_addr_lim; wire [7 : 0] near_mem_io$axi4_slave_arlen, near_mem_io$axi4_slave_awlen, near_mem_io$axi4_slave_wstrb; wire [3 : 0] near_mem_io$axi4_slave_arcache, near_mem_io$axi4_slave_arid, near_mem_io$axi4_slave_arqos, near_mem_io$axi4_slave_arregion, near_mem_io$axi4_slave_awcache, near_mem_io$axi4_slave_awid, near_mem_io$axi4_slave_awqos, near_mem_io$axi4_slave_awregion, near_mem_io$axi4_slave_bid, near_mem_io$axi4_slave_rid; wire [2 : 0] near_mem_io$axi4_slave_arprot, near_mem_io$axi4_slave_arsize, near_mem_io$axi4_slave_awprot, near_mem_io$axi4_slave_awsize; wire [1 : 0] near_mem_io$axi4_slave_arburst, near_mem_io$axi4_slave_awburst, near_mem_io$axi4_slave_bresp, near_mem_io$axi4_slave_rresp; wire near_mem_io$EN_get_sw_interrupt_req_get, near_mem_io$EN_get_timer_interrupt_req_get, near_mem_io$EN_server_reset_request_put, near_mem_io$EN_server_reset_response_get, near_mem_io$EN_set_addr_map, near_mem_io$RDY_get_sw_interrupt_req_get, near_mem_io$RDY_get_timer_interrupt_req_get, near_mem_io$RDY_server_reset_request_put, near_mem_io$RDY_server_reset_response_get, near_mem_io$axi4_slave_arlock, near_mem_io$axi4_slave_arready, near_mem_io$axi4_slave_arvalid, near_mem_io$axi4_slave_awlock, near_mem_io$axi4_slave_awready, near_mem_io$axi4_slave_awvalid, near_mem_io$axi4_slave_bready, near_mem_io$axi4_slave_bvalid, near_mem_io$axi4_slave_rlast, near_mem_io$axi4_slave_rready, near_mem_io$axi4_slave_rvalid, near_mem_io$axi4_slave_wlast, near_mem_io$axi4_slave_wready, near_mem_io$axi4_slave_wvalid, near_mem_io$get_sw_interrupt_req_get, near_mem_io$get_timer_interrupt_req_get; // ports of submodule plic wire [63 : 0] plic$axi4_slave_araddr, plic$axi4_slave_awaddr, plic$axi4_slave_rdata, plic$axi4_slave_wdata, plic$set_addr_map_addr_base, plic$set_addr_map_addr_lim; wire [7 : 0] plic$axi4_slave_arlen, plic$axi4_slave_awlen, plic$axi4_slave_wstrb; wire [3 : 0] plic$axi4_slave_arcache, plic$axi4_slave_arid, plic$axi4_slave_arqos, plic$axi4_slave_arregion, plic$axi4_slave_awcache, plic$axi4_slave_awid, plic$axi4_slave_awqos, plic$axi4_slave_awregion, plic$axi4_slave_bid, plic$axi4_slave_rid, plic$set_verbosity_verbosity; wire [2 : 0] plic$axi4_slave_arprot, plic$axi4_slave_arsize, plic$axi4_slave_awprot, plic$axi4_slave_awsize; wire [1 : 0] plic$axi4_slave_arburst, plic$axi4_slave_awburst, plic$axi4_slave_bresp, plic$axi4_slave_rresp; wire plic$EN_server_reset_request_put, plic$EN_server_reset_response_get, plic$EN_set_addr_map, plic$EN_set_verbosity, plic$EN_show_PLIC_state, plic$RDY_server_reset_request_put, plic$RDY_server_reset_response_get, plic$axi4_slave_arlock, plic$axi4_slave_arready, plic$axi4_slave_arvalid, plic$axi4_slave_awlock, plic$axi4_slave_awready, plic$axi4_slave_awvalid, plic$axi4_slave_bready, plic$axi4_slave_bvalid, plic$axi4_slave_rlast, plic$axi4_slave_rready, plic$axi4_slave_rvalid, plic$axi4_slave_wlast, plic$axi4_slave_wready, plic$axi4_slave_wvalid, plic$v_sources_0_m_interrupt_req_set_not_clear, plic$v_sources_10_m_interrupt_req_set_not_clear, plic$v_sources_11_m_interrupt_req_set_not_clear, plic$v_sources_12_m_interrupt_req_set_not_clear, plic$v_sources_13_m_interrupt_req_set_not_clear, plic$v_sources_14_m_interrupt_req_set_not_clear, plic$v_sources_15_m_interrupt_req_set_not_clear, plic$v_sources_1_m_interrupt_req_set_not_clear, plic$v_sources_2_m_interrupt_req_set_not_clear, plic$v_sources_3_m_interrupt_req_set_not_clear, plic$v_sources_4_m_interrupt_req_set_not_clear, plic$v_sources_5_m_interrupt_req_set_not_clear, plic$v_sources_6_m_interrupt_req_set_not_clear, plic$v_sources_7_m_interrupt_req_set_not_clear, plic$v_sources_8_m_interrupt_req_set_not_clear, plic$v_sources_9_m_interrupt_req_set_not_clear, plic$v_targets_0_m_eip, plic$v_targets_1_m_eip; // ports of submodule soc_map wire [63 : 0] soc_map$m_is_IO_addr_addr, soc_map$m_is_mem_addr_addr, soc_map$m_is_near_mem_IO_addr_addr, soc_map$m_near_mem_io_addr_base, soc_map$m_near_mem_io_addr_lim, soc_map$m_plic_addr_base, soc_map$m_plic_addr_lim; // rule scheduling signals wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete, CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, CAN_FIRE_RL_rl_rd_addr_channel, CAN_FIRE_RL_rl_rd_addr_channel_1, CAN_FIRE_RL_rl_rd_addr_channel_2, CAN_FIRE_RL_rl_rd_addr_channel_3, CAN_FIRE_RL_rl_rd_data_channel, CAN_FIRE_RL_rl_rd_data_channel_1, CAN_FIRE_RL_rl_rd_data_channel_2, CAN_FIRE_RL_rl_rd_data_channel_3, CAN_FIRE_RL_rl_relay_external_interrupts, CAN_FIRE_RL_rl_relay_sw_interrupts, CAN_FIRE_RL_rl_relay_timer_interrupts, CAN_FIRE_RL_rl_wr_addr_channel, CAN_FIRE_RL_rl_wr_addr_channel_1, CAN_FIRE_RL_rl_wr_addr_channel_2, CAN_FIRE_RL_rl_wr_addr_channel_3, CAN_FIRE_RL_rl_wr_data_channel, CAN_FIRE_RL_rl_wr_data_channel_1, CAN_FIRE_RL_rl_wr_data_channel_2, CAN_FIRE_RL_rl_wr_data_channel_3, CAN_FIRE_RL_rl_wr_response_channel, CAN_FIRE_RL_rl_wr_response_channel_1, CAN_FIRE_RL_rl_wr_response_channel_2, CAN_FIRE_RL_rl_wr_response_channel_3, CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, CAN_FIRE_cpu_dmem_master_m_arready, CAN_FIRE_cpu_dmem_master_m_awready, CAN_FIRE_cpu_dmem_master_m_bvalid, CAN_FIRE_cpu_dmem_master_m_rvalid, CAN_FIRE_cpu_dmem_master_m_wready, CAN_FIRE_cpu_imem_master_m_arready, CAN_FIRE_cpu_imem_master_m_awready, CAN_FIRE_cpu_imem_master_m_bvalid, CAN_FIRE_cpu_imem_master_m_rvalid, CAN_FIRE_cpu_imem_master_m_wready, CAN_FIRE_cpu_reset_server_request_put, CAN_FIRE_cpu_reset_server_response_get, CAN_FIRE_nmi_req, CAN_FIRE_set_verbosity, CAN_FIRE_set_watch_tohost, WILL_FIRE_RL_rl_cpu_hart0_reset_complete, WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, WILL_FIRE_RL_rl_rd_addr_channel, WILL_FIRE_RL_rl_rd_addr_channel_1, WILL_FIRE_RL_rl_rd_addr_channel_2, WILL_FIRE_RL_rl_rd_addr_channel_3, WILL_FIRE_RL_rl_rd_data_channel, WILL_FIRE_RL_rl_rd_data_channel_1, WILL_FIRE_RL_rl_rd_data_channel_2, WILL_FIRE_RL_rl_rd_data_channel_3, WILL_FIRE_RL_rl_relay_external_interrupts, WILL_FIRE_RL_rl_relay_sw_interrupts, WILL_FIRE_RL_rl_relay_timer_interrupts, WILL_FIRE_RL_rl_wr_addr_channel, WILL_FIRE_RL_rl_wr_addr_channel_1, WILL_FIRE_RL_rl_wr_addr_channel_2, WILL_FIRE_RL_rl_wr_addr_channel_3, WILL_FIRE_RL_rl_wr_data_channel, WILL_FIRE_RL_rl_wr_data_channel_1, WILL_FIRE_RL_rl_wr_data_channel_2, WILL_FIRE_RL_rl_wr_data_channel_3, WILL_FIRE_RL_rl_wr_response_channel, WILL_FIRE_RL_rl_wr_response_channel_1, WILL_FIRE_RL_rl_wr_response_channel_2, WILL_FIRE_RL_rl_wr_response_channel_3, WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, WILL_FIRE_cpu_dmem_master_m_arready, WILL_FIRE_cpu_dmem_master_m_awready, WILL_FIRE_cpu_dmem_master_m_bvalid, WILL_FIRE_cpu_dmem_master_m_rvalid, WILL_FIRE_cpu_dmem_master_m_wready, WILL_FIRE_cpu_imem_master_m_arready, WILL_FIRE_cpu_imem_master_m_awready, WILL_FIRE_cpu_imem_master_m_bvalid, WILL_FIRE_cpu_imem_master_m_rvalid, WILL_FIRE_cpu_imem_master_m_wready, WILL_FIRE_cpu_reset_server_request_put, WILL_FIRE_cpu_reset_server_response_get, WILL_FIRE_nmi_req, WILL_FIRE_set_verbosity, WILL_FIRE_set_watch_tohost; // declarations used by system tasks // synopsys translate_off reg [31 : 0] v__h4255; reg [31 : 0] v__h4496; reg [31 : 0] v__h4249; reg [31 : 0] v__h4490; // synopsys translate_on // remaining internal signals wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8; // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; assign CAN_FIRE_set_verbosity = 1'd1 ; assign WILL_FIRE_set_verbosity = EN_set_verbosity ; // action method cpu_reset_server_request_put assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; assign WILL_FIRE_cpu_reset_server_request_put = EN_cpu_reset_server_request_put ; // actionvalue method cpu_reset_server_response_get assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ; assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; assign WILL_FIRE_cpu_reset_server_response_get = EN_cpu_reset_server_response_get ; // value method cpu_imem_master_m_awvalid assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; // value method cpu_imem_master_m_awid assign cpu_imem_master_awid = cpu$imem_master_awid ; // value method cpu_imem_master_m_awaddr assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ; // value method cpu_imem_master_m_awlen assign cpu_imem_master_awlen = cpu$imem_master_awlen ; // value method cpu_imem_master_m_awsize assign cpu_imem_master_awsize = cpu$imem_master_awsize ; // value method cpu_imem_master_m_awburst assign cpu_imem_master_awburst = cpu$imem_master_awburst ; // value method cpu_imem_master_m_awlock assign cpu_imem_master_awlock = cpu$imem_master_awlock ; // value method cpu_imem_master_m_awcache assign cpu_imem_master_awcache = cpu$imem_master_awcache ; // value method cpu_imem_master_m_awprot assign cpu_imem_master_awprot = cpu$imem_master_awprot ; // value method cpu_imem_master_m_awqos assign cpu_imem_master_awqos = cpu$imem_master_awqos ; // value method cpu_imem_master_m_awregion assign cpu_imem_master_awregion = cpu$imem_master_awregion ; // action method cpu_imem_master_m_awready assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ; assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ; // value method cpu_imem_master_m_wvalid assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; // value method cpu_imem_master_m_wdata assign cpu_imem_master_wdata = cpu$imem_master_wdata ; // value method cpu_imem_master_m_wstrb assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ; // value method cpu_imem_master_m_wlast assign cpu_imem_master_wlast = cpu$imem_master_wlast ; // action method cpu_imem_master_m_wready assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ; assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ; // action method cpu_imem_master_m_bvalid assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; // value method cpu_imem_master_m_bready assign cpu_imem_master_bready = cpu$imem_master_bready ; // value method cpu_imem_master_m_arvalid assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; // value method cpu_imem_master_m_arid assign cpu_imem_master_arid = cpu$imem_master_arid ; // value method cpu_imem_master_m_araddr assign cpu_imem_master_araddr = cpu$imem_master_araddr ; // value method cpu_imem_master_m_arlen assign cpu_imem_master_arlen = cpu$imem_master_arlen ; // value method cpu_imem_master_m_arsize assign cpu_imem_master_arsize = cpu$imem_master_arsize ; // value method cpu_imem_master_m_arburst assign cpu_imem_master_arburst = cpu$imem_master_arburst ; // value method cpu_imem_master_m_arlock assign cpu_imem_master_arlock = cpu$imem_master_arlock ; // value method cpu_imem_master_m_arcache assign cpu_imem_master_arcache = cpu$imem_master_arcache ; // value method cpu_imem_master_m_arprot assign cpu_imem_master_arprot = cpu$imem_master_arprot ; // value method cpu_imem_master_m_arqos assign cpu_imem_master_arqos = cpu$imem_master_arqos ; // value method cpu_imem_master_m_arregion assign cpu_imem_master_arregion = cpu$imem_master_arregion ; // action method cpu_imem_master_m_arready assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ; assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ; // action method cpu_imem_master_m_rvalid assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; // value method cpu_imem_master_m_rready assign cpu_imem_master_rready = cpu$imem_master_rready ; // value method cpu_dmem_master_m_awvalid assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ; // value method cpu_dmem_master_m_awid assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ; // value method cpu_dmem_master_m_awaddr assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ; // value method cpu_dmem_master_m_awlen assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ; // value method cpu_dmem_master_m_awsize assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ; // value method cpu_dmem_master_m_awburst assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ; // value method cpu_dmem_master_m_awlock assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ; // value method cpu_dmem_master_m_awcache assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ; // value method cpu_dmem_master_m_awprot assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ; // value method cpu_dmem_master_m_awqos assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ; // value method cpu_dmem_master_m_awregion assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ; // action method cpu_dmem_master_m_awready assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ; assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ; // value method cpu_dmem_master_m_wvalid assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; // value method cpu_dmem_master_m_wdata assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; // value method cpu_dmem_master_m_wstrb assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ; // value method cpu_dmem_master_m_wlast assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ; // action method cpu_dmem_master_m_wready assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ; assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ; // action method cpu_dmem_master_m_bvalid assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; // value method cpu_dmem_master_m_bready assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ; // value method cpu_dmem_master_m_arvalid assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ; // value method cpu_dmem_master_m_arid assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ; // value method cpu_dmem_master_m_araddr assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ; // value method cpu_dmem_master_m_arlen assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ; // value method cpu_dmem_master_m_arsize assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ; // value method cpu_dmem_master_m_arburst assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ; // value method cpu_dmem_master_m_arlock assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ; // value method cpu_dmem_master_m_arcache assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ; // value method cpu_dmem_master_m_arprot assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ; // value method cpu_dmem_master_m_arqos assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ; // value method cpu_dmem_master_m_arregion assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ; // action method cpu_dmem_master_m_arready assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ; assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ; // action method cpu_dmem_master_m_rvalid assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; // value method cpu_dmem_master_m_rready assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ; // action method core_external_interrupt_sources_0_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_1_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_2_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_3_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_4_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_5_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_6_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_7_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_8_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_9_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_10_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_11_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_12_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_13_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_14_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_15_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; // action method nmi_req assign CAN_FIRE_nmi_req = 1'd1 ; assign WILL_FIRE_nmi_req = 1'd1 ; // action method set_watch_tohost assign RDY_set_watch_tohost = 1'd1 ; assign CAN_FIRE_set_watch_tohost = 1'd1 ; assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; // submodule cpu mkCPU cpu(.CLK(CLK), .RST_N(RST_N), .dmem_master_arready(cpu$dmem_master_arready), .dmem_master_awready(cpu$dmem_master_awready), .dmem_master_bid(cpu$dmem_master_bid), .dmem_master_bresp(cpu$dmem_master_bresp), .dmem_master_bvalid(cpu$dmem_master_bvalid), .dmem_master_rdata(cpu$dmem_master_rdata), .dmem_master_rid(cpu$dmem_master_rid), .dmem_master_rlast(cpu$dmem_master_rlast), .dmem_master_rresp(cpu$dmem_master_rresp), .dmem_master_rvalid(cpu$dmem_master_rvalid), .dmem_master_wready(cpu$dmem_master_wready), .hart0_server_reset_request_put(cpu$hart0_server_reset_request_put), .imem_master_arready(cpu$imem_master_arready), .imem_master_awready(cpu$imem_master_awready), .imem_master_bid(cpu$imem_master_bid), .imem_master_bresp(cpu$imem_master_bresp), .imem_master_bvalid(cpu$imem_master_bvalid), .imem_master_rdata(cpu$imem_master_rdata), .imem_master_rid(cpu$imem_master_rid), .imem_master_rlast(cpu$imem_master_rlast), .imem_master_rresp(cpu$imem_master_rresp), .imem_master_rvalid(cpu$imem_master_rvalid), .imem_master_wready(cpu$imem_master_wready), .m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear), .nmi_req_set_not_clear(cpu$nmi_req_set_not_clear), .s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear), .set_verbosity_logdelay(cpu$set_verbosity_logdelay), .set_verbosity_verbosity(cpu$set_verbosity_verbosity), .set_watch_tohost_tohost_addr(cpu$set_watch_tohost_tohost_addr), .set_watch_tohost_watch_tohost(cpu$set_watch_tohost_watch_tohost), .software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear), .timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear), .EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put), .EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get), .EN_set_verbosity(cpu$EN_set_verbosity), .EN_set_watch_tohost(cpu$EN_set_watch_tohost), .RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put), .hart0_server_reset_response_get(cpu$hart0_server_reset_response_get), .RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get), .imem_master_awvalid(cpu$imem_master_awvalid), .imem_master_awid(cpu$imem_master_awid), .imem_master_awaddr(cpu$imem_master_awaddr), .imem_master_awlen(cpu$imem_master_awlen), .imem_master_awsize(cpu$imem_master_awsize), .imem_master_awburst(cpu$imem_master_awburst), .imem_master_awlock(cpu$imem_master_awlock), .imem_master_awcache(cpu$imem_master_awcache), .imem_master_awprot(cpu$imem_master_awprot), .imem_master_awqos(cpu$imem_master_awqos), .imem_master_awregion(cpu$imem_master_awregion), .imem_master_wvalid(cpu$imem_master_wvalid), .imem_master_wdata(cpu$imem_master_wdata), .imem_master_wstrb(cpu$imem_master_wstrb), .imem_master_wlast(cpu$imem_master_wlast), .imem_master_bready(cpu$imem_master_bready), .imem_master_arvalid(cpu$imem_master_arvalid), .imem_master_arid(cpu$imem_master_arid), .imem_master_araddr(cpu$imem_master_araddr), .imem_master_arlen(cpu$imem_master_arlen), .imem_master_arsize(cpu$imem_master_arsize), .imem_master_arburst(cpu$imem_master_arburst), .imem_master_arlock(cpu$imem_master_arlock), .imem_master_arcache(cpu$imem_master_arcache), .imem_master_arprot(cpu$imem_master_arprot), .imem_master_arqos(cpu$imem_master_arqos), .imem_master_arregion(cpu$imem_master_arregion), .imem_master_rready(cpu$imem_master_rready), .dmem_master_awvalid(cpu$dmem_master_awvalid), .dmem_master_awid(cpu$dmem_master_awid), .dmem_master_awaddr(cpu$dmem_master_awaddr), .dmem_master_awlen(cpu$dmem_master_awlen), .dmem_master_awsize(cpu$dmem_master_awsize), .dmem_master_awburst(cpu$dmem_master_awburst), .dmem_master_awlock(cpu$dmem_master_awlock), .dmem_master_awcache(cpu$dmem_master_awcache), .dmem_master_awprot(cpu$dmem_master_awprot), .dmem_master_awqos(cpu$dmem_master_awqos), .dmem_master_awregion(cpu$dmem_master_awregion), .dmem_master_wvalid(cpu$dmem_master_wvalid), .dmem_master_wdata(cpu$dmem_master_wdata), .dmem_master_wstrb(cpu$dmem_master_wstrb), .dmem_master_wlast(cpu$dmem_master_wlast), .dmem_master_bready(cpu$dmem_master_bready), .dmem_master_arvalid(cpu$dmem_master_arvalid), .dmem_master_arid(cpu$dmem_master_arid), .dmem_master_araddr(cpu$dmem_master_araddr), .dmem_master_arlen(cpu$dmem_master_arlen), .dmem_master_arsize(cpu$dmem_master_arsize), .dmem_master_arburst(cpu$dmem_master_arburst), .dmem_master_arlock(cpu$dmem_master_arlock), .dmem_master_arcache(cpu$dmem_master_arcache), .dmem_master_arprot(cpu$dmem_master_arprot), .dmem_master_arqos(cpu$dmem_master_arqos), .dmem_master_arregion(cpu$dmem_master_arregion), .dmem_master_rready(cpu$dmem_master_rready), .RDY_set_verbosity(), .RDY_set_watch_tohost()); // submodule f_reset_reqs FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_reset_reqs$D_IN), .ENQ(f_reset_reqs$ENQ), .DEQ(f_reset_reqs$DEQ), .CLR(f_reset_reqs$CLR), .D_OUT(f_reset_reqs$D_OUT), .FULL_N(f_reset_reqs$FULL_N), .EMPTY_N(f_reset_reqs$EMPTY_N)); // submodule f_reset_rsps FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_reset_rsps$D_IN), .ENQ(f_reset_rsps$ENQ), .DEQ(f_reset_rsps$DEQ), .CLR(f_reset_rsps$CLR), .D_OUT(f_reset_rsps$D_OUT), .FULL_N(f_reset_rsps$FULL_N), .EMPTY_N(f_reset_rsps$EMPTY_N)); // submodule fabric_2x3 mkFabric_2x3 fabric_2x3(.CLK(CLK), .RST_N(RST_N), .set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity), .v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr), .v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst), .v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache), .v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid), .v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen), .v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock), .v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot), .v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos), .v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion), .v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize), .v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid), .v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr), .v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst), .v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache), .v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid), .v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen), .v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock), .v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot), .v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos), .v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion), .v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize), .v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid), .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), .v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr), .v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst), .v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache), .v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid), .v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen), .v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock), .v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot), .v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos), .v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion), .v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize), .v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid), .v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr), .v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst), .v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache), .v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid), .v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen), .v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock), .v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot), .v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos), .v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion), .v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize), .v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid), .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), .v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready), .v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready), .v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid), .v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp), .v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid), .v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata), .v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid), .v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast), .v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp), .v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid), .v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready), .v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready), .v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready), .v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid), .v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp), .v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid), .v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata), .v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid), .v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast), .v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp), .v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid), .v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready), .v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready), .v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready), .v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid), .v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp), .v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid), .v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata), .v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid), .v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast), .v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp), .v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid), .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), .EN_reset(fabric_2x3$EN_reset), .EN_set_verbosity(fabric_2x3$EN_set_verbosity), .RDY_reset(fabric_2x3$RDY_reset), .RDY_set_verbosity(), .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), .v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid), .v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid), .v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp), .v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready), .v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid), .v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid), .v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata), .v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp), .v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast), .v_from_masters_1_awready(), .v_from_masters_1_wready(), .v_from_masters_1_bvalid(), .v_from_masters_1_bid(), .v_from_masters_1_bresp(), .v_from_masters_1_arready(), .v_from_masters_1_rvalid(), .v_from_masters_1_rid(), .v_from_masters_1_rdata(), .v_from_masters_1_rresp(), .v_from_masters_1_rlast(), .v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid), .v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid), .v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr), .v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen), .v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize), .v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst), .v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock), .v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache), .v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot), .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), .v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready), .v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid), .v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid), .v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr), .v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen), .v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize), .v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst), .v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock), .v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache), .v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot), .v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos), .v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion), .v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready), .v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid), .v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid), .v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr), .v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen), .v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize), .v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst), .v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock), .v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache), .v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot), .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), .v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready), .v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid), .v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid), .v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr), .v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen), .v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize), .v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst), .v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock), .v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache), .v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot), .v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos), .v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion), .v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready), .v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid), .v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid), .v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr), .v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen), .v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize), .v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst), .v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock), .v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache), .v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot), .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), .v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready), .v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid), .v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid), .v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr), .v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen), .v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize), .v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst), .v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock), .v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache), .v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot), .v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos), .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); // submodule near_mem_io mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK), .RST_N(RST_N), .axi4_slave_araddr(near_mem_io$axi4_slave_araddr), .axi4_slave_arburst(near_mem_io$axi4_slave_arburst), .axi4_slave_arcache(near_mem_io$axi4_slave_arcache), .axi4_slave_arid(near_mem_io$axi4_slave_arid), .axi4_slave_arlen(near_mem_io$axi4_slave_arlen), .axi4_slave_arlock(near_mem_io$axi4_slave_arlock), .axi4_slave_arprot(near_mem_io$axi4_slave_arprot), .axi4_slave_arqos(near_mem_io$axi4_slave_arqos), .axi4_slave_arregion(near_mem_io$axi4_slave_arregion), .axi4_slave_arsize(near_mem_io$axi4_slave_arsize), .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), .axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr), .axi4_slave_awburst(near_mem_io$axi4_slave_awburst), .axi4_slave_awcache(near_mem_io$axi4_slave_awcache), .axi4_slave_awid(near_mem_io$axi4_slave_awid), .axi4_slave_awlen(near_mem_io$axi4_slave_awlen), .axi4_slave_awlock(near_mem_io$axi4_slave_awlock), .axi4_slave_awprot(near_mem_io$axi4_slave_awprot), .axi4_slave_awqos(near_mem_io$axi4_slave_awqos), .axi4_slave_awregion(near_mem_io$axi4_slave_awregion), .axi4_slave_awsize(near_mem_io$axi4_slave_awsize), .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), .axi4_slave_bready(near_mem_io$axi4_slave_bready), .axi4_slave_rready(near_mem_io$axi4_slave_rready), .axi4_slave_wdata(near_mem_io$axi4_slave_wdata), .axi4_slave_wlast(near_mem_io$axi4_slave_wlast), .axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb), .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), .set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base), .set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim), .EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put), .EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get), .EN_set_addr_map(near_mem_io$EN_set_addr_map), .EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get), .EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get), .RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put), .RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get), .RDY_set_addr_map(), .axi4_slave_awready(near_mem_io$axi4_slave_awready), .axi4_slave_wready(near_mem_io$axi4_slave_wready), .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), .axi4_slave_bid(near_mem_io$axi4_slave_bid), .axi4_slave_bresp(near_mem_io$axi4_slave_bresp), .axi4_slave_arready(near_mem_io$axi4_slave_arready), .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), .axi4_slave_rid(near_mem_io$axi4_slave_rid), .axi4_slave_rdata(near_mem_io$axi4_slave_rdata), .axi4_slave_rresp(near_mem_io$axi4_slave_rresp), .axi4_slave_rlast(near_mem_io$axi4_slave_rlast), .get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get), .RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get), .get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get), .RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get)); // submodule plic mkPLIC_16_2_7 plic(.CLK(CLK), .RST_N(RST_N), .axi4_slave_araddr(plic$axi4_slave_araddr), .axi4_slave_arburst(plic$axi4_slave_arburst), .axi4_slave_arcache(plic$axi4_slave_arcache), .axi4_slave_arid(plic$axi4_slave_arid), .axi4_slave_arlen(plic$axi4_slave_arlen), .axi4_slave_arlock(plic$axi4_slave_arlock), .axi4_slave_arprot(plic$axi4_slave_arprot), .axi4_slave_arqos(plic$axi4_slave_arqos), .axi4_slave_arregion(plic$axi4_slave_arregion), .axi4_slave_arsize(plic$axi4_slave_arsize), .axi4_slave_arvalid(plic$axi4_slave_arvalid), .axi4_slave_awaddr(plic$axi4_slave_awaddr), .axi4_slave_awburst(plic$axi4_slave_awburst), .axi4_slave_awcache(plic$axi4_slave_awcache), .axi4_slave_awid(plic$axi4_slave_awid), .axi4_slave_awlen(plic$axi4_slave_awlen), .axi4_slave_awlock(plic$axi4_slave_awlock), .axi4_slave_awprot(plic$axi4_slave_awprot), .axi4_slave_awqos(plic$axi4_slave_awqos), .axi4_slave_awregion(plic$axi4_slave_awregion), .axi4_slave_awsize(plic$axi4_slave_awsize), .axi4_slave_awvalid(plic$axi4_slave_awvalid), .axi4_slave_bready(plic$axi4_slave_bready), .axi4_slave_rready(plic$axi4_slave_rready), .axi4_slave_wdata(plic$axi4_slave_wdata), .axi4_slave_wlast(plic$axi4_slave_wlast), .axi4_slave_wstrb(plic$axi4_slave_wstrb), .axi4_slave_wvalid(plic$axi4_slave_wvalid), .set_addr_map_addr_base(plic$set_addr_map_addr_base), .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), .set_verbosity_verbosity(plic$set_verbosity_verbosity), .v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear), .v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear), .v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear), .v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear), .v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear), .v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear), .v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear), .v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear), .v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear), .v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear), .v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear), .v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear), .v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear), .v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear), .v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear), .v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear), .EN_set_verbosity(plic$EN_set_verbosity), .EN_show_PLIC_state(plic$EN_show_PLIC_state), .EN_server_reset_request_put(plic$EN_server_reset_request_put), .EN_server_reset_response_get(plic$EN_server_reset_response_get), .EN_set_addr_map(plic$EN_set_addr_map), .RDY_set_verbosity(), .RDY_show_PLIC_state(), .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), .RDY_set_addr_map(), .axi4_slave_awready(plic$axi4_slave_awready), .axi4_slave_wready(plic$axi4_slave_wready), .axi4_slave_bvalid(plic$axi4_slave_bvalid), .axi4_slave_bid(plic$axi4_slave_bid), .axi4_slave_bresp(plic$axi4_slave_bresp), .axi4_slave_arready(plic$axi4_slave_arready), .axi4_slave_rvalid(plic$axi4_slave_rvalid), .axi4_slave_rid(plic$axi4_slave_rid), .axi4_slave_rdata(plic$axi4_slave_rdata), .axi4_slave_rresp(plic$axi4_slave_rresp), .axi4_slave_rlast(plic$axi4_slave_rlast), .v_targets_0_m_eip(plic$v_targets_0_m_eip), .v_targets_1_m_eip(plic$v_targets_1_m_eip)); // submodule soc_map mkSoC_Map soc_map(.CLK(CLK), .RST_N(RST_N), .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), .m_near_mem_io_addr_size(), .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), .m_plic_addr_base(soc_map$m_plic_addr_base), .m_plic_addr_size(), .m_plic_addr_lim(soc_map$m_plic_addr_lim), .m_uart0_addr_base(), .m_uart0_addr_size(), .m_uart0_addr_lim(), .m_boot_rom_addr_base(), .m_boot_rom_addr_size(), .m_boot_rom_addr_lim(), .m_mem0_controller_addr_base(), .m_mem0_controller_addr_size(), .m_mem0_controller_addr_lim(), .m_tcm_addr_base(), .m_tcm_addr_size(), .m_tcm_addr_lim(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), .m_pc_reset_value(), .m_mtvec_reset_value(), .m_nmivec_reset_value()); // rule RL_rl_wr_addr_channel assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; // rule RL_rl_wr_data_channel assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; // rule RL_rl_wr_response_channel assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; // rule RL_rl_rd_addr_channel assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; // rule RL_rl_rd_data_channel assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; // rule RL_rl_wr_addr_channel_1 assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; // rule RL_rl_wr_data_channel_1 assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; // rule RL_rl_wr_response_channel_1 assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; // rule RL_rl_rd_addr_channel_1 assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; // rule RL_rl_rd_data_channel_1 assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; // rule RL_rl_wr_addr_channel_2 assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; // rule RL_rl_wr_data_channel_2 assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; // rule RL_rl_wr_response_channel_2 assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; // rule RL_rl_rd_addr_channel_2 assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; // rule RL_rl_rd_data_channel_2 assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; // rule RL_rl_wr_addr_channel_3 assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; // rule RL_rl_wr_data_channel_3 assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; // rule RL_rl_wr_response_channel_3 assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; // rule RL_rl_rd_addr_channel_3 assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; // rule RL_rl_rd_data_channel_3 assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; // rule RL_rl_relay_sw_interrupts assign CAN_FIRE_RL_rl_relay_sw_interrupts = near_mem_io$RDY_get_sw_interrupt_req_get ; assign WILL_FIRE_RL_rl_relay_sw_interrupts = near_mem_io$RDY_get_sw_interrupt_req_get ; // rule RL_rl_relay_timer_interrupts assign CAN_FIRE_RL_rl_relay_timer_interrupts = near_mem_io$RDY_get_timer_interrupt_req_get ; assign WILL_FIRE_RL_rl_relay_timer_interrupts = near_mem_io$RDY_get_timer_interrupt_req_get ; // rule RL_rl_relay_external_interrupts assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; // rule RL_rl_cpu_hart0_reset_from_soc_start assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = near_mem_io$RDY_server_reset_request_put && plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; // rule RL_rl_cpu_hart0_reset_complete assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = near_mem_io$RDY_server_reset_response_get && plic$RDY_server_reset_response_get && cpu$RDY_hart0_server_reset_response_get && f_reset_rsps$FULL_N ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; // submodule cpu assign cpu$dmem_master_arready = fabric_2x3$v_from_masters_0_arready ; assign cpu$dmem_master_awready = fabric_2x3$v_from_masters_0_awready ; assign cpu$dmem_master_bid = fabric_2x3$v_from_masters_0_bid ; assign cpu$dmem_master_bresp = fabric_2x3$v_from_masters_0_bresp ; assign cpu$dmem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ; assign cpu$dmem_master_rdata = fabric_2x3$v_from_masters_0_rdata ; assign cpu$dmem_master_rid = fabric_2x3$v_from_masters_0_rid ; assign cpu$dmem_master_rlast = fabric_2x3$v_from_masters_0_rlast ; assign cpu$dmem_master_rresp = fabric_2x3$v_from_masters_0_rresp ; assign cpu$dmem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ; assign cpu$dmem_master_wready = fabric_2x3$v_from_masters_0_wready ; assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ; assign cpu$imem_master_arready = cpu_imem_master_arready ; assign cpu$imem_master_awready = cpu_imem_master_awready ; assign cpu$imem_master_bid = cpu_imem_master_bid ; assign cpu$imem_master_bresp = cpu_imem_master_bresp ; assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; assign cpu$imem_master_rdata = cpu_imem_master_rdata ; assign cpu$imem_master_rid = cpu_imem_master_rid ; assign cpu$imem_master_rlast = cpu_imem_master_rlast ; assign cpu$imem_master_rresp = cpu_imem_master_rresp ; assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; assign cpu$imem_master_wready = cpu_imem_master_wready ; assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; assign cpu$set_watch_tohost_tohost_addr = set_watch_tohost_tohost_addr ; assign cpu$set_watch_tohost_watch_tohost = set_watch_tohost_watch_tohost ; assign cpu$software_interrupt_req_set_not_clear = near_mem_io$get_sw_interrupt_req_get ; assign cpu$timer_interrupt_req_set_not_clear = near_mem_io$get_timer_interrupt_req_get ; assign cpu$EN_hart0_server_reset_request_put = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; assign cpu$EN_hart0_server_reset_response_get = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; assign cpu$EN_set_verbosity = EN_set_verbosity ; assign cpu$EN_set_watch_tohost = EN_set_watch_tohost ; // submodule f_reset_reqs assign f_reset_reqs$D_IN = cpu_reset_server_request_put ; assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; assign f_reset_reqs$DEQ = near_mem_io$RDY_server_reset_request_put && plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_rsps assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ; assign f_reset_rsps$ENQ = near_mem_io$RDY_server_reset_response_get && plic$RDY_server_reset_response_get && cpu$RDY_hart0_server_reset_response_get && f_reset_rsps$FULL_N ; assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; assign f_reset_rsps$CLR = 1'b0 ; // submodule fabric_2x3 assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; assign fabric_2x3$v_from_masters_0_araddr = cpu$dmem_master_araddr ; assign fabric_2x3$v_from_masters_0_arburst = cpu$dmem_master_arburst ; assign fabric_2x3$v_from_masters_0_arcache = cpu$dmem_master_arcache ; assign fabric_2x3$v_from_masters_0_arid = cpu$dmem_master_arid ; assign fabric_2x3$v_from_masters_0_arlen = cpu$dmem_master_arlen ; assign fabric_2x3$v_from_masters_0_arlock = cpu$dmem_master_arlock ; assign fabric_2x3$v_from_masters_0_arprot = cpu$dmem_master_arprot ; assign fabric_2x3$v_from_masters_0_arqos = cpu$dmem_master_arqos ; assign fabric_2x3$v_from_masters_0_arregion = cpu$dmem_master_arregion ; assign fabric_2x3$v_from_masters_0_arsize = cpu$dmem_master_arsize ; assign fabric_2x3$v_from_masters_0_arvalid = cpu$dmem_master_arvalid ; assign fabric_2x3$v_from_masters_0_awaddr = cpu$dmem_master_awaddr ; assign fabric_2x3$v_from_masters_0_awburst = cpu$dmem_master_awburst ; assign fabric_2x3$v_from_masters_0_awcache = cpu$dmem_master_awcache ; assign fabric_2x3$v_from_masters_0_awid = cpu$dmem_master_awid ; assign fabric_2x3$v_from_masters_0_awlen = cpu$dmem_master_awlen ; assign fabric_2x3$v_from_masters_0_awlock = cpu$dmem_master_awlock ; assign fabric_2x3$v_from_masters_0_awprot = cpu$dmem_master_awprot ; assign fabric_2x3$v_from_masters_0_awqos = cpu$dmem_master_awqos ; assign fabric_2x3$v_from_masters_0_awregion = cpu$dmem_master_awregion ; assign fabric_2x3$v_from_masters_0_awsize = cpu$dmem_master_awsize ; assign fabric_2x3$v_from_masters_0_awvalid = cpu$dmem_master_awvalid ; assign fabric_2x3$v_from_masters_0_bready = cpu$dmem_master_bready ; assign fabric_2x3$v_from_masters_0_rready = cpu$dmem_master_rready ; assign fabric_2x3$v_from_masters_0_wdata = cpu$dmem_master_wdata ; assign fabric_2x3$v_from_masters_0_wlast = cpu$dmem_master_wlast ; assign fabric_2x3$v_from_masters_0_wstrb = cpu$dmem_master_wstrb ; assign fabric_2x3$v_from_masters_0_wvalid = cpu$dmem_master_wvalid ; assign fabric_2x3$v_from_masters_1_araddr = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arburst = 2'b10 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arcache = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arlen = 8'b10101010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arprot = 3'b010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arqos = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arregion = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arsize = 3'b010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ; assign fabric_2x3$v_from_masters_1_awaddr = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awburst = 2'b10 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awcache = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awlen = 8'b10101010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awprot = 3'b010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awqos = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awregion = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awsize = 3'b010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ; assign fabric_2x3$v_from_masters_1_bready = 1'd0 ; assign fabric_2x3$v_from_masters_1_rready = 1'd0 ; assign fabric_2x3$v_from_masters_1_wdata = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_wstrb = 8'b10101010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ; assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ; assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ; assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ; assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ; assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ; assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ; assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ; assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ; assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ; assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ; assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ; assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ; assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ; assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ; assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ; assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ; assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ; assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ; assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ; assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ; assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ; assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ; assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ; assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ; assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ; assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ; assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ; assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ; assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ; assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ; assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ; assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ; assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ; assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; assign fabric_2x3$EN_set_verbosity = 1'b0 ; // submodule near_mem_io assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ; assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ; assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ; assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ; assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ; assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ; assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ; assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ; assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ; assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ; assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ; assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ; assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ; assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ; assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ; assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ; assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ; assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ; assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ; assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ; assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ; assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ; assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; assign near_mem_io$set_addr_map_addr_base = soc_map$m_near_mem_io_addr_base ; assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ; assign near_mem_io$EN_server_reset_request_put = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; assign near_mem_io$EN_server_reset_response_get = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; assign near_mem_io$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; assign near_mem_io$EN_get_timer_interrupt_req_get = near_mem_io$RDY_get_timer_interrupt_req_get ; assign near_mem_io$EN_get_sw_interrupt_req_get = near_mem_io$RDY_get_sw_interrupt_req_get ; // submodule plic assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ; assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ; assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ; assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ; assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ; assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ; assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ; assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ; assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ; assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ; assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ; assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ; assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ; assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ; assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ; assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ; assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ; assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ; assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ; assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ; assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ; assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ; assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ; assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ; assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ; assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ; assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ; assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ; assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ; assign plic$set_verbosity_verbosity = 4'h0 ; assign plic$v_sources_0_m_interrupt_req_set_not_clear = core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; assign plic$v_sources_10_m_interrupt_req_set_not_clear = core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ; assign plic$v_sources_11_m_interrupt_req_set_not_clear = core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ; assign plic$v_sources_12_m_interrupt_req_set_not_clear = core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ; assign plic$v_sources_13_m_interrupt_req_set_not_clear = core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ; assign plic$v_sources_14_m_interrupt_req_set_not_clear = core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ; assign plic$v_sources_15_m_interrupt_req_set_not_clear = core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ; assign plic$v_sources_1_m_interrupt_req_set_not_clear = core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ; assign plic$v_sources_2_m_interrupt_req_set_not_clear = core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ; assign plic$v_sources_3_m_interrupt_req_set_not_clear = core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ; assign plic$v_sources_4_m_interrupt_req_set_not_clear = core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ; assign plic$v_sources_5_m_interrupt_req_set_not_clear = core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ; assign plic$v_sources_6_m_interrupt_req_set_not_clear = core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ; assign plic$v_sources_7_m_interrupt_req_set_not_clear = core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ; assign plic$v_sources_8_m_interrupt_req_set_not_clear = core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ; assign plic$v_sources_9_m_interrupt_req_set_not_clear = core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; assign plic$EN_set_verbosity = 1'b0 ; assign plic$EN_show_PLIC_state = 1'b0 ; assign plic$EN_server_reset_request_put = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; assign plic$EN_server_reset_response_get = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 = plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && cpu$RDY_hart0_server_reset_request_put && f_reset_reqs$EMPTY_N ; // handling of system tasks // synopsys translate_off always@(negedge CLK) begin #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) begin v__h4255 = $stime; #0; end v__h4249 = v__h4255 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4249); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) begin v__h4496 = $stime; #0; end v__h4490 = v__h4496 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4490); end // synopsys translate_on endmodule // mkCore

module antiDroopIIR_16 ( input clk, input trig, input signed [15:0] din, input signed [6:0] tapWeight, input accClr_en, //input oflowClr, (* shreg_extract = "no" *) output reg oflowDetect = 1'd0, output reg signed [15:0] dout = 16'sd0); parameter IIR_scale = 15; // define the scaling factor for the IIR multiplier, eg for 0.002 (din = 63, IIR_scale = 15). //`define ADDPIPEREG (* shreg_extract = "no" *) reg signed [15:0] din_del = 16'sd0; `ifdef ADDPIPEREG (* shreg_extract = "no" *) reg signed [15:0] din_del_b = 16'sd0; `endif reg signed [47:0] tap = 48'sd0; reg signed [22:0] multreg = 23'sd0; (* equivalent_register_removal = "no" *) reg trig_a = 1'b0, trig_b = 1'b0; wire trig_edge = trig_a & ~trig_b; //reg trig_edge = 1'b0; (* shreg_extract = "no" *) reg signed [6:0] tapWeight_a = 7'sd0, tapWeight_b = 7'sd0; //wire oflow = (^tap[IIR_scale+16:IIR_scale+15]); wire oflow = (~&tap[47:IIR_scale+15] && ~&(~tap[47:IIR_scale+15])); always @(posedge clk) begin //trig_edge <= trig_a & ~trig_b; tapWeight_a <= tapWeight; tapWeight_b <= tapWeight_a; trig_a <= trig; trig_b <= trig_a; din_del <= din; `ifdef ADDPIPEREG din_del_b <= din_del; multreg <= din_del*tapWeight_b; //dout <= din_del_b + tap[IIR_scale+15:IIR_scale]; if (oflow) dout <= (tap[IIR_scale+16]) ? -16'sd32768 : 16'sd32767; else dout <= din_del_b + tap[IIR_scale+15:IIR_scale]; `else multreg <= din*tapWeight_b; //dout <= din_del + tap[IIR_scale+15:IIR_scale]; if (oflow) dout <= (tap[IIR_scale+16]) ? -16'sd32768 : 16'sd32767; else dout <= din_del + tap[IIR_scale+15:IIR_scale]; `endif if (trig_edge && accClr_en) tap <= 48'sd0; else tap <= multreg + tap; //tap <= din*tapWeight + tap; //if (oflowDetect && oflowClr) oflowDetect <= 1'b0; //else if ((~& tap[47:IIR_scale+12]) || (& ~tap[47:IIR_scale+12])) oflowDetect <= 1'b1; //else if ((~& tap[47:IIR_scale+12]) || (& tap[47:IIR_scale+12])) oflowDetect <= 1'b1; //else if (^ tap[IIR_scale+16:IIR_scale+15]) oflowDetect <= 1'b1; //else oflowDetect <= oflowDetect; //oflowDetect <= (^tap[IIR_scale+16:IIR_scale+15]) ? 1'b1 : 1'b0; oflowDetect <= oflow; end endmodule

/* * Programing Notes: 1, there are four SPRs in uartlite, access using mtspr/mfspr instructions 2, the four register are: control register ctrl[0]: tx_start ctrl[1]: rx_disenable ctrl[2]: tx_interrupt_ebable - currently not in use ctrl[3]: rx_interrupt_enable - currently not in use ctrl[4]: interrupt status clear Reset Status: 8'h00 bit[0]/[4] are auto-cleared when writing true-"1" into it. status register - READ ONLY sta[0]: transmitter status which 1 means transmitter is busy, 0 means transmitter is idle sta[1]: receiver status which 1 means receiver is busy, 0 means receiver is idle sta[2]: interrupt status which 1 mean interrupt status, 0 means normal status sta[3]: transmitter interrupt status which means transmitter interrupt sta[4]: receiver interrupt status which means receiver interrupt receive data register transmit data register * Note: 1, there is no flow control, after received a byte, if second byte is coming, first byte is covered */ // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "def_pippo.v" module dsu_uartlite( clk, rst, txd, rxd, spr_dat_i, reg_txdata, reg_txdata_we, reg_ctrl, reg_ctrl_we, reg_sta, reg_sta_we, reg_rxdata, reg_rxdata_we, sram_ce, sram_we, sram_addr, sram_wdata, download_enable ); // input clk; input rst; // uart inout input rxd; output txd; // spr access interface input [7:0] spr_dat_i; input reg_txdata_we; input reg_ctrl_we; input reg_rxdata_we; input reg_sta_we; output [7:0] reg_txdata; output [7:0] reg_ctrl; output [7:0] reg_sta; output [7:0] reg_rxdata; // sram interface output sram_ce; output sram_we; output [31:0] sram_wdata; output [`IOCM_Word_BW-1:0] sram_addr; // backdoor control input download_enable; // // four internal SPRs for uartlite // reg [7:0] reg_ctrl; reg [7:0] reg_sta; reg [7:0] reg_txdata; reg [7:0] reg_rxdata; // wire tx_start; wire rx_enable; reg tx_busy_d; reg interrupt_tx; reg interrupt_rx; // // // wire txd; wire rxd; wire [7:0] rx_data; wire [7:0] rx_data_to_sram; wire rx_data_rdy; wire tx_busy; wire rx_idle; wire interrupt; // // SPR: control register // // [TBV]: coding style of auto-cleared always@(posedge clk or `dsu_RST_EVENT rst) begin if(rst==`dsu_RST_VALUE) reg_ctrl <= 8'h00; else if(reg_ctrl[0]) // the tx_enable bit (ctrl[0]) will auto cleared after write 1 reg_ctrl[0] <= 1'b0; else if(reg_ctrl_we) reg_ctrl <= spr_dat_i; else if(reg_ctrl[4]) // the int_clear bit (ctrl[4]) will auto cleared after write 1 reg_ctrl[4] <= 1'b0; end assign tx_start = reg_ctrl[0]; assign rx_enable = !reg_ctrl[1]; assign int_clear = reg_ctrl[4]; // // SPR: status register // // tx interrupt detect always@(posedge clk or `dsu_RST_EVENT rst) if(rst==`dsu_RST_VALUE) tx_busy_d <= 1'b0; else tx_busy_d <= tx_busy; //when detect the negedge of tx_busy that means transmitter is finished //if the tx_interrupt enable then generate interrupt of transmitter. always@(posedge clk or `dsu_RST_EVENT rst) if(rst==`dsu_RST_VALUE) interrupt_tx <= 1'b0; else if(!tx_busy && tx_busy_d) interrupt_tx <= 1'b1; else if(int_clear) interrupt_tx <= 1'b0; always@(posedge clk or `dsu_RST_EVENT rst) if(rst==`dsu_RST_VALUE) interrupt_rx <= 1'b0; else if(rx_data_rdy && rx_enable) interrupt_rx <= 1'b1; else if(int_clear) interrupt_rx <= 1'b0; assign interrupt = interrupt_rx || interrupt_tx; always@(posedge clk or `dsu_RST_EVENT rst) if(rst==`dsu_RST_VALUE) reg_sta <= 8'h00; else if(reg_sta_we) reg_sta <= spr_dat_i; else reg_sta <= {3'b000, interrupt_rx, interrupt_tx, interrupt, !rx_idle, tx_busy}; // // SPR: receive data register // always@(posedge clk or `dsu_RST_EVENT rst) begin if(rst==`dsu_RST_VALUE) reg_rxdata <= 8'h00; else if(rx_data_rdy && rx_enable ) reg_rxdata <= rx_data; end // // SPR: transmit data register // always@(posedge clk or `dsu_RST_EVENT rst) begin if(rst==`dsu_RST_VALUE) reg_txdata <= 8'h00; else if(reg_txdata_we) reg_txdata <= spr_dat_i; end // // transmitter and receiver // dsu_Tx tx( .clk(clk), .rst(rst), .TxD_start(tx_start), .TxD_data(reg_txdata), .TxD(txd), .TxD_busy(tx_busy) ); dsu_Rx rx( .clk(clk), .rst(rst), .RxD(rxd), .RxD_data_ready(rx_data_rdy), .RxD_data(rx_data), .RxD_endofpacket(), .RxD_idle(rx_idle) ); // // back door mode: burn sram using received data // assign rx_data_to_sram = download_enable ? rx_data : 8'h00; dsu_sram_ctrl sram_ctrl( .clk(clk), .rst(rst), .rxd(rx_data_to_sram), .rxd_ready(rx_data_rdy && download_enable), .sram_ce(sram_ce), .sram_we(sram_we), .sram_addr(sram_addr), .sram_wdata(sram_wdata), .download_enable(download_enable) ); endmodule

/**************************************** Mul Unit - Booth Algorithm - 32bit Adder Make : 2010/12/07 Update : ****************************************/ `default_nettype none module execute_mul_booth32( //iDATA input wire [31:0] iDATA_0, input wire [31:0] iDATA_1, //oDATA output wire [63:0] oDATA, output wire oHSF, output wire oHOF, output wire oHCF, output wire oHPF, output wire oHZF, output wire oLSF, output wire oLOF, output wire oLCF, output wire oLPF, output wire oLZF ); /**************************************** wire ****************************************/ wire [63:0] w_tmp_out; wire [63:0] w0_tmp; wire [63:0] w1_tmp; wire [63:0] w2_tmp; wire [63:0] w3_tmp; wire [63:0] w4_tmp; wire [63:0] w5_tmp; wire [63:0] w6_tmp; wire [63:0] w7_tmp; wire [63:0] w8_tmp; wire [63:0] w9_tmp; wire [63:0] w10_tmp; wire [63:0] w11_tmp; wire [63:0] w12_tmp; wire [63:0] w13_tmp; wire [63:0] w14_tmp; wire [63:0] w15_tmp; wire [63:0] w16_tmp; /**************************************** Booth - Encoder ****************************************/ assign w0_tmp = func_booth_algorithm(iDATA_0, iDATA_1[1], iDATA_1[0], 1'b0); assign w1_tmp = func_booth_algorithm(iDATA_0, iDATA_1[3], iDATA_1[2], iDATA_1[1]); assign w2_tmp = func_booth_algorithm(iDATA_0, iDATA_1[5], iDATA_1[4], iDATA_1[3]); assign w3_tmp = func_booth_algorithm(iDATA_0, iDATA_1[7], iDATA_1[6], iDATA_1[5]); assign w4_tmp = func_booth_algorithm(iDATA_0, iDATA_1[9], iDATA_1[8], iDATA_1[7]); assign w5_tmp = func_booth_algorithm(iDATA_0, iDATA_1[11], iDATA_1[10], iDATA_1[9]); assign w6_tmp = func_booth_algorithm(iDATA_0, iDATA_1[13], iDATA_1[12], iDATA_1[11]); assign w7_tmp = func_booth_algorithm(iDATA_0, iDATA_1[15], iDATA_1[14], iDATA_1[13]); assign w8_tmp = func_booth_algorithm(iDATA_0, iDATA_1[17], iDATA_1[16], iDATA_1[15]); assign w9_tmp = func_booth_algorithm(iDATA_0, iDATA_1[19], iDATA_1[18], iDATA_1[17]); assign w10_tmp = func_booth_algorithm(iDATA_0, iDATA_1[21], iDATA_1[20], iDATA_1[19]); assign w11_tmp = func_booth_algorithm(iDATA_0, iDATA_1[23], iDATA_1[22], iDATA_1[21]); assign w12_tmp = func_booth_algorithm(iDATA_0, iDATA_1[25], iDATA_1[24], iDATA_1[23]); assign w13_tmp = func_booth_algorithm(iDATA_0, iDATA_1[27], iDATA_1[26], iDATA_1[25]); assign w14_tmp = func_booth_algorithm(iDATA_0, iDATA_1[29], iDATA_1[28], iDATA_1[27]); assign w15_tmp = func_booth_algorithm(iDATA_0, iDATA_1[31], iDATA_1[30], iDATA_1[29]); assign w16_tmp = func_booth_algorithm(iDATA_0, 1'b0, 1'b0, iDATA_1[31]); /**************************************** Booth - Exeout ****************************************/ assign w_tmp_out = w0_tmp + w1_tmp<<2 + w2_tmp<<4 + w3_tmp<<6 + w4_tmp<<8 + w5_tmp<<10 + w6_tmp<<12 + w7_tmp<<14 + w8_tmp<<16 + w9_tmp<<18 + w10_tmp<<20 + w11_tmp<<22 + w12_tmp<<24 + w13_tmp<<26 + w14_tmp<<28 + w15_tmp<<30 + w16_tmp<<32; function [63:0] func_booth_algorithm; input [31:0] func_booth_algorithm_a; input func_booth_algorithm_b2; input func_booth_algorithm_b1; input func_booth_algorithm_b0; reg [2:0] reg_func_booth_algorithm_tmp; reg [2:0] reg_func_booth_algorithm_cmd; begin reg_func_booth_algorithm_tmp = {func_booth_algorithm_b2, func_booth_algorithm_b1, func_booth_algorithm_b0}; case(reg_func_booth_algorithm_tmp) 3'h0 : reg_func_booth_algorithm_cmd = 3'h0; 3'h1 : reg_func_booth_algorithm_cmd = 3'h1; 3'h2 : reg_func_booth_algorithm_cmd = 3'h1; 3'h3 : reg_func_booth_algorithm_cmd = 3'h2; 3'h4 : reg_func_booth_algorithm_cmd = {1'b1, 2'h2}; 3'h5 : reg_func_booth_algorithm_cmd = {1'b1, 2'h1}; 3'h6 : reg_func_booth_algorithm_cmd = {1'b1, 2'h1}; default : reg_func_booth_algorithm_cmd = 3'h0; endcase if(reg_func_booth_algorithm_cmd[2] == 0)begin //Plus if(reg_func_booth_algorithm_cmd[1:0] == 2'h0)begin func_booth_algorithm = {32{1'b0}}; end else if(reg_func_booth_algorithm_cmd[1:0] == 2'h1)begin func_booth_algorithm = {{32{1'b0}}, func_booth_algorithm_a}; end else begin func_booth_algorithm = {{32{1'b0}}, func_booth_algorithm_a} << 1; end end else begin if(reg_func_booth_algorithm_cmd[1:0] == 2'h0)begin func_booth_algorithm = {32{1'b0}}; end else if(reg_func_booth_algorithm_cmd[1:0] == 2'h1)begin func_booth_algorithm = -{{32{1'b0}}, func_booth_algorithm_a};//(~{{32{1'b0}}, func_booth_algorithm_a}) + {{63{1'b0}}, 1'b1}; end else begin func_booth_algorithm = -({{32{1'b0}}, func_booth_algorithm_a} << 1);//(~({{32{1'b0}}, func_booth_algorithm_a} << 1)) + {{63{1'b0}}, 1'b1}; end end end endfunction /**************************************** Assign ****************************************/ assign oDATA = w_tmp_out; assign oLSF = w_tmp_out[31]; assign oLCF = w_tmp_out[32]; assign oLOF = w_tmp_out[32] ^ w_tmp_out[31]; assign oLPF = w_tmp_out[0]; assign oLZF = (w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0; //(w_tmp_out[32:0] == {33{1'b0}})? 1'b1 : 1'b0; assign oHSF = w_tmp_out[32]; assign oHCF = 1'b0; assign oHOF = w_tmp_out[63]; assign oHPF = w_tmp_out[32]; assign oHZF = (w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0; //(w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0; endmodule `default_nettype wire

// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0 // IP Revision: 1 `timescale 1ns/1ps module daala_zynq_processing_system7_0_0 ( TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, TTC0_CLK0_IN, TTC0_CLK1_IN, TTC0_CLK2_IN, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, S_AXI_HP0_BVALID, S_AXI_HP0_RLAST, S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, S_AXI_HP0_RRESP, S_AXI_HP0_BID, S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, S_AXI_HP0_WCOUNT, S_AXI_HP0_RACOUNT, S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, S_AXI_HP0_ARVALID, S_AXI_HP0_AWVALID, S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, S_AXI_HP0_RREADY, S_AXI_HP0_WLAST, S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, S_AXI_HP0_ARBURST, S_AXI_HP0_ARLOCK, S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, S_AXI_HP0_AWLOCK, S_AXI_HP0_AWSIZE, S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, S_AXI_HP0_AWADDR, S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, S_AXI_HP0_AWLEN, S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, S_AXI_HP0_WDATA, S_AXI_HP0_WSTRB, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB, ); output TTC0_WAVE0_OUT; output TTC0_WAVE1_OUT; output TTC0_WAVE2_OUT; input TTC0_CLK0_IN; input TTC0_CLK1_IN; input TTC0_CLK2_IN; output [1 : 0] USB0_PORT_INDCTL; output USB0_VBUS_PWRSELECT; input USB0_VBUS_PWRFAULT; output M_AXI_GP0_ARVALID; output M_AXI_GP0_AWVALID; output M_AXI_GP0_BREADY; output M_AXI_GP0_RREADY; output M_AXI_GP0_WLAST; output M_AXI_GP0_WVALID; output [11 : 0] M_AXI_GP0_ARID; output [11 : 0] M_AXI_GP0_AWID; output [11 : 0] M_AXI_GP0_WID; output [1 : 0] M_AXI_GP0_ARBURST; output [1 : 0] M_AXI_GP0_ARLOCK; output [2 : 0] M_AXI_GP0_ARSIZE; output [1 : 0] M_AXI_GP0_AWBURST; output [1 : 0] M_AXI_GP0_AWLOCK; output [2 : 0] M_AXI_GP0_AWSIZE; output [2 : 0] M_AXI_GP0_ARPROT; output [2 : 0] M_AXI_GP0_AWPROT; output [31 : 0] M_AXI_GP0_ARADDR; output [31 : 0] M_AXI_GP0_AWADDR; output [31 : 0] M_AXI_GP0_WDATA; output [3 : 0] M_AXI_GP0_ARCACHE; output [3 : 0] M_AXI_GP0_ARLEN; output [3 : 0] M_AXI_GP0_ARQOS; output [3 : 0] M_AXI_GP0_AWCACHE; output [3 : 0] M_AXI_GP0_AWLEN; output [3 : 0] M_AXI_GP0_AWQOS; output [3 : 0] M_AXI_GP0_WSTRB; input M_AXI_GP0_ACLK; input M_AXI_GP0_ARREADY; input M_AXI_GP0_AWREADY; input M_AXI_GP0_BVALID; input M_AXI_GP0_RLAST; input M_AXI_GP0_RVALID; input M_AXI_GP0_WREADY; input [11 : 0] M_AXI_GP0_BID; input [11 : 0] M_AXI_GP0_RID; input [1 : 0] M_AXI_GP0_BRESP; input [1 : 0] M_AXI_GP0_RRESP; input [31 : 0] M_AXI_GP0_RDATA; output S_AXI_HP0_ARREADY; output S_AXI_HP0_AWREADY; output S_AXI_HP0_BVALID; output S_AXI_HP0_RLAST; output S_AXI_HP0_RVALID; output S_AXI_HP0_WREADY; output [1 : 0] S_AXI_HP0_BRESP; output [1 : 0] S_AXI_HP0_RRESP; output [5 : 0] S_AXI_HP0_BID; output [5 : 0] S_AXI_HP0_RID; output [63 : 0] S_AXI_HP0_RDATA; output [7 : 0] S_AXI_HP0_RCOUNT; output [7 : 0] S_AXI_HP0_WCOUNT; output [2 : 0] S_AXI_HP0_RACOUNT; output [5 : 0] S_AXI_HP0_WACOUNT; input S_AXI_HP0_ACLK; input S_AXI_HP0_ARVALID; input S_AXI_HP0_AWVALID; input S_AXI_HP0_BREADY; input S_AXI_HP0_RDISSUECAP1_EN; input S_AXI_HP0_RREADY; input S_AXI_HP0_WLAST; input S_AXI_HP0_WRISSUECAP1_EN; input S_AXI_HP0_WVALID; input [1 : 0] S_AXI_HP0_ARBURST; input [1 : 0] S_AXI_HP0_ARLOCK; input [2 : 0] S_AXI_HP0_ARSIZE; input [1 : 0] S_AXI_HP0_AWBURST; input [1 : 0] S_AXI_HP0_AWLOCK; input [2 : 0] S_AXI_HP0_AWSIZE; input [2 : 0] S_AXI_HP0_ARPROT; input [2 : 0] S_AXI_HP0_AWPROT; input [31 : 0] S_AXI_HP0_ARADDR; input [31 : 0] S_AXI_HP0_AWADDR; input [3 : 0] S_AXI_HP0_ARCACHE; input [3 : 0] S_AXI_HP0_ARLEN; input [3 : 0] S_AXI_HP0_ARQOS; input [3 : 0] S_AXI_HP0_AWCACHE; input [3 : 0] S_AXI_HP0_AWLEN; input [3 : 0] S_AXI_HP0_AWQOS; input [5 : 0] S_AXI_HP0_ARID; input [5 : 0] S_AXI_HP0_AWID; input [5 : 0] S_AXI_HP0_WID; input [63 : 0] S_AXI_HP0_WDATA; input [7 : 0] S_AXI_HP0_WSTRB; output FCLK_CLK0; output FCLK_RESET0_N; input [53 : 0] MIO; input DDR_CAS_n; input DDR_CKE; input DDR_Clk_n; input DDR_Clk; input DDR_CS_n; input DDR_DRSTB; input DDR_ODT; input DDR_RAS_n; input DDR_WEB; input [2 : 0] DDR_BankAddr; input [14 : 0] DDR_Addr; input DDR_VRN; input DDR_VRP; input [3 : 0] DDR_DM; input [31 : 0] DDR_DQ; input [3 : 0] DDR_DQS_n; input [3 : 0] DDR_DQS; input PS_SRSTB; input PS_CLK; input PS_PORB; processing_system7_bfm_v2_0_processing_system7_bfm #( .C_USE_M_AXI_GP0(1), .C_USE_M_AXI_GP1(0), .C_USE_S_AXI_ACP(0), .C_USE_S_AXI_GP0(0), .C_USE_S_AXI_GP1(0), .C_USE_S_AXI_HP0(1), .C_USE_S_AXI_HP1(0), .C_USE_S_AXI_HP2(0), .C_USE_S_AXI_HP3(0), .C_S_AXI_HP0_DATA_WIDTH(64), .C_S_AXI_HP1_DATA_WIDTH(64), .C_S_AXI_HP2_DATA_WIDTH(64), .C_S_AXI_HP3_DATA_WIDTH(64), .C_HIGH_OCM_EN(1), .C_FCLK_CLK0_FREQ(100), .C_FCLK_CLK1_FREQ(142), .C_FCLK_CLK2_FREQ(50), .C_FCLK_CLK3_FREQ(50) ) inst ( .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), .M_AXI_GP0_ARID(M_AXI_GP0_ARID), .M_AXI_GP0_AWID(M_AXI_GP0_AWID), .M_AXI_GP0_WID(M_AXI_GP0_WID), .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), .M_AXI_GP0_BID(M_AXI_GP0_BID), .M_AXI_GP0_RID(M_AXI_GP0_RID), .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), .M_AXI_GP1_ARVALID(), .M_AXI_GP1_AWVALID(), .M_AXI_GP1_BREADY(), .M_AXI_GP1_RREADY(), .M_AXI_GP1_WLAST(), .M_AXI_GP1_WVALID(), .M_AXI_GP1_ARID(), .M_AXI_GP1_AWID(), .M_AXI_GP1_WID(), .M_AXI_GP1_ARBURST(), .M_AXI_GP1_ARLOCK(), .M_AXI_GP1_ARSIZE(), .M_AXI_GP1_AWBURST(), .M_AXI_GP1_AWLOCK(), .M_AXI_GP1_AWSIZE(), .M_AXI_GP1_ARPROT(), .M_AXI_GP1_AWPROT(), .M_AXI_GP1_ARADDR(), .M_AXI_GP1_AWADDR(), .M_AXI_GP1_WDATA(), .M_AXI_GP1_ARCACHE(), .M_AXI_GP1_ARLEN(), .M_AXI_GP1_ARQOS(), .M_AXI_GP1_AWCACHE(), .M_AXI_GP1_AWLEN(), .M_AXI_GP1_AWQOS(), .M_AXI_GP1_WSTRB(), .M_AXI_GP1_ACLK(1'B0), .M_AXI_GP1_ARREADY(1'B0), .M_AXI_GP1_AWREADY(1'B0), .M_AXI_GP1_BVALID(1'B0), .M_AXI_GP1_RLAST(1'B0), .M_AXI_GP1_RVALID(1'B0), .M_AXI_GP1_WREADY(1'B0), .M_AXI_GP1_BID(12'B0), .M_AXI_GP1_RID(12'B0), .M_AXI_GP1_BRESP(2'B0), .M_AXI_GP1_RRESP(2'B0), .M_AXI_GP1_RDATA(32'B0), .S_AXI_GP0_ARREADY(), .S_AXI_GP0_AWREADY(), .S_AXI_GP0_BVALID(), .S_AXI_GP0_RLAST(), .S_AXI_GP0_RVALID(), .S_AXI_GP0_WREADY(), .S_AXI_GP0_BRESP(), .S_AXI_GP0_RRESP(), .S_AXI_GP0_RDATA(), .S_AXI_GP0_BID(), .S_AXI_GP0_RID(), .S_AXI_GP0_ACLK(1'B0), .S_AXI_GP0_ARVALID(1'B0), .S_AXI_GP0_AWVALID(1'B0), .S_AXI_GP0_BREADY(1'B0), .S_AXI_GP0_RREADY(1'B0), .S_AXI_GP0_WLAST(1'B0), .S_AXI_GP0_WVALID(1'B0), .S_AXI_GP0_ARBURST(2'B0), .S_AXI_GP0_ARLOCK(2'B0), .S_AXI_GP0_ARSIZE(3'B0), .S_AXI_GP0_AWBURST(2'B0), .S_AXI_GP0_AWLOCK(2'B0), .S_AXI_GP0_AWSIZE(3'B0), .S_AXI_GP0_ARPROT(3'B0), .S_AXI_GP0_AWPROT(3'B0), .S_AXI_GP0_ARADDR(32'B0), .S_AXI_GP0_AWADDR(32'B0), .S_AXI_GP0_WDATA(32'B0), .S_AXI_GP0_ARCACHE(4'B0), .S_AXI_GP0_ARLEN(4'B0), .S_AXI_GP0_ARQOS(4'B0), .S_AXI_GP0_AWCACHE(4'B0), .S_AXI_GP0_AWLEN(4'B0), .S_AXI_GP0_AWQOS(4'B0), .S_AXI_GP0_WSTRB(4'B0), .S_AXI_GP0_ARID(6'B0), .S_AXI_GP0_AWID(6'B0), .S_AXI_GP0_WID(6'B0), .S_AXI_GP1_ARREADY(), .S_AXI_GP1_AWREADY(), .S_AXI_GP1_BVALID(), .S_AXI_GP1_RLAST(), .S_AXI_GP1_RVALID(), .S_AXI_GP1_WREADY(), .S_AXI_GP1_BRESP(), .S_AXI_GP1_RRESP(), .S_AXI_GP1_RDATA(), .S_AXI_GP1_BID(), .S_AXI_GP1_RID(), .S_AXI_GP1_ACLK(1'B0), .S_AXI_GP1_ARVALID(1'B0), .S_AXI_GP1_AWVALID(1'B0), .S_AXI_GP1_BREADY(1'B0), .S_AXI_GP1_RREADY(1'B0), .S_AXI_GP1_WLAST(1'B0), .S_AXI_GP1_WVALID(1'B0), .S_AXI_GP1_ARBURST(2'B0), .S_AXI_GP1_ARLOCK(2'B0), .S_AXI_GP1_ARSIZE(3'B0), .S_AXI_GP1_AWBURST(2'B0), .S_AXI_GP1_AWLOCK(2'B0), .S_AXI_GP1_AWSIZE(3'B0), .S_AXI_GP1_ARPROT(3'B0), .S_AXI_GP1_AWPROT(3'B0), .S_AXI_GP1_ARADDR(32'B0), .S_AXI_GP1_AWADDR(32'B0), .S_AXI_GP1_WDATA(32'B0), .S_AXI_GP1_ARCACHE(4'B0), .S_AXI_GP1_ARLEN(4'B0), .S_AXI_GP1_ARQOS(4'B0), .S_AXI_GP1_AWCACHE(4'B0), .S_AXI_GP1_AWLEN(4'B0), .S_AXI_GP1_AWQOS(4'B0), .S_AXI_GP1_WSTRB(4'B0), .S_AXI_GP1_ARID(6'B0), .S_AXI_GP1_AWID(6'B0), .S_AXI_GP1_WID(6'B0), .S_AXI_ACP_ARREADY(), .S_AXI_ACP_AWREADY(), .S_AXI_ACP_BVALID(), .S_AXI_ACP_RLAST(), .S_AXI_ACP_RVALID(), .S_AXI_ACP_WREADY(), .S_AXI_ACP_BRESP(), .S_AXI_ACP_RRESP(), .S_AXI_ACP_BID(), .S_AXI_ACP_RID(), .S_AXI_ACP_RDATA(), .S_AXI_ACP_ACLK(1'B0), .S_AXI_ACP_ARVALID(1'B0), .S_AXI_ACP_AWVALID(1'B0), .S_AXI_ACP_BREADY(1'B0), .S_AXI_ACP_RREADY(1'B0), .S_AXI_ACP_WLAST(1'B0), .S_AXI_ACP_WVALID(1'B0), .S_AXI_ACP_ARID(3'B0), .S_AXI_ACP_ARPROT(3'B0), .S_AXI_ACP_AWID(3'B0), .S_AXI_ACP_AWPROT(3'B0), .S_AXI_ACP_WID(3'B0), .S_AXI_ACP_ARADDR(32'B0), .S_AXI_ACP_AWADDR(32'B0), .S_AXI_ACP_ARCACHE(4'B0), .S_AXI_ACP_ARLEN(4'B0), .S_AXI_ACP_ARQOS(4'B0), .S_AXI_ACP_AWCACHE(4'B0), .S_AXI_ACP_AWLEN(4'B0), .S_AXI_ACP_AWQOS(4'B0), .S_AXI_ACP_ARBURST(2'B0), .S_AXI_ACP_ARLOCK(2'B0), .S_AXI_ACP_ARSIZE(3'B0), .S_AXI_ACP_AWBURST(2'B0), .S_AXI_ACP_AWLOCK(2'B0), .S_AXI_ACP_AWSIZE(3'B0), .S_AXI_ACP_ARUSER(5'B0), .S_AXI_ACP_AWUSER(5'B0), .S_AXI_ACP_WDATA(64'B0), .S_AXI_ACP_WSTRB(8'B0), .S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY), .S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY), .S_AXI_HP0_BVALID(S_AXI_HP0_BVALID), .S_AXI_HP0_RLAST(S_AXI_HP0_RLAST), .S_AXI_HP0_RVALID(S_AXI_HP0_RVALID), .S_AXI_HP0_WREADY(S_AXI_HP0_WREADY), .S_AXI_HP0_BRESP(S_AXI_HP0_BRESP), .S_AXI_HP0_RRESP(S_AXI_HP0_RRESP), .S_AXI_HP0_BID(S_AXI_HP0_BID), .S_AXI_HP0_RID(S_AXI_HP0_RID), .S_AXI_HP0_RDATA(S_AXI_HP0_RDATA), .S_AXI_HP0_ACLK(S_AXI_HP0_ACLK), .S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID), .S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID), .S_AXI_HP0_BREADY(S_AXI_HP0_BREADY), .S_AXI_HP0_RREADY(S_AXI_HP0_RREADY), .S_AXI_HP0_WLAST(S_AXI_HP0_WLAST), .S_AXI_HP0_WVALID(S_AXI_HP0_WVALID), .S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST), .S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK), .S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE), .S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST), .S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK), .S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE), .S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT), .S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT), .S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR), .S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR), .S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE), .S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN), .S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS), .S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE), .S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN), .S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS), .S_AXI_HP0_ARID(S_AXI_HP0_ARID), .S_AXI_HP0_AWID(S_AXI_HP0_AWID), .S_AXI_HP0_WID(S_AXI_HP0_WID), .S_AXI_HP0_WDATA(S_AXI_HP0_WDATA), .S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB), .S_AXI_HP1_ARREADY(), .S_AXI_HP1_AWREADY(), .S_AXI_HP1_BVALID(), .S_AXI_HP1_RLAST(), .S_AXI_HP1_RVALID(), .S_AXI_HP1_WREADY(), .S_AXI_HP1_BRESP(), .S_AXI_HP1_RRESP(), .S_AXI_HP1_BID(), .S_AXI_HP1_RID(), .S_AXI_HP1_RDATA(), .S_AXI_HP1_ACLK(1'B0), .S_AXI_HP1_ARVALID(1'B0), .S_AXI_HP1_AWVALID(1'B0), .S_AXI_HP1_BREADY(1'B0), .S_AXI_HP1_RREADY(1'B0), .S_AXI_HP1_WLAST(1'B0), .S_AXI_HP1_WVALID(1'B0), .S_AXI_HP1_ARBURST(2'B0), .S_AXI_HP1_ARLOCK(2'B0), .S_AXI_HP1_ARSIZE(3'B0), .S_AXI_HP1_AWBURST(2'B0), .S_AXI_HP1_AWLOCK(2'B0), .S_AXI_HP1_AWSIZE(3'B0), .S_AXI_HP1_ARPROT(3'B0), .S_AXI_HP1_AWPROT(3'B0), .S_AXI_HP1_ARADDR(32'B0), .S_AXI_HP1_AWADDR(32'B0), .S_AXI_HP1_ARCACHE(4'B0), .S_AXI_HP1_ARLEN(4'B0), .S_AXI_HP1_ARQOS(4'B0), .S_AXI_HP1_AWCACHE(4'B0), .S_AXI_HP1_AWLEN(4'B0), .S_AXI_HP1_AWQOS(4'B0), .S_AXI_HP1_ARID(6'B0), .S_AXI_HP1_AWID(6'B0), .S_AXI_HP1_WID(6'B0), .S_AXI_HP1_WDATA(64'B0), .S_AXI_HP1_WSTRB(8'B0), .S_AXI_HP2_ARREADY(), .S_AXI_HP2_AWREADY(), .S_AXI_HP2_BVALID(), .S_AXI_HP2_RLAST(), .S_AXI_HP2_RVALID(), .S_AXI_HP2_WREADY(), .S_AXI_HP2_BRESP(), .S_AXI_HP2_RRESP(), .S_AXI_HP2_BID(), .S_AXI_HP2_RID(), .S_AXI_HP2_RDATA(), .S_AXI_HP2_ACLK(1'B0), .S_AXI_HP2_ARVALID(1'B0), .S_AXI_HP2_AWVALID(1'B0), .S_AXI_HP2_BREADY(1'B0), .S_AXI_HP2_RREADY(1'B0), .S_AXI_HP2_WLAST(1'B0), .S_AXI_HP2_WVALID(1'B0), .S_AXI_HP2_ARBURST(2'B0), .S_AXI_HP2_ARLOCK(2'B0), .S_AXI_HP2_ARSIZE(3'B0), .S_AXI_HP2_AWBURST(2'B0), .S_AXI_HP2_AWLOCK(2'B0), .S_AXI_HP2_AWSIZE(3'B0), .S_AXI_HP2_ARPROT(3'B0), .S_AXI_HP2_AWPROT(3'B0), .S_AXI_HP2_ARADDR(32'B0), .S_AXI_HP2_AWADDR(32'B0), .S_AXI_HP2_ARCACHE(4'B0), .S_AXI_HP2_ARLEN(4'B0), .S_AXI_HP2_ARQOS(4'B0), .S_AXI_HP2_AWCACHE(4'B0), .S_AXI_HP2_AWLEN(4'B0), .S_AXI_HP2_AWQOS(4'B0), .S_AXI_HP2_ARID(6'B0), .S_AXI_HP2_AWID(6'B0), .S_AXI_HP2_WID(6'B0), .S_AXI_HP2_WDATA(64'B0), .S_AXI_HP2_WSTRB(8'B0), .S_AXI_HP3_ARREADY(), .S_AXI_HP3_AWREADY(), .S_AXI_HP3_BVALID(), .S_AXI_HP3_RLAST(), .S_AXI_HP3_RVALID(), .S_AXI_HP3_WREADY(), .S_AXI_HP3_BRESP(), .S_AXI_HP3_RRESP(), .S_AXI_HP3_BID(), .S_AXI_HP3_RID(), .S_AXI_HP3_RDATA(), .S_AXI_HP3_ACLK(1'B0), .S_AXI_HP3_ARVALID(1'B0), .S_AXI_HP3_AWVALID(1'B0), .S_AXI_HP3_BREADY(1'B0), .S_AXI_HP3_RREADY(1'B0), .S_AXI_HP3_WLAST(1'B0), .S_AXI_HP3_WVALID(1'B0), .S_AXI_HP3_ARBURST(2'B0), .S_AXI_HP3_ARLOCK(2'B0), .S_AXI_HP3_ARSIZE(3'B0), .S_AXI_HP3_AWBURST(2'B0), .S_AXI_HP3_AWLOCK(2'B0), .S_AXI_HP3_AWSIZE(3'B0), .S_AXI_HP3_ARPROT(3'B0), .S_AXI_HP3_AWPROT(3'B0), .S_AXI_HP3_ARADDR(32'B0), .S_AXI_HP3_AWADDR(32'B0), .S_AXI_HP3_ARCACHE(4'B0), .S_AXI_HP3_ARLEN(4'B0), .S_AXI_HP3_ARQOS(4'B0), .S_AXI_HP3_AWCACHE(4'B0), .S_AXI_HP3_AWLEN(4'B0), .S_AXI_HP3_AWQOS(4'B0), .S_AXI_HP3_ARID(6'B0), .S_AXI_HP3_AWID(6'B0), .S_AXI_HP3_WID(6'B0), .S_AXI_HP3_WDATA(64'B0), .S_AXI_HP3_WSTRB(8'B0), .FCLK_CLK0(FCLK_CLK0), .FCLK_CLK1(), .FCLK_CLK2(), .FCLK_CLK3(), .FCLK_RESET0_N(FCLK_RESET0_N), .FCLK_RESET1_N(), .FCLK_RESET2_N(), .FCLK_RESET3_N(), .IRQ_F2P(16'B0), .PS_SRSTB(PS_SRSTB), .PS_CLK(PS_CLK), .PS_PORB(PS_PORB) ); endmodule

/** * bsg_cache_non_blocking_dma.v * * DMA engine * * @author tommy * */ `include "bsg_defines.v" module bsg_cache_non_blocking_dma import bsg_cache_non_blocking_pkg::*; #(parameter `BSG_INV_PARAM(addr_width_p) , parameter `BSG_INV_PARAM(data_width_p) , parameter `BSG_INV_PARAM(block_size_in_words_p) , parameter `BSG_INV_PARAM(sets_p) , parameter `BSG_INV_PARAM(ways_p) , parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p) , parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p) , parameter lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p) , parameter byte_sel_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3) , parameter tag_width_lp=(addr_width_p-lg_sets_lp-lg_block_size_in_words_lp-byte_sel_width_lp) , parameter dma_cmd_width_lp=`bsg_cache_non_blocking_dma_cmd_width(ways_p,sets_p,tag_width_lp) , parameter dma_pkt_width_lp=`bsg_cache_non_blocking_dma_pkt_width(addr_width_p) , parameter data_mem_pkt_width_lp= `bsg_cache_non_blocking_data_mem_pkt_width(ways_p,sets_p,block_size_in_words_p,data_width_p) ) ( input clk_i , input reset_i // MHU , input [dma_cmd_width_lp-1:0] dma_cmd_i , input dma_cmd_v_i , output logic [dma_cmd_width_lp-1:0] dma_cmd_return_o , output logic done_o , output logic pending_o , input ack_i , output logic [lg_ways_lp-1:0] curr_dma_way_id_o , output logic [lg_sets_lp-1:0] curr_dma_index_o , output logic curr_dma_v_o // data_mem , output logic data_mem_pkt_v_o , output logic [data_mem_pkt_width_lp-1:0] data_mem_pkt_o , input [data_width_p-1:0] data_mem_data_i // DMA request , output logic [dma_pkt_width_lp-1:0] dma_pkt_o , output logic dma_pkt_v_o , input dma_pkt_yumi_i // DMA data in , input [data_width_p-1:0] dma_data_i , input dma_data_v_i , output logic dma_data_ready_o // DMA data out , output logic [data_width_p-1:0] dma_data_o , output logic dma_data_v_o , input dma_data_yumi_i ); // localparam // localparam counter_width_lp=`BSG_SAFE_CLOG2(block_size_in_words_p+1); localparam block_offset_width_lp=byte_sel_width_lp+lg_block_size_in_words_lp; localparam data_mask_width_lp=(data_width_p>>3); // casting structs // `declare_bsg_cache_non_blocking_dma_cmd_s(ways_p,sets_p,tag_width_lp); `declare_bsg_cache_non_blocking_dma_pkt_s(addr_width_p); bsg_cache_non_blocking_dma_cmd_s dma_cmd_in; bsg_cache_non_blocking_dma_cmd_s dma_cmd_r; bsg_cache_non_blocking_dma_pkt_s dma_pkt; assign dma_cmd_in = dma_cmd_i; assign dma_cmd_return_o = dma_cmd_r; assign dma_pkt_o = dma_pkt; `declare_bsg_cache_non_blocking_data_mem_pkt_s(ways_p,sets_p,block_size_in_words_p,data_width_p); bsg_cache_non_blocking_data_mem_pkt_s data_mem_pkt; assign data_mem_pkt_o = data_mem_pkt; // data_cmd dff // logic dma_cmd_dff_en; bsg_dff_reset_en #( .width_p(dma_cmd_width_lp) ) dma_cmd_dff ( .clk_i(clk_i) ,.reset_i(reset_i) ,.en_i(dma_cmd_dff_en) ,.data_i(dma_cmd_in) ,.data_o(dma_cmd_r) ); // dma states // typedef enum logic [2:0] { DMA_IDLE ,SEND_REFILL_ADDR ,SEND_EVICT_ADDR ,SEND_EVICT_DATA ,RECV_REFILL_DATA ,DMA_DONE } dma_state_e; dma_state_e dma_state_r; dma_state_e dma_state_n; // dma counter // logic counter_clear; logic counter_up; logic [counter_width_lp-1:0] counter_r; bsg_counter_clear_up #( .max_val_p(block_size_in_words_p) ,.init_val_p(0) ) dma_counter ( .clk_i(clk_i) ,.reset_i(reset_i) ,.clear_i(counter_clear) ,.up_i(counter_up) ,.count_o(counter_r) ); logic counter_fill_max; logic counter_evict_max; assign counter_fill_max = counter_r == (block_size_in_words_p-1); assign counter_evict_max = counter_r == block_size_in_words_p; // in fifo // logic in_fifo_v_lo; logic [data_width_p-1:0] in_fifo_data_lo; logic in_fifo_yumi_li; bsg_fifo_1r1w_small #( .width_p(data_width_p) ,.els_p(block_size_in_words_p) ) in_fifo ( .clk_i(clk_i) ,.reset_i(reset_i) ,.data_i(dma_data_i) ,.v_i(dma_data_v_i) ,.ready_o(dma_data_ready_o) ,.data_o(in_fifo_data_lo) ,.v_o(in_fifo_v_lo) ,.yumi_i(in_fifo_yumi_li) ); // out fifo // logic out_fifo_v_li; logic out_fifo_ready_lo; logic [data_width_p-1:0] out_fifo_data_li; bsg_two_fifo #( .width_p(data_width_p) ) out_fifo ( .clk_i(clk_i) ,.reset_i(reset_i) ,.v_i(out_fifo_v_li) ,.data_i(out_fifo_data_li) ,.ready_o(out_fifo_ready_lo) ,.v_o(dma_data_v_o) ,.data_o(dma_data_o) ,.yumi_i(dma_data_yumi_i) ); // comb logic // assign out_fifo_data_li = data_mem_data_i; logic [addr_width_p-1:0] dma_pkt_refill_addr; logic [addr_width_p-1:0] dma_pkt_evict_addr; assign dma_pkt_refill_addr = { dma_cmd_r.refill_tag, dma_cmd_r.index, {block_offset_width_lp{1'b0}} }; assign dma_pkt_evict_addr = { dma_cmd_r.evict_tag, dma_cmd_r.index, {block_offset_width_lp{1'b0}} }; always_comb begin done_o = 1'b0; pending_o = 1'b0; dma_cmd_dff_en = 1'b0; counter_clear = 1'b0; counter_up = 1'b0; out_fifo_v_li = 1'b0; in_fifo_yumi_li = 1'b0; data_mem_pkt_v_o = 1'b0; data_mem_pkt.write_not_read = 1'b0; data_mem_pkt.way_id = dma_cmd_r.way_id; data_mem_pkt.addr = { dma_cmd_r.index, counter_r[0+:lg_block_size_in_words_lp] }; // for load data_mem_pkt.sigext_op = 1'b0; data_mem_pkt.size_op = (2)'($clog2(data_width_p>>3)); data_mem_pkt.byte_sel = (byte_sel_width_lp)'(0); // for store data_mem_pkt.mask_op = 1'b1; data_mem_pkt.mask = {data_mask_width_lp{1'b1}}; data_mem_pkt.data = in_fifo_data_lo; dma_pkt_v_o = 1'b0; dma_pkt.write_not_read = 1'b0; dma_pkt.addr = dma_pkt_refill_addr; case (dma_state_r) // Wait for dma_cmd from MHU. DMA_IDLE: begin dma_cmd_dff_en = dma_cmd_v_i; dma_state_n = dma_cmd_v_i ? (dma_cmd_in.refill ? SEND_REFILL_ADDR : SEND_EVICT_ADDR) : DMA_IDLE; end // Send refill address by dma_req channel. SEND_REFILL_ADDR: begin dma_pkt_v_o = 1'b1; dma_pkt.write_not_read = 1'b0; dma_pkt.addr = dma_pkt_refill_addr; pending_o = 1'b1; dma_state_n = dma_pkt_yumi_i ? (dma_cmd_r.evict ? SEND_EVICT_ADDR : RECV_REFILL_DATA) : SEND_REFILL_ADDR; end // Send evict address by dma_req channel. SEND_EVICT_ADDR: begin data_mem_pkt_v_o = dma_pkt_yumi_i; // read the first word in block. counter_up = dma_pkt_yumi_i; counter_clear = dma_pkt_yumi_i; dma_pkt_v_o = 1'b1; dma_pkt.write_not_read = 1'b1; dma_pkt.addr = dma_pkt_evict_addr; pending_o = 1'b1; dma_state_n = dma_pkt_yumi_i ? SEND_EVICT_DATA : SEND_EVICT_ADDR; end // Read the cache block word by word, send it out by dma_data_o channel. SEND_EVICT_DATA: begin data_mem_pkt_v_o = out_fifo_ready_lo & ~counter_evict_max; out_fifo_v_li = 1'b1; counter_up = out_fifo_ready_lo & ~counter_evict_max; counter_clear = out_fifo_ready_lo & counter_evict_max; pending_o = 1'b1; dma_state_n = (out_fifo_ready_lo & counter_evict_max) ? (dma_cmd_r.refill ? RECV_REFILL_DATA : DMA_DONE) : SEND_EVICT_DATA; end // Receive the cache block word by word from dma_data_i channel, // and write it to data_mem. RECV_REFILL_DATA: begin data_mem_pkt_v_o = in_fifo_v_lo; data_mem_pkt.write_not_read = 1'b1; in_fifo_yumi_li = in_fifo_v_lo; counter_up = in_fifo_v_lo & ~counter_fill_max; counter_clear = in_fifo_v_lo & counter_fill_max; pending_o = 1'b1; dma_state_n = in_fifo_v_lo & counter_fill_max ? DMA_DONE : RECV_REFILL_DATA; end // DMA transaction is over, and wait for MHU to acknowledge it. DMA_DONE: begin done_o = 1'b1; counter_clear = ack_i; dma_state_n = ack_i ? DMA_IDLE : DMA_DONE; end // this should never happen, but if it does, return to IDLE. default: begin dma_state_n = DMA_IDLE; end endcase end assign curr_dma_v_o = (dma_state_r != DMA_IDLE); assign curr_dma_way_id_o = dma_cmd_r.way_id; assign curr_dma_index_o = dma_cmd_r.index; // synopsys sync_set_reset "reset_i" always_ff @ (posedge clk_i) begin if (reset_i) begin dma_state_r <= DMA_IDLE; end else begin dma_state_r <= dma_state_n; end end endmodule `BSG_ABSTRACT_MODULE(bsg_cache_non_blocking_dma)

// DESCRIPTION: Verilator: Verilog Test module // // This test demonstrates an issue with sign extension. // Assigning to localparms larger than 32 bits broke in 3.862 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Mike Thyer. module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam [ 0:0] one1_lp = 1; localparam [ 1:0] one2_lp = 1; localparam [ 2:0] one3_lp = 1; localparam [ 3:0] one4_lp = 1; localparam [ 4:0] one5_lp = 1; localparam [ 5:0] one6_lp = 1; localparam [ 6:0] one7_lp = 1; localparam [ 7:0] one8_lp = 1; localparam [ 8:0] one9_lp = 1; localparam [ 9:0] one10_lp = 1; localparam [19:0] one20_lp = 1; localparam [29:0] one30_lp = 1; localparam [30:0] one31_lp = 1; localparam [31:0] one32_lp = 1; localparam [32:0] one33_lp = 1; localparam [33:0] one34_lp = 1; localparam [34:0] one35_lp = 1; localparam [35:0] one36_lp = 1; localparam [36:0] one37_lp = 1; localparam [37:0] one38_lp = 1; localparam [38:0] one39_lp = 1; localparam [39:0] one40_lp = 1; localparam [49:0] one50_lp = 1; localparam [59:0] one60_lp = 1; localparam [60:0] one61_lp = 1; localparam [61:0] one62_lp = 1; localparam [62:0] one63_lp = 1; localparam [63:0] one64_lp = 1; localparam [64:0] one65_lp = 1; localparam [65:0] one66_lp = 1; localparam [66:0] one67_lp = 1; localparam [67:0] one68_lp = 1; localparam [68:0] one69_lp = 1; localparam [69:0] one70_lp = 1; bit all_ok = 1; initial begin `ifdef TEST_VERBOSE $display("one1_lp : %x %d", one1_lp, one1_lp==1); $display("one2_lp : %x %d", one2_lp, one2_lp==1); $display("one3_lp : %x %d", one3_lp, one3_lp==1); $display("one4_lp : %x %d", one4_lp, one4_lp==1); $display("one5_lp : %x %d", one5_lp, one5_lp==1); $display("one6_lp : %x %d", one6_lp, one6_lp==1); $display("one7_lp : %x %d", one7_lp, one7_lp==1); $display("one8_lp : %x %d", one8_lp, one8_lp==1); $display("one9_lp : %x %d", one9_lp, one9_lp==1); $display("one10_lp: %x %d", one10_lp, one10_lp==1); $display("one20_lp: %x %d", one20_lp, one20_lp==1); $display("one30_lp: %x %d", one30_lp, one30_lp==1); $display("one31_lp: %x %d", one31_lp, one31_lp==1); $display("one32_lp: %x %d", one32_lp, one32_lp==1); $display("one33_lp: %x %d", one33_lp, one33_lp==1); $display("one34_lp: %x %d", one34_lp, one34_lp==1); $display("one35_lp: %x %d", one35_lp, one35_lp==1); $display("one36_lp: %x %d", one36_lp, one36_lp==1); $display("one37_lp: %x %d", one37_lp, one37_lp==1); $display("one38_lp: %x %d", one38_lp, one38_lp==1); $display("one39_lp: %x %d", one39_lp, one39_lp==1); $display("one40_lp: %x %d", one40_lp, one40_lp==1); $display("one50_lp: %x %d", one50_lp, one50_lp==1); $display("one60_lp: %x %d", one60_lp, one60_lp==1); $display("one61_lp: %x %d", one61_lp, one61_lp==1); $display("one62_lp: %x %d", one62_lp, one62_lp==1); $display("one63_lp: %x %d", one63_lp, one63_lp==1); $display("one64_lp: %x %d", one64_lp, one64_lp==1); $display("one65_lp: %x %d", one65_lp, one65_lp==1); $display("one66_lp: %x %d", one66_lp, one66_lp==1); $display("one67_lp: %x %d", one67_lp, one67_lp==1); $display("one68_lp: %x %d", one68_lp, one68_lp==1); $display("one69_lp: %x %d", one69_lp, one69_lp==1); $display("one70_lp: %x %d", one70_lp, one70_lp==1); `endif all_ok &= one1_lp == 1; all_ok &= one2_lp == 1; all_ok &= one3_lp == 1; all_ok &= one4_lp == 1; all_ok &= one5_lp == 1; all_ok &= one6_lp == 1; all_ok &= one7_lp == 1; all_ok &= one8_lp == 1; all_ok &= one9_lp == 1; all_ok &= one10_lp == 1; all_ok &= one20_lp == 1; all_ok &= one30_lp == 1; all_ok &= one31_lp == 1; all_ok &= one32_lp == 1; all_ok &= one33_lp == 1; all_ok &= one34_lp == 1; all_ok &= one35_lp == 1; all_ok &= one36_lp == 1; all_ok &= one37_lp == 1; all_ok &= one38_lp == 1; all_ok &= one39_lp == 1; all_ok &= one40_lp == 1; all_ok &= one50_lp == 1; all_ok &= one60_lp == 1; all_ok &= one61_lp == 1; all_ok &= one62_lp == 1; all_ok &= one63_lp == 1; all_ok &= one64_lp == 1; all_ok &= one65_lp == 1; all_ok &= one66_lp == 1; all_ok &= one67_lp == 1; all_ok &= one68_lp == 1; all_ok &= one69_lp == 1; all_ok &= one70_lp == 1; if (!all_ok) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule

// Library - static, Cell - th44w3, View - schematic // LAST TIME SAVED: May 23 17:58:12 2014 // NETLIST TIME: May 23 17:58:31 2014 `timescale 1ns / 1ns module th44w3 ( y, a, b, c, d ); output y; input a, b, c, d; specify specparam CDS_LIBNAME = "static"; specparam CDS_CELLNAME = "th44w3"; specparam CDS_VIEWNAME = "schematic"; endspecify nfet_b N6 ( .d(net042), .g(c), .s(cds_globals.gnd_), .b(cds_globals.gnd_)); nfet_b N5 ( .d(net32), .g(a), .s(net44), .b(cds_globals.gnd_)); nfet_b N4 ( .d(net042), .g(d), .s(cds_globals.gnd_), .b(cds_globals.gnd_)); nfet_b N10 ( .d(net32), .g(y), .s(net042), .b(cds_globals.gnd_)); nfet_b N3 ( .d(net44), .g(y), .s(cds_globals.gnd_), .b(cds_globals.gnd_)); nfet_b N2 ( .d(net042), .g(b), .s(cds_globals.gnd_), .b(cds_globals.gnd_)); nfet_b N1 ( .d(net32), .g(a), .s(net042), .b(cds_globals.gnd_)); pfet_b P7 ( .b(cds_globals.vdd_), .g(b), .s(net027), .d(net34)); pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(net49), .d(net32)); pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_), .d(net027)); pfet_b P3 ( .b(cds_globals.vdd_), .g(d), .s(net47), .d(net32)); pfet_b P2 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net47)); pfet_b P1 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_), .d(net027)); pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_), .d(net49)); inv I2 ( y, net32); endmodule

/////////////////////////////////////////////////////////////////////////////// // // Silicon Spectrum Corporation - All Rights Reserved // Copyright (C) 2009 - All rights reserved // // This File is copyright Silicon Spectrum Corporation and is licensed for // use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the // license agreement. // // This code may not be used as a basis for new development without a written // agreement between Silicon Spectrum and the licensee. // // New development includes, but is not limited to new designs based on this // code, using this code to aid verification or using this code to test code // developed independently by the licensee. // // This copyright notice must be maintained as written, modifying or removing // this copyright header will be considered a breach of the license agreement. // // The licensee may modify the code for the licensed project. // Silicon Spectrum does not give up the copyright to the original // file or encumber in any way. // // Use of this file is restricted by the license agreement between the // licensee and Silicon Spectrum, Inc. // // // Title : Bit BLT State Machine // File : dex_smblt.v // Author : Jim MacLeod // Created : 30-Dec-2008 // RCS File : $Source:$ // Status : $Id:$ // // /////////////////////////////////////////////////////////////////////////////// // // Description : // Included by dex_sm.v // ////////////////////////////////////////////////////////////////////////////// // // Modules Instantiated: // /////////////////////////////////////////////////////////////////////////////// // // Modification History: // // $Log:$ // /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// `timescale 1ns / 10ps module dex_smblt ( input de_clk, input de_rstn, input [1:0] dir, input goblt, input stpl_pk_1, input mcrdy, input cache_rdy, input signx, input signy, input yeqz, input xeqz, input read_2, input ps16_1, input ps32_1, input ps8_2, input ps16_2, input ps32_2, input apat8_2, input apat32_2, input frst_pass, input last_pass, input multi, input soc, input rmw, input eor, input local_sol, input frst8_1, input mw_fip, input eol_2, input end_pass, output reg [21:0] b_op, output reg [4:0] b_ksel, output reg b_set_busy, output reg b_clr_busy, output reg b_mem_req, output reg b_mem_rd, output reg b_ld_wcnt, output reg b_dchgy, output reg b_rstn_wad, output reg b_ld_rad, output reg b_set_sol, output reg b_set_eol, output reg b_set_eor, output reg b_ld_msk, output reg b_mul, output reg b_mod8, output reg b_mod32, output reg b_rst_cr, output reg b_set_soc, output reg b_clr_soc, output reg b_set_multi, output reg b_clr_multi, output reg b_set_frst_pass, output reg b_clr_frst_pass, output reg b_set_end, output reg b_clr_end, output reg b_set_last_pass, output reg b_clr_last_pass, output reg b_clr_ld_disab, output reg b_cin, output b_sdwn, output b_ddwn ); // The following are from de_param.h //`include "de_param.h" parameter one = 5'h1, B_WAIT = 5'h0, BS1 = 5'h1, BS2 = 5'h2, BS3 = 5'h3, BS4 = 5'h4, BS5 = 5'h5, BS6 = 5'h6, BS7 = 5'h7, BS8 = 5'h8, BS9 = 5'h9, BS10 = 5'ha, BS11 = 5'hb, BS12 = 5'hc, BS13 = 5'hd, BR1 = 5'he, BR2 = 5'hf, BR3 = 5'h10, BR4 = 5'h11, BR5 = 5'h12, BW1 = 5'h13, BW2 = 5'h14, BW3 = 5'h15, BW4 = 5'h16, BW5 = 5'h17, BW6 = 5'h18, BNL1 = 5'h19, BNL2 = 5'h1a, BNL3 = 5'h1b, BNL4 = 5'h1c, BNL5 = 5'h1d, BNL6 = 5'h1e, BNL7 = 5'h1f, size = 5'h2, // wrk0x and wrk0y wr_seg = 5'hd, // wrk7x noop = 5'h0, // noop address. pline = 5'h10,// pipeline address. sorgl = 5'he, // src org address low nibble. dorgl = 5'hf, // src org address low nibble. amcn = 5'h4, // ax-k, ay-k apcn_d = 5'h8, // {ax + const,ax + const} amcn_d = 5'h14,// {ax - const,ax - const} sub_d = 5'h17,// {ax - bx,ax - bx} wrhl = 2'b00,// define write enables wrhi = 2'b01, wrlo = 2'b10,// define write enables wrno = 2'b11,// define write enables D24 = 5'hd, // not used D48 = 5'he, // not used D95 = 5'h10, D94 = 5'h12, D96 = 5'h13, dst = 5'h1, // destination/end point add = 5'h1, // ax + bx, ay + by sub = 5'h12,// ax - bx, ay - by addnib = 5'h2, // ax + bx(nibble) movx = 5'hf, // bx--> fy, by--> fx dst_sav = 5'h9, // dst & wrk1y src = 5'h0, // source/start point register src_sav = 5'ha, // src & wrk1x mov = 5'hd, // bx--> fx, by--> fy mov_k = 5'he, // move constant rd_wrds = 5'h5, // wrk3x rd_wrds_sav = 5'hb, // wrk3x & wrk5x wr_wrds_sav = 5'hc, // wrk4x & wrk6x div16 = 5'ha, // bx/16 + wadj. two = 5'h2, four = 5'h4, eight = 5'h6, movmod = 5'h5, // ay + by mod 8 or 32 adr_ofs = 5'h5, mod_src = 5'h6, apcn = 5'h6, // ax+k, ay+k zoom = 5'h4, // wrk2x & wrk2y nib = 5'h11,// nibble sav_yzoom = 5'h5, // wrk3y wr_wrds = 5'h6, // wrk4x D16 = 5'h8, seven = 5'h5, D64 = 5'h11, D112 = 5'h14, D128 = 5'h15, D256 = 5'h7, sav_rd_wrds = 5'h7, // wrk5x sav_wr_wrds = 5'h8, // wrk6x sav_src_dst = 5'h3; // wrk1x & wrk1y /****************************************************************/ /* DEFINE PARAMETERS */ /****************************************************************/ /* define internal wires and make assignments */ reg [4:0] b_cs; reg [4:0] b_ns; assign b_sdwn = ~dir[0]; assign b_ddwn = ~dir[0]; /* create the state register */ always @(posedge de_clk or negedge de_rstn) begin if(!de_rstn) b_cs <= 5'b0; else b_cs <= b_ns; end always @* begin b_op = 22'b00000_00000_00000_00000_11; b_ksel = one; b_set_busy = 1'b0; b_clr_busy = 1'b0; b_ld_wcnt = 1'b0; b_mem_req = 1'b0; b_mem_rd = 1'b0; b_dchgy = 1'b0; b_rstn_wad = 1'b0; b_ld_rad = 1'b0; b_set_sol = 1'b0; b_set_eol = 1'b0; b_mem_req = 1'b0; b_mem_rd = 1'b0; b_set_eor = 1'b0; b_ld_msk = 1'b0; b_mul = 1'b0; b_mod32 = 1'b0; b_mod8 = 1'b0; b_rst_cr = 1'b0; b_set_soc = 1'b0; b_clr_soc = 1'b0; b_set_multi = 1'b0; b_clr_multi = 1'b0; b_set_frst_pass = 1'b0; b_clr_frst_pass = 1'b0; b_set_end = 1'b0; b_clr_end = 1'b0; b_set_last_pass = 1'b0; b_clr_last_pass = 1'b0; b_clr_ld_disab = 1'b0; b_cin = 1'b0; case(b_cs) /* synopsys full_case parallel_case */ /* Wait for goblt. */ B_WAIT: if(goblt && !stpl_pk_1) begin b_ns=BS1; b_set_busy = 1'b1; b_set_frst_pass = 1'b1; b_mul = 1'b1; b_op={size,noop,amcn,noop,wrno}; if(ps32_1)b_ksel=D24; else if(ps16_1)b_ksel=D48; else b_ksel=D96; end else b_ns= B_WAIT; /* multiply the src, dst, and size by 2 for 16BPP, or 4 for 32BPP. */ /* add org low nibble to destination point */ /* save the original destination X, to use on the next scan line. */ BS1: begin if(frst_pass) begin // b_op={dst,noop,apcn_d,dst_sav,wrhl}; b_op={dorgl,dst,addnib,dst_sav,wrhl}; if(read_2)b_cin = 1'b1; end else b_op={wr_seg,noop,movx,size,wrlo}; if(!read_2)b_ns=BS5; else b_ns=BS2; b_set_sol=1'b1; b_set_soc=1'b1; b_clr_ld_disab = 1'b1; // if(ps32_2) b_ksel=four; // else if(ps16_2)b_ksel=two; // else b_ksel=one; end BS2: begin if(!read_2)b_ns=BS5; else b_ns=BS3; if(dir[1] & !signx & !xeqz) begin b_set_multi = 1'b1; if(frst_pass)b_op={pline,noop,amcn_d,dst_sav,wrhl}; else b_op={dst,noop,amcn_d,dst_sav,wrhl}; end else if (dir[1]) begin b_set_last_pass = 1'b1; if(frst_pass) b_op={pline,size,sub_d,dst_sav,wrhl}; else b_op={dst,size,sub_d,dst_sav,wrhl}; end else b_op={pline,noop,amcn_d,dst_sav,wrhl}; if (dir[1] & frst_pass & ps32_2)b_ksel=D94; else if(dir[1] & frst_pass & ps16_2)b_ksel=D95; // if (dir[1] & frst_pass & ps32_2)b_ksel=D95; // else if(dir[1] & frst_pass & ps16_2)b_ksel=D96; else if(dir[1]) b_ksel=D96; else b_ksel=one; end /* add org low nibble to source point */ /* save the original source X, to use on the next scan line. */ BS3: begin if(frst_pass) begin b_op={sorgl,src,add,src_sav,wrhi}; b_cin = 1'b1; // b_op={src,noop,apcn_d,dst_sav,wrhl}; end // if(ps32_2) b_ksel=four; // else if(ps16_2)b_ksel=two; // else b_ksel=one; b_ns=BS4; end BS4: begin b_ns=BS5; if (multi & frst_pass & !last_pass) b_op={pline,noop,amcn,src_sav,wrhi}; else if(multi & !frst_pass & !last_pass) b_op={src,noop,amcn,src_sav,wrhi}; else if(multi & frst_pass & last_pass) b_op={pline,size,sub,src_sav,wrhi}; else if(multi & !frst_pass & last_pass) b_op={src,size,sub,src_sav,wrhi}; else if(dir[1]) b_op={pline,size,sub,src_sav,wrhi}; else b_op={pline,noop,amcn,src_sav,wrhi}; if (dir[1] & frst_pass & ps32_2)b_ksel=D94; else if(dir[1] & frst_pass & ps16_2)b_ksel=D95; // if (dir[1] & frst_pass & ps32_2)b_ksel=D95; // else if(dir[1] & frst_pass & ps16_2)b_ksel=D96; else if(dir[1]) b_ksel=D96; else b_ksel=one; end /* calculate the read words per line adjusted X size. */ BS5: begin if(apat32_2 | apat8_2 | (multi & ~last_pass))b_ns=BS6; else b_ns=BS8; if(apat32_2 | apat8_2)b_op={noop,noop,mov_k,rd_wrds_sav,wrhi}; else if(multi & ~last_pass)b_op={size,noop,amcn,size,wrhi}; else b_op={pline,size,div16,rd_wrds_sav,wrhi}; if(multi)b_ksel=D96; if(ps32_2 & apat32_2 & ~multi)b_ksel=eight; if(ps16_2 & apat32_2 & ~multi)b_ksel=four; if(ps8_2 & apat32_2 & ~multi) b_ksel=two; if(ps32_2 & apat8_2 & ~multi)b_ksel=two; if((ps16_2 | ps8_2) & apat8_2 & ~multi)b_ksel=one; end /* Calculate the offset between the source and destination. */ /* this code is exicuted for area patterns only.*/ BS6: begin b_ns=BS7; if(apat32_2)b_mod32 = 1'b1; if(apat8_2)b_mod8 = 1'b1; if(multi)b_op={noop,noop,mov_k,noop,wrno}; else b_op={noop,src,movmod,adr_ofs,wrlo}; b_ksel=D96; end /* this code is exicuted for area patterns only.*/ /* clear the lower 3 or 5 bits of the Y source.*/ BS7: begin b_ns=BS8; if(multi)b_op={src,pline,div16,rd_wrds_sav,wrhi}; else b_op={src,src,sub,mod_src,wrno}; if(apat32_2)b_mod32 = 1'b1; if(apat8_2)b_mod8 = 1'b1; end /* this code is exicuted for area patterns only.*/ /* add the source offset to the source. */ BS8: begin b_ns=BS9; if(multi & ~last_pass)b_op={noop,noop,mov_k,noop,wrno}; else b_op={pline,dst,add,mod_src,wrlo}; if(apat32_2)b_mod32 = 1'b1; if(apat8_2)b_mod8 = 1'b1; b_ksel=D96; end /* calculate the write words per line adjusted X size. */ BS9: begin b_ns=BS10; if(multi & ~last_pass)b_op={dst,pline,div16,wr_wrds_sav,wrhi}; else b_op={dst,size,div16,wr_wrds_sav,wrhi}; end /* generate the start and end mask to be loaded in BS10. */ BS10: begin b_ns=BS11; if(!dir[1] | last_pass)b_op={dst,size,add,noop,wrno}; else b_op={dst,size,apcn,noop,wrno}; b_rstn_wad = 1'b1; b_ksel=D96; end BS11: begin b_ld_msk=1'b1; /* load the mask. */ b_ns=BS12; if(multi)b_op={noop,src,mov,zoom,wrlo}; end /* source minus destination nibble mode. for FIFO ADDRESS read = write, read = write-1. */ /* this will set the first read 8 flag if source nibble is less than destination nibble.*/ BS12: begin if(mcrdy) begin b_ns=BS13; b_ld_rad = 1'b1; if(apat32_2 || apat8_2)b_op={mod_src,adr_ofs,add,src,wrlo}; else b_op={src,dst,nib,noop,wrno}; end else b_ns=BS12; end BS13: begin b_ns=BR1; if(multi && soc)b_op={noop,dst,mov,sav_yzoom,wrlo}; b_clr_soc = 1'b1; end /* write words minus max page count of eight for no reads. */ /* or seven for commands with reads. */ BR1: begin if(!read_2) begin b_ns=BW3; b_op={wr_wrds,noop,amcn,noop,wrno}; if(!rmw)b_ksel=eight; else b_ksel=four; end else if(eor && (apat32_2 || apat8_2)) begin b_ns=BW3; b_op={wr_wrds,noop,amcn,noop,wrno}; if(!rmw)b_ksel=eight; else b_ksel=four; end else if(eor) begin b_ns=BW3; b_ksel=seven; b_op={wr_wrds,noop,amcn,noop,wrno}; end else if(frst_pass) begin b_ns=BR2; b_op={noop,size,movx,wr_seg,wrhi}; end else b_ns=BR2; b_clr_frst_pass = 1'b1; end /* read words minus max page count of eight reads. */ BR2: begin b_op={rd_wrds,noop,amcn,noop,wrno}; b_ns=BR3; if((local_sol & !frst8_1) | apat32_2 | apat8_2)b_ksel=eight; else b_ksel=seven; end /* wait for the pipeline. */ /* subtract 7 or 8 from the read words. */ BR3: begin b_ns=BR4; b_op={rd_wrds,noop,amcn,rd_wrds,wrhi}; if((local_sol & !frst8_1) | apat32_2 | apat8_2)b_ksel=eight; else b_ksel=seven; end BR4: begin b_ld_wcnt=1'b1; /* this signal is externally delayed one clock. */ if(signx || xeqz) b_op={noop,rd_wrds,mov,noop,wrno}; if(!signx && !xeqz)b_op={noop,noop,mov_k,noop,wrno}; if(local_sol & !frst8_1)b_ksel=eight; else b_ksel=seven; b_ns=BR5; end BR5: begin if(signx | xeqz) b_set_eor=1'b1; b_ns=BW1; end /* Begin the write portion of the bit blt state machine. */ /* read words minus max page count of eight reads. */ BW1: if(mcrdy && !mw_fip) begin b_op={wr_wrds,noop,amcn,noop,wrno}; if(read_2 && apat32_2 && (ps8_2 || ps16_2))b_ns=BW2; else if(read_2 && apat8_2)b_ns=BW2; else b_ns=BW3; if(read_2)begin b_mem_req=1'b1; b_mem_rd=1'b1; end if(read_2 && !(apat32_2 || apat8_2)) b_ksel=seven; else if(!rmw)b_ksel=eight; else b_ksel=four; end else b_ns=BW1; BW2: if(mcrdy && !mw_fip) begin b_op={wr_wrds,noop,amcn,noop,wrno}; b_ns=BW3; b_mem_req=1'b1; b_mem_rd=1'b1; if(read_2 && !(apat32_2 || apat8_2)) b_ksel=seven; else if(!rmw)b_ksel=eight; else b_ksel=four; end else b_ns=BW2; /* add 128 or 112 to the source x pointer. */ BW3: begin b_ns=BW4; if(local_sol & !frst8_1)b_ksel=D128; else b_ksel=D112; if(!apat32_2)b_op={src,noop,apcn,src,wrhi}; end /* test to see which is less and use that one. */ /* and wait if memory controller is busy. */ BW4: begin b_ns=BW5; if(read_2 && !(apat32_2 || apat8_2))b_ksel=seven; else if(rmw)b_ksel=four; else b_ksel=eight; b_ld_wcnt=1'b1; if(signx | xeqz) begin b_op={noop,wr_wrds,mov,noop,wrno}; b_set_eol=1'b1; end else begin b_op={noop,noop,mov_k,noop,wrno}; end end /* subtract 7 from the write words. */ BW5: begin b_ns=BW6; b_op={wr_wrds,noop,amcn,wr_wrds,wrhi}; if(read_2 && !(apat32_2 || apat8_2))b_ksel=seven; else if(rmw)b_ksel=four; else b_ksel=eight; end /* add 128 to the destination x pointer. */ BW6: begin if(mcrdy && !eol_2 && cache_rdy) begin b_mem_req=1'b1; b_ns=BR1; b_op={dst,noop,apcn,dst,wrhi}; if(read_2 && !(apat32_2 || apat8_2))b_ksel=D112; else if(rmw)b_ksel=D64; else b_ksel=D128; end else if(mcrdy && eol_2 && cache_rdy) /* decrement the Y size register. */ begin b_mem_req=1'b1; b_ns=BNL1; b_op={size,noop,amcn,size,wrlo}; end else b_ns=BW6; end /* restore the write words per line. */ BNL1: begin b_dchgy = 1'b1; b_op={noop,sav_wr_wrds,mov,wr_wrds,wrhi}; b_ns=BNL2; end /* If Y size register goes to zero the bit blt is all done. */ /* else go back and read more data. */ /* Restore the original X destination registers. */ BNL2: begin if(yeqz & multi & ~last_pass) begin b_rst_cr = 1'b1; b_ns=BNL4; b_op={noop,sav_yzoom,mov,dst,wrlo}; // restore dst Y b_set_end = 1'b1; end else if(yeqz) begin b_clr_last_pass = 1'b1; b_clr_multi = 1'b1; b_rst_cr = 1'b1; b_clr_busy = 1'b1; b_ns=B_WAIT; end else begin if(read_2 && (apat32_2 || apat8_2))b_ns=BNL4; else if(read_2)b_ns=BNL3; else b_ns=BS13; b_set_sol=1'b1; b_op={noop,sav_src_dst,movx,dst,wrhi}; // restore dst Y end end /* Increment or decrement the source Y registers. */ BNL3: begin b_ns=BNL6; if(dir[0])b_op={src,noop,amcn,src,wrlo}; else b_op={src,noop,apcn,src,wrlo}; end /* increment the modulo source Y counter. */ BNL4: begin b_ns=BNL5; b_ksel=one; // b_rstn_wad=1'b1; if(apat32_2)b_mod32 = 1'b1; if(apat8_2)b_mod8 = 1'b1; if(multi)b_op={noop,zoom,mov,src,wrlo}; // restore src Y else b_op={mod_src,noop,apcn,mod_src,wrlo}; end /* add the source Y offset to the source Y. */ BNL5: begin if(multi) begin b_op={noop,sav_src_dst,movx,dst,wrhi}; // restore dstx b_ns=BNL6; end else begin b_op={pline,adr_ofs,add,src,wrlo}; b_ns=BNL6; end end /* Restore the original X source registers. */ BNL6: begin b_op={noop,sav_src_dst,mov,src,wrhi}; b_ns=BNL7; end /* restore the read words per line. */ BNL7: begin if(multi & end_pass) begin b_op={size,noop,amcn,noop,wrno}; b_ns=BS1; b_clr_end = 1'b1; end else begin b_op={noop,sav_rd_wrds,mov,rd_wrds,wrhi}; b_ns=BS13; end b_ksel=D96; end endcase end endmodule

// ========== Copyright Header Begin ========================================== // // OpenSPARC T1 Processor File: cpx_buf_p3.v // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. // // The above named program is free software; you can redistribute it and/or // modify it under the terms of the GNU General Public // License version 2 as published by the Free Software Foundation. // // The above named program is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU // General Public License for more details. // // You should have received a copy of the GNU General Public // License along with this work; if not, write to the Free Software // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. // // ========== Copyright Header End ============================================ //////////////////////////////////////////////////////////////////////// /* // Description: datapath portion of CPX */ //////////////////////////////////////////////////////////////////////// // Global header file includes //////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////// // Local header file includes / local defines //////////////////////////////////////////////////////////////////////// `include "sys.h" `include "iop.h" module cpx_buf_p3(/*AUTOARG*/ // Outputs scache3_cpx_req_bufp3_cq, scache3_cpx_atom_bufp3_cq, io_cpx_req_bufp3_cq, cpx_scache3_grant_bufp3_ca_l, cpx_spc5_data_rdy_bufp3_cx, cpx_spc6_data_rdy_bufp3_cx, cpx_spc7_data_rdy_bufp3_cx, arbcp0_cpxdp_grant_bufp3_ca_l_5, arbcp0_cpxdp_q0_hold_bufp3_ca_5, arbcp0_cpxdp_qsel0_bufp3_ca_l_5, arbcp0_cpxdp_qsel1_bufp3_ca_5, arbcp0_cpxdp_shift_bufp3_cx_l_5, arbcp1_cpxdp_grant_bufp3_ca_l_5, arbcp1_cpxdp_q0_hold_bufp3_ca_5, arbcp1_cpxdp_qsel0_bufp3_ca_l_5, arbcp1_cpxdp_qsel1_bufp3_ca_5, arbcp1_cpxdp_shift_bufp3_cx_l_5, arbcp2_cpxdp_grant_bufp3_ca_l_5, arbcp2_cpxdp_q0_hold_bufp3_ca_5, arbcp2_cpxdp_qsel0_bufp3_ca_l_5, arbcp2_cpxdp_qsel1_bufp3_ca_5, arbcp2_cpxdp_shift_bufp3_cx_l_5, arbcp3_cpxdp_grant_bufp3_ca_l_5, arbcp3_cpxdp_q0_hold_bufp3_ca_5, arbcp3_cpxdp_qsel0_bufp3_ca_l_5, arbcp3_cpxdp_qsel1_bufp3_ca_5, arbcp3_cpxdp_shift_bufp3_cx_l_5, arbcp4_cpxdp_grant_bufp3_ca_l_5, arbcp4_cpxdp_q0_hold_bufp3_ca_5, arbcp4_cpxdp_qsel0_bufp3_ca_l_5, arbcp4_cpxdp_qsel1_bufp3_ca_5, arbcp4_cpxdp_shift_bufp3_cx_l_5, arbcp5_cpxdp_grant_bufp3_ca_l_5, arbcp5_cpxdp_q0_hold_bufp3_ca_5, arbcp5_cpxdp_qsel0_bufp3_ca_l_5, arbcp5_cpxdp_qsel1_bufp3_ca_5, arbcp5_cpxdp_shift_bufp3_cx_l_5, arbcp6_cpxdp_grant_bufp3_ca_l_5, arbcp6_cpxdp_q0_hold_bufp3_ca_5, arbcp6_cpxdp_qsel0_bufp3_ca_l_5, arbcp6_cpxdp_qsel1_bufp3_ca_5, arbcp6_cpxdp_shift_bufp3_cx_l_5, arbcp7_cpxdp_grant_bufp3_ca_l_5, arbcp7_cpxdp_q0_hold_bufp3_ca_5, arbcp7_cpxdp_qsel0_bufp3_ca_l_5, arbcp7_cpxdp_qsel1_bufp3_ca_5, arbcp7_cpxdp_shift_bufp3_cx_l_5, arbcp0_cpxdp_grant_bufp3_ca_l_2, arbcp0_cpxdp_q0_hold_bufp3_ca_2, arbcp0_cpxdp_qsel0_bufp3_ca_l_2, arbcp0_cpxdp_qsel1_bufp3_ca_2, arbcp0_cpxdp_shift_bufp3_cx_l_2, arbcp1_cpxdp_grant_bufp3_ca_l_2, arbcp1_cpxdp_q0_hold_bufp3_ca_2, arbcp1_cpxdp_qsel0_bufp3_ca_l_2, arbcp1_cpxdp_qsel1_bufp3_ca_2, arbcp1_cpxdp_shift_bufp3_cx_l_2, arbcp2_cpxdp_grant_bufp3_ca_l_2, arbcp2_cpxdp_q0_hold_bufp3_ca_2, arbcp2_cpxdp_qsel0_bufp3_ca_l_2, arbcp2_cpxdp_qsel1_bufp3_ca_2, arbcp2_cpxdp_shift_bufp3_cx_l_2, arbcp3_cpxdp_grant_bufp3_ca_l_2, arbcp3_cpxdp_q0_hold_bufp3_ca_2, arbcp3_cpxdp_qsel0_bufp3_ca_l_2, arbcp3_cpxdp_qsel1_bufp3_ca_2, arbcp3_cpxdp_shift_bufp3_cx_l_2, arbcp4_cpxdp_grant_bufp3_ca_l_2, arbcp4_cpxdp_q0_hold_bufp3_ca_2, arbcp4_cpxdp_qsel0_bufp3_ca_l_2, arbcp4_cpxdp_qsel1_bufp3_ca_2, arbcp4_cpxdp_shift_bufp3_cx_l_2, arbcp5_cpxdp_grant_bufp3_ca_l_2, arbcp5_cpxdp_q0_hold_bufp3_ca_2, arbcp5_cpxdp_qsel0_bufp3_ca_l_2, arbcp5_cpxdp_qsel1_bufp3_ca_2, arbcp5_cpxdp_shift_bufp3_cx_l_2, arbcp6_cpxdp_grant_bufp3_ca_l_2, arbcp6_cpxdp_q0_hold_bufp3_ca_2, arbcp6_cpxdp_qsel0_bufp3_ca_l_2, arbcp6_cpxdp_qsel1_bufp3_ca_2, arbcp6_cpxdp_shift_bufp3_cx_l_2, arbcp7_cpxdp_grant_bufp3_ca_l_2, arbcp7_cpxdp_q0_hold_bufp3_ca_2, arbcp7_cpxdp_qsel0_bufp3_ca_l_2, arbcp7_cpxdp_qsel1_bufp3_ca_2, arbcp7_cpxdp_shift_bufp3_cx_l_2, // Inputs scache3_cpx_req_bufp4_cq, scache3_cpx_atom_bufp4_cq, io_cpx_req_bufp4_cq, cpx_scache3_grant_ca, cpx_spc5_data_rdy_cx, cpx_spc6_data_rdy_cx, cpx_spc7_data_rdy_cx, arbcp0_cpxdp_grant_arbbf_ca_5, arbcp0_cpxdp_q0_hold_arbbf_ca_l_5, arbcp0_cpxdp_qsel0_arbbf_ca_5, arbcp0_cpxdp_qsel1_arbbf_ca_l_5, arbcp0_cpxdp_shift_arbbf_cx_5, arbcp1_cpxdp_grant_arbbf_ca_5, arbcp1_cpxdp_q0_hold_arbbf_ca_l_5, arbcp1_cpxdp_qsel0_arbbf_ca_5, arbcp1_cpxdp_qsel1_arbbf_ca_l_5, arbcp1_cpxdp_shift_arbbf_cx_5, arbcp2_cpxdp_grant_arbbf_ca_5, arbcp2_cpxdp_q0_hold_arbbf_ca_l_5, arbcp2_cpxdp_qsel0_arbbf_ca_5, arbcp2_cpxdp_qsel1_arbbf_ca_l_5, arbcp2_cpxdp_shift_arbbf_cx_5, arbcp3_cpxdp_grant_arbbf_ca_5, arbcp3_cpxdp_q0_hold_arbbf_ca_l_5, arbcp3_cpxdp_qsel0_arbbf_ca_5, arbcp3_cpxdp_qsel1_arbbf_ca_l_5, arbcp3_cpxdp_shift_arbbf_cx_5, arbcp4_cpxdp_grant_arbbf_ca_5, arbcp4_cpxdp_q0_hold_arbbf_ca_l_5, arbcp4_cpxdp_qsel0_arbbf_ca_5, arbcp4_cpxdp_qsel1_arbbf_ca_l_5, arbcp4_cpxdp_shift_arbbf_cx_5, arbcp5_cpxdp_grant_arbbf_ca_5, arbcp5_cpxdp_q0_hold_arbbf_ca_l_5, arbcp5_cpxdp_qsel0_arbbf_ca_5, arbcp5_cpxdp_qsel1_arbbf_ca_l_5, arbcp5_cpxdp_shift_arbbf_cx_5, arbcp6_cpxdp_grant_arbbf_ca_5, arbcp6_cpxdp_q0_hold_arbbf_ca_l_5, arbcp6_cpxdp_qsel0_arbbf_ca_5, arbcp6_cpxdp_qsel1_arbbf_ca_l_5, arbcp6_cpxdp_shift_arbbf_cx_5, arbcp7_cpxdp_grant_arbbf_ca_5, arbcp7_cpxdp_q0_hold_arbbf_ca_l_5, arbcp7_cpxdp_qsel0_arbbf_ca_5, arbcp7_cpxdp_qsel1_arbbf_ca_l_5, arbcp7_cpxdp_shift_arbbf_cx_5, arbcp0_cpxdp_grant_arbbf_ca_2, arbcp0_cpxdp_q0_hold_arbbf_ca_l_2, arbcp0_cpxdp_qsel0_arbbf_ca_2, arbcp0_cpxdp_qsel1_arbbf_ca_l_2, arbcp0_cpxdp_shift_arbbf_cx_2, arbcp1_cpxdp_grant_arbbf_ca_2, arbcp1_cpxdp_q0_hold_arbbf_ca_l_2, arbcp1_cpxdp_qsel0_arbbf_ca_2, arbcp1_cpxdp_qsel1_arbbf_ca_l_2, arbcp1_cpxdp_shift_arbbf_cx_2, arbcp2_cpxdp_grant_arbbf_ca_2, arbcp2_cpxdp_q0_hold_arbbf_ca_l_2, arbcp2_cpxdp_qsel0_arbbf_ca_2, arbcp2_cpxdp_qsel1_arbbf_ca_l_2, arbcp2_cpxdp_shift_arbbf_cx_2, arbcp3_cpxdp_grant_arbbf_ca_2, arbcp3_cpxdp_q0_hold_arbbf_ca_l_2, arbcp3_cpxdp_qsel0_arbbf_ca_2, arbcp3_cpxdp_qsel1_arbbf_ca_l_2, arbcp3_cpxdp_shift_arbbf_cx_2, arbcp4_cpxdp_grant_arbbf_ca_2, arbcp4_cpxdp_q0_hold_arbbf_ca_l_2, arbcp4_cpxdp_qsel0_arbbf_ca_2, arbcp4_cpxdp_qsel1_arbbf_ca_l_2, arbcp4_cpxdp_shift_arbbf_cx_2, arbcp5_cpxdp_grant_arbbf_ca_2, arbcp5_cpxdp_q0_hold_arbbf_ca_l_2, arbcp5_cpxdp_qsel0_arbbf_ca_2, arbcp5_cpxdp_qsel1_arbbf_ca_l_2, arbcp5_cpxdp_shift_arbbf_cx_2, arbcp6_cpxdp_grant_arbbf_ca_2, arbcp6_cpxdp_q0_hold_arbbf_ca_l_2, arbcp6_cpxdp_qsel0_arbbf_ca_2, arbcp6_cpxdp_qsel1_arbbf_ca_l_2, arbcp6_cpxdp_shift_arbbf_cx_2, arbcp7_cpxdp_grant_arbbf_ca_2, arbcp7_cpxdp_q0_hold_arbbf_ca_l_2, arbcp7_cpxdp_qsel0_arbbf_ca_2, arbcp7_cpxdp_qsel1_arbbf_ca_l_2, arbcp7_cpxdp_shift_arbbf_cx_2 ); output [7:0] scache3_cpx_req_bufp3_cq ; output scache3_cpx_atom_bufp3_cq ; output [7:0] io_cpx_req_bufp3_cq ; output [7:0] cpx_scache3_grant_bufp3_ca_l; output cpx_spc5_data_rdy_bufp3_cx; output cpx_spc6_data_rdy_bufp3_cx; output cpx_spc7_data_rdy_bufp3_cx; output arbcp0_cpxdp_grant_bufp3_ca_l_5 ; output arbcp0_cpxdp_q0_hold_bufp3_ca_5 ; output arbcp0_cpxdp_qsel0_bufp3_ca_l_5 ; output arbcp0_cpxdp_qsel1_bufp3_ca_5 ; output arbcp0_cpxdp_shift_bufp3_cx_l_5 ; output arbcp1_cpxdp_grant_bufp3_ca_l_5 ; output arbcp1_cpxdp_q0_hold_bufp3_ca_5 ; output arbcp1_cpxdp_qsel0_bufp3_ca_l_5 ; output arbcp1_cpxdp_qsel1_bufp3_ca_5 ; output arbcp1_cpxdp_shift_bufp3_cx_l_5 ; output arbcp2_cpxdp_grant_bufp3_ca_l_5 ; output arbcp2_cpxdp_q0_hold_bufp3_ca_5 ; output arbcp2_cpxdp_qsel0_bufp3_ca_l_5 ; output arbcp2_cpxdp_qsel1_bufp3_ca_5 ; output arbcp2_cpxdp_shift_bufp3_cx_l_5 ; output arbcp3_cpxdp_grant_bufp3_ca_l_5 ; output arbcp3_cpxdp_q0_hold_bufp3_ca_5 ; output arbcp3_cpxdp_qsel0_bufp3_ca_l_5 ; output arbcp3_cpxdp_qsel1_bufp3_ca_5 ; output arbcp3_cpxdp_shift_bufp3_cx_l_5 ; output arbcp4_cpxdp_grant_bufp3_ca_l_5 ; output arbcp4_cpxdp_q0_hold_bufp3_ca_5 ; output arbcp4_cpxdp_qsel0_bufp3_ca_l_5 ; output arbcp4_cpxdp_qsel1_bufp3_ca_5 ; output arbcp4_cpxdp_shift_bufp3_cx_l_5 ; output arbcp5_cpxdp_grant_bufp3_ca_l_5 ; output arbcp5_cpxdp_q0_hold_bufp3_ca_5 ; output arbcp5_cpxdp_qsel0_bufp3_ca_l_5 ; output arbcp5_cpxdp_qsel1_bufp3_ca_5 ; output arbcp5_cpxdp_shift_bufp3_cx_l_5 ; output arbcp6_cpxdp_grant_bufp3_ca_l_5 ; output arbcp6_cpxdp_q0_hold_bufp3_ca_5 ; output arbcp6_cpxdp_qsel0_bufp3_ca_l_5 ; output arbcp6_cpxdp_qsel1_bufp3_ca_5 ; output arbcp6_cpxdp_shift_bufp3_cx_l_5 ; output arbcp7_cpxdp_grant_bufp3_ca_l_5 ; output arbcp7_cpxdp_q0_hold_bufp3_ca_5 ; output arbcp7_cpxdp_qsel0_bufp3_ca_l_5 ; output arbcp7_cpxdp_qsel1_bufp3_ca_5 ; output arbcp7_cpxdp_shift_bufp3_cx_l_5 ; input [7:0] scache3_cpx_req_bufp4_cq; input scache3_cpx_atom_bufp4_cq; input [7:0] io_cpx_req_bufp4_cq; input [7:0] cpx_scache3_grant_ca; input cpx_spc5_data_rdy_cx; input cpx_spc6_data_rdy_cx; input cpx_spc7_data_rdy_cx; input arbcp0_cpxdp_grant_arbbf_ca_5; input arbcp0_cpxdp_q0_hold_arbbf_ca_l_5; input arbcp0_cpxdp_qsel0_arbbf_ca_5; input arbcp0_cpxdp_qsel1_arbbf_ca_l_5; input arbcp0_cpxdp_shift_arbbf_cx_5; input arbcp1_cpxdp_grant_arbbf_ca_5; input arbcp1_cpxdp_q0_hold_arbbf_ca_l_5; input arbcp1_cpxdp_qsel0_arbbf_ca_5; input arbcp1_cpxdp_qsel1_arbbf_ca_l_5; input arbcp1_cpxdp_shift_arbbf_cx_5; input arbcp2_cpxdp_grant_arbbf_ca_5; input arbcp2_cpxdp_q0_hold_arbbf_ca_l_5; input arbcp2_cpxdp_qsel0_arbbf_ca_5; input arbcp2_cpxdp_qsel1_arbbf_ca_l_5; input arbcp2_cpxdp_shift_arbbf_cx_5; input arbcp3_cpxdp_grant_arbbf_ca_5; input arbcp3_cpxdp_q0_hold_arbbf_ca_l_5; input arbcp3_cpxdp_qsel0_arbbf_ca_5; input arbcp3_cpxdp_qsel1_arbbf_ca_l_5; input arbcp3_cpxdp_shift_arbbf_cx_5; input arbcp4_cpxdp_grant_arbbf_ca_5; input arbcp4_cpxdp_q0_hold_arbbf_ca_l_5; input arbcp4_cpxdp_qsel0_arbbf_ca_5; input arbcp4_cpxdp_qsel1_arbbf_ca_l_5; input arbcp4_cpxdp_shift_arbbf_cx_5; input arbcp5_cpxdp_grant_arbbf_ca_5; input arbcp5_cpxdp_q0_hold_arbbf_ca_l_5; input arbcp5_cpxdp_qsel0_arbbf_ca_5; input arbcp5_cpxdp_qsel1_arbbf_ca_l_5; input arbcp5_cpxdp_shift_arbbf_cx_5; input arbcp6_cpxdp_grant_arbbf_ca_5; input arbcp6_cpxdp_q0_hold_arbbf_ca_l_5; input arbcp6_cpxdp_qsel0_arbbf_ca_5; input arbcp6_cpxdp_qsel1_arbbf_ca_l_5; input arbcp6_cpxdp_shift_arbbf_cx_5; input arbcp7_cpxdp_grant_arbbf_ca_5; input arbcp7_cpxdp_q0_hold_arbbf_ca_l_5; input arbcp7_cpxdp_qsel0_arbbf_ca_5; input arbcp7_cpxdp_qsel1_arbbf_ca_l_5; input arbcp7_cpxdp_shift_arbbf_cx_5; output arbcp0_cpxdp_grant_bufp3_ca_l_2 ; output arbcp0_cpxdp_q0_hold_bufp3_ca_2 ; output arbcp0_cpxdp_qsel0_bufp3_ca_l_2 ; output arbcp0_cpxdp_qsel1_bufp3_ca_2 ; output arbcp0_cpxdp_shift_bufp3_cx_l_2 ; output arbcp1_cpxdp_grant_bufp3_ca_l_2 ; output arbcp1_cpxdp_q0_hold_bufp3_ca_2 ; output arbcp1_cpxdp_qsel0_bufp3_ca_l_2 ; output arbcp1_cpxdp_qsel1_bufp3_ca_2 ; output arbcp1_cpxdp_shift_bufp3_cx_l_2 ; output arbcp2_cpxdp_grant_bufp3_ca_l_2 ; output arbcp2_cpxdp_q0_hold_bufp3_ca_2 ; output arbcp2_cpxdp_qsel0_bufp3_ca_l_2 ; output arbcp2_cpxdp_qsel1_bufp3_ca_2 ; output arbcp2_cpxdp_shift_bufp3_cx_l_2 ; output arbcp3_cpxdp_grant_bufp3_ca_l_2 ; output arbcp3_cpxdp_q0_hold_bufp3_ca_2 ; output arbcp3_cpxdp_qsel0_bufp3_ca_l_2 ; output arbcp3_cpxdp_qsel1_bufp3_ca_2 ; output arbcp3_cpxdp_shift_bufp3_cx_l_2 ; output arbcp4_cpxdp_grant_bufp3_ca_l_2 ; output arbcp4_cpxdp_q0_hold_bufp3_ca_2 ; output arbcp4_cpxdp_qsel0_bufp3_ca_l_2 ; output arbcp4_cpxdp_qsel1_bufp3_ca_2 ; output arbcp4_cpxdp_shift_bufp3_cx_l_2 ; output arbcp5_cpxdp_grant_bufp3_ca_l_2 ; output arbcp5_cpxdp_q0_hold_bufp3_ca_2 ; output arbcp5_cpxdp_qsel0_bufp3_ca_l_2 ; output arbcp5_cpxdp_qsel1_bufp3_ca_2 ; output arbcp5_cpxdp_shift_bufp3_cx_l_2 ; output arbcp6_cpxdp_grant_bufp3_ca_l_2 ; output arbcp6_cpxdp_q0_hold_bufp3_ca_2 ; output arbcp6_cpxdp_qsel0_bufp3_ca_l_2 ; output arbcp6_cpxdp_qsel1_bufp3_ca_2 ; output arbcp6_cpxdp_shift_bufp3_cx_l_2 ; output arbcp7_cpxdp_grant_bufp3_ca_l_2 ; output arbcp7_cpxdp_q0_hold_bufp3_ca_2 ; output arbcp7_cpxdp_qsel0_bufp3_ca_l_2 ; output arbcp7_cpxdp_qsel1_bufp3_ca_2 ; output arbcp7_cpxdp_shift_bufp3_cx_l_2 ; input arbcp0_cpxdp_grant_arbbf_ca_2; input arbcp0_cpxdp_q0_hold_arbbf_ca_l_2; input arbcp0_cpxdp_qsel0_arbbf_ca_2; input arbcp0_cpxdp_qsel1_arbbf_ca_l_2; input arbcp0_cpxdp_shift_arbbf_cx_2; input arbcp1_cpxdp_grant_arbbf_ca_2; input arbcp1_cpxdp_q0_hold_arbbf_ca_l_2; input arbcp1_cpxdp_qsel0_arbbf_ca_2; input arbcp1_cpxdp_qsel1_arbbf_ca_l_2; input arbcp1_cpxdp_shift_arbbf_cx_2; input arbcp2_cpxdp_grant_arbbf_ca_2; input arbcp2_cpxdp_q0_hold_arbbf_ca_l_2; input arbcp2_cpxdp_qsel0_arbbf_ca_2; input arbcp2_cpxdp_qsel1_arbbf_ca_l_2; input arbcp2_cpxdp_shift_arbbf_cx_2; input arbcp3_cpxdp_grant_arbbf_ca_2; input arbcp3_cpxdp_q0_hold_arbbf_ca_l_2; input arbcp3_cpxdp_qsel0_arbbf_ca_2; input arbcp3_cpxdp_qsel1_arbbf_ca_l_2; input arbcp3_cpxdp_shift_arbbf_cx_2; input arbcp4_cpxdp_grant_arbbf_ca_2; input arbcp4_cpxdp_q0_hold_arbbf_ca_l_2; input arbcp4_cpxdp_qsel0_arbbf_ca_2; input arbcp4_cpxdp_qsel1_arbbf_ca_l_2; input arbcp4_cpxdp_shift_arbbf_cx_2; input arbcp5_cpxdp_grant_arbbf_ca_2; input arbcp5_cpxdp_q0_hold_arbbf_ca_l_2; input arbcp5_cpxdp_qsel0_arbbf_ca_2; input arbcp5_cpxdp_qsel1_arbbf_ca_l_2; input arbcp5_cpxdp_shift_arbbf_cx_2; input arbcp6_cpxdp_grant_arbbf_ca_2; input arbcp6_cpxdp_q0_hold_arbbf_ca_l_2; input arbcp6_cpxdp_qsel0_arbbf_ca_2; input arbcp6_cpxdp_qsel1_arbbf_ca_l_2; input arbcp6_cpxdp_shift_arbbf_cx_2; input arbcp7_cpxdp_grant_arbbf_ca_2; input arbcp7_cpxdp_q0_hold_arbbf_ca_l_2; input arbcp7_cpxdp_qsel0_arbbf_ca_2; input arbcp7_cpxdp_qsel1_arbbf_ca_l_2; input arbcp7_cpxdp_shift_arbbf_cx_2; assign scache3_cpx_req_bufp3_cq[7:0] = scache3_cpx_req_bufp4_cq[7:0]; assign scache3_cpx_atom_bufp3_cq = scache3_cpx_atom_bufp4_cq; assign io_cpx_req_bufp3_cq[7:0] = io_cpx_req_bufp4_cq[7:0]; assign cpx_scache3_grant_bufp3_ca_l = ~cpx_scache3_grant_ca; assign cpx_spc5_data_rdy_bufp3_cx = cpx_spc5_data_rdy_cx; assign cpx_spc6_data_rdy_bufp3_cx = cpx_spc6_data_rdy_cx; assign cpx_spc7_data_rdy_bufp3_cx = cpx_spc7_data_rdy_cx; assign arbcp0_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp0_cpxdp_grant_arbbf_ca_5; assign arbcp0_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp0_cpxdp_q0_hold_arbbf_ca_l_5; assign arbcp0_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp0_cpxdp_qsel0_arbbf_ca_5; assign arbcp0_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp0_cpxdp_qsel1_arbbf_ca_l_5; assign arbcp0_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp0_cpxdp_shift_arbbf_cx_5; assign arbcp1_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp1_cpxdp_grant_arbbf_ca_5; assign arbcp1_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp1_cpxdp_q0_hold_arbbf_ca_l_5; assign arbcp1_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp1_cpxdp_qsel0_arbbf_ca_5; assign arbcp1_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp1_cpxdp_qsel1_arbbf_ca_l_5; assign arbcp1_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp1_cpxdp_shift_arbbf_cx_5; assign arbcp2_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp2_cpxdp_grant_arbbf_ca_5; assign arbcp2_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp2_cpxdp_q0_hold_arbbf_ca_l_5; assign arbcp2_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp2_cpxdp_qsel0_arbbf_ca_5; assign arbcp2_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp2_cpxdp_qsel1_arbbf_ca_l_5; assign arbcp2_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp2_cpxdp_shift_arbbf_cx_5; assign arbcp3_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp3_cpxdp_grant_arbbf_ca_5; assign arbcp3_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp3_cpxdp_q0_hold_arbbf_ca_l_5; assign arbcp3_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp3_cpxdp_qsel0_arbbf_ca_5; assign arbcp3_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp3_cpxdp_qsel1_arbbf_ca_l_5; assign arbcp3_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp3_cpxdp_shift_arbbf_cx_5; assign arbcp4_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp4_cpxdp_grant_arbbf_ca_5; assign arbcp4_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp4_cpxdp_q0_hold_arbbf_ca_l_5; assign arbcp4_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp4_cpxdp_qsel0_arbbf_ca_5; assign arbcp4_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp4_cpxdp_qsel1_arbbf_ca_l_5; assign arbcp4_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp4_cpxdp_shift_arbbf_cx_5; assign arbcp5_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp5_cpxdp_grant_arbbf_ca_5; assign arbcp5_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp5_cpxdp_q0_hold_arbbf_ca_l_5; assign arbcp5_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp5_cpxdp_qsel0_arbbf_ca_5; assign arbcp5_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp5_cpxdp_qsel1_arbbf_ca_l_5; assign arbcp5_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp5_cpxdp_shift_arbbf_cx_5; assign arbcp6_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp6_cpxdp_grant_arbbf_ca_5; assign arbcp6_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp6_cpxdp_q0_hold_arbbf_ca_l_5; assign arbcp6_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp6_cpxdp_qsel0_arbbf_ca_5; assign arbcp6_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp6_cpxdp_qsel1_arbbf_ca_l_5; assign arbcp6_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp6_cpxdp_shift_arbbf_cx_5; assign arbcp7_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp7_cpxdp_grant_arbbf_ca_5; assign arbcp7_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp7_cpxdp_q0_hold_arbbf_ca_l_5; assign arbcp7_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp7_cpxdp_qsel0_arbbf_ca_5; assign arbcp7_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp7_cpxdp_qsel1_arbbf_ca_l_5; assign arbcp7_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp7_cpxdp_shift_arbbf_cx_5; assign arbcp0_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp0_cpxdp_grant_arbbf_ca_2; assign arbcp0_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp0_cpxdp_q0_hold_arbbf_ca_l_2; assign arbcp0_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp0_cpxdp_qsel0_arbbf_ca_2; assign arbcp0_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp0_cpxdp_qsel1_arbbf_ca_l_2; assign arbcp0_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp0_cpxdp_shift_arbbf_cx_2; assign arbcp1_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp1_cpxdp_grant_arbbf_ca_2; assign arbcp1_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp1_cpxdp_q0_hold_arbbf_ca_l_2; assign arbcp1_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp1_cpxdp_qsel0_arbbf_ca_2; assign arbcp1_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp1_cpxdp_qsel1_arbbf_ca_l_2; assign arbcp1_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp1_cpxdp_shift_arbbf_cx_2; assign arbcp2_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp2_cpxdp_grant_arbbf_ca_2; assign arbcp2_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp2_cpxdp_q0_hold_arbbf_ca_l_2; assign arbcp2_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp2_cpxdp_qsel0_arbbf_ca_2; assign arbcp2_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp2_cpxdp_qsel1_arbbf_ca_l_2; assign arbcp2_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp2_cpxdp_shift_arbbf_cx_2; assign arbcp3_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp3_cpxdp_grant_arbbf_ca_2; assign arbcp3_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp3_cpxdp_q0_hold_arbbf_ca_l_2; assign arbcp3_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp3_cpxdp_qsel0_arbbf_ca_2; assign arbcp3_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp3_cpxdp_qsel1_arbbf_ca_l_2; assign arbcp3_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp3_cpxdp_shift_arbbf_cx_2; assign arbcp4_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp4_cpxdp_grant_arbbf_ca_2; assign arbcp4_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp4_cpxdp_q0_hold_arbbf_ca_l_2; assign arbcp4_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp4_cpxdp_qsel0_arbbf_ca_2; assign arbcp4_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp4_cpxdp_qsel1_arbbf_ca_l_2; assign arbcp4_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp4_cpxdp_shift_arbbf_cx_2; assign arbcp5_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp5_cpxdp_grant_arbbf_ca_2; assign arbcp5_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp5_cpxdp_q0_hold_arbbf_ca_l_2; assign arbcp5_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp5_cpxdp_qsel0_arbbf_ca_2; assign arbcp5_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp5_cpxdp_qsel1_arbbf_ca_l_2; assign arbcp5_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp5_cpxdp_shift_arbbf_cx_2; assign arbcp6_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp6_cpxdp_grant_arbbf_ca_2; assign arbcp6_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp6_cpxdp_q0_hold_arbbf_ca_l_2; assign arbcp6_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp6_cpxdp_qsel0_arbbf_ca_2; assign arbcp6_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp6_cpxdp_qsel1_arbbf_ca_l_2; assign arbcp6_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp6_cpxdp_shift_arbbf_cx_2; assign arbcp7_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp7_cpxdp_grant_arbbf_ca_2; assign arbcp7_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp7_cpxdp_q0_hold_arbbf_ca_l_2; assign arbcp7_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp7_cpxdp_qsel0_arbbf_ca_2; assign arbcp7_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp7_cpxdp_qsel1_arbbf_ca_l_2; assign arbcp7_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp7_cpxdp_shift_arbbf_cx_2; endmodule // cpx_grant_ff

//////////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. // // // // Redistribution and use in source and binary forms, with or without // // modification, are permitted provided that the following conditions are met: // // * Redistributions of source code must retain the above copyright // // notice, this list of conditions and the following disclaimer. // // * Redistributions in binary form must reproduce the above copyright // // notice, this list of conditions and the following disclaimer in the // // documentation and/or other materials provided with the distribution. // // * Neither the name of the University of British Columbia (UBC) nor the names // // of its contributors may be used to endorse or promote products // // derived from this software without specific prior written permission. // // // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE // // DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE // // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL // // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR // // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER // // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, // // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////// // bcam_tb.v: A Test-bench for Binary Content Addressasble Memories (BCAM) // // // // Author: Ameer M.S. Abdelhadi (ameer@ece.ubc.ca, ameer.abdelhadi@gmail.com) // // SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 // //////////////////////////////////////////////////////////////////////////////////// `timescale 1 ps/1 ps `include "utils.vh" // deine simulation mode `define SIM module bcam_tb; // simulation parameter localparam CAMD = `CAMD ; // memory depth localparam CAMW = `CAMW ; // data width localparam SEGW = `SEGW ; // segment width for Segmented Transposed-RAM implementation localparam CYCC = `CYCC ; // simulation cycles count localparam CYCT = 10 ; // cycle time localparam RSTT = 5.2*CYCT ; // reset time localparam VERBOSE = 2 ; // verbose logging (0: no; 1: level 1; 2: level 2) localparam TERFAIL = 0 ; // terminate if fail? localparam TIMEOUT = 2*CYCT*CYCC; // simulation time localparam ADDRW = `log2(CAMD); // CAM address width = log2 (CAM depth) // enumerate implementations localparam REG = 3'b000; // register-based localparam TRS = 3'b001; // transposed-RAM stage localparam TRC = 3'b010; // transposed-RAM cascade localparam STR = 3'b011; // segmented transposed-RAM localparam ALL = 3'b100; // all implementations reg clk = 1'b0; // global clock reg rst = 1'b1; // global reset reg wEnb= 1'b0; // write enable reg [CAMW -1:0] wPatt, mPatt; // patterns reg [ADDRW-1:0] wAddr ; // write address wire [ADDRW-1:0] mAddrBhv, mAddrReg, mAddrTRS, mAddrTRC, mAddrSTR; // match addresses wire matchBhv, matchReg, matchTRS, matchTRC, matchSTR; // match indicators // registered outputs reg [ADDRW-1:0] mAddrRegR; // addresses reg matchRegR; // match indicator integer cycc=0; // cycles count // generate clock and reset always #(CYCT/2) clk = !clk; // toggle clock integer rep_fd, ferr; initial begin // lower reset #(RSTT ) rst = 1'b0; ////////////////////////////////////////////// // print header to results file rep_fd = $fopen("sim.res","r"); // try to open report file for read $ferror(rep_fd,ferr); // detect error $fclose(rep_fd); rep_fd = $fopen("sim.res","a+"); // open report file for append if (ferr) begin // if file is new (can't open for read); write header $fwrite(rep_fd,"* REG: Register-based Binary Content Addressasble Memory\n"); $fwrite(rep_fd,"* TRS: Transposed-RAM Binary Content Addressasble Memory stage\n"); $fwrite(rep_fd,"* TRC: Transposed-RAM Binary Content Addressasble Memory cascade\n"); $fwrite(rep_fd,"* STR: Segmented Transposed-RAM Binary Content Addressasble Memory\n\n"); $fwrite(rep_fd,"BCAM Architectural Parameters # Simulation Mismatches\n"); $fwrite(rep_fd,"=============================== =======================\n"); $fwrite(rep_fd,"CAM Pattern Segment Simula. REG TRS TRC STR \n"); $fwrite(rep_fd,"Depth Width Width Cycles \n"); $fwrite(rep_fd,"=========================================================\n"); end // print header $write("Simulating BAM with the following parameters:\n"); $write("CAM depth : %0d\n",CAMD); $write("Pattern width : %0d\n",CAMW); $write("Segment width (STRAM): %0d\n",SEGW); $write("Simulation Cycles : %0d\n",CYCC); // print header if no verbose if (VERBOSE==1) $write("\n 1k 2k 3k 4k 5k 6k 7k 8k 9k "); end reg [5:0] pass; // result for each implementation integer failCntReg = 0; // failures count integer failCntTRS = 0; // failures count integer failCntTRC = 0; // failures count integer failCntSTR = 0; // failures count integer failCntAll = 0; // failures count integer failCntTmp = 0; // failures count / temporal/ per few cycles always @(negedge clk) begin if (!rst) begin // Generate random inputs if ( !wEnb) begin `GETRAND( wEnb,1 ); `GETRAND(wAddr,ADDRW); `GETRAND(wPatt,CAMW ); end else wEnb = 1'b0; `GETRAND(mPatt,CAMW ); // write input data if (VERBOSE==2) $write("%-7d: ",cycc); #(CYCT/10) // a little after falling edge if (VERBOSE==2) $write("Before rise: wEnb=%h; wAddr=%h; wPatt=%h; mPatt=%h --- ",wEnb,wAddr,wPatt,mPatt); #(CYCT/2) // a little after rising edge if (VERBOSE==2) $write("After rise: match=(%b,%b,%b,%b,%b); mAddr=(%h,%h,%h,%h,%h) --- ",matchBhv,matchRegR,matchTRS,matchTRC,matchSTR,mAddrBhv,mAddrRegR,mAddrTRS,mAddrTRC,mAddrSTR); pass[REG] = !(matchBhv || matchRegR) || (matchBhv && matchRegR && (mAddrBhv===mAddrRegR)); pass[TRS] = !(matchBhv || matchTRS ) || (matchBhv && matchTRS && (mAddrBhv===mAddrTRS )); pass[TRC] = !(matchBhv || matchTRC ) || (matchBhv && matchTRC && (mAddrBhv===mAddrTRC )); pass[STR] = !(matchBhv || matchSTR ) || (matchBhv && matchSTR && (mAddrBhv===mAddrSTR )); pass[ALL] = pass[REG] && pass[TRS] && pass[TRC] && pass[STR]; if (!pass[REG]) failCntReg = failCntReg + 1; if (!pass[TRS]) failCntTRS = failCntTRS + 1; if (!pass[TRC]) failCntTRC = failCntTRC + 1; if (!pass[STR]) failCntSTR = failCntSTR + 1; if (!pass[ALL]) failCntAll = failCntAll + 1; failCntTmp = failCntAll ; if (VERBOSE==2) $write("%s\n",pass[ALL]?"Pass":"Fail"); if (VERBOSE==1) begin if ((cycc%10000)==0) $write("\n%4d X 10k: ",cycc/10000); else if ((cycc%1000 )==0) $write("|"); if ((cycc%100 )==0) begin if (failCntTmp>0) $write("x"); else $write("-"); end failCntTmp = 0; end // finish if terminate on any failure if (TERFAIL && (!pass[ALL])) begin $write("*** Simulation terminated due to output mismatch\n"); $fclose(rep_fd); $finish; end if (cycc==CYCC) begin // write to report file $fwrite(rep_fd,"%-7d %-7d %-7d %-7d %-5d %-5d %-5d %-5d\n",CAMD,CAMW,SEGW,CYCC,failCntReg,failCntTRS,failCntTRC,failCntSTR); // write to STDOUT $write("\n*** Simulation terminated after %0d cycles with %0d failures. Results:\n",CYCC,failCntAll); $write("REG = %-5d mismatches\n",failCntReg); $write("TRS = %-5d mismatches\n",failCntTRS); $write("TRC = %-5d mismatches\n",failCntTRC); $write("STR = %-5d mismatches\n",failCntSTR); $fclose(rep_fd); $finish; end cycc=cycc+1; end end // Behavioral BCAM bcam #( .CAMD ( CAMD ), // CAM depth .CAMW ( CAMW ), // CAM/pattern width .INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE) .REGW ( 1 ), // binary / register write inputs wEnb, wAddr, & wPatt? .REGM ( 0 ), // binary / register match input mPatt? .REGO ( 1 ), // binary / register outputs match & mAddr? .TYPE ( "BHV" )) // implementation type: BHV, REG, TRAM, STRAM bcam_bhv_i ( .clk ( clk ), // clock .rst ( rst ), // global registers reset .wEnb ( wEnb ), // write enable .wAddr( wAddr ), // write address .wPatt( wPatt ), // write pattern .mPatt( mPatt ), // patern to match .match( matchBhv ), // match indicator .mAddr( mAddrBhv )); // matched address // Register-based BCAM bcam #( .CAMD ( CAMD ), // CAM depth .CAMW ( CAMW ), // CAM/pattern width .INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE) .REGW ( 0 ), // binary / register write inputs wEnb, wAddr, & wPatt? .REGM ( 0 ), // binary / register match input mPatt? .REGO ( 1 ), // binary / register outputs match & mAddr? .TYPE ( "REG" )) // implementation type: BHV, REG, TRAM, STRAM bcam_reg_i ( .clk ( clk ), // clock .rst ( rst ), // global registers reset .wEnb ( wEnb ), // write enable .wAddr( wAddr ), // write address / [`log2(CAMD)-1:0] .wPatt( wPatt ), // write pattern / [ CAMW -1:0] .mPatt( mPatt ), // patern to match / [ CAMW -1:0] .match( matchReg ), // match indicator .mAddr( mAddrReg )); // matched address / [`log2(CAMD)-1:0] // Transposed-RAM stage (Brute-Force) BCAM bcam #( .CAMD ( CAMD ), // CAM depth .CAMW ( CAMW ), // CAM/pattern width .INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE) .REGW ( 0 ), // binary / register write inputs wEnb, wAddr, & wPatt? .REGM ( 0 ), // binary / register match input mPatt? .REGO ( 1 ), // binary / register outputs match & mAddr? .BRAM ( "M20K" ), // BRAM type- "M20K":Altera's M20K; "GEN":generic .TYPE ( "TRS" )) // implementation type: BHV, REG, TRAM, STRAM bcam_trs_i ( .clk ( clk ), // clock .rst ( rst ), // global registers reset .wEnb ( wEnb ), // write enable .wAddr( wAddr ), // write address / [`log2(CAMD)-1:0] .wPatt( wPatt ), // write pattern / [ CAMW -1:0] .mPatt( mPatt ), // patern to match / [ CAMW -1:0] .match( matchTRS ), // match indicator .mAddr( mAddrTRS )); // matched address / [`log2(CAMD)-1:0] // Transposed-RAM cascade (Brute-Force) BCAM bcam #( .CAMD ( CAMD ), // CAM depth .CAMW ( CAMW ), // CAM/pattern width .INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE) .REGW ( 0 ), // binary / register write inputs wEnb, wAddr, & wPatt? .REGM ( 0 ), // binary / register match input mPatt? .REGO ( 1 ), // binary / register outputs match & mAddr? .BRAM ( "M20K" ), // BRAM type- "M20K":Altera's M20K; "GEN":generic .TYPE ( "TRC" )) // implementation type: BHV, REG, TRAM, STRAM bcam_trc_i ( .clk ( clk ), // clock .rst ( rst ), // global registers reset .wEnb ( wEnb ), // write enable .wAddr( wAddr ), // write address / [`log2(CAMD)-1:0] .wPatt( wPatt ), // write pattern / [ CAMW -1:0] .mPatt( mPatt ), // patern to match / [ CAMW -1:0] .match( matchTRC ), // match indicator .mAddr( mAddrTRC )); // matched address / [`log2(CAMD)-1:0] // Segmented Transposed-RAM BCAM bcam #( .CAMD ( CAMD ), // CAM depth .CAMW ( CAMW ), // CAM/pattern width .SEGW ( SEGW ), // Segment width .INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE) .REGW ( 0 ), // binary / register write inputs wEnb, wAddr, & wPatt? .REGM ( 0 ), // binary / register match input mPatt? .REGO ( 0 ), // binary / register outputs match & mAddr? .BRAM ( "M20K" ), // BRAM type- "M20K":Altera's M20K; "GEN":generic .TYPE ( "STRAM" )) // implementation type: BHV, REG, TRAM, STRAM bcam_str_i ( .clk ( clk ), // clock .rst ( rst ), // global registers reset .wEnb ( wEnb ), // write enable .wAddr( wAddr ), // write address / [`log2(CAMD)-1:0] .wPatt( wPatt ), // write pattern / [ CAMW -1:0] .mPatt( mPatt ), // patern to match / [ CAMW -1:0] .match( matchSTR ), // match indicator .mAddr( mAddrSTR )); // matched address / [`log2(CAMD)-1:0] // Register outputs / second stage always @(posedge clk, posedge rst) if (rst) {mAddrRegR,matchRegR} <= {(ADDRW +1 ){1'b0}}; else {mAddrRegR,matchRegR} <= { mAddrReg,matchReg }; endmodule

// // Generated by Bluespec Compiler (build 0fccbb13) // // // Ports: // Name I/O size props // RDY_cpu_reset_server_request_put O 1 reg // cpu_reset_server_response_get O 1 reg // RDY_cpu_reset_server_response_get O 1 reg // cpu_imem_master_awvalid O 1 reg // cpu_imem_master_awid O 4 reg // cpu_imem_master_awaddr O 64 reg // cpu_imem_master_awlen O 8 reg // cpu_imem_master_awsize O 3 reg // cpu_imem_master_awburst O 2 reg // cpu_imem_master_awlock O 1 reg // cpu_imem_master_awcache O 4 reg // cpu_imem_master_awprot O 3 reg // cpu_imem_master_awqos O 4 reg // cpu_imem_master_awregion O 4 reg // cpu_imem_master_wvalid O 1 reg // cpu_imem_master_wdata O 64 reg // cpu_imem_master_wstrb O 8 reg // cpu_imem_master_wlast O 1 reg // cpu_imem_master_bready O 1 reg // cpu_imem_master_arvalid O 1 reg // cpu_imem_master_arid O 4 reg // cpu_imem_master_araddr O 64 reg // cpu_imem_master_arlen O 8 reg // cpu_imem_master_arsize O 3 reg // cpu_imem_master_arburst O 2 reg // cpu_imem_master_arlock O 1 reg // cpu_imem_master_arcache O 4 reg // cpu_imem_master_arprot O 3 reg // cpu_imem_master_arqos O 4 reg // cpu_imem_master_arregion O 4 reg // cpu_imem_master_rready O 1 reg // core_mem_master_awvalid O 1 reg // core_mem_master_awid O 4 reg // core_mem_master_awaddr O 64 reg // core_mem_master_awlen O 8 reg // core_mem_master_awsize O 3 reg // core_mem_master_awburst O 2 reg // core_mem_master_awlock O 1 reg // core_mem_master_awcache O 4 reg // core_mem_master_awprot O 3 reg // core_mem_master_awqos O 4 reg // core_mem_master_awregion O 4 reg // core_mem_master_wvalid O 1 reg // core_mem_master_wdata O 64 reg // core_mem_master_wstrb O 8 reg // core_mem_master_wlast O 1 reg // core_mem_master_bready O 1 reg // core_mem_master_arvalid O 1 reg // core_mem_master_arid O 4 reg // core_mem_master_araddr O 64 reg // core_mem_master_arlen O 8 reg // core_mem_master_arsize O 3 reg // core_mem_master_arburst O 2 reg // core_mem_master_arlock O 1 reg // core_mem_master_arcache O 4 reg // core_mem_master_arprot O 3 reg // core_mem_master_arqos O 4 reg // core_mem_master_arregion O 4 reg // core_mem_master_rready O 1 reg // dma_server_awready O 1 const // dma_server_wready O 1 const // dma_server_bvalid O 1 const // dma_server_bid O 16 const // dma_server_bresp O 2 const // dma_server_arready O 1 const // dma_server_rvalid O 1 const // dma_server_rid O 16 const // dma_server_rdata O 512 const // dma_server_rresp O 2 const // dma_server_rlast O 1 const // RDY_set_verbosity O 1 const // RDY_set_watch_tohost O 1 const // mv_tohost_value O 64 reg // RDY_mv_tohost_value O 1 const // RDY_ma_ddr4_ready O 1 const // mv_status O 8 // RST_N_dm_power_on_reset I 1 unused // CLK I 1 clock // RST_N I 1 reset // cpu_reset_server_request_put I 1 reg // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 // cpu_imem_master_bvalid I 1 // cpu_imem_master_bid I 4 reg // cpu_imem_master_bresp I 2 reg // cpu_imem_master_arready I 1 // cpu_imem_master_rvalid I 1 // cpu_imem_master_rid I 4 reg // cpu_imem_master_rdata I 64 reg // cpu_imem_master_rresp I 2 reg // cpu_imem_master_rlast I 1 reg // core_mem_master_awready I 1 // core_mem_master_wready I 1 // core_mem_master_bvalid I 1 // core_mem_master_bid I 4 reg // core_mem_master_bresp I 2 reg // core_mem_master_arready I 1 // core_mem_master_rvalid I 1 // core_mem_master_rid I 4 reg // core_mem_master_rdata I 64 reg // core_mem_master_rresp I 2 reg // core_mem_master_rlast I 1 reg // dma_server_awvalid I 1 unused // dma_server_awid I 16 unused // dma_server_awaddr I 64 unused // dma_server_awlen I 8 unused // dma_server_awsize I 3 unused // dma_server_awburst I 2 unused // dma_server_awlock I 1 unused // dma_server_awcache I 4 unused // dma_server_awprot I 3 unused // dma_server_awqos I 4 unused // dma_server_awregion I 4 unused // dma_server_wvalid I 1 unused // dma_server_wdata I 512 unused // dma_server_wstrb I 64 unused // dma_server_wlast I 1 unused // dma_server_bready I 1 unused // dma_server_arvalid I 1 unused // dma_server_arid I 16 unused // dma_server_araddr I 64 unused // dma_server_arlen I 8 unused // dma_server_arsize I 3 unused // dma_server_arburst I 2 unused // dma_server_arlock I 1 unused // dma_server_arcache I 4 unused // dma_server_arprot I 3 unused // dma_server_arqos I 4 unused // dma_server_arregion I 4 unused // dma_server_rready I 1 unused // core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 // core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 // nmi_req_set_not_clear I 1 // set_verbosity_verbosity I 4 reg // set_verbosity_logdelay I 64 reg // set_watch_tohost_watch_tohost I 1 reg // set_watch_tohost_tohost_addr I 64 reg // EN_cpu_reset_server_request_put I 1 // EN_set_verbosity I 1 // EN_set_watch_tohost I 1 // EN_ma_ddr4_ready I 1 // EN_cpu_reset_server_response_get I 1 // // No combinational paths from inputs to outputs // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module mkCore(RST_N_dm_power_on_reset, CLK, RST_N, cpu_reset_server_request_put, EN_cpu_reset_server_request_put, RDY_cpu_reset_server_request_put, EN_cpu_reset_server_response_get, cpu_reset_server_response_get, RDY_cpu_reset_server_response_get, cpu_imem_master_awvalid, cpu_imem_master_awid, cpu_imem_master_awaddr, cpu_imem_master_awlen, cpu_imem_master_awsize, cpu_imem_master_awburst, cpu_imem_master_awlock, cpu_imem_master_awcache, cpu_imem_master_awprot, cpu_imem_master_awqos, cpu_imem_master_awregion, cpu_imem_master_awready, cpu_imem_master_wvalid, cpu_imem_master_wdata, cpu_imem_master_wstrb, cpu_imem_master_wlast, cpu_imem_master_wready, cpu_imem_master_bvalid, cpu_imem_master_bid, cpu_imem_master_bresp, cpu_imem_master_bready, cpu_imem_master_arvalid, cpu_imem_master_arid, cpu_imem_master_araddr, cpu_imem_master_arlen, cpu_imem_master_arsize, cpu_imem_master_arburst, cpu_imem_master_arlock, cpu_imem_master_arcache, cpu_imem_master_arprot, cpu_imem_master_arqos, cpu_imem_master_arregion, cpu_imem_master_arready, cpu_imem_master_rvalid, cpu_imem_master_rid, cpu_imem_master_rdata, cpu_imem_master_rresp, cpu_imem_master_rlast, cpu_imem_master_rready, core_mem_master_awvalid, core_mem_master_awid, core_mem_master_awaddr, core_mem_master_awlen, core_mem_master_awsize, core_mem_master_awburst, core_mem_master_awlock, core_mem_master_awcache, core_mem_master_awprot, core_mem_master_awqos, core_mem_master_awregion, core_mem_master_awready, core_mem_master_wvalid, core_mem_master_wdata, core_mem_master_wstrb, core_mem_master_wlast, core_mem_master_wready, core_mem_master_bvalid, core_mem_master_bid, core_mem_master_bresp, core_mem_master_bready, core_mem_master_arvalid, core_mem_master_arid, core_mem_master_araddr, core_mem_master_arlen, core_mem_master_arsize, core_mem_master_arburst, core_mem_master_arlock, core_mem_master_arcache, core_mem_master_arprot, core_mem_master_arqos, core_mem_master_arregion, core_mem_master_arready, core_mem_master_rvalid, core_mem_master_rid, core_mem_master_rdata, core_mem_master_rresp, core_mem_master_rlast, core_mem_master_rready, dma_server_awvalid, dma_server_awid, dma_server_awaddr, dma_server_awlen, dma_server_awsize, dma_server_awburst, dma_server_awlock, dma_server_awcache, dma_server_awprot, dma_server_awqos, dma_server_awregion, dma_server_awready, dma_server_wvalid, dma_server_wdata, dma_server_wstrb, dma_server_wlast, dma_server_wready, dma_server_bvalid, dma_server_bid, dma_server_bresp, dma_server_bready, dma_server_arvalid, dma_server_arid, dma_server_araddr, dma_server_arlen, dma_server_arsize, dma_server_arburst, dma_server_arlock, dma_server_arcache, dma_server_arprot, dma_server_arqos, dma_server_arregion, dma_server_arready, dma_server_rvalid, dma_server_rid, dma_server_rdata, dma_server_rresp, dma_server_rlast, dma_server_rready, core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, nmi_req_set_not_clear, set_verbosity_verbosity, set_verbosity_logdelay, EN_set_verbosity, RDY_set_verbosity, set_watch_tohost_watch_tohost, set_watch_tohost_tohost_addr, EN_set_watch_tohost, RDY_set_watch_tohost, mv_tohost_value, RDY_mv_tohost_value, EN_ma_ddr4_ready, RDY_ma_ddr4_ready, mv_status); input RST_N_dm_power_on_reset; input CLK; input RST_N; // action method cpu_reset_server_request_put input cpu_reset_server_request_put; input EN_cpu_reset_server_request_put; output RDY_cpu_reset_server_request_put; // actionvalue method cpu_reset_server_response_get input EN_cpu_reset_server_response_get; output cpu_reset_server_response_get; output RDY_cpu_reset_server_response_get; // value method cpu_imem_master_m_awvalid output cpu_imem_master_awvalid; // value method cpu_imem_master_m_awid output [3 : 0] cpu_imem_master_awid; // value method cpu_imem_master_m_awaddr output [63 : 0] cpu_imem_master_awaddr; // value method cpu_imem_master_m_awlen output [7 : 0] cpu_imem_master_awlen; // value method cpu_imem_master_m_awsize output [2 : 0] cpu_imem_master_awsize; // value method cpu_imem_master_m_awburst output [1 : 0] cpu_imem_master_awburst; // value method cpu_imem_master_m_awlock output cpu_imem_master_awlock; // value method cpu_imem_master_m_awcache output [3 : 0] cpu_imem_master_awcache; // value method cpu_imem_master_m_awprot output [2 : 0] cpu_imem_master_awprot; // value method cpu_imem_master_m_awqos output [3 : 0] cpu_imem_master_awqos; // value method cpu_imem_master_m_awregion output [3 : 0] cpu_imem_master_awregion; // value method cpu_imem_master_m_awuser // action method cpu_imem_master_m_awready input cpu_imem_master_awready; // value method cpu_imem_master_m_wvalid output cpu_imem_master_wvalid; // value method cpu_imem_master_m_wdata output [63 : 0] cpu_imem_master_wdata; // value method cpu_imem_master_m_wstrb output [7 : 0] cpu_imem_master_wstrb; // value method cpu_imem_master_m_wlast output cpu_imem_master_wlast; // value method cpu_imem_master_m_wuser // action method cpu_imem_master_m_wready input cpu_imem_master_wready; // action method cpu_imem_master_m_bvalid input cpu_imem_master_bvalid; input [3 : 0] cpu_imem_master_bid; input [1 : 0] cpu_imem_master_bresp; // value method cpu_imem_master_m_bready output cpu_imem_master_bready; // value method cpu_imem_master_m_arvalid output cpu_imem_master_arvalid; // value method cpu_imem_master_m_arid output [3 : 0] cpu_imem_master_arid; // value method cpu_imem_master_m_araddr output [63 : 0] cpu_imem_master_araddr; // value method cpu_imem_master_m_arlen output [7 : 0] cpu_imem_master_arlen; // value method cpu_imem_master_m_arsize output [2 : 0] cpu_imem_master_arsize; // value method cpu_imem_master_m_arburst output [1 : 0] cpu_imem_master_arburst; // value method cpu_imem_master_m_arlock output cpu_imem_master_arlock; // value method cpu_imem_master_m_arcache output [3 : 0] cpu_imem_master_arcache; // value method cpu_imem_master_m_arprot output [2 : 0] cpu_imem_master_arprot; // value method cpu_imem_master_m_arqos output [3 : 0] cpu_imem_master_arqos; // value method cpu_imem_master_m_arregion output [3 : 0] cpu_imem_master_arregion; // value method cpu_imem_master_m_aruser // action method cpu_imem_master_m_arready input cpu_imem_master_arready; // action method cpu_imem_master_m_rvalid input cpu_imem_master_rvalid; input [3 : 0] cpu_imem_master_rid; input [63 : 0] cpu_imem_master_rdata; input [1 : 0] cpu_imem_master_rresp; input cpu_imem_master_rlast; // value method cpu_imem_master_m_rready output cpu_imem_master_rready; // value method core_mem_master_m_awvalid output core_mem_master_awvalid; // value method core_mem_master_m_awid output [3 : 0] core_mem_master_awid; // value method core_mem_master_m_awaddr output [63 : 0] core_mem_master_awaddr; // value method core_mem_master_m_awlen output [7 : 0] core_mem_master_awlen; // value method core_mem_master_m_awsize output [2 : 0] core_mem_master_awsize; // value method core_mem_master_m_awburst output [1 : 0] core_mem_master_awburst; // value method core_mem_master_m_awlock output core_mem_master_awlock; // value method core_mem_master_m_awcache output [3 : 0] core_mem_master_awcache; // value method core_mem_master_m_awprot output [2 : 0] core_mem_master_awprot; // value method core_mem_master_m_awqos output [3 : 0] core_mem_master_awqos; // value method core_mem_master_m_awregion output [3 : 0] core_mem_master_awregion; // value method core_mem_master_m_awuser // action method core_mem_master_m_awready input core_mem_master_awready; // value method core_mem_master_m_wvalid output core_mem_master_wvalid; // value method core_mem_master_m_wdata output [63 : 0] core_mem_master_wdata; // value method core_mem_master_m_wstrb output [7 : 0] core_mem_master_wstrb; // value method core_mem_master_m_wlast output core_mem_master_wlast; // value method core_mem_master_m_wuser // action method core_mem_master_m_wready input core_mem_master_wready; // action method core_mem_master_m_bvalid input core_mem_master_bvalid; input [3 : 0] core_mem_master_bid; input [1 : 0] core_mem_master_bresp; // value method core_mem_master_m_bready output core_mem_master_bready; // value method core_mem_master_m_arvalid output core_mem_master_arvalid; // value method core_mem_master_m_arid output [3 : 0] core_mem_master_arid; // value method core_mem_master_m_araddr output [63 : 0] core_mem_master_araddr; // value method core_mem_master_m_arlen output [7 : 0] core_mem_master_arlen; // value method core_mem_master_m_arsize output [2 : 0] core_mem_master_arsize; // value method core_mem_master_m_arburst output [1 : 0] core_mem_master_arburst; // value method core_mem_master_m_arlock output core_mem_master_arlock; // value method core_mem_master_m_arcache output [3 : 0] core_mem_master_arcache; // value method core_mem_master_m_arprot output [2 : 0] core_mem_master_arprot; // value method core_mem_master_m_arqos output [3 : 0] core_mem_master_arqos; // value method core_mem_master_m_arregion output [3 : 0] core_mem_master_arregion; // value method core_mem_master_m_aruser // action method core_mem_master_m_arready input core_mem_master_arready; // action method core_mem_master_m_rvalid input core_mem_master_rvalid; input [3 : 0] core_mem_master_rid; input [63 : 0] core_mem_master_rdata; input [1 : 0] core_mem_master_rresp; input core_mem_master_rlast; // value method core_mem_master_m_rready output core_mem_master_rready; // action method dma_server_m_awvalid input dma_server_awvalid; input [15 : 0] dma_server_awid; input [63 : 0] dma_server_awaddr; input [7 : 0] dma_server_awlen; input [2 : 0] dma_server_awsize; input [1 : 0] dma_server_awburst; input dma_server_awlock; input [3 : 0] dma_server_awcache; input [2 : 0] dma_server_awprot; input [3 : 0] dma_server_awqos; input [3 : 0] dma_server_awregion; // value method dma_server_m_awready output dma_server_awready; // action method dma_server_m_wvalid input dma_server_wvalid; input [511 : 0] dma_server_wdata; input [63 : 0] dma_server_wstrb; input dma_server_wlast; // value method dma_server_m_wready output dma_server_wready; // value method dma_server_m_bvalid output dma_server_bvalid; // value method dma_server_m_bid output [15 : 0] dma_server_bid; // value method dma_server_m_bresp output [1 : 0] dma_server_bresp; // value method dma_server_m_buser // action method dma_server_m_bready input dma_server_bready; // action method dma_server_m_arvalid input dma_server_arvalid; input [15 : 0] dma_server_arid; input [63 : 0] dma_server_araddr; input [7 : 0] dma_server_arlen; input [2 : 0] dma_server_arsize; input [1 : 0] dma_server_arburst; input dma_server_arlock; input [3 : 0] dma_server_arcache; input [2 : 0] dma_server_arprot; input [3 : 0] dma_server_arqos; input [3 : 0] dma_server_arregion; // value method dma_server_m_arready output dma_server_arready; // value method dma_server_m_rvalid output dma_server_rvalid; // value method dma_server_m_rid output [15 : 0] dma_server_rid; // value method dma_server_m_rdata output [511 : 0] dma_server_rdata; // value method dma_server_m_rresp output [1 : 0] dma_server_rresp; // value method dma_server_m_rlast output dma_server_rlast; // value method dma_server_m_ruser // action method dma_server_m_rready input dma_server_rready; // action method core_external_interrupt_sources_0_m_interrupt_req input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_1_m_interrupt_req input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_2_m_interrupt_req input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_3_m_interrupt_req input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_4_m_interrupt_req input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_5_m_interrupt_req input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_6_m_interrupt_req input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_7_m_interrupt_req input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_8_m_interrupt_req input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_9_m_interrupt_req input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_10_m_interrupt_req input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_11_m_interrupt_req input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_12_m_interrupt_req input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_13_m_interrupt_req input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_14_m_interrupt_req input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear; // action method core_external_interrupt_sources_15_m_interrupt_req input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; // action method nmi_req input nmi_req_set_not_clear; // action method set_verbosity input [3 : 0] set_verbosity_verbosity; input [63 : 0] set_verbosity_logdelay; input EN_set_verbosity; output RDY_set_verbosity; // action method set_watch_tohost input set_watch_tohost_watch_tohost; input [63 : 0] set_watch_tohost_tohost_addr; input EN_set_watch_tohost; output RDY_set_watch_tohost; // value method mv_tohost_value output [63 : 0] mv_tohost_value; output RDY_mv_tohost_value; // action method ma_ddr4_ready input EN_ma_ddr4_ready; output RDY_ma_ddr4_ready; // value method mv_status output [7 : 0] mv_status; // signals for module outputs wire [511 : 0] dma_server_rdata; wire [63 : 0] core_mem_master_araddr, core_mem_master_awaddr, core_mem_master_wdata, cpu_imem_master_araddr, cpu_imem_master_awaddr, cpu_imem_master_wdata, mv_tohost_value; wire [15 : 0] dma_server_bid, dma_server_rid; wire [7 : 0] core_mem_master_arlen, core_mem_master_awlen, core_mem_master_wstrb, cpu_imem_master_arlen, cpu_imem_master_awlen, cpu_imem_master_wstrb, mv_status; wire [3 : 0] core_mem_master_arcache, core_mem_master_arid, core_mem_master_arqos, core_mem_master_arregion, core_mem_master_awcache, core_mem_master_awid, core_mem_master_awqos, core_mem_master_awregion, cpu_imem_master_arcache, cpu_imem_master_arid, cpu_imem_master_arqos, cpu_imem_master_arregion, cpu_imem_master_awcache, cpu_imem_master_awid, cpu_imem_master_awqos, cpu_imem_master_awregion; wire [2 : 0] core_mem_master_arprot, core_mem_master_arsize, core_mem_master_awprot, core_mem_master_awsize, cpu_imem_master_arprot, cpu_imem_master_arsize, cpu_imem_master_awprot, cpu_imem_master_awsize; wire [1 : 0] core_mem_master_arburst, core_mem_master_awburst, cpu_imem_master_arburst, cpu_imem_master_awburst, dma_server_bresp, dma_server_rresp; wire RDY_cpu_reset_server_request_put, RDY_cpu_reset_server_response_get, RDY_ma_ddr4_ready, RDY_mv_tohost_value, RDY_set_verbosity, RDY_set_watch_tohost, core_mem_master_arlock, core_mem_master_arvalid, core_mem_master_awlock, core_mem_master_awvalid, core_mem_master_bready, core_mem_master_rready, core_mem_master_wlast, core_mem_master_wvalid, cpu_imem_master_arlock, cpu_imem_master_arvalid, cpu_imem_master_awlock, cpu_imem_master_awvalid, cpu_imem_master_bready, cpu_imem_master_rready, cpu_imem_master_wlast, cpu_imem_master_wvalid, cpu_reset_server_response_get, dma_server_arready, dma_server_awready, dma_server_bvalid, dma_server_rlast, dma_server_rvalid, dma_server_wready; // ports of submodule cpu wire [511 : 0] cpu$dma_server_rdata, cpu$dma_server_wdata; wire [63 : 0] cpu$dma_server_araddr, cpu$dma_server_awaddr, cpu$dma_server_wstrb, cpu$imem_master_araddr, cpu$imem_master_awaddr, cpu$imem_master_rdata, cpu$imem_master_wdata, cpu$mem_master_araddr, cpu$mem_master_awaddr, cpu$mem_master_rdata, cpu$mem_master_wdata, cpu$mv_tohost_value, cpu$set_verbosity_logdelay, cpu$set_watch_tohost_tohost_addr; wire [15 : 0] cpu$dma_server_arid, cpu$dma_server_awid, cpu$dma_server_bid, cpu$dma_server_rid; wire [7 : 0] cpu$dma_server_arlen, cpu$dma_server_awlen, cpu$imem_master_arlen, cpu$imem_master_awlen, cpu$imem_master_wstrb, cpu$mem_master_arlen, cpu$mem_master_awlen, cpu$mem_master_wstrb, cpu$mv_status; wire [3 : 0] cpu$dma_server_arcache, cpu$dma_server_arqos, cpu$dma_server_arregion, cpu$dma_server_awcache, cpu$dma_server_awqos, cpu$dma_server_awregion, cpu$imem_master_arcache, cpu$imem_master_arid, cpu$imem_master_arqos, cpu$imem_master_arregion, cpu$imem_master_awcache, cpu$imem_master_awid, cpu$imem_master_awqos, cpu$imem_master_awregion, cpu$imem_master_bid, cpu$imem_master_rid, cpu$mem_master_arcache, cpu$mem_master_arid, cpu$mem_master_arqos, cpu$mem_master_arregion, cpu$mem_master_awcache, cpu$mem_master_awid, cpu$mem_master_awqos, cpu$mem_master_awregion, cpu$mem_master_bid, cpu$mem_master_rid, cpu$set_verbosity_verbosity; wire [2 : 0] cpu$dma_server_arprot, cpu$dma_server_arsize, cpu$dma_server_awprot, cpu$dma_server_awsize, cpu$imem_master_arprot, cpu$imem_master_arsize, cpu$imem_master_awprot, cpu$imem_master_awsize, cpu$mem_master_arprot, cpu$mem_master_arsize, cpu$mem_master_awprot, cpu$mem_master_awsize; wire [1 : 0] cpu$dma_server_arburst, cpu$dma_server_awburst, cpu$dma_server_bresp, cpu$dma_server_rresp, cpu$imem_master_arburst, cpu$imem_master_awburst, cpu$imem_master_bresp, cpu$imem_master_rresp, cpu$mem_master_arburst, cpu$mem_master_awburst, cpu$mem_master_bresp, cpu$mem_master_rresp; wire cpu$EN_hart0_server_reset_request_put, cpu$EN_hart0_server_reset_response_get, cpu$EN_ma_ddr4_ready, cpu$EN_set_verbosity, cpu$EN_set_watch_tohost, cpu$RDY_hart0_server_reset_request_put, cpu$RDY_hart0_server_reset_response_get, cpu$dma_server_arlock, cpu$dma_server_arready, cpu$dma_server_arvalid, cpu$dma_server_awlock, cpu$dma_server_awready, cpu$dma_server_awvalid, cpu$dma_server_bready, cpu$dma_server_bvalid, cpu$dma_server_rlast, cpu$dma_server_rready, cpu$dma_server_rvalid, cpu$dma_server_wlast, cpu$dma_server_wready, cpu$dma_server_wvalid, cpu$hart0_server_reset_request_put, cpu$hart0_server_reset_response_get, cpu$imem_master_arlock, cpu$imem_master_arready, cpu$imem_master_arvalid, cpu$imem_master_awlock, cpu$imem_master_awready, cpu$imem_master_awvalid, cpu$imem_master_bready, cpu$imem_master_bvalid, cpu$imem_master_rlast, cpu$imem_master_rready, cpu$imem_master_rvalid, cpu$imem_master_wlast, cpu$imem_master_wready, cpu$imem_master_wvalid, cpu$m_external_interrupt_req_set_not_clear, cpu$mem_master_arlock, cpu$mem_master_arready, cpu$mem_master_arvalid, cpu$mem_master_awlock, cpu$mem_master_awready, cpu$mem_master_awvalid, cpu$mem_master_bready, cpu$mem_master_bvalid, cpu$mem_master_rlast, cpu$mem_master_rready, cpu$mem_master_rvalid, cpu$mem_master_wlast, cpu$mem_master_wready, cpu$mem_master_wvalid, cpu$nmi_req_set_not_clear, cpu$s_external_interrupt_req_set_not_clear, cpu$set_watch_tohost_watch_tohost, cpu$software_interrupt_req_set_not_clear, cpu$timer_interrupt_req_set_not_clear; // ports of submodule f_reset_reqs wire f_reset_reqs$CLR, f_reset_reqs$DEQ, f_reset_reqs$D_IN, f_reset_reqs$D_OUT, f_reset_reqs$EMPTY_N, f_reset_reqs$ENQ, f_reset_reqs$FULL_N; // ports of submodule f_reset_rsps wire f_reset_rsps$CLR, f_reset_rsps$DEQ, f_reset_rsps$D_IN, f_reset_rsps$D_OUT, f_reset_rsps$EMPTY_N, f_reset_rsps$ENQ, f_reset_rsps$FULL_N; // ports of submodule fabric_2x3 wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, fabric_2x3$v_from_masters_0_awaddr, fabric_2x3$v_from_masters_0_rdata, fabric_2x3$v_from_masters_0_wdata, fabric_2x3$v_from_masters_1_araddr, fabric_2x3$v_from_masters_1_awaddr, fabric_2x3$v_from_masters_1_wdata, fabric_2x3$v_to_slaves_0_araddr, fabric_2x3$v_to_slaves_0_awaddr, fabric_2x3$v_to_slaves_0_rdata, fabric_2x3$v_to_slaves_0_wdata, fabric_2x3$v_to_slaves_1_araddr, fabric_2x3$v_to_slaves_1_awaddr, fabric_2x3$v_to_slaves_1_rdata, fabric_2x3$v_to_slaves_1_wdata, fabric_2x3$v_to_slaves_2_araddr, fabric_2x3$v_to_slaves_2_awaddr, fabric_2x3$v_to_slaves_2_rdata, fabric_2x3$v_to_slaves_2_wdata; wire [7 : 0] fabric_2x3$v_from_masters_0_arlen, fabric_2x3$v_from_masters_0_awlen, fabric_2x3$v_from_masters_0_wstrb, fabric_2x3$v_from_masters_1_arlen, fabric_2x3$v_from_masters_1_awlen, fabric_2x3$v_from_masters_1_wstrb, fabric_2x3$v_to_slaves_0_arlen, fabric_2x3$v_to_slaves_0_awlen, fabric_2x3$v_to_slaves_0_wstrb, fabric_2x3$v_to_slaves_1_arlen, fabric_2x3$v_to_slaves_1_awlen, fabric_2x3$v_to_slaves_1_wstrb, fabric_2x3$v_to_slaves_2_arlen, fabric_2x3$v_to_slaves_2_awlen, fabric_2x3$v_to_slaves_2_wstrb; wire [3 : 0] fabric_2x3$set_verbosity_verbosity, fabric_2x3$v_from_masters_0_arcache, fabric_2x3$v_from_masters_0_arid, fabric_2x3$v_from_masters_0_arqos, fabric_2x3$v_from_masters_0_arregion, fabric_2x3$v_from_masters_0_awcache, fabric_2x3$v_from_masters_0_awid, fabric_2x3$v_from_masters_0_awqos, fabric_2x3$v_from_masters_0_awregion, fabric_2x3$v_from_masters_0_bid, fabric_2x3$v_from_masters_0_rid, fabric_2x3$v_from_masters_1_arcache, fabric_2x3$v_from_masters_1_arid, fabric_2x3$v_from_masters_1_arqos, fabric_2x3$v_from_masters_1_arregion, fabric_2x3$v_from_masters_1_awcache, fabric_2x3$v_from_masters_1_awid, fabric_2x3$v_from_masters_1_awqos, fabric_2x3$v_from_masters_1_awregion, fabric_2x3$v_to_slaves_0_arcache, fabric_2x3$v_to_slaves_0_arid, fabric_2x3$v_to_slaves_0_arqos, fabric_2x3$v_to_slaves_0_arregion, fabric_2x3$v_to_slaves_0_awcache, fabric_2x3$v_to_slaves_0_awid, fabric_2x3$v_to_slaves_0_awqos, fabric_2x3$v_to_slaves_0_awregion, fabric_2x3$v_to_slaves_0_bid, fabric_2x3$v_to_slaves_0_rid, fabric_2x3$v_to_slaves_1_arcache, fabric_2x3$v_to_slaves_1_arid, fabric_2x3$v_to_slaves_1_arqos, fabric_2x3$v_to_slaves_1_arregion, fabric_2x3$v_to_slaves_1_awcache, fabric_2x3$v_to_slaves_1_awid, fabric_2x3$v_to_slaves_1_awqos, fabric_2x3$v_to_slaves_1_awregion, fabric_2x3$v_to_slaves_1_bid, fabric_2x3$v_to_slaves_1_rid, fabric_2x3$v_to_slaves_2_arcache, fabric_2x3$v_to_slaves_2_arid, fabric_2x3$v_to_slaves_2_arqos, fabric_2x3$v_to_slaves_2_arregion, fabric_2x3$v_to_slaves_2_awcache, fabric_2x3$v_to_slaves_2_awid, fabric_2x3$v_to_slaves_2_awqos, fabric_2x3$v_to_slaves_2_awregion, fabric_2x3$v_to_slaves_2_bid, fabric_2x3$v_to_slaves_2_rid; wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, fabric_2x3$v_from_masters_0_arsize, fabric_2x3$v_from_masters_0_awprot, fabric_2x3$v_from_masters_0_awsize, fabric_2x3$v_from_masters_1_arprot, fabric_2x3$v_from_masters_1_arsize, fabric_2x3$v_from_masters_1_awprot, fabric_2x3$v_from_masters_1_awsize, fabric_2x3$v_to_slaves_0_arprot, fabric_2x3$v_to_slaves_0_arsize, fabric_2x3$v_to_slaves_0_awprot, fabric_2x3$v_to_slaves_0_awsize, fabric_2x3$v_to_slaves_1_arprot, fabric_2x3$v_to_slaves_1_arsize, fabric_2x3$v_to_slaves_1_awprot, fabric_2x3$v_to_slaves_1_awsize, fabric_2x3$v_to_slaves_2_arprot, fabric_2x3$v_to_slaves_2_arsize, fabric_2x3$v_to_slaves_2_awprot, fabric_2x3$v_to_slaves_2_awsize; wire [1 : 0] fabric_2x3$v_from_masters_0_arburst, fabric_2x3$v_from_masters_0_awburst, fabric_2x3$v_from_masters_0_bresp, fabric_2x3$v_from_masters_0_rresp, fabric_2x3$v_from_masters_1_arburst, fabric_2x3$v_from_masters_1_awburst, fabric_2x3$v_to_slaves_0_arburst, fabric_2x3$v_to_slaves_0_awburst, fabric_2x3$v_to_slaves_0_bresp, fabric_2x3$v_to_slaves_0_rresp, fabric_2x3$v_to_slaves_1_arburst, fabric_2x3$v_to_slaves_1_awburst, fabric_2x3$v_to_slaves_1_bresp, fabric_2x3$v_to_slaves_1_rresp, fabric_2x3$v_to_slaves_2_arburst, fabric_2x3$v_to_slaves_2_awburst, fabric_2x3$v_to_slaves_2_bresp, fabric_2x3$v_to_slaves_2_rresp; wire fabric_2x3$EN_reset, fabric_2x3$EN_set_verbosity, fabric_2x3$RDY_reset, fabric_2x3$v_from_masters_0_arlock, fabric_2x3$v_from_masters_0_arready, fabric_2x3$v_from_masters_0_arvalid, fabric_2x3$v_from_masters_0_awlock, fabric_2x3$v_from_masters_0_awready, fabric_2x3$v_from_masters_0_awvalid, fabric_2x3$v_from_masters_0_bready, fabric_2x3$v_from_masters_0_bvalid, fabric_2x3$v_from_masters_0_rlast, fabric_2x3$v_from_masters_0_rready, fabric_2x3$v_from_masters_0_rvalid, fabric_2x3$v_from_masters_0_wlast, fabric_2x3$v_from_masters_0_wready, fabric_2x3$v_from_masters_0_wvalid, fabric_2x3$v_from_masters_1_arlock, fabric_2x3$v_from_masters_1_arvalid, fabric_2x3$v_from_masters_1_awlock, fabric_2x3$v_from_masters_1_awvalid, fabric_2x3$v_from_masters_1_bready, fabric_2x3$v_from_masters_1_rready, fabric_2x3$v_from_masters_1_wlast, fabric_2x3$v_from_masters_1_wvalid, fabric_2x3$v_to_slaves_0_arlock, fabric_2x3$v_to_slaves_0_arready, fabric_2x3$v_to_slaves_0_arvalid, fabric_2x3$v_to_slaves_0_awlock, fabric_2x3$v_to_slaves_0_awready, fabric_2x3$v_to_slaves_0_awvalid, fabric_2x3$v_to_slaves_0_bready, fabric_2x3$v_to_slaves_0_bvalid, fabric_2x3$v_to_slaves_0_rlast, fabric_2x3$v_to_slaves_0_rready, fabric_2x3$v_to_slaves_0_rvalid, fabric_2x3$v_to_slaves_0_wlast, fabric_2x3$v_to_slaves_0_wready, fabric_2x3$v_to_slaves_0_wvalid, fabric_2x3$v_to_slaves_1_arlock, fabric_2x3$v_to_slaves_1_arready, fabric_2x3$v_to_slaves_1_arvalid, fabric_2x3$v_to_slaves_1_awlock, fabric_2x3$v_to_slaves_1_awready, fabric_2x3$v_to_slaves_1_awvalid, fabric_2x3$v_to_slaves_1_bready, fabric_2x3$v_to_slaves_1_bvalid, fabric_2x3$v_to_slaves_1_rlast, fabric_2x3$v_to_slaves_1_rready, fabric_2x3$v_to_slaves_1_rvalid, fabric_2x3$v_to_slaves_1_wlast, fabric_2x3$v_to_slaves_1_wready, fabric_2x3$v_to_slaves_1_wvalid, fabric_2x3$v_to_slaves_2_arlock, fabric_2x3$v_to_slaves_2_arready, fabric_2x3$v_to_slaves_2_arvalid, fabric_2x3$v_to_slaves_2_awlock, fabric_2x3$v_to_slaves_2_awready, fabric_2x3$v_to_slaves_2_awvalid, fabric_2x3$v_to_slaves_2_bready, fabric_2x3$v_to_slaves_2_bvalid, fabric_2x3$v_to_slaves_2_rlast, fabric_2x3$v_to_slaves_2_rready, fabric_2x3$v_to_slaves_2_rvalid, fabric_2x3$v_to_slaves_2_wlast, fabric_2x3$v_to_slaves_2_wready, fabric_2x3$v_to_slaves_2_wvalid; // ports of submodule near_mem_io wire [63 : 0] near_mem_io$axi4_slave_araddr, near_mem_io$axi4_slave_awaddr, near_mem_io$axi4_slave_rdata, near_mem_io$axi4_slave_wdata, near_mem_io$set_addr_map_addr_base, near_mem_io$set_addr_map_addr_lim; wire [7 : 0] near_mem_io$axi4_slave_arlen, near_mem_io$axi4_slave_awlen, near_mem_io$axi4_slave_wstrb; wire [3 : 0] near_mem_io$axi4_slave_arcache, near_mem_io$axi4_slave_arid, near_mem_io$axi4_slave_arqos, near_mem_io$axi4_slave_arregion, near_mem_io$axi4_slave_awcache, near_mem_io$axi4_slave_awid, near_mem_io$axi4_slave_awqos, near_mem_io$axi4_slave_awregion, near_mem_io$axi4_slave_bid, near_mem_io$axi4_slave_rid; wire [2 : 0] near_mem_io$axi4_slave_arprot, near_mem_io$axi4_slave_arsize, near_mem_io$axi4_slave_awprot, near_mem_io$axi4_slave_awsize; wire [1 : 0] near_mem_io$axi4_slave_arburst, near_mem_io$axi4_slave_awburst, near_mem_io$axi4_slave_bresp, near_mem_io$axi4_slave_rresp; wire near_mem_io$EN_get_sw_interrupt_req_get, near_mem_io$EN_get_timer_interrupt_req_get, near_mem_io$EN_server_reset_request_put, near_mem_io$EN_server_reset_response_get, near_mem_io$EN_set_addr_map, near_mem_io$RDY_get_sw_interrupt_req_get, near_mem_io$RDY_get_timer_interrupt_req_get, near_mem_io$RDY_server_reset_request_put, near_mem_io$RDY_server_reset_response_get, near_mem_io$axi4_slave_arlock, near_mem_io$axi4_slave_arready, near_mem_io$axi4_slave_arvalid, near_mem_io$axi4_slave_awlock, near_mem_io$axi4_slave_awready, near_mem_io$axi4_slave_awvalid, near_mem_io$axi4_slave_bready, near_mem_io$axi4_slave_bvalid, near_mem_io$axi4_slave_rlast, near_mem_io$axi4_slave_rready, near_mem_io$axi4_slave_rvalid, near_mem_io$axi4_slave_wlast, near_mem_io$axi4_slave_wready, near_mem_io$axi4_slave_wvalid, near_mem_io$get_sw_interrupt_req_get, near_mem_io$get_timer_interrupt_req_get; // ports of submodule plic wire [63 : 0] plic$axi4_slave_araddr, plic$axi4_slave_awaddr, plic$axi4_slave_rdata, plic$axi4_slave_wdata, plic$set_addr_map_addr_base, plic$set_addr_map_addr_lim; wire [7 : 0] plic$axi4_slave_arlen, plic$axi4_slave_awlen, plic$axi4_slave_wstrb; wire [3 : 0] plic$axi4_slave_arcache, plic$axi4_slave_arid, plic$axi4_slave_arqos, plic$axi4_slave_arregion, plic$axi4_slave_awcache, plic$axi4_slave_awid, plic$axi4_slave_awqos, plic$axi4_slave_awregion, plic$axi4_slave_bid, plic$axi4_slave_rid, plic$set_verbosity_verbosity; wire [2 : 0] plic$axi4_slave_arprot, plic$axi4_slave_arsize, plic$axi4_slave_awprot, plic$axi4_slave_awsize; wire [1 : 0] plic$axi4_slave_arburst, plic$axi4_slave_awburst, plic$axi4_slave_bresp, plic$axi4_slave_rresp; wire plic$EN_server_reset_request_put, plic$EN_server_reset_response_get, plic$EN_set_addr_map, plic$EN_set_verbosity, plic$EN_show_PLIC_state, plic$RDY_server_reset_request_put, plic$RDY_server_reset_response_get, plic$axi4_slave_arlock, plic$axi4_slave_arready, plic$axi4_slave_arvalid, plic$axi4_slave_awlock, plic$axi4_slave_awready, plic$axi4_slave_awvalid, plic$axi4_slave_bready, plic$axi4_slave_bvalid, plic$axi4_slave_rlast, plic$axi4_slave_rready, plic$axi4_slave_rvalid, plic$axi4_slave_wlast, plic$axi4_slave_wready, plic$axi4_slave_wvalid, plic$v_sources_0_m_interrupt_req_set_not_clear, plic$v_sources_10_m_interrupt_req_set_not_clear, plic$v_sources_11_m_interrupt_req_set_not_clear, plic$v_sources_12_m_interrupt_req_set_not_clear, plic$v_sources_13_m_interrupt_req_set_not_clear, plic$v_sources_14_m_interrupt_req_set_not_clear, plic$v_sources_15_m_interrupt_req_set_not_clear, plic$v_sources_1_m_interrupt_req_set_not_clear, plic$v_sources_2_m_interrupt_req_set_not_clear, plic$v_sources_3_m_interrupt_req_set_not_clear, plic$v_sources_4_m_interrupt_req_set_not_clear, plic$v_sources_5_m_interrupt_req_set_not_clear, plic$v_sources_6_m_interrupt_req_set_not_clear, plic$v_sources_7_m_interrupt_req_set_not_clear, plic$v_sources_8_m_interrupt_req_set_not_clear, plic$v_sources_9_m_interrupt_req_set_not_clear, plic$v_targets_0_m_eip, plic$v_targets_1_m_eip; // ports of submodule soc_map wire [63 : 0] soc_map$m_is_IO_addr_addr, soc_map$m_is_mem_addr_addr, soc_map$m_is_near_mem_IO_addr_addr, soc_map$m_near_mem_io_addr_base, soc_map$m_near_mem_io_addr_lim, soc_map$m_plic_addr_base, soc_map$m_plic_addr_lim; // rule scheduling signals wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete, CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, CAN_FIRE_RL_rl_rd_addr_channel, CAN_FIRE_RL_rl_rd_addr_channel_1, CAN_FIRE_RL_rl_rd_addr_channel_2, CAN_FIRE_RL_rl_rd_addr_channel_3, CAN_FIRE_RL_rl_rd_data_channel, CAN_FIRE_RL_rl_rd_data_channel_1, CAN_FIRE_RL_rl_rd_data_channel_2, CAN_FIRE_RL_rl_rd_data_channel_3, CAN_FIRE_RL_rl_relay_external_interrupts, CAN_FIRE_RL_rl_relay_sw_interrupts, CAN_FIRE_RL_rl_relay_timer_interrupts, CAN_FIRE_RL_rl_wr_addr_channel, CAN_FIRE_RL_rl_wr_addr_channel_1, CAN_FIRE_RL_rl_wr_addr_channel_2, CAN_FIRE_RL_rl_wr_addr_channel_3, CAN_FIRE_RL_rl_wr_data_channel, CAN_FIRE_RL_rl_wr_data_channel_1, CAN_FIRE_RL_rl_wr_data_channel_2, CAN_FIRE_RL_rl_wr_data_channel_3, CAN_FIRE_RL_rl_wr_response_channel, CAN_FIRE_RL_rl_wr_response_channel_1, CAN_FIRE_RL_rl_wr_response_channel_2, CAN_FIRE_RL_rl_wr_response_channel_3, CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, CAN_FIRE_core_mem_master_m_arready, CAN_FIRE_core_mem_master_m_awready, CAN_FIRE_core_mem_master_m_bvalid, CAN_FIRE_core_mem_master_m_rvalid, CAN_FIRE_core_mem_master_m_wready, CAN_FIRE_cpu_imem_master_m_arready, CAN_FIRE_cpu_imem_master_m_awready, CAN_FIRE_cpu_imem_master_m_bvalid, CAN_FIRE_cpu_imem_master_m_rvalid, CAN_FIRE_cpu_imem_master_m_wready, CAN_FIRE_cpu_reset_server_request_put, CAN_FIRE_cpu_reset_server_response_get, CAN_FIRE_dma_server_m_arvalid, CAN_FIRE_dma_server_m_awvalid, CAN_FIRE_dma_server_m_bready, CAN_FIRE_dma_server_m_rready, CAN_FIRE_dma_server_m_wvalid, CAN_FIRE_ma_ddr4_ready, CAN_FIRE_nmi_req, CAN_FIRE_set_verbosity, CAN_FIRE_set_watch_tohost, WILL_FIRE_RL_rl_cpu_hart0_reset_complete, WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, WILL_FIRE_RL_rl_rd_addr_channel, WILL_FIRE_RL_rl_rd_addr_channel_1, WILL_FIRE_RL_rl_rd_addr_channel_2, WILL_FIRE_RL_rl_rd_addr_channel_3, WILL_FIRE_RL_rl_rd_data_channel, WILL_FIRE_RL_rl_rd_data_channel_1, WILL_FIRE_RL_rl_rd_data_channel_2, WILL_FIRE_RL_rl_rd_data_channel_3, WILL_FIRE_RL_rl_relay_external_interrupts, WILL_FIRE_RL_rl_relay_sw_interrupts, WILL_FIRE_RL_rl_relay_timer_interrupts, WILL_FIRE_RL_rl_wr_addr_channel, WILL_FIRE_RL_rl_wr_addr_channel_1, WILL_FIRE_RL_rl_wr_addr_channel_2, WILL_FIRE_RL_rl_wr_addr_channel_3, WILL_FIRE_RL_rl_wr_data_channel, WILL_FIRE_RL_rl_wr_data_channel_1, WILL_FIRE_RL_rl_wr_data_channel_2, WILL_FIRE_RL_rl_wr_data_channel_3, WILL_FIRE_RL_rl_wr_response_channel, WILL_FIRE_RL_rl_wr_response_channel_1, WILL_FIRE_RL_rl_wr_response_channel_2, WILL_FIRE_RL_rl_wr_response_channel_3, WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, WILL_FIRE_core_mem_master_m_arready, WILL_FIRE_core_mem_master_m_awready, WILL_FIRE_core_mem_master_m_bvalid, WILL_FIRE_core_mem_master_m_rvalid, WILL_FIRE_core_mem_master_m_wready, WILL_FIRE_cpu_imem_master_m_arready, WILL_FIRE_cpu_imem_master_m_awready, WILL_FIRE_cpu_imem_master_m_bvalid, WILL_FIRE_cpu_imem_master_m_rvalid, WILL_FIRE_cpu_imem_master_m_wready, WILL_FIRE_cpu_reset_server_request_put, WILL_FIRE_cpu_reset_server_response_get, WILL_FIRE_dma_server_m_arvalid, WILL_FIRE_dma_server_m_awvalid, WILL_FIRE_dma_server_m_bready, WILL_FIRE_dma_server_m_rready, WILL_FIRE_dma_server_m_wvalid, WILL_FIRE_ma_ddr4_ready, WILL_FIRE_nmi_req, WILL_FIRE_set_verbosity, WILL_FIRE_set_watch_tohost; // declarations used by system tasks // synopsys translate_off reg [31 : 0] v__h4601; reg [31 : 0] v__h4817; reg [31 : 0] v__h4595; reg [31 : 0] v__h4811; // synopsys translate_on // remaining internal signals wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8; // action method cpu_reset_server_request_put assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; assign WILL_FIRE_cpu_reset_server_request_put = EN_cpu_reset_server_request_put ; // actionvalue method cpu_reset_server_response_get assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ; assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; assign WILL_FIRE_cpu_reset_server_response_get = EN_cpu_reset_server_response_get ; // value method cpu_imem_master_m_awvalid assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; // value method cpu_imem_master_m_awid assign cpu_imem_master_awid = cpu$imem_master_awid ; // value method cpu_imem_master_m_awaddr assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ; // value method cpu_imem_master_m_awlen assign cpu_imem_master_awlen = cpu$imem_master_awlen ; // value method cpu_imem_master_m_awsize assign cpu_imem_master_awsize = cpu$imem_master_awsize ; // value method cpu_imem_master_m_awburst assign cpu_imem_master_awburst = cpu$imem_master_awburst ; // value method cpu_imem_master_m_awlock assign cpu_imem_master_awlock = cpu$imem_master_awlock ; // value method cpu_imem_master_m_awcache assign cpu_imem_master_awcache = cpu$imem_master_awcache ; // value method cpu_imem_master_m_awprot assign cpu_imem_master_awprot = cpu$imem_master_awprot ; // value method cpu_imem_master_m_awqos assign cpu_imem_master_awqos = cpu$imem_master_awqos ; // value method cpu_imem_master_m_awregion assign cpu_imem_master_awregion = cpu$imem_master_awregion ; // action method cpu_imem_master_m_awready assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ; assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ; // value method cpu_imem_master_m_wvalid assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; // value method cpu_imem_master_m_wdata assign cpu_imem_master_wdata = cpu$imem_master_wdata ; // value method cpu_imem_master_m_wstrb assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ; // value method cpu_imem_master_m_wlast assign cpu_imem_master_wlast = cpu$imem_master_wlast ; // action method cpu_imem_master_m_wready assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ; assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ; // action method cpu_imem_master_m_bvalid assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; // value method cpu_imem_master_m_bready assign cpu_imem_master_bready = cpu$imem_master_bready ; // value method cpu_imem_master_m_arvalid assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; // value method cpu_imem_master_m_arid assign cpu_imem_master_arid = cpu$imem_master_arid ; // value method cpu_imem_master_m_araddr assign cpu_imem_master_araddr = cpu$imem_master_araddr ; // value method cpu_imem_master_m_arlen assign cpu_imem_master_arlen = cpu$imem_master_arlen ; // value method cpu_imem_master_m_arsize assign cpu_imem_master_arsize = cpu$imem_master_arsize ; // value method cpu_imem_master_m_arburst assign cpu_imem_master_arburst = cpu$imem_master_arburst ; // value method cpu_imem_master_m_arlock assign cpu_imem_master_arlock = cpu$imem_master_arlock ; // value method cpu_imem_master_m_arcache assign cpu_imem_master_arcache = cpu$imem_master_arcache ; // value method cpu_imem_master_m_arprot assign cpu_imem_master_arprot = cpu$imem_master_arprot ; // value method cpu_imem_master_m_arqos assign cpu_imem_master_arqos = cpu$imem_master_arqos ; // value method cpu_imem_master_m_arregion assign cpu_imem_master_arregion = cpu$imem_master_arregion ; // action method cpu_imem_master_m_arready assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ; assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ; // action method cpu_imem_master_m_rvalid assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; // value method cpu_imem_master_m_rready assign cpu_imem_master_rready = cpu$imem_master_rready ; // value method core_mem_master_m_awvalid assign core_mem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ; // value method core_mem_master_m_awid assign core_mem_master_awid = fabric_2x3$v_to_slaves_0_awid ; // value method core_mem_master_m_awaddr assign core_mem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ; // value method core_mem_master_m_awlen assign core_mem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ; // value method core_mem_master_m_awsize assign core_mem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ; // value method core_mem_master_m_awburst assign core_mem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ; // value method core_mem_master_m_awlock assign core_mem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ; // value method core_mem_master_m_awcache assign core_mem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ; // value method core_mem_master_m_awprot assign core_mem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ; // value method core_mem_master_m_awqos assign core_mem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ; // value method core_mem_master_m_awregion assign core_mem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ; // action method core_mem_master_m_awready assign CAN_FIRE_core_mem_master_m_awready = 1'd1 ; assign WILL_FIRE_core_mem_master_m_awready = 1'd1 ; // value method core_mem_master_m_wvalid assign core_mem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; // value method core_mem_master_m_wdata assign core_mem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; // value method core_mem_master_m_wstrb assign core_mem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ; // value method core_mem_master_m_wlast assign core_mem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ; // action method core_mem_master_m_wready assign CAN_FIRE_core_mem_master_m_wready = 1'd1 ; assign WILL_FIRE_core_mem_master_m_wready = 1'd1 ; // action method core_mem_master_m_bvalid assign CAN_FIRE_core_mem_master_m_bvalid = 1'd1 ; assign WILL_FIRE_core_mem_master_m_bvalid = 1'd1 ; // value method core_mem_master_m_bready assign core_mem_master_bready = fabric_2x3$v_to_slaves_0_bready ; // value method core_mem_master_m_arvalid assign core_mem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ; // value method core_mem_master_m_arid assign core_mem_master_arid = fabric_2x3$v_to_slaves_0_arid ; // value method core_mem_master_m_araddr assign core_mem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ; // value method core_mem_master_m_arlen assign core_mem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ; // value method core_mem_master_m_arsize assign core_mem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ; // value method core_mem_master_m_arburst assign core_mem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ; // value method core_mem_master_m_arlock assign core_mem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ; // value method core_mem_master_m_arcache assign core_mem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ; // value method core_mem_master_m_arprot assign core_mem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ; // value method core_mem_master_m_arqos assign core_mem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ; // value method core_mem_master_m_arregion assign core_mem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ; // action method core_mem_master_m_arready assign CAN_FIRE_core_mem_master_m_arready = 1'd1 ; assign WILL_FIRE_core_mem_master_m_arready = 1'd1 ; // action method core_mem_master_m_rvalid assign CAN_FIRE_core_mem_master_m_rvalid = 1'd1 ; assign WILL_FIRE_core_mem_master_m_rvalid = 1'd1 ; // value method core_mem_master_m_rready assign core_mem_master_rready = fabric_2x3$v_to_slaves_0_rready ; // action method dma_server_m_awvalid assign CAN_FIRE_dma_server_m_awvalid = 1'd1 ; assign WILL_FIRE_dma_server_m_awvalid = 1'd1 ; // value method dma_server_m_awready assign dma_server_awready = cpu$dma_server_awready ; // action method dma_server_m_wvalid assign CAN_FIRE_dma_server_m_wvalid = 1'd1 ; assign WILL_FIRE_dma_server_m_wvalid = 1'd1 ; // value method dma_server_m_wready assign dma_server_wready = cpu$dma_server_wready ; // value method dma_server_m_bvalid assign dma_server_bvalid = cpu$dma_server_bvalid ; // value method dma_server_m_bid assign dma_server_bid = cpu$dma_server_bid ; // value method dma_server_m_bresp assign dma_server_bresp = cpu$dma_server_bresp ; // action method dma_server_m_bready assign CAN_FIRE_dma_server_m_bready = 1'd1 ; assign WILL_FIRE_dma_server_m_bready = 1'd1 ; // action method dma_server_m_arvalid assign CAN_FIRE_dma_server_m_arvalid = 1'd1 ; assign WILL_FIRE_dma_server_m_arvalid = 1'd1 ; // value method dma_server_m_arready assign dma_server_arready = cpu$dma_server_arready ; // value method dma_server_m_rvalid assign dma_server_rvalid = cpu$dma_server_rvalid ; // value method dma_server_m_rid assign dma_server_rid = cpu$dma_server_rid ; // value method dma_server_m_rdata assign dma_server_rdata = cpu$dma_server_rdata ; // value method dma_server_m_rresp assign dma_server_rresp = cpu$dma_server_rresp ; // value method dma_server_m_rlast assign dma_server_rlast = cpu$dma_server_rlast ; // action method dma_server_m_rready assign CAN_FIRE_dma_server_m_rready = 1'd1 ; assign WILL_FIRE_dma_server_m_rready = 1'd1 ; // action method core_external_interrupt_sources_0_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_1_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_2_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_3_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_4_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_5_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_6_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_7_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_8_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_9_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_10_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_11_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_12_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_13_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_14_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; // action method core_external_interrupt_sources_15_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; // action method nmi_req assign CAN_FIRE_nmi_req = 1'd1 ; assign WILL_FIRE_nmi_req = 1'd1 ; // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; assign CAN_FIRE_set_verbosity = 1'd1 ; assign WILL_FIRE_set_verbosity = EN_set_verbosity ; // action method set_watch_tohost assign RDY_set_watch_tohost = 1'd1 ; assign CAN_FIRE_set_watch_tohost = 1'd1 ; assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; // value method mv_tohost_value assign mv_tohost_value = cpu$mv_tohost_value ; assign RDY_mv_tohost_value = 1'd1 ; // action method ma_ddr4_ready assign RDY_ma_ddr4_ready = 1'd1 ; assign CAN_FIRE_ma_ddr4_ready = 1'd1 ; assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ; // value method mv_status assign mv_status = cpu$mv_status ; // submodule cpu mkCPU cpu(.CLK(CLK), .RST_N(RST_N), .dma_server_araddr(cpu$dma_server_araddr), .dma_server_arburst(cpu$dma_server_arburst), .dma_server_arcache(cpu$dma_server_arcache), .dma_server_arid(cpu$dma_server_arid), .dma_server_arlen(cpu$dma_server_arlen), .dma_server_arlock(cpu$dma_server_arlock), .dma_server_arprot(cpu$dma_server_arprot), .dma_server_arqos(cpu$dma_server_arqos), .dma_server_arregion(cpu$dma_server_arregion), .dma_server_arsize(cpu$dma_server_arsize), .dma_server_arvalid(cpu$dma_server_arvalid), .dma_server_awaddr(cpu$dma_server_awaddr), .dma_server_awburst(cpu$dma_server_awburst), .dma_server_awcache(cpu$dma_server_awcache), .dma_server_awid(cpu$dma_server_awid), .dma_server_awlen(cpu$dma_server_awlen), .dma_server_awlock(cpu$dma_server_awlock), .dma_server_awprot(cpu$dma_server_awprot), .dma_server_awqos(cpu$dma_server_awqos), .dma_server_awregion(cpu$dma_server_awregion), .dma_server_awsize(cpu$dma_server_awsize), .dma_server_awvalid(cpu$dma_server_awvalid), .dma_server_bready(cpu$dma_server_bready), .dma_server_rready(cpu$dma_server_rready), .dma_server_wdata(cpu$dma_server_wdata), .dma_server_wlast(cpu$dma_server_wlast), .dma_server_wstrb(cpu$dma_server_wstrb), .dma_server_wvalid(cpu$dma_server_wvalid), .hart0_server_reset_request_put(cpu$hart0_server_reset_request_put), .imem_master_arready(cpu$imem_master_arready), .imem_master_awready(cpu$imem_master_awready), .imem_master_bid(cpu$imem_master_bid), .imem_master_bresp(cpu$imem_master_bresp), .imem_master_bvalid(cpu$imem_master_bvalid), .imem_master_rdata(cpu$imem_master_rdata), .imem_master_rid(cpu$imem_master_rid), .imem_master_rlast(cpu$imem_master_rlast), .imem_master_rresp(cpu$imem_master_rresp), .imem_master_rvalid(cpu$imem_master_rvalid), .imem_master_wready(cpu$imem_master_wready), .m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear), .mem_master_arready(cpu$mem_master_arready), .mem_master_awready(cpu$mem_master_awready), .mem_master_bid(cpu$mem_master_bid), .mem_master_bresp(cpu$mem_master_bresp), .mem_master_bvalid(cpu$mem_master_bvalid), .mem_master_rdata(cpu$mem_master_rdata), .mem_master_rid(cpu$mem_master_rid), .mem_master_rlast(cpu$mem_master_rlast), .mem_master_rresp(cpu$mem_master_rresp), .mem_master_rvalid(cpu$mem_master_rvalid), .mem_master_wready(cpu$mem_master_wready), .nmi_req_set_not_clear(cpu$nmi_req_set_not_clear), .s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear), .set_verbosity_logdelay(cpu$set_verbosity_logdelay), .set_verbosity_verbosity(cpu$set_verbosity_verbosity), .set_watch_tohost_tohost_addr(cpu$set_watch_tohost_tohost_addr), .set_watch_tohost_watch_tohost(cpu$set_watch_tohost_watch_tohost), .software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear), .timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear), .EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put), .EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get), .EN_set_verbosity(cpu$EN_set_verbosity), .EN_set_watch_tohost(cpu$EN_set_watch_tohost), .EN_ma_ddr4_ready(cpu$EN_ma_ddr4_ready), .RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put), .hart0_server_reset_response_get(cpu$hart0_server_reset_response_get), .RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get), .imem_master_awvalid(cpu$imem_master_awvalid), .imem_master_awid(cpu$imem_master_awid), .imem_master_awaddr(cpu$imem_master_awaddr), .imem_master_awlen(cpu$imem_master_awlen), .imem_master_awsize(cpu$imem_master_awsize), .imem_master_awburst(cpu$imem_master_awburst), .imem_master_awlock(cpu$imem_master_awlock), .imem_master_awcache(cpu$imem_master_awcache), .imem_master_awprot(cpu$imem_master_awprot), .imem_master_awqos(cpu$imem_master_awqos), .imem_master_awregion(cpu$imem_master_awregion), .imem_master_wvalid(cpu$imem_master_wvalid), .imem_master_wdata(cpu$imem_master_wdata), .imem_master_wstrb(cpu$imem_master_wstrb), .imem_master_wlast(cpu$imem_master_wlast), .imem_master_bready(cpu$imem_master_bready), .imem_master_arvalid(cpu$imem_master_arvalid), .imem_master_arid(cpu$imem_master_arid), .imem_master_araddr(cpu$imem_master_araddr), .imem_master_arlen(cpu$imem_master_arlen), .imem_master_arsize(cpu$imem_master_arsize), .imem_master_arburst(cpu$imem_master_arburst), .imem_master_arlock(cpu$imem_master_arlock), .imem_master_arcache(cpu$imem_master_arcache), .imem_master_arprot(cpu$imem_master_arprot), .imem_master_arqos(cpu$imem_master_arqos), .imem_master_arregion(cpu$imem_master_arregion), .imem_master_rready(cpu$imem_master_rready), .mem_master_awvalid(cpu$mem_master_awvalid), .mem_master_awid(cpu$mem_master_awid), .mem_master_awaddr(cpu$mem_master_awaddr), .mem_master_awlen(cpu$mem_master_awlen), .mem_master_awsize(cpu$mem_master_awsize), .mem_master_awburst(cpu$mem_master_awburst), .mem_master_awlock(cpu$mem_master_awlock), .mem_master_awcache(cpu$mem_master_awcache), .mem_master_awprot(cpu$mem_master_awprot), .mem_master_awqos(cpu$mem_master_awqos), .mem_master_awregion(cpu$mem_master_awregion), .mem_master_wvalid(cpu$mem_master_wvalid), .mem_master_wdata(cpu$mem_master_wdata), .mem_master_wstrb(cpu$mem_master_wstrb), .mem_master_wlast(cpu$mem_master_wlast), .mem_master_bready(cpu$mem_master_bready), .mem_master_arvalid(cpu$mem_master_arvalid), .mem_master_arid(cpu$mem_master_arid), .mem_master_araddr(cpu$mem_master_araddr), .mem_master_arlen(cpu$mem_master_arlen), .mem_master_arsize(cpu$mem_master_arsize), .mem_master_arburst(cpu$mem_master_arburst), .mem_master_arlock(cpu$mem_master_arlock), .mem_master_arcache(cpu$mem_master_arcache), .mem_master_arprot(cpu$mem_master_arprot), .mem_master_arqos(cpu$mem_master_arqos), .mem_master_arregion(cpu$mem_master_arregion), .mem_master_rready(cpu$mem_master_rready), .dma_server_awready(cpu$dma_server_awready), .dma_server_wready(cpu$dma_server_wready), .dma_server_bvalid(cpu$dma_server_bvalid), .dma_server_bid(cpu$dma_server_bid), .dma_server_bresp(cpu$dma_server_bresp), .dma_server_arready(cpu$dma_server_arready), .dma_server_rvalid(cpu$dma_server_rvalid), .dma_server_rid(cpu$dma_server_rid), .dma_server_rdata(cpu$dma_server_rdata), .dma_server_rresp(cpu$dma_server_rresp), .dma_server_rlast(cpu$dma_server_rlast), .RDY_set_verbosity(), .RDY_set_watch_tohost(), .mv_tohost_value(cpu$mv_tohost_value), .RDY_mv_tohost_value(), .RDY_ma_ddr4_ready(), .mv_status(cpu$mv_status)); // submodule f_reset_reqs FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_reset_reqs$D_IN), .ENQ(f_reset_reqs$ENQ), .DEQ(f_reset_reqs$DEQ), .CLR(f_reset_reqs$CLR), .D_OUT(f_reset_reqs$D_OUT), .FULL_N(f_reset_reqs$FULL_N), .EMPTY_N(f_reset_reqs$EMPTY_N)); // submodule f_reset_rsps FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_reset_rsps$D_IN), .ENQ(f_reset_rsps$ENQ), .DEQ(f_reset_rsps$DEQ), .CLR(f_reset_rsps$CLR), .D_OUT(f_reset_rsps$D_OUT), .FULL_N(f_reset_rsps$FULL_N), .EMPTY_N(f_reset_rsps$EMPTY_N)); // submodule fabric_2x3 mkFabric_2x3 fabric_2x3(.CLK(CLK), .RST_N(RST_N), .set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity), .v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr), .v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst), .v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache), .v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid), .v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen), .v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock), .v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot), .v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos), .v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion), .v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize), .v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid), .v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr), .v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst), .v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache), .v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid), .v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen), .v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock), .v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot), .v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos), .v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion), .v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize), .v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid), .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), .v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr), .v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst), .v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache), .v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid), .v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen), .v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock), .v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot), .v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos), .v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion), .v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize), .v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid), .v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr), .v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst), .v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache), .v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid), .v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen), .v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock), .v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot), .v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos), .v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion), .v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize), .v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid), .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), .v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready), .v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready), .v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid), .v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp), .v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid), .v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata), .v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid), .v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast), .v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp), .v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid), .v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready), .v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready), .v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready), .v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid), .v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp), .v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid), .v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata), .v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid), .v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast), .v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp), .v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid), .v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready), .v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready), .v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready), .v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid), .v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp), .v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid), .v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata), .v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid), .v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast), .v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp), .v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid), .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), .EN_reset(fabric_2x3$EN_reset), .EN_set_verbosity(fabric_2x3$EN_set_verbosity), .RDY_reset(fabric_2x3$RDY_reset), .RDY_set_verbosity(), .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), .v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid), .v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid), .v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp), .v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready), .v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid), .v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid), .v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata), .v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp), .v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast), .v_from_masters_1_awready(), .v_from_masters_1_wready(), .v_from_masters_1_bvalid(), .v_from_masters_1_bid(), .v_from_masters_1_bresp(), .v_from_masters_1_arready(), .v_from_masters_1_rvalid(), .v_from_masters_1_rid(), .v_from_masters_1_rdata(), .v_from_masters_1_rresp(), .v_from_masters_1_rlast(), .v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid), .v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid), .v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr), .v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen), .v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize), .v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst), .v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock), .v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache), .v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot), .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), .v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready), .v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid), .v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid), .v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr), .v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen), .v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize), .v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst), .v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock), .v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache), .v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot), .v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos), .v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion), .v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready), .v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid), .v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid), .v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr), .v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen), .v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize), .v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst), .v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock), .v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache), .v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot), .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), .v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready), .v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid), .v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid), .v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr), .v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen), .v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize), .v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst), .v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock), .v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache), .v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot), .v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos), .v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion), .v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready), .v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid), .v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid), .v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr), .v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen), .v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize), .v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst), .v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock), .v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache), .v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot), .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), .v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready), .v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid), .v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid), .v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr), .v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen), .v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize), .v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst), .v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock), .v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache), .v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot), .v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos), .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); // submodule near_mem_io mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK), .RST_N(RST_N), .axi4_slave_araddr(near_mem_io$axi4_slave_araddr), .axi4_slave_arburst(near_mem_io$axi4_slave_arburst), .axi4_slave_arcache(near_mem_io$axi4_slave_arcache), .axi4_slave_arid(near_mem_io$axi4_slave_arid), .axi4_slave_arlen(near_mem_io$axi4_slave_arlen), .axi4_slave_arlock(near_mem_io$axi4_slave_arlock), .axi4_slave_arprot(near_mem_io$axi4_slave_arprot), .axi4_slave_arqos(near_mem_io$axi4_slave_arqos), .axi4_slave_arregion(near_mem_io$axi4_slave_arregion), .axi4_slave_arsize(near_mem_io$axi4_slave_arsize), .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), .axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr), .axi4_slave_awburst(near_mem_io$axi4_slave_awburst), .axi4_slave_awcache(near_mem_io$axi4_slave_awcache), .axi4_slave_awid(near_mem_io$axi4_slave_awid), .axi4_slave_awlen(near_mem_io$axi4_slave_awlen), .axi4_slave_awlock(near_mem_io$axi4_slave_awlock), .axi4_slave_awprot(near_mem_io$axi4_slave_awprot), .axi4_slave_awqos(near_mem_io$axi4_slave_awqos), .axi4_slave_awregion(near_mem_io$axi4_slave_awregion), .axi4_slave_awsize(near_mem_io$axi4_slave_awsize), .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), .axi4_slave_bready(near_mem_io$axi4_slave_bready), .axi4_slave_rready(near_mem_io$axi4_slave_rready), .axi4_slave_wdata(near_mem_io$axi4_slave_wdata), .axi4_slave_wlast(near_mem_io$axi4_slave_wlast), .axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb), .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), .set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base), .set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim), .EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put), .EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get), .EN_set_addr_map(near_mem_io$EN_set_addr_map), .EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get), .EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get), .RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put), .RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get), .RDY_set_addr_map(), .axi4_slave_awready(near_mem_io$axi4_slave_awready), .axi4_slave_wready(near_mem_io$axi4_slave_wready), .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), .axi4_slave_bid(near_mem_io$axi4_slave_bid), .axi4_slave_bresp(near_mem_io$axi4_slave_bresp), .axi4_slave_arready(near_mem_io$axi4_slave_arready), .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), .axi4_slave_rid(near_mem_io$axi4_slave_rid), .axi4_slave_rdata(near_mem_io$axi4_slave_rdata), .axi4_slave_rresp(near_mem_io$axi4_slave_rresp), .axi4_slave_rlast(near_mem_io$axi4_slave_rlast), .get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get), .RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get), .get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get), .RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get)); // submodule plic mkPLIC_16_2_7 plic(.CLK(CLK), .RST_N(RST_N), .axi4_slave_araddr(plic$axi4_slave_araddr), .axi4_slave_arburst(plic$axi4_slave_arburst), .axi4_slave_arcache(plic$axi4_slave_arcache), .axi4_slave_arid(plic$axi4_slave_arid), .axi4_slave_arlen(plic$axi4_slave_arlen), .axi4_slave_arlock(plic$axi4_slave_arlock), .axi4_slave_arprot(plic$axi4_slave_arprot), .axi4_slave_arqos(plic$axi4_slave_arqos), .axi4_slave_arregion(plic$axi4_slave_arregion), .axi4_slave_arsize(plic$axi4_slave_arsize), .axi4_slave_arvalid(plic$axi4_slave_arvalid), .axi4_slave_awaddr(plic$axi4_slave_awaddr), .axi4_slave_awburst(plic$axi4_slave_awburst), .axi4_slave_awcache(plic$axi4_slave_awcache), .axi4_slave_awid(plic$axi4_slave_awid), .axi4_slave_awlen(plic$axi4_slave_awlen), .axi4_slave_awlock(plic$axi4_slave_awlock), .axi4_slave_awprot(plic$axi4_slave_awprot), .axi4_slave_awqos(plic$axi4_slave_awqos), .axi4_slave_awregion(plic$axi4_slave_awregion), .axi4_slave_awsize(plic$axi4_slave_awsize), .axi4_slave_awvalid(plic$axi4_slave_awvalid), .axi4_slave_bready(plic$axi4_slave_bready), .axi4_slave_rready(plic$axi4_slave_rready), .axi4_slave_wdata(plic$axi4_slave_wdata), .axi4_slave_wlast(plic$axi4_slave_wlast), .axi4_slave_wstrb(plic$axi4_slave_wstrb), .axi4_slave_wvalid(plic$axi4_slave_wvalid), .set_addr_map_addr_base(plic$set_addr_map_addr_base), .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), .set_verbosity_verbosity(plic$set_verbosity_verbosity), .v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear), .v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear), .v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear), .v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear), .v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear), .v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear), .v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear), .v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear), .v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear), .v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear), .v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear), .v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear), .v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear), .v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear), .v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear), .v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear), .EN_set_verbosity(plic$EN_set_verbosity), .EN_show_PLIC_state(plic$EN_show_PLIC_state), .EN_server_reset_request_put(plic$EN_server_reset_request_put), .EN_server_reset_response_get(plic$EN_server_reset_response_get), .EN_set_addr_map(plic$EN_set_addr_map), .RDY_set_verbosity(), .RDY_show_PLIC_state(), .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), .RDY_set_addr_map(), .axi4_slave_awready(plic$axi4_slave_awready), .axi4_slave_wready(plic$axi4_slave_wready), .axi4_slave_bvalid(plic$axi4_slave_bvalid), .axi4_slave_bid(plic$axi4_slave_bid), .axi4_slave_bresp(plic$axi4_slave_bresp), .axi4_slave_arready(plic$axi4_slave_arready), .axi4_slave_rvalid(plic$axi4_slave_rvalid), .axi4_slave_rid(plic$axi4_slave_rid), .axi4_slave_rdata(plic$axi4_slave_rdata), .axi4_slave_rresp(plic$axi4_slave_rresp), .axi4_slave_rlast(plic$axi4_slave_rlast), .v_targets_0_m_eip(plic$v_targets_0_m_eip), .v_targets_1_m_eip(plic$v_targets_1_m_eip)); // submodule soc_map mkSoC_Map soc_map(.CLK(CLK), .RST_N(RST_N), .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), .m_near_mem_io_addr_size(), .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), .m_plic_addr_base(soc_map$m_plic_addr_base), .m_plic_addr_size(), .m_plic_addr_lim(soc_map$m_plic_addr_lim), .m_uart0_addr_base(), .m_uart0_addr_size(), .m_uart0_addr_lim(), .m_boot_rom_addr_base(), .m_boot_rom_addr_size(), .m_boot_rom_addr_lim(), .m_mem0_controller_addr_base(), .m_mem0_controller_addr_size(), .m_mem0_controller_addr_lim(), .m_tcm_addr_base(), .m_tcm_addr_size(), .m_tcm_addr_lim(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), .m_pc_reset_value(), .m_mtvec_reset_value(), .m_nmivec_reset_value()); // rule RL_rl_wr_addr_channel assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; // rule RL_rl_wr_data_channel assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; // rule RL_rl_wr_response_channel assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; // rule RL_rl_rd_addr_channel assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; // rule RL_rl_rd_data_channel assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; // rule RL_rl_wr_addr_channel_1 assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; // rule RL_rl_wr_data_channel_1 assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; // rule RL_rl_wr_response_channel_1 assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; // rule RL_rl_rd_addr_channel_1 assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; // rule RL_rl_rd_data_channel_1 assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; // rule RL_rl_wr_addr_channel_2 assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; // rule RL_rl_wr_data_channel_2 assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; // rule RL_rl_wr_response_channel_2 assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; // rule RL_rl_rd_addr_channel_2 assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; // rule RL_rl_rd_data_channel_2 assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; // rule RL_rl_wr_addr_channel_3 assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; // rule RL_rl_wr_data_channel_3 assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; // rule RL_rl_wr_response_channel_3 assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; // rule RL_rl_rd_addr_channel_3 assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; // rule RL_rl_rd_data_channel_3 assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; // rule RL_rl_relay_sw_interrupts assign CAN_FIRE_RL_rl_relay_sw_interrupts = near_mem_io$RDY_get_sw_interrupt_req_get ; assign WILL_FIRE_RL_rl_relay_sw_interrupts = near_mem_io$RDY_get_sw_interrupt_req_get ; // rule RL_rl_relay_timer_interrupts assign CAN_FIRE_RL_rl_relay_timer_interrupts = near_mem_io$RDY_get_timer_interrupt_req_get ; assign WILL_FIRE_RL_rl_relay_timer_interrupts = near_mem_io$RDY_get_timer_interrupt_req_get ; // rule RL_rl_relay_external_interrupts assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; // rule RL_rl_cpu_hart0_reset_from_soc_start assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = near_mem_io$RDY_server_reset_request_put && plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; // rule RL_rl_cpu_hart0_reset_complete assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = near_mem_io$RDY_server_reset_response_get && plic$RDY_server_reset_response_get && cpu$RDY_hart0_server_reset_response_get && f_reset_rsps$FULL_N ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; // submodule cpu assign cpu$dma_server_araddr = dma_server_araddr ; assign cpu$dma_server_arburst = dma_server_arburst ; assign cpu$dma_server_arcache = dma_server_arcache ; assign cpu$dma_server_arid = dma_server_arid ; assign cpu$dma_server_arlen = dma_server_arlen ; assign cpu$dma_server_arlock = dma_server_arlock ; assign cpu$dma_server_arprot = dma_server_arprot ; assign cpu$dma_server_arqos = dma_server_arqos ; assign cpu$dma_server_arregion = dma_server_arregion ; assign cpu$dma_server_arsize = dma_server_arsize ; assign cpu$dma_server_arvalid = dma_server_arvalid ; assign cpu$dma_server_awaddr = dma_server_awaddr ; assign cpu$dma_server_awburst = dma_server_awburst ; assign cpu$dma_server_awcache = dma_server_awcache ; assign cpu$dma_server_awid = dma_server_awid ; assign cpu$dma_server_awlen = dma_server_awlen ; assign cpu$dma_server_awlock = dma_server_awlock ; assign cpu$dma_server_awprot = dma_server_awprot ; assign cpu$dma_server_awqos = dma_server_awqos ; assign cpu$dma_server_awregion = dma_server_awregion ; assign cpu$dma_server_awsize = dma_server_awsize ; assign cpu$dma_server_awvalid = dma_server_awvalid ; assign cpu$dma_server_bready = dma_server_bready ; assign cpu$dma_server_rready = dma_server_rready ; assign cpu$dma_server_wdata = dma_server_wdata ; assign cpu$dma_server_wlast = dma_server_wlast ; assign cpu$dma_server_wstrb = dma_server_wstrb ; assign cpu$dma_server_wvalid = dma_server_wvalid ; assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ; assign cpu$imem_master_arready = cpu_imem_master_arready ; assign cpu$imem_master_awready = cpu_imem_master_awready ; assign cpu$imem_master_bid = cpu_imem_master_bid ; assign cpu$imem_master_bresp = cpu_imem_master_bresp ; assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; assign cpu$imem_master_rdata = cpu_imem_master_rdata ; assign cpu$imem_master_rid = cpu_imem_master_rid ; assign cpu$imem_master_rlast = cpu_imem_master_rlast ; assign cpu$imem_master_rresp = cpu_imem_master_rresp ; assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; assign cpu$imem_master_wready = cpu_imem_master_wready ; assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; assign cpu$mem_master_arready = fabric_2x3$v_from_masters_0_arready ; assign cpu$mem_master_awready = fabric_2x3$v_from_masters_0_awready ; assign cpu$mem_master_bid = fabric_2x3$v_from_masters_0_bid ; assign cpu$mem_master_bresp = fabric_2x3$v_from_masters_0_bresp ; assign cpu$mem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ; assign cpu$mem_master_rdata = fabric_2x3$v_from_masters_0_rdata ; assign cpu$mem_master_rid = fabric_2x3$v_from_masters_0_rid ; assign cpu$mem_master_rlast = fabric_2x3$v_from_masters_0_rlast ; assign cpu$mem_master_rresp = fabric_2x3$v_from_masters_0_rresp ; assign cpu$mem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ; assign cpu$mem_master_wready = fabric_2x3$v_from_masters_0_wready ; assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; assign cpu$set_watch_tohost_tohost_addr = set_watch_tohost_tohost_addr ; assign cpu$set_watch_tohost_watch_tohost = set_watch_tohost_watch_tohost ; assign cpu$software_interrupt_req_set_not_clear = near_mem_io$get_sw_interrupt_req_get ; assign cpu$timer_interrupt_req_set_not_clear = near_mem_io$get_timer_interrupt_req_get ; assign cpu$EN_hart0_server_reset_request_put = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; assign cpu$EN_hart0_server_reset_response_get = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; assign cpu$EN_set_verbosity = EN_set_verbosity ; assign cpu$EN_set_watch_tohost = EN_set_watch_tohost ; assign cpu$EN_ma_ddr4_ready = EN_ma_ddr4_ready ; // submodule f_reset_reqs assign f_reset_reqs$D_IN = cpu_reset_server_request_put ; assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; assign f_reset_reqs$DEQ = near_mem_io$RDY_server_reset_request_put && plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_rsps assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ; assign f_reset_rsps$ENQ = near_mem_io$RDY_server_reset_response_get && plic$RDY_server_reset_response_get && cpu$RDY_hart0_server_reset_response_get && f_reset_rsps$FULL_N ; assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; assign f_reset_rsps$CLR = 1'b0 ; // submodule fabric_2x3 assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; assign fabric_2x3$v_from_masters_0_araddr = cpu$mem_master_araddr ; assign fabric_2x3$v_from_masters_0_arburst = cpu$mem_master_arburst ; assign fabric_2x3$v_from_masters_0_arcache = cpu$mem_master_arcache ; assign fabric_2x3$v_from_masters_0_arid = cpu$mem_master_arid ; assign fabric_2x3$v_from_masters_0_arlen = cpu$mem_master_arlen ; assign fabric_2x3$v_from_masters_0_arlock = cpu$mem_master_arlock ; assign fabric_2x3$v_from_masters_0_arprot = cpu$mem_master_arprot ; assign fabric_2x3$v_from_masters_0_arqos = cpu$mem_master_arqos ; assign fabric_2x3$v_from_masters_0_arregion = cpu$mem_master_arregion ; assign fabric_2x3$v_from_masters_0_arsize = cpu$mem_master_arsize ; assign fabric_2x3$v_from_masters_0_arvalid = cpu$mem_master_arvalid ; assign fabric_2x3$v_from_masters_0_awaddr = cpu$mem_master_awaddr ; assign fabric_2x3$v_from_masters_0_awburst = cpu$mem_master_awburst ; assign fabric_2x3$v_from_masters_0_awcache = cpu$mem_master_awcache ; assign fabric_2x3$v_from_masters_0_awid = cpu$mem_master_awid ; assign fabric_2x3$v_from_masters_0_awlen = cpu$mem_master_awlen ; assign fabric_2x3$v_from_masters_0_awlock = cpu$mem_master_awlock ; assign fabric_2x3$v_from_masters_0_awprot = cpu$mem_master_awprot ; assign fabric_2x3$v_from_masters_0_awqos = cpu$mem_master_awqos ; assign fabric_2x3$v_from_masters_0_awregion = cpu$mem_master_awregion ; assign fabric_2x3$v_from_masters_0_awsize = cpu$mem_master_awsize ; assign fabric_2x3$v_from_masters_0_awvalid = cpu$mem_master_awvalid ; assign fabric_2x3$v_from_masters_0_bready = cpu$mem_master_bready ; assign fabric_2x3$v_from_masters_0_rready = cpu$mem_master_rready ; assign fabric_2x3$v_from_masters_0_wdata = cpu$mem_master_wdata ; assign fabric_2x3$v_from_masters_0_wlast = cpu$mem_master_wlast ; assign fabric_2x3$v_from_masters_0_wstrb = cpu$mem_master_wstrb ; assign fabric_2x3$v_from_masters_0_wvalid = cpu$mem_master_wvalid ; assign fabric_2x3$v_from_masters_1_araddr = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arburst = 2'b10 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arcache = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arlen = 8'b10101010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arprot = 3'b010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arqos = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arregion = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arsize = 3'b010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ; assign fabric_2x3$v_from_masters_1_awaddr = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awburst = 2'b10 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awcache = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awlen = 8'b10101010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awprot = 3'b010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awqos = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awregion = 4'b1010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awsize = 3'b010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ; assign fabric_2x3$v_from_masters_1_bready = 1'd0 ; assign fabric_2x3$v_from_masters_1_rready = 1'd0 ; assign fabric_2x3$v_from_masters_1_wdata = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_wstrb = 8'b10101010 /* unspecified value */ ; assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ; assign fabric_2x3$v_to_slaves_0_arready = core_mem_master_arready ; assign fabric_2x3$v_to_slaves_0_awready = core_mem_master_awready ; assign fabric_2x3$v_to_slaves_0_bid = core_mem_master_bid ; assign fabric_2x3$v_to_slaves_0_bresp = core_mem_master_bresp ; assign fabric_2x3$v_to_slaves_0_bvalid = core_mem_master_bvalid ; assign fabric_2x3$v_to_slaves_0_rdata = core_mem_master_rdata ; assign fabric_2x3$v_to_slaves_0_rid = core_mem_master_rid ; assign fabric_2x3$v_to_slaves_0_rlast = core_mem_master_rlast ; assign fabric_2x3$v_to_slaves_0_rresp = core_mem_master_rresp ; assign fabric_2x3$v_to_slaves_0_rvalid = core_mem_master_rvalid ; assign fabric_2x3$v_to_slaves_0_wready = core_mem_master_wready ; assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ; assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ; assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ; assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ; assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ; assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ; assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ; assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ; assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ; assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ; assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ; assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ; assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ; assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ; assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ; assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ; assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ; assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ; assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ; assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ; assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ; assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ; assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; assign fabric_2x3$EN_set_verbosity = 1'b0 ; // submodule near_mem_io assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ; assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ; assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ; assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ; assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ; assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ; assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ; assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ; assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ; assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ; assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ; assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ; assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ; assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ; assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ; assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ; assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ; assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ; assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ; assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ; assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ; assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ; assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; assign near_mem_io$set_addr_map_addr_base = soc_map$m_near_mem_io_addr_base ; assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ; assign near_mem_io$EN_server_reset_request_put = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; assign near_mem_io$EN_server_reset_response_get = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; assign near_mem_io$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; assign near_mem_io$EN_get_timer_interrupt_req_get = near_mem_io$RDY_get_timer_interrupt_req_get ; assign near_mem_io$EN_get_sw_interrupt_req_get = near_mem_io$RDY_get_sw_interrupt_req_get ; // submodule plic assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ; assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ; assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ; assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ; assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ; assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ; assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ; assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ; assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ; assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ; assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ; assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ; assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ; assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ; assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ; assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ; assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ; assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ; assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ; assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ; assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ; assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ; assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ; assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ; assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ; assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ; assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ; assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ; assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ; assign plic$set_verbosity_verbosity = 4'h0 ; assign plic$v_sources_0_m_interrupt_req_set_not_clear = core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; assign plic$v_sources_10_m_interrupt_req_set_not_clear = core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ; assign plic$v_sources_11_m_interrupt_req_set_not_clear = core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ; assign plic$v_sources_12_m_interrupt_req_set_not_clear = core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ; assign plic$v_sources_13_m_interrupt_req_set_not_clear = core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ; assign plic$v_sources_14_m_interrupt_req_set_not_clear = core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ; assign plic$v_sources_15_m_interrupt_req_set_not_clear = core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ; assign plic$v_sources_1_m_interrupt_req_set_not_clear = core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ; assign plic$v_sources_2_m_interrupt_req_set_not_clear = core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ; assign plic$v_sources_3_m_interrupt_req_set_not_clear = core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ; assign plic$v_sources_4_m_interrupt_req_set_not_clear = core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ; assign plic$v_sources_5_m_interrupt_req_set_not_clear = core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ; assign plic$v_sources_6_m_interrupt_req_set_not_clear = core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ; assign plic$v_sources_7_m_interrupt_req_set_not_clear = core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ; assign plic$v_sources_8_m_interrupt_req_set_not_clear = core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ; assign plic$v_sources_9_m_interrupt_req_set_not_clear = core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; assign plic$EN_set_verbosity = 1'b0 ; assign plic$EN_show_PLIC_state = 1'b0 ; assign plic$EN_server_reset_request_put = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; assign plic$EN_server_reset_response_get = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 = plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && cpu$RDY_hart0_server_reset_request_put && f_reset_reqs$EMPTY_N ; // handling of system tasks // synopsys translate_off always@(negedge CLK) begin #0; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) begin v__h4601 = $stime; #0; end v__h4595 = v__h4601 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4595); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) begin v__h4817 = $stime; #0; end v__h4811 = v__h4817 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4811); end // synopsys translate_on endmodule // mkCore

/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ // > c60k28 (Viacheslav, VT) [at] yandex [dot] com // > Achronix eFPGA technology mapping. User must first simulate the generated \ // > netlist before going to test it on board/custom chip. // > Input/Output buffers < // Input buffer map module \$__inpad (input I, output O); PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I)); endmodule // Output buffer map module \$__outpad (input I, output O); PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1)); endmodule // > end buffers < // > Look-Up table < // > VT: I still think Achronix folks would have chosen a better \ // > logic architecture. // LUT Map module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; (* force_downto *) input [WIDTH-1:0] A; output Y; generate if (WIDTH == 1) begin // VT: This is not consistent and ACE will complain: assign Y = ~A[0]; LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0)); end else if (WIDTH == 2) begin LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0)); end else if(WIDTH == 3) begin LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0)); end else if(WIDTH == 4) begin LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3])); end else wire _TECHMAP_FAIL_ = 1; endgenerate endmodule // > end LUT < // > Flops < // DFF flop module \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.q(Q), .d(D), .ck(C)); endmodule

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HS__SDFSTP_FUNCTIONAL_PP_V `define SKY130_FD_SC_HS__SDFSTP_FUNCTIONAL_PP_V /** * sdfstp: Scan delay flop, inverted set, non-inverted clock, * single output. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import sub cells. `include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v" `include "../u_df_p_s_pg/sky130_fd_sc_hs__u_df_p_s_pg.v" `celldefine module sky130_fd_sc_hs__sdfstp ( VPWR , VGND , Q , CLK , D , SCD , SCE , SET_B ); // Module ports input VPWR ; input VGND ; output Q ; input CLK ; input D ; input SCD ; input SCE ; input SET_B; // Local signals wire buf_Q ; wire SET ; wire mux_out; // Delay Name Output Other arguments not not0 (SET , SET_B ); sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE ); sky130_fd_sc_hs__u_df_p_s_pg `UNIT_DELAY u_df_p_s_pg0 (buf_Q , mux_out, CLK, SET, VPWR, VGND); buf buf0 (Q , buf_Q ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HS__SDFSTP_FUNCTIONAL_PP_V

/* * These source files contain a hardware description of a network * automatically generated by CONNECT (CONfigurable NEtwork Creation Tool). * * This product includes a hardware design developed by Carnegie Mellon * University. * * Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University * * For more information, see the CONNECT project website at: * http://www.ece.cmu.edu/~mpapamic/connect * * This design is provided for internal, non-commercial research use only, * cannot be used for, or in support of, goods or services, and is not for * redistribution, with or without modifications. * * You may not use the name "Carnegie Mellon University" or derivations * thereof to endorse or promote products derived from this software. * * THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER * EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY * THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, * TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY * BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT, * SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN * ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY, * CONTRACT, TORT OR OTHERWISE). * */ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // // On Sat Feb 11 18:26:51 EST 2017 // // Method conflict info: // Method: enq // Conflict-free: deq, notEmpty, notFull // Conflicts: enq // // Method: deq // Conflict-free: enq, notEmpty, notFull // Conflicts: deq // // Method: notEmpty // Conflict-free: enq, deq, notEmpty, notFull // // Method: notFull // Conflict-free: enq, deq, notEmpty, notFull // // // Ports: // Name I/O size props // deq O 70 // notEmpty O 2 reg // notFull O 2 reg // CLK I 1 clock // RST_N I 1 reset // enq_fifo_in I 1 // enq_data_in I 70 // deq_fifo_out I 1 // EN_enq I 1 // EN_deq I 1 // // No combinational paths from inputs to outputs // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif module mkInputVCQueues(CLK, RST_N, enq_fifo_in, enq_data_in, EN_enq, deq_fifo_out, EN_deq, deq, notEmpty, notFull); input CLK; input RST_N; // action method enq input enq_fifo_in; input [69 : 0] enq_data_in; input EN_enq; // actionvalue method deq input deq_fifo_out; input EN_deq; output [69 : 0] deq; // value method notEmpty output [1 : 0] notEmpty; // value method notFull output [1 : 0] notFull; // signals for module outputs wire [69 : 0] deq; wire [1 : 0] notEmpty, notFull; // inlined wires wire [2 : 0] inputVCQueues_ifc_mf_ifc_new_head$wget, inputVCQueues_ifc_mf_ifc_new_tail$wget; wire [1 : 0] inputVCQueues_ifc_mf_ifc_rdFIFO$wget, inputVCQueues_ifc_mf_ifc_wrFIFO$wget; // register inputVCQueues_ifc_mf_ifc_heads reg [2 : 0] inputVCQueues_ifc_mf_ifc_heads; wire [2 : 0] inputVCQueues_ifc_mf_ifc_heads$D_IN; wire inputVCQueues_ifc_mf_ifc_heads$EN; // register inputVCQueues_ifc_mf_ifc_heads_1 reg [2 : 0] inputVCQueues_ifc_mf_ifc_heads_1; wire [2 : 0] inputVCQueues_ifc_mf_ifc_heads_1$D_IN; wire inputVCQueues_ifc_mf_ifc_heads_1$EN; // register inputVCQueues_ifc_mf_ifc_not_empty reg inputVCQueues_ifc_mf_ifc_not_empty; wire inputVCQueues_ifc_mf_ifc_not_empty$D_IN, inputVCQueues_ifc_mf_ifc_not_empty$EN; // register inputVCQueues_ifc_mf_ifc_not_empty_1 reg inputVCQueues_ifc_mf_ifc_not_empty_1; wire inputVCQueues_ifc_mf_ifc_not_empty_1$D_IN, inputVCQueues_ifc_mf_ifc_not_empty_1$EN; // register inputVCQueues_ifc_mf_ifc_not_full reg inputVCQueues_ifc_mf_ifc_not_full; wire inputVCQueues_ifc_mf_ifc_not_full$D_IN, inputVCQueues_ifc_mf_ifc_not_full$EN; // register inputVCQueues_ifc_mf_ifc_not_full_1 reg inputVCQueues_ifc_mf_ifc_not_full_1; wire inputVCQueues_ifc_mf_ifc_not_full_1$D_IN, inputVCQueues_ifc_mf_ifc_not_full_1$EN; // register inputVCQueues_ifc_mf_ifc_tails reg [2 : 0] inputVCQueues_ifc_mf_ifc_tails; wire [2 : 0] inputVCQueues_ifc_mf_ifc_tails$D_IN; wire inputVCQueues_ifc_mf_ifc_tails$EN; // register inputVCQueues_ifc_mf_ifc_tails_1 reg [2 : 0] inputVCQueues_ifc_mf_ifc_tails_1; wire [2 : 0] inputVCQueues_ifc_mf_ifc_tails_1$D_IN; wire inputVCQueues_ifc_mf_ifc_tails_1$EN; // ports of submodule inputVCQueues_ifc_mf_ifc_fifoMem wire [69 : 0] inputVCQueues_ifc_mf_ifc_fifoMem$D_IN, inputVCQueues_ifc_mf_ifc_fifoMem$D_OUT; wire [3 : 0] inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_IN, inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_OUT; wire inputVCQueues_ifc_mf_ifc_fifoMem$WE; // remaining internal signals wire [2 : 0] fifoRdPtr__h4019, fifoWrPtr__h3549, x__h2444, x__h3036, y__h2445, y__h3037; wire IF_deq_fifo_out_THEN_NOT_inputVCQueues_ifc_mf__ETC___d89, IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88, IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58, IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36, NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d38, NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d41, NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d43, NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d60, NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d63, NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d65, inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d52, inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d54, inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d30, inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d32; // actionvalue method deq assign deq = inputVCQueues_ifc_mf_ifc_fifoMem$D_OUT ; // value method notEmpty assign notEmpty = { inputVCQueues_ifc_mf_ifc_not_empty_1, inputVCQueues_ifc_mf_ifc_not_empty } ; // value method notFull assign notFull = { inputVCQueues_ifc_mf_ifc_not_full_1, inputVCQueues_ifc_mf_ifc_not_full } ; // submodule inputVCQueues_ifc_mf_ifc_fifoMem RegFile_1port #( /*data_width*/ 32'd70, /*addr_width*/ 32'd4) inputVCQueues_ifc_mf_ifc_fifoMem(.CLK(CLK), .rst_n(RST_N), .ADDR_IN(inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_IN), .ADDR_OUT(inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_OUT), .D_IN(inputVCQueues_ifc_mf_ifc_fifoMem$D_IN), .WE(inputVCQueues_ifc_mf_ifc_fifoMem$WE), .D_OUT(inputVCQueues_ifc_mf_ifc_fifoMem$D_OUT)); // inlined wires assign inputVCQueues_ifc_mf_ifc_wrFIFO$wget = { 1'd1, enq_fifo_in } ; assign inputVCQueues_ifc_mf_ifc_rdFIFO$wget = { 1'd1, deq_fifo_out } ; assign inputVCQueues_ifc_mf_ifc_new_tail$wget = fifoWrPtr__h3549 + 3'd1 ; assign inputVCQueues_ifc_mf_ifc_new_head$wget = fifoRdPtr__h4019 + 3'd1 ; // register inputVCQueues_ifc_mf_ifc_heads assign inputVCQueues_ifc_mf_ifc_heads$D_IN = x__h3036 ; assign inputVCQueues_ifc_mf_ifc_heads$EN = EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] && !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ; // register inputVCQueues_ifc_mf_ifc_heads_1 assign inputVCQueues_ifc_mf_ifc_heads_1$D_IN = x__h3036 ; assign inputVCQueues_ifc_mf_ifc_heads_1$EN = EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ; // register inputVCQueues_ifc_mf_ifc_not_empty assign inputVCQueues_ifc_mf_ifc_not_empty$D_IN = inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d32 ; assign inputVCQueues_ifc_mf_ifc_not_empty$EN = inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d32 || EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] && NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d63 ; // register inputVCQueues_ifc_mf_ifc_not_empty_1 assign inputVCQueues_ifc_mf_ifc_not_empty_1$D_IN = inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d30 ; assign inputVCQueues_ifc_mf_ifc_not_empty_1$EN = inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d30 || EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] && NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d60 ; // register inputVCQueues_ifc_mf_ifc_not_full assign inputVCQueues_ifc_mf_ifc_not_full$D_IN = !EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] || !NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d41 ; assign inputVCQueues_ifc_mf_ifc_not_full$EN = EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] && NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d41 || inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d54 ; // register inputVCQueues_ifc_mf_ifc_not_full_1 assign inputVCQueues_ifc_mf_ifc_not_full_1$D_IN = !EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] || !NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d38 ; assign inputVCQueues_ifc_mf_ifc_not_full_1$EN = EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] && NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d38 || inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d52 ; // register inputVCQueues_ifc_mf_ifc_tails assign inputVCQueues_ifc_mf_ifc_tails$D_IN = x__h2444 ; assign inputVCQueues_ifc_mf_ifc_tails$EN = EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] && !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ; // register inputVCQueues_ifc_mf_ifc_tails_1 assign inputVCQueues_ifc_mf_ifc_tails_1$D_IN = x__h2444 ; assign inputVCQueues_ifc_mf_ifc_tails_1$EN = EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ; // submodule inputVCQueues_ifc_mf_ifc_fifoMem assign inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_IN = { enq_fifo_in, fifoWrPtr__h3549 } ; assign inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_OUT = { deq_fifo_out, fifoRdPtr__h4019 } ; assign inputVCQueues_ifc_mf_ifc_fifoMem$D_IN = enq_data_in ; assign inputVCQueues_ifc_mf_ifc_fifoMem$WE = EN_enq ; // remaining internal signals assign IF_deq_fifo_out_THEN_NOT_inputVCQueues_ifc_mf__ETC___d89 = deq_fifo_out ? !inputVCQueues_ifc_mf_ifc_not_empty_1 : !inputVCQueues_ifc_mf_ifc_not_empty ; assign IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88 = enq_fifo_in ? !inputVCQueues_ifc_mf_ifc_not_full_1 : !inputVCQueues_ifc_mf_ifc_not_full ; assign IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58 = x__h3036 == y__h3037 ; assign IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36 = x__h2444 == y__h2445 ; assign NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d38 = (!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] || inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] != inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) && IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36 && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ; assign NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d41 = (!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] || inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] != inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) && IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36 && !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ; assign NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d43 = (!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] || inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] != inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) && IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36 ; assign NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d60 = (!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] || inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] != inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) && IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58 && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ; assign NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d63 = (!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] || inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] != inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) && IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58 && !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ; assign NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d65 = (!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] || inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] != inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) && IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58 ; assign fifoRdPtr__h4019 = deq_fifo_out ? inputVCQueues_ifc_mf_ifc_heads_1 : inputVCQueues_ifc_mf_ifc_heads ; assign fifoWrPtr__h3549 = enq_fifo_in ? inputVCQueues_ifc_mf_ifc_tails_1 : inputVCQueues_ifc_mf_ifc_tails ; assign inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d52 = EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] && (!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] || inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] != inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ; assign inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d54 = EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] && (!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] || inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] != inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) && !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ; assign inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d30 = EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] && (!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] || inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] != inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ; assign inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d32 = EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] && (!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] || inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] != inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) && !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ; assign x__h2444 = EN_enq ? inputVCQueues_ifc_mf_ifc_new_tail$wget : 3'd0 ; assign x__h3036 = EN_deq ? inputVCQueues_ifc_mf_ifc_new_head$wget : 3'd0 ; assign y__h2445 = inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ? inputVCQueues_ifc_mf_ifc_heads_1 : inputVCQueues_ifc_mf_ifc_heads ; assign y__h3037 = inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ? inputVCQueues_ifc_mf_ifc_tails_1 : inputVCQueues_ifc_mf_ifc_tails ; // handling of inlined registers always@(posedge CLK) begin if (!RST_N) begin inputVCQueues_ifc_mf_ifc_heads <= `BSV_ASSIGNMENT_DELAY 3'd0; inputVCQueues_ifc_mf_ifc_heads_1 <= `BSV_ASSIGNMENT_DELAY 3'd0; inputVCQueues_ifc_mf_ifc_not_empty <= `BSV_ASSIGNMENT_DELAY 1'd0; inputVCQueues_ifc_mf_ifc_not_empty_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; inputVCQueues_ifc_mf_ifc_not_full <= `BSV_ASSIGNMENT_DELAY 1'd1; inputVCQueues_ifc_mf_ifc_not_full_1 <= `BSV_ASSIGNMENT_DELAY 1'd1; inputVCQueues_ifc_mf_ifc_tails <= `BSV_ASSIGNMENT_DELAY 3'd0; inputVCQueues_ifc_mf_ifc_tails_1 <= `BSV_ASSIGNMENT_DELAY 3'd0; end else begin if (inputVCQueues_ifc_mf_ifc_heads$EN) inputVCQueues_ifc_mf_ifc_heads <= `BSV_ASSIGNMENT_DELAY inputVCQueues_ifc_mf_ifc_heads$D_IN; if (inputVCQueues_ifc_mf_ifc_heads_1$EN) inputVCQueues_ifc_mf_ifc_heads_1 <= `BSV_ASSIGNMENT_DELAY inputVCQueues_ifc_mf_ifc_heads_1$D_IN; if (inputVCQueues_ifc_mf_ifc_not_empty$EN) inputVCQueues_ifc_mf_ifc_not_empty <= `BSV_ASSIGNMENT_DELAY inputVCQueues_ifc_mf_ifc_not_empty$D_IN; if (inputVCQueues_ifc_mf_ifc_not_empty_1$EN) inputVCQueues_ifc_mf_ifc_not_empty_1 <= `BSV_ASSIGNMENT_DELAY inputVCQueues_ifc_mf_ifc_not_empty_1$D_IN; if (inputVCQueues_ifc_mf_ifc_not_full$EN) inputVCQueues_ifc_mf_ifc_not_full <= `BSV_ASSIGNMENT_DELAY inputVCQueues_ifc_mf_ifc_not_full$D_IN; if (inputVCQueues_ifc_mf_ifc_not_full_1$EN) inputVCQueues_ifc_mf_ifc_not_full_1 <= `BSV_ASSIGNMENT_DELAY inputVCQueues_ifc_mf_ifc_not_full_1$D_IN; if (inputVCQueues_ifc_mf_ifc_tails$EN) inputVCQueues_ifc_mf_ifc_tails <= `BSV_ASSIGNMENT_DELAY inputVCQueues_ifc_mf_ifc_tails$D_IN; if (inputVCQueues_ifc_mf_ifc_tails_1$EN) inputVCQueues_ifc_mf_ifc_tails_1 <= `BSV_ASSIGNMENT_DELAY inputVCQueues_ifc_mf_ifc_tails_1$D_IN; end end // synopsys translate_off `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS initial begin inputVCQueues_ifc_mf_ifc_heads = 3'h2; inputVCQueues_ifc_mf_ifc_heads_1 = 3'h2; inputVCQueues_ifc_mf_ifc_not_empty = 1'h0; inputVCQueues_ifc_mf_ifc_not_empty_1 = 1'h0; inputVCQueues_ifc_mf_ifc_not_full = 1'h0; inputVCQueues_ifc_mf_ifc_not_full_1 = 1'h0; inputVCQueues_ifc_mf_ifc_tails = 3'h2; inputVCQueues_ifc_mf_ifc_tails_1 = 3'h2; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on // handling of system tasks // synopsys translate_off always@(negedge CLK) begin #0; if (RST_N) if (EN_enq && IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88) $write(""); if (RST_N) if (EN_enq && IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88) $write(""); if (RST_N) if (EN_enq && IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88) $display("Dynamic assertion failed: \"MultiFIFOMem.bsv\", line 156, column 38\nEnqueing to full FIFO in MultiFIFOMem!"); if (RST_N) if (EN_enq && IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88) $finish(32'd0); if (RST_N) if (EN_enq) $write(""); if (RST_N) if (EN_deq && IF_deq_fifo_out_THEN_NOT_inputVCQueues_ifc_mf__ETC___d89) $display("Dynamic assertion failed: \"MultiFIFOMem.bsv\", line 190, column 40\nDequeing from empty FIFO in MultiFIFOMem!"); if (RST_N) if (EN_deq && IF_deq_fifo_out_THEN_NOT_inputVCQueues_ifc_mf__ETC___d89) $finish(32'd0); if (RST_N) if (EN_deq) $write(""); if (RST_N) if (EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] && NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d43) $write(""); if (RST_N) if (EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] && NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d65) $write(""); end // synopsys translate_on endmodule // mkInputVCQueues

// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 // Date : Wed Mar 01 09:52:04 2017 // Host : GILAMONSTER running 64-bit major release (build 9200) // Command : write_verilog -force -mode funcsim -rename_top system_ov7670_controller_1_0 -prefix // system_ov7670_controller_1_0_ system_ov7670_controller_0_0_sim_netlist.v // Design : system_ov7670_controller_0_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7z010clg400-1 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps module system_ov7670_controller_1_0_i2c_sender (E, sioc, p_0_in, \busy_sr_reg[1]_0 , siod, \busy_sr_reg[31]_0 , clk, p_1_in, DOADO, \busy_sr_reg[31]_1 ); output [0:0]E; output sioc; output p_0_in; output \busy_sr_reg[1]_0 ; output siod; input \busy_sr_reg[31]_0 ; input clk; input [0:0]p_1_in; input [15:0]DOADO; input [0:0]\busy_sr_reg[31]_1 ; wire [15:0]DOADO; wire [0:0]E; wire busy_sr0; wire \busy_sr[0]_i_3_n_0 ; wire \busy_sr[0]_i_5_n_0 ; wire \busy_sr[10]_i_1_n_0 ; wire \busy_sr[11]_i_1_n_0 ; wire \busy_sr[12]_i_1_n_0 ; wire \busy_sr[13]_i_1_n_0 ; wire \busy_sr[14]_i_1_n_0 ; wire \busy_sr[15]_i_1_n_0 ; wire \busy_sr[16]_i_1_n_0 ; wire \busy_sr[17]_i_1_n_0 ; wire \busy_sr[18]_i_1_n_0 ; wire \busy_sr[19]_i_1_n_0 ; wire \busy_sr[1]_i_1_n_0 ; wire \busy_sr[20]_i_1_n_0 ; wire \busy_sr[21]_i_1_n_0 ; wire \busy_sr[22]_i_1_n_0 ; wire \busy_sr[23]_i_1_n_0 ; wire \busy_sr[24]_i_1_n_0 ; wire \busy_sr[25]_i_1_n_0 ; wire \busy_sr[26]_i_1_n_0 ; wire \busy_sr[27]_i_1_n_0 ; wire \busy_sr[28]_i_1_n_0 ; wire \busy_sr[29]_i_1_n_0 ; wire \busy_sr[2]_i_1_n_0 ; wire \busy_sr[30]_i_1_n_0 ; wire \busy_sr[31]_i_1_n_0 ; wire \busy_sr[31]_i_2_n_0 ; wire \busy_sr[3]_i_1_n_0 ; wire \busy_sr[4]_i_1_n_0 ; wire \busy_sr[5]_i_1_n_0 ; wire \busy_sr[6]_i_1_n_0 ; wire \busy_sr[7]_i_1_n_0 ; wire \busy_sr[8]_i_1_n_0 ; wire \busy_sr[9]_i_1_n_0 ; wire \busy_sr_reg[1]_0 ; wire \busy_sr_reg[31]_0 ; wire [0:0]\busy_sr_reg[31]_1 ; wire \busy_sr_reg_n_0_[0] ; wire \busy_sr_reg_n_0_[10] ; wire \busy_sr_reg_n_0_[11] ; wire \busy_sr_reg_n_0_[12] ; wire \busy_sr_reg_n_0_[13] ; wire \busy_sr_reg_n_0_[14] ; wire \busy_sr_reg_n_0_[15] ; wire \busy_sr_reg_n_0_[16] ; wire \busy_sr_reg_n_0_[17] ; wire \busy_sr_reg_n_0_[18] ; wire \busy_sr_reg_n_0_[1] ; wire \busy_sr_reg_n_0_[21] ; wire \busy_sr_reg_n_0_[22] ; wire \busy_sr_reg_n_0_[23] ; wire \busy_sr_reg_n_0_[24] ; wire \busy_sr_reg_n_0_[25] ; wire \busy_sr_reg_n_0_[26] ; wire \busy_sr_reg_n_0_[27] ; wire \busy_sr_reg_n_0_[28] ; wire \busy_sr_reg_n_0_[29] ; wire \busy_sr_reg_n_0_[2] ; wire \busy_sr_reg_n_0_[30] ; wire \busy_sr_reg_n_0_[3] ; wire \busy_sr_reg_n_0_[4] ; wire \busy_sr_reg_n_0_[5] ; wire \busy_sr_reg_n_0_[6] ; wire \busy_sr_reg_n_0_[7] ; wire \busy_sr_reg_n_0_[8] ; wire \busy_sr_reg_n_0_[9] ; wire clk; wire \data_sr[10]_i_1_n_0 ; wire \data_sr[12]_i_1_n_0 ; wire \data_sr[13]_i_1_n_0 ; wire \data_sr[14]_i_1_n_0 ; wire \data_sr[15]_i_1_n_0 ; wire \data_sr[16]_i_1_n_0 ; wire \data_sr[17]_i_1_n_0 ; wire \data_sr[18]_i_1_n_0 ; wire \data_sr[19]_i_1_n_0 ; wire \data_sr[22]_i_1_n_0 ; wire \data_sr[27]_i_1_n_0 ; wire \data_sr[30]_i_1_n_0 ; wire \data_sr[31]_i_1_n_0 ; wire \data_sr[31]_i_2_n_0 ; wire \data_sr[3]_i_1_n_0 ; wire \data_sr[4]_i_1_n_0 ; wire \data_sr[5]_i_1_n_0 ; wire \data_sr[6]_i_1_n_0 ; wire \data_sr[7]_i_1_n_0 ; wire \data_sr[8]_i_1_n_0 ; wire \data_sr[9]_i_1_n_0 ; wire \data_sr_reg_n_0_[10] ; wire \data_sr_reg_n_0_[11] ; wire \data_sr_reg_n_0_[12] ; wire \data_sr_reg_n_0_[13] ; wire \data_sr_reg_n_0_[14] ; wire \data_sr_reg_n_0_[15] ; wire \data_sr_reg_n_0_[16] ; wire \data_sr_reg_n_0_[17] ; wire \data_sr_reg_n_0_[18] ; wire \data_sr_reg_n_0_[19] ; wire \data_sr_reg_n_0_[1] ; wire \data_sr_reg_n_0_[20] ; wire \data_sr_reg_n_0_[21] ; wire \data_sr_reg_n_0_[22] ; wire \data_sr_reg_n_0_[23] ; wire \data_sr_reg_n_0_[24] ; wire \data_sr_reg_n_0_[25] ; wire \data_sr_reg_n_0_[26] ; wire \data_sr_reg_n_0_[27] ; wire \data_sr_reg_n_0_[28] ; wire \data_sr_reg_n_0_[29] ; wire \data_sr_reg_n_0_[2] ; wire \data_sr_reg_n_0_[30] ; wire \data_sr_reg_n_0_[31] ; wire \data_sr_reg_n_0_[3] ; wire \data_sr_reg_n_0_[4] ; wire \data_sr_reg_n_0_[5] ; wire \data_sr_reg_n_0_[6] ; wire \data_sr_reg_n_0_[7] ; wire \data_sr_reg_n_0_[8] ; wire \data_sr_reg_n_0_[9] ; wire [7:6]divider_reg__0; wire [5:0]divider_reg__1; wire p_0_in; wire [7:0]p_0_in__0; wire [0:0]p_1_in; wire [1:0]p_1_in_0; wire sioc; wire sioc_i_1_n_0; wire sioc_i_2_n_0; wire sioc_i_3_n_0; wire sioc_i_4_n_0; wire sioc_i_5_n_0; wire siod; wire siod_INST_0_i_1_n_0; LUT6 #( .INIT(64'h4000FFFF40004000)) \busy_sr[0]_i_1 (.I0(\busy_sr[0]_i_3_n_0 ), .I1(divider_reg__0[6]), .I2(divider_reg__0[7]), .I3(p_0_in), .I4(\busy_sr_reg[1]_0 ), .I5(p_1_in), .O(busy_sr0)); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \busy_sr[0]_i_3 (.I0(divider_reg__1[4]), .I1(divider_reg__1[2]), .I2(divider_reg__1[0]), .I3(divider_reg__1[1]), .I4(divider_reg__1[3]), .I5(divider_reg__1[5]), .O(\busy_sr[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( .INIT(32'hFFFFFFFE)) \busy_sr[0]_i_4 (.I0(divider_reg__1[2]), .I1(divider_reg__1[3]), .I2(divider_reg__1[0]), .I3(divider_reg__1[1]), .I4(\busy_sr[0]_i_5_n_0 ), .O(\busy_sr_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT4 #( .INIT(16'hFFFE)) \busy_sr[0]_i_5 (.I0(divider_reg__1[5]), .I1(divider_reg__1[4]), .I2(divider_reg__0[7]), .I3(divider_reg__0[6]), .O(\busy_sr[0]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT2 #( .INIT(4'h8)) \busy_sr[10]_i_1 (.I0(\busy_sr_reg_n_0_[9] ), .I1(p_0_in), .O(\busy_sr[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT2 #( .INIT(4'h8)) \busy_sr[11]_i_1 (.I0(\busy_sr_reg_n_0_[10] ), .I1(p_0_in), .O(\busy_sr[11]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT2 #( .INIT(4'h8)) \busy_sr[12]_i_1 (.I0(\busy_sr_reg_n_0_[11] ), .I1(p_0_in), .O(\busy_sr[12]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT2 #( .INIT(4'h8)) \busy_sr[13]_i_1 (.I0(\busy_sr_reg_n_0_[12] ), .I1(p_0_in), .O(\busy_sr[13]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT2 #( .INIT(4'h8)) \busy_sr[14]_i_1 (.I0(\busy_sr_reg_n_0_[13] ), .I1(p_0_in), .O(\busy_sr[14]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT2 #( .INIT(4'h8)) \busy_sr[15]_i_1 (.I0(\busy_sr_reg_n_0_[14] ), .I1(p_0_in), .O(\busy_sr[15]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT2 #( .INIT(4'h8)) \busy_sr[16]_i_1 (.I0(\busy_sr_reg_n_0_[15] ), .I1(p_0_in), .O(\busy_sr[16]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT2 #( .INIT(4'h8)) \busy_sr[17]_i_1 (.I0(\busy_sr_reg_n_0_[16] ), .I1(p_0_in), .O(\busy_sr[17]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT2 #( .INIT(4'h8)) \busy_sr[18]_i_1 (.I0(\busy_sr_reg_n_0_[17] ), .I1(p_0_in), .O(\busy_sr[18]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT2 #( .INIT(4'h8)) \busy_sr[19]_i_1 (.I0(\busy_sr_reg_n_0_[18] ), .I1(p_0_in), .O(\busy_sr[19]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h8)) \busy_sr[1]_i_1 (.I0(\busy_sr_reg_n_0_[0] ), .I1(p_0_in), .O(\busy_sr[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT2 #( .INIT(4'h8)) \busy_sr[20]_i_1 (.I0(p_1_in_0[0]), .I1(p_0_in), .O(\busy_sr[20]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT2 #( .INIT(4'h8)) \busy_sr[21]_i_1 (.I0(p_1_in_0[1]), .I1(p_0_in), .O(\busy_sr[21]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT2 #( .INIT(4'h8)) \busy_sr[22]_i_1 (.I0(\busy_sr_reg_n_0_[21] ), .I1(p_0_in), .O(\busy_sr[22]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT2 #( .INIT(4'h8)) \busy_sr[23]_i_1 (.I0(\busy_sr_reg_n_0_[22] ), .I1(p_0_in), .O(\busy_sr[23]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT2 #( .INIT(4'h8)) \busy_sr[24]_i_1 (.I0(\busy_sr_reg_n_0_[23] ), .I1(p_0_in), .O(\busy_sr[24]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT2 #( .INIT(4'h8)) \busy_sr[25]_i_1 (.I0(\busy_sr_reg_n_0_[24] ), .I1(p_0_in), .O(\busy_sr[25]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT2 #( .INIT(4'h8)) \busy_sr[26]_i_1 (.I0(\busy_sr_reg_n_0_[25] ), .I1(p_0_in), .O(\busy_sr[26]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT2 #( .INIT(4'h8)) \busy_sr[27]_i_1 (.I0(\busy_sr_reg_n_0_[26] ), .I1(p_0_in), .O(\busy_sr[27]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT2 #( .INIT(4'h8)) \busy_sr[28]_i_1 (.I0(\busy_sr_reg_n_0_[27] ), .I1(p_0_in), .O(\busy_sr[28]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT2 #( .INIT(4'h8)) \busy_sr[29]_i_1 (.I0(\busy_sr_reg_n_0_[28] ), .I1(p_0_in), .O(\busy_sr[29]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT2 #( .INIT(4'h8)) \busy_sr[2]_i_1 (.I0(\busy_sr_reg_n_0_[1] ), .I1(p_0_in), .O(\busy_sr[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT2 #( .INIT(4'h8)) \busy_sr[30]_i_1 (.I0(\busy_sr_reg_n_0_[29] ), .I1(p_0_in), .O(\busy_sr[30]_i_1_n_0 )); LUT6 #( .INIT(64'h22222222A2222222)) \busy_sr[31]_i_1 (.I0(p_1_in), .I1(\busy_sr_reg[1]_0 ), .I2(p_0_in), .I3(divider_reg__0[7]), .I4(divider_reg__0[6]), .I5(\busy_sr[0]_i_3_n_0 ), .O(\busy_sr[31]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT2 #( .INIT(4'h8)) \busy_sr[31]_i_2 (.I0(p_0_in), .I1(\busy_sr_reg_n_0_[30] ), .O(\busy_sr[31]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT2 #( .INIT(4'h8)) \busy_sr[3]_i_1 (.I0(\busy_sr_reg_n_0_[2] ), .I1(p_0_in), .O(\busy_sr[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT2 #( .INIT(4'h8)) \busy_sr[4]_i_1 (.I0(\busy_sr_reg_n_0_[3] ), .I1(p_0_in), .O(\busy_sr[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT2 #( .INIT(4'h8)) \busy_sr[5]_i_1 (.I0(\busy_sr_reg_n_0_[4] ), .I1(p_0_in), .O(\busy_sr[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT2 #( .INIT(4'h8)) \busy_sr[6]_i_1 (.I0(\busy_sr_reg_n_0_[5] ), .I1(p_0_in), .O(\busy_sr[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT2 #( .INIT(4'h8)) \busy_sr[7]_i_1 (.I0(\busy_sr_reg_n_0_[6] ), .I1(p_0_in), .O(\busy_sr[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT2 #( .INIT(4'h8)) \busy_sr[8]_i_1 (.I0(\busy_sr_reg_n_0_[7] ), .I1(p_0_in), .O(\busy_sr[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT2 #( .INIT(4'h8)) \busy_sr[9]_i_1 (.I0(\busy_sr_reg_n_0_[8] ), .I1(p_0_in), .O(\busy_sr[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \busy_sr_reg[0] (.C(clk), .CE(busy_sr0), .D(p_1_in), .Q(\busy_sr_reg_n_0_[0] ), .R(1'b0)); FDSE #( .INIT(1'b0)) \busy_sr_reg[10] (.C(clk), .CE(busy_sr0), .D(\busy_sr[10]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[10] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[11] (.C(clk), .CE(busy_sr0), .D(\busy_sr[11]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[11] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[12] (.C(clk), .CE(busy_sr0), .D(\busy_sr[12]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[12] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[13] (.C(clk), .CE(busy_sr0), .D(\busy_sr[13]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[13] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[14] (.C(clk), .CE(busy_sr0), .D(\busy_sr[14]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[14] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[15] (.C(clk), .CE(busy_sr0), .D(\busy_sr[15]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[15] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[16] (.C(clk), .CE(busy_sr0), .D(\busy_sr[16]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[16] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[17] (.C(clk), .CE(busy_sr0), .D(\busy_sr[17]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[17] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[18] (.C(clk), .CE(busy_sr0), .D(\busy_sr[18]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[18] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[19] (.C(clk), .CE(busy_sr0), .D(\busy_sr[19]_i_1_n_0 ), .Q(p_1_in_0[0]), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[1] (.C(clk), .CE(busy_sr0), .D(\busy_sr[1]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[1] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[20] (.C(clk), .CE(busy_sr0), .D(\busy_sr[20]_i_1_n_0 ), .Q(p_1_in_0[1]), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[21] (.C(clk), .CE(busy_sr0), .D(\busy_sr[21]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[21] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[22] (.C(clk), .CE(busy_sr0), .D(\busy_sr[22]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[22] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[23] (.C(clk), .CE(busy_sr0), .D(\busy_sr[23]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[23] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[24] (.C(clk), .CE(busy_sr0), .D(\busy_sr[24]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[24] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[25] (.C(clk), .CE(busy_sr0), .D(\busy_sr[25]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[25] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[26] (.C(clk), .CE(busy_sr0), .D(\busy_sr[26]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[26] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[27] (.C(clk), .CE(busy_sr0), .D(\busy_sr[27]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[27] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[28] (.C(clk), .CE(busy_sr0), .D(\busy_sr[28]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[28] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[29] (.C(clk), .CE(busy_sr0), .D(\busy_sr[29]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[29] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[2] (.C(clk), .CE(busy_sr0), .D(\busy_sr[2]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[2] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[30] (.C(clk), .CE(busy_sr0), .D(\busy_sr[30]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[30] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[31] (.C(clk), .CE(busy_sr0), .D(\busy_sr[31]_i_2_n_0 ), .Q(p_0_in), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[3] (.C(clk), .CE(busy_sr0), .D(\busy_sr[3]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[3] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[4] (.C(clk), .CE(busy_sr0), .D(\busy_sr[4]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[4] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[5] (.C(clk), .CE(busy_sr0), .D(\busy_sr[5]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[5] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[6] (.C(clk), .CE(busy_sr0), .D(\busy_sr[6]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[6] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[7] (.C(clk), .CE(busy_sr0), .D(\busy_sr[7]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[7] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[8] (.C(clk), .CE(busy_sr0), .D(\busy_sr[8]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[8] ), .S(\busy_sr[31]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \busy_sr_reg[9] (.C(clk), .CE(busy_sr0), .D(\busy_sr[9]_i_1_n_0 ), .Q(\busy_sr_reg_n_0_[9] ), .S(\busy_sr[31]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT3 #( .INIT(8'hB8)) \data_sr[10]_i_1 (.I0(\data_sr_reg_n_0_[9] ), .I1(p_0_in), .I2(DOADO[7]), .O(\data_sr[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT3 #( .INIT(8'hB8)) \data_sr[12]_i_1 (.I0(\data_sr_reg_n_0_[11] ), .I1(p_0_in), .I2(DOADO[8]), .O(\data_sr[12]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT3 #( .INIT(8'hB8)) \data_sr[13]_i_1 (.I0(\data_sr_reg_n_0_[12] ), .I1(p_0_in), .I2(DOADO[9]), .O(\data_sr[13]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT3 #( .INIT(8'hB8)) \data_sr[14]_i_1 (.I0(\data_sr_reg_n_0_[13] ), .I1(p_0_in), .I2(DOADO[10]), .O(\data_sr[14]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT3 #( .INIT(8'hB8)) \data_sr[15]_i_1 (.I0(\data_sr_reg_n_0_[14] ), .I1(p_0_in), .I2(DOADO[11]), .O(\data_sr[15]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT3 #( .INIT(8'hB8)) \data_sr[16]_i_1 (.I0(\data_sr_reg_n_0_[15] ), .I1(p_0_in), .I2(DOADO[12]), .O(\data_sr[16]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT3 #( .INIT(8'hB8)) \data_sr[17]_i_1 (.I0(\data_sr_reg_n_0_[16] ), .I1(p_0_in), .I2(DOADO[13]), .O(\data_sr[17]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT3 #( .INIT(8'hB8)) \data_sr[18]_i_1 (.I0(\data_sr_reg_n_0_[17] ), .I1(p_0_in), .I2(DOADO[14]), .O(\data_sr[18]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT3 #( .INIT(8'hB8)) \data_sr[19]_i_1 (.I0(\data_sr_reg_n_0_[18] ), .I1(p_0_in), .I2(DOADO[15]), .O(\data_sr[19]_i_1_n_0 )); LUT6 #( .INIT(64'hCFCFCFCFAACAAAAA)) \data_sr[22]_i_1 (.I0(\data_sr_reg_n_0_[22] ), .I1(\data_sr_reg_n_0_[21] ), .I2(p_0_in), .I3(\data_sr[31]_i_2_n_0 ), .I4(divider_reg__0[7]), .I5(\busy_sr_reg[31]_0 ), .O(\data_sr[22]_i_1_n_0 )); LUT6 #( .INIT(64'hCFCFCFCFAACAAAAA)) \data_sr[27]_i_1 (.I0(\data_sr_reg_n_0_[27] ), .I1(\data_sr_reg_n_0_[26] ), .I2(p_0_in), .I3(\data_sr[31]_i_2_n_0 ), .I4(divider_reg__0[7]), .I5(\busy_sr_reg[31]_0 ), .O(\data_sr[27]_i_1_n_0 )); LUT3 #( .INIT(8'h02)) \data_sr[30]_i_1 (.I0(p_1_in), .I1(\busy_sr_reg[1]_0 ), .I2(p_0_in), .O(\data_sr[30]_i_1_n_0 )); LUT6 #( .INIT(64'hCFCFCFCFAACAAAAA)) \data_sr[31]_i_1 (.I0(\data_sr_reg_n_0_[31] ), .I1(\data_sr_reg_n_0_[30] ), .I2(p_0_in), .I3(\data_sr[31]_i_2_n_0 ), .I4(divider_reg__0[7]), .I5(\busy_sr_reg[31]_0 ), .O(\data_sr[31]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT2 #( .INIT(4'hB)) \data_sr[31]_i_2 (.I0(\busy_sr[0]_i_3_n_0 ), .I1(divider_reg__0[6]), .O(\data_sr[31]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT3 #( .INIT(8'hB8)) \data_sr[3]_i_1 (.I0(\data_sr_reg_n_0_[2] ), .I1(p_0_in), .I2(DOADO[0]), .O(\data_sr[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT3 #( .INIT(8'hB8)) \data_sr[4]_i_1 (.I0(\data_sr_reg_n_0_[3] ), .I1(p_0_in), .I2(DOADO[1]), .O(\data_sr[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT3 #( .INIT(8'hB8)) \data_sr[5]_i_1 (.I0(\data_sr_reg_n_0_[4] ), .I1(p_0_in), .I2(DOADO[2]), .O(\data_sr[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT3 #( .INIT(8'hB8)) \data_sr[6]_i_1 (.I0(\data_sr_reg_n_0_[5] ), .I1(p_0_in), .I2(DOADO[3]), .O(\data_sr[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT3 #( .INIT(8'hB8)) \data_sr[7]_i_1 (.I0(\data_sr_reg_n_0_[6] ), .I1(p_0_in), .I2(DOADO[4]), .O(\data_sr[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT3 #( .INIT(8'hB8)) \data_sr[8]_i_1 (.I0(\data_sr_reg_n_0_[7] ), .I1(p_0_in), .I2(DOADO[5]), .O(\data_sr[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT3 #( .INIT(8'hB8)) \data_sr[9]_i_1 (.I0(\data_sr_reg_n_0_[8] ), .I1(p_0_in), .I2(DOADO[6]), .O(\data_sr[9]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[10] (.C(clk), .CE(busy_sr0), .D(\data_sr[10]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[10] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[11] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[10] ), .Q(\data_sr_reg_n_0_[11] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[12] (.C(clk), .CE(busy_sr0), .D(\data_sr[12]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[12] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[13] (.C(clk), .CE(busy_sr0), .D(\data_sr[13]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[13] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[14] (.C(clk), .CE(busy_sr0), .D(\data_sr[14]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[14] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[15] (.C(clk), .CE(busy_sr0), .D(\data_sr[15]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[15] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[16] (.C(clk), .CE(busy_sr0), .D(\data_sr[16]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[16] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[17] (.C(clk), .CE(busy_sr0), .D(\data_sr[17]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[17] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[18] (.C(clk), .CE(busy_sr0), .D(\data_sr[18]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[18] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[19] (.C(clk), .CE(busy_sr0), .D(\data_sr[19]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[19] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[1] (.C(clk), .CE(busy_sr0), .D(p_0_in), .Q(\data_sr_reg_n_0_[1] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[20] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[19] ), .Q(\data_sr_reg_n_0_[20] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[21] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[20] ), .Q(\data_sr_reg_n_0_[21] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[22] (.C(clk), .CE(1'b1), .D(\data_sr[22]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[22] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[23] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[22] ), .Q(\data_sr_reg_n_0_[23] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[24] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[23] ), .Q(\data_sr_reg_n_0_[24] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[25] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[24] ), .Q(\data_sr_reg_n_0_[25] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[26] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[25] ), .Q(\data_sr_reg_n_0_[26] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[27] (.C(clk), .CE(1'b1), .D(\data_sr[27]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[27] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[28] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[27] ), .Q(\data_sr_reg_n_0_[28] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[29] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[28] ), .Q(\data_sr_reg_n_0_[29] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[2] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[1] ), .Q(\data_sr_reg_n_0_[2] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[30] (.C(clk), .CE(busy_sr0), .D(\data_sr_reg_n_0_[29] ), .Q(\data_sr_reg_n_0_[30] ), .R(\data_sr[30]_i_1_n_0 )); FDRE #( .INIT(1'b1)) \data_sr_reg[31] (.C(clk), .CE(1'b1), .D(\data_sr[31]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[31] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[3] (.C(clk), .CE(busy_sr0), .D(\data_sr[3]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[3] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[4] (.C(clk), .CE(busy_sr0), .D(\data_sr[4]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[4] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[5] (.C(clk), .CE(busy_sr0), .D(\data_sr[5]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[5] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[6] (.C(clk), .CE(busy_sr0), .D(\data_sr[6]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[6] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[7] (.C(clk), .CE(busy_sr0), .D(\data_sr[7]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[7] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[8] (.C(clk), .CE(busy_sr0), .D(\data_sr[8]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[8] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \data_sr_reg[9] (.C(clk), .CE(busy_sr0), .D(\data_sr[9]_i_1_n_0 ), .Q(\data_sr_reg_n_0_[9] ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT1 #( .INIT(2'h1)) \divider[0]_i_1 (.I0(divider_reg__1[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT2 #( .INIT(4'h6)) \divider[1]_i_1 (.I0(divider_reg__1[0]), .I1(divider_reg__1[1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT3 #( .INIT(8'h78)) \divider[2]_i_1 (.I0(divider_reg__1[1]), .I1(divider_reg__1[0]), .I2(divider_reg__1[2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT4 #( .INIT(16'h7F80)) \divider[3]_i_1 (.I0(divider_reg__1[2]), .I1(divider_reg__1[0]), .I2(divider_reg__1[1]), .I3(divider_reg__1[3]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT5 #( .INIT(32'h7FFF8000)) \divider[4]_i_1 (.I0(divider_reg__1[3]), .I1(divider_reg__1[1]), .I2(divider_reg__1[0]), .I3(divider_reg__1[2]), .I4(divider_reg__1[4]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \divider[5]_i_1 (.I0(divider_reg__1[4]), .I1(divider_reg__1[2]), .I2(divider_reg__1[0]), .I3(divider_reg__1[1]), .I4(divider_reg__1[3]), .I5(divider_reg__1[5]), .O(p_0_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT2 #( .INIT(4'h9)) \divider[6]_i_1 (.I0(\busy_sr[0]_i_3_n_0 ), .I1(divider_reg__0[6]), .O(p_0_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT3 #( .INIT(8'hD2)) \divider[7]_i_2 (.I0(divider_reg__0[6]), .I1(\busy_sr[0]_i_3_n_0 ), .I2(divider_reg__0[7]), .O(p_0_in__0[7])); FDRE #( .INIT(1'b1)) \divider_reg[0] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[0]), .Q(divider_reg__1[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[1] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[1]), .Q(divider_reg__1[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[2] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[2]), .Q(divider_reg__1[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[3] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[3]), .Q(divider_reg__1[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[4] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[4]), .Q(divider_reg__1[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[5] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[5]), .Q(divider_reg__1[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[6] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[6]), .Q(divider_reg__0[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \divider_reg[7] (.C(clk), .CE(\busy_sr_reg[31]_1 ), .D(p_0_in__0[7]), .Q(divider_reg__0[7]), .R(1'b0)); LUT6 #( .INIT(64'hFCFCFFF8FFFFFFFF)) sioc_i_1 (.I0(\busy_sr_reg_n_0_[0] ), .I1(sioc_i_2_n_0), .I2(sioc_i_3_n_0), .I3(\busy_sr_reg_n_0_[1] ), .I4(sioc_i_4_n_0), .I5(p_0_in), .O(sioc_i_1_n_0)); LUT2 #( .INIT(4'h6)) sioc_i_2 (.I0(divider_reg__0[6]), .I1(divider_reg__0[7]), .O(sioc_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT4 #( .INIT(16'hA222)) sioc_i_3 (.I0(sioc_i_5_n_0), .I1(\busy_sr_reg_n_0_[30] ), .I2(divider_reg__0[6]), .I3(p_0_in), .O(sioc_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT4 #( .INIT(16'h7FFF)) sioc_i_4 (.I0(\busy_sr_reg_n_0_[29] ), .I1(\busy_sr_reg_n_0_[2] ), .I2(p_0_in), .I3(\busy_sr_reg_n_0_[30] ), .O(sioc_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT4 #( .INIT(16'h0001)) sioc_i_5 (.I0(\busy_sr_reg_n_0_[0] ), .I1(\busy_sr_reg_n_0_[1] ), .I2(\busy_sr_reg_n_0_[29] ), .I3(\busy_sr_reg_n_0_[2] ), .O(sioc_i_5_n_0)); FDRE sioc_reg (.C(clk), .CE(1'b1), .D(sioc_i_1_n_0), .Q(sioc), .R(1'b0)); LUT2 #( .INIT(4'h8)) siod_INST_0 (.I0(\data_sr_reg_n_0_[31] ), .I1(siod_INST_0_i_1_n_0), .O(siod)); LUT6 #( .INIT(64'hB0BBB0BB0000B0BB)) siod_INST_0_i_1 (.I0(\busy_sr_reg_n_0_[28] ), .I1(\busy_sr_reg_n_0_[29] ), .I2(p_1_in_0[0]), .I3(p_1_in_0[1]), .I4(\busy_sr_reg_n_0_[11] ), .I5(\busy_sr_reg_n_0_[10] ), .O(siod_INST_0_i_1_n_0)); FDRE taken_reg (.C(clk), .CE(1'b1), .D(\busy_sr_reg[31]_0 ), .Q(E), .R(1'b0)); endmodule module system_ov7670_controller_1_0_ov7670_controller (config_finished, siod, xclk, sioc, resend, clk); output config_finished; output siod; output xclk; output sioc; input resend; input clk; wire Inst_i2c_sender_n_3; wire Inst_ov7670_registers_n_16; wire Inst_ov7670_registers_n_18; wire clk; wire config_finished; wire p_0_in; wire [0:0]p_1_in; wire resend; wire sioc; wire siod; wire [15:0]sreg_reg; wire sys_clk_i_1_n_0; wire taken; wire xclk; system_ov7670_controller_1_0_i2c_sender Inst_i2c_sender (.DOADO(sreg_reg), .E(taken), .\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3), .\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18), .\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16), .clk(clk), .p_0_in(p_0_in), .p_1_in(p_1_in), .sioc(sioc), .siod(siod)); system_ov7670_controller_1_0_ov7670_registers Inst_ov7670_registers (.DOADO(sreg_reg), .E(taken), .clk(clk), .config_finished(config_finished), .\divider_reg[2] (Inst_i2c_sender_n_3), .\divider_reg[7] (Inst_ov7670_registers_n_16), .p_0_in(p_0_in), .p_1_in(p_1_in), .resend(resend), .taken_reg(Inst_ov7670_registers_n_18)); LUT1 #( .INIT(2'h1)) sys_clk_i_1 (.I0(xclk), .O(sys_clk_i_1_n_0)); FDRE #( .INIT(1'b0)) sys_clk_reg (.C(clk), .CE(1'b1), .D(sys_clk_i_1_n_0), .Q(xclk), .R(1'b0)); endmodule module system_ov7670_controller_1_0_ov7670_registers (DOADO, \divider_reg[7] , config_finished, taken_reg, p_1_in, clk, \divider_reg[2] , p_0_in, resend, E); output [15:0]DOADO; output [0:0]\divider_reg[7] ; output config_finished; output taken_reg; output [0:0]p_1_in; input clk; input \divider_reg[2] ; input p_0_in; input resend; input [0:0]E; wire [15:0]DOADO; wire [0:0]E; wire [7:0]address; wire [7:0]address_reg__0; wire \address_rep[0]_i_1_n_0 ; wire \address_rep[1]_i_1_n_0 ; wire \address_rep[2]_i_1_n_0 ; wire \address_rep[3]_i_1_n_0 ; wire \address_rep[4]_i_1_n_0 ; wire \address_rep[5]_i_1_n_0 ; wire \address_rep[6]_i_1_n_0 ; wire \address_rep[7]_i_1_n_0 ; wire \address_rep[7]_i_2_n_0 ; wire clk; wire config_finished; wire config_finished_INST_0_i_1_n_0; wire config_finished_INST_0_i_2_n_0; wire config_finished_INST_0_i_3_n_0; wire config_finished_INST_0_i_4_n_0; wire \divider_reg[2] ; wire [0:0]\divider_reg[7] ; wire p_0_in; wire [0:0]p_1_in; wire resend; wire taken_reg; wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED; wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED; wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED; (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[0] (.C(clk), .CE(E), .D(\address_rep[0]_i_1_n_0 ), .Q(address_reg__0[0]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[1] (.C(clk), .CE(E), .D(\address_rep[1]_i_1_n_0 ), .Q(address_reg__0[1]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[2] (.C(clk), .CE(E), .D(\address_rep[2]_i_1_n_0 ), .Q(address_reg__0[2]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[3] (.C(clk), .CE(E), .D(\address_rep[3]_i_1_n_0 ), .Q(address_reg__0[3]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[4] (.C(clk), .CE(E), .D(\address_rep[4]_i_1_n_0 ), .Q(address_reg__0[4]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[5] (.C(clk), .CE(E), .D(\address_rep[5]_i_1_n_0 ), .Q(address_reg__0[5]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[6] (.C(clk), .CE(E), .D(\address_rep[6]_i_1_n_0 ), .Q(address_reg__0[6]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg[7] (.C(clk), .CE(E), .D(\address_rep[7]_i_1_n_0 ), .Q(address_reg__0[7]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[0] (.C(clk), .CE(E), .D(\address_rep[0]_i_1_n_0 ), .Q(address[0]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[1] (.C(clk), .CE(E), .D(\address_rep[1]_i_1_n_0 ), .Q(address[1]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[2] (.C(clk), .CE(E), .D(\address_rep[2]_i_1_n_0 ), .Q(address[2]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[3] (.C(clk), .CE(E), .D(\address_rep[3]_i_1_n_0 ), .Q(address[3]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[4] (.C(clk), .CE(E), .D(\address_rep[4]_i_1_n_0 ), .Q(address[4]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[5] (.C(clk), .CE(E), .D(\address_rep[5]_i_1_n_0 ), .Q(address[5]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[6] (.C(clk), .CE(E), .D(\address_rep[6]_i_1_n_0 ), .Q(address[6]), .R(resend)); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \address_reg_rep[7] (.C(clk), .CE(E), .D(\address_rep[7]_i_1_n_0 ), .Q(address[7]), .R(resend)); LUT1 #( .INIT(2'h1)) \address_rep[0]_i_1 (.I0(address_reg__0[0]), .O(\address_rep[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT2 #( .INIT(4'h6)) \address_rep[1]_i_1 (.I0(address_reg__0[0]), .I1(address_reg__0[1]), .O(\address_rep[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT3 #( .INIT(8'h78)) \address_rep[2]_i_1 (.I0(address_reg__0[1]), .I1(address_reg__0[0]), .I2(address_reg__0[2]), .O(\address_rep[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT4 #( .INIT(16'h7F80)) \address_rep[3]_i_1 (.I0(address_reg__0[2]), .I1(address_reg__0[0]), .I2(address_reg__0[1]), .I3(address_reg__0[3]), .O(\address_rep[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT5 #( .INIT(32'h7FFF8000)) \address_rep[4]_i_1 (.I0(address_reg__0[3]), .I1(address_reg__0[1]), .I2(address_reg__0[0]), .I3(address_reg__0[2]), .I4(address_reg__0[4]), .O(\address_rep[4]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \address_rep[5]_i_1 (.I0(address_reg__0[4]), .I1(address_reg__0[2]), .I2(address_reg__0[0]), .I3(address_reg__0[1]), .I4(address_reg__0[3]), .I5(address_reg__0[5]), .O(\address_rep[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT2 #( .INIT(4'h9)) \address_rep[6]_i_1 (.I0(\address_rep[7]_i_2_n_0 ), .I1(address_reg__0[6]), .O(\address_rep[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT3 #( .INIT(8'hD2)) \address_rep[7]_i_1 (.I0(address_reg__0[6]), .I1(\address_rep[7]_i_2_n_0 ), .I2(address_reg__0[7]), .O(\address_rep[7]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \address_rep[7]_i_2 (.I0(address_reg__0[4]), .I1(address_reg__0[2]), .I2(address_reg__0[0]), .I3(address_reg__0[1]), .I4(address_reg__0[3]), .I5(address_reg__0[5]), .O(\address_rep[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT5 #( .INIT(32'h0000FFFE)) \busy_sr[0]_i_2 (.I0(config_finished_INST_0_i_4_n_0), .I1(config_finished_INST_0_i_3_n_0), .I2(config_finished_INST_0_i_2_n_0), .I3(config_finished_INST_0_i_1_n_0), .I4(p_0_in), .O(p_1_in)); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT4 #( .INIT(16'h0001)) config_finished_INST_0 (.I0(config_finished_INST_0_i_1_n_0), .I1(config_finished_INST_0_i_2_n_0), .I2(config_finished_INST_0_i_3_n_0), .I3(config_finished_INST_0_i_4_n_0), .O(config_finished)); LUT4 #( .INIT(16'h7FFF)) config_finished_INST_0_i_1 (.I0(DOADO[5]), .I1(DOADO[4]), .I2(DOADO[7]), .I3(DOADO[6]), .O(config_finished_INST_0_i_1_n_0)); LUT4 #( .INIT(16'h7FFF)) config_finished_INST_0_i_2 (.I0(DOADO[1]), .I1(DOADO[0]), .I2(DOADO[3]), .I3(DOADO[2]), .O(config_finished_INST_0_i_2_n_0)); LUT4 #( .INIT(16'h7FFF)) config_finished_INST_0_i_3 (.I0(DOADO[13]), .I1(DOADO[12]), .I2(DOADO[15]), .I3(DOADO[14]), .O(config_finished_INST_0_i_3_n_0)); LUT4 #( .INIT(16'h7FFF)) config_finished_INST_0_i_4 (.I0(DOADO[9]), .I1(DOADO[8]), .I2(DOADO[11]), .I3(DOADO[10]), .O(config_finished_INST_0_i_4_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFE0000)) \divider[7]_i_1 (.I0(config_finished_INST_0_i_1_n_0), .I1(config_finished_INST_0_i_2_n_0), .I2(config_finished_INST_0_i_3_n_0), .I3(config_finished_INST_0_i_4_n_0), .I4(\divider_reg[2] ), .I5(p_0_in), .O(\divider_reg[7] )); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "4096" *) (* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *) (* bram_addr_begin = "0" *) (* bram_addr_end = "1023" *) (* bram_slice_begin = "0" *) (* bram_slice_end = "15" *) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280), .INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440), .INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907), .INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100), .INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(18'h00000), .INIT_B(18'h00000), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(18), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(18), .WRITE_WIDTH_B(0)) sreg_reg (.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}), .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .CLKARDCLK(clk), .CLKBWRCLK(1'b0), .DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .DIPADIP({1'b0,1'b0}), .DIPBDIP({1'b1,1'b1}), .DOADO(DOADO), .DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]), .DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]), .DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]), .ENARDEN(1'b1), .ENBWREN(1'b0), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({1'b0,1'b0}), .WEBWE({1'b0,1'b0,1'b0,1'b0})); LUT6 #( .INIT(64'h0000000055555554)) taken_i_1 (.I0(p_0_in), .I1(config_finished_INST_0_i_1_n_0), .I2(config_finished_INST_0_i_2_n_0), .I3(config_finished_INST_0_i_3_n_0), .I4(config_finished_INST_0_i_4_n_0), .I5(\divider_reg[2] ), .O(taken_reg)); endmodule (* CHECK_LICENSE_TYPE = "system_ov7670_controller_0_0,ov7670_controller,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_controller,Vivado 2016.4" *) (* NotValidForBitStream *) module system_ov7670_controller_1_0 (clk, resend, config_finished, sioc, siod, reset, pwdn, xclk); (* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk; input resend; output config_finished; output sioc; inout siod; (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset; output pwdn; output xclk; wire \<const0> ; wire \<const1> ; wire clk; wire config_finished; wire resend; wire sioc; wire siod; wire xclk; assign pwdn = \<const0> ; assign reset = \<const1> ; GND GND (.G(\<const0> )); system_ov7670_controller_1_0_ov7670_controller U0 (.clk(clk), .config_finished(config_finished), .resend(resend), .sioc(sioc), .siod(siod), .xclk(xclk)); VCC VCC (.P(\<const1> )); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif

/* * Milkymist VJ SoC * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 3 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ module tmu2_geninterp18( input sys_clk, input load, input next_point, input signed [17:0] init, input positive, input [16:0] q, input [16:0] r, input [16:0] divisor, output signed [17:0] o ); reg positive_r; reg [16:0] q_r; reg [16:0] r_r; reg [16:0] divisor_r; always @(posedge sys_clk) begin if(load) begin positive_r <= positive; q_r <= q; r_r <= r; divisor_r <= divisor; end end reg [17:0] err; reg correct; reg signed [17:0] o_r; assign o = o_r; always @(posedge sys_clk) begin if(load) begin err = 18'd0; o_r = init; end else if(next_point) begin err = err + r_r; correct = (err[16:0] > {1'b0, divisor_r[16:1]}) & ~err[17]; if(positive_r) begin o_r = o_r + {1'b0, q_r}; if(correct) o_r = o_r + 18'd1; end else begin o_r = o_r - {1'b0, q_r}; if(correct) o_r = o_r - 18'd1; end if(correct) err = err - {1'b0, divisor_r}; end end endmodule

/* * Copyright (C) 2011 Kiel Friedt * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ //authors Kiel Friedt, Kevin McIntosh,Cody DeHaan module proj1_testbench; //Inputs: Regs //Out: Wires reg A; reg B; wire out; reg select; reg clk; toplevel DUT(A, B, select, out, clk); always #5 clk=~clk; initial begin select = 1'b0; clk = 1'b0; A = 1'b0; B = 1'b0; end always @(posedge clk) begin if (select) select <= 0; else select <= 1; end endmodule

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_SYMBOL_V `define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_SYMBOL_V /** * UDP_OUT :=x when VPWR!=1 or VGND!=0 * UDP_OUT :=UDP_IN when VPWR==1 and VGND==0 * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_ls__udp_pwrgood_pp$PG ( //# {{data|Data Signals}} input UDP_IN , output UDP_OUT, //# {{power|Power}} input VPWR , input VGND ); endmodule `default_nettype wire `endif // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_SYMBOL_V

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LS__DLXBP_TB_V `define SKY130_FD_SC_LS__DLXBP_TB_V /** * dlxbp: Delay latch, non-inverted enable, complementary outputs. * * Autogenerated test bench. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none `include "sky130_fd_sc_ls__dlxbp.v" module top(); // Inputs are registered reg D; reg VPWR; reg VGND; reg VPB; reg VNB; // Outputs are wires wire Q; wire Q_N; initial begin // Initial state is x for all inputs. D = 1'bX; VGND = 1'bX; VNB = 1'bX; VPB = 1'bX; VPWR = 1'bX; #20 D = 1'b0; #40 VGND = 1'b0; #60 VNB = 1'b0; #80 VPB = 1'b0; #100 VPWR = 1'b0; #120 D = 1'b1; #140 VGND = 1'b1; #160 VNB = 1'b1; #180 VPB = 1'b1; #200 VPWR = 1'b1; #220 D = 1'b0; #240 VGND = 1'b0; #260 VNB = 1'b0; #280 VPB = 1'b0; #300 VPWR = 1'b0; #320 VPWR = 1'b1; #340 VPB = 1'b1; #360 VNB = 1'b1; #380 VGND = 1'b1; #400 D = 1'b1; #420 VPWR = 1'bx; #440 VPB = 1'bx; #460 VNB = 1'bx; #480 VGND = 1'bx; #500 D = 1'bx; end // Create a clock reg GATE; initial begin GATE = 1'b0; end always begin #5 GATE = ~GATE; end sky130_fd_sc_ls__dlxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE(GATE)); endmodule `default_nettype wire `endif // SKY130_FD_SC_LS__DLXBP_TB_V

/* Atari on an FPGA Masters of Engineering Project Cornell University, 2007 Daniel Beer RIOT.v Redesign of the MOS 6532 chip. Provides RAM, I/O and timers to the Atari. */ `timescale 1ns / 1ps `include "riot.vh" module RIOT(A, // Address bus input Din, // Data bus input Dout, // Data bus output CS, // Chip select input CS_n, // Active low chip select input R_W_n, // Active low read/write input RS_n, // Active low rom select input RES_n, // Active low reset input IRQ_n, // Active low interrupt output CLK, // Clock input PAin, // 8 bit port A input PAout, // 8 bit port A output PBin, // 8 bit port B input PBout);// 8 bit port B output input [6:0] A; input [7:0] Din; output [7:0] Dout; input CS, CS_n, R_W_n, RS_n, RES_n, CLK; output IRQ_n; input [7:0] PAin, PBin; output [7:0] PAout, PBout; // Output register reg [7:0] Dout; // RAM allocation reg [7:0] RAM[127:0]; // I/O registers reg [7:0] DRA, DRB; // Data registers reg [7:0] DDRA, DDRB; // Data direction registers wire PA7; reg R_PA7; assign PA7 = (PAin[7] & ~DDRA[7]) | (DRA[7] & DDRA[7]); assign PAout = DRA & DDRA; assign PBout = DRB & DDRB; // Timer registers reg [8:0] Timer; reg [9:0] Prescaler; reg [1:0] Timer_Mode; reg Timer_Int_Flag, PA7_Int_Flag, Timer_Int_Enable, PA7_Int_Enable, PA7_Int_Mode; // Timer prescaler constants wire [9:0] PRESCALER_VALS[3:0]; assign PRESCALER_VALS[0] = 10'd0; assign PRESCALER_VALS[1] = 10'd7; assign PRESCALER_VALS[2] = 10'd63; assign PRESCALER_VALS[3] = 10'd1023; // Interrupt assign IRQ_n = ~(Timer_Int_Flag & Timer_Int_Enable | PA7_Int_Flag & PA7_Int_Enable); // Operation decoding wire [6:0] op; reg [6:0] R_op; assign op = {RS_n, R_W_n, A[4:0]}; // Registered data in reg [7:0] R_Din; integer cnt; // Software operations always @(posedge CLK) begin // Reset operation if (~RES_n) begin DRA <= 8'b0; DDRA <= 8'b0; DRB <= 8'b0; DDRB <= 8'b0; Timer_Int_Flag <= 1'b0; PA7_Int_Flag <= 1'b0; PA7_Int_Enable <= 1'b0; PA7_Int_Mode <= 1'b0; // Fill RAM with 0s for (cnt = 0; cnt < 128; cnt = cnt + 1) RAM[cnt] <= 8'b0; R_PA7 <= 1'b0; R_op <= `NOP; R_Din <= 8'b0; end // If the chip is enabled, execute an operation else if (CS & ~CS_n) begin // Register inputs for use later R_PA7 <= PA7; R_op <= op; R_Din <= Din; // Update the timer interrupt flag casex (op) `WRITE_TIMER: Timer_Int_Flag <= 1'b0; `READ_TIMER: Timer_Int_Flag <= 1'b0; default: if (Timer == 9'b111111111) Timer_Int_Flag <= 1'b1; endcase // Update the port A interrupt flag casex (op) `READ_INT_FLAG: PA7_Int_Flag <= 1'b0; default: PA7_Int_Flag <= PA7_Int_Flag | (PA7 != R_PA7 & PA7 == PA7_Int_Mode); endcase // Process the current operation casex(op) // RAM access `READ_RAM: Dout <= RAM[A]; `WRITE_RAM: RAM[A] <= Din; // Port A data access `READ_DRA : Dout <= (PAin & ~DDRA) | (DRA & DDRA); `WRITE_DRA: DRA <= Din; // Port A direction register access `READ_DDRA: Dout <= DDRA; `WRITE_DDRA: DDRA <= Din; // Port B data access `READ_DRB: Dout <= (PBin & ~DDRB) | (DRB & DDRB); `WRITE_DRB: DRB <= Din; // Port B direction register access `READ_DDRB: Dout <= DDRB; `WRITE_DDRB: DDRB <= Din; // Timer access `READ_TIMER: Dout <= Timer[7:0]; // Status register access `READ_INT_FLAG: Dout <= {Timer_Int_Flag, PA7_Int_Flag, 6'b0}; // Enable the port A interrupt `WRITE_EDGE_DETECT: begin PA7_Int_Mode <= A[0]; PA7_Int_Enable <= A[1]; end endcase end // Even if the chip is not enabled, update background functions else begin // Update the timer interrupt if (Timer == 9'b111111111) Timer_Int_Flag <= 1'b1; // Update the port A interrupt R_PA7 <= PA7; PA7_Int_Flag <= PA7_Int_Flag | (PA7 != R_PA7 & PA7 == PA7_Int_Mode); // Set the operation to a NOP R_op <=`NOP; end end // Update the timer at the negative edge of the clock always @(negedge CLK)begin // Reset operation if (~RES_n) begin Timer <= 9'b0; Timer_Mode <= 2'b0; Prescaler <= 10'b0; Timer_Int_Enable <= 1'b0; end // Otherwise, process timer operations else casex (R_op) // Write value to the timer and update the prescaler based on the address `WRITE_TIMER:begin Timer <= {1'b0, R_Din}; Timer_Mode <= R_op[1:0]; Prescaler <= PRESCALER_VALS[R_op[1:0]]; Timer_Int_Enable <= R_op[3]; end // Otherwise decrement the prescaler and if necessary the timer. // The prescaler holds a variable number of counts that must be // run before the timer is decremented default:if (Timer != 9'b100000000) begin if (Prescaler != 10'b0) Prescaler <= Prescaler - 10'b1; else begin if (Timer == 9'b0) begin Prescaler <= 10'b0; Timer_Mode <= 2'b0; end else Prescaler <= PRESCALER_VALS[Timer_Mode]; Timer <= Timer - 9'b1; end end endcase end endmodule

/* * Quarter-wave sine table. * Features: * - Parameterized for arbitrary input & output widths * - 1/2 LSB angle offset for glitch-free quarter wave sine table * - Unsigned quarter wave Lookup table * - Sine table size is 2^(ANGLE_WIDTH-2) x OUT_WIDTH-1 * - 2 clock delay between input and output * * For a size example, an 18-bit output with a 12-bit angle requires a 1024x17 * sine table, which readily fits into a single RAM16 block in a Spartan 6 FPGA. */ /////////////////////////////////////////////////////////////////////////// // MODULE DECLARATION /////////////////////////////////////////////////////////////////////////// module sineTable #( parameter ANGLE_WIDTH = 12, parameter OUT_WIDTH = 18 ) ( input wire clk, ///< System Clock input wire [ANGLE_WIDTH-1:0] angle, ///< Angle to take sine of output reg signed [OUT_WIDTH-1:0] sine ///< Sine of angle ); /////////////////////////////////////////////////////////////////////////// // PARAMETER AND SIGNAL DECLARATIONS /////////////////////////////////////////////////////////////////////////// localparam TABLE_LEN = 2**(ANGLE_WIDTH-2); wire [ANGLE_WIDTH-3:0] quarterAngle; reg [OUT_WIDTH-2:0] sineTable [TABLE_LEN-1:0]; reg signBit; reg [OUT_WIDTH-2:0] halfSine; integer i; /////////////////////////////////////////////////////////////////////////// // MAIN CODE /////////////////////////////////////////////////////////////////////////// assign quarterAngle = (angle[ANGLE_WIDTH-2]) ? ~angle[ANGLE_WIDTH-3:0] : angle[ANGLE_WIDTH-3:0]; initial begin signBit = 1'b0; halfSine = 'd0; sine = 'd0; for(i=0; i<TABLE_LEN; i=i+1) begin sineTable[i] = $rtoi($floor($sin((i+0.5)*3.14159/(TABLE_LEN*2))*(2**(OUT_WIDTH-1)-1)+0.5)); end end always @(posedge clk) begin signBit <= angle[ANGLE_WIDTH-1]; halfSine <= sineTable[quarterAngle]; sine <= signBit ? -$signed({1'b0,halfSine}) : $signed({1'b0, halfSine}); end endmodule

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:41:14 04/19/2014 // Design Name: // Module Name: Image_viewer_top // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Image_viewer_top(ClkPort, Hsync, Vsync, vgaRed, vgaGreen, vgaBlue, MemOE, MemWR, MemClk, RamCS, RamUB, RamLB, RamAdv, RamCRE, MemAdr, data, An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp, Led, btnC, btnR, btnL, btnU, btnD ); // =========================================================================== // Port Declarations // =========================================================================== input ClkPort; output MemOE, MemWR, MemClk, RamCS, RamUB, RamLB, RamAdv, RamCRE; output [26:1] MemAdr; inout [15:0] data; //Button input btnC, btnR, btnL, btnU, btnD; //Light/Display output An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp; output Vsync, Hsync; output [2:0] vgaRed; output [2:0] vgaGreen; output [2:1] vgaBlue; output [1:0] Led; reg [2:0] _vgaRed; reg [2:0] _vgaGreen; reg [1:0] _vgaBlue; wire inDisplayArea; wire [9:0] CounterX; wire [9:0] CounterY; reg [5:0] bitCounter; assign vgaRed = _vgaRed; assign vgaGreen = _vgaGreen; assign vgaBlue = _vgaBlue; assign Led = readImage; // =========================================================================== // Parameters, Regsiters, and Wires // =========================================================================== //Global Stuff wire ClkPort, sys_clk, Reset; reg [26:0] DIV_CLK; assign sys_clk = ClkPort; assign MemClk = DIV_CLK[0]; //Memory Stuff reg [22:0] address; reg [15:0] dataRegister[0:127]; reg [22:0] imageRegister[0:3]; always@(posedge sys_clk) begin imageRegister[2'b00][22:0] <= 23'b00000000000000000000000; imageRegister[2'b01][22:0] <= 23'b00000000000000010000000; imageRegister[2'b10][22:0] <= 23'b00000000000000100000000; imageRegister[2'b11][22:0] <= 23'b00000000000000110000000; end wire [7:0] uByte; wire [7:0] lByte; reg [1:0] readImage; reg [6:0] readAddress; reg [6:0] writePointer; reg [6:0] readRow; assign uByte = data[15:8]; assign lByte = data[7:0]; //Button Stuff wire BtnR_Pulse, BtnL_Pulse, BtnU_Pulse, BtnD_Pulse; assign Reset = btnC; //-------------------------------------------------------------------// always @ (posedge sys_clk, posedge Reset) begin : CLOCK_DIVIDER if (Reset) DIV_CLK <= 0; else DIV_CLK <= DIV_CLK + 1; end //--------------------Debounce Controllers--------------------// ee201_debouncer #(.N_dc(20)) ee201_debouncer_left (.CLK(MemClk), .RESET(Reset), .PB(btnL), .DPB( ), .SCEN(BtnL_Pulse), .MCEN( ), .CCEN( )); ee201_debouncer #(.N_dc(20)) ee201_debouncer_right (.CLK(MemClk), .RESET(Reset), .PB(btnR), .DPB( ), .SCEN(BtnR_Pulse), .MCEN( ), .CCEN( )); ee201_debouncer #(.N_dc(20)) ee201_debouncer_up (.CLK(MemClk), .RESET(Reset), .PB(btnU), .DPB( ), .SCEN(BtnU_Pulse), .MCEN( ), .CCEN( )); ee201_debouncer #(.N_dc(20)) ee201_debouncer_down (.CLK(MemClk), .RESET(Reset), .PB(btnD), .DPB( ), .SCEN(BtnD_Pulse), .MCEN( ), .CCEN( )); //--------------------Display Controller--------------------// DisplayCtrl display (.Clk(DIV_CLK), .reset(Reset), .memoryData(dataRegister[readRow][15:0]), .An0(An0), .An1(An1), .An2(An2), .An3(An3), .Ca(Ca), .Cb(Cb), .Cc(Cc), .Cd(Cd), .Ce(Ce), .Cf(Cf), .Cg(Cg), .Dp(Dp) ); //--------------------Memory Controller--------------------// MemoryCtrl memory(.Clk(MemClk), .Reset(Reset), .MemAdr(MemAdr), .MemOE(MemOE), .MemWR(MemWR), .RamCS(RamCS), .RamUB(RamUB), .RamLB(RamLB), .RamAdv(RamAdv), .RamCRE(RamCRE), .writeData(writeData), .AddressIn(address), .BtnU_Pulse(BtnU_Pulse), .BtnD_Pulse(BtnD_Pulse) ); //--------------------VGA Controller--------------------// VGACtrl vga(.clk(DIV_CLK[1]), .reset(Reset), .vga_h_sync(Hsync), .vga_v_sync(Vsync), .inDisplayArea(inDisplayArea), .CounterX(CounterX), .CounterY(CounterY) ); reg toggleByte; always @(posedge DIV_CLK[1], posedge Reset) begin if(Reset) begin bitCounter <= 0; toggleByte <= 0; readAddress <= 0; end else if(CounterY > 192 && CounterY < 288) begin if(CounterX == 0) begin bitCounter <= 0; toggleByte <= 1'b0; end else if(CounterX > 284 && bitCounter < 35) begin if(toggleByte == 1'b0) begin {_vgaRed, _vgaGreen, _vgaBlue} <= dataRegister[readAddress][7:0]; toggleByte <= 1'b1; end else begin {_vgaRed, _vgaGreen, _vgaBlue} <= dataRegister[readAddress][15:8]; toggleByte <= 1'b0; bitCounter <= bitCounter + 1; readAddress <= readAddress + 1; end end else begin {_vgaRed, _vgaGreen, _vgaBlue} <= 0; end end else if (CounterY == 288) readAddress <= 0; end always@(posedge MemClk, posedge Reset) begin if(Reset) readImage <= 0; else if(BtnU_Pulse) readImage <= readImage + 1; else if(BtnD_Pulse) readImage <= readImage - 1; else address <= imageRegister[readImage][22:0]; end //--------------------Process Data--------------------// always@(posedge MemClk, posedge Reset) begin if(Reset) begin writePointer <= 0; end else if(writeData == 1'b1) begin dataRegister[writePointer][15:0] <= {lByte, uByte}; writePointer <= writePointer + 1; end else writePointer <= 0; end //--------------------SSD Display Data--------------------// always@(posedge MemClk, posedge Reset) begin if(Reset) readRow <= 0; else if(BtnR_Pulse) readRow <= readRow + 1; else if(BtnL_Pulse) readRow <= readRow - 1; end endmodule

// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 // Date : Thu Feb 09 23:36:35 2017 // Host : TheMosass-PC running 64-bit major release (build 9200) // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xlconcat_0_0_stub.v // Design : design_1_xlconcat_0_0 // Purpose : Stub declaration of top-level module interface // Device : xc7z010clg400-1 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "xlconcat,Vivado 2016.4" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(In0, In1, dout) /* synthesis syn_black_box black_box_pad_pin="In0[0:0],In1[0:0],dout[1:0]" */; input [0:0]In0; input [0:0]In1; output [1:0]dout; endmodule

/* * MBus Copyright 2015 Regents of the University of Michigan * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ always @ (posedge clk or negedge resetn) begin // not in reset if (resetn) begin case (state) // Wake up processor and all B.C. TASK0: begin c0_req_int <= 1; state <= TX_WAIT; end // Querry nodes TASK1: begin c0_tx_addr <= {28'h000000, `CHANNEL_ENUM}; c0_tx_data <= {`CMD_CHANNEL_ENUM_QUERRY, 28'h0}; c0_tx_req <= 1; c0_tx_pend <= 0; c0_priority <= 0; state <= TX_WAIT; end // Enumerate with 4'h2 TASK2: begin c0_tx_addr <= {28'h000000, `CHANNEL_ENUM}; // address should starts with 4'h2 c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h2, 24'h0}; c0_tx_req <= 1; c0_tx_pend <= 0; c0_priority <= 0; state <= TX_WAIT; end // Enumerate with 4'h3 TASK3: begin c0_tx_addr <= {28'h000000, `CHANNEL_ENUM}; c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h3, 24'h0}; c0_tx_req <= 1; c0_tx_pend <= 0; c0_priority <= 0; state <= TX_WAIT; end // Enumerate with 4'h4 TASK4: begin c0_tx_addr <= {28'h000000, `CHANNEL_ENUM}; c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h4, 24'h0}; c0_tx_req <= 1; c0_tx_pend <= 0; c0_priority <= 0; state <= TX_WAIT; end // Enumerate with 4'h5 TASK5: begin c0_tx_addr <= {28'h000000, `CHANNEL_ENUM}; c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h5, 24'h0}; c0_tx_req <= 1; c0_tx_pend <= 0; c0_priority <= 0; state <= TX_WAIT; end // n0 -> 4'h2 // n1 -> 4'h3 // n2 -> 4'h4 // n3 -> 4'h5 // n1 -> n2 byte streamming using short address TASK6: begin if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {24'h0, 4'h4, 4'h1}; // 4'h1 is functional ID n1_tx_data <= rand_dat; n1_tx_req <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat); if (word_counter) begin word_counter <= word_counter - 1; n1_tx_pend <= 1; end else begin n1_tx_pend <= 0; state <= TX_WAIT; end end end // n1 -> n0 byte streamming using short address TASK7: begin if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {24'h0, 4'h2, 4'h3}; // 4'h3 is functional ID n1_tx_data <= rand_dat; n1_tx_req <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat); if (word_counter) begin word_counter <= word_counter - 1; n1_tx_pend <= 1; end else begin n1_tx_pend <= 0; state <= TX_WAIT; end end end // n1 -> n2 byte streamming using long address TASK8: begin if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {4'hf, 4'h0, 20'hbbbb2, 4'h1}; // 4'h1 is functional ID n1_tx_data <= rand_dat; n1_tx_req <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat); if (word_counter) begin word_counter <= word_counter - 1; n1_tx_pend <= 1; end else begin n1_tx_pend <= 0; state <= TX_WAIT; end end end // n1 -> n0 byte streamming using short address TASK9: begin if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {4'hf, 4'h0, 20'hbbbb0, 4'h3}; // 4'h3 is functional ID n1_tx_data <= rand_dat; n1_tx_req <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat); if (word_counter) begin word_counter <= word_counter - 1; n1_tx_pend <= 1; end else begin n1_tx_pend <= 0; state <= TX_WAIT; end end end // Unknown address TASK10: begin if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {4'hf, 4'h0, 20'hbbbb5, 4'h2}; n1_tx_data <= rand_dat; n1_tx_pend <= 0; n1_tx_req <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat); state <= TX_WAIT; end end // n1 -> n2 TX buffer underflow TASK11: begin if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {24'h0, 4'h4, 4'h3}; n1_tx_data <= rand_dat; n1_tx_pend <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat); if (word_counter) begin n1_tx_req <= 1; word_counter <= word_counter - 1; end else begin n1_tx_req <= 0; state <= TX_WAIT; end end end // n1 -> n0 TX buffer underflow TASK12: begin if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {24'h0, 4'h2, 4'h8}; n1_tx_data <= rand_dat; n1_tx_pend <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat); if (word_counter) begin n1_tx_req <= 1; word_counter <= word_counter - 1; end else begin n1_tx_req <= 0; state <= TX_WAIT; end end end // n1 -> n2 RX buffer overflow, middle of transmission TASK13: begin if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {24'h0, 4'h4, 4'h3}; n1_tx_data <= rand_dat; n1_tx_req <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat); if (word_counter) begin word_counter <= word_counter - 1; n1_tx_pend <= 1; end else begin n1_tx_pend <= 0; state <= TX_WAIT; end end else if (n1_tx_fail) begin state <= TX_WAIT; n1_tx_req <= 0; end end // n1 -> n0 RX buffer overflow, middle of transmission TASK14: begin if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {24'h0, 4'h2, 4'h9}; n1_tx_data <= rand_dat; n1_tx_req <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat); if (word_counter) begin word_counter <= word_counter - 1; n1_tx_pend <= 1; end else begin n1_tx_pend <= 0; state <= TX_WAIT; end end else if (n1_tx_fail) begin state <= TX_WAIT; n1_tx_req <= 0; end end // n1 -> n2 RX buffer overflow, last word TASK15: begin if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {24'h0, 4'h4, 4'h3}; n1_tx_data <= rand_dat; n1_tx_req <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat); if (word_counter) begin word_counter <= word_counter - 1; n1_tx_pend <= 1; end else begin n1_tx_pend <= 0; state <= TX_WAIT; end end end // n1 -> n0 RX buffer overflow, last word TASK16: begin if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {24'h0, 4'h2, 4'h9}; n1_tx_data <= rand_dat; n1_tx_req <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat); if (word_counter) begin word_counter <= word_counter - 1; n1_tx_pend <= 1; end else begin n1_tx_pend <= 0; state <= TX_WAIT; end end end // Arbitration test, both n0, n1 transmit to n3. // n0 transmits first TASK17: begin if ((~n0_tx_ack) & (~n0_tx_req)) begin n0_tx_addr <= {24'h0, 4'h5, 4'h8}; n0_tx_data <= rand_dat; n0_tx_pend <= 0; n0_tx_req <= 1; $fdisplay(handle, "N0 Data in =\t32'h%h", rand_dat); end if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {24'h0, 4'h5, 4'h3}; n1_tx_data <= rand_dat2; n1_tx_pend <= 0; n1_tx_req <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat2); end state <= TX_WAIT; end // Priority test1, both n0, n1 transmit to n3 // n1 sets priority, n1 transmits first TASK18: begin if ((~n0_tx_ack) & (~n0_tx_req)) begin n0_tx_addr <= {24'h0, 4'h5, 4'h8}; n0_tx_data <= rand_dat; n0_tx_pend <= 0; n0_tx_req <= 1; $fdisplay(handle, "N0 Data in =\t32'h%h", rand_dat); end if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {24'h0, 4'h5, 4'h3}; n1_tx_data <= rand_dat2; n1_tx_pend <= 0; n1_tx_req <= 1; n1_priority <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat2); end state <= TX_WAIT; end // Priority test2, both n0, n1 transmit to n3 // both sets priority. n0 transmits first TASK19: begin if ((~n0_tx_ack) & (~n0_tx_req)) begin n0_tx_addr <= {24'h0, 4'h5, 4'h8}; n0_tx_data <= rand_dat; n0_tx_pend <= 0; n0_tx_req <= 1; n0_priority <= 1; $fdisplay(handle, "N0 Data in =\t32'h%h", rand_dat); end if ((~n1_tx_ack) & (~n1_tx_req)) begin n1_tx_addr <= {24'h0, 4'h5, 4'h3}; n1_tx_data <= rand_dat2; n1_tx_pend <= 0; n1_tx_req <= 1; n1_priority <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat2); end state <= TX_WAIT; end // Priority test3, only n0 transmits with priority set TASK20: begin if ((~n0_tx_ack) & (~n0_tx_req)) begin n0_tx_addr <= {24'h0, 4'h5, 4'h3}; n0_tx_data <= rand_dat; n0_tx_pend <= 0; n0_tx_req <= 1; n0_priority <= 1; $fdisplay(handle, "N0 Data in =\t32'h%h", rand_dat); state <= TX_WAIT; end end // Sleep all TASK21: begin c0_tx_addr <= {28'hf00000, `CHANNEL_POWER}; c0_tx_data <= {`CMD_CHANNEL_POWER_ALL_SLEEP, 28'h0}; c0_tx_req <= 1; c0_tx_pend <= 0; c0_priority <= 0; state <= TX_WAIT; end // N2 asserts interrupt TASK22: begin n2_req_int <= 1; state <= TX_WAIT; end // n2 -> c0 using short address TASK23: begin n2_tx_addr <= {24'h0, 4'h1, 4'h3}; // 4'h3 is functional ID n2_tx_data <= rand_dat; n2_tx_req <= 1; n2_tx_pend <= 0; n2_priority <= 0; $fdisplay(handle, "N2 Data in =\t32'h%h", rand_dat); state <= TX_WAIT; end // All layers wake TASK24: begin c0_tx_addr <= {28'hf00000, `CHANNEL_POWER}; c0_tx_data <= {`CMD_CHANNEL_POWER_ALL_WAKE, 28'h0}; c0_tx_req <= 1; c0_tx_pend <= 0; c0_priority <= 0; state <= TX_WAIT; end // stuck on TX (too long messages) TASK25: begin if ((~n2_tx_ack) & (~n2_tx_req)) begin n2_tx_addr <= {24'h0, 4'h2, 4'h9}; n2_tx_data <= rand_dat; n2_tx_req <= 1; $fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat); n2_tx_pend <= 1; end else if (n2_tx_fail) begin state <= TX_WAIT; n2_tx_req <= 0; n2_tx_pend <= 0; end end endcase end end

// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [1:0] [3:0] [3:0] array_simp; // big endian array logic [3:0] array_oned; initial begin array_oned = '{2:1'b1, 0:1'b1, default:1'b0}; if (array_oned != 4'b0101) $stop; array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; if (array_simp[0] !== 16'h3210) $stop; // verilator lint_off WIDTH array_simp[0] = '{ 3 ,2 ,1, 0 }; // verilator lint_on WIDTH if (array_simp[0] !== 16'h3210) $stop; // Doesn't seem to work for unpacked arrays in other simulators //if (array_simp[0] !== 16'h3210) $stop; //array_simp[0] = '{ 1:4'd3, default:13}; //if (array_simp[0] !== 16'hDD3D) $stop; array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; if (array_simp !== 32'h3210_1234) $stop; // IEEE says '{} allowed only on assignments, not !=, ==. // Doesn't seem to work for unpacked arrays in other simulators array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; if (array_simp !== 32'h3210_3210) $stop; array_simp = '{2{ '{4{ 4'd3 }} }}; if (array_simp !== 32'h3333_3333) $stop; // Not legal in other simulators - replication doesn't match // However IEEE suggests this is legal. //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} $write("*-* All Finished *-*\n"); $finish; end //==================== // parameters for array sizes localparam WA = 4; // address dimension size localparam WB = 4; // bit dimension size localparam NO = 11; // number of access events // 2D packed arrays logic [WA-1:0] [WB-1:0] array_bg; // big endian array /* verilator lint_off LITENDIAN */ logic [0:WA-1] [0:WB-1] array_lt; // little endian array /* verilator lint_on LITENDIAN */ integer cnt = 0; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin $write("*-* All Finished *-*\n"); $finish; end // big endian always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) if (cnt[30:2]== 0) array_bg <= '0; else if (cnt[30:2]== 1) array_bg <= '0; else if (cnt[30:2]== 2) array_bg <= '0; else if (cnt[30:2]== 3) array_bg <= '0; else if (cnt[30:2]== 4) array_bg <= '0; else if (cnt[30:2]== 5) array_bg <= '0; else if (cnt[30:2]== 6) array_bg <= '0; else if (cnt[30:2]== 7) array_bg <= '0; else if (cnt[30:2]== 8) array_bg <= '0; else if (cnt[30:2]== 9) array_bg <= '0; else if (cnt[30:2]==10) array_bg <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]== 0) begin end else if (cnt[30:2]== 1) array_bg <= '{ 3 ,2 ,1, 0 }; else if (cnt[30:2]== 2) array_bg <= '{default:13}; else if (cnt[30:2]== 3) array_bg <= '{0:4, 1:5, 2:6, 3:7}; else if (cnt[30:2]== 4) array_bg <= '{2:15, default:13}; else if (cnt[30:2]== 5) array_bg <= '{WA { {WB/2 {2'b10}} }}; else if (cnt[30:2]== 6) array_bg <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; end else if (cnt[1:0]==2'd2) begin // chack array agains expected value if (cnt[30:2]== 0) begin if (array_bg !== 16'b0000000000000000) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]== 1) begin if (array_bg !== 16'b0011001000010000) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]== 2) begin if (array_bg !== 16'b1101110111011101) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]== 3) begin if (array_bg !== 16'b0111011001010100) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]== 4) begin if (array_bg !== 16'b1101111111011101) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]== 5) begin if (array_bg !== 16'b1010101010101010) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]== 6) begin if (array_bg !== 16'b1001101010111100) begin $display("%b", array_bg); $stop(); end end end // little endian always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) if (cnt[30:2]== 0) array_lt <= '0; else if (cnt[30:2]== 1) array_lt <= '0; else if (cnt[30:2]== 2) array_lt <= '0; else if (cnt[30:2]== 3) array_lt <= '0; else if (cnt[30:2]== 4) array_lt <= '0; else if (cnt[30:2]== 5) array_lt <= '0; else if (cnt[30:2]== 6) array_lt <= '0; else if (cnt[30:2]== 7) array_lt <= '0; else if (cnt[30:2]== 8) array_lt <= '0; else if (cnt[30:2]== 9) array_lt <= '0; else if (cnt[30:2]==10) array_lt <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]== 0) begin end else if (cnt[30:2]== 1) array_lt <= '{ 3 ,2 ,1, 0 }; else if (cnt[30:2]== 2) array_lt <= '{default:13}; else if (cnt[30:2]== 3) array_lt <= '{3:4, 2:5, 1:6, 0:7}; else if (cnt[30:2]== 4) array_lt <= '{1:15, default:13}; else if (cnt[30:2]== 5) array_lt <= '{WA { {WB/2 {2'b10}} }}; else if (cnt[30:2]==10) array_lt <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; end else if (cnt[1:0]==2'd2) begin // chack array agains expected value if (cnt[30:2]== 0) begin if (array_lt !== 16'b0000000000000000) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]== 1) begin if (array_lt !== 16'b0011001000010000) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]== 2) begin if (array_lt !== 16'b1101110111011101) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]== 3) begin if (array_lt !== 16'b0111011001010100) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]== 4) begin if (array_lt !== 16'b1101111111011101) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]== 5) begin if (array_lt !== 16'b1010101010101010) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]==10) begin if (array_lt !== 16'b1001101010111100) begin $display("%b", array_lt); $stop(); end end end endmodule

`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 21:01:37 04/27/2014 // Design Name: Image_viewer_top // Module Name: /home/student/Dropbox/EE 201 Final Project/SynchronousRead/top_tb.v // Project Name: SynchronousRead // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: Image_viewer_top // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module top_tb; // Inputs reg ClkPort; reg btnC; reg btnR; reg btnL; // Outputs wire Hsync; wire Vsync; wire [2:0] vgaRed; wire [2:0] vgaGreen; wire [2:1] vgaBlue; wire MemOE; wire MemWR; wire MemClk; wire RamCS; wire RamUB; wire RamLB; wire RamAdv; wire RamCRE; wire [26:1] MemAdr; wire An0; wire An1; wire An2; wire An3; wire Ca; wire Cb; wire Cc; wire Cd; wire Ce; wire Cf; wire Cg; wire Dp; wire [1:0] Led; // Bidirs wire [15:0] data; // Instantiate the Unit Under Test (UUT) Image_viewer_top uut ( .ClkPort(ClkPort), .Hsync(Hsync), .Vsync(Vsync), .vgaRed(vgaRed), .vgaGreen(vgaGreen), .vgaBlue(vgaBlue), .MemOE(MemOE), .MemWR(MemWR), .MemClk(MemClk), .RamCS(RamCS), .RamUB(RamUB), .RamLB(RamLB), .RamAdv(RamAdv), .RamCRE(RamCRE), .MemAdr(MemAdr), .data(data), .An0(An0), .An1(An1), .An2(An2), .An3(An3), .Ca(Ca), .Cb(Cb), .Cc(Cc), .Cd(Cd), .Ce(Ce), .Cf(Cf), .Cg(Cg), .Dp(Dp), .Led(Led), .btnC(btnC), .btnR(btnR), .btnL(btnL) ); initial begin ClkPort = 0; forever #5 ClkPort = ~ClkPort; end initial begin // Initialize Inputs btnC = 1; btnR = 0; btnL = 0; // Wait 100 ns for global reset to finish #100; btnC = 0; // Add stimulus here end endmodule

/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__AND4_SYMBOL_V `define SKY130_FD_SC_LP__AND4_SYMBOL_V /** * and4: 4-input AND. * * Verilog stub (without power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_lp__and4 ( //# {{data|Data Signals}} input A, input B, input C, input D, output X ); // Voltage supply signals supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; endmodule `default_nettype wire `endif // SKY130_FD_SC_LP__AND4_SYMBOL_V

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V `define SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V /** * a222oi: 2-input AND into all inputs of 3-input NOR. * * Y = !((A1 & A2) | (B1 & B2) | (C1 & C2)) * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none `celldefine module sky130_fd_sc_hd__a222oi ( Y , A1, A2, B1, B2, C1, C2 ); // Module ports output Y ; input A1; input A2; input B1; input B2; input C1; input C2; // Module supplies supply1 VPWR; supply0 VGND; supply1 VPB ; supply0 VNB ; // Local signals wire nand0_out ; wire nand1_out ; wire nand2_out ; wire and0_out_Y; // Name Output Other arguments nand nand0 (nand0_out , A2, A1 ); nand nand1 (nand1_out , B2, B1 ); nand nand2 (nand2_out , C2, C1 ); and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out); buf buf0 (Y , and0_out_Y ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V