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// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: AXI3 Slave Converter // This module instantiates Address, Write Data and Read Data AXI3 Converter // modules, each one taking care of the channel specific tasks. // The Address AXI3 converter can handle both AR and AW channels. // The Write Respons Channel is reused from the Down-Sizer. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // axi3_conv // a_axi3_conv // axic_fifo // w_axi3_conv // b_downsizer // r_axi3_conv // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_axi3_conv # ( parameter C_FAMILY = "none", parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_SUPPORTS_WRITE = 1, parameter integer C_AXI_SUPPORTS_READ = 1, parameter integer C_SUPPORT_SPLITTING = 1, // Implement transaction splitting logic. // Disabled whan all connected masters are AXI3 and have same or narrower data width. parameter integer C_SUPPORT_BURSTS = 1, // Disabled when all connected masters are AxiLite, // allowing logic to be simplified. parameter integer C_SINGLE_THREAD = 1 // 0 = Ignore ID when propagating transactions (assume all responses are in order). // 1 = Enforce single-threading (one ID at a time) when any outstanding or // requested transaction requires splitting. // While no split is ongoing any new non-split transaction will pass immediately regardless // off ID. // A split transaction will stall if there are multiple ID (non-split) transactions // ongoing, once it has been forwarded only transactions with the same ID is allowed // (split or not) until all ongoing split transactios has been completed. ) ( // System Signals input wire ACLK, input wire ARESETN, // Slave Interface Write Address Ports input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [8-1:0] S_AXI_AWLEN, input wire [3-1:0] S_AXI_AWSIZE, input wire [2-1:0] S_AXI_AWBURST, input wire [1-1:0] S_AXI_AWLOCK, input wire [4-1:0] S_AXI_AWCACHE, input wire [3-1:0] S_AXI_AWPROT, input wire [4-1:0] S_AXI_AWQOS, input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, // Slave Interface Write Data Ports input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire S_AXI_WLAST, input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire S_AXI_WVALID, output wire S_AXI_WREADY, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, output wire [2-1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, // Slave Interface Read Address Ports input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, input wire [8-1:0] S_AXI_ARLEN, input wire [3-1:0] S_AXI_ARSIZE, input wire [2-1:0] S_AXI_ARBURST, input wire [1-1:0] S_AXI_ARLOCK, input wire [4-1:0] S_AXI_ARCACHE, input wire [3-1:0] S_AXI_ARPROT, input wire [4-1:0] S_AXI_ARQOS, input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, input wire S_AXI_ARVALID, output wire S_AXI_ARREADY, // Slave Interface Read Data Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID, output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, output wire [2-1:0] S_AXI_RRESP, output wire S_AXI_RLAST, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RVALID, input wire S_AXI_RREADY, // Master Interface Write Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [4-1:0] M_AXI_AWLEN, output wire [3-1:0] M_AXI_AWSIZE, output wire [2-1:0] M_AXI_AWBURST, output wire [2-1:0] M_AXI_AWLOCK, output wire [4-1:0] M_AXI_AWCACHE, output wire [3-1:0] M_AXI_AWPROT, output wire [4-1:0] M_AXI_AWQOS, output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire M_AXI_AWVALID, input wire M_AXI_AWREADY, // Master Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID, output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire M_AXI_WLAST, output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire M_AXI_WVALID, input wire M_AXI_WREADY, // Master Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, input wire [2-1:0] M_AXI_BRESP, input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire M_AXI_BVALID, output wire M_AXI_BREADY, // Master Interface Read Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID, output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, output wire [4-1:0] M_AXI_ARLEN, output wire [3-1:0] M_AXI_ARSIZE, output wire [2-1:0] M_AXI_ARBURST, output wire [2-1:0] M_AXI_ARLOCK, output wire [4-1:0] M_AXI_ARCACHE, output wire [3-1:0] M_AXI_ARPROT, output wire [4-1:0] M_AXI_ARQOS, output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, output wire M_AXI_ARVALID, input wire M_AXI_ARREADY, // Master Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID, input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, input wire [2-1:0] M_AXI_RRESP, input wire M_AXI_RLAST, input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, input wire M_AXI_RVALID, output wire M_AXI_RREADY ); ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Handle Write Channels (AW/W/B) ///////////////////////////////////////////////////////////////////////////// generate if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE // Write Channel Signals for Commands Queue Interface. wire wr_cmd_valid; wire [C_AXI_ID_WIDTH-1:0] wr_cmd_id; wire [4-1:0] wr_cmd_length; wire wr_cmd_ready; wire wr_cmd_b_valid; wire wr_cmd_b_split; wire [4-1:0] wr_cmd_b_repeat; wire wr_cmd_b_ready; // Write Address Channel. axi_protocol_converter_v2_1_a_axi3_conv # ( .C_FAMILY (C_FAMILY), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AUSER_WIDTH (C_AXI_AWUSER_WIDTH), .C_AXI_CHANNEL (0), .C_SUPPORT_SPLITTING (C_SUPPORT_SPLITTING), .C_SUPPORT_BURSTS (C_SUPPORT_BURSTS), .C_SINGLE_THREAD (C_SINGLE_THREAD) ) write_addr_inst ( // Global Signals .ARESET (~ARESETN), .ACLK (ACLK), // Command Interface (W) .cmd_valid (wr_cmd_valid), .cmd_split (), .cmd_id (wr_cmd_id), .cmd_length (wr_cmd_length), .cmd_ready (wr_cmd_ready), // Command Interface (B) .cmd_b_valid (wr_cmd_b_valid), .cmd_b_split (wr_cmd_b_split), .cmd_b_repeat (wr_cmd_b_repeat), .cmd_b_ready (wr_cmd_b_ready), // Slave Interface Write Address Ports .S_AXI_AID (S_AXI_AWID), .S_AXI_AADDR (S_AXI_AWADDR), .S_AXI_ALEN (S_AXI_AWLEN), .S_AXI_ASIZE (S_AXI_AWSIZE), .S_AXI_ABURST (S_AXI_AWBURST), .S_AXI_ALOCK (S_AXI_AWLOCK), .S_AXI_ACACHE (S_AXI_AWCACHE), .S_AXI_APROT (S_AXI_AWPROT), .S_AXI_AQOS (S_AXI_AWQOS), .S_AXI_AUSER (S_AXI_AWUSER), .S_AXI_AVALID (S_AXI_AWVALID), .S_AXI_AREADY (S_AXI_AWREADY), // Master Interface Write Address Port .M_AXI_AID (M_AXI_AWID), .M_AXI_AADDR (M_AXI_AWADDR), .M_AXI_ALEN (M_AXI_AWLEN), .M_AXI_ASIZE (M_AXI_AWSIZE), .M_AXI_ABURST (M_AXI_AWBURST), .M_AXI_ALOCK (M_AXI_AWLOCK), .M_AXI_ACACHE (M_AXI_AWCACHE), .M_AXI_APROT (M_AXI_AWPROT), .M_AXI_AQOS (M_AXI_AWQOS), .M_AXI_AUSER (M_AXI_AWUSER), .M_AXI_AVALID (M_AXI_AWVALID), .M_AXI_AREADY (M_AXI_AWREADY) ); // Write Data Channel. axi_protocol_converter_v2_1_w_axi3_conv # ( .C_FAMILY (C_FAMILY), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH), .C_SUPPORT_SPLITTING (C_SUPPORT_SPLITTING), .C_SUPPORT_BURSTS (C_SUPPORT_BURSTS) ) write_data_inst ( // Global Signals .ARESET (~ARESETN), .ACLK (ACLK), // Command Interface .cmd_valid (wr_cmd_valid), .cmd_id (wr_cmd_id), .cmd_length (wr_cmd_length), .cmd_ready (wr_cmd_ready), // Slave Interface Write Data Ports .S_AXI_WDATA (S_AXI_WDATA), .S_AXI_WSTRB (S_AXI_WSTRB), .S_AXI_WLAST (S_AXI_WLAST), .S_AXI_WUSER (S_AXI_WUSER), .S_AXI_WVALID (S_AXI_WVALID), .S_AXI_WREADY (S_AXI_WREADY), // Master Interface Write Data Ports .M_AXI_WID (M_AXI_WID), .M_AXI_WDATA (M_AXI_WDATA), .M_AXI_WSTRB (M_AXI_WSTRB), .M_AXI_WLAST (M_AXI_WLAST), .M_AXI_WUSER (M_AXI_WUSER), .M_AXI_WVALID (M_AXI_WVALID), .M_AXI_WREADY (M_AXI_WREADY) ); if ( C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_SPLIT_W // Write Data Response Channel. axi_protocol_converter_v2_1_b_downsizer # ( .C_FAMILY (C_FAMILY), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH) ) write_resp_inst ( // Global Signals .ARESET (~ARESETN), .ACLK (ACLK), // Command Interface .cmd_valid (wr_cmd_b_valid), .cmd_split (wr_cmd_b_split), .cmd_repeat (wr_cmd_b_repeat), .cmd_ready (wr_cmd_b_ready), // Slave Interface Write Response Ports .S_AXI_BID (S_AXI_BID), .S_AXI_BRESP (S_AXI_BRESP), .S_AXI_BUSER (S_AXI_BUSER), .S_AXI_BVALID (S_AXI_BVALID), .S_AXI_BREADY (S_AXI_BREADY), // Master Interface Write Response Ports .M_AXI_BID (M_AXI_BID), .M_AXI_BRESP (M_AXI_BRESP), .M_AXI_BUSER (M_AXI_BUSER), .M_AXI_BVALID (M_AXI_BVALID), .M_AXI_BREADY (M_AXI_BREADY) ); end else begin : NO_SPLIT_W // MI -> SI Interface Write Response Ports assign S_AXI_BID = M_AXI_BID; assign S_AXI_BRESP = M_AXI_BRESP; assign S_AXI_BUSER = M_AXI_BUSER; assign S_AXI_BVALID = M_AXI_BVALID; assign M_AXI_BREADY = S_AXI_BREADY; end end else begin : NO_WRITE // Slave Interface Write Address Ports assign S_AXI_AWREADY = 1'b0; // Slave Interface Write Data Ports assign S_AXI_WREADY = 1'b0; // Slave Interface Write Response Ports assign S_AXI_BID = {C_AXI_ID_WIDTH{1'b0}}; assign S_AXI_BRESP = 2'b0; assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}}; assign S_AXI_BVALID = 1'b0; // Master Interface Write Address Port assign M_AXI_AWID = {C_AXI_ID_WIDTH{1'b0}}; assign M_AXI_AWADDR = {C_AXI_ADDR_WIDTH{1'b0}}; assign M_AXI_AWLEN = 4'b0; assign M_AXI_AWSIZE = 3'b0; assign M_AXI_AWBURST = 2'b0; assign M_AXI_AWLOCK = 2'b0; assign M_AXI_AWCACHE = 4'b0; assign M_AXI_AWPROT = 3'b0; assign M_AXI_AWQOS = 4'b0; assign M_AXI_AWUSER = {C_AXI_AWUSER_WIDTH{1'b0}}; assign M_AXI_AWVALID = 1'b0; // Master Interface Write Data Ports assign M_AXI_WDATA = {C_AXI_DATA_WIDTH{1'b0}}; assign M_AXI_WSTRB = {C_AXI_DATA_WIDTH/8{1'b0}}; assign M_AXI_WLAST = 1'b0; assign M_AXI_WUSER = {C_AXI_WUSER_WIDTH{1'b0}}; assign M_AXI_WVALID = 1'b0; // Master Interface Write Response Ports assign M_AXI_BREADY = 1'b0; end endgenerate ///////////////////////////////////////////////////////////////////////////// // Handle Read Channels (AR/R) ///////////////////////////////////////////////////////////////////////////// generate if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ // Write Response channel. if ( C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_SPLIT_R // Read Channel Signals for Commands Queue Interface. wire rd_cmd_valid; wire rd_cmd_split; wire rd_cmd_ready; // Write Address Channel. axi_protocol_converter_v2_1_a_axi3_conv # ( .C_FAMILY (C_FAMILY), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_AUSER_WIDTH (C_AXI_ARUSER_WIDTH), .C_AXI_CHANNEL (1), .C_SUPPORT_SPLITTING (C_SUPPORT_SPLITTING), .C_SUPPORT_BURSTS (C_SUPPORT_BURSTS), .C_SINGLE_THREAD (C_SINGLE_THREAD) ) read_addr_inst ( // Global Signals .ARESET (~ARESETN), .ACLK (ACLK), // Command Interface (R) .cmd_valid (rd_cmd_valid), .cmd_split (rd_cmd_split), .cmd_id (), .cmd_length (), .cmd_ready (rd_cmd_ready), // Command Interface (B) .cmd_b_valid (), .cmd_b_split (), .cmd_b_repeat (), .cmd_b_ready (1'b0), // Slave Interface Write Address Ports .S_AXI_AID (S_AXI_ARID), .S_AXI_AADDR (S_AXI_ARADDR), .S_AXI_ALEN (S_AXI_ARLEN), .S_AXI_ASIZE (S_AXI_ARSIZE), .S_AXI_ABURST (S_AXI_ARBURST), .S_AXI_ALOCK (S_AXI_ARLOCK), .S_AXI_ACACHE (S_AXI_ARCACHE), .S_AXI_APROT (S_AXI_ARPROT), .S_AXI_AQOS (S_AXI_ARQOS), .S_AXI_AUSER (S_AXI_ARUSER), .S_AXI_AVALID (S_AXI_ARVALID), .S_AXI_AREADY (S_AXI_ARREADY), // Master Interface Write Address Port .M_AXI_AID (M_AXI_ARID), .M_AXI_AADDR (M_AXI_ARADDR), .M_AXI_ALEN (M_AXI_ARLEN), .M_AXI_ASIZE (M_AXI_ARSIZE), .M_AXI_ABURST (M_AXI_ARBURST), .M_AXI_ALOCK (M_AXI_ARLOCK), .M_AXI_ACACHE (M_AXI_ARCACHE), .M_AXI_APROT (M_AXI_ARPROT), .M_AXI_AQOS (M_AXI_ARQOS), .M_AXI_AUSER (M_AXI_ARUSER), .M_AXI_AVALID (M_AXI_ARVALID), .M_AXI_AREADY (M_AXI_ARREADY) ); // Read Data Channel. axi_protocol_converter_v2_1_r_axi3_conv # ( .C_FAMILY (C_FAMILY), .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS), .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH), .C_SUPPORT_SPLITTING (C_SUPPORT_SPLITTING), .C_SUPPORT_BURSTS (C_SUPPORT_BURSTS) ) read_data_inst ( // Global Signals .ARESET (~ARESETN), .ACLK (ACLK), // Command Interface .cmd_valid (rd_cmd_valid), .cmd_split (rd_cmd_split), .cmd_ready (rd_cmd_ready), // Slave Interface Read Data Ports .S_AXI_RID (S_AXI_RID), .S_AXI_RDATA (S_AXI_RDATA), .S_AXI_RRESP (S_AXI_RRESP), .S_AXI_RLAST (S_AXI_RLAST), .S_AXI_RUSER (S_AXI_RUSER), .S_AXI_RVALID (S_AXI_RVALID), .S_AXI_RREADY (S_AXI_RREADY), // Master Interface Read Data Ports .M_AXI_RID (M_AXI_RID), .M_AXI_RDATA (M_AXI_RDATA), .M_AXI_RRESP (M_AXI_RRESP), .M_AXI_RLAST (M_AXI_RLAST), .M_AXI_RUSER (M_AXI_RUSER), .M_AXI_RVALID (M_AXI_RVALID), .M_AXI_RREADY (M_AXI_RREADY) ); end else begin : NO_SPLIT_R // SI -> MI Interface Write Address Port assign M_AXI_ARID = S_AXI_ARID; assign M_AXI_ARADDR = S_AXI_ARADDR; assign M_AXI_ARLEN = S_AXI_ARLEN; assign M_AXI_ARSIZE = S_AXI_ARSIZE; assign M_AXI_ARBURST = S_AXI_ARBURST; assign M_AXI_ARLOCK = S_AXI_ARLOCK; assign M_AXI_ARCACHE = S_AXI_ARCACHE; assign M_AXI_ARPROT = S_AXI_ARPROT; assign M_AXI_ARQOS = S_AXI_ARQOS; assign M_AXI_ARUSER = S_AXI_ARUSER; assign M_AXI_ARVALID = S_AXI_ARVALID; assign S_AXI_ARREADY = M_AXI_ARREADY; // MI -> SI Interface Read Data Ports assign S_AXI_RID = M_AXI_RID; assign S_AXI_RDATA = M_AXI_RDATA; assign S_AXI_RRESP = M_AXI_RRESP; assign S_AXI_RLAST = M_AXI_RLAST; assign S_AXI_RUSER = M_AXI_RUSER; assign S_AXI_RVALID = M_AXI_RVALID; assign M_AXI_RREADY = S_AXI_RREADY; end end else begin : NO_READ // Slave Interface Read Address Ports assign S_AXI_ARREADY = 1'b0; // Slave Interface Read Data Ports assign S_AXI_RID = {C_AXI_ID_WIDTH{1'b0}}; assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}}; assign S_AXI_RRESP = 2'b0; assign S_AXI_RLAST = 1'b0; assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}}; assign S_AXI_RVALID = 1'b0; // Master Interface Read Address Port assign M_AXI_ARID = {C_AXI_ID_WIDTH{1'b0}}; assign M_AXI_ARADDR = {C_AXI_ADDR_WIDTH{1'b0}}; assign M_AXI_ARLEN = 4'b0; assign M_AXI_ARSIZE = 3'b0; assign M_AXI_ARBURST = 2'b0; assign M_AXI_ARLOCK = 2'b0; assign M_AXI_ARCACHE = 4'b0; assign M_AXI_ARPROT = 3'b0; assign M_AXI_ARQOS = 4'b0; assign M_AXI_ARUSER = {C_AXI_ARUSER_WIDTH{1'b0}}; assign M_AXI_ARVALID = 1'b0; // Master Interface Read Data Ports assign M_AXI_RREADY = 1'b0; end endgenerate endmodule
// (C) 2001-2015 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $Id: //acds/rel/15.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ // $Revision: #1 $ // $Date: 2015/08/09 $ // $Author: swbranch $ // ----------------------------------------------- // Reset Synchronizer // ----------------------------------------------- `timescale 1 ns / 1 ns module altera_reset_synchronizer #( parameter ASYNC_RESET = 1, parameter DEPTH = 2 ) ( input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, input clk, output reset_out ); // ----------------------------------------------- // Synchronizer register chain. We cannot reuse the // standard synchronizer in this implementation // because our timing constraints are different. // // Instead of cutting the timing path to the d-input // on the first flop we need to cut the aclr input. // // We omit the "preserve" attribute on the final // output register, so that the synthesis tool can // duplicate it where needed. // ----------------------------------------------- (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; reg altera_reset_synchronizer_int_chain_out; generate if (ASYNC_RESET) begin // ----------------------------------------------- // Assert asynchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk or posedge reset_in) begin if (reset_in) begin altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; altera_reset_synchronizer_int_chain_out <= 1'b1; end else begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end end assign reset_out = altera_reset_synchronizer_int_chain_out; end else begin // ----------------------------------------------- // Assert synchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk) begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end assign reset_out = altera_reset_synchronizer_int_chain_out; end endgenerate endmodule
// (C) 2001-2015 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $Id: //acds/rel/15.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ // $Revision: #1 $ // $Date: 2015/08/09 $ // $Author: swbranch $ // ----------------------------------------------- // Reset Synchronizer // ----------------------------------------------- `timescale 1 ns / 1 ns module altera_reset_synchronizer #( parameter ASYNC_RESET = 1, parameter DEPTH = 2 ) ( input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, input clk, output reset_out ); // ----------------------------------------------- // Synchronizer register chain. We cannot reuse the // standard synchronizer in this implementation // because our timing constraints are different. // // Instead of cutting the timing path to the d-input // on the first flop we need to cut the aclr input. // // We omit the "preserve" attribute on the final // output register, so that the synthesis tool can // duplicate it where needed. // ----------------------------------------------- (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; reg altera_reset_synchronizer_int_chain_out; generate if (ASYNC_RESET) begin // ----------------------------------------------- // Assert asynchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk or posedge reset_in) begin if (reset_in) begin altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; altera_reset_synchronizer_int_chain_out <= 1'b1; end else begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end end assign reset_out = altera_reset_synchronizer_int_chain_out; end else begin // ----------------------------------------------- // Assert synchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk) begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end assign reset_out = altera_reset_synchronizer_int_chain_out; end endgenerate endmodule
// (C) 2001-2015 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $Id: //acds/rel/15.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ // $Revision: #1 $ // $Date: 2015/08/09 $ // $Author: swbranch $ // ----------------------------------------------- // Reset Synchronizer // ----------------------------------------------- `timescale 1 ns / 1 ns module altera_reset_synchronizer #( parameter ASYNC_RESET = 1, parameter DEPTH = 2 ) ( input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, input clk, output reset_out ); // ----------------------------------------------- // Synchronizer register chain. We cannot reuse the // standard synchronizer in this implementation // because our timing constraints are different. // // Instead of cutting the timing path to the d-input // on the first flop we need to cut the aclr input. // // We omit the "preserve" attribute on the final // output register, so that the synthesis tool can // duplicate it where needed. // ----------------------------------------------- (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; reg altera_reset_synchronizer_int_chain_out; generate if (ASYNC_RESET) begin // ----------------------------------------------- // Assert asynchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk or posedge reset_in) begin if (reset_in) begin altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; altera_reset_synchronizer_int_chain_out <= 1'b1; end else begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end end assign reset_out = altera_reset_synchronizer_int_chain_out; end else begin // ----------------------------------------------- // Assert synchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk) begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end assign reset_out = altera_reset_synchronizer_int_chain_out; end endgenerate endmodule
// (C) 2001-2015 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $Id: //acds/rel/15.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ // $Revision: #1 $ // $Date: 2015/08/09 $ // $Author: swbranch $ // ----------------------------------------------- // Reset Synchronizer // ----------------------------------------------- `timescale 1 ns / 1 ns module altera_reset_synchronizer #( parameter ASYNC_RESET = 1, parameter DEPTH = 2 ) ( input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, input clk, output reset_out ); // ----------------------------------------------- // Synchronizer register chain. We cannot reuse the // standard synchronizer in this implementation // because our timing constraints are different. // // Instead of cutting the timing path to the d-input // on the first flop we need to cut the aclr input. // // We omit the "preserve" attribute on the final // output register, so that the synthesis tool can // duplicate it where needed. // ----------------------------------------------- (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; reg altera_reset_synchronizer_int_chain_out; generate if (ASYNC_RESET) begin // ----------------------------------------------- // Assert asynchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk or posedge reset_in) begin if (reset_in) begin altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; altera_reset_synchronizer_int_chain_out <= 1'b1; end else begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end end assign reset_out = altera_reset_synchronizer_int_chain_out; end else begin // ----------------------------------------------- // Assert synchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk) begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end assign reset_out = altera_reset_synchronizer_int_chain_out; end endgenerate endmodule
// (C) 2001-2015 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $ // $Revision: #1 $ // $Date: 2015/08/09 $ // $Author: swbranch $ //------------------------------------------------------------------------------ `timescale 1ns / 1ns module altera_avalon_st_pipeline_base ( clk, reset, in_ready, in_valid, in_data, out_ready, out_valid, out_data ); parameter SYMBOLS_PER_BEAT = 1; parameter BITS_PER_SYMBOL = 8; parameter PIPELINE_READY = 1; localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL; input clk; input reset; output in_ready; input in_valid; input [DATA_WIDTH-1:0] in_data; input out_ready; output out_valid; output [DATA_WIDTH-1:0] out_data; reg full0; reg full1; reg [DATA_WIDTH-1:0] data0; reg [DATA_WIDTH-1:0] data1; assign out_valid = full1; assign out_data = data1; generate if (PIPELINE_READY == 1) begin : REGISTERED_READY_PLINE assign in_ready = !full0; always @(posedge clk, posedge reset) begin if (reset) begin data0 <= {DATA_WIDTH{1'b0}}; data1 <= {DATA_WIDTH{1'b0}}; end else begin // ---------------------------- // always load the second slot if we can // ---------------------------- if (~full0) data0 <= in_data; // ---------------------------- // first slot is loaded either from the second, // or with new data // ---------------------------- if (~full1 || (out_ready && out_valid)) begin if (full0) data1 <= data0; else data1 <= in_data; end end end always @(posedge clk or posedge reset) begin if (reset) begin full0 <= 1'b0; full1 <= 1'b0; end else begin // no data in pipeline if (~full0 & ~full1) begin if (in_valid) begin full1 <= 1'b1; end end // ~f1 & ~f0 // one datum in pipeline if (full1 & ~full0) begin if (in_valid & ~out_ready) begin full0 <= 1'b1; end // back to empty if (~in_valid & out_ready) begin full1 <= 1'b0; end end // f1 & ~f0 // two data in pipeline if (full1 & full0) begin // go back to one datum state if (out_ready) begin full0 <= 1'b0; end end // end go back to one datum stage end end end else begin : UNREGISTERED_READY_PLINE // in_ready will be a pass through of the out_ready signal as it is not registered assign in_ready = (~full1) | out_ready; always @(posedge clk or posedge reset) begin if (reset) begin data1 <= 'b0; full1 <= 1'b0; end else begin if (in_ready) begin data1 <= in_data; full1 <= in_valid; end end end end endgenerate endmodule
// (C) 2001-2015 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $ // $Revision: #1 $ // $Date: 2015/08/09 $ // $Author: swbranch $ //------------------------------------------------------------------------------ `timescale 1ns / 1ns module altera_avalon_st_pipeline_base ( clk, reset, in_ready, in_valid, in_data, out_ready, out_valid, out_data ); parameter SYMBOLS_PER_BEAT = 1; parameter BITS_PER_SYMBOL = 8; parameter PIPELINE_READY = 1; localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL; input clk; input reset; output in_ready; input in_valid; input [DATA_WIDTH-1:0] in_data; input out_ready; output out_valid; output [DATA_WIDTH-1:0] out_data; reg full0; reg full1; reg [DATA_WIDTH-1:0] data0; reg [DATA_WIDTH-1:0] data1; assign out_valid = full1; assign out_data = data1; generate if (PIPELINE_READY == 1) begin : REGISTERED_READY_PLINE assign in_ready = !full0; always @(posedge clk, posedge reset) begin if (reset) begin data0 <= {DATA_WIDTH{1'b0}}; data1 <= {DATA_WIDTH{1'b0}}; end else begin // ---------------------------- // always load the second slot if we can // ---------------------------- if (~full0) data0 <= in_data; // ---------------------------- // first slot is loaded either from the second, // or with new data // ---------------------------- if (~full1 || (out_ready && out_valid)) begin if (full0) data1 <= data0; else data1 <= in_data; end end end always @(posedge clk or posedge reset) begin if (reset) begin full0 <= 1'b0; full1 <= 1'b0; end else begin // no data in pipeline if (~full0 & ~full1) begin if (in_valid) begin full1 <= 1'b1; end end // ~f1 & ~f0 // one datum in pipeline if (full1 & ~full0) begin if (in_valid & ~out_ready) begin full0 <= 1'b1; end // back to empty if (~in_valid & out_ready) begin full1 <= 1'b0; end end // f1 & ~f0 // two data in pipeline if (full1 & full0) begin // go back to one datum state if (out_ready) begin full0 <= 1'b0; end end // end go back to one datum stage end end end else begin : UNREGISTERED_READY_PLINE // in_ready will be a pass through of the out_ready signal as it is not registered assign in_ready = (~full1) | out_ready; always @(posedge clk or posedge reset) begin if (reset) begin data1 <= 'b0; full1 <= 1'b0; end else begin if (in_ready) begin data1 <= in_data; full1 <= in_valid; end end end end endgenerate endmodule
// (C) 2001-2015 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $ // $Revision: #1 $ // $Date: 2015/08/09 $ // $Author: swbranch $ //------------------------------------------------------------------------------ `timescale 1ns / 1ns module altera_avalon_st_pipeline_base ( clk, reset, in_ready, in_valid, in_data, out_ready, out_valid, out_data ); parameter SYMBOLS_PER_BEAT = 1; parameter BITS_PER_SYMBOL = 8; parameter PIPELINE_READY = 1; localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL; input clk; input reset; output in_ready; input in_valid; input [DATA_WIDTH-1:0] in_data; input out_ready; output out_valid; output [DATA_WIDTH-1:0] out_data; reg full0; reg full1; reg [DATA_WIDTH-1:0] data0; reg [DATA_WIDTH-1:0] data1; assign out_valid = full1; assign out_data = data1; generate if (PIPELINE_READY == 1) begin : REGISTERED_READY_PLINE assign in_ready = !full0; always @(posedge clk, posedge reset) begin if (reset) begin data0 <= {DATA_WIDTH{1'b0}}; data1 <= {DATA_WIDTH{1'b0}}; end else begin // ---------------------------- // always load the second slot if we can // ---------------------------- if (~full0) data0 <= in_data; // ---------------------------- // first slot is loaded either from the second, // or with new data // ---------------------------- if (~full1 || (out_ready && out_valid)) begin if (full0) data1 <= data0; else data1 <= in_data; end end end always @(posedge clk or posedge reset) begin if (reset) begin full0 <= 1'b0; full1 <= 1'b0; end else begin // no data in pipeline if (~full0 & ~full1) begin if (in_valid) begin full1 <= 1'b1; end end // ~f1 & ~f0 // one datum in pipeline if (full1 & ~full0) begin if (in_valid & ~out_ready) begin full0 <= 1'b1; end // back to empty if (~in_valid & out_ready) begin full1 <= 1'b0; end end // f1 & ~f0 // two data in pipeline if (full1 & full0) begin // go back to one datum state if (out_ready) begin full0 <= 1'b0; end end // end go back to one datum stage end end end else begin : UNREGISTERED_READY_PLINE // in_ready will be a pass through of the out_ready signal as it is not registered assign in_ready = (~full1) | out_ready; always @(posedge clk or posedge reset) begin if (reset) begin data1 <= 'b0; full1 <= 1'b0; end else begin if (in_ready) begin data1 <= in_data; full1 <= in_valid; end end end end endgenerate endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Address Write Channel for ATC // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // aw_atc // //-------------------------------------------------------------------------- `timescale 1ps/1ps module processing_system7_v5_5_aw_atc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6, spartan6 or later. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of checker. // Range: >= 1. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of all ADDR signals on SI and MI side of checker. // Range: 32. parameter integer C_AXI_AWUSER_WIDTH = 1, // Width of AWUSER signals. // Range: >= 1. parameter integer C_FIFO_DEPTH_LOG = 4 ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface output reg cmd_w_valid, output wire cmd_w_check, output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id, input wire cmd_w_ready, input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, input wire cmd_b_ready, // Slave Interface Write Address Port input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [4-1:0] S_AXI_AWLEN, input wire [3-1:0] S_AXI_AWSIZE, input wire [2-1:0] S_AXI_AWBURST, input wire [2-1:0] S_AXI_AWLOCK, input wire [4-1:0] S_AXI_AWCACHE, input wire [3-1:0] S_AXI_AWPROT, input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, // Master Interface Write Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [4-1:0] M_AXI_AWLEN, output wire [3-1:0] M_AXI_AWSIZE, output wire [2-1:0] M_AXI_AWBURST, output wire [2-1:0] M_AXI_AWLOCK, output wire [4-1:0] M_AXI_AWCACHE, output wire [3-1:0] M_AXI_AWPROT, output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire M_AXI_AWVALID, input wire M_AXI_AWREADY ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for burst types. localparam [2-1:0] C_FIX_BURST = 2'b00; localparam [2-1:0] C_INCR_BURST = 2'b01; localparam [2-1:0] C_WRAP_BURST = 2'b10; // Constants for size. localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011; // Constants for length. localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011; // Constants for cacheline address. localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0; // Command FIFO settings localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// integer index; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Transaction properties. wire access_is_incr; wire access_is_wrap; wire access_is_coherent; wire access_optimized_size; wire incr_addr_boundary; wire incr_is_optimized; wire wrap_is_optimized; wire access_is_optimized; // Command FIFO. wire cmd_w_push; reg cmd_full; reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr; reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; ///////////////////////////////////////////////////////////////////////////// // Transaction Decode: // // Detect if transaction is of correct typ, size and length to qualify as // an optimized transaction that has to be checked for errors. // ///////////////////////////////////////////////////////////////////////////// // Transaction burst type. assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST ); assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST ); // Transaction has to be Coherent. assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) & ( S_AXI_AWCACHE[1] == 1'b1 ); // Transaction cacheline boundary address. assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET ); // Transaction length & size. assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) & ( S_AXI_AWLEN == C_OPTIMIZED_LEN ); // Transaction is optimized. assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary; assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size; assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized ); ///////////////////////////////////////////////////////////////////////////// // Command FIFO: // // Since supported write interleaving is only 1, it is safe to use only a // simple SRL based FIFO as a command queue. // ///////////////////////////////////////////////////////////////////////////// // Determine when transaction infromation is pushed to the FIFO. assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full; // SRL FIFO Pointer. always @ (posedge ACLK) begin if (ARESET) begin addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_w_push & ~cmd_w_ready ) begin addr_ptr <= addr_ptr + 1; end else if ( ~cmd_w_push & cmd_w_ready ) begin addr_ptr <= addr_ptr - 1; end end end // Total number of buffered commands. assign all_addr_ptr = addr_ptr + cmd_b_addr + 2; // FIFO Flags. always @ (posedge ACLK) begin if (ARESET) begin cmd_full <= 1'b0; cmd_w_valid <= 1'b0; end else begin if ( cmd_w_push & ~cmd_w_ready ) begin cmd_w_valid <= 1'b1; end else if ( ~cmd_w_push & cmd_w_ready ) begin cmd_w_valid <= ( addr_ptr != 0 ); end if ( cmd_w_push & ~cmd_b_ready ) begin // Going to full. cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 ); end else if ( ~cmd_w_push & cmd_b_ready ) begin // Pop in middle of queue doesn't affect full status. cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 ); end end end // Infere SRL for storage. always @ (posedge ACLK) begin if ( cmd_w_push ) begin for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= {access_is_optimized, S_AXI_AWID}; end end // Get current transaction info. assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr]; ///////////////////////////////////////////////////////////////////////////// // Transaction Throttling: // // Stall commands if FIFO is full. // ///////////////////////////////////////////////////////////////////////////// // Propagate masked valid. assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full; // Return ready with push back. assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full; ///////////////////////////////////////////////////////////////////////////// // Address Write propagation: // // All information is simply forwarded on from the SI- to MI-Side untouched. // ///////////////////////////////////////////////////////////////////////////// // 1:1 mapping. assign M_AXI_AWID = S_AXI_AWID; assign M_AXI_AWADDR = S_AXI_AWADDR; assign M_AXI_AWLEN = S_AXI_AWLEN; assign M_AXI_AWSIZE = S_AXI_AWSIZE; assign M_AXI_AWBURST = S_AXI_AWBURST; assign M_AXI_AWLOCK = S_AXI_AWLOCK; assign M_AXI_AWCACHE = S_AXI_AWCACHE; assign M_AXI_AWPROT = S_AXI_AWPROT; assign M_AXI_AWUSER = S_AXI_AWUSER; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Address Write Channel for ATC // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // aw_atc // //-------------------------------------------------------------------------- `timescale 1ps/1ps module processing_system7_v5_5_aw_atc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6, spartan6 or later. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of checker. // Range: >= 1. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of all ADDR signals on SI and MI side of checker. // Range: 32. parameter integer C_AXI_AWUSER_WIDTH = 1, // Width of AWUSER signals. // Range: >= 1. parameter integer C_FIFO_DEPTH_LOG = 4 ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface output reg cmd_w_valid, output wire cmd_w_check, output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id, input wire cmd_w_ready, input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, input wire cmd_b_ready, // Slave Interface Write Address Port input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [4-1:0] S_AXI_AWLEN, input wire [3-1:0] S_AXI_AWSIZE, input wire [2-1:0] S_AXI_AWBURST, input wire [2-1:0] S_AXI_AWLOCK, input wire [4-1:0] S_AXI_AWCACHE, input wire [3-1:0] S_AXI_AWPROT, input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, // Master Interface Write Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [4-1:0] M_AXI_AWLEN, output wire [3-1:0] M_AXI_AWSIZE, output wire [2-1:0] M_AXI_AWBURST, output wire [2-1:0] M_AXI_AWLOCK, output wire [4-1:0] M_AXI_AWCACHE, output wire [3-1:0] M_AXI_AWPROT, output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire M_AXI_AWVALID, input wire M_AXI_AWREADY ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for burst types. localparam [2-1:0] C_FIX_BURST = 2'b00; localparam [2-1:0] C_INCR_BURST = 2'b01; localparam [2-1:0] C_WRAP_BURST = 2'b10; // Constants for size. localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011; // Constants for length. localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011; // Constants for cacheline address. localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0; // Command FIFO settings localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// integer index; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Transaction properties. wire access_is_incr; wire access_is_wrap; wire access_is_coherent; wire access_optimized_size; wire incr_addr_boundary; wire incr_is_optimized; wire wrap_is_optimized; wire access_is_optimized; // Command FIFO. wire cmd_w_push; reg cmd_full; reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr; reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; ///////////////////////////////////////////////////////////////////////////// // Transaction Decode: // // Detect if transaction is of correct typ, size and length to qualify as // an optimized transaction that has to be checked for errors. // ///////////////////////////////////////////////////////////////////////////// // Transaction burst type. assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST ); assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST ); // Transaction has to be Coherent. assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) & ( S_AXI_AWCACHE[1] == 1'b1 ); // Transaction cacheline boundary address. assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET ); // Transaction length & size. assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) & ( S_AXI_AWLEN == C_OPTIMIZED_LEN ); // Transaction is optimized. assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary; assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size; assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized ); ///////////////////////////////////////////////////////////////////////////// // Command FIFO: // // Since supported write interleaving is only 1, it is safe to use only a // simple SRL based FIFO as a command queue. // ///////////////////////////////////////////////////////////////////////////// // Determine when transaction infromation is pushed to the FIFO. assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full; // SRL FIFO Pointer. always @ (posedge ACLK) begin if (ARESET) begin addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_w_push & ~cmd_w_ready ) begin addr_ptr <= addr_ptr + 1; end else if ( ~cmd_w_push & cmd_w_ready ) begin addr_ptr <= addr_ptr - 1; end end end // Total number of buffered commands. assign all_addr_ptr = addr_ptr + cmd_b_addr + 2; // FIFO Flags. always @ (posedge ACLK) begin if (ARESET) begin cmd_full <= 1'b0; cmd_w_valid <= 1'b0; end else begin if ( cmd_w_push & ~cmd_w_ready ) begin cmd_w_valid <= 1'b1; end else if ( ~cmd_w_push & cmd_w_ready ) begin cmd_w_valid <= ( addr_ptr != 0 ); end if ( cmd_w_push & ~cmd_b_ready ) begin // Going to full. cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 ); end else if ( ~cmd_w_push & cmd_b_ready ) begin // Pop in middle of queue doesn't affect full status. cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 ); end end end // Infere SRL for storage. always @ (posedge ACLK) begin if ( cmd_w_push ) begin for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= {access_is_optimized, S_AXI_AWID}; end end // Get current transaction info. assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr]; ///////////////////////////////////////////////////////////////////////////// // Transaction Throttling: // // Stall commands if FIFO is full. // ///////////////////////////////////////////////////////////////////////////// // Propagate masked valid. assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full; // Return ready with push back. assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full; ///////////////////////////////////////////////////////////////////////////// // Address Write propagation: // // All information is simply forwarded on from the SI- to MI-Side untouched. // ///////////////////////////////////////////////////////////////////////////// // 1:1 mapping. assign M_AXI_AWID = S_AXI_AWID; assign M_AXI_AWADDR = S_AXI_AWADDR; assign M_AXI_AWLEN = S_AXI_AWLEN; assign M_AXI_AWSIZE = S_AXI_AWSIZE; assign M_AXI_AWBURST = S_AXI_AWBURST; assign M_AXI_AWLOCK = S_AXI_AWLOCK; assign M_AXI_AWCACHE = S_AXI_AWCACHE; assign M_AXI_AWPROT = S_AXI_AWPROT; assign M_AXI_AWUSER = S_AXI_AWUSER; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Address Write Channel for ATC // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // aw_atc // //-------------------------------------------------------------------------- `timescale 1ps/1ps module processing_system7_v5_5_aw_atc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6, spartan6 or later. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of checker. // Range: >= 1. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of all ADDR signals on SI and MI side of checker. // Range: 32. parameter integer C_AXI_AWUSER_WIDTH = 1, // Width of AWUSER signals. // Range: >= 1. parameter integer C_FIFO_DEPTH_LOG = 4 ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface output reg cmd_w_valid, output wire cmd_w_check, output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id, input wire cmd_w_ready, input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, input wire cmd_b_ready, // Slave Interface Write Address Port input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [4-1:0] S_AXI_AWLEN, input wire [3-1:0] S_AXI_AWSIZE, input wire [2-1:0] S_AXI_AWBURST, input wire [2-1:0] S_AXI_AWLOCK, input wire [4-1:0] S_AXI_AWCACHE, input wire [3-1:0] S_AXI_AWPROT, input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, // Master Interface Write Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [4-1:0] M_AXI_AWLEN, output wire [3-1:0] M_AXI_AWSIZE, output wire [2-1:0] M_AXI_AWBURST, output wire [2-1:0] M_AXI_AWLOCK, output wire [4-1:0] M_AXI_AWCACHE, output wire [3-1:0] M_AXI_AWPROT, output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire M_AXI_AWVALID, input wire M_AXI_AWREADY ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for burst types. localparam [2-1:0] C_FIX_BURST = 2'b00; localparam [2-1:0] C_INCR_BURST = 2'b01; localparam [2-1:0] C_WRAP_BURST = 2'b10; // Constants for size. localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011; // Constants for length. localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011; // Constants for cacheline address. localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0; // Command FIFO settings localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// integer index; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Transaction properties. wire access_is_incr; wire access_is_wrap; wire access_is_coherent; wire access_optimized_size; wire incr_addr_boundary; wire incr_is_optimized; wire wrap_is_optimized; wire access_is_optimized; // Command FIFO. wire cmd_w_push; reg cmd_full; reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr; reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; ///////////////////////////////////////////////////////////////////////////// // Transaction Decode: // // Detect if transaction is of correct typ, size and length to qualify as // an optimized transaction that has to be checked for errors. // ///////////////////////////////////////////////////////////////////////////// // Transaction burst type. assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST ); assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST ); // Transaction has to be Coherent. assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) & ( S_AXI_AWCACHE[1] == 1'b1 ); // Transaction cacheline boundary address. assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET ); // Transaction length & size. assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) & ( S_AXI_AWLEN == C_OPTIMIZED_LEN ); // Transaction is optimized. assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary; assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size; assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized ); ///////////////////////////////////////////////////////////////////////////// // Command FIFO: // // Since supported write interleaving is only 1, it is safe to use only a // simple SRL based FIFO as a command queue. // ///////////////////////////////////////////////////////////////////////////// // Determine when transaction infromation is pushed to the FIFO. assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full; // SRL FIFO Pointer. always @ (posedge ACLK) begin if (ARESET) begin addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_w_push & ~cmd_w_ready ) begin addr_ptr <= addr_ptr + 1; end else if ( ~cmd_w_push & cmd_w_ready ) begin addr_ptr <= addr_ptr - 1; end end end // Total number of buffered commands. assign all_addr_ptr = addr_ptr + cmd_b_addr + 2; // FIFO Flags. always @ (posedge ACLK) begin if (ARESET) begin cmd_full <= 1'b0; cmd_w_valid <= 1'b0; end else begin if ( cmd_w_push & ~cmd_w_ready ) begin cmd_w_valid <= 1'b1; end else if ( ~cmd_w_push & cmd_w_ready ) begin cmd_w_valid <= ( addr_ptr != 0 ); end if ( cmd_w_push & ~cmd_b_ready ) begin // Going to full. cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 ); end else if ( ~cmd_w_push & cmd_b_ready ) begin // Pop in middle of queue doesn't affect full status. cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 ); end end end // Infere SRL for storage. always @ (posedge ACLK) begin if ( cmd_w_push ) begin for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= {access_is_optimized, S_AXI_AWID}; end end // Get current transaction info. assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr]; ///////////////////////////////////////////////////////////////////////////// // Transaction Throttling: // // Stall commands if FIFO is full. // ///////////////////////////////////////////////////////////////////////////// // Propagate masked valid. assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full; // Return ready with push back. assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full; ///////////////////////////////////////////////////////////////////////////// // Address Write propagation: // // All information is simply forwarded on from the SI- to MI-Side untouched. // ///////////////////////////////////////////////////////////////////////////// // 1:1 mapping. assign M_AXI_AWID = S_AXI_AWID; assign M_AXI_AWADDR = S_AXI_AWADDR; assign M_AXI_AWLEN = S_AXI_AWLEN; assign M_AXI_AWSIZE = S_AXI_AWSIZE; assign M_AXI_AWBURST = S_AXI_AWBURST; assign M_AXI_AWLOCK = S_AXI_AWLOCK; assign M_AXI_AWCACHE = S_AXI_AWCACHE; assign M_AXI_AWPROT = S_AXI_AWPROT; assign M_AXI_AWUSER = S_AXI_AWUSER; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Address Write Channel for ATC // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // aw_atc // //-------------------------------------------------------------------------- `timescale 1ps/1ps module processing_system7_v5_5_aw_atc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6, spartan6 or later. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of checker. // Range: >= 1. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of all ADDR signals on SI and MI side of checker. // Range: 32. parameter integer C_AXI_AWUSER_WIDTH = 1, // Width of AWUSER signals. // Range: >= 1. parameter integer C_FIFO_DEPTH_LOG = 4 ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface output reg cmd_w_valid, output wire cmd_w_check, output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id, input wire cmd_w_ready, input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, input wire cmd_b_ready, // Slave Interface Write Address Port input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [4-1:0] S_AXI_AWLEN, input wire [3-1:0] S_AXI_AWSIZE, input wire [2-1:0] S_AXI_AWBURST, input wire [2-1:0] S_AXI_AWLOCK, input wire [4-1:0] S_AXI_AWCACHE, input wire [3-1:0] S_AXI_AWPROT, input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, // Master Interface Write Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [4-1:0] M_AXI_AWLEN, output wire [3-1:0] M_AXI_AWSIZE, output wire [2-1:0] M_AXI_AWBURST, output wire [2-1:0] M_AXI_AWLOCK, output wire [4-1:0] M_AXI_AWCACHE, output wire [3-1:0] M_AXI_AWPROT, output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire M_AXI_AWVALID, input wire M_AXI_AWREADY ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for burst types. localparam [2-1:0] C_FIX_BURST = 2'b00; localparam [2-1:0] C_INCR_BURST = 2'b01; localparam [2-1:0] C_WRAP_BURST = 2'b10; // Constants for size. localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011; // Constants for length. localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011; // Constants for cacheline address. localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0; // Command FIFO settings localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// integer index; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Transaction properties. wire access_is_incr; wire access_is_wrap; wire access_is_coherent; wire access_optimized_size; wire incr_addr_boundary; wire incr_is_optimized; wire wrap_is_optimized; wire access_is_optimized; // Command FIFO. wire cmd_w_push; reg cmd_full; reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr; reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; ///////////////////////////////////////////////////////////////////////////// // Transaction Decode: // // Detect if transaction is of correct typ, size and length to qualify as // an optimized transaction that has to be checked for errors. // ///////////////////////////////////////////////////////////////////////////// // Transaction burst type. assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST ); assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST ); // Transaction has to be Coherent. assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) & ( S_AXI_AWCACHE[1] == 1'b1 ); // Transaction cacheline boundary address. assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET ); // Transaction length & size. assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) & ( S_AXI_AWLEN == C_OPTIMIZED_LEN ); // Transaction is optimized. assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary; assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size; assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized ); ///////////////////////////////////////////////////////////////////////////// // Command FIFO: // // Since supported write interleaving is only 1, it is safe to use only a // simple SRL based FIFO as a command queue. // ///////////////////////////////////////////////////////////////////////////// // Determine when transaction infromation is pushed to the FIFO. assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full; // SRL FIFO Pointer. always @ (posedge ACLK) begin if (ARESET) begin addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_w_push & ~cmd_w_ready ) begin addr_ptr <= addr_ptr + 1; end else if ( ~cmd_w_push & cmd_w_ready ) begin addr_ptr <= addr_ptr - 1; end end end // Total number of buffered commands. assign all_addr_ptr = addr_ptr + cmd_b_addr + 2; // FIFO Flags. always @ (posedge ACLK) begin if (ARESET) begin cmd_full <= 1'b0; cmd_w_valid <= 1'b0; end else begin if ( cmd_w_push & ~cmd_w_ready ) begin cmd_w_valid <= 1'b1; end else if ( ~cmd_w_push & cmd_w_ready ) begin cmd_w_valid <= ( addr_ptr != 0 ); end if ( cmd_w_push & ~cmd_b_ready ) begin // Going to full. cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 ); end else if ( ~cmd_w_push & cmd_b_ready ) begin // Pop in middle of queue doesn't affect full status. cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 ); end end end // Infere SRL for storage. always @ (posedge ACLK) begin if ( cmd_w_push ) begin for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= {access_is_optimized, S_AXI_AWID}; end end // Get current transaction info. assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr]; ///////////////////////////////////////////////////////////////////////////// // Transaction Throttling: // // Stall commands if FIFO is full. // ///////////////////////////////////////////////////////////////////////////// // Propagate masked valid. assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full; // Return ready with push back. assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full; ///////////////////////////////////////////////////////////////////////////// // Address Write propagation: // // All information is simply forwarded on from the SI- to MI-Side untouched. // ///////////////////////////////////////////////////////////////////////////// // 1:1 mapping. assign M_AXI_AWID = S_AXI_AWID; assign M_AXI_AWADDR = S_AXI_AWADDR; assign M_AXI_AWLEN = S_AXI_AWLEN; assign M_AXI_AWSIZE = S_AXI_AWSIZE; assign M_AXI_AWBURST = S_AXI_AWBURST; assign M_AXI_AWLOCK = S_AXI_AWLOCK; assign M_AXI_AWCACHE = S_AXI_AWCACHE; assign M_AXI_AWPROT = S_AXI_AWPROT; assign M_AXI_AWUSER = S_AXI_AWUSER; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Address Write Channel for ATC // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // aw_atc // //-------------------------------------------------------------------------- `timescale 1ps/1ps module processing_system7_v5_5_aw_atc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6, spartan6 or later. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of checker. // Range: >= 1. parameter integer C_AXI_ADDR_WIDTH = 32, // Width of all ADDR signals on SI and MI side of checker. // Range: 32. parameter integer C_AXI_AWUSER_WIDTH = 1, // Width of AWUSER signals. // Range: >= 1. parameter integer C_FIFO_DEPTH_LOG = 4 ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface output reg cmd_w_valid, output wire cmd_w_check, output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id, input wire cmd_w_ready, input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, input wire cmd_b_ready, // Slave Interface Write Address Port input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, input wire [4-1:0] S_AXI_AWLEN, input wire [3-1:0] S_AXI_AWSIZE, input wire [2-1:0] S_AXI_AWBURST, input wire [2-1:0] S_AXI_AWLOCK, input wire [4-1:0] S_AXI_AWCACHE, input wire [3-1:0] S_AXI_AWPROT, input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, // Master Interface Write Address Port output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, output wire [4-1:0] M_AXI_AWLEN, output wire [3-1:0] M_AXI_AWSIZE, output wire [2-1:0] M_AXI_AWBURST, output wire [2-1:0] M_AXI_AWLOCK, output wire [4-1:0] M_AXI_AWCACHE, output wire [3-1:0] M_AXI_AWPROT, output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, output wire M_AXI_AWVALID, input wire M_AXI_AWREADY ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for burst types. localparam [2-1:0] C_FIX_BURST = 2'b00; localparam [2-1:0] C_INCR_BURST = 2'b01; localparam [2-1:0] C_WRAP_BURST = 2'b10; // Constants for size. localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011; // Constants for length. localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011; // Constants for cacheline address. localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0; // Command FIFO settings localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// integer index; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Transaction properties. wire access_is_incr; wire access_is_wrap; wire access_is_coherent; wire access_optimized_size; wire incr_addr_boundary; wire incr_is_optimized; wire wrap_is_optimized; wire access_is_optimized; // Command FIFO. wire cmd_w_push; reg cmd_full; reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr; reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; ///////////////////////////////////////////////////////////////////////////// // Transaction Decode: // // Detect if transaction is of correct typ, size and length to qualify as // an optimized transaction that has to be checked for errors. // ///////////////////////////////////////////////////////////////////////////// // Transaction burst type. assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST ); assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST ); // Transaction has to be Coherent. assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) & ( S_AXI_AWCACHE[1] == 1'b1 ); // Transaction cacheline boundary address. assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET ); // Transaction length & size. assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) & ( S_AXI_AWLEN == C_OPTIMIZED_LEN ); // Transaction is optimized. assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary; assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size; assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized ); ///////////////////////////////////////////////////////////////////////////// // Command FIFO: // // Since supported write interleaving is only 1, it is safe to use only a // simple SRL based FIFO as a command queue. // ///////////////////////////////////////////////////////////////////////////// // Determine when transaction infromation is pushed to the FIFO. assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full; // SRL FIFO Pointer. always @ (posedge ACLK) begin if (ARESET) begin addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_w_push & ~cmd_w_ready ) begin addr_ptr <= addr_ptr + 1; end else if ( ~cmd_w_push & cmd_w_ready ) begin addr_ptr <= addr_ptr - 1; end end end // Total number of buffered commands. assign all_addr_ptr = addr_ptr + cmd_b_addr + 2; // FIFO Flags. always @ (posedge ACLK) begin if (ARESET) begin cmd_full <= 1'b0; cmd_w_valid <= 1'b0; end else begin if ( cmd_w_push & ~cmd_w_ready ) begin cmd_w_valid <= 1'b1; end else if ( ~cmd_w_push & cmd_w_ready ) begin cmd_w_valid <= ( addr_ptr != 0 ); end if ( cmd_w_push & ~cmd_b_ready ) begin // Going to full. cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 ); end else if ( ~cmd_w_push & cmd_b_ready ) begin // Pop in middle of queue doesn't affect full status. cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 ); end end end // Infere SRL for storage. always @ (posedge ACLK) begin if ( cmd_w_push ) begin for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= {access_is_optimized, S_AXI_AWID}; end end // Get current transaction info. assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr]; ///////////////////////////////////////////////////////////////////////////// // Transaction Throttling: // // Stall commands if FIFO is full. // ///////////////////////////////////////////////////////////////////////////// // Propagate masked valid. assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full; // Return ready with push back. assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full; ///////////////////////////////////////////////////////////////////////////// // Address Write propagation: // // All information is simply forwarded on from the SI- to MI-Side untouched. // ///////////////////////////////////////////////////////////////////////////// // 1:1 mapping. assign M_AXI_AWID = S_AXI_AWID; assign M_AXI_AWADDR = S_AXI_AWADDR; assign M_AXI_AWLEN = S_AXI_AWLEN; assign M_AXI_AWSIZE = S_AXI_AWSIZE; assign M_AXI_AWBURST = S_AXI_AWBURST; assign M_AXI_AWLOCK = S_AXI_AWLOCK; assign M_AXI_AWCACHE = S_AXI_AWCACHE; assign M_AXI_AWPROT = S_AXI_AWPROT; assign M_AXI_AWUSER = S_AXI_AWUSER; endmodule
`include "../../firmware/include/fpga_regs_common.v" `include "../../firmware/include/fpga_regs_standard.v" module adc_interface (input clock, input reset, input enable, input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe, input wire [11:0] rx_a_a, input wire [11:0] rx_b_a, input wire [11:0] rx_a_b, input wire [11:0] rx_b_b, output wire [31:0] rssi_0, output wire [31:0] rssi_1, output wire [31:0] rssi_2, output wire [31:0] rssi_3, output reg [15:0] ddc0_in_i, output reg [15:0] ddc0_in_q, output reg [15:0] ddc1_in_i, output reg [15:0] ddc1_in_q, output reg [15:0] ddc2_in_i, output reg [15:0] ddc2_in_q, output reg [15:0] ddc3_in_i, output reg [15:0] ddc3_in_q, output wire [3:0] rx_numchan); // Buffer at input to chip reg [11:0] adc0,adc1,adc2,adc3; always @(posedge clock) begin adc0 <= #1 rx_a_a; adc1 <= #1 rx_b_a; adc2 <= #1 rx_a_b; adc3 <= #1 rx_b_b; end // then scale and subtract dc offset wire [3:0] dco_en; wire [15:0] adc0_corr,adc1_corr,adc2_corr,adc3_corr; setting_reg #(`FR_DC_OFFSET_CL_EN) sr_dco_en(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), .out(dco_en)); rx_dcoffset #(`FR_ADC_OFFSET_0) rx_dcoffset0(.clock(clock),.enable(dco_en[0]),.reset(reset),.adc_in({adc0[11],adc0,3'b0}),.adc_out(adc0_corr), .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); rx_dcoffset #(`FR_ADC_OFFSET_1) rx_dcoffset1(.clock(clock),.enable(dco_en[1]),.reset(reset),.adc_in({adc1[11],adc1,3'b0}),.adc_out(adc1_corr), .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); rx_dcoffset #(`FR_ADC_OFFSET_2) rx_dcoffset2(.clock(clock),.enable(dco_en[2]),.reset(reset),.adc_in({adc2[11],adc2,3'b0}),.adc_out(adc2_corr), .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); rx_dcoffset #(`FR_ADC_OFFSET_3) rx_dcoffset3(.clock(clock),.enable(dco_en[3]),.reset(reset),.adc_in({adc3[11],adc3,3'b0}),.adc_out(adc3_corr), .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); // Level sensing for AGC rssi rssi_block_0 (.clock(clock),.reset(reset),.enable(enable),.adc(adc0),.rssi(rssi_0[15:0]),.over_count(rssi_0[31:16])); rssi rssi_block_1 (.clock(clock),.reset(reset),.enable(enable),.adc(adc1),.rssi(rssi_1[15:0]),.over_count(rssi_1[31:16])); rssi rssi_block_2 (.clock(clock),.reset(reset),.enable(enable),.adc(adc2),.rssi(rssi_2[15:0]),.over_count(rssi_2[31:16])); rssi rssi_block_3 (.clock(clock),.reset(reset),.enable(enable),.adc(adc3),.rssi(rssi_3[15:0]),.over_count(rssi_3[31:16])); // And mux to the appropriate outputs wire [3:0] ddc3mux,ddc2mux,ddc1mux,ddc0mux; wire rx_realsignals; setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr), .in(serial_data),.out({ddc3mux,ddc2mux,ddc1mux,ddc0mux,rx_realsignals,rx_numchan[3:1]})); assign rx_numchan[0] = 1'b0; always @(posedge clock) begin ddc0_in_i <= #1 ddc0mux[1] ? (ddc0mux[0] ? adc3_corr : adc2_corr) : (ddc0mux[0] ? adc1_corr : adc0_corr); ddc0_in_q <= #1 rx_realsignals ? 16'd0 : ddc0mux[3] ? (ddc0mux[2] ? adc3_corr : adc2_corr) : (ddc0mux[2] ? adc1_corr : adc0_corr); ddc1_in_i <= #1 ddc1mux[1] ? (ddc1mux[0] ? adc3_corr : adc2_corr) : (ddc1mux[0] ? adc1_corr : adc0_corr); ddc1_in_q <= #1 rx_realsignals ? 16'd0 : ddc1mux[3] ? (ddc1mux[2] ? adc3_corr : adc2_corr) : (ddc1mux[2] ? adc1_corr : adc0_corr); ddc2_in_i <= #1 ddc2mux[1] ? (ddc2mux[0] ? adc3_corr : adc2_corr) : (ddc2mux[0] ? adc1_corr : adc0_corr); ddc2_in_q <= #1 rx_realsignals ? 16'd0 : ddc2mux[3] ? (ddc2mux[2] ? adc3_corr : adc2_corr) : (ddc2mux[2] ? adc1_corr : adc0_corr); ddc3_in_i <= #1 ddc3mux[1] ? (ddc3mux[0] ? adc3_corr : adc2_corr) : (ddc3mux[0] ? adc1_corr : adc0_corr); ddc3_in_q <= #1 rx_realsignals ? 16'd0 : ddc3mux[3] ? (ddc3mux[2] ? adc3_corr : adc2_corr) : (ddc3mux[2] ? adc1_corr : adc0_corr); end endmodule // adc_interface
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 // Digital model of a traffic light // By Dan Hyde August 10, 1995 module traffic; parameter on = 1, off = 0, red_tics = 35, amber_tics = 3, green_tics = 20; reg clock, red, amber, green; // will stop the simulation after 1000 time units initial begin: stop_at #1000; $stop; end // initialize the lights and set up monitoring of registers initial begin: Init red = off; amber = off; green = off; $display(" Time green amber red"); $monitor("%3d %b %b %b", $time, green, amber, red); end // task to wait for 'tics' positive edge clocks // before turning light off task light; output color; input [31:0] tics; begin repeat(tics) // wait to detect tics positive edges on clock @(posedge clock); color = off; end endtask // waveform for clock period of 2 time units always begin: clock_wave #1 clock = 0; #1 clock = 1; end always begin: main_process red = on; light(red, red_tics); // call task to wait green = on; light(green, green_tics); amber = on; light(amber, amber_tics); end endmodule
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 // Digital model of a traffic light // By Dan Hyde August 10, 1995 module traffic; parameter on = 1, off = 0, red_tics = 35, amber_tics = 3, green_tics = 20; reg clock, red, amber, green; // will stop the simulation after 1000 time units initial begin: stop_at #1000; $stop; end // initialize the lights and set up monitoring of registers initial begin: Init red = off; amber = off; green = off; $display(" Time green amber red"); $monitor("%3d %b %b %b", $time, green, amber, red); end // task to wait for 'tics' positive edge clocks // before turning light off task light; output color; input [31:0] tics; begin repeat(tics) // wait to detect tics positive edges on clock @(posedge clock); color = off; end endtask // waveform for clock period of 2 time units always begin: clock_wave #1 clock = 0; #1 clock = 1; end always begin: main_process red = on; light(red, red_tics); // call task to wait green = on; light(green, green_tics); amber = on; light(amber, amber_tics); end endmodule
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 // Digital model of a traffic light // By Dan Hyde August 10, 1995 module traffic; parameter on = 1, off = 0, red_tics = 35, amber_tics = 3, green_tics = 20; reg clock, red, amber, green; // will stop the simulation after 1000 time units initial begin: stop_at #1000; $stop; end // initialize the lights and set up monitoring of registers initial begin: Init red = off; amber = off; green = off; $display(" Time green amber red"); $monitor("%3d %b %b %b", $time, green, amber, red); end // task to wait for 'tics' positive edge clocks // before turning light off task light; output color; input [31:0] tics; begin repeat(tics) // wait to detect tics positive edges on clock @(posedge clock); color = off; end endtask // waveform for clock period of 2 time units always begin: clock_wave #1 clock = 0; #1 clock = 1; end always begin: main_process red = on; light(red, red_tics); // call task to wait green = on; light(green, green_tics); amber = on; light(amber, amber_tics); end endmodule
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 // Digital model of a traffic light // By Dan Hyde August 10, 1995 module traffic; parameter on = 1, off = 0, red_tics = 35, amber_tics = 3, green_tics = 20; reg clock, red, amber, green; // will stop the simulation after 1000 time units initial begin: stop_at #1000; $stop; end // initialize the lights and set up monitoring of registers initial begin: Init red = off; amber = off; green = off; $display(" Time green amber red"); $monitor("%3d %b %b %b", $time, green, amber, red); end // task to wait for 'tics' positive edge clocks // before turning light off task light; output color; input [31:0] tics; begin repeat(tics) // wait to detect tics positive edges on clock @(posedge clock); color = off; end endtask // waveform for clock period of 2 time units always begin: clock_wave #1 clock = 0; #1 clock = 1; end always begin: main_process red = on; light(red, red_tics); // call task to wait green = on; light(green, green_tics); amber = on; light(amber, amber_tics); end endmodule
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 // Digital model of a traffic light // By Dan Hyde August 10, 1995 module traffic; parameter on = 1, off = 0, red_tics = 35, amber_tics = 3, green_tics = 20; reg clock, red, amber, green; // will stop the simulation after 1000 time units initial begin: stop_at #1000; $stop; end // initialize the lights and set up monitoring of registers initial begin: Init red = off; amber = off; green = off; $display(" Time green amber red"); $monitor("%3d %b %b %b", $time, green, amber, red); end // task to wait for 'tics' positive edge clocks // before turning light off task light; output color; input [31:0] tics; begin repeat(tics) // wait to detect tics positive edges on clock @(posedge clock); color = off; end endtask // waveform for clock period of 2 time units always begin: clock_wave #1 clock = 0; #1 clock = 1; end always begin: main_process red = on; light(red, red_tics); // call task to wait green = on; light(green, green_tics); amber = on; light(amber, amber_tics); end endmodule
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 // Digital model of a traffic light // By Dan Hyde August 10, 1995 module traffic; parameter on = 1, off = 0, red_tics = 35, amber_tics = 3, green_tics = 20; reg clock, red, amber, green; // will stop the simulation after 1000 time units initial begin: stop_at #1000; $stop; end // initialize the lights and set up monitoring of registers initial begin: Init red = off; amber = off; green = off; $display(" Time green amber red"); $monitor("%3d %b %b %b", $time, green, amber, red); end // task to wait for 'tics' positive edge clocks // before turning light off task light; output color; input [31:0] tics; begin repeat(tics) // wait to detect tics positive edges on clock @(posedge clock); color = off; end endtask // waveform for clock period of 2 time units always begin: clock_wave #1 clock = 0; #1 clock = 1; end always begin: main_process red = on; light(red, red_tics); // call task to wait green = on; light(green, green_tics); amber = on; light(amber, amber_tics); end endmodule
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 // Digital model of a traffic light // By Dan Hyde August 10, 1995 module traffic; parameter on = 1, off = 0, red_tics = 35, amber_tics = 3, green_tics = 20; reg clock, red, amber, green; // will stop the simulation after 1000 time units initial begin: stop_at #1000; $stop; end // initialize the lights and set up monitoring of registers initial begin: Init red = off; amber = off; green = off; $display(" Time green amber red"); $monitor("%3d %b %b %b", $time, green, amber, red); end // task to wait for 'tics' positive edge clocks // before turning light off task light; output color; input [31:0] tics; begin repeat(tics) // wait to detect tics positive edges on clock @(posedge clock); color = off; end endtask // waveform for clock period of 2 time units always begin: clock_wave #1 clock = 0; #1 clock = 1; end always begin: main_process red = on; light(red, red_tics); // call task to wait green = on; light(green, green_tics); amber = on; light(amber, amber_tics); end endmodule
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 // Digital model of a traffic light // By Dan Hyde August 10, 1995 module traffic; parameter on = 1, off = 0, red_tics = 35, amber_tics = 3, green_tics = 20; reg clock, red, amber, green; // will stop the simulation after 1000 time units initial begin: stop_at #1000; $stop; end // initialize the lights and set up monitoring of registers initial begin: Init red = off; amber = off; green = off; $display(" Time green amber red"); $monitor("%3d %b %b %b", $time, green, amber, red); end // task to wait for 'tics' positive edge clocks // before turning light off task light; output color; input [31:0] tics; begin repeat(tics) // wait to detect tics positive edges on clock @(posedge clock); color = off; end endtask // waveform for clock period of 2 time units always begin: clock_wave #1 clock = 0; #1 clock = 1; end always begin: main_process red = on; light(red, red_tics); // call task to wait green = on; light(green, green_tics); amber = on; light(amber, amber_tics); end endmodule
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 // Digital model of a traffic light // By Dan Hyde August 10, 1995 module traffic; parameter on = 1, off = 0, red_tics = 35, amber_tics = 3, green_tics = 20; reg clock, red, amber, green; // will stop the simulation after 1000 time units initial begin: stop_at #1000; $stop; end // initialize the lights and set up monitoring of registers initial begin: Init red = off; amber = off; green = off; $display(" Time green amber red"); $monitor("%3d %b %b %b", $time, green, amber, red); end // task to wait for 'tics' positive edge clocks // before turning light off task light; output color; input [31:0] tics; begin repeat(tics) // wait to detect tics positive edges on clock @(posedge clock); color = off; end endtask // waveform for clock period of 2 time units always begin: clock_wave #1 clock = 0; #1 clock = 1; end always begin: main_process red = on; light(red, red_tics); // call task to wait green = on; light(green, green_tics); amber = on; light(amber, amber_tics); end endmodule
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 // Digital model of a traffic light // By Dan Hyde August 10, 1995 module traffic; parameter on = 1, off = 0, red_tics = 35, amber_tics = 3, green_tics = 20; reg clock, red, amber, green; // will stop the simulation after 1000 time units initial begin: stop_at #1000; $stop; end // initialize the lights and set up monitoring of registers initial begin: Init red = off; amber = off; green = off; $display(" Time green amber red"); $monitor("%3d %b %b %b", $time, green, amber, red); end // task to wait for 'tics' positive edge clocks // before turning light off task light; output color; input [31:0] tics; begin repeat(tics) // wait to detect tics positive edges on clock @(posedge clock); color = off; end endtask // waveform for clock period of 2 time units always begin: clock_wave #1 clock = 0; #1 clock = 1; end always begin: main_process red = on; light(red, red_tics); // call task to wait green = on; light(green, green_tics); amber = on; light(amber, amber_tics); end endmodule
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 // Digital model of a traffic light // By Dan Hyde August 10, 1995 module traffic; parameter on = 1, off = 0, red_tics = 35, amber_tics = 3, green_tics = 20; reg clock, red, amber, green; // will stop the simulation after 1000 time units initial begin: stop_at #1000; $stop; end // initialize the lights and set up monitoring of registers initial begin: Init red = off; amber = off; green = off; $display(" Time green amber red"); $monitor("%3d %b %b %b", $time, green, amber, red); end // task to wait for 'tics' positive edge clocks // before turning light off task light; output color; input [31:0] tics; begin repeat(tics) // wait to detect tics positive edges on clock @(posedge clock); color = off; end endtask // waveform for clock period of 2 time units always begin: clock_wave #1 clock = 0; #1 clock = 1; end always begin: main_process red = on; light(red, red_tics); // call task to wait green = on; light(green, green_tics); amber = on; light(amber, amber_tics); end endmodule
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 // Digital model of a traffic light // By Dan Hyde August 10, 1995 module traffic; parameter on = 1, off = 0, red_tics = 35, amber_tics = 3, green_tics = 20; reg clock, red, amber, green; // will stop the simulation after 1000 time units initial begin: stop_at #1000; $stop; end // initialize the lights and set up monitoring of registers initial begin: Init red = off; amber = off; green = off; $display(" Time green amber red"); $monitor("%3d %b %b %b", $time, green, amber, red); end // task to wait for 'tics' positive edge clocks // before turning light off task light; output color; input [31:0] tics; begin repeat(tics) // wait to detect tics positive edges on clock @(posedge clock); color = off; end endtask // waveform for clock period of 2 time units always begin: clock_wave #1 clock = 0; #1 clock = 1; end always begin: main_process red = on; light(red, red_tics); // call task to wait green = on; light(green, green_tics); amber = on; light(amber, amber_tics); end endmodule
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: decerr_slave.v // // Description: // Phantom slave interface used to complete W, R and B channel transfers when an // erroneous transaction is trapped in the crossbar. //-------------------------------------------------------------------------- // // Structure: // decerr_slave // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_decerr_slave # ( parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_PROTOCOL = 0, parameter integer C_RESP = 2'b11, parameter integer C_IGNORE_ID = 0 ) ( input wire ACLK, input wire ARESETN, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, input wire S_AXI_WLAST, input wire S_AXI_WVALID, output wire S_AXI_WREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID, output wire [1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN, input wire S_AXI_ARVALID, output wire S_AXI_ARREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID, output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA, output wire [1:0] S_AXI_RRESP, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RLAST, output wire S_AXI_RVALID, input wire S_AXI_RREADY ); reg s_axi_awready_i; reg s_axi_wready_i; reg s_axi_bvalid_i; reg s_axi_arready_i; reg s_axi_rvalid_i; localparam P_WRITE_IDLE = 2'b00; localparam P_WRITE_DATA = 2'b01; localparam P_WRITE_RESP = 2'b10; localparam P_READ_IDLE = 2'b00; localparam P_READ_START = 2'b01; localparam P_READ_DATA = 2'b10; localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; assign S_AXI_BRESP = C_RESP; assign S_AXI_RRESP = C_RESP; assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}}; assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}}; assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}}; assign S_AXI_AWREADY = s_axi_awready_i; assign S_AXI_WREADY = s_axi_wready_i; assign S_AXI_BVALID = s_axi_bvalid_i; assign S_AXI_ARREADY = s_axi_arready_i; assign S_AXI_RVALID = s_axi_rvalid_i; generate if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite reg s_axi_rvalid_en; assign S_AXI_RLAST = 1'b1; assign S_AXI_BID = 0; assign S_AXI_RID = 0; always @(posedge ACLK) begin if (~ARESETN) begin s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b0; end else begin if (s_axi_bvalid_i) begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1'b0; s_axi_awready_i <= 1'b1; end end else if (S_AXI_WVALID & s_axi_wready_i) begin s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b1; end else if (S_AXI_AWVALID & s_axi_awready_i) begin s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b1; end else begin s_axi_awready_i <= 1'b1; end end end always @(posedge ACLK) begin if (~ARESETN) begin s_axi_arready_i <= 1'b0; s_axi_rvalid_i <= 1'b0; s_axi_rvalid_en <= 1'b0; end else begin if (s_axi_rvalid_i) begin if (S_AXI_RREADY) begin s_axi_rvalid_i <= 1'b0; s_axi_arready_i <= 1'b1; end end else if (s_axi_rvalid_en) begin s_axi_rvalid_en <= 1'b0; s_axi_rvalid_i <= 1'b1; end else if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1'b0; s_axi_rvalid_en <= 1'b1; end else begin s_axi_arready_i <= 1'b1; end end end end else begin : gen_axi reg s_axi_rlast_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i; reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt; reg [1:0] write_cs; reg [1:0] read_cs; assign S_AXI_RLAST = s_axi_rlast_i; assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i; assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i; always @(posedge ACLK) begin if (~ARESETN) begin write_cs <= P_WRITE_IDLE; s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b0; s_axi_bid_i <= 0; end else begin case (write_cs) P_WRITE_IDLE: begin if (S_AXI_AWVALID & s_axi_awready_i) begin s_axi_awready_i <= 1'b0; if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID; s_axi_wready_i <= 1'b1; write_cs <= P_WRITE_DATA; end else begin s_axi_awready_i <= 1'b1; end end P_WRITE_DATA: begin if (S_AXI_WVALID & S_AXI_WLAST) begin s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b1; write_cs <= P_WRITE_RESP; end end P_WRITE_RESP: begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1'b0; s_axi_awready_i <= 1'b1; write_cs <= P_WRITE_IDLE; end end endcase end end always @(posedge ACLK) begin if (~ARESETN) begin read_cs <= P_READ_IDLE; s_axi_arready_i <= 1'b0; s_axi_rvalid_i <= 1'b0; s_axi_rlast_i <= 1'b0; s_axi_rid_i <= 0; read_cnt <= 0; end else begin case (read_cs) P_READ_IDLE: begin if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1'b0; if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID; read_cnt <= S_AXI_ARLEN; s_axi_rlast_i <= (S_AXI_ARLEN == 0); read_cs <= P_READ_START; end else begin s_axi_arready_i <= 1'b1; end end P_READ_START: begin s_axi_rvalid_i <= 1'b1; read_cs <= P_READ_DATA; end P_READ_DATA: begin if (S_AXI_RREADY) begin if (read_cnt == 0) begin s_axi_rvalid_i <= 1'b0; s_axi_rlast_i <= 1'b0; s_axi_arready_i <= 1'b1; read_cs <= P_READ_IDLE; end else begin if (read_cnt == 1) begin s_axi_rlast_i <= 1'b1; end read_cnt <= read_cnt - 1; end end end endcase end end end endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: decerr_slave.v // // Description: // Phantom slave interface used to complete W, R and B channel transfers when an // erroneous transaction is trapped in the crossbar. //-------------------------------------------------------------------------- // // Structure: // decerr_slave // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_decerr_slave # ( parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_PROTOCOL = 0, parameter integer C_RESP = 2'b11, parameter integer C_IGNORE_ID = 0 ) ( input wire ACLK, input wire ARESETN, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, input wire S_AXI_WLAST, input wire S_AXI_WVALID, output wire S_AXI_WREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID, output wire [1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN, input wire S_AXI_ARVALID, output wire S_AXI_ARREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID, output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA, output wire [1:0] S_AXI_RRESP, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RLAST, output wire S_AXI_RVALID, input wire S_AXI_RREADY ); reg s_axi_awready_i; reg s_axi_wready_i; reg s_axi_bvalid_i; reg s_axi_arready_i; reg s_axi_rvalid_i; localparam P_WRITE_IDLE = 2'b00; localparam P_WRITE_DATA = 2'b01; localparam P_WRITE_RESP = 2'b10; localparam P_READ_IDLE = 2'b00; localparam P_READ_START = 2'b01; localparam P_READ_DATA = 2'b10; localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; assign S_AXI_BRESP = C_RESP; assign S_AXI_RRESP = C_RESP; assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}}; assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}}; assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}}; assign S_AXI_AWREADY = s_axi_awready_i; assign S_AXI_WREADY = s_axi_wready_i; assign S_AXI_BVALID = s_axi_bvalid_i; assign S_AXI_ARREADY = s_axi_arready_i; assign S_AXI_RVALID = s_axi_rvalid_i; generate if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite reg s_axi_rvalid_en; assign S_AXI_RLAST = 1'b1; assign S_AXI_BID = 0; assign S_AXI_RID = 0; always @(posedge ACLK) begin if (~ARESETN) begin s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b0; end else begin if (s_axi_bvalid_i) begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1'b0; s_axi_awready_i <= 1'b1; end end else if (S_AXI_WVALID & s_axi_wready_i) begin s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b1; end else if (S_AXI_AWVALID & s_axi_awready_i) begin s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b1; end else begin s_axi_awready_i <= 1'b1; end end end always @(posedge ACLK) begin if (~ARESETN) begin s_axi_arready_i <= 1'b0; s_axi_rvalid_i <= 1'b0; s_axi_rvalid_en <= 1'b0; end else begin if (s_axi_rvalid_i) begin if (S_AXI_RREADY) begin s_axi_rvalid_i <= 1'b0; s_axi_arready_i <= 1'b1; end end else if (s_axi_rvalid_en) begin s_axi_rvalid_en <= 1'b0; s_axi_rvalid_i <= 1'b1; end else if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1'b0; s_axi_rvalid_en <= 1'b1; end else begin s_axi_arready_i <= 1'b1; end end end end else begin : gen_axi reg s_axi_rlast_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i; reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt; reg [1:0] write_cs; reg [1:0] read_cs; assign S_AXI_RLAST = s_axi_rlast_i; assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i; assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i; always @(posedge ACLK) begin if (~ARESETN) begin write_cs <= P_WRITE_IDLE; s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b0; s_axi_bid_i <= 0; end else begin case (write_cs) P_WRITE_IDLE: begin if (S_AXI_AWVALID & s_axi_awready_i) begin s_axi_awready_i <= 1'b0; if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID; s_axi_wready_i <= 1'b1; write_cs <= P_WRITE_DATA; end else begin s_axi_awready_i <= 1'b1; end end P_WRITE_DATA: begin if (S_AXI_WVALID & S_AXI_WLAST) begin s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b1; write_cs <= P_WRITE_RESP; end end P_WRITE_RESP: begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1'b0; s_axi_awready_i <= 1'b1; write_cs <= P_WRITE_IDLE; end end endcase end end always @(posedge ACLK) begin if (~ARESETN) begin read_cs <= P_READ_IDLE; s_axi_arready_i <= 1'b0; s_axi_rvalid_i <= 1'b0; s_axi_rlast_i <= 1'b0; s_axi_rid_i <= 0; read_cnt <= 0; end else begin case (read_cs) P_READ_IDLE: begin if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1'b0; if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID; read_cnt <= S_AXI_ARLEN; s_axi_rlast_i <= (S_AXI_ARLEN == 0); read_cs <= P_READ_START; end else begin s_axi_arready_i <= 1'b1; end end P_READ_START: begin s_axi_rvalid_i <= 1'b1; read_cs <= P_READ_DATA; end P_READ_DATA: begin if (S_AXI_RREADY) begin if (read_cnt == 0) begin s_axi_rvalid_i <= 1'b0; s_axi_rlast_i <= 1'b0; s_axi_arready_i <= 1'b1; read_cs <= P_READ_IDLE; end else begin if (read_cnt == 1) begin s_axi_rlast_i <= 1'b1; end read_cnt <= read_cnt - 1; end end end endcase end end end endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: decerr_slave.v // // Description: // Phantom slave interface used to complete W, R and B channel transfers when an // erroneous transaction is trapped in the crossbar. //-------------------------------------------------------------------------- // // Structure: // decerr_slave // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_decerr_slave # ( parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_PROTOCOL = 0, parameter integer C_RESP = 2'b11, parameter integer C_IGNORE_ID = 0 ) ( input wire ACLK, input wire ARESETN, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, input wire S_AXI_WLAST, input wire S_AXI_WVALID, output wire S_AXI_WREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID, output wire [1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN, input wire S_AXI_ARVALID, output wire S_AXI_ARREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID, output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA, output wire [1:0] S_AXI_RRESP, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RLAST, output wire S_AXI_RVALID, input wire S_AXI_RREADY ); reg s_axi_awready_i; reg s_axi_wready_i; reg s_axi_bvalid_i; reg s_axi_arready_i; reg s_axi_rvalid_i; localparam P_WRITE_IDLE = 2'b00; localparam P_WRITE_DATA = 2'b01; localparam P_WRITE_RESP = 2'b10; localparam P_READ_IDLE = 2'b00; localparam P_READ_START = 2'b01; localparam P_READ_DATA = 2'b10; localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; assign S_AXI_BRESP = C_RESP; assign S_AXI_RRESP = C_RESP; assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}}; assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}}; assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}}; assign S_AXI_AWREADY = s_axi_awready_i; assign S_AXI_WREADY = s_axi_wready_i; assign S_AXI_BVALID = s_axi_bvalid_i; assign S_AXI_ARREADY = s_axi_arready_i; assign S_AXI_RVALID = s_axi_rvalid_i; generate if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite reg s_axi_rvalid_en; assign S_AXI_RLAST = 1'b1; assign S_AXI_BID = 0; assign S_AXI_RID = 0; always @(posedge ACLK) begin if (~ARESETN) begin s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b0; end else begin if (s_axi_bvalid_i) begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1'b0; s_axi_awready_i <= 1'b1; end end else if (S_AXI_WVALID & s_axi_wready_i) begin s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b1; end else if (S_AXI_AWVALID & s_axi_awready_i) begin s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b1; end else begin s_axi_awready_i <= 1'b1; end end end always @(posedge ACLK) begin if (~ARESETN) begin s_axi_arready_i <= 1'b0; s_axi_rvalid_i <= 1'b0; s_axi_rvalid_en <= 1'b0; end else begin if (s_axi_rvalid_i) begin if (S_AXI_RREADY) begin s_axi_rvalid_i <= 1'b0; s_axi_arready_i <= 1'b1; end end else if (s_axi_rvalid_en) begin s_axi_rvalid_en <= 1'b0; s_axi_rvalid_i <= 1'b1; end else if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1'b0; s_axi_rvalid_en <= 1'b1; end else begin s_axi_arready_i <= 1'b1; end end end end else begin : gen_axi reg s_axi_rlast_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i; reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt; reg [1:0] write_cs; reg [1:0] read_cs; assign S_AXI_RLAST = s_axi_rlast_i; assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i; assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i; always @(posedge ACLK) begin if (~ARESETN) begin write_cs <= P_WRITE_IDLE; s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b0; s_axi_bid_i <= 0; end else begin case (write_cs) P_WRITE_IDLE: begin if (S_AXI_AWVALID & s_axi_awready_i) begin s_axi_awready_i <= 1'b0; if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID; s_axi_wready_i <= 1'b1; write_cs <= P_WRITE_DATA; end else begin s_axi_awready_i <= 1'b1; end end P_WRITE_DATA: begin if (S_AXI_WVALID & S_AXI_WLAST) begin s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b1; write_cs <= P_WRITE_RESP; end end P_WRITE_RESP: begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1'b0; s_axi_awready_i <= 1'b1; write_cs <= P_WRITE_IDLE; end end endcase end end always @(posedge ACLK) begin if (~ARESETN) begin read_cs <= P_READ_IDLE; s_axi_arready_i <= 1'b0; s_axi_rvalid_i <= 1'b0; s_axi_rlast_i <= 1'b0; s_axi_rid_i <= 0; read_cnt <= 0; end else begin case (read_cs) P_READ_IDLE: begin if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1'b0; if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID; read_cnt <= S_AXI_ARLEN; s_axi_rlast_i <= (S_AXI_ARLEN == 0); read_cs <= P_READ_START; end else begin s_axi_arready_i <= 1'b1; end end P_READ_START: begin s_axi_rvalid_i <= 1'b1; read_cs <= P_READ_DATA; end P_READ_DATA: begin if (S_AXI_RREADY) begin if (read_cnt == 0) begin s_axi_rvalid_i <= 1'b0; s_axi_rlast_i <= 1'b0; s_axi_arready_i <= 1'b1; read_cs <= P_READ_IDLE; end else begin if (read_cnt == 1) begin s_axi_rlast_i <= 1'b1; end read_cnt <= read_cnt - 1; end end end endcase end end end endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // File name: decerr_slave.v // // Description: // Phantom slave interface used to complete W, R and B channel transfers when an // erroneous transaction is trapped in the crossbar. //-------------------------------------------------------------------------- // // Structure: // decerr_slave // //----------------------------------------------------------------------------- `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_decerr_slave # ( parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AXI_PROTOCOL = 0, parameter integer C_RESP = 2'b11, parameter integer C_IGNORE_ID = 0 ) ( input wire ACLK, input wire ARESETN, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID, input wire S_AXI_AWVALID, output wire S_AXI_AWREADY, input wire S_AXI_WLAST, input wire S_AXI_WVALID, output wire S_AXI_WREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID, output wire [1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID, input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN, input wire S_AXI_ARVALID, output wire S_AXI_ARREADY, output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID, output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA, output wire [1:0] S_AXI_RRESP, output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, output wire S_AXI_RLAST, output wire S_AXI_RVALID, input wire S_AXI_RREADY ); reg s_axi_awready_i; reg s_axi_wready_i; reg s_axi_bvalid_i; reg s_axi_arready_i; reg s_axi_rvalid_i; localparam P_WRITE_IDLE = 2'b00; localparam P_WRITE_DATA = 2'b01; localparam P_WRITE_RESP = 2'b10; localparam P_READ_IDLE = 2'b00; localparam P_READ_START = 2'b01; localparam P_READ_DATA = 2'b10; localparam integer P_AXI4 = 0; localparam integer P_AXI3 = 1; localparam integer P_AXILITE = 2; assign S_AXI_BRESP = C_RESP; assign S_AXI_RRESP = C_RESP; assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}}; assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}}; assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}}; assign S_AXI_AWREADY = s_axi_awready_i; assign S_AXI_WREADY = s_axi_wready_i; assign S_AXI_BVALID = s_axi_bvalid_i; assign S_AXI_ARREADY = s_axi_arready_i; assign S_AXI_RVALID = s_axi_rvalid_i; generate if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite reg s_axi_rvalid_en; assign S_AXI_RLAST = 1'b1; assign S_AXI_BID = 0; assign S_AXI_RID = 0; always @(posedge ACLK) begin if (~ARESETN) begin s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b0; end else begin if (s_axi_bvalid_i) begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1'b0; s_axi_awready_i <= 1'b1; end end else if (S_AXI_WVALID & s_axi_wready_i) begin s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b1; end else if (S_AXI_AWVALID & s_axi_awready_i) begin s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b1; end else begin s_axi_awready_i <= 1'b1; end end end always @(posedge ACLK) begin if (~ARESETN) begin s_axi_arready_i <= 1'b0; s_axi_rvalid_i <= 1'b0; s_axi_rvalid_en <= 1'b0; end else begin if (s_axi_rvalid_i) begin if (S_AXI_RREADY) begin s_axi_rvalid_i <= 1'b0; s_axi_arready_i <= 1'b1; end end else if (s_axi_rvalid_en) begin s_axi_rvalid_en <= 1'b0; s_axi_rvalid_i <= 1'b1; end else if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1'b0; s_axi_rvalid_en <= 1'b1; end else begin s_axi_arready_i <= 1'b1; end end end end else begin : gen_axi reg s_axi_rlast_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i; reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i; reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt; reg [1:0] write_cs; reg [1:0] read_cs; assign S_AXI_RLAST = s_axi_rlast_i; assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i; assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i; always @(posedge ACLK) begin if (~ARESETN) begin write_cs <= P_WRITE_IDLE; s_axi_awready_i <= 1'b0; s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b0; s_axi_bid_i <= 0; end else begin case (write_cs) P_WRITE_IDLE: begin if (S_AXI_AWVALID & s_axi_awready_i) begin s_axi_awready_i <= 1'b0; if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID; s_axi_wready_i <= 1'b1; write_cs <= P_WRITE_DATA; end else begin s_axi_awready_i <= 1'b1; end end P_WRITE_DATA: begin if (S_AXI_WVALID & S_AXI_WLAST) begin s_axi_wready_i <= 1'b0; s_axi_bvalid_i <= 1'b1; write_cs <= P_WRITE_RESP; end end P_WRITE_RESP: begin if (S_AXI_BREADY) begin s_axi_bvalid_i <= 1'b0; s_axi_awready_i <= 1'b1; write_cs <= P_WRITE_IDLE; end end endcase end end always @(posedge ACLK) begin if (~ARESETN) begin read_cs <= P_READ_IDLE; s_axi_arready_i <= 1'b0; s_axi_rvalid_i <= 1'b0; s_axi_rlast_i <= 1'b0; s_axi_rid_i <= 0; read_cnt <= 0; end else begin case (read_cs) P_READ_IDLE: begin if (S_AXI_ARVALID & s_axi_arready_i) begin s_axi_arready_i <= 1'b0; if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID; read_cnt <= S_AXI_ARLEN; s_axi_rlast_i <= (S_AXI_ARLEN == 0); read_cs <= P_READ_START; end else begin s_axi_arready_i <= 1'b1; end end P_READ_START: begin s_axi_rvalid_i <= 1'b1; read_cs <= P_READ_DATA; end P_READ_DATA: begin if (S_AXI_RREADY) begin if (read_cnt == 0) begin s_axi_rvalid_i <= 1'b0; s_axi_rlast_i <= 1'b0; s_axi_arready_i <= 1'b1; read_cs <= P_READ_IDLE; end else begin if (read_cnt == 1) begin s_axi_rlast_i <= 1'b1; end read_cnt <= read_cnt - 1; end end end endcase end end end endgenerate endmodule `default_nettype wire
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Write Data AXI3 Slave Converter // Forward and split transactions as required. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // w_axi3_conv // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_w_axi3_conv # ( parameter C_FAMILY = "none", parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_SUPPORT_SPLITTING = 1, // Implement transaction splitting logic. // Disabled whan all connected masters are AXI3 and have same or narrower data width. parameter integer C_SUPPORT_BURSTS = 1 // Disabled when all connected masters are AxiLite, // allowing logic to be simplified. ) ( // System Signals input wire ACLK, input wire ARESET, // Command Interface input wire cmd_valid, input wire [C_AXI_ID_WIDTH-1:0] cmd_id, input wire [4-1:0] cmd_length, output wire cmd_ready, // Slave Interface Write Data Ports input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire S_AXI_WLAST, input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire S_AXI_WVALID, output wire S_AXI_WREADY, // Master Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID, output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire M_AXI_WLAST, output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire M_AXI_WVALID, input wire M_AXI_WREADY ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Burst length handling. reg first_mi_word; reg [8-1:0] length_counter_1; reg [8-1:0] length_counter; wire [8-1:0] next_length_counter; wire last_beat; wire last_word; // Throttling help signals. wire cmd_ready_i; wire pop_mi_data; wire mi_stalling; // Internal SI side control signals. wire S_AXI_WREADY_I; // Internal signals for MI-side. wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID_I; wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I; wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I; wire M_AXI_WLAST_I; wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I; wire M_AXI_WVALID_I; wire M_AXI_WREADY_I; ///////////////////////////////////////////////////////////////////////////// // Handle interface handshaking: // // Forward data from SI-Side to MI-Side while a command is available. When // the transaction has completed the command is popped from the Command FIFO. // ///////////////////////////////////////////////////////////////////////////// // Pop word from SI-side. assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling; assign S_AXI_WREADY = S_AXI_WREADY_I; // Indicate when there is data available @ MI-side. assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid; // Get MI-side data. assign pop_mi_data = M_AXI_WVALID_I & M_AXI_WREADY_I; // Signal that the command is done (so that it can be poped from command queue). assign cmd_ready_i = cmd_valid & pop_mi_data & last_word; assign cmd_ready = cmd_ready_i; // Detect when MI-side is stalling. assign mi_stalling = M_AXI_WVALID_I & ~M_AXI_WREADY_I; ///////////////////////////////////////////////////////////////////////////// // Keep track of data forwarding: // // On the first cycle of the transaction is the length taken from the Command // FIFO. The length is decreased until 0 is reached which indicates last data // word. // // If bursts are unsupported will all data words be the last word, each one // from a separate transaction. // ///////////////////////////////////////////////////////////////////////////// // Select command length or counted length. always @ * begin if ( first_mi_word ) length_counter = cmd_length; else length_counter = length_counter_1; end // Calculate next length counter value. assign next_length_counter = length_counter - 1'b1; // Keep track of burst length. always @ (posedge ACLK) begin if (ARESET) begin first_mi_word <= 1'b1; length_counter_1 <= 4'b0; end else begin if ( pop_mi_data ) begin if ( M_AXI_WLAST_I ) begin first_mi_word <= 1'b1; end else begin first_mi_word <= 1'b0; end length_counter_1 <= next_length_counter; end end end // Detect last beat in a burst. assign last_beat = ( length_counter == 4'b0 ); // Determine if this last word that shall be extracted from this SI-side word. assign last_word = ( last_beat ) | ( C_SUPPORT_BURSTS == 0 ); ///////////////////////////////////////////////////////////////////////////// // Select the SI-side word to write. // // Most information can be reused directly (DATA, STRB, ID and USER). // ID is taken from the Command FIFO. // // Split transactions needs to insert new LAST transactions. So to simplify // is the LAST signal always generated. // ///////////////////////////////////////////////////////////////////////////// // ID and USER is copied from the SI word to all MI word transactions. assign M_AXI_WUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1'b0}}; // Data has to be multiplexed. assign M_AXI_WDATA_I = S_AXI_WDATA; assign M_AXI_WSTRB_I = S_AXI_WSTRB; // ID is taken directly from the command queue. assign M_AXI_WID_I = cmd_id; // Handle last flag, i.e. set for MI-side last word. assign M_AXI_WLAST_I = last_word; ///////////////////////////////////////////////////////////////////////////// // MI-side output handling // ///////////////////////////////////////////////////////////////////////////// // TODO: registered? assign M_AXI_WID = M_AXI_WID_I; assign M_AXI_WDATA = M_AXI_WDATA_I; assign M_AXI_WSTRB = M_AXI_WSTRB_I; assign M_AXI_WLAST = M_AXI_WLAST_I; assign M_AXI_WUSER = M_AXI_WUSER_I; assign M_AXI_WVALID = M_AXI_WVALID_I; assign M_AXI_WREADY_I = M_AXI_WREADY; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Write Data AXI3 Slave Converter // Forward and split transactions as required. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // w_axi3_conv // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_w_axi3_conv # ( parameter C_FAMILY = "none", parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_SUPPORT_SPLITTING = 1, // Implement transaction splitting logic. // Disabled whan all connected masters are AXI3 and have same or narrower data width. parameter integer C_SUPPORT_BURSTS = 1 // Disabled when all connected masters are AxiLite, // allowing logic to be simplified. ) ( // System Signals input wire ACLK, input wire ARESET, // Command Interface input wire cmd_valid, input wire [C_AXI_ID_WIDTH-1:0] cmd_id, input wire [4-1:0] cmd_length, output wire cmd_ready, // Slave Interface Write Data Ports input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire S_AXI_WLAST, input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire S_AXI_WVALID, output wire S_AXI_WREADY, // Master Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID, output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire M_AXI_WLAST, output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire M_AXI_WVALID, input wire M_AXI_WREADY ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Burst length handling. reg first_mi_word; reg [8-1:0] length_counter_1; reg [8-1:0] length_counter; wire [8-1:0] next_length_counter; wire last_beat; wire last_word; // Throttling help signals. wire cmd_ready_i; wire pop_mi_data; wire mi_stalling; // Internal SI side control signals. wire S_AXI_WREADY_I; // Internal signals for MI-side. wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID_I; wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I; wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I; wire M_AXI_WLAST_I; wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I; wire M_AXI_WVALID_I; wire M_AXI_WREADY_I; ///////////////////////////////////////////////////////////////////////////// // Handle interface handshaking: // // Forward data from SI-Side to MI-Side while a command is available. When // the transaction has completed the command is popped from the Command FIFO. // ///////////////////////////////////////////////////////////////////////////// // Pop word from SI-side. assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling; assign S_AXI_WREADY = S_AXI_WREADY_I; // Indicate when there is data available @ MI-side. assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid; // Get MI-side data. assign pop_mi_data = M_AXI_WVALID_I & M_AXI_WREADY_I; // Signal that the command is done (so that it can be poped from command queue). assign cmd_ready_i = cmd_valid & pop_mi_data & last_word; assign cmd_ready = cmd_ready_i; // Detect when MI-side is stalling. assign mi_stalling = M_AXI_WVALID_I & ~M_AXI_WREADY_I; ///////////////////////////////////////////////////////////////////////////// // Keep track of data forwarding: // // On the first cycle of the transaction is the length taken from the Command // FIFO. The length is decreased until 0 is reached which indicates last data // word. // // If bursts are unsupported will all data words be the last word, each one // from a separate transaction. // ///////////////////////////////////////////////////////////////////////////// // Select command length or counted length. always @ * begin if ( first_mi_word ) length_counter = cmd_length; else length_counter = length_counter_1; end // Calculate next length counter value. assign next_length_counter = length_counter - 1'b1; // Keep track of burst length. always @ (posedge ACLK) begin if (ARESET) begin first_mi_word <= 1'b1; length_counter_1 <= 4'b0; end else begin if ( pop_mi_data ) begin if ( M_AXI_WLAST_I ) begin first_mi_word <= 1'b1; end else begin first_mi_word <= 1'b0; end length_counter_1 <= next_length_counter; end end end // Detect last beat in a burst. assign last_beat = ( length_counter == 4'b0 ); // Determine if this last word that shall be extracted from this SI-side word. assign last_word = ( last_beat ) | ( C_SUPPORT_BURSTS == 0 ); ///////////////////////////////////////////////////////////////////////////// // Select the SI-side word to write. // // Most information can be reused directly (DATA, STRB, ID and USER). // ID is taken from the Command FIFO. // // Split transactions needs to insert new LAST transactions. So to simplify // is the LAST signal always generated. // ///////////////////////////////////////////////////////////////////////////// // ID and USER is copied from the SI word to all MI word transactions. assign M_AXI_WUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1'b0}}; // Data has to be multiplexed. assign M_AXI_WDATA_I = S_AXI_WDATA; assign M_AXI_WSTRB_I = S_AXI_WSTRB; // ID is taken directly from the command queue. assign M_AXI_WID_I = cmd_id; // Handle last flag, i.e. set for MI-side last word. assign M_AXI_WLAST_I = last_word; ///////////////////////////////////////////////////////////////////////////// // MI-side output handling // ///////////////////////////////////////////////////////////////////////////// // TODO: registered? assign M_AXI_WID = M_AXI_WID_I; assign M_AXI_WDATA = M_AXI_WDATA_I; assign M_AXI_WSTRB = M_AXI_WSTRB_I; assign M_AXI_WLAST = M_AXI_WLAST_I; assign M_AXI_WUSER = M_AXI_WUSER_I; assign M_AXI_WVALID = M_AXI_WVALID_I; assign M_AXI_WREADY_I = M_AXI_WREADY; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Write Data AXI3 Slave Converter // Forward and split transactions as required. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // w_axi3_conv // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_w_axi3_conv # ( parameter C_FAMILY = "none", parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_SUPPORT_SPLITTING = 1, // Implement transaction splitting logic. // Disabled whan all connected masters are AXI3 and have same or narrower data width. parameter integer C_SUPPORT_BURSTS = 1 // Disabled when all connected masters are AxiLite, // allowing logic to be simplified. ) ( // System Signals input wire ACLK, input wire ARESET, // Command Interface input wire cmd_valid, input wire [C_AXI_ID_WIDTH-1:0] cmd_id, input wire [4-1:0] cmd_length, output wire cmd_ready, // Slave Interface Write Data Ports input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire S_AXI_WLAST, input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire S_AXI_WVALID, output wire S_AXI_WREADY, // Master Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID, output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire M_AXI_WLAST, output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire M_AXI_WVALID, input wire M_AXI_WREADY ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Burst length handling. reg first_mi_word; reg [8-1:0] length_counter_1; reg [8-1:0] length_counter; wire [8-1:0] next_length_counter; wire last_beat; wire last_word; // Throttling help signals. wire cmd_ready_i; wire pop_mi_data; wire mi_stalling; // Internal SI side control signals. wire S_AXI_WREADY_I; // Internal signals for MI-side. wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID_I; wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I; wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I; wire M_AXI_WLAST_I; wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I; wire M_AXI_WVALID_I; wire M_AXI_WREADY_I; ///////////////////////////////////////////////////////////////////////////// // Handle interface handshaking: // // Forward data from SI-Side to MI-Side while a command is available. When // the transaction has completed the command is popped from the Command FIFO. // ///////////////////////////////////////////////////////////////////////////// // Pop word from SI-side. assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling; assign S_AXI_WREADY = S_AXI_WREADY_I; // Indicate when there is data available @ MI-side. assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid; // Get MI-side data. assign pop_mi_data = M_AXI_WVALID_I & M_AXI_WREADY_I; // Signal that the command is done (so that it can be poped from command queue). assign cmd_ready_i = cmd_valid & pop_mi_data & last_word; assign cmd_ready = cmd_ready_i; // Detect when MI-side is stalling. assign mi_stalling = M_AXI_WVALID_I & ~M_AXI_WREADY_I; ///////////////////////////////////////////////////////////////////////////// // Keep track of data forwarding: // // On the first cycle of the transaction is the length taken from the Command // FIFO. The length is decreased until 0 is reached which indicates last data // word. // // If bursts are unsupported will all data words be the last word, each one // from a separate transaction. // ///////////////////////////////////////////////////////////////////////////// // Select command length or counted length. always @ * begin if ( first_mi_word ) length_counter = cmd_length; else length_counter = length_counter_1; end // Calculate next length counter value. assign next_length_counter = length_counter - 1'b1; // Keep track of burst length. always @ (posedge ACLK) begin if (ARESET) begin first_mi_word <= 1'b1; length_counter_1 <= 4'b0; end else begin if ( pop_mi_data ) begin if ( M_AXI_WLAST_I ) begin first_mi_word <= 1'b1; end else begin first_mi_word <= 1'b0; end length_counter_1 <= next_length_counter; end end end // Detect last beat in a burst. assign last_beat = ( length_counter == 4'b0 ); // Determine if this last word that shall be extracted from this SI-side word. assign last_word = ( last_beat ) | ( C_SUPPORT_BURSTS == 0 ); ///////////////////////////////////////////////////////////////////////////// // Select the SI-side word to write. // // Most information can be reused directly (DATA, STRB, ID and USER). // ID is taken from the Command FIFO. // // Split transactions needs to insert new LAST transactions. So to simplify // is the LAST signal always generated. // ///////////////////////////////////////////////////////////////////////////// // ID and USER is copied from the SI word to all MI word transactions. assign M_AXI_WUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1'b0}}; // Data has to be multiplexed. assign M_AXI_WDATA_I = S_AXI_WDATA; assign M_AXI_WSTRB_I = S_AXI_WSTRB; // ID is taken directly from the command queue. assign M_AXI_WID_I = cmd_id; // Handle last flag, i.e. set for MI-side last word. assign M_AXI_WLAST_I = last_word; ///////////////////////////////////////////////////////////////////////////// // MI-side output handling // ///////////////////////////////////////////////////////////////////////////// // TODO: registered? assign M_AXI_WID = M_AXI_WID_I; assign M_AXI_WDATA = M_AXI_WDATA_I; assign M_AXI_WSTRB = M_AXI_WSTRB_I; assign M_AXI_WLAST = M_AXI_WLAST_I; assign M_AXI_WUSER = M_AXI_WUSER_I; assign M_AXI_WVALID = M_AXI_WVALID_I; assign M_AXI_WREADY_I = M_AXI_WREADY; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Write Data AXI3 Slave Converter // Forward and split transactions as required. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // w_axi3_conv // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_w_axi3_conv # ( parameter C_FAMILY = "none", parameter integer C_AXI_ID_WIDTH = 1, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_SUPPORT_SPLITTING = 1, // Implement transaction splitting logic. // Disabled whan all connected masters are AXI3 and have same or narrower data width. parameter integer C_SUPPORT_BURSTS = 1 // Disabled when all connected masters are AxiLite, // allowing logic to be simplified. ) ( // System Signals input wire ACLK, input wire ARESET, // Command Interface input wire cmd_valid, input wire [C_AXI_ID_WIDTH-1:0] cmd_id, input wire [4-1:0] cmd_length, output wire cmd_ready, // Slave Interface Write Data Ports input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, input wire S_AXI_WLAST, input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, input wire S_AXI_WVALID, output wire S_AXI_WREADY, // Master Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID, output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, output wire M_AXI_WLAST, output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, output wire M_AXI_WVALID, input wire M_AXI_WREADY ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Burst length handling. reg first_mi_word; reg [8-1:0] length_counter_1; reg [8-1:0] length_counter; wire [8-1:0] next_length_counter; wire last_beat; wire last_word; // Throttling help signals. wire cmd_ready_i; wire pop_mi_data; wire mi_stalling; // Internal SI side control signals. wire S_AXI_WREADY_I; // Internal signals for MI-side. wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID_I; wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I; wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I; wire M_AXI_WLAST_I; wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I; wire M_AXI_WVALID_I; wire M_AXI_WREADY_I; ///////////////////////////////////////////////////////////////////////////// // Handle interface handshaking: // // Forward data from SI-Side to MI-Side while a command is available. When // the transaction has completed the command is popped from the Command FIFO. // ///////////////////////////////////////////////////////////////////////////// // Pop word from SI-side. assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling; assign S_AXI_WREADY = S_AXI_WREADY_I; // Indicate when there is data available @ MI-side. assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid; // Get MI-side data. assign pop_mi_data = M_AXI_WVALID_I & M_AXI_WREADY_I; // Signal that the command is done (so that it can be poped from command queue). assign cmd_ready_i = cmd_valid & pop_mi_data & last_word; assign cmd_ready = cmd_ready_i; // Detect when MI-side is stalling. assign mi_stalling = M_AXI_WVALID_I & ~M_AXI_WREADY_I; ///////////////////////////////////////////////////////////////////////////// // Keep track of data forwarding: // // On the first cycle of the transaction is the length taken from the Command // FIFO. The length is decreased until 0 is reached which indicates last data // word. // // If bursts are unsupported will all data words be the last word, each one // from a separate transaction. // ///////////////////////////////////////////////////////////////////////////// // Select command length or counted length. always @ * begin if ( first_mi_word ) length_counter = cmd_length; else length_counter = length_counter_1; end // Calculate next length counter value. assign next_length_counter = length_counter - 1'b1; // Keep track of burst length. always @ (posedge ACLK) begin if (ARESET) begin first_mi_word <= 1'b1; length_counter_1 <= 4'b0; end else begin if ( pop_mi_data ) begin if ( M_AXI_WLAST_I ) begin first_mi_word <= 1'b1; end else begin first_mi_word <= 1'b0; end length_counter_1 <= next_length_counter; end end end // Detect last beat in a burst. assign last_beat = ( length_counter == 4'b0 ); // Determine if this last word that shall be extracted from this SI-side word. assign last_word = ( last_beat ) | ( C_SUPPORT_BURSTS == 0 ); ///////////////////////////////////////////////////////////////////////////// // Select the SI-side word to write. // // Most information can be reused directly (DATA, STRB, ID and USER). // ID is taken from the Command FIFO. // // Split transactions needs to insert new LAST transactions. So to simplify // is the LAST signal always generated. // ///////////////////////////////////////////////////////////////////////////// // ID and USER is copied from the SI word to all MI word transactions. assign M_AXI_WUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1'b0}}; // Data has to be multiplexed. assign M_AXI_WDATA_I = S_AXI_WDATA; assign M_AXI_WSTRB_I = S_AXI_WSTRB; // ID is taken directly from the command queue. assign M_AXI_WID_I = cmd_id; // Handle last flag, i.e. set for MI-side last word. assign M_AXI_WLAST_I = last_word; ///////////////////////////////////////////////////////////////////////////// // MI-side output handling // ///////////////////////////////////////////////////////////////////////////// // TODO: registered? assign M_AXI_WID = M_AXI_WID_I; assign M_AXI_WDATA = M_AXI_WDATA_I; assign M_AXI_WSTRB = M_AXI_WSTRB_I; assign M_AXI_WLAST = M_AXI_WLAST_I; assign M_AXI_WUSER = M_AXI_WUSER_I; assign M_AXI_WVALID = M_AXI_WVALID_I; assign M_AXI_WREADY_I = M_AXI_WREADY; endmodule
/* Copyright (c) 2014-2018 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ // Language: Verilog-2001 `timescale 1 ns / 1 ps /* * Synchronizes switch and button inputs with a slow sampled shift register */ module debounce_switch #( parameter WIDTH=1, // width of the input and output signals parameter N=3, // length of shift register parameter RATE=125000 // clock division factor )( input wire clk, input wire rst, input wire [WIDTH-1:0] in, output wire [WIDTH-1:0] out ); reg [23:0] cnt_reg = 24'd0; reg [N-1:0] debounce_reg[WIDTH-1:0]; reg [WIDTH-1:0] state; /* * The synchronized output is the state register */ assign out = state; integer k; always @(posedge clk or posedge rst) begin if (rst) begin cnt_reg <= 0; state <= 0; for (k = 0; k < WIDTH; k = k + 1) begin debounce_reg[k] <= 0; end end else begin if (cnt_reg < RATE) begin cnt_reg <= cnt_reg + 24'd1; end else begin cnt_reg <= 24'd0; end if (cnt_reg == 24'd0) begin for (k = 0; k < WIDTH; k = k + 1) begin debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; end end for (k = 0; k < WIDTH; k = k + 1) begin if (|debounce_reg[k] == 0) begin state[k] <= 0; end else if (&debounce_reg[k] == 1) begin state[k] <= 1; end else begin state[k] <= state[k]; end end end end endmodule
/* Copyright (c) 2014-2018 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ // Language: Verilog-2001 `timescale 1 ns / 1 ps /* * Synchronizes switch and button inputs with a slow sampled shift register */ module debounce_switch #( parameter WIDTH=1, // width of the input and output signals parameter N=3, // length of shift register parameter RATE=125000 // clock division factor )( input wire clk, input wire rst, input wire [WIDTH-1:0] in, output wire [WIDTH-1:0] out ); reg [23:0] cnt_reg = 24'd0; reg [N-1:0] debounce_reg[WIDTH-1:0]; reg [WIDTH-1:0] state; /* * The synchronized output is the state register */ assign out = state; integer k; always @(posedge clk or posedge rst) begin if (rst) begin cnt_reg <= 0; state <= 0; for (k = 0; k < WIDTH; k = k + 1) begin debounce_reg[k] <= 0; end end else begin if (cnt_reg < RATE) begin cnt_reg <= cnt_reg + 24'd1; end else begin cnt_reg <= 24'd0; end if (cnt_reg == 24'd0) begin for (k = 0; k < WIDTH; k = k + 1) begin debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; end end for (k = 0; k < WIDTH; k = k + 1) begin if (|debounce_reg[k] == 0) begin state[k] <= 0; end else if (&debounce_reg[k] == 1) begin state[k] <= 1; end else begin state[k] <= state[k]; end end end end endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 03/12/2016 06:26:54 PM // Design Name: // Module Name: shift_mux_array // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module shift_mux_array #(parameter SWR=26, parameter LEVEL=5) ( input wire [SWR-1:0] Data_i, input wire select_i, input wire bit_shift_i, output wire [SWR-1:0] Data_o ); genvar j; generate for (j=0; j<=SWR-1 ; j=j+1) begin localparam sh=(2**LEVEL)+j; //value for second mux input. It changes in exponentation by 2 for each level case (sh>SWR-1) 1'b1:begin Multiplexer_AC #(.W(1)) rotate_mux( .ctrl(select_i), .D0 (Data_i[j]), .D1 (bit_shift_i), .S (Data_o[j]) ); end 1'b0:begin Multiplexer_AC #(.W(1)) rotate_mux( .ctrl(select_i), .D0 (Data_i[j]), .D1 (Data_i[sh]), .S (Data_o[j]) ); end endcase end endgenerate endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 03/12/2016 06:26:54 PM // Design Name: // Module Name: shift_mux_array // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module shift_mux_array #(parameter SWR=26, parameter LEVEL=5) ( input wire [SWR-1:0] Data_i, input wire select_i, input wire bit_shift_i, output wire [SWR-1:0] Data_o ); genvar j; generate for (j=0; j<=SWR-1 ; j=j+1) begin localparam sh=(2**LEVEL)+j; //value for second mux input. It changes in exponentation by 2 for each level case (sh>SWR-1) 1'b1:begin Multiplexer_AC #(.W(1)) rotate_mux( .ctrl(select_i), .D0 (Data_i[j]), .D1 (bit_shift_i), .S (Data_o[j]) ); end 1'b0:begin Multiplexer_AC #(.W(1)) rotate_mux( .ctrl(select_i), .D0 (Data_i[j]), .D1 (Data_i[sh]), .S (Data_o[j]) ); end endcase end endgenerate endmodule
// This is a component of pluto_servo, a PWM servo driver and quadrature // counter for emc2 // Copyright 2006 Jeff Epler <jepler@unpythonic.net> // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr, nAddrStr, dout, din, quadA, quadB, quadZ, up, down); parameter QW=14; input clk; output led, nConfig; inout [7:0] pport_data; input nWrite; output nWait; input nDataStr, nAddrStr, epp_nReset; wire do_tristate; reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout; input [7:0] din; input [3:0] quadA; input [3:0] quadB; input [3:0] quadZ; wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up; wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down; reg Zpolarity; wire [2*QW:0] quad0, quad1, quad2, quad3; wire do_enable_wdt; wire pwm_at_top; wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate); // PWM stuff // PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt reg [10:0] pwmcnt; wire [10:0] top = 11'd2046; assign pwm_at_top = (pwmcnt == top); reg [15:0] pwm0, pwm1, pwm2, pwm3; always @(posedge clk) begin if(pwm_at_top) pwmcnt <= 0; else pwmcnt <= pwmcnt + 11'd1; end wire [10:0] pwmrev = { pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9], pwmcnt[10], pwmcnt[3:0]}; wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt; // wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt; // wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt; // wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt; wire pwmact0 = pwm0[10:0] > pwmcmp0; wire pwmact1 = pwm1[10:0] > pwmcmp0; wire pwmact2 = pwm2[10:0] > pwmcmp0; wire pwmact3 = pwm3[10:0] > pwmcmp0; assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0); assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1); assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2); assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3); assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0); assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1); assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2); assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3); // Quadrature stuff // Quadrature is digitized at 40MHz into 14-bit counters // Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period reg qtest; wire qr0, qr1, qr2, qr3; quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0); quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1); quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2); quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3); // EPP stuff wire EPP_write = ~nWrite; wire EPP_read = nWrite; wire EPP_addr_strobe = ~nAddrStr; wire EPP_data_strobe = ~nDataStr; wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe; wire EPP_wait; assign nWait = ~EPP_wait; wire [7:0] EPP_datain = pport_data; wire [7:0] EPP_dataout; assign pport_data = EPP_dataout; reg [4:0] EPP_strobe_reg; always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe}; wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01); // reg led; assign EPP_wait = EPP_strobe_reg[4]; reg[4:0] addr_reg; reg[7:0] lowbyte; always @(posedge clk) if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin addr_reg <= EPP_datain[4:0]; end else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1; always @(posedge clk) begin if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd9) begin real_dout <= { EPP_datain[1:0], lowbyte }; Zpolarity <= EPP_datain[7]; qtest <= EPP_datain[5]; end else lowbyte <= EPP_datain; end end reg [31:0] data_buf; always @(posedge clk) begin if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin if(addr_reg[4:2] == 3'd0) data_buf <= quad0; else if(addr_reg[4:2] == 3'd1) data_buf <= quad1; else if(addr_reg[4:2] == 3'd2) data_buf <= quad2; else if(addr_reg[4:2] == 3'd3) data_buf <= quad3; else if(addr_reg[4:2] == 3'd4) data_buf <= {quadA, quadB, quadZ, din}; end end // the addr_reg test looks funny because it is auto-incremented in an always // block so "1" reads the low byte, "2 and "3" read middle bytes, and "0" // reads the high byte I have a feeling that I'm doing this in the wrong way. wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] : (addr_reg[1:0] == 2'd2 ? data_buf[15:8] : (addr_reg[1:0] == 2'd3 ? data_buf[23:16] : data_buf[31:24])); wire [7:0] EPP_data_mux = data_reg; assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ; assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6]; assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0); assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1); assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2); assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3); assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]); assign nConfig = epp_nReset; // 1'b1; endmodule
// This is a component of pluto_servo, a PWM servo driver and quadrature // counter for emc2 // Copyright 2006 Jeff Epler <jepler@unpythonic.net> // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr, nAddrStr, dout, din, quadA, quadB, quadZ, up, down); parameter QW=14; input clk; output led, nConfig; inout [7:0] pport_data; input nWrite; output nWait; input nDataStr, nAddrStr, epp_nReset; wire do_tristate; reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout; input [7:0] din; input [3:0] quadA; input [3:0] quadB; input [3:0] quadZ; wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up; wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down; reg Zpolarity; wire [2*QW:0] quad0, quad1, quad2, quad3; wire do_enable_wdt; wire pwm_at_top; wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate); // PWM stuff // PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt reg [10:0] pwmcnt; wire [10:0] top = 11'd2046; assign pwm_at_top = (pwmcnt == top); reg [15:0] pwm0, pwm1, pwm2, pwm3; always @(posedge clk) begin if(pwm_at_top) pwmcnt <= 0; else pwmcnt <= pwmcnt + 11'd1; end wire [10:0] pwmrev = { pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9], pwmcnt[10], pwmcnt[3:0]}; wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt; // wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt; // wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt; // wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt; wire pwmact0 = pwm0[10:0] > pwmcmp0; wire pwmact1 = pwm1[10:0] > pwmcmp0; wire pwmact2 = pwm2[10:0] > pwmcmp0; wire pwmact3 = pwm3[10:0] > pwmcmp0; assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0); assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1); assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2); assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3); assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0); assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1); assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2); assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3); // Quadrature stuff // Quadrature is digitized at 40MHz into 14-bit counters // Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period reg qtest; wire qr0, qr1, qr2, qr3; quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0); quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1); quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2); quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3); // EPP stuff wire EPP_write = ~nWrite; wire EPP_read = nWrite; wire EPP_addr_strobe = ~nAddrStr; wire EPP_data_strobe = ~nDataStr; wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe; wire EPP_wait; assign nWait = ~EPP_wait; wire [7:0] EPP_datain = pport_data; wire [7:0] EPP_dataout; assign pport_data = EPP_dataout; reg [4:0] EPP_strobe_reg; always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe}; wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01); // reg led; assign EPP_wait = EPP_strobe_reg[4]; reg[4:0] addr_reg; reg[7:0] lowbyte; always @(posedge clk) if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin addr_reg <= EPP_datain[4:0]; end else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1; always @(posedge clk) begin if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd9) begin real_dout <= { EPP_datain[1:0], lowbyte }; Zpolarity <= EPP_datain[7]; qtest <= EPP_datain[5]; end else lowbyte <= EPP_datain; end end reg [31:0] data_buf; always @(posedge clk) begin if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin if(addr_reg[4:2] == 3'd0) data_buf <= quad0; else if(addr_reg[4:2] == 3'd1) data_buf <= quad1; else if(addr_reg[4:2] == 3'd2) data_buf <= quad2; else if(addr_reg[4:2] == 3'd3) data_buf <= quad3; else if(addr_reg[4:2] == 3'd4) data_buf <= {quadA, quadB, quadZ, din}; end end // the addr_reg test looks funny because it is auto-incremented in an always // block so "1" reads the low byte, "2 and "3" read middle bytes, and "0" // reads the high byte I have a feeling that I'm doing this in the wrong way. wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] : (addr_reg[1:0] == 2'd2 ? data_buf[15:8] : (addr_reg[1:0] == 2'd3 ? data_buf[23:16] : data_buf[31:24])); wire [7:0] EPP_data_mux = data_reg; assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ; assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6]; assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0); assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1); assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2); assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3); assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]); assign nConfig = epp_nReset; // 1'b1; endmodule
// This is a component of pluto_servo, a PWM servo driver and quadrature // counter for emc2 // Copyright 2006 Jeff Epler <jepler@unpythonic.net> // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr, nAddrStr, dout, din, quadA, quadB, quadZ, up, down); parameter QW=14; input clk; output led, nConfig; inout [7:0] pport_data; input nWrite; output nWait; input nDataStr, nAddrStr, epp_nReset; wire do_tristate; reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout; input [7:0] din; input [3:0] quadA; input [3:0] quadB; input [3:0] quadZ; wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up; wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down; reg Zpolarity; wire [2*QW:0] quad0, quad1, quad2, quad3; wire do_enable_wdt; wire pwm_at_top; wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate); // PWM stuff // PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt reg [10:0] pwmcnt; wire [10:0] top = 11'd2046; assign pwm_at_top = (pwmcnt == top); reg [15:0] pwm0, pwm1, pwm2, pwm3; always @(posedge clk) begin if(pwm_at_top) pwmcnt <= 0; else pwmcnt <= pwmcnt + 11'd1; end wire [10:0] pwmrev = { pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9], pwmcnt[10], pwmcnt[3:0]}; wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt; // wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt; // wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt; // wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt; wire pwmact0 = pwm0[10:0] > pwmcmp0; wire pwmact1 = pwm1[10:0] > pwmcmp0; wire pwmact2 = pwm2[10:0] > pwmcmp0; wire pwmact3 = pwm3[10:0] > pwmcmp0; assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0); assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1); assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2); assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3); assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0); assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1); assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2); assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3); // Quadrature stuff // Quadrature is digitized at 40MHz into 14-bit counters // Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period reg qtest; wire qr0, qr1, qr2, qr3; quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0); quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1); quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2); quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3); // EPP stuff wire EPP_write = ~nWrite; wire EPP_read = nWrite; wire EPP_addr_strobe = ~nAddrStr; wire EPP_data_strobe = ~nDataStr; wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe; wire EPP_wait; assign nWait = ~EPP_wait; wire [7:0] EPP_datain = pport_data; wire [7:0] EPP_dataout; assign pport_data = EPP_dataout; reg [4:0] EPP_strobe_reg; always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe}; wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01); // reg led; assign EPP_wait = EPP_strobe_reg[4]; reg[4:0] addr_reg; reg[7:0] lowbyte; always @(posedge clk) if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin addr_reg <= EPP_datain[4:0]; end else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1; always @(posedge clk) begin if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd9) begin real_dout <= { EPP_datain[1:0], lowbyte }; Zpolarity <= EPP_datain[7]; qtest <= EPP_datain[5]; end else lowbyte <= EPP_datain; end end reg [31:0] data_buf; always @(posedge clk) begin if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin if(addr_reg[4:2] == 3'd0) data_buf <= quad0; else if(addr_reg[4:2] == 3'd1) data_buf <= quad1; else if(addr_reg[4:2] == 3'd2) data_buf <= quad2; else if(addr_reg[4:2] == 3'd3) data_buf <= quad3; else if(addr_reg[4:2] == 3'd4) data_buf <= {quadA, quadB, quadZ, din}; end end // the addr_reg test looks funny because it is auto-incremented in an always // block so "1" reads the low byte, "2 and "3" read middle bytes, and "0" // reads the high byte I have a feeling that I'm doing this in the wrong way. wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] : (addr_reg[1:0] == 2'd2 ? data_buf[15:8] : (addr_reg[1:0] == 2'd3 ? data_buf[23:16] : data_buf[31:24])); wire [7:0] EPP_data_mux = data_reg; assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ; assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6]; assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0); assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1); assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2); assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3); assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]); assign nConfig = epp_nReset; // 1'b1; endmodule
// This is a component of pluto_servo, a PWM servo driver and quadrature // counter for emc2 // Copyright 2006 Jeff Epler <jepler@unpythonic.net> // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr, nAddrStr, dout, din, quadA, quadB, quadZ, up, down); parameter QW=14; input clk; output led, nConfig; inout [7:0] pport_data; input nWrite; output nWait; input nDataStr, nAddrStr, epp_nReset; wire do_tristate; reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout; input [7:0] din; input [3:0] quadA; input [3:0] quadB; input [3:0] quadZ; wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up; wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down; reg Zpolarity; wire [2*QW:0] quad0, quad1, quad2, quad3; wire do_enable_wdt; wire pwm_at_top; wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate); // PWM stuff // PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt reg [10:0] pwmcnt; wire [10:0] top = 11'd2046; assign pwm_at_top = (pwmcnt == top); reg [15:0] pwm0, pwm1, pwm2, pwm3; always @(posedge clk) begin if(pwm_at_top) pwmcnt <= 0; else pwmcnt <= pwmcnt + 11'd1; end wire [10:0] pwmrev = { pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9], pwmcnt[10], pwmcnt[3:0]}; wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt; // wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt; // wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt; // wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt; wire pwmact0 = pwm0[10:0] > pwmcmp0; wire pwmact1 = pwm1[10:0] > pwmcmp0; wire pwmact2 = pwm2[10:0] > pwmcmp0; wire pwmact3 = pwm3[10:0] > pwmcmp0; assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0); assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1); assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2); assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3); assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0); assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1); assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2); assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3); // Quadrature stuff // Quadrature is digitized at 40MHz into 14-bit counters // Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period reg qtest; wire qr0, qr1, qr2, qr3; quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0); quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1); quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2); quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3); // EPP stuff wire EPP_write = ~nWrite; wire EPP_read = nWrite; wire EPP_addr_strobe = ~nAddrStr; wire EPP_data_strobe = ~nDataStr; wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe; wire EPP_wait; assign nWait = ~EPP_wait; wire [7:0] EPP_datain = pport_data; wire [7:0] EPP_dataout; assign pport_data = EPP_dataout; reg [4:0] EPP_strobe_reg; always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe}; wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01); // reg led; assign EPP_wait = EPP_strobe_reg[4]; reg[4:0] addr_reg; reg[7:0] lowbyte; always @(posedge clk) if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin addr_reg <= EPP_datain[4:0]; end else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1; always @(posedge clk) begin if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte }; else if(addr_reg[3:0] == 4'd9) begin real_dout <= { EPP_datain[1:0], lowbyte }; Zpolarity <= EPP_datain[7]; qtest <= EPP_datain[5]; end else lowbyte <= EPP_datain; end end reg [31:0] data_buf; always @(posedge clk) begin if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin if(addr_reg[4:2] == 3'd0) data_buf <= quad0; else if(addr_reg[4:2] == 3'd1) data_buf <= quad1; else if(addr_reg[4:2] == 3'd2) data_buf <= quad2; else if(addr_reg[4:2] == 3'd3) data_buf <= quad3; else if(addr_reg[4:2] == 3'd4) data_buf <= {quadA, quadB, quadZ, din}; end end // the addr_reg test looks funny because it is auto-incremented in an always // block so "1" reads the low byte, "2 and "3" read middle bytes, and "0" // reads the high byte I have a feeling that I'm doing this in the wrong way. wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] : (addr_reg[1:0] == 2'd2 ? data_buf[15:8] : (addr_reg[1:0] == 2'd3 ? data_buf[23:16] : data_buf[31:24])); wire [7:0] EPP_data_mux = data_reg; assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ; assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6]; assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0); assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1); assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2); assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3); assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]); assign nConfig = epp_nReset; // 1'b1; endmodule
// This is a component of pluto_step, a hardware step waveform generator // Copyright 2007 Jeff Epler <jepler@unpythonic.net> // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // install ubuntu package "verilog" from universe // Compile with: iverilog -DTESTING test_stepgen.v stepgen.v // run with "./a.out | less" and look at output for problems module test_stepgen(); reg clk; reg [4:0] vel; wire [19:0] pos; wire step, dir; stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3); integer q; reg ost; initial begin vel = 5'h8; // two useful test cases: // vel=5'h8 (max step speed) // vel=5'h2 (~1 step per repeat) q = 0; repeat(50) begin repeat(50) begin #20 clk<=1; #20 clk<=0; if(step && !ost) begin if(dir) q = q+1; else q = q - 1; end ost <= step; $display("%d %d %x %x %d %d %d %d %d", step, dir, vel, pos, s.state, s.ones, s.pbit, s.timer, q); end vel = 6'h20 - vel; end end endmodule
// This is a component of pluto_step, a hardware step waveform generator // Copyright 2007 Jeff Epler <jepler@unpythonic.net> // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // install ubuntu package "verilog" from universe // Compile with: iverilog -DTESTING test_stepgen.v stepgen.v // run with "./a.out | less" and look at output for problems module test_stepgen(); reg clk; reg [4:0] vel; wire [19:0] pos; wire step, dir; stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3); integer q; reg ost; initial begin vel = 5'h8; // two useful test cases: // vel=5'h8 (max step speed) // vel=5'h2 (~1 step per repeat) q = 0; repeat(50) begin repeat(50) begin #20 clk<=1; #20 clk<=0; if(step && !ost) begin if(dir) q = q+1; else q = q - 1; end ost <= step; $display("%d %d %x %x %d %d %d %d %d", step, dir, vel, pos, s.state, s.ones, s.pbit, s.timer, q); end vel = 6'h20 - vel; end end endmodule
// This is a component of pluto_step, a hardware step waveform generator // Copyright 2007 Jeff Epler <jepler@unpythonic.net> // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // install ubuntu package "verilog" from universe // Compile with: iverilog -DTESTING test_stepgen.v stepgen.v // run with "./a.out | less" and look at output for problems module test_stepgen(); reg clk; reg [4:0] vel; wire [19:0] pos; wire step, dir; stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3); integer q; reg ost; initial begin vel = 5'h8; // two useful test cases: // vel=5'h8 (max step speed) // vel=5'h2 (~1 step per repeat) q = 0; repeat(50) begin repeat(50) begin #20 clk<=1; #20 clk<=0; if(step && !ost) begin if(dir) q = q+1; else q = q - 1; end ost <= step; $display("%d %d %x %x %d %d %d %d %d", step, dir, vel, pos, s.state, s.ones, s.pbit, s.timer, q); end vel = 6'h20 - vel; end end endmodule
// This is a component of pluto_step, a hardware step waveform generator // Copyright 2007 Jeff Epler <jepler@unpythonic.net> // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // install ubuntu package "verilog" from universe // Compile with: iverilog -DTESTING test_stepgen.v stepgen.v // run with "./a.out | less" and look at output for problems module test_stepgen(); reg clk; reg [4:0] vel; wire [19:0] pos; wire step, dir; stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3); integer q; reg ost; initial begin vel = 5'h8; // two useful test cases: // vel=5'h8 (max step speed) // vel=5'h2 (~1 step per repeat) q = 0; repeat(50) begin repeat(50) begin #20 clk<=1; #20 clk<=0; if(step && !ost) begin if(dir) q = q+1; else q = q - 1; end ost <= step; $display("%d %d %x %x %d %d %d %d %d", step, dir, vel, pos, s.state, s.ones, s.pbit, s.timer, q); end vel = 6'h20 - vel; end end endmodule
/* ******************************************************************************* * * FIFO Generator - Verilog Behavioral Model * ******************************************************************************* * * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. * * This file contains confidential and proprietary information * of Xilinx, Inc. and is protected under U.S. and * international copyright and other intellectual property * laws. * * DISCLAIMER * This disclaimer is not a license and does not grant any * rights to the materials distributed herewith. Except as * otherwise provided in a valid license issued to you by * Xilinx, and to the maximum extent permitted by applicable * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * (2) Xilinx shall not be liable (whether in contract or tort, * including negligence, or under any other theory of * liability) for any loss or damage of any kind or nature * related to, arising under or in connection with these * materials, including for any direct, or any indirect, * special, incidental, or consequential loss or damage * (including loss of data, profits, goodwill, or any type of * loss or damage suffered as a result of any action brought * by a third party) even if such damage or loss was * reasonably foreseeable or Xilinx had been advised of the * possibility of the same. * * CRITICAL APPLICATIONS * Xilinx products are not designed or intended to be fail- * safe, or for use in any application requiring fail-safe * performance, such as life-support or safety devices or * systems, Class III medical devices, nuclear facilities, * applications related to the deployment of airbags, or any * other applications that could lead to death, personal * injury, or severe property or environmental damage * (individually and collectively, "Critical * Applications"). Customer assumes the sole risk and * liability of any use of Xilinx products in Critical * Applications, subject only to applicable laws and * regulations governing limitations on product liability. * * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * PART OF THIS FILE AT ALL TIMES. * ******************************************************************************* ******************************************************************************* * * Filename: fifo_generator_vlog_beh.v * * Author : Xilinx * ******************************************************************************* * Structure: * * fifo_generator_vlog_beh.v * | * +-fifo_generator_v13_1_3_bhv_ver_as * | * +-fifo_generator_v13_1_3_bhv_ver_ss * | * +-fifo_generator_v13_1_3_bhv_ver_preload0 * ******************************************************************************* * Description: * * The Verilog behavioral model for the FIFO Generator. * * The behavioral model has three parts: * - The behavioral model for independent clocks FIFOs (_as) * - The behavioral model for common clock FIFOs (_ss) * - The "preload logic" block which implements First-word Fall-through * ******************************************************************************* * Description: * The verilog behavioral model for the FIFO generator core. * ******************************************************************************* */ `timescale 1ps/1ps `ifndef TCQ `define TCQ 100 `endif /******************************************************************************* * Declaration of top-level module ******************************************************************************/ module fifo_generator_vlog_beh #( //----------------------------------------------------------------------- // Generic Declarations //----------------------------------------------------------------------- parameter C_COMMON_CLOCK = 0, parameter C_COUNT_TYPE = 0, parameter C_DATA_COUNT_WIDTH = 2, parameter C_DEFAULT_VALUE = "", parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_ENABLE_RLOCS = 0, parameter C_FAMILY = "", parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_ALMOST_EMPTY = 0, parameter C_HAS_ALMOST_FULL = 0, parameter C_HAS_BACKUP = 0, parameter C_HAS_DATA_COUNT = 0, parameter C_HAS_INT_CLK = 0, parameter C_HAS_MEMINIT_FILE = 0, parameter C_HAS_OVERFLOW = 0, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_RD_RST = 0, parameter C_HAS_RST = 1, parameter C_HAS_SRST = 0, parameter C_HAS_UNDERFLOW = 0, parameter C_HAS_VALID = 0, parameter C_HAS_WR_ACK = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_HAS_WR_RST = 0, parameter C_IMPLEMENTATION_TYPE = 0, parameter C_INIT_WR_PNTR_VAL = 0, parameter C_MEMORY_TYPE = 1, parameter C_MIF_FILE_NAME = "", parameter C_OPTIMIZATION_MODE = 0, parameter C_OVERFLOW_LOW = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_PRELOAD_LATENCY = 1, parameter C_PRELOAD_REGS = 0, parameter C_PRIM_FIFO_TYPE = "4kx4", parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, parameter C_PROG_EMPTY_TYPE = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, parameter C_PROG_FULL_TYPE = 0, parameter C_RD_DATA_COUNT_WIDTH = 2, parameter C_RD_DEPTH = 256, parameter C_RD_FREQ = 1, parameter C_RD_PNTR_WIDTH = 8, parameter C_UNDERFLOW_LOW = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_ECC = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_USE_PIPELINE_REG = 0, parameter C_POWER_SAVING_MODE = 0, parameter C_USE_FIFO16_FLAGS = 0, parameter C_USE_FWFT_DATA_COUNT = 0, parameter C_VALID_LOW = 0, parameter C_WR_ACK_LOW = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_FREQ = 1, parameter C_WR_PNTR_WIDTH = 8, parameter C_WR_RESPONSE_LATENCY = 1, parameter C_MSGON_VAL = 1, parameter C_ENABLE_RST_SYNC = 1, parameter C_ERROR_INJECTION_TYPE = 0, parameter C_SYNCHRONIZER_STAGE = 2, // AXI Interface related parameters start here parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3 parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3 parameter C_HAS_AXI_WR_CHANNEL = 0, parameter C_HAS_AXI_RD_CHANNEL = 0, parameter C_HAS_SLAVE_CE = 0, parameter C_HAS_MASTER_CE = 0, parameter C_ADD_NGC_CONSTRAINT = 0, parameter C_USE_COMMON_UNDERFLOW = 0, parameter C_USE_COMMON_OVERFLOW = 0, parameter C_USE_DEFAULT_SETTINGS = 0, // AXI Full/Lite parameter C_AXI_ID_WIDTH = 0, parameter C_AXI_ADDR_WIDTH = 0, parameter C_AXI_DATA_WIDTH = 0, parameter C_AXI_LEN_WIDTH = 8, parameter C_AXI_LOCK_WIDTH = 2, parameter C_HAS_AXI_ID = 0, parameter C_HAS_AXI_AWUSER = 0, parameter C_HAS_AXI_WUSER = 0, parameter C_HAS_AXI_BUSER = 0, parameter C_HAS_AXI_ARUSER = 0, parameter C_HAS_AXI_RUSER = 0, parameter C_AXI_ARUSER_WIDTH = 0, parameter C_AXI_AWUSER_WIDTH = 0, parameter C_AXI_WUSER_WIDTH = 0, parameter C_AXI_BUSER_WIDTH = 0, parameter C_AXI_RUSER_WIDTH = 0, // AXI Streaming parameter C_HAS_AXIS_TDATA = 0, parameter C_HAS_AXIS_TID = 0, parameter C_HAS_AXIS_TDEST = 0, parameter C_HAS_AXIS_TUSER = 0, parameter C_HAS_AXIS_TREADY = 0, parameter C_HAS_AXIS_TLAST = 0, parameter C_HAS_AXIS_TSTRB = 0, parameter C_HAS_AXIS_TKEEP = 0, parameter C_AXIS_TDATA_WIDTH = 1, parameter C_AXIS_TID_WIDTH = 1, parameter C_AXIS_TDEST_WIDTH = 1, parameter C_AXIS_TUSER_WIDTH = 1, parameter C_AXIS_TSTRB_WIDTH = 1, parameter C_AXIS_TKEEP_WIDTH = 1, // AXI Channel Type // WACH --> Write Address Channel // WDCH --> Write Data Channel // WRCH --> Write Response Channel // RACH --> Read Address Channel // RDCH --> Read Data Channel // AXIS --> AXI Streaming parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie // AXI Implementation Type // 1 = Common Clock Block RAM FIFO // 2 = Common Clock Distributed RAM FIFO // 11 = Independent Clock Block RAM FIFO // 12 = Independent Clock Distributed RAM FIFO parameter C_IMPLEMENTATION_TYPE_WACH = 0, parameter C_IMPLEMENTATION_TYPE_WDCH = 0, parameter C_IMPLEMENTATION_TYPE_WRCH = 0, parameter C_IMPLEMENTATION_TYPE_RACH = 0, parameter C_IMPLEMENTATION_TYPE_RDCH = 0, parameter C_IMPLEMENTATION_TYPE_AXIS = 0, // AXI FIFO Type // 0 = Data FIFO // 1 = Packet FIFO // 2 = Low Latency Sync FIFO // 3 = Low Latency Async FIFO parameter C_APPLICATION_TYPE_WACH = 0, parameter C_APPLICATION_TYPE_WDCH = 0, parameter C_APPLICATION_TYPE_WRCH = 0, parameter C_APPLICATION_TYPE_RACH = 0, parameter C_APPLICATION_TYPE_RDCH = 0, parameter C_APPLICATION_TYPE_AXIS = 0, // AXI Built-in FIFO Primitive Type // 512x36, 1kx18, 2kx9, 4kx4, etc parameter C_PRIM_FIFO_TYPE_WACH = "512x36", parameter C_PRIM_FIFO_TYPE_WDCH = "512x36", parameter C_PRIM_FIFO_TYPE_WRCH = "512x36", parameter C_PRIM_FIFO_TYPE_RACH = "512x36", parameter C_PRIM_FIFO_TYPE_RDCH = "512x36", parameter C_PRIM_FIFO_TYPE_AXIS = "512x36", // Enable ECC // 0 = ECC disabled // 1 = ECC enabled parameter C_USE_ECC_WACH = 0, parameter C_USE_ECC_WDCH = 0, parameter C_USE_ECC_WRCH = 0, parameter C_USE_ECC_RACH = 0, parameter C_USE_ECC_RDCH = 0, parameter C_USE_ECC_AXIS = 0, // ECC Error Injection Type // 0 = No Error Injection // 1 = Single Bit Error Injection // 2 = Double Bit Error Injection // 3 = Single Bit and Double Bit Error Injection parameter C_ERROR_INJECTION_TYPE_WACH = 0, parameter C_ERROR_INJECTION_TYPE_WDCH = 0, parameter C_ERROR_INJECTION_TYPE_WRCH = 0, parameter C_ERROR_INJECTION_TYPE_RACH = 0, parameter C_ERROR_INJECTION_TYPE_RDCH = 0, parameter C_ERROR_INJECTION_TYPE_AXIS = 0, // Input Data Width // Accumulation of all AXI input signal's width parameter C_DIN_WIDTH_WACH = 1, parameter C_DIN_WIDTH_WDCH = 1, parameter C_DIN_WIDTH_WRCH = 1, parameter C_DIN_WIDTH_RACH = 1, parameter C_DIN_WIDTH_RDCH = 1, parameter C_DIN_WIDTH_AXIS = 1, parameter C_WR_DEPTH_WACH = 16, parameter C_WR_DEPTH_WDCH = 16, parameter C_WR_DEPTH_WRCH = 16, parameter C_WR_DEPTH_RACH = 16, parameter C_WR_DEPTH_RDCH = 16, parameter C_WR_DEPTH_AXIS = 16, parameter C_WR_PNTR_WIDTH_WACH = 4, parameter C_WR_PNTR_WIDTH_WDCH = 4, parameter C_WR_PNTR_WIDTH_WRCH = 4, parameter C_WR_PNTR_WIDTH_RACH = 4, parameter C_WR_PNTR_WIDTH_RDCH = 4, parameter C_WR_PNTR_WIDTH_AXIS = 4, parameter C_HAS_DATA_COUNTS_WACH = 0, parameter C_HAS_DATA_COUNTS_WDCH = 0, parameter C_HAS_DATA_COUNTS_WRCH = 0, parameter C_HAS_DATA_COUNTS_RACH = 0, parameter C_HAS_DATA_COUNTS_RDCH = 0, parameter C_HAS_DATA_COUNTS_AXIS = 0, parameter C_HAS_PROG_FLAGS_WACH = 0, parameter C_HAS_PROG_FLAGS_WDCH = 0, parameter C_HAS_PROG_FLAGS_WRCH = 0, parameter C_HAS_PROG_FLAGS_RACH = 0, parameter C_HAS_PROG_FLAGS_RDCH = 0, parameter C_HAS_PROG_FLAGS_AXIS = 0, parameter C_PROG_FULL_TYPE_WACH = 0, parameter C_PROG_FULL_TYPE_WDCH = 0, parameter C_PROG_FULL_TYPE_WRCH = 0, parameter C_PROG_FULL_TYPE_RACH = 0, parameter C_PROG_FULL_TYPE_RDCH = 0, parameter C_PROG_FULL_TYPE_AXIS = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0, parameter C_PROG_EMPTY_TYPE_WACH = 0, parameter C_PROG_EMPTY_TYPE_WDCH = 0, parameter C_PROG_EMPTY_TYPE_WRCH = 0, parameter C_PROG_EMPTY_TYPE_RACH = 0, parameter C_PROG_EMPTY_TYPE_RDCH = 0, parameter C_PROG_EMPTY_TYPE_AXIS = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0, parameter C_REG_SLICE_MODE_WACH = 0, parameter C_REG_SLICE_MODE_WDCH = 0, parameter C_REG_SLICE_MODE_WRCH = 0, parameter C_REG_SLICE_MODE_RACH = 0, parameter C_REG_SLICE_MODE_RDCH = 0, parameter C_REG_SLICE_MODE_AXIS = 0 ) ( //------------------------------------------------------------------------------ // Input and Output Declarations //------------------------------------------------------------------------------ // Conventional FIFO Interface Signals input backup, input backup_marker, input clk, input rst, input srst, input wr_clk, input wr_rst, input rd_clk, input rd_rst, input [C_DIN_WIDTH-1:0] din, input wr_en, input rd_en, // Optional inputs input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh, input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert, input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate, input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh, input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert, input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate, input int_clk, input injectdbiterr, input injectsbiterr, input sleep, output [C_DOUT_WIDTH-1:0] dout, output full, output almost_full, output wr_ack, output overflow, output empty, output almost_empty, output valid, output underflow, output [C_DATA_COUNT_WIDTH-1:0] data_count, output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count, output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count, output prog_full, output prog_empty, output sbiterr, output dbiterr, output wr_rst_busy, output rd_rst_busy, // AXI Global Signal input m_aclk, input s_aclk, input s_aresetn, input s_aclk_en, input m_aclk_en, // AXI Full/Lite Slave Write Channel (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_awid, input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen, input [3-1:0] s_axi_awsize, input [2-1:0] s_axi_awburst, input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock, input [4-1:0] s_axi_awcache, input [3-1:0] s_axi_awprot, input [4-1:0] s_axi_awqos, input [4-1:0] s_axi_awregion, input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, input s_axi_awvalid, output s_axi_awready, input [C_AXI_ID_WIDTH-1:0] s_axi_wid, input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, input s_axi_wlast, input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, input s_axi_wvalid, output s_axi_wready, output [C_AXI_ID_WIDTH-1:0] s_axi_bid, output [2-1:0] s_axi_bresp, output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, output s_axi_bvalid, input s_axi_bready, // AXI Full/Lite Master Write Channel (read side) output [C_AXI_ID_WIDTH-1:0] m_axi_awid, output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen, output [3-1:0] m_axi_awsize, output [2-1:0] m_axi_awburst, output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock, output [4-1:0] m_axi_awcache, output [3-1:0] m_axi_awprot, output [4-1:0] m_axi_awqos, output [4-1:0] m_axi_awregion, output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, output m_axi_awvalid, input m_axi_awready, output [C_AXI_ID_WIDTH-1:0] m_axi_wid, output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output m_axi_wlast, output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, output m_axi_wvalid, input m_axi_wready, input [C_AXI_ID_WIDTH-1:0] m_axi_bid, input [2-1:0] m_axi_bresp, input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, input m_axi_bvalid, output m_axi_bready, // AXI Full/Lite Slave Read Channel (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_arid, input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen, input [3-1:0] s_axi_arsize, input [2-1:0] s_axi_arburst, input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock, input [4-1:0] s_axi_arcache, input [3-1:0] s_axi_arprot, input [4-1:0] s_axi_arqos, input [4-1:0] s_axi_arregion, input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, input s_axi_arvalid, output s_axi_arready, output [C_AXI_ID_WIDTH-1:0] s_axi_rid, output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, output [2-1:0] s_axi_rresp, output s_axi_rlast, output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, output s_axi_rvalid, input s_axi_rready, // AXI Full/Lite Master Read Channel (read side) output [C_AXI_ID_WIDTH-1:0] m_axi_arid, output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen, output [3-1:0] m_axi_arsize, output [2-1:0] m_axi_arburst, output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock, output [4-1:0] m_axi_arcache, output [3-1:0] m_axi_arprot, output [4-1:0] m_axi_arqos, output [4-1:0] m_axi_arregion, output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, output m_axi_arvalid, input m_axi_arready, input [C_AXI_ID_WIDTH-1:0] m_axi_rid, input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, input [2-1:0] m_axi_rresp, input m_axi_rlast, input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, input m_axi_rvalid, output m_axi_rready, // AXI Streaming Slave Signals (Write side) input s_axis_tvalid, output s_axis_tready, input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata, input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb, input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep, input s_axis_tlast, input [C_AXIS_TID_WIDTH-1:0] s_axis_tid, input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest, input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser, // AXI Streaming Master Signals (Read side) output m_axis_tvalid, input m_axis_tready, output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata, output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb, output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep, output m_axis_tlast, output [C_AXIS_TID_WIDTH-1:0] m_axis_tid, output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest, output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser, // AXI Full/Lite Write Address Channel signals input axi_aw_injectsbiterr, input axi_aw_injectdbiterr, input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh, input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh, output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count, output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count, output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count, output axi_aw_sbiterr, output axi_aw_dbiterr, output axi_aw_overflow, output axi_aw_underflow, output axi_aw_prog_full, output axi_aw_prog_empty, // AXI Full/Lite Write Data Channel signals input axi_w_injectsbiterr, input axi_w_injectdbiterr, input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh, input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh, output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count, output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count, output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count, output axi_w_sbiterr, output axi_w_dbiterr, output axi_w_overflow, output axi_w_underflow, output axi_w_prog_full, output axi_w_prog_empty, // AXI Full/Lite Write Response Channel signals input axi_b_injectsbiterr, input axi_b_injectdbiterr, input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh, input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh, output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count, output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count, output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count, output axi_b_sbiterr, output axi_b_dbiterr, output axi_b_overflow, output axi_b_underflow, output axi_b_prog_full, output axi_b_prog_empty, // AXI Full/Lite Read Address Channel signals input axi_ar_injectsbiterr, input axi_ar_injectdbiterr, input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh, input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh, output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count, output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count, output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count, output axi_ar_sbiterr, output axi_ar_dbiterr, output axi_ar_overflow, output axi_ar_underflow, output axi_ar_prog_full, output axi_ar_prog_empty, // AXI Full/Lite Read Data Channel Signals input axi_r_injectsbiterr, input axi_r_injectdbiterr, input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh, input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh, output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count, output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count, output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count, output axi_r_sbiterr, output axi_r_dbiterr, output axi_r_overflow, output axi_r_underflow, output axi_r_prog_full, output axi_r_prog_empty, // AXI Streaming FIFO Related Signals input axis_injectsbiterr, input axis_injectdbiterr, input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh, input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh, output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count, output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count, output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count, output axis_sbiterr, output axis_dbiterr, output axis_overflow, output axis_underflow, output axis_prog_full, output axis_prog_empty ); wire BACKUP; wire BACKUP_MARKER; wire CLK; wire RST; wire SRST; wire WR_CLK; wire WR_RST; wire RD_CLK; wire RD_RST; wire [C_DIN_WIDTH-1:0] DIN; wire WR_EN; wire RD_EN; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; wire INT_CLK; wire INJECTDBITERR; wire INJECTSBITERR; wire SLEEP; wire [C_DOUT_WIDTH-1:0] DOUT; wire FULL; wire ALMOST_FULL; wire WR_ACK; wire OVERFLOW; wire EMPTY; wire ALMOST_EMPTY; wire VALID; wire UNDERFLOW; wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; wire PROG_FULL; wire PROG_EMPTY; wire SBITERR; wire DBITERR; wire WR_RST_BUSY; wire RD_RST_BUSY; wire M_ACLK; wire S_ACLK; wire S_ARESETN; wire S_ACLK_EN; wire M_ACLK_EN; wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID; wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR; wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN; wire [3-1:0] S_AXI_AWSIZE; wire [2-1:0] S_AXI_AWBURST; wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK; wire [4-1:0] S_AXI_AWCACHE; wire [3-1:0] S_AXI_AWPROT; wire [4-1:0] S_AXI_AWQOS; wire [4-1:0] S_AXI_AWREGION; wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER; wire S_AXI_AWVALID; wire S_AXI_AWREADY; wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID; wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA; wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB; wire S_AXI_WLAST; wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER; wire S_AXI_WVALID; wire S_AXI_WREADY; wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID; wire [2-1:0] S_AXI_BRESP; wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER; wire S_AXI_BVALID; wire S_AXI_BREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID; wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR; wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN; wire [3-1:0] M_AXI_AWSIZE; wire [2-1:0] M_AXI_AWBURST; wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK; wire [4-1:0] M_AXI_AWCACHE; wire [3-1:0] M_AXI_AWPROT; wire [4-1:0] M_AXI_AWQOS; wire [4-1:0] M_AXI_AWREGION; wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER; wire M_AXI_AWVALID; wire M_AXI_AWREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID; wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA; wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB; wire M_AXI_WLAST; wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER; wire M_AXI_WVALID; wire M_AXI_WREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID; wire [2-1:0] M_AXI_BRESP; wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER; wire M_AXI_BVALID; wire M_AXI_BREADY; wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID; wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR; wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN; wire [3-1:0] S_AXI_ARSIZE; wire [2-1:0] S_AXI_ARBURST; wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK; wire [4-1:0] S_AXI_ARCACHE; wire [3-1:0] S_AXI_ARPROT; wire [4-1:0] S_AXI_ARQOS; wire [4-1:0] S_AXI_ARREGION; wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER; wire S_AXI_ARVALID; wire S_AXI_ARREADY; wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA; wire [2-1:0] S_AXI_RRESP; wire S_AXI_RLAST; wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER; wire S_AXI_RVALID; wire S_AXI_RREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID; wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR; wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN; wire [3-1:0] M_AXI_ARSIZE; wire [2-1:0] M_AXI_ARBURST; wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK; wire [4-1:0] M_AXI_ARCACHE; wire [3-1:0] M_AXI_ARPROT; wire [4-1:0] M_AXI_ARQOS; wire [4-1:0] M_AXI_ARREGION; wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER; wire M_AXI_ARVALID; wire M_AXI_ARREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID; wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA; wire [2-1:0] M_AXI_RRESP; wire M_AXI_RLAST; wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER; wire M_AXI_RVALID; wire M_AXI_RREADY; wire S_AXIS_TVALID; wire S_AXIS_TREADY; wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA; wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB; wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP; wire S_AXIS_TLAST; wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID; wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST; wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER; wire M_AXIS_TVALID; wire M_AXIS_TREADY; wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA; wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB; wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP; wire M_AXIS_TLAST; wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID; wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST; wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER; wire AXI_AW_INJECTSBITERR; wire AXI_AW_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT; wire AXI_AW_SBITERR; wire AXI_AW_DBITERR; wire AXI_AW_OVERFLOW; wire AXI_AW_UNDERFLOW; wire AXI_AW_PROG_FULL; wire AXI_AW_PROG_EMPTY; wire AXI_W_INJECTSBITERR; wire AXI_W_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT; wire AXI_W_SBITERR; wire AXI_W_DBITERR; wire AXI_W_OVERFLOW; wire AXI_W_UNDERFLOW; wire AXI_W_PROG_FULL; wire AXI_W_PROG_EMPTY; wire AXI_B_INJECTSBITERR; wire AXI_B_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT; wire AXI_B_SBITERR; wire AXI_B_DBITERR; wire AXI_B_OVERFLOW; wire AXI_B_UNDERFLOW; wire AXI_B_PROG_FULL; wire AXI_B_PROG_EMPTY; wire AXI_AR_INJECTSBITERR; wire AXI_AR_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT; wire AXI_AR_SBITERR; wire AXI_AR_DBITERR; wire AXI_AR_OVERFLOW; wire AXI_AR_UNDERFLOW; wire AXI_AR_PROG_FULL; wire AXI_AR_PROG_EMPTY; wire AXI_R_INJECTSBITERR; wire AXI_R_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT; wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT; wire AXI_R_SBITERR; wire AXI_R_DBITERR; wire AXI_R_OVERFLOW; wire AXI_R_UNDERFLOW; wire AXI_R_PROG_FULL; wire AXI_R_PROG_EMPTY; wire AXIS_INJECTSBITERR; wire AXIS_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT; wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT; wire AXIS_SBITERR; wire AXIS_DBITERR; wire AXIS_OVERFLOW; wire AXIS_UNDERFLOW; wire AXIS_PROG_FULL; wire AXIS_PROG_EMPTY; wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in; wire wr_rst_int; wire rd_rst_int; wire wr_rst_busy_o; wire wr_rst_busy_ntve; wire wr_rst_busy_axis; wire wr_rst_busy_wach; wire wr_rst_busy_wdch; wire wr_rst_busy_wrch; wire wr_rst_busy_rach; wire wr_rst_busy_rdch; function integer find_log2; input integer int_val; integer i,j; begin i = 1; j = 0; for (i = 1; i < int_val; i = i*2) begin j = j + 1; end find_log2 = j; end endfunction // Conventional FIFO Interface Signals assign BACKUP = backup; assign BACKUP_MARKER = backup_marker; assign CLK = clk; assign RST = rst; assign SRST = srst; assign WR_CLK = wr_clk; assign WR_RST = wr_rst; assign RD_CLK = rd_clk; assign RD_RST = rd_rst; assign WR_EN = wr_en; assign RD_EN = rd_en; assign INT_CLK = int_clk; assign INJECTDBITERR = injectdbiterr; assign INJECTSBITERR = injectsbiterr; assign SLEEP = sleep; assign full = FULL; assign almost_full = ALMOST_FULL; assign wr_ack = WR_ACK; assign overflow = OVERFLOW; assign empty = EMPTY; assign almost_empty = ALMOST_EMPTY; assign valid = VALID; assign underflow = UNDERFLOW; assign prog_full = PROG_FULL; assign prog_empty = PROG_EMPTY; assign sbiterr = SBITERR; assign dbiterr = DBITERR; // assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o; assign wr_rst_busy = wr_rst_busy_o; assign rd_rst_busy = RD_RST_BUSY; assign M_ACLK = m_aclk; assign S_ACLK = s_aclk; assign S_ARESETN = s_aresetn; assign S_ACLK_EN = s_aclk_en; assign M_ACLK_EN = m_aclk_en; assign S_AXI_AWVALID = s_axi_awvalid; assign s_axi_awready = S_AXI_AWREADY; assign S_AXI_WLAST = s_axi_wlast; assign S_AXI_WVALID = s_axi_wvalid; assign s_axi_wready = S_AXI_WREADY; assign s_axi_bvalid = S_AXI_BVALID; assign S_AXI_BREADY = s_axi_bready; assign m_axi_awvalid = M_AXI_AWVALID; assign M_AXI_AWREADY = m_axi_awready; assign m_axi_wlast = M_AXI_WLAST; assign m_axi_wvalid = M_AXI_WVALID; assign M_AXI_WREADY = m_axi_wready; assign M_AXI_BVALID = m_axi_bvalid; assign m_axi_bready = M_AXI_BREADY; assign S_AXI_ARVALID = s_axi_arvalid; assign s_axi_arready = S_AXI_ARREADY; assign s_axi_rlast = S_AXI_RLAST; assign s_axi_rvalid = S_AXI_RVALID; assign S_AXI_RREADY = s_axi_rready; assign m_axi_arvalid = M_AXI_ARVALID; assign M_AXI_ARREADY = m_axi_arready; assign M_AXI_RLAST = m_axi_rlast; assign M_AXI_RVALID = m_axi_rvalid; assign m_axi_rready = M_AXI_RREADY; assign S_AXIS_TVALID = s_axis_tvalid; assign s_axis_tready = S_AXIS_TREADY; assign S_AXIS_TLAST = s_axis_tlast; assign m_axis_tvalid = M_AXIS_TVALID; assign M_AXIS_TREADY = m_axis_tready; assign m_axis_tlast = M_AXIS_TLAST; assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr; assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr; assign axi_aw_sbiterr = AXI_AW_SBITERR; assign axi_aw_dbiterr = AXI_AW_DBITERR; assign axi_aw_overflow = AXI_AW_OVERFLOW; assign axi_aw_underflow = AXI_AW_UNDERFLOW; assign axi_aw_prog_full = AXI_AW_PROG_FULL; assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY; assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr; assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr; assign axi_w_sbiterr = AXI_W_SBITERR; assign axi_w_dbiterr = AXI_W_DBITERR; assign axi_w_overflow = AXI_W_OVERFLOW; assign axi_w_underflow = AXI_W_UNDERFLOW; assign axi_w_prog_full = AXI_W_PROG_FULL; assign axi_w_prog_empty = AXI_W_PROG_EMPTY; assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr; assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr; assign axi_b_sbiterr = AXI_B_SBITERR; assign axi_b_dbiterr = AXI_B_DBITERR; assign axi_b_overflow = AXI_B_OVERFLOW; assign axi_b_underflow = AXI_B_UNDERFLOW; assign axi_b_prog_full = AXI_B_PROG_FULL; assign axi_b_prog_empty = AXI_B_PROG_EMPTY; assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr; assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr; assign axi_ar_sbiterr = AXI_AR_SBITERR; assign axi_ar_dbiterr = AXI_AR_DBITERR; assign axi_ar_overflow = AXI_AR_OVERFLOW; assign axi_ar_underflow = AXI_AR_UNDERFLOW; assign axi_ar_prog_full = AXI_AR_PROG_FULL; assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY; assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr; assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr; assign axi_r_sbiterr = AXI_R_SBITERR; assign axi_r_dbiterr = AXI_R_DBITERR; assign axi_r_overflow = AXI_R_OVERFLOW; assign axi_r_underflow = AXI_R_UNDERFLOW; assign axi_r_prog_full = AXI_R_PROG_FULL; assign axi_r_prog_empty = AXI_R_PROG_EMPTY; assign AXIS_INJECTSBITERR = axis_injectsbiterr; assign AXIS_INJECTDBITERR = axis_injectdbiterr; assign axis_sbiterr = AXIS_SBITERR; assign axis_dbiterr = AXIS_DBITERR; assign axis_overflow = AXIS_OVERFLOW; assign axis_underflow = AXIS_UNDERFLOW; assign axis_prog_full = AXIS_PROG_FULL; assign axis_prog_empty = AXIS_PROG_EMPTY; assign DIN = din; assign PROG_EMPTY_THRESH = prog_empty_thresh; assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert; assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate; assign PROG_FULL_THRESH = prog_full_thresh; assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert; assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate; assign dout = DOUT; assign data_count = DATA_COUNT; assign rd_data_count = RD_DATA_COUNT; assign wr_data_count = WR_DATA_COUNT; assign S_AXI_AWID = s_axi_awid; assign S_AXI_AWADDR = s_axi_awaddr; assign S_AXI_AWLEN = s_axi_awlen; assign S_AXI_AWSIZE = s_axi_awsize; assign S_AXI_AWBURST = s_axi_awburst; assign S_AXI_AWLOCK = s_axi_awlock; assign S_AXI_AWCACHE = s_axi_awcache; assign S_AXI_AWPROT = s_axi_awprot; assign S_AXI_AWQOS = s_axi_awqos; assign S_AXI_AWREGION = s_axi_awregion; assign S_AXI_AWUSER = s_axi_awuser; assign S_AXI_WID = s_axi_wid; assign S_AXI_WDATA = s_axi_wdata; assign S_AXI_WSTRB = s_axi_wstrb; assign S_AXI_WUSER = s_axi_wuser; assign s_axi_bid = S_AXI_BID; assign s_axi_bresp = S_AXI_BRESP; assign s_axi_buser = S_AXI_BUSER; assign m_axi_awid = M_AXI_AWID; assign m_axi_awaddr = M_AXI_AWADDR; assign m_axi_awlen = M_AXI_AWLEN; assign m_axi_awsize = M_AXI_AWSIZE; assign m_axi_awburst = M_AXI_AWBURST; assign m_axi_awlock = M_AXI_AWLOCK; assign m_axi_awcache = M_AXI_AWCACHE; assign m_axi_awprot = M_AXI_AWPROT; assign m_axi_awqos = M_AXI_AWQOS; assign m_axi_awregion = M_AXI_AWREGION; assign m_axi_awuser = M_AXI_AWUSER; assign m_axi_wid = M_AXI_WID; assign m_axi_wdata = M_AXI_WDATA; assign m_axi_wstrb = M_AXI_WSTRB; assign m_axi_wuser = M_AXI_WUSER; assign M_AXI_BID = m_axi_bid; assign M_AXI_BRESP = m_axi_bresp; assign M_AXI_BUSER = m_axi_buser; assign S_AXI_ARID = s_axi_arid; assign S_AXI_ARADDR = s_axi_araddr; assign S_AXI_ARLEN = s_axi_arlen; assign S_AXI_ARSIZE = s_axi_arsize; assign S_AXI_ARBURST = s_axi_arburst; assign S_AXI_ARLOCK = s_axi_arlock; assign S_AXI_ARCACHE = s_axi_arcache; assign S_AXI_ARPROT = s_axi_arprot; assign S_AXI_ARQOS = s_axi_arqos; assign S_AXI_ARREGION = s_axi_arregion; assign S_AXI_ARUSER = s_axi_aruser; assign s_axi_rid = S_AXI_RID; assign s_axi_rdata = S_AXI_RDATA; assign s_axi_rresp = S_AXI_RRESP; assign s_axi_ruser = S_AXI_RUSER; assign m_axi_arid = M_AXI_ARID; assign m_axi_araddr = M_AXI_ARADDR; assign m_axi_arlen = M_AXI_ARLEN; assign m_axi_arsize = M_AXI_ARSIZE; assign m_axi_arburst = M_AXI_ARBURST; assign m_axi_arlock = M_AXI_ARLOCK; assign m_axi_arcache = M_AXI_ARCACHE; assign m_axi_arprot = M_AXI_ARPROT; assign m_axi_arqos = M_AXI_ARQOS; assign m_axi_arregion = M_AXI_ARREGION; assign m_axi_aruser = M_AXI_ARUSER; assign M_AXI_RID = m_axi_rid; assign M_AXI_RDATA = m_axi_rdata; assign M_AXI_RRESP = m_axi_rresp; assign M_AXI_RUSER = m_axi_ruser; assign S_AXIS_TDATA = s_axis_tdata; assign S_AXIS_TSTRB = s_axis_tstrb; assign S_AXIS_TKEEP = s_axis_tkeep; assign S_AXIS_TID = s_axis_tid; assign S_AXIS_TDEST = s_axis_tdest; assign S_AXIS_TUSER = s_axis_tuser; assign m_axis_tdata = M_AXIS_TDATA; assign m_axis_tstrb = M_AXIS_TSTRB; assign m_axis_tkeep = M_AXIS_TKEEP; assign m_axis_tid = M_AXIS_TID; assign m_axis_tdest = M_AXIS_TDEST; assign m_axis_tuser = M_AXIS_TUSER; assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh; assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh; assign axi_aw_data_count = AXI_AW_DATA_COUNT; assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT; assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT; assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh; assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh; assign axi_w_data_count = AXI_W_DATA_COUNT; assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT; assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT; assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh; assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh; assign axi_b_data_count = AXI_B_DATA_COUNT; assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT; assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT; assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh; assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh; assign axi_ar_data_count = AXI_AR_DATA_COUNT; assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT; assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT; assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh; assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh; assign axi_r_data_count = AXI_R_DATA_COUNT; assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT; assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT; assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh; assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh; assign axis_data_count = AXIS_DATA_COUNT; assign axis_wr_data_count = AXIS_WR_DATA_COUNT; assign axis_rd_data_count = AXIS_RD_DATA_COUNT; generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo fifo_generator_v13_1_3_CONV_VER #( .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_FAMILY (C_FAMILY), .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_RD_RST (C_HAS_RD_RST), .C_HAS_RST (C_HAS_RST), .C_HAS_SRST (C_HAS_SRST), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_HAS_VALID (C_HAS_VALID), .C_HAS_WR_ACK (C_HAS_WR_ACK), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_HAS_WR_RST (C_HAS_WR_RST), .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), .C_PRELOAD_REGS (C_PRELOAD_REGS), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_FREQ (C_RD_FREQ), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_ECC (C_USE_ECC), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), .C_VALID_LOW (C_VALID_LOW), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_FREQ (C_WR_FREQ), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE), .C_AXI_TYPE (C_AXI_TYPE), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE) ) fifo_generator_v13_1_3_conv_dut ( .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .CLK (CLK), .RST (RST), .SRST (SRST), .WR_CLK (WR_CLK), .WR_RST (WR_RST), .RD_CLK (RD_CLK), .RD_RST (RD_RST), .DIN (DIN), .WR_EN (WR_EN), .RD_EN (RD_EN), .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), .PROG_FULL_THRESH (PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), .INT_CLK (INT_CLK), .INJECTDBITERR (INJECTDBITERR), .INJECTSBITERR (INJECTSBITERR), .DOUT (DOUT), .FULL (FULL), .ALMOST_FULL (ALMOST_FULL), .WR_ACK (WR_ACK), .OVERFLOW (OVERFLOW), .EMPTY (EMPTY), .ALMOST_EMPTY (ALMOST_EMPTY), .VALID (VALID), .UNDERFLOW (UNDERFLOW), .DATA_COUNT (DATA_COUNT), .RD_DATA_COUNT (RD_DATA_COUNT), .WR_DATA_COUNT (wr_data_count_in), .PROG_FULL (PROG_FULL), .PROG_EMPTY (PROG_EMPTY), .SBITERR (SBITERR), .DBITERR (DBITERR), .wr_rst_busy_o (wr_rst_busy_o), .wr_rst_busy (wr_rst_busy_i), .rd_rst_busy (rd_rst_busy), .wr_rst_i_out (wr_rst_int), .rd_rst_i_out (rd_rst_int) ); end endgenerate localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0; localparam C_AXI_SIZE_WIDTH = 3; localparam C_AXI_BURST_WIDTH = 2; localparam C_AXI_CACHE_WIDTH = 4; localparam C_AXI_PROT_WIDTH = 3; localparam C_AXI_QOS_WIDTH = 4; localparam C_AXI_REGION_WIDTH = 4; localparam C_AXI_BRESP_WIDTH = 2; localparam C_AXI_RRESP_WIDTH = 2; localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0; localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS; localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET; localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET; localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET; localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET; localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET; localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS); localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH); function [LOG_DEPTH_AXIS-1:0] bin2gray; input [LOG_DEPTH_AXIS-1:0] x; begin bin2gray = x ^ (x>>1); end endfunction function [LOG_DEPTH_AXIS-1:0] gray2bin; input [LOG_DEPTH_AXIS-1:0] x; integer i; begin gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1]; for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin gray2bin[i] = gray2bin[i+1] ^ x[i]; end end endfunction wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last; wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ; wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ; reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0; reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0; reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0; reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0; wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad; wire [LOG_WR_DEPTH : 0] r_inv_pad; wire [LOG_WR_DEPTH-1 : 0] d_cnt; reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0; reg adj_w_cnt_rd_pad_0 = 0; reg r_inv_pad_0 = 0; genvar l; generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage fifo_generator_v13_1_3_sync_stage #( .C_WIDTH (LOG_WR_DEPTH) ) rd_stg_inst ( .RST (rd_rst_int), .CLK (RD_CLK), .DIN (w_q[l-1]), .DOUT (w_q[l]) ); end endgenerate // gpkt_cnt_sync_stage generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter assign wr_eop_ad = WR_EN & !(FULL); assign rd_eop_ad = RD_EN & !(EMPTY); always @ (posedge wr_rst_int or posedge WR_CLK) begin if (wr_rst_int) w_cnt <= 1'b0; else if (wr_eop_ad) w_cnt <= w_cnt + 1; end always @ (posedge wr_rst_int or posedge WR_CLK) begin if (wr_rst_int) w_cnt_gc <= 1'b0; else w_cnt_gc <= bin2gray(w_cnt); end assign w_q[0] = w_cnt_gc; assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE]; always @ (posedge rd_rst_int or posedge RD_CLK) begin if (rd_rst_int) w_cnt_rd <= 1'b0; else w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last); end always @ (posedge rd_rst_int or posedge RD_CLK) begin if (rd_rst_int) r_cnt <= 1'b0; else if (rd_eop_ad) r_cnt <= r_cnt + 1; end // Take the difference of write and read packet count // Logic is similar to rd_pe_as assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd; assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt; assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0; assign r_inv_pad[0] = r_inv_pad_0; always @ ( rd_eop_ad ) begin if (!rd_eop_ad) begin adj_w_cnt_rd_pad_0 <= 1'b1; r_inv_pad_0 <= 1'b1; end else begin adj_w_cnt_rd_pad_0 <= 1'b0; r_inv_pad_0 <= 1'b0; end end always @ (posedge rd_rst_int or posedge RD_CLK) begin if (rd_rst_int) d_cnt_pad <= 1'b0; else d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ; end assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ; assign WR_DATA_COUNT = d_cnt; end endgenerate // fifo_ic_adapter generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter assign WR_DATA_COUNT = wr_data_count_in; end endgenerate // fifo_icn_adapter wire inverted_reset = ~S_ARESETN; wire axi_rs_rst; wire [C_DIN_WIDTH_AXIS-1:0] axis_din ; wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ; wire axis_full ; wire axis_almost_full ; wire axis_empty ; wire axis_s_axis_tready; wire axis_m_axis_tvalid; wire axis_wr_en ; wire axis_rd_en ; wire axis_we ; wire axis_re ; wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc; reg axis_pkt_read = 1'b0; wire axis_rd_rst; wire axis_wr_rst; generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 || C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst reg rst_d1 = 0 ; reg rst_d2 = 0 ; reg [3:0] axi_rst = 4'h0 ; always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) begin rst_d1 <= 1'b1; rst_d2 <= 1'b1; axi_rst <= 4'hf; end else begin rst_d1 <= #`TCQ 1'b0; rst_d2 <= #`TCQ rst_d1; axi_rst <= #`TCQ {axi_rst[2:0],1'b0}; end end assign axi_rs_rst = axi_rst[3];//rst_d2; end endgenerate // gaxi_rs_rst generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming // Write protection when almost full or prog_full is high assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID; // Read protection when almost empty or prog_empty is high assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY : (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY; assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we; assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re; fifo_generator_v13_1_3_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : (C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 : (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_AXIS), .C_WR_DEPTH (C_WR_DEPTH_AXIS), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS), .C_DOUT_WIDTH (C_DIN_WIDTH_AXIS), .C_RD_DEPTH (C_WR_DEPTH_AXIS), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS), .C_USE_ECC (C_USE_ECC_AXIS), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_3_axis_dut ( .CLK (S_ACLK), .WR_CLK (S_ACLK), .RD_CLK (M_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (axis_wr_en), .RD_EN (axis_rd_en), .PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), .PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), .INJECTDBITERR (AXIS_INJECTDBITERR), .INJECTSBITERR (AXIS_INJECTSBITERR), .DIN (axis_din), .DOUT (axis_dout), .FULL (axis_full), .EMPTY (axis_empty), .ALMOST_FULL (axis_almost_full), .PROG_FULL (AXIS_PROG_FULL), .ALMOST_EMPTY (), .PROG_EMPTY (AXIS_PROG_EMPTY), .WR_ACK (), .OVERFLOW (AXIS_OVERFLOW), .VALID (), .UNDERFLOW (AXIS_UNDERFLOW), .DATA_COUNT (axis_dc), .RD_DATA_COUNT (AXIS_RD_DATA_COUNT), .WR_DATA_COUNT (AXIS_WR_DATA_COUNT), .SBITERR (AXIS_SBITERR), .DBITERR (AXIS_DBITERR), .wr_rst_busy (wr_rst_busy_axis), .rd_rst_busy (rd_rst_busy_axis), .wr_rst_i_out (axis_wr_rst), .rd_rst_i_out (axis_rd_rst), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full; assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read; assign S_AXIS_TREADY = axis_s_axis_tready; assign M_AXIS_TVALID = axis_m_axis_tvalid; end endgenerate // axi_streaming wire axis_wr_eop; reg axis_wr_eop_d1 = 1'b0; wire axis_rd_eop; integer axis_pkt_cnt; generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST; assign axis_rd_eop = axis_rd_en & axis_dout[0]; always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) axis_pkt_read <= 1'b0; else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1) axis_pkt_read <= 1'b0; else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty)) axis_pkt_read <= 1'b1; end always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) axis_wr_eop_d1 <= 1'b0; else axis_wr_eop_d1 <= axis_wr_eop; end always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) axis_pkt_cnt <= 0; else if (axis_wr_eop_d1 && ~axis_rd_eop) axis_pkt_cnt <= axis_pkt_cnt + 1; else if (axis_rd_eop && ~axis_wr_eop_d1) axis_pkt_cnt <= axis_pkt_cnt - 1; end end endgenerate // gaxis_pkt_fifo_cc reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0; wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last; wire axis_rd_has_rst; wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ; wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ; wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0; wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ; reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0; reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0; reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0; wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad; wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad; wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt; reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0; reg adj_axis_wpkt_cnt_rd_pad_0 = 0; reg rpkt_inv_pad_0 = 0; wire axis_af_rd ; generate if (C_HAS_RST == 1) begin : rst_blk_has assign axis_rd_has_rst = axis_rd_rst; end endgenerate //rst_blk_has generate if (C_HAS_RST == 0) begin :rst_blk_no assign axis_rd_has_rst = 1'b0; end endgenerate //rst_blk_no genvar i; generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage fifo_generator_v13_1_3_sync_stage #( .C_WIDTH (LOG_DEPTH_AXIS) ) rd_stg_inst ( .RST (axis_rd_has_rst), .CLK (M_ACLK), .DIN (wpkt_q[i-1]), .DOUT (wpkt_q[i]) ); fifo_generator_v13_1_3_sync_stage #( .C_WIDTH (1) ) wr_stg_inst ( .RST (axis_rd_has_rst), .CLK (M_ACLK), .DIN (axis_af_q[i-1]), .DOUT (axis_af_q[i]) ); end endgenerate // gpkt_cnt_sync_stage generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST; assign axis_rd_eop = axis_rd_en & axis_dout[0]; always @ (posedge axis_rd_has_rst or posedge M_ACLK) begin if (axis_rd_has_rst) axis_pkt_read <= 1'b0; else if (axis_rd_eop && (diff_pkt_cnt == 1)) axis_pkt_read <= 1'b0; else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty)) axis_pkt_read <= 1'b1; end always @ (posedge axis_wr_rst or posedge S_ACLK) begin if (axis_wr_rst) axis_wpkt_cnt <= 1'b0; else if (axis_wr_eop) axis_wpkt_cnt <= axis_wpkt_cnt + 1; end always @ (posedge axis_wr_rst or posedge S_ACLK) begin if (axis_wr_rst) axis_wpkt_cnt_gc <= 1'b0; else axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt); end assign wpkt_q[0] = axis_wpkt_cnt_gc; assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE]; assign axis_af_q[0] = axis_almost_full; //assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE]; assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE]; always @ (posedge axis_rd_has_rst or posedge M_ACLK) begin if (axis_rd_has_rst) axis_wpkt_cnt_rd <= 1'b0; else axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last); end always @ (posedge axis_rd_rst or posedge M_ACLK) begin if (axis_rd_has_rst) axis_rpkt_cnt <= 1'b0; else if (axis_rd_eop) axis_rpkt_cnt <= axis_rpkt_cnt + 1; end // Take the difference of write and read packet count // Logic is similar to rd_pe_as assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd; assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt; assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0; assign rpkt_inv_pad[0] = rpkt_inv_pad_0; always @ ( axis_rd_eop ) begin if (!axis_rd_eop) begin adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1; rpkt_inv_pad_0 <= 1'b1; end else begin adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0; rpkt_inv_pad_0 <= 1'b0; end end always @ (posedge axis_rd_rst or posedge M_ACLK) begin if (axis_rd_has_rst) diff_pkt_cnt_pad <= 1'b0; else diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ; end assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ; end endgenerate // gaxis_pkt_fifo_ic // Generate the accurate data count for axi stream packet fifo configuration reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0; generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) axis_dc_pkt_fifo <= 0; else if (axis_wr_en && (~axis_rd_en)) axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1; else if (~axis_wr_en && axis_rd_en) axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1; end assign AXIS_DATA_COUNT = axis_dc_pkt_fifo; end endgenerate // gdc_pkt generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt assign AXIS_DATA_COUNT = 0; end endgenerate // gndc_pkt generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc assign AXIS_DATA_COUNT = axis_dc; end endgenerate // gdc // Register Slice for Write Address Channel generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID; assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY; fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_AXIS), .C_REG_CONFIG (C_REG_SLICE_MODE_AXIS) ) axis_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (axis_din), .S_VALID (axis_wr_en), .S_READY (S_AXIS_TREADY), // Master side .M_PAYLOAD_DATA (axis_dout), .M_VALID (M_AXIS_TVALID), .M_READY (axis_rd_en) ); end endgenerate // gaxis_reg_slice generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA; assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB; assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP; assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID; assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST; assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER; assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast assign axis_din[0] = S_AXIS_TLAST; assign M_AXIS_TLAST = axis_dout[0]; end endgenerate //########################################################################### // AXI FULL Write Channel (axi_write_channel) //########################################################################### localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0; localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0; localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0; localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0; localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0; localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0; localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0; localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH; localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH; localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET; localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET; localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET; localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET; localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET; localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH; localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH; localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET; localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET; localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH; localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH; localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8; localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET; localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH; localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH; localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET; wire [C_DIN_WIDTH_WACH-1:0] wach_din ; wire [C_DIN_WIDTH_WACH-1:0] wach_dout ; wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ; wire wach_full ; wire wach_almost_full ; wire wach_prog_full ; wire wach_empty ; wire wach_almost_empty ; wire wach_prog_empty ; wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ; wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ; wire wdch_full ; wire wdch_almost_full ; wire wdch_prog_full ; wire wdch_empty ; wire wdch_almost_empty ; wire wdch_prog_empty ; wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ; wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ; wire wrch_full ; wire wrch_almost_full ; wire wrch_prog_full ; wire wrch_empty ; wire wrch_almost_empty ; wire wrch_prog_empty ; wire axi_aw_underflow_i; wire axi_w_underflow_i ; wire axi_b_underflow_i ; wire axi_aw_overflow_i ; wire axi_w_overflow_i ; wire axi_b_overflow_i ; wire axi_wr_underflow_i; wire axi_wr_overflow_i ; wire wach_s_axi_awready; wire wach_m_axi_awvalid; wire wach_wr_en ; wire wach_rd_en ; wire wdch_s_axi_wready ; wire wdch_m_axi_wvalid ; wire wdch_wr_en ; wire wdch_rd_en ; wire wrch_s_axi_bvalid ; wire wrch_m_axi_bready ; wire wrch_wr_en ; wire wrch_rd_en ; wire txn_count_up ; wire txn_count_down ; wire awvalid_en ; wire awvalid_pkt ; wire awready_pkt ; integer wr_pkt_count ; wire wach_we ; wire wach_re ; wire wdch_we ; wire wdch_re ; wire wrch_we ; wire wrch_re ; generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel // Write protection when almost full or prog_full is high assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID; // Read protection when almost empty or prog_empty is high assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? wach_m_axi_awvalid & awready_pkt & awvalid_en : (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? M_AXI_AWREADY && wach_m_axi_awvalid : (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? awready_pkt & awvalid_en : (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? M_AXI_AWREADY : 1'b0; assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we; assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re; fifo_generator_v13_1_3_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_WACH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_WR_DEPTH (C_WR_DEPTH_WACH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH), .C_DOUT_WIDTH (C_DIN_WIDTH_WACH), .C_RD_DEPTH (C_WR_DEPTH_WACH), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH), .C_USE_ECC (C_USE_ECC_WACH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_3_wach_dut ( .CLK (S_ACLK), .WR_CLK (S_ACLK), .RD_CLK (M_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (wach_wr_en), .RD_EN (wach_rd_en), .PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}), .PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}), .INJECTDBITERR (AXI_AW_INJECTDBITERR), .INJECTSBITERR (AXI_AW_INJECTSBITERR), .DIN (wach_din), .DOUT (wach_dout_pkt), .FULL (wach_full), .EMPTY (wach_empty), .ALMOST_FULL (), .PROG_FULL (AXI_AW_PROG_FULL), .ALMOST_EMPTY (), .PROG_EMPTY (AXI_AW_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_aw_overflow_i), .VALID (), .UNDERFLOW (axi_aw_underflow_i), .DATA_COUNT (AXI_AW_DATA_COUNT), .RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT), .SBITERR (AXI_AW_SBITERR), .DBITERR (AXI_AW_DBITERR), .wr_rst_busy (wr_rst_busy_wach), .rd_rst_busy (rd_rst_busy_wach), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full; assign wach_m_axi_awvalid = ~wach_empty; assign S_AXI_AWREADY = wach_s_axi_awready; assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0; assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0; end endgenerate // axi_write_address_channel // Register Slice for Write Address Channel generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_WACH), .C_REG_CONFIG (C_REG_SLICE_MODE_WACH) ) wach_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (wach_din), .S_VALID (S_AXI_AWVALID), .S_READY (S_AXI_AWREADY), // Master side .M_PAYLOAD_DATA (wach_dout), .M_VALID (M_AXI_AWVALID), .M_READY (M_AXI_AWREADY) ); end endgenerate // gwach_reg_slice generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_WACH), .C_REG_CONFIG (1) ) wach_pkt_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (inverted_reset), // Slave side .S_PAYLOAD_DATA (wach_dout_pkt), .S_VALID (awvalid_pkt), .S_READY (awready_pkt), // Master side .M_PAYLOAD_DATA (wach_dout), .M_VALID (M_AXI_AWVALID), .M_READY (M_AXI_AWREADY) ); assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en; assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en; always@(posedge S_ACLK or posedge inverted_reset) begin if(inverted_reset == 1) begin wr_pkt_count <= 0; end else begin if(txn_count_up == 1 && txn_count_down == 0) begin wr_pkt_count <= wr_pkt_count + 1; end else if(txn_count_up == 0 && txn_count_down == 1) begin wr_pkt_count <= wr_pkt_count - 1; end end end //Always end assign awvalid_en = (wr_pkt_count > 0)?1:0; end endgenerate generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr assign awvalid_en = 1; assign wach_dout = wach_dout_pkt; assign M_AXI_AWVALID = wach_m_axi_awvalid; end endgenerate generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel // Write protection when almost full or prog_full is high assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID; // Read protection when almost empty or prog_empty is high assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY; assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we; assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re; fifo_generator_v13_1_3_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_WDCH), .C_WR_DEPTH (C_WR_DEPTH_WDCH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH), .C_DOUT_WIDTH (C_DIN_WIDTH_WDCH), .C_RD_DEPTH (C_WR_DEPTH_WDCH), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH), .C_USE_ECC (C_USE_ECC_WDCH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_3_wdch_dut ( .CLK (S_ACLK), .WR_CLK (S_ACLK), .RD_CLK (M_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (wdch_wr_en), .RD_EN (wdch_rd_en), .PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), .PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), .INJECTDBITERR (AXI_W_INJECTDBITERR), .INJECTSBITERR (AXI_W_INJECTSBITERR), .DIN (wdch_din), .DOUT (wdch_dout), .FULL (wdch_full), .EMPTY (wdch_empty), .ALMOST_FULL (), .PROG_FULL (AXI_W_PROG_FULL), .ALMOST_EMPTY (), .PROG_EMPTY (AXI_W_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_w_overflow_i), .VALID (), .UNDERFLOW (axi_w_underflow_i), .DATA_COUNT (AXI_W_DATA_COUNT), .RD_DATA_COUNT (AXI_W_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_W_WR_DATA_COUNT), .SBITERR (AXI_W_SBITERR), .DBITERR (AXI_W_DBITERR), .wr_rst_busy (wr_rst_busy_wdch), .rd_rst_busy (rd_rst_busy_wdch), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full; assign wdch_m_axi_wvalid = ~wdch_empty; assign S_AXI_WREADY = wdch_s_axi_wready; assign M_AXI_WVALID = wdch_m_axi_wvalid; assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0; assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0; end endgenerate // axi_write_data_channel // Register Slice for Write Data Channel generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_WDCH), .C_REG_CONFIG (C_REG_SLICE_MODE_WDCH) ) wdch_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (wdch_din), .S_VALID (S_AXI_WVALID), .S_READY (S_AXI_WREADY), // Master side .M_PAYLOAD_DATA (wdch_dout), .M_VALID (M_AXI_WVALID), .M_READY (M_AXI_WREADY) ); end endgenerate // gwdch_reg_slice generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel // Write protection when almost full or prog_full is high assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID; // Read protection when almost empty or prog_empty is high assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY; assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we; assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re; fifo_generator_v13_1_3_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_WRCH), .C_WR_DEPTH (C_WR_DEPTH_WRCH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH), .C_DOUT_WIDTH (C_DIN_WIDTH_WRCH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_RD_DEPTH (C_WR_DEPTH_WRCH), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH), .C_USE_ECC (C_USE_ECC_WRCH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_3_wrch_dut ( .CLK (S_ACLK), .WR_CLK (M_ACLK), .RD_CLK (S_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (wrch_wr_en), .RD_EN (wrch_rd_en), .PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), .PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), .INJECTDBITERR (AXI_B_INJECTDBITERR), .INJECTSBITERR (AXI_B_INJECTSBITERR), .DIN (wrch_din), .DOUT (wrch_dout), .FULL (wrch_full), .EMPTY (wrch_empty), .ALMOST_FULL (), .ALMOST_EMPTY (), .PROG_FULL (AXI_B_PROG_FULL), .PROG_EMPTY (AXI_B_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_b_overflow_i), .VALID (), .UNDERFLOW (axi_b_underflow_i), .DATA_COUNT (AXI_B_DATA_COUNT), .RD_DATA_COUNT (AXI_B_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_B_WR_DATA_COUNT), .SBITERR (AXI_B_SBITERR), .DBITERR (AXI_B_DBITERR), .wr_rst_busy (wr_rst_busy_wrch), .rd_rst_busy (rd_rst_busy_wrch), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign wrch_s_axi_bvalid = ~wrch_empty; assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full; assign S_AXI_BVALID = wrch_s_axi_bvalid; assign M_AXI_BREADY = wrch_m_axi_bready; assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0; assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0; end endgenerate // axi_write_resp_channel // Register Slice for Write Response Channel generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_WRCH), .C_REG_CONFIG (C_REG_SLICE_MODE_WRCH) ) wrch_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (wrch_din), .S_VALID (M_AXI_BVALID), .S_READY (M_AXI_BREADY), // Master side .M_PAYLOAD_DATA (wrch_dout), .M_VALID (S_AXI_BVALID), .M_READY (S_AXI_BREADY) ); end endgenerate // gwrch_reg_slice assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0; assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0; generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET]; assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET]; assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET]; assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET]; assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET]; assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET]; assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET]; assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET]; assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR; assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN; assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE; assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST; assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK; assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE; assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT; assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS; end endgenerate // axi_wach_output generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET]; end endgenerate // axi_awregion generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion assign M_AXI_AWREGION = 0; end endgenerate // naxi_awregion generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET]; end endgenerate // axi_awuser generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser assign M_AXI_AWUSER = 0; end endgenerate // naxi_awuser generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET]; end endgenerate //axi_awid generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid assign M_AXI_AWID = 0; end endgenerate //naxi_awid generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET]; assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET]; assign M_AXI_WLAST = wdch_dout[0]; assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA; assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB; assign wdch_din[0] = S_AXI_WLAST; end endgenerate // axi_wdch_output generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET]; end endgenerate generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin assign M_AXI_WID = 0; end endgenerate generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET]; end endgenerate generate if (C_HAS_AXI_WUSER == 0) begin assign M_AXI_WUSER = 0; end endgenerate generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP; end endgenerate // axi_wrch_output generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET]; end endgenerate // axi_buser generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser assign S_AXI_BUSER = 0; end endgenerate // naxi_buser generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET]; end endgenerate // axi_bid generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid assign S_AXI_BID = 0 ; end endgenerate // naxi_bid generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1 assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT}; assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET]; assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET]; end endgenerate // axi_wach_output1 generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1 assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB}; assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET]; assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET]; end endgenerate // axi_wdch_output1 generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1 assign wrch_din = M_AXI_BRESP; assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; end endgenerate // axi_wrch_output1 generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1 assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER; end endgenerate // gwach_din1 generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2 assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID; end endgenerate // gwach_din2 generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3 assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION; end endgenerate // gwach_din3 generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1 assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER; end endgenerate // gwdch_din1 generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2 assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID; end endgenerate // gwdch_din2 generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1 assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER; end endgenerate // gwrch_din1 generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2 assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID; end endgenerate // gwrch_din2 //end of axi_write_channel //########################################################################### // AXI FULL Read Channel (axi_read_channel) //########################################################################### wire [C_DIN_WIDTH_RACH-1:0] rach_din ; wire [C_DIN_WIDTH_RACH-1:0] rach_dout ; wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ; wire rach_full ; wire rach_almost_full ; wire rach_prog_full ; wire rach_empty ; wire rach_almost_empty ; wire rach_prog_empty ; wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ; wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ; wire rdch_full ; wire rdch_almost_full ; wire rdch_prog_full ; wire rdch_empty ; wire rdch_almost_empty ; wire rdch_prog_empty ; wire axi_ar_underflow_i ; wire axi_r_underflow_i ; wire axi_ar_overflow_i ; wire axi_r_overflow_i ; wire axi_rd_underflow_i ; wire axi_rd_overflow_i ; wire rach_s_axi_arready ; wire rach_m_axi_arvalid ; wire rach_wr_en ; wire rach_rd_en ; wire rdch_m_axi_rready ; wire rdch_s_axi_rvalid ; wire rdch_wr_en ; wire rdch_rd_en ; wire arvalid_pkt ; wire arready_pkt ; wire arvalid_en ; wire rdch_rd_ok ; wire accept_next_pkt ; integer rdch_free_space ; integer rdch_commited_space ; wire rach_we ; wire rach_re ; wire rdch_we ; wire rdch_re ; localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH; localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH; localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET; localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET; localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET; localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET; localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET; localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH; localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH; localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET; localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET; localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH; localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH; localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH; localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET; generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel // Write protection when almost full or prog_full is high assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID; // Read protection when almost empty or prog_empty is high // assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en; assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? rach_m_axi_arvalid & arready_pkt & arvalid_en : (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? M_AXI_ARREADY && rach_m_axi_arvalid : (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? arready_pkt & arvalid_en : (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? M_AXI_ARREADY : 1'b0; assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we; assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re; fifo_generator_v13_1_3_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_RACH), .C_WR_DEPTH (C_WR_DEPTH_RACH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_DOUT_WIDTH (C_DIN_WIDTH_RACH), .C_RD_DEPTH (C_WR_DEPTH_RACH), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH), .C_USE_ECC (C_USE_ECC_RACH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_3_rach_dut ( .CLK (S_ACLK), .WR_CLK (S_ACLK), .RD_CLK (M_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (rach_wr_en), .RD_EN (rach_rd_en), .PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}), .PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}), .INJECTDBITERR (AXI_AR_INJECTDBITERR), .INJECTSBITERR (AXI_AR_INJECTSBITERR), .DIN (rach_din), .DOUT (rach_dout_pkt), .FULL (rach_full), .EMPTY (rach_empty), .ALMOST_FULL (), .ALMOST_EMPTY (), .PROG_FULL (AXI_AR_PROG_FULL), .PROG_EMPTY (AXI_AR_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_ar_overflow_i), .VALID (), .UNDERFLOW (axi_ar_underflow_i), .DATA_COUNT (AXI_AR_DATA_COUNT), .RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT), .SBITERR (AXI_AR_SBITERR), .DBITERR (AXI_AR_DBITERR), .wr_rst_busy (wr_rst_busy_rach), .rd_rst_busy (rd_rst_busy_rach), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full; assign rach_m_axi_arvalid = ~rach_empty; assign S_AXI_ARREADY = rach_s_axi_arready; assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0; assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0; end endgenerate // axi_read_addr_channel // Register Slice for Read Address Channel generate if (C_RACH_TYPE == 1) begin : grach_reg_slice fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_RACH), .C_REG_CONFIG (C_REG_SLICE_MODE_RACH) ) rach_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (rach_din), .S_VALID (S_AXI_ARVALID), .S_READY (S_AXI_ARREADY), // Master side .M_PAYLOAD_DATA (rach_dout), .M_VALID (M_AXI_ARVALID), .M_READY (M_AXI_ARREADY) ); end endgenerate // grach_reg_slice // Register Slice for Read Address Channel for MM Packet FIFO generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_RACH), .C_REG_CONFIG (1) ) reg_slice_mm_pkt_fifo_inst ( // System Signals .ACLK (S_ACLK), .ARESET (inverted_reset), // Slave side .S_PAYLOAD_DATA (rach_dout_pkt), .S_VALID (arvalid_pkt), .S_READY (arready_pkt), // Master side .M_PAYLOAD_DATA (rach_dout), .M_VALID (M_AXI_ARVALID), .M_READY (M_AXI_ARREADY) ); end endgenerate // grach_reg_slice_mm_pkt_fifo generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid assign M_AXI_ARVALID = rach_m_axi_arvalid; assign rach_dout = rach_dout_pkt; end endgenerate // grach_m_axi_arvalid generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en; assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en; assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en; always@(posedge S_ACLK or posedge inverted_reset) begin if(inverted_reset) begin rdch_commited_space <= 0; end else begin if(rdch_rd_ok && !accept_next_pkt) begin rdch_commited_space <= rdch_commited_space-1; end else if(!rdch_rd_ok && accept_next_pkt) begin rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1); end else if(rdch_rd_ok && accept_next_pkt) begin rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]); end end end //Always end always@(*) begin rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1)); end assign arvalid_en = (rdch_free_space >= 0)?1:0; end endgenerate generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd assign arvalid_en = 1; end endgenerate generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel // Write protection when almost full or prog_full is high assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID; // Read protection when almost empty or prog_empty is high assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY; assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we; assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re; fifo_generator_v13_1_3_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_RDCH), .C_WR_DEPTH (C_WR_DEPTH_RDCH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH), .C_DOUT_WIDTH (C_DIN_WIDTH_RDCH), .C_RD_DEPTH (C_WR_DEPTH_RDCH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH), .C_USE_ECC (C_USE_ECC_RDCH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_3_rdch_dut ( .CLK (S_ACLK), .WR_CLK (M_ACLK), .RD_CLK (S_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (rdch_wr_en), .RD_EN (rdch_rd_en), .PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), .PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), .INJECTDBITERR (AXI_R_INJECTDBITERR), .INJECTSBITERR (AXI_R_INJECTSBITERR), .DIN (rdch_din), .DOUT (rdch_dout), .FULL (rdch_full), .EMPTY (rdch_empty), .ALMOST_FULL (), .ALMOST_EMPTY (), .PROG_FULL (AXI_R_PROG_FULL), .PROG_EMPTY (AXI_R_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_r_overflow_i), .VALID (), .UNDERFLOW (axi_r_underflow_i), .DATA_COUNT (AXI_R_DATA_COUNT), .RD_DATA_COUNT (AXI_R_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_R_WR_DATA_COUNT), .SBITERR (AXI_R_SBITERR), .DBITERR (AXI_R_DBITERR), .wr_rst_busy (wr_rst_busy_rdch), .rd_rst_busy (rd_rst_busy_rdch), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign rdch_s_axi_rvalid = ~rdch_empty; assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full; assign S_AXI_RVALID = rdch_s_axi_rvalid; assign M_AXI_RREADY = rdch_m_axi_rready; assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0; assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0; end endgenerate //axi_read_data_channel // Register Slice for read Data Channel generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_RDCH), .C_REG_CONFIG (C_REG_SLICE_MODE_RDCH) ) rdch_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (rdch_din), .S_VALID (M_AXI_RVALID), .S_READY (M_AXI_RREADY), // Master side .M_PAYLOAD_DATA (rdch_dout), .M_VALID (S_AXI_RVALID), .M_READY (S_AXI_RREADY) ); end endgenerate // grdch_reg_slice assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0; assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0; generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET]; assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET]; assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET]; assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET]; assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET]; assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET]; assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET]; assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET]; assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR; assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN; assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE; assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST; assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK; assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE; assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT; assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS; end endgenerate // axi_full_rach_output generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET]; end endgenerate // axi_arregion generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion assign M_AXI_ARREGION = 0; end endgenerate // naxi_arregion generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET]; end endgenerate // axi_aruser generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser assign M_AXI_ARUSER = 0; end endgenerate // naxi_aruser generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET]; end endgenerate // axi_arid generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid assign M_AXI_ARID = 0; end endgenerate // naxi_arid generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET]; assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET]; assign S_AXI_RLAST = rdch_dout[0]; assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA; assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP; assign rdch_din[0] = M_AXI_RLAST; end endgenerate // axi_full_rdch_output generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET]; end endgenerate // axi_full_ruser_output generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output assign S_AXI_RUSER = 0; end endgenerate // axi_full_nruser_output generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET]; end endgenerate // axi_rid generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid assign S_AXI_RID = 0; end endgenerate // naxi_rid generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1 assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT}; assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET]; assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET]; end endgenerate // axi_lite_rach_output generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1 assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP}; assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET]; assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET]; end endgenerate // axi_lite_rdch_output generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1 assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER; end endgenerate // grach_din1 generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2 assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID; end endgenerate // grach_din2 generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION; end endgenerate generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1 assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER; end endgenerate // grdch_din1 generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2 assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID; end endgenerate // grdch_din2 //end of axi_read_channel generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) : (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i : (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0; end endgenerate // gaxi_comm_uf generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) : (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i : (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0; end endgenerate // gaxi_comm_of //------------------------------------------------------------------------- //------------------------------------------------------------------------- //------------------------------------------------------------------------- // Pass Through Logic or Wiring Logic //------------------------------------------------------------------------- //------------------------------------------------------------------------- //------------------------------------------------------------------------- //------------------------------------------------------------------------- // Pass Through Logic for Read Channel //------------------------------------------------------------------------- // Wiring logic for Write Address Channel generate if (C_WACH_TYPE == 2) begin : gwach_pass_through assign M_AXI_AWID = S_AXI_AWID; assign M_AXI_AWADDR = S_AXI_AWADDR; assign M_AXI_AWLEN = S_AXI_AWLEN; assign M_AXI_AWSIZE = S_AXI_AWSIZE; assign M_AXI_AWBURST = S_AXI_AWBURST; assign M_AXI_AWLOCK = S_AXI_AWLOCK; assign M_AXI_AWCACHE = S_AXI_AWCACHE; assign M_AXI_AWPROT = S_AXI_AWPROT; assign M_AXI_AWQOS = S_AXI_AWQOS; assign M_AXI_AWREGION = S_AXI_AWREGION; assign M_AXI_AWUSER = S_AXI_AWUSER; assign S_AXI_AWREADY = M_AXI_AWREADY; assign M_AXI_AWVALID = S_AXI_AWVALID; end endgenerate // gwach_pass_through; // Wiring logic for Write Data Channel generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through assign M_AXI_WID = S_AXI_WID; assign M_AXI_WDATA = S_AXI_WDATA; assign M_AXI_WSTRB = S_AXI_WSTRB; assign M_AXI_WLAST = S_AXI_WLAST; assign M_AXI_WUSER = S_AXI_WUSER; assign S_AXI_WREADY = M_AXI_WREADY; assign M_AXI_WVALID = S_AXI_WVALID; end endgenerate // gwdch_pass_through; // Wiring logic for Write Response Channel generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through assign S_AXI_BID = M_AXI_BID; assign S_AXI_BRESP = M_AXI_BRESP; assign S_AXI_BUSER = M_AXI_BUSER; assign M_AXI_BREADY = S_AXI_BREADY; assign S_AXI_BVALID = M_AXI_BVALID; end endgenerate // gwrch_pass_through; //------------------------------------------------------------------------- // Pass Through Logic for Read Channel //------------------------------------------------------------------------- // Wiring logic for Read Address Channel generate if (C_RACH_TYPE == 2) begin : grach_pass_through assign M_AXI_ARID = S_AXI_ARID; assign M_AXI_ARADDR = S_AXI_ARADDR; assign M_AXI_ARLEN = S_AXI_ARLEN; assign M_AXI_ARSIZE = S_AXI_ARSIZE; assign M_AXI_ARBURST = S_AXI_ARBURST; assign M_AXI_ARLOCK = S_AXI_ARLOCK; assign M_AXI_ARCACHE = S_AXI_ARCACHE; assign M_AXI_ARPROT = S_AXI_ARPROT; assign M_AXI_ARQOS = S_AXI_ARQOS; assign M_AXI_ARREGION = S_AXI_ARREGION; assign M_AXI_ARUSER = S_AXI_ARUSER; assign S_AXI_ARREADY = M_AXI_ARREADY; assign M_AXI_ARVALID = S_AXI_ARVALID; end endgenerate // grach_pass_through; // Wiring logic for Read Data Channel generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through assign S_AXI_RID = M_AXI_RID; assign S_AXI_RLAST = M_AXI_RLAST; assign S_AXI_RUSER = M_AXI_RUSER; assign S_AXI_RDATA = M_AXI_RDATA; assign S_AXI_RRESP = M_AXI_RRESP; assign S_AXI_RVALID = M_AXI_RVALID; assign M_AXI_RREADY = S_AXI_RREADY; end endgenerate // grdch_pass_through; // Wiring logic for AXI Streaming generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through assign M_AXIS_TDATA = S_AXIS_TDATA; assign M_AXIS_TSTRB = S_AXIS_TSTRB; assign M_AXIS_TKEEP = S_AXIS_TKEEP; assign M_AXIS_TID = S_AXIS_TID; assign M_AXIS_TDEST = S_AXIS_TDEST; assign M_AXIS_TUSER = S_AXIS_TUSER; assign M_AXIS_TLAST = S_AXIS_TLAST; assign S_AXIS_TREADY = M_AXIS_TREADY; assign M_AXIS_TVALID = S_AXIS_TVALID; end endgenerate // gaxis_pass_through; endmodule //fifo_generator_v13_1_3 /******************************************************************************* * Declaration of top-level module for Conventional FIFO ******************************************************************************/ module fifo_generator_v13_1_3_CONV_VER #( parameter C_COMMON_CLOCK = 0, parameter C_INTERFACE_TYPE = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_COUNT_TYPE = 0, parameter C_DATA_COUNT_WIDTH = 2, parameter C_DEFAULT_VALUE = "", parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_ENABLE_RLOCS = 0, parameter C_FAMILY = "virtex7", //Not allowed in Verilog model parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_ALMOST_EMPTY = 0, parameter C_HAS_ALMOST_FULL = 0, parameter C_HAS_BACKUP = 0, parameter C_HAS_DATA_COUNT = 0, parameter C_HAS_INT_CLK = 0, parameter C_HAS_MEMINIT_FILE = 0, parameter C_HAS_OVERFLOW = 0, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_RD_RST = 0, parameter C_HAS_RST = 0, parameter C_HAS_SRST = 0, parameter C_HAS_UNDERFLOW = 0, parameter C_HAS_VALID = 0, parameter C_HAS_WR_ACK = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_HAS_WR_RST = 0, parameter C_IMPLEMENTATION_TYPE = 0, parameter C_INIT_WR_PNTR_VAL = 0, parameter C_MEMORY_TYPE = 1, parameter C_MIF_FILE_NAME = "", parameter C_OPTIMIZATION_MODE = 0, parameter C_OVERFLOW_LOW = 0, parameter C_PRELOAD_LATENCY = 1, parameter C_PRELOAD_REGS = 0, parameter C_PRIM_FIFO_TYPE = "", parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, parameter C_PROG_EMPTY_TYPE = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, parameter C_PROG_FULL_TYPE = 0, parameter C_RD_DATA_COUNT_WIDTH = 2, parameter C_RD_DEPTH = 256, parameter C_RD_FREQ = 1, parameter C_RD_PNTR_WIDTH = 8, parameter C_UNDERFLOW_LOW = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_ECC = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_USE_FIFO16_FLAGS = 0, parameter C_USE_FWFT_DATA_COUNT = 0, parameter C_VALID_LOW = 0, parameter C_WR_ACK_LOW = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_FREQ = 1, parameter C_WR_PNTR_WIDTH = 8, parameter C_WR_RESPONSE_LATENCY = 1, parameter C_MSGON_VAL = 1, parameter C_ENABLE_RST_SYNC = 1, parameter C_ERROR_INJECTION_TYPE = 0, parameter C_FIFO_TYPE = 0, parameter C_SYNCHRONIZER_STAGE = 2, parameter C_AXI_TYPE = 0 ) ( input BACKUP, input BACKUP_MARKER, input CLK, input RST, input SRST, input WR_CLK, input WR_RST, input RD_CLK, input RD_RST, input [C_DIN_WIDTH-1:0] DIN, input WR_EN, input RD_EN, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, input INT_CLK, input INJECTDBITERR, input INJECTSBITERR, output [C_DOUT_WIDTH-1:0] DOUT, output FULL, output ALMOST_FULL, output WR_ACK, output OVERFLOW, output EMPTY, output ALMOST_EMPTY, output VALID, output UNDERFLOW, output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, output PROG_FULL, output PROG_EMPTY, output SBITERR, output DBITERR, output wr_rst_busy_o, output wr_rst_busy, output rd_rst_busy, output wr_rst_i_out, output rd_rst_i_out ); /* ****************************************************************************** * Definition of Parameters ****************************************************************************** * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) * C_COUNT_TYPE : *not used * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus * C_DEFAULT_VALUE : *not used * C_DIN_WIDTH : Width of DIN bus * C_DOUT_RST_VAL : Reset value of DOUT * C_DOUT_WIDTH : Width of DOUT bus * C_ENABLE_RLOCS : *not used * C_FAMILY : not used in bhv model * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag * C_HAS_BACKUP : *not used * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus * C_HAS_INT_CLK : not used in bhv model * C_HAS_MEMINIT_FILE : *not used * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus * C_HAS_RD_RST : *not used * C_HAS_RST : 1=Core has Async Rst * C_HAS_SRST : 1=Core has Sync Rst * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag * C_HAS_VALID : 1=Core has VALID flag * C_HAS_WR_ACK : 1=Core has WR_ACK flag * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus * C_HAS_WR_RST : *not used * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram * 1=Common-Clock ShiftRam * 2=Indep. Clocks Bram/Dram * 3=Virtex-4 Built-in * 4=Virtex-5 Built-in * C_INIT_WR_PNTR_VAL : *not used * C_MEMORY_TYPE : 1=Block RAM * 2=Distributed RAM * 3=Shift RAM * 4=Built-in FIFO * C_MIF_FILE_NAME : *not used * C_OPTIMIZATION_MODE : *not used * C_OVERFLOW_LOW : 1=OVERFLOW active low * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 * C_PRELOAD_REGS : 1=Use output registers * C_PRIM_FIFO_TYPE : not used in bhv model * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold * C_PROG_EMPTY_TYPE : 0=No programmable empty * 1=Single prog empty thresh constant * 2=Multiple prog empty thresh constants * 3=Single prog empty thresh input * 4=Multiple prog empty thresh inputs * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold * C_PROG_FULL_TYPE : 0=No prog full * 1=Single prog full thresh constant * 2=Multiple prog full thresh constants * 3=Single prog full thresh input * 4=Multiple prog full thresh inputs * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus * C_RD_DEPTH : Depth of read interface (2^N) * C_RD_FREQ : not used in bhv model * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) * C_UNDERFLOW_LOW : 1=UNDERFLOW active low * C_USE_DOUT_RST : 1=Resets DOUT on RST * C_USE_ECC : Used for error injection purpose * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register * C_USE_FIFO16_FLAGS : not used in bhv model * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count * C_VALID_LOW : 1=VALID active low * C_WR_ACK_LOW : 1=WR_ACK active low * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus * C_WR_DEPTH : Depth of write interface (2^N) * C_WR_FREQ : not used in bhv model * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) * C_WR_RESPONSE_LATENCY : *not used * C_MSGON_VAL : *not used by bhv model * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST * 1 = Use RST * C_ERROR_INJECTION_TYPE : 0 = No error injection * 1 = Single bit error injection only * 2 = Double bit error injection only * 3 = Single and double bit error injection ****************************************************************************** * Definition of Ports ****************************************************************************** * BACKUP : Not used * BACKUP_MARKER: Not used * CLK : Clock * DIN : Input data bus * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag * PROG_FULL_THRESH : Threshold for Programmable Full Flag * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag * RD_CLK : Read Domain Clock * RD_EN : Read enable * RD_RST : Read Reset * RST : Asynchronous Reset * SRST : Synchronous Reset * WR_CLK : Write Domain Clock * WR_EN : Write enable * WR_RST : Write Reset * INT_CLK : Internal Clock * INJECTSBITERR: Inject Signle bit error * INJECTDBITERR: Inject Double bit error * ALMOST_EMPTY : One word remaining in FIFO * ALMOST_FULL : One empty space remaining in FIFO * DATA_COUNT : Number of data words in fifo( synchronous to CLK) * DOUT : Output data bus * EMPTY : Empty flag * FULL : Full flag * OVERFLOW : Last write rejected * PROG_EMPTY : Programmable Empty Flag * PROG_FULL : Programmable Full Flag * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) * UNDERFLOW : Last read rejected * VALID : Last read acknowledged, DOUT bus VALID * WR_ACK : Last write acknowledged * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) * SBITERR : Single Bit ECC Error Detected * DBITERR : Double Bit ECC Error Detected ****************************************************************************** */ //---------------------------------------------------------------------------- //- Internal Signals for delayed input signals //- All the input signals except Clock are delayed by 100 ps and then given to //- the models. //---------------------------------------------------------------------------- reg rst_delayed ; reg empty_fb ; reg srst_delayed ; reg wr_rst_delayed ; reg rd_rst_delayed ; reg wr_en_delayed ; reg rd_en_delayed ; reg [C_DIN_WIDTH-1:0] din_delayed ; reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ; reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ; reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ; reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ; reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ; reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ; reg injectdbiterr_delayed ; reg injectsbiterr_delayed ; wire empty_p0_out; always @* rst_delayed <= #`TCQ RST ; always @* empty_fb <= #`TCQ empty_p0_out ; always @* srst_delayed <= #`TCQ SRST ; always @* wr_rst_delayed <= #`TCQ WR_RST ; always @* rd_rst_delayed <= #`TCQ RD_RST ; always @* din_delayed <= #`TCQ DIN ; always @* wr_en_delayed <= #`TCQ WR_EN ; always @* rd_en_delayed <= #`TCQ RD_EN ; always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ; always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ; always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ; always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ; always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ; always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ; /***************************************************************************** * Derived parameters ****************************************************************************/ //There are 2 Verilog behavioral models // 0 = Common-Clock FIFO/ShiftRam FIFO // 1 = Independent Clocks FIFO // 2 = Low Latency Synchronous FIFO // 3 = Low Latency Asynchronous FIFO localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 : (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0; localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0; //Internal reset signals reg rd_rst_asreg = 0; wire rd_rst_asreg_d1; wire rd_rst_asreg_d2; reg rd_rst_asreg_d3 = 0; reg rd_rst_reg = 0; wire rd_rst_comb; reg wr_rst_d0 = 0; reg wr_rst_d1 = 0; reg wr_rst_d2 = 0; reg rd_rst_d0 = 0; reg rd_rst_d1 = 0; reg rd_rst_d2 = 0; reg rd_rst_d3 = 0; reg wrrst_done = 0; reg rdrst_done = 0; reg wr_rst_asreg = 0; wire wr_rst_asreg_d1; wire wr_rst_asreg_d2; reg wr_rst_asreg_d3 = 0; reg rd_rst_wr_d0 = 0; reg rd_rst_wr_d1 = 0; reg rd_rst_wr_d2 = 0; reg wr_rst_reg = 0; reg rst_active_i = 1'b1; reg rst_delayed_d1 = 1'b1; reg rst_delayed_d2 = 1'b1; wire wr_rst_comb; wire wr_rst_i; wire rd_rst_i; wire rst_i; //Internal reset signals reg rst_asreg = 0; reg srst_asreg = 0; wire rst_asreg_d1; wire rst_asreg_d2; reg srst_asreg_d1 = 0; reg srst_asreg_d2 = 0; reg rst_reg = 0; reg srst_reg = 0; wire rst_comb; wire srst_comb; reg rst_full_gen_i = 0; reg rst_full_ff_i = 0; reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}}; wire RD_CLK_P0_IN; wire RST_P0_IN; wire RD_EN_FIFO_IN; wire RD_EN_P0_IN; wire ALMOST_EMPTY_FIFO_OUT; wire ALMOST_FULL_FIFO_OUT; wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; wire EMPTY_FIFO_OUT; wire fifo_empty_fb; wire FULL_FIFO_OUT; wire OVERFLOW_FIFO_OUT; wire PROG_EMPTY_FIFO_OUT; wire PROG_FULL_FIFO_OUT; wire VALID_FIFO_OUT; wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; wire UNDERFLOW_FIFO_OUT; wire WR_ACK_FIFO_OUT; wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; //*************************************************************************** // Internal Signals // The core uses either the internal_ wires or the preload0_ wires depending // on whether the core uses Preload0 or not. // When using preload0, the internal signals connect the internal core to // the preload logic, and the external core's interfaces are tied to the // preload0 signals from the preload logic. //*************************************************************************** wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; wire VALID_P0_OUT; wire EMPTY_P0_OUT; wire ALMOSTEMPTY_P0_OUT; reg EMPTY_P0_OUT_Q; reg ALMOSTEMPTY_P0_OUT_Q; wire UNDERFLOW_P0_OUT; wire RDEN_P0_OUT; wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; wire EMPTY_P0_IN; reg [31:0] DATA_COUNT_FWFT; reg SS_FWFT_WR ; reg SS_FWFT_RD ; wire sbiterr_fifo_out; wire dbiterr_fifo_out; wire inject_sbit_err; wire inject_dbit_err; wire safety_ckt_wr_rst; wire safety_ckt_rd_rst; reg sckt_wr_rst_i_q = 1'b0; wire w_fab_read_data_valid_i; wire w_read_data_valid_i; wire w_ram_valid_i; // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR. assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ? injectsbiterr_delayed : 0; assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ? injectdbiterr_delayed : 0; assign wr_rst_i_out = wr_rst_i; assign rd_rst_i_out = rd_rst_i; assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2]; generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK; always @ (posedge clk_i) sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; end endgenerate // Choose the behavioral model to instantiate based on the C_VERILOG_IMPL // parameter (1=Independent Clocks, 0=Common Clock) localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL; generate case (C_VERILOG_IMPL) 0 : begin : block1 //Common Clock Behavioral Model fifo_generator_v13_1_3_bhv_ver_ss #( .C_FAMILY (C_FAMILY), .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL), .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), .C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL), .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_RST (C_HAS_RST), .C_HAS_SRST (C_HAS_SRST), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_HAS_VALID (C_HAS_VALID), .C_HAS_WR_ACK (C_HAS_WR_ACK), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), .C_PRELOAD_REGS (C_PRELOAD_REGS), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), .C_VALID_LOW (C_VALID_LOW), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_USE_ECC (C_USE_ECC), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE), .C_FIFO_TYPE (C_FIFO_TYPE) ) gen_ss ( .SAFETY_CKT_WR_RST (safety_ckt_wr_rst), .CLK (CLK), .RST (rst_i), .SRST (srst_delayed), .RST_FULL_GEN (rst_full_gen_i), .RST_FULL_FF (rst_full_ff_i), .DIN (din_delayed), .WR_EN (wr_en_delayed), .RD_EN (RD_EN_FIFO_IN), .RD_EN_USER (rd_en_delayed), .USER_EMPTY_FB (empty_fb), .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), .PROG_FULL_THRESH (prog_full_thresh_delayed), .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), .INJECTSBITERR (inject_sbit_err), .INJECTDBITERR (inject_dbit_err), .DOUT (DOUT_FIFO_OUT), .FULL (FULL_FIFO_OUT), .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), .WR_ACK (WR_ACK_FIFO_OUT), .OVERFLOW (OVERFLOW_FIFO_OUT), .EMPTY (EMPTY_FIFO_OUT), .EMPTY_FB (fifo_empty_fb), .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), .VALID (VALID_FIFO_OUT), .UNDERFLOW (UNDERFLOW_FIFO_OUT), .DATA_COUNT (DATA_COUNT_FIFO_OUT), .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), .PROG_FULL (PROG_FULL_FIFO_OUT), .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), .WR_RST_BUSY (wr_rst_busy), .RD_RST_BUSY (rd_rst_busy), .SBITERR (sbiterr_fifo_out), .DBITERR (dbiterr_fifo_out) ); end 1 : begin : block1 //Independent Clocks Behavioral Model fifo_generator_v13_1_3_bhv_ver_as #( .C_FAMILY (C_FAMILY), .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_RST (C_HAS_RST), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_HAS_VALID (C_HAS_VALID), .C_HAS_WR_ACK (C_HAS_WR_ACK), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), .C_PRELOAD_REGS (C_PRELOAD_REGS), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), .C_VALID_LOW (C_VALID_LOW), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_USE_ECC (C_USE_ECC), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) ) gen_as ( .SAFETY_CKT_WR_RST (safety_ckt_wr_rst), .SAFETY_CKT_RD_RST (safety_ckt_rd_rst), .WR_CLK (WR_CLK), .RD_CLK (RD_CLK), .RST (rst_i), .RST_FULL_GEN (rst_full_gen_i), .RST_FULL_FF (rst_full_ff_i), .WR_RST (wr_rst_i), .RD_RST (rd_rst_i), .DIN (din_delayed), .WR_EN (wr_en_delayed), .RD_EN (RD_EN_FIFO_IN), .RD_EN_USER (rd_en_delayed), .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), .PROG_FULL_THRESH (prog_full_thresh_delayed), .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), .INJECTSBITERR (inject_sbit_err), .INJECTDBITERR (inject_dbit_err), .USER_EMPTY_FB (EMPTY_P0_OUT), .DOUT (DOUT_FIFO_OUT), .FULL (FULL_FIFO_OUT), .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), .WR_ACK (WR_ACK_FIFO_OUT), .OVERFLOW (OVERFLOW_FIFO_OUT), .EMPTY (EMPTY_FIFO_OUT), .EMPTY_FB (fifo_empty_fb), .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), .VALID (VALID_FIFO_OUT), .UNDERFLOW (UNDERFLOW_FIFO_OUT), .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), .PROG_FULL (PROG_FULL_FIFO_OUT), .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), .SBITERR (sbiterr_fifo_out), .fab_read_data_valid_i (w_fab_read_data_valid_i), .read_data_valid_i (w_read_data_valid_i), .ram_valid_i (w_ram_valid_i), .DBITERR (dbiterr_fifo_out) ); end 2 : begin : ll_afifo_inst fifo_generator_v13_1_3_beh_ver_ll_afifo #( .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_FIFO_TYPE (C_FIFO_TYPE) ) gen_ll_afifo ( .DIN (din_delayed), .RD_CLK (RD_CLK), .RD_EN (rd_en_delayed), .WR_RST (wr_rst_i), .RD_RST (rd_rst_i), .WR_CLK (WR_CLK), .WR_EN (wr_en_delayed), .DOUT (DOUT), .EMPTY (EMPTY), .FULL (FULL) ); end default : begin : block1 //Independent Clocks Behavioral Model fifo_generator_v13_1_3_bhv_ver_as #( .C_FAMILY (C_FAMILY), .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_RST (C_HAS_RST), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_HAS_VALID (C_HAS_VALID), .C_HAS_WR_ACK (C_HAS_WR_ACK), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), .C_PRELOAD_REGS (C_PRELOAD_REGS), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), .C_VALID_LOW (C_VALID_LOW), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_USE_ECC (C_USE_ECC), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) ) gen_as ( .SAFETY_CKT_WR_RST (safety_ckt_wr_rst), .SAFETY_CKT_RD_RST (safety_ckt_rd_rst), .WR_CLK (WR_CLK), .RD_CLK (RD_CLK), .RST (rst_i), .RST_FULL_GEN (rst_full_gen_i), .RST_FULL_FF (rst_full_ff_i), .WR_RST (wr_rst_i), .RD_RST (rd_rst_i), .DIN (din_delayed), .WR_EN (wr_en_delayed), .RD_EN (RD_EN_FIFO_IN), .RD_EN_USER (rd_en_delayed), .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), .PROG_FULL_THRESH (prog_full_thresh_delayed), .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), .INJECTSBITERR (inject_sbit_err), .INJECTDBITERR (inject_dbit_err), .USER_EMPTY_FB (EMPTY_P0_OUT), .DOUT (DOUT_FIFO_OUT), .FULL (FULL_FIFO_OUT), .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), .WR_ACK (WR_ACK_FIFO_OUT), .OVERFLOW (OVERFLOW_FIFO_OUT), .EMPTY (EMPTY_FIFO_OUT), .EMPTY_FB (fifo_empty_fb), .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), .VALID (VALID_FIFO_OUT), .UNDERFLOW (UNDERFLOW_FIFO_OUT), .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), .PROG_FULL (PROG_FULL_FIFO_OUT), .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), .SBITERR (sbiterr_fifo_out), .DBITERR (dbiterr_fifo_out) ); end endcase endgenerate //************************************************************************** // Connect Internal Signals // (Signals labeled internal_*) // In the normal case, these signals tie directly to the FIFO's inputs and // outputs. // In the case of Preload Latency 0 or 1, there are intermediate // signals between the internal FIFO and the preload logic. //************************************************************************** //*********************************************** // If First-Word Fall-Through, instantiate // the preload0 (FWFT) module //*********************************************** wire rd_en_to_fwft_fifo; wire sbiterr_fwft; wire dbiterr_fwft; wire [C_DOUT_WIDTH-1:0] dout_fwft; wire empty_fwft; wire rd_en_fifo_in; wire stage2_reg_en_i; wire [1:0] valid_stages_i; wire rst_fwft; //wire empty_p0_out; reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1; localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0; localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0; localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0; assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0; generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2 fifo_generator_v13_1_3_bhv_ver_preload0 #( .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_HAS_RST (C_HAS_RST), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_HAS_SRST (C_HAS_SRST), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_USE_ECC (C_USE_ECC), .C_USERVALID_LOW (C_VALID_LOW), .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_FIFO_TYPE (C_FIFO_TYPE) ) fgpl0 ( .SAFETY_CKT_RD_RST(safety_ckt_rd_rst), .RD_CLK (RD_CLK_P0_IN), .RD_RST (RST_P0_IN), .SRST (srst_delayed), .WR_RST_BUSY (wr_rst_busy), .RD_RST_BUSY (rd_rst_busy), .RD_EN (RD_EN_P0_IN), .FIFOEMPTY (EMPTY_P0_IN), .FIFODATA (DATA_P0_IN), .FIFOSBITERR (sbiterr_fifo_out), .FIFODBITERR (dbiterr_fifo_out), // Output .USERDATA (dout_fwft), .USERVALID (VALID_P0_OUT), .USEREMPTY (empty_fwft), .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), .USERUNDERFLOW (UNDERFLOW_P0_OUT), .RAMVALID (), .FIFORDEN (rd_en_fifo_in), .USERSBITERR (sbiterr_fwft), .USERDBITERR (dbiterr_fwft), .STAGE2_REG_EN (stage2_reg_en_i), .fab_read_data_valid_i_o (w_fab_read_data_valid_i), .read_data_valid_i_o (w_read_data_valid_i), .ram_valid_i_o (w_ram_valid_i), .VALID_STAGES (valid_stages_i) ); //*********************************************** // Connect inputs to preload (FWFT) module //*********************************************** //Connect the RD_CLK of the Preload (FWFT) module to CLK if we // have a common-clock FIFO, or RD_CLK if we have an // independent clock FIFO assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0; assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo; assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT; assign DATA_P0_IN = DOUT_FIFO_OUT; //*********************************************** // Connect outputs from preload (FWFT) module //*********************************************** assign VALID = VALID_P0_OUT ; assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; assign UNDERFLOW = UNDERFLOW_P0_OUT ; assign RD_EN_FIFO_IN = rd_en_fifo_in; //*********************************************** // Create DATA_COUNT from First-Word Fall-Through // data count //*********************************************** assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; //*********************************************** // Create DATA_COUNT from First-Word Fall-Through // data count //*********************************************** always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin if (RST_P0_IN) begin EMPTY_P0_OUT_Q <= 1; ALMOSTEMPTY_P0_OUT_Q <= 1; end else begin EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out; // EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT; ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; end end //always //*********************************************** // logic for common-clock data count when FWFT is selected //*********************************************** initial begin SS_FWFT_RD = 1'b0; DATA_COUNT_FWFT = 0 ; SS_FWFT_WR = 1'b0 ; end //initial //*********************************************** // common-clock data count is implemented as an // up-down counter. SS_FWFT_WR and SS_FWFT_RD // are the up/down enables for the counter. //*********************************************** always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin if (C_VALID_LOW == 1) begin SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ; end else begin SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ; end SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; end //*********************************************** // common-clock data count is implemented as an // up-down counter for FWFT. This always block // calculates the counter. //*********************************************** always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin if (RST_P0_IN) begin DATA_COUNT_FWFT <= 0; end else begin //if (srst_delayed && (C_HAS_SRST == 1) ) begin if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin DATA_COUNT_FWFT <= #`TCQ 0; end else begin case ( {SS_FWFT_WR, SS_FWFT_RD}) 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; endcase end //if SRST end //IF RST end //always end endgenerate // : block2 // AXI Streaming Packet FIFO reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0; reg partial_packet = 0; reg stage1_eop_d1 = 0; reg rd_en_fifo_in_d1 = 0; reg eop_at_stage2 = 0; reg ram_pkt_empty = 0; reg ram_pkt_empty_d1 = 0; wire [C_DOUT_WIDTH-1:0] dout_p0_out; wire packet_empty_wr; wire wr_rst_fwft_pkt_fifo; wire dummy_wr_eop; wire ram_wr_en_pkt_fifo; wire wr_eop; wire ram_rd_en_compare; wire stage1_eop; wire pkt_ready_to_read; wire rd_en_2_stage2; // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming) // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of // write packet count generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin if (wr_rst_fwft_pkt_fifo) partial_packet <= 1'b0; else begin if (srst_delayed | wr_rst_busy | rd_rst_busy) partial_packet <= #`TCQ 1'b0; else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0])) partial_packet <= #`TCQ 1'b1; else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo) partial_packet <= #`TCQ 1'b0; end end end endgenerate // gdummy_wr_eop generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0; assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet); assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1]; always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) begin stage1_eop_d1 <= 1'b0; rd_en_fifo_in_d1 <= 1'b0; end else begin if (srst_delayed | wr_rst_busy | rd_rst_busy) begin stage1_eop_d1 <= #`TCQ 1'b0; rd_en_fifo_in_d1 <= #`TCQ 1'b0; end else begin stage1_eop_d1 <= #`TCQ stage1_eop; rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in; end end end assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1; assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT); assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop); assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop; fifo_generator_v13_1_3_bhv_ver_preload0 #( .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_HAS_RST (C_HAS_RST), .C_HAS_SRST (C_HAS_SRST), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_ECC (C_USE_ECC), .C_USERVALID_LOW (C_VALID_LOW), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_FIFO_TYPE (2) // Enable low latency fwft logic ) pkt_fifo_fwft ( .SAFETY_CKT_RD_RST(safety_ckt_rd_rst), .RD_CLK (RD_CLK_P0_IN), .RD_RST (rst_fwft), .SRST (srst_delayed), .WR_RST_BUSY (wr_rst_busy), .RD_RST_BUSY (rd_rst_busy), .RD_EN (rd_en_delayed), .FIFOEMPTY (pkt_ready_to_read), .FIFODATA (dout_fwft), .FIFOSBITERR (sbiterr_fwft), .FIFODBITERR (dbiterr_fwft), // Output .USERDATA (dout_p0_out), .USERVALID (), .USEREMPTY (empty_p0_out), .USERALMOSTEMPTY (), .USERUNDERFLOW (), .RAMVALID (), .FIFORDEN (rd_en_2_stage2), .USERSBITERR (SBITERR), .USERDBITERR (DBITERR), .STAGE2_REG_EN (), .VALID_STAGES () ); assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2)); assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2; always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) eop_at_stage2 <= 1'b0; else if (stage2_reg_en_i) eop_at_stage2 <= #`TCQ stage1_eop; end //--------------------------------------------------------------------------- // Write and Read Packet Count //--------------------------------------------------------------------------- always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin if (wr_rst_fwft_pkt_fifo) wr_pkt_count <= 0; else if (srst_delayed | wr_rst_busy | rd_rst_busy) wr_pkt_count <= #`TCQ 0; else if (wr_eop) wr_pkt_count <= #`TCQ wr_pkt_count + 1; end end endgenerate // gpkt_fifo_fwft assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out; assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out; generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) begin rd_pkt_count <= 0; rd_pkt_count_plus1 <= 1; end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin rd_pkt_count <= #`TCQ 0; rd_pkt_count_plus1 <= #`TCQ 1; end else if (stage2_reg_en_i && stage1_eop) begin rd_pkt_count <= #`TCQ rd_pkt_count + 1; rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1; end end always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) begin ram_pkt_empty <= 1'b1; ram_pkt_empty_d1 <= 1'b1; end else if (SRST | wr_rst_busy | rd_rst_busy) begin ram_pkt_empty <= #`TCQ 1'b1; ram_pkt_empty_d1 <= #`TCQ 1'b1; end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin ram_pkt_empty <= #`TCQ 1'b0; ram_pkt_empty_d1 <= #`TCQ 1'b0; end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin ram_pkt_empty <= #`TCQ 1'b1; end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin ram_pkt_empty_d1 <= #`TCQ 1'b1; end end end endgenerate //grss_pkt_cnt localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH; reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0; wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd; generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin if (wr_rst_fwft_pkt_fifo) wr_pkt_count_b2g <= 0; else wr_pkt_count_b2g <= #`TCQ wr_pkt_count; end // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) wr_pkt_count_q <= 0; else wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g}; end always @* begin if (stage1_eop) rd_pkt_count <= rd_pkt_count_reg + 1; else rd_pkt_count <= rd_pkt_count_reg; end assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH]; always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) rd_pkt_count_reg <= 0; else if (rd_en_fifo_in) rd_pkt_count_reg <= #`TCQ rd_pkt_count; end always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) begin ram_pkt_empty <= 1'b1; ram_pkt_empty_d1 <= 1'b1; end else if (rd_pkt_count != wr_pkt_count_rd) begin ram_pkt_empty <= #`TCQ 1'b0; ram_pkt_empty_d1 <= #`TCQ 1'b0; end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin ram_pkt_empty <= #`TCQ 1'b1; end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin ram_pkt_empty_d1 <= #`TCQ 1'b1; end end // Synchronize the empty in write domain always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin if (wr_rst_fwft_pkt_fifo) pkt_empty_sync <= 'b1; else pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out}; end end endgenerate //gras_pkt_cnt generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO //*********************************************** // If NOT First-Word Fall-Through, wire the outputs // of the internal _ss or _as FIFO directly to the // output, and do not instantiate the preload0 // module. //*********************************************** assign RD_CLK_P0_IN = 0; assign RST_P0_IN = 0; assign RD_EN_P0_IN = 0; assign RD_EN_FIFO_IN = rd_en_delayed; assign DOUT = DOUT_FIFO_OUT; assign DATA_P0_IN = 0; assign VALID = VALID_FIFO_OUT; assign EMPTY = EMPTY_FIFO_OUT; assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; assign EMPTY_P0_IN = 0; assign UNDERFLOW = UNDERFLOW_FIFO_OUT; assign DATA_COUNT = DATA_COUNT_FIFO_OUT; assign SBITERR = sbiterr_fifo_out; assign DBITERR = dbiterr_fifo_out; end endgenerate // STD_FIFO generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO assign empty_p0_out = empty_fwft; assign SBITERR = sbiterr_fwft; assign DBITERR = dbiterr_fwft; assign DOUT = dout_fwft; assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo; end endgenerate // NO_PKT_FIFO //*********************************************** // Connect user flags to internal signals //*********************************************** //If we are using extra logic for the FWFT data count, then override the //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. generate if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3 if (C_COMMON_CLOCK == 0) begin : block_ic assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); end //block_ic else begin assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end end //block3 endgenerate //If we are using extra logic for the FWFT data count, then override the //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. generate if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30 if (C_COMMON_CLOCK == 0) begin : block_ic assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); end else begin assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end end //block30 endgenerate //If we are using extra logic for the FWFT data count, then override the //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. generate if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both if (C_COMMON_CLOCK == 0) begin : block_ic_both assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT)); end else begin assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end end //block30_both endgenerate generate if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both if (C_COMMON_CLOCK == 0) begin : block_ic_both assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT)); end //block_ic_both else begin assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end end //block3_both endgenerate //If we are not using extra logic for the FWFT data count, //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the //internal FIFO instance generate if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end endgenerate //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal //FIFO instance generate if (C_USE_FWFT_DATA_COUNT==1) begin : block4 assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; end else begin : block4 assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; end endgenerate //Connect other flags to the internal FIFO instance assign FULL = FULL_FIFO_OUT; assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; assign WR_ACK = WR_ACK_FIFO_OUT; assign OVERFLOW = OVERFLOW_FIFO_OUT; assign PROG_FULL = PROG_FULL_FIFO_OUT; assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; /************************************************************************** * find_log2 * Returns the 'log2' value for the input value for the supported ratios ***************************************************************************/ function integer find_log2; input integer int_val; integer i,j; begin i = 1; j = 0; for (i = 1; i < int_val; i = i*2) begin j = j + 1; end find_log2 = j; end endfunction // if an asynchronous FIFO has been selected, display a message that the FIFO // will not be cycle-accurate in simulation initial begin if (C_IMPLEMENTATION_TYPE == 2) begin $display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information."); end else if (C_MEMORY_TYPE == 4) begin $display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado."); $finish; end if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin $display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH."); $finish; end if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin $display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH."); $finish; end if (C_USE_ECC == 1) begin if (C_DIN_WIDTH != C_DOUT_WIDTH) begin $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration."); $finish; end if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection."); $finish; end end end //initial /************************************************************************** * Internal reset logic **************************************************************************/ assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0; assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0; assign rst_i = C_HAS_RST ? rst_reg : 0; wire rst_2_sync; wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST; wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK; wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK; localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE : (C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2; reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}}; reg [1:0] wrst_cc = {2{1'b0}}; reg [1:0] rrst_cc = {2{1'b0}}; generate if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt reg[1:0] rst_d1_safety =1; reg[1:0] rst_d2_safety =1; reg[1:0] rst_d3_safety =1; reg[1:0] rst_d4_safety =1; reg[1:0] rst_d5_safety =1; reg[1:0] rst_d6_safety =1; reg[1:0] rst_d7_safety =1; always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst if (rst_2_sync_safety == 1'b1) begin rst_d1_safety <= 1'b1; rst_d2_safety <= 1'b1; rst_d3_safety <= 1'b1; rst_d4_safety <= 1'b1; rst_d5_safety <= 1'b1; rst_d6_safety <= 1'b1; rst_d7_safety <= 1'b1; end else begin rst_d1_safety <= #`TCQ 1'b0; rst_d2_safety <= #`TCQ rst_d1_safety; rst_d3_safety <= #`TCQ rst_d2_safety; rst_d4_safety <= #`TCQ rst_d3_safety; rst_d5_safety <= #`TCQ rst_d4_safety; rst_d6_safety <= #`TCQ rst_d5_safety; rst_d7_safety <= #`TCQ rst_d6_safety; end //if end //prst always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety if(rst_d7_safety == 1 && WR_EN == 1) begin $display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled."); end //if end //always end // grst_safety_ckt endgenerate // if (C_EN_SAFET_CKT == 1) // assertion:the reset shud be atleast 3 cycles wide. generate reg safety_ckt_wr_rst_i = 1'b0; if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync always @* begin wr_rst_reg <= wr_rst_delayed; rd_rst_reg <= rd_rst_delayed; rst_reg <= 1'b0; srst_reg <= 1'b0; end assign rst_2_sync = wr_rst_delayed; assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0; assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0; assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0; assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0; // end : gnrst_sync end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst reg fifo_wrst_done = 1'b0; reg fifo_rrst_done = 1'b0; reg sckt_wrst_i = 1'b0; reg sckt_wrst_i_q = 1'b0; reg rd_rst_active = 1'b0; reg rd_rst_middle = 1'b0; reg sckt_rd_rst_d1 = 1'b0; reg [1:0] rst_delayed_ic_w = 2'h0; wire rst_delayed_ic_w_i; reg [1:0] rst_delayed_ic_r = 2'h0; wire rst_delayed_ic_r_i; wire arst_sync_rst; wire fifo_rst_done; wire fifo_rst_active; assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg; assign rst_2_sync = rst_delayed_ic_w_i; assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1]; assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0; assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0; assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done; assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1]; always @(posedge WR_CLK or posedge rst_delayed) begin if (rst_delayed == 1'b1 && C_HAS_RST) rst_delayed_ic_w <= 2'b11; else rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0}; end assign rst_delayed_ic_w_i = rst_delayed_ic_w[1]; always @(posedge RD_CLK or posedge rst_delayed) begin if (rst_delayed == 1'b1 && C_HAS_RST) rst_delayed_ic_r <= 2'b11; else rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0}; end assign rst_delayed_ic_r_i = rst_delayed_ic_r[1]; always @(posedge WR_CLK) begin sckt_wrst_i_q <= #`TCQ sckt_wrst_i; sckt_wr_rst_i_q <= #`TCQ wr_rst_busy; safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q; if (arst_sync_rst && ~fifo_rst_active) sckt_wrst_i <= #`TCQ 1'b1; else if (sckt_wrst_i && fifo_rst_done) sckt_wrst_i <= #`TCQ 1'b0; else sckt_wrst_i <= #`TCQ sckt_wrst_i; if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1]) fifo_rrst_done <= #`TCQ 1'b1; else if (fifo_rst_done) fifo_rrst_done <= #`TCQ 1'b0; else fifo_rrst_done <= #`TCQ fifo_rrst_done; if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1]) fifo_wrst_done <= #`TCQ 1'b1; else if (fifo_rst_done) fifo_wrst_done <= #`TCQ 1'b0; else fifo_wrst_done <= #`TCQ fifo_wrst_done; end always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin if (rst_delayed_ic_w_i == 1'b1) begin wr_rst_asreg <= 1'b1; end else begin if (wr_rst_asreg_d1 == 1'b1) begin wr_rst_asreg <= #`TCQ 1'b0; end else begin wr_rst_asreg <= #`TCQ wr_rst_asreg; end end end always @(posedge WR_CLK or posedge rst_delayed) begin if (rst_delayed == 1'b1) begin wr_rst_asreg <= 1'b1; end else begin if (wr_rst_asreg_d1 == 1'b1) begin wr_rst_asreg <= #`TCQ 1'b0; end else begin wr_rst_asreg <= #`TCQ wr_rst_asreg; end end end always @(posedge WR_CLK) begin wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg}; wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i}; rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst}; arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i}; end assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2]; assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1]; assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0; always @(posedge WR_CLK or posedge wr_rst_comb) begin if (wr_rst_comb == 1'b1) begin wr_rst_reg <= 1'b1; end else begin wr_rst_reg <= #`TCQ 1'b0; end end always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin if (rst_delayed_ic_r_i == 1'b1) begin rd_rst_asreg <= 1'b1; end else begin if (rd_rst_asreg_d1 == 1'b1) begin rd_rst_asreg <= #`TCQ 1'b0; end else begin rd_rst_asreg <= #`TCQ rd_rst_asreg; end end end always @(posedge RD_CLK) begin rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg}; rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i}; rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2}; sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst; if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin rd_rst_active <= #`TCQ 1'b1; rd_rst_middle <= #`TCQ 1'b1; end else if (safety_ckt_rd_rst) rd_rst_active <= #`TCQ 1'b0; else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst) rd_rst_middle <= #`TCQ 1'b0; end assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2]; assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1]; assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0; always @(posedge RD_CLK or posedge rd_rst_comb) begin if (rd_rst_comb == 1'b1) begin rd_rst_reg <= 1'b1; end else begin rd_rst_reg <= #`TCQ 1'b0; end end // end : g7s_ic_rst end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst reg [1:0] rst_delayed_cc = 2'h0; wire rst_delayed_cc_i; assign rst_comb = !rst_asreg_d2 && rst_asreg; assign rst_2_sync = rst_delayed_cc_i; assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0; assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0; always @(posedge CLK or posedge rst_delayed) begin if (rst_delayed == 1'b1) rst_delayed_cc <= 2'b11; else rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0}; end assign rst_delayed_cc_i = rst_delayed_cc[1]; always @(posedge CLK or posedge rst_delayed_cc_i) begin if (rst_delayed_cc_i == 1'b1) begin rst_asreg <= 1'b1; end else begin if (rst_asreg_d1 == 1'b1) begin rst_asreg <= #`TCQ 1'b0; end else begin rst_asreg <= #`TCQ rst_asreg; end end end always @(posedge CLK) begin wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg}; wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]}; sckt_wr_rst_i_q <= #`TCQ wr_rst_busy; safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q; arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i}; end assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2]; assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1]; assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0; assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0; always @(posedge CLK or posedge rst_comb) begin if (rst_comb == 1'b1) begin rst_reg <= 1'b1; end else begin rst_reg <= #`TCQ 1'b0; end end // end : g7s_cc_rst end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i; assign rd_rst_busy = rst_reg; assign rst_2_sync = srst_delayed; always @* rst_full_ff_i <= rst_reg; always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0; assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0; assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0; always @(posedge CLK) begin rst_delayed_d1 <= #`TCQ srst_delayed; rst_delayed_d2 <= #`TCQ rst_delayed_d1; sckt_wr_rst_i_q <= #`TCQ wr_rst_busy; if (rst_reg || rst_delayed_d2) begin rst_active_i <= #`TCQ 1'b1; end else begin rst_active_i <= #`TCQ rst_reg; end end always @(posedge CLK) begin if (~rst_reg && srst_delayed) begin rst_reg <= #`TCQ 1'b1; end else if (rst_reg) begin rst_reg <= #`TCQ 1'b0; end else begin rst_reg <= #`TCQ rst_reg; end end // end : g8s_cc_rst end else begin assign wr_rst_busy = 1'b0; assign rd_rst_busy = 1'b0; assign safety_ckt_wr_rst = 1'b0; assign safety_ckt_rd_rst = 1'b0; end endgenerate generate if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1 // RST_FULL_GEN replaces the reset falling edge detection used to de-assert // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & // PROG_FULL reg rst_d1 = 1'b0; reg rst_d2 = 1'b0; reg rst_d3 = 1'b0; reg rst_d4 = 1'b0; reg rst_d5 = 1'b0; always @ (posedge rst_2_sync or posedge clk_2_sync) begin if (rst_2_sync) begin rst_d1 <= 1'b1; rst_d2 <= 1'b1; rst_d3 <= 1'b1; rst_d4 <= 1'b1; end else begin if (srst_delayed) begin rst_d1 <= #`TCQ 1'b1; rst_d2 <= #`TCQ 1'b1; rst_d3 <= #`TCQ 1'b1; rst_d4 <= #`TCQ 1'b1; end else begin rst_d1 <= #`TCQ wr_rst_busy; rst_d2 <= #`TCQ rst_d1; rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst; rst_d4 <= #`TCQ rst_d3; end end end always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ; always @* rst_full_gen_i <= rst_d3; end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; end endgenerate // grstd1 endmodule //fifo_generator_v13_1_3_conv_ver module fifo_generator_v13_1_3_sync_stage #( parameter C_WIDTH = 10 ) ( input RST, input CLK, input [C_WIDTH-1:0] DIN, output reg [C_WIDTH-1:0] DOUT = 0 ); always @ (posedge RST or posedge CLK) begin if (RST) DOUT <= 0; else DOUT <= #`TCQ DIN; end endmodule // fifo_generator_v13_1_3_sync_stage /******************************************************************************* * Declaration of Independent-Clocks FIFO Module ******************************************************************************/ module fifo_generator_v13_1_3_bhv_ver_as /*************************************************************************** * Declare user parameters and their defaults ***************************************************************************/ #( parameter C_FAMILY = "virtex7", parameter C_DATA_COUNT_WIDTH = 2, parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_ALMOST_EMPTY = 0, parameter C_HAS_ALMOST_FULL = 0, parameter C_HAS_DATA_COUNT = 0, parameter C_HAS_OVERFLOW = 0, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_RST = 0, parameter C_HAS_UNDERFLOW = 0, parameter C_HAS_VALID = 0, parameter C_HAS_WR_ACK = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_IMPLEMENTATION_TYPE = 0, parameter C_MEMORY_TYPE = 1, parameter C_OVERFLOW_LOW = 0, parameter C_PRELOAD_LATENCY = 1, parameter C_PRELOAD_REGS = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, parameter C_PROG_EMPTY_TYPE = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, parameter C_PROG_FULL_TYPE = 0, parameter C_RD_DATA_COUNT_WIDTH = 2, parameter C_RD_DEPTH = 256, parameter C_RD_PNTR_WIDTH = 8, parameter C_UNDERFLOW_LOW = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_USE_FWFT_DATA_COUNT = 0, parameter C_VALID_LOW = 0, parameter C_WR_ACK_LOW = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_PNTR_WIDTH = 8, parameter C_USE_ECC = 0, parameter C_ENABLE_RST_SYNC = 1, parameter C_ERROR_INJECTION_TYPE = 0, parameter C_SYNCHRONIZER_STAGE = 2 ) /*************************************************************************** * Declare Input and Output Ports ***************************************************************************/ ( input SAFETY_CKT_WR_RST, input SAFETY_CKT_RD_RST, input [C_DIN_WIDTH-1:0] DIN, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, input RD_CLK, input RD_EN, input RD_EN_USER, input RST, input RST_FULL_GEN, input RST_FULL_FF, input WR_RST, input RD_RST, input WR_CLK, input WR_EN, input INJECTDBITERR, input INJECTSBITERR, input USER_EMPTY_FB, input fab_read_data_valid_i, input read_data_valid_i, input ram_valid_i, output reg ALMOST_EMPTY = 1'b1, output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL, output [C_DOUT_WIDTH-1:0] DOUT, output reg EMPTY = 1'b1, output reg EMPTY_FB = 1'b1, output reg FULL = C_FULL_FLAGS_RST_VAL, output OVERFLOW, output PROG_EMPTY, output PROG_FULL, output VALID, output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, output UNDERFLOW, output WR_ACK, output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, output SBITERR, output DBITERR ); reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; /*************************************************************************** * Parameters used as constants **************************************************************************/ localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0; //When RST is present, set FULL reset value to '1'. //If core has no RST, make sure FULL powers-on as '0'. localparam C_DEPTH_RATIO_WR = (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; localparam C_DEPTH_RATIO_RD = (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC // -----------------|------------------|-----------------|--------------- // 1 | 8 | C_RD_PNTR_WIDTH | 2 // 1 | 4 | C_RD_PNTR_WIDTH | 2 // 1 | 2 | C_RD_PNTR_WIDTH | 2 // 1 | 1 | C_WR_PNTR_WIDTH | 2 // 2 | 1 | C_WR_PNTR_WIDTH | 4 // 4 | 1 | C_WR_PNTR_WIDTH | 8 // 8 | 1 | C_WR_PNTR_WIDTH | 16 localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; localparam [31:0] log2_reads_per_write = log2_val(reads_per_write); localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; localparam [31:0] log2_writes_per_read = log2_val(writes_per_read); /************************************************************************** * FIFO Contents Tracking and Data Count Calculations *************************************************************************/ // Memory which will be used to simulate a FIFO reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; // Local parameters used to determine whether to inject ECC error or not localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0; localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION; // Array that holds the error injection type (single/double bit error) on // a specific write operation, which is returned on read to corrupt the // output data. reg [1:0] ecc_err[C_WR_DEPTH-1:0]; //The amount of data stored in the FIFO at any time is given // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK // domain. //num_wr_bits is calculated by considering the total words in the FIFO, // and the state of the read pointer (which may not have yet crossed clock // domains.) //num_rd_bits is calculated by considering the total words in the FIFO, // and the state of the write pointer (which may not have yet crossed clock // domains.) reg [31:0] num_wr_bits; reg [31:0] num_rd_bits; reg [31:0] next_num_wr_bits; reg [31:0] next_num_rd_bits; //The write pointer - tracks write operations // (Works opposite to core: wr_ptr is a DOWN counter) reg [31:0] wr_ptr; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; wire wr_rst_i = WR_RST; reg wr_rst_d1 =0; //The read pointer - tracks read operations // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) reg [31:0] rd_ptr; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; wire rd_rst_i = RD_RST; wire ram_rd_en; wire empty_int; wire almost_empty_int; wire ram_wr_en; wire full_int; wire almost_full_int; reg ram_rd_en_d1 = 1'b0; reg fab_rd_en_d1 = 1'b0; // Delayed ram_rd_en is needed only for STD Embedded register option generate if (C_PRELOAD_LATENCY == 2) begin : grd_d always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) ram_rd_en_d1 <= 1'b0; else ram_rd_en_d1 <= #`TCQ ram_rd_en; end end endgenerate generate if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1 always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) ram_rd_en_d1 <= 1'b0; else ram_rd_en_d1 <= #`TCQ ram_rd_en; fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; end end endgenerate // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; end else begin : rdl // Read depth lesser than or equal to write depth assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end endgenerate // Generate Empty and Almost Empty // ram_rd_en used to determine EMPTY should depend on the EMPTY. assign ram_rd_en = RD_EN & !EMPTY; assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); // Register Empty and Almost Empty always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin EMPTY <= 1'b1; ALMOST_EMPTY <= 1'b1; rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}}; end else begin rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; if (empty_int) EMPTY <= #`TCQ 1'b1; else EMPTY <= #`TCQ 1'b0; if (!EMPTY) begin if (almost_empty_int) ALMOST_EMPTY <= #`TCQ 1'b1; else ALMOST_EMPTY <= #`TCQ 1'b0; end end // rd_rst_i end // always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin EMPTY_FB <= 1'b1; end else begin if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) EMPTY_FB <= #`TCQ 1'b1; else if (empty_int) EMPTY_FB <= #`TCQ 1'b1; else EMPTY_FB <= #`TCQ 1'b0; end // rd_rst_i end // always // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; end else begin : wdl // Write depth lesser than or equal to read depth assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; end endgenerate // Generate FULL and ALMOST_FULL // ram_wr_en used to determine FULL should depend on the FULL. assign ram_wr_en = WR_EN & !FULL; assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); // Register FULL and ALMOST_FULL Empty always @ (posedge WR_CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF) begin FULL <= C_FULL_FLAGS_RST_VAL; ALMOST_FULL <= C_FULL_FLAGS_RST_VAL; end else begin if (full_int) begin FULL <= #`TCQ 1'b1; end else begin FULL <= #`TCQ 1'b0; end if (RST_FULL_GEN) begin ALMOST_FULL <= #`TCQ 1'b0; end else if (!FULL) begin if (almost_full_int) ALMOST_FULL <= #`TCQ 1'b1; else ALMOST_FULL <= #`TCQ 1'b0; end end // wr_rst_i end // always always @ (posedge WR_CLK or posedge wr_rst_i) begin if (wr_rst_i) begin wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}}; end else begin wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; end // wr_rst_i end // always // Determine which stage in FWFT registers are valid reg stage1_valid = 0; reg stage2_valid = 0; generate if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin stage1_valid <= 0; stage2_valid <= 0; end else begin if (!stage1_valid && !stage2_valid) begin if (!EMPTY) stage1_valid <= #`TCQ 1'b1; else stage1_valid <= #`TCQ 1'b0; end else if (stage1_valid && !stage2_valid) begin if (EMPTY) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end end else if (!stage1_valid && stage2_valid) begin if (EMPTY && RD_EN_USER) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b0; end else if (!EMPTY && RD_EN_USER) begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b0; end else if (!EMPTY && !RD_EN_USER) begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end end else if (stage1_valid && stage2_valid) begin if (EMPTY && RD_EN_USER) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end end else begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b0; end end // rd_rst_i end // always end endgenerate //Pointers passed into opposite clock domain reg [31:0] wr_ptr_rdclk; reg [31:0] wr_ptr_rdclk_next; reg [31:0] rd_ptr_wrclk; reg [31:0] rd_ptr_wrclk_next; //Amount of data stored in the FIFO scaled to the narrowest (deepest) port // (Do not include data in FWFT stages) //Used to calculate PROG_EMPTY. wire [31:0] num_read_words_pe = num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); //Amount of data stored in the FIFO scaled to the narrowest (deepest) port // (Do not include data in FWFT stages) //Used to calculate PROG_FULL. wire [31:0] num_write_words_pf = num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); /************************** * Read Data Count *************************/ reg [31:0] num_read_words_dc; reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; always @(num_rd_bits) begin if (C_USE_FWFT_DATA_COUNT) begin //If using extra logic for FWFT Data Counts, // then scale FIFO contents to read domain, // and add two read words for FWFT stages //This value is only a temporary value and not used in the code. num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); //Trim the read words for use with RD_DATA_COUNT num_read_words_sized_i = num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; end else begin //If not using extra logic for FWFT Data Counts, // then scale FIFO contents to read domain. //This value is only a temporary value and not used in the code. num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; //Trim the read words for use with RD_DATA_COUNT num_read_words_sized_i = num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; end //if (C_USE_FWFT_DATA_COUNT) end //always /************************** * Write Data Count *************************/ reg [31:0] num_write_words_dc; reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; always @(num_wr_bits) begin if (C_USE_FWFT_DATA_COUNT) begin //Calculate the Data Count value for the number of write words, // when using First-Word Fall-Through with extra logic for Data // Counts. This takes into consideration the number of words that // are expected to be stored in the FWFT register stages (it always // assumes they are filled). //This value is scaled to the Write Domain. //The expression (((A-1)/B))+1 divides A/B, but takes the // ceiling of the result. //When num_wr_bits==0, set the result manually to prevent // division errors. //EXTRA_WORDS_DC is the number of words added to write_words // due to FWFT. //This value is only a temporary value and not used in the code. num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; //Trim the write words for use with WR_DATA_COUNT num_write_words_sized_i = num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; end else begin //Calculate the Data Count value for the number of write words, when NOT // using First-Word Fall-Through with extra logic for Data Counts. This // calculates only the number of words in the internal FIFO. //The expression (((A-1)/B))+1 divides A/B, but takes the // ceiling of the result. //This value is scaled to the Write Domain. //When num_wr_bits==0, set the result manually to prevent // division errors. //This value is only a temporary value and not used in the code. num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; //Trim the read words for use with RD_DATA_COUNT num_write_words_sized_i = num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; end //if (C_USE_FWFT_DATA_COUNT) end //always /*************************************************************************** * Internal registers and wires **************************************************************************/ //Temporary signals used for calculating the model's outputs. These //are only used in the assign statements immediately following wire, //parameter, and function declarations. wire [C_DOUT_WIDTH-1:0] ideal_dout_out; wire valid_i; wire valid_out1; wire valid_out2; wire valid_out; wire underflow_i; //Ideal FIFO signals. These are the raw output of the behavioral model, //which behaves like an ideal FIFO. reg [1:0] err_type = 0; reg [1:0] err_type_d1 = 0; reg [1:0] err_type_both = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0; reg ideal_wr_ack = 0; reg ideal_valid = 0; reg ideal_overflow = C_OVERFLOW_LOW; reg ideal_underflow = C_UNDERFLOW_LOW; reg ideal_prog_full = 0; reg ideal_prog_empty = 1; reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; //Assorted reg values for delayed versions of signals reg valid_d1 = 0; reg valid_d2 = 0; //user specified value for reseting the size of the fifo reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; //temporary registers for WR_RESPONSE_LATENCY feature integer tmp_wr_listsize; integer tmp_rd_listsize; //Signal for registered version of prog full and empty //Threshold values for Programmable Flags integer prog_empty_actual_thresh_assert; integer prog_empty_actual_thresh_negate; integer prog_full_actual_thresh_assert; integer prog_full_actual_thresh_negate; /**************************************************************************** * Function Declarations ***************************************************************************/ /************************************************************************** * write_fifo * This task writes a word to the FIFO memory and updates the * write pointer. * FIFO size is relative to write domain. ***************************************************************************/ task write_fifo; begin memory[wr_ptr] <= DIN; wr_pntr <= #`TCQ wr_pntr + 1; // Store the type of error injection (double/single) on write case (C_ERROR_INJECTION_TYPE) 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; default: ecc_err[wr_ptr] <= 0; endcase // (Works opposite to core: wr_ptr is a DOWN counter) if (wr_ptr == 0) begin wr_ptr <= C_WR_DEPTH - 1; end else begin wr_ptr <= wr_ptr - 1; end end endtask // write_fifo /************************************************************************** * read_fifo * This task reads a word from the FIFO memory and updates the read * pointer. It's output is the ideal_dout bus. * FIFO size is relative to write domain. ***************************************************************************/ task read_fifo; integer i; reg [C_DOUT_WIDTH-1:0] tmp_dout; reg [C_DIN_WIDTH-1:0] memory_read; reg [31:0] tmp_rd_ptr; reg [31:0] rd_ptr_high; reg [31:0] rd_ptr_low; reg [1:0] tmp_ecc_err; begin rd_pntr <= #`TCQ rd_pntr + 1; // output is wider than input if (reads_per_write == 0) begin tmp_dout = 0; tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); for (i = writes_per_read - 1; i >= 0; i = i - 1) begin tmp_dout = tmp_dout << C_DIN_WIDTH; tmp_dout = tmp_dout | memory[tmp_rd_ptr]; // (Works opposite to core: rd_ptr is a DOWN counter) if (tmp_rd_ptr == 0) begin tmp_rd_ptr = C_WR_DEPTH - 1; end else begin tmp_rd_ptr = tmp_rd_ptr - 1; end end // output is symmetric end else if (reads_per_write == 1) begin tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; // Retreive the error injection type. Based on the error injection type // corrupt the output data. tmp_ecc_err = ecc_err[rd_ptr]; if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error if (C_DOUT_WIDTH == 1) begin $display("FAILURE : Data width must be >= 2 for double bit error injection."); $finish; end else if (C_DOUT_WIDTH == 2) tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; else tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; end else begin tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; end err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; end else begin err_type <= 0; end // input is wider than output end else begin rd_ptr_high = rd_ptr >> log2_reads_per_write; rd_ptr_low = rd_ptr & (reads_per_write - 1); memory_read = memory[rd_ptr_high]; tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); end ideal_dout <= tmp_dout; // (Works opposite to core: rd_ptr is a DOWN counter) if (rd_ptr == 0) begin rd_ptr <= C_RD_DEPTH - 1; end else begin rd_ptr <= rd_ptr - 1; end end endtask /************************************************************************** * log2_val * Returns the 'log2' value for the input value for the supported ratios ***************************************************************************/ function [31:0] log2_val; input [31:0] binary_val; begin if (binary_val == 8) begin log2_val = 3; end else if (binary_val == 4) begin log2_val = 2; end else begin log2_val = 1; end end endfunction /*********************************************************************** * hexstr_conv * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) ***********************************************************************/ function [C_DOUT_WIDTH-1:0] hexstr_conv; input [(C_DOUT_WIDTH*8)-1:0] def_data; integer index,i,j; reg [3:0] bin; begin index = 0; hexstr_conv = 'b0; for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin case (def_data[7:0]) 8'b00000000 : begin bin = 4'b0000; i = -1; end 8'b00110000 : bin = 4'b0000; 8'b00110001 : bin = 4'b0001; 8'b00110010 : bin = 4'b0010; 8'b00110011 : bin = 4'b0011; 8'b00110100 : bin = 4'b0100; 8'b00110101 : bin = 4'b0101; 8'b00110110 : bin = 4'b0110; 8'b00110111 : bin = 4'b0111; 8'b00111000 : bin = 4'b1000; 8'b00111001 : bin = 4'b1001; 8'b01000001 : bin = 4'b1010; 8'b01000010 : bin = 4'b1011; 8'b01000011 : bin = 4'b1100; 8'b01000100 : bin = 4'b1101; 8'b01000101 : bin = 4'b1110; 8'b01000110 : bin = 4'b1111; 8'b01100001 : bin = 4'b1010; 8'b01100010 : bin = 4'b1011; 8'b01100011 : bin = 4'b1100; 8'b01100100 : bin = 4'b1101; 8'b01100101 : bin = 4'b1110; 8'b01100110 : bin = 4'b1111; default : begin bin = 4'bx; end endcase for( j=0; j<4; j=j+1) begin if ((index*4)+j < C_DOUT_WIDTH) begin hexstr_conv[(index*4)+j] = bin[j]; end end index = index + 1; def_data = def_data >> 8; end end endfunction /************************************************************************* * Initialize Signals for clean power-on simulation *************************************************************************/ initial begin num_wr_bits = 0; num_rd_bits = 0; next_num_wr_bits = 0; next_num_rd_bits = 0; rd_ptr = C_RD_DEPTH - 1; wr_ptr = C_WR_DEPTH - 1; wr_pntr = 0; rd_pntr = 0; rd_ptr_wrclk = rd_ptr; wr_ptr_rdclk = wr_ptr; dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); ideal_dout = dout_reset_val; err_type = 0; err_type_d1 = 0; err_type_both = 0; ideal_dout_d1 = dout_reset_val; ideal_wr_ack = 1'b0; ideal_valid = 1'b0; valid_d1 = 1'b0; valid_d2 = 1'b0; ideal_overflow = C_OVERFLOW_LOW; ideal_underflow = C_UNDERFLOW_LOW; ideal_wr_count = 0; ideal_rd_count = 0; ideal_prog_full = 1'b0; ideal_prog_empty = 1'b1; end /************************************************************************* * Connect the module inputs and outputs to the internal signals of the * behavioral model. *************************************************************************/ //Inputs /* wire [C_DIN_WIDTH-1:0] DIN; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; wire RD_CLK; wire RD_EN; wire RST; wire WR_CLK; wire WR_EN; */ //*************************************************************************** // Dout may change behavior based on latency //*************************************************************************** assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )? ideal_dout_d1: ideal_dout; assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; //*************************************************************************** // Assign SBITERR and DBITERR based on latency //*************************************************************************** assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && (C_PRELOAD_LATENCY == 2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ? err_type_d1[0]: err_type[0]; assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? err_type_d1[1]: err_type[1]; //*************************************************************************** // Safety-ckt logic with embedded reg/fabric reg //*************************************************************************** generate if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; // if (C_HAS_VALID == 1) begin // assign valid_out = valid_d1; // end always@(posedge RD_CLK) begin rst_delayed_sft1 <= #`TCQ rd_rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) ram_rd_en_d1 <= #`TCQ 1'b0; else ram_rd_en_d1 <= #`TCQ ram_rd_en; end always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin if (rst_delayed_sft2 == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge RD_CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin if (ram_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout; err_type_d1[0] <= #`TCQ err_type[0]; err_type_d1[1] <= #`TCQ err_type[1]; end end end end endgenerate //*************************************************************************** // Safety-ckt logic with embedded reg + fabric reg //*************************************************************************** generate if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge RD_CLK) begin rst_delayed_sft1 <= #`TCQ rd_rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) ram_rd_en_d1 <= #`TCQ 1'b0; else begin ram_rd_en_d1 <= #`TCQ ram_rd_en; fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; end end always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin if (rst_delayed_sft2 == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge RD_CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end end else begin if (ram_rd_en_d1) begin ideal_dout_both <= #`TCQ ideal_dout; err_type_both[0] <= #`TCQ err_type[0]; err_type_both[1] <= #`TCQ err_type[1]; end if (fab_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout_both; err_type_d1[0] <= #`TCQ err_type_both[0]; err_type_d1[1] <= #`TCQ err_type_both[1]; end end end end endgenerate //*************************************************************************** // Overflow may be active-low //*************************************************************************** generate if (C_HAS_OVERFLOW==1) begin : blockOF1 assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; end endgenerate assign PROG_EMPTY = ideal_prog_empty; assign PROG_FULL = ideal_prog_full; //*************************************************************************** // Valid may change behavior based on latency or active-low //*************************************************************************** generate if (C_HAS_VALID==1) begin : blockVL1 assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; assign valid_out1 = (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)? valid_d1: valid_i; assign valid_out2 = (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)? valid_d2: valid_i; assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1; assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; end endgenerate //*************************************************************************** // Underflow may change behavior based on latency or active-low //*************************************************************************** generate if (C_HAS_UNDERFLOW==1) begin : blockUF1 assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; end endgenerate //*************************************************************************** // Write acknowledge may be active low //*************************************************************************** generate if (C_HAS_WR_ACK==1) begin : blockWK1 assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; end endgenerate //*************************************************************************** // Generate RD_DATA_COUNT if Use Extra Logic option is selected //*************************************************************************** generate if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; wire [C_PNTR_WIDTH:0] diff_wr_rd; reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; always @* begin if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin adjusted_wr_pntr = wr_pntr; adjusted_rd_pntr = 0; adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin adjusted_rd_pntr = rd_pntr_wr; adjusted_wr_pntr = 0; adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; end else begin adjusted_wr_pntr = wr_pntr; adjusted_rd_pntr = rd_pntr_wr; end end // always @* assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; always @ (posedge wr_rst_i or posedge WR_CLK) begin if (wr_rst_i) wr_data_count_i <= 0; else wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; end // always @ (posedge WR_CLK or posedge WR_CLK) always @* begin if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; else wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; end // always @* end // wdc_fwft_ext endgenerate //*************************************************************************** // Generate RD_DATA_COUNT if Use Extra Logic option is selected //*************************************************************************** reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; always @* begin if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin adjusted_wr_pntr_rd = 0; adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; end else begin adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end end // always @* assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i) begin rdc_fwft_ext_as <= 0; end else begin if (!stage2_valid) rdc_fwft_ext_as <= #`TCQ 0; else if (!stage1_valid && stage2_valid) rdc_fwft_ext_as <= #`TCQ 1; else rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; end end // always @ (posedge WR_CLK or posedge WR_CLK) end // rdc_fwft_ext end endgenerate generate if (C_USE_EMBEDDED_REG == 3) begin if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; always @* begin if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin adjusted_wr_pntr_rd = 0; adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; end else begin adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end end // always @* assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1; // assign diff_rd_wr_1 = diff_rd_wr +2'h2; always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i) begin rdc_fwft_ext_as <= #`TCQ 0; end else begin //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1))) // rdc_fwft_ext_as <= 1'b0; //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) // rdc_fwft_ext_as <= 1'b1; //else rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ; end end end end endgenerate //*************************************************************************** // Assign the read data count value only if it is selected, // otherwise output zeros. //*************************************************************************** generate if (C_HAS_RD_DATA_COUNT == 1) begin : grdc assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; end endgenerate generate if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}}; end endgenerate //*************************************************************************** // Assign the write data count value only if it is selected, // otherwise output zeros //*************************************************************************** generate if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; end endgenerate generate if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}}; end endgenerate /************************************************************************** * Assorted registers for delayed versions of signals **************************************************************************/ //Capture delayed version of valid generate if (C_HAS_VALID==1) begin : blockVL2 always @(posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i == 1'b1) begin valid_d1 <= 1'b0; valid_d2 <= 1'b0; end else begin valid_d1 <= #`TCQ valid_i; valid_d2 <= #`TCQ valid_d1; end // if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin // valid_d2 <= #`TCQ valid_d1; // end end end endgenerate //Capture delayed version of dout /************************************************************************** *embedded/fabric reg with no safety ckt **************************************************************************/ generate if (C_USE_EMBEDDED_REG < 3) begin always @(posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge RD_CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout <= #`TCQ dout_reset_val; end // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) err_type_d1 <= #`TCQ 0; end else if (ram_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout; err_type_d1 <= #`TCQ err_type; end end end endgenerate /************************************************************************** *embedded + fabric reg with no safety ckt **************************************************************************/ generate if (C_USE_EMBEDDED_REG == 3) begin always @(posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge RD_CLK) ideal_dout <= #`TCQ dout_reset_val; ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end end else begin if (ram_rd_en_d1) begin ideal_dout_both <= #`TCQ ideal_dout; err_type_both <= #`TCQ err_type; end if (fab_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout_both; err_type_d1 <= #`TCQ err_type_both; end end end end endgenerate /************************************************************************** * Overflow and Underflow Flag calculation * (handled separately because they don't support rst) **************************************************************************/ generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw always @(posedge WR_CLK) begin ideal_overflow <= #`TCQ WR_EN & FULL; end end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw always @(posedge WR_CLK) begin //ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i); ideal_overflow <= #`TCQ WR_EN & (FULL ); end end endgenerate generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw always @(posedge RD_CLK) begin ideal_underflow <= #`TCQ EMPTY & RD_EN; end end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw always @(posedge RD_CLK) begin ideal_underflow <= #`TCQ (EMPTY) & RD_EN; //ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN; end end endgenerate /************************************************************************** * Write/Read Pointer Synchronization **************************************************************************/ localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1; wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B]; wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B]; genvar gss; generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst fifo_generator_v13_1_3_sync_stage #( .C_WIDTH (C_WR_PNTR_WIDTH) ) rd_stg_inst ( .RST (rd_rst_i), .CLK (RD_CLK), .DIN (wr_pntr_sync_stgs[gss-1]), .DOUT (wr_pntr_sync_stgs[gss]) ); fifo_generator_v13_1_3_sync_stage #( .C_WIDTH (C_RD_PNTR_WIDTH) ) wr_stg_inst ( .RST (wr_rst_i), .CLK (WR_CLK), .DIN (rd_pntr_sync_stgs[gss-1]), .DOUT (rd_pntr_sync_stgs[gss]) ); end endgenerate // Sync_stage_inst assign wr_pntr_sync_stgs[0] = wr_pntr_rd1; assign rd_pntr_sync_stgs[0] = rd_pntr_wr1; always@* begin wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B]; rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B]; end /************************************************************************** * Write Domain Logic **************************************************************************/ reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0) wr_pntr <= 0; else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1) wr_pntr <= #`TCQ 0; end always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w /****** Reset fifo (case 1)***************************************/ if (wr_rst_i == 1'b1) begin num_wr_bits <= 0; next_num_wr_bits = 0; wr_ptr <= C_WR_DEPTH - 1; rd_ptr_wrclk <= C_RD_DEPTH - 1; ideal_wr_ack <= 0; ideal_wr_count <= 0; tmp_wr_listsize = 0; rd_ptr_wrclk_next <= 0; wr_pntr_rd1 <= 0; end else begin //wr_rst_i==0 wr_pntr_rd1 <= #`TCQ wr_pntr; //Determine the current number of words in the FIFO tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : num_wr_bits/C_DIN_WIDTH; rd_ptr_wrclk_next = rd_ptr; if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin next_num_wr_bits = num_wr_bits - C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH - rd_ptr_wrclk_next); end else begin next_num_wr_bits = num_wr_bits - C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); end //If this is a write, handle the write by adding the value // to the linked list, and updating all outputs appropriately if (WR_EN == 1'b1) begin if (FULL == 1'b1) begin //If the FIFO is full, do NOT perform the write, // update flags accordingly if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) begin //write unsuccessful - do not change contents //Do not acknowledge the write ideal_wr_ack <= #`TCQ 0; //Reminder that FIFO is still full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is one from full, but reporting full end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == C_FIFO_WR_DEPTH-1) begin //No change to FIFO //Write not successful ideal_wr_ack <= #`TCQ 0; //With DEPTH-1 words in the FIFO, it is almost_full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is completely empty, but it is // reporting FULL for some reason (like reset) end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= C_FIFO_WR_DEPTH-2) begin //No change to FIFO //Write not successful ideal_wr_ack <= #`TCQ 0; //FIFO is really not close to full, so change flag status. ideal_wr_count <= #`TCQ num_write_words_sized_i; end //(tmp_wr_listsize == 0) end else begin //If the FIFO is full, do NOT perform the write, // update flags accordingly if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) begin //write unsuccessful - do not change contents //Do not acknowledge the write ideal_wr_ack <= #`TCQ 0; //Reminder that FIFO is still full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is one from full end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == C_FIFO_WR_DEPTH-1) begin //Add value on DIN port to FIFO write_fifo; next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; //Write successful, so issue acknowledge // and no error ideal_wr_ack <= #`TCQ 1; //This write is CAUSING the FIFO to go full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is 2 from full end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == C_FIFO_WR_DEPTH-2) begin //Add value on DIN port to FIFO write_fifo; next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; //Write successful, so issue acknowledge // and no error ideal_wr_ack <= #`TCQ 1; //Still 2 from full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is not close to being full end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < C_FIFO_WR_DEPTH-2) begin //Add value on DIN port to FIFO write_fifo; next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; //Write successful, so issue acknowledge // and no error ideal_wr_ack <= #`TCQ 1; //Not even close to full. ideal_wr_count <= num_write_words_sized_i; end end end else begin //(WR_EN == 1'b1) //If user did not attempt a write, then do not // give ack or err ideal_wr_ack <= #`TCQ 0; ideal_wr_count <= #`TCQ num_write_words_sized_i; end num_wr_bits <= #`TCQ next_num_wr_bits; rd_ptr_wrclk <= #`TCQ rd_ptr; end //wr_rst_i==0 end // gen_fifo_w /*************************************************************************** * Programmable FULL flags ***************************************************************************/ wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val; wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val; generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC; assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC; end else begin // STD assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL; assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL; end endgenerate always @(posedge WR_CLK or posedge wr_rst_i) begin if (wr_rst_i == 1'b1) begin diff_pntr <= 0; end else begin if (ram_wr_en) diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1); else if (!ram_wr_en) diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr); end end always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf if (RST_FULL_FF == 1'b1) begin ideal_prog_full <= C_FULL_FLAGS_RST_VAL; end else begin if (RST_FULL_GEN) ideal_prog_full <= #`TCQ 0; //Single Programmable Full Constant Threshold else if (C_PROG_FULL_TYPE == 1) begin if (FULL == 0) begin if (diff_pntr >= pf_thr_assert_val) ideal_prog_full <= #`TCQ 1; else ideal_prog_full <= #`TCQ 0; end else ideal_prog_full <= #`TCQ ideal_prog_full; //Two Programmable Full Constant Thresholds end else if (C_PROG_FULL_TYPE == 2) begin if (FULL == 0) begin if (diff_pntr >= pf_thr_assert_val) ideal_prog_full <= #`TCQ 1; else if (diff_pntr < pf_thr_negate_val) ideal_prog_full <= #`TCQ 0; else ideal_prog_full <= #`TCQ ideal_prog_full; end else ideal_prog_full <= #`TCQ ideal_prog_full; //Single Programmable Full Threshold Input end else if (C_PROG_FULL_TYPE == 3) begin if (FULL == 0) begin if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC)) ideal_prog_full <= #`TCQ 1; else ideal_prog_full <= #`TCQ 0; end else begin // STD if (diff_pntr >= PROG_FULL_THRESH) ideal_prog_full <= #`TCQ 1; else ideal_prog_full <= #`TCQ 0; end end else ideal_prog_full <= #`TCQ ideal_prog_full; //Two Programmable Full Threshold Inputs end else if (C_PROG_FULL_TYPE == 4) begin if (FULL == 0) begin if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC)) ideal_prog_full <= #`TCQ 1; else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC)) ideal_prog_full <= #`TCQ 0; else ideal_prog_full <= #`TCQ ideal_prog_full; end else begin // STD if (diff_pntr >= PROG_FULL_THRESH_ASSERT) ideal_prog_full <= #`TCQ 1; else if (diff_pntr < PROG_FULL_THRESH_NEGATE) ideal_prog_full <= #`TCQ 0; else ideal_prog_full <= #`TCQ ideal_prog_full; end end else ideal_prog_full <= #`TCQ ideal_prog_full; end // C_PROG_FULL_TYPE end //wr_rst_i==0 end // /************************************************************************** * Read Domain Logic **************************************************************************/ /********************************************************* * Programmable EMPTY flags *********************************************************/ //Determine the Assert and Negate thresholds for Programmable Empty wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val; wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val; reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0; always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe if (rd_rst_i) begin diff_pntr_rd <= 0; ideal_prog_empty <= 1'b1; end else begin if (ram_rd_en) diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1; else if (!ram_rd_en) diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr); else diff_pntr_rd <= #`TCQ diff_pntr_rd; if (C_PROG_EMPTY_TYPE == 1) begin if (EMPTY == 0) begin if (diff_pntr_rd <= pe_thr_assert_val) ideal_prog_empty <= #`TCQ 1; else ideal_prog_empty <= #`TCQ 0; end else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else if (C_PROG_EMPTY_TYPE == 2) begin if (EMPTY == 0) begin if (diff_pntr_rd <= pe_thr_assert_val) ideal_prog_empty <= #`TCQ 1; else if (diff_pntr_rd > pe_thr_negate_val) ideal_prog_empty <= #`TCQ 0; else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else if (C_PROG_EMPTY_TYPE == 3) begin if (EMPTY == 0) begin if (diff_pntr_rd <= pe_thr_assert_val) ideal_prog_empty <= #`TCQ 1; else ideal_prog_empty <= #`TCQ 0; end else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else if (C_PROG_EMPTY_TYPE == 4) begin if (EMPTY == 0) begin if (diff_pntr_rd <= pe_thr_assert_val) ideal_prog_empty <= #`TCQ 1; else if (diff_pntr_rd > pe_thr_negate_val) ideal_prog_empty <= #`TCQ 0; else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else ideal_prog_empty <= #`TCQ ideal_prog_empty; end //C_PROG_EMPTY_TYPE end end // gen_pe generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH; end endgenerate // single_pe_thr_input generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT; assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE; end endgenerate // multiple_pe_thr_input generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL; assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL; end endgenerate // single_multiple_pe_thr_const always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp if (rd_rst_i && C_EN_SAFETY_CKT == 0) rd_pntr <= 0; else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1) rd_pntr <= #`TCQ 0; end always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as /****** Reset fifo (case 1)***************************************/ if (rd_rst_i) begin num_rd_bits <= 0; next_num_rd_bits = 0; rd_ptr <= C_RD_DEPTH -1; rd_pntr_wr1 <= 0; wr_ptr_rdclk <= C_WR_DEPTH -1; // DRAM resets asynchronously if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) ideal_dout <= dout_reset_val; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type <= 0; err_type_d1 <= 0; err_type_both <= 0; end ideal_valid <= 1'b0; ideal_rd_count <= 0; end else begin //rd_rst_i==0 rd_pntr_wr1 <= #`TCQ rd_pntr; //Determine the current number of words in the FIFO tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : num_rd_bits/C_DOUT_WIDTH; wr_ptr_rdclk_next = wr_ptr; if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin next_num_rd_bits = num_rd_bits + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH - wr_ptr_rdclk_next); end else begin next_num_rd_bits = num_rd_bits + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); end /*****************************************************************/ // Read Operation - Read Latency 1 /*****************************************************************/ if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin ideal_valid <= #`TCQ 1'b0; if (ram_rd_en == 1'b1) begin if (EMPTY == 1'b1) begin //If the FIFO is completely empty, and is reporting empty if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Reminder that FIFO is still empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize <= 0) //If the FIFO is one from empty, but it is reporting empty else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Note that FIFO is no longer empty, but is almost empty (has one word left) ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 1) //If the FIFO is two from empty, and is reporting empty else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Fifo has two words, so is neither empty or almost empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 2) //If the FIFO is not close to empty, but is reporting that it is // Treat the FIFO as empty this time, but unset EMPTY flags. if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Note that the FIFO is No Longer Empty or Almost Empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) end // else: if(ideal_empty == 1'b1) else //if (ideal_empty == 1'b0) begin //If the FIFO is completely full, and we are successfully reading from it if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Not close to empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) //If the FIFO is not close to being empty else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Not close to empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) //If the FIFO is two from empty else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Fifo is not yet empty. It is going almost_empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 2) //If the FIFO is one from empty else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Note that FIFO is GOING empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 1) //If the FIFO is completely empty else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize <= 0) end // if (ideal_empty == 1'b0) end //(RD_EN == 1'b1) else //if (RD_EN == 1'b0) begin //If user did not attempt a read, do not give an ack or err ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ num_read_words_sized_i; end // else: !if(RD_EN == 1'b1) /*****************************************************************/ // Read Operation - Read Latency 0 /*****************************************************************/ end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin ideal_valid <= #`TCQ 1'b0; if (ram_rd_en == 1'b1) begin if (EMPTY == 1'b1) begin //If the FIFO is completely empty, and is reporting empty if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Reminder that FIFO is still empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is one from empty, but it is reporting empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Note that FIFO is no longer empty, but is almost empty (has one word left) ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is two from empty, and is reporting empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Fifo has two words, so is neither empty or almost empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is not close to empty, but is reporting that it is // Treat the FIFO as empty this time, but unset EMPTY flags. end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Note that the FIFO is No Longer Empty or Almost Empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) end else begin //If the FIFO is completely full, and we are successfully reading from it if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Not close to empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is not close to being empty end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Not close to empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is two from empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Fifo is not yet empty. It is going almost_empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is one from empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Note that FIFO is GOING empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is completely empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Reminder that FIFO is still empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize <= 0) end // if (ideal_empty == 1'b0) end else begin//(RD_EN == 1'b0) //If user did not attempt a read, do not give an ack or err ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ num_read_words_sized_i; end // else: !if(RD_EN == 1'b1) end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) num_rd_bits <= #`TCQ next_num_rd_bits; wr_ptr_rdclk <= #`TCQ wr_ptr; end //rd_rst_i==0 end //always gen_fifo_r_as endmodule // fifo_generator_v13_1_3_bhv_ver_as /******************************************************************************* * Declaration of Low Latency Asynchronous FIFO ******************************************************************************/ module fifo_generator_v13_1_3_beh_ver_ll_afifo /*************************************************************************** * Declare user parameters and their defaults ***************************************************************************/ #( parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_RD_DEPTH = 256, parameter C_RD_PNTR_WIDTH = 8, parameter C_USE_DOUT_RST = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_PNTR_WIDTH = 8, parameter C_FIFO_TYPE = 0 ) /*************************************************************************** * Declare Input and Output Ports ***************************************************************************/ ( input [C_DIN_WIDTH-1:0] DIN, input RD_CLK, input RD_EN, input WR_RST, input RD_RST, input WR_CLK, input WR_EN, output reg [C_DOUT_WIDTH-1:0] DOUT = 0, output reg EMPTY = 1'b1, output reg FULL = C_FULL_FLAGS_RST_VAL ); //----------------------------------------------------------------------------- // Low Latency Asynchronous FIFO //----------------------------------------------------------------------------- // Memory which will be used to simulate a FIFO reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; integer i; initial begin for (i = 0; i < C_WR_DEPTH; i = i + 1) memory[i] = 0; end reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0; wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0; reg ll_afifo_full = 1'b0; reg ll_afifo_empty = 1'b1; wire write_allow; wire read_allow; assign write_allow = WR_EN & ~ll_afifo_full; assign read_allow = RD_EN & ~ll_afifo_empty; //----------------------------------------------------------------------------- // Write Pointer Generation //----------------------------------------------------------------------------- always @(posedge WR_CLK or posedge WR_RST) begin if (WR_RST) wr_pntr_ll_afifo <= 0; else if (write_allow) wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1; end //----------------------------------------------------------------------------- // Read Pointer Generation //----------------------------------------------------------------------------- always @(posedge RD_CLK or posedge RD_RST) begin if (RD_RST) rd_pntr_ll_afifo_q <= 0; else rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo; end assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q; //----------------------------------------------------------------------------- // Fill the Memory //----------------------------------------------------------------------------- always @(posedge WR_CLK) begin if (write_allow) memory[wr_pntr_ll_afifo] <= #`TCQ DIN; end //----------------------------------------------------------------------------- // Generate DOUT //----------------------------------------------------------------------------- always @(posedge RD_CLK) begin DOUT <= #`TCQ memory[rd_pntr_ll_afifo]; end //----------------------------------------------------------------------------- // Generate EMPTY //----------------------------------------------------------------------------- always @(posedge RD_CLK or posedge RD_RST) begin if (RD_RST) ll_afifo_empty <= 1'b1; else ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1)))); end //----------------------------------------------------------------------------- // Generate FULL //----------------------------------------------------------------------------- always @(posedge WR_CLK or posedge WR_RST) begin if (WR_RST) ll_afifo_full <= 1'b1; else ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2)))); end always @* begin FULL <= ll_afifo_full; EMPTY <= ll_afifo_empty; end endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo /******************************************************************************* * Declaration of top-level module ******************************************************************************/ module fifo_generator_v13_1_3_bhv_ver_ss /************************************************************************** * Declare user parameters and their defaults *************************************************************************/ #( parameter C_FAMILY = "virtex7", parameter C_DATA_COUNT_WIDTH = 2, parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_ALMOST_EMPTY = 0, parameter C_HAS_ALMOST_FULL = 0, parameter C_HAS_DATA_COUNT = 0, parameter C_HAS_OVERFLOW = 0, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_RST = 0, parameter C_HAS_SRST = 0, parameter C_HAS_UNDERFLOW = 0, parameter C_HAS_VALID = 0, parameter C_HAS_WR_ACK = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_IMPLEMENTATION_TYPE = 0, parameter C_MEMORY_TYPE = 1, parameter C_OVERFLOW_LOW = 0, parameter C_PRELOAD_LATENCY = 1, parameter C_PRELOAD_REGS = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, parameter C_PROG_EMPTY_TYPE = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, parameter C_PROG_FULL_TYPE = 0, parameter C_RD_DATA_COUNT_WIDTH = 2, parameter C_RD_DEPTH = 256, parameter C_RD_PNTR_WIDTH = 8, parameter C_UNDERFLOW_LOW = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_USE_FWFT_DATA_COUNT = 0, parameter C_VALID_LOW = 0, parameter C_WR_ACK_LOW = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_PNTR_WIDTH = 8, parameter C_USE_ECC = 0, parameter C_ENABLE_RST_SYNC = 1, parameter C_ERROR_INJECTION_TYPE = 0, parameter C_FIFO_TYPE = 0 ) /************************************************************************** * Declare Input and Output Ports *************************************************************************/ ( //Inputs input SAFETY_CKT_WR_RST, input CLK, input [C_DIN_WIDTH-1:0] DIN, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, input RD_EN, input RD_EN_USER, input USER_EMPTY_FB, input RST, input RST_FULL_GEN, input RST_FULL_FF, input SRST, input WR_EN, input INJECTDBITERR, input INJECTSBITERR, input WR_RST_BUSY, input RD_RST_BUSY, //Outputs output ALMOST_EMPTY, output ALMOST_FULL, output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0, output [C_DOUT_WIDTH-1:0] DOUT, output EMPTY, output reg EMPTY_FB = 1'b1, output FULL, output OVERFLOW, output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, output PROG_EMPTY, output PROG_FULL, output VALID, output UNDERFLOW, output WR_ACK, output SBITERR, output DBITERR ); reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss; wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss; reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; /*************************************************************************** * Parameters used as constants **************************************************************************/ localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0; localparam C_DEPTH_RATIO_WR = (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; localparam C_DEPTH_RATIO_RD = (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC // -----------------|------------------|-----------------|--------------- // 1 | 8 | C_RD_PNTR_WIDTH | 2 // 1 | 4 | C_RD_PNTR_WIDTH | 2 // 1 | 2 | C_RD_PNTR_WIDTH | 2 // 1 | 1 | C_WR_PNTR_WIDTH | 2 // 2 | 1 | C_WR_PNTR_WIDTH | 4 // 4 | 1 | C_WR_PNTR_WIDTH | 8 // 8 | 1 | C_WR_PNTR_WIDTH | 16 localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR); localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); //localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR); localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; localparam [31:0] log2_reads_per_write = log2_val(reads_per_write); localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; localparam [31:0] log2_writes_per_read = log2_val(writes_per_read); //When RST is present, set FULL reset value to '1'. //If core has no RST, make sure FULL powers-on as '0'. //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. // Therefore, during SRST, all the FULL flags reset to 0. localparam C_HAS_FAST_FIFO = 0; localparam C_FIFO_WR_DEPTH = C_WR_DEPTH; localparam C_FIFO_RD_DEPTH = C_RD_DEPTH; // Local parameters used to determine whether to inject ECC error or not localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0; localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH; localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1; localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; /************************************************************************** * FIFO Contents Tracking and Data Count Calculations *************************************************************************/ // Memory which will be used to simulate a FIFO reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; reg [1:0] ecc_err[C_WR_DEPTH-1:0]; /************************************************************************** * Internal Registers and wires *************************************************************************/ //Temporary signals used for calculating the model's outputs. These //are only used in the assign statements immediately following wire, //parameter, and function declarations. wire underflow_i; wire valid_i; wire valid_out; reg [31:0] num_wr_bits; reg [31:0] num_rd_bits; reg [31:0] next_num_wr_bits; reg [31:0] next_num_rd_bits; //The write pointer - tracks write operations // (Works opposite to core: wr_ptr is a DOWN counter) reg [31:0] wr_ptr; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; reg wr_rst_d1 =0; //The read pointer - tracks read operations // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) reg [31:0] rd_ptr; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; wire ram_rd_en; wire empty_int; wire almost_empty_int; wire ram_wr_en; wire full_int; wire almost_full_int; reg ram_rd_en_reg = 1'b0; reg ram_rd_en_d1 = 1'b0; reg fab_rd_en_d1 = 1'b0; wire srst_rrst_busy; //Ideal FIFO signals. These are the raw output of the behavioral model, //which behaves like an ideal FIFO. reg [1:0] err_type = 0; reg [1:0] err_type_d1 = 0; reg [1:0] err_type_both = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0; wire [C_DOUT_WIDTH-1:0] ideal_dout_out; wire fwft_enabled; reg ideal_wr_ack = 0; reg ideal_valid = 0; reg ideal_overflow = C_OVERFLOW_LOW; reg ideal_underflow = C_UNDERFLOW_LOW; reg full_i = C_FULL_FLAGS_RST_VAL; reg full_i_temp = 0; reg empty_i = 1; reg almost_full_i = 0; reg almost_empty_i = 1; reg prog_full_i = 0; reg prog_empty_i = 1; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0; reg write_allow_q = 0; reg read_allow_q = 0; reg valid_d1 = 0; reg valid_both = 0; reg valid_d2 = 0; wire rst_i; wire srst_i; //user specified value for reseting the size of the fifo reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; reg [31:0] wr_ptr_rdclk; reg [31:0] wr_ptr_rdclk_next; reg [31:0] rd_ptr_wrclk; reg [31:0] rd_ptr_wrclk_next; /**************************************************************************** * Function Declarations ***************************************************************************/ /**************************************************************************** * hexstr_conv * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) ***************************************************************************/ function [C_DOUT_WIDTH-1:0] hexstr_conv; input [(C_DOUT_WIDTH*8)-1:0] def_data; integer index,i,j; reg [3:0] bin; begin index = 0; hexstr_conv = 'b0; for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin case (def_data[7:0]) 8'b00000000 : begin bin = 4'b0000; i = -1; end 8'b00110000 : bin = 4'b0000; 8'b00110001 : bin = 4'b0001; 8'b00110010 : bin = 4'b0010; 8'b00110011 : bin = 4'b0011; 8'b00110100 : bin = 4'b0100; 8'b00110101 : bin = 4'b0101; 8'b00110110 : bin = 4'b0110; 8'b00110111 : bin = 4'b0111; 8'b00111000 : bin = 4'b1000; 8'b00111001 : bin = 4'b1001; 8'b01000001 : bin = 4'b1010; 8'b01000010 : bin = 4'b1011; 8'b01000011 : bin = 4'b1100; 8'b01000100 : bin = 4'b1101; 8'b01000101 : bin = 4'b1110; 8'b01000110 : bin = 4'b1111; 8'b01100001 : bin = 4'b1010; 8'b01100010 : bin = 4'b1011; 8'b01100011 : bin = 4'b1100; 8'b01100100 : bin = 4'b1101; 8'b01100101 : bin = 4'b1110; 8'b01100110 : bin = 4'b1111; default : begin bin = 4'bx; end endcase for( j=0; j<4; j=j+1) begin if ((index*4)+j < C_DOUT_WIDTH) begin hexstr_conv[(index*4)+j] = bin[j]; end end index = index + 1; def_data = def_data >> 8; end end endfunction /************************************************************************** * log2_val * Returns the 'log2' value for the input value for the supported ratios ***************************************************************************/ function [31:0] log2_val; input [31:0] binary_val; begin if (binary_val == 8) begin log2_val = 3; end else if (binary_val == 4) begin log2_val = 2; end else begin log2_val = 1; end end endfunction reg ideal_prog_full = 0; reg ideal_prog_empty = 1; reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; //Assorted reg values for delayed versions of signals //reg valid_d1 = 0; //user specified value for reseting the size of the fifo //reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; //temporary registers for WR_RESPONSE_LATENCY feature integer tmp_wr_listsize; integer tmp_rd_listsize; //Signal for registered version of prog full and empty //Threshold values for Programmable Flags integer prog_empty_actual_thresh_assert; integer prog_empty_actual_thresh_negate; integer prog_full_actual_thresh_assert; integer prog_full_actual_thresh_negate; /************************************************************************** * write_fifo * This task writes a word to the FIFO memory and updates the * write pointer. * FIFO size is relative to write domain. ***************************************************************************/ task write_fifo; begin memory[wr_ptr] <= DIN; wr_pntr <= #`TCQ wr_pntr + 1; // Store the type of error injection (double/single) on write case (C_ERROR_INJECTION_TYPE) 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; default: ecc_err[wr_ptr] <= 0; endcase // (Works opposite to core: wr_ptr is a DOWN counter) if (wr_ptr == 0) begin wr_ptr <= C_WR_DEPTH - 1; end else begin wr_ptr <= wr_ptr - 1; end end endtask // write_fifo /************************************************************************** * read_fifo * This task reads a word from the FIFO memory and updates the read * pointer. It's output is the ideal_dout bus. * FIFO size is relative to write domain. ***************************************************************************/ task read_fifo; integer i; reg [C_DOUT_WIDTH-1:0] tmp_dout; reg [C_DIN_WIDTH-1:0] memory_read; reg [31:0] tmp_rd_ptr; reg [31:0] rd_ptr_high; reg [31:0] rd_ptr_low; reg [1:0] tmp_ecc_err; begin rd_pntr <= #`TCQ rd_pntr + 1; // output is wider than input if (reads_per_write == 0) begin tmp_dout = 0; tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); for (i = writes_per_read - 1; i >= 0; i = i - 1) begin tmp_dout = tmp_dout << C_DIN_WIDTH; tmp_dout = tmp_dout | memory[tmp_rd_ptr]; // (Works opposite to core: rd_ptr is a DOWN counter) if (tmp_rd_ptr == 0) begin tmp_rd_ptr = C_WR_DEPTH - 1; end else begin tmp_rd_ptr = tmp_rd_ptr - 1; end end // output is symmetric end else if (reads_per_write == 1) begin tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; // Retreive the error injection type. Based on the error injection type // corrupt the output data. tmp_ecc_err = ecc_err[rd_ptr]; if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error if (C_DOUT_WIDTH == 1) begin $display("FAILURE : Data width must be >= 2 for double bit error injection."); $finish; end else if (C_DOUT_WIDTH == 2) tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; else tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; end else begin tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; end err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; end else begin err_type <= 0; end // input is wider than output end else begin rd_ptr_high = rd_ptr >> log2_reads_per_write; rd_ptr_low = rd_ptr & (reads_per_write - 1); memory_read = memory[rd_ptr_high]; tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); end ideal_dout <= tmp_dout; // (Works opposite to core: rd_ptr is a DOWN counter) if (rd_ptr == 0) begin rd_ptr <= C_RD_DEPTH - 1; end else begin rd_ptr <= rd_ptr - 1; end end endtask /************************************************************************* * Initialize Signals for clean power-on simulation *************************************************************************/ initial begin num_wr_bits = 0; num_rd_bits = 0; next_num_wr_bits = 0; next_num_rd_bits = 0; rd_ptr = C_RD_DEPTH - 1; wr_ptr = C_WR_DEPTH - 1; wr_pntr = 0; rd_pntr = 0; rd_ptr_wrclk = rd_ptr; wr_ptr_rdclk = wr_ptr; dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); ideal_dout = dout_reset_val; err_type = 0; err_type_d1 = 0; err_type_both = 0; ideal_dout_d1 = dout_reset_val; ideal_dout_both = dout_reset_val; ideal_wr_ack = 1'b0; ideal_valid = 1'b0; valid_d1 = 1'b0; valid_both = 1'b0; ideal_overflow = C_OVERFLOW_LOW; ideal_underflow = C_UNDERFLOW_LOW; ideal_wr_count = 0; ideal_rd_count = 0; ideal_prog_full = 1'b0; ideal_prog_empty = 1'b1; end /************************************************************************* * Connect the module inputs and outputs to the internal signals of the * behavioral model. *************************************************************************/ //Inputs /* wire CLK; wire [C_DIN_WIDTH-1:0] DIN; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; wire RD_EN; wire RST; wire WR_EN; */ // Assign ALMOST_EPMTY generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae assign ALMOST_EMPTY = almost_empty_i; end else begin : gnae assign ALMOST_EMPTY = 0; end endgenerate // gae // Assign ALMOST_FULL generate if (C_HAS_ALMOST_FULL==1) begin : gaf assign ALMOST_FULL = almost_full_i; end else begin : gnaf assign ALMOST_FULL = 0; end endgenerate // gaf // Dout may change behavior based on latency localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? 1: 0; assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? 1: 0; assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? ideal_dout_d1: ideal_dout; assign DOUT = ideal_dout_out; // Assign SBITERR and DBITERR based on latency assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? err_type_d1[0]: err_type[0]; assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? err_type_d1[1]: err_type[1]; assign EMPTY = empty_i; assign FULL = full_i; //saftey_ckt with one register generate if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge CLK) begin rst_delayed_sft1 <= #`TCQ rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin ram_rd_en_d1 <= #`TCQ 1'b0; valid_d1 <= #`TCQ 1'b0; end else begin ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i)); valid_d1 <= #`TCQ valid_i; end end always@(posedge rst_delayed_sft2 or posedge CLK) begin if (rst_delayed_sft2 == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else if (srst_rrst_busy == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end end else if (ram_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout; err_type_d1[0] <= #`TCQ err_type[0]; err_type_d1[1] <= #`TCQ err_type[1]; end end end //if endgenerate //safety ckt with both registers generate if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge CLK) begin rst_delayed_sft1 <= #`TCQ rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin ram_rd_en_d1 <= #`TCQ 1'b0; valid_d1 <= #`TCQ 1'b0; end else begin ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i)); fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; valid_both <= #`TCQ valid_i; valid_d1 <= #`TCQ valid_both; end end always@(posedge rst_delayed_sft2 or posedge CLK) begin if (rst_delayed_sft2 == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else if (srst_rrst_busy == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin if (ram_rd_en_d1) begin ideal_dout_both <= #`TCQ ideal_dout; err_type_both[0] <= #`TCQ err_type[0]; err_type_both[1] <= #`TCQ err_type[1]; end if (fab_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout_both; err_type_d1[0] <= #`TCQ err_type_both[0]; err_type_d1[1] <= #`TCQ err_type_both[1]; end end end end //if endgenerate //Overflow may be active-low generate if (C_HAS_OVERFLOW==1) begin : gof assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; end else begin : gnof assign OVERFLOW = 0; end endgenerate // gof assign PROG_EMPTY = prog_empty_i; assign PROG_FULL = prog_full_i; //Valid may change behavior based on latency or active-low generate if (C_HAS_VALID==1) begin : gvalid assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid; assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ? valid_d1 : valid_i; assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; end else begin : gnvalid assign VALID = 0; end endgenerate // gvalid //Trim data count differently depending on set widths generate if (C_HAS_DATA_COUNT == 1) begin : gdc always @* begin diff_count <= wr_pntr - rd_pntr; if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count; DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; end else begin DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; end end // end else begin : gndc // always @* DATA_COUNT <= 0; end endgenerate // gdc //Underflow may change behavior based on latency or active-low generate if (C_HAS_UNDERFLOW==1) begin : guf assign underflow_i = ideal_underflow; assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; end else begin : gnuf assign UNDERFLOW = 0; end endgenerate // guf //Write acknowledge may be active low generate if (C_HAS_WR_ACK==1) begin : gwr_ack assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; end else begin : gnwr_ack assign WR_ACK = 0; end endgenerate // gwr_ack /***************************************************************************** * Internal reset logic ****************************************************************************/ assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0; assign rst_i = C_HAS_RST ? RST : 0; assign srst_wrst_busy = srst_i; assign srst_rrst_busy = srst_i; /************************************************************************** * Assorted registers for delayed versions of signals **************************************************************************/ //Capture delayed version of valid generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20 always @(posedge CLK or posedge rst_i) begin if (rst_i == 1'b1) begin valid_d1 <= 1'b0; end else begin if (srst_rrst_busy) begin valid_d1 <= #`TCQ 1'b0; end else begin valid_d1 <= #`TCQ valid_i; end end end // always @ (posedge CLK or posedge rst_i) end endgenerate // blockVL20 generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin always @(posedge CLK or posedge rst_i) begin if (rst_i == 1'b1) begin valid_d1 <= 1'b0; valid_both <= 1'b0; end else begin if (srst_rrst_busy) begin valid_d1 <= #`TCQ 1'b0; valid_both <= #`TCQ 1'b0; end else begin valid_both <= #`TCQ valid_i; valid_d1 <= #`TCQ valid_both; end end end // always @ (posedge CLK or posedge rst_i) end endgenerate // blockVL20 // Determine which stage in FWFT registers are valid reg stage1_valid = 0; reg stage2_valid = 0; generate if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc always @ (posedge CLK or posedge rst_i) begin if (rst_i) begin stage1_valid <= #`TCQ 0; stage2_valid <= #`TCQ 0; end else begin if (!stage1_valid && !stage2_valid) begin if (!EMPTY) stage1_valid <= #`TCQ 1'b1; else stage1_valid <= #`TCQ 1'b0; end else if (stage1_valid && !stage2_valid) begin if (EMPTY) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end end else if (!stage1_valid && stage2_valid) begin if (EMPTY && RD_EN) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b0; end else if (!EMPTY && RD_EN) begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b0; end else if (!EMPTY && !RD_EN) begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end end else if (stage1_valid && stage2_valid) begin if (EMPTY && RD_EN) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end end else begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b0; end end // rd_rst_i end // always end endgenerate //*************************************************************************** // Assign the read data count value only if it is selected, // otherwise output zeros. //*************************************************************************** generate if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; end endgenerate generate if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}}; end endgenerate //*************************************************************************** // Assign the write data count value only if it is selected, // otherwise output zeros //*************************************************************************** generate if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ; end endgenerate generate if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}}; end endgenerate //reg ram_rd_en_d1 = 1'b0; //Capture delayed version of dout generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin always @(posedge CLK or posedge rst_i) begin if (rst_i == 1'b1) begin // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end // DRAM and SRAM reset asynchronously if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end ram_rd_en_d1 <= #`TCQ 1'b0; if (C_USE_DOUT_RST == 1) begin @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY; if (srst_rrst_busy) begin ram_rd_en_d1 <= #`TCQ 1'b0; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end if (C_USE_DOUT_RST == 1) begin // @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin if (ram_rd_en_d1 ) begin ideal_dout_d1 <= #`TCQ ideal_dout; err_type_d1 <= #`TCQ err_type; end end end end // always end endgenerate //no safety ckt with both registers generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin always @(posedge CLK or posedge rst_i) begin if (rst_i == 1'b1) begin ram_rd_en_d1 <= #`TCQ 1'b0; fab_rd_en_d1 <= #`TCQ 1'b0; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end // DRAM and SRAM reset asynchronously if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end if (C_USE_DOUT_RST == 1) begin @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end end else begin if (srst_rrst_busy) begin ram_rd_en_d1 <= #`TCQ 1'b0; fab_rd_en_d1 <= #`TCQ 1'b0; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end if (C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY; fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1); if (ram_rd_en_d1 ) begin ideal_dout_both <= #`TCQ ideal_dout; err_type_both <= #`TCQ err_type; end if (fab_rd_en_d1 ) begin ideal_dout_d1 <= #`TCQ ideal_dout_both; err_type_d1 <= #`TCQ err_type_both; end end end end // always end endgenerate /************************************************************************** * Overflow and Underflow Flag calculation * (handled separately because they don't support rst) **************************************************************************/ generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw always @(posedge CLK) begin ideal_overflow <= #`TCQ WR_EN & full_i; end end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw always @(posedge CLK) begin //ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i); ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i); end end endgenerate // blockOF20 generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw always @(posedge CLK) begin ideal_underflow <= #`TCQ empty_i & RD_EN; end end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw always @(posedge CLK) begin //ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN; ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN; end end endgenerate // blockUF20 /************************** * Read Data Count *************************/ reg [31:0] num_read_words_dc; reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; always @(num_rd_bits) begin if (C_USE_FWFT_DATA_COUNT) begin //If using extra logic for FWFT Data Counts, // then scale FIFO contents to read domain, // and add two read words for FWFT stages //This value is only a temporary value and not used in the code. num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); //Trim the read words for use with RD_DATA_COUNT num_read_words_sized_i = num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; end else begin //If not using extra logic for FWFT Data Counts, // then scale FIFO contents to read domain. //This value is only a temporary value and not used in the code. num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; //Trim the read words for use with RD_DATA_COUNT num_read_words_sized_i = num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; end //if (C_USE_FWFT_DATA_COUNT) end //always /************************** * Write Data Count *************************/ reg [31:0] num_write_words_dc; reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; always @(num_wr_bits) begin if (C_USE_FWFT_DATA_COUNT) begin //Calculate the Data Count value for the number of write words, // when using First-Word Fall-Through with extra logic for Data // Counts. This takes into consideration the number of words that // are expected to be stored in the FWFT register stages (it always // assumes they are filled). //This value is scaled to the Write Domain. //The expression (((A-1)/B))+1 divides A/B, but takes the // ceiling of the result. //When num_wr_bits==0, set the result manually to prevent // division errors. //EXTRA_WORDS_DC is the number of words added to write_words // due to FWFT. //This value is only a temporary value and not used in the code. num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; //Trim the write words for use with WR_DATA_COUNT num_write_words_sized_i = num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; end else begin //Calculate the Data Count value for the number of write words, when NOT // using First-Word Fall-Through with extra logic for Data Counts. This // calculates only the number of words in the internal FIFO. //The expression (((A-1)/B))+1 divides A/B, but takes the // ceiling of the result. //This value is scaled to the Write Domain. //When num_wr_bits==0, set the result manually to prevent // division errors. //This value is only a temporary value and not used in the code. num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; //Trim the read words for use with RD_DATA_COUNT num_write_words_sized_i = num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; end //if (C_USE_FWFT_DATA_COUNT) end //always /************************************************************************* * Write and Read Logic ************************************************************************/ wire write_allow; wire read_allow; wire read_allow_dc; wire write_only; wire read_only; //wire write_only_q; reg write_only_q; //wire read_only_q; reg read_only_q; reg full_reg; reg rst_full_ff_reg1; reg rst_full_ff_reg2; wire ram_full_comb; wire carry; assign write_allow = WR_EN & ~full_i; assign read_allow = RD_EN & ~empty_i; assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB; //assign write_only = write_allow & ~read_allow; //assign write_only_q = write_allow_q; //assign read_only = read_allow & ~write_allow; //assign read_only_q = read_allow_q ; wire [C_WR_PNTR_WIDTH-1:0] diff_pntr; wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe; reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0; reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0; reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0; wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ; wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym; reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0; reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0; wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max; wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max; assign diff_pntr_pe_max = DIFF_MAX_RD; assign diff_pntr_max = DIFF_MAX_WR; generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym assign write_only = write_allow & ~read_allow; assign read_only = read_allow & ~write_allow; end endgenerate generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow; assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])); end endgenerate generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow; end endgenerate //----------------------------------------------------------------------------- // Write and Read pointer generation //----------------------------------------------------------------------------- always @(posedge CLK or posedge rst_i) begin if (rst_i && C_EN_SAFETY_CKT == 0) begin wr_pntr <= 0; rd_pntr <= 0; end else begin if (srst_i) begin wr_pntr <= #`TCQ 0; rd_pntr <= #`TCQ 0; end else begin if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1; if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1; end end end generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout always @(posedge CLK) begin if (write_allow) begin if (ENABLE_ERR_INJECTION == 1) memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN}; else memory[wr_pntr] <= #`TCQ DIN; end end reg [C_DATA_WIDTH-1:0] dout_tmp_q; reg [C_DATA_WIDTH-1:0] dout_tmp = 0; reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0; always @(posedge CLK) begin dout_tmp_q <= #`TCQ ideal_dout; end always @* begin if (read_allow) ideal_dout <= memory[rd_pntr]; else ideal_dout <= dout_tmp_q; end end endgenerate // gll_dm_dout /************************************************************************** * Write Domain Logic **************************************************************************/ assign ram_rd_en = RD_EN & !EMPTY; //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; generate if (C_FIFO_TYPE != 2) begin : gnll_din always @(posedge CLK or posedge rst_i) begin : gen_fifo_w /****** Reset fifo (case 1)***************************************/ if (rst_i == 1'b1) begin num_wr_bits <= #`TCQ 0; next_num_wr_bits = #`TCQ 0; wr_ptr <= #`TCQ C_WR_DEPTH - 1; rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; ideal_wr_ack <= #`TCQ 0; ideal_wr_count <= #`TCQ 0; tmp_wr_listsize = #`TCQ 0; rd_ptr_wrclk_next <= #`TCQ 0; wr_pntr <= #`TCQ 0; wr_pntr_rd1 <= #`TCQ 0; end else begin //rst_i==0 if (srst_wrst_busy) begin num_wr_bits <= #`TCQ 0; next_num_wr_bits = #`TCQ 0; wr_ptr <= #`TCQ C_WR_DEPTH - 1; rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; ideal_wr_ack <= #`TCQ 0; ideal_wr_count <= #`TCQ 0; tmp_wr_listsize = #`TCQ 0; rd_ptr_wrclk_next <= #`TCQ 0; wr_pntr <= #`TCQ 0; wr_pntr_rd1 <= #`TCQ 0; end else begin//srst_i=0 wr_pntr_rd1 <= #`TCQ wr_pntr; //Determine the current number of words in the FIFO tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : num_wr_bits/C_DIN_WIDTH; rd_ptr_wrclk_next = rd_ptr; if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin next_num_wr_bits = num_wr_bits - C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH - rd_ptr_wrclk_next); end else begin next_num_wr_bits = num_wr_bits - C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); end if (WR_EN == 1'b1) begin if (FULL == 1'b1) begin ideal_wr_ack <= #`TCQ 0; //Reminder that FIFO is still full ideal_wr_count <= #`TCQ num_write_words_sized_i; end else begin write_fifo; next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; //Write successful, so issue acknowledge // and no error ideal_wr_ack <= #`TCQ 1; //Not even close to full. ideal_wr_count <= num_write_words_sized_i; //end end end else begin //(WR_EN == 1'b1) //If user did not attempt a write, then do not // give ack or err ideal_wr_ack <= #`TCQ 0; ideal_wr_count <= #`TCQ num_write_words_sized_i; end num_wr_bits <= #`TCQ next_num_wr_bits; rd_ptr_wrclk <= #`TCQ rd_ptr; end //srst_i==0 end //wr_rst_i==0 end // gen_fifo_w end endgenerate generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout always @(posedge CLK) begin if (rst_i || srst_rrst_busy) begin if (C_USE_DOUT_RST == 1) begin ideal_dout <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end end end end endgenerate generate if (C_FIFO_TYPE != 2) begin : gnll_dout always @(posedge CLK or posedge rst_i) begin : gen_fifo_r /****** Reset fifo (case 1)***************************************/ if (rst_i) begin num_rd_bits <= #`TCQ 0; next_num_rd_bits = #`TCQ 0; rd_ptr <= #`TCQ C_RD_DEPTH -1; rd_pntr <= #`TCQ 0; //rd_pntr_wr1 <= #`TCQ 0; wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; // DRAM resets asynchronously if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1) ideal_dout <= #`TCQ dout_reset_val; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type <= #`TCQ 0; err_type_d1 <= 0; err_type_both <= 0; end ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ 0; end else begin //rd_rst_i==0 if (srst_rrst_busy) begin num_rd_bits <= #`TCQ 0; next_num_rd_bits = #`TCQ 0; rd_ptr <= #`TCQ C_RD_DEPTH -1; rd_pntr <= #`TCQ 0; //rd_pntr_wr1 <= #`TCQ 0; wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; // DRAM resets synchronously if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1) ideal_dout <= #`TCQ dout_reset_val; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type <= #`TCQ 0; err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ 0; end //srst_i else begin //rd_pntr_wr1 <= #`TCQ rd_pntr; //Determine the current number of words in the FIFO tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : num_rd_bits/C_DOUT_WIDTH; wr_ptr_rdclk_next = wr_ptr; if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin next_num_rd_bits = num_rd_bits + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH - wr_ptr_rdclk_next); end else begin next_num_rd_bits = num_rd_bits + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); end if (RD_EN == 1'b1) begin if (EMPTY == 1'b1) begin ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ num_read_words_sized_i; end else begin read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 2) end num_rd_bits <= #`TCQ next_num_rd_bits; wr_ptr_rdclk <= #`TCQ wr_ptr; end //s_rst_i==0 end //rd_rst_i==0 end //always end endgenerate //----------------------------------------------------------------------------- // Generate diff_pntr for PROG_FULL generation // Generate diff_pntr_pe for PROG_EMPTY generation //----------------------------------------------------------------------------- generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow always @(posedge CLK ) begin if (rst_i) begin write_only_q <= 1'b0; read_only_q <= 1'b0; diff_pntr_reg1 <= 0; diff_pntr_pe_reg1 <= 0; diff_pntr_reg2 <= 0; diff_pntr_pe_reg2 <= 0; end else begin if (srst_i || srst_wrst_busy || srst_rrst_busy) begin if (srst_rrst_busy) begin read_only_q <= #`TCQ 1'b0; diff_pntr_pe_reg1 <= #`TCQ 0; diff_pntr_pe_reg2 <= #`TCQ 0; end if (srst_wrst_busy) begin write_only_q <= #`TCQ 1'b0; diff_pntr_reg1 <= #`TCQ 0; diff_pntr_reg2 <= #`TCQ 0; end end else begin write_only_q <= #`TCQ write_only; read_only_q <= #`TCQ read_only; diff_pntr_reg2 <= #`TCQ diff_pntr_reg1; diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1; // Add 1 to the difference pointer value when only write happens. if (write_only) diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1; else diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr; // Add 1 to the difference pointer value when write or both write & read or no write & read happen. if (read_only) diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1; else diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr; end end end assign diff_pntr_pe = diff_pntr_pe_reg1; assign diff_pntr = diff_pntr_reg1; end endgenerate // reg_write_allow generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1}; assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1}; always @(posedge CLK ) begin if (rst_i) begin diff_pntr_pe_asym <= 0; diff_pntr_reg1 <= 0; full_reg <= 0; rst_full_ff_reg1 <= 1; rst_full_ff_reg2 <= 1; diff_pntr_pe_reg1 <= 0; end else begin if (srst_i || srst_wrst_busy || srst_rrst_busy) begin if (srst_wrst_busy) diff_pntr_reg1 <= #`TCQ 0; if (srst_rrst_busy) full_reg <= #`TCQ 0; rst_full_ff_reg1 <= #`TCQ 1; rst_full_ff_reg2 <= #`TCQ 1; diff_pntr_pe_asym <= #`TCQ 0; diff_pntr_pe_reg1 <= #`TCQ 0; end else begin diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym; full_reg <= #`TCQ full_i; rst_full_ff_reg1 <= #`TCQ RST_FULL_FF; rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1; if (~full_i) begin diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr; end end end end assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1]))); assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1]; assign diff_pntr = diff_pntr_reg1; end endgenerate // reg_write_allow_asym //----------------------------------------------------------------------------- // Generate FULL flag //----------------------------------------------------------------------------- wire comp0; wire comp1; wire going_full; wire leaving_full; generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr; assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0; end endgenerate generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; end endgenerate assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1)); assign comp0 = (adj_rd_pntr_wr == wr_pntr); generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp assign going_full = (comp1 & write_allow & ~read_allow); assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN; end endgenerate // Write data width is bigger than read data width // Write depth is smaller than read depth // One write could be equal to 2 or 4 or 8 reads generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])))); assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN; end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp assign going_full = (comp1 & write_allow & ~read_allow); assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN; end endgenerate assign ram_full_comb = going_full | (~leaving_full & full_i); always @(posedge CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF) full_i <= C_FULL_FLAGS_RST_VAL; else if (srst_wrst_busy) full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else full_i <= #`TCQ ram_full_comb; end //----------------------------------------------------------------------------- // Generate EMPTY flag //----------------------------------------------------------------------------- wire ecomp0; wire ecomp1; wire going_empty; wire leaving_empty; wire ram_empty_comb; generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0; end endgenerate generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end endgenerate assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1)); assign ecomp0 = (adj_wr_pntr_rd == rd_pntr); generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp assign going_empty = (ecomp1 & ~write_allow & read_allow); assign leaving_empty = (ecomp0 & write_allow); end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])))); assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); end endgenerate generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp assign going_empty = (ecomp1 & ~write_allow & read_allow); assign leaving_empty =(ecomp0 & write_allow); end endgenerate assign ram_empty_comb = going_empty | (~leaving_empty & empty_i); always @(posedge CLK or posedge rst_i) begin if (rst_i) empty_i <= 1'b1; else if (srst_rrst_busy) empty_i <= #`TCQ 1'b1; else empty_i <= #`TCQ ram_empty_comb; end always @(posedge CLK or posedge rst_i) begin if (rst_i && C_EN_SAFETY_CKT == 0) begin EMPTY_FB <= 1'b1; end else begin if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT)) EMPTY_FB <= #`TCQ 1'b1; else EMPTY_FB <= #`TCQ ram_empty_comb; end end // always //----------------------------------------------------------------------------- // Generate Read and write data counts for asymmetic common clock //----------------------------------------------------------------------------- reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; wire [C_GRTR_PNTR_WIDTH :0] ratio; wire decr_by_one; wire incr_by_ratio; wire incr_by_one; wire decr_by_ratio; localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0; generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr assign ratio = C_DEPTH_RATIO_RD; assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow; assign incr_by_ratio = write_allow; always @(posedge CLK or posedge rst_i) begin if (rst_i) count_dc <= #`TCQ 0; else if (srst_wrst_busy) count_dc <= #`TCQ 0; else begin if (decr_by_one) begin if (!incr_by_ratio) count_dc <= #`TCQ count_dc - 1; else count_dc <= #`TCQ count_dc - 1 + ratio ; end else begin if (!incr_by_ratio) count_dc <= #`TCQ count_dc ; else count_dc <= #`TCQ count_dc + ratio ; end end end assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc; assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd assign ratio = C_DEPTH_RATIO_WR; assign incr_by_one = write_allow; assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow; always @(posedge CLK or posedge rst_i) begin if (rst_i) count_dc <= #`TCQ 0; else if (srst_wrst_busy) count_dc <= #`TCQ 0; else begin if (incr_by_one) begin if (!decr_by_ratio) count_dc <= #`TCQ count_dc + 1; else count_dc <= #`TCQ count_dc + 1 - ratio ; end else begin if (!decr_by_ratio) count_dc <= #`TCQ count_dc ; else count_dc <= #`TCQ count_dc - ratio ; end end end assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc; assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end endgenerate //----------------------------------------------------------------------------- // Generate WR_ACK flag //----------------------------------------------------------------------------- always @(posedge CLK or posedge rst_i) begin if (rst_i) ideal_wr_ack <= 1'b0; else if (srst_wrst_busy) ideal_wr_ack <= #`TCQ 1'b0; else if (WR_EN & ~full_i) ideal_wr_ack <= #`TCQ 1'b1; else ideal_wr_ack <= #`TCQ 1'b0; end //----------------------------------------------------------------------------- // Generate VALID flag //----------------------------------------------------------------------------- always @(posedge CLK or posedge rst_i) begin if (rst_i) ideal_valid <= 1'b0; else if (srst_rrst_busy) ideal_valid <= #`TCQ 1'b0; else if (RD_EN & ~empty_i) ideal_valid <= #`TCQ 1'b1; else ideal_valid <= #`TCQ 1'b0; end //----------------------------------------------------------------------------- // Generate ALMOST_FULL flag //----------------------------------------------------------------------------- //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss wire fcomp2; wire going_afull; wire leaving_afull; wire ram_afull_comb; assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2)); generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp assign going_afull = (fcomp2 & write_allow & ~read_allow); assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN; end endgenerate // Write data width is bigger than read data width // Write depth is smaller than read depth // One write could be equal to 2 or 4 or 8 reads generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])))); assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN; end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp assign going_afull = (fcomp2 & write_allow & ~read_allow); assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN; end endgenerate assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i); always @(posedge CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF) almost_full_i <= C_FULL_FLAGS_RST_VAL; else if (srst_wrst_busy) almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else almost_full_i <= #`TCQ ram_afull_comb; end // end endgenerate // gaf_ss //----------------------------------------------------------------------------- // Generate ALMOST_EMPTY flag //----------------------------------------------------------------------------- //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss wire ecomp2; wire going_aempty; wire leaving_aempty; wire ram_aempty_comb; assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2)); generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp assign going_aempty = (ecomp2 & ~write_allow & read_allow); assign leaving_aempty = (ecomp1 & write_allow & ~read_allow); end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])))); assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); end endgenerate generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp assign going_aempty = (ecomp2 & ~write_allow & read_allow); assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow); end endgenerate assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i); always @(posedge CLK or posedge rst_i) begin if (rst_i) almost_empty_i <= 1'b1; else if (srst_rrst_busy) almost_empty_i <= #`TCQ 1'b1; else almost_empty_i <= #`TCQ ram_aempty_comb; end // end endgenerate // gae_ss //----------------------------------------------------------------------------- // Generate PROG_FULL //----------------------------------------------------------------------------- localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT C_PROG_FULL_THRESH_ASSERT_VAL; // STD localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT C_PROG_FULL_THRESH_NEGATE_VAL; // STD //----------------------------------------------------------------------------- // Generate PROG_FULL for single programmable threshold constant //----------------------------------------------------------------------------- wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL; generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const always @(posedge CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF && C_HAS_RST) prog_full_i <= C_FULL_FLAGS_RST_VAL; else begin if (srst_wrst_busy) prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else if (IS_ASYMMETRY == 0) begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~RST_FULL_GEN ) begin if (diff_pntr>= C_PF_ASSERT_VAL ) prog_full_i <= #`TCQ 1'b1; else if ((diff_pntr) < C_PF_ASSERT_VAL ) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ 1'b0; end else prog_full_i <= #`TCQ prog_full_i; end end end end endgenerate // single_pf_const //----------------------------------------------------------------------------- // Generate PROG_FULL for multiple programmable threshold constants //----------------------------------------------------------------------------- generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const always @(posedge CLK or posedge RST_FULL_FF) begin //if (RST_FULL_FF) if (RST_FULL_FF && C_HAS_RST) prog_full_i <= C_FULL_FLAGS_RST_VAL; else begin if (srst_wrst_busy) prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else if (IS_ASYMMETRY == 0) begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~RST_FULL_GEN ) begin if (diff_pntr >= C_PF_ASSERT_VAL ) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr < C_PF_NEGATE_VAL) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else prog_full_i <= #`TCQ prog_full_i; end end end end endgenerate //multiple_pf_const //----------------------------------------------------------------------------- // Generate PROG_FULL for single programmable threshold input port //----------------------------------------------------------------------------- wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT PROG_FULL_THRESH; // STD generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input always @(posedge CLK or posedge RST_FULL_FF) begin//0 //if (RST_FULL_FF) if (RST_FULL_FF && C_HAS_RST) prog_full_i <= C_FULL_FLAGS_RST_VAL; else begin //1 if (srst_wrst_busy) prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else if (IS_ASYMMETRY == 0) begin//2 if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~almost_full_i) begin//3 if (diff_pntr > pf3_assert_val) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr == pf3_assert_val) begin//4 if (read_only_q) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ 1'b1; end else//4 prog_full_i <= #`TCQ 1'b0; end else//3 prog_full_i <= #`TCQ prog_full_i; end //2 else begin//5 if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~full_i ) begin//6 if (diff_pntr >= pf3_assert_val ) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr < pf3_assert_val) begin//7 prog_full_i <= #`TCQ 1'b0; end//7 end//6 else prog_full_i <= #`TCQ prog_full_i; end//5 end//1 end//0 end endgenerate //single_pf_input //----------------------------------------------------------------------------- // Generate PROG_FULL for multiple programmable threshold input ports //----------------------------------------------------------------------------- wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT PROG_FULL_THRESH_ASSERT; // STD wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT PROG_FULL_THRESH_NEGATE; // STD generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs always @(posedge CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF && C_HAS_RST) prog_full_i <= C_FULL_FLAGS_RST_VAL; else begin if (srst_wrst_busy) prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else if (IS_ASYMMETRY == 0) begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~almost_full_i) begin if (diff_pntr >= pf_assert_val) prog_full_i <= #`TCQ 1'b1; else if ((diff_pntr == pf_negate_val && read_only_q) || diff_pntr < pf_negate_val) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else prog_full_i <= #`TCQ prog_full_i; end else begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~full_i ) begin if (diff_pntr >= pf_assert_val ) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr < pf_negate_val) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else prog_full_i <= #`TCQ prog_full_i; end end end end endgenerate //multiple_pf_inputs //----------------------------------------------------------------------------- // Generate PROG_EMPTY //----------------------------------------------------------------------------- localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD //----------------------------------------------------------------------------- // Generate PROG_EMPTY for single programmable threshold constant //----------------------------------------------------------------------------- generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const always @(posedge CLK or posedge rst_i) begin //if (rst_i) if (rst_i && C_HAS_RST) prog_empty_i <= 1'b1; else begin if (srst_rrst_busy) prog_empty_i <= #`TCQ 1'b1; else if (IS_ASYMMETRY == 0) begin if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end else begin if (~rst_i ) begin if (diff_pntr_pe <= C_PE_ASSERT_VAL) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe > C_PE_ASSERT_VAL) prog_empty_i <= #`TCQ 1'b0; end else prog_empty_i <= #`TCQ prog_empty_i; end end end end endgenerate // single_pe_const //----------------------------------------------------------------------------- // Generate PROG_EMPTY for multiple programmable threshold constants //----------------------------------------------------------------------------- generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const always @(posedge CLK or posedge rst_i) begin //if (rst_i) if (rst_i && C_HAS_RST) prog_empty_i <= 1'b1; else begin if (srst_rrst_busy) prog_empty_i <= #`TCQ 1'b1; else if (IS_ASYMMETRY == 0) begin if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end else begin if (~rst_i ) begin if (diff_pntr_pe <= C_PE_ASSERT_VAL ) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe > C_PE_NEGATE_VAL) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end else prog_empty_i <= #`TCQ prog_empty_i; end end end end endgenerate //multiple_pe_const //----------------------------------------------------------------------------- // Generate PROG_EMPTY for single programmable threshold input port //----------------------------------------------------------------------------- wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ? (PROG_EMPTY_THRESH -2) : // FWFT PROG_EMPTY_THRESH; // STD generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input always @(posedge CLK or posedge rst_i) begin //if (rst_i) if (rst_i && C_HAS_RST) prog_empty_i <= 1'b1; else begin if (srst_rrst_busy) prog_empty_i <= #`TCQ 1'b1; else if (IS_ASYMMETRY == 0) begin if (~almost_full_i) begin if (diff_pntr_pe < pe3_assert_val) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe == pe3_assert_val) begin if (write_only_q) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ 1'b1; end else prog_empty_i <= #`TCQ 1'b0; end else prog_empty_i <= #`TCQ prog_empty_i; end else begin if (diff_pntr_pe <= pe3_assert_val ) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe > pe3_assert_val) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end end end end endgenerate // single_pe_input //----------------------------------------------------------------------------- // Generate PROG_EMPTY for multiple programmable threshold input ports //----------------------------------------------------------------------------- wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ? (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT PROG_EMPTY_THRESH_ASSERT; // STD wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ? (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT PROG_EMPTY_THRESH_NEGATE; // STD generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs always @(posedge CLK or posedge rst_i) begin //if (rst_i) if (rst_i && C_HAS_RST) prog_empty_i <= 1'b1; else begin if (srst_rrst_busy) prog_empty_i <= #`TCQ 1'b1; else if (IS_ASYMMETRY == 0) begin if (~almost_full_i) begin if (diff_pntr_pe <= pe4_assert_val) prog_empty_i <= #`TCQ 1'b1; else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || (diff_pntr_pe > pe4_negate_val)) begin prog_empty_i <= #`TCQ 1'b0; end else prog_empty_i <= #`TCQ prog_empty_i; end else prog_empty_i <= #`TCQ prog_empty_i; end else begin if (diff_pntr_pe <= pe4_assert_val ) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe > pe4_negate_val) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end end end end endgenerate // multiple_pe_inputs endmodule // fifo_generator_v13_1_3_bhv_ver_ss /************************************************************************** * First-Word Fall-Through module (preload 0) **************************************************************************/ module fifo_generator_v13_1_3_bhv_ver_preload0 #( parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_HAS_RST = 0, parameter C_ENABLE_RST_SYNC = 0, parameter C_HAS_SRST = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_ECC = 0, parameter C_USERVALID_LOW = 0, parameter C_USERUNDERFLOW_LOW = 0, parameter C_MEMORY_TYPE = 0, parameter C_FIFO_TYPE = 0 ) ( //Inputs input SAFETY_CKT_RD_RST, input RD_CLK, input RD_RST, input SRST, input WR_RST_BUSY, input RD_RST_BUSY, input RD_EN, input FIFOEMPTY, input [C_DOUT_WIDTH-1:0] FIFODATA, input FIFOSBITERR, input FIFODBITERR, //Outputs output reg [C_DOUT_WIDTH-1:0] USERDATA, output USERVALID, output USERUNDERFLOW, output USEREMPTY, output USERALMOSTEMPTY, output RAMVALID, output FIFORDEN, output reg USERSBITERR, output reg USERDBITERR, output reg STAGE2_REG_EN, output fab_read_data_valid_i_o, output read_data_valid_i_o, output ram_valid_i_o, output [1:0] VALID_STAGES ); //Internal signals wire preloadstage1; wire preloadstage2; reg ram_valid_i; reg fab_valid; reg read_data_valid_i; reg fab_read_data_valid_i; reg fab_read_data_valid_i_1; reg ram_valid_i_d; reg read_data_valid_i_d; reg fab_read_data_valid_i_d; wire ram_regout_en; reg ram_regout_en_d1; reg ram_regout_en_d2; wire fab_regout_en; wire ram_rd_en; reg empty_i = 1'b1; reg empty_sckt = 1'b1; reg sckt_rrst_q = 1'b0; reg sckt_rrst_done = 1'b0; reg empty_q = 1'b1; reg rd_en_q = 1'b0; reg almost_empty_i = 1'b1; reg almost_empty_q = 1'b1; wire rd_rst_i; wire srst_i; reg [C_DOUT_WIDTH-1:0] userdata_both; wire uservalid_both; wire uservalid_one; reg user_sbiterr_both = 1'b0; reg user_dbiterr_both = 1'b0; assign ram_valid_i_o = ram_valid_i; assign read_data_valid_i_o = read_data_valid_i; assign fab_read_data_valid_i_o = fab_read_data_valid_i; /************************************************************************* * FUNCTIONS *************************************************************************/ /************************************************************************* * hexstr_conv * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) ***********************************************************************/ function [C_DOUT_WIDTH-1:0] hexstr_conv; input [(C_DOUT_WIDTH*8)-1:0] def_data; integer index,i,j; reg [3:0] bin; begin index = 0; hexstr_conv = 'b0; for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin case (def_data[7:0]) 8'b00000000 : begin bin = 4'b0000; i = -1; end 8'b00110000 : bin = 4'b0000; 8'b00110001 : bin = 4'b0001; 8'b00110010 : bin = 4'b0010; 8'b00110011 : bin = 4'b0011; 8'b00110100 : bin = 4'b0100; 8'b00110101 : bin = 4'b0101; 8'b00110110 : bin = 4'b0110; 8'b00110111 : bin = 4'b0111; 8'b00111000 : bin = 4'b1000; 8'b00111001 : bin = 4'b1001; 8'b01000001 : bin = 4'b1010; 8'b01000010 : bin = 4'b1011; 8'b01000011 : bin = 4'b1100; 8'b01000100 : bin = 4'b1101; 8'b01000101 : bin = 4'b1110; 8'b01000110 : bin = 4'b1111; 8'b01100001 : bin = 4'b1010; 8'b01100010 : bin = 4'b1011; 8'b01100011 : bin = 4'b1100; 8'b01100100 : bin = 4'b1101; 8'b01100101 : bin = 4'b1110; 8'b01100110 : bin = 4'b1111; default : begin bin = 4'bx; end endcase for( j=0; j<4; j=j+1) begin if ((index*4)+j < C_DOUT_WIDTH) begin hexstr_conv[(index*4)+j] = bin[j]; end end index = index + 1; def_data = def_data >> 8; end end endfunction //************************************************************************* // Set power-on states for regs //************************************************************************* initial begin ram_valid_i = 1'b0; fab_valid = 1'b0; read_data_valid_i = 1'b0; fab_read_data_valid_i = 1'b0; fab_read_data_valid_i_1 = 1'b0; USERDATA = hexstr_conv(C_DOUT_RST_VAL); userdata_both = hexstr_conv(C_DOUT_RST_VAL); USERSBITERR = 1'b0; USERDBITERR = 1'b0; user_sbiterr_both = 1'b0; user_dbiterr_both = 1'b0; end //initial //*************************************************************************** // connect up optional reset //*************************************************************************** assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0; reg sckt_rd_rst_fwft = 1'b0; reg fwft_rst_done_i = 1'b0; wire fwft_rst_done; assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1; always @ (posedge RD_CLK) begin sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST; end always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i) fwft_rst_done_i <= 1'b0; else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST) fwft_rst_done_i <= #`TCQ 1'b1; end localparam INVALID = 0; localparam STAGE1_VALID = 2; localparam STAGE2_VALID = 1; localparam BOTH_STAGES_VALID = 3; reg [1:0] curr_fwft_state = INVALID; reg [1:0] next_fwft_state = INVALID; generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin always @* begin case (curr_fwft_state) INVALID: begin if (~FIFOEMPTY) next_fwft_state <= STAGE1_VALID; else next_fwft_state <= INVALID; end STAGE1_VALID: begin if (FIFOEMPTY) next_fwft_state <= STAGE2_VALID; else next_fwft_state <= BOTH_STAGES_VALID; end STAGE2_VALID: begin if (FIFOEMPTY && RD_EN) next_fwft_state <= INVALID; else if (~FIFOEMPTY && RD_EN) next_fwft_state <= STAGE1_VALID; else if (~FIFOEMPTY && ~RD_EN) next_fwft_state <= BOTH_STAGES_VALID; else next_fwft_state <= STAGE2_VALID; end BOTH_STAGES_VALID: begin if (FIFOEMPTY && RD_EN) next_fwft_state <= STAGE2_VALID; else if (~FIFOEMPTY && RD_EN) next_fwft_state <= BOTH_STAGES_VALID; else next_fwft_state <= BOTH_STAGES_VALID; end default: next_fwft_state <= INVALID; endcase end always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i && C_EN_SAFETY_CKT == 0) curr_fwft_state <= INVALID; else if (srst_i) curr_fwft_state <= #`TCQ INVALID; else curr_fwft_state <= #`TCQ next_fwft_state; end always @* begin case (curr_fwft_state) INVALID: STAGE2_REG_EN <= 1'b0; STAGE1_VALID: STAGE2_REG_EN <= 1'b1; STAGE2_VALID: STAGE2_REG_EN <= 1'b0; BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN; default: STAGE2_REG_EN <= 1'b0; endcase end assign VALID_STAGES = curr_fwft_state; //*************************************************************************** // preloadstage2 indicates that stage2 needs to be updated. This is true // whenever read_data_valid is false, and RAM_valid is true. //*************************************************************************** assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN ); //*************************************************************************** // preloadstage1 indicates that stage1 needs to be updated. This is true // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is // false (indicating that Stage1 needs updating), or preloadstage2 is active // (indicating that Stage2 is going to update, so Stage1, therefore, must // also be updated to keep it valid. //*************************************************************************** assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); //*************************************************************************** // Calculate RAM_REGOUT_EN // The output registers are controlled by the ram_regout_en signal. // These registers should be updated either when the output in Stage2 is // invalid (preloadstage2), OR when the user is reading, in which case the // Stage2 value will go invalid unless it is replenished. //*************************************************************************** assign ram_regout_en = preloadstage2; //*************************************************************************** // Calculate RAM_RD_EN // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to // update the value in Stage1. // One case when this happens is when preloadstage1=true, which indicates // that the data in Stage1 or Stage2 is invalid, and needs to automatically // be updated. // The other case is when the user is reading from the FIFO, which // guarantees that Stage1 or Stage2 will be invalid on the next clock // cycle, unless it is replinished by data from the memory. So, as long // as the RAM has data in it, a read of the RAM should occur. //*************************************************************************** assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; end endgenerate // gnll_fifo reg curr_state = 0; reg next_state = 0; reg leaving_empty_fwft = 0; reg going_empty_fwft = 0; reg empty_i_q = 0; reg ram_rd_en_fwft = 0; generate if (C_FIFO_TYPE == 2) begin : gll_fifo always @* begin // FSM fo FWFT case (curr_state) 1'b0: begin if (~FIFOEMPTY) next_state <= 1'b1; else next_state <= 1'b0; end 1'b1: begin if (FIFOEMPTY && RD_EN) next_state <= 1'b0; else next_state <= 1'b1; end default: next_state <= 1'b0; endcase end always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin empty_i <= 1'b1; empty_i_q <= 1'b1; ram_valid_i <= 1'b0; end else if (srst_i) begin empty_i <= #`TCQ 1'b1; empty_i_q <= #`TCQ 1'b1; ram_valid_i <= #`TCQ 1'b0; end else begin empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i); empty_i_q <= #`TCQ FIFOEMPTY; ram_valid_i <= #`TCQ next_state; end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin curr_state <= 1'b0; end else if (srst_i) begin curr_state <= #`TCQ 1'b0; end else begin curr_state <= #`TCQ next_state; end end //always wire fe_of_empty; assign fe_of_empty = empty_i_q & ~FIFOEMPTY; always @* begin // Finding leaving empty case (curr_state) 1'b0: leaving_empty_fwft <= fe_of_empty; 1'b1: leaving_empty_fwft <= 1'b1; default: leaving_empty_fwft <= 1'b0; endcase end always @* begin // Finding going empty case (curr_state) 1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN; default: going_empty_fwft <= 1'b0; endcase end always @* begin // Generating FWFT rd_en case (curr_state) 1'b0: ram_rd_en_fwft <= ~FIFOEMPTY; 1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN; default: ram_rd_en_fwft <= 1'b0; endcase end assign ram_regout_en = ram_rd_en_fwft; //assign ram_regout_en_d1 = ram_rd_en_fwft; //assign ram_regout_en_d2 = ram_rd_en_fwft; assign ram_rd_en = ram_rd_en_fwft; end endgenerate // gll_fifo //*************************************************************************** // Calculate RAMVALID_P0_OUT // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. // // If the RAM is being read from on this clock cycle (ram_rd_en=1), then // RAMVALID_P0_OUT is certainly going to be true. // If the RAM is not being read from, but the output registers are being // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, // therefore causing RAMVALID_P0_OUT to be false. // Otherwise, RAMVALID_P0_OUT will remain unchanged. //*************************************************************************** // PROCESS regout_valid generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) ram_valid_i <= #`TCQ 1'b0; end else begin if (srst_i) begin // synchronous reset (active high) ram_valid_i <= #`TCQ 1'b0; end else begin if (ram_rd_en == 1'b1) begin ram_valid_i <= #`TCQ 1'b1; end else begin if (ram_regout_en == 1'b1) ram_valid_i <= #`TCQ 1'b0; else ram_valid_i <= #`TCQ ram_valid_i; end end //srst_i end //rd_rst_i end //always end endgenerate // gnll_fifo_ram_valid //*************************************************************************** // Calculate READ_DATA_VALID // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. // Stage2 has valid data whenever Stage1 had valid data and // ram_regout_en_i=1, such that the data in Stage1 is propogated // into Stage2. //*************************************************************************** generate if(C_USE_EMBEDDED_REG < 3) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) read_data_valid_i <= #`TCQ 1'b0; else if (srst_i) read_data_valid_i <= #`TCQ 1'b0; else read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); end //always end endgenerate //************************************************************************** // Calculate EMPTY // Defined as the inverse of READ_DATA_VALID // // Description: // // If read_data_valid_i indicates that the output is not valid, // and there is no valid data on the output of the ram to preload it // with, then we will report empty. // // If there is no valid data on the output of the ram and we are // reading, then the FIFO will go empty. // //************************************************************************** generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) empty_i <= #`TCQ 1'b1; end else begin if (srst_i) begin // synchronous reset (active high) empty_i <= #`TCQ 1'b1; end else begin // rising clock edge empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); end end end //always end endgenerate // gnll_fifo_empty // Register RD_EN from user to calculate USERUNDERFLOW. // Register empty_i to calculate USERUNDERFLOW. always @ (posedge RD_CLK) begin rd_en_q <= #`TCQ RD_EN; empty_q <= #`TCQ empty_i; end //always //*************************************************************************** // Calculate user_almost_empty // user_almost_empty is defined such that, unless more words are written // to the FIFO, the next read will cause the FIFO to go EMPTY. // // In most cases, whenever the output registers are updated (due to a user // read or a preload condition), then user_almost_empty will update to // whatever RAM_EMPTY is. // // The exception is when the output is valid, the user is not reading, and // Stage1 is not empty. In this condition, Stage1 will be preloaded from the // memory, so we need to make sure user_almost_empty deasserts properly under // this condition. //*************************************************************************** generate if ( C_USE_EMBEDDED_REG < 3) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) almost_empty_i <= #`TCQ 1'b1; almost_empty_q <= #`TCQ 1'b1; end else begin // rising clock edge if (srst_i) begin // synchronous reset (active high) almost_empty_i <= #`TCQ 1'b1; almost_empty_q <= #`TCQ 1'b1; end else begin if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin almost_empty_i <= #`TCQ FIFOEMPTY; end almost_empty_q <= #`TCQ empty_i; end end end //always end endgenerate // BRAM resets synchronously generate if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin always @ ( posedge rd_rst_i) begin if (rd_rst_i || srst_i) begin if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) @(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin //asynchronous reset (active high) if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; end // DRAM resets asynchronously if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else begin // rising clock edge if (srst_i) begin if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; end if (C_USE_DOUT_RST == 1) begin USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else if (fwft_rst_done) begin if (ram_regout_en) begin USERDATA <= #`TCQ FIFODATA; USERSBITERR <= #`TCQ FIFOSBITERR; USERDBITERR <= #`TCQ FIFODBITERR; end end end end //always end //if endgenerate //safety ckt with one register generate if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge RD_CLK) begin rst_delayed_sft1 <= #`TCQ rd_rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always @ (posedge RD_CLK) begin if (rd_rst_i || srst_i) begin if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin @(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin //asynchronous reset (active high) if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; end // DRAM resets asynchronously if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high) //@(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else begin // rising clock edge if (srst_i) begin if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; end if (C_USE_DOUT_RST == 1) begin // @(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else if (fwft_rst_done) begin if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin USERDATA <= #`TCQ FIFODATA; USERSBITERR <= #`TCQ FIFOSBITERR; USERDBITERR <= #`TCQ FIFODBITERR; end end end end //always end //if endgenerate generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin always @* begin case (curr_fwft_state) INVALID: begin if (~FIFOEMPTY) next_fwft_state <= STAGE1_VALID; else next_fwft_state <= INVALID; end STAGE1_VALID: begin if (FIFOEMPTY) next_fwft_state <= STAGE2_VALID; else next_fwft_state <= BOTH_STAGES_VALID; end STAGE2_VALID: begin if (FIFOEMPTY && RD_EN) next_fwft_state <= INVALID; else if (~FIFOEMPTY && RD_EN) next_fwft_state <= STAGE1_VALID; else if (~FIFOEMPTY && ~RD_EN) next_fwft_state <= BOTH_STAGES_VALID; else next_fwft_state <= STAGE2_VALID; end BOTH_STAGES_VALID: begin if (FIFOEMPTY && RD_EN) next_fwft_state <= STAGE2_VALID; else if (~FIFOEMPTY && RD_EN) next_fwft_state <= BOTH_STAGES_VALID; else next_fwft_state <= BOTH_STAGES_VALID; end default: next_fwft_state <= INVALID; endcase end always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i && C_EN_SAFETY_CKT == 0) curr_fwft_state <= INVALID; else if (srst_i) curr_fwft_state <= #`TCQ INVALID; else curr_fwft_state <= #`TCQ next_fwft_state; end always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay if (rd_rst_i == 1) begin ram_regout_en_d1 <= #`TCQ 1'b0; end else begin if (srst_i == 1'b1) ram_regout_en_d1 <= #`TCQ 1'b0; else ram_regout_en_d1 <= #`TCQ ram_regout_en; end end //always // assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i)); assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0; always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1 if (rd_rst_i == 1) begin ram_regout_en_d2 <= #`TCQ 1'b0; end else begin if (srst_i == 1'b1) ram_regout_en_d2 <= #`TCQ 1'b0; else ram_regout_en_d2 <= #`TCQ ram_regout_en_d1; end end //always always @* begin case (curr_fwft_state) INVALID: STAGE2_REG_EN <= 1'b0; STAGE1_VALID: STAGE2_REG_EN <= 1'b1; STAGE2_VALID: STAGE2_REG_EN <= 1'b0; BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN; default: STAGE2_REG_EN <= 1'b0; endcase end always @ (posedge RD_CLK) begin ram_valid_i_d <= #`TCQ ram_valid_i; read_data_valid_i_d <= #`TCQ read_data_valid_i; fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i; end assign VALID_STAGES = curr_fwft_state; //*************************************************************************** // preloadstage2 indicates that stage2 needs to be updated. This is true // whenever read_data_valid is false, and RAM_valid is true. //*************************************************************************** assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN ); //*************************************************************************** // preloadstage1 indicates that stage1 needs to be updated. This is true // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is // false (indicating that Stage1 needs updating), or preloadstage2 is active // (indicating that Stage2 is going to update, so Stage1, therefore, must // also be updated to keep it valid. //*************************************************************************** assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); //*************************************************************************** // Calculate RAM_REGOUT_EN // The output registers are controlled by the ram_regout_en signal. // These registers should be updated either when the output in Stage2 is // invalid (preloadstage2), OR when the user is reading, in which case the // Stage2 value will go invalid unless it is replenished. //*************************************************************************** assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0; //*************************************************************************** // Calculate RAM_RD_EN // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to // update the value in Stage1. // One case when this happens is when preloadstage1=true, which indicates // that the data in Stage1 or Stage2 is invalid, and needs to automatically // be updated. // The other case is when the user is reading from the FIFO, which // guarantees that Stage1 or Stage2 will be invalid on the next clock // cycle, unless it is replinished by data from the memory. So, as long // as the RAM has data in it, a read of the RAM should occur. //*************************************************************************** assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1; end endgenerate // gnll_fifo //*************************************************************************** // Calculate RAMVALID_P0_OUT // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. // // If the RAM is being read from on this clock cycle (ram_rd_en=1), then // RAMVALID_P0_OUT is certainly going to be true. // If the RAM is not being read from, but the output registers are being // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, // therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged. //*************************************************************************** // PROCESS regout_valid generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) fab_valid <= #`TCQ 1'b0; end else begin if (srst_i) begin // synchronous reset (active high) fab_valid <= #`TCQ 1'b0; end else begin if (ram_regout_en == 1'b1) begin fab_valid <= #`TCQ 1'b1; end else begin if (fab_regout_en == 1'b1) fab_valid <= #`TCQ 1'b0; else fab_valid <= #`TCQ fab_valid; end end //srst_i end //rd_rst_i end //always end endgenerate // gnll_fifo_fab_valid //*************************************************************************** // Calculate READ_DATA_VALID // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. // Stage2 has valid data whenever Stage1 had valid data and // ram_regout_en_i=1, such that the data in Stage1 is propogated // into Stage2. //*************************************************************************** generate if(C_USE_EMBEDDED_REG == 3) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) read_data_valid_i <= #`TCQ 1'b0; else if (srst_i) read_data_valid_i <= #`TCQ 1'b0; else begin if (ram_regout_en == 1'b1) begin read_data_valid_i <= #`TCQ 1'b1; end else begin if (fab_regout_en == 1'b1) read_data_valid_i <= #`TCQ 1'b0; else read_data_valid_i <= #`TCQ read_data_valid_i; end end end //always end endgenerate //generate if(C_USE_EMBEDDED_REG == 3) begin // always @ (posedge RD_CLK or posedge rd_rst_i) begin // if (rd_rst_i) // read_data_valid_i <= #`TCQ 1'b0; // else if (srst_i) // read_data_valid_i <= #`TCQ 1'b0; // // if (ram_regout_en == 1'b1) begin // fab_read_data_valid_i <= #`TCQ 1'b0; // end else begin // if (fab_regout_en == 1'b1) // fab_read_data_valid_i <= #`TCQ 1'b1; // else // fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i; // end // end //always //end //endgenerate generate if(C_USE_EMBEDDED_REG == 3 ) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid if (rd_rst_i) fab_read_data_valid_i <= #`TCQ 1'b0; else if (srst_i) fab_read_data_valid_i <= #`TCQ 1'b0; else fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN); end //always end endgenerate always @ (posedge RD_CLK ) begin : proc_del1 begin fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i; end end //always //************************************************************************** // Calculate EMPTY // Defined as the inverse of READ_DATA_VALID // // Description: // // If read_data_valid_i indicates that the output is not valid, // and there is no valid data on the output of the ram to preload it // with, then we will report empty. // // If there is no valid data on the output of the ram and we are // reading, then the FIFO will go empty. // //************************************************************************** generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) empty_i <= #`TCQ 1'b1; end else begin if (srst_i) begin // synchronous reset (active high) empty_i <= #`TCQ 1'b1; end else begin // rising clock edge empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN); end end end //always end endgenerate // gnll_fifo_empty_both // Register RD_EN from user to calculate USERUNDERFLOW. // Register empty_i to calculate USERUNDERFLOW. always @ (posedge RD_CLK) begin rd_en_q <= #`TCQ RD_EN; empty_q <= #`TCQ empty_i; end //always //*************************************************************************** // Calculate user_almost_empty // user_almost_empty is defined such that, unless more words are written // to the FIFO, the next read will cause the FIFO to go EMPTY. // // In most cases, whenever the output registers are updated (due to a user // read or a preload condition), then user_almost_empty will update to // whatever RAM_EMPTY is. // // The exception is when the output is valid, the user is not reading, and // Stage1 is not empty. In this condition, Stage1 will be preloaded from the // memory, so we need to make sure user_almost_empty deasserts properly under // this condition. //*************************************************************************** reg FIFOEMPTY_1; generate if (C_USE_EMBEDDED_REG == 3 ) begin always @(posedge RD_CLK) begin FIFOEMPTY_1 <= #`TCQ FIFOEMPTY; end end endgenerate generate if (C_USE_EMBEDDED_REG == 3 ) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) almost_empty_i <= #`TCQ 1'b1; almost_empty_q <= #`TCQ 1'b1; end else begin // rising clock edge if (srst_i) begin // synchronous reset (active high) almost_empty_i <= #`TCQ 1'b1; almost_empty_q <= #`TCQ 1'b1; end else begin if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin almost_empty_i <= #`TCQ (~ram_valid_i); end almost_empty_q <= #`TCQ empty_i; end end end //always end endgenerate always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin empty_sckt <= #`TCQ 1'b1; sckt_rrst_q <= #`TCQ 1'b0; sckt_rrst_done <= #`TCQ 1'b0; end else begin sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST; if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin sckt_rrst_done <= #`TCQ 1'b1; end else if (sckt_rrst_done) begin // rising clock edge empty_sckt <= #`TCQ 1'b0; end end end //always // assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i; assign USEREMPTY = empty_i; assign USERALMOSTEMPTY = almost_empty_i; assign FIFORDEN = ram_rd_en; assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i; assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0); assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0); assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one; assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; //no safety ckt with both reg generate if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin always @ (posedge RD_CLK) begin if (rd_rst_i || srst_i) begin if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin //asynchronous reset (active high) if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end // DRAM resets asynchronously if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end else begin // rising clock edge if (srst_i) begin if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end else begin if (fwft_rst_done) begin if (ram_regout_en) begin userdata_both <= #`TCQ FIFODATA; user_dbiterr_both <= #`TCQ FIFODBITERR; user_sbiterr_both <= #`TCQ FIFOSBITERR; end if (fab_regout_en) begin USERDATA <= #`TCQ userdata_both; USERDBITERR <= #`TCQ user_dbiterr_both; USERSBITERR <= #`TCQ user_sbiterr_both; end end end end end //always end //if endgenerate //safety_ckt with both registers generate if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge RD_CLK) begin rst_delayed_sft1 <= #`TCQ rd_rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always @ (posedge RD_CLK) begin if (rd_rst_i || srst_i) begin if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin @(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin //asynchronous reset (active high) if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end // DRAM resets asynchronously if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end else begin // rising clock edge if (srst_i) begin if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else if (fwft_rst_done) begin if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin userdata_both <= #`TCQ FIFODATA; user_dbiterr_both <= #`TCQ FIFODBITERR; user_sbiterr_both <= #`TCQ FIFOSBITERR; end if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin USERDATA <= #`TCQ userdata_both; USERDBITERR <= #`TCQ user_dbiterr_both; USERSBITERR <= #`TCQ user_sbiterr_both; end end end end //always end //if endgenerate endmodule //fifo_generator_v13_1_3_bhv_ver_preload0 //----------------------------------------------------------------------------- // // Register Slice // Register one AXI channel on forward and/or reverse signal path // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // reg_slice // //-------------------------------------------------------------------------- module fifo_generator_v13_1_3_axic_reg_slice # ( parameter C_FAMILY = "virtex7", parameter C_DATA_WIDTH = 32, parameter C_REG_CONFIG = 32'h00000000 ) ( // System Signals input wire ACLK, input wire ARESET, // Slave side input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, input wire S_VALID, output wire S_READY, // Master side output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, output wire M_VALID, input wire M_READY ); generate //////////////////////////////////////////////////////////////////// // // Both FWD and REV mode // //////////////////////////////////////////////////////////////////// if (C_REG_CONFIG == 32'h00000000) begin reg [1:0] state; localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01; reg [C_DATA_WIDTH-1:0] storage_data1 = 0; reg [C_DATA_WIDTH-1:0] storage_data2 = 0; reg load_s1; wire load_s2; wire load_s1_from_s2; reg s_ready_i; //local signal of output wire m_valid_i; //local signal of output // assign local signal to its output signal assign S_READY = s_ready_i; assign M_VALID = m_valid_i; reg areset_d1; // Reset delay register always @(posedge ACLK) begin areset_d1 <= ARESET; end // Load storage1 with either slave side data or from storage2 always @(posedge ACLK) begin if (load_s1) if (load_s1_from_s2) storage_data1 <= storage_data2; else storage_data1 <= S_PAYLOAD_DATA; end // Load storage2 with slave side data always @(posedge ACLK) begin if (load_s2) storage_data2 <= S_PAYLOAD_DATA; end assign M_PAYLOAD_DATA = storage_data1; // Always load s2 on a valid transaction even if it's unnecessary assign load_s2 = S_VALID & s_ready_i; // Loading s1 always @ * begin if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction // Load when ONE if we both have read and write at the same time ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) || // Load when TWO and we have a transaction on Master side ((state == TWO) && (M_READY == 1))) load_s1 = 1'b1; else load_s1 = 1'b0; end // always @ * assign load_s1_from_s2 = (state == TWO); // State Machine for handling output signals always @(posedge ACLK) begin if (ARESET) begin s_ready_i <= 1'b0; state <= ZERO; end else if (areset_d1) begin s_ready_i <= 1'b1; end else begin case (state) // No transaction stored locally ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE // One transaction stored locally ONE: begin if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO if (~M_READY & S_VALID) begin state <= TWO; // Got another one so move to TWO s_ready_i <= 1'b0; end end // TWO transaction stored locally TWO: if (M_READY) begin state <= ONE; // Read out one so move to ONE s_ready_i <= 1'b1; end endcase // case (state) end end // always @ (posedge ACLK) assign m_valid_i = state[0]; end // if (C_REG_CONFIG == 1) //////////////////////////////////////////////////////////////////// // // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining // Operates same as 1-deep FIFO // //////////////////////////////////////////////////////////////////// else if (C_REG_CONFIG == 32'h00000001) begin reg [C_DATA_WIDTH-1:0] storage_data1 = 0; reg s_ready_i; //local signal of output reg m_valid_i; //local signal of output // assign local signal to its output signal assign S_READY = s_ready_i; assign M_VALID = m_valid_i; reg areset_d1; // Reset delay register always @(posedge ACLK) begin areset_d1 <= ARESET; end // Load storage1 with slave side data always @(posedge ACLK) begin if (ARESET) begin s_ready_i <= 1'b0; m_valid_i <= 1'b0; end else if (areset_d1) begin s_ready_i <= 1'b1; end else if (m_valid_i & M_READY) begin s_ready_i <= 1'b1; m_valid_i <= 1'b0; end else if (S_VALID & s_ready_i) begin s_ready_i <= 1'b0; m_valid_i <= 1'b1; end if (~m_valid_i) begin storage_data1 <= S_PAYLOAD_DATA; end end assign M_PAYLOAD_DATA = storage_data1; end // if (C_REG_CONFIG == 7) else begin : default_case // Passthrough assign M_PAYLOAD_DATA = S_PAYLOAD_DATA; assign M_VALID = S_VALID; assign S_READY = M_READY; end endgenerate endmodule // reg_slice
/* ******************************************************************************* * * FIFO Generator - Verilog Behavioral Model * ******************************************************************************* * * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. * * This file contains confidential and proprietary information * of Xilinx, Inc. and is protected under U.S. and * international copyright and other intellectual property * laws. * * DISCLAIMER * This disclaimer is not a license and does not grant any * rights to the materials distributed herewith. Except as * otherwise provided in a valid license issued to you by * Xilinx, and to the maximum extent permitted by applicable * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * (2) Xilinx shall not be liable (whether in contract or tort, * including negligence, or under any other theory of * liability) for any loss or damage of any kind or nature * related to, arising under or in connection with these * materials, including for any direct, or any indirect, * special, incidental, or consequential loss or damage * (including loss of data, profits, goodwill, or any type of * loss or damage suffered as a result of any action brought * by a third party) even if such damage or loss was * reasonably foreseeable or Xilinx had been advised of the * possibility of the same. * * CRITICAL APPLICATIONS * Xilinx products are not designed or intended to be fail- * safe, or for use in any application requiring fail-safe * performance, such as life-support or safety devices or * systems, Class III medical devices, nuclear facilities, * applications related to the deployment of airbags, or any * other applications that could lead to death, personal * injury, or severe property or environmental damage * (individually and collectively, "Critical * Applications"). Customer assumes the sole risk and * liability of any use of Xilinx products in Critical * Applications, subject only to applicable laws and * regulations governing limitations on product liability. * * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * PART OF THIS FILE AT ALL TIMES. * ******************************************************************************* ******************************************************************************* * * Filename: fifo_generator_vlog_beh.v * * Author : Xilinx * ******************************************************************************* * Structure: * * fifo_generator_vlog_beh.v * | * +-fifo_generator_v13_1_3_bhv_ver_as * | * +-fifo_generator_v13_1_3_bhv_ver_ss * | * +-fifo_generator_v13_1_3_bhv_ver_preload0 * ******************************************************************************* * Description: * * The Verilog behavioral model for the FIFO Generator. * * The behavioral model has three parts: * - The behavioral model for independent clocks FIFOs (_as) * - The behavioral model for common clock FIFOs (_ss) * - The "preload logic" block which implements First-word Fall-through * ******************************************************************************* * Description: * The verilog behavioral model for the FIFO generator core. * ******************************************************************************* */ `timescale 1ps/1ps `ifndef TCQ `define TCQ 100 `endif /******************************************************************************* * Declaration of top-level module ******************************************************************************/ module fifo_generator_vlog_beh #( //----------------------------------------------------------------------- // Generic Declarations //----------------------------------------------------------------------- parameter C_COMMON_CLOCK = 0, parameter C_COUNT_TYPE = 0, parameter C_DATA_COUNT_WIDTH = 2, parameter C_DEFAULT_VALUE = "", parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_ENABLE_RLOCS = 0, parameter C_FAMILY = "", parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_ALMOST_EMPTY = 0, parameter C_HAS_ALMOST_FULL = 0, parameter C_HAS_BACKUP = 0, parameter C_HAS_DATA_COUNT = 0, parameter C_HAS_INT_CLK = 0, parameter C_HAS_MEMINIT_FILE = 0, parameter C_HAS_OVERFLOW = 0, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_RD_RST = 0, parameter C_HAS_RST = 1, parameter C_HAS_SRST = 0, parameter C_HAS_UNDERFLOW = 0, parameter C_HAS_VALID = 0, parameter C_HAS_WR_ACK = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_HAS_WR_RST = 0, parameter C_IMPLEMENTATION_TYPE = 0, parameter C_INIT_WR_PNTR_VAL = 0, parameter C_MEMORY_TYPE = 1, parameter C_MIF_FILE_NAME = "", parameter C_OPTIMIZATION_MODE = 0, parameter C_OVERFLOW_LOW = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_PRELOAD_LATENCY = 1, parameter C_PRELOAD_REGS = 0, parameter C_PRIM_FIFO_TYPE = "4kx4", parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, parameter C_PROG_EMPTY_TYPE = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, parameter C_PROG_FULL_TYPE = 0, parameter C_RD_DATA_COUNT_WIDTH = 2, parameter C_RD_DEPTH = 256, parameter C_RD_FREQ = 1, parameter C_RD_PNTR_WIDTH = 8, parameter C_UNDERFLOW_LOW = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_ECC = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_USE_PIPELINE_REG = 0, parameter C_POWER_SAVING_MODE = 0, parameter C_USE_FIFO16_FLAGS = 0, parameter C_USE_FWFT_DATA_COUNT = 0, parameter C_VALID_LOW = 0, parameter C_WR_ACK_LOW = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_FREQ = 1, parameter C_WR_PNTR_WIDTH = 8, parameter C_WR_RESPONSE_LATENCY = 1, parameter C_MSGON_VAL = 1, parameter C_ENABLE_RST_SYNC = 1, parameter C_ERROR_INJECTION_TYPE = 0, parameter C_SYNCHRONIZER_STAGE = 2, // AXI Interface related parameters start here parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3 parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3 parameter C_HAS_AXI_WR_CHANNEL = 0, parameter C_HAS_AXI_RD_CHANNEL = 0, parameter C_HAS_SLAVE_CE = 0, parameter C_HAS_MASTER_CE = 0, parameter C_ADD_NGC_CONSTRAINT = 0, parameter C_USE_COMMON_UNDERFLOW = 0, parameter C_USE_COMMON_OVERFLOW = 0, parameter C_USE_DEFAULT_SETTINGS = 0, // AXI Full/Lite parameter C_AXI_ID_WIDTH = 0, parameter C_AXI_ADDR_WIDTH = 0, parameter C_AXI_DATA_WIDTH = 0, parameter C_AXI_LEN_WIDTH = 8, parameter C_AXI_LOCK_WIDTH = 2, parameter C_HAS_AXI_ID = 0, parameter C_HAS_AXI_AWUSER = 0, parameter C_HAS_AXI_WUSER = 0, parameter C_HAS_AXI_BUSER = 0, parameter C_HAS_AXI_ARUSER = 0, parameter C_HAS_AXI_RUSER = 0, parameter C_AXI_ARUSER_WIDTH = 0, parameter C_AXI_AWUSER_WIDTH = 0, parameter C_AXI_WUSER_WIDTH = 0, parameter C_AXI_BUSER_WIDTH = 0, parameter C_AXI_RUSER_WIDTH = 0, // AXI Streaming parameter C_HAS_AXIS_TDATA = 0, parameter C_HAS_AXIS_TID = 0, parameter C_HAS_AXIS_TDEST = 0, parameter C_HAS_AXIS_TUSER = 0, parameter C_HAS_AXIS_TREADY = 0, parameter C_HAS_AXIS_TLAST = 0, parameter C_HAS_AXIS_TSTRB = 0, parameter C_HAS_AXIS_TKEEP = 0, parameter C_AXIS_TDATA_WIDTH = 1, parameter C_AXIS_TID_WIDTH = 1, parameter C_AXIS_TDEST_WIDTH = 1, parameter C_AXIS_TUSER_WIDTH = 1, parameter C_AXIS_TSTRB_WIDTH = 1, parameter C_AXIS_TKEEP_WIDTH = 1, // AXI Channel Type // WACH --> Write Address Channel // WDCH --> Write Data Channel // WRCH --> Write Response Channel // RACH --> Read Address Channel // RDCH --> Read Data Channel // AXIS --> AXI Streaming parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie // AXI Implementation Type // 1 = Common Clock Block RAM FIFO // 2 = Common Clock Distributed RAM FIFO // 11 = Independent Clock Block RAM FIFO // 12 = Independent Clock Distributed RAM FIFO parameter C_IMPLEMENTATION_TYPE_WACH = 0, parameter C_IMPLEMENTATION_TYPE_WDCH = 0, parameter C_IMPLEMENTATION_TYPE_WRCH = 0, parameter C_IMPLEMENTATION_TYPE_RACH = 0, parameter C_IMPLEMENTATION_TYPE_RDCH = 0, parameter C_IMPLEMENTATION_TYPE_AXIS = 0, // AXI FIFO Type // 0 = Data FIFO // 1 = Packet FIFO // 2 = Low Latency Sync FIFO // 3 = Low Latency Async FIFO parameter C_APPLICATION_TYPE_WACH = 0, parameter C_APPLICATION_TYPE_WDCH = 0, parameter C_APPLICATION_TYPE_WRCH = 0, parameter C_APPLICATION_TYPE_RACH = 0, parameter C_APPLICATION_TYPE_RDCH = 0, parameter C_APPLICATION_TYPE_AXIS = 0, // AXI Built-in FIFO Primitive Type // 512x36, 1kx18, 2kx9, 4kx4, etc parameter C_PRIM_FIFO_TYPE_WACH = "512x36", parameter C_PRIM_FIFO_TYPE_WDCH = "512x36", parameter C_PRIM_FIFO_TYPE_WRCH = "512x36", parameter C_PRIM_FIFO_TYPE_RACH = "512x36", parameter C_PRIM_FIFO_TYPE_RDCH = "512x36", parameter C_PRIM_FIFO_TYPE_AXIS = "512x36", // Enable ECC // 0 = ECC disabled // 1 = ECC enabled parameter C_USE_ECC_WACH = 0, parameter C_USE_ECC_WDCH = 0, parameter C_USE_ECC_WRCH = 0, parameter C_USE_ECC_RACH = 0, parameter C_USE_ECC_RDCH = 0, parameter C_USE_ECC_AXIS = 0, // ECC Error Injection Type // 0 = No Error Injection // 1 = Single Bit Error Injection // 2 = Double Bit Error Injection // 3 = Single Bit and Double Bit Error Injection parameter C_ERROR_INJECTION_TYPE_WACH = 0, parameter C_ERROR_INJECTION_TYPE_WDCH = 0, parameter C_ERROR_INJECTION_TYPE_WRCH = 0, parameter C_ERROR_INJECTION_TYPE_RACH = 0, parameter C_ERROR_INJECTION_TYPE_RDCH = 0, parameter C_ERROR_INJECTION_TYPE_AXIS = 0, // Input Data Width // Accumulation of all AXI input signal's width parameter C_DIN_WIDTH_WACH = 1, parameter C_DIN_WIDTH_WDCH = 1, parameter C_DIN_WIDTH_WRCH = 1, parameter C_DIN_WIDTH_RACH = 1, parameter C_DIN_WIDTH_RDCH = 1, parameter C_DIN_WIDTH_AXIS = 1, parameter C_WR_DEPTH_WACH = 16, parameter C_WR_DEPTH_WDCH = 16, parameter C_WR_DEPTH_WRCH = 16, parameter C_WR_DEPTH_RACH = 16, parameter C_WR_DEPTH_RDCH = 16, parameter C_WR_DEPTH_AXIS = 16, parameter C_WR_PNTR_WIDTH_WACH = 4, parameter C_WR_PNTR_WIDTH_WDCH = 4, parameter C_WR_PNTR_WIDTH_WRCH = 4, parameter C_WR_PNTR_WIDTH_RACH = 4, parameter C_WR_PNTR_WIDTH_RDCH = 4, parameter C_WR_PNTR_WIDTH_AXIS = 4, parameter C_HAS_DATA_COUNTS_WACH = 0, parameter C_HAS_DATA_COUNTS_WDCH = 0, parameter C_HAS_DATA_COUNTS_WRCH = 0, parameter C_HAS_DATA_COUNTS_RACH = 0, parameter C_HAS_DATA_COUNTS_RDCH = 0, parameter C_HAS_DATA_COUNTS_AXIS = 0, parameter C_HAS_PROG_FLAGS_WACH = 0, parameter C_HAS_PROG_FLAGS_WDCH = 0, parameter C_HAS_PROG_FLAGS_WRCH = 0, parameter C_HAS_PROG_FLAGS_RACH = 0, parameter C_HAS_PROG_FLAGS_RDCH = 0, parameter C_HAS_PROG_FLAGS_AXIS = 0, parameter C_PROG_FULL_TYPE_WACH = 0, parameter C_PROG_FULL_TYPE_WDCH = 0, parameter C_PROG_FULL_TYPE_WRCH = 0, parameter C_PROG_FULL_TYPE_RACH = 0, parameter C_PROG_FULL_TYPE_RDCH = 0, parameter C_PROG_FULL_TYPE_AXIS = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0, parameter C_PROG_EMPTY_TYPE_WACH = 0, parameter C_PROG_EMPTY_TYPE_WDCH = 0, parameter C_PROG_EMPTY_TYPE_WRCH = 0, parameter C_PROG_EMPTY_TYPE_RACH = 0, parameter C_PROG_EMPTY_TYPE_RDCH = 0, parameter C_PROG_EMPTY_TYPE_AXIS = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0, parameter C_REG_SLICE_MODE_WACH = 0, parameter C_REG_SLICE_MODE_WDCH = 0, parameter C_REG_SLICE_MODE_WRCH = 0, parameter C_REG_SLICE_MODE_RACH = 0, parameter C_REG_SLICE_MODE_RDCH = 0, parameter C_REG_SLICE_MODE_AXIS = 0 ) ( //------------------------------------------------------------------------------ // Input and Output Declarations //------------------------------------------------------------------------------ // Conventional FIFO Interface Signals input backup, input backup_marker, input clk, input rst, input srst, input wr_clk, input wr_rst, input rd_clk, input rd_rst, input [C_DIN_WIDTH-1:0] din, input wr_en, input rd_en, // Optional inputs input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh, input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert, input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate, input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh, input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert, input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate, input int_clk, input injectdbiterr, input injectsbiterr, input sleep, output [C_DOUT_WIDTH-1:0] dout, output full, output almost_full, output wr_ack, output overflow, output empty, output almost_empty, output valid, output underflow, output [C_DATA_COUNT_WIDTH-1:0] data_count, output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count, output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count, output prog_full, output prog_empty, output sbiterr, output dbiterr, output wr_rst_busy, output rd_rst_busy, // AXI Global Signal input m_aclk, input s_aclk, input s_aresetn, input s_aclk_en, input m_aclk_en, // AXI Full/Lite Slave Write Channel (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_awid, input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen, input [3-1:0] s_axi_awsize, input [2-1:0] s_axi_awburst, input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock, input [4-1:0] s_axi_awcache, input [3-1:0] s_axi_awprot, input [4-1:0] s_axi_awqos, input [4-1:0] s_axi_awregion, input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, input s_axi_awvalid, output s_axi_awready, input [C_AXI_ID_WIDTH-1:0] s_axi_wid, input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, input s_axi_wlast, input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, input s_axi_wvalid, output s_axi_wready, output [C_AXI_ID_WIDTH-1:0] s_axi_bid, output [2-1:0] s_axi_bresp, output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, output s_axi_bvalid, input s_axi_bready, // AXI Full/Lite Master Write Channel (read side) output [C_AXI_ID_WIDTH-1:0] m_axi_awid, output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen, output [3-1:0] m_axi_awsize, output [2-1:0] m_axi_awburst, output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock, output [4-1:0] m_axi_awcache, output [3-1:0] m_axi_awprot, output [4-1:0] m_axi_awqos, output [4-1:0] m_axi_awregion, output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, output m_axi_awvalid, input m_axi_awready, output [C_AXI_ID_WIDTH-1:0] m_axi_wid, output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output m_axi_wlast, output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, output m_axi_wvalid, input m_axi_wready, input [C_AXI_ID_WIDTH-1:0] m_axi_bid, input [2-1:0] m_axi_bresp, input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, input m_axi_bvalid, output m_axi_bready, // AXI Full/Lite Slave Read Channel (write side) input [C_AXI_ID_WIDTH-1:0] s_axi_arid, input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen, input [3-1:0] s_axi_arsize, input [2-1:0] s_axi_arburst, input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock, input [4-1:0] s_axi_arcache, input [3-1:0] s_axi_arprot, input [4-1:0] s_axi_arqos, input [4-1:0] s_axi_arregion, input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, input s_axi_arvalid, output s_axi_arready, output [C_AXI_ID_WIDTH-1:0] s_axi_rid, output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, output [2-1:0] s_axi_rresp, output s_axi_rlast, output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, output s_axi_rvalid, input s_axi_rready, // AXI Full/Lite Master Read Channel (read side) output [C_AXI_ID_WIDTH-1:0] m_axi_arid, output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen, output [3-1:0] m_axi_arsize, output [2-1:0] m_axi_arburst, output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock, output [4-1:0] m_axi_arcache, output [3-1:0] m_axi_arprot, output [4-1:0] m_axi_arqos, output [4-1:0] m_axi_arregion, output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, output m_axi_arvalid, input m_axi_arready, input [C_AXI_ID_WIDTH-1:0] m_axi_rid, input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, input [2-1:0] m_axi_rresp, input m_axi_rlast, input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, input m_axi_rvalid, output m_axi_rready, // AXI Streaming Slave Signals (Write side) input s_axis_tvalid, output s_axis_tready, input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata, input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb, input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep, input s_axis_tlast, input [C_AXIS_TID_WIDTH-1:0] s_axis_tid, input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest, input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser, // AXI Streaming Master Signals (Read side) output m_axis_tvalid, input m_axis_tready, output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata, output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb, output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep, output m_axis_tlast, output [C_AXIS_TID_WIDTH-1:0] m_axis_tid, output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest, output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser, // AXI Full/Lite Write Address Channel signals input axi_aw_injectsbiterr, input axi_aw_injectdbiterr, input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh, input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh, output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count, output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count, output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count, output axi_aw_sbiterr, output axi_aw_dbiterr, output axi_aw_overflow, output axi_aw_underflow, output axi_aw_prog_full, output axi_aw_prog_empty, // AXI Full/Lite Write Data Channel signals input axi_w_injectsbiterr, input axi_w_injectdbiterr, input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh, input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh, output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count, output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count, output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count, output axi_w_sbiterr, output axi_w_dbiterr, output axi_w_overflow, output axi_w_underflow, output axi_w_prog_full, output axi_w_prog_empty, // AXI Full/Lite Write Response Channel signals input axi_b_injectsbiterr, input axi_b_injectdbiterr, input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh, input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh, output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count, output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count, output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count, output axi_b_sbiterr, output axi_b_dbiterr, output axi_b_overflow, output axi_b_underflow, output axi_b_prog_full, output axi_b_prog_empty, // AXI Full/Lite Read Address Channel signals input axi_ar_injectsbiterr, input axi_ar_injectdbiterr, input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh, input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh, output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count, output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count, output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count, output axi_ar_sbiterr, output axi_ar_dbiterr, output axi_ar_overflow, output axi_ar_underflow, output axi_ar_prog_full, output axi_ar_prog_empty, // AXI Full/Lite Read Data Channel Signals input axi_r_injectsbiterr, input axi_r_injectdbiterr, input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh, input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh, output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count, output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count, output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count, output axi_r_sbiterr, output axi_r_dbiterr, output axi_r_overflow, output axi_r_underflow, output axi_r_prog_full, output axi_r_prog_empty, // AXI Streaming FIFO Related Signals input axis_injectsbiterr, input axis_injectdbiterr, input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh, input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh, output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count, output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count, output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count, output axis_sbiterr, output axis_dbiterr, output axis_overflow, output axis_underflow, output axis_prog_full, output axis_prog_empty ); wire BACKUP; wire BACKUP_MARKER; wire CLK; wire RST; wire SRST; wire WR_CLK; wire WR_RST; wire RD_CLK; wire RD_RST; wire [C_DIN_WIDTH-1:0] DIN; wire WR_EN; wire RD_EN; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; wire INT_CLK; wire INJECTDBITERR; wire INJECTSBITERR; wire SLEEP; wire [C_DOUT_WIDTH-1:0] DOUT; wire FULL; wire ALMOST_FULL; wire WR_ACK; wire OVERFLOW; wire EMPTY; wire ALMOST_EMPTY; wire VALID; wire UNDERFLOW; wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; wire PROG_FULL; wire PROG_EMPTY; wire SBITERR; wire DBITERR; wire WR_RST_BUSY; wire RD_RST_BUSY; wire M_ACLK; wire S_ACLK; wire S_ARESETN; wire S_ACLK_EN; wire M_ACLK_EN; wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID; wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR; wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN; wire [3-1:0] S_AXI_AWSIZE; wire [2-1:0] S_AXI_AWBURST; wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK; wire [4-1:0] S_AXI_AWCACHE; wire [3-1:0] S_AXI_AWPROT; wire [4-1:0] S_AXI_AWQOS; wire [4-1:0] S_AXI_AWREGION; wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER; wire S_AXI_AWVALID; wire S_AXI_AWREADY; wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID; wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA; wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB; wire S_AXI_WLAST; wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER; wire S_AXI_WVALID; wire S_AXI_WREADY; wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID; wire [2-1:0] S_AXI_BRESP; wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER; wire S_AXI_BVALID; wire S_AXI_BREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID; wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR; wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN; wire [3-1:0] M_AXI_AWSIZE; wire [2-1:0] M_AXI_AWBURST; wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK; wire [4-1:0] M_AXI_AWCACHE; wire [3-1:0] M_AXI_AWPROT; wire [4-1:0] M_AXI_AWQOS; wire [4-1:0] M_AXI_AWREGION; wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER; wire M_AXI_AWVALID; wire M_AXI_AWREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID; wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA; wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB; wire M_AXI_WLAST; wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER; wire M_AXI_WVALID; wire M_AXI_WREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID; wire [2-1:0] M_AXI_BRESP; wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER; wire M_AXI_BVALID; wire M_AXI_BREADY; wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID; wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR; wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN; wire [3-1:0] S_AXI_ARSIZE; wire [2-1:0] S_AXI_ARBURST; wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK; wire [4-1:0] S_AXI_ARCACHE; wire [3-1:0] S_AXI_ARPROT; wire [4-1:0] S_AXI_ARQOS; wire [4-1:0] S_AXI_ARREGION; wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER; wire S_AXI_ARVALID; wire S_AXI_ARREADY; wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA; wire [2-1:0] S_AXI_RRESP; wire S_AXI_RLAST; wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER; wire S_AXI_RVALID; wire S_AXI_RREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID; wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR; wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN; wire [3-1:0] M_AXI_ARSIZE; wire [2-1:0] M_AXI_ARBURST; wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK; wire [4-1:0] M_AXI_ARCACHE; wire [3-1:0] M_AXI_ARPROT; wire [4-1:0] M_AXI_ARQOS; wire [4-1:0] M_AXI_ARREGION; wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER; wire M_AXI_ARVALID; wire M_AXI_ARREADY; wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID; wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA; wire [2-1:0] M_AXI_RRESP; wire M_AXI_RLAST; wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER; wire M_AXI_RVALID; wire M_AXI_RREADY; wire S_AXIS_TVALID; wire S_AXIS_TREADY; wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA; wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB; wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP; wire S_AXIS_TLAST; wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID; wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST; wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER; wire M_AXIS_TVALID; wire M_AXIS_TREADY; wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA; wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB; wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP; wire M_AXIS_TLAST; wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID; wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST; wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER; wire AXI_AW_INJECTSBITERR; wire AXI_AW_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT; wire AXI_AW_SBITERR; wire AXI_AW_DBITERR; wire AXI_AW_OVERFLOW; wire AXI_AW_UNDERFLOW; wire AXI_AW_PROG_FULL; wire AXI_AW_PROG_EMPTY; wire AXI_W_INJECTSBITERR; wire AXI_W_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT; wire AXI_W_SBITERR; wire AXI_W_DBITERR; wire AXI_W_OVERFLOW; wire AXI_W_UNDERFLOW; wire AXI_W_PROG_FULL; wire AXI_W_PROG_EMPTY; wire AXI_B_INJECTSBITERR; wire AXI_B_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT; wire AXI_B_SBITERR; wire AXI_B_DBITERR; wire AXI_B_OVERFLOW; wire AXI_B_UNDERFLOW; wire AXI_B_PROG_FULL; wire AXI_B_PROG_EMPTY; wire AXI_AR_INJECTSBITERR; wire AXI_AR_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT; wire AXI_AR_SBITERR; wire AXI_AR_DBITERR; wire AXI_AR_OVERFLOW; wire AXI_AR_UNDERFLOW; wire AXI_AR_PROG_FULL; wire AXI_AR_PROG_EMPTY; wire AXI_R_INJECTSBITERR; wire AXI_R_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT; wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT; wire AXI_R_SBITERR; wire AXI_R_DBITERR; wire AXI_R_OVERFLOW; wire AXI_R_UNDERFLOW; wire AXI_R_PROG_FULL; wire AXI_R_PROG_EMPTY; wire AXIS_INJECTSBITERR; wire AXIS_INJECTDBITERR; wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH; wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT; wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT; wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT; wire AXIS_SBITERR; wire AXIS_DBITERR; wire AXIS_OVERFLOW; wire AXIS_UNDERFLOW; wire AXIS_PROG_FULL; wire AXIS_PROG_EMPTY; wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in; wire wr_rst_int; wire rd_rst_int; wire wr_rst_busy_o; wire wr_rst_busy_ntve; wire wr_rst_busy_axis; wire wr_rst_busy_wach; wire wr_rst_busy_wdch; wire wr_rst_busy_wrch; wire wr_rst_busy_rach; wire wr_rst_busy_rdch; function integer find_log2; input integer int_val; integer i,j; begin i = 1; j = 0; for (i = 1; i < int_val; i = i*2) begin j = j + 1; end find_log2 = j; end endfunction // Conventional FIFO Interface Signals assign BACKUP = backup; assign BACKUP_MARKER = backup_marker; assign CLK = clk; assign RST = rst; assign SRST = srst; assign WR_CLK = wr_clk; assign WR_RST = wr_rst; assign RD_CLK = rd_clk; assign RD_RST = rd_rst; assign WR_EN = wr_en; assign RD_EN = rd_en; assign INT_CLK = int_clk; assign INJECTDBITERR = injectdbiterr; assign INJECTSBITERR = injectsbiterr; assign SLEEP = sleep; assign full = FULL; assign almost_full = ALMOST_FULL; assign wr_ack = WR_ACK; assign overflow = OVERFLOW; assign empty = EMPTY; assign almost_empty = ALMOST_EMPTY; assign valid = VALID; assign underflow = UNDERFLOW; assign prog_full = PROG_FULL; assign prog_empty = PROG_EMPTY; assign sbiterr = SBITERR; assign dbiterr = DBITERR; // assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o; assign wr_rst_busy = wr_rst_busy_o; assign rd_rst_busy = RD_RST_BUSY; assign M_ACLK = m_aclk; assign S_ACLK = s_aclk; assign S_ARESETN = s_aresetn; assign S_ACLK_EN = s_aclk_en; assign M_ACLK_EN = m_aclk_en; assign S_AXI_AWVALID = s_axi_awvalid; assign s_axi_awready = S_AXI_AWREADY; assign S_AXI_WLAST = s_axi_wlast; assign S_AXI_WVALID = s_axi_wvalid; assign s_axi_wready = S_AXI_WREADY; assign s_axi_bvalid = S_AXI_BVALID; assign S_AXI_BREADY = s_axi_bready; assign m_axi_awvalid = M_AXI_AWVALID; assign M_AXI_AWREADY = m_axi_awready; assign m_axi_wlast = M_AXI_WLAST; assign m_axi_wvalid = M_AXI_WVALID; assign M_AXI_WREADY = m_axi_wready; assign M_AXI_BVALID = m_axi_bvalid; assign m_axi_bready = M_AXI_BREADY; assign S_AXI_ARVALID = s_axi_arvalid; assign s_axi_arready = S_AXI_ARREADY; assign s_axi_rlast = S_AXI_RLAST; assign s_axi_rvalid = S_AXI_RVALID; assign S_AXI_RREADY = s_axi_rready; assign m_axi_arvalid = M_AXI_ARVALID; assign M_AXI_ARREADY = m_axi_arready; assign M_AXI_RLAST = m_axi_rlast; assign M_AXI_RVALID = m_axi_rvalid; assign m_axi_rready = M_AXI_RREADY; assign S_AXIS_TVALID = s_axis_tvalid; assign s_axis_tready = S_AXIS_TREADY; assign S_AXIS_TLAST = s_axis_tlast; assign m_axis_tvalid = M_AXIS_TVALID; assign M_AXIS_TREADY = m_axis_tready; assign m_axis_tlast = M_AXIS_TLAST; assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr; assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr; assign axi_aw_sbiterr = AXI_AW_SBITERR; assign axi_aw_dbiterr = AXI_AW_DBITERR; assign axi_aw_overflow = AXI_AW_OVERFLOW; assign axi_aw_underflow = AXI_AW_UNDERFLOW; assign axi_aw_prog_full = AXI_AW_PROG_FULL; assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY; assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr; assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr; assign axi_w_sbiterr = AXI_W_SBITERR; assign axi_w_dbiterr = AXI_W_DBITERR; assign axi_w_overflow = AXI_W_OVERFLOW; assign axi_w_underflow = AXI_W_UNDERFLOW; assign axi_w_prog_full = AXI_W_PROG_FULL; assign axi_w_prog_empty = AXI_W_PROG_EMPTY; assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr; assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr; assign axi_b_sbiterr = AXI_B_SBITERR; assign axi_b_dbiterr = AXI_B_DBITERR; assign axi_b_overflow = AXI_B_OVERFLOW; assign axi_b_underflow = AXI_B_UNDERFLOW; assign axi_b_prog_full = AXI_B_PROG_FULL; assign axi_b_prog_empty = AXI_B_PROG_EMPTY; assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr; assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr; assign axi_ar_sbiterr = AXI_AR_SBITERR; assign axi_ar_dbiterr = AXI_AR_DBITERR; assign axi_ar_overflow = AXI_AR_OVERFLOW; assign axi_ar_underflow = AXI_AR_UNDERFLOW; assign axi_ar_prog_full = AXI_AR_PROG_FULL; assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY; assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr; assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr; assign axi_r_sbiterr = AXI_R_SBITERR; assign axi_r_dbiterr = AXI_R_DBITERR; assign axi_r_overflow = AXI_R_OVERFLOW; assign axi_r_underflow = AXI_R_UNDERFLOW; assign axi_r_prog_full = AXI_R_PROG_FULL; assign axi_r_prog_empty = AXI_R_PROG_EMPTY; assign AXIS_INJECTSBITERR = axis_injectsbiterr; assign AXIS_INJECTDBITERR = axis_injectdbiterr; assign axis_sbiterr = AXIS_SBITERR; assign axis_dbiterr = AXIS_DBITERR; assign axis_overflow = AXIS_OVERFLOW; assign axis_underflow = AXIS_UNDERFLOW; assign axis_prog_full = AXIS_PROG_FULL; assign axis_prog_empty = AXIS_PROG_EMPTY; assign DIN = din; assign PROG_EMPTY_THRESH = prog_empty_thresh; assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert; assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate; assign PROG_FULL_THRESH = prog_full_thresh; assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert; assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate; assign dout = DOUT; assign data_count = DATA_COUNT; assign rd_data_count = RD_DATA_COUNT; assign wr_data_count = WR_DATA_COUNT; assign S_AXI_AWID = s_axi_awid; assign S_AXI_AWADDR = s_axi_awaddr; assign S_AXI_AWLEN = s_axi_awlen; assign S_AXI_AWSIZE = s_axi_awsize; assign S_AXI_AWBURST = s_axi_awburst; assign S_AXI_AWLOCK = s_axi_awlock; assign S_AXI_AWCACHE = s_axi_awcache; assign S_AXI_AWPROT = s_axi_awprot; assign S_AXI_AWQOS = s_axi_awqos; assign S_AXI_AWREGION = s_axi_awregion; assign S_AXI_AWUSER = s_axi_awuser; assign S_AXI_WID = s_axi_wid; assign S_AXI_WDATA = s_axi_wdata; assign S_AXI_WSTRB = s_axi_wstrb; assign S_AXI_WUSER = s_axi_wuser; assign s_axi_bid = S_AXI_BID; assign s_axi_bresp = S_AXI_BRESP; assign s_axi_buser = S_AXI_BUSER; assign m_axi_awid = M_AXI_AWID; assign m_axi_awaddr = M_AXI_AWADDR; assign m_axi_awlen = M_AXI_AWLEN; assign m_axi_awsize = M_AXI_AWSIZE; assign m_axi_awburst = M_AXI_AWBURST; assign m_axi_awlock = M_AXI_AWLOCK; assign m_axi_awcache = M_AXI_AWCACHE; assign m_axi_awprot = M_AXI_AWPROT; assign m_axi_awqos = M_AXI_AWQOS; assign m_axi_awregion = M_AXI_AWREGION; assign m_axi_awuser = M_AXI_AWUSER; assign m_axi_wid = M_AXI_WID; assign m_axi_wdata = M_AXI_WDATA; assign m_axi_wstrb = M_AXI_WSTRB; assign m_axi_wuser = M_AXI_WUSER; assign M_AXI_BID = m_axi_bid; assign M_AXI_BRESP = m_axi_bresp; assign M_AXI_BUSER = m_axi_buser; assign S_AXI_ARID = s_axi_arid; assign S_AXI_ARADDR = s_axi_araddr; assign S_AXI_ARLEN = s_axi_arlen; assign S_AXI_ARSIZE = s_axi_arsize; assign S_AXI_ARBURST = s_axi_arburst; assign S_AXI_ARLOCK = s_axi_arlock; assign S_AXI_ARCACHE = s_axi_arcache; assign S_AXI_ARPROT = s_axi_arprot; assign S_AXI_ARQOS = s_axi_arqos; assign S_AXI_ARREGION = s_axi_arregion; assign S_AXI_ARUSER = s_axi_aruser; assign s_axi_rid = S_AXI_RID; assign s_axi_rdata = S_AXI_RDATA; assign s_axi_rresp = S_AXI_RRESP; assign s_axi_ruser = S_AXI_RUSER; assign m_axi_arid = M_AXI_ARID; assign m_axi_araddr = M_AXI_ARADDR; assign m_axi_arlen = M_AXI_ARLEN; assign m_axi_arsize = M_AXI_ARSIZE; assign m_axi_arburst = M_AXI_ARBURST; assign m_axi_arlock = M_AXI_ARLOCK; assign m_axi_arcache = M_AXI_ARCACHE; assign m_axi_arprot = M_AXI_ARPROT; assign m_axi_arqos = M_AXI_ARQOS; assign m_axi_arregion = M_AXI_ARREGION; assign m_axi_aruser = M_AXI_ARUSER; assign M_AXI_RID = m_axi_rid; assign M_AXI_RDATA = m_axi_rdata; assign M_AXI_RRESP = m_axi_rresp; assign M_AXI_RUSER = m_axi_ruser; assign S_AXIS_TDATA = s_axis_tdata; assign S_AXIS_TSTRB = s_axis_tstrb; assign S_AXIS_TKEEP = s_axis_tkeep; assign S_AXIS_TID = s_axis_tid; assign S_AXIS_TDEST = s_axis_tdest; assign S_AXIS_TUSER = s_axis_tuser; assign m_axis_tdata = M_AXIS_TDATA; assign m_axis_tstrb = M_AXIS_TSTRB; assign m_axis_tkeep = M_AXIS_TKEEP; assign m_axis_tid = M_AXIS_TID; assign m_axis_tdest = M_AXIS_TDEST; assign m_axis_tuser = M_AXIS_TUSER; assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh; assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh; assign axi_aw_data_count = AXI_AW_DATA_COUNT; assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT; assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT; assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh; assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh; assign axi_w_data_count = AXI_W_DATA_COUNT; assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT; assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT; assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh; assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh; assign axi_b_data_count = AXI_B_DATA_COUNT; assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT; assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT; assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh; assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh; assign axi_ar_data_count = AXI_AR_DATA_COUNT; assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT; assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT; assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh; assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh; assign axi_r_data_count = AXI_R_DATA_COUNT; assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT; assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT; assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh; assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh; assign axis_data_count = AXIS_DATA_COUNT; assign axis_wr_data_count = AXIS_WR_DATA_COUNT; assign axis_rd_data_count = AXIS_RD_DATA_COUNT; generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo fifo_generator_v13_1_3_CONV_VER #( .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_FAMILY (C_FAMILY), .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_RD_RST (C_HAS_RD_RST), .C_HAS_RST (C_HAS_RST), .C_HAS_SRST (C_HAS_SRST), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_HAS_VALID (C_HAS_VALID), .C_HAS_WR_ACK (C_HAS_WR_ACK), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_HAS_WR_RST (C_HAS_WR_RST), .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), .C_PRELOAD_REGS (C_PRELOAD_REGS), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_FREQ (C_RD_FREQ), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_ECC (C_USE_ECC), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), .C_VALID_LOW (C_VALID_LOW), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_FREQ (C_WR_FREQ), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE), .C_AXI_TYPE (C_AXI_TYPE), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE) ) fifo_generator_v13_1_3_conv_dut ( .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .CLK (CLK), .RST (RST), .SRST (SRST), .WR_CLK (WR_CLK), .WR_RST (WR_RST), .RD_CLK (RD_CLK), .RD_RST (RD_RST), .DIN (DIN), .WR_EN (WR_EN), .RD_EN (RD_EN), .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), .PROG_FULL_THRESH (PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), .INT_CLK (INT_CLK), .INJECTDBITERR (INJECTDBITERR), .INJECTSBITERR (INJECTSBITERR), .DOUT (DOUT), .FULL (FULL), .ALMOST_FULL (ALMOST_FULL), .WR_ACK (WR_ACK), .OVERFLOW (OVERFLOW), .EMPTY (EMPTY), .ALMOST_EMPTY (ALMOST_EMPTY), .VALID (VALID), .UNDERFLOW (UNDERFLOW), .DATA_COUNT (DATA_COUNT), .RD_DATA_COUNT (RD_DATA_COUNT), .WR_DATA_COUNT (wr_data_count_in), .PROG_FULL (PROG_FULL), .PROG_EMPTY (PROG_EMPTY), .SBITERR (SBITERR), .DBITERR (DBITERR), .wr_rst_busy_o (wr_rst_busy_o), .wr_rst_busy (wr_rst_busy_i), .rd_rst_busy (rd_rst_busy), .wr_rst_i_out (wr_rst_int), .rd_rst_i_out (rd_rst_int) ); end endgenerate localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0; localparam C_AXI_SIZE_WIDTH = 3; localparam C_AXI_BURST_WIDTH = 2; localparam C_AXI_CACHE_WIDTH = 4; localparam C_AXI_PROT_WIDTH = 3; localparam C_AXI_QOS_WIDTH = 4; localparam C_AXI_REGION_WIDTH = 4; localparam C_AXI_BRESP_WIDTH = 2; localparam C_AXI_RRESP_WIDTH = 2; localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0; localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS; localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET; localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET; localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET; localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET; localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET; localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS); localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH); function [LOG_DEPTH_AXIS-1:0] bin2gray; input [LOG_DEPTH_AXIS-1:0] x; begin bin2gray = x ^ (x>>1); end endfunction function [LOG_DEPTH_AXIS-1:0] gray2bin; input [LOG_DEPTH_AXIS-1:0] x; integer i; begin gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1]; for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin gray2bin[i] = gray2bin[i+1] ^ x[i]; end end endfunction wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last; wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ; wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ; reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0; reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0; reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0; reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0; wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad; wire [LOG_WR_DEPTH : 0] r_inv_pad; wire [LOG_WR_DEPTH-1 : 0] d_cnt; reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0; reg adj_w_cnt_rd_pad_0 = 0; reg r_inv_pad_0 = 0; genvar l; generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage fifo_generator_v13_1_3_sync_stage #( .C_WIDTH (LOG_WR_DEPTH) ) rd_stg_inst ( .RST (rd_rst_int), .CLK (RD_CLK), .DIN (w_q[l-1]), .DOUT (w_q[l]) ); end endgenerate // gpkt_cnt_sync_stage generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter assign wr_eop_ad = WR_EN & !(FULL); assign rd_eop_ad = RD_EN & !(EMPTY); always @ (posedge wr_rst_int or posedge WR_CLK) begin if (wr_rst_int) w_cnt <= 1'b0; else if (wr_eop_ad) w_cnt <= w_cnt + 1; end always @ (posedge wr_rst_int or posedge WR_CLK) begin if (wr_rst_int) w_cnt_gc <= 1'b0; else w_cnt_gc <= bin2gray(w_cnt); end assign w_q[0] = w_cnt_gc; assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE]; always @ (posedge rd_rst_int or posedge RD_CLK) begin if (rd_rst_int) w_cnt_rd <= 1'b0; else w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last); end always @ (posedge rd_rst_int or posedge RD_CLK) begin if (rd_rst_int) r_cnt <= 1'b0; else if (rd_eop_ad) r_cnt <= r_cnt + 1; end // Take the difference of write and read packet count // Logic is similar to rd_pe_as assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd; assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt; assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0; assign r_inv_pad[0] = r_inv_pad_0; always @ ( rd_eop_ad ) begin if (!rd_eop_ad) begin adj_w_cnt_rd_pad_0 <= 1'b1; r_inv_pad_0 <= 1'b1; end else begin adj_w_cnt_rd_pad_0 <= 1'b0; r_inv_pad_0 <= 1'b0; end end always @ (posedge rd_rst_int or posedge RD_CLK) begin if (rd_rst_int) d_cnt_pad <= 1'b0; else d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ; end assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ; assign WR_DATA_COUNT = d_cnt; end endgenerate // fifo_ic_adapter generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter assign WR_DATA_COUNT = wr_data_count_in; end endgenerate // fifo_icn_adapter wire inverted_reset = ~S_ARESETN; wire axi_rs_rst; wire [C_DIN_WIDTH_AXIS-1:0] axis_din ; wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ; wire axis_full ; wire axis_almost_full ; wire axis_empty ; wire axis_s_axis_tready; wire axis_m_axis_tvalid; wire axis_wr_en ; wire axis_rd_en ; wire axis_we ; wire axis_re ; wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc; reg axis_pkt_read = 1'b0; wire axis_rd_rst; wire axis_wr_rst; generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 || C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst reg rst_d1 = 0 ; reg rst_d2 = 0 ; reg [3:0] axi_rst = 4'h0 ; always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) begin rst_d1 <= 1'b1; rst_d2 <= 1'b1; axi_rst <= 4'hf; end else begin rst_d1 <= #`TCQ 1'b0; rst_d2 <= #`TCQ rst_d1; axi_rst <= #`TCQ {axi_rst[2:0],1'b0}; end end assign axi_rs_rst = axi_rst[3];//rst_d2; end endgenerate // gaxi_rs_rst generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming // Write protection when almost full or prog_full is high assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID; // Read protection when almost empty or prog_empty is high assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY : (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY; assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we; assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re; fifo_generator_v13_1_3_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : (C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 : (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_AXIS), .C_WR_DEPTH (C_WR_DEPTH_AXIS), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS), .C_DOUT_WIDTH (C_DIN_WIDTH_AXIS), .C_RD_DEPTH (C_WR_DEPTH_AXIS), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS), .C_USE_ECC (C_USE_ECC_AXIS), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_3_axis_dut ( .CLK (S_ACLK), .WR_CLK (S_ACLK), .RD_CLK (M_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (axis_wr_en), .RD_EN (axis_rd_en), .PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), .PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), .INJECTDBITERR (AXIS_INJECTDBITERR), .INJECTSBITERR (AXIS_INJECTSBITERR), .DIN (axis_din), .DOUT (axis_dout), .FULL (axis_full), .EMPTY (axis_empty), .ALMOST_FULL (axis_almost_full), .PROG_FULL (AXIS_PROG_FULL), .ALMOST_EMPTY (), .PROG_EMPTY (AXIS_PROG_EMPTY), .WR_ACK (), .OVERFLOW (AXIS_OVERFLOW), .VALID (), .UNDERFLOW (AXIS_UNDERFLOW), .DATA_COUNT (axis_dc), .RD_DATA_COUNT (AXIS_RD_DATA_COUNT), .WR_DATA_COUNT (AXIS_WR_DATA_COUNT), .SBITERR (AXIS_SBITERR), .DBITERR (AXIS_DBITERR), .wr_rst_busy (wr_rst_busy_axis), .rd_rst_busy (rd_rst_busy_axis), .wr_rst_i_out (axis_wr_rst), .rd_rst_i_out (axis_rd_rst), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full; assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read; assign S_AXIS_TREADY = axis_s_axis_tready; assign M_AXIS_TVALID = axis_m_axis_tvalid; end endgenerate // axi_streaming wire axis_wr_eop; reg axis_wr_eop_d1 = 1'b0; wire axis_rd_eop; integer axis_pkt_cnt; generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST; assign axis_rd_eop = axis_rd_en & axis_dout[0]; always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) axis_pkt_read <= 1'b0; else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1) axis_pkt_read <= 1'b0; else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty)) axis_pkt_read <= 1'b1; end always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) axis_wr_eop_d1 <= 1'b0; else axis_wr_eop_d1 <= axis_wr_eop; end always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) axis_pkt_cnt <= 0; else if (axis_wr_eop_d1 && ~axis_rd_eop) axis_pkt_cnt <= axis_pkt_cnt + 1; else if (axis_rd_eop && ~axis_wr_eop_d1) axis_pkt_cnt <= axis_pkt_cnt - 1; end end endgenerate // gaxis_pkt_fifo_cc reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0; wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last; wire axis_rd_has_rst; wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ; wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ; wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0; wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ; reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0; reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0; reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0; wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad; wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad; wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt; reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0; reg adj_axis_wpkt_cnt_rd_pad_0 = 0; reg rpkt_inv_pad_0 = 0; wire axis_af_rd ; generate if (C_HAS_RST == 1) begin : rst_blk_has assign axis_rd_has_rst = axis_rd_rst; end endgenerate //rst_blk_has generate if (C_HAS_RST == 0) begin :rst_blk_no assign axis_rd_has_rst = 1'b0; end endgenerate //rst_blk_no genvar i; generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage fifo_generator_v13_1_3_sync_stage #( .C_WIDTH (LOG_DEPTH_AXIS) ) rd_stg_inst ( .RST (axis_rd_has_rst), .CLK (M_ACLK), .DIN (wpkt_q[i-1]), .DOUT (wpkt_q[i]) ); fifo_generator_v13_1_3_sync_stage #( .C_WIDTH (1) ) wr_stg_inst ( .RST (axis_rd_has_rst), .CLK (M_ACLK), .DIN (axis_af_q[i-1]), .DOUT (axis_af_q[i]) ); end endgenerate // gpkt_cnt_sync_stage generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST; assign axis_rd_eop = axis_rd_en & axis_dout[0]; always @ (posedge axis_rd_has_rst or posedge M_ACLK) begin if (axis_rd_has_rst) axis_pkt_read <= 1'b0; else if (axis_rd_eop && (diff_pkt_cnt == 1)) axis_pkt_read <= 1'b0; else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty)) axis_pkt_read <= 1'b1; end always @ (posedge axis_wr_rst or posedge S_ACLK) begin if (axis_wr_rst) axis_wpkt_cnt <= 1'b0; else if (axis_wr_eop) axis_wpkt_cnt <= axis_wpkt_cnt + 1; end always @ (posedge axis_wr_rst or posedge S_ACLK) begin if (axis_wr_rst) axis_wpkt_cnt_gc <= 1'b0; else axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt); end assign wpkt_q[0] = axis_wpkt_cnt_gc; assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE]; assign axis_af_q[0] = axis_almost_full; //assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE]; assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE]; always @ (posedge axis_rd_has_rst or posedge M_ACLK) begin if (axis_rd_has_rst) axis_wpkt_cnt_rd <= 1'b0; else axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last); end always @ (posedge axis_rd_rst or posedge M_ACLK) begin if (axis_rd_has_rst) axis_rpkt_cnt <= 1'b0; else if (axis_rd_eop) axis_rpkt_cnt <= axis_rpkt_cnt + 1; end // Take the difference of write and read packet count // Logic is similar to rd_pe_as assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd; assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt; assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0; assign rpkt_inv_pad[0] = rpkt_inv_pad_0; always @ ( axis_rd_eop ) begin if (!axis_rd_eop) begin adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1; rpkt_inv_pad_0 <= 1'b1; end else begin adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0; rpkt_inv_pad_0 <= 1'b0; end end always @ (posedge axis_rd_rst or posedge M_ACLK) begin if (axis_rd_has_rst) diff_pkt_cnt_pad <= 1'b0; else diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ; end assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ; end endgenerate // gaxis_pkt_fifo_ic // Generate the accurate data count for axi stream packet fifo configuration reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0; generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt always @ (posedge inverted_reset or posedge S_ACLK) begin if (inverted_reset) axis_dc_pkt_fifo <= 0; else if (axis_wr_en && (~axis_rd_en)) axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1; else if (~axis_wr_en && axis_rd_en) axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1; end assign AXIS_DATA_COUNT = axis_dc_pkt_fifo; end endgenerate // gdc_pkt generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt assign AXIS_DATA_COUNT = 0; end endgenerate // gndc_pkt generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc assign AXIS_DATA_COUNT = axis_dc; end endgenerate // gdc // Register Slice for Write Address Channel generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID; assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY; fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_AXIS), .C_REG_CONFIG (C_REG_SLICE_MODE_AXIS) ) axis_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (axis_din), .S_VALID (axis_wr_en), .S_READY (S_AXIS_TREADY), // Master side .M_PAYLOAD_DATA (axis_dout), .M_VALID (M_AXIS_TVALID), .M_READY (axis_rd_en) ); end endgenerate // gaxis_reg_slice generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA; assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB; assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP; assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID; assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST; assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER; assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET]; end endgenerate generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast assign axis_din[0] = S_AXIS_TLAST; assign M_AXIS_TLAST = axis_dout[0]; end endgenerate //########################################################################### // AXI FULL Write Channel (axi_write_channel) //########################################################################### localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0; localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0; localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0; localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0; localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0; localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0; localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0; localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH; localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH; localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET; localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET; localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET; localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET; localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET; localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH; localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH; localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET; localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET; localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH; localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH; localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8; localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET; localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH; localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH; localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET; wire [C_DIN_WIDTH_WACH-1:0] wach_din ; wire [C_DIN_WIDTH_WACH-1:0] wach_dout ; wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ; wire wach_full ; wire wach_almost_full ; wire wach_prog_full ; wire wach_empty ; wire wach_almost_empty ; wire wach_prog_empty ; wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ; wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ; wire wdch_full ; wire wdch_almost_full ; wire wdch_prog_full ; wire wdch_empty ; wire wdch_almost_empty ; wire wdch_prog_empty ; wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ; wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ; wire wrch_full ; wire wrch_almost_full ; wire wrch_prog_full ; wire wrch_empty ; wire wrch_almost_empty ; wire wrch_prog_empty ; wire axi_aw_underflow_i; wire axi_w_underflow_i ; wire axi_b_underflow_i ; wire axi_aw_overflow_i ; wire axi_w_overflow_i ; wire axi_b_overflow_i ; wire axi_wr_underflow_i; wire axi_wr_overflow_i ; wire wach_s_axi_awready; wire wach_m_axi_awvalid; wire wach_wr_en ; wire wach_rd_en ; wire wdch_s_axi_wready ; wire wdch_m_axi_wvalid ; wire wdch_wr_en ; wire wdch_rd_en ; wire wrch_s_axi_bvalid ; wire wrch_m_axi_bready ; wire wrch_wr_en ; wire wrch_rd_en ; wire txn_count_up ; wire txn_count_down ; wire awvalid_en ; wire awvalid_pkt ; wire awready_pkt ; integer wr_pkt_count ; wire wach_we ; wire wach_re ; wire wdch_we ; wire wdch_re ; wire wrch_we ; wire wrch_re ; generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel // Write protection when almost full or prog_full is high assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID; // Read protection when almost empty or prog_empty is high assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? wach_m_axi_awvalid & awready_pkt & awvalid_en : (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? M_AXI_AWREADY && wach_m_axi_awvalid : (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? awready_pkt & awvalid_en : (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? M_AXI_AWREADY : 1'b0; assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we; assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re; fifo_generator_v13_1_3_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_WACH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_WR_DEPTH (C_WR_DEPTH_WACH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH), .C_DOUT_WIDTH (C_DIN_WIDTH_WACH), .C_RD_DEPTH (C_WR_DEPTH_WACH), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH), .C_USE_ECC (C_USE_ECC_WACH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_3_wach_dut ( .CLK (S_ACLK), .WR_CLK (S_ACLK), .RD_CLK (M_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (wach_wr_en), .RD_EN (wach_rd_en), .PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}), .PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}), .INJECTDBITERR (AXI_AW_INJECTDBITERR), .INJECTSBITERR (AXI_AW_INJECTSBITERR), .DIN (wach_din), .DOUT (wach_dout_pkt), .FULL (wach_full), .EMPTY (wach_empty), .ALMOST_FULL (), .PROG_FULL (AXI_AW_PROG_FULL), .ALMOST_EMPTY (), .PROG_EMPTY (AXI_AW_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_aw_overflow_i), .VALID (), .UNDERFLOW (axi_aw_underflow_i), .DATA_COUNT (AXI_AW_DATA_COUNT), .RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT), .SBITERR (AXI_AW_SBITERR), .DBITERR (AXI_AW_DBITERR), .wr_rst_busy (wr_rst_busy_wach), .rd_rst_busy (rd_rst_busy_wach), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full; assign wach_m_axi_awvalid = ~wach_empty; assign S_AXI_AWREADY = wach_s_axi_awready; assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0; assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0; end endgenerate // axi_write_address_channel // Register Slice for Write Address Channel generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_WACH), .C_REG_CONFIG (C_REG_SLICE_MODE_WACH) ) wach_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (wach_din), .S_VALID (S_AXI_AWVALID), .S_READY (S_AXI_AWREADY), // Master side .M_PAYLOAD_DATA (wach_dout), .M_VALID (M_AXI_AWVALID), .M_READY (M_AXI_AWREADY) ); end endgenerate // gwach_reg_slice generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_WACH), .C_REG_CONFIG (1) ) wach_pkt_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (inverted_reset), // Slave side .S_PAYLOAD_DATA (wach_dout_pkt), .S_VALID (awvalid_pkt), .S_READY (awready_pkt), // Master side .M_PAYLOAD_DATA (wach_dout), .M_VALID (M_AXI_AWVALID), .M_READY (M_AXI_AWREADY) ); assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en; assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en; always@(posedge S_ACLK or posedge inverted_reset) begin if(inverted_reset == 1) begin wr_pkt_count <= 0; end else begin if(txn_count_up == 1 && txn_count_down == 0) begin wr_pkt_count <= wr_pkt_count + 1; end else if(txn_count_up == 0 && txn_count_down == 1) begin wr_pkt_count <= wr_pkt_count - 1; end end end //Always end assign awvalid_en = (wr_pkt_count > 0)?1:0; end endgenerate generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr assign awvalid_en = 1; assign wach_dout = wach_dout_pkt; assign M_AXI_AWVALID = wach_m_axi_awvalid; end endgenerate generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel // Write protection when almost full or prog_full is high assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID; // Read protection when almost empty or prog_empty is high assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY; assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we; assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re; fifo_generator_v13_1_3_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_WDCH), .C_WR_DEPTH (C_WR_DEPTH_WDCH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH), .C_DOUT_WIDTH (C_DIN_WIDTH_WDCH), .C_RD_DEPTH (C_WR_DEPTH_WDCH), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH), .C_USE_ECC (C_USE_ECC_WDCH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_3_wdch_dut ( .CLK (S_ACLK), .WR_CLK (S_ACLK), .RD_CLK (M_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (wdch_wr_en), .RD_EN (wdch_rd_en), .PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), .PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), .INJECTDBITERR (AXI_W_INJECTDBITERR), .INJECTSBITERR (AXI_W_INJECTSBITERR), .DIN (wdch_din), .DOUT (wdch_dout), .FULL (wdch_full), .EMPTY (wdch_empty), .ALMOST_FULL (), .PROG_FULL (AXI_W_PROG_FULL), .ALMOST_EMPTY (), .PROG_EMPTY (AXI_W_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_w_overflow_i), .VALID (), .UNDERFLOW (axi_w_underflow_i), .DATA_COUNT (AXI_W_DATA_COUNT), .RD_DATA_COUNT (AXI_W_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_W_WR_DATA_COUNT), .SBITERR (AXI_W_SBITERR), .DBITERR (AXI_W_DBITERR), .wr_rst_busy (wr_rst_busy_wdch), .rd_rst_busy (rd_rst_busy_wdch), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full; assign wdch_m_axi_wvalid = ~wdch_empty; assign S_AXI_WREADY = wdch_s_axi_wready; assign M_AXI_WVALID = wdch_m_axi_wvalid; assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0; assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0; end endgenerate // axi_write_data_channel // Register Slice for Write Data Channel generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_WDCH), .C_REG_CONFIG (C_REG_SLICE_MODE_WDCH) ) wdch_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (wdch_din), .S_VALID (S_AXI_WVALID), .S_READY (S_AXI_WREADY), // Master side .M_PAYLOAD_DATA (wdch_dout), .M_VALID (M_AXI_WVALID), .M_READY (M_AXI_WREADY) ); end endgenerate // gwdch_reg_slice generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel // Write protection when almost full or prog_full is high assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID; // Read protection when almost empty or prog_empty is high assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY; assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we; assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re; fifo_generator_v13_1_3_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_WRCH), .C_WR_DEPTH (C_WR_DEPTH_WRCH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH), .C_DOUT_WIDTH (C_DIN_WIDTH_WRCH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_RD_DEPTH (C_WR_DEPTH_WRCH), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH), .C_USE_ECC (C_USE_ECC_WRCH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_3_wrch_dut ( .CLK (S_ACLK), .WR_CLK (M_ACLK), .RD_CLK (S_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (wrch_wr_en), .RD_EN (wrch_rd_en), .PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), .PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), .INJECTDBITERR (AXI_B_INJECTDBITERR), .INJECTSBITERR (AXI_B_INJECTSBITERR), .DIN (wrch_din), .DOUT (wrch_dout), .FULL (wrch_full), .EMPTY (wrch_empty), .ALMOST_FULL (), .ALMOST_EMPTY (), .PROG_FULL (AXI_B_PROG_FULL), .PROG_EMPTY (AXI_B_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_b_overflow_i), .VALID (), .UNDERFLOW (axi_b_underflow_i), .DATA_COUNT (AXI_B_DATA_COUNT), .RD_DATA_COUNT (AXI_B_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_B_WR_DATA_COUNT), .SBITERR (AXI_B_SBITERR), .DBITERR (AXI_B_DBITERR), .wr_rst_busy (wr_rst_busy_wrch), .rd_rst_busy (rd_rst_busy_wrch), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign wrch_s_axi_bvalid = ~wrch_empty; assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full; assign S_AXI_BVALID = wrch_s_axi_bvalid; assign M_AXI_BREADY = wrch_m_axi_bready; assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0; assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0; end endgenerate // axi_write_resp_channel // Register Slice for Write Response Channel generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_WRCH), .C_REG_CONFIG (C_REG_SLICE_MODE_WRCH) ) wrch_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (wrch_din), .S_VALID (M_AXI_BVALID), .S_READY (M_AXI_BREADY), // Master side .M_PAYLOAD_DATA (wrch_dout), .M_VALID (S_AXI_BVALID), .M_READY (S_AXI_BREADY) ); end endgenerate // gwrch_reg_slice assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0; assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0; generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET]; assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET]; assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET]; assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET]; assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET]; assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET]; assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET]; assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET]; assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR; assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN; assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE; assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST; assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK; assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE; assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT; assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS; end endgenerate // axi_wach_output generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET]; end endgenerate // axi_awregion generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion assign M_AXI_AWREGION = 0; end endgenerate // naxi_awregion generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET]; end endgenerate // axi_awuser generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser assign M_AXI_AWUSER = 0; end endgenerate // naxi_awuser generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET]; end endgenerate //axi_awid generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid assign M_AXI_AWID = 0; end endgenerate //naxi_awid generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET]; assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET]; assign M_AXI_WLAST = wdch_dout[0]; assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA; assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB; assign wdch_din[0] = S_AXI_WLAST; end endgenerate // axi_wdch_output generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET]; end endgenerate generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin assign M_AXI_WID = 0; end endgenerate generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET]; end endgenerate generate if (C_HAS_AXI_WUSER == 0) begin assign M_AXI_WUSER = 0; end endgenerate generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP; end endgenerate // axi_wrch_output generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET]; end endgenerate // axi_buser generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser assign S_AXI_BUSER = 0; end endgenerate // naxi_buser generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET]; end endgenerate // axi_bid generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid assign S_AXI_BID = 0 ; end endgenerate // naxi_bid generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1 assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT}; assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET]; assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET]; end endgenerate // axi_wach_output1 generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1 assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB}; assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET]; assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET]; end endgenerate // axi_wdch_output1 generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1 assign wrch_din = M_AXI_BRESP; assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; end endgenerate // axi_wrch_output1 generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1 assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER; end endgenerate // gwach_din1 generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2 assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID; end endgenerate // gwach_din2 generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3 assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION; end endgenerate // gwach_din3 generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1 assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER; end endgenerate // gwdch_din1 generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2 assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID; end endgenerate // gwdch_din2 generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1 assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER; end endgenerate // gwrch_din1 generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2 assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID; end endgenerate // gwrch_din2 //end of axi_write_channel //########################################################################### // AXI FULL Read Channel (axi_read_channel) //########################################################################### wire [C_DIN_WIDTH_RACH-1:0] rach_din ; wire [C_DIN_WIDTH_RACH-1:0] rach_dout ; wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ; wire rach_full ; wire rach_almost_full ; wire rach_prog_full ; wire rach_empty ; wire rach_almost_empty ; wire rach_prog_empty ; wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ; wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ; wire rdch_full ; wire rdch_almost_full ; wire rdch_prog_full ; wire rdch_empty ; wire rdch_almost_empty ; wire rdch_prog_empty ; wire axi_ar_underflow_i ; wire axi_r_underflow_i ; wire axi_ar_overflow_i ; wire axi_r_overflow_i ; wire axi_rd_underflow_i ; wire axi_rd_overflow_i ; wire rach_s_axi_arready ; wire rach_m_axi_arvalid ; wire rach_wr_en ; wire rach_rd_en ; wire rdch_m_axi_rready ; wire rdch_s_axi_rvalid ; wire rdch_wr_en ; wire rdch_rd_en ; wire arvalid_pkt ; wire arready_pkt ; wire arvalid_en ; wire rdch_rd_ok ; wire accept_next_pkt ; integer rdch_free_space ; integer rdch_commited_space ; wire rach_we ; wire rach_re ; wire rdch_we ; wire rdch_re ; localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH; localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH; localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET; localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET; localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET; localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET; localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET; localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH; localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH; localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET; localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET; localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH; localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH; localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH; localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET; generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel // Write protection when almost full or prog_full is high assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID; // Read protection when almost empty or prog_empty is high // assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en; assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? rach_m_axi_arvalid & arready_pkt & arvalid_en : (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? M_AXI_ARREADY && rach_m_axi_arvalid : (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? arready_pkt & arvalid_en : (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? M_AXI_ARREADY : 1'b0; assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we; assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re; fifo_generator_v13_1_3_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_RACH), .C_WR_DEPTH (C_WR_DEPTH_RACH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_DOUT_WIDTH (C_DIN_WIDTH_RACH), .C_RD_DEPTH (C_WR_DEPTH_RACH), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH), .C_USE_ECC (C_USE_ECC_RACH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_3_rach_dut ( .CLK (S_ACLK), .WR_CLK (S_ACLK), .RD_CLK (M_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (rach_wr_en), .RD_EN (rach_rd_en), .PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}), .PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}), .INJECTDBITERR (AXI_AR_INJECTDBITERR), .INJECTSBITERR (AXI_AR_INJECTSBITERR), .DIN (rach_din), .DOUT (rach_dout_pkt), .FULL (rach_full), .EMPTY (rach_empty), .ALMOST_FULL (), .ALMOST_EMPTY (), .PROG_FULL (AXI_AR_PROG_FULL), .PROG_EMPTY (AXI_AR_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_ar_overflow_i), .VALID (), .UNDERFLOW (axi_ar_underflow_i), .DATA_COUNT (AXI_AR_DATA_COUNT), .RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT), .SBITERR (AXI_AR_SBITERR), .DBITERR (AXI_AR_DBITERR), .wr_rst_busy (wr_rst_busy_rach), .rd_rst_busy (rd_rst_busy_rach), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full; assign rach_m_axi_arvalid = ~rach_empty; assign S_AXI_ARREADY = rach_s_axi_arready; assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0; assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0; end endgenerate // axi_read_addr_channel // Register Slice for Read Address Channel generate if (C_RACH_TYPE == 1) begin : grach_reg_slice fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_RACH), .C_REG_CONFIG (C_REG_SLICE_MODE_RACH) ) rach_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (rach_din), .S_VALID (S_AXI_ARVALID), .S_READY (S_AXI_ARREADY), // Master side .M_PAYLOAD_DATA (rach_dout), .M_VALID (M_AXI_ARVALID), .M_READY (M_AXI_ARREADY) ); end endgenerate // grach_reg_slice // Register Slice for Read Address Channel for MM Packet FIFO generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_RACH), .C_REG_CONFIG (1) ) reg_slice_mm_pkt_fifo_inst ( // System Signals .ACLK (S_ACLK), .ARESET (inverted_reset), // Slave side .S_PAYLOAD_DATA (rach_dout_pkt), .S_VALID (arvalid_pkt), .S_READY (arready_pkt), // Master side .M_PAYLOAD_DATA (rach_dout), .M_VALID (M_AXI_ARVALID), .M_READY (M_AXI_ARREADY) ); end endgenerate // grach_reg_slice_mm_pkt_fifo generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid assign M_AXI_ARVALID = rach_m_axi_arvalid; assign rach_dout = rach_dout_pkt; end endgenerate // grach_m_axi_arvalid generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en; assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en; assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en; always@(posedge S_ACLK or posedge inverted_reset) begin if(inverted_reset) begin rdch_commited_space <= 0; end else begin if(rdch_rd_ok && !accept_next_pkt) begin rdch_commited_space <= rdch_commited_space-1; end else if(!rdch_rd_ok && accept_next_pkt) begin rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1); end else if(rdch_rd_ok && accept_next_pkt) begin rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]); end end end //Always end always@(*) begin rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1)); end assign arvalid_en = (rdch_free_space >= 0)?1:0; end endgenerate generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd assign arvalid_en = 1; end endgenerate generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel // Write protection when almost full or prog_full is high assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID; // Read protection when almost empty or prog_empty is high assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY; assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we; assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re; fifo_generator_v13_1_3_CONV_VER #( .C_FAMILY (C_FAMILY), .C_COMMON_CLOCK (C_COMMON_CLOCK), .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : (C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4), .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 : (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6), .C_PRELOAD_REGS (1), // always FWFT for AXI .C_PRELOAD_LATENCY (0), // always FWFT for AXI .C_DIN_WIDTH (C_DIN_WIDTH_RDCH), .C_WR_DEPTH (C_WR_DEPTH_RDCH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH), .C_DOUT_WIDTH (C_DIN_WIDTH_RDCH), .C_RD_DEPTH (C_WR_DEPTH_RDCH), .C_INTERFACE_TYPE (C_INTERFACE_TYPE), .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH), .C_USE_ECC (C_USE_ECC_RDCH), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH), .C_HAS_ALMOST_EMPTY (0), .C_HAS_ALMOST_FULL (0), .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), .C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_HAS_WR_RST (0), .C_HAS_RD_RST (0), .C_HAS_RST (1), .C_HAS_SRST (0), .C_DOUT_RST_VAL (0), .C_HAS_VALID (0), .C_VALID_LOW (C_VALID_LOW), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_HAS_WR_ACK (0), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), .C_FULL_FLAGS_RST_VAL (1), .C_USE_EMBEDDED_REG (0), .C_USE_DOUT_RST (0), .C_MSGON_VAL (C_MSGON_VAL), .C_ENABLE_RST_SYNC (1), .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0), .C_COUNT_TYPE (C_COUNT_TYPE), .C_DEFAULT_VALUE (C_DEFAULT_VALUE), .C_ENABLE_RLOCS (C_ENABLE_RLOCS), .C_HAS_BACKUP (C_HAS_BACKUP), .C_HAS_INT_CLK (C_HAS_INT_CLK), .C_MIF_FILE_NAME (C_MIF_FILE_NAME), .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), .C_RD_FREQ (C_RD_FREQ), .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), .C_WR_FREQ (C_WR_FREQ), .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) ) fifo_generator_v13_1_3_rdch_dut ( .CLK (S_ACLK), .WR_CLK (M_ACLK), .RD_CLK (S_ACLK), .RST (inverted_reset), .SRST (1'b0), .WR_RST (inverted_reset), .RD_RST (inverted_reset), .WR_EN (rdch_wr_en), .RD_EN (rdch_rd_en), .PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH), .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), .PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH), .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), .INJECTDBITERR (AXI_R_INJECTDBITERR), .INJECTSBITERR (AXI_R_INJECTSBITERR), .DIN (rdch_din), .DOUT (rdch_dout), .FULL (rdch_full), .EMPTY (rdch_empty), .ALMOST_FULL (), .ALMOST_EMPTY (), .PROG_FULL (AXI_R_PROG_FULL), .PROG_EMPTY (AXI_R_PROG_EMPTY), .WR_ACK (), .OVERFLOW (axi_r_overflow_i), .VALID (), .UNDERFLOW (axi_r_underflow_i), .DATA_COUNT (AXI_R_DATA_COUNT), .RD_DATA_COUNT (AXI_R_RD_DATA_COUNT), .WR_DATA_COUNT (AXI_R_WR_DATA_COUNT), .SBITERR (AXI_R_SBITERR), .DBITERR (AXI_R_DBITERR), .wr_rst_busy (wr_rst_busy_rdch), .rd_rst_busy (rd_rst_busy_rdch), .wr_rst_i_out (), .rd_rst_i_out (), .BACKUP (BACKUP), .BACKUP_MARKER (BACKUP_MARKER), .INT_CLK (INT_CLK) ); assign rdch_s_axi_rvalid = ~rdch_empty; assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full; assign S_AXI_RVALID = rdch_s_axi_rvalid; assign M_AXI_RREADY = rdch_m_axi_rready; assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0; assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0; end endgenerate //axi_read_data_channel // Register Slice for read Data Channel generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice fifo_generator_v13_1_3_axic_reg_slice #( .C_FAMILY (C_FAMILY), .C_DATA_WIDTH (C_DIN_WIDTH_RDCH), .C_REG_CONFIG (C_REG_SLICE_MODE_RDCH) ) rdch_reg_slice_inst ( // System Signals .ACLK (S_ACLK), .ARESET (axi_rs_rst), // Slave side .S_PAYLOAD_DATA (rdch_din), .S_VALID (M_AXI_RVALID), .S_READY (M_AXI_RREADY), // Master side .M_PAYLOAD_DATA (rdch_dout), .M_VALID (S_AXI_RVALID), .M_READY (S_AXI_RREADY) ); end endgenerate // grdch_reg_slice assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0; assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0; generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET]; assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET]; assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET]; assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET]; assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET]; assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET]; assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET]; assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET]; assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR; assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN; assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE; assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST; assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK; assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE; assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT; assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS; end endgenerate // axi_full_rach_output generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET]; end endgenerate // axi_arregion generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion assign M_AXI_ARREGION = 0; end endgenerate // naxi_arregion generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET]; end endgenerate // axi_aruser generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser assign M_AXI_ARUSER = 0; end endgenerate // naxi_aruser generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET]; end endgenerate // axi_arid generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid assign M_AXI_ARID = 0; end endgenerate // naxi_arid generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET]; assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET]; assign S_AXI_RLAST = rdch_dout[0]; assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA; assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP; assign rdch_din[0] = M_AXI_RLAST; end endgenerate // axi_full_rdch_output generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET]; end endgenerate // axi_full_ruser_output generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output assign S_AXI_RUSER = 0; end endgenerate // axi_full_nruser_output generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET]; end endgenerate // axi_rid generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid assign S_AXI_RID = 0; end endgenerate // naxi_rid generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1 assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT}; assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET]; assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET]; end endgenerate // axi_lite_rach_output generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1 assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP}; assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET]; assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET]; end endgenerate // axi_lite_rdch_output generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1 assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER; end endgenerate // grach_din1 generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2 assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID; end endgenerate // grach_din2 generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION; end endgenerate generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1 assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER; end endgenerate // grdch_din1 generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2 assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID; end endgenerate // grdch_din2 //end of axi_read_channel generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) : (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i : (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0; end endgenerate // gaxi_comm_uf generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) : (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i : (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0; end endgenerate // gaxi_comm_of //------------------------------------------------------------------------- //------------------------------------------------------------------------- //------------------------------------------------------------------------- // Pass Through Logic or Wiring Logic //------------------------------------------------------------------------- //------------------------------------------------------------------------- //------------------------------------------------------------------------- //------------------------------------------------------------------------- // Pass Through Logic for Read Channel //------------------------------------------------------------------------- // Wiring logic for Write Address Channel generate if (C_WACH_TYPE == 2) begin : gwach_pass_through assign M_AXI_AWID = S_AXI_AWID; assign M_AXI_AWADDR = S_AXI_AWADDR; assign M_AXI_AWLEN = S_AXI_AWLEN; assign M_AXI_AWSIZE = S_AXI_AWSIZE; assign M_AXI_AWBURST = S_AXI_AWBURST; assign M_AXI_AWLOCK = S_AXI_AWLOCK; assign M_AXI_AWCACHE = S_AXI_AWCACHE; assign M_AXI_AWPROT = S_AXI_AWPROT; assign M_AXI_AWQOS = S_AXI_AWQOS; assign M_AXI_AWREGION = S_AXI_AWREGION; assign M_AXI_AWUSER = S_AXI_AWUSER; assign S_AXI_AWREADY = M_AXI_AWREADY; assign M_AXI_AWVALID = S_AXI_AWVALID; end endgenerate // gwach_pass_through; // Wiring logic for Write Data Channel generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through assign M_AXI_WID = S_AXI_WID; assign M_AXI_WDATA = S_AXI_WDATA; assign M_AXI_WSTRB = S_AXI_WSTRB; assign M_AXI_WLAST = S_AXI_WLAST; assign M_AXI_WUSER = S_AXI_WUSER; assign S_AXI_WREADY = M_AXI_WREADY; assign M_AXI_WVALID = S_AXI_WVALID; end endgenerate // gwdch_pass_through; // Wiring logic for Write Response Channel generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through assign S_AXI_BID = M_AXI_BID; assign S_AXI_BRESP = M_AXI_BRESP; assign S_AXI_BUSER = M_AXI_BUSER; assign M_AXI_BREADY = S_AXI_BREADY; assign S_AXI_BVALID = M_AXI_BVALID; end endgenerate // gwrch_pass_through; //------------------------------------------------------------------------- // Pass Through Logic for Read Channel //------------------------------------------------------------------------- // Wiring logic for Read Address Channel generate if (C_RACH_TYPE == 2) begin : grach_pass_through assign M_AXI_ARID = S_AXI_ARID; assign M_AXI_ARADDR = S_AXI_ARADDR; assign M_AXI_ARLEN = S_AXI_ARLEN; assign M_AXI_ARSIZE = S_AXI_ARSIZE; assign M_AXI_ARBURST = S_AXI_ARBURST; assign M_AXI_ARLOCK = S_AXI_ARLOCK; assign M_AXI_ARCACHE = S_AXI_ARCACHE; assign M_AXI_ARPROT = S_AXI_ARPROT; assign M_AXI_ARQOS = S_AXI_ARQOS; assign M_AXI_ARREGION = S_AXI_ARREGION; assign M_AXI_ARUSER = S_AXI_ARUSER; assign S_AXI_ARREADY = M_AXI_ARREADY; assign M_AXI_ARVALID = S_AXI_ARVALID; end endgenerate // grach_pass_through; // Wiring logic for Read Data Channel generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through assign S_AXI_RID = M_AXI_RID; assign S_AXI_RLAST = M_AXI_RLAST; assign S_AXI_RUSER = M_AXI_RUSER; assign S_AXI_RDATA = M_AXI_RDATA; assign S_AXI_RRESP = M_AXI_RRESP; assign S_AXI_RVALID = M_AXI_RVALID; assign M_AXI_RREADY = S_AXI_RREADY; end endgenerate // grdch_pass_through; // Wiring logic for AXI Streaming generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through assign M_AXIS_TDATA = S_AXIS_TDATA; assign M_AXIS_TSTRB = S_AXIS_TSTRB; assign M_AXIS_TKEEP = S_AXIS_TKEEP; assign M_AXIS_TID = S_AXIS_TID; assign M_AXIS_TDEST = S_AXIS_TDEST; assign M_AXIS_TUSER = S_AXIS_TUSER; assign M_AXIS_TLAST = S_AXIS_TLAST; assign S_AXIS_TREADY = M_AXIS_TREADY; assign M_AXIS_TVALID = S_AXIS_TVALID; end endgenerate // gaxis_pass_through; endmodule //fifo_generator_v13_1_3 /******************************************************************************* * Declaration of top-level module for Conventional FIFO ******************************************************************************/ module fifo_generator_v13_1_3_CONV_VER #( parameter C_COMMON_CLOCK = 0, parameter C_INTERFACE_TYPE = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_COUNT_TYPE = 0, parameter C_DATA_COUNT_WIDTH = 2, parameter C_DEFAULT_VALUE = "", parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_ENABLE_RLOCS = 0, parameter C_FAMILY = "virtex7", //Not allowed in Verilog model parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_ALMOST_EMPTY = 0, parameter C_HAS_ALMOST_FULL = 0, parameter C_HAS_BACKUP = 0, parameter C_HAS_DATA_COUNT = 0, parameter C_HAS_INT_CLK = 0, parameter C_HAS_MEMINIT_FILE = 0, parameter C_HAS_OVERFLOW = 0, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_RD_RST = 0, parameter C_HAS_RST = 0, parameter C_HAS_SRST = 0, parameter C_HAS_UNDERFLOW = 0, parameter C_HAS_VALID = 0, parameter C_HAS_WR_ACK = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_HAS_WR_RST = 0, parameter C_IMPLEMENTATION_TYPE = 0, parameter C_INIT_WR_PNTR_VAL = 0, parameter C_MEMORY_TYPE = 1, parameter C_MIF_FILE_NAME = "", parameter C_OPTIMIZATION_MODE = 0, parameter C_OVERFLOW_LOW = 0, parameter C_PRELOAD_LATENCY = 1, parameter C_PRELOAD_REGS = 0, parameter C_PRIM_FIFO_TYPE = "", parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, parameter C_PROG_EMPTY_TYPE = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, parameter C_PROG_FULL_TYPE = 0, parameter C_RD_DATA_COUNT_WIDTH = 2, parameter C_RD_DEPTH = 256, parameter C_RD_FREQ = 1, parameter C_RD_PNTR_WIDTH = 8, parameter C_UNDERFLOW_LOW = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_ECC = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_USE_FIFO16_FLAGS = 0, parameter C_USE_FWFT_DATA_COUNT = 0, parameter C_VALID_LOW = 0, parameter C_WR_ACK_LOW = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_FREQ = 1, parameter C_WR_PNTR_WIDTH = 8, parameter C_WR_RESPONSE_LATENCY = 1, parameter C_MSGON_VAL = 1, parameter C_ENABLE_RST_SYNC = 1, parameter C_ERROR_INJECTION_TYPE = 0, parameter C_FIFO_TYPE = 0, parameter C_SYNCHRONIZER_STAGE = 2, parameter C_AXI_TYPE = 0 ) ( input BACKUP, input BACKUP_MARKER, input CLK, input RST, input SRST, input WR_CLK, input WR_RST, input RD_CLK, input RD_RST, input [C_DIN_WIDTH-1:0] DIN, input WR_EN, input RD_EN, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, input INT_CLK, input INJECTDBITERR, input INJECTSBITERR, output [C_DOUT_WIDTH-1:0] DOUT, output FULL, output ALMOST_FULL, output WR_ACK, output OVERFLOW, output EMPTY, output ALMOST_EMPTY, output VALID, output UNDERFLOW, output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, output PROG_FULL, output PROG_EMPTY, output SBITERR, output DBITERR, output wr_rst_busy_o, output wr_rst_busy, output rd_rst_busy, output wr_rst_i_out, output rd_rst_i_out ); /* ****************************************************************************** * Definition of Parameters ****************************************************************************** * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) * C_COUNT_TYPE : *not used * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus * C_DEFAULT_VALUE : *not used * C_DIN_WIDTH : Width of DIN bus * C_DOUT_RST_VAL : Reset value of DOUT * C_DOUT_WIDTH : Width of DOUT bus * C_ENABLE_RLOCS : *not used * C_FAMILY : not used in bhv model * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag * C_HAS_BACKUP : *not used * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus * C_HAS_INT_CLK : not used in bhv model * C_HAS_MEMINIT_FILE : *not used * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus * C_HAS_RD_RST : *not used * C_HAS_RST : 1=Core has Async Rst * C_HAS_SRST : 1=Core has Sync Rst * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag * C_HAS_VALID : 1=Core has VALID flag * C_HAS_WR_ACK : 1=Core has WR_ACK flag * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus * C_HAS_WR_RST : *not used * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram * 1=Common-Clock ShiftRam * 2=Indep. Clocks Bram/Dram * 3=Virtex-4 Built-in * 4=Virtex-5 Built-in * C_INIT_WR_PNTR_VAL : *not used * C_MEMORY_TYPE : 1=Block RAM * 2=Distributed RAM * 3=Shift RAM * 4=Built-in FIFO * C_MIF_FILE_NAME : *not used * C_OPTIMIZATION_MODE : *not used * C_OVERFLOW_LOW : 1=OVERFLOW active low * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 * C_PRELOAD_REGS : 1=Use output registers * C_PRIM_FIFO_TYPE : not used in bhv model * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold * C_PROG_EMPTY_TYPE : 0=No programmable empty * 1=Single prog empty thresh constant * 2=Multiple prog empty thresh constants * 3=Single prog empty thresh input * 4=Multiple prog empty thresh inputs * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold * C_PROG_FULL_TYPE : 0=No prog full * 1=Single prog full thresh constant * 2=Multiple prog full thresh constants * 3=Single prog full thresh input * 4=Multiple prog full thresh inputs * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus * C_RD_DEPTH : Depth of read interface (2^N) * C_RD_FREQ : not used in bhv model * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) * C_UNDERFLOW_LOW : 1=UNDERFLOW active low * C_USE_DOUT_RST : 1=Resets DOUT on RST * C_USE_ECC : Used for error injection purpose * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register * C_USE_FIFO16_FLAGS : not used in bhv model * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count * C_VALID_LOW : 1=VALID active low * C_WR_ACK_LOW : 1=WR_ACK active low * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus * C_WR_DEPTH : Depth of write interface (2^N) * C_WR_FREQ : not used in bhv model * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) * C_WR_RESPONSE_LATENCY : *not used * C_MSGON_VAL : *not used by bhv model * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST * 1 = Use RST * C_ERROR_INJECTION_TYPE : 0 = No error injection * 1 = Single bit error injection only * 2 = Double bit error injection only * 3 = Single and double bit error injection ****************************************************************************** * Definition of Ports ****************************************************************************** * BACKUP : Not used * BACKUP_MARKER: Not used * CLK : Clock * DIN : Input data bus * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag * PROG_FULL_THRESH : Threshold for Programmable Full Flag * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag * RD_CLK : Read Domain Clock * RD_EN : Read enable * RD_RST : Read Reset * RST : Asynchronous Reset * SRST : Synchronous Reset * WR_CLK : Write Domain Clock * WR_EN : Write enable * WR_RST : Write Reset * INT_CLK : Internal Clock * INJECTSBITERR: Inject Signle bit error * INJECTDBITERR: Inject Double bit error * ALMOST_EMPTY : One word remaining in FIFO * ALMOST_FULL : One empty space remaining in FIFO * DATA_COUNT : Number of data words in fifo( synchronous to CLK) * DOUT : Output data bus * EMPTY : Empty flag * FULL : Full flag * OVERFLOW : Last write rejected * PROG_EMPTY : Programmable Empty Flag * PROG_FULL : Programmable Full Flag * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) * UNDERFLOW : Last read rejected * VALID : Last read acknowledged, DOUT bus VALID * WR_ACK : Last write acknowledged * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) * SBITERR : Single Bit ECC Error Detected * DBITERR : Double Bit ECC Error Detected ****************************************************************************** */ //---------------------------------------------------------------------------- //- Internal Signals for delayed input signals //- All the input signals except Clock are delayed by 100 ps and then given to //- the models. //---------------------------------------------------------------------------- reg rst_delayed ; reg empty_fb ; reg srst_delayed ; reg wr_rst_delayed ; reg rd_rst_delayed ; reg wr_en_delayed ; reg rd_en_delayed ; reg [C_DIN_WIDTH-1:0] din_delayed ; reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ; reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ; reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ; reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ; reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ; reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ; reg injectdbiterr_delayed ; reg injectsbiterr_delayed ; wire empty_p0_out; always @* rst_delayed <= #`TCQ RST ; always @* empty_fb <= #`TCQ empty_p0_out ; always @* srst_delayed <= #`TCQ SRST ; always @* wr_rst_delayed <= #`TCQ WR_RST ; always @* rd_rst_delayed <= #`TCQ RD_RST ; always @* din_delayed <= #`TCQ DIN ; always @* wr_en_delayed <= #`TCQ WR_EN ; always @* rd_en_delayed <= #`TCQ RD_EN ; always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ; always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ; always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ; always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ; always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ; always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ; /***************************************************************************** * Derived parameters ****************************************************************************/ //There are 2 Verilog behavioral models // 0 = Common-Clock FIFO/ShiftRam FIFO // 1 = Independent Clocks FIFO // 2 = Low Latency Synchronous FIFO // 3 = Low Latency Asynchronous FIFO localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 : (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0; localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0; //Internal reset signals reg rd_rst_asreg = 0; wire rd_rst_asreg_d1; wire rd_rst_asreg_d2; reg rd_rst_asreg_d3 = 0; reg rd_rst_reg = 0; wire rd_rst_comb; reg wr_rst_d0 = 0; reg wr_rst_d1 = 0; reg wr_rst_d2 = 0; reg rd_rst_d0 = 0; reg rd_rst_d1 = 0; reg rd_rst_d2 = 0; reg rd_rst_d3 = 0; reg wrrst_done = 0; reg rdrst_done = 0; reg wr_rst_asreg = 0; wire wr_rst_asreg_d1; wire wr_rst_asreg_d2; reg wr_rst_asreg_d3 = 0; reg rd_rst_wr_d0 = 0; reg rd_rst_wr_d1 = 0; reg rd_rst_wr_d2 = 0; reg wr_rst_reg = 0; reg rst_active_i = 1'b1; reg rst_delayed_d1 = 1'b1; reg rst_delayed_d2 = 1'b1; wire wr_rst_comb; wire wr_rst_i; wire rd_rst_i; wire rst_i; //Internal reset signals reg rst_asreg = 0; reg srst_asreg = 0; wire rst_asreg_d1; wire rst_asreg_d2; reg srst_asreg_d1 = 0; reg srst_asreg_d2 = 0; reg rst_reg = 0; reg srst_reg = 0; wire rst_comb; wire srst_comb; reg rst_full_gen_i = 0; reg rst_full_ff_i = 0; reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}}; wire RD_CLK_P0_IN; wire RST_P0_IN; wire RD_EN_FIFO_IN; wire RD_EN_P0_IN; wire ALMOST_EMPTY_FIFO_OUT; wire ALMOST_FULL_FIFO_OUT; wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; wire EMPTY_FIFO_OUT; wire fifo_empty_fb; wire FULL_FIFO_OUT; wire OVERFLOW_FIFO_OUT; wire PROG_EMPTY_FIFO_OUT; wire PROG_FULL_FIFO_OUT; wire VALID_FIFO_OUT; wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; wire UNDERFLOW_FIFO_OUT; wire WR_ACK_FIFO_OUT; wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; //*************************************************************************** // Internal Signals // The core uses either the internal_ wires or the preload0_ wires depending // on whether the core uses Preload0 or not. // When using preload0, the internal signals connect the internal core to // the preload logic, and the external core's interfaces are tied to the // preload0 signals from the preload logic. //*************************************************************************** wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; wire VALID_P0_OUT; wire EMPTY_P0_OUT; wire ALMOSTEMPTY_P0_OUT; reg EMPTY_P0_OUT_Q; reg ALMOSTEMPTY_P0_OUT_Q; wire UNDERFLOW_P0_OUT; wire RDEN_P0_OUT; wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; wire EMPTY_P0_IN; reg [31:0] DATA_COUNT_FWFT; reg SS_FWFT_WR ; reg SS_FWFT_RD ; wire sbiterr_fifo_out; wire dbiterr_fifo_out; wire inject_sbit_err; wire inject_dbit_err; wire safety_ckt_wr_rst; wire safety_ckt_rd_rst; reg sckt_wr_rst_i_q = 1'b0; wire w_fab_read_data_valid_i; wire w_read_data_valid_i; wire w_ram_valid_i; // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR. assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ? injectsbiterr_delayed : 0; assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ? injectdbiterr_delayed : 0; assign wr_rst_i_out = wr_rst_i; assign rd_rst_i_out = rd_rst_i; assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2]; generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK; always @ (posedge clk_i) sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; end endgenerate // Choose the behavioral model to instantiate based on the C_VERILOG_IMPL // parameter (1=Independent Clocks, 0=Common Clock) localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL; generate case (C_VERILOG_IMPL) 0 : begin : block1 //Common Clock Behavioral Model fifo_generator_v13_1_3_bhv_ver_ss #( .C_FAMILY (C_FAMILY), .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL), .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), .C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL), .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_RST (C_HAS_RST), .C_HAS_SRST (C_HAS_SRST), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_HAS_VALID (C_HAS_VALID), .C_HAS_WR_ACK (C_HAS_WR_ACK), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), .C_PRELOAD_REGS (C_PRELOAD_REGS), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), .C_VALID_LOW (C_VALID_LOW), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_USE_ECC (C_USE_ECC), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE), .C_FIFO_TYPE (C_FIFO_TYPE) ) gen_ss ( .SAFETY_CKT_WR_RST (safety_ckt_wr_rst), .CLK (CLK), .RST (rst_i), .SRST (srst_delayed), .RST_FULL_GEN (rst_full_gen_i), .RST_FULL_FF (rst_full_ff_i), .DIN (din_delayed), .WR_EN (wr_en_delayed), .RD_EN (RD_EN_FIFO_IN), .RD_EN_USER (rd_en_delayed), .USER_EMPTY_FB (empty_fb), .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), .PROG_FULL_THRESH (prog_full_thresh_delayed), .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), .INJECTSBITERR (inject_sbit_err), .INJECTDBITERR (inject_dbit_err), .DOUT (DOUT_FIFO_OUT), .FULL (FULL_FIFO_OUT), .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), .WR_ACK (WR_ACK_FIFO_OUT), .OVERFLOW (OVERFLOW_FIFO_OUT), .EMPTY (EMPTY_FIFO_OUT), .EMPTY_FB (fifo_empty_fb), .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), .VALID (VALID_FIFO_OUT), .UNDERFLOW (UNDERFLOW_FIFO_OUT), .DATA_COUNT (DATA_COUNT_FIFO_OUT), .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), .PROG_FULL (PROG_FULL_FIFO_OUT), .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), .WR_RST_BUSY (wr_rst_busy), .RD_RST_BUSY (rd_rst_busy), .SBITERR (sbiterr_fifo_out), .DBITERR (dbiterr_fifo_out) ); end 1 : begin : block1 //Independent Clocks Behavioral Model fifo_generator_v13_1_3_bhv_ver_as #( .C_FAMILY (C_FAMILY), .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_RST (C_HAS_RST), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_HAS_VALID (C_HAS_VALID), .C_HAS_WR_ACK (C_HAS_WR_ACK), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), .C_PRELOAD_REGS (C_PRELOAD_REGS), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), .C_VALID_LOW (C_VALID_LOW), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_USE_ECC (C_USE_ECC), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) ) gen_as ( .SAFETY_CKT_WR_RST (safety_ckt_wr_rst), .SAFETY_CKT_RD_RST (safety_ckt_rd_rst), .WR_CLK (WR_CLK), .RD_CLK (RD_CLK), .RST (rst_i), .RST_FULL_GEN (rst_full_gen_i), .RST_FULL_FF (rst_full_ff_i), .WR_RST (wr_rst_i), .RD_RST (rd_rst_i), .DIN (din_delayed), .WR_EN (wr_en_delayed), .RD_EN (RD_EN_FIFO_IN), .RD_EN_USER (rd_en_delayed), .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), .PROG_FULL_THRESH (prog_full_thresh_delayed), .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), .INJECTSBITERR (inject_sbit_err), .INJECTDBITERR (inject_dbit_err), .USER_EMPTY_FB (EMPTY_P0_OUT), .DOUT (DOUT_FIFO_OUT), .FULL (FULL_FIFO_OUT), .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), .WR_ACK (WR_ACK_FIFO_OUT), .OVERFLOW (OVERFLOW_FIFO_OUT), .EMPTY (EMPTY_FIFO_OUT), .EMPTY_FB (fifo_empty_fb), .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), .VALID (VALID_FIFO_OUT), .UNDERFLOW (UNDERFLOW_FIFO_OUT), .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), .PROG_FULL (PROG_FULL_FIFO_OUT), .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), .SBITERR (sbiterr_fifo_out), .fab_read_data_valid_i (w_fab_read_data_valid_i), .read_data_valid_i (w_read_data_valid_i), .ram_valid_i (w_ram_valid_i), .DBITERR (dbiterr_fifo_out) ); end 2 : begin : ll_afifo_inst fifo_generator_v13_1_3_beh_ver_ll_afifo #( .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_FIFO_TYPE (C_FIFO_TYPE) ) gen_ll_afifo ( .DIN (din_delayed), .RD_CLK (RD_CLK), .RD_EN (rd_en_delayed), .WR_RST (wr_rst_i), .RD_RST (rd_rst_i), .WR_CLK (WR_CLK), .WR_EN (wr_en_delayed), .DOUT (DOUT), .EMPTY (EMPTY), .FULL (FULL) ); end default : begin : block1 //Independent Clocks Behavioral Model fifo_generator_v13_1_3_bhv_ver_as #( .C_FAMILY (C_FAMILY), .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), .C_DIN_WIDTH (C_DIN_WIDTH), .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), .C_HAS_OVERFLOW (C_HAS_OVERFLOW), .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), .C_HAS_RST (C_HAS_RST), .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), .C_HAS_VALID (C_HAS_VALID), .C_HAS_WR_ACK (C_HAS_WR_ACK), .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_OVERFLOW_LOW (C_OVERFLOW_LOW), .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), .C_PRELOAD_REGS (C_PRELOAD_REGS), .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), .C_RD_DEPTH (C_RD_DEPTH), .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), .C_VALID_LOW (C_VALID_LOW), .C_WR_ACK_LOW (C_WR_ACK_LOW), .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), .C_WR_DEPTH (C_WR_DEPTH), .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), .C_USE_ECC (C_USE_ECC), .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) ) gen_as ( .SAFETY_CKT_WR_RST (safety_ckt_wr_rst), .SAFETY_CKT_RD_RST (safety_ckt_rd_rst), .WR_CLK (WR_CLK), .RD_CLK (RD_CLK), .RST (rst_i), .RST_FULL_GEN (rst_full_gen_i), .RST_FULL_FF (rst_full_ff_i), .WR_RST (wr_rst_i), .RD_RST (rd_rst_i), .DIN (din_delayed), .WR_EN (wr_en_delayed), .RD_EN (RD_EN_FIFO_IN), .RD_EN_USER (rd_en_delayed), .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), .PROG_FULL_THRESH (prog_full_thresh_delayed), .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), .INJECTSBITERR (inject_sbit_err), .INJECTDBITERR (inject_dbit_err), .USER_EMPTY_FB (EMPTY_P0_OUT), .DOUT (DOUT_FIFO_OUT), .FULL (FULL_FIFO_OUT), .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), .WR_ACK (WR_ACK_FIFO_OUT), .OVERFLOW (OVERFLOW_FIFO_OUT), .EMPTY (EMPTY_FIFO_OUT), .EMPTY_FB (fifo_empty_fb), .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), .VALID (VALID_FIFO_OUT), .UNDERFLOW (UNDERFLOW_FIFO_OUT), .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), .PROG_FULL (PROG_FULL_FIFO_OUT), .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), .SBITERR (sbiterr_fifo_out), .DBITERR (dbiterr_fifo_out) ); end endcase endgenerate //************************************************************************** // Connect Internal Signals // (Signals labeled internal_*) // In the normal case, these signals tie directly to the FIFO's inputs and // outputs. // In the case of Preload Latency 0 or 1, there are intermediate // signals between the internal FIFO and the preload logic. //************************************************************************** //*********************************************** // If First-Word Fall-Through, instantiate // the preload0 (FWFT) module //*********************************************** wire rd_en_to_fwft_fifo; wire sbiterr_fwft; wire dbiterr_fwft; wire [C_DOUT_WIDTH-1:0] dout_fwft; wire empty_fwft; wire rd_en_fifo_in; wire stage2_reg_en_i; wire [1:0] valid_stages_i; wire rst_fwft; //wire empty_p0_out; reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1; localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0; localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0; localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0; assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0; generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2 fifo_generator_v13_1_3_bhv_ver_preload0 #( .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_HAS_RST (C_HAS_RST), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_HAS_SRST (C_HAS_SRST), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), .C_USE_ECC (C_USE_ECC), .C_USERVALID_LOW (C_VALID_LOW), .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_FIFO_TYPE (C_FIFO_TYPE) ) fgpl0 ( .SAFETY_CKT_RD_RST(safety_ckt_rd_rst), .RD_CLK (RD_CLK_P0_IN), .RD_RST (RST_P0_IN), .SRST (srst_delayed), .WR_RST_BUSY (wr_rst_busy), .RD_RST_BUSY (rd_rst_busy), .RD_EN (RD_EN_P0_IN), .FIFOEMPTY (EMPTY_P0_IN), .FIFODATA (DATA_P0_IN), .FIFOSBITERR (sbiterr_fifo_out), .FIFODBITERR (dbiterr_fifo_out), // Output .USERDATA (dout_fwft), .USERVALID (VALID_P0_OUT), .USEREMPTY (empty_fwft), .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), .USERUNDERFLOW (UNDERFLOW_P0_OUT), .RAMVALID (), .FIFORDEN (rd_en_fifo_in), .USERSBITERR (sbiterr_fwft), .USERDBITERR (dbiterr_fwft), .STAGE2_REG_EN (stage2_reg_en_i), .fab_read_data_valid_i_o (w_fab_read_data_valid_i), .read_data_valid_i_o (w_read_data_valid_i), .ram_valid_i_o (w_ram_valid_i), .VALID_STAGES (valid_stages_i) ); //*********************************************** // Connect inputs to preload (FWFT) module //*********************************************** //Connect the RD_CLK of the Preload (FWFT) module to CLK if we // have a common-clock FIFO, or RD_CLK if we have an // independent clock FIFO assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0; assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo; assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT; assign DATA_P0_IN = DOUT_FIFO_OUT; //*********************************************** // Connect outputs from preload (FWFT) module //*********************************************** assign VALID = VALID_P0_OUT ; assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; assign UNDERFLOW = UNDERFLOW_P0_OUT ; assign RD_EN_FIFO_IN = rd_en_fifo_in; //*********************************************** // Create DATA_COUNT from First-Word Fall-Through // data count //*********************************************** assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; //*********************************************** // Create DATA_COUNT from First-Word Fall-Through // data count //*********************************************** always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin if (RST_P0_IN) begin EMPTY_P0_OUT_Q <= 1; ALMOSTEMPTY_P0_OUT_Q <= 1; end else begin EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out; // EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT; ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; end end //always //*********************************************** // logic for common-clock data count when FWFT is selected //*********************************************** initial begin SS_FWFT_RD = 1'b0; DATA_COUNT_FWFT = 0 ; SS_FWFT_WR = 1'b0 ; end //initial //*********************************************** // common-clock data count is implemented as an // up-down counter. SS_FWFT_WR and SS_FWFT_RD // are the up/down enables for the counter. //*********************************************** always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin if (C_VALID_LOW == 1) begin SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ; end else begin SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ; end SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; end //*********************************************** // common-clock data count is implemented as an // up-down counter for FWFT. This always block // calculates the counter. //*********************************************** always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin if (RST_P0_IN) begin DATA_COUNT_FWFT <= 0; end else begin //if (srst_delayed && (C_HAS_SRST == 1) ) begin if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin DATA_COUNT_FWFT <= #`TCQ 0; end else begin case ( {SS_FWFT_WR, SS_FWFT_RD}) 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; endcase end //if SRST end //IF RST end //always end endgenerate // : block2 // AXI Streaming Packet FIFO reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0; reg partial_packet = 0; reg stage1_eop_d1 = 0; reg rd_en_fifo_in_d1 = 0; reg eop_at_stage2 = 0; reg ram_pkt_empty = 0; reg ram_pkt_empty_d1 = 0; wire [C_DOUT_WIDTH-1:0] dout_p0_out; wire packet_empty_wr; wire wr_rst_fwft_pkt_fifo; wire dummy_wr_eop; wire ram_wr_en_pkt_fifo; wire wr_eop; wire ram_rd_en_compare; wire stage1_eop; wire pkt_ready_to_read; wire rd_en_2_stage2; // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming) // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of // write packet count generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin if (wr_rst_fwft_pkt_fifo) partial_packet <= 1'b0; else begin if (srst_delayed | wr_rst_busy | rd_rst_busy) partial_packet <= #`TCQ 1'b0; else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0])) partial_packet <= #`TCQ 1'b1; else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo) partial_packet <= #`TCQ 1'b0; end end end endgenerate // gdummy_wr_eop generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0; assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet); assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1]; always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) begin stage1_eop_d1 <= 1'b0; rd_en_fifo_in_d1 <= 1'b0; end else begin if (srst_delayed | wr_rst_busy | rd_rst_busy) begin stage1_eop_d1 <= #`TCQ 1'b0; rd_en_fifo_in_d1 <= #`TCQ 1'b0; end else begin stage1_eop_d1 <= #`TCQ stage1_eop; rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in; end end end assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1; assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT); assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop); assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop; fifo_generator_v13_1_3_bhv_ver_preload0 #( .C_DOUT_RST_VAL (C_DOUT_RST_VAL), .C_DOUT_WIDTH (C_DOUT_WIDTH), .C_HAS_RST (C_HAS_RST), .C_HAS_SRST (C_HAS_SRST), .C_USE_DOUT_RST (C_USE_DOUT_RST), .C_USE_ECC (C_USE_ECC), .C_USERVALID_LOW (C_VALID_LOW), .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW), .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), .C_MEMORY_TYPE (C_MEMORY_TYPE), .C_FIFO_TYPE (2) // Enable low latency fwft logic ) pkt_fifo_fwft ( .SAFETY_CKT_RD_RST(safety_ckt_rd_rst), .RD_CLK (RD_CLK_P0_IN), .RD_RST (rst_fwft), .SRST (srst_delayed), .WR_RST_BUSY (wr_rst_busy), .RD_RST_BUSY (rd_rst_busy), .RD_EN (rd_en_delayed), .FIFOEMPTY (pkt_ready_to_read), .FIFODATA (dout_fwft), .FIFOSBITERR (sbiterr_fwft), .FIFODBITERR (dbiterr_fwft), // Output .USERDATA (dout_p0_out), .USERVALID (), .USEREMPTY (empty_p0_out), .USERALMOSTEMPTY (), .USERUNDERFLOW (), .RAMVALID (), .FIFORDEN (rd_en_2_stage2), .USERSBITERR (SBITERR), .USERDBITERR (DBITERR), .STAGE2_REG_EN (), .VALID_STAGES () ); assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2)); assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2; always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) eop_at_stage2 <= 1'b0; else if (stage2_reg_en_i) eop_at_stage2 <= #`TCQ stage1_eop; end //--------------------------------------------------------------------------- // Write and Read Packet Count //--------------------------------------------------------------------------- always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin if (wr_rst_fwft_pkt_fifo) wr_pkt_count <= 0; else if (srst_delayed | wr_rst_busy | rd_rst_busy) wr_pkt_count <= #`TCQ 0; else if (wr_eop) wr_pkt_count <= #`TCQ wr_pkt_count + 1; end end endgenerate // gpkt_fifo_fwft assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out; assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out; generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) begin rd_pkt_count <= 0; rd_pkt_count_plus1 <= 1; end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin rd_pkt_count <= #`TCQ 0; rd_pkt_count_plus1 <= #`TCQ 1; end else if (stage2_reg_en_i && stage1_eop) begin rd_pkt_count <= #`TCQ rd_pkt_count + 1; rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1; end end always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) begin ram_pkt_empty <= 1'b1; ram_pkt_empty_d1 <= 1'b1; end else if (SRST | wr_rst_busy | rd_rst_busy) begin ram_pkt_empty <= #`TCQ 1'b1; ram_pkt_empty_d1 <= #`TCQ 1'b1; end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin ram_pkt_empty <= #`TCQ 1'b0; ram_pkt_empty_d1 <= #`TCQ 1'b0; end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin ram_pkt_empty <= #`TCQ 1'b1; end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin ram_pkt_empty_d1 <= #`TCQ 1'b1; end end end endgenerate //grss_pkt_cnt localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH; reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0; wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd; generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin if (wr_rst_fwft_pkt_fifo) wr_pkt_count_b2g <= 0; else wr_pkt_count_b2g <= #`TCQ wr_pkt_count; end // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) wr_pkt_count_q <= 0; else wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g}; end always @* begin if (stage1_eop) rd_pkt_count <= rd_pkt_count_reg + 1; else rd_pkt_count <= rd_pkt_count_reg; end assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH]; always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) rd_pkt_count_reg <= 0; else if (rd_en_fifo_in) rd_pkt_count_reg <= #`TCQ rd_pkt_count; end always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin if (rst_fwft) begin ram_pkt_empty <= 1'b1; ram_pkt_empty_d1 <= 1'b1; end else if (rd_pkt_count != wr_pkt_count_rd) begin ram_pkt_empty <= #`TCQ 1'b0; ram_pkt_empty_d1 <= #`TCQ 1'b0; end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin ram_pkt_empty <= #`TCQ 1'b1; end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin ram_pkt_empty_d1 <= #`TCQ 1'b1; end end // Synchronize the empty in write domain always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin if (wr_rst_fwft_pkt_fifo) pkt_empty_sync <= 'b1; else pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out}; end end endgenerate //gras_pkt_cnt generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO //*********************************************** // If NOT First-Word Fall-Through, wire the outputs // of the internal _ss or _as FIFO directly to the // output, and do not instantiate the preload0 // module. //*********************************************** assign RD_CLK_P0_IN = 0; assign RST_P0_IN = 0; assign RD_EN_P0_IN = 0; assign RD_EN_FIFO_IN = rd_en_delayed; assign DOUT = DOUT_FIFO_OUT; assign DATA_P0_IN = 0; assign VALID = VALID_FIFO_OUT; assign EMPTY = EMPTY_FIFO_OUT; assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; assign EMPTY_P0_IN = 0; assign UNDERFLOW = UNDERFLOW_FIFO_OUT; assign DATA_COUNT = DATA_COUNT_FIFO_OUT; assign SBITERR = sbiterr_fifo_out; assign DBITERR = dbiterr_fifo_out; end endgenerate // STD_FIFO generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO assign empty_p0_out = empty_fwft; assign SBITERR = sbiterr_fwft; assign DBITERR = dbiterr_fwft; assign DOUT = dout_fwft; assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo; end endgenerate // NO_PKT_FIFO //*********************************************** // Connect user flags to internal signals //*********************************************** //If we are using extra logic for the FWFT data count, then override the //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. generate if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3 if (C_COMMON_CLOCK == 0) begin : block_ic assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); end //block_ic else begin assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end end //block3 endgenerate //If we are using extra logic for the FWFT data count, then override the //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. generate if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30 if (C_COMMON_CLOCK == 0) begin : block_ic assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); end else begin assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end end //block30 endgenerate //If we are using extra logic for the FWFT data count, then override the //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. generate if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both if (C_COMMON_CLOCK == 0) begin : block_ic_both assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT)); end else begin assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end end //block30_both endgenerate generate if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both if (C_COMMON_CLOCK == 0) begin : block_ic_both assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT)); end //block_ic_both else begin assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end end //block3_both endgenerate //If we are not using extra logic for the FWFT data count, //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the //internal FIFO instance generate if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; end endgenerate //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal //FIFO instance generate if (C_USE_FWFT_DATA_COUNT==1) begin : block4 assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; end else begin : block4 assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; end endgenerate //Connect other flags to the internal FIFO instance assign FULL = FULL_FIFO_OUT; assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; assign WR_ACK = WR_ACK_FIFO_OUT; assign OVERFLOW = OVERFLOW_FIFO_OUT; assign PROG_FULL = PROG_FULL_FIFO_OUT; assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; /************************************************************************** * find_log2 * Returns the 'log2' value for the input value for the supported ratios ***************************************************************************/ function integer find_log2; input integer int_val; integer i,j; begin i = 1; j = 0; for (i = 1; i < int_val; i = i*2) begin j = j + 1; end find_log2 = j; end endfunction // if an asynchronous FIFO has been selected, display a message that the FIFO // will not be cycle-accurate in simulation initial begin if (C_IMPLEMENTATION_TYPE == 2) begin $display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information."); end else if (C_MEMORY_TYPE == 4) begin $display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado."); $finish; end if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin $display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH."); $finish; end if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin $display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH."); $finish; end if (C_USE_ECC == 1) begin if (C_DIN_WIDTH != C_DOUT_WIDTH) begin $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration."); $finish; end if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection."); $finish; end end end //initial /************************************************************************** * Internal reset logic **************************************************************************/ assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0; assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0; assign rst_i = C_HAS_RST ? rst_reg : 0; wire rst_2_sync; wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST; wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK; wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK; localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE : (C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2; reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}}; reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}}; reg [1:0] wrst_cc = {2{1'b0}}; reg [1:0] rrst_cc = {2{1'b0}}; generate if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt reg[1:0] rst_d1_safety =1; reg[1:0] rst_d2_safety =1; reg[1:0] rst_d3_safety =1; reg[1:0] rst_d4_safety =1; reg[1:0] rst_d5_safety =1; reg[1:0] rst_d6_safety =1; reg[1:0] rst_d7_safety =1; always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst if (rst_2_sync_safety == 1'b1) begin rst_d1_safety <= 1'b1; rst_d2_safety <= 1'b1; rst_d3_safety <= 1'b1; rst_d4_safety <= 1'b1; rst_d5_safety <= 1'b1; rst_d6_safety <= 1'b1; rst_d7_safety <= 1'b1; end else begin rst_d1_safety <= #`TCQ 1'b0; rst_d2_safety <= #`TCQ rst_d1_safety; rst_d3_safety <= #`TCQ rst_d2_safety; rst_d4_safety <= #`TCQ rst_d3_safety; rst_d5_safety <= #`TCQ rst_d4_safety; rst_d6_safety <= #`TCQ rst_d5_safety; rst_d7_safety <= #`TCQ rst_d6_safety; end //if end //prst always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety if(rst_d7_safety == 1 && WR_EN == 1) begin $display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled."); end //if end //always end // grst_safety_ckt endgenerate // if (C_EN_SAFET_CKT == 1) // assertion:the reset shud be atleast 3 cycles wide. generate reg safety_ckt_wr_rst_i = 1'b0; if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync always @* begin wr_rst_reg <= wr_rst_delayed; rd_rst_reg <= rd_rst_delayed; rst_reg <= 1'b0; srst_reg <= 1'b0; end assign rst_2_sync = wr_rst_delayed; assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0; assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0; assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0; assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0; // end : gnrst_sync end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst reg fifo_wrst_done = 1'b0; reg fifo_rrst_done = 1'b0; reg sckt_wrst_i = 1'b0; reg sckt_wrst_i_q = 1'b0; reg rd_rst_active = 1'b0; reg rd_rst_middle = 1'b0; reg sckt_rd_rst_d1 = 1'b0; reg [1:0] rst_delayed_ic_w = 2'h0; wire rst_delayed_ic_w_i; reg [1:0] rst_delayed_ic_r = 2'h0; wire rst_delayed_ic_r_i; wire arst_sync_rst; wire fifo_rst_done; wire fifo_rst_active; assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg; assign rst_2_sync = rst_delayed_ic_w_i; assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1]; assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0; assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0; assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done; assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1]; always @(posedge WR_CLK or posedge rst_delayed) begin if (rst_delayed == 1'b1 && C_HAS_RST) rst_delayed_ic_w <= 2'b11; else rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0}; end assign rst_delayed_ic_w_i = rst_delayed_ic_w[1]; always @(posedge RD_CLK or posedge rst_delayed) begin if (rst_delayed == 1'b1 && C_HAS_RST) rst_delayed_ic_r <= 2'b11; else rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0}; end assign rst_delayed_ic_r_i = rst_delayed_ic_r[1]; always @(posedge WR_CLK) begin sckt_wrst_i_q <= #`TCQ sckt_wrst_i; sckt_wr_rst_i_q <= #`TCQ wr_rst_busy; safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q; if (arst_sync_rst && ~fifo_rst_active) sckt_wrst_i <= #`TCQ 1'b1; else if (sckt_wrst_i && fifo_rst_done) sckt_wrst_i <= #`TCQ 1'b0; else sckt_wrst_i <= #`TCQ sckt_wrst_i; if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1]) fifo_rrst_done <= #`TCQ 1'b1; else if (fifo_rst_done) fifo_rrst_done <= #`TCQ 1'b0; else fifo_rrst_done <= #`TCQ fifo_rrst_done; if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1]) fifo_wrst_done <= #`TCQ 1'b1; else if (fifo_rst_done) fifo_wrst_done <= #`TCQ 1'b0; else fifo_wrst_done <= #`TCQ fifo_wrst_done; end always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin if (rst_delayed_ic_w_i == 1'b1) begin wr_rst_asreg <= 1'b1; end else begin if (wr_rst_asreg_d1 == 1'b1) begin wr_rst_asreg <= #`TCQ 1'b0; end else begin wr_rst_asreg <= #`TCQ wr_rst_asreg; end end end always @(posedge WR_CLK or posedge rst_delayed) begin if (rst_delayed == 1'b1) begin wr_rst_asreg <= 1'b1; end else begin if (wr_rst_asreg_d1 == 1'b1) begin wr_rst_asreg <= #`TCQ 1'b0; end else begin wr_rst_asreg <= #`TCQ wr_rst_asreg; end end end always @(posedge WR_CLK) begin wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg}; wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i}; rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst}; arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i}; end assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2]; assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1]; assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0; always @(posedge WR_CLK or posedge wr_rst_comb) begin if (wr_rst_comb == 1'b1) begin wr_rst_reg <= 1'b1; end else begin wr_rst_reg <= #`TCQ 1'b0; end end always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin if (rst_delayed_ic_r_i == 1'b1) begin rd_rst_asreg <= 1'b1; end else begin if (rd_rst_asreg_d1 == 1'b1) begin rd_rst_asreg <= #`TCQ 1'b0; end else begin rd_rst_asreg <= #`TCQ rd_rst_asreg; end end end always @(posedge RD_CLK) begin rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg}; rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i}; rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2}; sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst; if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin rd_rst_active <= #`TCQ 1'b1; rd_rst_middle <= #`TCQ 1'b1; end else if (safety_ckt_rd_rst) rd_rst_active <= #`TCQ 1'b0; else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst) rd_rst_middle <= #`TCQ 1'b0; end assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2]; assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1]; assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0; always @(posedge RD_CLK or posedge rd_rst_comb) begin if (rd_rst_comb == 1'b1) begin rd_rst_reg <= 1'b1; end else begin rd_rst_reg <= #`TCQ 1'b0; end end // end : g7s_ic_rst end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst reg [1:0] rst_delayed_cc = 2'h0; wire rst_delayed_cc_i; assign rst_comb = !rst_asreg_d2 && rst_asreg; assign rst_2_sync = rst_delayed_cc_i; assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0; assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0; always @(posedge CLK or posedge rst_delayed) begin if (rst_delayed == 1'b1) rst_delayed_cc <= 2'b11; else rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0}; end assign rst_delayed_cc_i = rst_delayed_cc[1]; always @(posedge CLK or posedge rst_delayed_cc_i) begin if (rst_delayed_cc_i == 1'b1) begin rst_asreg <= 1'b1; end else begin if (rst_asreg_d1 == 1'b1) begin rst_asreg <= #`TCQ 1'b0; end else begin rst_asreg <= #`TCQ rst_asreg; end end end always @(posedge CLK) begin wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg}; wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]}; sckt_wr_rst_i_q <= #`TCQ wr_rst_busy; safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q; arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i}; end assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2]; assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1]; assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0; assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0; always @(posedge CLK or posedge rst_comb) begin if (rst_comb == 1'b1) begin rst_reg <= 1'b1; end else begin rst_reg <= #`TCQ 1'b0; end end // end : g7s_cc_rst end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i; assign rd_rst_busy = rst_reg; assign rst_2_sync = srst_delayed; always @* rst_full_ff_i <= rst_reg; always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0; assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0; assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0; always @(posedge CLK) begin rst_delayed_d1 <= #`TCQ srst_delayed; rst_delayed_d2 <= #`TCQ rst_delayed_d1; sckt_wr_rst_i_q <= #`TCQ wr_rst_busy; if (rst_reg || rst_delayed_d2) begin rst_active_i <= #`TCQ 1'b1; end else begin rst_active_i <= #`TCQ rst_reg; end end always @(posedge CLK) begin if (~rst_reg && srst_delayed) begin rst_reg <= #`TCQ 1'b1; end else if (rst_reg) begin rst_reg <= #`TCQ 1'b0; end else begin rst_reg <= #`TCQ rst_reg; end end // end : g8s_cc_rst end else begin assign wr_rst_busy = 1'b0; assign rd_rst_busy = 1'b0; assign safety_ckt_wr_rst = 1'b0; assign safety_ckt_rd_rst = 1'b0; end endgenerate generate if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1 // RST_FULL_GEN replaces the reset falling edge detection used to de-assert // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & // PROG_FULL reg rst_d1 = 1'b0; reg rst_d2 = 1'b0; reg rst_d3 = 1'b0; reg rst_d4 = 1'b0; reg rst_d5 = 1'b0; always @ (posedge rst_2_sync or posedge clk_2_sync) begin if (rst_2_sync) begin rst_d1 <= 1'b1; rst_d2 <= 1'b1; rst_d3 <= 1'b1; rst_d4 <= 1'b1; end else begin if (srst_delayed) begin rst_d1 <= #`TCQ 1'b1; rst_d2 <= #`TCQ 1'b1; rst_d3 <= #`TCQ 1'b1; rst_d4 <= #`TCQ 1'b1; end else begin rst_d1 <= #`TCQ wr_rst_busy; rst_d2 <= #`TCQ rst_d1; rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst; rst_d4 <= #`TCQ rst_d3; end end end always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ; always @* rst_full_gen_i <= rst_d3; end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; end endgenerate // grstd1 endmodule //fifo_generator_v13_1_3_conv_ver module fifo_generator_v13_1_3_sync_stage #( parameter C_WIDTH = 10 ) ( input RST, input CLK, input [C_WIDTH-1:0] DIN, output reg [C_WIDTH-1:0] DOUT = 0 ); always @ (posedge RST or posedge CLK) begin if (RST) DOUT <= 0; else DOUT <= #`TCQ DIN; end endmodule // fifo_generator_v13_1_3_sync_stage /******************************************************************************* * Declaration of Independent-Clocks FIFO Module ******************************************************************************/ module fifo_generator_v13_1_3_bhv_ver_as /*************************************************************************** * Declare user parameters and their defaults ***************************************************************************/ #( parameter C_FAMILY = "virtex7", parameter C_DATA_COUNT_WIDTH = 2, parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_ALMOST_EMPTY = 0, parameter C_HAS_ALMOST_FULL = 0, parameter C_HAS_DATA_COUNT = 0, parameter C_HAS_OVERFLOW = 0, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_RST = 0, parameter C_HAS_UNDERFLOW = 0, parameter C_HAS_VALID = 0, parameter C_HAS_WR_ACK = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_IMPLEMENTATION_TYPE = 0, parameter C_MEMORY_TYPE = 1, parameter C_OVERFLOW_LOW = 0, parameter C_PRELOAD_LATENCY = 1, parameter C_PRELOAD_REGS = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, parameter C_PROG_EMPTY_TYPE = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, parameter C_PROG_FULL_TYPE = 0, parameter C_RD_DATA_COUNT_WIDTH = 2, parameter C_RD_DEPTH = 256, parameter C_RD_PNTR_WIDTH = 8, parameter C_UNDERFLOW_LOW = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_USE_FWFT_DATA_COUNT = 0, parameter C_VALID_LOW = 0, parameter C_WR_ACK_LOW = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_PNTR_WIDTH = 8, parameter C_USE_ECC = 0, parameter C_ENABLE_RST_SYNC = 1, parameter C_ERROR_INJECTION_TYPE = 0, parameter C_SYNCHRONIZER_STAGE = 2 ) /*************************************************************************** * Declare Input and Output Ports ***************************************************************************/ ( input SAFETY_CKT_WR_RST, input SAFETY_CKT_RD_RST, input [C_DIN_WIDTH-1:0] DIN, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, input RD_CLK, input RD_EN, input RD_EN_USER, input RST, input RST_FULL_GEN, input RST_FULL_FF, input WR_RST, input RD_RST, input WR_CLK, input WR_EN, input INJECTDBITERR, input INJECTSBITERR, input USER_EMPTY_FB, input fab_read_data_valid_i, input read_data_valid_i, input ram_valid_i, output reg ALMOST_EMPTY = 1'b1, output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL, output [C_DOUT_WIDTH-1:0] DOUT, output reg EMPTY = 1'b1, output reg EMPTY_FB = 1'b1, output reg FULL = C_FULL_FLAGS_RST_VAL, output OVERFLOW, output PROG_EMPTY, output PROG_FULL, output VALID, output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, output UNDERFLOW, output WR_ACK, output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, output SBITERR, output DBITERR ); reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; /*************************************************************************** * Parameters used as constants **************************************************************************/ localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0; //When RST is present, set FULL reset value to '1'. //If core has no RST, make sure FULL powers-on as '0'. localparam C_DEPTH_RATIO_WR = (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; localparam C_DEPTH_RATIO_RD = (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC // -----------------|------------------|-----------------|--------------- // 1 | 8 | C_RD_PNTR_WIDTH | 2 // 1 | 4 | C_RD_PNTR_WIDTH | 2 // 1 | 2 | C_RD_PNTR_WIDTH | 2 // 1 | 1 | C_WR_PNTR_WIDTH | 2 // 2 | 1 | C_WR_PNTR_WIDTH | 4 // 4 | 1 | C_WR_PNTR_WIDTH | 8 // 8 | 1 | C_WR_PNTR_WIDTH | 16 localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; localparam [31:0] log2_reads_per_write = log2_val(reads_per_write); localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; localparam [31:0] log2_writes_per_read = log2_val(writes_per_read); /************************************************************************** * FIFO Contents Tracking and Data Count Calculations *************************************************************************/ // Memory which will be used to simulate a FIFO reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; // Local parameters used to determine whether to inject ECC error or not localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0; localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION; // Array that holds the error injection type (single/double bit error) on // a specific write operation, which is returned on read to corrupt the // output data. reg [1:0] ecc_err[C_WR_DEPTH-1:0]; //The amount of data stored in the FIFO at any time is given // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK // domain. //num_wr_bits is calculated by considering the total words in the FIFO, // and the state of the read pointer (which may not have yet crossed clock // domains.) //num_rd_bits is calculated by considering the total words in the FIFO, // and the state of the write pointer (which may not have yet crossed clock // domains.) reg [31:0] num_wr_bits; reg [31:0] num_rd_bits; reg [31:0] next_num_wr_bits; reg [31:0] next_num_rd_bits; //The write pointer - tracks write operations // (Works opposite to core: wr_ptr is a DOWN counter) reg [31:0] wr_ptr; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; wire wr_rst_i = WR_RST; reg wr_rst_d1 =0; //The read pointer - tracks read operations // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) reg [31:0] rd_ptr; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; wire rd_rst_i = RD_RST; wire ram_rd_en; wire empty_int; wire almost_empty_int; wire ram_wr_en; wire full_int; wire almost_full_int; reg ram_rd_en_d1 = 1'b0; reg fab_rd_en_d1 = 1'b0; // Delayed ram_rd_en is needed only for STD Embedded register option generate if (C_PRELOAD_LATENCY == 2) begin : grd_d always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) ram_rd_en_d1 <= 1'b0; else ram_rd_en_d1 <= #`TCQ ram_rd_en; end end endgenerate generate if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1 always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) ram_rd_en_d1 <= 1'b0; else ram_rd_en_d1 <= #`TCQ ram_rd_en; fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; end end endgenerate // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; end else begin : rdl // Read depth lesser than or equal to write depth assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end endgenerate // Generate Empty and Almost Empty // ram_rd_en used to determine EMPTY should depend on the EMPTY. assign ram_rd_en = RD_EN & !EMPTY; assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); // Register Empty and Almost Empty always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin EMPTY <= 1'b1; ALMOST_EMPTY <= 1'b1; rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}}; end else begin rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; if (empty_int) EMPTY <= #`TCQ 1'b1; else EMPTY <= #`TCQ 1'b0; if (!EMPTY) begin if (almost_empty_int) ALMOST_EMPTY <= #`TCQ 1'b1; else ALMOST_EMPTY <= #`TCQ 1'b0; end end // rd_rst_i end // always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin EMPTY_FB <= 1'b1; end else begin if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) EMPTY_FB <= #`TCQ 1'b1; else if (empty_int) EMPTY_FB <= #`TCQ 1'b1; else EMPTY_FB <= #`TCQ 1'b0; end // rd_rst_i end // always // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; end else begin : wdl // Write depth lesser than or equal to read depth assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; end endgenerate // Generate FULL and ALMOST_FULL // ram_wr_en used to determine FULL should depend on the FULL. assign ram_wr_en = WR_EN & !FULL; assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); // Register FULL and ALMOST_FULL Empty always @ (posedge WR_CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF) begin FULL <= C_FULL_FLAGS_RST_VAL; ALMOST_FULL <= C_FULL_FLAGS_RST_VAL; end else begin if (full_int) begin FULL <= #`TCQ 1'b1; end else begin FULL <= #`TCQ 1'b0; end if (RST_FULL_GEN) begin ALMOST_FULL <= #`TCQ 1'b0; end else if (!FULL) begin if (almost_full_int) ALMOST_FULL <= #`TCQ 1'b1; else ALMOST_FULL <= #`TCQ 1'b0; end end // wr_rst_i end // always always @ (posedge WR_CLK or posedge wr_rst_i) begin if (wr_rst_i) begin wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}}; end else begin wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; end // wr_rst_i end // always // Determine which stage in FWFT registers are valid reg stage1_valid = 0; reg stage2_valid = 0; generate if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin stage1_valid <= 0; stage2_valid <= 0; end else begin if (!stage1_valid && !stage2_valid) begin if (!EMPTY) stage1_valid <= #`TCQ 1'b1; else stage1_valid <= #`TCQ 1'b0; end else if (stage1_valid && !stage2_valid) begin if (EMPTY) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end end else if (!stage1_valid && stage2_valid) begin if (EMPTY && RD_EN_USER) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b0; end else if (!EMPTY && RD_EN_USER) begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b0; end else if (!EMPTY && !RD_EN_USER) begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end end else if (stage1_valid && stage2_valid) begin if (EMPTY && RD_EN_USER) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end end else begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b0; end end // rd_rst_i end // always end endgenerate //Pointers passed into opposite clock domain reg [31:0] wr_ptr_rdclk; reg [31:0] wr_ptr_rdclk_next; reg [31:0] rd_ptr_wrclk; reg [31:0] rd_ptr_wrclk_next; //Amount of data stored in the FIFO scaled to the narrowest (deepest) port // (Do not include data in FWFT stages) //Used to calculate PROG_EMPTY. wire [31:0] num_read_words_pe = num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); //Amount of data stored in the FIFO scaled to the narrowest (deepest) port // (Do not include data in FWFT stages) //Used to calculate PROG_FULL. wire [31:0] num_write_words_pf = num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); /************************** * Read Data Count *************************/ reg [31:0] num_read_words_dc; reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; always @(num_rd_bits) begin if (C_USE_FWFT_DATA_COUNT) begin //If using extra logic for FWFT Data Counts, // then scale FIFO contents to read domain, // and add two read words for FWFT stages //This value is only a temporary value and not used in the code. num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); //Trim the read words for use with RD_DATA_COUNT num_read_words_sized_i = num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; end else begin //If not using extra logic for FWFT Data Counts, // then scale FIFO contents to read domain. //This value is only a temporary value and not used in the code. num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; //Trim the read words for use with RD_DATA_COUNT num_read_words_sized_i = num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; end //if (C_USE_FWFT_DATA_COUNT) end //always /************************** * Write Data Count *************************/ reg [31:0] num_write_words_dc; reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; always @(num_wr_bits) begin if (C_USE_FWFT_DATA_COUNT) begin //Calculate the Data Count value for the number of write words, // when using First-Word Fall-Through with extra logic for Data // Counts. This takes into consideration the number of words that // are expected to be stored in the FWFT register stages (it always // assumes they are filled). //This value is scaled to the Write Domain. //The expression (((A-1)/B))+1 divides A/B, but takes the // ceiling of the result. //When num_wr_bits==0, set the result manually to prevent // division errors. //EXTRA_WORDS_DC is the number of words added to write_words // due to FWFT. //This value is only a temporary value and not used in the code. num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; //Trim the write words for use with WR_DATA_COUNT num_write_words_sized_i = num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; end else begin //Calculate the Data Count value for the number of write words, when NOT // using First-Word Fall-Through with extra logic for Data Counts. This // calculates only the number of words in the internal FIFO. //The expression (((A-1)/B))+1 divides A/B, but takes the // ceiling of the result. //This value is scaled to the Write Domain. //When num_wr_bits==0, set the result manually to prevent // division errors. //This value is only a temporary value and not used in the code. num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; //Trim the read words for use with RD_DATA_COUNT num_write_words_sized_i = num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; end //if (C_USE_FWFT_DATA_COUNT) end //always /*************************************************************************** * Internal registers and wires **************************************************************************/ //Temporary signals used for calculating the model's outputs. These //are only used in the assign statements immediately following wire, //parameter, and function declarations. wire [C_DOUT_WIDTH-1:0] ideal_dout_out; wire valid_i; wire valid_out1; wire valid_out2; wire valid_out; wire underflow_i; //Ideal FIFO signals. These are the raw output of the behavioral model, //which behaves like an ideal FIFO. reg [1:0] err_type = 0; reg [1:0] err_type_d1 = 0; reg [1:0] err_type_both = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0; reg ideal_wr_ack = 0; reg ideal_valid = 0; reg ideal_overflow = C_OVERFLOW_LOW; reg ideal_underflow = C_UNDERFLOW_LOW; reg ideal_prog_full = 0; reg ideal_prog_empty = 1; reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; //Assorted reg values for delayed versions of signals reg valid_d1 = 0; reg valid_d2 = 0; //user specified value for reseting the size of the fifo reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; //temporary registers for WR_RESPONSE_LATENCY feature integer tmp_wr_listsize; integer tmp_rd_listsize; //Signal for registered version of prog full and empty //Threshold values for Programmable Flags integer prog_empty_actual_thresh_assert; integer prog_empty_actual_thresh_negate; integer prog_full_actual_thresh_assert; integer prog_full_actual_thresh_negate; /**************************************************************************** * Function Declarations ***************************************************************************/ /************************************************************************** * write_fifo * This task writes a word to the FIFO memory and updates the * write pointer. * FIFO size is relative to write domain. ***************************************************************************/ task write_fifo; begin memory[wr_ptr] <= DIN; wr_pntr <= #`TCQ wr_pntr + 1; // Store the type of error injection (double/single) on write case (C_ERROR_INJECTION_TYPE) 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; default: ecc_err[wr_ptr] <= 0; endcase // (Works opposite to core: wr_ptr is a DOWN counter) if (wr_ptr == 0) begin wr_ptr <= C_WR_DEPTH - 1; end else begin wr_ptr <= wr_ptr - 1; end end endtask // write_fifo /************************************************************************** * read_fifo * This task reads a word from the FIFO memory and updates the read * pointer. It's output is the ideal_dout bus. * FIFO size is relative to write domain. ***************************************************************************/ task read_fifo; integer i; reg [C_DOUT_WIDTH-1:0] tmp_dout; reg [C_DIN_WIDTH-1:0] memory_read; reg [31:0] tmp_rd_ptr; reg [31:0] rd_ptr_high; reg [31:0] rd_ptr_low; reg [1:0] tmp_ecc_err; begin rd_pntr <= #`TCQ rd_pntr + 1; // output is wider than input if (reads_per_write == 0) begin tmp_dout = 0; tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); for (i = writes_per_read - 1; i >= 0; i = i - 1) begin tmp_dout = tmp_dout << C_DIN_WIDTH; tmp_dout = tmp_dout | memory[tmp_rd_ptr]; // (Works opposite to core: rd_ptr is a DOWN counter) if (tmp_rd_ptr == 0) begin tmp_rd_ptr = C_WR_DEPTH - 1; end else begin tmp_rd_ptr = tmp_rd_ptr - 1; end end // output is symmetric end else if (reads_per_write == 1) begin tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; // Retreive the error injection type. Based on the error injection type // corrupt the output data. tmp_ecc_err = ecc_err[rd_ptr]; if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error if (C_DOUT_WIDTH == 1) begin $display("FAILURE : Data width must be >= 2 for double bit error injection."); $finish; end else if (C_DOUT_WIDTH == 2) tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; else tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; end else begin tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; end err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; end else begin err_type <= 0; end // input is wider than output end else begin rd_ptr_high = rd_ptr >> log2_reads_per_write; rd_ptr_low = rd_ptr & (reads_per_write - 1); memory_read = memory[rd_ptr_high]; tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); end ideal_dout <= tmp_dout; // (Works opposite to core: rd_ptr is a DOWN counter) if (rd_ptr == 0) begin rd_ptr <= C_RD_DEPTH - 1; end else begin rd_ptr <= rd_ptr - 1; end end endtask /************************************************************************** * log2_val * Returns the 'log2' value for the input value for the supported ratios ***************************************************************************/ function [31:0] log2_val; input [31:0] binary_val; begin if (binary_val == 8) begin log2_val = 3; end else if (binary_val == 4) begin log2_val = 2; end else begin log2_val = 1; end end endfunction /*********************************************************************** * hexstr_conv * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) ***********************************************************************/ function [C_DOUT_WIDTH-1:0] hexstr_conv; input [(C_DOUT_WIDTH*8)-1:0] def_data; integer index,i,j; reg [3:0] bin; begin index = 0; hexstr_conv = 'b0; for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin case (def_data[7:0]) 8'b00000000 : begin bin = 4'b0000; i = -1; end 8'b00110000 : bin = 4'b0000; 8'b00110001 : bin = 4'b0001; 8'b00110010 : bin = 4'b0010; 8'b00110011 : bin = 4'b0011; 8'b00110100 : bin = 4'b0100; 8'b00110101 : bin = 4'b0101; 8'b00110110 : bin = 4'b0110; 8'b00110111 : bin = 4'b0111; 8'b00111000 : bin = 4'b1000; 8'b00111001 : bin = 4'b1001; 8'b01000001 : bin = 4'b1010; 8'b01000010 : bin = 4'b1011; 8'b01000011 : bin = 4'b1100; 8'b01000100 : bin = 4'b1101; 8'b01000101 : bin = 4'b1110; 8'b01000110 : bin = 4'b1111; 8'b01100001 : bin = 4'b1010; 8'b01100010 : bin = 4'b1011; 8'b01100011 : bin = 4'b1100; 8'b01100100 : bin = 4'b1101; 8'b01100101 : bin = 4'b1110; 8'b01100110 : bin = 4'b1111; default : begin bin = 4'bx; end endcase for( j=0; j<4; j=j+1) begin if ((index*4)+j < C_DOUT_WIDTH) begin hexstr_conv[(index*4)+j] = bin[j]; end end index = index + 1; def_data = def_data >> 8; end end endfunction /************************************************************************* * Initialize Signals for clean power-on simulation *************************************************************************/ initial begin num_wr_bits = 0; num_rd_bits = 0; next_num_wr_bits = 0; next_num_rd_bits = 0; rd_ptr = C_RD_DEPTH - 1; wr_ptr = C_WR_DEPTH - 1; wr_pntr = 0; rd_pntr = 0; rd_ptr_wrclk = rd_ptr; wr_ptr_rdclk = wr_ptr; dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); ideal_dout = dout_reset_val; err_type = 0; err_type_d1 = 0; err_type_both = 0; ideal_dout_d1 = dout_reset_val; ideal_wr_ack = 1'b0; ideal_valid = 1'b0; valid_d1 = 1'b0; valid_d2 = 1'b0; ideal_overflow = C_OVERFLOW_LOW; ideal_underflow = C_UNDERFLOW_LOW; ideal_wr_count = 0; ideal_rd_count = 0; ideal_prog_full = 1'b0; ideal_prog_empty = 1'b1; end /************************************************************************* * Connect the module inputs and outputs to the internal signals of the * behavioral model. *************************************************************************/ //Inputs /* wire [C_DIN_WIDTH-1:0] DIN; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; wire RD_CLK; wire RD_EN; wire RST; wire WR_CLK; wire WR_EN; */ //*************************************************************************** // Dout may change behavior based on latency //*************************************************************************** assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )? ideal_dout_d1: ideal_dout; assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; //*************************************************************************** // Assign SBITERR and DBITERR based on latency //*************************************************************************** assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && (C_PRELOAD_LATENCY == 2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ? err_type_d1[0]: err_type[0]; assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? err_type_d1[1]: err_type[1]; //*************************************************************************** // Safety-ckt logic with embedded reg/fabric reg //*************************************************************************** generate if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; // if (C_HAS_VALID == 1) begin // assign valid_out = valid_d1; // end always@(posedge RD_CLK) begin rst_delayed_sft1 <= #`TCQ rd_rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) ram_rd_en_d1 <= #`TCQ 1'b0; else ram_rd_en_d1 <= #`TCQ ram_rd_en; end always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin if (rst_delayed_sft2 == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge RD_CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin if (ram_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout; err_type_d1[0] <= #`TCQ err_type[0]; err_type_d1[1] <= #`TCQ err_type[1]; end end end end endgenerate //*************************************************************************** // Safety-ckt logic with embedded reg + fabric reg //*************************************************************************** generate if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge RD_CLK) begin rst_delayed_sft1 <= #`TCQ rd_rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) ram_rd_en_d1 <= #`TCQ 1'b0; else begin ram_rd_en_d1 <= #`TCQ ram_rd_en; fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; end end always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin if (rst_delayed_sft2 == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge RD_CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end end else begin if (ram_rd_en_d1) begin ideal_dout_both <= #`TCQ ideal_dout; err_type_both[0] <= #`TCQ err_type[0]; err_type_both[1] <= #`TCQ err_type[1]; end if (fab_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout_both; err_type_d1[0] <= #`TCQ err_type_both[0]; err_type_d1[1] <= #`TCQ err_type_both[1]; end end end end endgenerate //*************************************************************************** // Overflow may be active-low //*************************************************************************** generate if (C_HAS_OVERFLOW==1) begin : blockOF1 assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; end endgenerate assign PROG_EMPTY = ideal_prog_empty; assign PROG_FULL = ideal_prog_full; //*************************************************************************** // Valid may change behavior based on latency or active-low //*************************************************************************** generate if (C_HAS_VALID==1) begin : blockVL1 assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; assign valid_out1 = (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)? valid_d1: valid_i; assign valid_out2 = (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)? valid_d2: valid_i; assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1; assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; end endgenerate //*************************************************************************** // Underflow may change behavior based on latency or active-low //*************************************************************************** generate if (C_HAS_UNDERFLOW==1) begin : blockUF1 assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; end endgenerate //*************************************************************************** // Write acknowledge may be active low //*************************************************************************** generate if (C_HAS_WR_ACK==1) begin : blockWK1 assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; end endgenerate //*************************************************************************** // Generate RD_DATA_COUNT if Use Extra Logic option is selected //*************************************************************************** generate if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; wire [C_PNTR_WIDTH:0] diff_wr_rd; reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; always @* begin if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin adjusted_wr_pntr = wr_pntr; adjusted_rd_pntr = 0; adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin adjusted_rd_pntr = rd_pntr_wr; adjusted_wr_pntr = 0; adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; end else begin adjusted_wr_pntr = wr_pntr; adjusted_rd_pntr = rd_pntr_wr; end end // always @* assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; always @ (posedge wr_rst_i or posedge WR_CLK) begin if (wr_rst_i) wr_data_count_i <= 0; else wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; end // always @ (posedge WR_CLK or posedge WR_CLK) always @* begin if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; else wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; end // always @* end // wdc_fwft_ext endgenerate //*************************************************************************** // Generate RD_DATA_COUNT if Use Extra Logic option is selected //*************************************************************************** reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; always @* begin if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin adjusted_wr_pntr_rd = 0; adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; end else begin adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end end // always @* assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i) begin rdc_fwft_ext_as <= 0; end else begin if (!stage2_valid) rdc_fwft_ext_as <= #`TCQ 0; else if (!stage1_valid && stage2_valid) rdc_fwft_ext_as <= #`TCQ 1; else rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; end end // always @ (posedge WR_CLK or posedge WR_CLK) end // rdc_fwft_ext end endgenerate generate if (C_USE_EMBEDDED_REG == 3) begin if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; always @* begin if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin adjusted_wr_pntr_rd = 0; adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; end else begin adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end end // always @* assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1; // assign diff_rd_wr_1 = diff_rd_wr +2'h2; always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i) begin rdc_fwft_ext_as <= #`TCQ 0; end else begin //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1))) // rdc_fwft_ext_as <= 1'b0; //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) // rdc_fwft_ext_as <= 1'b1; //else rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ; end end end end endgenerate //*************************************************************************** // Assign the read data count value only if it is selected, // otherwise output zeros. //*************************************************************************** generate if (C_HAS_RD_DATA_COUNT == 1) begin : grdc assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; end endgenerate generate if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}}; end endgenerate //*************************************************************************** // Assign the write data count value only if it is selected, // otherwise output zeros //*************************************************************************** generate if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; end endgenerate generate if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}}; end endgenerate /************************************************************************** * Assorted registers for delayed versions of signals **************************************************************************/ //Capture delayed version of valid generate if (C_HAS_VALID==1) begin : blockVL2 always @(posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i == 1'b1) begin valid_d1 <= 1'b0; valid_d2 <= 1'b0; end else begin valid_d1 <= #`TCQ valid_i; valid_d2 <= #`TCQ valid_d1; end // if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin // valid_d2 <= #`TCQ valid_d1; // end end end endgenerate //Capture delayed version of dout /************************************************************************** *embedded/fabric reg with no safety ckt **************************************************************************/ generate if (C_USE_EMBEDDED_REG < 3) begin always @(posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge RD_CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout <= #`TCQ dout_reset_val; end // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) err_type_d1 <= #`TCQ 0; end else if (ram_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout; err_type_d1 <= #`TCQ err_type; end end end endgenerate /************************************************************************** *embedded + fabric reg with no safety ckt **************************************************************************/ generate if (C_USE_EMBEDDED_REG == 3) begin always @(posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge RD_CLK) ideal_dout <= #`TCQ dout_reset_val; ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end end else begin if (ram_rd_en_d1) begin ideal_dout_both <= #`TCQ ideal_dout; err_type_both <= #`TCQ err_type; end if (fab_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout_both; err_type_d1 <= #`TCQ err_type_both; end end end end endgenerate /************************************************************************** * Overflow and Underflow Flag calculation * (handled separately because they don't support rst) **************************************************************************/ generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw always @(posedge WR_CLK) begin ideal_overflow <= #`TCQ WR_EN & FULL; end end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw always @(posedge WR_CLK) begin //ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i); ideal_overflow <= #`TCQ WR_EN & (FULL ); end end endgenerate generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw always @(posedge RD_CLK) begin ideal_underflow <= #`TCQ EMPTY & RD_EN; end end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw always @(posedge RD_CLK) begin ideal_underflow <= #`TCQ (EMPTY) & RD_EN; //ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN; end end endgenerate /************************************************************************** * Write/Read Pointer Synchronization **************************************************************************/ localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1; wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B]; wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B]; genvar gss; generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst fifo_generator_v13_1_3_sync_stage #( .C_WIDTH (C_WR_PNTR_WIDTH) ) rd_stg_inst ( .RST (rd_rst_i), .CLK (RD_CLK), .DIN (wr_pntr_sync_stgs[gss-1]), .DOUT (wr_pntr_sync_stgs[gss]) ); fifo_generator_v13_1_3_sync_stage #( .C_WIDTH (C_RD_PNTR_WIDTH) ) wr_stg_inst ( .RST (wr_rst_i), .CLK (WR_CLK), .DIN (rd_pntr_sync_stgs[gss-1]), .DOUT (rd_pntr_sync_stgs[gss]) ); end endgenerate // Sync_stage_inst assign wr_pntr_sync_stgs[0] = wr_pntr_rd1; assign rd_pntr_sync_stgs[0] = rd_pntr_wr1; always@* begin wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B]; rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B]; end /************************************************************************** * Write Domain Logic **************************************************************************/ reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0) wr_pntr <= 0; else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1) wr_pntr <= #`TCQ 0; end always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w /****** Reset fifo (case 1)***************************************/ if (wr_rst_i == 1'b1) begin num_wr_bits <= 0; next_num_wr_bits = 0; wr_ptr <= C_WR_DEPTH - 1; rd_ptr_wrclk <= C_RD_DEPTH - 1; ideal_wr_ack <= 0; ideal_wr_count <= 0; tmp_wr_listsize = 0; rd_ptr_wrclk_next <= 0; wr_pntr_rd1 <= 0; end else begin //wr_rst_i==0 wr_pntr_rd1 <= #`TCQ wr_pntr; //Determine the current number of words in the FIFO tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : num_wr_bits/C_DIN_WIDTH; rd_ptr_wrclk_next = rd_ptr; if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin next_num_wr_bits = num_wr_bits - C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH - rd_ptr_wrclk_next); end else begin next_num_wr_bits = num_wr_bits - C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); end //If this is a write, handle the write by adding the value // to the linked list, and updating all outputs appropriately if (WR_EN == 1'b1) begin if (FULL == 1'b1) begin //If the FIFO is full, do NOT perform the write, // update flags accordingly if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) begin //write unsuccessful - do not change contents //Do not acknowledge the write ideal_wr_ack <= #`TCQ 0; //Reminder that FIFO is still full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is one from full, but reporting full end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == C_FIFO_WR_DEPTH-1) begin //No change to FIFO //Write not successful ideal_wr_ack <= #`TCQ 0; //With DEPTH-1 words in the FIFO, it is almost_full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is completely empty, but it is // reporting FULL for some reason (like reset) end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= C_FIFO_WR_DEPTH-2) begin //No change to FIFO //Write not successful ideal_wr_ack <= #`TCQ 0; //FIFO is really not close to full, so change flag status. ideal_wr_count <= #`TCQ num_write_words_sized_i; end //(tmp_wr_listsize == 0) end else begin //If the FIFO is full, do NOT perform the write, // update flags accordingly if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) begin //write unsuccessful - do not change contents //Do not acknowledge the write ideal_wr_ack <= #`TCQ 0; //Reminder that FIFO is still full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is one from full end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == C_FIFO_WR_DEPTH-1) begin //Add value on DIN port to FIFO write_fifo; next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; //Write successful, so issue acknowledge // and no error ideal_wr_ack <= #`TCQ 1; //This write is CAUSING the FIFO to go full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is 2 from full end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == C_FIFO_WR_DEPTH-2) begin //Add value on DIN port to FIFO write_fifo; next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; //Write successful, so issue acknowledge // and no error ideal_wr_ack <= #`TCQ 1; //Still 2 from full ideal_wr_count <= #`TCQ num_write_words_sized_i; //If the FIFO is not close to being full end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < C_FIFO_WR_DEPTH-2) begin //Add value on DIN port to FIFO write_fifo; next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; //Write successful, so issue acknowledge // and no error ideal_wr_ack <= #`TCQ 1; //Not even close to full. ideal_wr_count <= num_write_words_sized_i; end end end else begin //(WR_EN == 1'b1) //If user did not attempt a write, then do not // give ack or err ideal_wr_ack <= #`TCQ 0; ideal_wr_count <= #`TCQ num_write_words_sized_i; end num_wr_bits <= #`TCQ next_num_wr_bits; rd_ptr_wrclk <= #`TCQ rd_ptr; end //wr_rst_i==0 end // gen_fifo_w /*************************************************************************** * Programmable FULL flags ***************************************************************************/ wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val; wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val; generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC; assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC; end else begin // STD assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL; assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL; end endgenerate always @(posedge WR_CLK or posedge wr_rst_i) begin if (wr_rst_i == 1'b1) begin diff_pntr <= 0; end else begin if (ram_wr_en) diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1); else if (!ram_wr_en) diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr); end end always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf if (RST_FULL_FF == 1'b1) begin ideal_prog_full <= C_FULL_FLAGS_RST_VAL; end else begin if (RST_FULL_GEN) ideal_prog_full <= #`TCQ 0; //Single Programmable Full Constant Threshold else if (C_PROG_FULL_TYPE == 1) begin if (FULL == 0) begin if (diff_pntr >= pf_thr_assert_val) ideal_prog_full <= #`TCQ 1; else ideal_prog_full <= #`TCQ 0; end else ideal_prog_full <= #`TCQ ideal_prog_full; //Two Programmable Full Constant Thresholds end else if (C_PROG_FULL_TYPE == 2) begin if (FULL == 0) begin if (diff_pntr >= pf_thr_assert_val) ideal_prog_full <= #`TCQ 1; else if (diff_pntr < pf_thr_negate_val) ideal_prog_full <= #`TCQ 0; else ideal_prog_full <= #`TCQ ideal_prog_full; end else ideal_prog_full <= #`TCQ ideal_prog_full; //Single Programmable Full Threshold Input end else if (C_PROG_FULL_TYPE == 3) begin if (FULL == 0) begin if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC)) ideal_prog_full <= #`TCQ 1; else ideal_prog_full <= #`TCQ 0; end else begin // STD if (diff_pntr >= PROG_FULL_THRESH) ideal_prog_full <= #`TCQ 1; else ideal_prog_full <= #`TCQ 0; end end else ideal_prog_full <= #`TCQ ideal_prog_full; //Two Programmable Full Threshold Inputs end else if (C_PROG_FULL_TYPE == 4) begin if (FULL == 0) begin if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC)) ideal_prog_full <= #`TCQ 1; else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC)) ideal_prog_full <= #`TCQ 0; else ideal_prog_full <= #`TCQ ideal_prog_full; end else begin // STD if (diff_pntr >= PROG_FULL_THRESH_ASSERT) ideal_prog_full <= #`TCQ 1; else if (diff_pntr < PROG_FULL_THRESH_NEGATE) ideal_prog_full <= #`TCQ 0; else ideal_prog_full <= #`TCQ ideal_prog_full; end end else ideal_prog_full <= #`TCQ ideal_prog_full; end // C_PROG_FULL_TYPE end //wr_rst_i==0 end // /************************************************************************** * Read Domain Logic **************************************************************************/ /********************************************************* * Programmable EMPTY flags *********************************************************/ //Determine the Assert and Negate thresholds for Programmable Empty wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val; wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val; reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0; always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe if (rd_rst_i) begin diff_pntr_rd <= 0; ideal_prog_empty <= 1'b1; end else begin if (ram_rd_en) diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1; else if (!ram_rd_en) diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr); else diff_pntr_rd <= #`TCQ diff_pntr_rd; if (C_PROG_EMPTY_TYPE == 1) begin if (EMPTY == 0) begin if (diff_pntr_rd <= pe_thr_assert_val) ideal_prog_empty <= #`TCQ 1; else ideal_prog_empty <= #`TCQ 0; end else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else if (C_PROG_EMPTY_TYPE == 2) begin if (EMPTY == 0) begin if (diff_pntr_rd <= pe_thr_assert_val) ideal_prog_empty <= #`TCQ 1; else if (diff_pntr_rd > pe_thr_negate_val) ideal_prog_empty <= #`TCQ 0; else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else if (C_PROG_EMPTY_TYPE == 3) begin if (EMPTY == 0) begin if (diff_pntr_rd <= pe_thr_assert_val) ideal_prog_empty <= #`TCQ 1; else ideal_prog_empty <= #`TCQ 0; end else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else if (C_PROG_EMPTY_TYPE == 4) begin if (EMPTY == 0) begin if (diff_pntr_rd <= pe_thr_assert_val) ideal_prog_empty <= #`TCQ 1; else if (diff_pntr_rd > pe_thr_negate_val) ideal_prog_empty <= #`TCQ 0; else ideal_prog_empty <= #`TCQ ideal_prog_empty; end else ideal_prog_empty <= #`TCQ ideal_prog_empty; end //C_PROG_EMPTY_TYPE end end // gen_pe generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH; end endgenerate // single_pe_thr_input generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT; assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE; end endgenerate // multiple_pe_thr_input generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL; assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL; end endgenerate // single_multiple_pe_thr_const always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp if (rd_rst_i && C_EN_SAFETY_CKT == 0) rd_pntr <= 0; else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1) rd_pntr <= #`TCQ 0; end always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as /****** Reset fifo (case 1)***************************************/ if (rd_rst_i) begin num_rd_bits <= 0; next_num_rd_bits = 0; rd_ptr <= C_RD_DEPTH -1; rd_pntr_wr1 <= 0; wr_ptr_rdclk <= C_WR_DEPTH -1; // DRAM resets asynchronously if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) ideal_dout <= dout_reset_val; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type <= 0; err_type_d1 <= 0; err_type_both <= 0; end ideal_valid <= 1'b0; ideal_rd_count <= 0; end else begin //rd_rst_i==0 rd_pntr_wr1 <= #`TCQ rd_pntr; //Determine the current number of words in the FIFO tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : num_rd_bits/C_DOUT_WIDTH; wr_ptr_rdclk_next = wr_ptr; if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin next_num_rd_bits = num_rd_bits + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH - wr_ptr_rdclk_next); end else begin next_num_rd_bits = num_rd_bits + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); end /*****************************************************************/ // Read Operation - Read Latency 1 /*****************************************************************/ if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin ideal_valid <= #`TCQ 1'b0; if (ram_rd_en == 1'b1) begin if (EMPTY == 1'b1) begin //If the FIFO is completely empty, and is reporting empty if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Reminder that FIFO is still empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize <= 0) //If the FIFO is one from empty, but it is reporting empty else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Note that FIFO is no longer empty, but is almost empty (has one word left) ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 1) //If the FIFO is two from empty, and is reporting empty else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Fifo has two words, so is neither empty or almost empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 2) //If the FIFO is not close to empty, but is reporting that it is // Treat the FIFO as empty this time, but unset EMPTY flags. if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Note that the FIFO is No Longer Empty or Almost Empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) end // else: if(ideal_empty == 1'b1) else //if (ideal_empty == 1'b0) begin //If the FIFO is completely full, and we are successfully reading from it if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Not close to empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) //If the FIFO is not close to being empty else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Not close to empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) //If the FIFO is two from empty else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Fifo is not yet empty. It is going almost_empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 2) //If the FIFO is one from empty else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Note that FIFO is GOING empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 1) //If the FIFO is completely empty else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize <= 0) end // if (ideal_empty == 1'b0) end //(RD_EN == 1'b1) else //if (RD_EN == 1'b0) begin //If user did not attempt a read, do not give an ack or err ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ num_read_words_sized_i; end // else: !if(RD_EN == 1'b1) /*****************************************************************/ // Read Operation - Read Latency 0 /*****************************************************************/ end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin ideal_valid <= #`TCQ 1'b0; if (ram_rd_en == 1'b1) begin if (EMPTY == 1'b1) begin //If the FIFO is completely empty, and is reporting empty if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Reminder that FIFO is still empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is one from empty, but it is reporting empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Note that FIFO is no longer empty, but is almost empty (has one word left) ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is two from empty, and is reporting empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Fifo has two words, so is neither empty or almost empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is not close to empty, but is reporting that it is // Treat the FIFO as empty this time, but unset EMPTY flags. end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Note that the FIFO is No Longer Empty or Almost Empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) end else begin //If the FIFO is completely full, and we are successfully reading from it if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Not close to empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is not close to being empty end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Not close to empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is two from empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Fifo is not yet empty. It is going almost_empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is one from empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin //Read the value from the FIFO read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; //Note that FIFO is GOING empty ideal_rd_count <= #`TCQ num_read_words_sized_i; //If the FIFO is completely empty end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin //Do not change the contents of the FIFO //Do not acknowledge the read from empty FIFO ideal_valid <= #`TCQ 1'b0; //Reminder that FIFO is still empty ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize <= 0) end // if (ideal_empty == 1'b0) end else begin//(RD_EN == 1'b0) //If user did not attempt a read, do not give an ack or err ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ num_read_words_sized_i; end // else: !if(RD_EN == 1'b1) end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) num_rd_bits <= #`TCQ next_num_rd_bits; wr_ptr_rdclk <= #`TCQ wr_ptr; end //rd_rst_i==0 end //always gen_fifo_r_as endmodule // fifo_generator_v13_1_3_bhv_ver_as /******************************************************************************* * Declaration of Low Latency Asynchronous FIFO ******************************************************************************/ module fifo_generator_v13_1_3_beh_ver_ll_afifo /*************************************************************************** * Declare user parameters and their defaults ***************************************************************************/ #( parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_RD_DEPTH = 256, parameter C_RD_PNTR_WIDTH = 8, parameter C_USE_DOUT_RST = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_PNTR_WIDTH = 8, parameter C_FIFO_TYPE = 0 ) /*************************************************************************** * Declare Input and Output Ports ***************************************************************************/ ( input [C_DIN_WIDTH-1:0] DIN, input RD_CLK, input RD_EN, input WR_RST, input RD_RST, input WR_CLK, input WR_EN, output reg [C_DOUT_WIDTH-1:0] DOUT = 0, output reg EMPTY = 1'b1, output reg FULL = C_FULL_FLAGS_RST_VAL ); //----------------------------------------------------------------------------- // Low Latency Asynchronous FIFO //----------------------------------------------------------------------------- // Memory which will be used to simulate a FIFO reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; integer i; initial begin for (i = 0; i < C_WR_DEPTH; i = i + 1) memory[i] = 0; end reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0; wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0; reg ll_afifo_full = 1'b0; reg ll_afifo_empty = 1'b1; wire write_allow; wire read_allow; assign write_allow = WR_EN & ~ll_afifo_full; assign read_allow = RD_EN & ~ll_afifo_empty; //----------------------------------------------------------------------------- // Write Pointer Generation //----------------------------------------------------------------------------- always @(posedge WR_CLK or posedge WR_RST) begin if (WR_RST) wr_pntr_ll_afifo <= 0; else if (write_allow) wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1; end //----------------------------------------------------------------------------- // Read Pointer Generation //----------------------------------------------------------------------------- always @(posedge RD_CLK or posedge RD_RST) begin if (RD_RST) rd_pntr_ll_afifo_q <= 0; else rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo; end assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q; //----------------------------------------------------------------------------- // Fill the Memory //----------------------------------------------------------------------------- always @(posedge WR_CLK) begin if (write_allow) memory[wr_pntr_ll_afifo] <= #`TCQ DIN; end //----------------------------------------------------------------------------- // Generate DOUT //----------------------------------------------------------------------------- always @(posedge RD_CLK) begin DOUT <= #`TCQ memory[rd_pntr_ll_afifo]; end //----------------------------------------------------------------------------- // Generate EMPTY //----------------------------------------------------------------------------- always @(posedge RD_CLK or posedge RD_RST) begin if (RD_RST) ll_afifo_empty <= 1'b1; else ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1)))); end //----------------------------------------------------------------------------- // Generate FULL //----------------------------------------------------------------------------- always @(posedge WR_CLK or posedge WR_RST) begin if (WR_RST) ll_afifo_full <= 1'b1; else ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2)))); end always @* begin FULL <= ll_afifo_full; EMPTY <= ll_afifo_empty; end endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo /******************************************************************************* * Declaration of top-level module ******************************************************************************/ module fifo_generator_v13_1_3_bhv_ver_ss /************************************************************************** * Declare user parameters and their defaults *************************************************************************/ #( parameter C_FAMILY = "virtex7", parameter C_DATA_COUNT_WIDTH = 2, parameter C_DIN_WIDTH = 8, parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_FULL_FLAGS_RST_VAL = 1, parameter C_HAS_ALMOST_EMPTY = 0, parameter C_HAS_ALMOST_FULL = 0, parameter C_HAS_DATA_COUNT = 0, parameter C_HAS_OVERFLOW = 0, parameter C_HAS_RD_DATA_COUNT = 0, parameter C_HAS_RST = 0, parameter C_HAS_SRST = 0, parameter C_HAS_UNDERFLOW = 0, parameter C_HAS_VALID = 0, parameter C_HAS_WR_ACK = 0, parameter C_HAS_WR_DATA_COUNT = 0, parameter C_IMPLEMENTATION_TYPE = 0, parameter C_MEMORY_TYPE = 1, parameter C_OVERFLOW_LOW = 0, parameter C_PRELOAD_LATENCY = 1, parameter C_PRELOAD_REGS = 0, parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, parameter C_PROG_EMPTY_TYPE = 0, parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, parameter C_PROG_FULL_TYPE = 0, parameter C_RD_DATA_COUNT_WIDTH = 2, parameter C_RD_DEPTH = 256, parameter C_RD_PNTR_WIDTH = 8, parameter C_UNDERFLOW_LOW = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_USE_FWFT_DATA_COUNT = 0, parameter C_VALID_LOW = 0, parameter C_WR_ACK_LOW = 0, parameter C_WR_DATA_COUNT_WIDTH = 2, parameter C_WR_DEPTH = 256, parameter C_WR_PNTR_WIDTH = 8, parameter C_USE_ECC = 0, parameter C_ENABLE_RST_SYNC = 1, parameter C_ERROR_INJECTION_TYPE = 0, parameter C_FIFO_TYPE = 0 ) /************************************************************************** * Declare Input and Output Ports *************************************************************************/ ( //Inputs input SAFETY_CKT_WR_RST, input CLK, input [C_DIN_WIDTH-1:0] DIN, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, input RD_EN, input RD_EN_USER, input USER_EMPTY_FB, input RST, input RST_FULL_GEN, input RST_FULL_FF, input SRST, input WR_EN, input INJECTDBITERR, input INJECTSBITERR, input WR_RST_BUSY, input RD_RST_BUSY, //Outputs output ALMOST_EMPTY, output ALMOST_FULL, output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0, output [C_DOUT_WIDTH-1:0] DOUT, output EMPTY, output reg EMPTY_FB = 1'b1, output FULL, output OVERFLOW, output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, output PROG_EMPTY, output PROG_FULL, output VALID, output UNDERFLOW, output WR_ACK, output SBITERR, output DBITERR ); reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss; wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss; reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; /*************************************************************************** * Parameters used as constants **************************************************************************/ localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0; localparam C_DEPTH_RATIO_WR = (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; localparam C_DEPTH_RATIO_RD = (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC // -----------------|------------------|-----------------|--------------- // 1 | 8 | C_RD_PNTR_WIDTH | 2 // 1 | 4 | C_RD_PNTR_WIDTH | 2 // 1 | 2 | C_RD_PNTR_WIDTH | 2 // 1 | 1 | C_WR_PNTR_WIDTH | 2 // 2 | 1 | C_WR_PNTR_WIDTH | 4 // 4 | 1 | C_WR_PNTR_WIDTH | 8 // 8 | 1 | C_WR_PNTR_WIDTH | 16 localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR); localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); //localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR); localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; localparam [31:0] log2_reads_per_write = log2_val(reads_per_write); localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; localparam [31:0] log2_writes_per_read = log2_val(writes_per_read); //When RST is present, set FULL reset value to '1'. //If core has no RST, make sure FULL powers-on as '0'. //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. // Therefore, during SRST, all the FULL flags reset to 0. localparam C_HAS_FAST_FIFO = 0; localparam C_FIFO_WR_DEPTH = C_WR_DEPTH; localparam C_FIFO_RD_DEPTH = C_RD_DEPTH; // Local parameters used to determine whether to inject ECC error or not localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0; localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH; localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1; localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; /************************************************************************** * FIFO Contents Tracking and Data Count Calculations *************************************************************************/ // Memory which will be used to simulate a FIFO reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; reg [1:0] ecc_err[C_WR_DEPTH-1:0]; /************************************************************************** * Internal Registers and wires *************************************************************************/ //Temporary signals used for calculating the model's outputs. These //are only used in the assign statements immediately following wire, //parameter, and function declarations. wire underflow_i; wire valid_i; wire valid_out; reg [31:0] num_wr_bits; reg [31:0] num_rd_bits; reg [31:0] next_num_wr_bits; reg [31:0] next_num_rd_bits; //The write pointer - tracks write operations // (Works opposite to core: wr_ptr is a DOWN counter) reg [31:0] wr_ptr; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; reg wr_rst_d1 =0; //The read pointer - tracks read operations // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) reg [31:0] rd_ptr; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; wire ram_rd_en; wire empty_int; wire almost_empty_int; wire ram_wr_en; wire full_int; wire almost_full_int; reg ram_rd_en_reg = 1'b0; reg ram_rd_en_d1 = 1'b0; reg fab_rd_en_d1 = 1'b0; wire srst_rrst_busy; //Ideal FIFO signals. These are the raw output of the behavioral model, //which behaves like an ideal FIFO. reg [1:0] err_type = 0; reg [1:0] err_type_d1 = 0; reg [1:0] err_type_both = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0; wire [C_DOUT_WIDTH-1:0] ideal_dout_out; wire fwft_enabled; reg ideal_wr_ack = 0; reg ideal_valid = 0; reg ideal_overflow = C_OVERFLOW_LOW; reg ideal_underflow = C_UNDERFLOW_LOW; reg full_i = C_FULL_FLAGS_RST_VAL; reg full_i_temp = 0; reg empty_i = 1; reg almost_full_i = 0; reg almost_empty_i = 1; reg prog_full_i = 0; reg prog_empty_i = 1; reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0; reg write_allow_q = 0; reg read_allow_q = 0; reg valid_d1 = 0; reg valid_both = 0; reg valid_d2 = 0; wire rst_i; wire srst_i; //user specified value for reseting the size of the fifo reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; reg [31:0] wr_ptr_rdclk; reg [31:0] wr_ptr_rdclk_next; reg [31:0] rd_ptr_wrclk; reg [31:0] rd_ptr_wrclk_next; /**************************************************************************** * Function Declarations ***************************************************************************/ /**************************************************************************** * hexstr_conv * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) ***************************************************************************/ function [C_DOUT_WIDTH-1:0] hexstr_conv; input [(C_DOUT_WIDTH*8)-1:0] def_data; integer index,i,j; reg [3:0] bin; begin index = 0; hexstr_conv = 'b0; for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin case (def_data[7:0]) 8'b00000000 : begin bin = 4'b0000; i = -1; end 8'b00110000 : bin = 4'b0000; 8'b00110001 : bin = 4'b0001; 8'b00110010 : bin = 4'b0010; 8'b00110011 : bin = 4'b0011; 8'b00110100 : bin = 4'b0100; 8'b00110101 : bin = 4'b0101; 8'b00110110 : bin = 4'b0110; 8'b00110111 : bin = 4'b0111; 8'b00111000 : bin = 4'b1000; 8'b00111001 : bin = 4'b1001; 8'b01000001 : bin = 4'b1010; 8'b01000010 : bin = 4'b1011; 8'b01000011 : bin = 4'b1100; 8'b01000100 : bin = 4'b1101; 8'b01000101 : bin = 4'b1110; 8'b01000110 : bin = 4'b1111; 8'b01100001 : bin = 4'b1010; 8'b01100010 : bin = 4'b1011; 8'b01100011 : bin = 4'b1100; 8'b01100100 : bin = 4'b1101; 8'b01100101 : bin = 4'b1110; 8'b01100110 : bin = 4'b1111; default : begin bin = 4'bx; end endcase for( j=0; j<4; j=j+1) begin if ((index*4)+j < C_DOUT_WIDTH) begin hexstr_conv[(index*4)+j] = bin[j]; end end index = index + 1; def_data = def_data >> 8; end end endfunction /************************************************************************** * log2_val * Returns the 'log2' value for the input value for the supported ratios ***************************************************************************/ function [31:0] log2_val; input [31:0] binary_val; begin if (binary_val == 8) begin log2_val = 3; end else if (binary_val == 4) begin log2_val = 2; end else begin log2_val = 1; end end endfunction reg ideal_prog_full = 0; reg ideal_prog_empty = 1; reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; //Assorted reg values for delayed versions of signals //reg valid_d1 = 0; //user specified value for reseting the size of the fifo //reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; //temporary registers for WR_RESPONSE_LATENCY feature integer tmp_wr_listsize; integer tmp_rd_listsize; //Signal for registered version of prog full and empty //Threshold values for Programmable Flags integer prog_empty_actual_thresh_assert; integer prog_empty_actual_thresh_negate; integer prog_full_actual_thresh_assert; integer prog_full_actual_thresh_negate; /************************************************************************** * write_fifo * This task writes a word to the FIFO memory and updates the * write pointer. * FIFO size is relative to write domain. ***************************************************************************/ task write_fifo; begin memory[wr_ptr] <= DIN; wr_pntr <= #`TCQ wr_pntr + 1; // Store the type of error injection (double/single) on write case (C_ERROR_INJECTION_TYPE) 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; default: ecc_err[wr_ptr] <= 0; endcase // (Works opposite to core: wr_ptr is a DOWN counter) if (wr_ptr == 0) begin wr_ptr <= C_WR_DEPTH - 1; end else begin wr_ptr <= wr_ptr - 1; end end endtask // write_fifo /************************************************************************** * read_fifo * This task reads a word from the FIFO memory and updates the read * pointer. It's output is the ideal_dout bus. * FIFO size is relative to write domain. ***************************************************************************/ task read_fifo; integer i; reg [C_DOUT_WIDTH-1:0] tmp_dout; reg [C_DIN_WIDTH-1:0] memory_read; reg [31:0] tmp_rd_ptr; reg [31:0] rd_ptr_high; reg [31:0] rd_ptr_low; reg [1:0] tmp_ecc_err; begin rd_pntr <= #`TCQ rd_pntr + 1; // output is wider than input if (reads_per_write == 0) begin tmp_dout = 0; tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); for (i = writes_per_read - 1; i >= 0; i = i - 1) begin tmp_dout = tmp_dout << C_DIN_WIDTH; tmp_dout = tmp_dout | memory[tmp_rd_ptr]; // (Works opposite to core: rd_ptr is a DOWN counter) if (tmp_rd_ptr == 0) begin tmp_rd_ptr = C_WR_DEPTH - 1; end else begin tmp_rd_ptr = tmp_rd_ptr - 1; end end // output is symmetric end else if (reads_per_write == 1) begin tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; // Retreive the error injection type. Based on the error injection type // corrupt the output data. tmp_ecc_err = ecc_err[rd_ptr]; if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error if (C_DOUT_WIDTH == 1) begin $display("FAILURE : Data width must be >= 2 for double bit error injection."); $finish; end else if (C_DOUT_WIDTH == 2) tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; else tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; end else begin tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; end err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; end else begin err_type <= 0; end // input is wider than output end else begin rd_ptr_high = rd_ptr >> log2_reads_per_write; rd_ptr_low = rd_ptr & (reads_per_write - 1); memory_read = memory[rd_ptr_high]; tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); end ideal_dout <= tmp_dout; // (Works opposite to core: rd_ptr is a DOWN counter) if (rd_ptr == 0) begin rd_ptr <= C_RD_DEPTH - 1; end else begin rd_ptr <= rd_ptr - 1; end end endtask /************************************************************************* * Initialize Signals for clean power-on simulation *************************************************************************/ initial begin num_wr_bits = 0; num_rd_bits = 0; next_num_wr_bits = 0; next_num_rd_bits = 0; rd_ptr = C_RD_DEPTH - 1; wr_ptr = C_WR_DEPTH - 1; wr_pntr = 0; rd_pntr = 0; rd_ptr_wrclk = rd_ptr; wr_ptr_rdclk = wr_ptr; dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); ideal_dout = dout_reset_val; err_type = 0; err_type_d1 = 0; err_type_both = 0; ideal_dout_d1 = dout_reset_val; ideal_dout_both = dout_reset_val; ideal_wr_ack = 1'b0; ideal_valid = 1'b0; valid_d1 = 1'b0; valid_both = 1'b0; ideal_overflow = C_OVERFLOW_LOW; ideal_underflow = C_UNDERFLOW_LOW; ideal_wr_count = 0; ideal_rd_count = 0; ideal_prog_full = 1'b0; ideal_prog_empty = 1'b1; end /************************************************************************* * Connect the module inputs and outputs to the internal signals of the * behavioral model. *************************************************************************/ //Inputs /* wire CLK; wire [C_DIN_WIDTH-1:0] DIN; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; wire RD_EN; wire RST; wire WR_EN; */ // Assign ALMOST_EPMTY generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae assign ALMOST_EMPTY = almost_empty_i; end else begin : gnae assign ALMOST_EMPTY = 0; end endgenerate // gae // Assign ALMOST_FULL generate if (C_HAS_ALMOST_FULL==1) begin : gaf assign ALMOST_FULL = almost_full_i; end else begin : gnaf assign ALMOST_FULL = 0; end endgenerate // gaf // Dout may change behavior based on latency localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? 1: 0; assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? 1: 0; assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? ideal_dout_d1: ideal_dout; assign DOUT = ideal_dout_out; // Assign SBITERR and DBITERR based on latency assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? err_type_d1[0]: err_type[0]; assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? err_type_d1[1]: err_type[1]; assign EMPTY = empty_i; assign FULL = full_i; //saftey_ckt with one register generate if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge CLK) begin rst_delayed_sft1 <= #`TCQ rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin ram_rd_en_d1 <= #`TCQ 1'b0; valid_d1 <= #`TCQ 1'b0; end else begin ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i)); valid_d1 <= #`TCQ valid_i; end end always@(posedge rst_delayed_sft2 or posedge CLK) begin if (rst_delayed_sft2 == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else if (srst_rrst_busy == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end end else if (ram_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout; err_type_d1[0] <= #`TCQ err_type[0]; err_type_d1[1] <= #`TCQ err_type[1]; end end end //if endgenerate //safety ckt with both registers generate if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge CLK) begin rst_delayed_sft1 <= #`TCQ rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin ram_rd_en_d1 <= #`TCQ 1'b0; valid_d1 <= #`TCQ 1'b0; end else begin ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i)); fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; valid_both <= #`TCQ valid_i; valid_d1 <= #`TCQ valid_both; end end always@(posedge rst_delayed_sft2 or posedge CLK) begin if (rst_delayed_sft2 == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else if (srst_rrst_busy == 1'b1) begin if (C_USE_DOUT_RST == 1'b1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin if (ram_rd_en_d1) begin ideal_dout_both <= #`TCQ ideal_dout; err_type_both[0] <= #`TCQ err_type[0]; err_type_both[1] <= #`TCQ err_type[1]; end if (fab_rd_en_d1) begin ideal_dout_d1 <= #`TCQ ideal_dout_both; err_type_d1[0] <= #`TCQ err_type_both[0]; err_type_d1[1] <= #`TCQ err_type_both[1]; end end end end //if endgenerate //Overflow may be active-low generate if (C_HAS_OVERFLOW==1) begin : gof assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; end else begin : gnof assign OVERFLOW = 0; end endgenerate // gof assign PROG_EMPTY = prog_empty_i; assign PROG_FULL = prog_full_i; //Valid may change behavior based on latency or active-low generate if (C_HAS_VALID==1) begin : gvalid assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid; assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ? valid_d1 : valid_i; assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; end else begin : gnvalid assign VALID = 0; end endgenerate // gvalid //Trim data count differently depending on set widths generate if (C_HAS_DATA_COUNT == 1) begin : gdc always @* begin diff_count <= wr_pntr - rd_pntr; if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count; DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; end else begin DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; end end // end else begin : gndc // always @* DATA_COUNT <= 0; end endgenerate // gdc //Underflow may change behavior based on latency or active-low generate if (C_HAS_UNDERFLOW==1) begin : guf assign underflow_i = ideal_underflow; assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; end else begin : gnuf assign UNDERFLOW = 0; end endgenerate // guf //Write acknowledge may be active low generate if (C_HAS_WR_ACK==1) begin : gwr_ack assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; end else begin : gnwr_ack assign WR_ACK = 0; end endgenerate // gwr_ack /***************************************************************************** * Internal reset logic ****************************************************************************/ assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0; assign rst_i = C_HAS_RST ? RST : 0; assign srst_wrst_busy = srst_i; assign srst_rrst_busy = srst_i; /************************************************************************** * Assorted registers for delayed versions of signals **************************************************************************/ //Capture delayed version of valid generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20 always @(posedge CLK or posedge rst_i) begin if (rst_i == 1'b1) begin valid_d1 <= 1'b0; end else begin if (srst_rrst_busy) begin valid_d1 <= #`TCQ 1'b0; end else begin valid_d1 <= #`TCQ valid_i; end end end // always @ (posedge CLK or posedge rst_i) end endgenerate // blockVL20 generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin always @(posedge CLK or posedge rst_i) begin if (rst_i == 1'b1) begin valid_d1 <= 1'b0; valid_both <= 1'b0; end else begin if (srst_rrst_busy) begin valid_d1 <= #`TCQ 1'b0; valid_both <= #`TCQ 1'b0; end else begin valid_both <= #`TCQ valid_i; valid_d1 <= #`TCQ valid_both; end end end // always @ (posedge CLK or posedge rst_i) end endgenerate // blockVL20 // Determine which stage in FWFT registers are valid reg stage1_valid = 0; reg stage2_valid = 0; generate if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc always @ (posedge CLK or posedge rst_i) begin if (rst_i) begin stage1_valid <= #`TCQ 0; stage2_valid <= #`TCQ 0; end else begin if (!stage1_valid && !stage2_valid) begin if (!EMPTY) stage1_valid <= #`TCQ 1'b1; else stage1_valid <= #`TCQ 1'b0; end else if (stage1_valid && !stage2_valid) begin if (EMPTY) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end end else if (!stage1_valid && stage2_valid) begin if (EMPTY && RD_EN) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b0; end else if (!EMPTY && RD_EN) begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b0; end else if (!EMPTY && !RD_EN) begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end end else if (stage1_valid && stage2_valid) begin if (EMPTY && RD_EN) begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b1; end else begin stage1_valid <= #`TCQ 1'b1; stage2_valid <= #`TCQ 1'b1; end end else begin stage1_valid <= #`TCQ 1'b0; stage2_valid <= #`TCQ 1'b0; end end // rd_rst_i end // always end endgenerate //*************************************************************************** // Assign the read data count value only if it is selected, // otherwise output zeros. //*************************************************************************** generate if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; end endgenerate generate if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}}; end endgenerate //*************************************************************************** // Assign the write data count value only if it is selected, // otherwise output zeros //*************************************************************************** generate if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ; end endgenerate generate if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}}; end endgenerate //reg ram_rd_en_d1 = 1'b0; //Capture delayed version of dout generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin always @(posedge CLK or posedge rst_i) begin if (rst_i == 1'b1) begin // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end // DRAM and SRAM reset asynchronously if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end ram_rd_en_d1 <= #`TCQ 1'b0; if (C_USE_DOUT_RST == 1) begin @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY; if (srst_rrst_busy) begin ram_rd_en_d1 <= #`TCQ 1'b0; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end if (C_USE_DOUT_RST == 1) begin // @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin if (ram_rd_en_d1 ) begin ideal_dout_d1 <= #`TCQ ideal_dout; err_type_d1 <= #`TCQ err_type; end end end end // always end endgenerate //no safety ckt with both registers generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin always @(posedge CLK or posedge rst_i) begin if (rst_i == 1'b1) begin ram_rd_en_d1 <= #`TCQ 1'b0; fab_rd_en_d1 <= #`TCQ 1'b0; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end // DRAM and SRAM reset asynchronously if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end if (C_USE_DOUT_RST == 1) begin @(posedge CLK) ideal_dout_d1 <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end end else begin if (srst_rrst_busy) begin ram_rd_en_d1 <= #`TCQ 1'b0; fab_rd_en_d1 <= #`TCQ 1'b0; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end if (C_USE_DOUT_RST == 1) begin ideal_dout_d1 <= #`TCQ dout_reset_val; end end else begin ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY; fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1); if (ram_rd_en_d1 ) begin ideal_dout_both <= #`TCQ ideal_dout; err_type_both <= #`TCQ err_type; end if (fab_rd_en_d1 ) begin ideal_dout_d1 <= #`TCQ ideal_dout_both; err_type_d1 <= #`TCQ err_type_both; end end end end // always end endgenerate /************************************************************************** * Overflow and Underflow Flag calculation * (handled separately because they don't support rst) **************************************************************************/ generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw always @(posedge CLK) begin ideal_overflow <= #`TCQ WR_EN & full_i; end end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw always @(posedge CLK) begin //ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i); ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i); end end endgenerate // blockOF20 generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw always @(posedge CLK) begin ideal_underflow <= #`TCQ empty_i & RD_EN; end end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw always @(posedge CLK) begin //ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN; ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN; end end endgenerate // blockUF20 /************************** * Read Data Count *************************/ reg [31:0] num_read_words_dc; reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; always @(num_rd_bits) begin if (C_USE_FWFT_DATA_COUNT) begin //If using extra logic for FWFT Data Counts, // then scale FIFO contents to read domain, // and add two read words for FWFT stages //This value is only a temporary value and not used in the code. num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); //Trim the read words for use with RD_DATA_COUNT num_read_words_sized_i = num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; end else begin //If not using extra logic for FWFT Data Counts, // then scale FIFO contents to read domain. //This value is only a temporary value and not used in the code. num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; //Trim the read words for use with RD_DATA_COUNT num_read_words_sized_i = num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; end //if (C_USE_FWFT_DATA_COUNT) end //always /************************** * Write Data Count *************************/ reg [31:0] num_write_words_dc; reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; always @(num_wr_bits) begin if (C_USE_FWFT_DATA_COUNT) begin //Calculate the Data Count value for the number of write words, // when using First-Word Fall-Through with extra logic for Data // Counts. This takes into consideration the number of words that // are expected to be stored in the FWFT register stages (it always // assumes they are filled). //This value is scaled to the Write Domain. //The expression (((A-1)/B))+1 divides A/B, but takes the // ceiling of the result. //When num_wr_bits==0, set the result manually to prevent // division errors. //EXTRA_WORDS_DC is the number of words added to write_words // due to FWFT. //This value is only a temporary value and not used in the code. num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; //Trim the write words for use with WR_DATA_COUNT num_write_words_sized_i = num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; end else begin //Calculate the Data Count value for the number of write words, when NOT // using First-Word Fall-Through with extra logic for Data Counts. This // calculates only the number of words in the internal FIFO. //The expression (((A-1)/B))+1 divides A/B, but takes the // ceiling of the result. //This value is scaled to the Write Domain. //When num_wr_bits==0, set the result manually to prevent // division errors. //This value is only a temporary value and not used in the code. num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; //Trim the read words for use with RD_DATA_COUNT num_write_words_sized_i = num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; end //if (C_USE_FWFT_DATA_COUNT) end //always /************************************************************************* * Write and Read Logic ************************************************************************/ wire write_allow; wire read_allow; wire read_allow_dc; wire write_only; wire read_only; //wire write_only_q; reg write_only_q; //wire read_only_q; reg read_only_q; reg full_reg; reg rst_full_ff_reg1; reg rst_full_ff_reg2; wire ram_full_comb; wire carry; assign write_allow = WR_EN & ~full_i; assign read_allow = RD_EN & ~empty_i; assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB; //assign write_only = write_allow & ~read_allow; //assign write_only_q = write_allow_q; //assign read_only = read_allow & ~write_allow; //assign read_only_q = read_allow_q ; wire [C_WR_PNTR_WIDTH-1:0] diff_pntr; wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe; reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0; reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0; reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0; wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ; wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym; reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0; reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0; wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max; wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max; assign diff_pntr_pe_max = DIFF_MAX_RD; assign diff_pntr_max = DIFF_MAX_WR; generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym assign write_only = write_allow & ~read_allow; assign read_only = read_allow & ~write_allow; end endgenerate generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow; assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])); end endgenerate generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow; end endgenerate //----------------------------------------------------------------------------- // Write and Read pointer generation //----------------------------------------------------------------------------- always @(posedge CLK or posedge rst_i) begin if (rst_i && C_EN_SAFETY_CKT == 0) begin wr_pntr <= 0; rd_pntr <= 0; end else begin if (srst_i) begin wr_pntr <= #`TCQ 0; rd_pntr <= #`TCQ 0; end else begin if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1; if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1; end end end generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout always @(posedge CLK) begin if (write_allow) begin if (ENABLE_ERR_INJECTION == 1) memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN}; else memory[wr_pntr] <= #`TCQ DIN; end end reg [C_DATA_WIDTH-1:0] dout_tmp_q; reg [C_DATA_WIDTH-1:0] dout_tmp = 0; reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0; always @(posedge CLK) begin dout_tmp_q <= #`TCQ ideal_dout; end always @* begin if (read_allow) ideal_dout <= memory[rd_pntr]; else ideal_dout <= dout_tmp_q; end end endgenerate // gll_dm_dout /************************************************************************** * Write Domain Logic **************************************************************************/ assign ram_rd_en = RD_EN & !EMPTY; //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; generate if (C_FIFO_TYPE != 2) begin : gnll_din always @(posedge CLK or posedge rst_i) begin : gen_fifo_w /****** Reset fifo (case 1)***************************************/ if (rst_i == 1'b1) begin num_wr_bits <= #`TCQ 0; next_num_wr_bits = #`TCQ 0; wr_ptr <= #`TCQ C_WR_DEPTH - 1; rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; ideal_wr_ack <= #`TCQ 0; ideal_wr_count <= #`TCQ 0; tmp_wr_listsize = #`TCQ 0; rd_ptr_wrclk_next <= #`TCQ 0; wr_pntr <= #`TCQ 0; wr_pntr_rd1 <= #`TCQ 0; end else begin //rst_i==0 if (srst_wrst_busy) begin num_wr_bits <= #`TCQ 0; next_num_wr_bits = #`TCQ 0; wr_ptr <= #`TCQ C_WR_DEPTH - 1; rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; ideal_wr_ack <= #`TCQ 0; ideal_wr_count <= #`TCQ 0; tmp_wr_listsize = #`TCQ 0; rd_ptr_wrclk_next <= #`TCQ 0; wr_pntr <= #`TCQ 0; wr_pntr_rd1 <= #`TCQ 0; end else begin//srst_i=0 wr_pntr_rd1 <= #`TCQ wr_pntr; //Determine the current number of words in the FIFO tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : num_wr_bits/C_DIN_WIDTH; rd_ptr_wrclk_next = rd_ptr; if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin next_num_wr_bits = num_wr_bits - C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH - rd_ptr_wrclk_next); end else begin next_num_wr_bits = num_wr_bits - C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); end if (WR_EN == 1'b1) begin if (FULL == 1'b1) begin ideal_wr_ack <= #`TCQ 0; //Reminder that FIFO is still full ideal_wr_count <= #`TCQ num_write_words_sized_i; end else begin write_fifo; next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; //Write successful, so issue acknowledge // and no error ideal_wr_ack <= #`TCQ 1; //Not even close to full. ideal_wr_count <= num_write_words_sized_i; //end end end else begin //(WR_EN == 1'b1) //If user did not attempt a write, then do not // give ack or err ideal_wr_ack <= #`TCQ 0; ideal_wr_count <= #`TCQ num_write_words_sized_i; end num_wr_bits <= #`TCQ next_num_wr_bits; rd_ptr_wrclk <= #`TCQ rd_ptr; end //srst_i==0 end //wr_rst_i==0 end // gen_fifo_w end endgenerate generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout always @(posedge CLK) begin if (rst_i || srst_rrst_busy) begin if (C_USE_DOUT_RST == 1) begin ideal_dout <= #`TCQ dout_reset_val; ideal_dout_both <= #`TCQ dout_reset_val; end end end end endgenerate generate if (C_FIFO_TYPE != 2) begin : gnll_dout always @(posedge CLK or posedge rst_i) begin : gen_fifo_r /****** Reset fifo (case 1)***************************************/ if (rst_i) begin num_rd_bits <= #`TCQ 0; next_num_rd_bits = #`TCQ 0; rd_ptr <= #`TCQ C_RD_DEPTH -1; rd_pntr <= #`TCQ 0; //rd_pntr_wr1 <= #`TCQ 0; wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; // DRAM resets asynchronously if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1) ideal_dout <= #`TCQ dout_reset_val; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type <= #`TCQ 0; err_type_d1 <= 0; err_type_both <= 0; end ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ 0; end else begin //rd_rst_i==0 if (srst_rrst_busy) begin num_rd_bits <= #`TCQ 0; next_num_rd_bits = #`TCQ 0; rd_ptr <= #`TCQ C_RD_DEPTH -1; rd_pntr <= #`TCQ 0; //rd_pntr_wr1 <= #`TCQ 0; wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; // DRAM resets synchronously if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1) ideal_dout <= #`TCQ dout_reset_val; // Reset err_type only if ECC is not selected if (C_USE_ECC == 0) begin err_type <= #`TCQ 0; err_type_d1 <= #`TCQ 0; err_type_both <= #`TCQ 0; end ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ 0; end //srst_i else begin //rd_pntr_wr1 <= #`TCQ rd_pntr; //Determine the current number of words in the FIFO tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : num_rd_bits/C_DOUT_WIDTH; wr_ptr_rdclk_next = wr_ptr; if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin next_num_rd_bits = num_rd_bits + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH - wr_ptr_rdclk_next); end else begin next_num_rd_bits = num_rd_bits + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); end if (RD_EN == 1'b1) begin if (EMPTY == 1'b1) begin ideal_valid <= #`TCQ 1'b0; ideal_rd_count <= #`TCQ num_read_words_sized_i; end else begin read_fifo; next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; //Acknowledge the read from the FIFO, no error ideal_valid <= #`TCQ 1'b1; ideal_rd_count <= #`TCQ num_read_words_sized_i; end // if (tmp_rd_listsize == 2) end num_rd_bits <= #`TCQ next_num_rd_bits; wr_ptr_rdclk <= #`TCQ wr_ptr; end //s_rst_i==0 end //rd_rst_i==0 end //always end endgenerate //----------------------------------------------------------------------------- // Generate diff_pntr for PROG_FULL generation // Generate diff_pntr_pe for PROG_EMPTY generation //----------------------------------------------------------------------------- generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow always @(posedge CLK ) begin if (rst_i) begin write_only_q <= 1'b0; read_only_q <= 1'b0; diff_pntr_reg1 <= 0; diff_pntr_pe_reg1 <= 0; diff_pntr_reg2 <= 0; diff_pntr_pe_reg2 <= 0; end else begin if (srst_i || srst_wrst_busy || srst_rrst_busy) begin if (srst_rrst_busy) begin read_only_q <= #`TCQ 1'b0; diff_pntr_pe_reg1 <= #`TCQ 0; diff_pntr_pe_reg2 <= #`TCQ 0; end if (srst_wrst_busy) begin write_only_q <= #`TCQ 1'b0; diff_pntr_reg1 <= #`TCQ 0; diff_pntr_reg2 <= #`TCQ 0; end end else begin write_only_q <= #`TCQ write_only; read_only_q <= #`TCQ read_only; diff_pntr_reg2 <= #`TCQ diff_pntr_reg1; diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1; // Add 1 to the difference pointer value when only write happens. if (write_only) diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1; else diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr; // Add 1 to the difference pointer value when write or both write & read or no write & read happen. if (read_only) diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1; else diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr; end end end assign diff_pntr_pe = diff_pntr_pe_reg1; assign diff_pntr = diff_pntr_reg1; end endgenerate // reg_write_allow generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1}; assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1}; always @(posedge CLK ) begin if (rst_i) begin diff_pntr_pe_asym <= 0; diff_pntr_reg1 <= 0; full_reg <= 0; rst_full_ff_reg1 <= 1; rst_full_ff_reg2 <= 1; diff_pntr_pe_reg1 <= 0; end else begin if (srst_i || srst_wrst_busy || srst_rrst_busy) begin if (srst_wrst_busy) diff_pntr_reg1 <= #`TCQ 0; if (srst_rrst_busy) full_reg <= #`TCQ 0; rst_full_ff_reg1 <= #`TCQ 1; rst_full_ff_reg2 <= #`TCQ 1; diff_pntr_pe_asym <= #`TCQ 0; diff_pntr_pe_reg1 <= #`TCQ 0; end else begin diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym; full_reg <= #`TCQ full_i; rst_full_ff_reg1 <= #`TCQ RST_FULL_FF; rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1; if (~full_i) begin diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr; end end end end assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1]))); assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1]; assign diff_pntr = diff_pntr_reg1; end endgenerate // reg_write_allow_asym //----------------------------------------------------------------------------- // Generate FULL flag //----------------------------------------------------------------------------- wire comp0; wire comp1; wire going_full; wire leaving_full; generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr; assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0; end endgenerate generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; end endgenerate assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1)); assign comp0 = (adj_rd_pntr_wr == wr_pntr); generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp assign going_full = (comp1 & write_allow & ~read_allow); assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN; end endgenerate // Write data width is bigger than read data width // Write depth is smaller than read depth // One write could be equal to 2 or 4 or 8 reads generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])))); assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN; end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp assign going_full = (comp1 & write_allow & ~read_allow); assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN; end endgenerate assign ram_full_comb = going_full | (~leaving_full & full_i); always @(posedge CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF) full_i <= C_FULL_FLAGS_RST_VAL; else if (srst_wrst_busy) full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else full_i <= #`TCQ ram_full_comb; end //----------------------------------------------------------------------------- // Generate EMPTY flag //----------------------------------------------------------------------------- wire ecomp0; wire ecomp1; wire going_empty; wire leaving_empty; wire ram_empty_comb; generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0; end endgenerate generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end endgenerate assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1)); assign ecomp0 = (adj_wr_pntr_rd == rd_pntr); generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp assign going_empty = (ecomp1 & ~write_allow & read_allow); assign leaving_empty = (ecomp0 & write_allow); end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])))); assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); end endgenerate generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp assign going_empty = (ecomp1 & ~write_allow & read_allow); assign leaving_empty =(ecomp0 & write_allow); end endgenerate assign ram_empty_comb = going_empty | (~leaving_empty & empty_i); always @(posedge CLK or posedge rst_i) begin if (rst_i) empty_i <= 1'b1; else if (srst_rrst_busy) empty_i <= #`TCQ 1'b1; else empty_i <= #`TCQ ram_empty_comb; end always @(posedge CLK or posedge rst_i) begin if (rst_i && C_EN_SAFETY_CKT == 0) begin EMPTY_FB <= 1'b1; end else begin if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT)) EMPTY_FB <= #`TCQ 1'b1; else EMPTY_FB <= #`TCQ ram_empty_comb; end end // always //----------------------------------------------------------------------------- // Generate Read and write data counts for asymmetic common clock //----------------------------------------------------------------------------- reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; wire [C_GRTR_PNTR_WIDTH :0] ratio; wire decr_by_one; wire incr_by_ratio; wire incr_by_one; wire decr_by_ratio; localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0; generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr assign ratio = C_DEPTH_RATIO_RD; assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow; assign incr_by_ratio = write_allow; always @(posedge CLK or posedge rst_i) begin if (rst_i) count_dc <= #`TCQ 0; else if (srst_wrst_busy) count_dc <= #`TCQ 0; else begin if (decr_by_one) begin if (!incr_by_ratio) count_dc <= #`TCQ count_dc - 1; else count_dc <= #`TCQ count_dc - 1 + ratio ; end else begin if (!incr_by_ratio) count_dc <= #`TCQ count_dc ; else count_dc <= #`TCQ count_dc + ratio ; end end end assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc; assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd assign ratio = C_DEPTH_RATIO_WR; assign incr_by_one = write_allow; assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow; always @(posedge CLK or posedge rst_i) begin if (rst_i) count_dc <= #`TCQ 0; else if (srst_wrst_busy) count_dc <= #`TCQ 0; else begin if (incr_by_one) begin if (!decr_by_ratio) count_dc <= #`TCQ count_dc + 1; else count_dc <= #`TCQ count_dc + 1 - ratio ; end else begin if (!decr_by_ratio) count_dc <= #`TCQ count_dc ; else count_dc <= #`TCQ count_dc - ratio ; end end end assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc; assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; end endgenerate //----------------------------------------------------------------------------- // Generate WR_ACK flag //----------------------------------------------------------------------------- always @(posedge CLK or posedge rst_i) begin if (rst_i) ideal_wr_ack <= 1'b0; else if (srst_wrst_busy) ideal_wr_ack <= #`TCQ 1'b0; else if (WR_EN & ~full_i) ideal_wr_ack <= #`TCQ 1'b1; else ideal_wr_ack <= #`TCQ 1'b0; end //----------------------------------------------------------------------------- // Generate VALID flag //----------------------------------------------------------------------------- always @(posedge CLK or posedge rst_i) begin if (rst_i) ideal_valid <= 1'b0; else if (srst_rrst_busy) ideal_valid <= #`TCQ 1'b0; else if (RD_EN & ~empty_i) ideal_valid <= #`TCQ 1'b1; else ideal_valid <= #`TCQ 1'b0; end //----------------------------------------------------------------------------- // Generate ALMOST_FULL flag //----------------------------------------------------------------------------- //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss wire fcomp2; wire going_afull; wire leaving_afull; wire ram_afull_comb; assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2)); generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp assign going_afull = (fcomp2 & write_allow & ~read_allow); assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN; end endgenerate // Write data width is bigger than read data width // Write depth is smaller than read depth // One write could be equal to 2 or 4 or 8 reads generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])))); assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN; end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp assign going_afull = (fcomp2 & write_allow & ~read_allow); assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN; end endgenerate assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i); always @(posedge CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF) almost_full_i <= C_FULL_FLAGS_RST_VAL; else if (srst_wrst_busy) almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else almost_full_i <= #`TCQ ram_afull_comb; end // end endgenerate // gaf_ss //----------------------------------------------------------------------------- // Generate ALMOST_EMPTY flag //----------------------------------------------------------------------------- //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss wire ecomp2; wire going_aempty; wire leaving_aempty; wire ram_aempty_comb; assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2)); generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp assign going_aempty = (ecomp2 & ~write_allow & read_allow); assign leaving_aempty = (ecomp1 & write_allow & ~read_allow); end endgenerate generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])))); assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); end endgenerate generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp assign going_aempty = (ecomp2 & ~write_allow & read_allow); assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow); end endgenerate assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i); always @(posedge CLK or posedge rst_i) begin if (rst_i) almost_empty_i <= 1'b1; else if (srst_rrst_busy) almost_empty_i <= #`TCQ 1'b1; else almost_empty_i <= #`TCQ ram_aempty_comb; end // end endgenerate // gae_ss //----------------------------------------------------------------------------- // Generate PROG_FULL //----------------------------------------------------------------------------- localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT C_PROG_FULL_THRESH_ASSERT_VAL; // STD localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT C_PROG_FULL_THRESH_NEGATE_VAL; // STD //----------------------------------------------------------------------------- // Generate PROG_FULL for single programmable threshold constant //----------------------------------------------------------------------------- wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL; generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const always @(posedge CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF && C_HAS_RST) prog_full_i <= C_FULL_FLAGS_RST_VAL; else begin if (srst_wrst_busy) prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else if (IS_ASYMMETRY == 0) begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~RST_FULL_GEN ) begin if (diff_pntr>= C_PF_ASSERT_VAL ) prog_full_i <= #`TCQ 1'b1; else if ((diff_pntr) < C_PF_ASSERT_VAL ) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ 1'b0; end else prog_full_i <= #`TCQ prog_full_i; end end end end endgenerate // single_pf_const //----------------------------------------------------------------------------- // Generate PROG_FULL for multiple programmable threshold constants //----------------------------------------------------------------------------- generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const always @(posedge CLK or posedge RST_FULL_FF) begin //if (RST_FULL_FF) if (RST_FULL_FF && C_HAS_RST) prog_full_i <= C_FULL_FLAGS_RST_VAL; else begin if (srst_wrst_busy) prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else if (IS_ASYMMETRY == 0) begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~RST_FULL_GEN ) begin if (diff_pntr >= C_PF_ASSERT_VAL ) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr < C_PF_NEGATE_VAL) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else prog_full_i <= #`TCQ prog_full_i; end end end end endgenerate //multiple_pf_const //----------------------------------------------------------------------------- // Generate PROG_FULL for single programmable threshold input port //----------------------------------------------------------------------------- wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT PROG_FULL_THRESH; // STD generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input always @(posedge CLK or posedge RST_FULL_FF) begin//0 //if (RST_FULL_FF) if (RST_FULL_FF && C_HAS_RST) prog_full_i <= C_FULL_FLAGS_RST_VAL; else begin //1 if (srst_wrst_busy) prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else if (IS_ASYMMETRY == 0) begin//2 if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~almost_full_i) begin//3 if (diff_pntr > pf3_assert_val) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr == pf3_assert_val) begin//4 if (read_only_q) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ 1'b1; end else//4 prog_full_i <= #`TCQ 1'b0; end else//3 prog_full_i <= #`TCQ prog_full_i; end //2 else begin//5 if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~full_i ) begin//6 if (diff_pntr >= pf3_assert_val ) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr < pf3_assert_val) begin//7 prog_full_i <= #`TCQ 1'b0; end//7 end//6 else prog_full_i <= #`TCQ prog_full_i; end//5 end//1 end//0 end endgenerate //single_pf_input //----------------------------------------------------------------------------- // Generate PROG_FULL for multiple programmable threshold input ports //----------------------------------------------------------------------------- wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT PROG_FULL_THRESH_ASSERT; // STD wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT PROG_FULL_THRESH_NEGATE; // STD generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs always @(posedge CLK or posedge RST_FULL_FF) begin if (RST_FULL_FF && C_HAS_RST) prog_full_i <= C_FULL_FLAGS_RST_VAL; else begin if (srst_wrst_busy) prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; else if (IS_ASYMMETRY == 0) begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~almost_full_i) begin if (diff_pntr >= pf_assert_val) prog_full_i <= #`TCQ 1'b1; else if ((diff_pntr == pf_negate_val && read_only_q) || diff_pntr < pf_negate_val) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else prog_full_i <= #`TCQ prog_full_i; end else begin if (RST_FULL_GEN) prog_full_i <= #`TCQ 1'b0; else if (~full_i ) begin if (diff_pntr >= pf_assert_val ) prog_full_i <= #`TCQ 1'b1; else if (diff_pntr < pf_negate_val) prog_full_i <= #`TCQ 1'b0; else prog_full_i <= #`TCQ prog_full_i; end else prog_full_i <= #`TCQ prog_full_i; end end end end endgenerate //multiple_pf_inputs //----------------------------------------------------------------------------- // Generate PROG_EMPTY //----------------------------------------------------------------------------- localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD //----------------------------------------------------------------------------- // Generate PROG_EMPTY for single programmable threshold constant //----------------------------------------------------------------------------- generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const always @(posedge CLK or posedge rst_i) begin //if (rst_i) if (rst_i && C_HAS_RST) prog_empty_i <= 1'b1; else begin if (srst_rrst_busy) prog_empty_i <= #`TCQ 1'b1; else if (IS_ASYMMETRY == 0) begin if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end else begin if (~rst_i ) begin if (diff_pntr_pe <= C_PE_ASSERT_VAL) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe > C_PE_ASSERT_VAL) prog_empty_i <= #`TCQ 1'b0; end else prog_empty_i <= #`TCQ prog_empty_i; end end end end endgenerate // single_pe_const //----------------------------------------------------------------------------- // Generate PROG_EMPTY for multiple programmable threshold constants //----------------------------------------------------------------------------- generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const always @(posedge CLK or posedge rst_i) begin //if (rst_i) if (rst_i && C_HAS_RST) prog_empty_i <= 1'b1; else begin if (srst_rrst_busy) prog_empty_i <= #`TCQ 1'b1; else if (IS_ASYMMETRY == 0) begin if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end else begin if (~rst_i ) begin if (diff_pntr_pe <= C_PE_ASSERT_VAL ) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe > C_PE_NEGATE_VAL) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end else prog_empty_i <= #`TCQ prog_empty_i; end end end end endgenerate //multiple_pe_const //----------------------------------------------------------------------------- // Generate PROG_EMPTY for single programmable threshold input port //----------------------------------------------------------------------------- wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ? (PROG_EMPTY_THRESH -2) : // FWFT PROG_EMPTY_THRESH; // STD generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input always @(posedge CLK or posedge rst_i) begin //if (rst_i) if (rst_i && C_HAS_RST) prog_empty_i <= 1'b1; else begin if (srst_rrst_busy) prog_empty_i <= #`TCQ 1'b1; else if (IS_ASYMMETRY == 0) begin if (~almost_full_i) begin if (diff_pntr_pe < pe3_assert_val) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe == pe3_assert_val) begin if (write_only_q) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ 1'b1; end else prog_empty_i <= #`TCQ 1'b0; end else prog_empty_i <= #`TCQ prog_empty_i; end else begin if (diff_pntr_pe <= pe3_assert_val ) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe > pe3_assert_val) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end end end end endgenerate // single_pe_input //----------------------------------------------------------------------------- // Generate PROG_EMPTY for multiple programmable threshold input ports //----------------------------------------------------------------------------- wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ? (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT PROG_EMPTY_THRESH_ASSERT; // STD wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ? (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT PROG_EMPTY_THRESH_NEGATE; // STD generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs always @(posedge CLK or posedge rst_i) begin //if (rst_i) if (rst_i && C_HAS_RST) prog_empty_i <= 1'b1; else begin if (srst_rrst_busy) prog_empty_i <= #`TCQ 1'b1; else if (IS_ASYMMETRY == 0) begin if (~almost_full_i) begin if (diff_pntr_pe <= pe4_assert_val) prog_empty_i <= #`TCQ 1'b1; else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || (diff_pntr_pe > pe4_negate_val)) begin prog_empty_i <= #`TCQ 1'b0; end else prog_empty_i <= #`TCQ prog_empty_i; end else prog_empty_i <= #`TCQ prog_empty_i; end else begin if (diff_pntr_pe <= pe4_assert_val ) prog_empty_i <= #`TCQ 1'b1; else if (diff_pntr_pe > pe4_negate_val) prog_empty_i <= #`TCQ 1'b0; else prog_empty_i <= #`TCQ prog_empty_i; end end end end endgenerate // multiple_pe_inputs endmodule // fifo_generator_v13_1_3_bhv_ver_ss /************************************************************************** * First-Word Fall-Through module (preload 0) **************************************************************************/ module fifo_generator_v13_1_3_bhv_ver_preload0 #( parameter C_DOUT_RST_VAL = "", parameter C_DOUT_WIDTH = 8, parameter C_HAS_RST = 0, parameter C_ENABLE_RST_SYNC = 0, parameter C_HAS_SRST = 0, parameter C_USE_EMBEDDED_REG = 0, parameter C_EN_SAFETY_CKT = 0, parameter C_USE_DOUT_RST = 0, parameter C_USE_ECC = 0, parameter C_USERVALID_LOW = 0, parameter C_USERUNDERFLOW_LOW = 0, parameter C_MEMORY_TYPE = 0, parameter C_FIFO_TYPE = 0 ) ( //Inputs input SAFETY_CKT_RD_RST, input RD_CLK, input RD_RST, input SRST, input WR_RST_BUSY, input RD_RST_BUSY, input RD_EN, input FIFOEMPTY, input [C_DOUT_WIDTH-1:0] FIFODATA, input FIFOSBITERR, input FIFODBITERR, //Outputs output reg [C_DOUT_WIDTH-1:0] USERDATA, output USERVALID, output USERUNDERFLOW, output USEREMPTY, output USERALMOSTEMPTY, output RAMVALID, output FIFORDEN, output reg USERSBITERR, output reg USERDBITERR, output reg STAGE2_REG_EN, output fab_read_data_valid_i_o, output read_data_valid_i_o, output ram_valid_i_o, output [1:0] VALID_STAGES ); //Internal signals wire preloadstage1; wire preloadstage2; reg ram_valid_i; reg fab_valid; reg read_data_valid_i; reg fab_read_data_valid_i; reg fab_read_data_valid_i_1; reg ram_valid_i_d; reg read_data_valid_i_d; reg fab_read_data_valid_i_d; wire ram_regout_en; reg ram_regout_en_d1; reg ram_regout_en_d2; wire fab_regout_en; wire ram_rd_en; reg empty_i = 1'b1; reg empty_sckt = 1'b1; reg sckt_rrst_q = 1'b0; reg sckt_rrst_done = 1'b0; reg empty_q = 1'b1; reg rd_en_q = 1'b0; reg almost_empty_i = 1'b1; reg almost_empty_q = 1'b1; wire rd_rst_i; wire srst_i; reg [C_DOUT_WIDTH-1:0] userdata_both; wire uservalid_both; wire uservalid_one; reg user_sbiterr_both = 1'b0; reg user_dbiterr_both = 1'b0; assign ram_valid_i_o = ram_valid_i; assign read_data_valid_i_o = read_data_valid_i; assign fab_read_data_valid_i_o = fab_read_data_valid_i; /************************************************************************* * FUNCTIONS *************************************************************************/ /************************************************************************* * hexstr_conv * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) ***********************************************************************/ function [C_DOUT_WIDTH-1:0] hexstr_conv; input [(C_DOUT_WIDTH*8)-1:0] def_data; integer index,i,j; reg [3:0] bin; begin index = 0; hexstr_conv = 'b0; for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin case (def_data[7:0]) 8'b00000000 : begin bin = 4'b0000; i = -1; end 8'b00110000 : bin = 4'b0000; 8'b00110001 : bin = 4'b0001; 8'b00110010 : bin = 4'b0010; 8'b00110011 : bin = 4'b0011; 8'b00110100 : bin = 4'b0100; 8'b00110101 : bin = 4'b0101; 8'b00110110 : bin = 4'b0110; 8'b00110111 : bin = 4'b0111; 8'b00111000 : bin = 4'b1000; 8'b00111001 : bin = 4'b1001; 8'b01000001 : bin = 4'b1010; 8'b01000010 : bin = 4'b1011; 8'b01000011 : bin = 4'b1100; 8'b01000100 : bin = 4'b1101; 8'b01000101 : bin = 4'b1110; 8'b01000110 : bin = 4'b1111; 8'b01100001 : bin = 4'b1010; 8'b01100010 : bin = 4'b1011; 8'b01100011 : bin = 4'b1100; 8'b01100100 : bin = 4'b1101; 8'b01100101 : bin = 4'b1110; 8'b01100110 : bin = 4'b1111; default : begin bin = 4'bx; end endcase for( j=0; j<4; j=j+1) begin if ((index*4)+j < C_DOUT_WIDTH) begin hexstr_conv[(index*4)+j] = bin[j]; end end index = index + 1; def_data = def_data >> 8; end end endfunction //************************************************************************* // Set power-on states for regs //************************************************************************* initial begin ram_valid_i = 1'b0; fab_valid = 1'b0; read_data_valid_i = 1'b0; fab_read_data_valid_i = 1'b0; fab_read_data_valid_i_1 = 1'b0; USERDATA = hexstr_conv(C_DOUT_RST_VAL); userdata_both = hexstr_conv(C_DOUT_RST_VAL); USERSBITERR = 1'b0; USERDBITERR = 1'b0; user_sbiterr_both = 1'b0; user_dbiterr_both = 1'b0; end //initial //*************************************************************************** // connect up optional reset //*************************************************************************** assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0; reg sckt_rd_rst_fwft = 1'b0; reg fwft_rst_done_i = 1'b0; wire fwft_rst_done; assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1; always @ (posedge RD_CLK) begin sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST; end always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i) fwft_rst_done_i <= 1'b0; else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST) fwft_rst_done_i <= #`TCQ 1'b1; end localparam INVALID = 0; localparam STAGE1_VALID = 2; localparam STAGE2_VALID = 1; localparam BOTH_STAGES_VALID = 3; reg [1:0] curr_fwft_state = INVALID; reg [1:0] next_fwft_state = INVALID; generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin always @* begin case (curr_fwft_state) INVALID: begin if (~FIFOEMPTY) next_fwft_state <= STAGE1_VALID; else next_fwft_state <= INVALID; end STAGE1_VALID: begin if (FIFOEMPTY) next_fwft_state <= STAGE2_VALID; else next_fwft_state <= BOTH_STAGES_VALID; end STAGE2_VALID: begin if (FIFOEMPTY && RD_EN) next_fwft_state <= INVALID; else if (~FIFOEMPTY && RD_EN) next_fwft_state <= STAGE1_VALID; else if (~FIFOEMPTY && ~RD_EN) next_fwft_state <= BOTH_STAGES_VALID; else next_fwft_state <= STAGE2_VALID; end BOTH_STAGES_VALID: begin if (FIFOEMPTY && RD_EN) next_fwft_state <= STAGE2_VALID; else if (~FIFOEMPTY && RD_EN) next_fwft_state <= BOTH_STAGES_VALID; else next_fwft_state <= BOTH_STAGES_VALID; end default: next_fwft_state <= INVALID; endcase end always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i && C_EN_SAFETY_CKT == 0) curr_fwft_state <= INVALID; else if (srst_i) curr_fwft_state <= #`TCQ INVALID; else curr_fwft_state <= #`TCQ next_fwft_state; end always @* begin case (curr_fwft_state) INVALID: STAGE2_REG_EN <= 1'b0; STAGE1_VALID: STAGE2_REG_EN <= 1'b1; STAGE2_VALID: STAGE2_REG_EN <= 1'b0; BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN; default: STAGE2_REG_EN <= 1'b0; endcase end assign VALID_STAGES = curr_fwft_state; //*************************************************************************** // preloadstage2 indicates that stage2 needs to be updated. This is true // whenever read_data_valid is false, and RAM_valid is true. //*************************************************************************** assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN ); //*************************************************************************** // preloadstage1 indicates that stage1 needs to be updated. This is true // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is // false (indicating that Stage1 needs updating), or preloadstage2 is active // (indicating that Stage2 is going to update, so Stage1, therefore, must // also be updated to keep it valid. //*************************************************************************** assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); //*************************************************************************** // Calculate RAM_REGOUT_EN // The output registers are controlled by the ram_regout_en signal. // These registers should be updated either when the output in Stage2 is // invalid (preloadstage2), OR when the user is reading, in which case the // Stage2 value will go invalid unless it is replenished. //*************************************************************************** assign ram_regout_en = preloadstage2; //*************************************************************************** // Calculate RAM_RD_EN // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to // update the value in Stage1. // One case when this happens is when preloadstage1=true, which indicates // that the data in Stage1 or Stage2 is invalid, and needs to automatically // be updated. // The other case is when the user is reading from the FIFO, which // guarantees that Stage1 or Stage2 will be invalid on the next clock // cycle, unless it is replinished by data from the memory. So, as long // as the RAM has data in it, a read of the RAM should occur. //*************************************************************************** assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; end endgenerate // gnll_fifo reg curr_state = 0; reg next_state = 0; reg leaving_empty_fwft = 0; reg going_empty_fwft = 0; reg empty_i_q = 0; reg ram_rd_en_fwft = 0; generate if (C_FIFO_TYPE == 2) begin : gll_fifo always @* begin // FSM fo FWFT case (curr_state) 1'b0: begin if (~FIFOEMPTY) next_state <= 1'b1; else next_state <= 1'b0; end 1'b1: begin if (FIFOEMPTY && RD_EN) next_state <= 1'b0; else next_state <= 1'b1; end default: next_state <= 1'b0; endcase end always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin empty_i <= 1'b1; empty_i_q <= 1'b1; ram_valid_i <= 1'b0; end else if (srst_i) begin empty_i <= #`TCQ 1'b1; empty_i_q <= #`TCQ 1'b1; ram_valid_i <= #`TCQ 1'b0; end else begin empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i); empty_i_q <= #`TCQ FIFOEMPTY; ram_valid_i <= #`TCQ next_state; end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin curr_state <= 1'b0; end else if (srst_i) begin curr_state <= #`TCQ 1'b0; end else begin curr_state <= #`TCQ next_state; end end //always wire fe_of_empty; assign fe_of_empty = empty_i_q & ~FIFOEMPTY; always @* begin // Finding leaving empty case (curr_state) 1'b0: leaving_empty_fwft <= fe_of_empty; 1'b1: leaving_empty_fwft <= 1'b1; default: leaving_empty_fwft <= 1'b0; endcase end always @* begin // Finding going empty case (curr_state) 1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN; default: going_empty_fwft <= 1'b0; endcase end always @* begin // Generating FWFT rd_en case (curr_state) 1'b0: ram_rd_en_fwft <= ~FIFOEMPTY; 1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN; default: ram_rd_en_fwft <= 1'b0; endcase end assign ram_regout_en = ram_rd_en_fwft; //assign ram_regout_en_d1 = ram_rd_en_fwft; //assign ram_regout_en_d2 = ram_rd_en_fwft; assign ram_rd_en = ram_rd_en_fwft; end endgenerate // gll_fifo //*************************************************************************** // Calculate RAMVALID_P0_OUT // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. // // If the RAM is being read from on this clock cycle (ram_rd_en=1), then // RAMVALID_P0_OUT is certainly going to be true. // If the RAM is not being read from, but the output registers are being // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, // therefore causing RAMVALID_P0_OUT to be false. // Otherwise, RAMVALID_P0_OUT will remain unchanged. //*************************************************************************** // PROCESS regout_valid generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) ram_valid_i <= #`TCQ 1'b0; end else begin if (srst_i) begin // synchronous reset (active high) ram_valid_i <= #`TCQ 1'b0; end else begin if (ram_rd_en == 1'b1) begin ram_valid_i <= #`TCQ 1'b1; end else begin if (ram_regout_en == 1'b1) ram_valid_i <= #`TCQ 1'b0; else ram_valid_i <= #`TCQ ram_valid_i; end end //srst_i end //rd_rst_i end //always end endgenerate // gnll_fifo_ram_valid //*************************************************************************** // Calculate READ_DATA_VALID // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. // Stage2 has valid data whenever Stage1 had valid data and // ram_regout_en_i=1, such that the data in Stage1 is propogated // into Stage2. //*************************************************************************** generate if(C_USE_EMBEDDED_REG < 3) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) read_data_valid_i <= #`TCQ 1'b0; else if (srst_i) read_data_valid_i <= #`TCQ 1'b0; else read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); end //always end endgenerate //************************************************************************** // Calculate EMPTY // Defined as the inverse of READ_DATA_VALID // // Description: // // If read_data_valid_i indicates that the output is not valid, // and there is no valid data on the output of the ram to preload it // with, then we will report empty. // // If there is no valid data on the output of the ram and we are // reading, then the FIFO will go empty. // //************************************************************************** generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) empty_i <= #`TCQ 1'b1; end else begin if (srst_i) begin // synchronous reset (active high) empty_i <= #`TCQ 1'b1; end else begin // rising clock edge empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); end end end //always end endgenerate // gnll_fifo_empty // Register RD_EN from user to calculate USERUNDERFLOW. // Register empty_i to calculate USERUNDERFLOW. always @ (posedge RD_CLK) begin rd_en_q <= #`TCQ RD_EN; empty_q <= #`TCQ empty_i; end //always //*************************************************************************** // Calculate user_almost_empty // user_almost_empty is defined such that, unless more words are written // to the FIFO, the next read will cause the FIFO to go EMPTY. // // In most cases, whenever the output registers are updated (due to a user // read or a preload condition), then user_almost_empty will update to // whatever RAM_EMPTY is. // // The exception is when the output is valid, the user is not reading, and // Stage1 is not empty. In this condition, Stage1 will be preloaded from the // memory, so we need to make sure user_almost_empty deasserts properly under // this condition. //*************************************************************************** generate if ( C_USE_EMBEDDED_REG < 3) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) almost_empty_i <= #`TCQ 1'b1; almost_empty_q <= #`TCQ 1'b1; end else begin // rising clock edge if (srst_i) begin // synchronous reset (active high) almost_empty_i <= #`TCQ 1'b1; almost_empty_q <= #`TCQ 1'b1; end else begin if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin almost_empty_i <= #`TCQ FIFOEMPTY; end almost_empty_q <= #`TCQ empty_i; end end end //always end endgenerate // BRAM resets synchronously generate if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin always @ ( posedge rd_rst_i) begin if (rd_rst_i || srst_i) begin if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) @(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin //asynchronous reset (active high) if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; end // DRAM resets asynchronously if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else begin // rising clock edge if (srst_i) begin if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; end if (C_USE_DOUT_RST == 1) begin USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else if (fwft_rst_done) begin if (ram_regout_en) begin USERDATA <= #`TCQ FIFODATA; USERSBITERR <= #`TCQ FIFOSBITERR; USERDBITERR <= #`TCQ FIFODBITERR; end end end end //always end //if endgenerate //safety ckt with one register generate if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge RD_CLK) begin rst_delayed_sft1 <= #`TCQ rd_rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always @ (posedge RD_CLK) begin if (rd_rst_i || srst_i) begin if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin @(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin //asynchronous reset (active high) if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; end // DRAM resets asynchronously if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high) //@(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else begin // rising clock edge if (srst_i) begin if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; end if (C_USE_DOUT_RST == 1) begin // @(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else if (fwft_rst_done) begin if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin USERDATA <= #`TCQ FIFODATA; USERSBITERR <= #`TCQ FIFOSBITERR; USERDBITERR <= #`TCQ FIFODBITERR; end end end end //always end //if endgenerate generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin always @* begin case (curr_fwft_state) INVALID: begin if (~FIFOEMPTY) next_fwft_state <= STAGE1_VALID; else next_fwft_state <= INVALID; end STAGE1_VALID: begin if (FIFOEMPTY) next_fwft_state <= STAGE2_VALID; else next_fwft_state <= BOTH_STAGES_VALID; end STAGE2_VALID: begin if (FIFOEMPTY && RD_EN) next_fwft_state <= INVALID; else if (~FIFOEMPTY && RD_EN) next_fwft_state <= STAGE1_VALID; else if (~FIFOEMPTY && ~RD_EN) next_fwft_state <= BOTH_STAGES_VALID; else next_fwft_state <= STAGE2_VALID; end BOTH_STAGES_VALID: begin if (FIFOEMPTY && RD_EN) next_fwft_state <= STAGE2_VALID; else if (~FIFOEMPTY && RD_EN) next_fwft_state <= BOTH_STAGES_VALID; else next_fwft_state <= BOTH_STAGES_VALID; end default: next_fwft_state <= INVALID; endcase end always @ (posedge rd_rst_i or posedge RD_CLK) begin if (rd_rst_i && C_EN_SAFETY_CKT == 0) curr_fwft_state <= INVALID; else if (srst_i) curr_fwft_state <= #`TCQ INVALID; else curr_fwft_state <= #`TCQ next_fwft_state; end always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay if (rd_rst_i == 1) begin ram_regout_en_d1 <= #`TCQ 1'b0; end else begin if (srst_i == 1'b1) ram_regout_en_d1 <= #`TCQ 1'b0; else ram_regout_en_d1 <= #`TCQ ram_regout_en; end end //always // assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i)); assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0; always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1 if (rd_rst_i == 1) begin ram_regout_en_d2 <= #`TCQ 1'b0; end else begin if (srst_i == 1'b1) ram_regout_en_d2 <= #`TCQ 1'b0; else ram_regout_en_d2 <= #`TCQ ram_regout_en_d1; end end //always always @* begin case (curr_fwft_state) INVALID: STAGE2_REG_EN <= 1'b0; STAGE1_VALID: STAGE2_REG_EN <= 1'b1; STAGE2_VALID: STAGE2_REG_EN <= 1'b0; BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN; default: STAGE2_REG_EN <= 1'b0; endcase end always @ (posedge RD_CLK) begin ram_valid_i_d <= #`TCQ ram_valid_i; read_data_valid_i_d <= #`TCQ read_data_valid_i; fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i; end assign VALID_STAGES = curr_fwft_state; //*************************************************************************** // preloadstage2 indicates that stage2 needs to be updated. This is true // whenever read_data_valid is false, and RAM_valid is true. //*************************************************************************** assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN ); //*************************************************************************** // preloadstage1 indicates that stage1 needs to be updated. This is true // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is // false (indicating that Stage1 needs updating), or preloadstage2 is active // (indicating that Stage2 is going to update, so Stage1, therefore, must // also be updated to keep it valid. //*************************************************************************** assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); //*************************************************************************** // Calculate RAM_REGOUT_EN // The output registers are controlled by the ram_regout_en signal. // These registers should be updated either when the output in Stage2 is // invalid (preloadstage2), OR when the user is reading, in which case the // Stage2 value will go invalid unless it is replenished. //*************************************************************************** assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0; //*************************************************************************** // Calculate RAM_RD_EN // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to // update the value in Stage1. // One case when this happens is when preloadstage1=true, which indicates // that the data in Stage1 or Stage2 is invalid, and needs to automatically // be updated. // The other case is when the user is reading from the FIFO, which // guarantees that Stage1 or Stage2 will be invalid on the next clock // cycle, unless it is replinished by data from the memory. So, as long // as the RAM has data in it, a read of the RAM should occur. //*************************************************************************** assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1; end endgenerate // gnll_fifo //*************************************************************************** // Calculate RAMVALID_P0_OUT // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. // // If the RAM is being read from on this clock cycle (ram_rd_en=1), then // RAMVALID_P0_OUT is certainly going to be true. // If the RAM is not being read from, but the output registers are being // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, // therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged. //*************************************************************************** // PROCESS regout_valid generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) fab_valid <= #`TCQ 1'b0; end else begin if (srst_i) begin // synchronous reset (active high) fab_valid <= #`TCQ 1'b0; end else begin if (ram_regout_en == 1'b1) begin fab_valid <= #`TCQ 1'b1; end else begin if (fab_regout_en == 1'b1) fab_valid <= #`TCQ 1'b0; else fab_valid <= #`TCQ fab_valid; end end //srst_i end //rd_rst_i end //always end endgenerate // gnll_fifo_fab_valid //*************************************************************************** // Calculate READ_DATA_VALID // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. // Stage2 has valid data whenever Stage1 had valid data and // ram_regout_en_i=1, such that the data in Stage1 is propogated // into Stage2. //*************************************************************************** generate if(C_USE_EMBEDDED_REG == 3) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) read_data_valid_i <= #`TCQ 1'b0; else if (srst_i) read_data_valid_i <= #`TCQ 1'b0; else begin if (ram_regout_en == 1'b1) begin read_data_valid_i <= #`TCQ 1'b1; end else begin if (fab_regout_en == 1'b1) read_data_valid_i <= #`TCQ 1'b0; else read_data_valid_i <= #`TCQ read_data_valid_i; end end end //always end endgenerate //generate if(C_USE_EMBEDDED_REG == 3) begin // always @ (posedge RD_CLK or posedge rd_rst_i) begin // if (rd_rst_i) // read_data_valid_i <= #`TCQ 1'b0; // else if (srst_i) // read_data_valid_i <= #`TCQ 1'b0; // // if (ram_regout_en == 1'b1) begin // fab_read_data_valid_i <= #`TCQ 1'b0; // end else begin // if (fab_regout_en == 1'b1) // fab_read_data_valid_i <= #`TCQ 1'b1; // else // fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i; // end // end //always //end //endgenerate generate if(C_USE_EMBEDDED_REG == 3 ) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid if (rd_rst_i) fab_read_data_valid_i <= #`TCQ 1'b0; else if (srst_i) fab_read_data_valid_i <= #`TCQ 1'b0; else fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN); end //always end endgenerate always @ (posedge RD_CLK ) begin : proc_del1 begin fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i; end end //always //************************************************************************** // Calculate EMPTY // Defined as the inverse of READ_DATA_VALID // // Description: // // If read_data_valid_i indicates that the output is not valid, // and there is no valid data on the output of the ram to preload it // with, then we will report empty. // // If there is no valid data on the output of the ram and we are // reading, then the FIFO will go empty. // //************************************************************************** generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) empty_i <= #`TCQ 1'b1; end else begin if (srst_i) begin // synchronous reset (active high) empty_i <= #`TCQ 1'b1; end else begin // rising clock edge empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN); end end end //always end endgenerate // gnll_fifo_empty_both // Register RD_EN from user to calculate USERUNDERFLOW. // Register empty_i to calculate USERUNDERFLOW. always @ (posedge RD_CLK) begin rd_en_q <= #`TCQ RD_EN; empty_q <= #`TCQ empty_i; end //always //*************************************************************************** // Calculate user_almost_empty // user_almost_empty is defined such that, unless more words are written // to the FIFO, the next read will cause the FIFO to go EMPTY. // // In most cases, whenever the output registers are updated (due to a user // read or a preload condition), then user_almost_empty will update to // whatever RAM_EMPTY is. // // The exception is when the output is valid, the user is not reading, and // Stage1 is not empty. In this condition, Stage1 will be preloaded from the // memory, so we need to make sure user_almost_empty deasserts properly under // this condition. //*************************************************************************** reg FIFOEMPTY_1; generate if (C_USE_EMBEDDED_REG == 3 ) begin always @(posedge RD_CLK) begin FIFOEMPTY_1 <= #`TCQ FIFOEMPTY; end end endgenerate generate if (C_USE_EMBEDDED_REG == 3 ) begin always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin // asynchronous reset (active high) almost_empty_i <= #`TCQ 1'b1; almost_empty_q <= #`TCQ 1'b1; end else begin // rising clock edge if (srst_i) begin // synchronous reset (active high) almost_empty_i <= #`TCQ 1'b1; almost_empty_q <= #`TCQ 1'b1; end else begin if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin almost_empty_i <= #`TCQ (~ram_valid_i); end almost_empty_q <= #`TCQ empty_i; end end end //always end endgenerate always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin empty_sckt <= #`TCQ 1'b1; sckt_rrst_q <= #`TCQ 1'b0; sckt_rrst_done <= #`TCQ 1'b0; end else begin sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST; if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin sckt_rrst_done <= #`TCQ 1'b1; end else if (sckt_rrst_done) begin // rising clock edge empty_sckt <= #`TCQ 1'b0; end end end //always // assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i; assign USEREMPTY = empty_i; assign USERALMOSTEMPTY = almost_empty_i; assign FIFORDEN = ram_rd_en; assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i; assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0); assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0); assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one; assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; //no safety ckt with both reg generate if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin always @ (posedge RD_CLK) begin if (rd_rst_i || srst_i) begin if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin //asynchronous reset (active high) if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end // DRAM resets asynchronously if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end else begin // rising clock edge if (srst_i) begin if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end else begin if (fwft_rst_done) begin if (ram_regout_en) begin userdata_both <= #`TCQ FIFODATA; user_dbiterr_both <= #`TCQ FIFODBITERR; user_sbiterr_both <= #`TCQ FIFOSBITERR; end if (fab_regout_en) begin USERDATA <= #`TCQ userdata_both; USERDBITERR <= #`TCQ user_dbiterr_both; USERSBITERR <= #`TCQ user_sbiterr_both; end end end end end //always end //if endgenerate //safety_ckt with both registers generate if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; reg [1:0] rst_delayed_sft1 =1; reg [1:0] rst_delayed_sft2 =1; reg [1:0] rst_delayed_sft3 =1; reg [1:0] rst_delayed_sft4 =1; always@(posedge RD_CLK) begin rst_delayed_sft1 <= #`TCQ rd_rst_i; rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; end always @ (posedge RD_CLK) begin if (rd_rst_i || srst_i) begin if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin @(posedge RD_CLK) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end end //always always @ (posedge RD_CLK or posedge rd_rst_i) begin if (rd_rst_i) begin //asynchronous reset (active high) if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end // DRAM resets asynchronously if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high) USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end end else begin // rising clock edge if (srst_i) begin if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF USERSBITERR <= #`TCQ 0; USERDBITERR <= #`TCQ 0; user_sbiterr_both <= #`TCQ 0; user_dbiterr_both <= #`TCQ 0; end if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); end end else if (fwft_rst_done) begin if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin userdata_both <= #`TCQ FIFODATA; user_dbiterr_both <= #`TCQ FIFODBITERR; user_sbiterr_both <= #`TCQ FIFOSBITERR; end if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin USERDATA <= #`TCQ userdata_both; USERDBITERR <= #`TCQ user_dbiterr_both; USERSBITERR <= #`TCQ user_sbiterr_both; end end end end //always end //if endgenerate endmodule //fifo_generator_v13_1_3_bhv_ver_preload0 //----------------------------------------------------------------------------- // // Register Slice // Register one AXI channel on forward and/or reverse signal path // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // reg_slice // //-------------------------------------------------------------------------- module fifo_generator_v13_1_3_axic_reg_slice # ( parameter C_FAMILY = "virtex7", parameter C_DATA_WIDTH = 32, parameter C_REG_CONFIG = 32'h00000000 ) ( // System Signals input wire ACLK, input wire ARESET, // Slave side input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, input wire S_VALID, output wire S_READY, // Master side output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, output wire M_VALID, input wire M_READY ); generate //////////////////////////////////////////////////////////////////// // // Both FWD and REV mode // //////////////////////////////////////////////////////////////////// if (C_REG_CONFIG == 32'h00000000) begin reg [1:0] state; localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01; reg [C_DATA_WIDTH-1:0] storage_data1 = 0; reg [C_DATA_WIDTH-1:0] storage_data2 = 0; reg load_s1; wire load_s2; wire load_s1_from_s2; reg s_ready_i; //local signal of output wire m_valid_i; //local signal of output // assign local signal to its output signal assign S_READY = s_ready_i; assign M_VALID = m_valid_i; reg areset_d1; // Reset delay register always @(posedge ACLK) begin areset_d1 <= ARESET; end // Load storage1 with either slave side data or from storage2 always @(posedge ACLK) begin if (load_s1) if (load_s1_from_s2) storage_data1 <= storage_data2; else storage_data1 <= S_PAYLOAD_DATA; end // Load storage2 with slave side data always @(posedge ACLK) begin if (load_s2) storage_data2 <= S_PAYLOAD_DATA; end assign M_PAYLOAD_DATA = storage_data1; // Always load s2 on a valid transaction even if it's unnecessary assign load_s2 = S_VALID & s_ready_i; // Loading s1 always @ * begin if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction // Load when ONE if we both have read and write at the same time ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) || // Load when TWO and we have a transaction on Master side ((state == TWO) && (M_READY == 1))) load_s1 = 1'b1; else load_s1 = 1'b0; end // always @ * assign load_s1_from_s2 = (state == TWO); // State Machine for handling output signals always @(posedge ACLK) begin if (ARESET) begin s_ready_i <= 1'b0; state <= ZERO; end else if (areset_d1) begin s_ready_i <= 1'b1; end else begin case (state) // No transaction stored locally ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE // One transaction stored locally ONE: begin if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO if (~M_READY & S_VALID) begin state <= TWO; // Got another one so move to TWO s_ready_i <= 1'b0; end end // TWO transaction stored locally TWO: if (M_READY) begin state <= ONE; // Read out one so move to ONE s_ready_i <= 1'b1; end endcase // case (state) end end // always @ (posedge ACLK) assign m_valid_i = state[0]; end // if (C_REG_CONFIG == 1) //////////////////////////////////////////////////////////////////// // // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining // Operates same as 1-deep FIFO // //////////////////////////////////////////////////////////////////// else if (C_REG_CONFIG == 32'h00000001) begin reg [C_DATA_WIDTH-1:0] storage_data1 = 0; reg s_ready_i; //local signal of output reg m_valid_i; //local signal of output // assign local signal to its output signal assign S_READY = s_ready_i; assign M_VALID = m_valid_i; reg areset_d1; // Reset delay register always @(posedge ACLK) begin areset_d1 <= ARESET; end // Load storage1 with slave side data always @(posedge ACLK) begin if (ARESET) begin s_ready_i <= 1'b0; m_valid_i <= 1'b0; end else if (areset_d1) begin s_ready_i <= 1'b1; end else if (m_valid_i & M_READY) begin s_ready_i <= 1'b1; m_valid_i <= 1'b0; end else if (S_VALID & s_ready_i) begin s_ready_i <= 1'b0; m_valid_i <= 1'b1; end if (~m_valid_i) begin storage_data1 <= S_PAYLOAD_DATA; end end assign M_PAYLOAD_DATA = storage_data1; end // if (C_REG_CONFIG == 7) else begin : default_case // Passthrough assign M_PAYLOAD_DATA = S_PAYLOAD_DATA; assign M_VALID = S_VALID; assign S_READY = M_READY; end endgenerate endmodule // reg_slice
// -*- verilog -*- // // USRP - Universal Software Radio Peripheral // // Copyright (C) 2003 Matt Ettus // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // DUC block module duc(input clock, input reset, input enable, input [3:0] rate1, input [3:0] rate2, output strobe, input [31:0] freq, input [15:0] i_in, input [15:0] q_in, output [15:0] i_out, output [15:0] q_out ); parameter bw = 16; parameter zw = 16; wire [15:0] i_interp_out, q_interp_out; wire [31:0] phase; wire strobe1, strobe2; reg [3:0] strobe_ctr1,strobe_ctr2; always @(posedge clock) if(reset | ~enable) strobe_ctr2 <= #1 4'd0; else if(strobe2) strobe_ctr2 <= #1 4'd0; else strobe_ctr2 <= #1 strobe_ctr2 + 4'd1; always @(posedge clock) if(reset | ~enable) strobe_ctr1 <= #1 4'd0; else if(strobe1) strobe_ctr1 <= #1 4'd0; else if(strobe2) strobe_ctr1 <= #1 strobe_ctr1 + 4'd1; assign strobe2 = enable & ( strobe_ctr2 == rate2 ); assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 ); assign strobe = strobe1; function [2:0] log_ceil; input [3:0] val; log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; endfunction wire [2:0] shift1 = log_ceil(rate1); wire [2:0] shift2 = log_ceil(rate2); cordic #(.bitwidth(bw),.zwidth(zw),.stages(16)) cordic(.clock(clock), .reset(reset), .enable(enable), .xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]), .xo(i_out), .yo(q_out), .zo() ); cic_interp_2stage #(.bw(bw),.N(4)) interp_i(.clock(clock),.reset(reset),.enable(enable), .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2), .signal_in(i_in),.signal_out(i_interp_out)); cic_interp_2stage #(.bw(bw),.N(4)) interp_q(.clock(clock),.reset(reset),.enable(enable), .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2), .signal_in(q_in),.signal_out(q_interp_out)); phase_acc #(.resolution(32)) nco (.clk(clock),.reset(reset),.enable(enable), .freq(freq),.phase(phase)); endmodule
// -*- verilog -*- // // USRP - Universal Software Radio Peripheral // // Copyright (C) 2003 Matt Ettus // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // DUC block module duc(input clock, input reset, input enable, input [3:0] rate1, input [3:0] rate2, output strobe, input [31:0] freq, input [15:0] i_in, input [15:0] q_in, output [15:0] i_out, output [15:0] q_out ); parameter bw = 16; parameter zw = 16; wire [15:0] i_interp_out, q_interp_out; wire [31:0] phase; wire strobe1, strobe2; reg [3:0] strobe_ctr1,strobe_ctr2; always @(posedge clock) if(reset | ~enable) strobe_ctr2 <= #1 4'd0; else if(strobe2) strobe_ctr2 <= #1 4'd0; else strobe_ctr2 <= #1 strobe_ctr2 + 4'd1; always @(posedge clock) if(reset | ~enable) strobe_ctr1 <= #1 4'd0; else if(strobe1) strobe_ctr1 <= #1 4'd0; else if(strobe2) strobe_ctr1 <= #1 strobe_ctr1 + 4'd1; assign strobe2 = enable & ( strobe_ctr2 == rate2 ); assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 ); assign strobe = strobe1; function [2:0] log_ceil; input [3:0] val; log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; endfunction wire [2:0] shift1 = log_ceil(rate1); wire [2:0] shift2 = log_ceil(rate2); cordic #(.bitwidth(bw),.zwidth(zw),.stages(16)) cordic(.clock(clock), .reset(reset), .enable(enable), .xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]), .xo(i_out), .yo(q_out), .zo() ); cic_interp_2stage #(.bw(bw),.N(4)) interp_i(.clock(clock),.reset(reset),.enable(enable), .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2), .signal_in(i_in),.signal_out(i_interp_out)); cic_interp_2stage #(.bw(bw),.N(4)) interp_q(.clock(clock),.reset(reset),.enable(enable), .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2), .signal_in(q_in),.signal_out(q_interp_out)); phase_acc #(.resolution(32)) nco (.clk(clock),.reset(reset),.enable(enable), .freq(freq),.phase(phase)); endmodule
// -*- verilog -*- // // USRP - Universal Software Radio Peripheral // // Copyright (C) 2003 Matt Ettus // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // DUC block module duc(input clock, input reset, input enable, input [3:0] rate1, input [3:0] rate2, output strobe, input [31:0] freq, input [15:0] i_in, input [15:0] q_in, output [15:0] i_out, output [15:0] q_out ); parameter bw = 16; parameter zw = 16; wire [15:0] i_interp_out, q_interp_out; wire [31:0] phase; wire strobe1, strobe2; reg [3:0] strobe_ctr1,strobe_ctr2; always @(posedge clock) if(reset | ~enable) strobe_ctr2 <= #1 4'd0; else if(strobe2) strobe_ctr2 <= #1 4'd0; else strobe_ctr2 <= #1 strobe_ctr2 + 4'd1; always @(posedge clock) if(reset | ~enable) strobe_ctr1 <= #1 4'd0; else if(strobe1) strobe_ctr1 <= #1 4'd0; else if(strobe2) strobe_ctr1 <= #1 strobe_ctr1 + 4'd1; assign strobe2 = enable & ( strobe_ctr2 == rate2 ); assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 ); assign strobe = strobe1; function [2:0] log_ceil; input [3:0] val; log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; endfunction wire [2:0] shift1 = log_ceil(rate1); wire [2:0] shift2 = log_ceil(rate2); cordic #(.bitwidth(bw),.zwidth(zw),.stages(16)) cordic(.clock(clock), .reset(reset), .enable(enable), .xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]), .xo(i_out), .yo(q_out), .zo() ); cic_interp_2stage #(.bw(bw),.N(4)) interp_i(.clock(clock),.reset(reset),.enable(enable), .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2), .signal_in(i_in),.signal_out(i_interp_out)); cic_interp_2stage #(.bw(bw),.N(4)) interp_q(.clock(clock),.reset(reset),.enable(enable), .strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2), .signal_in(q_in),.signal_out(q_interp_out)); phase_acc #(.resolution(32)) nco (.clk(clock),.reset(reset),.enable(enable), .freq(freq),.phase(phase)); endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Addr Decoder // Each received address is compared to base and high address pairs for each // of a set of decode targets. // The matching target's index (if any) is output combinatorially. // If the decode is successful (matches any target), the MATCH output is asserted. // For each target, a set of alternative address ranges may be specified. // The base and high address pairs are formatted as a pair of 2-dimensional arrays, // alternative address ranges iterate within each target. // The alternative range which matches the address is also output as REGION. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // addr_decoder // comparator_static // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_addr_decoder # ( parameter C_FAMILY = "none", parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16] parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS) parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that // can match each target [1:16] parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of // each base and high address [2:64] parameter integer C_TARGET_ENC = 0, // Enable encoded target output parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output parameter integer C_REGION_ENC = 0, // Enable REGION output parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}}, parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}}, parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}}, // Indicates whether each target has connectivity. // Format: C_NUM_TARGETS{Bit1}. parameter integer C_RESOLUTION = 0, // Number of low-order ADDR bits that can be ignored when decoding. parameter integer C_COMPARATOR_THRESHOLD = 6 // Number of decoded ADDR bits above which will implement comparator_static. ) ( input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot) output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded) output wire MATCH, // Decode successful output wire [3:0] REGION // Range within target matching address (encoded) ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. genvar target_cnt; genvar region_cnt; ///////////////////////////////////////////////////////////////////////////// // Function to detect addrs is in the addressable range. // Only compare 4KB page address (ignore low-order 12 bits) function decode_address; input [C_ADDR_WIDTH-1:0] base, high, addr; reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask; reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page; reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page; reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page; begin addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION]; base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION]; high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION]; if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin decode_address = 1'b0; end else begin mask = base_page ^ high_page; if ( (base_page & ~mask) == (addr_page & ~mask) ) begin decode_address = 1'b1; end else begin decode_address = 1'b0; end end end endfunction // Generates a binary coded from onehotone encoded function [3:0] f_hot2enc ( input [15:0] one_hot ); begin f_hot2enc[0] = |(one_hot & 16'b1010101010101010); f_hot2enc[1] = |(one_hot & 16'b1100110011001100); f_hot2enc[2] = |(one_hot & 16'b1111000011110000); f_hot2enc[3] = |(one_hot & 16'b1111111100000000); end endfunction ///////////////////////////////////////////////////////////////////////////// // Internal signals wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot). wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot). wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot). wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot). wire [3:0] TARGET_ENC_I; // Internal version of encoded hit. ///////////////////////////////////////////////////////////////////////////// // Generate detection per region per target. generate for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region // Detect if this is an address hit (including used region decoding). if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static if (C_TARGET_QUAL[target_cnt] && ((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) || (C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range generic_baseblocks_v2_1_comparator_static # ( .C_FAMILY("rtl"), .C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]), .C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION) ) addr_decode_comparator ( .CIN(1'b1), .A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] & ~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^ C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])), .COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt]) ); end else begin : gen_null_range assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0; end end else begin : gen_no_comparator_static assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ? decode_address( C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH], C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH], ADDR) : 1'b0; end // gen_comparator_static assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt]; assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS]; end // gen_region // All regions are non-overlapping // => Or all the region detections for this target to determine if it is a hit. assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES]; end // gen_target endgenerate ///////////////////////////////////////////////////////////////////////////// // All regions are non-overlapping // => Or all the target hit detections if it is a match. assign MATCH = | TARGET_HOT_I; ///////////////////////////////////////////////////////////////////////////// // Assign conditional onehot target output signal. generate if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1; end else begin : NO_TARGET_ONEHOT assign TARGET_HOT = {C_NUM_TARGETS{1'b0}}; end endgenerate ///////////////////////////////////////////////////////////////////////////// // Assign conditional encoded target output signal. generate if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I); assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0]; end else begin : NO_TARGET_ENCODED assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}}; end endgenerate ///////////////////////////////////////////////////////////////////////////// // Assign conditional encoded region output signal. generate if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED assign REGION = f_hot2enc(REGION_HOT); end else begin : NO_REGION_ENCODED assign REGION = 4'b0; end endgenerate endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Addr Decoder // Each received address is compared to base and high address pairs for each // of a set of decode targets. // The matching target's index (if any) is output combinatorially. // If the decode is successful (matches any target), the MATCH output is asserted. // For each target, a set of alternative address ranges may be specified. // The base and high address pairs are formatted as a pair of 2-dimensional arrays, // alternative address ranges iterate within each target. // The alternative range which matches the address is also output as REGION. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // addr_decoder // comparator_static // //-------------------------------------------------------------------------- `timescale 1ps/1ps (* DowngradeIPIdentifiedWarnings="yes" *) module axi_crossbar_v2_1_addr_decoder # ( parameter C_FAMILY = "none", parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16] parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS) parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that // can match each target [1:16] parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of // each base and high address [2:64] parameter integer C_TARGET_ENC = 0, // Enable encoded target output parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output parameter integer C_REGION_ENC = 0, // Enable REGION output parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}}, parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}}, parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}}, // Indicates whether each target has connectivity. // Format: C_NUM_TARGETS{Bit1}. parameter integer C_RESOLUTION = 0, // Number of low-order ADDR bits that can be ignored when decoding. parameter integer C_COMPARATOR_THRESHOLD = 6 // Number of decoded ADDR bits above which will implement comparator_static. ) ( input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot) output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded) output wire MATCH, // Decode successful output wire [3:0] REGION // Range within target matching address (encoded) ); ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. genvar target_cnt; genvar region_cnt; ///////////////////////////////////////////////////////////////////////////// // Function to detect addrs is in the addressable range. // Only compare 4KB page address (ignore low-order 12 bits) function decode_address; input [C_ADDR_WIDTH-1:0] base, high, addr; reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask; reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page; reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page; reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page; begin addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION]; base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION]; high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION]; if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin decode_address = 1'b0; end else begin mask = base_page ^ high_page; if ( (base_page & ~mask) == (addr_page & ~mask) ) begin decode_address = 1'b1; end else begin decode_address = 1'b0; end end end endfunction // Generates a binary coded from onehotone encoded function [3:0] f_hot2enc ( input [15:0] one_hot ); begin f_hot2enc[0] = |(one_hot & 16'b1010101010101010); f_hot2enc[1] = |(one_hot & 16'b1100110011001100); f_hot2enc[2] = |(one_hot & 16'b1111000011110000); f_hot2enc[3] = |(one_hot & 16'b1111111100000000); end endfunction ///////////////////////////////////////////////////////////////////////////// // Internal signals wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot). wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot). wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot). wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot). wire [3:0] TARGET_ENC_I; // Internal version of encoded hit. ///////////////////////////////////////////////////////////////////////////// // Generate detection per region per target. generate for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region // Detect if this is an address hit (including used region decoding). if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static if (C_TARGET_QUAL[target_cnt] && ((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) || (C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range generic_baseblocks_v2_1_comparator_static # ( .C_FAMILY("rtl"), .C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]), .C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION) ) addr_decode_comparator ( .CIN(1'b1), .A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] & ~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^ C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])), .COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt]) ); end else begin : gen_null_range assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0; end end else begin : gen_no_comparator_static assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ? decode_address( C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH], C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH], ADDR) : 1'b0; end // gen_comparator_static assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt]; assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS]; end // gen_region // All regions are non-overlapping // => Or all the region detections for this target to determine if it is a hit. assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES]; end // gen_target endgenerate ///////////////////////////////////////////////////////////////////////////// // All regions are non-overlapping // => Or all the target hit detections if it is a match. assign MATCH = | TARGET_HOT_I; ///////////////////////////////////////////////////////////////////////////// // Assign conditional onehot target output signal. generate if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1; end else begin : NO_TARGET_ONEHOT assign TARGET_HOT = {C_NUM_TARGETS{1'b0}}; end endgenerate ///////////////////////////////////////////////////////////////////////////// // Assign conditional encoded target output signal. generate if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I); assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0]; end else begin : NO_TARGET_ENCODED assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}}; end endgenerate ///////////////////////////////////////////////////////////////////////////// // Assign conditional encoded region output signal. generate if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED assign REGION = f_hot2enc(REGION_HOT); end else begin : NO_REGION_ENCODED assign REGION = 4'b0; end endgenerate endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 15:15:08 08/27/2015 // Design Name: // Module Name: Tenth_Phase // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Tenth_Phase //Module Parameters /***SINGLE PRECISION***/ // W = 32 // EW = 8 // SW = 23 /***DOUBLE PRECISION***/ // W = 64 // EW = 11 // SW = 52 # (parameter W = 32, parameter EW = 8, parameter SW = 23) // # (parameter W = 64, parameter EW = 11, parameter SW = 52) ( //INPUTS input wire clk, //Clock Signal input wire rst, //Reset Signal input wire load_i, input wire sel_a_i, //Overflow/add/subt result's mux's selector input wire sel_b_i, //underflow/add/subt result's mux's selector input wire sign_i, //Sign of the largest Operand input wire [EW-1:0] exp_ieee_i, //Final Exponent input wire [SW-1:0] sgf_ieee_i,//Final Significand //OUTPUTS output wire [W-1:0] final_result_ieee_o //Final Result ); //Wire Connection signals wire [SW-1:0] Sgf_S_mux; wire [EW-1:0] Exp_S_mux; wire Sign_S_mux; wire [W-1:0] final_result_reg; wire overunder; wire [EW-1:0] exp_mux_D1; wire [SW-1:0] sgf_mux_D1; ////////////////////////////////////////////////////////// assign overunder = sel_a_i | sel_b_i; Mux_3x1 #(.W(1)) Sign_Mux ( .ctrl({sel_a_i,sel_b_i}), .D0(sign_i), .D1(1'b1), .D2(1'b0), .S(Sign_S_mux) ); Multiplexer_AC #(.W(EW)) Exp_Mux ( .ctrl(overunder), .D0(exp_ieee_i), .D1(exp_mux_D1), .S(Exp_S_mux) ); Multiplexer_AC #(.W(SW)) Sgf_Mux ( .ctrl(overunder), .D0(sgf_ieee_i), .D1(sgf_mux_D1), .S(Sgf_S_mux) ); ///////////////////////////////////////////////////////// generate if(W == 32) begin assign exp_mux_D1 =8'hff; assign sgf_mux_D1 =23'd0; end else begin assign exp_mux_D1 =11'hfff; assign sgf_mux_D1 =52'd0; end endgenerate //////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////// RegisterAdd #(.W(W)) Final_Result_IEEE ( .clk(clk), .rst(rst), .load(load_i), .D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}), .Q(final_result_ieee_o) ); endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 15:15:08 08/27/2015 // Design Name: // Module Name: Tenth_Phase // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Tenth_Phase //Module Parameters /***SINGLE PRECISION***/ // W = 32 // EW = 8 // SW = 23 /***DOUBLE PRECISION***/ // W = 64 // EW = 11 // SW = 52 # (parameter W = 32, parameter EW = 8, parameter SW = 23) // # (parameter W = 64, parameter EW = 11, parameter SW = 52) ( //INPUTS input wire clk, //Clock Signal input wire rst, //Reset Signal input wire load_i, input wire sel_a_i, //Overflow/add/subt result's mux's selector input wire sel_b_i, //underflow/add/subt result's mux's selector input wire sign_i, //Sign of the largest Operand input wire [EW-1:0] exp_ieee_i, //Final Exponent input wire [SW-1:0] sgf_ieee_i,//Final Significand //OUTPUTS output wire [W-1:0] final_result_ieee_o //Final Result ); //Wire Connection signals wire [SW-1:0] Sgf_S_mux; wire [EW-1:0] Exp_S_mux; wire Sign_S_mux; wire [W-1:0] final_result_reg; wire overunder; wire [EW-1:0] exp_mux_D1; wire [SW-1:0] sgf_mux_D1; ////////////////////////////////////////////////////////// assign overunder = sel_a_i | sel_b_i; Mux_3x1 #(.W(1)) Sign_Mux ( .ctrl({sel_a_i,sel_b_i}), .D0(sign_i), .D1(1'b1), .D2(1'b0), .S(Sign_S_mux) ); Multiplexer_AC #(.W(EW)) Exp_Mux ( .ctrl(overunder), .D0(exp_ieee_i), .D1(exp_mux_D1), .S(Exp_S_mux) ); Multiplexer_AC #(.W(SW)) Sgf_Mux ( .ctrl(overunder), .D0(sgf_ieee_i), .D1(sgf_mux_D1), .S(Sgf_S_mux) ); ///////////////////////////////////////////////////////// generate if(W == 32) begin assign exp_mux_D1 =8'hff; assign sgf_mux_D1 =23'd0; end else begin assign exp_mux_D1 =11'hfff; assign sgf_mux_D1 =52'd0; end endgenerate //////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////// RegisterAdd #(.W(W)) Final_Result_IEEE ( .clk(clk), .rst(rst), .load(load_i), .D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}), .Q(final_result_ieee_o) ); endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 15:15:08 08/27/2015 // Design Name: // Module Name: Tenth_Phase // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Tenth_Phase //Module Parameters /***SINGLE PRECISION***/ // W = 32 // EW = 8 // SW = 23 /***DOUBLE PRECISION***/ // W = 64 // EW = 11 // SW = 52 # (parameter W = 32, parameter EW = 8, parameter SW = 23) // # (parameter W = 64, parameter EW = 11, parameter SW = 52) ( //INPUTS input wire clk, //Clock Signal input wire rst, //Reset Signal input wire load_i, input wire sel_a_i, //Overflow/add/subt result's mux's selector input wire sel_b_i, //underflow/add/subt result's mux's selector input wire sign_i, //Sign of the largest Operand input wire [EW-1:0] exp_ieee_i, //Final Exponent input wire [SW-1:0] sgf_ieee_i,//Final Significand //OUTPUTS output wire [W-1:0] final_result_ieee_o //Final Result ); //Wire Connection signals wire [SW-1:0] Sgf_S_mux; wire [EW-1:0] Exp_S_mux; wire Sign_S_mux; wire [W-1:0] final_result_reg; wire overunder; wire [EW-1:0] exp_mux_D1; wire [SW-1:0] sgf_mux_D1; ////////////////////////////////////////////////////////// assign overunder = sel_a_i | sel_b_i; Mux_3x1 #(.W(1)) Sign_Mux ( .ctrl({sel_a_i,sel_b_i}), .D0(sign_i), .D1(1'b1), .D2(1'b0), .S(Sign_S_mux) ); Multiplexer_AC #(.W(EW)) Exp_Mux ( .ctrl(overunder), .D0(exp_ieee_i), .D1(exp_mux_D1), .S(Exp_S_mux) ); Multiplexer_AC #(.W(SW)) Sgf_Mux ( .ctrl(overunder), .D0(sgf_ieee_i), .D1(sgf_mux_D1), .S(Sgf_S_mux) ); ///////////////////////////////////////////////////////// generate if(W == 32) begin assign exp_mux_D1 =8'hff; assign sgf_mux_D1 =23'd0; end else begin assign exp_mux_D1 =11'hfff; assign sgf_mux_D1 =52'd0; end endgenerate //////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////// RegisterAdd #(.W(W)) Final_Result_IEEE ( .clk(clk), .rst(rst), .load(load_i), .D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}), .Q(final_result_ieee_o) ); endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 15:15:08 08/27/2015 // Design Name: // Module Name: Tenth_Phase // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Tenth_Phase //Module Parameters /***SINGLE PRECISION***/ // W = 32 // EW = 8 // SW = 23 /***DOUBLE PRECISION***/ // W = 64 // EW = 11 // SW = 52 # (parameter W = 32, parameter EW = 8, parameter SW = 23) // # (parameter W = 64, parameter EW = 11, parameter SW = 52) ( //INPUTS input wire clk, //Clock Signal input wire rst, //Reset Signal input wire load_i, input wire sel_a_i, //Overflow/add/subt result's mux's selector input wire sel_b_i, //underflow/add/subt result's mux's selector input wire sign_i, //Sign of the largest Operand input wire [EW-1:0] exp_ieee_i, //Final Exponent input wire [SW-1:0] sgf_ieee_i,//Final Significand //OUTPUTS output wire [W-1:0] final_result_ieee_o //Final Result ); //Wire Connection signals wire [SW-1:0] Sgf_S_mux; wire [EW-1:0] Exp_S_mux; wire Sign_S_mux; wire [W-1:0] final_result_reg; wire overunder; wire [EW-1:0] exp_mux_D1; wire [SW-1:0] sgf_mux_D1; ////////////////////////////////////////////////////////// assign overunder = sel_a_i | sel_b_i; Mux_3x1 #(.W(1)) Sign_Mux ( .ctrl({sel_a_i,sel_b_i}), .D0(sign_i), .D1(1'b1), .D2(1'b0), .S(Sign_S_mux) ); Multiplexer_AC #(.W(EW)) Exp_Mux ( .ctrl(overunder), .D0(exp_ieee_i), .D1(exp_mux_D1), .S(Exp_S_mux) ); Multiplexer_AC #(.W(SW)) Sgf_Mux ( .ctrl(overunder), .D0(sgf_ieee_i), .D1(sgf_mux_D1), .S(Sgf_S_mux) ); ///////////////////////////////////////////////////////// generate if(W == 32) begin assign exp_mux_D1 =8'hff; assign sgf_mux_D1 =23'd0; end else begin assign exp_mux_D1 =11'hfff; assign sgf_mux_D1 =52'd0; end endgenerate //////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////// RegisterAdd #(.W(W)) Final_Result_IEEE ( .clk(clk), .rst(rst), .load(load_i), .D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}), .Q(final_result_ieee_o) ); endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 15:15:08 08/27/2015 // Design Name: // Module Name: Tenth_Phase // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Tenth_Phase //Module Parameters /***SINGLE PRECISION***/ // W = 32 // EW = 8 // SW = 23 /***DOUBLE PRECISION***/ // W = 64 // EW = 11 // SW = 52 # (parameter W = 32, parameter EW = 8, parameter SW = 23) // # (parameter W = 64, parameter EW = 11, parameter SW = 52) ( //INPUTS input wire clk, //Clock Signal input wire rst, //Reset Signal input wire load_i, input wire sel_a_i, //Overflow/add/subt result's mux's selector input wire sel_b_i, //underflow/add/subt result's mux's selector input wire sign_i, //Sign of the largest Operand input wire [EW-1:0] exp_ieee_i, //Final Exponent input wire [SW-1:0] sgf_ieee_i,//Final Significand //OUTPUTS output wire [W-1:0] final_result_ieee_o //Final Result ); //Wire Connection signals wire [SW-1:0] Sgf_S_mux; wire [EW-1:0] Exp_S_mux; wire Sign_S_mux; wire [W-1:0] final_result_reg; wire overunder; wire [EW-1:0] exp_mux_D1; wire [SW-1:0] sgf_mux_D1; ////////////////////////////////////////////////////////// assign overunder = sel_a_i | sel_b_i; Mux_3x1 #(.W(1)) Sign_Mux ( .ctrl({sel_a_i,sel_b_i}), .D0(sign_i), .D1(1'b1), .D2(1'b0), .S(Sign_S_mux) ); Multiplexer_AC #(.W(EW)) Exp_Mux ( .ctrl(overunder), .D0(exp_ieee_i), .D1(exp_mux_D1), .S(Exp_S_mux) ); Multiplexer_AC #(.W(SW)) Sgf_Mux ( .ctrl(overunder), .D0(sgf_ieee_i), .D1(sgf_mux_D1), .S(Sgf_S_mux) ); ///////////////////////////////////////////////////////// generate if(W == 32) begin assign exp_mux_D1 =8'hff; assign sgf_mux_D1 =23'd0; end else begin assign exp_mux_D1 =11'hfff; assign sgf_mux_D1 =52'd0; end endgenerate //////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////// RegisterAdd #(.W(W)) Final_Result_IEEE ( .clk(clk), .rst(rst), .load(load_i), .D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}), .Q(final_result_ieee_o) ); endmodule
/////////////////////////////////////////////////////////////////////////////// // // File name: axi_protocol_converter_v2_1_b2s_cmd_translator.v // // Description: // INCR and WRAP burst modes are decoded in parallel and then the output is // chosen based on the AxBURST value. FIXED burst mode is not supported and // is mapped to the INCR command instead. // // Specifications: // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_b2s_cmd_translator # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of AxADDR // Range: 32. parameter integer C_AXI_ADDR_WIDTH = 32 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , input wire [C_AXI_ADDR_WIDTH-1:0] s_axaddr , input wire [7:0] s_axlen , input wire [2:0] s_axsize , input wire [1:0] s_axburst , input wire s_axhandshake , output wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr , output wire incr_burst , // Connections to/from fsm module // signal to increment to the next mc transaction input wire next , // signal to the fsm there is another transaction required output wire next_pending ); //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// // AXBURST decodes localparam P_AXBURST_FIXED = 2'b00; localparam P_AXBURST_INCR = 2'b01; localparam P_AXBURST_WRAP = 2'b10; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// wire [C_AXI_ADDR_WIDTH-1:0] incr_cmd_byte_addr; wire incr_next_pending; wire [C_AXI_ADDR_WIDTH-1:0] wrap_cmd_byte_addr; wire wrap_next_pending; reg sel_first; reg s_axburst_eq1; reg s_axburst_eq0; reg sel_first_i; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // INCR and WRAP translations are calcuated in independently, select the one // for our transactions // right shift by the UI width to the DRAM width ratio assign m_axaddr = (s_axburst == P_AXBURST_FIXED) ? s_axaddr : (s_axburst == P_AXBURST_INCR) ? incr_cmd_byte_addr : wrap_cmd_byte_addr; assign incr_burst = (s_axburst[1]) ? 1'b0 : 1'b1; // Indicates if we are on the first transaction of a mc translation with more // than 1 transaction. always @(posedge clk) begin if (reset | s_axhandshake) begin sel_first <= 1'b1; end else if (next) begin sel_first <= 1'b0; end end always @( * ) begin if (reset | s_axhandshake) begin sel_first_i = 1'b1; end else if (next) begin sel_first_i = 1'b0; end else begin sel_first_i = sel_first; end end assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0; always @(posedge clk) begin if (sel_first_i || s_axburst[1]) begin s_axburst_eq1 <= wrap_next_pending; end else begin s_axburst_eq1 <= incr_next_pending; end if (sel_first_i || !s_axburst[1]) begin s_axburst_eq0 <= incr_next_pending; end else begin s_axburst_eq0 <= wrap_next_pending; end end axi_protocol_converter_v2_1_b2s_incr_cmd #( .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH) ) incr_cmd_0 ( .clk ( clk ) , .reset ( reset ) , .axaddr ( s_axaddr ) , .axlen ( s_axlen ) , .axsize ( s_axsize ) , .axhandshake ( s_axhandshake ) , .cmd_byte_addr ( incr_cmd_byte_addr ) , .next ( next ) , .next_pending ( incr_next_pending ) ); axi_protocol_converter_v2_1_b2s_wrap_cmd #( .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH) ) wrap_cmd_0 ( .clk ( clk ) , .reset ( reset ) , .axaddr ( s_axaddr ) , .axlen ( s_axlen ) , .axsize ( s_axsize ) , .axhandshake ( s_axhandshake ) , .cmd_byte_addr ( wrap_cmd_byte_addr ) , .next ( next ) , .next_pending ( wrap_next_pending ) ); endmodule `default_nettype wire
`include "lo_read.v" /* pck0 - input main 24Mhz clock (PLL / 4) [7:0] adc_d - input data from A/D converter lo_is_125khz - input freq selector (1=125Khz, 0=136Khz) pwr_lo - output to coil drivers (ssp_clk / 8) adc_clk - output A/D clock signal ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted) ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first) ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) ) ck_1356meg - input unused ck_1356megb - input unused ssp_dout - input unused cross_hi - input unused cross_lo - input unused pwr_hi - output unused, tied low pwr_oe1 - output unused, undefined pwr_oe2 - output unused, undefined pwr_oe3 - output unused, undefined pwr_oe4 - output unused, undefined dbg - output alias for adc_clk */ module testbed_lo_read; reg pck0; reg [7:0] adc_d; reg lo_is_125khz; reg [15:0] divisor; wire pwr_lo; wire adc_clk; wire ck_1356meg; wire ck_1356megb; wire ssp_frame; wire ssp_din; wire ssp_clk; reg ssp_dout; wire pwr_hi; wire pwr_oe1; wire pwr_oe2; wire pwr_oe3; wire pwr_oe4; wire cross_lo; wire cross_hi; wire dbg; lo_read #(5,10) dut( .pck0(pck0), .ck_1356meg(ck_1356meg), .ck_1356megb(ck_1356megb), .pwr_lo(pwr_lo), .pwr_hi(pwr_hi), .pwr_oe1(pwr_oe1), .pwr_oe2(pwr_oe2), .pwr_oe3(pwr_oe3), .pwr_oe4(pwr_oe4), .adc_d(adc_d), .adc_clk(adc_clk), .ssp_frame(ssp_frame), .ssp_din(ssp_din), .ssp_dout(ssp_dout), .ssp_clk(ssp_clk), .cross_hi(cross_hi), .cross_lo(cross_lo), .dbg(dbg), .lo_is_125khz(lo_is_125khz), .divisor(divisor) ); integer idx, i, adc_val=8; // main clock always #5 pck0 = !pck0; task crank_dut; begin @(posedge adc_clk) ; adc_d = adc_val; adc_val = (adc_val *2) + 53; end endtask initial begin // init inputs pck0 = 0; adc_d = 0; ssp_dout = 0; lo_is_125khz = 1; divisor = 255; //min 16, 95=125Khz, max 255 // simulate 4 A/D cycles at 125Khz for (i = 0 ; i < 8 ; i = i + 1) begin crank_dut; end $finish; end endmodule // main
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module soc_design_niosII_core_cpu_debug_slave_tck ( // inputs: MonDReg, break_readreg, dbrk_hit0_latch, dbrk_hit1_latch, dbrk_hit2_latch, dbrk_hit3_latch, debugack, ir_in, jtag_state_rti, monitor_error, monitor_ready, reset_n, resetlatch, tck, tdi, tracemem_on, tracemem_trcdata, tracemem_tw, trc_im_addr, trc_on, trc_wrap, trigbrktype, trigger_state_1, vs_cdr, vs_sdr, vs_uir, // outputs: ir_out, jrst_n, sr, st_ready_test_idle, tdo ) ; output [ 1: 0] ir_out; output jrst_n; output [ 37: 0] sr; output st_ready_test_idle; output tdo; input [ 31: 0] MonDReg; input [ 31: 0] break_readreg; input dbrk_hit0_latch; input dbrk_hit1_latch; input dbrk_hit2_latch; input dbrk_hit3_latch; input debugack; input [ 1: 0] ir_in; input jtag_state_rti; input monitor_error; input monitor_ready; input reset_n; input resetlatch; input tck; input tdi; input tracemem_on; input [ 35: 0] tracemem_trcdata; input tracemem_tw; input [ 6: 0] trc_im_addr; input trc_on; input trc_wrap; input trigbrktype; input trigger_state_1; input vs_cdr; input vs_sdr; input vs_uir; reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; wire debugack_sync; reg [ 1: 0] ir_out; wire jrst_n; wire monitor_ready_sync; reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; wire st_ready_test_idle; wire tdo; wire unxcomplemented_resetxx1; wire unxcomplemented_resetxx2; always @(posedge tck) begin if (vs_cdr) case (ir_in) 2'b00: begin sr[35] <= debugack_sync; sr[34] <= monitor_error; sr[33] <= resetlatch; sr[32 : 1] <= MonDReg; sr[0] <= monitor_ready_sync; end // 2'b00 2'b01: begin sr[35 : 0] <= tracemem_trcdata; sr[37] <= tracemem_tw; sr[36] <= tracemem_on; end // 2'b01 2'b10: begin sr[37] <= trigger_state_1; sr[36] <= dbrk_hit3_latch; sr[35] <= dbrk_hit2_latch; sr[34] <= dbrk_hit1_latch; sr[33] <= dbrk_hit0_latch; sr[32 : 1] <= break_readreg; sr[0] <= trigbrktype; end // 2'b10 2'b11: begin sr[15 : 2] <= trc_im_addr; sr[1] <= trc_wrap; sr[0] <= trc_on; end // 2'b11 endcase // ir_in if (vs_sdr) case (DRsize) 3'b000: begin sr <= {tdi, sr[37 : 2], tdi}; end // 3'b000 3'b001: begin sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]}; end // 3'b001 3'b010: begin sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]}; end // 3'b010 3'b011: begin sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]}; end // 3'b011 3'b100: begin sr <= {tdi, sr[37], tdi, sr[35 : 1]}; end // 3'b100 3'b101: begin sr <= {tdi, sr[37 : 1]}; end // 3'b101 default: begin sr <= {tdi, sr[37 : 2], tdi}; end // default endcase // DRsize if (vs_uir) case (ir_in) 2'b00: begin DRsize <= 3'b100; end // 2'b00 2'b01: begin DRsize <= 3'b101; end // 2'b01 2'b10: begin DRsize <= 3'b101; end // 2'b10 2'b11: begin DRsize <= 3'b010; end // 2'b11 endcase // ir_in end assign tdo = sr[0]; assign st_ready_test_idle = jtag_state_rti; assign unxcomplemented_resetxx1 = jrst_n; altera_std_synchronizer the_altera_std_synchronizer1 ( .clk (tck), .din (debugack), .dout (debugack_sync), .reset_n (unxcomplemented_resetxx1) ); defparam the_altera_std_synchronizer1.depth = 2; assign unxcomplemented_resetxx2 = jrst_n; altera_std_synchronizer the_altera_std_synchronizer2 ( .clk (tck), .din (monitor_ready), .dout (monitor_ready_sync), .reset_n (unxcomplemented_resetxx2) ); defparam the_altera_std_synchronizer2.depth = 2; always @(posedge tck or negedge jrst_n) begin if (jrst_n == 0) ir_out <= 2'b0; else ir_out <= {debugack_sync, monitor_ready_sync}; end //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS assign jrst_n = reset_n; //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // assign jrst_n = 1; //synthesis read_comments_as_HDL off endmodule
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module soc_design_niosII_core_cpu_debug_slave_sysclk ( // inputs: clk, ir_in, sr, vs_udr, vs_uir, // outputs: jdo, take_action_break_a, take_action_break_b, take_action_break_c, take_action_ocimem_a, take_action_ocimem_b, take_action_tracectrl, take_no_action_break_a, take_no_action_break_b, take_no_action_break_c, take_no_action_ocimem_a ) ; output [ 37: 0] jdo; output take_action_break_a; output take_action_break_b; output take_action_break_c; output take_action_ocimem_a; output take_action_ocimem_b; output take_action_tracectrl; output take_no_action_break_a; output take_no_action_break_b; output take_no_action_break_c; output take_no_action_ocimem_a; input clk; input [ 1: 0] ir_in; input [ 37: 0] sr; input vs_udr; input vs_uir; reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; wire sync_udr; wire sync_uir; wire take_action_break_a; wire take_action_break_b; wire take_action_break_c; wire take_action_ocimem_a; wire take_action_ocimem_b; wire take_action_tracectrl; wire take_no_action_break_a; wire take_no_action_break_b; wire take_no_action_break_c; wire take_no_action_ocimem_a; wire unxunused_resetxx3; wire unxunused_resetxx4; reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; assign unxunused_resetxx3 = 1'b1; altera_std_synchronizer the_altera_std_synchronizer3 ( .clk (clk), .din (vs_udr), .dout (sync_udr), .reset_n (unxunused_resetxx3) ); defparam the_altera_std_synchronizer3.depth = 2; assign unxunused_resetxx4 = 1'b1; altera_std_synchronizer the_altera_std_synchronizer4 ( .clk (clk), .din (vs_uir), .dout (sync_uir), .reset_n (unxunused_resetxx4) ); defparam the_altera_std_synchronizer4.depth = 2; always @(posedge clk) begin sync2_udr <= sync_udr; update_jdo_strobe <= sync_udr & ~sync2_udr; enable_action_strobe <= update_jdo_strobe; sync2_uir <= sync_uir; jxuir <= sync_uir & ~sync2_uir; end assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && ~jdo[35] && jdo[34]; assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && ~jdo[35] && ~jdo[34]; assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && jdo[35]; assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && ~jdo[36] && jdo[37]; assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && ~jdo[36] && ~jdo[37]; assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && jdo[36] && ~jdo[35] && jdo[37]; assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && jdo[36] && ~jdo[35] && ~jdo[37]; assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && jdo[36] && jdo[35] && jdo[37]; assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && jdo[36] && jdo[35] && ~jdo[37]; assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) && jdo[15]; always @(posedge clk) begin if (jxuir) ir <= ir_in; if (update_jdo_strobe) jdo <= sr; end endmodule
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module soc_design_niosII_core_cpu_debug_slave_sysclk ( // inputs: clk, ir_in, sr, vs_udr, vs_uir, // outputs: jdo, take_action_break_a, take_action_break_b, take_action_break_c, take_action_ocimem_a, take_action_ocimem_b, take_action_tracectrl, take_no_action_break_a, take_no_action_break_b, take_no_action_break_c, take_no_action_ocimem_a ) ; output [ 37: 0] jdo; output take_action_break_a; output take_action_break_b; output take_action_break_c; output take_action_ocimem_a; output take_action_ocimem_b; output take_action_tracectrl; output take_no_action_break_a; output take_no_action_break_b; output take_no_action_break_c; output take_no_action_ocimem_a; input clk; input [ 1: 0] ir_in; input [ 37: 0] sr; input vs_udr; input vs_uir; reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; wire sync_udr; wire sync_uir; wire take_action_break_a; wire take_action_break_b; wire take_action_break_c; wire take_action_ocimem_a; wire take_action_ocimem_b; wire take_action_tracectrl; wire take_no_action_break_a; wire take_no_action_break_b; wire take_no_action_break_c; wire take_no_action_ocimem_a; wire unxunused_resetxx3; wire unxunused_resetxx4; reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; assign unxunused_resetxx3 = 1'b1; altera_std_synchronizer the_altera_std_synchronizer3 ( .clk (clk), .din (vs_udr), .dout (sync_udr), .reset_n (unxunused_resetxx3) ); defparam the_altera_std_synchronizer3.depth = 2; assign unxunused_resetxx4 = 1'b1; altera_std_synchronizer the_altera_std_synchronizer4 ( .clk (clk), .din (vs_uir), .dout (sync_uir), .reset_n (unxunused_resetxx4) ); defparam the_altera_std_synchronizer4.depth = 2; always @(posedge clk) begin sync2_udr <= sync_udr; update_jdo_strobe <= sync_udr & ~sync2_udr; enable_action_strobe <= update_jdo_strobe; sync2_uir <= sync_uir; jxuir <= sync_uir & ~sync2_uir; end assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && ~jdo[35] && jdo[34]; assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && ~jdo[35] && ~jdo[34]; assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && jdo[35]; assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && ~jdo[36] && jdo[37]; assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && ~jdo[36] && ~jdo[37]; assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && jdo[36] && ~jdo[35] && jdo[37]; assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && jdo[36] && ~jdo[35] && ~jdo[37]; assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && jdo[36] && jdo[35] && jdo[37]; assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && jdo[36] && jdo[35] && ~jdo[37]; assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) && jdo[15]; always @(posedge clk) begin if (jxuir) ir <= ir_in; if (update_jdo_strobe) jdo <= sr; end endmodule
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module soc_design_niosII_core_cpu_debug_slave_sysclk ( // inputs: clk, ir_in, sr, vs_udr, vs_uir, // outputs: jdo, take_action_break_a, take_action_break_b, take_action_break_c, take_action_ocimem_a, take_action_ocimem_b, take_action_tracectrl, take_no_action_break_a, take_no_action_break_b, take_no_action_break_c, take_no_action_ocimem_a ) ; output [ 37: 0] jdo; output take_action_break_a; output take_action_break_b; output take_action_break_c; output take_action_ocimem_a; output take_action_ocimem_b; output take_action_tracectrl; output take_no_action_break_a; output take_no_action_break_b; output take_no_action_break_c; output take_no_action_ocimem_a; input clk; input [ 1: 0] ir_in; input [ 37: 0] sr; input vs_udr; input vs_uir; reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; wire sync_udr; wire sync_uir; wire take_action_break_a; wire take_action_break_b; wire take_action_break_c; wire take_action_ocimem_a; wire take_action_ocimem_b; wire take_action_tracectrl; wire take_no_action_break_a; wire take_no_action_break_b; wire take_no_action_break_c; wire take_no_action_ocimem_a; wire unxunused_resetxx3; wire unxunused_resetxx4; reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; assign unxunused_resetxx3 = 1'b1; altera_std_synchronizer the_altera_std_synchronizer3 ( .clk (clk), .din (vs_udr), .dout (sync_udr), .reset_n (unxunused_resetxx3) ); defparam the_altera_std_synchronizer3.depth = 2; assign unxunused_resetxx4 = 1'b1; altera_std_synchronizer the_altera_std_synchronizer4 ( .clk (clk), .din (vs_uir), .dout (sync_uir), .reset_n (unxunused_resetxx4) ); defparam the_altera_std_synchronizer4.depth = 2; always @(posedge clk) begin sync2_udr <= sync_udr; update_jdo_strobe <= sync_udr & ~sync2_udr; enable_action_strobe <= update_jdo_strobe; sync2_uir <= sync_uir; jxuir <= sync_uir & ~sync2_uir; end assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && ~jdo[35] && jdo[34]; assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && ~jdo[35] && ~jdo[34]; assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && jdo[35]; assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && ~jdo[36] && jdo[37]; assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && ~jdo[36] && ~jdo[37]; assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && jdo[36] && ~jdo[35] && jdo[37]; assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && jdo[36] && ~jdo[35] && ~jdo[37]; assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && jdo[36] && jdo[35] && jdo[37]; assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && jdo[36] && jdo[35] && ~jdo[37]; assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) && jdo[15]; always @(posedge clk) begin if (jxuir) ir <= ir_in; if (update_jdo_strobe) jdo <= sr; end endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Write Response Channel for ATC // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // b_atc // //-------------------------------------------------------------------------- `timescale 1ps/1ps module processing_system7_v5_5_b_atc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6, spartan6 or later. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of checker. // Range: >= 1. parameter integer C_AXI_BUSER_WIDTH = 1, // Width of AWUSER signals. // Range: >= 1. parameter integer C_FIFO_DEPTH_LOG = 4 ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface input wire cmd_b_push, input wire cmd_b_error, input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id, output wire cmd_b_ready, output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, output reg cmd_b_full, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, output reg [2-1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, // Master Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, input wire [2-1:0] M_AXI_BRESP, input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire M_AXI_BVALID, output wire M_AXI_BREADY, // Trigger detection output reg ERROR_TRIGGER, output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for packing levels. localparam [2-1:0] C_RESP_OKAY = 2'b00; localparam [2-1:0] C_RESP_EXOKAY = 2'b01; localparam [2-1:0] C_RESP_SLVERROR = 2'b10; localparam [2-1:0] C_RESP_DECERR = 2'b11; // Command FIFO settings localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// integer index; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Command Queue. reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; reg cmd_b_valid; wire cmd_b_ready_i; wire inject_error; wire [C_AXI_ID_WIDTH-1:0] current_id; // Search command. wire found_match; wire use_match; wire matching_id; // Manage valid command. wire write_valid_cmd; reg [C_FIFO_DEPTH-2:0] valid_cmd; reg [C_FIFO_DEPTH-2:0] updated_valid_cmd; reg [C_FIFO_DEPTH-2:0] next_valid_cmd; reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr; reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr; // Pipelined data reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I; reg [2-1:0] M_AXI_BRESP_I; reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I; reg M_AXI_BVALID_I; wire M_AXI_BREADY_I; ///////////////////////////////////////////////////////////////////////////// // Command Queue: // // Keep track of depth of Queue to generate full flag. // // Also generate valid to mark pressence of commands in Queue. // // Maintain Queue and extract data from currently searched entry. // ///////////////////////////////////////////////////////////////////////////// // SRL FIFO Pointer. always @ (posedge ACLK) begin if (ARESET) begin addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_b_push & ~cmd_b_ready_i ) begin // Pushing data increase length/addr. addr_ptr <= addr_ptr + 1; end else if ( cmd_b_ready_i ) begin // Collapse addr when data is popped. addr_ptr <= collapsed_addr_ptr; end end end // FIFO Flags. always @ (posedge ACLK) begin if (ARESET) begin cmd_b_full <= 1'b0; cmd_b_valid <= 1'b0; end else begin if ( cmd_b_push & ~cmd_b_ready_i ) begin cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 ); cmd_b_valid <= 1'b1; end else if ( ~cmd_b_push & cmd_b_ready_i ) begin cmd_b_full <= 1'b0; cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 ); end end end // Infere SRL for storage. always @ (posedge ACLK) begin if ( cmd_b_push ) begin for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= {cmd_b_error, cmd_b_id}; end end // Get current transaction info. assign {inject_error, current_id} = data_srl[search_addr_ptr]; // Assign outputs. assign cmd_b_addr = collapsed_addr_ptr; ///////////////////////////////////////////////////////////////////////////// // Search Command Queue: // // Search for matching valid command in queue. // // A command is found when an valid entry with correct ID is found. The queue // is search from the oldest entry, i.e. from a high value. // When new commands are pushed the search address has to be updated to always // start the search from the oldest available. // ///////////////////////////////////////////////////////////////////////////// // Handle search addr. always @ (posedge ACLK) begin if (ARESET) begin search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_b_ready_i ) begin // Collapse addr when data is popped. search_addr_ptr <= collapsed_addr_ptr; end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin // Skip non valid command. search_addr_ptr <= search_addr_ptr - 1; end else if ( cmd_b_push ) begin search_addr_ptr <= search_addr_ptr + 1; end end end // Check if searched command is valid and match ID (for existing response on MI side). assign matching_id = ( M_AXI_BID_I == current_id ); assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I; assign use_match = found_match & S_AXI_BREADY; ///////////////////////////////////////////////////////////////////////////// // Track Used Commands: // // Actions that affect Valid Command: // * When a new command is pushed // => Shift valid vector one step // * When a command is used // => Clear corresponding valid bit // ///////////////////////////////////////////////////////////////////////////// // Valid command status is updated when a command is used or a new one is pushed. assign write_valid_cmd = cmd_b_push | cmd_b_ready_i; // Update the used command valid bit. always @ * begin updated_valid_cmd = valid_cmd; updated_valid_cmd[search_addr_ptr] = ~use_match; end // Shift valid vector when command is pushed. always @ * begin if ( cmd_b_push ) begin next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1}; end else begin next_valid_cmd = updated_valid_cmd; end end // Valid signals for next cycle. always @ (posedge ACLK) begin if (ARESET) begin valid_cmd <= {C_FIFO_WIDTH{1'b0}}; end else if ( write_valid_cmd ) begin valid_cmd <= next_valid_cmd; end end // Detect oldest available command in Queue. always @ * begin // Default to empty. collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}}; for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin if ( next_valid_cmd[index] ) begin collapsed_addr_ptr = index; end end end ///////////////////////////////////////////////////////////////////////////// // Pipe incoming data: // // The B channel is piped to improve timing and avoid impact in search // mechanism due to late arriving signals. // ///////////////////////////////////////////////////////////////////////////// // Clock data. always @ (posedge ACLK) begin if (ARESET) begin M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}}; M_AXI_BRESP_I <= 2'b00; M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}}; M_AXI_BVALID_I <= 1'b0; end else begin if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin M_AXI_BVALID_I <= 1'b0; end if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin M_AXI_BID_I <= M_AXI_BID; M_AXI_BRESP_I <= M_AXI_BRESP; M_AXI_BUSER_I <= M_AXI_BUSER; M_AXI_BVALID_I <= 1'b1; end end end // Generate ready to get new transaction. assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I; ///////////////////////////////////////////////////////////////////////////// // Inject Error: // // BRESP is modified according to command information. // ///////////////////////////////////////////////////////////////////////////// // Inject error in response. always @ * begin if ( inject_error ) begin S_AXI_BRESP = C_RESP_SLVERROR; end else begin S_AXI_BRESP = M_AXI_BRESP_I; end end // Handle interrupt generation. always @ (posedge ACLK) begin if (ARESET) begin ERROR_TRIGGER <= 1'b0; ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}}; end else begin if ( inject_error & cmd_b_ready_i ) begin ERROR_TRIGGER <= 1'b1; ERROR_TRANSACTION_ID <= M_AXI_BID_I; end else begin ERROR_TRIGGER <= 1'b0; end end end ///////////////////////////////////////////////////////////////////////////// // Transaction Throttling: // // Response is passed forward when a matching entry has been found in queue. // Both ready and valid are set when the command is completed. // ///////////////////////////////////////////////////////////////////////////// // Propagate masked valid. assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match; // Return ready with push back. assign M_AXI_BREADY_I = cmd_b_valid & use_match; // Command has been handled. assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match; assign cmd_b_ready = cmd_b_ready_i; ///////////////////////////////////////////////////////////////////////////// // Write Response Propagation: // // All information is simply forwarded on from MI- to SI-Side untouched. // ///////////////////////////////////////////////////////////////////////////// // 1:1 mapping. assign S_AXI_BID = M_AXI_BID_I; assign S_AXI_BUSER = M_AXI_BUSER_I; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Write Response Channel for ATC // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // b_atc // //-------------------------------------------------------------------------- `timescale 1ps/1ps module processing_system7_v5_5_b_atc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6, spartan6 or later. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of checker. // Range: >= 1. parameter integer C_AXI_BUSER_WIDTH = 1, // Width of AWUSER signals. // Range: >= 1. parameter integer C_FIFO_DEPTH_LOG = 4 ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface input wire cmd_b_push, input wire cmd_b_error, input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id, output wire cmd_b_ready, output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, output reg cmd_b_full, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, output reg [2-1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, // Master Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, input wire [2-1:0] M_AXI_BRESP, input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire M_AXI_BVALID, output wire M_AXI_BREADY, // Trigger detection output reg ERROR_TRIGGER, output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for packing levels. localparam [2-1:0] C_RESP_OKAY = 2'b00; localparam [2-1:0] C_RESP_EXOKAY = 2'b01; localparam [2-1:0] C_RESP_SLVERROR = 2'b10; localparam [2-1:0] C_RESP_DECERR = 2'b11; // Command FIFO settings localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// integer index; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Command Queue. reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; reg cmd_b_valid; wire cmd_b_ready_i; wire inject_error; wire [C_AXI_ID_WIDTH-1:0] current_id; // Search command. wire found_match; wire use_match; wire matching_id; // Manage valid command. wire write_valid_cmd; reg [C_FIFO_DEPTH-2:0] valid_cmd; reg [C_FIFO_DEPTH-2:0] updated_valid_cmd; reg [C_FIFO_DEPTH-2:0] next_valid_cmd; reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr; reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr; // Pipelined data reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I; reg [2-1:0] M_AXI_BRESP_I; reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I; reg M_AXI_BVALID_I; wire M_AXI_BREADY_I; ///////////////////////////////////////////////////////////////////////////// // Command Queue: // // Keep track of depth of Queue to generate full flag. // // Also generate valid to mark pressence of commands in Queue. // // Maintain Queue and extract data from currently searched entry. // ///////////////////////////////////////////////////////////////////////////// // SRL FIFO Pointer. always @ (posedge ACLK) begin if (ARESET) begin addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_b_push & ~cmd_b_ready_i ) begin // Pushing data increase length/addr. addr_ptr <= addr_ptr + 1; end else if ( cmd_b_ready_i ) begin // Collapse addr when data is popped. addr_ptr <= collapsed_addr_ptr; end end end // FIFO Flags. always @ (posedge ACLK) begin if (ARESET) begin cmd_b_full <= 1'b0; cmd_b_valid <= 1'b0; end else begin if ( cmd_b_push & ~cmd_b_ready_i ) begin cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 ); cmd_b_valid <= 1'b1; end else if ( ~cmd_b_push & cmd_b_ready_i ) begin cmd_b_full <= 1'b0; cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 ); end end end // Infere SRL for storage. always @ (posedge ACLK) begin if ( cmd_b_push ) begin for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= {cmd_b_error, cmd_b_id}; end end // Get current transaction info. assign {inject_error, current_id} = data_srl[search_addr_ptr]; // Assign outputs. assign cmd_b_addr = collapsed_addr_ptr; ///////////////////////////////////////////////////////////////////////////// // Search Command Queue: // // Search for matching valid command in queue. // // A command is found when an valid entry with correct ID is found. The queue // is search from the oldest entry, i.e. from a high value. // When new commands are pushed the search address has to be updated to always // start the search from the oldest available. // ///////////////////////////////////////////////////////////////////////////// // Handle search addr. always @ (posedge ACLK) begin if (ARESET) begin search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_b_ready_i ) begin // Collapse addr when data is popped. search_addr_ptr <= collapsed_addr_ptr; end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin // Skip non valid command. search_addr_ptr <= search_addr_ptr - 1; end else if ( cmd_b_push ) begin search_addr_ptr <= search_addr_ptr + 1; end end end // Check if searched command is valid and match ID (for existing response on MI side). assign matching_id = ( M_AXI_BID_I == current_id ); assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I; assign use_match = found_match & S_AXI_BREADY; ///////////////////////////////////////////////////////////////////////////// // Track Used Commands: // // Actions that affect Valid Command: // * When a new command is pushed // => Shift valid vector one step // * When a command is used // => Clear corresponding valid bit // ///////////////////////////////////////////////////////////////////////////// // Valid command status is updated when a command is used or a new one is pushed. assign write_valid_cmd = cmd_b_push | cmd_b_ready_i; // Update the used command valid bit. always @ * begin updated_valid_cmd = valid_cmd; updated_valid_cmd[search_addr_ptr] = ~use_match; end // Shift valid vector when command is pushed. always @ * begin if ( cmd_b_push ) begin next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1}; end else begin next_valid_cmd = updated_valid_cmd; end end // Valid signals for next cycle. always @ (posedge ACLK) begin if (ARESET) begin valid_cmd <= {C_FIFO_WIDTH{1'b0}}; end else if ( write_valid_cmd ) begin valid_cmd <= next_valid_cmd; end end // Detect oldest available command in Queue. always @ * begin // Default to empty. collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}}; for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin if ( next_valid_cmd[index] ) begin collapsed_addr_ptr = index; end end end ///////////////////////////////////////////////////////////////////////////// // Pipe incoming data: // // The B channel is piped to improve timing and avoid impact in search // mechanism due to late arriving signals. // ///////////////////////////////////////////////////////////////////////////// // Clock data. always @ (posedge ACLK) begin if (ARESET) begin M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}}; M_AXI_BRESP_I <= 2'b00; M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}}; M_AXI_BVALID_I <= 1'b0; end else begin if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin M_AXI_BVALID_I <= 1'b0; end if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin M_AXI_BID_I <= M_AXI_BID; M_AXI_BRESP_I <= M_AXI_BRESP; M_AXI_BUSER_I <= M_AXI_BUSER; M_AXI_BVALID_I <= 1'b1; end end end // Generate ready to get new transaction. assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I; ///////////////////////////////////////////////////////////////////////////// // Inject Error: // // BRESP is modified according to command information. // ///////////////////////////////////////////////////////////////////////////// // Inject error in response. always @ * begin if ( inject_error ) begin S_AXI_BRESP = C_RESP_SLVERROR; end else begin S_AXI_BRESP = M_AXI_BRESP_I; end end // Handle interrupt generation. always @ (posedge ACLK) begin if (ARESET) begin ERROR_TRIGGER <= 1'b0; ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}}; end else begin if ( inject_error & cmd_b_ready_i ) begin ERROR_TRIGGER <= 1'b1; ERROR_TRANSACTION_ID <= M_AXI_BID_I; end else begin ERROR_TRIGGER <= 1'b0; end end end ///////////////////////////////////////////////////////////////////////////// // Transaction Throttling: // // Response is passed forward when a matching entry has been found in queue. // Both ready and valid are set when the command is completed. // ///////////////////////////////////////////////////////////////////////////// // Propagate masked valid. assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match; // Return ready with push back. assign M_AXI_BREADY_I = cmd_b_valid & use_match; // Command has been handled. assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match; assign cmd_b_ready = cmd_b_ready_i; ///////////////////////////////////////////////////////////////////////////// // Write Response Propagation: // // All information is simply forwarded on from MI- to SI-Side untouched. // ///////////////////////////////////////////////////////////////////////////// // 1:1 mapping. assign S_AXI_BID = M_AXI_BID_I; assign S_AXI_BUSER = M_AXI_BUSER_I; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Write Response Channel for ATC // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // b_atc // //-------------------------------------------------------------------------- `timescale 1ps/1ps module processing_system7_v5_5_b_atc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6, spartan6 or later. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of checker. // Range: >= 1. parameter integer C_AXI_BUSER_WIDTH = 1, // Width of AWUSER signals. // Range: >= 1. parameter integer C_FIFO_DEPTH_LOG = 4 ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface input wire cmd_b_push, input wire cmd_b_error, input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id, output wire cmd_b_ready, output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, output reg cmd_b_full, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, output reg [2-1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, // Master Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, input wire [2-1:0] M_AXI_BRESP, input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire M_AXI_BVALID, output wire M_AXI_BREADY, // Trigger detection output reg ERROR_TRIGGER, output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for packing levels. localparam [2-1:0] C_RESP_OKAY = 2'b00; localparam [2-1:0] C_RESP_EXOKAY = 2'b01; localparam [2-1:0] C_RESP_SLVERROR = 2'b10; localparam [2-1:0] C_RESP_DECERR = 2'b11; // Command FIFO settings localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// integer index; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Command Queue. reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; reg cmd_b_valid; wire cmd_b_ready_i; wire inject_error; wire [C_AXI_ID_WIDTH-1:0] current_id; // Search command. wire found_match; wire use_match; wire matching_id; // Manage valid command. wire write_valid_cmd; reg [C_FIFO_DEPTH-2:0] valid_cmd; reg [C_FIFO_DEPTH-2:0] updated_valid_cmd; reg [C_FIFO_DEPTH-2:0] next_valid_cmd; reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr; reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr; // Pipelined data reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I; reg [2-1:0] M_AXI_BRESP_I; reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I; reg M_AXI_BVALID_I; wire M_AXI_BREADY_I; ///////////////////////////////////////////////////////////////////////////// // Command Queue: // // Keep track of depth of Queue to generate full flag. // // Also generate valid to mark pressence of commands in Queue. // // Maintain Queue and extract data from currently searched entry. // ///////////////////////////////////////////////////////////////////////////// // SRL FIFO Pointer. always @ (posedge ACLK) begin if (ARESET) begin addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_b_push & ~cmd_b_ready_i ) begin // Pushing data increase length/addr. addr_ptr <= addr_ptr + 1; end else if ( cmd_b_ready_i ) begin // Collapse addr when data is popped. addr_ptr <= collapsed_addr_ptr; end end end // FIFO Flags. always @ (posedge ACLK) begin if (ARESET) begin cmd_b_full <= 1'b0; cmd_b_valid <= 1'b0; end else begin if ( cmd_b_push & ~cmd_b_ready_i ) begin cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 ); cmd_b_valid <= 1'b1; end else if ( ~cmd_b_push & cmd_b_ready_i ) begin cmd_b_full <= 1'b0; cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 ); end end end // Infere SRL for storage. always @ (posedge ACLK) begin if ( cmd_b_push ) begin for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= {cmd_b_error, cmd_b_id}; end end // Get current transaction info. assign {inject_error, current_id} = data_srl[search_addr_ptr]; // Assign outputs. assign cmd_b_addr = collapsed_addr_ptr; ///////////////////////////////////////////////////////////////////////////// // Search Command Queue: // // Search for matching valid command in queue. // // A command is found when an valid entry with correct ID is found. The queue // is search from the oldest entry, i.e. from a high value. // When new commands are pushed the search address has to be updated to always // start the search from the oldest available. // ///////////////////////////////////////////////////////////////////////////// // Handle search addr. always @ (posedge ACLK) begin if (ARESET) begin search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_b_ready_i ) begin // Collapse addr when data is popped. search_addr_ptr <= collapsed_addr_ptr; end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin // Skip non valid command. search_addr_ptr <= search_addr_ptr - 1; end else if ( cmd_b_push ) begin search_addr_ptr <= search_addr_ptr + 1; end end end // Check if searched command is valid and match ID (for existing response on MI side). assign matching_id = ( M_AXI_BID_I == current_id ); assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I; assign use_match = found_match & S_AXI_BREADY; ///////////////////////////////////////////////////////////////////////////// // Track Used Commands: // // Actions that affect Valid Command: // * When a new command is pushed // => Shift valid vector one step // * When a command is used // => Clear corresponding valid bit // ///////////////////////////////////////////////////////////////////////////// // Valid command status is updated when a command is used or a new one is pushed. assign write_valid_cmd = cmd_b_push | cmd_b_ready_i; // Update the used command valid bit. always @ * begin updated_valid_cmd = valid_cmd; updated_valid_cmd[search_addr_ptr] = ~use_match; end // Shift valid vector when command is pushed. always @ * begin if ( cmd_b_push ) begin next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1}; end else begin next_valid_cmd = updated_valid_cmd; end end // Valid signals for next cycle. always @ (posedge ACLK) begin if (ARESET) begin valid_cmd <= {C_FIFO_WIDTH{1'b0}}; end else if ( write_valid_cmd ) begin valid_cmd <= next_valid_cmd; end end // Detect oldest available command in Queue. always @ * begin // Default to empty. collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}}; for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin if ( next_valid_cmd[index] ) begin collapsed_addr_ptr = index; end end end ///////////////////////////////////////////////////////////////////////////// // Pipe incoming data: // // The B channel is piped to improve timing and avoid impact in search // mechanism due to late arriving signals. // ///////////////////////////////////////////////////////////////////////////// // Clock data. always @ (posedge ACLK) begin if (ARESET) begin M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}}; M_AXI_BRESP_I <= 2'b00; M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}}; M_AXI_BVALID_I <= 1'b0; end else begin if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin M_AXI_BVALID_I <= 1'b0; end if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin M_AXI_BID_I <= M_AXI_BID; M_AXI_BRESP_I <= M_AXI_BRESP; M_AXI_BUSER_I <= M_AXI_BUSER; M_AXI_BVALID_I <= 1'b1; end end end // Generate ready to get new transaction. assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I; ///////////////////////////////////////////////////////////////////////////// // Inject Error: // // BRESP is modified according to command information. // ///////////////////////////////////////////////////////////////////////////// // Inject error in response. always @ * begin if ( inject_error ) begin S_AXI_BRESP = C_RESP_SLVERROR; end else begin S_AXI_BRESP = M_AXI_BRESP_I; end end // Handle interrupt generation. always @ (posedge ACLK) begin if (ARESET) begin ERROR_TRIGGER <= 1'b0; ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}}; end else begin if ( inject_error & cmd_b_ready_i ) begin ERROR_TRIGGER <= 1'b1; ERROR_TRANSACTION_ID <= M_AXI_BID_I; end else begin ERROR_TRIGGER <= 1'b0; end end end ///////////////////////////////////////////////////////////////////////////// // Transaction Throttling: // // Response is passed forward when a matching entry has been found in queue. // Both ready and valid are set when the command is completed. // ///////////////////////////////////////////////////////////////////////////// // Propagate masked valid. assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match; // Return ready with push back. assign M_AXI_BREADY_I = cmd_b_valid & use_match; // Command has been handled. assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match; assign cmd_b_ready = cmd_b_ready_i; ///////////////////////////////////////////////////////////////////////////// // Write Response Propagation: // // All information is simply forwarded on from MI- to SI-Side untouched. // ///////////////////////////////////////////////////////////////////////////// // 1:1 mapping. assign S_AXI_BID = M_AXI_BID_I; assign S_AXI_BUSER = M_AXI_BUSER_I; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Write Response Channel for ATC // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // b_atc // //-------------------------------------------------------------------------- `timescale 1ps/1ps module processing_system7_v5_5_b_atc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6, spartan6 or later. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of checker. // Range: >= 1. parameter integer C_AXI_BUSER_WIDTH = 1, // Width of AWUSER signals. // Range: >= 1. parameter integer C_FIFO_DEPTH_LOG = 4 ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface input wire cmd_b_push, input wire cmd_b_error, input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id, output wire cmd_b_ready, output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, output reg cmd_b_full, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, output reg [2-1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, // Master Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, input wire [2-1:0] M_AXI_BRESP, input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire M_AXI_BVALID, output wire M_AXI_BREADY, // Trigger detection output reg ERROR_TRIGGER, output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for packing levels. localparam [2-1:0] C_RESP_OKAY = 2'b00; localparam [2-1:0] C_RESP_EXOKAY = 2'b01; localparam [2-1:0] C_RESP_SLVERROR = 2'b10; localparam [2-1:0] C_RESP_DECERR = 2'b11; // Command FIFO settings localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// integer index; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Command Queue. reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; reg cmd_b_valid; wire cmd_b_ready_i; wire inject_error; wire [C_AXI_ID_WIDTH-1:0] current_id; // Search command. wire found_match; wire use_match; wire matching_id; // Manage valid command. wire write_valid_cmd; reg [C_FIFO_DEPTH-2:0] valid_cmd; reg [C_FIFO_DEPTH-2:0] updated_valid_cmd; reg [C_FIFO_DEPTH-2:0] next_valid_cmd; reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr; reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr; // Pipelined data reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I; reg [2-1:0] M_AXI_BRESP_I; reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I; reg M_AXI_BVALID_I; wire M_AXI_BREADY_I; ///////////////////////////////////////////////////////////////////////////// // Command Queue: // // Keep track of depth of Queue to generate full flag. // // Also generate valid to mark pressence of commands in Queue. // // Maintain Queue and extract data from currently searched entry. // ///////////////////////////////////////////////////////////////////////////// // SRL FIFO Pointer. always @ (posedge ACLK) begin if (ARESET) begin addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_b_push & ~cmd_b_ready_i ) begin // Pushing data increase length/addr. addr_ptr <= addr_ptr + 1; end else if ( cmd_b_ready_i ) begin // Collapse addr when data is popped. addr_ptr <= collapsed_addr_ptr; end end end // FIFO Flags. always @ (posedge ACLK) begin if (ARESET) begin cmd_b_full <= 1'b0; cmd_b_valid <= 1'b0; end else begin if ( cmd_b_push & ~cmd_b_ready_i ) begin cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 ); cmd_b_valid <= 1'b1; end else if ( ~cmd_b_push & cmd_b_ready_i ) begin cmd_b_full <= 1'b0; cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 ); end end end // Infere SRL for storage. always @ (posedge ACLK) begin if ( cmd_b_push ) begin for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= {cmd_b_error, cmd_b_id}; end end // Get current transaction info. assign {inject_error, current_id} = data_srl[search_addr_ptr]; // Assign outputs. assign cmd_b_addr = collapsed_addr_ptr; ///////////////////////////////////////////////////////////////////////////// // Search Command Queue: // // Search for matching valid command in queue. // // A command is found when an valid entry with correct ID is found. The queue // is search from the oldest entry, i.e. from a high value. // When new commands are pushed the search address has to be updated to always // start the search from the oldest available. // ///////////////////////////////////////////////////////////////////////////// // Handle search addr. always @ (posedge ACLK) begin if (ARESET) begin search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_b_ready_i ) begin // Collapse addr when data is popped. search_addr_ptr <= collapsed_addr_ptr; end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin // Skip non valid command. search_addr_ptr <= search_addr_ptr - 1; end else if ( cmd_b_push ) begin search_addr_ptr <= search_addr_ptr + 1; end end end // Check if searched command is valid and match ID (for existing response on MI side). assign matching_id = ( M_AXI_BID_I == current_id ); assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I; assign use_match = found_match & S_AXI_BREADY; ///////////////////////////////////////////////////////////////////////////// // Track Used Commands: // // Actions that affect Valid Command: // * When a new command is pushed // => Shift valid vector one step // * When a command is used // => Clear corresponding valid bit // ///////////////////////////////////////////////////////////////////////////// // Valid command status is updated when a command is used or a new one is pushed. assign write_valid_cmd = cmd_b_push | cmd_b_ready_i; // Update the used command valid bit. always @ * begin updated_valid_cmd = valid_cmd; updated_valid_cmd[search_addr_ptr] = ~use_match; end // Shift valid vector when command is pushed. always @ * begin if ( cmd_b_push ) begin next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1}; end else begin next_valid_cmd = updated_valid_cmd; end end // Valid signals for next cycle. always @ (posedge ACLK) begin if (ARESET) begin valid_cmd <= {C_FIFO_WIDTH{1'b0}}; end else if ( write_valid_cmd ) begin valid_cmd <= next_valid_cmd; end end // Detect oldest available command in Queue. always @ * begin // Default to empty. collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}}; for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin if ( next_valid_cmd[index] ) begin collapsed_addr_ptr = index; end end end ///////////////////////////////////////////////////////////////////////////// // Pipe incoming data: // // The B channel is piped to improve timing and avoid impact in search // mechanism due to late arriving signals. // ///////////////////////////////////////////////////////////////////////////// // Clock data. always @ (posedge ACLK) begin if (ARESET) begin M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}}; M_AXI_BRESP_I <= 2'b00; M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}}; M_AXI_BVALID_I <= 1'b0; end else begin if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin M_AXI_BVALID_I <= 1'b0; end if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin M_AXI_BID_I <= M_AXI_BID; M_AXI_BRESP_I <= M_AXI_BRESP; M_AXI_BUSER_I <= M_AXI_BUSER; M_AXI_BVALID_I <= 1'b1; end end end // Generate ready to get new transaction. assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I; ///////////////////////////////////////////////////////////////////////////// // Inject Error: // // BRESP is modified according to command information. // ///////////////////////////////////////////////////////////////////////////// // Inject error in response. always @ * begin if ( inject_error ) begin S_AXI_BRESP = C_RESP_SLVERROR; end else begin S_AXI_BRESP = M_AXI_BRESP_I; end end // Handle interrupt generation. always @ (posedge ACLK) begin if (ARESET) begin ERROR_TRIGGER <= 1'b0; ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}}; end else begin if ( inject_error & cmd_b_ready_i ) begin ERROR_TRIGGER <= 1'b1; ERROR_TRANSACTION_ID <= M_AXI_BID_I; end else begin ERROR_TRIGGER <= 1'b0; end end end ///////////////////////////////////////////////////////////////////////////// // Transaction Throttling: // // Response is passed forward when a matching entry has been found in queue. // Both ready and valid are set when the command is completed. // ///////////////////////////////////////////////////////////////////////////// // Propagate masked valid. assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match; // Return ready with push back. assign M_AXI_BREADY_I = cmd_b_valid & use_match; // Command has been handled. assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match; assign cmd_b_ready = cmd_b_ready_i; ///////////////////////////////////////////////////////////////////////////// // Write Response Propagation: // // All information is simply forwarded on from MI- to SI-Side untouched. // ///////////////////////////////////////////////////////////////////////////// // 1:1 mapping. assign S_AXI_BID = M_AXI_BID_I; assign S_AXI_BUSER = M_AXI_BUSER_I; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Write Response Channel for ATC // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // b_atc // //-------------------------------------------------------------------------- `timescale 1ps/1ps module processing_system7_v5_5_b_atc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6, spartan6 or later. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of checker. // Range: >= 1. parameter integer C_AXI_BUSER_WIDTH = 1, // Width of AWUSER signals. // Range: >= 1. parameter integer C_FIFO_DEPTH_LOG = 4 ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface input wire cmd_b_push, input wire cmd_b_error, input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id, output wire cmd_b_ready, output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, output reg cmd_b_full, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, output reg [2-1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, // Master Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, input wire [2-1:0] M_AXI_BRESP, input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire M_AXI_BVALID, output wire M_AXI_BREADY, // Trigger detection output reg ERROR_TRIGGER, output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for packing levels. localparam [2-1:0] C_RESP_OKAY = 2'b00; localparam [2-1:0] C_RESP_EXOKAY = 2'b01; localparam [2-1:0] C_RESP_SLVERROR = 2'b10; localparam [2-1:0] C_RESP_DECERR = 2'b11; // Command FIFO settings localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// integer index; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Command Queue. reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; reg cmd_b_valid; wire cmd_b_ready_i; wire inject_error; wire [C_AXI_ID_WIDTH-1:0] current_id; // Search command. wire found_match; wire use_match; wire matching_id; // Manage valid command. wire write_valid_cmd; reg [C_FIFO_DEPTH-2:0] valid_cmd; reg [C_FIFO_DEPTH-2:0] updated_valid_cmd; reg [C_FIFO_DEPTH-2:0] next_valid_cmd; reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr; reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr; // Pipelined data reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I; reg [2-1:0] M_AXI_BRESP_I; reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I; reg M_AXI_BVALID_I; wire M_AXI_BREADY_I; ///////////////////////////////////////////////////////////////////////////// // Command Queue: // // Keep track of depth of Queue to generate full flag. // // Also generate valid to mark pressence of commands in Queue. // // Maintain Queue and extract data from currently searched entry. // ///////////////////////////////////////////////////////////////////////////// // SRL FIFO Pointer. always @ (posedge ACLK) begin if (ARESET) begin addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_b_push & ~cmd_b_ready_i ) begin // Pushing data increase length/addr. addr_ptr <= addr_ptr + 1; end else if ( cmd_b_ready_i ) begin // Collapse addr when data is popped. addr_ptr <= collapsed_addr_ptr; end end end // FIFO Flags. always @ (posedge ACLK) begin if (ARESET) begin cmd_b_full <= 1'b0; cmd_b_valid <= 1'b0; end else begin if ( cmd_b_push & ~cmd_b_ready_i ) begin cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 ); cmd_b_valid <= 1'b1; end else if ( ~cmd_b_push & cmd_b_ready_i ) begin cmd_b_full <= 1'b0; cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 ); end end end // Infere SRL for storage. always @ (posedge ACLK) begin if ( cmd_b_push ) begin for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= {cmd_b_error, cmd_b_id}; end end // Get current transaction info. assign {inject_error, current_id} = data_srl[search_addr_ptr]; // Assign outputs. assign cmd_b_addr = collapsed_addr_ptr; ///////////////////////////////////////////////////////////////////////////// // Search Command Queue: // // Search for matching valid command in queue. // // A command is found when an valid entry with correct ID is found. The queue // is search from the oldest entry, i.e. from a high value. // When new commands are pushed the search address has to be updated to always // start the search from the oldest available. // ///////////////////////////////////////////////////////////////////////////// // Handle search addr. always @ (posedge ACLK) begin if (ARESET) begin search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_b_ready_i ) begin // Collapse addr when data is popped. search_addr_ptr <= collapsed_addr_ptr; end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin // Skip non valid command. search_addr_ptr <= search_addr_ptr - 1; end else if ( cmd_b_push ) begin search_addr_ptr <= search_addr_ptr + 1; end end end // Check if searched command is valid and match ID (for existing response on MI side). assign matching_id = ( M_AXI_BID_I == current_id ); assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I; assign use_match = found_match & S_AXI_BREADY; ///////////////////////////////////////////////////////////////////////////// // Track Used Commands: // // Actions that affect Valid Command: // * When a new command is pushed // => Shift valid vector one step // * When a command is used // => Clear corresponding valid bit // ///////////////////////////////////////////////////////////////////////////// // Valid command status is updated when a command is used or a new one is pushed. assign write_valid_cmd = cmd_b_push | cmd_b_ready_i; // Update the used command valid bit. always @ * begin updated_valid_cmd = valid_cmd; updated_valid_cmd[search_addr_ptr] = ~use_match; end // Shift valid vector when command is pushed. always @ * begin if ( cmd_b_push ) begin next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1}; end else begin next_valid_cmd = updated_valid_cmd; end end // Valid signals for next cycle. always @ (posedge ACLK) begin if (ARESET) begin valid_cmd <= {C_FIFO_WIDTH{1'b0}}; end else if ( write_valid_cmd ) begin valid_cmd <= next_valid_cmd; end end // Detect oldest available command in Queue. always @ * begin // Default to empty. collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}}; for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin if ( next_valid_cmd[index] ) begin collapsed_addr_ptr = index; end end end ///////////////////////////////////////////////////////////////////////////// // Pipe incoming data: // // The B channel is piped to improve timing and avoid impact in search // mechanism due to late arriving signals. // ///////////////////////////////////////////////////////////////////////////// // Clock data. always @ (posedge ACLK) begin if (ARESET) begin M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}}; M_AXI_BRESP_I <= 2'b00; M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}}; M_AXI_BVALID_I <= 1'b0; end else begin if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin M_AXI_BVALID_I <= 1'b0; end if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin M_AXI_BID_I <= M_AXI_BID; M_AXI_BRESP_I <= M_AXI_BRESP; M_AXI_BUSER_I <= M_AXI_BUSER; M_AXI_BVALID_I <= 1'b1; end end end // Generate ready to get new transaction. assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I; ///////////////////////////////////////////////////////////////////////////// // Inject Error: // // BRESP is modified according to command information. // ///////////////////////////////////////////////////////////////////////////// // Inject error in response. always @ * begin if ( inject_error ) begin S_AXI_BRESP = C_RESP_SLVERROR; end else begin S_AXI_BRESP = M_AXI_BRESP_I; end end // Handle interrupt generation. always @ (posedge ACLK) begin if (ARESET) begin ERROR_TRIGGER <= 1'b0; ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}}; end else begin if ( inject_error & cmd_b_ready_i ) begin ERROR_TRIGGER <= 1'b1; ERROR_TRANSACTION_ID <= M_AXI_BID_I; end else begin ERROR_TRIGGER <= 1'b0; end end end ///////////////////////////////////////////////////////////////////////////// // Transaction Throttling: // // Response is passed forward when a matching entry has been found in queue. // Both ready and valid are set when the command is completed. // ///////////////////////////////////////////////////////////////////////////// // Propagate masked valid. assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match; // Return ready with push back. assign M_AXI_BREADY_I = cmd_b_valid & use_match; // Command has been handled. assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match; assign cmd_b_ready = cmd_b_ready_i; ///////////////////////////////////////////////////////////////////////////// // Write Response Propagation: // // All information is simply forwarded on from MI- to SI-Side untouched. // ///////////////////////////////////////////////////////////////////////////// // 1:1 mapping. assign S_AXI_BID = M_AXI_BID_I; assign S_AXI_BUSER = M_AXI_BUSER_I; endmodule
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. // -- // -- This file contains confidential and proprietary information // -- of Xilinx, Inc. and is protected under U.S. and // -- international copyright and other intellectual property // -- laws. // -- // -- DISCLAIMER // -- This disclaimer is not a license and does not grant any // -- rights to the materials distributed herewith. Except as // -- otherwise provided in a valid license issued to you by // -- Xilinx, and to the maximum extent permitted by applicable // -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // -- (2) Xilinx shall not be liable (whether in contract or tort, // -- including negligence, or under any other theory of // -- liability) for any loss or damage of any kind or nature // -- related to, arising under or in connection with these // -- materials, including for any direct, or any indirect, // -- special, incidental, or consequential loss or damage // -- (including loss of data, profits, goodwill, or any type of // -- loss or damage suffered as a result of any action brought // -- by a third party) even if such damage or loss was // -- reasonably foreseeable or Xilinx had been advised of the // -- possibility of the same. // -- // -- CRITICAL APPLICATIONS // -- Xilinx products are not designed or intended to be fail- // -- safe, or for use in any application requiring fail-safe // -- performance, such as life-support or safety devices or // -- systems, Class III medical devices, nuclear facilities, // -- applications related to the deployment of airbags, or any // -- other applications that could lead to death, personal // -- injury, or severe property or environmental damage // -- (individually and collectively, "Critical // -- Applications"). Customer assumes the sole risk and // -- liability of any use of Xilinx products in Critical // -- Applications, subject only to applicable laws and // -- regulations governing limitations on product liability. // -- // -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // -- PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // Description: Write Response Channel for ATC // // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // // Structure: // b_atc // //-------------------------------------------------------------------------- `timescale 1ps/1ps module processing_system7_v5_5_b_atc # ( parameter C_FAMILY = "rtl", // FPGA Family. Current version: virtex6, spartan6 or later. parameter integer C_AXI_ID_WIDTH = 4, // Width of all ID signals on SI and MI side of checker. // Range: >= 1. parameter integer C_AXI_BUSER_WIDTH = 1, // Width of AWUSER signals. // Range: >= 1. parameter integer C_FIFO_DEPTH_LOG = 4 ) ( // Global Signals input wire ARESET, input wire ACLK, // Command Interface input wire cmd_b_push, input wire cmd_b_error, input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id, output wire cmd_b_ready, output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, output reg cmd_b_full, // Slave Interface Write Response Ports output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, output reg [2-1:0] S_AXI_BRESP, output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, output wire S_AXI_BVALID, input wire S_AXI_BREADY, // Master Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, input wire [2-1:0] M_AXI_BRESP, input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, input wire M_AXI_BVALID, output wire M_AXI_BREADY, // Trigger detection output reg ERROR_TRIGGER, output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID ); ///////////////////////////////////////////////////////////////////////////// // Local params ///////////////////////////////////////////////////////////////////////////// // Constants for packing levels. localparam [2-1:0] C_RESP_OKAY = 2'b00; localparam [2-1:0] C_RESP_EXOKAY = 2'b01; localparam [2-1:0] C_RESP_SLVERROR = 2'b10; localparam [2-1:0] C_RESP_DECERR = 2'b11; // Command FIFO settings localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; ///////////////////////////////////////////////////////////////////////////// // Variables for generating parameter controlled instances. ///////////////////////////////////////////////////////////////////////////// integer index; ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// // Internal signals ///////////////////////////////////////////////////////////////////////////// // Command Queue. reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; reg cmd_b_valid; wire cmd_b_ready_i; wire inject_error; wire [C_AXI_ID_WIDTH-1:0] current_id; // Search command. wire found_match; wire use_match; wire matching_id; // Manage valid command. wire write_valid_cmd; reg [C_FIFO_DEPTH-2:0] valid_cmd; reg [C_FIFO_DEPTH-2:0] updated_valid_cmd; reg [C_FIFO_DEPTH-2:0] next_valid_cmd; reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr; reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr; // Pipelined data reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I; reg [2-1:0] M_AXI_BRESP_I; reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I; reg M_AXI_BVALID_I; wire M_AXI_BREADY_I; ///////////////////////////////////////////////////////////////////////////// // Command Queue: // // Keep track of depth of Queue to generate full flag. // // Also generate valid to mark pressence of commands in Queue. // // Maintain Queue and extract data from currently searched entry. // ///////////////////////////////////////////////////////////////////////////// // SRL FIFO Pointer. always @ (posedge ACLK) begin if (ARESET) begin addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_b_push & ~cmd_b_ready_i ) begin // Pushing data increase length/addr. addr_ptr <= addr_ptr + 1; end else if ( cmd_b_ready_i ) begin // Collapse addr when data is popped. addr_ptr <= collapsed_addr_ptr; end end end // FIFO Flags. always @ (posedge ACLK) begin if (ARESET) begin cmd_b_full <= 1'b0; cmd_b_valid <= 1'b0; end else begin if ( cmd_b_push & ~cmd_b_ready_i ) begin cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 ); cmd_b_valid <= 1'b1; end else if ( ~cmd_b_push & cmd_b_ready_i ) begin cmd_b_full <= 1'b0; cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 ); end end end // Infere SRL for storage. always @ (posedge ACLK) begin if ( cmd_b_push ) begin for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin data_srl[index+1] <= data_srl[index]; end data_srl[0] <= {cmd_b_error, cmd_b_id}; end end // Get current transaction info. assign {inject_error, current_id} = data_srl[search_addr_ptr]; // Assign outputs. assign cmd_b_addr = collapsed_addr_ptr; ///////////////////////////////////////////////////////////////////////////// // Search Command Queue: // // Search for matching valid command in queue. // // A command is found when an valid entry with correct ID is found. The queue // is search from the oldest entry, i.e. from a high value. // When new commands are pushed the search address has to be updated to always // start the search from the oldest available. // ///////////////////////////////////////////////////////////////////////////// // Handle search addr. always @ (posedge ACLK) begin if (ARESET) begin search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; end else begin if ( cmd_b_ready_i ) begin // Collapse addr when data is popped. search_addr_ptr <= collapsed_addr_ptr; end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin // Skip non valid command. search_addr_ptr <= search_addr_ptr - 1; end else if ( cmd_b_push ) begin search_addr_ptr <= search_addr_ptr + 1; end end end // Check if searched command is valid and match ID (for existing response on MI side). assign matching_id = ( M_AXI_BID_I == current_id ); assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I; assign use_match = found_match & S_AXI_BREADY; ///////////////////////////////////////////////////////////////////////////// // Track Used Commands: // // Actions that affect Valid Command: // * When a new command is pushed // => Shift valid vector one step // * When a command is used // => Clear corresponding valid bit // ///////////////////////////////////////////////////////////////////////////// // Valid command status is updated when a command is used or a new one is pushed. assign write_valid_cmd = cmd_b_push | cmd_b_ready_i; // Update the used command valid bit. always @ * begin updated_valid_cmd = valid_cmd; updated_valid_cmd[search_addr_ptr] = ~use_match; end // Shift valid vector when command is pushed. always @ * begin if ( cmd_b_push ) begin next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1}; end else begin next_valid_cmd = updated_valid_cmd; end end // Valid signals for next cycle. always @ (posedge ACLK) begin if (ARESET) begin valid_cmd <= {C_FIFO_WIDTH{1'b0}}; end else if ( write_valid_cmd ) begin valid_cmd <= next_valid_cmd; end end // Detect oldest available command in Queue. always @ * begin // Default to empty. collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}}; for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin if ( next_valid_cmd[index] ) begin collapsed_addr_ptr = index; end end end ///////////////////////////////////////////////////////////////////////////// // Pipe incoming data: // // The B channel is piped to improve timing and avoid impact in search // mechanism due to late arriving signals. // ///////////////////////////////////////////////////////////////////////////// // Clock data. always @ (posedge ACLK) begin if (ARESET) begin M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}}; M_AXI_BRESP_I <= 2'b00; M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}}; M_AXI_BVALID_I <= 1'b0; end else begin if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin M_AXI_BVALID_I <= 1'b0; end if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin M_AXI_BID_I <= M_AXI_BID; M_AXI_BRESP_I <= M_AXI_BRESP; M_AXI_BUSER_I <= M_AXI_BUSER; M_AXI_BVALID_I <= 1'b1; end end end // Generate ready to get new transaction. assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I; ///////////////////////////////////////////////////////////////////////////// // Inject Error: // // BRESP is modified according to command information. // ///////////////////////////////////////////////////////////////////////////// // Inject error in response. always @ * begin if ( inject_error ) begin S_AXI_BRESP = C_RESP_SLVERROR; end else begin S_AXI_BRESP = M_AXI_BRESP_I; end end // Handle interrupt generation. always @ (posedge ACLK) begin if (ARESET) begin ERROR_TRIGGER <= 1'b0; ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}}; end else begin if ( inject_error & cmd_b_ready_i ) begin ERROR_TRIGGER <= 1'b1; ERROR_TRANSACTION_ID <= M_AXI_BID_I; end else begin ERROR_TRIGGER <= 1'b0; end end end ///////////////////////////////////////////////////////////////////////////// // Transaction Throttling: // // Response is passed forward when a matching entry has been found in queue. // Both ready and valid are set when the command is completed. // ///////////////////////////////////////////////////////////////////////////// // Propagate masked valid. assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match; // Return ready with push back. assign M_AXI_BREADY_I = cmd_b_valid & use_match; // Command has been handled. assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match; assign cmd_b_ready = cmd_b_ready_i; ///////////////////////////////////////////////////////////////////////////// // Write Response Propagation: // // All information is simply forwarded on from MI- to SI-Side untouched. // ///////////////////////////////////////////////////////////////////////////// // 1:1 mapping. assign S_AXI_BID = M_AXI_BID_I; assign S_AXI_BUSER = M_AXI_BUSER_I; endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 03/17/2016 05:20:59 PM // Design Name: // Module Name: Priority_Codec_32 // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Priority_Codec_32( input wire [25:0] Data_Dec_i, output reg [4:0] Data_Bin_o ); always @(Data_Dec_i) begin if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0 end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1 end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2 end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3 end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4 end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5 end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6 end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7 end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8 end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9 end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10 end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11 end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12 end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13 end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14 end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15 end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16 end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17 end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18 end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19 end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20 end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21 end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22 end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23 end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24 end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25 end else Data_Bin_o = 5'b00000;//zero value end endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 03/17/2016 05:20:59 PM // Design Name: // Module Name: Priority_Codec_32 // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Priority_Codec_32( input wire [25:0] Data_Dec_i, output reg [4:0] Data_Bin_o ); always @(Data_Dec_i) begin if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0 end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1 end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2 end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3 end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4 end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5 end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6 end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7 end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8 end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9 end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10 end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11 end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12 end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13 end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14 end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15 end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16 end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17 end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18 end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19 end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20 end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21 end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22 end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23 end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24 end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25 end else Data_Bin_o = 5'b00000;//zero value end endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 22:40:46 12/20/2010 // Design Name: // Module Name: clk_test // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module clk_test( input clk, input sysclk, output [31:0] snes_sysclk_freq ); reg [31:0] snes_sysclk_freq_r; assign snes_sysclk_freq = snes_sysclk_freq_r; reg [31:0] sysclk_counter; reg [31:0] sysclk_value; initial snes_sysclk_freq_r = 32'hFFFFFFFF; initial sysclk_counter = 0; initial sysclk_value = 0; reg [1:0] sysclk_sreg; always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk}; wire sysclk_rising = (sysclk_sreg == 2'b01); always @(posedge clk) begin if(sysclk_counter < 96000000) begin sysclk_counter <= sysclk_counter + 1; if(sysclk_rising) sysclk_value <= sysclk_value + 1; end else begin snes_sysclk_freq_r <= sysclk_value; sysclk_counter <= 0; sysclk_value <= 0; end end endmodule
// (c) Copyright 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // axi to vector // A generic module to merge all axi signals into one signal called payload. // This is strictly wires, so no clk, reset, aclken, valid/ready are required. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_infrastructure_v1_1_vector2axi # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter integer C_AXI_PROTOCOL = 0, parameter integer C_AXI_ID_WIDTH = 4, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AWPAYLOAD_WIDTH = 61, parameter integer C_WPAYLOAD_WIDTH = 73, parameter integer C_BPAYLOAD_WIDTH = 6, parameter integer C_ARPAYLOAD_WIDTH = 61, parameter integer C_RPAYLOAD_WIDTH = 69 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // Slave Interface Write Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, output wire [3-1:0] m_axi_awsize, output wire [2-1:0] m_axi_awburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, output wire [4-1:0] m_axi_awcache, output wire [3-1:0] m_axi_awprot, output wire [4-1:0] m_axi_awregion, output wire [4-1:0] m_axi_awqos, output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, // Slave Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid, output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output wire m_axi_wlast, output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, // Slave Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid, input wire [2-1:0] m_axi_bresp, input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, // Slave Interface Read Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, output wire [3-1:0] m_axi_arsize, output wire [2-1:0] m_axi_arburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, output wire [4-1:0] m_axi_arcache, output wire [3-1:0] m_axi_arprot, output wire [4-1:0] m_axi_arregion, output wire [4-1:0] m_axi_arqos, output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, // Slave Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid, input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [2-1:0] m_axi_rresp, input wire m_axi_rlast, input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, // payloads input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload, input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload, output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload, input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload, output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// `include "axi_infrastructure_v1_1_header.vh" //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // AXI4, AXI4LITE, AXI3 packing assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH]; assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH]; assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH]; assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH]; assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp; assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH]; assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH]; assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata; assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp; generate if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ; assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH]; assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH]; assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ; assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ; assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ; assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ; assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ; if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ; end else begin : gen_no_axi3_wid_packing assign m_axi_wid = 1'b0; end assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid; assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ; assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH]; assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH]; assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ; assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ; assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ; assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ; assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast; assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ; if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH]; assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH]; end else begin : gen_no_region_signals assign m_axi_awregion = 'b0; assign m_axi_arregion = 'b0; end if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH]; assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ; assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ; assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH]; assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ; end else begin : gen_no_user_signals assign m_axi_awuser = 'b0; assign m_axi_wuser = 'b0; assign m_axi_aruser = 'b0; end end else begin : gen_axi4lite_packing assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; assign m_axi_awburst = 'b0; assign m_axi_awcache = 'b0; assign m_axi_awlen = 'b0; assign m_axi_awlock = 'b0; assign m_axi_awid = 'b0; assign m_axi_awqos = 'b0; assign m_axi_wlast = 1'b1; assign m_axi_wid = 'b0; assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; assign m_axi_arburst = 'b0; assign m_axi_arcache = 'b0; assign m_axi_arlen = 'b0; assign m_axi_arlock = 'b0; assign m_axi_arid = 'b0; assign m_axi_arqos = 'b0; assign m_axi_awregion = 'b0; assign m_axi_arregion = 'b0; assign m_axi_awuser = 'b0; assign m_axi_wuser = 'b0; assign m_axi_aruser = 'b0; end endgenerate endmodule `default_nettype wire
// (c) Copyright 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. //----------------------------------------------------------------------------- // // axi to vector // A generic module to merge all axi signals into one signal called payload. // This is strictly wires, so no clk, reset, aclken, valid/ready are required. // // Verilog-standard: Verilog 2001 //-------------------------------------------------------------------------- // `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_infrastructure_v1_1_vector2axi # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter integer C_AXI_PROTOCOL = 0, parameter integer C_AXI_ID_WIDTH = 4, parameter integer C_AXI_ADDR_WIDTH = 32, parameter integer C_AXI_DATA_WIDTH = 32, parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, parameter integer C_AXI_AWUSER_WIDTH = 1, parameter integer C_AXI_WUSER_WIDTH = 1, parameter integer C_AXI_BUSER_WIDTH = 1, parameter integer C_AXI_ARUSER_WIDTH = 1, parameter integer C_AXI_RUSER_WIDTH = 1, parameter integer C_AWPAYLOAD_WIDTH = 61, parameter integer C_WPAYLOAD_WIDTH = 73, parameter integer C_BPAYLOAD_WIDTH = 6, parameter integer C_ARPAYLOAD_WIDTH = 61, parameter integer C_RPAYLOAD_WIDTH = 69 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// // Slave Interface Write Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, output wire [3-1:0] m_axi_awsize, output wire [2-1:0] m_axi_awburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, output wire [4-1:0] m_axi_awcache, output wire [3-1:0] m_axi_awprot, output wire [4-1:0] m_axi_awregion, output wire [4-1:0] m_axi_awqos, output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, // Slave Interface Write Data Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid, output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, output wire m_axi_wlast, output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, // Slave Interface Write Response Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid, input wire [2-1:0] m_axi_bresp, input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, // Slave Interface Read Address Ports output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid, output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, output wire [3-1:0] m_axi_arsize, output wire [2-1:0] m_axi_arburst, output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, output wire [4-1:0] m_axi_arcache, output wire [3-1:0] m_axi_arprot, output wire [4-1:0] m_axi_arregion, output wire [4-1:0] m_axi_arqos, output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, // Slave Interface Read Data Ports input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid, input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [2-1:0] m_axi_rresp, input wire m_axi_rlast, input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, // payloads input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload, input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload, output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload, input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload, output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload ); //////////////////////////////////////////////////////////////////////////////// // Functions //////////////////////////////////////////////////////////////////////////////// `include "axi_infrastructure_v1_1_header.vh" //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// // AXI4, AXI4LITE, AXI3 packing assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH]; assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH]; assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH]; assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH]; assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp; assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH]; assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH]; assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata; assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp; generate if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ; assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH]; assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH]; assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ; assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ; assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ; assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ; assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ; if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ; end else begin : gen_no_axi3_wid_packing assign m_axi_wid = 1'b0; end assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid; assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ; assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH]; assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH]; assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ; assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ; assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ; assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ; assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast; assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ; if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH]; assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH]; end else begin : gen_no_region_signals assign m_axi_awregion = 'b0; assign m_axi_arregion = 'b0; end if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH]; assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ; assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ; assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH]; assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ; end else begin : gen_no_user_signals assign m_axi_awuser = 'b0; assign m_axi_wuser = 'b0; assign m_axi_aruser = 'b0; end end else begin : gen_axi4lite_packing assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; assign m_axi_awburst = 'b0; assign m_axi_awcache = 'b0; assign m_axi_awlen = 'b0; assign m_axi_awlock = 'b0; assign m_axi_awid = 'b0; assign m_axi_awqos = 'b0; assign m_axi_wlast = 1'b1; assign m_axi_wid = 'b0; assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; assign m_axi_arburst = 'b0; assign m_axi_arcache = 'b0; assign m_axi_arlen = 'b0; assign m_axi_arlock = 'b0; assign m_axi_arid = 'b0; assign m_axi_arqos = 'b0; assign m_axi_awregion = 'b0; assign m_axi_arregion = 'b0; assign m_axi_awuser = 'b0; assign m_axi_wuser = 'b0; assign m_axi_aruser = 'b0; end endgenerate endmodule `default_nettype wire
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_MS__A311OI_PP_SYMBOL_V `define SKY130_FD_SC_MS__A311OI_PP_SYMBOL_V /** * a311oi: 3-input AND into first input of 3-input NOR. * * Y = !((A1 & A2 & A3) | B1 | C1) * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_ms__a311oi ( //# {{data|Data Signals}} input A1 , input A2 , input A3 , input B1 , input C1 , output Y , //# {{power|Power}} input VPB , input VPWR, input VGND, input VNB ); endmodule `default_nettype wire `endif // SKY130_FD_SC_MS__A311OI_PP_SYMBOL_V
//***************************************************************************** // (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2.0 // \ \ Application : MIG // / / Filename : wiredly.v // /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $ // \ \ / \ Date Created : Fri Oct 14 2011 // \___\/\___\ // // Device : 7Series // Design Name : DDR2 SDRAM // Purpose : // This module provide the definition of a zero ohm component (A, B). // // The applications of this component include: // . Normal operation of a jumper wire (data flowing in both directions) // This can corrupt data from DRAM to FPGA useful for verifying ECC function. // // The component consists of 2 ports: // . Port A: One side of the pass-through switch // . Port B: The other side of the pass-through switch // The model is sensitive to transactions on all ports. Once a transaction // is detected, all other transactions are ignored for that simulation time // (i.e. further transactions in that delta time are ignored). // Model Limitations and Restrictions: // Signals asserted on the ports of the error injector should not have // transactions occuring in multiple delta times because the model // is sensitive to transactions on port A, B ONLY ONCE during // a simulation time. Thus, once fired, a process will // not refire if there are multiple transactions occuring in delta times. // This condition may occur in gate level simulations with // ZERO delays because transactions may occur in multiple delta times. // // Reference : // Revision History : //***************************************************************************** `timescale 1ns / 1ps module WireDelay # ( parameter Delay_g = 0, parameter Delay_rd = 0, parameter ERR_INSERT = "OFF" ) ( inout A, inout B, input reset, input phy_init_done ); reg A_r; reg B_r; reg B_inv ; reg line_en; reg B_nonX; assign A = A_r; assign B = B_r; always @ (*) begin if (B === 1'bx) B_nonX <= $random; else B_nonX <= B; end always@(*) begin if((B_nonX == 'b1) || (B_nonX == 'b0)) B_inv <= #0 ~B_nonX ; else B_inv <= #0 'bz ; end always @(*) begin if (!reset) begin A_r <= 1'bz; B_r <= 1'bz; line_en <= 1'b0; end else begin if (line_en) begin B_r <= 1'bz; if ((ERR_INSERT == "ON") & (phy_init_done)) A_r <= #Delay_rd B_inv; else A_r <= #Delay_rd B_nonX; end else begin B_r <= #Delay_g A; A_r <= 1'bz; end end end always @(A or B) begin if (!reset) begin line_en <= 1'b0; end else if (A !== A_r) begin line_en <= 1'b0; end else if (B_r !== B) begin line_en <= 1'b1; end else begin line_en <= line_en; end end endmodule
/////////////////////////////////////////////////////////////////////////////// // vim:set shiftwidth=3 softtabstop=3 expandtab: // // Module: router_op_lut_regs_non_cntr.v // Project: NF2.1 // Description: Demultiplexes, stores and serves register requests // // Contains the non-counter registers. // /////////////////////////////////////////////////////////////////////////////// module router_op_lut_regs_non_cntr #( parameter NUM_QUEUES = 5, parameter ARP_LUT_DEPTH_BITS = 4, parameter LPM_LUT_DEPTH_BITS = 4, parameter FILTER_DEPTH_BITS = 4, parameter UDP_REG_SRC_WIDTH = 2 ) ( input reg_req_in, input reg_ack_in, input reg_rd_wr_L_in, input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in, input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in, input [UDP_REG_SRC_WIDTH-1:0] reg_src_in, output reg reg_req_out, output reg reg_ack_out, output reg reg_rd_wr_L_out, output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out, output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out, output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out, // --- interface to ip_lpm output reg [LPM_LUT_DEPTH_BITS-1:0 ] lpm_rd_addr, // address in table to read output reg lpm_rd_req, // request a read input [31:0] lpm_rd_ip, // ip to match in the CAM input [31:0] lpm_rd_mask, // subnet mask input [NUM_QUEUES-1:0] lpm_rd_oq, // input queue input [31:0] lpm_rd_next_hop_ip, // ip addr of next hop input lpm_rd_ack, // pulses high output reg [LPM_LUT_DEPTH_BITS-1:0] lpm_wr_addr, output reg lpm_wr_req, output [NUM_QUEUES-1:0] lpm_wr_oq, output [31:0] lpm_wr_next_hop_ip, // ip addr of next hop output [31:0] lpm_wr_ip, // data to match in the CAM output [31:0] lpm_wr_mask, input lpm_wr_ack, // --- ip_arp output reg [ARP_LUT_DEPTH_BITS-1:0] arp_rd_addr, // address in table to read output reg arp_rd_req, // request a read input [47:0] arp_rd_mac, // data read from the LUT at rd_addr input [31:0] arp_rd_ip, // ip to match in the CAM input arp_rd_ack, // pulses high output reg [ARP_LUT_DEPTH_BITS-1:0] arp_wr_addr, output reg arp_wr_req, output [47:0] arp_wr_mac, output [31:0] arp_wr_ip, // data to match in the CAM input arp_wr_ack, // --- interface to dest_ip_filter output reg [FILTER_DEPTH_BITS-1:0] dest_ip_filter_rd_addr, // address in table to read output reg dest_ip_filter_rd_req, // request a read input [31:0] dest_ip_filter_rd_ip, // ip to match in the CAM input dest_ip_filter_rd_ack, // pulses high output reg [FILTER_DEPTH_BITS-1:0] dest_ip_filter_wr_addr, output reg dest_ip_filter_wr_req, output [31:0] dest_ip_filter_wr_ip, // data to match in the CAM input dest_ip_filter_wr_ack, // --- eth_parser output reg [47:0] mac_0, // address of rx queue 0 output reg [47:0] mac_1, // address of rx queue 1 output reg [47:0] mac_2, // address of rx queue 2 output reg [47:0] mac_3, // address of rx queue 3 input clk, input reset ); function integer log2; input integer number; begin log2=0; while(2**log2<number) begin log2=log2+1; end end endfunction // log2 // ------------- Internal parameters -------------- localparam NUM_REGS_USED = 32; localparam ADDR_WIDTH = log2(NUM_REGS_USED); localparam WAIT_FOR_REQ = 1; localparam WRITE_TO_ARP_LUT = 2; localparam READ_FROM_ARP_LUT = 4; localparam WRITE_TO_RT_LUT = 8; localparam READ_FROM_RT_LUT = 16; localparam WRITE_TO_DEST_IP_FILTER = 32; localparam READ_FROM_DEST_IP_FILTER = 64; localparam DONE = 128; // ------------- Wires/reg ------------------ wire [ADDR_WIDTH-1:0] addr; wire [`ROUTER_OP_LUT_REG_ADDR_WIDTH- 1:0] reg_addr; wire [`UDP_REG_ADDR_WIDTH-`ROUTER_OP_LUT_REG_ADDR_WIDTH- 1:0] tag_addr; wire addr_good; wire tag_hit; reg [7:0] state; reg reg_rd_wr_L_held; reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_held; reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_held; reg [UDP_REG_SRC_WIDTH-1:0] reg_src_held; reg [NUM_QUEUES-1:0] lpm_oq; reg [31:0] lpm_next_hop_ip; reg [31:0] lpm_ip; reg [31:0] lpm_mask; reg [47:0] arp_mac; reg [31:0] arp_ip; reg [31:0] dest_ip_filter_ip; // -------------- Logic -------------------- assign addr = reg_addr_in[ADDR_WIDTH-1:0]; assign reg_addr = reg_addr_in[`ROUTER_OP_LUT_REG_ADDR_WIDTH-1:0]; assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:`ROUTER_OP_LUT_REG_ADDR_WIDTH]; //assign addr_good = reg_addr < NUM_REGS_USED; assign addr_good = reg_addr >= `ROUTER_OP_LUT_MAC_0_HI && reg_addr <= `ROUTER_OP_LUT_DST_IP_FILTER_TABLE_WR_ADDR; assign tag_hit = tag_addr == `ROUTER_OP_LUT_BLOCK_ADDR; assign lpm_wr_oq = lpm_oq; assign lpm_wr_next_hop_ip = lpm_next_hop_ip; assign lpm_wr_ip = lpm_ip; assign lpm_wr_mask = lpm_mask; assign dest_ip_filter_wr_ip = dest_ip_filter_ip; assign arp_wr_ip = arp_ip; assign arp_wr_mac = arp_mac; // The following resets have been moved here to enable optimization by // pushing some registers into RAMs // synthesis translate_off initial begin arp_rd_addr = 'h0; arp_wr_addr = 'h0; lpm_rd_addr = 'h0; lpm_wr_addr = 'h0; dest_ip_filter_rd_addr = 'h0; dest_ip_filter_wr_addr = 'h0; end // synthesis translate_on /* run the counters and mux between write and update */ always @(posedge clk) begin if(reset) begin arp_mac <= 48'h0; arp_ip <= 32'h0; lpm_ip <= 'h0; lpm_mask <= 'h0; lpm_next_hop_ip <= 'h0; lpm_oq <= 'h0; mac_0 <= {`ROUTER_OP_LUT_DEFAULT_MAC_0_HI, `ROUTER_OP_LUT_DEFAULT_MAC_0_LO}; mac_1 <= {`ROUTER_OP_LUT_DEFAULT_MAC_1_HI, `ROUTER_OP_LUT_DEFAULT_MAC_1_LO}; mac_2 <= {`ROUTER_OP_LUT_DEFAULT_MAC_2_HI, `ROUTER_OP_LUT_DEFAULT_MAC_2_LO}; mac_3 <= {`ROUTER_OP_LUT_DEFAULT_MAC_3_HI, `ROUTER_OP_LUT_DEFAULT_MAC_3_LO}; dest_ip_filter_ip <= 'h0; reg_req_out <= 0; reg_ack_out <= 0; reg_rd_wr_L_out <= 0; reg_addr_out <= 0; reg_data_out <= 0; reg_src_out <= 0; reg_rd_wr_L_held <= 0; reg_addr_held <= 0; reg_data_held <= 0; reg_src_held <= 0; state <= WAIT_FOR_REQ; lpm_rd_req <= 0; lpm_wr_req <= 0; arp_rd_req <= 0; arp_wr_req <= 0; dest_ip_filter_wr_req <= 0; dest_ip_filter_rd_req <= 0; end // if (reset) else begin case(state) WAIT_FOR_REQ: begin if (reg_req_in && tag_hit) begin if (!reg_rd_wr_L_in && addr_good) begin // write // Update the appropriate register case (addr) `ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_HI : arp_mac[47:32] <= reg_data_in; `ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_LO : arp_mac[31:0] <= reg_data_in; `ROUTER_OP_LUT_ARP_TABLE_ENTRY_NEXT_HOP_IP : arp_ip <= reg_data_in; `ROUTER_OP_LUT_ARP_TABLE_RD_ADDR : arp_rd_addr <= reg_data_in; `ROUTER_OP_LUT_ARP_TABLE_WR_ADDR : arp_wr_addr <= reg_data_in; `ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_IP : lpm_ip <= reg_data_in; `ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_MASK : lpm_mask <= reg_data_in; `ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_NEXT_HOP_IP : lpm_next_hop_ip <= reg_data_in; `ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_OUTPUT_PORT : lpm_oq <= reg_data_in; `ROUTER_OP_LUT_ROUTE_TABLE_RD_ADDR : lpm_rd_addr <= reg_data_in; `ROUTER_OP_LUT_ROUTE_TABLE_WR_ADDR : lpm_wr_addr <= reg_data_in; `ROUTER_OP_LUT_MAC_0_HI : mac_0[47:32] <= reg_data_in; `ROUTER_OP_LUT_MAC_0_LO : mac_0[31:0] <= reg_data_in; `ROUTER_OP_LUT_MAC_1_HI : mac_1[47:32] <= reg_data_in; `ROUTER_OP_LUT_MAC_1_LO : mac_1[31:0] <= reg_data_in; `ROUTER_OP_LUT_MAC_2_HI : mac_2[47:32] <= reg_data_in; `ROUTER_OP_LUT_MAC_2_LO : mac_2[31:0] <= reg_data_in; `ROUTER_OP_LUT_MAC_3_HI : mac_3[47:32] <= reg_data_in; `ROUTER_OP_LUT_MAC_3_LO : mac_3[31:0] <= reg_data_in; `ROUTER_OP_LUT_DST_IP_FILTER_TABLE_ENTRY_IP : dest_ip_filter_ip<= reg_data_in; `ROUTER_OP_LUT_DST_IP_FILTER_TABLE_RD_ADDR : dest_ip_filter_rd_addr <= reg_data_in; `ROUTER_OP_LUT_DST_IP_FILTER_TABLE_WR_ADDR : dest_ip_filter_wr_addr <= reg_data_in; endcase // Perform the correct post processing case(addr) `ROUTER_OP_LUT_ARP_TABLE_WR_ADDR : state <= WRITE_TO_ARP_LUT; `ROUTER_OP_LUT_ARP_TABLE_RD_ADDR : state <= READ_FROM_ARP_LUT; `ROUTER_OP_LUT_ROUTE_TABLE_WR_ADDR : state <= WRITE_TO_RT_LUT; `ROUTER_OP_LUT_ROUTE_TABLE_RD_ADDR : state <= READ_FROM_RT_LUT; `ROUTER_OP_LUT_DST_IP_FILTER_TABLE_WR_ADDR : state <= WRITE_TO_DEST_IP_FILTER; `ROUTER_OP_LUT_DST_IP_FILTER_TABLE_RD_ADDR : state <= READ_FROM_DEST_IP_FILTER; default : state <= DONE; endcase // case(addr) reg_req_out <= 0; reg_ack_out <= 0; reg_rd_wr_L_out <= 0; reg_addr_out <= 0; reg_data_out <= 0; reg_src_out <= 0; reg_rd_wr_L_held <= reg_rd_wr_L_in; reg_addr_held <= reg_addr_in; reg_data_held <= reg_data_in; reg_src_held <= reg_src_in; end else begin reg_req_out <= 1'b 1; reg_rd_wr_L_out <= reg_rd_wr_L_in; reg_addr_out <= reg_addr_in; if (addr_good) begin reg_ack_out <= 1'b 1; case (addr) `ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_HI : reg_data_out <= arp_mac[47:32]; `ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_LO : reg_data_out <= arp_mac[31:0]; `ROUTER_OP_LUT_ARP_TABLE_ENTRY_NEXT_HOP_IP : reg_data_out <= arp_ip; `ROUTER_OP_LUT_ARP_TABLE_RD_ADDR : reg_data_out <= arp_rd_addr; `ROUTER_OP_LUT_ARP_TABLE_WR_ADDR : reg_data_out <= arp_wr_addr; `ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_IP : reg_data_out <= lpm_ip; `ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_MASK : reg_data_out <= lpm_mask; `ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_NEXT_HOP_IP : reg_data_out <= lpm_next_hop_ip; `ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_OUTPUT_PORT : reg_data_out <= lpm_oq; `ROUTER_OP_LUT_ROUTE_TABLE_RD_ADDR : reg_data_out <= lpm_rd_addr; `ROUTER_OP_LUT_ROUTE_TABLE_WR_ADDR : reg_data_out <= lpm_wr_addr; `ROUTER_OP_LUT_MAC_0_HI : reg_data_out <= mac_0[47:32]; `ROUTER_OP_LUT_MAC_0_LO : reg_data_out <= mac_0[31:0]; `ROUTER_OP_LUT_MAC_1_HI : reg_data_out <= mac_1[47:32]; `ROUTER_OP_LUT_MAC_1_LO : reg_data_out <= mac_1[31:0]; `ROUTER_OP_LUT_MAC_2_HI : reg_data_out <= mac_2[47:32]; `ROUTER_OP_LUT_MAC_2_LO : reg_data_out <= mac_2[31:0]; `ROUTER_OP_LUT_MAC_3_HI : reg_data_out <= mac_3[47:32]; `ROUTER_OP_LUT_MAC_3_LO : reg_data_out <= mac_3[31:0]; `ROUTER_OP_LUT_DST_IP_FILTER_TABLE_ENTRY_IP : reg_data_out <= dest_ip_filter_ip; `ROUTER_OP_LUT_DST_IP_FILTER_TABLE_RD_ADDR : reg_data_out <= dest_ip_filter_rd_addr; `ROUTER_OP_LUT_DST_IP_FILTER_TABLE_WR_ADDR : reg_data_out <= dest_ip_filter_wr_addr; default : reg_data_out <= 32'h DEAD_BEEF; endcase end else begin reg_ack_out <= 1'b 0; reg_data_out <= reg_data_in; end reg_src_out <= reg_src_in; end end else begin reg_req_out <= reg_req_in; reg_ack_out <= reg_ack_in; reg_rd_wr_L_out <= reg_rd_wr_L_in; reg_addr_out <= reg_addr_in; reg_data_out <= reg_data_in; reg_src_out <= reg_src_in; end end // case: WAIT_FOR_REQ WRITE_TO_ARP_LUT: begin if(arp_wr_ack) begin state <= DONE; arp_wr_req <= 0; end else begin arp_wr_req <= 1; end end READ_FROM_ARP_LUT: begin if(arp_rd_ack) begin arp_mac[47:32] <= arp_rd_mac[47:32]; arp_mac[31:0] <= arp_rd_mac[31:0]; arp_ip <= arp_rd_ip; state <= DONE; arp_rd_req <= 0; end // if (rd_ack) else begin arp_rd_req <= 1; end end // case: READ_FROM_MAC_LUT WRITE_TO_RT_LUT: begin if(lpm_wr_ack) begin state <= DONE; lpm_wr_req <= 0; end else begin lpm_wr_req <= 1; end end READ_FROM_RT_LUT: begin if(lpm_rd_ack) begin lpm_ip <= lpm_rd_ip; lpm_mask <= lpm_rd_mask; lpm_next_hop_ip <= lpm_rd_next_hop_ip; lpm_oq <= lpm_rd_oq; state <= DONE; lpm_rd_req <= 0; end // if (rd_ack) else begin lpm_rd_req <= 1; end end // case: READ_FROM_MAC_LUT WRITE_TO_DEST_IP_FILTER: begin if(dest_ip_filter_wr_ack) begin state <= DONE; dest_ip_filter_wr_req <= 0; end else begin dest_ip_filter_wr_req <= 1; end end // case: WRITE_TO_DEST_IP_FILTER READ_FROM_DEST_IP_FILTER: begin if(dest_ip_filter_rd_ack) begin dest_ip_filter_ip <= dest_ip_filter_rd_ip; state <= DONE; dest_ip_filter_rd_req <= 0; end // if (rd_ack) else begin dest_ip_filter_rd_req <= 1; end end // case: READ_FROM_DEST_IP_FILTER DONE: begin state <= WAIT_FOR_REQ; reg_req_out <= 1'b 1; reg_ack_out <= 1'b 1; reg_rd_wr_L_out <= reg_rd_wr_L_held; reg_addr_out <= reg_addr_held; reg_data_out <= reg_data_held; reg_src_out <= reg_src_held; end endcase // case(state) end // else: !if(reset) end // always @ (posedge clk) endmodule
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_PP_V `define SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_PP_V /** * a21oi: 2-input AND into first input of 2-input NOR. * * Y = !((A1 & A2) | B1) * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import user defined primitives. `include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v" `celldefine module sky130_fd_sc_hvl__a21oi ( Y , A1 , A2 , B1 , VPWR, VGND, VPB , VNB ); // Module ports output Y ; input A1 ; input A2 ; input B1 ; input VPWR; input VGND; input VPB ; input VNB ; // Local signals wire and0_out ; wire nor0_out_Y ; wire pwrgood_pp0_out_Y; // Name Output Other arguments and and0 (and0_out , A1, A2 ); nor nor0 (nor0_out_Y , B1, and0_out ); sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND); buf buf0 (Y , pwrgood_pp0_out_Y ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_PP_V
// Accellera Standard V2.5 Open Verification Library (OVL). // Accellera Copyright (c) 2005-2010. All rights reserved. `include "std_ovl_defines.h" `module ovl_no_underflow (clock, reset, enable, test_expr, fire); parameter severity_level = `OVL_SEVERITY_DEFAULT; parameter width = 1; parameter min = 0; parameter max = ((1<<width)-1); parameter property_type = `OVL_PROPERTY_DEFAULT; parameter msg = `OVL_MSG_DEFAULT; parameter coverage_level = `OVL_COVER_DEFAULT; parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT; parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT; parameter gating_type = `OVL_GATING_TYPE_DEFAULT; input clock, reset, enable; input [width-1:0] test_expr; output [`OVL_FIRE_WIDTH-1:0] fire; // Parameters that should not be edited parameter assert_name = "OVL_NO_UNDERFLOW"; `include "std_ovl_reset.h" `include "std_ovl_clock.h" `include "std_ovl_cover.h" `include "std_ovl_task.h" `include "std_ovl_init.h" `ifdef OVL_VERILOG `include "./vlog95/assert_no_underflow_logic.v" assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3 `endif `ifdef OVL_SVA `include "./sva05/assert_no_underflow_logic.sv" assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3 `endif `ifdef OVL_PSL assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3 `include "./psl05/assert_no_underflow_psl_logic.v" `else `endmodule // ovl_no_underflow `endif
// TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_015.v // This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes // will probably be lost. // // Generated using ACDS version 16.0 222 `timescale 1 ps / 1 ps module TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_015 #( parameter inBitsPerSymbol = 18, parameter inUsePackets = 0, parameter inDataWidth = 18, parameter inChannelWidth = 0, parameter inErrorWidth = 0, parameter inUseEmptyPort = 0, parameter inUseValid = 1, parameter inUseReady = 1, parameter inReadyLatency = 0, parameter outDataWidth = 18, parameter outChannelWidth = 0, parameter outErrorWidth = 1, parameter outUseEmptyPort = 0, parameter outUseValid = 1, parameter outUseReady = 1, parameter outReadyLatency = 0 ) ( input wire in_clk_0_clk, // in_clk_0.clk input wire in_rst_0_reset, // in_rst_0.reset input wire [17:0] in_0_data, // in_0.data input wire in_0_valid, // .valid output wire in_0_ready, // .ready output wire [17:0] out_0_data, // out_0.data output wire out_0_valid, // .valid input wire out_0_ready, // .ready output wire [0:0] out_0_error // .error ); generate // If any of the display statements (or deliberately broken // instantiations) within this generate block triggers then this module // has been instantiated this module with a set of parameters different // from those it was generated for. This will usually result in a // non-functioning system. if (inBitsPerSymbol != 18) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above inbitspersymbol_check ( .error(1'b1) ); end if (inUsePackets != 0) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above inusepackets_check ( .error(1'b1) ); end if (inDataWidth != 18) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above indatawidth_check ( .error(1'b1) ); end if (inChannelWidth != 0) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above inchannelwidth_check ( .error(1'b1) ); end if (inErrorWidth != 0) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above inerrorwidth_check ( .error(1'b1) ); end if (inUseEmptyPort != 0) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above inuseemptyport_check ( .error(1'b1) ); end if (inUseValid != 1) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above inusevalid_check ( .error(1'b1) ); end if (inUseReady != 1) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above inuseready_check ( .error(1'b1) ); end if (inReadyLatency != 0) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above inreadylatency_check ( .error(1'b1) ); end if (outDataWidth != 18) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above outdatawidth_check ( .error(1'b1) ); end if (outChannelWidth != 0) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above outchannelwidth_check ( .error(1'b1) ); end if (outErrorWidth != 1) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above outerrorwidth_check ( .error(1'b1) ); end if (outUseEmptyPort != 0) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above outuseemptyport_check ( .error(1'b1) ); end if (outUseValid != 1) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above outusevalid_check ( .error(1'b1) ); end if (outUseReady != 1) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above outuseready_check ( .error(1'b1) ); end if (outReadyLatency != 0) begin initial begin $display("Generated module instantiated with wrong parameters"); $stop; end instantiated_with_wrong_parameters_error_see_comment_above outreadylatency_check ( .error(1'b1) ); end endgenerate TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_015_error_adapter_0 error_adapter_0 ( .clk (in_clk_0_clk), // clk.clk .reset_n (~in_rst_0_reset), // reset.reset_n .in_data (in_0_data), // in.data .in_valid (in_0_valid), // .valid .in_ready (in_0_ready), // .ready .out_data (out_0_data), // out.data .out_valid (out_0_valid), // .valid .out_ready (out_0_ready), // .ready .out_error (out_0_error) // .error ); endmodule
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HS__FILL_FUNCTIONAL_PP_V `define SKY130_FD_SC_HS__FILL_FUNCTIONAL_PP_V /** * fill: Fill cell. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none `celldefine module sky130_fd_sc_hs__fill ( VPWR, VGND, VPB , VNB ); // Module ports input VPWR; input VGND; input VPB ; input VNB ; // No contents. endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HS__FILL_FUNCTIONAL_PP_V
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_SN_BLACKBOX_V `define SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_SN_BLACKBOX_V /** * udp_dlatch$PR_pp$sN: D-latch, gated clear direct / gate active high * (Q output UDP) * * Verilog stub definition (black box with power pins). * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hs__udp_dlatch$PR_pp$sN ( Q , D , GATE , RESET , SLEEP_B , NOTIFIER ); output Q ; input D ; input GATE ; input RESET ; input SLEEP_B ; input NOTIFIER; endmodule `default_nettype wire `endif // SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_SN_BLACKBOX_V
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HVL__SDFSTP_PP_BLACKBOX_V `define SKY130_FD_SC_HVL__SDFSTP_PP_BLACKBOX_V /** * sdfstp: Scan delay flop, inverted set, non-inverted clock, * single output. * * Verilog stub definition (black box with power pins). * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hvl__sdfstp ( Q , CLK , D , SCD , SCE , SET_B, VPWR , VGND , VPB , VNB ); output Q ; input CLK ; input D ; input SCD ; input SCE ; input SET_B; input VPWR ; input VGND ; input VPB ; input VNB ; endmodule `default_nettype wire `endif // SKY130_FD_SC_HVL__SDFSTP_PP_BLACKBOX_V
// megafunction wizard: %ALTPLL%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ============================================================ // File Name: pll_sys.v // Megafunction Name(s): // altpll // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 18.0.0 Build 614 04/24/2018 SJ Lite Edition // ************************************************************ //Copyright (C) 2018 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Intel Program License //Subscription Agreement, the Intel Quartus Prime License Agreement, //the Intel FPGA IP License Agreement, or other applicable license //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by //Intel and sold by Intel or its authorized distributors. Please //refer to the applicable agreement for further details. module pll_sys ( inclk0, c0, c1, c2, locked); input inclk0; output c0; output c1; output c2; output locked; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "7.372800" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "1.843200" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "7.37280000" // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "1.84320000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_sys.mif" // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" // Retrieval info: PRIVATE: SPREAD_USE STRING "0" // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "15625" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2304" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "15625" // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "576" // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.ppf TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys_inst.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys_bb.v TRUE // Retrieval info: LIB_FILE: altera_mf // Retrieval info: CBX_MODULE_PREFIX: ON
// megafunction wizard: %RAM: 2-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: upd77c25_datrom.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 18.1.0 Build 625 09/12/2018 SJ Lite Edition // ************************************************************ //Copyright (C) 2018 Intel Corporation. All rights reserved. //Your use of Intel Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Intel Program License //Subscription Agreement, the Intel Quartus Prime License Agreement, //the Intel FPGA IP License Agreement, or other applicable license //agreement, including, without limitation, that your use is for //the sole purpose of programming logic devices manufactured by //Intel and sold by Intel or its authorized distributors. Please //refer to the applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module upd77c25_datrom ( clock, data, rdaddress, wraddress, wren, q); input clock; input [15:0] data; input [10:0] rdaddress; input [10:0] wraddress; input wren; output [15:0] q; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri1 clock; tri0 wren; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire [15:0] sub_wire0; wire [15:0] q = sub_wire0[15:0]; altsyncram altsyncram_component ( .address_a (wraddress), .address_b (rdaddress), .clock0 (clock), .data_a (data), .wren_a (wren), .q_b (sub_wire0), .aclr0 (1'b0), .aclr1 (1'b0), .addressstall_a (1'b0), .addressstall_b (1'b0), .byteena_a (1'b1), .byteena_b (1'b1), .clock1 (1'b1), .clocken0 (1'b1), .clocken1 (1'b1), .clocken2 (1'b1), .clocken3 (1'b1), .data_b ({16{1'b1}}), .eccstatus (), .q_a (), .rden_a (1'b1), .rden_b (1'b1), .wren_b (1'b0)); defparam altsyncram_component.address_aclr_b = "NONE", altsyncram_component.address_reg_b = "CLOCK0", altsyncram_component.clock_enable_input_a = "BYPASS", altsyncram_component.clock_enable_input_b = "BYPASS", altsyncram_component.clock_enable_output_b = "BYPASS", altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = 2048, altsyncram_component.numwords_b = 2048, altsyncram_component.operation_mode = "DUAL_PORT", altsyncram_component.outdata_aclr_b = "NONE", altsyncram_component.outdata_reg_b = "UNREGISTERED", altsyncram_component.power_up_uninitialized = "FALSE", altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", altsyncram_component.widthad_a = 11, altsyncram_component.widthad_b = 11, altsyncram_component.width_a = 16, altsyncram_component.width_b = 16, altsyncram_component.width_byteena_a = 1; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" // Retrieval info: PRIVATE: CLRdata NUMERIC "0" // Retrieval info: PRIVATE: CLRq NUMERIC "0" // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" // Retrieval info: PRIVATE: CLRrren NUMERIC "0" // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" // Retrieval info: PRIVATE: CLRwren NUMERIC "0" // Retrieval info: PRIVATE: Clock NUMERIC "0" // Retrieval info: PRIVATE: Clock_A NUMERIC "0" // Retrieval info: PRIVATE: Clock_B NUMERIC "0" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768" // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "" // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" // Retrieval info: PRIVATE: REGdata NUMERIC "1" // Retrieval info: PRIVATE: REGq NUMERIC "1" // Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" // Retrieval info: PRIVATE: REGrren NUMERIC "1" // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" // Retrieval info: PRIVATE: REGwren NUMERIC "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" // Retrieval info: PRIVATE: VarWidth NUMERIC "0" // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16" // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16" // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: enable NUMERIC "0" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048" // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" // Retrieval info: CONSTANT: WIDTH_B NUMERIC "16" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" // Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL "rdaddress[10..0]" // Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL "wraddress[10..0]" // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" // Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0 // Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0 // Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datrom.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datrom.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datrom.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datrom.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datrom_inst.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datrom_bb.v TRUE // Retrieval info: LIB_FILE: altera_mf
// megafunction wizard: %FIFO% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: scfifo // ============================================================ // File Name: sfifo_15x16.v // Megafunction Name(s): // scfifo // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 10.0 Build 262 08/18/2010 SP 1.191 SJ Full Version // ************************************************************ //Copyright (C) 1991-2010 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module sfifo_15x16 ( aclr, clock, data, rdreq, wrreq, almost_full, empty, full, q, usedw); input aclr; input clock; input [14:0] data; input rdreq; input wrreq; output almost_full; output empty; output full; output [14:0] q; output [3:0] usedw; wire [3:0] sub_wire0; wire sub_wire1; wire sub_wire2; wire [14:0] sub_wire3; wire sub_wire4; wire [3:0] usedw = sub_wire0[3:0]; wire empty = sub_wire1; wire full = sub_wire2; wire [14:0] q = sub_wire3[14:0]; wire almost_full = sub_wire4; scfifo scfifo_component ( .clock (clock), .wrreq (wrreq), .aclr (aclr), .data (data), .rdreq (rdreq), .usedw (sub_wire0), .empty (sub_wire1), .full (sub_wire2), .q (sub_wire3), .almost_full (sub_wire4), .almost_empty (), .sclr ()); defparam scfifo_component.add_ram_output_register = "OFF", scfifo_component.almost_full_value = 12, scfifo_component.intended_device_family = "Arria II GX", scfifo_component.lpm_numwords = 16, scfifo_component.lpm_showahead = "OFF", scfifo_component.lpm_type = "scfifo", scfifo_component.lpm_width = 15, scfifo_component.lpm_widthu = 4, scfifo_component.overflow_checking = "ON", scfifo_component.underflow_checking = "ON", scfifo_component.use_eab = "ON"; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" // Retrieval info: PRIVATE: AlmostFull NUMERIC "1" // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "12" // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" // Retrieval info: PRIVATE: Clock NUMERIC "0" // Retrieval info: PRIVATE: Depth NUMERIC "16" // Retrieval info: PRIVATE: Empty NUMERIC "1" // Retrieval info: PRIVATE: Full NUMERIC "1" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX" // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" // Retrieval info: PRIVATE: Optimize NUMERIC "2" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" // Retrieval info: PRIVATE: UsedW NUMERIC "1" // Retrieval info: PRIVATE: Width NUMERIC "15" // Retrieval info: PRIVATE: dc_aclr NUMERIC "0" // Retrieval info: PRIVATE: diff_widths NUMERIC "0" // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" // Retrieval info: PRIVATE: output_width NUMERIC "15" // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" // Retrieval info: PRIVATE: rsFull NUMERIC "0" // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" // Retrieval info: PRIVATE: sc_aclr NUMERIC "1" // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" // Retrieval info: PRIVATE: wsFull NUMERIC "1" // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" // Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "12" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX" // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16" // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" // Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "15" // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4" // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" // Retrieval info: CONSTANT: USE_EAB STRING "ON" // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" // Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" // Retrieval info: USED_PORT: data 0 0 15 0 INPUT NODEFVAL "data[14..0]" // Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" // Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full" // Retrieval info: USED_PORT: q 0 0 15 0 OUTPUT NODEFVAL "q[14..0]" // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" // Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]" // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @data 0 0 15 0 data 0 0 15 0 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 // Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0 // Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 // Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 // Retrieval info: CONNECT: q 0 0 15 0 @q 0 0 15 0 // Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0 // Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_15x16.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_15x16.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_15x16.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_15x16.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_15x16_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_15x16_bb.v TRUE // Retrieval info: LIB_FILE: altera_mf
module axis2buffer #( parameter DWIDTH = 32, parameter WIDTH = 8 )( // Control signals clk, rstn, // Color conversion signals alive_color, dead_color, // AXIS Connection S_AXIS_TDATA, S_AXIS_TVALID, S_AXIS_TREADY, S_AXIS_TLAST, // Output to conware computation out_data, out_valid, out_ready, num_reads, counter ); // Port descriptions input clk; input rstn; input [DWIDTH-1:0] alive_color; input [DWIDTH-1:0] dead_color; input [DWIDTH-1:0] S_AXIS_TDATA; input S_AXIS_TVALID; input S_AXIS_TLAST; output reg S_AXIS_TREADY; output reg [WIDTH-1:0] out_data; output reg out_valid; input out_ready; output reg [31:0] num_reads; reg next_num_reads; // State params reg state; reg next_state; localparam Wait = 0; localparam Read = 1; // Internal values reg in_state; output reg [7:0] counter; reg [7:0] next_counter; initial begin state <= Read; out_data <= 0; counter <= 0; num_reads <= 0; end // Combinational Logic always @* begin next_num_reads <= num_reads; if ((state == Read) && (S_AXIS_TVALID == 1)) begin in_state <= (S_AXIS_TDATA == alive_color)? 1'b1 : 1'b0; end else begin in_state <= out_data[counter]; end case (state) Wait: begin next_counter <= 0; S_AXIS_TREADY <= 0; out_valid <= 1; if (out_ready) begin next_state <= Read; end else begin next_state <= Wait; end end Read: begin S_AXIS_TREADY <= 1; next_state <= Read; out_valid <= 0; if (S_AXIS_TVALID == 1) begin if (counter == WIDTH-1) begin next_counter <= 0; next_state <= Wait; next_num_reads <= num_reads + 1; end else begin next_counter <= counter + 1; end end else begin // Data source stalled next_counter <= counter; end end endcase end // Clocked Logic always @(posedge clk) begin if (!rstn) begin counter <= 8'h00; state <= Read; num_reads <= 0; end else begin out_data[counter] <= in_state; state <= next_state; counter <= next_counter; num_reads <= next_num_reads; end end endmodule
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 13:55:30 03/10/2014 // Design Name: // Module Name: Frequency // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Frequency( input wire clk, input wire rst, input wire rand, output reg pass ); parameter N = 20000, U = 10182, L = 9818; reg [14:0] count_bits0, count_bits1, count_ones; always @(posedge clk) if (rst) begin count_bits0 <= 15'H7FFF; count_bits1 <= 0; count_ones <= 0; pass <= 0; end else begin count_bits0 <= count_bits0 + 1; count_bits1 <= count_bits0; if (count_bits0 == (N-1)) begin count_bits0 <= 0; end if (rand) count_ones <= count_ones + 1; if (count_bits1 == (N-1)) begin count_ones <= rand; if ((count_ones <= U) && (count_ones >= L)) pass <= 1; else pass <= 0; end end endmodule
(* Copyright © 1998-2006 * Henk Barendregt * Luís Cruz-Filipe * Herman Geuvers * Mariusz Giero * Rik van Ginneken * Dimitri Hendriks * Sébastien Hinderer * Bart Kirkels * Pierre Letouzey * Iris Loeb * Lionel Mamane * Milad Niqui * Russell O’Connor * Randy Pollack * Nickolay V. Shmyrev * Bas Spitters * Dan Synek * Freek Wiedijk * Jan Zwanenburg * * This work is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This work is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License along * with this work; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *) Require Export CoRN.algebra.CPoly_NthCoeff. Require Export CoRN.algebra.CFields. Require Export CoRN.tactics.Rational. Require Import Lia. Import CRing_Homomorphisms.coercions. Set Automatic Introduction. (** * Degrees of Polynomials ** Degrees of polynomials over a ring %\begin{convention}% Let [R] be a ring and write [RX] for the ring of polynomials over [R]. %\end{convention}% *) Section Degree_def. Variable R : CRing. (* begin hide *) Notation RX := (cpoly_cring R). (* end hide *) (** The length of a polynomial is the number of its coefficients. This is a syntactical property, as the highest coefficient may be [0]. Note that the `zero' polynomial [cpoly_zero] has length [0], a constant polynomial has length [1] and so forth. So the length is always [1] higher than the `degree' (assuming that the highest coefficient is [[#][0]])! *) Arguments cpoly_zero {CR}. Arguments cpoly_linear [CR]. Fixpoint lth_of_poly (p : RX) : nat := match p with | cpoly_zero => 0 | cpoly_linear d q => S (lth_of_poly q) end. (** When dealing with constructive polynomials, notably over the reals or complex numbers, the degree may be unknown, as we can not decide whether the highest coefficient is [[#][0]]. Hence, degree is a relation between polynomials and natural numbers; if the degree is unknown for polynomial [p], degree(n,p) doesn't hold for any [n]. If we don't know the degree of [p], we may still know it to be below or above a certain number. E.g. for the polynomial $p_0 +p_1 X +\cdots + p_{n-1} X^{n-1}$#p0 +p1 X + ... + p(n-1) X^(n-1)#, if $p_i \mathrel{\#}0$#pi apart from 0#, we can say that the `degree is at least [i]' and if $p_{j+1} = \ldots =p_n =0$#p(j+1) = ... =pn =0# (with [n] the length of the polynomial), we can say that the `degree is at most [j]'. *) Definition degree_le n (p : RX) : Prop := forall m, n < m -> nth_coeff m p [=] [0]. Definition degree n (p : RX) : CProp := nth_coeff n p [#] [0] and degree_le n p. Definition monic n (p : RX) : Prop := nth_coeff n p [=] [1] /\ degree_le n p. Definition odd_cpoly (p : RX) : CProp := {n : nat | Codd n | degree n p}. Definition even_cpoly (p : RX) : CProp := {n : nat | Ceven n | degree n p}. Definition regular (p : RX) : CProp := {n : nat | degree n p}. End Degree_def. Arguments degree_le [R]. Arguments degree [R]. Arguments monic [R]. Arguments lth_of_poly [R]. Section Degree_props. Variable R : CRing. Add Ring R: (CRing_Ring R). (* begin hide *) Notation RX := (cpoly_cring R). (* end hide *) Lemma degree_le_wd : forall (p p' : RX) n, p [=] p' -> degree_le n p -> degree_le n p'. Proof. unfold degree_le in |- *. intros. Step_final (nth_coeff m p). Qed. Lemma degree_wd : forall (p p' : RX) n, p [=] p' -> degree n p -> degree n p'. Proof. unfold degree in |- *. intros p p' n H H0. elim H0. clear H0. intros. split. astepl (nth_coeff n p). auto. apply degree_le_wd with p; auto. Qed. Lemma monic_wd : forall (p p' : RX) n, p [=] p' -> monic n p -> monic n p'. Proof. unfold monic in |- *. intros. elim H0. clear H0. intros. split. Step_final (nth_coeff n p). apply degree_le_wd with p; auto. Qed. Lemma degree_imp_degree_le : forall (p : RX) n, degree n p -> degree_le n p. Proof. unfold degree in |- *. intros p n H. elim H. auto. Qed. Lemma degree_le_cpoly_zero n: degree_le n (cpoly_zero R). Proof. intro. reflexivity. Qed. Lemma degree_le_c_ : forall c : R, degree_le 0 (_C_ c). Proof. unfold degree_le in |- *. intros c m. elim m; intros. elim (lt_irrefl _ H). simpl in |- *. algebra. Qed. Lemma degree_c_ : forall c : R, c [#] [0] -> degree 0 (_C_ c). Proof. unfold degree in |- *. intros. split. simpl in |- *. auto. apply degree_le_c_. Qed. Lemma monic_c_one : monic 0 (_C_ ([1]:R)). Proof. unfold monic in |- *. intros. split. simpl in |- *. algebra. apply degree_le_c_. Qed. Lemma degree_le_x_ : degree_le 1 (_X_:RX). Proof. unfold degree_le in |- *. intro. elim m. intros. elim (lt_n_O _ H). intro. elim n. intros. elim (lt_irrefl _ H0). intros. simpl in |- *. algebra. Qed. Lemma degree_x_ : degree 1 (_X_:RX). Proof. unfold degree in |- *. split. simpl in |- *. algebra. exact degree_le_x_. Qed. Lemma monic_x_ : monic 1 (_X_:RX). Proof. unfold monic in |- *. split. simpl in |- *. algebra. exact degree_le_x_. Qed. Lemma degree_le_mon : forall (p : RX) m n, m <= n -> degree_le m p -> degree_le n p. Proof. unfold degree_le in |- *. intros. apply H0. apply le_lt_trans with n; auto with arith. Qed. Lemma degree_le_inv : forall (p : RX) n, degree_le n p -> degree_le n [--]p. Proof. unfold degree_le in |- *. intros. astepl ( [--] (nth_coeff m p)). Step_final ( [--] ([0]:R)). Qed. Lemma degree_le_plus : forall (p q : RX) n, degree_le n p -> degree_le n q -> degree_le n (p[+]q). Proof. unfold degree_le in |- *. intros. astepl (nth_coeff m p[+]nth_coeff m q). Step_final ([0][+] ([0]:R)). Qed. Lemma degree_le_minus : forall (p q : RX) n, degree_le n p -> degree_le n q -> degree_le n (p[-]q). Proof. unfold degree_le in |- *. intros. astepl (nth_coeff m p[-]nth_coeff m q). Step_final ([0][-] ([0]:R)). Qed. Lemma Sum_degree_le : forall (f : nat -> RX) (n k l : nat), k <= S l -> (forall i, k <= i -> i <= l -> degree_le n (f i)) -> degree_le n (Sum k l f). Proof. unfold degree_le in |- *. intros. induction l as [| l Hrecl]; intros. generalize (toCle _ _ H); clear H; intro H. inversion H as [|m0 X]. unfold Sum in |- *. unfold Sum1 in |- *. simpl in |- *. apply eq_transitive with (nth_coeff m ([0]:RX)). apply nth_coeff_wd. algebra. algebra. inversion X. rename H3 into kis0. unfold Sum in |- *. unfold Sum1 in |- *. simpl in |- *. apply eq_transitive with (nth_coeff m (f 0)). apply nth_coeff_wd. cut (f 0[-][0] [=] f 0). auto. algebra. apply H0; try auto. rewrite kis0; auto. elim (le_lt_eq_dec _ _ H); intro y. apply eq_transitive_unfolded with (nth_coeff m (Sum k l f[+]f (S l))). apply nth_coeff_wd. algebra. astepl (nth_coeff m (Sum k l f) [+]nth_coeff m (f (S l))). astepr ([0][+] ([0]:R)). apply bin_op_wd_unfolded. apply Hrecl. auto with arith. intros. apply H0. auto. auto. auto. apply H0. auto with arith. auto. auto. rewrite y. unfold Sum in |- *. unfold Sum1 in |- *. simpl in |- *. apply eq_transitive_unfolded with (nth_coeff m ([0]:RX)). apply nth_coeff_wd. algebra. algebra. Qed. Lemma degree_le_Sum (l: list (cpoly R)) n: (forall p, In p l -> degree_le n p) -> degree_le n (cm_Sum l). Proof. induction l; intros. apply degree_le_cpoly_zero. change (degree_le n (a [+] cm_Sum l)). apply degree_le_plus; intuition. Qed. Lemma degree_inv : forall (p : RX) (n : nat), degree n p -> degree n [--]p. Proof. unfold degree in |- *. intros p n H. elim H. clear H. intros. split. astepl ( [--] (nth_coeff n p)). algebra. apply degree_le_inv; auto. Qed. Lemma degree_plus_rht : forall (p q : RX) m n, degree_le m p -> degree n q -> m < n -> degree n (p[+]q). Proof. unfold degree in |- *. unfold degree_le in |- *. intros. elim X. clear X. intros. split. astepl (nth_coeff n p[+]nth_coeff n q). astepl ([0][+]nth_coeff n q). astepl (nth_coeff n q). auto. intros. astepl (nth_coeff m0 p[+]nth_coeff m0 q). cut (m < m0). intro. Step_final ([0][+] ([0]:R)). apply lt_trans with n; auto. Qed. Lemma degree_minus_lft : forall (p q : RX) m n, degree_le m p -> degree n q -> m < n -> degree n (q[-]p). Proof. intros. apply degree_wd with ( [--]p[+]q). Step_final (q[+][--]p). apply degree_plus_rht with m. apply degree_le_inv. auto. auto. auto. Qed. Lemma monic_plus : forall (p q : RX) m n, degree_le m p -> monic n q -> m < n -> monic n (p[+]q). Proof. unfold monic in |- *. unfold degree_le in |- *. intros. elim H0. clear H0. intros. split. astepl (nth_coeff n p[+]nth_coeff n q). astepl ([0][+]nth_coeff n q). Step_final (nth_coeff n q). intros. astepl (nth_coeff m0 p[+]nth_coeff m0 q). cut (m < m0). intro. Step_final ([0][+] ([0]:R)). apply lt_trans with n; auto. Qed. Lemma monic_minus : forall (p q : RX) m n, degree_le m p -> monic n q -> m < n -> monic n (q[-]p). Proof. intros. apply monic_wd with ( [--]p[+]q). Step_final (q[+][--]p). apply monic_plus with m. apply degree_le_inv. auto. auto. auto. Qed. Lemma degree_le_mult : forall (p q : RX) m n, degree_le m p -> degree_le n q -> degree_le (m + n) (p[*]q). Proof. unfold degree_le in |- *. intros. astepl (Sum 0 m0 (fun i : nat => nth_coeff i p[*]nth_coeff (m0 - i) q)). apply Sum_zero. auto with arith. intros. cut ({m < i} + {n < m0 - i}). intro. elim H4; clear H4; intros. Step_final ([0][*]nth_coeff (m0 - i) q). Step_final (nth_coeff i p[*][0]). elim (lt_eq_lt_dec m i); intro. elim a; intro. auto. right. lia. right. lia. Qed. Lemma degree_le_Product (l: list (cpoly R)) n: (forall p, In p l -> degree_le n p) -> degree_le (length l * n) (cr_Product l). Proof. induction l; intros. apply (degree_le_c_ [1]). change (degree_le (n + length l * n) (a [*] cr_Product l)). apply degree_le_mult; intuition. Qed. Lemma degree_le_mult_constant_l (p: cpoly R) (x: R) (n: nat): degree_le n p -> degree_le n (_C_ x [*] p). Proof with auto. intros. replace n with (0 + n)%nat... apply degree_le_mult... apply degree_le_c_. Qed. Lemma degree_le_mult_constant_r (p: cpoly R) (x: R) (n: nat): degree_le n p -> degree_le n (p [*] _C_ x). Proof with auto. intros. replace n with (n + 0)%nat... apply degree_le_mult... apply degree_le_c_. Qed. Lemma degree_mult_aux : forall (p q : RX) m n, degree_le m p -> degree_le n q -> nth_coeff (m + n) (p[*]q) [=] nth_coeff m p[*]nth_coeff n q. Proof. unfold degree_le in |- *. intros. astepl (Sum 0 (m + n) (fun i : nat => nth_coeff i p[*]nth_coeff (m + n - i) q)). astepl (Sum 0 m (fun i : nat => nth_coeff i p[*]nth_coeff (m + n - i) q) [+] Sum (S m) (m + n) (fun i : nat => nth_coeff i p[*]nth_coeff (m + n - i) q)). astepr (nth_coeff m p[*]nth_coeff n q[+][0]). apply bin_op_wd_unfolded. elim (O_or_S m); intro y. elim y. clear y. intros x y. rewrite <- y in H. rewrite <- y. apply eq_transitive_unfolded with (Sum 0 x (fun i : nat => nth_coeff i p[*]nth_coeff (S x + n - i) q) [+] nth_coeff (S x) p[*]nth_coeff (S x + n - S x) q). apply Sum_last with (f := fun i : nat => nth_coeff i p[*]nth_coeff (S x + n - i) q). astepr ([0][+]nth_coeff (S x) p[*]nth_coeff n q). apply bin_op_wd_unfolded. apply Sum_zero. auto with arith. intros. cut (n < S x + n - i). intro. Step_final (nth_coeff i p[*][0]). lia. replace (S x + n - S x) with n. algebra. auto with arith. rewrite <- y in H. rewrite <- y. pattern n at 2 in |- *. replace n with (0 + n - 0). apply Sum_one with (f := fun i : nat => nth_coeff i p[*]nth_coeff (0 + n - i) q). auto with arith. apply Sum_zero. auto with arith. intros. cut (m < i). intro. Step_final ([0][*]nth_coeff (m + n - i) q). auto. Qed. Lemma lead_coeff_product_1 (n: nat) (l: list (cpoly R)): (forall p, In p l -> (nth_coeff n p [=] [1] /\ degree_le n p)) -> nth_coeff (length l * n) (cr_Product l) [=] [1]. Proof with auto. intro H. induction l. simpl. reflexivity. change (nth_coeff (n + length l * n) (a [*] cr_Product l)[=][1]). rewrite degree_mult_aux. setoid_replace (nth_coeff n a) with ([1]:R). rewrite IHl. apply mult_one. intros. apply H... apply H... apply H... apply degree_le_Product. intros. apply H... Qed. Hint Resolve degree_mult_aux: algebra. Lemma monic_mult : forall (p q : RX) m n, monic m p -> monic n q -> monic (m + n) (p[*]q). Proof. unfold monic in |- *. intros. elim H. clear H. intros. elim H0. clear H0. intros. split. astepl (nth_coeff m p[*]nth_coeff n q). Step_final ([1][*] ([1]:R)). apply degree_le_mult; auto. Qed. Lemma degree_le_nexp : forall (p : RX) m n, degree_le m p -> degree_le (m * n) (p[^]n). Proof. intros. induction n as [| n Hrecn]; intros. replace (m * 0) with 0. apply degree_le_wd with (_C_ ([1]:R)). algebra. apply degree_le_c_. auto. replace (m * S n) with (m * n + m). apply degree_le_wd with (p[^]n[*]p). algebra. apply degree_le_mult; auto. auto. Qed. Lemma monic_nexp : forall (p : RX) m n, monic m p -> monic (m * n) (p[^]n). Proof. intros. induction n as [| n Hrecn]; intros. replace (m * 0) with 0. apply monic_wd with (_C_ ([1]:R)). algebra. apply monic_c_one. auto. replace (m * S n) with (m * n + m). apply monic_wd with (p[^]n[*]p). algebra. apply monic_mult; auto. auto. Qed. Lemma lt_i_lth_of_poly : forall i (p : RX), nth_coeff i p [#] [0] -> i < lth_of_poly p. Proof. intros i. induction i as [| i Hreci]; intros; rename X into H. induction p as [| s p Hrecp]; intros. simpl in H. elim (ap_irreflexive_unfolded _ _ H). simpl in |- *. auto with arith. induction p as [| s p Hrecp]; intros. simpl in H. elim (ap_irreflexive_unfolded _ _ H). simpl in |- *. simpl in H. apply lt_n_S. auto. Qed. Lemma poly_degree_lth : forall p : RX, degree_le (lth_of_poly p) p. Proof. unfold degree_le in |- *. intros. apply not_ap_imp_eq. intro. elim (lt_not_le _ _ H). apply lt_le_weak. apply lt_i_lth_of_poly. auto. Qed. Lemma Cpoly_ex_degree : forall p : RX, {n : nat | degree_le n p}. Proof. intros. exists (lth_of_poly p). apply poly_degree_lth. Qed. Lemma poly_as_sum'' : forall (p : RX) n, degree_le n p -> p [=] Sum 0 n (fun i => _C_ (nth_coeff i p) [*]_X_[^]i). Proof. unfold degree_le in |- *. intros. apply all_nth_coeff_eq_imp. intros. apply eq_symmetric_unfolded. apply eq_transitive_unfolded with (Sum 0 n (fun i0 : nat => nth_coeff i (_C_ (nth_coeff i0 p) [*]_X_[^]i0))). apply nth_coeff_sum with (p_ := fun i : nat => _C_ (nth_coeff i p) [*]_X_[^]i). apply eq_transitive_unfolded with (Sum 0 n (fun i0 : nat => nth_coeff i0 p[*]nth_coeff i (_X_[^]i0))). apply Sum_wd. intros. algebra. elim (le_lt_dec i n); intros. astepr (nth_coeff i p[*][1]). astepr (nth_coeff i p[*]nth_coeff i (_X_[^]i)). apply Sum_term with (i := i) (f := fun i0 : nat => nth_coeff i0 p[*]nth_coeff i (_X_[^]i0)). auto with arith. auto. intros. Step_final (nth_coeff j p[*][0]). astepr ([0]:R). apply Sum_zero. auto with arith. intros. cut (i <> i0). intro. Step_final (nth_coeff i0 p[*][0]). intro; rewrite <- H2 in H1. apply (le_not_lt i n); auto. Qed. Hint Resolve poly_as_sum'': algebra. Lemma poly_as_sum' : forall p : RX, p [=] Sum 0 (lth_of_poly p) (fun i => _C_ (nth_coeff i p) [*]_X_[^]i). Proof. intros. apply poly_as_sum''. apply poly_degree_lth. Qed. Lemma poly_as_sum : forall (p : RX) n, degree_le n p -> forall x, p ! x [=] Sum 0 n (fun i => nth_coeff i p[*]x[^]i). Proof. intros. astepl (Sum 0 n (fun i : nat => _C_ (nth_coeff i p) [*]_X_[^]i)) ! x. apply eq_transitive_unfolded with (Sum 0 n (fun i : nat => (_C_ (nth_coeff i p) [*]_X_[^]i) ! x)). apply Sum_cpoly_ap with (f := fun i : nat => _C_ (nth_coeff i p) [*]_X_[^]i). apply Sum_wd. intros. astepl ((_C_ (nth_coeff i p)) ! x[*] (_X_[^]i) ! x). Step_final (nth_coeff i p[*]_X_ ! x[^]i). Qed. Lemma degree_le_zero : forall p : RX, degree_le 0 p -> {a : R | p [=] _C_ a}. Proof. unfold degree_le in |- *. intros. exists (nth_coeff 0 p). apply all_nth_coeff_eq_imp. intros. elim (O_or_S i); intro y. elim y. clear y. intros x y. rewrite <- y. cut (0 < S x). intro. Step_final ([0]:R). auto with arith. rewrite <- y. algebra. Qed. Lemma degree_le_1_imp : forall p : RX, degree_le 1 p -> {a : R | {b : R | p [=] _C_ a[*]_X_[+]_C_ b}}. Proof. unfold degree_le in |- *. intros. exists (nth_coeff 1 p). exists (nth_coeff 0 p). apply all_nth_coeff_eq_imp. intros. elim i; intros. simpl in |- *. ring. elim n; intros. simpl in |- *. algebra. simpl in |- *. apply H. auto with arith. Qed. Lemma degree_le_cpoly_linear : forall (p : cpoly R) c n, degree_le (S n) (c[+X*]p) -> degree_le n p. Proof. unfold degree_le in |- *. intros. change (nth_coeff (S m) (cpoly_linear _ c p) [=] [0]) in |- *. apply H. auto with arith. Qed. Lemma degree_le_cpoly_linear_inv (p: cpoly R) (c: R) (n: nat): degree_le n p -> degree_le (S n) (c[+X*]p). Proof. intros H [|m] E. inversion E. apply (H m). auto with arith. Qed. Lemma monic_cpoly_linear : forall (p : cpoly R) c n, monic (S n) (c[+X*]p) -> monic n p. Proof. unfold monic in |- *. intros. elim H. clear H. intros. split. auto. apply degree_le_cpoly_linear with c. auto. Qed. Lemma monic_one : forall (p : cpoly R) c, monic 1 (c[+X*]p) -> forall x, p ! x [=] [1]. Proof. intros. cut (monic 0 p). unfold monic in |- *. intros. elim H0. clear H0. intros H0 H1. elim (degree_le_zero _ H1). intro d. intros. astepl (_C_ d) ! x. astepl d. astepl (nth_coeff 0 (_C_ d)). Step_final (nth_coeff 0 p). apply monic_cpoly_linear with c. auto. Qed. Lemma monic_apzero : forall (p : RX) n, monic n p -> p [#] [0]. Proof. unfold monic in |- *. intros. elim H. clear H. intros. apply nth_coeff_ap_zero_imp with n. astepl ([1]:R). apply one_ap_zero. Qed. End Degree_props. Hint Resolve poly_as_sum'' poly_as_sum' poly_as_sum: algebra. Hint Resolve degree_mult_aux: algebra. Section degree_props_Field. (** ** Degrees of polynomials over a field %\begin{convention}% Let [F] be a field and write [FX] for the ring of polynomials over [F]. %\end{convention}% *) Variable F : CField. (* begin hide *) Notation FX := (cpoly_cring F). (* end hide *) Lemma degree_mult : forall (p q : FX) m n, degree m p -> degree n q -> degree (m + n) (p[*]q). Proof. unfold degree in |- *. intros. rename X into H. rename X0 into H0. elim H. clear H. intros H1 H2. elim H0. clear H0. intros H3 H4. split. astepl (nth_coeff m p[*]nth_coeff n q). algebra. apply degree_le_mult; auto. Qed. Lemma degree_nexp : forall (p : FX) m n, degree m p -> degree (m * n) (p[^]n). Proof. intros. induction n as [| n Hrecn]; intros. replace (m * 0) with 0. apply degree_wd with (_C_ ([1]:F)). algebra. apply degree_c_. algebra. auto. replace (m * S n) with (m * n + m). apply degree_wd with (p[^]n[*]p). algebra. apply degree_mult; auto. auto. Qed. Lemma degree_le_mult_imp : forall (p q : FX) m n, degree m p -> degree_le (m + n) (p[*]q) -> degree_le n q. Proof. unfold degree in |- *. unfold degree_le in |- *. intros. rename H0 into H1. rename H into H0. rename X into H. elim H. clear H. intros H2 H3. elim (Cpoly_ex_degree _ q). unfold degree_le in |- *. intro N. intro H4. (* Set_ not necessary *) cut (forall k i : nat, n < i -> N - k < i -> nth_coeff i q [=] [0]). intro H5. elim (le_lt_dec m0 N); intros H6. replace m0 with (N - (N - m0)). apply H5 with (N - n). lia. lia. lia. apply H4; auto. intro. induction k as [| k Hreck]; intros. apply H4. rewrite <- minus_n_O in H5; auto. elim (le_lt_eq_dec (N - k) i); try intro y. auto. rewrite y in Hreck. apply mult_cancel_lft with (nth_coeff m p). auto. astepr ([0]:F). apply eq_transitive_unfolded with (Sum 0 (m + i) (fun j : nat => nth_coeff j p[*]nth_coeff (m + i - j) q)). pattern i at 1 in |- *. replace i with (m + i - m). apply eq_symmetric_unfolded. apply Sum_term with (f := fun j : nat => nth_coeff j p[*]nth_coeff (m + i - j) q). auto with arith. auto with arith. intros. elim (le_lt_dec j m); intros. cut (i < m + i - j). intro. cut (n < m + i - j). intro. Step_final (nth_coeff j p[*][0]). lia. lia. Step_final ([0][*]nth_coeff (m + i - j) q). auto with arith. astepl (nth_coeff (m + i) (p[*]q)). cut (m + n < m + i). intro. auto. auto with arith. lia. Qed. Lemma degree_mult_imp : forall (p q : FX) m n, degree m p -> degree (m + n) (p[*]q) -> degree n q. Proof. unfold degree in |- *. intros. rename X into H. rename X0 into H0. elim H. clear H. intros H H1. elim H0. clear H0. intros H0 H2. cut (degree_le n q). intro H3. split. apply mult_cancel_ap_zero_rht with (nth_coeff m p). astepl (nth_coeff (m + n) (p[*]q)). auto. assumption. apply degree_le_mult_imp with p m; auto. unfold degree in |- *. split. auto. assumption. Qed. End degree_props_Field.
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LS__EINVP_FUNCTIONAL_V `define SKY130_FD_SC_LS__EINVP_FUNCTIONAL_V /** * einvp: Tri-state inverter, positive enable. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none `celldefine module sky130_fd_sc_ls__einvp ( Z , A , TE ); // Module ports output Z ; input A ; input TE; // Name Output Other arguments notif1 notif10 (Z , A, TE ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_LS__EINVP_FUNCTIONAL_V
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Wilson Snyder. `define STRINGIFY(x) `"x`" `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); //====================================================================== module t; integer file; integer r_i; byte r_upb[20:10]; byte r_dnb[20:10]; reg [13:0] r_ups[20:10]; reg [13:0] r_dns[10:20]; reg [30:0] r_upi[20:10]; reg [30:0] r_dni[10:20]; reg [61:0] r_upq[20:10]; reg [61:0] r_dnq[10:20]; reg [71:0] r_upw[20:10]; reg [71:0] r_dnw[10:20]; task clear; // Initialize memories to zero, // avoid differences between 2-state and 4-state. r_i = ~0; foreach (r_upb[i]) r_upb[i] = ~0; foreach (r_dnb[i]) r_dnb[i] = ~0; foreach (r_ups[i]) r_ups[i] = ~0; foreach (r_dns[i]) r_dns[i] = ~0; foreach (r_upi[i]) r_upi[i] = ~0; foreach (r_dni[i]) r_dni[i] = ~0; foreach (r_upq[i]) r_upq[i] = ~0; foreach (r_dnq[i]) r_dnq[i] = ~0; foreach (r_upw[i]) r_upw[i] = ~0; foreach (r_dnw[i]) r_dnw[i] = ~0; // Open file $fclose(file); file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_fread.mem"}, "r"); if ($feof(file)) $stop; endtask task dump; $write("Dump:"); $write("\n r_i:"); $write(" %x",r_i); $write("\n r_upb:"); foreach (r_upb[i]) $write(" %x", r_upb[i]); $write("\n r_dnb:"); foreach (r_dnb[i]) $write(" %x", r_dnb[i]); $write("\n r_ups:"); foreach (r_ups[i]) $write(" %x", r_ups[i]); $write("\n r_dns:"); foreach (r_dns[i]) $write(" %x", r_dns[i]); $write("\n r_upi:"); foreach (r_upi[i]) $write(" %x", r_upi[i]); $write("\n r_dni:"); foreach (r_dni[i]) $write(" %x", r_dni[i]); $write("\n r_upq:"); foreach (r_upq[i]) $write(" %x", r_upq[i]); $write("\n r_dnq:"); foreach (r_dnq[i]) $write(" %x", r_dnq[i]); $write("\n r_upw:"); foreach (r_upw[i]) $write(" %x", r_upw[i]); $write("\n r_dnw:"); foreach (r_dnw[i]) $write(" %x", r_dnw[i]); $write("\n\n"); endtask integer code; initial begin clear; code = $fread(r_i, file); `checkd(code, 4); code = $fread(r_upb, file); `checkd(code, 11); code = $fread(r_dnb, file); `checkd(code, 11); code = $fread(r_ups, file); `checkd(code, 22); code = $fread(r_dns, file); `checkd(code, 22); code = $fread(r_upi, file); `checkd(code, 44); code = $fread(r_dni, file); `checkd(code, 44); code = $fread(r_upq, file); `checkd(code, 88); code = $fread(r_dnq, file); `checkd(code, 88); code = $fread(r_upw, file); `checkd(code, 99); code = $fread(r_dnw, file); `checkd(code, 99); dump; clear; code = $fread(r_upb, file, 15); `checkd(code, 6); code = $fread(r_ups, file, 15, 2); `checkd(code, 4); dump; $write("*-* All Finished *-*\n"); $finish; end endmodule
// megafunction wizard: %FIFO% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: scfifo // ============================================================ // File Name: ff_40x32_fwft.v // Megafunction Name(s): // scfifo // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 13.1.0 Build 162 10/23/2013 SJ Web Edition // ************************************************************ //Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module ff_40x32_fwft ( aclr, clock, data, rdreq, wrreq, empty, full, q, usedw); input aclr; input clock; input [39:0] data; input rdreq; input wrreq; output empty; output full; output [39:0] q; output [4:0] usedw; wire [4:0] sub_wire0; wire sub_wire1; wire sub_wire2; wire [39:0] sub_wire3; wire [4:0] usedw = sub_wire0[4:0]; wire empty = sub_wire1; wire full = sub_wire2; wire [39:0] q = sub_wire3[39:0]; scfifo scfifo_component ( .clock (clock), .wrreq (wrreq), .aclr (aclr), .data (data), .rdreq (rdreq), .usedw (sub_wire0), .empty (sub_wire1), .full (sub_wire2), .q (sub_wire3), .almost_empty (), .almost_full (), .sclr ()); defparam scfifo_component.add_ram_output_register = "ON", scfifo_component.intended_device_family = "Cyclone V", scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB", scfifo_component.lpm_numwords = 32, scfifo_component.lpm_showahead = "ON", scfifo_component.lpm_type = "scfifo", scfifo_component.lpm_width = 40, scfifo_component.lpm_widthu = 5, scfifo_component.overflow_checking = "ON", scfifo_component.underflow_checking = "ON", scfifo_component.use_eab = "ON"; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" // Retrieval info: PRIVATE: Clock NUMERIC "0" // Retrieval info: PRIVATE: Depth NUMERIC "32" // Retrieval info: PRIVATE: Empty NUMERIC "1" // Retrieval info: PRIVATE: Full NUMERIC "1" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" // Retrieval info: PRIVATE: Optimize NUMERIC "1" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" // Retrieval info: PRIVATE: UsedW NUMERIC "1" // Retrieval info: PRIVATE: Width NUMERIC "40" // Retrieval info: PRIVATE: dc_aclr NUMERIC "0" // Retrieval info: PRIVATE: diff_widths NUMERIC "0" // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" // Retrieval info: PRIVATE: output_width NUMERIC "40" // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" // Retrieval info: PRIVATE: rsFull NUMERIC "0" // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" // Retrieval info: PRIVATE: sc_aclr NUMERIC "1" // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" // Retrieval info: PRIVATE: wsFull NUMERIC "1" // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" // Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=MLAB" // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32" // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" // Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "40" // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5" // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" // Retrieval info: CONSTANT: USE_EAB STRING "ON" // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" // Retrieval info: USED_PORT: data 0 0 40 0 INPUT NODEFVAL "data[39..0]" // Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" // Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full" // Retrieval info: USED_PORT: q 0 0 40 0 OUTPUT NODEFVAL "q[39..0]" // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" // Retrieval info: USED_PORT: usedw 0 0 5 0 OUTPUT NODEFVAL "usedw[4..0]" // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @data 0 0 40 0 data 0 0 40 0 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 // Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 // Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 // Retrieval info: CONNECT: q 0 0 40 0 @q 0 0 40 0 // Retrieval info: CONNECT: usedw 0 0 5 0 @usedw 0 0 5 0 // Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft_bb.v FALSE // Retrieval info: LIB_FILE: altera_mf
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_MS__O22A_PP_SYMBOL_V `define SKY130_FD_SC_MS__O22A_PP_SYMBOL_V /** * o22a: 2-input OR into both inputs of 2-input AND. * * X = ((A1 | A2) & (B1 | B2)) * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_ms__o22a ( //# {{data|Data Signals}} input A1 , input A2 , input B1 , input B2 , output X , //# {{power|Power}} input VPB , input VPWR, input VGND, input VNB ); endmodule `default_nettype wire `endif // SKY130_FD_SC_MS__O22A_PP_SYMBOL_V
//----------------------------------------------------------------------------- // // (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // // Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express // File : pcie3_7x_0_pcie_pipe_lane.v // Version : 3.0 //----------------------------------------------------------------------------// // Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express // // Filename : pcie3_7x_0_pcie_pipe_lane.v // // Description : Implements the PIPE interface PIPELINE for all per lane // // interface signals // //---------- PIPE Wrapper Hierarchy ------------------------------------------// // pcie_pipe_lane.v // //----------------------------------------------------------------------------// `timescale 1ps/1ps module pcie3_7x_0_pcie_pipe_lane # ( parameter TCQ = 100, parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages ) ( output wire [ 1:0] pipe_rx_char_is_k_o ,// Pipelined PIPE Rx Char Is K output wire [31:0] pipe_rx_data_o ,// Pipelined PIPE Rx Data output wire pipe_rx_valid_o ,// Pipelined PIPE Rx Valid output wire pipe_rx_data_valid_o ,// Pipelined PIPE Rx Data Valid output wire [ 2:0] pipe_rx_status_o ,// Pipelined PIPE Rx Status output wire pipe_rx_phy_status_o ,// Pipelined PIPE Rx Phy Status output wire pipe_rx_elec_idle_o ,// Pipelined PIPE Rx Electrical Idle output wire pipe_rx_eqdone_o ,// Pipelined PIPE Rx Eq output wire pipe_rx_eqlpadaptdone_o ,// Pipelined PIPE Rx Eq output wire pipe_rx_eqlplffssel_o ,// Pipelined PIPE Rx Eq output wire [17:0] pipe_rx_eqlpnewtxcoefforpreset_o,// Pipelined PIPE Rx Eq output wire pipe_rx_startblock_o ,// Pipelined PIPE Rx Start Block output wire [ 1:0] pipe_rx_syncheader_o ,// Pipelined PIPE Rx Sync Header output wire pipe_rx_slide_o ,// Pipelined PIPE Rx Slide output wire pipe_rx_syncdone_o ,// Pipelined PIPE Rx Sync done input wire pipe_rx_polarity_i ,// PIPE Rx Polarity input wire [ 1:0] pipe_rx_eqcontrol_i ,// PIPE Rx Eq control input wire [ 5:0] pipe_rx_eqlplffs_i ,// PIPE Rx Eq input wire [ 3:0] pipe_rx_eqlptxpreset_i ,// PIPE Rx Eq input wire [ 2:0] pipe_rx_eqpreset_i ,// PIPE Rx Eq output wire [17:0] pipe_tx_eqcoeff_o ,// Pipelined Tx Eq Coefficient output wire pipe_tx_eqdone_o ,// Pipelined Tx Eq Done input wire pipe_tx_compliance_i ,// PIPE Tx Compliance input wire [ 1:0] pipe_tx_char_is_k_i ,// PIPE Tx Char Is K input wire [31:0] pipe_tx_data_i ,// PIPE Tx Data input wire pipe_tx_elec_idle_i ,// PIPE Tx Electrical Idle input wire [ 1:0] pipe_tx_powerdown_i ,// PIPE Tx Powerdown input wire pipe_tx_datavalid_i ,// PIPE Tx Data Valid input wire pipe_tx_startblock_i ,// PIPE Tx Start Block input wire [ 1:0] pipe_tx_syncheader_i ,// PIPE Tx Sync Header input wire [ 1:0] pipe_tx_eqcontrol_i ,// PIPE Tx Eq Control input wire [ 5:0] pipe_tx_eqdeemph_i ,// PIPE Tx Eq Deemphesis input wire [ 3:0] pipe_tx_eqpreset_i ,// PIPE Tx Preset input wire [ 1:0] pipe_rx_char_is_k_i ,// PIPE Rx Char Is K input wire [31:0] pipe_rx_data_i ,// PIPE Rx Data input wire pipe_rx_valid_i ,// PIPE Rx Valid input wire pipe_rx_data_valid_i ,// PIPE Rx Data Valid input wire [ 2:0] pipe_rx_status_i ,// PIPE Rx Status input wire pipe_rx_phy_status_i ,// PIPE Rx Phy Status input wire pipe_rx_elec_idle_i ,// PIPE Rx Electrical Idle input wire pipe_rx_eqdone_i ,// PIPE Rx Eq input wire pipe_rx_eqlpadaptdone_i ,// PIPE Rx Eq input wire pipe_rx_eqlplffssel_i ,// PIPE Rx Eq input wire [17:0] pipe_rx_eqlpnewtxcoefforpreset_i,// PIPE Rx Eq input wire pipe_rx_startblock_i ,// PIPE Rx Start Block input wire [ 1:0] pipe_rx_syncheader_i ,// PIPE Rx Sync Header input wire pipe_rx_slide_i ,// PIPE Rx Slide input wire pipe_rx_syncdone_i ,// PIPE Rx Sync done output wire pipe_rx_polarity_o ,// Pipelined PIPE Rx Polarity output wire [ 1:0] pipe_rx_eqcontrol_o ,// Pipelined PIPE Rx Eq control output wire [ 5:0] pipe_rx_eqlplffs_o ,// Pipelined PIPE Rx Eq output wire [ 3:0] pipe_rx_eqlptxpreset_o ,// Pipelined PIPE Rx Eq output wire [ 2:0] pipe_rx_eqpreset_o ,// Pipelined PIPE Rx Eq input wire [17:0] pipe_tx_eqcoeff_i ,// PIPE Tx Eq Coefficient input wire pipe_tx_eqdone_i ,// PIPE Tx Eq Done output wire pipe_tx_compliance_o ,// Pipelined PIPE Tx Compliance output wire [ 1:0] pipe_tx_char_is_k_o ,// Pipelined PIPE Tx Char Is K output wire [31:0] pipe_tx_data_o ,// Pipelined PIPE Tx Data output wire pipe_tx_elec_idle_o ,// Pipelined PIPE Tx Electrical Idle output wire [ 1:0] pipe_tx_powerdown_o ,// Pipelined PIPE Tx Powerdown output wire pipe_tx_datavalid_o ,// Pipelined PIPE Tx Data Valid output wire pipe_tx_startblock_o ,// Pipelined PIPE Tx Start Block output wire [ 1:0] pipe_tx_syncheader_o ,// Pipelined PIPE Tx Sync Header output wire [ 1:0] pipe_tx_eqcontrol_o ,// Pipelined PIPE Tx Eq Control output wire [ 5:0] pipe_tx_eqdeemph_o ,// Pipelined PIPE Tx Eq Deemphesis output wire [ 3:0] pipe_tx_eqpreset_o ,// Pipelined PIPE Tx Preset input wire pipe_clk ,// PIPE Clock input wire rst_n // Reset ); //******************************************************************// // Reality check. // //******************************************************************// reg [ 1:0] pipe_rx_char_is_k_q ; reg [31:0] pipe_rx_data_q ; reg pipe_rx_valid_q ; reg pipe_rx_data_valid_q ; reg [ 2:0] pipe_rx_status_q ; reg pipe_rx_phy_status_q ; reg pipe_rx_elec_idle_q ; reg pipe_rx_eqdone_q ; reg pipe_rx_eqlpadaptdone_q ; reg pipe_rx_eqlplffssel_q ; reg [17:0] pipe_rx_eqlpnewtxcoefforpreset_q ; reg pipe_rx_startblock_q ; reg [ 1:0] pipe_rx_syncheader_q ; reg pipe_rx_slide_q ; reg pipe_rx_syncdone_q ; reg pipe_rx_polarity_q ; reg [ 1:0] pipe_rx_eqcontrol_q ; reg [ 5:0] pipe_rx_eqlplffs_q ; reg [ 3:0] pipe_rx_eqlptxpreset_q ; reg [ 2:0] pipe_rx_eqpreset_q ; reg [17:0] pipe_tx_eqcoeff_q ; reg pipe_tx_eqdone_q ; reg pipe_tx_compliance_q ; reg [ 1:0] pipe_tx_char_is_k_q ; reg [31:0] pipe_tx_data_q ; reg pipe_tx_elec_idle_q ; reg [ 1:0] pipe_tx_powerdown_q ; reg pipe_tx_datavalid_q ; reg pipe_tx_startblock_q ; reg [ 1:0] pipe_tx_syncheader_q ; reg [ 1:0] pipe_tx_eqcontrol_q ; reg [ 5:0] pipe_tx_eqdeemph_q ; reg [ 3:0] pipe_tx_eqpreset_q ; reg [ 1:0] pipe_rx_char_is_k_qq ; reg [31:0] pipe_rx_data_qq ; reg pipe_rx_valid_qq ; reg pipe_rx_data_valid_qq ; reg [ 2:0] pipe_rx_status_qq ; reg pipe_rx_phy_status_qq ; reg pipe_rx_elec_idle_qq ; reg pipe_rx_eqdone_qq ; reg pipe_rx_eqlpadaptdone_qq ; reg pipe_rx_eqlplffssel_qq ; reg [17:0] pipe_rx_eqlpnewtxcoefforpreset_qq ; reg pipe_rx_startblock_qq ; reg [ 1:0] pipe_rx_syncheader_qq ; reg pipe_rx_slide_qq ; reg pipe_rx_syncdone_qq ; reg pipe_rx_polarity_qq ; reg [ 1:0] pipe_rx_eqcontrol_qq ; reg [ 5:0] pipe_rx_eqlplffs_qq ; reg [ 3:0] pipe_rx_eqlptxpreset_qq ; reg [ 2:0] pipe_rx_eqpreset_qq ; reg [17:0] pipe_tx_eqcoeff_qq ; reg pipe_tx_eqdone_qq ; reg pipe_tx_compliance_qq ; reg [ 1:0] pipe_tx_char_is_k_qq ; reg [31:0] pipe_tx_data_qq ; reg pipe_tx_elec_idle_qq ; reg [ 1:0] pipe_tx_powerdown_qq ; reg pipe_tx_datavalid_qq ; reg pipe_tx_startblock_qq ; reg [ 1:0] pipe_tx_syncheader_qq ; reg [ 1:0] pipe_tx_eqcontrol_qq ; reg [ 5:0] pipe_tx_eqdeemph_qq ; reg [ 3:0] pipe_tx_eqpreset_qq ; generate if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0 assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i ; assign pipe_rx_data_o = pipe_rx_data_i ; assign pipe_rx_valid_o = pipe_rx_valid_i ; assign pipe_rx_data_valid_o = pipe_rx_data_valid_i ; assign pipe_rx_status_o = pipe_rx_status_i ; assign pipe_rx_phy_status_o = pipe_rx_phy_status_i ; assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i ; assign pipe_rx_eqdone_o = pipe_rx_eqdone_i ; assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_i ; assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_i ; assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_i ; assign pipe_rx_startblock_o = pipe_rx_startblock_i ; assign pipe_rx_syncheader_o = pipe_rx_syncheader_i ; assign pipe_rx_slide_o = pipe_rx_slide_i ; assign pipe_rx_syncdone_o = pipe_rx_syncdone_i ; assign pipe_rx_polarity_o = pipe_rx_polarity_i ; assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_i ; assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_i ; assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_i ; assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_i ; assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_i ; assign pipe_tx_eqdone_o = pipe_tx_eqdone_i ; assign pipe_tx_compliance_o = pipe_tx_compliance_i ; assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i ; assign pipe_tx_data_o = pipe_tx_data_i ; assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i ; assign pipe_tx_powerdown_o = pipe_tx_powerdown_i ; assign pipe_tx_datavalid_o = pipe_tx_datavalid_i ; assign pipe_tx_startblock_o = pipe_tx_startblock_i ; assign pipe_tx_syncheader_o = pipe_tx_syncheader_i ; assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_i ; assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_i ; assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_i ; end // if (PIPE_PIPELINE_STAGES == 0) else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1 always @(posedge pipe_clk) begin if (!rst_n) begin pipe_rx_char_is_k_q <= #TCQ 2'b00; pipe_rx_data_q <= #TCQ 32'h00000000; pipe_rx_valid_q <= #TCQ 1'b0; pipe_rx_data_valid_q <= #TCQ 1'b0; pipe_rx_status_q <= #TCQ 2'b00; pipe_rx_phy_status_q <= #TCQ 1'b0; pipe_rx_elec_idle_q <= #TCQ 1'b1; pipe_rx_eqdone_q <= #TCQ 1'b0; pipe_rx_eqlpadaptdone_q <= #TCQ 1'b0; pipe_rx_eqlplffssel_q <= #TCQ 1'b0; pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ 17'b00000000000000000; pipe_rx_startblock_q <= #TCQ 1'b0; pipe_rx_syncheader_q <= #TCQ 2'b00; pipe_rx_slide_q <= #TCQ 1'b0; pipe_rx_syncdone_q <= #TCQ 1'b0; pipe_rx_polarity_q <= #TCQ 17'b00000000000000000; pipe_rx_eqcontrol_q <= #TCQ 1'b0; pipe_rx_eqlplffs_q <= #TCQ 1'b0; pipe_rx_eqlptxpreset_q <= #TCQ 2'b00; pipe_rx_eqpreset_q <= #TCQ 6'b000000; pipe_tx_eqcoeff_q <= #TCQ 4'h0; pipe_tx_eqdone_q <= #TCQ 3'b000; pipe_tx_compliance_q <= #TCQ 1'b0; pipe_tx_char_is_k_q <= #TCQ 2'b00; pipe_tx_data_q <= #TCQ 32'h00000000; pipe_tx_elec_idle_q <= #TCQ 1'b1; pipe_tx_powerdown_q <= #TCQ 2'b00; pipe_tx_datavalid_q <= #TCQ 1'b0; pipe_tx_startblock_q <= #TCQ 1'b0; pipe_tx_syncheader_q <= #TCQ 2'b00; pipe_tx_eqcontrol_q <= #TCQ 2'b00; pipe_tx_eqdeemph_q <= #TCQ 6'b000000; pipe_tx_eqpreset_q <= #TCQ 4'h0; end else begin pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i ; pipe_rx_data_q <= #TCQ pipe_rx_data_i ; pipe_rx_valid_q <= #TCQ pipe_rx_valid_i ; pipe_rx_data_valid_q <= #TCQ pipe_rx_data_valid_i ; pipe_rx_status_q <= #TCQ pipe_rx_status_i ; pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i ; pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i ; pipe_rx_eqdone_q <= #TCQ pipe_rx_eqdone_i ; pipe_rx_eqlpadaptdone_q <= #TCQ pipe_rx_eqlpadaptdone_i ; pipe_rx_eqlplffssel_q <= #TCQ pipe_rx_eqlplffssel_i ; pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ pipe_rx_eqlpnewtxcoefforpreset_i ; pipe_rx_startblock_q <= #TCQ pipe_rx_startblock_i ; pipe_rx_syncheader_q <= #TCQ pipe_rx_syncheader_i ; pipe_rx_slide_q <= #TCQ pipe_rx_slide_i ; pipe_rx_syncdone_q <= #TCQ pipe_rx_syncdone_i ; pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i ; pipe_rx_eqcontrol_q <= #TCQ pipe_rx_eqcontrol_i ; pipe_rx_eqlplffs_q <= #TCQ pipe_rx_eqlplffs_i ; pipe_rx_eqlptxpreset_q <= #TCQ pipe_rx_eqlptxpreset_i ; pipe_rx_eqpreset_q <= #TCQ pipe_rx_eqpreset_i ; pipe_tx_eqcoeff_q <= #TCQ pipe_tx_eqcoeff_i ; pipe_tx_eqdone_q <= #TCQ pipe_tx_eqdone_i ; pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i ; pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i ; pipe_tx_data_q <= #TCQ pipe_tx_data_i ; pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i ; pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i ; pipe_tx_datavalid_q <= #TCQ pipe_tx_datavalid_i ; pipe_tx_startblock_q <= #TCQ pipe_tx_startblock_i ; pipe_tx_syncheader_q <= #TCQ pipe_tx_syncheader_i ; pipe_tx_eqcontrol_q <= #TCQ pipe_tx_eqcontrol_i ; pipe_tx_eqdeemph_q <= #TCQ pipe_tx_eqdeemph_i ; pipe_tx_eqpreset_q <= #TCQ pipe_tx_eqpreset_i ; end end assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_q ; assign pipe_rx_data_o = pipe_rx_data_q ; assign pipe_rx_valid_o = pipe_rx_valid_q ; assign pipe_rx_data_valid_o = pipe_rx_data_valid_q ; assign pipe_rx_status_o = pipe_rx_status_q ; assign pipe_rx_phy_status_o = pipe_rx_phy_status_q ; assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_q ; assign pipe_rx_eqdone_o = pipe_rx_eqdone_q ; assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_q ; assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_q ; assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_q ; assign pipe_rx_startblock_o = pipe_rx_startblock_q ; assign pipe_rx_syncheader_o = pipe_rx_syncheader_q ; assign pipe_rx_slide_o = pipe_rx_slide_q ; assign pipe_rx_syncdone_o = pipe_rx_syncdone_q ; assign pipe_rx_polarity_o = pipe_rx_polarity_q ; assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_q ; assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_q ; assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_q ; assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_q ; assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_q ; assign pipe_tx_eqdone_o = pipe_tx_eqdone_q ; assign pipe_tx_compliance_o = pipe_tx_compliance_q ; assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_q ; assign pipe_tx_data_o = pipe_tx_data_q ; assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_q ; assign pipe_tx_powerdown_o = pipe_tx_powerdown_q ; assign pipe_tx_datavalid_o = pipe_tx_datavalid_q ; assign pipe_tx_startblock_o = pipe_tx_startblock_q ; assign pipe_tx_syncheader_o = pipe_tx_syncheader_q ; assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_q ; assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_q ; assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_q ; end // if (PIPE_PIPELINE_STAGES == 1) else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2 always @(posedge pipe_clk) begin if (!rst_n) begin pipe_rx_char_is_k_q <= #TCQ 2'b00; pipe_rx_data_q <= #TCQ 32'h00000000; pipe_rx_valid_q <= #TCQ 1'b0; pipe_rx_data_valid_q <= #TCQ 1'b0; pipe_rx_status_q <= #TCQ 2'b00; pipe_rx_phy_status_q <= #TCQ 1'b0; pipe_rx_elec_idle_q <= #TCQ 1'b1; pipe_rx_eqdone_q <= #TCQ 1'b0; pipe_rx_eqlpadaptdone_q <= #TCQ 1'b0; pipe_rx_eqlplffssel_q <= #TCQ 1'b0; pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ 17'b00000000000000000; pipe_rx_startblock_q <= #TCQ 1'b0; pipe_rx_syncheader_q <= #TCQ 2'b00; pipe_rx_slide_q <= #TCQ 1'b0; pipe_rx_syncdone_q <= #TCQ 1'b0; pipe_rx_polarity_q <= #TCQ 17'b00000000000000000; pipe_rx_eqcontrol_q <= #TCQ 1'b0; pipe_rx_eqlplffs_q <= #TCQ 1'b0; pipe_rx_eqlptxpreset_q <= #TCQ 2'b00; pipe_rx_eqpreset_q <= #TCQ 6'b000000; pipe_tx_eqcoeff_q <= #TCQ 4'h0; pipe_tx_eqdone_q <= #TCQ 3'b000; pipe_tx_compliance_q <= #TCQ 1'b0; pipe_tx_char_is_k_q <= #TCQ 2'b00; pipe_tx_data_q <= #TCQ 32'h00000000; pipe_tx_elec_idle_q <= #TCQ 1'b1; pipe_tx_powerdown_q <= #TCQ 2'b00; pipe_tx_datavalid_q <= #TCQ 1'b0; pipe_tx_startblock_q <= #TCQ 1'b0; pipe_tx_syncheader_q <= #TCQ 2'b00; pipe_tx_eqcontrol_q <= #TCQ 2'b00; pipe_tx_eqdeemph_q <= #TCQ 6'b000000; pipe_tx_eqpreset_q <= #TCQ 4'h0; pipe_rx_char_is_k_qq <= #TCQ 2'b00; pipe_rx_data_qq <= #TCQ 32'h00000000; pipe_rx_valid_qq <= #TCQ 1'b0; pipe_rx_data_valid_qq <= #TCQ 1'b0; pipe_rx_status_qq <= #TCQ 2'b00; pipe_rx_phy_status_qq <= #TCQ 1'b0; pipe_rx_elec_idle_qq <= #TCQ 1'b1; pipe_rx_eqdone_qq <= #TCQ 1'b0; pipe_rx_eqlpadaptdone_qq <= #TCQ 1'b0; pipe_rx_eqlplffssel_qq <= #TCQ 1'b0; pipe_rx_eqlpnewtxcoefforpreset_qq<= #TCQ 17'b00000000000000000; pipe_rx_startblock_qq <= #TCQ 1'b0; pipe_rx_syncheader_qq <= #TCQ 2'b00; pipe_rx_slide_qq <= #TCQ 1'b0; pipe_rx_syncdone_qq <= #TCQ 1'b0; pipe_rx_polarity_qq <= #TCQ 17'b00000000000000000; pipe_rx_eqcontrol_qq <= #TCQ 1'b0; pipe_rx_eqlplffs_qq <= #TCQ 1'b0; pipe_rx_eqlptxpreset_qq <= #TCQ 2'b00; pipe_rx_eqpreset_qq <= #TCQ 6'b000000; pipe_tx_eqcoeff_qq <= #TCQ 4'h0; pipe_tx_eqdone_qq <= #TCQ 3'b000; pipe_tx_compliance_qq <= #TCQ 1'b0; pipe_tx_char_is_k_qq <= #TCQ 2'b00; pipe_tx_data_qq <= #TCQ 32'h00000000; pipe_tx_elec_idle_qq <= #TCQ 1'b1; pipe_tx_powerdown_qq <= #TCQ 2'b00; pipe_tx_datavalid_qq <= #TCQ 1'b0; pipe_tx_startblock_qq <= #TCQ 1'b0; pipe_tx_syncheader_qq <= #TCQ 2'b00; pipe_tx_eqcontrol_qq <= #TCQ 2'b00; pipe_tx_eqdeemph_qq <= #TCQ 6'b000000; pipe_tx_eqpreset_qq <= #TCQ 4'h0; end else begin pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i ; pipe_rx_data_q <= #TCQ pipe_rx_data_i ; pipe_rx_valid_q <= #TCQ pipe_rx_valid_i ; pipe_rx_data_valid_q <= #TCQ pipe_rx_data_valid_i ; pipe_rx_status_q <= #TCQ pipe_rx_status_i ; pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i ; pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i ; pipe_rx_eqdone_q <= #TCQ pipe_rx_eqdone_i ; pipe_rx_eqlpadaptdone_q <= #TCQ pipe_rx_eqlpadaptdone_i ; pipe_rx_eqlplffssel_q <= #TCQ pipe_rx_eqlplffssel_i ; pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ pipe_rx_eqlpnewtxcoefforpreset_i ; pipe_rx_startblock_q <= #TCQ pipe_rx_startblock_i ; pipe_rx_syncheader_q <= #TCQ pipe_rx_syncheader_i ; pipe_rx_slide_q <= #TCQ pipe_rx_slide_i ; pipe_rx_syncdone_q <= #TCQ pipe_rx_syncdone_i ; pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i ; pipe_rx_eqcontrol_q <= #TCQ pipe_rx_eqcontrol_i ; pipe_rx_eqlplffs_q <= #TCQ pipe_rx_eqlplffs_i ; pipe_rx_eqlptxpreset_q <= #TCQ pipe_rx_eqlptxpreset_i ; pipe_rx_eqpreset_q <= #TCQ pipe_rx_eqpreset_i ; pipe_tx_eqcoeff_q <= #TCQ pipe_tx_eqcoeff_i ; pipe_tx_eqdone_q <= #TCQ pipe_tx_eqdone_i ; pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i ; pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i ; pipe_tx_data_q <= #TCQ pipe_tx_data_i ; pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i ; pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i ; pipe_tx_datavalid_q <= #TCQ pipe_tx_datavalid_i ; pipe_tx_startblock_q <= #TCQ pipe_tx_startblock_i ; pipe_tx_syncheader_q <= #TCQ pipe_tx_syncheader_i ; pipe_tx_eqcontrol_q <= #TCQ pipe_tx_eqcontrol_i ; pipe_tx_eqdeemph_q <= #TCQ pipe_tx_eqdeemph_i ; pipe_tx_eqpreset_q <= #TCQ pipe_tx_eqpreset_i ; pipe_rx_char_is_k_qq <= #TCQ pipe_rx_char_is_k_q ; pipe_rx_data_qq <= #TCQ pipe_rx_data_q ; pipe_rx_valid_qq <= #TCQ pipe_rx_valid_q ; pipe_rx_data_valid_qq <= #TCQ pipe_rx_data_valid_q ; pipe_rx_status_qq <= #TCQ pipe_rx_status_q ; pipe_rx_phy_status_qq <= #TCQ pipe_rx_phy_status_q ; pipe_rx_elec_idle_qq <= #TCQ pipe_rx_elec_idle_q ; pipe_rx_eqdone_qq <= #TCQ pipe_rx_eqdone_q ; pipe_rx_eqlpadaptdone_qq <= #TCQ pipe_rx_eqlpadaptdone_q ; pipe_rx_eqlplffssel_qq <= #TCQ pipe_rx_eqlplffssel_q ; pipe_rx_eqlpnewtxcoefforpreset_qq<= #TCQ pipe_rx_eqlpnewtxcoefforpreset_q ; pipe_rx_startblock_qq <= #TCQ pipe_rx_startblock_q ; pipe_rx_syncheader_qq <= #TCQ pipe_rx_syncheader_q ; pipe_rx_slide_qq <= #TCQ pipe_rx_slide_q ; pipe_rx_syncdone_qq <= #TCQ pipe_rx_syncdone_q ; pipe_rx_polarity_qq <= #TCQ pipe_rx_polarity_q ; pipe_rx_eqcontrol_qq <= #TCQ pipe_rx_eqcontrol_q ; pipe_rx_eqlplffs_qq <= #TCQ pipe_rx_eqlplffs_q ; pipe_rx_eqlptxpreset_qq <= #TCQ pipe_rx_eqlptxpreset_q ; pipe_rx_eqpreset_qq <= #TCQ pipe_rx_eqpreset_q ; pipe_tx_eqcoeff_qq <= #TCQ pipe_tx_eqcoeff_q ; pipe_tx_eqdone_qq <= #TCQ pipe_tx_eqdone_q ; pipe_tx_compliance_qq <= #TCQ pipe_tx_compliance_q ; pipe_tx_char_is_k_qq <= #TCQ pipe_tx_char_is_k_q ; pipe_tx_data_qq <= #TCQ pipe_tx_data_q ; pipe_tx_elec_idle_qq <= #TCQ pipe_tx_elec_idle_q ; pipe_tx_powerdown_qq <= #TCQ pipe_tx_powerdown_q ; pipe_tx_datavalid_qq <= #TCQ pipe_tx_datavalid_q ; pipe_tx_startblock_qq <= #TCQ pipe_tx_startblock_q ; pipe_tx_syncheader_qq <= #TCQ pipe_tx_syncheader_q ; pipe_tx_eqcontrol_qq <= #TCQ pipe_tx_eqcontrol_q ; pipe_tx_eqdeemph_qq <= #TCQ pipe_tx_eqdeemph_q ; pipe_tx_eqpreset_qq <= #TCQ pipe_tx_eqpreset_q ; end end assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_qq ; assign pipe_rx_data_o = pipe_rx_data_qq ; assign pipe_rx_valid_o = pipe_rx_valid_qq ; assign pipe_rx_data_valid_o = pipe_rx_data_valid_qq ; assign pipe_rx_status_o = pipe_rx_status_qq ; assign pipe_rx_phy_status_o = pipe_rx_phy_status_qq ; assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_qq ; assign pipe_rx_eqdone_o = pipe_rx_eqdone_qq ; assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_qq ; assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_qq ; assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_qq ; assign pipe_rx_startblock_o = pipe_rx_startblock_qq ; assign pipe_rx_syncheader_o = pipe_rx_syncheader_qq ; assign pipe_rx_slide_o = pipe_rx_slide_qq ; assign pipe_rx_syncdone_o = pipe_rx_syncdone_qq ; assign pipe_rx_polarity_o = pipe_rx_polarity_qq ; assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_qq ; assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_qq ; assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_qq ; assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_qq ; assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_qq ; assign pipe_tx_eqdone_o = pipe_tx_eqdone_qq ; assign pipe_tx_compliance_o = pipe_tx_compliance_qq ; assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_qq ; assign pipe_tx_data_o = pipe_tx_data_qq ; assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_qq ; assign pipe_tx_powerdown_o = pipe_tx_powerdown_qq ; assign pipe_tx_datavalid_o = pipe_tx_datavalid_qq ; assign pipe_tx_startblock_o = pipe_tx_startblock_qq ; assign pipe_tx_syncheader_o = pipe_tx_syncheader_qq ; assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_qq ; assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_qq ; assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_qq ; end // if (PIPE_PIPELINE_STAGES == 2) // Default to zero pipeline stages if PIPE_PIPELINE_STAGES != 0,1,2 else begin assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i ; assign pipe_rx_data_o = pipe_rx_data_i ; assign pipe_rx_valid_o = pipe_rx_valid_i ; assign pipe_rx_data_valid_o = pipe_rx_data_valid_i ; assign pipe_rx_status_o = pipe_rx_status_i ; assign pipe_rx_phy_status_o = pipe_rx_phy_status_i ; assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i ; assign pipe_rx_eqdone_o = pipe_rx_eqdone_i ; assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_i ; assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_i ; assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_i ; assign pipe_rx_startblock_o = pipe_rx_startblock_i ; assign pipe_rx_syncheader_o = pipe_rx_syncheader_i ; assign pipe_rx_slide_o = pipe_rx_slide_i ; assign pipe_rx_syncdone_o = pipe_rx_syncdone_i ; assign pipe_rx_polarity_o = pipe_rx_polarity_i ; assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_i ; assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_i ; assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_i ; assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_i ; assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_i ; assign pipe_tx_eqdone_o = pipe_tx_eqdone_i ; assign pipe_tx_compliance_o = pipe_tx_compliance_i ; assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i ; assign pipe_tx_data_o = pipe_tx_data_i ; assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i ; assign pipe_tx_powerdown_o = pipe_tx_powerdown_i ; assign pipe_tx_datavalid_o = pipe_tx_datavalid_i ; assign pipe_tx_startblock_o = pipe_tx_startblock_i ; assign pipe_tx_syncheader_o = pipe_tx_syncheader_i ; assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_i ; assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_i ; assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_i ; end endgenerate endmodule
// usb_system.v // Generated using ACDS version 14.0 200 at 2015.04.28.18:24:52 `timescale 1 ps / 1 ps module usb_system ( input wire clk_clk, // clk.clk output wire [7:0] keycode_export, // keycode.export input wire reset_reset_n, // reset.reset_n output wire sdram_out_clk_clk, // sdram_out_clk.clk output wire [12:0] sdram_wire_addr, // sdram_wire.addr output wire [1:0] sdram_wire_ba, // .ba output wire sdram_wire_cas_n, // .cas_n output wire sdram_wire_cke, // .cke output wire sdram_wire_cs_n, // .cs_n inout wire [31:0] sdram_wire_dq, // .dq output wire [3:0] sdram_wire_dqm, // .dqm output wire sdram_wire_ras_n, // .ras_n output wire sdram_wire_we_n, // .we_n inout wire [15:0] usb_DATA, // usb.DATA output wire [1:0] usb_ADDR, // .ADDR output wire usb_RD_N, // .RD_N output wire usb_WR_N, // .WR_N output wire usb_CS_N, // .CS_N output wire usb_RST_N, // .RST_N input wire usb_INT, // .INT output wire usb_out_clk_clk // usb_out_clk.clk ); wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata wire [28:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata wire cpu_data_master_debugaccess; // cpu:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest wire [28:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata wire mm_interconnect_0_cpu_jtag_debug_module_waitrequest; // cpu:jtag_debug_module_waitrequest -> mm_interconnect_0:cpu_jtag_debug_module_waitrequest wire [31:0] mm_interconnect_0_cpu_jtag_debug_module_writedata; // mm_interconnect_0:cpu_jtag_debug_module_writedata -> cpu:jtag_debug_module_writedata wire [8:0] mm_interconnect_0_cpu_jtag_debug_module_address; // mm_interconnect_0:cpu_jtag_debug_module_address -> cpu:jtag_debug_module_address wire mm_interconnect_0_cpu_jtag_debug_module_write; // mm_interconnect_0:cpu_jtag_debug_module_write -> cpu:jtag_debug_module_write wire mm_interconnect_0_cpu_jtag_debug_module_read; // mm_interconnect_0:cpu_jtag_debug_module_read -> cpu:jtag_debug_module_read wire [31:0] mm_interconnect_0_cpu_jtag_debug_module_readdata; // cpu:jtag_debug_module_readdata -> mm_interconnect_0:cpu_jtag_debug_module_readdata wire mm_interconnect_0_cpu_jtag_debug_module_debugaccess; // mm_interconnect_0:cpu_jtag_debug_module_debugaccess -> cpu:jtag_debug_module_debugaccess wire [3:0] mm_interconnect_0_cpu_jtag_debug_module_byteenable; // mm_interconnect_0:cpu_jtag_debug_module_byteenable -> cpu:jtag_debug_module_byteenable wire [31:0] mm_interconnect_0_clocks_pll_slave_writedata; // mm_interconnect_0:clocks_pll_slave_writedata -> clocks:writedata wire [1:0] mm_interconnect_0_clocks_pll_slave_address; // mm_interconnect_0:clocks_pll_slave_address -> clocks:address wire mm_interconnect_0_clocks_pll_slave_write; // mm_interconnect_0:clocks_pll_slave_write -> clocks:write wire mm_interconnect_0_clocks_pll_slave_read; // mm_interconnect_0:clocks_pll_slave_read -> clocks:read wire [31:0] mm_interconnect_0_clocks_pll_slave_readdata; // clocks:readdata -> mm_interconnect_0:clocks_pll_slave_readdata wire mm_interconnect_0_clock_crossing_io_s0_waitrequest; // clock_crossing_io:s0_waitrequest -> mm_interconnect_0:clock_crossing_io_s0_waitrequest wire [0:0] mm_interconnect_0_clock_crossing_io_s0_burstcount; // mm_interconnect_0:clock_crossing_io_s0_burstcount -> clock_crossing_io:s0_burstcount wire [31:0] mm_interconnect_0_clock_crossing_io_s0_writedata; // mm_interconnect_0:clock_crossing_io_s0_writedata -> clock_crossing_io:s0_writedata wire [21:0] mm_interconnect_0_clock_crossing_io_s0_address; // mm_interconnect_0:clock_crossing_io_s0_address -> clock_crossing_io:s0_address wire mm_interconnect_0_clock_crossing_io_s0_write; // mm_interconnect_0:clock_crossing_io_s0_write -> clock_crossing_io:s0_write wire mm_interconnect_0_clock_crossing_io_s0_read; // mm_interconnect_0:clock_crossing_io_s0_read -> clock_crossing_io:s0_read wire [31:0] mm_interconnect_0_clock_crossing_io_s0_readdata; // clock_crossing_io:s0_readdata -> mm_interconnect_0:clock_crossing_io_s0_readdata wire mm_interconnect_0_clock_crossing_io_s0_debugaccess; // mm_interconnect_0:clock_crossing_io_s0_debugaccess -> clock_crossing_io:s0_debugaccess wire mm_interconnect_0_clock_crossing_io_s0_readdatavalid; // clock_crossing_io:s0_readdatavalid -> mm_interconnect_0:clock_crossing_io_s0_readdatavalid wire [3:0] mm_interconnect_0_clock_crossing_io_s0_byteenable; // mm_interconnect_0:clock_crossing_io_s0_byteenable -> clock_crossing_io:s0_byteenable wire [31:0] mm_interconnect_0_keycode_s1_writedata; // mm_interconnect_0:keycode_s1_writedata -> keycode:writedata wire [1:0] mm_interconnect_0_keycode_s1_address; // mm_interconnect_0:keycode_s1_address -> keycode:address wire mm_interconnect_0_keycode_s1_chipselect; // mm_interconnect_0:keycode_s1_chipselect -> keycode:chipselect wire mm_interconnect_0_keycode_s1_write; // mm_interconnect_0:keycode_s1_write -> keycode:write_n wire [31:0] mm_interconnect_0_keycode_s1_readdata; // keycode:readdata -> mm_interconnect_0:keycode_s1_readdata wire mm_interconnect_0_sdram_s1_waitrequest; // sdram:za_waitrequest -> mm_interconnect_0:sdram_s1_waitrequest wire [31:0] mm_interconnect_0_sdram_s1_writedata; // mm_interconnect_0:sdram_s1_writedata -> sdram:az_data wire [24:0] mm_interconnect_0_sdram_s1_address; // mm_interconnect_0:sdram_s1_address -> sdram:az_addr wire mm_interconnect_0_sdram_s1_chipselect; // mm_interconnect_0:sdram_s1_chipselect -> sdram:az_cs wire mm_interconnect_0_sdram_s1_write; // mm_interconnect_0:sdram_s1_write -> sdram:az_wr_n wire mm_interconnect_0_sdram_s1_read; // mm_interconnect_0:sdram_s1_read -> sdram:az_rd_n wire [31:0] mm_interconnect_0_sdram_s1_readdata; // sdram:za_data -> mm_interconnect_0:sdram_s1_readdata wire mm_interconnect_0_sdram_s1_readdatavalid; // sdram:za_valid -> mm_interconnect_0:sdram_s1_readdatavalid wire [3:0] mm_interconnect_0_sdram_s1_byteenable; // mm_interconnect_0:sdram_s1_byteenable -> sdram:az_be_n wire [0:0] clock_crossing_io_m0_burstcount; // clock_crossing_io:m0_burstcount -> mm_interconnect_1:clock_crossing_io_m0_burstcount wire clock_crossing_io_m0_waitrequest; // mm_interconnect_1:clock_crossing_io_m0_waitrequest -> clock_crossing_io:m0_waitrequest wire [21:0] clock_crossing_io_m0_address; // clock_crossing_io:m0_address -> mm_interconnect_1:clock_crossing_io_m0_address wire [31:0] clock_crossing_io_m0_writedata; // clock_crossing_io:m0_writedata -> mm_interconnect_1:clock_crossing_io_m0_writedata wire clock_crossing_io_m0_write; // clock_crossing_io:m0_write -> mm_interconnect_1:clock_crossing_io_m0_write wire clock_crossing_io_m0_read; // clock_crossing_io:m0_read -> mm_interconnect_1:clock_crossing_io_m0_read wire [31:0] clock_crossing_io_m0_readdata; // mm_interconnect_1:clock_crossing_io_m0_readdata -> clock_crossing_io:m0_readdata wire clock_crossing_io_m0_debugaccess; // clock_crossing_io:m0_debugaccess -> mm_interconnect_1:clock_crossing_io_m0_debugaccess wire [3:0] clock_crossing_io_m0_byteenable; // clock_crossing_io:m0_byteenable -> mm_interconnect_1:clock_crossing_io_m0_byteenable wire clock_crossing_io_m0_readdatavalid; // mm_interconnect_1:clock_crossing_io_m0_readdatavalid -> clock_crossing_io:m0_readdatavalid wire [31:0] mm_interconnect_1_cy7c67200_if_0_hpi_writedata; // mm_interconnect_1:CY7C67200_IF_0_hpi_writedata -> CY7C67200_IF_0:iDATA wire [1:0] mm_interconnect_1_cy7c67200_if_0_hpi_address; // mm_interconnect_1:CY7C67200_IF_0_hpi_address -> CY7C67200_IF_0:iADDR wire mm_interconnect_1_cy7c67200_if_0_hpi_chipselect; // mm_interconnect_1:CY7C67200_IF_0_hpi_chipselect -> CY7C67200_IF_0:iCS_N wire mm_interconnect_1_cy7c67200_if_0_hpi_write; // mm_interconnect_1:CY7C67200_IF_0_hpi_write -> CY7C67200_IF_0:iWR_N wire mm_interconnect_1_cy7c67200_if_0_hpi_read; // mm_interconnect_1:CY7C67200_IF_0_hpi_read -> CY7C67200_IF_0:iRD_N wire [31:0] mm_interconnect_1_cy7c67200_if_0_hpi_readdata; // CY7C67200_IF_0:oDATA -> mm_interconnect_1:CY7C67200_IF_0_hpi_readdata wire irq_mapper_receiver1_irq; // jtag_uart:av_irq -> irq_mapper:receiver1_irq wire [31:0] cpu_d_irq_irq; // irq_mapper:sender_irq -> cpu:d_irq wire irq_mapper_receiver0_irq; // irq_synchronizer:sender_irq -> irq_mapper:receiver0_irq wire [0:0] irq_synchronizer_receiver_irq; // CY7C67200_IF_0:oINT -> irq_synchronizer:receiver_irq wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [CY7C67200_IF_0:iRST_N, clock_crossing_io:m0_reset, irq_synchronizer:receiver_reset, mm_interconnect_1:clock_crossing_io_m0_reset_reset_bridge_in_reset_reset] wire cpu_jtag_debug_module_reset_reset; // cpu:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1, rst_controller_002:reset_in1] wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [clock_crossing_io:s0_reset, clocks:reset, cpu:reset_n, irq_mapper:reset, irq_synchronizer:sender_reset, jtag_uart:rst_n, keycode:reset_n, mm_interconnect_0:cpu_reset_n_reset_bridge_in_reset_reset, rst_translator:in_reset] wire rst_controller_001_reset_out_reset_req; // rst_controller_001:reset_req -> [cpu:reset_req, rst_translator:reset_req_in] wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [mm_interconnect_0:sdram_reset_reset_bridge_in_reset_reset, sdram:reset_n] CY7C67200_IF cy7c67200_if_0 ( .oDATA (mm_interconnect_1_cy7c67200_if_0_hpi_readdata), // hpi.readdata .iADDR (mm_interconnect_1_cy7c67200_if_0_hpi_address), // .address .iRD_N (~mm_interconnect_1_cy7c67200_if_0_hpi_read), // .read_n .iWR_N (~mm_interconnect_1_cy7c67200_if_0_hpi_write), // .write_n .iCS_N (~mm_interconnect_1_cy7c67200_if_0_hpi_chipselect), // .chipselect_n .iDATA (mm_interconnect_1_cy7c67200_if_0_hpi_writedata), // .writedata .iCLK (usb_out_clk_clk), // clock_sink.clk .iRST_N (~rst_controller_reset_out_reset), // clock_sink_reset.reset_n .oINT (irq_synchronizer_receiver_irq), // interrupt_sender.irq .HPI_DATA (usb_DATA), // conduit_end.export .HPI_ADDR (usb_ADDR), // .export .HPI_RD_N (usb_RD_N), // .export .HPI_WR_N (usb_WR_N), // .export .HPI_CS_N (usb_CS_N), // .export .HPI_RST_N (usb_RST_N), // .export .HPI_INT (usb_INT) // .export ); altera_avalon_mm_clock_crossing_bridge #( .DATA_WIDTH (32), .SYMBOL_WIDTH (8), .HDL_ADDR_WIDTH (22), .BURSTCOUNT_WIDTH (1), .COMMAND_FIFO_DEPTH (32), .RESPONSE_FIFO_DEPTH (256), .MASTER_SYNC_DEPTH (3), .SLAVE_SYNC_DEPTH (3) ) clock_crossing_io ( .m0_clk (usb_out_clk_clk), // m0_clk.clk .m0_reset (rst_controller_reset_out_reset), // m0_reset.reset .s0_clk (clk_clk), // s0_clk.clk .s0_reset (rst_controller_001_reset_out_reset), // s0_reset.reset .s0_waitrequest (mm_interconnect_0_clock_crossing_io_s0_waitrequest), // s0.waitrequest .s0_readdata (mm_interconnect_0_clock_crossing_io_s0_readdata), // .readdata .s0_readdatavalid (mm_interconnect_0_clock_crossing_io_s0_readdatavalid), // .readdatavalid .s0_burstcount (mm_interconnect_0_clock_crossing_io_s0_burstcount), // .burstcount .s0_writedata (mm_interconnect_0_clock_crossing_io_s0_writedata), // .writedata .s0_address (mm_interconnect_0_clock_crossing_io_s0_address), // .address .s0_write (mm_interconnect_0_clock_crossing_io_s0_write), // .write .s0_read (mm_interconnect_0_clock_crossing_io_s0_read), // .read .s0_byteenable (mm_interconnect_0_clock_crossing_io_s0_byteenable), // .byteenable .s0_debugaccess (mm_interconnect_0_clock_crossing_io_s0_debugaccess), // .debugaccess .m0_waitrequest (clock_crossing_io_m0_waitrequest), // m0.waitrequest .m0_readdata (clock_crossing_io_m0_readdata), // .readdata .m0_readdatavalid (clock_crossing_io_m0_readdatavalid), // .readdatavalid .m0_burstcount (clock_crossing_io_m0_burstcount), // .burstcount .m0_writedata (clock_crossing_io_m0_writedata), // .writedata .m0_address (clock_crossing_io_m0_address), // .address .m0_write (clock_crossing_io_m0_write), // .write .m0_read (clock_crossing_io_m0_read), // .read .m0_byteenable (clock_crossing_io_m0_byteenable), // .byteenable .m0_debugaccess (clock_crossing_io_m0_debugaccess) // .debugaccess ); usb_system_clocks clocks ( .clk (clk_clk), // inclk_interface.clk .reset (rst_controller_001_reset_out_reset), // inclk_interface_reset.reset .read (mm_interconnect_0_clocks_pll_slave_read), // pll_slave.read .write (mm_interconnect_0_clocks_pll_slave_write), // .write .address (mm_interconnect_0_clocks_pll_slave_address), // .address .readdata (mm_interconnect_0_clocks_pll_slave_readdata), // .readdata .writedata (mm_interconnect_0_clocks_pll_slave_writedata), // .writedata .c0 (sdram_out_clk_clk), // c0.clk .c1 (usb_out_clk_clk), // c1.clk .areset (), // areset_conduit.export .locked (), // locked_conduit.export .phasedone () // phasedone_conduit.export ); usb_system_cpu cpu ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_001_reset_out_reset), // reset_n.reset_n .reset_req (rst_controller_001_reset_out_reset_req), // .reset_req .d_address (cpu_data_master_address), // data_master.address .d_byteenable (cpu_data_master_byteenable), // .byteenable .d_read (cpu_data_master_read), // .read .d_readdata (cpu_data_master_readdata), // .readdata .d_waitrequest (cpu_data_master_waitrequest), // .waitrequest .d_write (cpu_data_master_write), // .write .d_writedata (cpu_data_master_writedata), // .writedata .jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess), // .debugaccess .i_address (cpu_instruction_master_address), // instruction_master.address .i_read (cpu_instruction_master_read), // .read .i_readdata (cpu_instruction_master_readdata), // .readdata .i_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest .d_irq (cpu_d_irq_irq), // d_irq.irq .jtag_debug_module_resetrequest (cpu_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset .jtag_debug_module_address (mm_interconnect_0_cpu_jtag_debug_module_address), // jtag_debug_module.address .jtag_debug_module_byteenable (mm_interconnect_0_cpu_jtag_debug_module_byteenable), // .byteenable .jtag_debug_module_debugaccess (mm_interconnect_0_cpu_jtag_debug_module_debugaccess), // .debugaccess .jtag_debug_module_read (mm_interconnect_0_cpu_jtag_debug_module_read), // .read .jtag_debug_module_readdata (mm_interconnect_0_cpu_jtag_debug_module_readdata), // .readdata .jtag_debug_module_waitrequest (mm_interconnect_0_cpu_jtag_debug_module_waitrequest), // .waitrequest .jtag_debug_module_write (mm_interconnect_0_cpu_jtag_debug_module_write), // .write .jtag_debug_module_writedata (mm_interconnect_0_cpu_jtag_debug_module_writedata), // .writedata .no_ci_readra () // custom_instruction_master.readra ); usb_system_jtag_uart jtag_uart ( .clk (clk_clk), // clk.clk .rst_n (~rst_controller_001_reset_out_reset), // reset.reset_n .av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect .av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address .av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n .av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata .av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n .av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata .av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest .av_irq (irq_mapper_receiver1_irq) // irq.irq ); usb_system_keycode keycode ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n .address (mm_interconnect_0_keycode_s1_address), // s1.address .write_n (~mm_interconnect_0_keycode_s1_write), // .write_n .writedata (mm_interconnect_0_keycode_s1_writedata), // .writedata .chipselect (mm_interconnect_0_keycode_s1_chipselect), // .chipselect .readdata (mm_interconnect_0_keycode_s1_readdata), // .readdata .out_port (keycode_export) // external_connection.export ); usb_system_sdram sdram ( .clk (sdram_out_clk_clk), // clk.clk .reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n .az_addr (mm_interconnect_0_sdram_s1_address), // s1.address .az_be_n (~mm_interconnect_0_sdram_s1_byteenable), // .byteenable_n .az_cs (mm_interconnect_0_sdram_s1_chipselect), // .chipselect .az_data (mm_interconnect_0_sdram_s1_writedata), // .writedata .az_rd_n (~mm_interconnect_0_sdram_s1_read), // .read_n .az_wr_n (~mm_interconnect_0_sdram_s1_write), // .write_n .za_data (mm_interconnect_0_sdram_s1_readdata), // .readdata .za_valid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid .za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest .zs_addr (sdram_wire_addr), // wire.export .zs_ba (sdram_wire_ba), // .export .zs_cas_n (sdram_wire_cas_n), // .export .zs_cke (sdram_wire_cke), // .export .zs_cs_n (sdram_wire_cs_n), // .export .zs_dq (sdram_wire_dq), // .export .zs_dqm (sdram_wire_dqm), // .export .zs_ras_n (sdram_wire_ras_n), // .export .zs_we_n (sdram_wire_we_n) // .export ); usb_system_mm_interconnect_0 mm_interconnect_0 ( .clk_clk_clk (clk_clk), // clk_clk.clk .clocks_c0_clk (sdram_out_clk_clk), // clocks_c0.clk .cpu_reset_n_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // cpu_reset_n_reset_bridge_in_reset.reset .sdram_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // sdram_reset_reset_bridge_in_reset.reset .cpu_data_master_address (cpu_data_master_address), // cpu_data_master.address .cpu_data_master_waitrequest (cpu_data_master_waitrequest), // .waitrequest .cpu_data_master_byteenable (cpu_data_master_byteenable), // .byteenable .cpu_data_master_read (cpu_data_master_read), // .read .cpu_data_master_readdata (cpu_data_master_readdata), // .readdata .cpu_data_master_write (cpu_data_master_write), // .write .cpu_data_master_writedata (cpu_data_master_writedata), // .writedata .cpu_data_master_debugaccess (cpu_data_master_debugaccess), // .debugaccess .cpu_instruction_master_address (cpu_instruction_master_address), // cpu_instruction_master.address .cpu_instruction_master_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest .cpu_instruction_master_read (cpu_instruction_master_read), // .read .cpu_instruction_master_readdata (cpu_instruction_master_readdata), // .readdata .clock_crossing_io_s0_address (mm_interconnect_0_clock_crossing_io_s0_address), // clock_crossing_io_s0.address .clock_crossing_io_s0_write (mm_interconnect_0_clock_crossing_io_s0_write), // .write .clock_crossing_io_s0_read (mm_interconnect_0_clock_crossing_io_s0_read), // .read .clock_crossing_io_s0_readdata (mm_interconnect_0_clock_crossing_io_s0_readdata), // .readdata .clock_crossing_io_s0_writedata (mm_interconnect_0_clock_crossing_io_s0_writedata), // .writedata .clock_crossing_io_s0_burstcount (mm_interconnect_0_clock_crossing_io_s0_burstcount), // .burstcount .clock_crossing_io_s0_byteenable (mm_interconnect_0_clock_crossing_io_s0_byteenable), // .byteenable .clock_crossing_io_s0_readdatavalid (mm_interconnect_0_clock_crossing_io_s0_readdatavalid), // .readdatavalid .clock_crossing_io_s0_waitrequest (mm_interconnect_0_clock_crossing_io_s0_waitrequest), // .waitrequest .clock_crossing_io_s0_debugaccess (mm_interconnect_0_clock_crossing_io_s0_debugaccess), // .debugaccess .clocks_pll_slave_address (mm_interconnect_0_clocks_pll_slave_address), // clocks_pll_slave.address .clocks_pll_slave_write (mm_interconnect_0_clocks_pll_slave_write), // .write .clocks_pll_slave_read (mm_interconnect_0_clocks_pll_slave_read), // .read .clocks_pll_slave_readdata (mm_interconnect_0_clocks_pll_slave_readdata), // .readdata .clocks_pll_slave_writedata (mm_interconnect_0_clocks_pll_slave_writedata), // .writedata .cpu_jtag_debug_module_address (mm_interconnect_0_cpu_jtag_debug_module_address), // cpu_jtag_debug_module.address .cpu_jtag_debug_module_write (mm_interconnect_0_cpu_jtag_debug_module_write), // .write .cpu_jtag_debug_module_read (mm_interconnect_0_cpu_jtag_debug_module_read), // .read .cpu_jtag_debug_module_readdata (mm_interconnect_0_cpu_jtag_debug_module_readdata), // .readdata .cpu_jtag_debug_module_writedata (mm_interconnect_0_cpu_jtag_debug_module_writedata), // .writedata .cpu_jtag_debug_module_byteenable (mm_interconnect_0_cpu_jtag_debug_module_byteenable), // .byteenable .cpu_jtag_debug_module_waitrequest (mm_interconnect_0_cpu_jtag_debug_module_waitrequest), // .waitrequest .cpu_jtag_debug_module_debugaccess (mm_interconnect_0_cpu_jtag_debug_module_debugaccess), // .debugaccess .jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address .jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write .jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read .jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata .jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata .jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest .jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect .keycode_s1_address (mm_interconnect_0_keycode_s1_address), // keycode_s1.address .keycode_s1_write (mm_interconnect_0_keycode_s1_write), // .write .keycode_s1_readdata (mm_interconnect_0_keycode_s1_readdata), // .readdata .keycode_s1_writedata (mm_interconnect_0_keycode_s1_writedata), // .writedata .keycode_s1_chipselect (mm_interconnect_0_keycode_s1_chipselect), // .chipselect .sdram_s1_address (mm_interconnect_0_sdram_s1_address), // sdram_s1.address .sdram_s1_write (mm_interconnect_0_sdram_s1_write), // .write .sdram_s1_read (mm_interconnect_0_sdram_s1_read), // .read .sdram_s1_readdata (mm_interconnect_0_sdram_s1_readdata), // .readdata .sdram_s1_writedata (mm_interconnect_0_sdram_s1_writedata), // .writedata .sdram_s1_byteenable (mm_interconnect_0_sdram_s1_byteenable), // .byteenable .sdram_s1_readdatavalid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid .sdram_s1_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest .sdram_s1_chipselect (mm_interconnect_0_sdram_s1_chipselect) // .chipselect ); usb_system_mm_interconnect_1 mm_interconnect_1 ( .clocks_c1_clk (usb_out_clk_clk), // clocks_c1.clk .clock_crossing_io_m0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // clock_crossing_io_m0_reset_reset_bridge_in_reset.reset .clock_crossing_io_m0_address (clock_crossing_io_m0_address), // clock_crossing_io_m0.address .clock_crossing_io_m0_waitrequest (clock_crossing_io_m0_waitrequest), // .waitrequest .clock_crossing_io_m0_burstcount (clock_crossing_io_m0_burstcount), // .burstcount .clock_crossing_io_m0_byteenable (clock_crossing_io_m0_byteenable), // .byteenable .clock_crossing_io_m0_read (clock_crossing_io_m0_read), // .read .clock_crossing_io_m0_readdata (clock_crossing_io_m0_readdata), // .readdata .clock_crossing_io_m0_readdatavalid (clock_crossing_io_m0_readdatavalid), // .readdatavalid .clock_crossing_io_m0_write (clock_crossing_io_m0_write), // .write .clock_crossing_io_m0_writedata (clock_crossing_io_m0_writedata), // .writedata .clock_crossing_io_m0_debugaccess (clock_crossing_io_m0_debugaccess), // .debugaccess .CY7C67200_IF_0_hpi_address (mm_interconnect_1_cy7c67200_if_0_hpi_address), // CY7C67200_IF_0_hpi.address .CY7C67200_IF_0_hpi_write (mm_interconnect_1_cy7c67200_if_0_hpi_write), // .write .CY7C67200_IF_0_hpi_read (mm_interconnect_1_cy7c67200_if_0_hpi_read), // .read .CY7C67200_IF_0_hpi_readdata (mm_interconnect_1_cy7c67200_if_0_hpi_readdata), // .readdata .CY7C67200_IF_0_hpi_writedata (mm_interconnect_1_cy7c67200_if_0_hpi_writedata), // .writedata .CY7C67200_IF_0_hpi_chipselect (mm_interconnect_1_cy7c67200_if_0_hpi_chipselect) // .chipselect ); usb_system_irq_mapper irq_mapper ( .clk (clk_clk), // clk.clk .reset (rst_controller_001_reset_out_reset), // clk_reset.reset .receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq .receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq .sender_irq (cpu_d_irq_irq) // sender.irq ); altera_irq_clock_crosser #( .IRQ_WIDTH (1) ) irq_synchronizer ( .receiver_clk (usb_out_clk_clk), // receiver_clk.clk .sender_clk (clk_clk), // sender_clk.clk .receiver_reset (rst_controller_reset_out_reset), // receiver_clk_reset.reset .sender_reset (rst_controller_001_reset_out_reset), // sender_clk_reset.reset .receiver_irq (irq_synchronizer_receiver_irq), // receiver.irq .sender_irq (irq_mapper_receiver0_irq) // sender.irq ); altera_reset_controller #( .NUM_RESET_INPUTS (2), .OUTPUT_RESET_SYNC_EDGES ("deassert"), .SYNC_DEPTH (2), .RESET_REQUEST_PRESENT (0), .RESET_REQ_WAIT_TIME (1), .MIN_RST_ASSERTION_TIME (3), .RESET_REQ_EARLY_DSRT_TIME (1), .USE_RESET_REQUEST_IN0 (0), .USE_RESET_REQUEST_IN1 (0), .USE_RESET_REQUEST_IN2 (0), .USE_RESET_REQUEST_IN3 (0), .USE_RESET_REQUEST_IN4 (0), .USE_RESET_REQUEST_IN5 (0), .USE_RESET_REQUEST_IN6 (0), .USE_RESET_REQUEST_IN7 (0), .USE_RESET_REQUEST_IN8 (0), .USE_RESET_REQUEST_IN9 (0), .USE_RESET_REQUEST_IN10 (0), .USE_RESET_REQUEST_IN11 (0), .USE_RESET_REQUEST_IN12 (0), .USE_RESET_REQUEST_IN13 (0), .USE_RESET_REQUEST_IN14 (0), .USE_RESET_REQUEST_IN15 (0), .ADAPT_RESET_REQUEST (0) ) rst_controller ( .reset_in0 (~reset_reset_n), // reset_in0.reset .reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset .clk (usb_out_clk_clk), // clk.clk .reset_out (rst_controller_reset_out_reset), // reset_out.reset .reset_req (), // (terminated) .reset_req_in0 (1'b0), // (terminated) .reset_req_in1 (1'b0), // (terminated) .reset_in2 (1'b0), // (terminated) .reset_req_in2 (1'b0), // (terminated) .reset_in3 (1'b0), // (terminated) .reset_req_in3 (1'b0), // (terminated) .reset_in4 (1'b0), // (terminated) .reset_req_in4 (1'b0), // (terminated) .reset_in5 (1'b0), // (terminated) .reset_req_in5 (1'b0), // (terminated) .reset_in6 (1'b0), // (terminated) .reset_req_in6 (1'b0), // (terminated) .reset_in7 (1'b0), // (terminated) .reset_req_in7 (1'b0), // (terminated) .reset_in8 (1'b0), // (terminated) .reset_req_in8 (1'b0), // (terminated) .reset_in9 (1'b0), // (terminated) .reset_req_in9 (1'b0), // (terminated) .reset_in10 (1'b0), // (terminated) .reset_req_in10 (1'b0), // (terminated) .reset_in11 (1'b0), // (terminated) .reset_req_in11 (1'b0), // (terminated) .reset_in12 (1'b0), // (terminated) .reset_req_in12 (1'b0), // (terminated) .reset_in13 (1'b0), // (terminated) .reset_req_in13 (1'b0), // (terminated) .reset_in14 (1'b0), // (terminated) .reset_req_in14 (1'b0), // (terminated) .reset_in15 (1'b0), // (terminated) .reset_req_in15 (1'b0) // (terminated) ); altera_reset_controller #( .NUM_RESET_INPUTS (2), .OUTPUT_RESET_SYNC_EDGES ("deassert"), .SYNC_DEPTH (2), .RESET_REQUEST_PRESENT (1), .RESET_REQ_WAIT_TIME (1), .MIN_RST_ASSERTION_TIME (3), .RESET_REQ_EARLY_DSRT_TIME (1), .USE_RESET_REQUEST_IN0 (0), .USE_RESET_REQUEST_IN1 (0), .USE_RESET_REQUEST_IN2 (0), .USE_RESET_REQUEST_IN3 (0), .USE_RESET_REQUEST_IN4 (0), .USE_RESET_REQUEST_IN5 (0), .USE_RESET_REQUEST_IN6 (0), .USE_RESET_REQUEST_IN7 (0), .USE_RESET_REQUEST_IN8 (0), .USE_RESET_REQUEST_IN9 (0), .USE_RESET_REQUEST_IN10 (0), .USE_RESET_REQUEST_IN11 (0), .USE_RESET_REQUEST_IN12 (0), .USE_RESET_REQUEST_IN13 (0), .USE_RESET_REQUEST_IN14 (0), .USE_RESET_REQUEST_IN15 (0), .ADAPT_RESET_REQUEST (0) ) rst_controller_001 ( .reset_in0 (~reset_reset_n), // reset_in0.reset .reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset .clk (clk_clk), // clk.clk .reset_out (rst_controller_001_reset_out_reset), // reset_out.reset .reset_req (rst_controller_001_reset_out_reset_req), // .reset_req .reset_req_in0 (1'b0), // (terminated) .reset_req_in1 (1'b0), // (terminated) .reset_in2 (1'b0), // (terminated) .reset_req_in2 (1'b0), // (terminated) .reset_in3 (1'b0), // (terminated) .reset_req_in3 (1'b0), // (terminated) .reset_in4 (1'b0), // (terminated) .reset_req_in4 (1'b0), // (terminated) .reset_in5 (1'b0), // (terminated) .reset_req_in5 (1'b0), // (terminated) .reset_in6 (1'b0), // (terminated) .reset_req_in6 (1'b0), // (terminated) .reset_in7 (1'b0), // (terminated) .reset_req_in7 (1'b0), // (terminated) .reset_in8 (1'b0), // (terminated) .reset_req_in8 (1'b0), // (terminated) .reset_in9 (1'b0), // (terminated) .reset_req_in9 (1'b0), // (terminated) .reset_in10 (1'b0), // (terminated) .reset_req_in10 (1'b0), // (terminated) .reset_in11 (1'b0), // (terminated) .reset_req_in11 (1'b0), // (terminated) .reset_in12 (1'b0), // (terminated) .reset_req_in12 (1'b0), // (terminated) .reset_in13 (1'b0), // (terminated) .reset_req_in13 (1'b0), // (terminated) .reset_in14 (1'b0), // (terminated) .reset_req_in14 (1'b0), // (terminated) .reset_in15 (1'b0), // (terminated) .reset_req_in15 (1'b0) // (terminated) ); altera_reset_controller #( .NUM_RESET_INPUTS (2), .OUTPUT_RESET_SYNC_EDGES ("deassert"), .SYNC_DEPTH (2), .RESET_REQUEST_PRESENT (0), .RESET_REQ_WAIT_TIME (1), .MIN_RST_ASSERTION_TIME (3), .RESET_REQ_EARLY_DSRT_TIME (1), .USE_RESET_REQUEST_IN0 (0), .USE_RESET_REQUEST_IN1 (0), .USE_RESET_REQUEST_IN2 (0), .USE_RESET_REQUEST_IN3 (0), .USE_RESET_REQUEST_IN4 (0), .USE_RESET_REQUEST_IN5 (0), .USE_RESET_REQUEST_IN6 (0), .USE_RESET_REQUEST_IN7 (0), .USE_RESET_REQUEST_IN8 (0), .USE_RESET_REQUEST_IN9 (0), .USE_RESET_REQUEST_IN10 (0), .USE_RESET_REQUEST_IN11 (0), .USE_RESET_REQUEST_IN12 (0), .USE_RESET_REQUEST_IN13 (0), .USE_RESET_REQUEST_IN14 (0), .USE_RESET_REQUEST_IN15 (0), .ADAPT_RESET_REQUEST (0) ) rst_controller_002 ( .reset_in0 (~reset_reset_n), // reset_in0.reset .reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset .clk (sdram_out_clk_clk), // clk.clk .reset_out (rst_controller_002_reset_out_reset), // reset_out.reset .reset_req (), // (terminated) .reset_req_in0 (1'b0), // (terminated) .reset_req_in1 (1'b0), // (terminated) .reset_in2 (1'b0), // (terminated) .reset_req_in2 (1'b0), // (terminated) .reset_in3 (1'b0), // (terminated) .reset_req_in3 (1'b0), // (terminated) .reset_in4 (1'b0), // (terminated) .reset_req_in4 (1'b0), // (terminated) .reset_in5 (1'b0), // (terminated) .reset_req_in5 (1'b0), // (terminated) .reset_in6 (1'b0), // (terminated) .reset_req_in6 (1'b0), // (terminated) .reset_in7 (1'b0), // (terminated) .reset_req_in7 (1'b0), // (terminated) .reset_in8 (1'b0), // (terminated) .reset_req_in8 (1'b0), // (terminated) .reset_in9 (1'b0), // (terminated) .reset_req_in9 (1'b0), // (terminated) .reset_in10 (1'b0), // (terminated) .reset_req_in10 (1'b0), // (terminated) .reset_in11 (1'b0), // (terminated) .reset_req_in11 (1'b0), // (terminated) .reset_in12 (1'b0), // (terminated) .reset_req_in12 (1'b0), // (terminated) .reset_in13 (1'b0), // (terminated) .reset_req_in13 (1'b0), // (terminated) .reset_in14 (1'b0), // (terminated) .reset_req_in14 (1'b0), // (terminated) .reset_in15 (1'b0), // (terminated) .reset_req_in15 (1'b0) // (terminated) ); endmodule
/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HS__A211O_BEHAVIORAL_PP_V `define SKY130_FD_SC_HS__A211O_BEHAVIORAL_PP_V /** * a211o: 2-input AND into first input of 3-input OR. * * X = ((A1 & A2) | B1 | C1) * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none // Import sub cells. `include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v" `celldefine module sky130_fd_sc_hs__a211o ( VPWR, VGND, X , A1 , A2 , B1 , C1 ); // Module ports input VPWR; input VGND; output X ; input A1 ; input A2 ; input B1 ; input C1 ; // Local signals wire C1 and0_out ; wire or0_out_X ; wire u_vpwr_vgnd0_out_X; // Name Output Other arguments and and0 (and0_out , A1, A2 ); or or0 (or0_out_X , and0_out, C1, B1 ); sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND); buf buf0 (X , u_vpwr_vgnd0_out_X ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_HS__A211O_BEHAVIORAL_PP_V
/** * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_SYMBOL_V `define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_SYMBOL_V /** * udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high * (Q output UDP) * * Verilog stub (with power pins) for graphical symbol definition * generation. * * WARNING: This file is autogenerated, do not modify directly! */ `timescale 1ns / 1ps `default_nettype none (* blackbox *) module sky130_fd_sc_hs__udp_dlatch$P_pp$PG$N ( //# {{data|Data Signals}} input D , output Q , //# {{clocks|Clocking}} input GATE , //# {{power|Power}} input NOTIFIER, input VPWR , input VGND ); endmodule `default_nettype wire `endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
/* SPDX-License-Identifier: MIT */ /* (c) Copyright 2018 David M. Koltak, all rights reserved. */ // // RCN bus RAM // module rcn_ram ( input clk, input rst, input [68:0] rcn_in, output [68:0] rcn_out ); parameter ADDR_BASE = 0; wire cs; wire wr; wire [3:0] mask; wire [23:0] addr; wire [31:0] wdata; wire [31:0] rdata; rcn_slave #(.ADDR_MASK(24'hFF0000), .ADDR_BASE(ADDR_BASE)) rcn_slave ( .rst(rst), .clk(clk), .rcn_in(rcn_in), .rcn_out(rcn_out), .cs(cs), .wr(wr), .mask(mask), .addr(addr), .wdata(wdata), .rdata(rdata) ); reg [7:0] byte_0[(1024 * 16)-1:0]; reg [7:0] byte_1[(1024 * 16)-1:0]; reg [7:0] byte_2[(1024 * 16)-1:0]; reg [7:0] byte_3[(1024 * 16)-1:0]; reg [31:0] data_out; always @ (posedge clk) if (cs && wr) begin if (mask[0]) byte_0[addr[15:2]] <= wdata[7:0]; if (mask[1]) byte_1[addr[15:2]] <= wdata[15:8]; if (mask[2]) byte_2[addr[15:2]] <= wdata[23:16]; if (mask[3]) byte_3[addr[15:2]] <= wdata[31:24]; end always @ (posedge clk) if (cs) data_out <= {byte_3[addr[15:2]], byte_2[addr[15:2]], byte_1[addr[15:2]], byte_0[addr[15:2]]}; assign rdata = data_out; endmodule
`timescale 1ns / 1ps module DataMemory( output reg [31:0] ReadData, output reg [31:0] DATO1, output reg [31:0] DATO2, output reg [31:0] RESULTADO, input [31:0] Address, input [31:0] WriteData, input [31:0] MouseData, input MouseEnable, input WriteEnable, input CLK ); reg [31:0] block [0:9]; always @ (*) begin DATO1 = block[4]; DATO2 = block[5]; RESULTADO = block[7]; if (CLK) begin case (Address) 32'h00000000: ReadData = block[0]; 32'h00000004: ReadData = block[1]; 32'h00000008: ReadData = block[2]; 32'h0000000c: ReadData = block[3]; 32'h00000010: ReadData = block[4]; 32'h00000014: ReadData = block[5]; 32'h00000018: ReadData = block[6]; 32'h0000001c: ReadData = block[7]; 32'h00000020: ReadData = block[8]; 32'h00000024: ReadData = block[9]; default: ReadData = 32'b0; endcase end else begin if (MouseEnable) begin block[1] = MouseData; end if (WriteEnable) case (Address) 32'h00000000: block[0] = WriteData; 32'h00000004: block[1] = WriteData; 32'h00000008: block[2] = WriteData; 32'h0000000c: block[3] = WriteData; 32'h00000010: block[4] = WriteData; 32'h00000014: block[5] = WriteData; 32'h00000018: block[6] = WriteData; 32'h0000001c: block[7] = WriteData; 32'h00000020: block[8] = WriteData; 32'h00000024: block[9] = WriteData; endcase end end integer i = 0; initial begin for (i=0;i<10;i=i+1) block[i] = 32'b0; block[1] = 2; block[4] = 2; end endmodule