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Datasets:
shailja
/
Verilog_GitHub
like
18
Modalities:
Text
Formats:
csv
Size:
100K - 1M
ArXiv:
arxiv:
2212.11140
Libraries:
Datasets
pandas
Croissant
+ 1
License:
mit
Dataset card
Viewer
Files
Files and versions
Community
3
b73de31
Verilog_GitHub
Commit History
Delete old duckdb index files
b73de31
verified
parquet-converter
commited on
Mar 7
Update duckdb index files
c85424e
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commited on
Sep 20, 2023
Update parquet files
4c8cf68
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commited on
Sep 20, 2023
Update duckdb index files
d879e1d
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commited on
Sep 4, 2023
Update duckdb index files
21cc5da
parquet-converter
commited on
Sep 4, 2023
Update parquet files
106c92e
parquet-converter
commited on
Sep 4, 2023
Update duckdb index files
9ad1f48
parquet-converter
commited on
Aug 30, 2023
Update parquet files
2aca461
parquet-converter
commited on
Aug 17, 2023
Update duckdb index files
f086582
parquet-converter
commited on
Aug 4, 2023
Update parquet files
0051bec
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commited on
Jun 6, 2023
Update parquet files
faea96c
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commited on
May 4, 2023
Update parquet files
78b80b4
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commited on
Apr 29, 2023
Update parquet files
9007d73
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commited on
Jan 20, 2023
initial commit
bbc7768
shailja
commited on
Dec 19, 2022