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shailja
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Verilog_GitHub

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parquet-converter commited on
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2aca461
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1 Parent(s): f086582

Update parquet files

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  1. shailja--Verilog_GitHub/{csv-train-00000-of-00004.parquet → train/0000.parquet} +0 -0
  2. shailja--Verilog_GitHub/{csv-train-00001-of-00004.parquet → train/0001.parquet} +0 -0
  3. shailja--Verilog_GitHub/{csv-train-00002-of-00004.parquet → train/0002.parquet} +0 -0
  4. shailja--Verilog_GitHub/{csv-train-00003-of-00004.parquet → train/0003.parquet} +0 -0
shailja--Verilog_GitHub/{csv-train-00000-of-00004.parquet → train/0000.parquet} RENAMED
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shailja--Verilog_GitHub/{csv-train-00001-of-00004.parquet → train/0001.parquet} RENAMED
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shailja--Verilog_GitHub/{csv-train-00002-of-00004.parquet → train/0002.parquet} RENAMED
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shailja--Verilog_GitHub/{csv-train-00003-of-00004.parquet → train/0003.parquet} RENAMED
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