sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: In addition, the multipliers and accumulators in the asynchronous data-path consist of fine-grain partitioned bit-slices that are selectively activated by mask control signals.
Sentence 2: secondly, while ripple-carry adders have relatively long worst-case delay, the bit­partitioning of the multiplier array (including the ripple-carry adder) leads to very good average case delay for this application.
Relationship: neutral
Domain: Hardware
Sentence 1: This concept has been preserved for the next standard versions as well.
Sentence 2: recon.gurable (FPGA) implementations require triv­ial hardware costs (low number of recon.gurable cells -419 Xilinx CLBs and 1024 Altera LCs for a 16-pixel line processing) and low frequencies (varying between 11 and 25 MHz)  All these design achievements have been validated both for Altera and Xilinx FPGA families.
Relationship: neutral
Domain: Hardware
Sentence 1: As an example, the comparator could be designed in order to give to its output: i) (1, 0) or (0, 1), as Pass indication; ii) (0, 0) or (1, 1), as Fail indication and in the case of faults affecting itself.
Sentence 2: we analyzed the possible effects of such faults by means of logical and electrical level simulations.
Relationship: neutral
Domain: Hardware
Sentence 1: 6.1 Collaboration Mechanism In mobile ad hoc networks, the attackers can launch at­tacks when they are close to victims.
Sentence 2: correlationAlert name Routing_Disruption_Attack alertident analyzerid 1 alertident analyzerid 4 alertident analyzerid 6 source 22 END Figure 8: An example of one aggregated alert.
Relationship: neutral
Domain: Hardware
Sentence 1: 978-1-4577-0995-1/11/$26.00 &#38;#169;2011 IEEE 162   On one hand, the high number of control signals increases the risk of instability and the inability to realize some functions in the case of the presence of defects on one control signal.
Sentence 2: dTIS 2006, 5-7 September, 2006, Tunis, Tunisia, in press.
Relationship: neutral
Domain: Hardware
Sentence 1: Note that, in this context, idle refers to channels which are marked as idle in the channel map, since this is the only infor­mation available to a CPAN piconet and its coordinator.
Sentence 2: as sensing is performed in discrete intervals, any change in the state of a channel can be detected only upon the next sensing event; therefore, state changes in the channel map are always delayed with respect to the actual changes.
Relationship: neutral
Domain: Hardware
Sentence 1: [2] R. J. Widlar, New Developments in IC Voltage Regulators, IEEE J. Solid-State Circuits, vol.
Sentence 2: bVR circuits have been adapted to CMOS process using vertical bipolar transistors and OpAmps [3] seeking to break the barrier of 1.2 V , with a supply voltage near to 1 V , and even below this voltage to reduce dissipation.
Relationship: neutral
Domain: Hardware
Sentence 1: o m 2 ddnCr g 0 y rya ]i the selection of a suitable codec that improves QoS often regard­less of the underlying network, fast hardware that can process (e.g., compress) data better, and high-end speakers enhancing the sound quality, to name a few.
Sentence 2: o m 2 d w d o C n d C o Q r 2 JC n m e d 2m om m e o C Dmea wQDrC n D .
Relationship: neutral
Domain: Hardware
Sentence 1: The reason for this performance di.erence is that the multi-channel estimator only needs to detect multipath ar­rivals over the delay spread of the individual channels, which is of length Np, whereas the single channel estimator needs to detect multipath arrivals over the delay spread of the overall channel, which is of length Nh.The ratio Nh/KNp is in general quite large, on the order of tens to thousands, for low SNR.
Sentence 2: a target false alarm probability of 0.01 is used with the structured estimators to obtain the corresponding thresholds, .c and .p, for the single channel and multi-channel estimators, respectively.
Relationship: neutral
Domain: Hardware
Sentence 1: [22] P. Y. Chang, M. Evers, and Y. Patt, Improving Branch Pre­diction Accuracy by Reducing Pattern History Table Interfer­ence, in International Conference on Parallel Architectures and Compilation Techniques, October 1996.
Sentence 2: it is not dif.cult to observe that it is the non-biased Branch A that steers the control .ow through either the Branch B or the Branches C and D that subsequently leads up to the Branch E. As a result, the change in the direction of the Branch A provides suf.cient evidence to cause a change in the direction of the Branch E. In other words, the control .ow through either the Branch B or the Branches C and D in the two program paths merely reinforces the prediction decision of the Branch E that can independently be established by correlating only with the non-biased branch A.
Relationship: neutral
Domain: Hardware
Sentence 1: Throughout this paper, we consider the sixth order accurate approximation to the Laplacian, which approximates the second order differential in each dimension with the following stencil: d2 pi 1 (2pi-3 - 27pi-2 + 270pi-1 - 490pi dx2 180h2 +270pi+1 - 27pi+2 + 2pi+3)+ O(h6), (2) where pi is the ith grid cell in the corresponding dimension.
Sentence 2: video sequences are then played back during the study.
Relationship: neutral
Domain: Hardware
Sentence 1: Until the cache is completely filled, the tasks (only whole tasks are allowed) are allocated to the cache from the lowest address to the highest.
Sentence 2: since tasks in cache will wrap around the cache, an offset Zr, can be added to each task allocated to processor r, and the task can be placed from memory location tx + Zr + I*sizeof (cache r) to memory location tx + Zr + i * sizeof (cache r).
Relationship: neutral
Domain: Hardware
Sentence 1: However, during backtrace, if we are selecting the easiest way to justify x to 0, our algorithm would prefer to backtrace through B since it has a 0-controllability value of 2 which is less than the 0-controllability value of A (3).
Sentence 2: in a the forward logic simulation performed by the ATPG, only the implica­tions h = 0 and n = 0 would be known.
Relationship: neutral
Domain: Hardware
Sentence 1: Among them, chip identi.cation using power-up values of SRAM cells, called SRAM .ngerprints, has been emphasized lately [6 10] in part because SRAM cells are virtually free in a lot of cases (e.g., caches in the modern microprocessors, emerging use of SRAM-based FPGAs, etc.).
Sentence 2: accuracy is represented by system error rates.
Relationship: neutral
Domain: Hardware
Sentence 1: Given any partition, there can be at most m times of involved dis­cretization process since there are only m sets of Fsmall,j (note that at any partition differently colored capacitance can be actually from the same Fsmall,j in Figure 5).
Sentence 2: [8] J. Wang, X. Chen, C. Liao and S. Hu, The Approximation Scheme For Peak Power Driven Voltage Partitioning , in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2011.
Relationship: neutral
Domain: Hardware
Sentence 1: They compare the execution time of the two applications on a platform including a conventional DMA and a platform including the proposed DMA on its clusters, when increasing the size of the DMA data FIFOs that determines, in a conventional implementation, the number of outstanding transactions that can be performed by the DMA to hide the external memory latency.
Sentence 2: in the following, all the results are obtained performing cycle accurate simulations on a RTL platform including one cluster of OpenRISC processors as described in Figure 1, connected to a L2 memory that store the program and the data buffers used for the experiments.
Relationship: neutral
Domain: Hardware
Sentence 1: For the remaining input vectors of the circuit, g = h. Therefore, line g can be eliminated and replaced with line h. When line g is eliminated, all the logic that drives only line g can be eliminated as well.
Sentence 2: using accurate fault simulation of zero resistance bridges the experiments conducted in [5] indicate that A ­dominate and B -dominate faults capture the dominance behavior exhibited by bridges.
Relationship: neutral
Domain: Hardware
Sentence 1: In all the scenarios the RS-system reaches the maximum bandwidth using an amount of storage smaller than the cor­responding FF-system, with an improvement that goes from 40% in case of small values of K down to 15% for K equal to ten.
Sentence 2: hence, in the case of a persistent congestion the .its of a worm end up being stored in the router queues while the channel FF-repeaters are empty.
Relationship: neutral
Domain: Hardware
Sentence 1: Categories and Subject Descriptors B.4.3 [Input/Output and Data Communications]: Interconnec­tions Topology;J.6 [Computer-Aided Engineering]: Computer­aided design General Terms Networks, Algorithms, Performance  Keywords Networks on Chip, adaptive routing, deadlock-free routing, appli­cation speci.c 1.
Sentence 2: this technique is more prone to deadlocks than other switching techniques.
Relationship: neutral
Domain: Hardware
Sentence 1: Since these algorithms differ from one feature to the next, and therefore different kinds of similarities occurs, changing the feature under observation, the application aware approach must de.ne some managing rules for each different feature.
Sentence 2: the ratio of undetected error is less than expected, (should be 25%, since M = 4), since the aliasing does not occur when the fault inside the TCAM produces a pseudo-HIT.
Relationship: neutral
Domain: Hardware
Sentence 1: Datapath-oriented FPGA research has investigated logic con.g­uration bit-sharing [4], as well as interconnect con.guration-bit sharing and bus-based multiplexers [34].
Sentence 2: for both the M-CAD and M-HOT .ows, the compile-time  Frequency (MHz) 35 30 25 20 15 10 5 0 HOT Wf=0 HOT Wf=1 HOT Wf=4 Wf=0 Parser Max Wf=1 Parser Max Wf=4 Parser Theoretical Max Frequency CAD Wf=0 CAD Wf=1 CAD Wf=4  10 100 1000 CLBs Figure 7: Frequency versus area tradeoff for the ethernet benchmark.
Relationship: neutral
Domain: Hardware
Sentence 1: This is one of the most important aspects of EMMON, since it shows that our hier­archical architecture can scale easily to thousands of nodes by dividing the network into patches.
Sentence 2: the idea behind this simulation model was triggered by the need to build a very reliable model of the IEEE 802.15.4 and ZigBee protocols for Wireless Sensor Networks (WSNs).
Relationship: neutral
Domain: Hardware
Sentence 1: $10.00 Wei-Ngan Chin Department of Computer Science, National University of Singapore chinwn@comp.nus.edu.sg aliasing, where it is challenging [8] to maintain invariants of aliased objects otherwise.
Sentence 2: after a call to the ll build method, any caller will only be allowed to read the list, and cannot update it in any way.
Relationship: neutral
Domain: Hardware
Sentence 1: INTRODUCTION To cope with power/performance trade-off , the accepted solution to integrate multiple cores in a single chip poses new communication challenges, and Network-on-Chip (NoC) [1] emerges as a viable and effective design paradigm to manage performance and reliability requirements.
Sentence 2: chan, J. Sartori, P. Gupta, and R. Kumar, On the ef.cacy of nbti mitigation techniques, in Design, Automation Test in Europe Conference Exhibition (DATE), 2011, march 2011, pp.
Relationship: neutral
Domain: Hardware
Sentence 1: Thus, the Effective Number Of Bits (ENOB) of the A-ADC is independent of the hardware resolution M. This signal theory is completely dual with the Nyquist one where the time instants are precise, and the amplitude of samples is quantized.
Sentence 2: moreover, the Figure of Merit (FoM=2.1019) is twice higher than the one of recent classical synchronous Nyquist ADCs.
Relationship: neutral
Domain: Hardware
Sentence 1: STG Optimisation in the Direct Mapping of Asynchronous Circuits D. Sokolov, A. Bystrov, A. Yakovlev  School of Electrical, Electronic and Computer Engineering, University of Newcastle upon Tyne, UK Abstract Direct mapping from Petri nets (PN) and Signal Transi­tion Graphs (STG) avoids algorithmic complexity inherent in logic synthesis methods based on optimal state encoding.
Sentence 2: in some cases (e.g count) petrify failed to resolve a CSC con.ict (even if it was reducible) and our algorithm has completed the job.
Relationship: neutral
Domain: Hardware
Sentence 1: SPECint95(refinput,frst1billioninstructions) 2.3StatisticalCodeGeneration Oncethestatisticalprofleisgenerated,thefrststepinthe simulationprocessistogeneratethesymboliccodesample.
Sentence 2: insomerespectsthegoalsofourapproacharesimi­lartothegoalsofthecreatorsofthesyntheticWhetstone [CWW76]andDhrystone[Wei94]benchmarks.weattempttoprovideanautomatedapproachtogenerat­ingasyntheticbenchmark.Furthermorethisautomated approachisbaseduponanalysisofrealprogramsandis demonstrablymorerepresentativeofactualmachineper­formance.
Relationship: neutral
Domain: Hardware
Sentence 1: Inputs Clock (a)  Inputs Emulation Clock Memory elements Main  Clock (b)  Figure 4: (a) A sequential circuit, (b) The sequential circuit emulated at the switch-level To ensure proper operation, the time between two main clock transitions must be longer than the time it takes the combinational circuit (which is emulated at the switch-level) to reach a stable state.
Sentence 2: in order to attain a better utilization of the FPGA resources a mixed­mode emulation approach has been used.
Relationship: neutral
Domain: Hardware
Sentence 1: Hence, we believe that the proposed self-calibrating SRAM can reduce standby power without significant yield degradation.
Sentence 2: in our simulation to determine the adaptive source biasing voltage for a 2KB memory array, we pick a chip from an inter-die corner and find the total number of failing cells (NF) at a source bias N = NP F cells hfcell (5)  1.2 1  1 I n put : # of redu n d an t col .
Relationship: neutral
Domain: Hardware
Sentence 1: Fast pll simulation using nonlinear vco macromodels for accurate prediction of jitter and cycle­slipping due to loop non-idealities and supply noise.
Sentence 2: the PPV macromodel, as developed so far, only predicts oscillator behavior under electrical perturbations (such as power supply interference and thermal noise); it is not variability aware, i.e., it does not take into account, e.g., random and systematic process variations.
Relationship: neutral
Domain: Hardware
Sentence 1: 3In our experiments, Feng Shui 1.2 misinterpreted row infor­ mation in PEKO01 benchmarks.
Sentence 2: pE Opti-Kraft +DO Capo Dragon Feng mPL KO mal Werk MINO 8.6 2.20 Shui 1.2 1.2b #WLWLWL WL WL WL WL 66666 66 [15] .e.e.e.e.e.e.e 01 0.81 1.39 1.74 1.29 1.46 3.18 1.17 02 1.26 1.98 2.61 2.03 2.43 5.26 1.78 03 1.50 3.02 3.78 2.66 2.93 6.82 2.33 04 1.75 3.25 4.25 3.12 3.87 8.09 2.35 05 1.91 3.92 4.79 3.16 3.79 9.08 2.77 06 2.06 4.07 5.38 3.57 4.35 10.14 2.98 07 2.88 5.73 7.56 5.07 6.24 12.55 4.29 08 3.14 5.87 8.17 5.57 6.79 13.78 4.95 09 3.64 8.52 10.74 6.47 7.72 16.24 5.42 10 3.73 8.9 12.03 8.0 8.49 20.12 7.01  Table 2: HPWL on 10 out of 18 PEKO benchmarks in suite 1.
Relationship: neutral
Domain: Hardware
Sentence 1: To aid with this process, re­searchers have developed a number of anonymization techniques to scrub data for release [10, 18, 5, 14, 13].
Sentence 2: the authors de-anonymization scheme clearly has signi.cant merit, since in addition they employed the same anonymization techniques as used on the LBNL traces on their own packet traces (in line with the approach for which we advocate above), for which their de-anonymization techniques worked well.
Relationship: neutral
Domain: Hardware
Sentence 1: As the soft error injection rate increases, a conven­tional implementation of the image segmentation algorithm rapidly degrades until the output image is no longer recognizable.
Sentence 2: (6) t=0 i=0 j=0 Based on equation (4), (5), and (6), we obtain i j t· t x y Pt = Pi×N+j = , (7) Mr-1 Nr-1 tu · tv x y u=0 v=0 where tx and ty are, PX PK tx = · , 1 - PX 1 - PK PX 1 - PK ty = · .
Relationship: neutral
Domain: Hardware
Sentence 1: To accessdatafrom arow Aofasubarray, theDRAMcon­troller first issuesanACTIVATE commandwiththerow address.
Sentence 2: itcanensurethatthedestinationisal­locatedinthesamesubarrayasthesource,therebyenablingthe processortouseFPMtoperformthecopy.
Relationship: neutral
Domain: Hardware
Sentence 1: As de.ned earlier, xm and v are: xm =[(xu|s0)D0 T + s0 × [1]n0 ×1]/m (19) (xu|s0 - xm)D(xu|s0 - xm)T+(s0 - xm)(s0 - xm)T v = (20) m - 1 Those two variables xm and v illustrate the underlying char­acteristics of the conditional chip oxide thickness distribution given measurements s0 at n0 sites.
Sentence 2: we can perform a re.nement step iteratively to reduce the deviation to a negligible level, i.e.,tomake uchip xN+n0 by repeatedly replacing uchip in (13) with xN+n0 and then computing xN+n0 with (16).
Relationship: neutral
Domain: Hardware
Sentence 1: somelinksmaybeover-utilized(i.e.
Sentence 2: each node can continuously monitor thebuffer evolution ofitsprevioushop byusing a simple sniffer routine such as tcpdump;(iii)we coded three newfunctionstothewlancon.g commandin orderto access theinstantaneousbufferqueue occupancy andto access and mod­ifythe maximalMACqueuelength(usuallylockedto50 packets).
Relationship: neutral
Domain: Hardware
Sentence 1: INTRODUCTION Over the past decade, we have witnessed the rapid pro­ liferation of the wireless technologies that are widely used in various areas including consumer electronics, education, energy, health care, and public safety.
Sentence 2: if the received energy has an energy level higher than the energy threshold as well as the bandwidth of the received signal is higher than band­width threshold, the received signal can be considered as a desired signal.
Relationship: neutral
Domain: Hardware
Sentence 1: Last, the wire load between two pins p1 and p2, WL(p1,p2), could be estimated by, WL(p1,p2)= MDh(p1,p2) · Uh(p1,p2)+ MDv(p1,p2) · Uv(p1,p2) (3) where MDh(p1,p2)(MDv(p1,p2)) represents the Manhattan distance in horizontal (vertical) direction.
Sentence 2: when the ECO size is large, those spare cells may not always be found in the ideal area and tools need to search for the nearby gates to substitute.
Relationship: neutral
Domain: Hardware
Sentence 1: Given that the completion of an OCPce port request requires all OCPi ports to ac­knowledge (step 5), no upcoming con.icting OCPce port request will be completed, because the blocked OCPi port will not acknowledge its corresponding system intervention.
Sentence 2: a typical optimization that a system architect applies to non-broadcasting coherence schemes is 3-way communication (or 3-party transaction).
Relationship: neutral
Domain: Hardware
Sentence 1: Note that, in Theorem 1, a(t) covers any deterministic arrival curve, linear and nonlinear.
Sentence 2: tH To estimate Hurst parameter H, there are a number of methods: analysis of R/S (Range/Scale, rescaled adjusted range) statistic, analysisofthevariance-timeplot,theWhit­tle estimation and analysisbased on waveletfunction[13].
Relationship: neutral
Domain: Hardware
Sentence 1: The correct Verilog code would look like: o1 = (({1 b0,b4}+{1 b0,c4}) > 5 hF); This problem also occurs with right shifts (>>) and other types of comparisons (e.g., , ==, !=).
Sentence 2: its size equals the sum of the widths of all the .elds in the structure.
Relationship: neutral
Domain: Hardware
Sentence 1: Form factor    Thinning and Joined Points Polygon Extracted Endpoints Fig 2. various stages for extracting polygon  2.3 Signature Classification Euclidean distance is the most common measure of dissimilarity and is used by our system.
Sentence 2: iNTRODUCTION Off-line signature verification can be used in many applications such as cheques, certificates, contracts and historical documents.
Relationship: neutral
Domain: Hardware
Sentence 1: ALL SPECint GraphicsPointer bzip2 gzip mcfparserperl twolf ammpartequake facerec fma3d lucas mesamgridsixtrackswim 1.21 1.26  missed/non-forwardings, causing loads to stall until all prior stores have committed.
Sentence 2: conventional implementations of out-of-order instruction windows are limited with respect to how large they can be scaled be­fore negatively impacting the overall processor clock speed and power consumption.
Relationship: neutral
Domain: Hardware
Sentence 1: Barring unforeseen rapid adoption of restricted layout practices, DPL is likely to play a more important role than previously anticipated, since lithography alternatives such as hyper-NA immersion lithography and EUV are continually delayed.
Sentence 2: a well-known example: the appropriate juncture for correction of poly-layer litho hotspots is after detailed placement, but before routing.
Relationship: neutral
Domain: Hardware
Sentence 1: The savings in energy per instruction (total energy dis­sipated) ranges from very low values to 8%.
Sentence 2: since we were testing con.gurations with RUU sizes of 16, 32, 48 and 64 and with fetch rates of 4, 6 and 8, we had a total of 4 .3=12 con.gurations, requiring an FSM of only 12 states.
Relationship: neutral
Domain: Hardware
Sentence 1: During BM addition, a similar concept to carry-save addition is applied: instead of propagating the carry from the LSB part to the MSB part as in regular ACSU, the carry is saved to the sec­ond clock cycle.
Sentence 2: a .exibility in recursive ar­chitecture is that you can retime the feedback register to a place where it is easy to estimate the output and correct the timing errors as shown in Figure 7(b) where it maybe easier to correct errors at the output of block C than at the output of Block A.
Relationship: neutral
Domain: Hardware
Sentence 1: A PASS signal from the property checker provides strong evidence that the acquired micro­processor is trusted because it is consistent with the de.ned security properties.
Sentence 2: fixpoint update (u:updateblock)(t:nat) {struct u} := (* Non-blocking assignment *) match u with | (upd_expr bus exp) => (bus (S t)) = (eval exp t) | (updcons block1 block2) => (update block1 t) / (update block2 t) | upd_useless => True end.
Relationship: neutral
Domain: Hardware
Sentence 1: v T I,J=1 I,J=2 I,J=4 I,J=8 I,J=16 1 2 4 8 16 256 256 256 256 256 256 256 256 256 256 256 256 256 256 257 16385 4096 1024 259 260 16385 4097 1027 272 272 Address Difference Figure 5.
Sentence 2: a performance bottleneck is observed for a subset of video processing memory access patterns for which sub-optimal cache behaviour occurs [1].
Relationship: neutral
Domain: Hardware
Sentence 1: When the industry is entering the nanoscale era, the worries about reliability is even worsened, as their bottom-up manufactering processes are inherently prone to defects and their runtime faults are expected to be high, caused by shunkened device demensions and low supply voltages.
Sentence 2: the stress time window for NBTI and HCI is illustrated in Figure 4 for an inverter circuit.
Relationship: neutral
Domain: Hardware
Sentence 1: Also, it can shorten the test application time because the length of the scan chains becomes shorter.
Sentence 2: ncan be represented by the following binomial distribution if the probability of a scan-out response being an unknown (p)is the same for every response: (sn {N=n}=n) p (1 p)s-n(4) We can now re-express the E[f(K)]in Equation(3) as a function of N(denoted as EN[f(K)]), and a response s unobservable proba­bility () becomes: s = .
Relationship: neutral
Domain: Hardware
Sentence 1: If a node has already forwarded a packet for the source node, it is reasonable to assume that, because it already has spent en­ergy for forwarding, it wants to maintain a good status in the eyes of the source.
Sentence 2: the model can be seen to be­ information about nodes that belong to its neighborhood Gi and nodes that belong to Gi are assumed to have beliefs about the class of node i and vice versa.
Relationship: neutral