sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Because of its shared nature between the input and output schedulers, the internal bu.ers occupancies can serve as a good arbitration criterion.
Sentence 2: our previously proposed MCBF (Most Critical internal Bu.er First) algo­rithm [9] was shown to outperform all existing algorithms while basing its scheduling decision exclusively on the inter­nal bu.ers occupancies only.
Relationship: entailment
Domain: Hardware
Sentence 1: As a result, in a TR LLC controlling eviction fre­quency, by delaying when misses are served for each task, is enough to trustworthily upper-bound the maximum e.ect that such task may have on other co-running ones in the LLC.
Sentence 2: the WCET estimated for a task ti is trustworthy regardless of its particular co-runner tasks as long as their aggregated miss frequency and so their eviction frequency  is below the pre­de.ned miss frequency threshold, M Ti, for which ti s WCET estimate is computed.
Relationship: entailment
Domain: Hardware
Sentence 1: Nei­ther of these techniques, however, can guarantee freshness.
Sentence 2: this is because even if the client encrypts the data and uses a signature or MAC, this does not prevent an adversary who can access and manipulate the memory, disk space, or software of the untrusted server, or who can intercept and manipulate messages transmitted over the untrusted network, from performing a replay attack.in response to a read request, the adversary can replace the most recent signed and encrypted version of the desired data with an older but likewise signed and encrypted version.
Relationship: entailment
Domain: Hardware
Sentence 1: Training network: We will use two networks for letters &#38; numbers training with noises, in each network we will adjust the weights of each unit in such a way that the error between the desired output and the actual output is reduced, we compute the error derivative of the weights.
Sentence 2: it must calculate how the error changes as each weight is increased or decreased slightly, the MLP network trained with input vector Xi and desired output Dj , m input layers (m=200), l hidden layers was picked by guesswork and experience (l=10), n output layers (n=15 for letters recognition, n = 10 for numbers recognition).
Relationship: entailment
Domain: Hardware
Sentence 1: Measurement Testbed Architecture with QMA More specifically, air-ground, wireless ad-hoc and satellite segments have been considered to emulate a particular emergency scenario where terrestrial, on board of an aerial vehicle, and both local and remote headquarters operators have to effectively collaborate.
Sentence 2: air-ground segment has been emulated by Wideband Radio Channel Emulator made by Elektrobit, named PropsimC2.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION S  p+(VBN) n+(VBP) Major challenges in developing deep-sub volt embedded (e-) NiSi DRAMs are to achieve a high signal-to-noise-ratio (S/N) cell SOI G G array with a logic-compatible planar cell and high-speed midpoint (tSOI < 20 nm) S D S D sensing (i.e., a half-VDD data-line precharge), and to reduce the BOX p+ n+ (tBOX < 10 nm) speed variation of peripheral circuits caused by the threshold (VT) n-Well STI variation of MOST.
Sentence 2: noise in the array must be p-Sub  significantly reduced.
Relationship: entailment
Domain: Hardware
Sentence 1: The .ow throughput decreases from ck to ck/m for each ring k. 4.2 Admission control based on the minimum data rate We now consider an admission control based on the mini­mum data rate: a new data transfer is accepted if and only if its rate and the rate of ongoing transfers would be larger than cmin.
Sentence 2: the admission decision now de­pends on the location of users.
Relationship: entailment
Domain: Hardware
Sentence 1: Towards this goal, we design our system with the following considerations: (i) ability to work across metering devices with different sampling rates; (ii) support for easy installa­tion and untethered operation; (iii) scalability and .exibility for users to target speci.c subsets of end-loads at distributed locations for the monitoring.
Sentence 2: the second and third design considerations require the add-on mote sensor to run on battery with aggressive sleep scheduling to con­serve energy.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition, the G for interconnect is non-singular in VNA.
Sentence 2: let the resulting BBD system equation is L-1 at branch ik be an element between node vi and vj .The kk Yx= Bu (19) product of ElL-1 is where 3 ik 2 3 ik 3 2 Y1 0 ... 0 X10 .
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we show that we can solve such potential timing violations in high-level synthesis without degrading speed performance, but by devising register assignment and clocking scheme.
Sentence 2: we will combine Backward-Data-Direction (BDD) clocking, Forward-Data-Direction (FDD) clocking, and Structural Robustness against delay Variation (SRV)-based register assignment to solve potential timing vi­olations.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition, it shall be noted that compared with conven­tional color assignment problem, in TPL-OSR the solution space is much larger.
Sentence 2: to resolve the coloring con.ict between two abutted cells ci, cj , apart from picking up com­patible coloring solutions, TPL-OSR can seek to .ip cells (see Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: It turns out kernel based learning methods such as support vector machines [5] [6] are useful tools for this purpose.
Sentence 2: this paper adopts kernel ridge regression [7] [8] and the related con.dence interval computing algorithm [9] to construct such analog models for the digital block and estimate the error interval, the latter of which ensures the conservativeness of this conversion as required by formal ver­i.cation.
Relationship: entailment
Domain: Hardware
Sentence 1: Loh and Hill observed that the tags and data reside in the same DRAM row, and so the actual latency of a cache hit can be less than two full accesses by exploiting row buffer locality [11].
Sentence 2: the DRAM row is opened or activated into the row buffer only once, and then tag and data requests can be served directly out of the row buffer at a lower latency compared to two back-to-back accesses to different rows.
Relationship: entailment
Domain: Hardware
Sentence 1: xzhao@us.ibm.com, yangwan@gatech.edu, mikeman@us.ibm.com, limsk@ece.gatech.edu Abstract In this paper, we present a transient modeling of electromi­gration (EM) in TSV and TSV-to-wire interfaces in the power delivery network (PDN) of 3D ICs.
Sentence 2: we model atomic depletion and accumulation, effective resistance degradation, and full chip-scale PDN lifetime degradation due to EM.
Relationship: entailment
Domain: Hardware
Sentence 1: A link is composed of either 8 or 16 lanes, each of which transfers one bit at a time with 10 to 15 Gb/s of the signaling rate.
Sentence 2: between o.-chip link transceivers and vault controllers, there exists a crossbar network to route each packet to the vault corresponding to its target address.1 unlike traditional memory organization where each memory address is statically mapped to a speci.c channel, any link can be used to transmit a packet regardless of its target address as shown in Figure 2.
Relationship: entailment
Domain: Hardware
Sentence 1: also encoding the local or the contextual labels as follows: A simple stratagem used to accelerate the clustering pro­ cesses is to start the algorithms with codebooks properly = f(ci,LN (i)) (2) c initialized [14].
Sentence 2: a good initialization of code-i books for the current task could be one of those proposed where LN (i)is the setof labels of node i, ci is the start­ i is the resulting centroid also encoding the for the baseline algorithms, i.e.
Relationship: entailment
Domain: Hardware
Sentence 1: Mainstream AMD GPUs tended to outperform NVidia GPUs in terms of Gh/s per $, in part due to a instruction set well-suited for the bit-level nature of the SHA256 algorithm, and also because the AMD VLIW ISA provides for a greater number parallel ALUs running at slightly lower frequency than NVidia products.
Sentence 2: rotate operations and bit-wise choose operations could be implemented with single instructions in the AMD ISAs.
Relationship: entailment
Domain: Hardware
Sentence 1: Based on the values of X and Y, which are in turn computed by our leakage minimization algorithm, this gate is changed as follows: If (X==1) out = g(in)  else if (Y == 1) out = OR(NOT(SLEEP), g(in)) else out = AND(SLEEP,g(in)) Modifying this gate as described above enables controlling the output of the gate independent of its inputs in the standby mode.
Sentence 2: if we must have a ONE at the output of the gate when in the standby mode, we replace the gate with AND(SLEEP,g(in)).
Relationship: entailment
Domain: Hardware
Sentence 1: A simpli.ed model of spatial correlation can be achieved by partitioning the chip into N grids and assum­ing perfect spatial correlation within each grid [11, 12].
Sentence 2: the devices within one grid have the correlation coe.cient of 1 and hence bear the same spatially-correlated variation component, whereas devices in two di.erent grids, ith and jth corr for example, have a covariance of .i,j s2 ,with a correlation coe.cient .i,j <1 [11].
Relationship: entailment
Domain: Hardware
Sentence 1: Each sensor provides the con­troller with a measurement; an interval containing all possible values of the true state is then computed based on that sensor s precision, implementation guarantees and sampling jitter.
Sentence 2: if the manufacturer s precision guarantee is d, then an interval of size 2d centered at the sensor s measurement is constructed; the interval size is further increased if the worst-case guarantees for sampling jitter (and implementation limitations) are considered (e.g., the design of intervals in [5]).
Relationship: entailment
Domain: Hardware
Sentence 1: This means that its design and implementation is simpli.ed by building off of the existing lan­guage, adding some features and restricting others.
Sentence 2: bioProto modi.es Proto as follows: Primitives can be annotated with genetic regulatory network speci.cations, and  Only a restricted subset of Proto is used, excluding all non-Boolean types, all operations that require non-Boolean types, and all operations over space or time.
Relationship: entailment
Domain: Hardware
Sentence 1: Although the attenuation values spans over a large range (in this example from -53 dB to -34 dB), the transmitting power, Pt ,is set assuming the maximum attenuation, GAmax,that in this case is -53 dB.
Sentence 2: pt = Pr - Gamax, where Pr is the required receiving power which guarantees a certain BER: 2 Pr = N0Rb [Q-1(BE R)r, where, N0 is the transceiver noise spectral density, Rb is the data rate, and Q-1 is the inverse function of the tail probability of stan­dard normal distribution.
Relationship: entailment
Domain: Hardware
Sentence 1: Xc = xab ni k The second type of closure constraints combines all variables Xc that correspond to all nets connecting chip c with other chips using the pin type k. Among variables belonging to Xc k there should be no more than m variables equal to 1.
Sentence 2: in every group of m+1 variables belonging to Xc k , there should be at least one variable equal to 0.
Relationship: entailment
Domain: Hardware
Sentence 1: (iv) Their diagnosis time is dominated by the time for diagnosing Data Retention Faults (DRFs), which, in practice, are diagnosed by performing a read operation following a predetermined delay (e.g., 100 ms) [3].
Sentence 2: the total diagnosis time for these small e-SRAMs is at least a couple of hundred milliseconds, regardless of the memory size/capacity and diagnosis methodology, e.g., parallel or sequential diagnosis.
Relationship: entailment
Domain: Hardware
Sentence 1: These protocols to­gether can be represented in a semi-lattice or a lattice, with the least constrained and most constrained protocols as its top and bottom elements, respectively.
Sentence 2: the unique top element corre­sponds to the most concurrent protocol for which safe data compu­tation is guaranteed (i.e., no data overrun or sampling of stale data), as derived in Sections 3.2 and 3.3.
Relationship: entailment
Domain: Hardware
Sentence 1: An operation v is extendable if v can be assigned to the low Vdd and executed in multiple clock cycles, and the extended execution delay of v will not violate the overall latency constraint, and in the same time, the data dependencies between v and other operations are still valid.
Sentence 2: v will still generate its data in time so that the data can flow to all the other operations that require it.
Relationship: entailment
Domain: Hardware
Sentence 1: E.ectively,in our system, the size ofa memory regionhas noimpact ontheperformance of the co­herencyprotocolbecausethenumber of cachessharingdata in that region is limited to the caches in a node.
Sentence 2: as each memory region is an independent coherency domain,aprocessorbound toacertain memory regiondoes not need to know what happens in other regions, and thus changesina memory regionareonly noti.edtothecachesof that memory region.
Relationship: entailment
Domain: Hardware
Sentence 1: Z+ indicates the queue size for an edge e, denoted as q(e).
Sentence 2: for an edge e = (v1, v2), w(e) specifies the number of tokens in the place on solid edge from transition v1 to transition v2 and q(e) specifies the one on dashed edge from transition v2 to transition v1 in the original MG, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: For instance, L1 caches occupy 50% chip area and are one of the main energy contributors in the ARM Cor­tex A5 processor [3] in order to improve energy e.ciency at HP mode.
Sentence 2: our approach is built on top of a 6T+10T hybrid cache although any other hybrid con.gura­tions proposed in [16] may be used.
Relationship: entailment
Domain: Hardware
Sentence 1: R_node R_cwise R_ccwise R_across  Figure 4: Octagon Router  4.2 Veri.cation of the RTL Implementation Model We have written a request-response tra.c environment and a basic router model in VHDL.
Sentence 2: a request is generated at a source Octagon node to be sent to a destina­tion Octagon node.
Relationship: entailment
Domain: Hardware
Sentence 1: or: scl(si1,wj1) + scl(si2,wj2) .
Sentence 2: scl(smax,wmax) +scl(si4,wj4) (5) where, (si4,wj4) = argminDist(I(si1,wj1)+(si2,wj2), I(smax ,wmax )+(s,w))(s,w) for a 3 core processor, one of which hosts a0 and the remaining two cores host2 other applications, instead of measuring performance degradation with all scl settings for the re­maining two cores, we only need to measure performance with (i) all possible settings of scl on one core (which effectively covers also the scl pairs satisfying the conditions for Equation (4)) and, (ii) scl (smax , wmax )on one core and all settings of scl on the 3rd core (covering the combinations satisfying Equation (5)).
Relationship: entailment
Domain: Hardware
Sentence 1: In the PBCA, BS of a cell is able to pro-actively allocate channel resource by estimating the channel request based on the predicted location information in order to reduce the ratio of dropping call request within hotspot cells.
Sentence 2: if a BS predicts that it will need more channels than its own channel limit after a speci.c lookahead time, it pro-actively borrows available channels from neighboring cells before re­ceiving surge of call requests.
Relationship: entailment
Domain: Hardware
Sentence 1: Because a lower value of Nsampgives rise to a higher uncertainty in the objective function evaluation, a larger number of generations is required for a stable evaluation of the performance of designs.
Sentence 2: because the value of Nsampis directly correlated with the reliability of the clock speed estimate, GAs run­ning with low Nsampvalues require more generations to properly evaluate the performance of designs.
Relationship: entailment
Domain: Hardware
Sentence 1: Returning to our running example, let us derive from D a slightly higher abstraction, having the same objects and relation L as D but only one additional relation G= N. S. This abstraction, which we call U,provides partial information about a user s interpretation of the SFC diagram.
Sentence 2: g contains exactly those action-step associations which are explicitly guaranteed in the diagram, and thus hold in all semantic interpre­tations which respect the meaning of quali.ers.
Relationship: entailment
Domain: Hardware
Sentence 1: Li = Ci +1 ÷-1 (34) i =1 «i =1 Ci «i =1 .
Sentence 2: c0 / for a chain of N identical gates with logical effort g, LGR is preferable in terms of power if Nrep > N = g (35) In terms of delay, it would be beneficial to combine the two techniques: use smaller wire segments and add some repeaters.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition, the multipliers and accumulators in the asynchronous data-path consist of fine-grain partitioned bit-slices that are selectively activated by mask control signals.
Sentence 2: the MASK unit identifies bit-slices of input data that contains non-SEBs as well as the special case in which the data is  MSB LSB Input ( x1 ' ) m(3) m(2) m(1) 4 >>9 2 >>7 0 >>5 0 >>4 >>2   Figure 4.
Relationship: entailment
Domain: Hardware
Sentence 1: In Figure 5 an example of assembly code is reported by which it is possible to read a register with all read_ports of the selected domain.
Sentence 2: considering the domain 1 and the register r0.0 we notice that this register is used as operand 1 in the first instruction of the macro-instruction 1 and then as operand 2 in the first instruction of macro-instruction 2.
Relationship: entailment
Domain: Hardware
Sentence 1: Synthesis of Low Power Clock Trees for Handling Power-supply Variations Shashank BujimallaCheng-Kok KohSchool of Electrical and Computer Engineering, School of Electrical and Computer Engineering, Purdue University, W. Lafayette, IN 47907, USA Purdue University, W. Lafayette, IN 47907, USA sbujimal@purdue.edu chengkok@purdue.edu ABSTRACT The International Symposium on Physical Design (ISPD) 2010 contest presents the challenge of synthesizing clock dis­tribution networks that are tolerant to severe power-supply and wire-width variations.
Sentence 2: a robust clock net­work should satisfy the local clock skew (LCS) constraint, i.e., the clock skew between any pair of sequential elements that are closer than a user-speci.ed distance is below a user­speci.ed limit, even in the presence of variations.
Relationship: entailment
Domain: Hardware
Sentence 1: These 32 data input signals will actually reuse some of the signals that are the inputs the ESB when it is in RAM mode.
Sentence 2: the 16 bit data input bus, the 11 bit read address bus and the low order 5 bits of the write address bus will be used as the 32 literal input signals for the ESB in product term mode.
Relationship: entailment
Domain: Hardware
Sentence 1: To understand the performance impact of each front-end technique, we applied one technique at a time to the baseline and measured the resulting IPC degradations normalized to the baseline (Figure 4).
Sentence 2: each stack from top to bottom represents the following in cumulative form: IPCs when adding commit-time misprediction recovery (&#38; Chkpt Removal); our most aggressive speculation control of allowing only one in-flight unresolved branch (&#38; Spec Cntrl); fetch buffer resizing (&#38; Fetch Buff); and register file resizing (&#38; Regs).
Relationship: entailment
Domain: Hardware
Sentence 1: Our experiments have shown however that for the .lter­ing engine application, the variable ordering does not have a strong in.uence on the BDD size, apparently because the boolean functions we consider are shallow, i.e., structurally simple, but numerous.
Sentence 2: the natural variable ordering where either BDD variables corresponding to the same attribute are kept close together, or variables are or­dered according to frequency, both give good results; how­ever they do not show signi.cant improvement over random orders.
Relationship: entailment
Domain: Hardware
Sentence 1: More importantly, the PL and PL-EC-Perf variations of Knapsack and LRU-Ordered can conserve at least as much en­ergy as state-of-the-art techniques that conserve energy explicitly in the absence of a power limit, for equally small performance degra­dations.
Sentence 2: these techniques can match the energy sav­ings of the latter approach by appropriately setting the power bud­get.
Relationship: entailment
Domain: Hardware
Sentence 1: Our aim is now to .nd the bucket which contains the Median.
Sentence 2: we .nd j such that the following three constraints are satis.ed: el + c0 + c1 + ... + cj-1 < (N + 1)/2 (2) c0 + c1 + ... + cj = (N + 1)/2 (3) cj = 2EN (4) where el is equal to 0 in the .rst iteration and updated as follows in other cases.
Relationship: entailment
Domain: Hardware
Sentence 1: The constraint of x is tokeep thepoly-to-poly space x to be withingivenprocess tolerance P andlayoutdesign tolerance D. Theprocesstolerance, P,de.nesthelimitation oflithog­raphy patterning for poly layer.
Sentence 2: we can not get a proper gate patterning image below a certain pitch of poly.
Relationship: entailment
Domain: Hardware
Sentence 1: The re­sults show thatSHiP-PCand SHiP-ISeqboth dynamicallycorrelatethe current program context to an expected re-reference interval.
Sentence 2: sHiP-PC and SHiP-ISeq are especially effective inmanaging a commonly found access pattern in applications such as halo, excel, gemsFDTD,and zeusmp.Figure 7 captures astreamofmemoryreferencestoaparticularcachesetingemsFDTD.
Relationship: entailment
Domain: Hardware
Sentence 1: As respect to the event rate, the plots indicate that semi-asynchronous checkpointing allows an acceleration of the simulation model execution.
Sentence 2: the best event rate of semi-asynchronous checkpointing is about 63 × 103 events per sec., while the best event rate with CPU based checkpointing is about 58 × 103 events per sec., thus semi­asynchronous checkpointing provides a performance gain in the order of 9%.
Relationship: entailment
Domain: Hardware
Sentence 1: On the other way, and with a more applicable point of view, the two other speakers will talk about certain optical and quantum devices.
Sentence 2: dr de Riedmatten from the Institute of Photonic Sciences will dissert about quantum memories as an alternative to the actual magnetic memories, while Dr. Assefa will expose his last research in IBM Thomas J. Watson Research Center about nanophotonic devices for next generation of supercomputers.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION This paper explores the design space of memory-management unit (MMU) caches for accelerating virtual-to-physical address translation in processor architectures, like x86-64, that implement paged virtual memory using a radix tree for their page table.
Sentence 2: these caches accelerate the page table walk that occurs after a miss in the Translation Lookaside Buffer (TLB).
Relationship: entailment
Domain: Hardware
Sentence 1: Alternately, the lfp bound n and the gfp bound m together give the completeness bounds for BMC on the property F(p.G(q)).
Sentence 2: for our customized formulation of property F(p.G(q)) (in Figure 3) we need to search for a path prefix (called stem) of length at most n to a state, where p=true and from which there exists a finite path of length m where q=true always.
Relationship: entailment
Domain: Hardware
Sentence 1: Experimental results show that our algorithms can e.ectively generate con.ict-free mi­grated layouts with 14% smaller layout areas and 28% smaller layout changes, compared with the traditional method of layout decomposition followed by layout migration.
Sentence 2: our re­duction technique can reduce the runtimes for the test cases from more than one day for the basic ILP formulation to only seconds.
Relationship: entailment