sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: We also include nonredundant can­didates whose Q are decided by both T(v1)and T(v2)si­multaneously.
Sentence 2: for each candidate ai in A(v2), we want to .nd a candidate ßj in A(v1) such that Q(v1,ßj) =Q(v2,ai), and C(v1,ßj) is the minimum among all such ßj s. we want to .nd index j: j =min {k |ßk .A(v1),Q(v1,ßk) =Q(v2,ai)}.
Relationship: entailment
Domain: Hardware
Sentence 1: Theorem 1: For two random variables (possibly correlated), Aand B, with arbitrary distributions, the following identity holds: P(A = B)= P(A = A&#38;A = B)= P(A = max(A,B)).
Sentence 2: (4) the probability that A exceeds B is the same as the probability that A exceeds max(A,B).
Relationship: entailment
Domain: Hardware
Sentence 1: Fast and Accurate Transaction Level Models using Result Oriented Modeling Gunar Schirner and Rainer D ¨omer Center for Embedded Computer Systems University of California, Irvine, USA {hschirne,doemer}@uci.edu ABSTRACT E.cient communication modeling is a critical task in SoC design and exploration.
Sentence 2: fast and accurate communication is needed to predict the performance of a system.
Relationship: entailment
Domain: Hardware
Sentence 1: According to Theorem 1, we can compute edge criticality as t = P(A = B)= P(A = max(A,B))= P(A = C), (5) where A is the edge slack, B is the complement edge slack, and C = max(A,B) is the chip slack, which is the max delay of all paths from the source to the sink or simply AT at the sink node.
Sentence 2: the criticality of edge e is the probability that its edge slack dominates the chip slack.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition, based on the throughput rate of 400 M pixels/sec, Wang s design [4] re-designed and the proposed SPST­based design respectively consume 10.96mW and 9.83mW.
Sentence 2: the proposed design achieve about 10% power improvement when compared with Wang s design [4] re-designed, based on the same data throughput rate.
Relationship: entailment
Domain: Hardware
Sentence 1: As each CLB input (other than LUT feedbacks) is driven by a W×Fcin:1 multiplexer, reducing the number of CLB inputs reduces the overall cost of the C Block, at the expense of some flexibility.
Sentence 2: n independent K-input logic functions cannot be packed into a CLB due to I/O limitations, despite the fact that the CLB has sufficient LUT capacity.
Relationship: entailment
Domain: Hardware
Sentence 1: A basic logic element (e.g., a Logic Element in Altera Stratix FPGAs or a Slice in Xilinx Virtex series FPGAs) contains a LUT as well as a flip-flop, so that the output of a logic gate (implemented in LUTs) can be configured as either an unregistered mode or a registered mode.
Sentence 2: if a logic gate is connected to only one register, it can be implemented in the registered mode.
Relationship: entailment
Domain: Hardware
Sentence 1: The con­trol bits generating algorithm is presented in Section V. }, at least one encoded cofactor of each pair is equal to ** {f ,f ¯ 3 or 5.
Sentence 2: the theorem is true if we can prove thatno matrix X can yield a 3, 5, or both for all the three encoded x zz cofactor pairs at the same time.
Relationship: entailment
Domain: Hardware
Sentence 1: Different from the guard-banding approach employed in [1,16], where multiple models are required to make identical decisions, the guard band invoked here uses a single model.
Sentence 2: testing is only terminated after the model predicts test termination for M successive failing patterns, where M is an integer that can be 0 (no guard banding), 1, 2, etc.
Relationship: entailment
Domain: Hardware
Sentence 1: To thoroughly investigate the aforementioned performance im­ pact and interplay of SSD advanced commands, allocation strategy, and data granularity, in this paper, we carefully examine several internal behaviors rarely discussed in the literature, which may have potentially important impact on the performance and endurance of SSD.
Sentence 2: we carry out in-depth evaluations of these fea­ tures and their interplay, obtaining the following main insights.
Relationship: entailment
Domain: Hardware
Sentence 1: Moreover, we can also note that the possible P-circuit implementations of f differ in the distribution of the = d= points of I among the three sets f, f, fI .
Sentence 2: each minterm in I can be associated to one of the following outputs of Rf: 001 if it belongs only to fI, that is, it has been kept = in I, and not added to f= and fd; = 101 if it has been added to fand it is kept in I; d = 011 if it has been added to fand it is kept in I; = d= 111 if it has been added to fand f, and it is kept in I; = 110 if it has been added to f= and fd, and it is removed from I.
Relationship: entailment
Domain: Hardware
Sentence 1: 3 We need to show that the probability that the NLFSR output does not repeat within the composite m-sequence of the 3 LFSRs can be made asymptotically low.
Sentence 2: we need to show that for two different clock cycles j and k in the composite m-sequence of jjj the 3 LFSRs, p(M(V1 ,V2 ,V )= M(V1 k ,V2 k ,Vk)) .0 for an appro­ 33 priately large n. To show this, we note that for the majority function computing the output of the ith bit of the NLFSR, the output will be the same across two clock cycles j and k if at least two of the sets {V1 j ,V1 k}, {V2 j ,Vk}, and {V3 j ,Vk} contain identical values.
Relationship: entailment
Domain: Hardware
Sentence 1: Experimental results .rst demonstrate that reducing corners in power rings signi.cantly mitigates IR drop, and then show that the proposed algorithm can reduce the number of corners by 33% on average for the GSRC .oorplan benchmarks.
Sentence 2: the total running time for the 16 GSRC benchmarks is less than one second on an AMD-64 machine with a 2.2 GHz CPU and 8 GB memory.
Relationship: entailment
Domain: Hardware
Sentence 1: Alternatively, it could be used for routing two nets, both of e.ective width 2W , or one of e.ective width 3W and one of 1W .
Sentence 2: using only tracks of 1W (and spacing of 1S), routing perhaps can be more .exible, and di.erent wiring patterns may be advantageous in di.erent scenarios.
Relationship: entailment
Domain: Hardware
Sentence 1: However, the code layout generated for C may perform badly for other con.gurations, though it is good for con.guration C. For example, for benchmark Ispell, 4k-1-way code layout is better than 4k-2-way code layout for 4k-1-way cache con.guration, but worse than 4k-2-way code layout for 4k-2-way cache con.guration.
Sentence 2: there is no single code layout that performs better than other code layouts for all the con.gurations.
Relationship: entailment
Domain: Hardware
Sentence 1: A MAX7000 macrocell uses product terms that can be ORed or XORed together to implement logic functions.
Sentence 2: the APEX E ESB can be configured to implement up to 16-product term macrocells with 2 product terms each at one extreme, or 1 product term macrocell with 32 product terms at the other extreme.
Relationship: entailment
Domain: Hardware
Sentence 1: We .rst develop stochastic, nonstationary models for charge carrier traps in semiconductors, i.e., RTS noise, by bene.ting from the two decades of ion channel noise modeling and simulation work in neurobiology [32] and the extensive literature on modeling and simulation of stochastic chemical kinetics [43], [44].
Sentence 2: we develop (i) a continuous-time, discrete-space, .ne-grained Markov chain model in Section II-B (previously known [8]), and (ii) a continuous-time, continuous-space, coarse-grained Langevin stochas­tic model (completely new) in Section II-C for a charge carrier trap, that are both fully nonstationary capturing the impact of arbitrary time-varying bias conditions.
Relationship: entailment
Domain: Hardware
Sentence 1: 10 shows that, in general, superblock-based code caching helps reduce I-cache misses, except for the threaded variation which suffers more I-cache misses due to the replicated dispatch code.
Sentence 2: improved I-cache locality by superblock caching works to offset increased I­cache pressure from chaining (as is implied by the dy­namic instruction count increase).
Relationship: entailment
Domain: Hardware
Sentence 1: n .. n is monotonic  To this end, we have to extend the basic Boolean operators ¬, ., and .to corresponding operators ¬e, .e, and .eon ..
Sentence 2: the monotonicity is a strong requirement that predetermines most of the extensions: there is only one possi­ble extension ¬efor the negation ¬.
Relationship: entailment
Domain: Hardware
Sentence 1: UVM is for sure a step further from the point view of the universality of the simulation tool, however, it is not for sure a universal approach with respect to the design and veri.cation language.
Sentence 2: the methodology is too language centered, while an ideal universal veri.cation methodology should be language independent: veri.cation is not a matter of syntax, but of semantics.
Relationship: entailment
Domain: Hardware
Sentence 1: One explanation of why pose-speci.c did not outperform pose-independent classi.ers could be the number of train­ing samples, because, for k poses, each pose-speci.c classi­.er was able to use only about 1/k of the training data that the all-pose classi.er had.
Sentence 2: the number of training examples compensates for pose-speci.c difference in walk­ing speed estimation.
Relationship: entailment
Domain: Hardware
Sentence 1: K is selected (Line 4), the kernel matrix F is updated (Line 7) to represent the residual knob settings, so that the next selection would be picked among those under-represented by previously se­lected settings.
Sentence 2: the algorithm tends to select knob settings that cannot be well represented by selected ones, i.e., to favor potentially hard-to-predict knob settings if not being selected as training examples.
Relationship: entailment
Domain: Hardware
Sentence 1: If given full access to the network's resources, these infected users then represent a clear threat to the network in the form of a lurking Trojan horse, a worm, denial-of-service daemon, or a tunnel to an outside attacker or freeloader, Other local devices also make easy targets for further exploitation, and may in turn carry malicious code into other possibly more secure environments.
Sentence 2: people may place their exploited machines on your network and behind your firewall, and by doing so expose your machines to crackers or malicious code.
Relationship: entailment
Domain: Hardware
Sentence 1: Adapting to Intermittent Faults in Multicore Systems PhilipM.Wells KoushikChakraborty GurindarS.Sohi ComputerSciencesDepartment University ofWisconsin,Madison {pwells,kchak, sohi}@cs.wisc.edu Abstract Future multicoreprocessors willbe more susceptibleto a varietyof hardware failures.
Sentence 2: intermittent faults, caused in part bymanufacturing, thermal, and voltage variations, can causebursts of frequent faults that last from several cycles to several seconds or more.
Relationship: entailment
Domain: Hardware
Sentence 1: 2.3 PID Logging Due to the competitive nature of process scheduling in the Linux kernel, the variance in statistical results from one run to the next is greater than one would .nd when running a stand alone application.
Sentence 2: one could potentially see large di.erences in execution time if an infrequent pro­cess, such as a kernel daemon, should be scheduled in one experimental run but not in another.
Relationship: entailment
Domain: Hardware
Sentence 1: Exhaustive Scheduler One way to improve the scheduling decision of an FU for an operation is to consider the effects of the current decision on all future decisions, accounting for all of the interactions between dependent operations, resources, and bypass paths.
Sentence 2: for each possible resource and time assign­ment for a given operation, the scheduler could look at pos­sible resource and time assignments for future operations, taking into account bypass path availability, and choose the assignment that gives the shortest overall schedule length.
Relationship: entailment
Domain: Hardware
Sentence 1: It will take the same amount of time for thedata element to reach the consumer no matter how the different FIFOs are sized as long as the total storage space is same and each FIFO at least has a capacity of 2.
Sentence 2: the time taken by andata element in the queue to reach the consumer de­ pends only upon the total number of storage elements between theelement and the consumer and not on the distribution of the storage el­ements among different stages.
Relationship: entailment
Domain: Hardware
Sentence 1: In the weight function, x1(v, r) is the size of MUXR(r) if v is assigned to r. This item tries to reduce the maximal MUX width.
Sentence 2: x2(v, r) represents the increase of the width of MUXR(r) if v is assigned to r. x2(v, r) = 0 if the functional unit producing v already drove register r before this register binding iteration.
Relationship: entailment
Domain: Hardware
Sentence 1: The above result has later been generalized to Markov­modulated G/GI/1 queues [19], and for short range depen­dent arrival processes [2].
Sentence 2: when the arrival process is stationary and ergodic, but can otherwise be de­pendent, [2] provided a su.cient condition under which (1) still holds.
Relationship: entailment
Domain: Hardware
Sentence 1: (14) Substituting (13) and (14) into (10) yields g-1 g-1 1 1 k k VT H(s) Uk,r Vr T (s-zQ)= Uk,r (s-zQ)r .
Sentence 2: (15) k=0 k=0 we have computed an approximate low­ g-1 rank SVD for H(s)inwhich Ur(s)= .
Relationship: entailment
Domain: Hardware
Sentence 1: p1 p2 p3 a1: Wx1 b1: Rx1 c1: Ry1 b2: Wy1 c2: Rx0 In the absence of barriers, P3:x=0 is permissible.
Sentence 2: p3 is not guaranteed to see the write from P1 and the write from P2 in any particular order (despite the fact that the store from P2 can only happen after P2 has observed the store from P1).
Relationship: entailment
Domain: Hardware
Sentence 1: 4.2 Design Choice for Neural Networks Neural networks of one hidden layer and one output layer are used, because a neural network with two layers of ap­propriate units can approximate everybounded continuous function [4].
Sentence 2: sigmoid units with output range [-1, 1] and linear units are respectively adopted for the hid- Figure 3: The spatialpositions of the road junctions and links used for analysis.
Relationship: entailment
Domain: Hardware
Sentence 1: Mea­sured data [5, 6] from commercial processors such as Intel s StrongARM and Hitachi s SH-3 indicates that as much as 17% on-chip power is consumed in the TLBs with an esca­lating trend.
Sentence 2: in this paper, we analyze the access pattern of mem­ory operations performed within a cycle and in successive cycles, and exploit the characteristics of the addresses for energy reduction opportunities we .nd that concurrent and consecutive memory operations demonstrate very high locality and are often synonymous accessing the same memory page.
Relationship: entailment
Domain: Hardware
Sentence 1: On the other hand, in the execution scenario built by Algorithm 1, (k+1) ti s execution reaches a progression of prog= pnext by being executed for Qi time units, and with a cumulative preemp­tion delay of total delay(k+1) = total delay(k) + delay= max total delay(k).
Sentence 2: algorithm 1 manages to progress slower in ti s execution while suffering from a greater preemption delay.
Relationship: entailment
Domain: Hardware
Sentence 1: Since state changes cause delay and consume energy, h d fewer changes reduce state-transition overhead (and d ).
Sentence 2: task scheduling can save power E h d dh yfP P P h dN5 }hTh 552}T5 h Device { T E8 T dd 2 2Thh 22 8 dd h { T5{ }6 66h d 5 2 {2 } TT T 5 Table 3: hardware parameters.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.7 SUEF Heuristic Note that the greedy scheme discussed in the preceding section attempts to reduce the processing speed for the selected tasks ag­gressively without considering overall energy ef.ciency.
Sentence 2: to evalu­ate the ef.ciency of slack usage for each task, we de.ne the slack usage ef.ciency factor (SUEF) for task Tk running at speed f as: E0 k - Ek(f) SUEFk(f)= (14) sk(f) where Ek 0 and Ek(f)is the energy consumption of task Tk at fmax and f, respectively; and sk(f)is the total amount of slack needed (including the slack reserved for recovery) for task Tk to run at f. it is the ratio of the amount of energy saved to the total amount of slack needed when task Tk runs at a certain speed.
Relationship: entailment
Domain: Hardware
Sentence 1: This method of encryption is used in place of a compression method when preparing the encrypted CBLOCK record, with uncomp-byte-count and comp-byte-count referring to the decrypted and encrypted byte-counts.
Sentence 2: the PSE-CBLOCK format will be: '34' enc-type decrypt-byte-count encrypt-byte­count encrypted-bytes  Since CBLOCKs can be used at the cell level, at the top of a hierarchy, or at the level of individual polygons, encryption can occur at any of these levels as well.
Relationship: entailment
Domain: Hardware
Sentence 1: This on-chip block holds each data block in turn, and when a data block is resident in it, all the 3 nodes (coming from the different nests) are scheduled one after an­other.
Sentence 2: in this particular case, we achieve perfect data block reuse, i.e., even if we have more on-chip blocks, we could not achieve a better performance.
Relationship: entailment
Domain: Hardware
Sentence 1: We also aim our temperature-aware scheme to be able to dynamically adjust the trade-off between the aggressiveness of the power optimization mechanism and resulting temperature reduction at the expense of more storage for buffering the data and orchestrating the buffer-DRAM coordination.
Sentence 2: throughout the execution of an application, power consumption will vary depending on the nature of the application and the workload, resulting in varying power densities and operating temperatures.
Relationship: entailment
Domain: Hardware
Sentence 1: Tables 2-5 compares the number of resulting move instructions on the di.erent out-of-SSA algorithms de­tailed in Table 1.
Sentence 2: we illustrate here com- Experiments Sreedhar pinningCSSA pinningSP pinningABI pinningf out-of-pinned-SSA NaiveABI Coalescing Lf+C2 CTable Sf+C Lf,ABI+C Sf+LABI +CTable 3 LABI +C C Lf,ABI 4 SfTable LABI Table 1.
Relationship: entailment
Domain: Hardware
Sentence 1: Using a list scheduler con.gured for each of our cluster con.gurations, we then build schedules for the trace.2 We use the term schedule here to denote a placement (at a cluster) and a slotting (into an issue slot) of each instruction in the trace.
Sentence 2: our list scheduler performs both steering and in­struction scheduling in a single pass.
Relationship: entailment
Domain: Hardware
Sentence 1: Let us suppose that the k upper order statistics X , X ,K, X belong to the right tail of the distribution n-k +1:n n-k +2:n n:n (we discuss the appropriate selection of their number k in Section II-D).
Sentence 2: let the (n - k) -th order statistic X n-k:n  constitute a high threshold u marking the beginning of the right tail.
Relationship: entailment
Domain: Hardware
Sentence 1: Early Estimation of the Size of VHDL Projects William Fornaciari, Fabio Salice, Daniele Paolo Scarpazza, Politecnico di Milano -DEI Piazza Leonardo da Vinci, 32, Milano, Italy {fornacia, salice, scarpazz}@elet.polimi.it ABSTRACT The analysis of the amount of human resources required to com­plete a project is felt as a critical issue in any company of the elec­tronics industry.
Sentence 2: early estimating the effort involved in a development process is a key requirement for any cost-driven system-level design decision.
Relationship: entailment
Domain: Hardware
Sentence 1: show that these codes have a performance very close to ideal, i.e., the failure probability of the code is such that if N is only slightly more than K, the code can recover the source block with a given probability.
Sentence 2: for K > 200 the small inef.ciency of the Raptor code can quite well be modeled by the following equation, 1 if m < K, Pf (m, K) = 0.85 ×0.567m-K if m =K, whereby Pf (m, K) denotes the failure probability of the code with K source symbols if m symbols have been received.
Relationship: entailment
Domain: Hardware
Sentence 1: More in detail, Figure 5 shows the approximate Pareto curves for the two accelerators, found by using the proposed methodology, compared to the exact Pareto curves 2 .
Sentence 2: figures 5(a) and 5(b) present the results for the 2D-IDCT and YUV2RGBA obtained respectively after 154 and 263 evaluations.
Relationship: entailment
Domain: Hardware
Sentence 1: Acknowledgements We would like to thank a number of people who helped us realize DCA under very trying circumstances.
Sentence 2: we would like to acknowledge the contributions and support from Jeff Gilbert, Jack Doweck, Julius Mandelblat, Suresh Chittor, Siva Radhakrishnan, Don Newell, Ravi Iyer, Luke Chang, Linden Cornett, Scott Tetrick, Ittai Anati and Thom Sawicki.
Relationship: entailment
Domain: Hardware
Sentence 1: By looking at which benchmarks were present in which work­loads, and how these workloads fared in terms of predictions, we were able to determine that some applications are more dif.cult to predict.
Sentence 2: workloads including the COREMARK and VITERBI benchmarks fared badly in these predictions, as did work­loads with a small number of benchmarks.
Relationship: entailment
Domain: Hardware
Sentence 1: However, as aforementioned in Section III-A, the MTJ switching is probabilistic process under thermal .uctuations.
Sentence 2: the STT-RAM write error rate PW F is the probability that the MTJ switching time t is longer than the write pulse width TW , or: PW F = aßP (tth0 > TW ) + (1 - a)(1 - ß)P (tth1 > TW ) (5) Here, a is the probability of a cell storing 1 , ß is the probability that a cell will be written to 0 .
Relationship: entailment
Domain: Hardware
Sentence 1: 5, a validity proof enables a client to determine the validity of the output of the read or incre­ment protocol, and to detect any malicious or erroneous behavior by the VCM in the past.
Sentence 2: for each of the past increments by any of a client s devices, the client can check whether the in­crement was based on a retrieved counter value (received from the virtual counter manager during one of its protocols) that is equal to the current counter value just prior to the increment.
Relationship: entailment
Domain: Hardware
Sentence 1: As the CPL-based de­ 2 sign is a class of static pass-transistor logic, it inherits the design problems that are specific to that circuit class.
Sentence 2: as we have chains of nMOS transistors in the nMOS networks, after a careful study of the situation additional intermediate swing restora­tion may be needed (see the arrows in Figure 8 for their possible placement, after 4-transistor paths).
Relationship: entailment
Domain: Hardware
Sentence 1: Figure 2 (d) and (h) illustrate the third and the fourth classes whose applications require very few SLLC resources.
Sentence 2: milc is a streaming application due to its high miss rate regardless of the amount of allocated SLLC capac­ity, while crafty is CPU-bound and can yield very high hit rates given a small amount of allocated SLLC capacity.
Relationship: entailment
Domain: Hardware
Sentence 1: The handshaking protocol between stages follows similar rules to PS0 (see Sec­tion 2), but with added explicit synchronization to ensure more robust operation.
Sentence 2: a stage in the precharge phase cannot enter precharge-release until its precharge operation is complete (checked by the output CD) and its previous data in­puts have been reset (checked by the input CD).
Relationship: entailment
Domain: Hardware
Sentence 1: Leakage reduction techniques have been widely researched for application processors used in mobile phones, and their standby power is very small (e.g., the leakage current is only 11µA in ultra standby mode [8]).
Sentence 2: the more leakage reduction such processor cores achieve, the more im­pact the leakage power of on-chip routers will give; therefore leakage reduction techniques are essential for on-chip routers as well as processing cores in order to reduce the standby power of the chip.
Relationship: entailment