sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: As a versatile framework that allows different teams or even different companies to work on it together to exchange information, a system-level power estimation system has to be both super-fastand highly accurate on one hand, and be able to create somemiddle models that allow different parties to share powerinformation without revealing too much detail.
Sentence 2: itwill need the integration of bottom-up power modeling capability(for IP providers) and top-down power estimation capability (forESL designer and IP integrators).
Relationship: entailment
Domain: Hardware
Sentence 1: To access the tool .ows of other veri.cation researchers, our tool will have to be able to translate speci.cations into the lower-level speci.cations used by other tools.
Sentence 2: we do not anticipate dif.culties translating from our speci.cations into the speci.cations used in the interface-monitor research that inspired this work [8, 13, 7].
Relationship: entailment
Domain: Hardware
Sentence 1: For com­press, the end-to-end perturbation of HPMs is less than the standard deviation and, therefore, within measurement noise.
Sentence 2: end-to-end perturbations are 0.68% for Cyc, 0.5% for InstCmpl/Cyc, and 0.4% for LsuFlush, which is less than the corresponding standard deviations of 1.47% for Cyc, 0.22% for InstCmpl, and 6.74% for LsuFlush.
Relationship: entailment
Domain: Hardware
Sentence 1: (0) + 1 N is updated in a similar way when the blockinformation of b is evicted from the ghost directory.
Sentence 2: n(i)records the number of memory-blocks where Ltc/gJ-Ltl/gJ= i.N(i) records the approximate number of memory-blocks whose BDs are from gi to g (i +1).
Relationship: entailment
Domain: Hardware
Sentence 1: By circuit simulation it was possible to show that the conductance variation during the filament growth can be controlled by a regulating device, which establishes a negative feedback on the electrochemical reaction rate.
Sentence 2: for three different load types (current source, linear resistor, and source coupled NMOS transistor) the regulating properties in regard to variability reduction (and partly observed in experiments) were shown by Monte Carlo simulation.
Relationship: entailment
Domain: Hardware
Sentence 1: Reduction(%) 1 363.4 305.2 15,7 398.1 328.7 17,4 437.9 378.3 13,6 486.6 398.4 18,1 2 612.7 633.2 -3,3 622.4 659.8 -6,0 1019.5 956.5 6,2 798.8 845.3 -5,8 3 802.4 759.8 5,3 852.1 804.1 5,6 1307.8 1272.2 2,7 1026.5 956.3 6,8 4 490.1 470.1 4,1 499.7 471.1 5,7 893.6 971.8 -8,7 639.8 610.5 4,6 5 672.3 619.2 7,9 663.9 611.4 7,9 1146.0 1112.7 2,9 927.0 841.8 9,2 6 1044.5 1038.2 0,6 1041.6 1014.2 2,6 2147.0 2036.2 5,2 1426.1 1393.9 2,25 7 1071.5 1032.0 3,7 1052.5 995.0 5,5 2169.5 2178.0 -0,4 1458.0 1376.0 5,6 8 1801.8 1821.0 -1,0 1598.4 1642.2 -2,7 4071.0 3784.2 7,0 2328.0 2319.0 0,39  As can be observed in Table 6 and Table 7, with the ordering and the partitioning of the coefficients, significant power reductions can be achievable for some of the filters using all the multipliers.
Sentence 2: the use of the radix4 multiplier of [11] power per samples savings can be achievable for almost all the sequential and semi-parallel filters.
Relationship: entailment
Domain: Hardware
Sentence 1: 1.2 VV VV (, ) I (, ) =I (, ) +I V V (4) For both transistors, the driving currents are completely 0.9 inv in out nmos in out pmos in out characterized by their gate-to-source voltage ( Vgs) and drain-to­ source voltage (Vds ).
Sentence 2: for NMOS, Vgs =Vin and ds out V =V .
Relationship: entailment
Domain: Hardware
Sentence 1: OCN (a) Multiple memory accesses: an example D is blocked at master 1 Memory 1 Memory 2 D A B C C D A B B is blocked at master 2 Master 1 Master 2 Time  (b) Deadlock problem Figure 1 Multiple memory accesses and deadlock problem First, assume that each master uses its own single transaction id.
Sentence 2: the order of memory accesses needs to be maintained at the I/O port of each of the two masters.
Relationship: entailment
Domain: Hardware
Sentence 1: Namely, if the variance of the estimator logPg,q MC is large, logPg,q MC becomes non-critical when determining the optimal values of a, ß and ..
Sentence 2: the MLE framework has already optimally weighted the importance of {logPg,q MC; q = 1, 2, , Q} based on the confidence level of these estimators.
Relationship: entailment
Domain: Hardware
Sentence 1: R+ (12) allows the minimization of aeC Lp e(x) + ßeC Lq e(x).
Sentence 2: for the interesting case of RC-delay minimization [22] with p = 2 and q = 1, (12) yields the sequence F (k)(x) =  1   this method converges [17].
Relationship: entailment
Domain: Hardware
Sentence 1: When multiple con.guration contexts could be recon.gured simultaneously, there is no need to move the loading time of each task forward.
Sentence 2: the loading time of each task ti is set as the starting time minus the recon.guration latency of the corresponding PE F(ti ), i.e., RT(ti )= s(ti )-L(F(ti )).
Relationship: entailment
Domain: Hardware
Sentence 1: 5.1 RTL-to-TLM abstraction The abstraction step presented in Section 3 has been im­plemented in A2T (Automatic Abstraction Tool), a tool built on the top of HIFSuite [13].
Sentence 2: a2T has been extendedto automatically abstractsRTLIPs(imple­mented in VHDL, Verilog or SystemC) towards SystemC TLM models with timing annotation.
Relationship: entailment
Domain: Hardware
Sentence 1: Minimum Implant Area-Aware Gate Sizing and Placement Andrew B. Kahng and Hyein Lee ECE and CSE Departments, University of California at San Diego abk@ucsd.edu, hyeinlee@ucsd.edu ABSTRACT With reduction of minimum feature size, the minimum implant area (MinIA) constraint is emerging as a new challenge for the physical implementation .ow in sub-22nm technology.
Sentence 2: the MinIA constraint induces a new problem formulation wherein gate sizing and Vt -swapping must now be linked closely with detailed placement changes.
Relationship: entailment
Domain: Hardware
Sentence 1: We apply this flow to a simple, out-of-order superscalar microprocessor to evaluate the performance and thermal behavior in 2D and 3D designs, and demonstrate the value of MEVA-3D in providing quantitative evaluation results to guide 3D architecture designs.
Sentence 2: we show that it is feasible to manage thermal challenges with a combination of thermal vias and double-sided heat sinks, and report modest system performance gains in 3D designs for these simple test examples.
Relationship: entailment
Domain: Hardware
Sentence 1: But TDM requires that all routers have a global notion of time, to keep their TDM slots aligned.
Sentence 2: 2.2 Notion of Time TDM (and FDM) (virtual)-circuit switching treat the en­tire NOC as a single shared resource with a single arbiter.packets wait only at the ingress network inter­faces (NI) until their TDM slot, after which they progress without contention to the egress NIs, with minimal latency.
Relationship: entailment
Domain: Hardware
Sentence 1: The BL abstraction is close to the tuple space, in the sense that components do not directly interact (e.g., by invok­ing each other s methods), but via a form of object pool .
Sentence 2: the BL abstraction comes close to recent tu­ple space variants such as JavaSpaces, by delivering objects of interest through a call-back, and through the possibil­ity of limiting the time during which objects are available to others.
Relationship: entailment
Domain: Hardware
Sentence 1: We notably de.ne the notion of cell capacity , critical for dimensioning purposes, and show that: sharing the transmission power in a fair way is e.cient with respect to user performance;  the waste of radio resources due to the granularity of feasible rates induced by coding constraints is typically not signi.cant;  the so-called cell breathing e.ect arises at very high loads only.
Sentence 2: a simple admission control independent of user locations is su.cient in practice;  the number of active users is typically rather small in steady state.
Relationship: entailment
Domain: Hardware
Sentence 1: This can be formalized as bipartization (making 2-colorable, or equivalently, ensuring no odd cycles ) of a shifter graph with nodes corresponding to shifters and edges corresponding to (i) pairs of shifters which define critical features and (ii) pairs of overlapping shifters.
Sentence 2: determining whether a given layout can be phase-shifted requires a global analysis of a phase conflict graph defined over the layout to determine whether this graph is bipartite [8, 9].
Relationship: entailment
Domain: Hardware
Sentence 1: To exploit inherent FPGA recon.gurability while avoiding full CAD mapping, we propose lightweight tech­niques compatible with the current single bitstream model that can avoid defective devices, reducing yield loss at high defect rates.
Sentence 2: by embedding testing operations and alternative path con.gurations into the bitstream, each FPGA can avoid defects by making only simple, greedy de­cisions at bitstream load time.
Relationship: entailment
Domain: Hardware
Sentence 1: The consideration of sce­nario C is one of the pillars of PAMPA s robustness, be­cause frequency is reduced and cores are folded only if all the turned-on cores have low utilization.
Sentence 2: pAMPA prevents frequency reduction and core folding even if just one physical thread in the processor presents high uti­lization to avoid severe performance degradation.
Relationship: entailment
Domain: Hardware
Sentence 1: Zero copy gathers data from non-contiguous memory regions and incurs an average of 7% performance degra­dation when compared with chunking+ remapping; however, all of our applications still get an average speedup of 16.2% on the over­all performance due to improved GPU kernel execution time.
Sentence 2: our proposed remapping approach has an advantage despite the extra copy step because the GPU, working from GPU memory, can achieve higher throughput on data layout transforma­tion than attempting to perform transformation as part of the PCI-E transfer.
Relationship: entailment
Domain: Hardware
Sentence 1: First-order approximations are proposed to help us quantitatively determine:  (a) the most energy-ef.cient capacity and bandwidth of the levels in the cache hierarchy, (b) the optimal number of cache levels, (c) potential performance bene.ts of multiple levels of memory as­suming a .xed power budget.
Sentence 2: given a power budget, our model and theories suggest the best memory hierarchy (in terms of capacity and bandwidth provided).
Relationship: entailment
Domain: Hardware
Sentence 1: As can be clearly seen from the .gure, ForTER is able to achieve much higher TPP than both Original and BER.
Sentence 2: forTER achieves more than 20% improvement over BER for s38417.It is worth noting that, in most cases, ForTER with 10% constraint outper­forms the case with 5% constraint in terms of TPP.
Relationship: entailment
Domain: Hardware
Sentence 1: For example, imagine that enough keys are inserted that all bits in v have been set; in this case, every search will be successful whether or not the key was actually inserted.
Sentence 2: the false positive rate is a clear consequence of the design parameters chosen, namely, n, m, and k. the probability of a false positive, or the false positive rate, is Thus 5 bits per counter is amply sufficient.
Relationship: entailment
Domain: Hardware
Sentence 1: However, this dif.culty does not pose any problems in practice since these cases can be easily iden­ti.ed and solved by inspection.
Sentence 2: if the noise margin for any pin on a net is approximately equal to its minimum feasible CPU time (sec) 90 80 70 60 50 40 30 20 10 0 Number of spacing variables Figure 6: CPU time to compute optimal spacing based on MERT estimate for randomly selected noise margins (lower cloud ), and for worst case performance (upper curve).
Relationship: entailment
Domain: Hardware
Sentence 1: Since windowing is guaranteed to produce a DC lower bound and simulation produces a DC upper bound, the difference (scaled to total number of configuration bits in the circuit) can be used to evaluate the quality of the solution.
Sentence 2: the quality of the solution can be evaluated using the following equation: I-DCsim--I-DCwin- Gap = (1) Iz-inputs- For a LUT node with -inputs-inputs, -DCwin- (-DCsim-) is the size of the DC set computed by the windowing formulation (Monte Carlo simulation), L is a summation over all the nodes in the circuit, and z-inputs- is the number of configuration bits of the node and also the maximum possible size of the DC.
Relationship: entailment
Domain: Hardware
Sentence 1: Conditional criticality of an edge e is expressed as follows: p(e ~ crit&#38; T fails) p(e ~ crit | T fails)= (12) p(T fails) where p(e ~ crit| T fails) is the conditional probability that the edge e is critical conditional upon the timing con­straints being violated; p(e ~ crit &#38; T fails) is the proba­bility that the edge e is critical and the timing constraints are violated; p(T fails) is the probability that the timing constraints are violated.
Sentence 2: conditional criti­cality is the probability of being critical computed for the sample space consisting of only those chips violating timing constraints.
Relationship: entailment
Domain: Hardware
Sentence 1: As can be seen, our method has autonomously discovered that fuel inst (instantaneous fuel consumption) can be approxi­mated using cac in p (charge air cooler input pressure) and in manif t (input manifold temperature).
Sentence 2: there exists a relation fuel inst = p1 *cac in p+p2 *in manif t The actual values of p1 and p2 parameters, of course, de­pend on the exact values of the signals in question, but as can be seen in .gures 3 and 4, they show an interesting regular­ities.
Relationship: entailment
Domain: Hardware
Sentence 1: The table demonstrate that the newly proposed technique for designing totally self-checking SSCs based on the reduced m-out­of-n coding results in a hardware overhead of about 30%, while the Berger coding implementations require an overhead of about 50% and the Smith coding about 40%.
Sentence 2: the authors approach leads to a reduction of about 10-20% of the overhead as compared with the traditional methods.
Relationship: entailment
Domain: Hardware
Sentence 1: Since Griggs and Yeh intractability proof for L(2, 1)- coloring can be easily extended also to the L(2, 1,1)-coloring problem, optimal solutions for special networks are consid- ered.
Sentence 2: solutions to the L(2, 1)-coloring and L(2, I, 1)-coloring problems are provided for hexagonal, bidi- mensional and cellular grids.
Relationship: entailment
Domain: Hardware
Sentence 1: I will discuss why this view is the best we can do with current popular languages, and why it is inadequate moving forward, requiring rethinking popular parallel languages and hardware.
Sentence 2: i will argue that (1) parallel languages should not only promote high-level disciplined models, but they should also enforce the discipline, and (2) for scalable and efficient performance, hardware should be co-designed to take advantage of and support such disciplined models.
Relationship: entailment
Domain: Hardware
Sentence 1: For the computational Grid, we chose an implementation of mpi named mpich-g2 which is a Grid-enabled implementation of the mpi v1.1 standard.
Sentence 2: using services from the Globus Toolkit (e.g., job startup and security), mpich-g2 al­lows one to couple multiple machines, potentially of di.erent architectures, to run mpi applications.
Relationship: entailment
Domain: Hardware
Sentence 1: Here, a and ß are the parameters of the Weibull distribution.
Sentence 2: a common representation of a Weibull distribution is on the so-called Weibull scale, under the transform W = ln(- ln(1 - Pr)) = ß ln(.it/a) + ln(ai) (7) 1.2 if we plot W as a function of ln(t), the result is a 0 (m) 15 30 (m) 45 straight line with slope ß and intercept ln(ai).
Relationship: entailment
Domain: Hardware
Sentence 1: Analysis Framework: We leverage recent advances in anal­ysis and optimization to construct a coherent framework for adaptive microarchitectures based on random spatial sampling, spline-based regression for prediction, and genetic algorithms for optimization (Section2).We apply this frameworkto assess the bips3/w ef.ciencyfrom high temporal and comprehensive spatial adaptivity.
Sentence 2: we optimize 1,125 adaptive in­tervals each with 80,000 instructions over an adaptive space of 240B con.gurations de.nedbycombinationsof15 parameters.
Relationship: entailment
Domain: Hardware
Sentence 1: Furthermore, the total number of si-variables allowed to be assigned to 1 is lim­ited to k. The problem of .nding a set of gates that can be corrected is translated to an instance of the Boolean satis.­ability(SAT) problem: If there is a valid assignment to all signals for a given k, then each gate whose corresponding  P to a missing control error, since adding control lines would not lead to a di.erent output on line 4. i=1 t .T These examples motivate further investigation of the de­ bugging problem for missing control errors.
Sentence 2: the last observation can be exploited for a new debugging vt ' v t S(t) approach.
Relationship: entailment
Domain: Hardware
Sentence 1: In order to recover after losing track of the tasklist, the coprocessor restarts the search from the init process whenever it encounters an invalid physical memory pointer.
Sentence 2: the coprocessor knows it is lost when any physical memory address it needs to process next is outside of the range of physical memory addresses available in the system or when certain members of the task structures contain values that are not normally possible (e.g., negative PID).
Relationship: entailment
Domain: Hardware
Sentence 1: 4.1.1 Self-term Volume Integration  For the separate case where r.V.V, a simple approximation scheme is used.
Sentence 2: .- jk|r-r ' | .edv ' = .e- jk|r-ric| 1 dr ' , (20) V |r - r ' | Vi |r - r ' | i where the source .lament is divided into sub-.laments, and ric is the center of the ith sub-.lament.
Relationship: entailment
Domain: Hardware
Sentence 1: Incaseofhavingfaultylines,accessesthatwouldhave experienced a hit in a fault-free cache or a fault-free VC may observe a signi.cant increase in their latency.
Sentence 2: those accesses should have had the WCET indicated in equation 1 or equation 2 but, instead, they have the WCET indicated in equation 3 as we cannot determine whether their data will be available in L1 or theVCduetothefaulty cache lines.
Relationship: entailment
Domain: Hardware
Sentence 1: : then d1 + dB = d2 + dC  Using the technique proposed in [12], ful.lling each of the above constraints will falsify the other constraint.
Sentence 2: adding extra gates on one of the branches to guaran­tee correctness of circuit operation for one of the transitions on X makes it impossible to ful.ll another timing constraint on the opposite transition.
Relationship: entailment
Domain: Hardware
Sentence 1: Beside the general design issues of OD3P, note that: 1) since the number of lines in a page is limited and it is prac­tical to check FreeECPs at low complexity, no TPS mech­anism is required at line-level OD3P, and 2) line-level and page-level OD3P mechanisms should not be applied to one page at the same time.
Sentence 2: if lines of a page are paired, the pairing algorithm should not select it as a tar­get at page-level.
Relationship: entailment
Domain: Hardware
Sentence 1: Inspired by this promising result that motivates a grid-based analog circuit optimizer, this paper explores the use of discrete optimization techniques for variability-aware analog circuit synthesis.
Sentence 2: the paper addresses three main challenges: an efficient grid scheme to discretize a continuous design space, a search algorithm to find the optimal design point on the discretized grid, and a way to reduce the computational burden of comparing the statistical measures among the multiple candidate points.
Relationship: entailment
Domain: Hardware
Sentence 1: The slope of EHypnos and ECLP M with respect to T1 is a testa­ ment to the dominating e.ect that idle time power consump­tion places on the overall energy cost.
Sentence 2: this also signi.es that the energy cost due to the higher latency overhead for Hypnos gets amortized in heavily duty cycled systems.
Relationship: entailment
Domain: Hardware
Sentence 1: For the emerging three­dimensional integrated circuits (3D ICs), the introduction of through-silicon vias (TSVs) as the vertical signal carrier complicates the electromigration analysis.
Sentence 2: an accurate EM analysis on TSV arrays that are used in the power supply network is critical since the large current go­ing through those TSVs can accelerate their degradation.
Relationship: entailment
Domain: Hardware
Sentence 1: During recent and ongoing work, the IMPACT compiler is enhanced with a strong synergistic portfolio of different analysis techniques that can help expose the coarse-grain parallelism [21] inherent in many of the popular applications used in embedded systems 9D-2 today.
Sentence 2: a combination of different analysis techniques focusing on 1) pointers, 2) arrays and structures and 3) variable constraints and relationships, are effectively applied to discover different forms of coarse-grain parallelism.
Relationship: entailment
Domain: Hardware
Sentence 1: 5.1.1 Delay The delay of a transmission gate is e.ectively determined by the time to charge or discharge a load capacitance CL at its output through the equivalent resistance Req of the two transistors connected in parallel.
Sentence 2: vout (t) = (1 - e -t/ReqCL )VDD , so that propagation delay (Vout (tp) = VDD /2) is given by [7]: tp = ln(2)ReqCL = ln(2) 2VDD (1) kn(VDD -VT n )2+kp(VDD -|VT p |)2 CL.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper we propose a new BIST-based on-line testing method, High-DiagnosabilityBIST (HD-BIST), for testing the PLBs of the FPGA that has much higher diagnosability, for random as well as clustered faults, than previous on-line [1, 2, 3, 7, 8] as well as o.-line [4, 5, 6] testing methods1 .
Sentence 2: our method out­performs the two previous best on-line BIST methods [1, 2], both in terms of fault coverage and fault latency.
Relationship: entailment
Domain: Hardware
Sentence 1: For example, 16-bit narrow-width value has its meaningful bit portion in 16 bits of LSB side and the remaining 48 bits (MSB side) of data are all 0 s. The main benefit by exploiting the narrow-width value is that it makes storage utilization more efficient.
Sentence 2: with same storage capacity, we can store more data by exploiting the narrow-width value feature.
Relationship: entailment
Domain: Hardware
Sentence 1: As we have discussed, instead of placing strict con­straint on the maximum temperature Tm, we investigate the possibility of increasing the temperature and allow the temperature to violate this constraint for a while, as long as this period is within some bound.
Sentence 2: starting from the steady state Tm,for some period tf ,say severalmin­utes, we allow the temperature to increase above Tm,as long as at the end of tf , the temperature goes back to the steady state Tm.
Relationship: entailment
Domain: Hardware
Sentence 1: Comparing to the results of Table 3, the ratio of saving is smaller, since not only is the operational temperature range determined by the on-line algorithm but also the energy of the greedy approach is calculated for the same time that on­line algorithm .nishes the task (not a complete cool down).
Sentence 2: when the processor is assigned a slightly longer time period (than Tw) to execute a task, it can use thermal management technique to reduce the leakage en­ergy.
Relationship: entailment
Domain: Hardware
Sentence 1: IN T RO D U C T I O N Higher semiconductor technology integration due to geometry scaling opens the door to new market segments.
Sentence 2: technology evolution enables adding some degree of intelligence to any control or measuring engine such as biomedical sensor applications to monitor the body, environment sensor applica­tions to monitor wind, temperature, tsunamis, etc., by means of battery-powered ultra-low-cost (e.g., below 1 C) computing devices.
Relationship: entailment