sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: These rout­ings are computed using the LP models developed in Section 5.3.  nm-gravity-opt: When thebaseTM D is Bimodal, we also consider an optimal routing for Gravity TMs (the reverse would not work, as routing for bimodal TMs are de.ned only on subset of OD pairs).
Sentence 2: a routing f such that optU(DG)= perf(f, {DG}) (where DG is the gravity TM).
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper we describe a new scheduler that converts a rich set of scheduling constraints into a system of difference constraints (SDC) and performs a variety of powerful optimizations under a uni.ed mathematical programming framework.
Sentence 2: we show that our SDC-based scheduling algorithm can ef.ciently support resource constraints, frequency constraints, latency con­straints, and relative timing constraints, and effectively optimize longest path latency, expected overall latency, and the slack dis­tribution.
Relationship: entailment
Domain: Hardware
Sentence 1: Then, clustered objects are processed and placed together for most part of placement .ow and start to be dissolved slowly at late stage of the .ow.
Sentence 2: during the early stage of the placement algorithm, a global optimization process is performed on highly clustered netlist while only local optimization/re.nement is executed on the almost .at­tened netlist at later stage.
Relationship: entailment
Domain: Hardware
Sentence 1: Given such an application that requires t memory ar­rays and a FPGA architecture with a maximum of N(= t) on-chip embedded memory arrays and k-LUTs, .nd a map­ping such that the number of k-LUTs used is minimized.
Sentence 2: the utilization of the n (= (N - t)) avail­able on-chip embedded memory for implementing the com­binational elements of the circuit is maximized.
Relationship: entailment
Domain: Hardware
Sentence 1: The constraint is then formulated as a penalty function that is added to the ob jective function for the placer.
Sentence 2: cells with region constraints contribute a penalty mi to the placement objective as given by: mi(xi,yi)= m(xi,xli ,xhi )+ m(yi,yli ,yhi ), (1) where function m(xi,xli ,xhi ) (similarly, m(yi,yli ,yhi )) is de.ned as: 8 >  xhi (2) > : 0, xli = xi = xhi cells placed outside their constrained regions will increase the objective function by a quadratic term that is proportional to the distance between cells and its desired region boundaries.
Relationship: entailment
Domain: Hardware
Sentence 1: Mathematically, this problem can be formulated as the following optimization problem: Z µv+3sv `´2 T=arg min h(v, T) - max(v, 0)dv (4) E[h(V,T)]=µm µv-3sv where µv and sv 2 are the mean and variance of the random variable V , respectively; while µm and E[h(V, T)] are the exact and approximated mean of max(V, 0), respectively.
Sentence 2: 2 2 µm = E[max(V, 0)],E[h(V, T)] = .2(s+ µ)+ .1µv + .0.
Relationship: entailment
Domain: Hardware
Sentence 1: Introduction to Special Issue: Novel Paradigms in System-Level Design This special issue of the ACM Transactions on Design Automation of Electronic Systems contains a comprehensive review of emerging directions and disci­plines in system-level design in the context of newly emerging design plat­forms for embedded applications.
Sentence 2: the focus of the four papers included here is centered on the ideas of communication , platform-based de­sign , schedulability analysis , and architecture exploration as foundations of ef.cient design for complex (possibly recon.gurable or distributed real-time) systems of the future.
Relationship: entailment
Domain: Hardware
Sentence 1: Interestingly, our proposed hybrid method represents a new Pareto solution which is signi.cantly faster than the statistical method and offers a higher estimation accuracy than the analytical method.
Sentence 2: our results show that the hybrid method pre­sented in this paper is able to reduce signi.cantly the maxi­mum estimation error of the analytical approach, up to a factor 4.
Relationship: entailment
Domain: Hardware
Sentence 1: Table 2: Results for VIS benchmarks Circuit Name Verilog Lines Property/Result ITC99-b01 91 controller property passed ITC99-b12 494 controller property failed as specified in the benchmark ITC99-b13 274 Absence of reset, passed In the ITC99-b12 UCLID generated a false negative due to the absence of integer semantics in the concatenation UFs.
Sentence 2: it determined that {1 b1,1 b1,1 b1,1 b1} " .
Relationship: entailment
Domain: Hardware
Sentence 1: A nonmeasurable state is thus a state that provably can not reach the goal states on the concrete system.
Sentence 2: the state depths in a given trace segment on the concrete system can only vary in a very simple way: If state n has measurable depth k+ 1, then if state n+ 1 is measurable, its depth is lower bounded by k. a legal transi­tion in the concrete system that starts in a measurable state may either correspond to a one shell progression towards the goal, or it may correspond to one or more steps backwards.
Relationship: entailment
Domain: Hardware
Sentence 1: Formally, a lower bound for the L(1, 1 .... ,1)-coloring problem is also a lower bound for the L(61,1,..., 1)-coloring problem, with 61 _> 1.
Sentence 2: lower bounds for L(1, 1) and L(1, 1, 1) hold also for L(2, 1) and L(2, 1, 1).
Relationship: entailment
Domain: Hardware
Sentence 1: 3.2 Test Point Structure Design To measure the delay for one of the parallel paths, we insert a test point .ip-.op (D-type) at each reconvergence point.
Sentence 2: we feed the data input of the D .ip-.op with the output of the last gate on the path which enables us to measure the path delay by using clocking and standard scan chain delay-fault testing methods.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION Cathodic protection (CP) is the most effective electrical method of controlling and reducing corrosion on metallic structures such as water storage tanks, lock gates and dams, steel pilings, ship hulls and interiors, and water treatment equipment, located underground or underwater.
Sentence 2: the CP method has been widely used on the metal pipeline systems for the transmission and distribution of gas, petrochemical, and water [9, 10, 12].
Relationship: entailment
Domain: Hardware
Sentence 1: This work evaluates many alternative policies for the creation of fragments within the Strata SDT framework.
Sentence 2: we examine the effects of ending translation at conditional branches; ending translation at unconditional branches; whether to use partial inlining for call instructions; whether to build the target of calls immediately or lazily; whether to align branch targets; and how to place code to transition back to the dynamic translator.
Relationship: entailment
Domain: Hardware
Sentence 1: We make use of slightly larger SVW struc­tures than used in the SQIP study [21] because we use the reference input sets for SPEC which results in larger mem­ory footprints for several benchmarks.
Sentence 2: we use a 4K-entry SSBF with 16-bit SSNs (8KB state total) with a similarly con.gured 4K-entry SPCT using 8-bit partial store PCs (4KB).
Relationship: entailment
Domain: Hardware
Sentence 1: EXPERIMENTAL RESULTS The target MP SoC platform described in Figure 1 has been con.gured with a set of .xed parameters and a set of variable parameters to explore, such as the number of threads per processor, interconnect and memory latency, NOC topology, etc..
Sentence 2: the simulated target ar­chitecture includes the parameterizable PIRATE NOC-IP interconnecting the following 12 nodes: Four ARM v7 processor cores con.gured with 4 pipe­line stages and a variable number of threads per pro­cessor;  The con.gurable memory sub-system composed of 3 nodes: Global SRAM, Stacked Memory, Packet Mem­ory;  The Concurrency Engine to support both thread and processor level parallelism;   The Packet Engine to support packet I/O;  The Horba (Hardware Object Request Broker) Engine to coordinate objects communication;  The Client Ware Master;  DSOC (Distributed System Object Component) En­gine.
Relationship: entailment
Domain: Hardware
Sentence 1: we put more weight on the switching statistics on these memory blocks.
Sentence 2: for example, assume B1, Bm+1 and B2m+1 share the same permutation and we know B1 will always be loaded to the cache, then the permutation will bias to B1.the permutation is suited better for B1.Miss rate and execution frequency statistics of the memory block are obtained by analyzing the dynamic trace during the benchmarking of the program.
Relationship: entailment
Domain: Hardware
Sentence 1: Instructions from both states then move to I D. Instructions which move from I D have a transition time of 1 cycle and instructions which originate from I D&#38;ROBF ull have minimum transition time of 3 and maximum transition time of 113.
Sentence 2: a full ROB takes minimum 3 cycles and max­imum 113 cycles to make itself available again.
Relationship: entailment
Domain: Hardware
Sentence 1: One the other hand, a more sophisticated model was required for the OneNAND® which is an active device, but we could easily find an already-existing in­house model for such a widely used component.9 We took a practical approach to create a model of host device.
Sentence 2: the host model plays the role of input-pattern generator; it reads a script file and, in timely manner, generates a stream of ATA commands to the virtual host-interface model.
Relationship: entailment
Domain: Hardware
Sentence 1: Therefore, the problem attacked in this paper is to re­duce power consumption while keeping the amount of repli­cation under control.
Sentence 2: given a .xed amount of extra memory we can use for replicating read-only data blocks, our approach makes best use of that space for re­ducing the power consumption of the banked memory by exploiting the available low-power modes.
Relationship: entailment
Domain: Hardware
Sentence 1: Besides, our approach is always able to generate a DVI solution in which the number of inserted redundant vias is the same or larger (i.e., #RVI is the same or larger), as compared to the commercial tool and MIS-DVI.
Sentence 2: for each test case, our approach always generated an optimal solution, but the commercial tool and MIS-DVI did not.
Relationship: entailment
Domain: Hardware
Sentence 1: Past studies have observed that the overall cache miss rate (measured in terms of misses per access, or MPA) is a simple function of the sum of the miss rates of the contributing threads [15, 18].
Sentence 2: for N threads, where M P Ai(pi) is the the miss rate of of thread i with cache allocation pi: N X 1 OverallM issRate = M P Ai(pi) (2) N i=1 Combining this observation with miss rate data for each application of interest on a range of cache sizes, a simple search algorithm can statically determine the optimal cache allocation p1, p2, ...pN for applications 1 - N that minimizes the total misses incurred.
Relationship: entailment
Domain: Hardware
Sentence 1: MOTIVATION A characterization of the interconnections in ULSI circuit designs is needed because the contributions of the on-chip interconnections to the size of the capacitive loading on the global clock are not well defined during the majority of the duration of the chip design project.
Sentence 2: well­understood values of the load in these designs are not typically available until as late as near the time of tape-out.
Relationship: entailment
Domain: Hardware
Sentence 1: Since k2 = a +1 and l2 = b - 1, the BRV be­tween them can be calculated as fr = If2-If1 = (a+1 b-1)T -(ab)T = (1 - 1)T .
Sentence 2: the data block has a reuse distance of (1 - 1)T .
Relationship: entailment
Domain: Hardware
Sentence 1: CONCLUSIONS We have presented the novel aspects of the MDGRAPE-4 NoC which we hope will .nd broader use in future NoCs.
Sentence 2: the quadrature capacitive signalling and quadra­ture sense-amp architectures should enable reductions in power consumption, area and delay for a broad range of NoCs in current and future nanometer CMOS technologies.
Relationship: entailment
Domain: Hardware
Sentence 1: Since it is inefficient to have only one clock tree for all different power modes, in this paper, we propose to use an adjustable feature of ADBs to assign different values of ADBs for different voltage modes.
Sentence 2: given a power mode such as mode Active1 in Figure 1, we first insert ADBs into the clock tree and then assign certain values of ADBs to minimize the clock skew for this particular power mode.
Relationship: entailment
Domain: Hardware
Sentence 1: Because we needed a large number of experiments, we focused on two small units from these designs, but as often arises in practice, we examined the integration of two separate de­signs.
Sentence 2: the DUV is the USB Packet Disassembly Unit (usbf pd) from the USB Function Core integrated with the USB Re­ceive Unit (rx phy) from the USB PHY.
Relationship: entailment
Domain: Hardware
Sentence 1: This is consistent with the results reported in [8] and af.rms that the hardware Trojans do not violate the circuit speci.cations.
Sentence 2: a transmission of a Trojan-infested circuit with the Trojan activated appears to be perfectly legitimate and within the margins allowed for process variations and operational conditions .uctuation, hence the Trojans evade detection.
Relationship: entailment
Domain: Hardware
Sentence 1: However, if the number of configu­rations is greater than the size of the LFSR, some extra gates will be needed in order to actually connect each configuration control line Di to a tristate gate that is used in more than one configurations.
Sentence 2: for controlling a tristate gate in multi­ple configurations, an extra gate, which receives as inputs the respective configurations control lines, is required.
Relationship: entailment
Domain: Hardware
Sentence 1: If the OS is informed of the degradation status of each core, it can make better decisions on job-to-core mapping and increase overall processor lifetime.
Sentence 2: we evaluate three task mapping schemes to study the implications of process variations: lifetime minimization (LTMin), which results in the worst-case power and lifetime for a given workload; random, which is the expected case with conventional mapping; and lifetime maximization (LTMax), which uses a greedy approach that tries to maximize overall lifetime.
Relationship: entailment
Domain: Hardware
Sentence 1: That is, the rise and fall edge responses must have the property that vR(t)= vhigh and vF (t)= vlow for all t> (D + NT ).
Sentence 2: that vR and vF have known values for large time leads to an explicit formula for conditional PDF of VtN .fV N |BN (v|0) = d(v - vlow ) t fV N (v|1) = d(v - vhigh) (8) t |BN where again d is the usual impulse function.
Relationship: entailment
Domain: Hardware
Sentence 1: In this session, we will show from Raphael RI3 inductance extraction results that if a signal wire is guarded by two ground wires of at least equal width either on left and right in the same layer or on the layers above and below with or without local ground plane(s), then this kind of multi-conductor systems may be lin­early cascaded to determine the total effective loop inductance.
Sentence 2: the total loop inductance is the serial or parallel combination of the loop induc­tances of the cascaded segments determined individu­ally.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we propose a new technique, referred to as Bayesian Virtual Probe (BVP), to efficiently measure, characterize and monitor spatial variations posed by manufacturing uncertainties.
Sentence 2: the proposed BVP method borrows the idea of Bayesian inference and information theory from statistics to determine an optimal set of sampling locations where test structures should be deployed and measured to monitor spatial variations with maximum accuracy.
Relationship: entailment
Domain: Hardware
Sentence 1: Combined Place and Route While the previous results demonstrate that trade-offs exist among different placement algorithms and routing algorithms, they do not address the critical question of deciding which set of algorithms should be chosen for a specified trade-off.
Sentence 2: given that the user is willing to trade-off some quality for an improved run­time, should a faster placement algorithm and a slower route algorithm be chosen, or a slower placement algorithm and a faster route algorithm?
Relationship: entailment
Domain: Hardware
Sentence 1: EVALUATION We evaluate the impact of rank subsetting on memory power,processorperformance, andsystem energy-delayprod­uct using the con.gurations described in the previous sec­tion.
Sentence 2: we focus on understanding the inter­play between subsetting DRAM ranks and utilizing DRAM power-down modes as the capacity and the reliability level of the memory systems are varied, which was not studied before.
Relationship: entailment
Domain: Hardware
Sentence 1: When the binary digits {xQn; n = 1,2, ,N} are stored in an SRAM, the stored value {yQn; n = 1,2, ,N} can be different from {xQn; n = 1,2, ,N}, since each bit cell can possibly fail.
Sentence 2: the stored value: N Q nQ y =L2- y (5) n n=1 can be different from the actual quantized value xQ.
Relationship: entailment
Domain: Hardware
Sentence 1: Prior work on memory dependence prediction has already shown that there are stable patterns between loads and the store in­structions they receive their values from [5, 15, 25].
Sentence 2: a static load that is dependent on an earlier store is usu­ally dependent on the same static store for each dynamic instance of that load, and furthermore the relative position of the store will also be the same.
Relationship: entailment
Domain: Hardware
Sentence 1: News media may also serve as a source of information, but this information needs to be considered in the context of the type of work performed by these media outlets.
Sentence 2: since the focus of reporters is going to be necessarily be on the most heavily damaged areas, relying on such information without considering a proper context may lead to the erroneous impression that a hugely vast area was completely obliterated by the disasters when almost always the reality is that intense damage is usually observed in very bounded and relatively small areas.
Relationship: entailment
Domain: Hardware
Sentence 1: WithCOGS, we conduct an empirical characterizationof en­try guards fueledby real data onTor routers capturedby the Tor Metrics Portal.
Sentence 2: we analyze natural churn, entry guard rotation, the number of entry guards chosen, and other parameters in terms of their effects on security and per­formance through large-scale simulation ofTor s current en­try guard selection and rotation algorithms.
Relationship: entailment
Domain: Hardware
Sentence 1: Here we note that, as for the hold timing constraint, each edge ((da,dq), (da,on)) depends on the the binding solution, and is not .xed before binding.
Sentence 2: we can only say that if dq is bound to the same register with dp , then (da,dq)is needed, and if on is bound to the same FU with oa , then (da,on) is needed.
Relationship: entailment
Domain: Hardware
Sentence 1: New energies of states of molecular orbitals Enew are obtained by adding the self­consistent .eld energy USC F and the contribution of the gate potential to molecular orbital shift eVge f f .
Sentence 2: in our model when the electrostatic potential is applied to the gate electrode, only a part of this electrostatic potential would e.ect the molecular energies.
Relationship: entailment
Domain: Hardware
Sentence 1: We assume that all the intra-tile wires regardless of dimensions, are latency-optimized.
Sentence 2: compared to inter-tile wires,  8 AF = 1% AF = 0.1% 10 100 100 0 5 10 15 20 10 relative power 6 10 90 90 80 80 4 70 10 70 number of wires relative power 60 60 2 50 50 10 40 40 30 0 30 10 20 20 0 1 2 3 4 5 101010101010 wire length (gate pitch) 10 10 00 Figure 3: Wire distribution of our base chip.
Relationship: entailment
Domain: Hardware
Sentence 1: PROBLEM DEFINITION Given a set of Boolean functions representing an arith­metic component, our goal is to enumerate all possible fac­torizations which expose CSEs common to more than one of the functions in the set.
Sentence 2: we look for all those which (1) are Pareto-optimal that is, circuits that are bet­ter in area and/or in critical-path delay than any other and which (2) are not equivalent for logic synthesis.
Relationship: entailment
Domain: Hardware
Sentence 1: The reason is that most of the error bits caused by program disturbs could be led into another reliable block whose sibling reliable block is currently free when .ash space is not fully­utilized.
Sentence 2: the percentage of disturb errors on invalid data decreases as the .ash space utilization increases, but this agrees with the aforementioned observation that high space utilization of .ash memory would reduce the probability on allocating free reliable blocks from free or semi-free physical block.
Relationship: entailment
Domain: Hardware
Sentence 1: Our methodology aims at minimizing the total number of component synthesis to achieve a rich set of target system implementations.
Sentence 2: we propose: 978-3-9810801-8-6/DATE12/ c.2012 EDAA · a concise component-library format, which preserves the freedom of system designers to select a wide range of component implementation alternatives to .t the speci.c design context of a system; · an algorithm that, for a given system design context, prunes the design space of a component to minimize the set of its implementation candidates for integration into the system.
Relationship: entailment
Domain: Hardware
Sentence 1: Moreover, because all signals belonging to thesameI/O interfacewillbevery likelyrouted tothe same I/O interface in other chips on the PCB, it is desir­able to have the I/O cells belonging to the same interface physically close toeachother (oreveninapreferredorder), which reduces the delay and SI variations between signals of the same interface.
Sentence 2: di.erential signal pairs are usually required to escape and to be routed together on the package.
Relationship: entailment
Domain: Hardware
Sentence 1: However, when we are working with an SPM where the different lines have different latencies (i.e., without assuming the worst-case latency for all lines uni­formly), the execution can easily lead to faults if we read data from a line which has high latency and assume that it has a low latency.
Sentence 2: dropping the worst-case based design option requires us to carefully manage the data SPM performance as much as possible without causing any access timing failures.
Relationship: entailment
Domain: Hardware
Sentence 1: Weobservethatlargerthecacheblockis, shorterthelength of thedormantperiodis.
Sentence 2: sincelargerblocks store moredata,thelength of theperiod between their two consecutive accesses is smaller, leading to lessfrequentinvalidations; and as a result,theimprovement in APEC through invalidation becomes less.
Relationship: entailment
Domain: Hardware
Sentence 1: Although it is clear that it is not possible to obtain arbitrarily low values of area and negative slack (the Gaussian distributions are truncated), better results with respect to the original .le can be obtained by running sev­eral synthesis .ows on transformed input .les.
Sentence 2: we note that the best performance area-wise and slack-wise shown in Table 2 were not obtained with the same design: the samples create a Pareto-curve from which designers can select the trade-o.
Relationship: entailment
Domain: Hardware
Sentence 1: The proposed method generates test functions for each transition fault under any activation/propagation sensitiza­tion criterion and at the same time allows the event to propa­gate along any path in a subcircuit whose paths have exactly the same delay.
Sentence 2: using a dynamic programming algorithm, k subcircuits are de.ned: The .rst contains all longest paths, the second all second longest paths, and so on.
Relationship: entailment