sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Usually, optimizers use the above cost metric to choose between multiple query plan options before issuing a query.
Sentence 2: when a cost is attached to each page (block) read/write operation, an estimate of the access time is obtained as follows: Costblock f etch = T cycles Costseq scan = Nblocks * T + CPU * Ntuples * block tuples * T In these expressions, T is the delay in cycles to fetch a block from the memory.
Relationship: reasoning
Domain: Hardware
Sentence 1: When examining the intru­sion detection process from an information-theoretic point of view, intuitively, we should have less uncertainty about the input (event data) given the IDS output (alarm data).
Sentence 2: our new metric, CI D (Intrusion Detection Capability), is de.ned as the ratio of the mutual information between the IDS input and output to the entropy of the input.
Relationship: reasoning
Domain: Hardware
Sentence 1: =- wk s wk 1 88 I = h ( v ) v -1 dv = 2 h ( v ) vu cosh xdx = H ( x ) dx i .
Sentence 2: i .. 0 -8 -8 u = exp( - 2 sinh x ); v = (1 + u ) -1 at each step of the recursion, we compute the mean and standard deviation of wk.
Relationship: reasoning
Domain: Hardware
Sentence 1: Each IPD represents a in­tegral union of parameterized polytopes containing all IPs at which the input argument of the assignment statement embedded in the process is being produced by one process.
Sentence 2: without lost of general­ity, we will assume that each IPD is represented by only one inte­ k gral parameterized polytope of dimension k,D=C(N)n. P. each P/C pair is uniquely represented by a polytope C(N) together with an af.ne dependency function frepresented by an integral matrix M, and an offset vector 0, i.e., f(x)=x+0.
Relationship: reasoning
Domain: Hardware
Sentence 1: For a difference vector between the same notes with different timbres, its spectral components are mostly placed at the positions of f0, 2f0, 3f0, etc, assuming f0 is the fundamental frequency.
Sentence 2: the spectral peaks are mostly spaced with some prominent regular intervals, such as 12 semitones (octave), 7 semitones (perfect fifth) or 4 semitones (major third).
Relationship: reasoning
Domain: Hardware
Sentence 1: Similarly, from Section 2.2, we also know that (i, s) remains unchanged on cast by P. Moreover, we know that the .nal output of P is s, while by design of A and Property P5, the cast vote record of A generates an accurate ' copy of s. Thus, IO(zm)= zm = s. ' m In all cases, we have shown that IO(zm)= zm and that s = (s m) ' .
Sentence 2: by induction we have shown that IO(zi)= zi ' for all i s.t.
Relationship: reasoning
Domain: Hardware
Sentence 1: Actually, PCS simula­tions exhibit high locality of communication among the LPs hosted by the same machine, thus yielding a situation in which communication operations typically under-utilize the network hardware.
Sentence 2: pCS simulation should actu­ally take advantage from semi-asynchronous checkpointing since no additional rollback penalty (due to excessive in­crease in the delivery delay of messages/antimessages at the simulation application level caused by overload on the hardware) should be paid.
Relationship: reasoning
Domain: Hardware
Sentence 1: Many important characteristics of such large networks have been essentially impossible to understand fully using hand analysis so far, in part because pattern generation is often very sensitive to small details of the nature of and coupling between individual network entities [13], [14].
Sentence 2: analytical simpli.cations that may be justi.ed for small systems are potentially inapplicable to much larger ones and can lead to egregious mispredictions.
Relationship: reasoning
Domain: Hardware
Sentence 1: In the desired case, shown in Table 2, the delays vary between paths in either voltage domains for PVT corners, the skew being affected less from PVT variations.
Sentence 2: although the skew is increased in the best corner (from 5.28 ps to 25.4 ps), global skew is de.ned as the worst case of all corners: global skew is improved from 86.11 ps to 39.47 ps, when the insertion delay is shifted by an upsizing.
Relationship: reasoning
Domain: Hardware
Sentence 1: In particular, Weinberg s method tended to overestimate walking speed on stairs, be­cause walking up/down stairs has higher acceleration range compared to walking on a .at surface, while the actual strides were con.ned to the step length of the stairs.
Sentence 2: weinberg s method, which assumes that the stride length is proportional to the acceleration range, consistently overesti­mated the walking speed.
Relationship: reasoning
Domain: Hardware
Sentence 1: Using our transformations allows the creation of a range of instances around any given arbitrary benchmark.
Sentence 2: for the .rst time, the .eld is a.orded a means of cre­ating similar instances in a systematic way such that the suboptimality and consistency of placement quality can be immediately evaluated Our future work will focus on extending this work to (1) 8-change transformations, where the introduced transforma­tions cause a 8 change in the HPWL, but at the same time, the change in the optimal HPWL can be bounded, and (2) suboptimality evaluation using other metrics such as recti­linear minimum spanning trees, or Steiner trees.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then, for each S-Box a.ected by a fault, there ex­ist several key values that satisfy the equivalence given by Equation 9.
Sentence 2: one can understand why several erro­neous cipher texts are needed to obtain the key K16.For each erroneous cipher text analyzed, the key search space be­comes smaller, since the keys that do not satisfy the equality are discarded.
Relationship: reasoning
Domain: Hardware
Sentence 1: of the voltage VC , and since this voltage is used to supply the comparators, the whole power pro.le cannot be used to 4.1 Performance in a real-life case test the harvester equipped with the LM V 7271-based rec- As .nal test, we calculated the amount of energy collected ti.ers, because the maximum supply voltage is 5.5V.
Sentence 2: by a two-stage air-.ow energy harvester equipped with the to emulate a real case study, the reduced window delim­ discussed recti.ers.
Relationship: reasoning
Domain: Hardware
Sentence 1: Parameterized Block-Based Non-Gaussian Statistical Gate Timing Analysis Soroush Abbaspour, Hanif Fatemi, Massoud Pedram Department of Electrical Engineering, University of Southern California {sabbaspo, fatemi, pedram}@usc.edu Abstract As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability.
Sentence 2: statistical timing analysis (denoted by sTA) is becoming unavoidable.
Relationship: reasoning
Domain: Hardware
Sentence 1: The smallest value in this lattice is CF, the largest is C. Figure 3: Annotation Lattice If the result of DERIVEREL(R1, R2) is an element of the set {CF, <, EXT, <R}, then enabling R1 and R2 simultaneously will appear as though R1 executes before R2 (provided of course, the circuits to call the methods that R1 and R2 call are correct).
Sentence 2: for each pair of rules, we can determine their sequential scheduling relationship.
Relationship: reasoning
Domain: Hardware
Sentence 1: Among the replacement policies, cache with the Round-robin replace­ment policy demonstrates lower energy consumption compared to a cache with the LRU replacement policy [4].
Sentence 2: round-robin is widely used for L1 cache replacement policy in embedded pro­cessors (i.e., Tensilica Xtensa LX2 processors [3] and Intel XScale processors [1]).
Relationship: reasoning
Domain: Hardware
Sentence 1: Similarly, we first classify all entries into three circles, R , R , and 0.5 2.5 R 4.5 , and then pair all entries in each circle.
Sentence 2: we derive the pair sequence P4×4 = [(a22, a33), (a32, a23), (a12, a43), (a21, a34), (a31, a24), (a42, a13), (a11, a44), (a41, a14)].
Relationship: reasoning
Domain: Hardware
Sentence 1: The resulting automaton graphs still contain e-transitions which must not exist in the .nal controller RTL description in order to be synthesizable into hardware.
Sentence 2: in the next step a trans-  s == p1 s == p2 G1 G1 G2  e e .. 12  (a) FA graph with labeled e edges (b) condensed FA graph without e edges Figure 6: Transformation of FA graph with e transitions into a condensed FA without e transitions formation is applied to the two automaton graphs which gener­ates equivalent graphs without e-transitions.
Relationship: reasoning
Domain: Hardware
Sentence 1: 978-3-9810801-8-6/DATE12/ c @2012 EDAA old and new circuits [1, 6, 24]; however, when the old and new circuits are synthesized from RTL designs, these two circuits can be drastically changed due to logic synthesis.
Sentence 2: fault modeling methods are not adequate to de­scribe the di.erences.
Relationship: reasoning
Domain: Hardware
Sentence 1: for a template of the CDFG G is represented by a vertex vS in the con.ict graph G.If two matches S1 and S2 have one or more nodes in common, there will be an edge between the two corresponding vertices vS1 and vS2 in the con.ict graph G.The weight w(vS )of a con.ict graph vertex vS is the number of CDFG nodes |S|within the corresponding match S. The vertex set of the con.ict graph are partitioned into subsets, each of which cor­responds to a certain template (see Figure 9).
Sentence 2: on the con.ict graph, vertices of the same subset have the same weight.
Relationship: reasoning
Domain: Hardware
Sentence 1: The minimal-length sequences are concatenated in the applied test, leading to the well known MATS+ test [6]: m(wB);*(rB,wB);+ (rB,wB)Because address faults may cause a high num­ : ber of cells to show faulty behavior and the amount of re­sources for recon.guration is assumed to be restricted, di­agnosis of the type of address decoder fault is not performed here.
Sentence 2: recon.guration for address decoder faults is not addressed.
Relationship: reasoning
Domain: Hardware
Sentence 1: If we allow the simultaneous triggering of different tasks, which was our assump­tion, this leads to synchronizing the event streams, and that is to assume all the intervals, out of which we obtained the time lengths for our event streams, have a common start.
Sentence 2: the sum of the worst-case execution times of all events in all event streams hap­pening during a time of length .t, having their deadline within that time, gives us an upper bound of the execution demand for any interval of length .t.
Relationship: reasoning
Domain: Hardware
Sentence 1: Concretely, each word unit consists of the following sequences: AA AE AH ... Z ZH AA AA AA AE ... ZH ZH AA AA AA AA AA AE ... ZH ZH ZH  We allow the recognizer to treat each audio sample as consisting of from 0 up to 10 words, and match each word to one of the above sequences.
Sentence 2: the upper bound on the number of phonemes in a word that our system can recognize is 30 phonemes large enough to adequately capture any word or short phrase.
Relationship: reasoning
Domain: Hardware
Sentence 1: The row interchange is easily performed by switching the elements of the register at positions j and m. As it is done in the mathematical speci.cation, the function partial_pivoting_arch is used by the operator elim_col_below_arch, with row indices for the current col­umn and the row of the pivot found by f_p_arch.
Sentence 2: elim_col_below_arch modi.es the rows by linear combina­tions in such a way that all values below the current diagonal element become equal to zero.
Relationship: reasoning
Domain: Hardware
Sentence 1: Error Detectability Table In order to understand the above constraints, observe that () n+k (i) if V1j ßmod 2=1, the XOR of the bits in the j=1 j set represented by the vector ß(i) detects the erroneous case EC1.
Sentence 2: in order to detect EC1, we require that at least one of the £ subsets represented by the vectors ß(i) detects the erroneous case.
Relationship: reasoning
Domain: Hardware
Sentence 1: The spacer acts like a lay­out separator among main mandrels and secondarypatterns.
Sentence 2: if we split apolygonintotwopolygons and select one (1) target (2) core mask (3) sidewall spacer (4) trim mask Figure 2: A 2D .ow of SID-type SADP (1) Decomposable in LELE (2) Undecomposable (3) Odd cycle using stitch insertion even in LELE coloring conflict Figure 3: Coloring con.ict in layout decomposition polygon as a main mandrel, it would result in disconnecting the .nal patterning results due to spacer blocks.
Relationship: reasoning
Domain: Hardware
Sentence 1: This makes it an interesting alternative to other approaches for increasing resolution, such as the combination of STFT and autocorre­lation function [10]: A key feature of the NSGT is that once a beat period has been estimated, the beat phase informa­tion is contained in the phase information of the complex analysis coe.cients.
Sentence 2: beat tracking can be performed by computing the inverse transform after appropriate .lter­ing in the transform domain.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, an MC requires a lot of resource since it is composed of a read queue, a write queue, a command queue and the TSV array that provides vertical lines for control signals and the data bus to the stacked DRAMs.
Sentence 2: for a 3D integrated processor-DRAM system to go into the mainstream market, a system­level synthesis tool to design the distributed memory interface of NoCs with stacked DRAMs is necessary.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, the exact analysis of task schedulability is finally : VTj E hp(i), 3RTi < Di with RTi~-Ci+Bi.-t-Tcomi.-I-~ rRV~q,(C~+Tcomj) (2) :~hpCi) I Pj I This is not the scope of this paper to detail precisely how HW/SW communication are correlated with the size of the HW accelerator, but we can indicate that it depends on four parameters given in eq.3 : Tinitis the initialization delay of the communication, Tda~ais linked with the data format, Dmemis the number of data transfered to/from the local memory of an accelerator and Nit the number of times the accelerator is fired to execute the task (in a given period).
Sentence 2: 87 we observe a trade-off between the accelerator parallelism (i.e.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then the number of nodes in the overall graph model is 6n - 4, which is linear in n. Similarly, the number of edges in the overall graph model is also linear in n. In the implementation, the graph model is constructed in linear time, and the shortest path algorithm is implemented using Fibonacci heaps [6].
Sentence 2: the entire time complexity of our algorithm is O(nlogn).
Relationship: reasoning
Domain: Hardware
Sentence 1: For each such case, the minimum leakage in the subtree rooted at Gi is the sum of leakage at gate Gi and the minimum leakage at each of its fanin gate Gij with output xij , LK(ij ,xij ).
Sentence 2: we have t LK(i, z)= min (L(Gi(x )) + LK(ij ,xij )) .xx,s.t.Gi outputs z j=1 (2) Note that Gi s fanin gates {Gi1 , ··· ,Git }do not share any com­mon input signals due to the structure of tree circuit.
Relationship: reasoning
Domain: Hardware
Sentence 1: The peak power draw of the CPU operating at 520 MHz under 100% load is around 735mW (Figure 4), while the peak power dissipa­tion in Figure 7 is around 600mW hence the CPU load is not at 100%.
Sentence 2: lower CPU speeds yield simi­lar performance bene.ts while requiring less energy due to lower idle and peak power dissipation.
Relationship: reasoning
Domain: Hardware
Sentence 1: 13, we .nd that PDeVeriT rust is dominated by the probabilities of some terms, such as cn0 pn0 that is used to com­bine with the malicious on-set term cm0 pm0 .
Sentence 2: we pro­pose the following three methods to increase the stealthiness of HTs against VeriTrust: Combine simpli.ed malicious products (rather than malicious on-set terms) with on-set terms from the normal function, so that fewer terms from the normal function are required to be activated to evade VeriTrust.
Relationship: reasoning
Domain: Hardware
Sentence 1: The theory of Lagrange multipliers shows that for every W, there exists a Lagrange multiplier .such that the minimization of max{T1(w1)T2(w2)}is equivalent to the minimization of the right-hand expression in Equation (4) [12].
Sentence 2: instead of min­imizing max{T1(w1)T2(w2)}, we solve Equation (4).
Relationship: reasoning
Domain: Hardware
Sentence 1: Although the CAM access latency fits in the decoder slack and introduces only 10% per-cache-access energy overhead at 0.18um technology, as it comes to a nano-scale technology such as 32nm, the CAM access latency exceeds the decoder slack by 20%~40% and incurs a large per-cache-access energy overhead [13].
Sentence 2: it is important to find an energy-efficient approach to addressing the hot cache set problem in hybrid caches without requiring serial tag/data array access.
Relationship: reasoning
Domain: Hardware
Sentence 1: For the baseline cache random replace­ment reduces MPKI for the thrashing workloads: art by 34%, mcf by 1.6%, facerec by 14.4%, and health by 16.9%, whereas, DIP reduces MPKI for art by 54%, mcf by 17%, facerec by 36% and health by 35%.
Sentence 2: the effectiveness of random replacement at reducing misses signi.cantly reduces as the size of the working set increases.
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, the payoff function of any net segment in the channel depends only on two other players (the left and right immediate neighbors) rather than on all the N-1 players.
Sentence 2: for each channel, instead of having a single game with N-players, we divide the game into N subgames with each subgame involving 3-players the given net segment, its left neighbor, and, its right neighbor.
Relationship: reasoning
Domain: Hardware
Sentence 1: By employing a fixed pruning threshold of 17, the 0.0037 BER is not exceeded for Eb/N0 greater than 2.1 dB while decoding the rate-1/2 code.
Sentence 2: with this pruning threshold, a slight coding loss of about 0.1 dB is incurred when decoding the rate-1/2 code.
Relationship: reasoning
Domain: Hardware
Sentence 1: To tackle this problem, we add a dummy FF node to each LC (including the LC originally in combinational mode), and constrain that FFs can only be inserted at edges from FF node to LC output node as shownin(B).ToensureanLUT drives onlyFFs within the same cluster after retiming, the total FFs used within one cluster can not exceed the number of available FFs in the cluster.
Sentence 2: we have the following constraints X e(u,v).ECi w(e)+ r(v) - r(u) = SCi, .Ci r(v) - r(u)=0, .e(u, v) .
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that March element M0 takes 1N clock cy­cles, March elements M1 'M4 take 2N clock cycles each, and March element M5 takes 1N clock cycles, where N is the num­ber of memory cells.
Sentence 2: the proposed BIST scheme takes only 10N clock cycles to perform the March C test al­gorithm.
Relationship: reasoning
Domain: Hardware
Sentence 1: The bene.tofcyclic partitioning can be illustratedby the following example: EXAMPLE 12. for(i=0;i<=N; i++) t+= A[2* i] +A[2* i+1]; Itisclearly that those two array accesses will be split to bank 0and1 respectively for partitioning P(a)=a mod 2.
Sentence 2: no decoderis needed compared with the"segment con.guration" architecture,while only one bank is activatedfor each original ar­ray access.
Relationship: reasoning
Domain: Hardware
Sentence 1: ThisfamilyhasbeendesignedatPhilipsSemiconductors Z.andisbasedontheasynchronous80C51 urichmicro­controller.Themainreasonforanasynchronousdesign wasreducingtheelectro-magneticemission.
Sentence 2: inmostofthecurrentpagerproducts,themicrocon­trollerhastobedeactivatedduringreceptionofames­sagetoavoidinterferencewiththehighlysensitiveradio receiver.Thereforedecodingisperformedbyadedicated  80C51microcontroller,reducedtheelectro-magneticin­terferencetoadegreeallowingthemicrocontrollertobe activealsoduringreception.themajorityof thedecoderfunctionalitycouldbeimplementedinsoft­wareresultinginalow-costpagingchip,whichcanhandle anyprotocolusingdedicatedsoftware.
Relationship: reasoning
Domain: Hardware
Sentence 1: ].x-1)]V Y[1...(T H[b.].y-1)])+w(b.)
Sentence 2: thebuketlistiskeptininreasingorderonindex.Theel­ementinthebuketlistwithgreaterindexbutlessvalueis uselesstosubsequentLCSomputation.Inline10,theuse­lesselementsaredeleted.predeeSSor(p)(now, p=T H[b].y=j)willbeT H[b.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since it is rare if not impossible for di.erent regions to simultaneously reach their maximum thermal-power, the assump­tion of steady-state analysis may also lead to excessive numbers of vias.
Sentence 2: it urges us to provide a stapling method us­ing transient analysis to .nd the minimum number of non-signal vias, such that both power integrity in P/G planes and thermal integrity at device layers can be satis.ed.
Relationship: reasoning
Domain: Hardware
Sentence 1: For instance, for the largest benchmark circuit s38417, when as­suming that the non-Gaussian Le parameters follow Gaussian dis­tributions, the error observed is 2.81% for µ, 34.62% for s, 21.63 % for the 95% point and 2.51% for the 5% point.
Sentence 2: modeling the non-Gaussian parameters as normally distributed ones leads to signi.cant inaccuracy.
Relationship: reasoning
Domain: Hardware
Sentence 1: IR-drop constraint IR-drop is the voltage .uctuation due to the resistance of the on-chip P/G networks.
Sentence 2: e.g., the voltage .uctua­tion from ground pads to the leaf nodes must be restricted = Vmax, (11) Vk.Nleaf where Nleaf is a set of leaf nodes and Vmax is the maxi­mum voltage of ground bounce.
Relationship: reasoning
Domain: Hardware
Sentence 1: (38) 2 Moreover, we assume that the LQG cost W = I and U =1.
Sentence 2: 1.5 the control gain is given by L = -1.2439 -0.4221 1 (39) 1 We consider two cases, where either the velocity sensor or 0.5 the position sensor is compromised, i.e.
Relationship: reasoning
Domain: Hardware
Sentence 1: Also, since we are interested in the relative weight between temporal and spatial di.erence, we set tscale = 1.
Sentence 2: the distance between two o.sets is:  |T | 2 i=1 Ti d(oi,oj )=+ oscale × (oi -oj )2 |T| Wechose meanover medianbecauseofthevariabilityinthe potential workloads.
Relationship: reasoning
Domain: Hardware
Sentence 1: Moreover, level shifters need to be inserted at the boundaries between low-Vdd and high-Vdd, causing extra penalty in area, delay and power.
Sentence 2: it is desired that cells of dif­ferent supply voltages are grouped into a small number of voltage islands (each having a single supply voltage), so that both the de­sign cost and the amount of level shifters are limited.
Relationship: reasoning
Domain: Hardware
Sentence 1: The congestion cost computation of a match takes O(lNtalxNs),where lNtalis the number of nets associated with a match and Nsis the number of bins over entire layout; Nsis a constant for a given layout.
Sentence 2: congestion cost computation takes O(lNtal)time, the same as that required for structural matching used in the SIS mapper [9].
Relationship: reasoning
Domain: Hardware
Sentence 1: Recall that in section 3.2, if Vout > Vref, QN-1 will be 1 and if Vout < Vref, QN-1 will be 0.
Sentence 2: the sensors outputs, QiN-1 s, i = 1 4, can indicate whether the output voltage is larger or smaller than Vref.
Relationship: reasoning
Domain: Hardware
Sentence 1: Let q£ (respectively, qu) be the query rate of items obtaining allocation e (respectively, u).
Sentence 2: we have xq£ +(m - x)qu =1 and vv v q£/(xq£ +(m - x) qu)= e. Substituting x and solving the above we obtain 2 e q£ = u + e - meu 2 u qu = u + e - meu at the minimum point, vvv v qi = xq£ +(m - x) qu =1/u + e - meu .
Relationship: reasoning
Domain: Hardware
Sentence 1: As well known, however, OFDM-based systems are very sensitive to the frequency o.set (FO) caused by a mismatch between the oscillators in the transmitter and receiver or a Doppler frequency, resulting in a signi.cant performance degradation.
Sentence 2: the FO estimation is one of the most important procedures in the OFDM-based systems.
Relationship: reasoning