sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: As the weight associated to variables [,,,x3 and x4 is 2, there are two transmission gates connected to logic 1 at the bottom, and another two transmission gates connected to logic 0 at the top for both columns.
Sentence 2: as we have chains of nMOS transistors in the nMOS networks, after a careful study of the situation additional intermediate swing restora­tion may be needed (see the arrows in Figure 8 for their possible placement, after 4-transistor paths).
Relationship: neutral
Domain: Hardware
Sentence 1: With all prefetchers we vary the degree of prefetching from 1 to 16.
Sentence 2: comparing G/DC and our proposed prefetcher PC/DC/MG reveals that PC/DC/MG outperforms G/DC in 11 of the applications by as much as 45% in milc G/DC outperforms PC/DC/MG in 5 of the applications by as much as 32% in lbm and they perform similarly (within 1% of each other) in the remaining 4 applications.
Relationship: neutral
Domain: Hardware
Sentence 1: [10] N. Shirazi, A. Walters and P. Athanas, Quantitative analysis of floating point arithmetic on FPGA based custom computing machines, IEEE Symposium on FPGAs for Custom Computing Machines, April, 1995.
Sentence 2: [19] J. Patterson, Accurate Static Branch Prediction by Value Range Propagation, Proc.of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pp.
Relationship: neutral
Domain: Hardware
Sentence 1: The algorithm proposed in [12], [2] and [6] base on the fact that the HPWL wire-length function of the x-coordinate of a cell is a convex function.
Sentence 2: by comparing the over.ow values in Table 2, 3 with the over.ow values of given input global placement solution from Table 1, we can see that our detailed placer can e.ectively reduce the placement density over.ow to nearly zero, while HPWL is also signi.cantly reduced by 6.27% on average even under the tight displace­ment constraint, and 9.49% under the relaxed displacement constraint.
Relationship: neutral
Domain: Hardware
Sentence 1: With .le-level LFU, 200 streams are served from the .ash memory when the arrival rate is 0.16, consuming only 31% (200/647) of the available bandwidth of the .ash memory.
Sentence 2: flash memory SSD designer should design the SSD architecture to increase the capacity and the bandwidth both by maxi­mizing the parallelism of .ash memory chips to make a .ash memory SSD suitable for VoD storage.
Relationship: neutral
Domain: Hardware
Sentence 1: Sincethese latter play a dominant role in determining the minimumoptical power that laser sources should provide to satisfyspeci.c detector sensitivities, we consider two relevant and TABLE I LAYO U T-AWA R E P RO P E RT I E S O F TO P O L O G I E S U N D E R T E S T Total number of Wavelenghts Max number Crossing Max wire length cm Total number of MRRs Type of MRR 4-RINGS 4 3 3.2 40 (8 IC) 4 4x4 SNAKE 4 6 2.4 32 (8 IC) 4 4x4 .-Router 4 15 1.8 32 (8 IC) 4 4x4 Folded Crossbar 4 21 2 40 (8 IC) 4 5x5 GWOR 4 31 2.4 40 (8 IC) 4 increasingly aggressive optimizations: elliptical tapers [13] andMulti-Mode-Interference (MMI) tapers [14].
Sentence 2: an alternative topology is illustrated in [7] and is named4x4-lambda Router.
Relationship: neutral
Domain: Hardware
Sentence 1: On each time interval boundary, the SLLC s space partitioning result for Corei is kept in the partition quota counter, denoted as Qi, where 0 = i = N - 1.
Sentence 2: one of our research motivation lies in the question of whether or not locality optimiza­tion alone can provide high enough performance for prac­tical SLLC capacity management.
Relationship: neutral
Domain: Hardware
Sentence 1: The true voltage values at node A, B, C and D are 0.6, 0.8, 0.7 and 0.9, respectively.
Sentence 2: for a power grid with N non-VDD nodes, we can estimate worst-case time complexity as O(LMN), where each unit corresponds to one random-number generation, a few logic operations and one addition.
Relationship: neutral
Domain: Hardware
Sentence 1: Fig.6 shows the normalized operating $¢n~ of Frlquer)cy to Vdd 9 -IT = , m Figure 4: VTC for Various Vad Ratio of (W&#38;)~(W/L)n V= D~ay x to "l 14 13 12 11 lO i i i 2 3 5 Ratio of (WtL)p/(W/t_)n Figure 5: Size Ratio of PMOS to NMOS vs. Delay frequency sensitivity to Vad variation.
Sentence 2: one way to achieve this goal is by running the digital circuits in sub-threshold re-gion.
Relationship: neutral
Domain: Hardware
Sentence 1: Neither of the two endpoints can locate inside an obstacle (see Figure 2(c)), but they could be on the bound­ary or at the corner of an obstacle (see Figure 2(d)).
Sentence 2: a direct extension of Escape Graph to the OAPDST problem is to modify rule 1 to meet the PD constraints and con­struct the modi.ed Escape Graph on each layer.
Relationship: neutral
Domain: Hardware
Sentence 1: 1.2 Our Contributions To address the above challenge, this paper makes one of the .rst steps in providing performance guaranteed energy management (conserving energy without violating the user speci.ed slowdown limit) for multithreaded applications on multiprocessor architectures.
Sentence 2: the fact that it cannot provide performance guar­antee o.sets the small bene.t in energy conservation.
Relationship: neutral
Domain: Hardware
Sentence 1: (C1 · gm11 · K · (N - 1)) Gm2 = v (9) (C1 + C2) · .VT · 2(1+ 1+4 · IC)(N +1) · M where, K is the current mirror gain and N is the ratio of aspect ratio of M11 to aspect ratio of M13.
Sentence 2: w = 100µmand L =3µm for input transistors having transconductance of Gm1.
Relationship: neutral
Domain: Hardware
Sentence 1: (8+dlog2ndictionarye) bits,wherendictionaryisthenumberofmemoryentriesof thedictionary.Similarly,thememoryrequirementsforthe indexarenindex.dlog2ndictionaryebits,wherenindexisthe numberofmemoryentriesoftheindexanddlog2ndictionarye isthenumberofbitsrequiredtoaddressthedictionary.
Sentence 2: oUR COMPRESSION TECHNIQUE Ourcompressiontechniqueisbasedontheprinciplesof dictionary-basedcompressionalgorithms.Eventhoughsta­tisticalmethodscanachievehighercompressionratios[11], weproposeadictionary-basedapproachbecausedictionary­basedschemesleadtosimplerandfasterdecompressionhard­ware.Inourapproach,thedictionarycorrespondstocon­ .gurationdataandtheindexcorrespondstothewaythe dictionaryisreadinordertoreconstructacon.guration bit-stream.InFigure2,anoverviewofourcon.guration compressiontechniqueisshown.Theinputcon.guration bit-streamisreadsequentiallyinthereverseorder.Then, thedictionaryandtheindexarederivedbasedontheprin­ciplesofthewell-knownLZWcompressionalgorithm[11].
Relationship: neutral
Domain: Hardware
Sentence 1: The V-FPGA was downloaded to an FPGA for hardware testing.
Sentence 2: in order to implement the clock divider circuit in Figure 7, the following V-FPGA was generated: Number of LEs, n = 3  Number of DFFs, m = 1  Number of external inputs, p = 1  Number of external outputs, o = 1.
Relationship: neutral
Domain: Hardware
Sentence 1: After that, dummy value assignment is performed with the guidance generated by using a quasi-inverse lithography technique to evaluate the dummydemands of di.erent regions.
Sentence 2: previous work has reported that one percent change in .are level may cause 10 nm change in CD (CD sensitivity on .are is 10 nm/% ..are level) at the 22 nm technology node and may be considerably larger for more advanced technology nodes [10].
Relationship: neutral
Domain: Hardware
Sentence 1: We say that the blockage effect is additive (the denominator is taken care of by the redistribution effect) and we can treat the problem as a combina­tion of single obstacle problems.
Sentence 2: otherwise, the cal­culation under the assumption that it is additive produces an over­estimation of the blockage effect.Observation 11 The total wirelength increases as the number of obstacles increases while the total obstacle area remains the same.
Relationship: neutral
Domain: Hardware
Sentence 1: The hit counter Hk is increased by one when an access to cache line C hits in the kth way of the shadow tag of the pro.l­ing unit, which means k distinct cache lines in the same memory region have been accessed between the two consecutive accesses to cache line C. The value k is referred to re-use distance of the cache line C. If k is large (say 12 for a cache with associativity of 16), it is highly likely that the access to cache line C would be a cache miss when the memory region shares the cache color with a large number of memory regions, and vice versa.
Sentence 2: a memory region refers to a group of physical pages that share the k least signi.cant bits of page num­ber, where k is a design choice.
Relationship: neutral
Domain: Hardware
Sentence 1: entries: Local: 64(L1)+128(L2), Global: 512, Choice: 512, RAS: 16, CTB: 16, BTB: 128, Btype: 256.
Sentence 2: globalwiredelayshaveresultedinthe emergenceofpar­titioned architectures, such as CMPs and tiled architec­tures[22].
Relationship: neutral
Domain: Hardware
Sentence 1: While partitioning a cache into banks mitigates the impact of localized wire delay, the glo­bal wire delay to access the appropriate banks becomes the dominant factor as chips move to smaller geometries.
Sentence 2: the latency of a transmission line to the .rst order is determined by the speed of light in the dielectric sur­rounding the interconnect instead of the time to change the charge across the wire s capacitance.
Relationship: neutral
Domain: Hardware
Sentence 1: Sensi­tivity analysis is based on the assumption that the statistical circuit response to variations in process parameters (f ) is approximately by a linear superposition of input sensitivities, n with f = s + P i=1 [sV ti · .Vti + sßi · .ßi/ßi].
Sentence 2: they are simple to imple­ment by simulating the response of the circuit to changes in Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: neutral
Domain: Hardware
Sentence 1: When technology scales down into 45nm and 32nm technol­ogy, each SKITTER sensor tends to have increasing number of stages, thereby larger area overhead.
Sentence 2: the variations considered in the experiments are: 10% (3 sigma) variation on the e.ective channel length Leff , and 15% (3 sigma) variation on the threshold voltage Vth.
Relationship: neutral
Domain: Hardware
Sentence 1: Accordingly, the number of SWAP gates is the di.erence of quantum cost before and after the op­timization.
Sentence 2: after distinguishing sets and appropriate qubit orderings for each set, we apply [19, Theorem 1] to .nd the minimum 5Trees, rectangular and square meshes and hypercubes are exam­ples of graphs that can be solved in polynomial time with optimal MinLA solution [25].
Relationship: neutral
Domain: Hardware
Sentence 1: Instead, it may be more attractive to merely test for errors and detect/correct errors at a high enough rate so as to reduce error rates to an acceptable level.
Sentence 2: note that the ECQ is essentially a .rst-in-.rst-out structure (FIFO) and can be implemented as a cir­cular queue; instructions are inserted starting at the tail of the queue and removed starting at the head.
Relationship: neutral
Domain: Hardware
Sentence 1: LowP ressureLimit(LP L)= min +(a × (max -min)) (1) PACT 10, September 11 15, 2010, Vienna, Austria.
Sentence 2: when the pressure of a set is above HPL, the set is considered to be within the limit of source sets and is permitted, accordingly, to retain its lines at multiple des­tinations sets.
Relationship: neutral
Domain: Hardware
Sentence 1: the iteration has to be continued as long as new activations of ti arrive before the previous .nish; Bi(wi(q)) is the maximum blocking time of ti in wi(q); .j +(wi(q)) · Cj is the interference ti suffers due to the maximum workload of a higher priority job tj in wi(q).
Sentence 2: the activating events are modeled as arbitrary event streams [21], [22] using upper and lower event arrival func­tions .+(.t) and .-(.t).
Relationship: neutral
Domain: Hardware
Sentence 1: As ..¯= ..¯, .. .. ..=1 ..=1 (2) (1) there exists at least one .. ' >.. such that ..¯> ..¯= 0.As .. ' .. ' n for ...1,..2 ..... , L..1 L..2 /= Ø (both contain ..), we have L..1 .L..2 or L..1 .L..2 .
Sentence 2: power grid veri.cation is becom­ing an indispensable procedure to guarantee a functional and ro­bust chip design.
Relationship: neutral
Domain: Hardware
Sentence 1: Incremental partitioning-based vectorless power grid veri.cation.
Sentence 2: = b, (10) xrm xm where Gri (Gi) is the conductance matrix of the coarse (.ne) grid block i, m is the number of blocks, ti for i =1, ..., m are the block scaling factors to be found, a is a weighting coe.­cient, and nri (ni) is the number of nodes in the coarse (.ne) grid block.
Relationship: neutral
Domain: Hardware
Sentence 1: Ioff difference between the best and worst case is ~20X for DG and ~175X for bulk Si.
Sentence 2: to resolve 0 500 1000 1500 2000 Clock Frequency (MHz) 5 Power(1,1)/Power(0,0) 4 3 2 this, DG CMOS could be resorted.
Relationship: neutral
Domain: Hardware
Sentence 1: ASP Design Automation Conf., pp.
Sentence 2: since f is invariant with respect to permutations inside C1 or C2, there are only 222!=8 distinct transformations, which result from transformations on NE-classes C1 and C2 i.e., (C1,C2), (C1,C2 ), ( C1 ,C2), ( C1 ,C2 ), (C2, C1), (C2, C1 ), ( C2 ,C1), and ( C2 , C1 ).
Relationship: neutral
Domain: Hardware
Sentence 1: Another important point to be noted is that, the use of MS-CMOS circuits in RCM barely perform ~10x better than the digital implementation and hence achieve far less energy efficiency as compared to the proposed design.
Sentence 2: 7, and the result is used to modify the SAR logic using the scheme described above (though pass-gate based multiplexers P, driven by a global controller).
Relationship: neutral
Domain: Hardware
Sentence 1: These equations are reproduced now in terms of our model param­eters.
Sentence 2: y0 ./B(x0) for at least one net segment playing the game (say, segment 1), 1 there is an y1 .S1 such that ( )( ) 10 00 f1y1, x2, ...x0 = f1y1, x20, ...x.
Relationship: neutral
Domain: Hardware
Sentence 1: However in wireless network which user doesn t have to be at one place to have access to the network, the result shows that streaming video with Flash video uses less CPU usage while with HTML5 video have a high video FPS.
Sentence 2: majority of online videos are shorter than 5 minutes in duration, a length generally preferred by users who view such content on computers or portable equipment, like cell phones, MP3 players or video game consoles.
Relationship: neutral
Domain: Hardware
Sentence 1: OurworkismostcloselyrelatedtotheapproachbyCoumeriand Thomas[13]toembeddedSRAMoptimizationforlowpower.
Sentence 2: thissimpleexamplehelpsinclarifyingwhymemorypartition­ingcanbeadvantageous.Inordertoautomatememorypar­titioning,weneedtorigorouslydefnecostmetricsandsearch space,andtoformulateanoptimizationalgorithmthatcanef­cientlysolverealisticinstancesoftheproblem.Theseissueswill beaddressedinSection4.Inthenextsection,wewillbriefy surveyrelatedworkonmemoryoptimization.
Relationship: neutral
Domain: Hardware
Sentence 1: The flexibility of the cell makes it power efficient with a minimum number of transistors which means improved integration density at the layout level.
Sentence 2: [5] M. H. Ben Jamaa, K. Mohanram and G. De Micheli, Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis , Design,Automation and Test in Europe (DATE).
Relationship: neutral
Domain: Hardware
Sentence 1: Instead, it relies on the application of a short read-pulse width, relying on the read-dynamic noise margin (DNM) characteristic of the 6T TFET cell, along with a ground-lowering read-assist, to avoid an upset during read operation.
Sentence 2: (C) Id-Vg characteristic for HTFET and (D) Id-Vg characteristic for Si NMOS cell, i.e.
Relationship: neutral
Domain: Hardware
Sentence 1: By this procedure, we convert the conventional GP formulation of the gate sizing problem to a robust gate sizing prob­lem, which is also a GP and hence, can be ef.ciently solved using the convex optimization machinery.
Sentence 2: the use of posynomial delay mod­els for the gate sizing problem enables the use of ef.cient convex optimization tools to solve the problem [3].
Relationship: neutral
Domain: Hardware
Sentence 1: Recent work proposes other per-structure optimizations for reducing resource pressure [6], such as packing dual instances of a dynamic instruction into the same physical register for short­width values (exploiting advance knowledge from the leading thread) or intelligently reallocating some leading thread s physical registers to the trailing thread to yield a net reduction in physical register pressure.
Sentence 2: general Terms Design, Performance, Reliability.
Relationship: neutral
Domain: Hardware
Sentence 1: Most existing solvers, in­cluding Chaff [17], do not support dynamically adding new Boolean  1000 1000 1000 Per variable assignment Per full assignment 100 10 1 Figure 3: Different invoking settings for theory propagation: per predicate assignment, per decision level, and per full assignment.
Sentence 2: such an exhaustive approach may be costly.
Relationship: neutral
Domain: Hardware
Sentence 1: The number of possible states increases exponentially to the number of FUs in a cluster and one change (exchanging spares) can cause switch-box state recursive dependency.
Sentence 2: each switch box can redirect data in four ways: straight (north to south), left (north to west and east to south), right (north to east and west to south) and pass-through (east to west or west to east) as shown in Fig.
Relationship: neutral
Domain: Hardware
Sentence 1: While state-based full predication (SFP) can remove wasteful power consumption onissuing/decoding instructions from conventional full predication,generating code for SFP is challenging for general CGRAs,especially when there are multiple conditionals to be handleddue to exploiting data level parallelism.
Sentence 2: sFP mechanism is implemented on PEs as suggested in [9].
Relationship: neutral
Domain: Hardware
Sentence 1: So, the direct BEM is more suitable for simulation of the parasitic capacitors with finite domain and multiple dielectrics.
Sentence 2: 4×4 95 9903 0 993038 30 9.6 × 5 37647 1 964454 34 5.4 Table II shows the total capacitance, CPU time and memory usage of the QMM compared with those of non-QMM.
Relationship: neutral
Domain: Hardware
Sentence 1: To further alleviate the impact of multipath noise, a 10ms guard time between the sync signals, as well as a 3ms guard time between the adjacent Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Sentence 2: the depth of the experimental area is 1.5-2m.
Relationship: neutral
Domain: Hardware
Sentence 1: Setion4proposesthenewmethodologythatseletivelyap­pliestestpatternsandhenereduesthetestingtimein randompatterntesting.ConlusionsaregiveninSetion6  2.
Sentence 2: arithmetibuilt-inself-test(ABIST)shemein[12].Their methodologyusestheprogrammabilityofDSPorestotest peripheraldevies.theyassumedthatadediated testaessmehanismexistsfromtheDSPoretoeahore undertest,whihwedonotneed.Ourapproahisalsodif­ferentfrom[8,12]inthatweuseatestpatternseletion mehanismtoreduethetestappliationtimefortheran­domtesting.ComparedtotheirombinedmethodofBIST anddeterministitehnique,ourtehniquerequiresfarless memoryusage.Papahristouetal.suggestedmiroproessor­basedtestingforore-basedSOCsin[13].Theyfousedon howtoahievetestpathsfromtheproessor,bypassingthe otheroresinbetween,andusedgraphmodelingtogetthe shortestpath.Ourapproahissimpler,sinewereusethe systembusintestmodeaswellasinfuntionalmode.
Relationship: neutral
Domain: Hardware
Sentence 1: --UhktRRtRtdss ,)()()(1[P())'(ßan(s', s)] =h1The (11) givesthe decodingprocess forinformationbits.
Sentence 2: the estimated MAI for the m-th sub-carrier is (3) .K) I~ ~)cos((()()',',''1)((),kmmkkrkcrkmiTticdEt.-.-=- k '=1 k '.k (r ) The I~k ,m (t) is low-pass filtered , and then subtracted from yk,m(t).
Relationship: neutral
Domain: Hardware
Sentence 1: A Morphing Approach To Address Placement Stability Philip Chong Cadence Berkeley Labs Berkeley, CA 94704 pchong@cadence.com ABSTRACT Traditionally, research in global placement has focused on relatively few simple metrics, such as pure wirelength or routability estimates.
Sentence 2: the future holds even more di.culties as phys­ical models for devices and interconnects become increas­ingly complex and unpredictable.
Relationship: neutral
Domain: Hardware
Sentence 1: The reason is that the difference between the sFMT and FMT comes from a reduction in the amount of stor­age, not logic, which leads to a reduction in leakage power; dy­namic power is affected less.
Sentence 2: 5.2 Microarchitectural evaluation Next to understanding the area, power and performance impli­cations of the new CPI counter architecture, it is also important to evaluate the impact on accuracy for the obtained CPI stack.
Relationship: neutral
Domain: Hardware
Sentence 1: If the inputs are connected in a way depicted in Figure 5(a), then based on the rules described in the pre­vious section, all three transistors are in recovery mode (see Figure 2(b) ABC = 100).
Sentence 2: vDD-Vth .Vth = AHCI × a × f × e toxE1 × t0.5 (2) where AHCI is a technology dependent constant, a is the activity factor, and f is the clock frequency.
Relationship: neutral
Domain: Hardware
Sentence 1: Three different prefetch hints can be speci.ed: NO_PREFETCH: do not perform prefetching at all.
Sentence 2: interaction between L0 Buffers and the L1 Cache The proposed L0 buffers are write-through (data is updated at L0 and L1 in parallel in case a store is marked to access L0, and only in L1 otherwise) so L0 buffers satisfy the inclusion property with respect to L1.
Relationship: neutral
Domain: Hardware
Sentence 1: This is a real advantage if one aims to -12 mirror CMOS circuit architectures in SET, because the equivalent SET circuits would require the use of a unique type of device.
Sentence 2: [26] K. Uchida et al., ''Programmable single-electron transistor logic for low-power intelligent Si LSI'', Digest of ISSCC 2002, pp.
Relationship: neutral
Domain: Hardware
Sentence 1: CONCLUSIONS We presented a framework for fast post-silicon segment diagnosis on failing speedpaths, which was based on our pro­posed ILP formulation.
Sentence 2: we enforce our de.nition of .j+1 using the alternative conditions of uj = lj+1 = L (when .j+1 =0) and uj +1 = lj+1 (when .j+1 =1).
Relationship: neutral
Domain: Hardware
Sentence 1: Evaluation I plan to use the Critical Exploration [3] methodology to co­explore the environment with children.
Sentence 2: this allows people to learn in a way that matches their style, and gives a path to re­see  what was originally out of the scope of awareness Film and Time­Lapse The camera also comes with  film  in the form of memory, which allows explorers to record and play back measurements over time.
Relationship: neutral
Domain: Hardware
Sentence 1: super-Vth sub-Vth comparison 2D 2D 3D 2Dsub 2Dsuper 3Dsub 2Dsub Target clock 15 50000 3333.33 1 Timing slack 1.626 9331 9938 Internal power 4.713 0.0001714 0.0001713 1/27497 1 Switching power 5.893 0.0001322 0.0001303 1/44576 0.985 Leakage power 0.00595 0.0008611 0.0008609 1/6.9 1 Memory power 0.7145 0.0008861 0.0008861 1/806 1 Total power 10.6 0.001165 0.001163 1/9099 1 TABLE V. TIMING AND POWER RESULTS FOR 8052 MICROPROCESSOR WITH 64KB EXTERNAL MEMORY.
Sentence 2: we add transistors in diode connection to control the pull up current.
Relationship: neutral
Domain: Hardware
Sentence 1: Instead of controlling/activating the bitlines according to the bit width of the narrow-width values, we divides the integer register values into two categories: 34-bit narrow-width values and 64-bit regular values.
Sentence 2: if a device has a highly biased duty cycle ratio, i.e., logic 0 for the pMOS device, it will have a heavy stress and the aging of the device will be accelerated.
Relationship: neutral