sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Low number of transitions is achieved by using a proper encoding, called di.erential bar encoding (DBE), which allows to achieve one transition per transmit­ted pixel.
Sentence 2: the encoding proposed in this work, called Limited Intra-Word Transition (LIWT), builds upon [3] and [4], in that it transmits pixel di.erences and uses the di.erential bar encoding as encoding basis; it generalizes the DBE by allowing codes with more than one intra-word transition per pixel.
Relationship: contrasting
Domain: Hardware
Sentence 1: Such value is an essential input to the instruction set ex­tension search algorithm, as it is a nonnegligible part of the speedup Table 1: Speedup results for two selected kernels of the JPEG  Atasu 1.1 0.9 Biswas coherence violating 9.0 1.3   Biswas Data Cache Flush 1.3 0.2 Biswas no Data Cache 6.2 0.7 Biswas corrected M(C) 1.1 0.9 Coherent DMA 6.3 1.0 Speculative DMA 9.6 9.0 metric that such algorithm tries to optimize.
Sentence 2: due to the dynamic nature of the speculative DMA transfers, the value calcu­lated statically for .overhead as in [4] may be extremely imprecise.
Relationship: contrasting
Domain: Hardware
Sentence 1: The far greater accuracy of the time-shifted nonlinear phase equation stems from its provable correctness for small perturbations [10].
Sentence 2: despite being nonlinear, time-shifted oscillator macro­models still have the drawback that they are small signal models extracted from linearizing oscillators about their steady-states; they only work well when perturbations to the oscillator are small.
Relationship: contrasting
Domain: Hardware
Sentence 1: For every value of d, we show the total number of faults with d(g1,g2,AND ) =d or d(g1,g2,OR ) =d, and the number of undetectable faults with this value of d. Table 4 shows that many undetect­able faults have d=0.
Sentence 2: not all the faults with d=0 are undetectable.
Relationship: contrasting
Domain: Hardware
Sentence 1: There is a number of methods that do not model electrical masking, and instead just focus on logical masking [5][7][8][10] and, in some cases, on latching-window (timing) masking (described in Section 2.4) [2][5][7][8][10].
Sentence 2: approaches that completely overlook electrical masking and simplify modeling by assuming logical and latching-window masking only, are unable to estimate the magnitude of error masking due to electrical effects, and thus provide too pessimistic error rate values, in many cases overestimated by more than a factor of 3X.
Relationship: contrasting
Domain: Hardware
Sentence 1: Static vs. dynamic data.ow: in ASH, at most one instance of an operation may be executing at any given time, because each op­eration has a single output latch for storing the result.
Sentence 2: a superscalar processor may have multiple instances of any instruc­tion in .ight at once, because the register renaming mechanism ef­fectively provides a different storage element for each instance of an in-.ight instruction.
Relationship: contrasting
Domain: Hardware
Sentence 1: Gi 3.4 Global Constraint Relaxation Based on the above, our problem reduces to visiting the vertices at the intersection of a global constraint hyperplane with the local constraint hypercube.
Sentence 2: the number of these vertices may Initial global constraint hyperplane  b constraint Figure 2: Before theraise,a,b,and c are left out of G and KnHG includes .ve vertices.
Relationship: contrasting
Domain: Hardware
Sentence 1: [1] studied the impact of thermal stress on mobilities, and performed static timing analysis considering stress e.ect.
Sentence 2: tem­perature also a.ects the gate delay by changing the mobility Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: contrasting
Domain: Hardware
Sentence 1: To offset this, one could increase the number of entries in the first level as in configuration (ii) to ensure the work- ing set is captured by the first level.
Sentence 2: the results presented in Figure 6 show that while performance is opti- 193 3SO0 36oo ............................................................................................................................. 3400 --3200 i thus improving the iTLB energy savings with our proaches, and detailed results can be found in [19].
Relationship: contrasting
Domain: Hardware
Sentence 1: Much of the literature in this area [3] [6] is based entirely on the use of one-dimensional models that account for stress components only along the longitudinal direction (i.e., along the channel direction).
Sentence 2: .nite element simulations in [1], [2] show that STI stress in the transverse direction, perpendicular to the channel direction, also impacts the circuit performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: These operations can be implemented with simpler, faster circuits, and consume less power than an equivalent FP circuit.
Sentence 2: addition and subtraction are more complicated in LNS, and commonly implemented using the trascendental functions sb(z)and db(z), de.ned as: logb(1 + Z)= logb(1 + bz)= sb(z), z<0 (8) logb(1 -Z)=logb(1 -bz)= db(z), z<0.
Relationship: contrasting
Domain: Hardware
Sentence 1: The Internet Underwater: An IP-compatible Protocol Stack for Commercial Undersea Modems Yifan Sun Tommaso Melodia Department of Electrical Engineering Department of Electrical Engineering State University of New York at Buffalo State University of New York at Buffalo ysun24@buffalo.edu tmelodia@eng.buffalo.edu Abstract Recent underwater sensor network research has focused on developing physical, medium access control, and network layer protocols to enable high data rate, energy-ef.cient and reliable acoustic communications.
Sentence 2: it is now essen­tial to design and standardize architectures that will enhance the usability and interoperability of underwater networks.
Relationship: contrasting
Domain: Hardware
Sentence 1: Our CDR sensor is composed of a reference ring oscillator (Refer­ence RO) and a stressed ring oscillator (Stressed RO) which is con­ceptually similar to [17] [18].
Sentence 2: the Stressed RO is designed to age at a very high rate by using high threshold voltage (HVT) gates (to expedite aging so that ICs used even for a very short period of time can be identi.ed) while the Reference RO is gated off from the power supply during chip operation, so that it experiences no stress.
Relationship: contrasting
Domain: Hardware
Sentence 1: However, they do not consider and discuss the suitability of the gates positions, since the optimal gates positions may have already been occupied by other cells or it will incur a lot of overlaps.
Sentence 2: todeal with thisproblem, wehaveto resort toEngineering ChangeOrder(ECO).ECOis not always e.ective or e.cient since there are a lot of gates, re­moving these overlaps may deteriorate other performances greatly, such as increasing the chip area and the signal net wirelength, and thus increasing the power inversely.
Relationship: contrasting
Domain: Hardware
Sentence 1: The CR used in ISC has the same capacity advantages that we discussed for read-only sharing in Section 3.1 It may seem that private caches can avoid coherence misses in read-write sharing by using an update protocol, making the com­munication state unnecessary.
Sentence 2: unlike ISC in CMP-NuRAPID, an update protocol requires the updates to go through the bus for copying the data to the reader s caches, incurring an overhead on every write.
Relationship: contrasting
Domain: Hardware
Sentence 1: With a high-frequency EWOD chip, the comple­tion time of frequency-sensitive operations can be e.ectively decreased while the completion time of other frequency­insensitive operations can also be partially decreased [13].
Sentence 2: for a high-frequency pin-constrained EWOD chip, although the number of control pins can be e.ectively re­duced by broadcast addressing technique, reliability of the chip degrades if the signals are shared arbitrarily.
Relationship: contrasting
Domain: Hardware
Sentence 1: TR A N S M I S S I V I T Y A N D RE FL E C T I V I T Y F O R T H E 1 -D CA S C A D E O F MR R FI LT E R S  The derivation of transmissivity and re.ectivity for the cascade of N identical MRRs is not a trivial task because of the involvement of N-times multiplication of transfer-matrix of a single MRR as given in Theorem 4.
Sentence 2: if the determinant of a resonator matrix [m] is 1 (which is the case in practice [14]), a matrix can be written in such a form that .M.
Relationship: contrasting
Domain: Hardware
Sentence 1: Our initial evaluation of these results indicates that the existing policy to maximize use of our local cluster is a good choice at this time.
Sentence 2: we anticipate an increase in users requiring large numbers of cores as they scale up jobs that, for instance, utilize compute intensive programs such as MIT Electromagnetic Equation Propagation (MEEP), abinit, and Large-Scale Atomic/Molecular Massively Parallel Simulator (LAMMPS).
Relationship: contrasting
Domain: Hardware
Sentence 1: Given a layout, let us consider the change of D after routing through an edge e.We considertwo casesfor routing e: If ..H > 0, then as shown by the argument and example afterTheorem2, D couldincreaseby alarge amountdueto thelargecardinalityofsetQ1,so weelaborate costfunctions to avoidusing edge e onthe routingpath.
Sentence 2: if ..H =0, then as revealed by Theorem 2, .G =-b.Md , i.e., the largest possible reduction in G is b.Md .
Relationship: contrasting
Domain: Hardware
Sentence 1: Traditionally all cells used in an SRAM block are identical (i.e., the transistors with the same name in two different cells have the same width and threshold voltage) which results in identical leakage characteristic for all cells.
Sentence 2: as we shall demonstrate later, by usingnon-identical cells, yet with the same layout footprint, one can realize more power efficient designs.
Relationship: contrasting
Domain: Hardware
Sentence 1: These include Lord's ctool [16], Crew's ASTLOG [9], Shigeru Chiba's Open C++ [5, 6], and Sri- vastava and Eustace's ATOM [20] object-code modifica- tion system.
Sentence 2: it appears that the first three would have required extensive retooling to support the analysis we needed.
Relationship: contrasting
Domain: Hardware
Sentence 1: On the other hand, inductivereasoning may seem out of place here, since typically an inductive argument only ensures that the truth of its premises make it likely or probable that its conclu­sion is also true.
Sentence 2: one observes that humans often employ a combination of inductive and deductive reasoning while perform­ingveri.cation or synthesis.Forexample, while provingatheorem, one often starts by working out examples and trying to .nd a pat­tern in the properties satis.ed by those examples.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is a reduced number of measurements compared to measuring with each possible application since the number of scl settings is bounded while the number of applications in the hosting platform can grow unbounded.
Sentence 2: the number of measurements as described above is still exponential in n since all possible scl set­tings are to be covered for each of the (n- 1) scl instances, which is (smax × wmax )(n-1) number of measurements.
Relationship: contrasting
Domain: Hardware
Sentence 1: The discovery of the memristor presents a promising hardware realization of neuromorphic systems with incredible power ef.ciency, allowing ef.ciently executing the analog matrix-vector multiplication on the memristor crossbar architecture.
Sentence 2: during computations, the memristor will slowly drift from its initial pro­grammed state, leading to a gradual decline of the computation precision of memristor crossbar-based computing engine (MCE).
Relationship: contrasting
Domain: Hardware
Sentence 1: Ingeneral, wire sizing and wire spacing are weaker optimization knobsand their effect at the system-level can be ignored.
Sentence 2: we optimize only the number and size of repeaters during interconnect optimization.we support the use of double-width and double-spacingdesign styles which the system designer can invoke to optimize in­terconnect area, delay, noise, and power.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the predicted computation error is less than the maximum tolerable computation error (dpredict < sup d), the calibration mechanism will assume that there s no need for calibration.
Sentence 2: (Line 35 ~ 37 in Algorithm 1) once the predicted computation error is greater than the maximum tolerable computation error (dpredict = sup d), the calibration mechanism will assume that it s necessary to calibrate the MCE before the next time of I&#38;B operation and start to predict the best calibration time by solving the equation sup d = f(T , d).
Relationship: contrasting
Domain: Hardware
Sentence 1: In our framework, we can thus construct complex com­posite analyses with a few lines of programming.
Sentence 2: instance PROVER CL (s) ZCHAFF (s) c1355 0.3 2.4 c1908 bug 0.0 3.2 c1908 0.0 3.5 c2670 bug 0.2 0.0 c2670 0.1 1.8 c3540 bug 1.0 0.0 c3540 1.0 51.6 c432 0.0 0.1 c499 0.1 4.5 c5315 bug 1.7 1.1 c5315 0.8 46.4 c6288 4.2 [>60 min] c7552 bug 2.2 0.4 c7552 2.2 84.5 c880 0.1 1.4 Table 1: ISCAS 85 benchmark results when we are experimenting with di.erent compositions (for example, when developing default analyses), it is desirable to avoid writing code and recompiling altogether.
Relationship: contrasting
Domain: Hardware
Sentence 1: It is observed that the number of the LSAs does not oscillate and remains constant.
Sentence 2: if according to an another implementation, it is preferred to accept the newly arrived LSA and discard the existing one (in our model in Figure 5, it is enough to change the fourteenth row of RecentFunction to be else zAA[p1] ), the Age Increment Acceleration vulnerability can be exploited.
Relationship: contrasting
Domain: Hardware
Sentence 1: The dedicated counter required by this traditional approach can be maintained if one of the clients is known and guaranteed to be online all the time, or if at each moment at least a majority of the client s devices are online and reachable by any client device who needs access to the counter value.
Sentence 2: in the general case where the client s different devices may be of.ine at any possible time, it is impossible for the client s devices to reliably and securely maintain and agree on the current value of the dedicated counter.
Relationship: contrasting
Domain: Hardware
Sentence 1: Interestingly, as nanomotes are expected to operate in the terahertz band [3], the absorption coe.cient and the packet error rate (PER) at the receiver are also heavily in.uenced by the molecular composition of the reactor.
Sentence 2: unlike a home or an o.ce environment, the chemical composition of the reactor varies rapidly due to the chain reactions consuming certain molecules and producing others.
Relationship: contrasting
Domain: Hardware
Sentence 1: Baseline Core-Based Parallel Issue Host-Centric 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 These results can be non-intuitive since the Host-Centric policy, essentially, requests the host and the target blocks sequentially, differently from the other two policies.
Sentence 2: it is important to note that the RDB configuration plays a key role in these results, especially for the Host-Centric policy.
Relationship: contrasting
Domain: Hardware
Sentence 1: {0, 1}|Kf | which have not been discarded by the DFA for each fault point f. Currently, determining the cipher dependent value of |xf | is still an open problem [3].
Sentence 2: coherently with the observation in Sec­tion 2.1, i.e., willing to provide conservative estimates for the DFA ef.ciency, it is possible to assume |xf |=1 for all f.F chosen by the adversary.
Relationship: contrasting
Domain: Hardware
Sentence 1: CONCLUDING REMARKS In this paper, we have made the case that repeaters, which are already a problem at the full-chip level, will become critical at the synthesizable block level also.
Sentence 2: since blocks actually implement the logic (unlike the full-chip level that focuses primarily on block assembly and the handling of global nets), the exploding repeater count at the block level has numerous algorithmic implications for post-RTL design.
Relationship: contrasting
Domain: Hardware
Sentence 1: Our preliminary experiments on determining build­ing orientations using extracted straight-line perimeters of build­ings on Google Maps map views achieved 0.1. accuracy in the orientations of the detected lines.
Sentence 2: we found detecting straight lines became much more dif.cult on satellite views,pri­marily due to the existence of cars, trees, and road marks on the map.
Relationship: contrasting
Domain: Hardware
Sentence 1: Delay between fetching a new bu.er for the DMA to .ll was mini­mized by prefetching an additional spare bu.er and making it available at the instant it was requested.
Sentence 2: the MSP430 DMA causes truncation of the 12 bits ADC data  Figure 9: System Architecture of the End-to-End Acoustic Ranging System.
Relationship: contrasting
Domain: Hardware
Sentence 1: In particular, for each upstream down­stream routers pair, the NBTI degradation is evaluated in the downstream router by means of sensors, since it physi­cally hosts the VC bu.ers.
Sentence 2: the selection of the downstream router VCs that can be recovered is in charge to the upstream one, since it has all the required traf­.c information and performs the VA stage for the VCs in the downstream router.
Relationship: contrasting
Domain: Hardware
Sentence 1: Future research includes studying the impact of the new partitioner within the framework of top-down, partitioning­based, timing driven placement.
Sentence 2: note that after a length-l path has been placed, its total hopcount is basically equal to l. by reducing the hopcount at the upper levels of the partitioning hierarchy, we may be able to reduce the number of long edges in the placement of the timing path.7 We also seek e.cient ways of biasing the partitioning result for d(k), k>2.
Relationship: contrasting
Domain: Hardware
Sentence 1: Serge Goossens CoWare, Inc. Interleuvenlaan 15A B-3001 Leuven, Belgium http://www.CoWare.com Serge.Goossens@CoWare.com programming model, high .exibility and IP availability, this con­cept is clearly advantageous for today s small and medium scale embedded systems, where a small number of blocks exchange mod­erate amount of data.
Sentence 2: shared busses are not eligible for high throughput requirements and chip-wide interconnect, because of the limited scalability with respect to performance, number of connected blocks and range of coverage as well as limited support for QoS requirements.
Relationship: contrasting
Domain: Hardware
Sentence 1: For exam­ple, the STG in Figure 4(a) can be transformed as shown in Figure 4(b) by output exposure and removal of redundant places p2 and p4.
Sentence 2: if the place p3 is eliminated as shown in Figure 4(c), then the tracker cannot distinguish between the output being not yet set and the output being already reset.
Relationship: contrasting
Domain: Hardware
Sentence 1: Due to severe W2W variation, the baseline yield in 3D chips is significantly low.When adopting naïve way-reduction schemes (nw-sp, nw-wp, and nw-bp), yield is improved compared to the baseline schemes by36.7~41.3%.
Sentence 2: our proposed scheme shows still higher yield than the naïve way-reduction schemes by 17.4~22.0%.
Relationship: contrasting
Domain: Hardware
Sentence 1: Hence, for obtaining the same performance improvement as TPGR, we need to perform multiple iterations of P&#38;R, which can be more costly in terms of running time than TPGR and there is no guarantee that this iterative process converges at the end.
Sentence 2: the TPGR flow is a one-shot optimization process based on a stable and rather efficient optimization method.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this readback-again strategy, the user memory contents in the frame written back is always updated because of the second readback period, and system-level user  Stall operations are not stalled for memory writes to error-free columns that are read back for configuration error detection.
Sentence 2: this readback-again approach still creates an unnecessary overhead by stalling the system-level user operations for the second readback of a faulty frame when the user memory contents in this frame are not updated since the first readback.
Relationship: contrasting
Domain: Hardware
Sentence 1: Reverse body biasing (RBB) is one of the most widely used methods to reduce subthreshold leakage, which has already been introduced by [1].
Sentence 2: the increasing RBB increases drain-induced barrier lowering (DIBL) and substrate doping Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: contrasting
Domain: Hardware
Sentence 1: If a region is located inside a bank, then our current side-channel attack model cannot identify the exact map­ping from a physical address to a memory line.
Sentence 2: the side-channel attack performed in Step 1 can still reveal all phys­ 2In the case of a system using a closed row policy, the memory linesize can be as small as the last-level cache line size.
Relationship: contrasting
Domain: Hardware
Sentence 1: Further, since our proposed method applies the net bounding-box model to evaluate the routing congestion, instead of Steiner tree decomposition or LZ-shaped global routing, our algorithm is much more e.cient in .nding placement solutions without any routing over.ows (about a 6.28X speedup over ROOSTER on average).
Sentence 2: even if the NTHU router can .nd a legal global routing solution very easily in shorter time on the placement solutions of ROOSTER than ours (excluding bigblue1 ), ROOSTER incurs a large wirelength penalty due to its tendency to spread the modules too much for routability optimization, which results in a very sparse net distribution.
Relationship: contrasting
Domain: Hardware
Sentence 1: For instance, the circuit shown in Figure 2 is a result of moving F F2 forward by a de­lay d. The corresponding path delay distribution, shown in 2, is sub-optimal in terms of its longest path and incurs timing errors if operated at 4d.
Sentence 2: since logic cone X has rela­tively few paths, the path wall is pushed in to a delay of 3d (due to logic cones Y and Z).
Relationship: contrasting
Domain: Hardware
Sentence 1: Figure 17 shows that if running on FIOS, the value of I/O throughput of these virtual machine decreases only about 6%, from 230MB/sec to 216MB/sec, while the number of normal VM increases from 1 to 5.
Sentence 2: if running on Xen, the value of I/O throughput suffers a significant decrease about 75%, from 171MB/sec to 43MB/sec.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since this is a combinatorially expensive search space, memory compilers interpolate across a large space of depth and width com­binations and use lookup table techniques to converge to the best con.gurations.
Sentence 2: even such approaches cannot handle both dimensions simultaneously and it common practice to identify the best depths .rst since the range of memory depth instances is con­siderably larger (bits.Mbits) in comparison to the range of mem­ory width instances (1.2048).
Relationship: contrasting
Domain: Hardware
Sentence 1: Such routines produce all simula­tor elements by reading from the database the VHDL Com­ponent to be Testedand the Error List.In the current implementation some modules are written in VHDL and other modules in C to improve the simulation perfor­mances.
Sentence 2: if the used VHDL simulation environ­ment does not allow such a mixed simulation, C modules can be rewritten in VHDL.
Relationship: contrasting