sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: On one hand, the effect of device scaling is covered in the theoretical deduction by the specific dependence of the variance from the filament area Afil.
Sentence 2: (23), (30), (39), and  (19) show that the obtained variance of the conductance G depends on parameters which are not ECM device parameters but parameters of the regulating device: VDD, VB, VThp, and k. Hence, as initially stated, the variance is the consequence of a joint interaction between RS device and the load circuit.
Relationship: contrasting
Domain: Hardware
Sentence 1: IMPROVING COVERAGE OF MULTI-CYCLE FAULTS Thus far, we have assumed that transient faults are of very short duration, so that simple time redundancy is as effective as space redundancy for fault detection.
Sentence 2: some faults may persist for multiple cycles, such that two redundant operations could pass through the same hardware during the duration of the fault and experience the same error.
Relationship: contrasting
Domain: Hardware
Sentence 1: + + .L .1L .R .2R Figure 11: The change in .L and .R with l w + t The physical explanation of this trend for a constant aspect ratio isthat increasing the length, width, and thickness of the interconnect such that l/(w+t) is kept constant decreases the frequency point .R since the skin depth becomes comparable to the wire width at lowerfrequencies.
Sentence 2: this scaling in the wire dimensions decreases the resistance and at the same time increases the inductive impedance.
Relationship: contrasting
Domain: Hardware
Sentence 1: Our observations that certain regions can execute and commit out­of-order, and that con.ict checks and region execution in different processors can allproceedinparallelisunique.Itmayhelpimprove the ef.ciency and complexity ofBulk system as well.
Sentence 2: sC can be guaranteed at the language level even on hardware that supports a weaker consistency model using static analysis toinsertfences[24,39,41].computing a minimal set of fences for a program is NP-complete [25].
Relationship: contrasting
Domain: Hardware
Sentence 1: Figure2illustratestheuseofseparateShiftQseachre­ceivingastreamofoperandsfromafunctionunitoutput.
Sentence 2: eachEVRinaloopschedulehasanassociatedfunctionunit onwhichitiscomputedandtheEVR'svaluesarestored withintheShiftQassociatedwiththatunit.Bypartition­ingregisterstoragetooneShiftQperfunctionunit,thisap­proachdecreasesthemaximumnumberofinput(one)and outputportstoeachShiftQ1 .eachShiftQisstill allowedtosupportmorethanoneEVR.Thisoftenallowsa singleregisterelementwithinaShiftQtosupportmultiple 1Alternatepartitioningsarepossible[3]buttheypreclude subsequentcustomizationasdiscussedlater.
Relationship: contrasting
Domain: Hardware
Sentence 1: Main di.erences with our work were that they studied four di.erent power manage­ment policies under DVFS and centered their study on the relationship between CPU utilization and power consum­ption.
Sentence 2: they also present interesting results about disk consumption that match partially our results, showing a .at consumption in reading operations and variations in the writing ones that they attribute to the size of the .les being written.
Relationship: contrasting
Domain: Hardware
Sentence 1: The .rst approach, used in [17, 23], consists in having a one-cell distance between any two adjacent modules, which is suf­.cient for isolating the functional regions on which operations are executing.
Sentence 2: if routing is not considered at the same time with placement, the resulted solution will require signi.cant modi­.cations for accomodating the necessary routes.
Relationship: contrasting
Domain: Hardware
Sentence 1: The 4/2 encoded bus should ideally result in energy savings at lower switching activities than the 8/4 encoded bus since the probability of the energy saving cycles (more than 2 bits switching) is higher than the probability of the energy saving cycles for the 8/4 encoded bus (more than 4 bits switching).
Sentence 2: the energy gains are marginal due to the fact that the standard bus energy can be reduced further under the increased area penalty (25%) of the 4/2 encoder.
Relationship: contrasting
Domain: Hardware
Sentence 1: The resynthesis is performed by mapping logic blocks extracted from a circuit against a library set of logic blocks (e.g., hard-wired LUTs) and replacing them with a functionally equivalent logic block if area can be reduced.
Sentence 2: o1 O1 O1O1  x1 x2 x3 x1 x2 x3 x1x2x3 x1x2 x3 (a) (b) (c) (d) Figure 1: Motivating example for resynthesis con­sidering retiming and multi-output logic blocks existing techniques perform resynthesis only within the combinational portion of a circuit, and only consider single­output Boolean functions [15, 16].
Relationship: contrasting
Domain: Hardware
Sentence 1: Figure7(d)depictstheretimeddemultiplexeddata.The diferencebetweenthewaveformsresultsfromsystematic diferencesbetweenthebondwiresandtracesonthetest board.Thecircuitalsogeneratesafull-rateoutput.Using thisoutput,theBERofthesystemcanbemeasured.With arandomsequenceof27 ;1,theBERissmallerthat10;12 .
Sentence 2: arandomsequenceof223 ;1resultsinaBERof 1:28x10;6 .
Relationship: contrasting
Domain: Hardware
Sentence 1: Theotherategory,simulation­basedATPGforverifa­tion,isinvestigatedinthiswork.Unlikethedeterminis­tiounterpartwhihtriestoexhausttheompletesearh spae,simulation­basedATPGdoesa"randomwalk"inthe statespae,hopingtohitthe"target"inalimitednumber ofsteps.Thewalkisguidedbysomeheuristis,thusit isnotanentirelyrandomtraversal.Ateahstep,anum­beroftrialstepsaremadeandevaluatedbyaostfun­tionwhihmeasureshowfarthestateoftheiruitisfrom thetargetstate.Theostfuntionisomputedthroughei­therlogisimulationorfaultsimulation.Thestepwiththe leastostispikedasthenextstepandtheproessisre­peateduntilthetargetisreahedorertainlimitisexeeded.
Sentence 2: suhATPGshavetheadvantageofsalingtolargedesigns beauseofitssimulation­basednature,whereonlyforward simulationisusedandbaktraksneverour.the majordrawbaksare:(1)itannotproveorretness,due tosimulation­basedATPG'sinabilitytoidentifyuntestable faults;(2)agoodostfuntionisneededtoguidethesearh, otherwisealotoftimewillbewastedontraversingtheuse­lessstates.Althoughthesimulation­basedmethodsannot proveorretnessinverifation,itftsquitewelltheobje­tiveof"debugging".Inpratie,foralargeindustrydesign, theverifationobjetiveisusuallyonernedlesswithpro­vidingformalproofsoforretnessthanfndingbugs.In otherwords,designersaremoreonernedwithfndinga ounterexampletofalsifythelargedesign,whihisgener­allyeasierthanprovingifitis100%orret.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is because the underlying cache parameters match exactly with the assumed cache parameters during procedure placement.
Sentence 2: the code layout generated for C may perform badly for other con.gurations, though it is good for con.guration C. For example, for benchmark Ispell, 4k-1-way code layout is better than 4k-2-way code layout for 4k-1-way cache con.guration, but worse than 4k-2-way code layout for 4k-2-way cache con.guration.
Relationship: contrasting
Domain: Hardware
Sentence 1: At the application level, DRAM-aware mapping of application tasks to the processing nodes exploits bank-level parallelism [22] has been proposed, and memory-centric scheduling approach in which statically computed TDMA schedules are made for each core to access the memory system to avoid memory access contention, allowing applications to be veri.ed in isolation [23].
Sentence 2: those were not optimized in terms of area and/or power consumption.
Relationship: contrasting
Domain: Hardware
Sentence 1: This scenario models major con­text switches (or program phase changes) If a context switch is of long duration or there is a major program phase change to code that has never been executed (or has not been executed for a very long time), then the required translated code is not in the code cache.
Sentence 2: the architected ISA code is in main memory, and will need to be (re)translated before it can be executed.
Relationship: contrasting
Domain: Hardware
Sentence 1: While one can envision a scenario where users can address and access underwater nodes from any Internet­connected terminal, including workstations or smartphones, as of today existing underwater acoustic sensor network (UW-ASN) cannot be recon.gured or reprogrammed once the modems have been deployed.
Sentence 2: with sup­port for the TCP/IP protocol stack, applications such as FTP and SSH could be utilized to recon.gure the network.
Relationship: contrasting
Domain: Hardware
Sentence 1: = true indicates no low Vdd buffer is to be placed in upstream, it is overly aggressive to perform PSP by using RL (>RH ).
Sentence 2: it makes PSP more effective (to prune more) by using RL if there is no high Vdd buffer downstream from F. To make the algorithm even faster, we may use a resistance larger than Rmin (i.e.
Relationship: contrasting
Domain: Hardware
Sentence 1: The study reports apparent mappings between the IP addresses in anonymized datasets and the real IP addresses, as inferred by the authors techniques.
Sentence 2: the authors did not approach the data providers regarding this attempt, for fear of creating a con­.ict of interest [11], illustrating the uncertain community culture regarding how to undertake such studies.5 The down-side to the study not including such interactions is that the authors were un­able to compare their results with ground truth and thus, in fact, ended up incorrectly de-anonymizing nearly all of the IP address mappings reported in the paper for our LBNL dataset [2], to the detriment of assessing the underlying scienti.c issues.
Relationship: contrasting
Domain: Hardware
Sentence 1: New optimal solutions for reduced TSVs to tran­sistors ratios can be found at the physical design level by altering the floorplan, placement or routing [11] [12] without design changes albeit with some additional performance overhead due to increased wire length.
Sentence 2: as we show in this work, for extremely regular microprocessor blocks like SRAM registers and caches, the number of TSVs and their positions are decided at the architectural level and, unlike ASICs, rarely can be optimized at a layout level.
Relationship: contrasting
Domain: Hardware
Sentence 1: [15] discuss the possibility of having a two-tiered DRAM-based hierarchy where an on-chip dram is used in conjunc- tion with traditional off-chip DDR DIMMs.
Sentence 2: in contrast to convention [24, 47, 20], the on-chip dram is not used as a large LLC, but instead considered a part of the main memory.
Relationship: contrasting
Domain: Hardware
Sentence 1: Secondly, their approach allows the grouping of di.erent dominant cuts, which can result in a signi.cant increase of area, thereby indirectly degrade the timing performance of the optimized solution.
Sentence 2: we propose two di.erent cutting strategies, one that aims to preserve the topological structure of CUO and the other one would allow for other possible topologies.
Relationship: contrasting
Domain: Hardware
Sentence 1: Moreover, since the most-signi.cant bit of the input operands is the sign bit, Booth 2 multipliers reduce the number of partial product rows to Ln 2 J. Truncated Booth multipliers can utilize the same meth­ods discussed in Section 2.
Sentence 2: since truncation can remove the bits from the two s complement conversion, the constant has to be modi.ed.
Relationship: contrasting
Domain: Hardware
Sentence 1: We observe that both CB and HS are not satisfying in many cases sincethey eitheryield tens of thousandsof error candidatesortimeout(andthus, may notpinpointthede­signer to the error location).
Sentence 2: hS does not abort as often as CB.Inparticular, CB tends to timeout on large in­stances sometimes without delivering any candidate.
Relationship: contrasting
Domain: Hardware
Sentence 1: In some ways, this is similar to the cost of a hierarchical scan structure where two LSIBs must be opened in sequence for hidden instrument access.
Sentence 2: for a scan chain of length n (including the one-bit dead end), the cost of a guess with this SLSIB architecture is: Cost of guessLSIB_behind_SLSIB = 15+3n+d (11) deterministically opening the SLSIB repeatedly on each try is not possible because opening the SLSIB provides no information to the attacker.
Relationship: contrasting
Domain: Hardware
Sentence 1: 0 xL (a) E(V/m) (b) 3.37E+8 Gate B  Gate A 3.03E+8 2.35E+8 Source 2.01E+8 1.68E+8 1.34E+8 1.01E+8 6.73E+7 3.37E+7 0.00E+2  3.2 Solving Euler-Bernoulli s Equation in the x-Domain Equation (3(a)) is a non-linear fourth-order differential equation, which implies that there is no systematic way to solve it analytically.
Sentence 2: it is possible to find a closed-form answer, if the right-hand side of the differential equation is linearized.
Relationship: contrasting
Domain: Hardware
Sentence 1: There are other scenarios, such as that shown in 5(b), where, even in a write-back cache, dirty lines are usually only written to once before they are subsequently evicted.
Sentence 2: on average across all of our workloads, we observed that a write-through DRAM cache results in ~3.7× greater write traf.c to main memory than a write-back policy (although the amount varies signi.cantly based on the exact workloads).
Relationship: contrasting
Domain: Hardware
Sentence 1: Jmax(T) compared to Jmax (Tref = 25°C) [ 1] interconnects, it is the wire width that exerts a direct influence on current density: The wider the wire, the smaller the current density and the greater the resistance to electromigration.
Sentence 2: there is an exception to this accepted wisdom: If you reduce wire width to below the average grain size of the wire material, the resistance to electromigration increases, despite an increase in current density.
Relationship: contrasting
Domain: Hardware
Sentence 1: Antifuse-based FPGAs are one-time pro­grammable and do not support recon.guration which makes them out of scope in recon.guration systems.
Sentence 2: more recent emerging NVM technologies such as RRAM and memresistor are not mature enough to be considered as a replacement for SRAM cells in the near future and are not discussed in this work.
Relationship: contrasting
Domain: Hardware
Sentence 1: It shows that speech recognition has reached an acceptable level to be integrated in querying systems.
Sentence 2: one of the weaknesses of current sys­tems is that multimodality is still very limited: Speech recognition makes errors in broad domains and realistic en­vironments; unnatural-sounding speech synthesis, with very limited control of expression and emotion; dialogue systems operate in limited, simple domains; very few systems make use of multimodal, heterogeneous inputs.
Relationship: contrasting
Domain: Hardware
Sentence 1: In reality, the distribution for x1 is located on an inter­val x1 = [x1, x1], i.e., on a set with in.nitely many points.
Sentence 2: with an arbitrary large value N (and thus, for an arbitrarily small discretization error d = (x1 - x1)/N ), we can assume that all the distributions are located on a .nite grid of values def def def v0 = x1, v1 = x1 + d, v2 = x1 + 2d, .
Relationship: contrasting
Domain: Hardware
Sentence 1: While static logic cells generally (excluding the XOR function) require 2n transistors (n representing fan-in), and conventional dynamic logic cells n+2 transistors, the new cells only require n+1 transistors In this study, we did not compare the new standard cell performance to that of CMOS standard cells because any quantitative results would depend to a large extent on the quality of the device model used.
Sentence 2: we highlighted the improvement that these new structures, exploiting the back­gate of the DG-CNTFET, could provide, to furnish a dynamic logic with faster gates and fewer transistors.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4.2 RRR-based interconnect parameter reduction A full account of global and local variations in a large multi-layer interconnect network can lead to the considera­tion of a large set of geometrical variables, i.e., np is large.
Sentence 2: if we are only interested in analyzing the circuit performances at the output nodes, the e.ective parameter dimension of a given network may not be very large since the speci.c circuit structure can hide certain parametric varia­tions and may even introduce canceling e.ects between mul­tiple variations.
Relationship: contrasting
Domain: Hardware
Sentence 1: In essence, the methodsin[2,3,12]attempttodecrease the variation ofCMPonly accordingtotheIPDin atile anditsim­mediate neighbors.
Sentence 2: metrics such astheIPD andtheIPD gradientare onlyindirect measures oftheEPD, andtheir abilityto optimizeCMP variationislikelytobeinferiorto an approach that addressestheEPDvariation moredirectly.
Relationship: contrasting
Domain: Hardware
Sentence 1: Conventional gate sizing formulations either minimize the worst case delay or minimize the power under delay constraints [1, 2, 3, 4, 5, 6, 7].
Sentence 2: gate sizing is never considered to help the Vt-swapping algorithm to maximize the power reduction over­all, although Vt-swapping is known to be much more effective on * This work is supported in part by NSF, SRC, and IBM Faculty Award.
Relationship: contrasting
Domain: Hardware
Sentence 1: On one hand, dummy patterns may either connect to power/ground nets (tied .lls) or left .oating (.oating .lls), both of which may induce coupling capacitances, a.ect in­terconnect delay, and lead to timing violations [13].
Sentence 2: those extra dummy patterns increase the mask data size, lengthening the time of mask-making processes and complicating the following time-consuming reticle en­hancement techniques, such as OPC (optical proximity cor­rection).
Relationship: contrasting
Domain: Hardware
Sentence 1: VT Balancing and Device Sizing Towards High Yield of Sub-threshold Static Logic Gates Yu Pu1,2,3 José Pineda de Gyvez 1,2 Henk Corporaal1 Yajun Ha3 Technische Universiteit Eindhoven1 NXP Research Eindhoven2 National University of Singapore3 {y.pu, h.corporaal}@tue.nl jose.pineda.de.gyvez@philips.com elehy@nus.edu.sg ABSTRACT Operating digital circuits in the sub-threshold region is potentially a solution for ultra low-power applications.
Sentence 2: simply reducing supply voltage well below threshold voltage causes functional yield degradation.
Relationship: contrasting
Domain: Hardware
Sentence 1: Hence, the power modeling that follows focuses only on FFMs (the effect of POR will be discussed in Section 2.5).
Sentence 2: for a (n, k, t) BCH decoder, more power will be consumed by the Chien search correcting t errors than the same circuit correcting only one error as the former requires t-1 more FFMs than the latter.
Relationship: contrasting
Domain: Hardware
Sentence 1: Perception of multiple simultaneous sources is a complex prob­lem which is actively studied in the community of auditory scene analysis (ASA) [Bregman 1990; Ellis 1992] where perceptual orga­nization of the auditory world follows the principles of Gestalt psy­chology.
Sentence 2: computational ASA usually attempts to solve the inverse and more complex problem of segregating a complex sound mixture into discrete, perceptually relevant auditory events.
Relationship: contrasting
Domain: Hardware
Sentence 1: This technique has been dubbed Dynamic Voltage and Frequency Scaling (DVFS).
Sentence 2: 978-3-9815370-2-4/DATE14/ c@2014 EDAA with every new technology node, the number of faults (transient, intermittent and permanent) per device is on the rise [3], and energy-aware scheduling techniques do not address fault-tolerance, that needs to be speci.cally dealt with.
Relationship: contrasting
Domain: Hardware
Sentence 1: FIR 87% 17.35 1.45 93% 22.29 1.94 JAC 77% 5.73 3.67 89% 10.25 5.93 PAT 92% 34.85 1.51 96% 46.7 2.35 SOBEL 75% 3.96 2.25 75% 3.96 3.96 MM 76% 13.37 1.86 85% 16.5 2.21 Table 2.
Sentence 2: percentage of reduction in memory cycles and Speedups custom data layout can exploit memory parallelism no matter how two loops are unrolled, thereby requiring much less unroll factors.
Relationship: contrasting
Domain: Hardware
Sentence 1: To overwhelm complication, we de-9: curS = newS ; curC = newC M. is that some mode-to-mode switchings consume not only the 4: else  M The other problem 3: newS = NeighborT (curS, di.erence of two stored energies but also an extra energy de-5: newS = NeighborD(curS, .ned that M never include a element which consume extra energy with other elements.
Sentence 2: there are many sets of depths which satisfy two conditions, Pareto-optimality and extra energy free.
Relationship: contrasting
Domain: Hardware
Sentence 1: To overcome the long runtime problem of ILP solver, for double patterning, partitioning/matching based methods have been proposed [6, 7]; while for triple patterning, some speedup tech­niques, e.g., semide.nite programming (SDP) [4,10], and heuris­tic coloring assignment [8, 9] have been proposed.
Sentence 2: how to e.ectively solve the quadruple patterning, or even gen­eral multiple patterning problems, is still an open question.
Relationship: contrasting
Domain: Hardware
Sentence 1: All of some versus some of all Processor caches store only a small subset of frequently used data in the cache (all of some).
Sentence 2: the   N counters of size M in DRAM Packets N counters of size m in SRAM Figure 1: Statistics counter architecture : N counters of size M are maintained in DRAM and N counters of size m<M are maintained in SRAM.
Relationship: contrasting
Domain: Hardware
Sentence 1: The characteristics of this methodology make the results particular for the prob­lem under study.
Sentence 2: the nature of the application (processors for embedded control) justi.es this approach: the controller can be de.ned as a hardware description lan­guage (HDL) core with some parameters, such as the word length, and these can be found for each particular SoC to be developed.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4.1 Modeling Repeaters with Repulsive Forces Of the four spreading force requirements derived in [5], the first two (viz., dependence only on the cell co-ordinates, and direction from high to lower density regions) serve solely to capture the semantics of overlap removal among cells.
Sentence 2: the third and fourth requirements (viz., loop-free force field, and zero forces at infinity) contribute directly towards the existence of a unique and easily computable solution.
Relationship: contrasting
Domain: Hardware
Sentence 1: Higher memory order codes can achieve superior coding performance without requiring precious additional channel bandwidth.
Sentence 2: to counteract the exponential dependence of Viterbi decoder complexity on Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: contrasting
Domain: Hardware
Sentence 1: This will lead to a higher one-way delay of about 1200 ms = t = 1520 ms if we use the same AMR encoding.
Sentence 2: switching back to an AMR 4.75 codec, a smaller number of voice samples per IP packet be­comes possible again (1 0= n = 17) and the minimal E2E delay can be reduced to 980 ms.
Relationship: contrasting
Domain: Hardware
Sentence 1: The savings of Equalizer for compute kernels is 5% as reducing memory frequency cannot provide very high savings.
Sentence 2: memory kernels save 11% energy bp-2 bfs-2 histo-1 kmn mmer prtcl-1 spmv GMEAN Figure 10: Comparison of Equalizer with DynCTA and CCWS by lowering SM frequency.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since bgth Su,v and Stu,~ induce a clique in GB,4, at least 8 colors are needed to satisfy the co-channel reuse constraint.
Sentence 2: as proved in the following, 8 colors are not enough to color the set L~,~ of vertices depicted in Figure 6, which consists of S~,~ along with all the vertices of B at horizontal distance exactly 1 from the vertices on the border of S~,..
Relationship: contrasting