sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Under the Neyman Pearson (NP) framework, we de.ne that a WSN channel a is always preferred over a WSN channel b if .aa =ab,ßa = ßb, where aa and ab represent the probability of false alarm in each WSN channel and ßa and ßb represent the probability of detection in each WSN channel.
Sentence 2: a WSN channel a is always preferred over a WSN channel b if the receiver operating characteris­tic (ROC) curve of WSN channel a is always not below the ROC curve of WSN channel b. Martinez [9] and Warren et al.
Relationship: entailment
Domain: Hardware
Sentence 1: masking them) from the graph and deleting from the edge count until the upper bound on the worst-case slack and the lower bound on the best-case slack meet.
Sentence 2: if the least critical edge has worst-case slack 45 and best-case slack 80 and the number of paths in G with that edge removed contains more than k paths with best-ca se slack less than or equal to 45 then the edge is safe to delete (mask).
Relationship: entailment
Domain: Hardware
Sentence 1: This weight function re.ects more accurately the ben­e.t of inserting an mfence at the location.
Sentence 2: we are trying to insert as few mfences as possible to enforce the load-store and store-load delays, while at the same time enforcing as many load-load and store-store delays as pos- The global optimization optimizes fences inserted to en­ force inter-block delays.
Relationship: entailment
Domain: Hardware
Sentence 1: The use of a LFSR entails the advantage that, once the initial states of the flip-flops have been set, the finite input sequence is univocally determined, thus the tail of its auto-correlation function is always the same and the input-output cross­correlation function depends only on the current tuning configuration of the filter.
Sentence 2: the tails of the auto-correlation function of the input sequence do not depend on the particular realization of a stationary and ergodic process x(t).
Relationship: entailment
Domain: Hardware
Sentence 1: Thesignalintegrity problems aremuchmorecomplicated in the inductance-dominant RLC lines than in capacitance­dominant RLC lines since the system step response may be non-monotonic oscillating-waveshape contaminated with spurious noise spikes.
Sentence 2: not only may the response sig­nals of the inductance-dominant lines oscillate until they set­tle down at the .nal value but they may also contain many spurious glitches.
Relationship: entailment
Domain: Hardware
Sentence 1: A speci.ca­tion may be realizable at the beginning of simulation, but when a fault occurs (that is, the module makes a wrong move), the speci.cation may become unrealizable but not unsatis.able.
Sentence 2: the property has not yet been refuted, but it is possible to drive the module to a state where the property is guaranteed to be refuted.
Relationship: entailment
Domain: Hardware
Sentence 1: tually, this means CPL and DPL can be thought of instead as code privilege label and data privilege label, allowing the creation of many labeled code/data contexts.
Sentence 2: the context identi.er of the code (CPL) determines which data it is allowed to access, and the context identi.er of the data (DPL) determines which code is allowed to access it.
Relationship: entailment
Domain: Hardware
Sentence 1: The results from both .oor­planners are shown in Table 1 under column [27] and ours re­spectively.
Sentence 2: column n lists the number of modules in each test .le, column t(sec) lists the running time in seconds, col­umn DS% lists the percentage of deadspace, and column w/h lists the aspect ratio of the .oorplan solution.
Relationship: entailment
Domain: Hardware
Sentence 1: Hsiao code [12] is often cited as the most cost-e.ective SEC-DED scheme due to the min­imum number of XOR gates it uses to generate its check bits.
Sentence 2: a Hsiao code, henceforth also referred to as code, needs an n bit codeword to protect m bits of data, where n>m, the number of check bits k=n-m, and m= 2k-1-k. A Hsiao code can be uniquely de.ned by its check (or generator) matrix.
Relationship: entailment
Domain: Hardware
Sentence 1: However, in most existing fault-tolerant resynthesis algo­rithms, a logic block to be restructured is expressed by the completed speci.ed function (CSF) derived from the LUTs inside this block.
Sentence 2: the Boolean .exibility due to the rest of the network outside the logic block is not taken into consideration, and therefore the opportunity of resynthesis is limited.
Relationship: entailment
Domain: Hardware
Sentence 1: From the above, simpli.ed products or sums containing malicious on-set minterms or malicious off-set maxterms cannot be activated during the veri.cation.
Sentence 2: during the tracing process, we can record the activation history of products and sums instead of that of each logic entry, and hence the memory requirement and runtime overhead of our tracer can be dramatically reduced.
Relationship: entailment
Domain: Hardware
Sentence 1: Contrary to timing analysis, the early and late arrival times of glitch noise are not determined by the net s fanin, but by the net s aggressors early and late arrival times.
Sentence 2: [t1E,t1L] 1 [t3E,t3L] 3 tCK 2 [t2E,t2L] [t3E,t3L] = [min(t1E+tD,t2E+tD),max(t1L+tD,t2L+tD)] t3L  tCK -tCYCLE + tHOLD Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: Thus, the un-correlation between two Gaussian random vari­ables V1 and V2 implies their independence.
Sentence 2: v is a Gaussian random variable, the mean and variance of which can be computed from (23) and (24): E(v)=[V0 + tr(V )]/(m - 1) (25) 2tr(V 2)4 T var(v)= + vcoe.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION  With the advance to the multi-core era and replication of processor cores on a single die, the surrounding un-core logic, such as cache, memory controllers, and network interfaces, is growing in importance.
Sentence 2: implementing the necessary data sharing and communication protocols for multi-core processors involves handling a large amount of transient state that is not necessarily visible to the high-level protocol.
Relationship: entailment
Domain: Hardware
Sentence 1: (13)) for µi ,si (µi, si) 7: end for 8: until |a-aold|2+|b-bold|2+||µ-µold||2 2+||s-sold||2 2 < o the mean, EB gives the so-called James-Stein estimator [14] for the mean.
Sentence 2: a nice feature of the James-Stein estimator is that it is superior to the sample mean estimate, in the sense that the expected sum of mean square error of µi s at all populations is smaller than that of the sample mean estimator, i.e.
Relationship: entailment
Domain: Hardware
Sentence 1: [n] be a feasible design for the i-th component and q be the design for the system ob­tained as the union of the qi s. In particular, qi is a 2-dimensional vector point in the xy plane whose .rst coordinate is the x­value (the clock period of the corresponding design) and whose second coordinate is its y-value (its power) We assume there are two combining functions fx,fy : Rn .
Sentence 2: r that specify how q is related to the qi s. x(q)= fx(x(q1),...,x(qn)) and y(q)= fy(y(q1),...,y(qn)).
Relationship: entailment
Domain: Hardware
Sentence 1: Note that the rate of two cycle operations is a TABLE II: Quality con.gurable circuits synthesized for Error Rate with two quality modes Circuit Delay (ns) Area (%) Power (%) P2cycle E nergyacc (%) E nergyapp (%) Error rate (%) KSA 0.2 16.3 14.79 0.009 14.02 22.27 0.7 c880 0.22 13.1 18.03 0.064 12.78 31.9 4.8 c1908 0.25 13.8 22.9 0.0102 22.11 31.31 0.95 c2670 0.22 5.09 15.68 0.0051 15.25 24.51 0.2 c3540 0.36 21.94 19.72 0.008 19.08 23.56 0.65 c7552 0.32 12.79 19.18 0.064 14.01 22.54 4.8 little larger than the actual error rate at the outputs, because not all errors at the substitution points are sensitized at the outputs.
Sentence 2: the clock extension mechanism and the error indicator output bit are conservative.
Relationship: entailment
Domain: Hardware
Sentence 1: The efficiency in memory utilization, together with many other desirable features, makes our solution a very attractive alternative for streaming services to battery-powered small devices.
Sentence 2: the clear difference between our scheme and the existing schemes is that most existing schemes work in the MDCT domain, while ours works in the quantized MDCT (QMDCT) domain or Huffman coded domain.
Relationship: entailment
Domain: Hardware
Sentence 1: Similarly to previous schemes ([19, 20]) the pro­posed methodology uses the remote IPC to implementthe interaction between SW and HW models; how­ever, the use of a real board and the requirement of timed HW-SW co-simulation completely differentiates the methodology proposed in this work.
Sentence 2: our scheme can be viewed as a variant of the solu­tion originally proposed in [20]; the details will be de­scribed in Section 5.
Relationship: entailment
Domain: Hardware
Sentence 1: The results of the analysis on DES, reported in Figure 3b, show that the number of nonlinear dependencies increases briskly in correspondence of the load operations performed from the S-Boxes after a KE YAD D IT I O N has been performed.
Sentence 2: the quick increase in the number of bits depending nonlinearly is to be as­cribed to the combined effect of the bitwise diffusion of DES into its S-boxes, while the large amount of instructions which are not vulner­able at the end of the cipher are to be ascribed to the .nal unkeyed permutation present in the DES design.
Relationship: entailment
Domain: Hardware
Sentence 1: We intend to do further tests with varying gradients as blending zones.
Sentence 2: we are interested in why no signi.cant im­provement can be seen for display bezels, while we did see signif­icant improvements for other related tasks (e.g., a blending zone around a 2D monoscopic text inlay in a 3D stereo scene).
Relationship: entailment
Domain: Hardware
Sentence 1: lectionfor atleasttwo of thefour spawngoodnesspro.les described in Section 3.3.
Sentence 2: the closest spawn policy will make a good choicefor monotonicallydecreas­ing and valleypro.les, whilefurthest spawningislikely to workfor monotonicallyincreasingand valleypro.les.
Relationship: entailment
Domain: Hardware
Sentence 1: inst_out_0[221:0] inst_in_0[209:0]  inst_in_1[209:0] inst_in_2[209:0] inst_in_3[209:0] inst_out_5[221:0]  that can be identified as FICs and employed to provide the scheduler with a partial on-line testing ability.
Sentence 2: as for the internal signal issue_tail[4:0], we verified that it produces always a recurring sequence of patterns that is repeated every 8 clock cycles.
Relationship: entailment
Domain: Hardware
Sentence 1: The contributing components are additive onalogarithmic scale,or multiplicativeona nominal scale.Aneg­ativecomponent meansthatthe componentisa contributorinfavor of the low-end server.
Sentence 2: tCO is always infavor of the low-end server because the TCO for the low-end server is about 12 times as low as for the high-end server.
Relationship: entailment
Domain: Hardware
Sentence 1: Here, we propose embedded STT-MRAM as a unified eNVM solution for replacing eFlash, OTP, retention flip-flop, and even SRAM when needed.
Sentence 2: for battery-powered emerging mobile products with low duty cycles, the STT-MRAM-only memory configuration would be a highly efficient way of maximizing battery life and reducing cost, providing greater system­level benefits than replacing eFlash alone.
Relationship: entailment
Domain: Hardware
Sentence 1: As future work, we plan to populate a library of generators to demonstrate the ef.cacy of BAG.
Sentence 2: three different SC DC-DC regulator instances, targeting different speci.cations, will be fabricated in a commercial CMOS 65nm and we will migrate the full design to CMOS 40nm to explore how to write generators to enable full technology independence.
Relationship: entailment
Domain: Hardware
Sentence 1: It was clear to the second author that continuing transistor bounty could be used to rethink the microarchitecture of the multiprocessor portion of a CMP.
Sentence 2: since the designers of a CMP had complete control of what hardware it contained and how it would function, they could contemplate and implement techniques that could never be practical if they required interactions between distinct chips over which the designers may not have complete control, as was the case in canonical SMPs.
Relationship: entailment
Domain: Hardware
Sentence 1: Figure 2: Phase delay detection/re-alignment and phase delay modulation receiver Figure 3: Aligning DQ using DQS and DQ/DQS misalignment Figure 4: Slew rate with respect to trace capacitance 4.1 Case Study Phase Delay Modulation In this paper, we explore the possibility of fine-grain timing modulation implemented on high speed communication lines.
Sentence 2: we add a delay-based signal to a DDR2 memory interface.
Relationship: entailment
Domain: Hardware
Sentence 1: Given that the completion of an OCPce port request requires all OCPi ports to ac­knowledge (step 5), no upcoming con.icting OCPce port request will be completed, because the blocked OCPi port will not acknowledge its corresponding system intervention.
Sentence 2: if two con.icting OCPce port requests are issued concurrently, the .rst to be turned to intervention Figure 5: hardware for serialization port request and show up on bus will block the second; once the .rst one is completed, the requestor s OCPi port will unblock and the second system intervention port request will be acknowledged, enabling the generation of the second OCPce port response.
Relationship: entailment
Domain: Hardware
Sentence 1: For example, if all optimal circuits are written to a hypothetical 100+TB 5400 RPM hard drive, the average time to extract a random circuit from the drive would be expected to take on the order of 0.01-0.02 seconds (typical access time for 5400 RPM hard drives).
Sentence 2: it would likely take longer to read the answer from a hypothetical hard drive than to compute it with our implementation.
Relationship: entailment
Domain: Hardware
Sentence 1: This paper presents the first method to successfully synthesize compressor trees on LUT-based FPGAs.
Sentence 2: we have found that generalized parallel counters (GPCs) map quite well to LUTs on FPGAs; a heuristic, presented within, constructs a compressor tree from a library of GPCs that can efficiently be implemented on the target FPGA.
Relationship: entailment
Domain: Hardware
Sentence 1: It results in the following astonishing expres­sion: µ (,l2)= ------d (14) Mloop l1 2p The above formula shows that the (dipole) forward coupling between the loops is (approximately) a small constant when the segment lengths are long enough.
Sentence 2: the forward cou­pling inductance between the loops is well approximated by a con­stant which only depends on the distance of the current return; when the segment lengths increase, the forward coupling induc­tance approaches this constant as the limit value.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that the dependent events could be repetitive among send events.
Sentence 2: if an upcoming send event n +1 occurs right after send event n, the observing window of these two send events might overlap, which results in the same depen­dency pattern, the reason is that these two send events are just dependent on the same receive events simultaneously (such as the MPI group communication as MPI_allgather, MPI_alltoall, etc.)
Relationship: entailment
Domain: Hardware
Sentence 1: In rare instances, there may be more than one tiles with EPD equal to .H.Inthiscase,wejust .rstprocessthetilefound .rst.
Sentence 2: thenafteracoupleofrip-up-and-reroute operations,itislikelythat theEPDofthistilebecomes smallerthan .H, and next weprocess anothertilewithEPDequalto .H.thetieisbroken arbitrarily, and then the other tile(s) with the same EPD will be considered soonin a subsequentiteration.
Relationship: entailment
Domain: Hardware
Sentence 1: This heuristic optimizes multi objective 0 1 ILPs with also non linear objective functions and design space exploration problems, respectively.
Sentence 2: the PB solver is used to force a common heuristic approach, like a MOEA, to stay in the feasible search space allowing to focus merely on the optimization of the objectives: With the de.ned constraints from Section A and without any objective function, the PB solver will .nd one speci.c feasible implementation for a given design space exploration problem.
Relationship: entailment
Domain: Hardware
Sentence 1: Although the notion of PMA can be applied to different power reduction techniques, in this paper, we use a scheme that combines selective cache ways [3] and gated-Vdd [19] as the example of a thermal-unaware power reduction technique.
Sentence 2: we modify this thermal-unaware cache is accessed through charging and discharging capacitances such as wordlines, bitlines, address lines, and data output lines.
Relationship: entailment
Domain: Hardware
Sentence 1: Our method is implemented in perl and is much faster than SPICE simulation.
Sentence 2: for the resultsshown in this section, the SPICE simulations for the inverter withinput 1 (input 0) took 12.6s (10.9s) while the perl script generatedthe result for input 1 as well as input 0 in 0.008s.
Relationship: entailment
Domain: Hardware
Sentence 1: 2.5 Micromechanical Circuits Although stand-alone vibrating µmechanical resonators are them­selves applicable to local oscillator synthesizer applications in transceivers [19][20], their application range can be greatly ex­tended by using them in circuit networks.
Sentence 2: by inter­linking mechanical elements into specific networks, a variety of low-loss circuit functions are available, from bandpass filters [9] to mixers [21] to gain devices [22].
Relationship: entailment
Domain: Hardware
Sentence 1: Thus, unlike the approach given in [7], we lift the entire veri.cation problem to the abstract level: Whenever we succeed in verifying that Kh¯|=Fh¯holds, our results imply that also K|=Fholds.
Sentence 2: our method applies to any kind of counters (with increment/decrement inputs) and any kind of ACTL * speci.cation that compares the counter s value with some .xed constants.
Relationship: entailment
Domain: Hardware
Sentence 1: Thus, all of the above routing problems  brick routing, minimum wirelengh brick routing, minimum via brick routing, and pattern-prohibited brick routing are decision problems in the complexity class NP [5], and there­fore have polynomial reductions to the Boolean Satis.abil­ity (SAT) problem.
Sentence 2: for each instance of any of the aforementioned routing problems, we can generate a boolean formula corresponding to an instance of the SAT problem such that the formula is satis.able if and only if the instance of the asso ciated routing problem has a solu­tion.
Relationship: entailment
Domain: Hardware
Sentence 1: The graphical model for the influence model is identical to that of the generalized N-chain coupled HMM, but there is one very important simplification.
Sentence 2: instead of keeping the entire 1 N j P(St i | St -1,..., St -1) , we only keep P(St i | St -1) and approximate the former with: 1 N j P(St i | St -1,..., St -1) = .aij P(St i | St -1) j we form our probability for the next state by taking a convex combination of the pair wise conditional probabilities for our next state given our previous state and the neighbors previous state.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.3 Data-path and Controller Veri.cation Objectives: The .nal output of the high-level synthesis is a control-path and a data-path (CP-DP) so that (i) all the register transfer operations and the status conditions in M2 are indeed provided for the DP com­ponents and theirs interconnections and (ii) the set of all control signals generated and status signals sensed in the states of the con­troller FSMD M3 do realize the corresponding register transfers of FSMD M2.
Sentence 2: the veri.cation task in this phase is de.ned as follows: given the control signal assertion pattern in each state of the controller FSM, it is required to identify the cor­responding register transfer operation in the DP and construct the FSMD M3.
Relationship: entailment
Domain: Hardware
Sentence 1: One such instruction is the subleq instruction, which has been used for instructional pur­posesinthepast.We.ndthatthe scopeforusingsuchaTuring­complete instructionisfar greater, andin this paper, we present its applicability to fault tolerance.
Sentence 2: we extend a MIPS processor with a co-processor (called ultra-reduced instruction set co-processor URISC) that implements the subleq instruction.We use the URISC to execute sequences of subleq that are semanti­callyequivalenttothefaulty instructions.We formallyprove this, and implement the translations in the back-end of the LLVM com­piler.Wegenerate binaries for our hardware prototype called MIPS-URISC, which we synthesize and execute on an Altera FPGA.
Relationship: entailment
Domain: Hardware
Sentence 1: Figure 5: Complex shape for CU density layer Figure 6: Complex shape for memory block density layer Figure 7: Complex shape for LUT density layer With the new multi-layer density system and the proper shape generation procedure shown above, a heterogeneous placement task is translated to a set of homogeneous ones, with each of them being handled at a different density layer.
Sentence 2: the placer needs to make sure that density is properly distributed for all the layers in order to avoid both resource waste (Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that actual sampling rate is higher than what is speci.ed to the Android sensor manager) Power (mW) Increase over base power Accl (20 Hz) 230 112% Accl (10 Hz) 180 67% Accl (2 Hz) 164 51% Baro (1 Hz) 110 2% CPU Awake (base) 108 x CPU Asleep 25 x dimensional accelerometer data?
Sentence 2: can more be done with less data?
Relationship: entailment
Domain: Hardware
Sentence 1: Because our algorithm employs a thresholding heuris­tic when generating triangles,low-degree networks tend to produce insuf.ciently many shared triangles for propaga­tion of localization information.
Sentence 2: the algo­rithm prefers to achieve high-quality localization, even if only part of the network can be localized, than to localize the entire network with lower accuracy.
Relationship: entailment
Domain: Hardware
Sentence 1: E. Extraction of Distributions over Parameters As mentioned above, one of the advantages of using GMMs for clustering is that we have a probabilistic model from which we can extract the distribution corresponding to each cluster straightforwardly.
Sentence 2: at the end of a GMM run, we obtain a Gaussian distribution for each cluster, which we will use to draw parameter values as candidates to be a Pareto optimal point on our unseen (test) input.
Relationship: entailment
Domain: Hardware
Sentence 1: While not pictured here, the energy savings obtained from using the di.erent control architectures are similar  the system using the FD controller has about 8% higher energy consumption than the FC controller, while CF-8 actually has 1% lower energy consumption than FC.
Sentence 2: the performance of the three FC, FD and CF-8 controllers from an energy savings perspective is comparable.
Relationship: entailment
Domain: Hardware
Sentence 1: In [15] and [5], the au­thors introduce approaches to consider trajectory patterns between di.erent spatial levels as well as the relation among user, location and trajectory.
Sentence 2: geoLife [15] is a social networking service which increases social connectivity among users taking multiple geospatial scales into account while the work described by [5] focuses on Regions of Interest (ROI) as opposed to multiple abstraction levels.
Relationship: entailment