sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: For the case of a 266 MHz clock with a triangular modulation and with a 2.5% frequency deviation, around 13 dB attenuation is measured with this technique [4].
Sentence 2: in this model the impedance between Vdd and Vss is represented by a capacitance (Cc) in series with a resistance (Rch) in parallel with a capacitance (Cch) (Fig.
Relationship: neutral
Domain: Hardware
Sentence 1: Currently, the majority of power dissipation in FPGAs is dynamic power dissipation [12], resulting from the charging and discharging of parasitic capacitance and characterized by: 1 .
Sentence 2: o0 o1 o127 primary outputs  i2 i1 i0 primary inputs i127 Figure 2: Circuit with regularity the size of modern circuits is up to two orders of magnitude larger than the MCNC circuits.
Relationship: neutral
Domain: Hardware
Sentence 1: The area consumption and frequency of each stream are summarized in Table 5.
Sentence 2: it is need to cache the entireimage on-chip(for animage of512 × 512 32 bit pixels, it corresponds to 1 MB storage)to implement a ful­ly pipelined computing module, which easily exceeds the on-chip memory limitation of the FPGA and renders this approach impractical.
Relationship: neutral
Domain: Hardware
Sentence 1: [15] W. Zhao, E. Belhaire, C. Chappert, and J. O. Klein.
Sentence 2: 3 shows a plot of the critical switching current Ic versus the pulse width d. In reality, Ic is exponentially related to d, for small values of d. this particular device was simulated for a limited range of d over which it is linear.
Relationship: neutral
Domain: Hardware
Sentence 1: [4]H.H.ChenandD.D.Ling.PowerSupplyNoise AnalysisMethodologyforDeep­SubmironVLSIChip Design.InPro.DesignAutomationConferene, pages638.643,Anaheim,CA,June1997.
Sentence 2: werepresentthetotalwidthoupiedbypowergridwires onboundarybasP(b).IfapowergridwirePihasa trakwidthofw(Pi),whihinludesitswirewidthand therequiredspaingfromanadjaentwire,andthereare asetofsuhwires,Pl,P , Pm,thatrossb,thenP(b)= m i.lw(Pi)representsthespaethatisunavailableforsig­nalwirestorosstheboundary.wesubtratthis quantityfromtheboundarywidthtoobtainthespaeavail­ableforsignalwiresasW(b)-P(b).Typially,auniform trakwidthw isappliedtoallthesignalwiresintheon­gestionestimationorglobalroutingstage.Hene,signal wireongestionisoftenexpressedintermsofthenumber ofwiringtraksandthenumberoftraksavailableforsig­ LW(b) P(b) nalwiresisT(b)=.IfthereareS(b)signal :  wiresthatrossaboundaryb,thentheoverfowonbis max(0,S(b)-T(b)).Alltileboundarieswithpositiveover­fowvaluesformaongestionmapforahip.Thewire densityatbisrepresentedasS(b)/T(b),measuringtheon­gestionofb.Aommonobjetiveforglobalroutingistoen­surethatthereisnoboundarywiththewiredensitygreater thanone,i.e.,S(b):T(b).
Relationship: neutral
Domain: Hardware
Sentence 1: Section 3 presents the optimization problem and block (intra) and system (inter) level dependencies that exist between system (quality), circuit (energy, delay) metrics and various design variables.
Sentence 2: [6] G. Karakonstantis, et al., Design methodology to trade-off power, output quality and error resiliency: application to color interpolation filtering , IEEE ICCAD, 2007.
Relationship: neutral
Domain: Hardware
Sentence 1: Chip Testing Result Our E-test results show that the variation of TSMC process is well controlled: the mean (P) and the standard deviation (Std., or V) of the NMOS select transistor resistance are 917: and 15:, respectively.
Sentence 2: enhanced Technologies for NSRS A. R-I curve skewing A large IR2, is favored in NSRS because of the incurred large difference between the resistance changes of an MTJ at high-and low-resistance states when the sensing current varies from IR1 to IR2.
Relationship: neutral
Domain: Hardware
Sentence 1: Wosnitza [8] 8925 µJ DoubleBW [9] 2834 µJ DSP-24 [10] 1822 nJ Spiffee [11] 781 nJ Energy-Scalable 16-bit 564 nJ Energy-Scalable 8-bit 304 nJ  5.
Sentence 2: the extra control logic of energy scalable designs incur an area and device count penalty when compared to a non-scalable design.
Relationship: neutral
Domain: Hardware
Sentence 1: pR2  7.3 Localization Error vs. Antenna Sectors In our second experiment, we examined the impact of the num­ber of antenna sectors M on the average localization error LE.In Figure 7(b), we show the LE vs. LH, for different number of an­tenna sectors.
Sentence 2: the wormhole attack is very dif.cult to detect, since it can be launched without compromising any host, or the in­tegrity and authenticity of the communication [3, 19, 20].
Relationship: neutral
Domain: Hardware
Sentence 1: Our results indicate that estimator automation can result in high-performance circuits; when compared with a software implementation of the same ECC application on a 32-node Beowulf cluster computer, FPGA implementation using designs selected by our method can achieve an order of magnitude speedup and still meet critical area and device timing constraints.
Sentence 2: for any two given multipliers, no given one is clearly better than the other in terms of both resource usage and computational latency.
Relationship: neutral
Domain: Hardware
Sentence 1: To tackle these problems, we believe that it is necessary to 1) develop coverage metrics for I/O validation; 2) develop specialized data mining and analysis techniques to discover correlations among various sources of data, which can be used to increase validation ef.ciency; 3) maximize the usage of simulation and bridge the gap between simulation and validation results.
Sentence 2: the bug might not be excited in the debugging environment, due to interactions with boards and oscilloscope probes.
Relationship: neutral
Domain: Hardware
Sentence 1: iWalkusestheinputqueryanduserlocationtoretrieveuptotenlistingsfromabusinesslistingdatabasecomprisingtensofmillionsoflistings.iWalkthenpresentstheselistingstotheuserone-by-oneinincreasingorderofdistancefromtheuser scurrentlocation.Summaryinformationabouteachlisting,includingname,address,phonenumberanddistancefromtheuser,ispresentedintextandspeech(seeFigure1(b)).SoiWalkmightsaytotheuserDestinationPizzaGrille,3HeadquartersPlaza,0.23miles(about3min-utes).Jennycanusetheleftandrightsoftkeys,ortheNextandBackbuttons,tomovebetweenlistings.Whenshehasfoundherdesireddestination,shecanclickeitheronthelistingsummaryorontheDirectionsbutton.iWalkstoresthetenmostrecentdestinationspreviouslychosenbythisuseras favorites .IftheuserchoosesFa-vorites,iWalkwilllistthesedestinations.
Sentence 2: iWalk:ALightweightNavigationSystemforLow-VisionUsers AmandaStentAT&#38;TLabs-Research180ParkAve.,Building103FlorhamPark,NJ07932stent@research.att.com ShiriAzenkotUniversityofWashingtonSeattle,WA98195shiri@cs.washington.edu BenSternAT&#38;TLabs-Research180ParkAve.,Building103FlorhamPark,NJ07932bjs@research.att.com ABSTRACT SmartphonestypicallysupportarangeofGPS-enablednav-igationservices.mostnavigationservicesonsmartphonesareoflimitedusetopeoplewithvisualdisabili-ties.Inthispaper,wepresentiWalk,aspeech-enabledlocalsearchandnavigationprototypeforpeoplewithlowvision.iWalkrunsonsmartphones.Itsupportsspeechinput,andprovidesreal-timeturn-by-turnwalkingdirectionsinspeechandtext,usingdistancesandtime-to-turninformationinadditiontostreetnamessothatusersarenotforcedtoreadstreetsigns.InbetweenturnsiWalkusesnon-speechcuestoindicatetotheuserthats/heis ontrack .
Relationship: neutral
Domain: Hardware
Sentence 1: In order to determine the utility of allocating extra ways to a thread, the authors maintain a record of CPI vs cache-space and use cubic spline interpola­tion to predict the change in CPI with change in allocation at runtime.
Sentence 2: mEMORY REUSE BEHAVIOR This section presents our analysis of the memory reuse be­havior of data-parallel programs and explains how the ana­lysis leads to our proposed scheme.
Relationship: neutral
Domain: Hardware
Sentence 1: A stochastic optimizer for­mulates the problem as an in.nite horizon MDP, which con­siders the bu.er occupancy and residual energy level of the member node as the input states.
Sentence 2: mDP is performed o.ine and the obtained optimal slot policy matrix P (b, e), for all possible bu.er bn and energy e n states, respectively, are stored in a table in­side each node.
Relationship: neutral
Domain: Hardware
Sentence 1: 1, we get: X X i j Cw j b= Cj m= (n -i) t(3) 1 0 E D , n j.Di j.Di since the Elmore delay tj of the line until the j-th subsegment is E D given by the .rst moment m0 j [9].
Sentence 2: then, we determine if a timing violation has occurred as described next.
Relationship: neutral
Domain: Hardware
Sentence 1: (2) If we are given in.nite run time to .nd a placement, a trivial solution is to construct a new timing analysis graph G(V,E) after every accepted swap.
Sentence 2: needed to calculate the critical path delay, our dupli­cated results may result in some discrepancy between the original PATH algorithm.2 we believe the follow­ing argument is valid: PATH needs more routing resources We contacted the author of PATH for detailed experimen­tal settings but did not get any response.
Relationship: neutral
Domain: Hardware
Sentence 1: [8] Tanaka, K., Yamabe, T., and Fukui, K. The Science and Technology of Carbon Nanotubes, Elsevier, Amsterdam, 1999.
Sentence 2: latter CNT-FETs fabricated in 2004 [18,19] did not show any of this barrier characteristic, which was achieved by changing the electrode material at the source and drain ends.
Relationship: neutral
Domain: Hardware
Sentence 1: (Ki ×.Li), (EQ 12) , i where Ki is the coef.cient of total path delay change due to intra-die device length .Li at gate i.Given the mean µand the standard devi­ i ation si for intra-die device length .Li with normal distribution and the coef.cients Ki, we can compute mean and standard deviation of the probability distribution for Dp,intra directly using the following standard equations: µ= Ki ×µi (EQ 13) D. pintra , i s2= (Ki 2 ×s2) (EQ 14) D. i pintra , i Given precharacterized sensitivities, the .nal computation of the dis­tribution of Dp,intra is performed very ef.ciently and requires only a single traversal of the path.
Sentence 2: often the necessary models and layout information for incorporating deterministic variations in delay computation are not available and hence, deterministic variations are treated as ran­dom variations.
Relationship: neutral
Domain: Hardware
Sentence 1: The number of transistors in new BICS are 27 where as for BICS in [3] are 34, so the area overhead of new BICS is smaller than the BICS in [3] The BICS in [3] wasn t validated for PVT, noise and current shape anal­ysis.
Sentence 2: soft errors are today a concern even at ground level, at least for those applications where reliability is an important attribute.
Relationship: neutral
Domain: Hardware
Sentence 1: Improved Memoryless RNS Forward Converter Based on the Periodicity of Residues.
Sentence 2: this is done to remove the 2n+3-k 2n+1-1 - 1 , k<n +3 |P1 -1|P2 = 3 (10) modular operation w.r.t 2n+1 - 1.
Relationship: neutral
Domain: Hardware
Sentence 1: The MUXFX multiplexer implements the MUXF6, MUXF7, or MUXF8, as shown in Figure 9.
Sentence 2: aRCHITECTURE REVIEW OF XILINX FPGAS Before going to the actual topic we .rst take a quick re­view of internal architecture of some modern Xilinx s FP-GAs.
Relationship: neutral
Domain: Hardware
Sentence 1: An Exploration of Gesture-Speech Multimodal Patterns for Touch Interfaces Prasenjit Dey, Sriganesh Madhvanath, Amit Ranjan Suvodeep Das Hewlett-Packard Labs, 24, Salarpuria Arena, Adugodi, Hosur Road, Bangalore-560030, India {pday,srig,amitr}@hp.com  ABSTRACT Multimodal interfaces that integrate multiple input modalities such as speech, gestures, gaze, and so on have shown considerable promise in terms of higher task efficiency, lower error rates and higher user satisfaction.
Sentence 2: [2] Oviatt, S. L., Mutual Disambiguation of Recognition Errors in a Multimodal Architecture , Proc.
Relationship: neutral
Domain: Hardware
Sentence 1: Inverter: The delay, power, and noise margins for simultaneous defects and variations in the GNRFET inverter are dominated by variations in GNR width and exacerbated by charge impurities.
Sentence 2: dense memories, which are the biggest prospect for graphene-based devices, are par­ticularly susceptible to variations and defects with near-zero noise margins and an increase in leakage power of over 5X.
Relationship: neutral
Domain: Hardware
Sentence 1: Weextractpower-lawexponentsfromthelinearre­gressiononthelog-logplot.6  Weapplynon-linearregression(aLevenberg-Marquardt variant)tofndtheminimumstandarddeviationftof eachmodeltoexperimentaldata.
Sentence 2: zarkesh-HamodeldependsonTnet(i)beingthesamein boththeN-gatecircuitandthe(N;1)-gatecircuit,for alliN.suchanassumptionmaynotbevalid.
Relationship: neutral
Domain: Hardware
Sentence 1: For example, we can see that the prefetches performed by clients P0, P1 and P2 most affect the data of clients P1, P2 andP3.Similarly, prefetches carried outbyP3andP4displace from the cache mostly the data required by P4, P6 and P7.
Sentence 2: setting the value of K to 3 seems to be the right Fig.
Relationship: neutral
Domain: Hardware
Sentence 1: For example, closed-loop mechanical ventilation that is coupled with oximeter readings to monitor blood oxygen levels would require a complex and perhaps unbuildable system of physical mockups to emulate respiratory mechanics and complete cardiopulmonary activity.
Sentence 2: 4.2 Model Configuration The lung model hosted by the digital mockup consists of the RRCC model described by Borello [2].
Relationship: neutral
Domain: Hardware
Sentence 1: From Figure 7 we observe that merely selecting the energy-aware cache con.gurations (scheme F) has only a nominal impact on energy.
Sentence 2: projecting to sub-.1 fm technology design considerations that call for a three-level conventional cache hierarchy for performance reasons, we demonstrate that a con.gurable L2/L3 cache hierarchy coupled with a conven­tional L1 results in an average 43% reduction in memory hierarchy energy in addition to improved performance.
Relationship: neutral
Domain: Hardware
Sentence 1: This assumption is intuitively reasonable in that when objects,suchasgridpanelsofdropped ceilings,tubelampsorelec­tricity wires, are hung on the ceilings, they are usually oriented to be parallel or perpendicular to the ceiling edges for aesthetic con­siderations such as visual neatness and consistency.
Sentence 2: if the location of the compass does not change over time, such as a user holding hermobilephone whilesittinginhercubicle, themagnetic interferencefromthemetalliccubiclecannotbeeliminatedbyonly using averaging.
Relationship: neutral
Domain: Hardware
Sentence 1: The key bene.t of TAPE ST RI-multi is that it achieves very high density by sharing the read/write ports across multiple bits that are stored in the ferromagnetic wire.
Sentence 2: the bit-cell also consists of two separate access transistors  a read access transistor (T2) and a write access transistor (T1), which are used to control the direction of currents during the read/write operations.
Relationship: neutral
Domain: Hardware
Sentence 1: To reduce the hardware logic complexity, we developed a software design to facilitate the use of the DLIC cache; to increase the e.ciency of the design, we re­ducethe storage consumptionby using ahierarchicaldesign sothatthecachetableinDLICissmallyet cancapture most of loops in a given application, including the large complex ones.
Sentence 2: [22] Shuai Wang, Jie Hu, and Sotirios G. Ziavras.
Relationship: neutral
Domain: Hardware
Sentence 1: Online per­formance analysis by statistical sampling of microprocessor performance counters.
Sentence 2: fig­ure 4(a) says that together is better than adjacent, which is 2While Pearson s product moment coef.cient appears to be more com­monly used, it is not applicable in our domain because Pearson s assumes a normal distribution of the metrics under consideration, an assumption which is not necessarily valid for our data.
Relationship: neutral
Domain: Hardware
Sentence 1: In mPL2, the a.nity rij between vertices iand j has the initial form w(e) rij = , (|e|-1)area(e) {e.E | i,j.e} where H =(V, E) is the underlying weighted hypergraph representation; w(e) is the weight associated to hyperedge e,area(e) denotes the sum of the areas of the cells (vertices) in e,and |e| denotes the number of vertices in hyperedge e. The purpose of weighted area in the denominator is to give higher a.nity to smaller cells joined by smaller nets.
Sentence 2: both phases typically incorporate wirelength, timing, and routability into their ob jectives or constraints.
Relationship: neutral
Domain: Hardware
Sentence 1: CONCLUSION We discussed the state of the art in interconnect fabric, their limitations, and identified energy as the primary barrier for the future.
Sentence 2: the advantage of a mesh network is that the average latency grows slowly (square root) with the number of agents, but adds more complexity into the network protocols and implementation logic, and if not careful then could create hazardous conditions such as dead-locks [2] [3].
Relationship: neutral
Domain: Hardware
Sentence 1: AlgorithmElet-and-Broadast l.Preproessing Preproessingworksiny=x 2(x 2 -l)phases,numbered0 toy-l,orrespondingtoouples(i,j),whereiE{l,...,x 2}andjE{l,...,x 2}{t}.Inthephaseorrespondingto(i,j) weonsiderenumerationai,desribedinSetion2.l,and arryoutProedureElet­Coupleinparallelforallpairsof tileswithnumberstandjinthisenumeration.
Sentence 2: pROOF.Theproofisbasedonanideafrom[4,7]wherea lassofgraphsrequiringbroadastingtimen(nlogn)has beenonstruted.Agraphdesribedin[7]isshownin Fig.l(a).Itwasshownin[7]thatthesouremessageneeds timen(logn)totraverseeaheye"ofthegraphthusyield­ingthelowerboundn(nlogn)forgraphswithlinearlymany eyes".thesegraphsannotbeusedinourase, asitiseasytoseethattheyarenotGRN.
Relationship: neutral
Domain: Hardware
Sentence 1: Categories and Subject Descriptors D.7.2 [Integrated Circuits]: Design Aids General Terms Algorithms, Design, Theory Keywords Simulated annealing, electronic design automation, EDA, computer-aided design, CAD, VLSI Copyright is held by the author/owner(s).
Sentence 2: liu s simulated annealing algorithms have a completely different style: They resemble clever algorithms that attempt to solve difficult problems in polynomial time, and they often have a strong algorithmic flavor with a significant effort spent on optimizing the solution space and cost function.
Relationship: neutral
Domain: Hardware
Sentence 1: An estimate on the execution time of actor vCD is ~289627 , 14071, 289622 , 14071, 289623 , 14071. microseconds and the actor switching cost CCD is 631 mi­croseconds.
Sentence 2: examples of loop transformations are interchanging two nested loops, reversing the order in which a loop s iter­ations are performed, and fusing two loop bodies together into one.
Relationship: neutral
Domain: Hardware
Sentence 1: [7] N. Hanchate and N.Ranganathan, LECTOR: A Technique for Leakage Reduction in CMOS Circuits , IEEE Transactions on VLSI Systems,vol.
Sentence 2: figure 3 (a) LECTOR technique (b) GALEOR technique In [8], a technique called as GALEOR (GAted LEakage TransistOR) is introduced as shown in figure 3(b) which achieves 52% savings in leakage power compared to 30% power reduction obtained using LECTOR which is depicted in figure 4.
Relationship: neutral
Domain: Hardware
Sentence 1: 12th annual ACM symposium on User interface software and technology (New York, NY, USA, 1999), ACM Press, pp.
Sentence 2: in tasks such as map navigation, exploring the space typically involves having to manipulate a scroll bar or a zoom control widget, requiring the user to take the pointer off of the primary point of interest, when bimanual control is not available.
Relationship: neutral
Domain: Hardware
Sentence 1: metrics are code metrics, such as statement coverage, branch coverage, path coverage, toggle coverage, and some metrics related to the structure of the design, such as FSM state coverage, transition coverage and OCCOM coverage [1], etc.
Sentence 2: in design practices, after adding assertions for runtime design errors monitor, it always wastes lots of simulation resource with large amount of randomly generated stimulus without triggering the inserted assertions.
Relationship: neutral
Domain: Hardware
Sentence 1: Furthermore, for each row, the time used in RB depends only on the number of the nodes, which means that the time and memory usage are linear in the number of nodes.
Sentence 2: [3] J. Kozhaya, S. R. Nassif, and F. N. Najm, A Multigrid-like Technique for Power Grid Analysis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.
Relationship: neutral
Domain: Hardware
Sentence 1: In Figure 1(b), the same datapath is shown with some low-utilized bypass paths removed.
Sentence 2: p the function FLASH RANK essentially com­ putes: MAX(weighted-min-sched-length(Sk 1), weighted-min­ sched-length(Sk), ..., weighted-min-sched-length(Sk)), 2 p given that the operation a is scheduled on FU ra.The MAX function ensures that we get the (best) sched­ule length of the dependence chain that is most con­strained by latency.
Relationship: neutral
Domain: Hardware
Sentence 1: Dynamic node is eventually discharged to a steady-state voltage less than |Vtplow| by the high subthreshold leakage currents of the low-Vt NMOS transistors in the pull-down network.
Sentence 2: all of the NMOS sleep transistors (required within every domino gate) are placed into the maximum gate oxide leakage current state with the dual-Vt -NMOS technique.
Relationship: neutral
Domain: Hardware
Sentence 1: A sensor network Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Sentence 2: the occurrence of blind spots does not fully cap­ture the impact of the limited node lifetimes on the life­time of the network.
Relationship: neutral
Domain: Hardware
Sentence 1: Two pillars of our pro­ 1.2 posed system are early prediction of timing errors from pro­ 1 0.8 gram phases, and exploiting a low-overhead controller for 0.6 frequency and clock skew tuning.
Sentence 2: combined with timing speculation, clock skew tuning can be even more effective, as it becomes possible to con.g­ure the clock skews more aggressively to allow occasional errors, thereby improving both performance and energy ef.­ciency [20].
Relationship: neutral
Domain: Hardware
Sentence 1: Intheimpreiseomputation,eahvariableorre­spondstoapairofdataasitsownrepresentation.Eah funtionalunitperformsitsfuntionwithagiveninput datasetandproduesapairofdataasanintermediatere­sultratherthanproduinganexatvalueompletely.The omputationispartiallyproesseduntilthepairofthere­sultdatahavebeenprodued,iftheresultisnotritially demandedintheformofanexatvalue.Apairofdata representingaertainvalueisalledanimpreisevalue.
Sentence 2: inthispaper,weproposeanimpreiseomputation (IC)asanewarhiteturalomputingmodeltoaeler­atedataomputationsstritlyserializedduetodatade­pendenieswithutilizingthehighavailabilityofhardware resoures.Thisisanorthogonalapproahtotheprevi­ousapproahes,whihtriedtoresolvethedatadependen­iesbyexploitingmoreonurreny.Thebasionept ofanimpreiseomputationhasbeenintroduedbyLin etal.
Relationship: neutral
Domain: Hardware
Sentence 1: 8 describes the pseudo code of the control bits generat­ x ing algorithm.
Sentence 2: therefore, at least one of the four minterms {m3,m4,m5,m6} is contained in function f.no matter which minterm belongs to f ,the value of f z * able set Sa and can be respectively mapped to a pair of availableboolean functions {AND, NAND, OR, NOR, XOR, XNOR}.As both of the expansion variable and its complement can be fedas the select bit of the MUX, the order of the boolean functionpairs can be exchanged.
Relationship: neutral