sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: To stem this trend, and to relieve the pressure placed on memory bandwidth by supply pins, the supply pin count should ideally grow no faster than the total pin count growth rate of doubling every six years.
Sentence 2: d100.0479·year-93.2391 dNsupply = , dyear dyear (4) 0.0479·year-93.2391 = 0.1103 · 10.
Relationship: entailment
Domain: Hardware
Sentence 1: 6.2 Hardware working set analysis Besides collecting working set signatures, hardware can also be used for estimating working set size and/or to de- tect working set changes, thereby reducing software over- head.
Sentence 2: detecting working set changes in hardware avoids invoking the VMM between each inter- val; the VMM has to be invoked only when the working set actually changes.
Relationship: entailment
Domain: Hardware
Sentence 1: Similarly to the underlying protocols, abstractions es­tablished in distributed object programming, such as the remote method invocation (RMI, typical for client/server interaction), the tuple space (emerged from parallel computing based on distributed shared memory) or the publish/subscribe (for mass dissemination of events) ab­stractions, do indeed also make sense in P2P settings, and have already been used successfully in such contexts.
Sentence 2: the publish/subscribe abstraction captures many characteristics of P2P environments, and has been widely employed to model and implement remote interaction in P2P settings (e.g., [12]).
Relationship: entailment
Domain: Hardware
Sentence 1: The second f or loop (Line 9) assigns the magnetization state of each magnet according to the binary bit information from q.
Sentence 2: the magnetization state of magnet i, Myi , is set to Ms (resp., -Ms) if bit i of q is 1 (resp., 0), where Ms is the saturation magnetization of the magnet.
Relationship: entailment
Domain: Hardware
Sentence 1: To be able to use the huge quantity of hardware resources available inside today s FPGAs, new electronic system level (ESL) design methodologies and tools are necessary.
Sentence 2: the ever increasing density of transistors, the complexity (number of gates) of assembled hardware functions and the apparition of new 3D ICs have the consequence that energetic needs are rising, and will drastically continue to do so.
Relationship: entailment
Domain: Hardware
Sentence 1: Counter-based Component Power Estimation We use the component access rates either given di­rectly by a performance counter or approximated indirectly by one or more performance counters to weight com­ponent power numbers.
Sentence 2: we use the access rates as weighting factors to multiply against each compo­nent s maximum power value along with a scaling strategy that is based on microarchitectural and structural proper­ties.
Relationship: entailment
Domain: Hardware
Sentence 1: In this example, not all the input signal values from 1st to 10th cycle are responsible for this erroneous output value, but only the input values at 6th cycle (....1, ....2, ....3)= (1, 5, 2) are.
Sentence 2: we need only the input values (....1, ....2, ....3) = (1, 5, 2) for debugging the error.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION Three-dimensional integrated circuits (3D-ICs) are rapidly becoming a viable option for overcoming the performance and power bottlenecks of global interconnects in multipro­cessor systems-on-chip (MPSoCs).
Sentence 2: 3D-ICs of­fer reduced interconnect lengths, which reduce power, de­crease latency, increase bandwidth, and thus increase perfor­mance.
Relationship: entailment
Domain: Hardware
Sentence 1: For a single faulty node, the respective e.ects are always limited to increasing skews by at most a few d+, since we can work around the defective node in our reasoning.
Sentence 2: when inductively constructing a zig-zag path (which will imply a skew bound), we can switch to the other causal link of the current node if we run into a Byzantine node.
Relationship: entailment
Domain: Hardware
Sentence 1: In this section we assume that the application requirements can be satis.ed with a range of network transmission delays, and examine how an adaptive packet transmission scheduling strategy can reduce contention on the channel and reduce overall energy.
Sentence 2: we observed that transmission delays of up to 50 ms do not have a noticeable e.ect on the quality of fall detection (percentage of correct detection over percentage of false positives and false negatives).
Relationship: entailment
Domain: Hardware
Sentence 1: Copyright 2007 ACM 978-1-59593-627-1/07/0006 5.00 As the supply voltage is lowered, the circuit delay increases and hence the ration of leakage energy over dynamic energy increases as devices spend more time leaking.
Sentence 2: as the supply voltage falls below the threshold voltage of the devices, the delay increases exponentially leading to a rapid increase in the leakage energy.
Relationship: entailment
Domain: Hardware
Sentence 1: When a multiple step BDF method is used, the derivative is ap­proximated by the formula: k x.n = a0xn + X aixn-i (1) i=1 where coef.cients ai and a0 are functions of the present and past time step sizes.
Sentence 2: the leading coef.cient a0 determines whether the matrix has to be refactorized.
Relationship: entailment
Domain: Hardware
Sentence 1: ISCA 00 Vancouver, British Columbia Canada Copyright (c) 2000 ACM 1-58113-287-5/00/06-1 $5.00 .ow and memory access patterns.
Sentence 2: it is the fact that memory addresses are dif.cult (if not impossible) to statically predict in part because they often depend on run-time inputs and behavior that makes it extremely dif.cult for the compiler to stat­ically prove whether or not potential threads are independent.
Relationship: entailment
Domain: Hardware
Sentence 1: It is reported when the attack occurs, the router s LSA which is modi­.ed by an attacker is removed from all routers tables in at least 5 seconds (based on Section 12.1.6 of the OSPF proto­col description, the router which loses its LSA will generate an LSA with a new sequence number after .ve seconds).
Sentence 2: the number of the tokens in certain places (routers kernel tables) decreases for a while.
Relationship: entailment
Domain: Hardware
Sentence 1: In our implementation, this is realized as a lifetime, or window of cache time for each reference count value.
Sentence 2: for a window of k cache writes, if value v is written to cache on write i, v will be evicted on write i + k. We evaluate both uni.ed and data (non-uni.ed) cache con.gu­rations, and with each, we simulate write-through, write-back, and dusty policies.
Relationship: entailment
Domain: Hardware
Sentence 1: E. Setting of Test Limits The lower and upper BIST limits, denoted herein by ml and mu, are optimized, in order to obtain a desired trade-off between yield loss and defect level.
Sentence 2: we apply the rule-of-ten [12], which suggests that it is at least ten times moreexpensivetoshipafaultydevicethanto discarda functional one.
Relationship: entailment
Domain: Hardware
Sentence 1: If A s sibling B is not a leaf because the sibling file portion has been further split, then it is necessary to perform a depth first search (DFS) in the sub-tree rooted at B until a leaf vertex is found.
Sentence 2: in order to remerge with the neighbor region nearby and if A is the left sibling of B, the DFS must visit left siblings before right ones.
Relationship: entailment
Domain: Hardware
Sentence 1: The algorithm consists of three stages: (1) 3D analytical global place­ment with density optimization and whitespace reservation for TSVs, (2) TSV insertion and TSV-aware legalization, and (3) layer-by-layer detailed placement.
Sentence 2: the global placement is based on a novel weighted-average wirelength model, giving the .rst model in the literature that can outperform the well-known log-sum-exp wirelength model theoretically and empirically.
Relationship: entailment
Domain: Hardware
Sentence 1: The computation of V 0 can be parallelized as Ns vector inner products (correlations) Vi 0 = Si T r. Since the columns Si of S are generated as .l­tered circular-shifted versions of the transmitted DS-CDMA spreading sequence, the computation of V 0 is equivalent to matched .ltering the received signal r. MP maximizes (3) iteratively, one channel coe.cient f qj at a time, using a greedy approach in which qj and f qj are selected such that the increase in (3) at each stage j is the largest possible.
Sentence 2: the multipath signal compo­nents are estimated via successive interference cancellation.
Relationship: entailment
Domain: Hardware
Sentence 1: Programming is made easier (both in C and VHDL) because no explicit reference to the dual-port mem­ory is required: It is important to stress that all of the ex­periments are performed by simply changing the input data size, without the need of modifying neither the application code, nor the coprocessor design.
Sentence 2: no modi.­cations are needed even for datasets which cannot be stored at once in the physical ly available dual-port memory.
Relationship: entailment
Domain: Hardware
Sentence 1: A number of tools have been de­veloped to enable veri.cation engineers to have more control over the generation of random tests.
Sentence 2: some of these techniques involve the use of program templates that de.ne the structure of the desired test, along with primitives to control the randomization of the related data, such as opcodes, register operands, and memory addresses [4].
Relationship: entailment
Domain: Hardware
Sentence 1: Accordingly, the process characteristics may be far from ideal for implement­ing analog circuits.
Sentence 2: high threshold voltages and low operating voltages to reduce the power consumption of digital cir­cuits provide little headroom for analog designs, complicating the * This work was supported in part by grants from Intel, SUN Mi­crosystems and the Natural Sciences and Engineering Research Council of Canada.
Relationship: entailment
Domain: Hardware
Sentence 1: Therefore our extended synthesis subset in­cludes most of the class related language constructs provided by C++.
Sentence 2: this means the ability to: declare classes;  create new classes by means of inheritance from al­ready existing classes;  derive classes from multiple and virtual parent classes;  declare data members of scalar and complex type, in­cluding class types and array types;  declare member functions and operators;  rede.ne member functions and data members in de­rived classes;  declare constructor methods;  declare class templates with scalar and type parame­ters.
Relationship: entailment
Domain: Hardware
Sentence 1: The GMRES method with the standard Krylov-subspace based iteration converges fast only when the eigenvalues of Jfhas a clustered distribution (close to 1).
Sentence 2: t the circuit time-constants need to be much smaller than the period T. Unfortunately this is not always the case for RF/MM-IC designs since the time-period T become very small at this frequency scale.
Relationship: entailment
Domain: Hardware
Sentence 1: The random variable e3.z3 = e1.z1 +e2.z2, serves as a place holder to store the moments of (e1.z1 +e2.z2).
Sentence 2: rather than propagating an uncorrelated component (a) PDF (b) CDF z in the canonical form, we propagate its 2M moments.
Relationship: entailment
Domain: Hardware
Sentence 1: Each such constraint is referred to as the locality constraint as it imposes a condition that needs to be satis.ed by the data transformation ma­trix Mxif we are to optimize the locality behavior of the corre­sponding reference.
Sentence 2: let LCi;j;k;pdenote the locality constraint due to the kth ref­erence to array Xjin nest iof procedure p. The set of locality constraints of procedure pis denoted by LC(p)=LCi;j;k;p: ijk it contains all constraints due to all arrays, all references, and all loop nests.
Relationship: entailment
Domain: Hardware
Sentence 1: Inaccuracies in the analog di.erence be­ 2.2 Model of Bonding and Package Parasitics Bonding and package parasitics e.ects cannot be neglected in an accurate mixed-signal IC design, as they severely a.ect the stability of bias voltages.
Sentence 2: bondwire and pin parasitic resistance, inductance and capacitance consti­tute an RLC network which can cause the internal supply voltages to be signi.cantly di.erent from external voltages.
Relationship: entailment
Domain: Hardware
Sentence 1: As the counterpart, if the task instances have already good fault detectors (e.g., in the case of curve d), the system reliability will be improved more smoothly by inserting more redundancy, i.e., both DUF s and SDCs can be eliminated at the same time.
Sentence 2: the e.ect of active redundancy could be ampli.ed by good fault detection.
Relationship: entailment
Domain: Hardware
Sentence 1: The reconstruction workload bound is 50% and 25% in stan­dard mirroring and chained declustering, respectively.
Sentence 2: two disks in standard mirroring and four disks in chained declustering would shoulder a heavy workload as a result of the redirected load from the failed disk, and result in a service bottleneck under degraded mode.
Relationship: entailment
Domain: Hardware
Sentence 1: RESULTS AND DISCUSSION 4.1 Simulation environment In order to perform a complete evaluation of the proposed rout­ing algorithm, we modi.ed the open Noxim [7], which is an open source SystemC simulator for mesh-based NoC.
Sentence 2: we modi.ed the router architecture by adding additional ports for com­municating the DP values and introduced a routing-table updating scheme as described in previous section.
Relationship: entailment
Domain: Hardware
Sentence 1: In other words, if loadX accesses srcX_1 in its first iteration and srcX_2 in its second while loadY accesses srcY_1 and srcY_2 in the same order, there is a high probability that the following will hold: | srcX_1 | - | srcY_1 | = | srcX_2 | - | srcY_2 | In this paper, we design a cache architecture that takes advantage of this knowledge.
Sentence 2: our contributions in this paper are: 1) We introduce load source correlation, 2) We show that there is a strong source correlation in a variety of networking applications, 3) We design a memory subsystem that utilizes the correlation information, and 4) We present simulation results indicating that our proposed architecture can be efficiently used in Network Processors to reduce the energy consumption and execution time.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we present an architectural technique to reduce the power consumption of multi-core processors.
Sentence 2: we: a) present simulation results showing that most of the misses in networking applications are caused by only a few instructions, b) devise a power reduction technique, which is a combination of a locality detection mechanism and an execution engine, c) discuss a fine-grain technique to offload code segments to the engine, and d) conduct simulation experiments to evaluate the effectiveness of our technique.
Relationship: entailment
Domain: Hardware
Sentence 1: Simpli.ed Implementation of during() B. Synchronization and Time Modeling The ideas presented up to now allow running a piece of code in parallel with a SystemC simulation, but up to now, the task can hardly communicate with the SystemC thread.
Sentence 2: it cannot call SystemC primitives like wait() and notify(), and shared variables between the SystemC thread would create race-conditions.
Relationship: entailment
Domain: Hardware
Sentence 1: This principle provides the basis for right-to-left digit serial integer operations.
Sentence 2: if we assume we have determined the low order (k-1)-bits of the result from the (k-1) low order operand input bits, incorporating the k-th bits of the operands, the k-th result bit can then be determined with the (k-1) lower order result bits inherited from the preceding serial computation.
Relationship: entailment
Domain: Hardware
Sentence 1: In this study, we set out to conduct a more thorough analysis of the performance characteristics of the Vocal Joystick in the context of target acquisition tasks.
Sentence 2: we were interested .rst in determining whether the Vocal Joystick used as a pointing device can be modeled by a Fitts law performance model, and second in calculating the Index of Performance (IP) of the Vocal Joystick with respect to the mouse.
Relationship: entailment
Domain: Hardware
Sentence 1: The new index expression is then Mp(RpTk -1Ifik + fop).
Sentence 2: now, to have spatial locality, the innermost loop in Ifkimust access consecutive elements in same row of Ap.to have spatial locality we need to satisfy the relation: ()() Mp RpTk -1(Ifki+ Ufdim(IJk))+ fop-Mp RpTk -1Ifki+ fop= Ufdim(Ap),where dim(Ifk)and dim(Ap)are thedimensions of Ifk and array Ap, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: V. TH E DE S I G N SPAC E EX P L O R AT I O N EN G I N E An engine based on a multi-objective genetic algorithm has been designed to automate the described DSE process by evaluating at the same time both the two reliability aspects.
Sentence 2: the Non-dominated Sorting Genetic Algorithm (NSGA-II [18]) has been adopted, due to its capability to perform an ef.cient multi-objective optimization; indeed it features an advanced ranking and elitism mechanisms that allow to preserve diversity into the pool of candidates solutions (i.e., the population) considered during the design space ex­ploration, thus supporting the exploration of several directions minimizing the risk of getting stuck in local minima.
Relationship: entailment
Domain: Hardware
Sentence 1: To satisfy the strict reliability requirements of mission-critical systems, various redundancy-based error de­tection solutions have been proposed [7], [14], [20], [22], [21], [26].
Sentence 2: lockstepping is a popular hardware based error detection scheme and is widely implemented in systems requiring high-reliability such as the IBM S/390 G5 [20] or the HP NonStop servers [26].
Relationship: entailment
Domain: Hardware
Sentence 1: Although the shrinking clock signal in the proposed method will be less sensitive to the PVT variations compared with delay cell-based shrinking pulses, the quality of the shrink­ing clock would su.er from jitter or skew in the tester clock signals.
Sentence 2: jitter and pin-to-pin skew in the clock signals from the ATE directly a.ect the amount of shrinking.
Relationship: entailment
Domain: Hardware
Sentence 1: While the W fresh items are in arbitrary order, it is possible to take advantage of the fact that the B old items are previous outputs of the selection network, and hence can be sorted or partially sorted if we wish.
Sentence 2: if we can get independently sorted lists of the best B old candidates and the best B new candidates, we can merge the lists in a single step by reversing one list and taking the pairwise min.
Relationship: entailment
Domain: Hardware
Sentence 1: The key is to lever­age TCM to reduce the memory bit error rate to relieve the burden of BCH codes, at no cost of extra redundant mem­ory cells.
Sentence 2: we designed a TCM-BCH approach geared to 2 bits per cell NAND .ash memories, and its ef­fectiveness has been demonstrated by simulations based on an approximate memory cell threshold voltage distribution model.
Relationship: entailment
Domain: Hardware
Sentence 1: Because each .ne-grained ac­cess reads or writes only 8B of data, it requires a factor of 8 more memory requests to achieve the equivalent throughput of coarse-grained accesses.
Sentence 2: .ne-grained ac­cesses will saturate an address/commandbus(ABUS) that is designed for coarse-grained accesses, and greater com­mand signaling bandwidth is required for .ne-grained ac­cesses tofully utilize theDRAMbandwidth.
Relationship: entailment
Domain: Hardware
Sentence 1: Susceptibility of Analog Cells to Substrate Interference Franco Fiori Politecnico di Torino Dipartimento di Elettronica C.so Duca degli Abruzzi 29, I-10124 Torino, Italy .ori@polito.it Abstract This paper deals with the susceptibility of smart power integrated circuits to substrate interference.
Sentence 2: propagation of RF interference through substrate and its ef­fects on analog cells are investigated.
Relationship: entailment
Domain: Hardware
Sentence 1: V (representing some input, output, or PCHB/WCHB module) is associated with three delay attributes: the evaluation delay (denoted v.teval ), the precharge delay (denoted v.tprech ), and the combined delay of completion detector tCD and, for the PCHB case, C-element tC (denoted v.tc).
Sentence 2: v.tc = tCD + tC for PCHB and v.tc = tCD for WCHB.
Relationship: entailment
Domain: Hardware
Sentence 1: Although the notion of YAPD can be applied to different power reduction techniques, in this paper we use a scheme that combines Selective Cache Ways [4] and Gated-Vdd [30] as the example of a yield-unaware power reduction technique.
Sentence 2: we modify this yield-unaware scheme with YAPD to investigate how the yield is affected by our optimization.
Relationship: entailment
Domain: Hardware
Sentence 1: An example of Harr wavelet transform on data {3, 4, 20, 25, 15, 5, 20, 3} As a result, wavelet decomposition is the collection of average and details coefficients at all scales.
Sentence 2: the wavelet transform of the original data is the single coefficient representing the overall average of the original data, followed by the detail coefficients in order of increasing resolutions.
Relationship: entailment
Domain: Hardware
Sentence 1: The meaning of the N + 1 nodes at level k is clear: starting from the left, the first node corresponds to the fact that all N customers are still to be placed in queues k,... , 1; the second node corresponds to the fact that one customer is at one of the queues K,... , k + 1, so only N -1 customers are still to be placed in queues k,... , 1; and so on, until the last node, where no customers are left to be placed in queues k,... , 1.
Sentence 2: the common property distinguishing the paths o~ = (iK,... ,ik+l) leading to the nTM node at level k is that they correspond to having as- signed the same number L ----iK + ... + ik+l of customers to queues K,... ,k+l.
Relationship: entailment
Domain: Hardware
Sentence 1: Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing Tobias Gemmeke2, Mohamed M. Sabry3, Jan Stuijt2, Praveen Raghavan1, Francky Catthoor1, David Atienza3 1 imec 2 Holst-Centre / imec 3 ESL-EPFL Leuven, Belgium Eindhoven, The Netherlands Lausanne, Switzerland tobias.gemmeke@imec-nl.nl  Abstract This paper focuses on a review of state-of-the-art memory designs and new design methods for near-threshold computing (NTC).
Sentence 2: it presents new ways to design reliable low-voltage NTC memories cost-effectively by reusing available cell libraries, or by adding a digital wrapper around existing commercially available memories.
Relationship: entailment
Domain: Hardware
Sentence 1: Potential for Power Reduction The improvement in throughput achieved by selective protection of significant data bits translates into improvement of yield and offers the potential for power savings through aggressive voltage over-scaling beyond i) the limit of reliable operation of 6T memory cells and ii) the limits imposed by the inherent error resilience of the fully unprotected system described in Section 5.
Sentence 2: as discussed in Section 6.1 the proposed storage scheme can limit the throughput loss, providing acceptable performance even under high number of defects (1%­10%) which could be induced by aggressive voltage scaling down to 0.6V (Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: R(q)represents the e.ective frequency for a particle hit of charge q in unit time according to [24][31].
Sentence 2: 1 -q R(q)= F ×K ×A ××exp( ) (5) Qs Qs where F , K, A and Qs denote neutron .ux (> 10MeV), technology-independent .tting parameter, the susceptible area in cm 2, and charge collection slop, respectively.
Relationship: entailment