sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Checking 1 against A1 we are presented with the following counterexample: r1 : 0 0 0 (0 ....) g1 : 0 0 0 (0 ....) r2 : 0 0 0 (0 ....) g2 : 1 1 1 (1 ....) The trace shows that we forgot to rule out initial spurious grants.
Sentence 2: we add a new requirement R3 stating that there must be no grants until there is a request.
Relationship: reasoning
Domain: Hardware
Sentence 1: Here, we observe that the detection and false-alarm probabilities is related to the complementary cdf (ccdf ) of the DV.
Sentence 2: we design a technique by de­riving the MGF of the DV and then employ the inverse Laplace transform to obtain the acquisition probabilities, valid for arbitrary multipath intensity pro.le (MIP) with uniformly-spaced paths.
Relationship: reasoning
Domain: Hardware
Sentence 1: Fi­nally, the nodes that have di.erent values in MAs(nt = sa0) and imp((nf1 = v) .
Sentence 2: mAs(nt = sa1)) can be nf2.in step 4, the nodes that driven by nf1 and nf2 are the added substitute nodes of Types 1 ~ 4.
Relationship: reasoning
Domain: Hardware
Sentence 1: An additional delayis introduced by the MUX with EQGLBF as the select signal.
Sentence 2: cLK DEL should be delayed (compared to the system clock CLK) by: delay for CLK DEL = 28 + DCW SP + delay of MUX + TSETUP EQ (3)where TSETUP EQ is the setup time of the Equivalence Checker design.
Relationship: reasoning
Domain: Hardware
Sentence 1: It is also worth mentioning that, as people carry along mobile devices all day long, the learning process can happen in any moment and place, because we can learn in unbelievable places.
Sentence 2: these devices break the frontier between formal and non-formal education, and guaranteeing that the leaning processes that happen both inside and outside an academic environment support each other and answers to the diversity of people and  Second International Conference on Technological Ecosystems for Enhancing Multiculturality -TEEM 14 situations with which we normally coexist, thanks to possibilities such as text zooming, voice transcription, location detection, text reading, etc, breaking barriers to communication and access for people with different capacities.
Relationship: reasoning
Domain: Hardware
Sentence 1: PLACEMENT While the floorplanning study described above was good enough to provide the answer to the question discussed in this paper, relevant for the systems in which its functional blocks (or IP cores such as embedded memories) are large, it was not good to provide sufficient insight needed for the systems implemented using low granularity components.
Sentence 2: in this section of the paper we are discussing traditional placement procedure implemented for 2-D and 2.5-D systems built with ordinary standard cells.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then the cost of the net between the cells is: 1 Wij [(xi - xj)2 +(yi - yj)2] (1) 2 1Equivalently, a force equilibrium state of the spring sy stem is found.
Sentence 2: if a cell i is connected to a .xed cell f with coordinates (xf ,yf ), the cost of the net is given by: 1 Wif [(xi - xf )2 +(yi - yf )2] (2) 2 the objective function which sums up the cost of all the nets can be written in matrix notation as [9]: 1 1 T T T T F(x, y)= x Qx + dx x + y Qy + dy y + constant (3) 2 2 where Q is an n × n symmetric positive de.nite matrix and dx, dy are n-dimensional vectors.
Relationship: reasoning
Domain: Hardware
Sentence 1: To this end, in the proposed approach, data dependencies are extracted automatically by using the symbolic execution de­scribed in the following section, which makes it possible to express Figure 3: An example of the cone-based architectural template the result of the (i + m)-th iteration as a function of (part of) the el­ements computed at the i-th iteration.
Sentence 2: given the data available from the i-th iteration, instead of trying to compute the whole fi+1, we can focus on a subset of the matrix elements and directly compute the results of a generic m-th iteration (with m = 1), thus obtaining a subset of fi+m.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that, in general, if AEr has out-degree 0, then again any v of interest is just AEr itself, and similarly to the base case, s(AEr,AEr) = AF(AEr) = 1 and the claim holds.
Sentence 2: if the removed vertex was AEr, we already know that the claim holds for C, so consider the case where AEr was not the removed vertex, and therefore it is also in D. Table 1: Signi.cance values of the adders in the graph shown in Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: The tuner aims to minimize namic pulldown network), the quadrature.binary conver- F = a X s X x RC(x, s)+ b X y (s X s RC(y, s)) sion does not incur any overhead as the conversion logic is folded into logic implementing other NoC features (such as crossbar muxing and link hot-sparing.)
Sentence 2: the overhead of the quadrature logic conversion is approximately 3.5% in our implementation.
Relationship: reasoning
Domain: Hardware
Sentence 1: In fact, starting with 180nm devices, the wavelength of optical source has remained the same (at 193nm) due to difficulties in finding a flicker-free, high energy, coherent light source with compatible improvement in lens material for focusing this light.
Sentence 2: upcoming technology nodes (65nm, 45nm, 32nm and 22nm) will be using a light source with wavelength much greater than the feature size.
Relationship: reasoning
Domain: Hardware
Sentence 1: When the NMOS Vth is low, sub-threshold leakage across N4 will cause transistor N5 to be turned ON more strongly (both due to stronger gate-bias as well as its own lesser than nominal Vth) which will cause the drain-voltage of N4 to reduce further and hence, reduce VA as well.
Sentence 2: n4 and N5 form a positive feedback loop and provide magnified voltage variations to threshold variations across N4-N5.
Relationship: reasoning
Domain: Hardware
Sentence 1: Extracting assertions from the graph follows exactly the same approach as described above for the sequentially-composable relation.
Sentence 2: we end up with the assertions of the following form (provided that C .C is a cycle in the graph of _): `V ´ locCon.uentC : assert G¬ r.C .r Again, statically determining the con.ict free relation is a hard problem, so that there is an alternative syntactic check, which conservatively approximates the relation: r1 ¨= r2).
Relationship: reasoning
Domain: Hardware
Sentence 1: Since the required charge is provided by an on-chip decoupling capacitor, the voltage at the capacitor during discharge drops below the initial (power supply) voltage.
Sentence 2: the required charge during the entire switching event is Imax × (tr + tf ) f Qdis = = Cdec × (Vdd - V ), (4) C 2 where Imax is the maximum magnitude of the current load, tr and tf are the rise and fall times, respectively, Cdec is the decoupling capacitance, Vdd is the power supply voltage, and VC f is the voltage across the decoupling capacitor after the switching event.
Relationship: reasoning
Domain: Hardware
Sentence 1: System_type is, a) sqc for software-controlled cache, b) nc for base system, c) dc for data cache, and d) qc for queuing cache.
Sentence 2: sD1_70.sqc.32.fa indi­cates that a) the traffic type is single dominating queue taking 70% of the link capacity, b) system is software-controlled cache, c) the cache array size is 32, and d) it is fully associative.
Relationship: reasoning
Domain: Hardware
Sentence 1: For ex­ample, by using 0000 to indicate that the cache line is not in the cache, and 0001 to mean that the cache line is in the .rst way.
Sentence 2: we can represent valid and 15-ways with only 4 Access Time (ns) Energy (nJ) per Bank 2-HT 1-HT per Bank 2-HT 1-HT 1 Bank 8 Banks 0.2459 0.1377 0.1991 0.1844 0.0082 0.0020 0.0062 0.0059  -7% -5% Table 5: Access time and read energy for 1 and 8 banks, where the eTLB and the data-array are banked separately (2-HT), and together (1-HT) for a 32 kB, 8-way, 512 B micro-page TLC.
Relationship: reasoning
Domain: Hardware
Sentence 1: Given that wr¯(u, v) = w(u,v) + r¯(v) - r¯(u) = 1, we have w(u,v) + r¯(v) - 1= r¯(u).
Sentence 2: r '(u) = r¯(u), i.e., r = r¯is kept after the increase of r(u).
Relationship: reasoning
Domain: Hardware
Sentence 1: 4.3 Symbolic Implementation by BDDs Using dual rail encoding, we can encode the values of .and all desired operations on .by corresponding Boolean values and operations, respectively.
Sentence 2: canonical normal forms for propositional logic like binary decision diagrams (BDDs) [7, 41] lead to canonical normal forms for functions on ..To obtain an ef.cient implementation, we can therefore easily use BDDs for representing and manipulating these formulas.
Relationship: reasoning
Domain: Hardware
Sentence 1: PriSM partitions a cache in a similar way to PF, i.e., .rst choosing a partition (Partition-Selection) and then evicting from the selected par­tition (Victim-Identi.cation).
Sentence 2: priSM is supposed to suffer from the associativity degradation the same way as PF when the list of replacement candidates is shortened in the Victim-Identi.cation step.
Relationship: reasoning
Domain: Hardware
Sentence 1: Analyzing the different digital image processing algorithms mapped on DRIP datapath it is readily seen that a significant similarity level exists, which reflects in a huge number of static and semi-static PEs.
Sentence 2: we can map only the really needed elements to the reconfigurable fabric reducing resources usage significantly and, at the same time, minimizing the logic depth of the cells that leads to higher operational frequencies.
Relationship: reasoning
Domain: Hardware
Sentence 1: If thhe energy deteccted on channell is greater thann a Carrier-Sennse TThreshold (CSThhresh), the statioon must assume tthat the channel is bbusy, and defer.
Sentence 2: a small CCSThresh impliees that even noddes qquite far away fr om a transmittinng node shall dettect the channel as bbusy, and defer.
Relationship: reasoning
Domain: Hardware
Sentence 1: We note thatspectral decompositionisa crucial .rst­step for many sensor network applications such as acous­tic or seismic object classi.cation, event detection, and vibration monitoring [34, 4, 2].
Sentence 2: these ana­log circuits hold great promise for use in wireless sensor networks, and in this paper, we show di.erent ways to leverage these circuits.
Relationship: reasoning
Domain: Hardware
Sentence 1: This vector imposes the dependencies (1,O,...,O,In order to construct a time schedule for this example, O)T=(1,O,...,O,O,O,...,O)Tand l 1 m; ,O ,..., we group together the tiles that should be concurrently O)T=(1,O,...,O,1,O,...,O)T 1 mj in the Group Space.
Sentence 2: the Dependence matrix of the O,I l,O (1,O executed by the same SMP node.
Relationship: reasoning
Domain: Hardware
Sentence 1: (17) We proceed by assuming that the process according to which sector SEC is read/written is Poisson with parameter h given by (7).
Sentence 2: consequently, the process according to which sector SEC is read and the process according to which sector SEC is written are Poisson with parameters hr and hw , respectively, given by hr =(1 - rw)h, and hw = rw h, (18) the probability qr that SEC is read within an in­.nitesimal interval dt is given by qr " P(SEC is read within dt)= hr dt.
Relationship: reasoning
Domain: Hardware
Sentence 1: According to the Machinee Correctness TTheorem, the crritical­secction-level syncchronization exeecution is equivvalent to the shhared­varriable synchronnization and thhe shared-variaable synchronizzation exeecution is prooved to be ass same as thee original proogram.
Sentence 2: by maintaining thee execution ordder of critical se ctions ammoong simulated programs, the ccorrectness of mmulti-core simuulation is gguaranteed.
Relationship: reasoning
Domain: Hardware
Sentence 1: Let w1>w2> >wk> >wn be the sorted list of all edge weights, then wk will be the gain of the perfect matching found by the algorithm; moreover, there is no perfect matching of only edges with weights among {wi|i=1..k-1}, otherwise the algorithm would have terminated earlier.
Sentence 2: any perfect matching would have to contain at least one edge whose weight is among {wi| i=k..n}, thus of a gain no larger than wk.
Relationship: reasoning
Domain: Hardware
Sentence 1: If a glitch is propagated from gate c to gate v and the output value of gate u is 1 , the glitch will be logically masked by the controlling value 1 from gate u.
Sentence 2: the higher probability of going to cv(v) gate u has, the more likely glitches from gate v s fanin gates (except gate u) will be logically masked at gate v. we introduce this constraint to minimize the loss on logical masking as a result of wire removal.
Relationship: reasoning
Domain: Hardware
Sentence 1: It has been shown, for instance, that processvariations can cause up to 2000% variation in leakage current and 30% variation in frequency of a chip fabricated in 180nm CMOS technology [4].
Sentence 2: without properly addressing and predicting variations in devices and interconnects, the yield of chips can drop to unacceptably low levels due to timing violations or increased power consumption.
Relationship: reasoning
Domain: Hardware
Sentence 1: Switching processes in the PMC a) The CF vertically grows prior to set occurs, b) the CF laterally dissolves prior to reset The VHW (OFF to ON state transition) and the UHVHW ON to OFF state transition) processes of a PMC device are shown in Figure 1. x Under a positive bias, the top active electrode is oxidized, and the fast metal ions (Ag+ or Cu2+) drift toward the bottom electrode and form the CF.
Sentence 2: the CF vertically grows until it reaches the top electrode, at which time the set occurs.
Relationship: reasoning
Domain: Hardware
Sentence 1: Moreover, there are 7 SPECint codes that have so few misses that a perfect MHA (unlimited number of MSHRs, subentries, and bandwidth) makes not even a 5% perfor­mance impact in any of the architectures analyzed.
Sentence 2: we SPECint2000 SPECfp2000 256.bzip2 (bzip2) 188.ammp (ammp) 254.gap (gap) 173.applu (applu) 181.mcf (mcf) 179.art (art) 253.perlbmk (perlbmk) 183.equake (equake) 177.mesa (mesa) 172.mgrid (mgrid) 171.swim (swim) 168.wupwise (wupwise) Mix 179.art, 183.equake (artequake) 179.art, 254.gap (artgap) 179.art, 253.perlbmk (artperlbmk) 183.equake, 253.perlbmk (equakeperlbmk) 177.mesa, 179.art (mesaart) 172.mgrid, 181.mcf (mgridmcf) 171.swim, 181.mcf (swimmcf) 168.wupwise, 253.perlbmk (wupwiseperlbmk) Table 6.
Relationship: reasoning
Domain: Hardware
Sentence 1: To address this issue, a de.nition of p at the level of a digital building block (e.g., an adder) is considered basedonathreshold d. Informally, the threshold d desig­nates a maximum tolerable deviation in magnitude between the expected and observed output of the primitive.
Sentence 2: errors that do not cause the magnitude of the output to vary from the correct value by more than d in magnitude are con­sidered to be correct.
Relationship: reasoning
Domain: Hardware
Sentence 1: In practice rd is much larger than Rl s where Cl s are comparable to Cin values.
Sentence 2: it is more important to have an accurate value for Cl s than for Rl s. For this reason, we use the Steiner points to obtain accurate values for the capacitance of partial nets (Cl s), but use the minimum bounding box to derive the resistance of the whole net.
Relationship: reasoning
Domain: Hardware
Sentence 1: A.1 Instrumenting Parallel Applications HRM organizes instrumented applications in groups, where each group is a set of tasks cooperating on a certain activity (e.g., en­coding a video) that is bound to a SLO.
Sentence 2: to properly use libhrm, a multi-threaded application must: (1) attach its tasks (i.e., threads) to a group; (2) set the SLO;4 (3) emit one heartbeat upon completion of a unit of work; and (4) detach its tasks from the group upon termination.
Relationship: reasoning
Domain: Hardware
Sentence 1: Adaptive Set Pinning architecture.
Sentence 2: the policy of allocating ownership of sets to processors that is described in the previous section is based on a .rst come .rst serve allocationpolicy.Thissimplepolicy couldpotentiallyresult Incase1,theindexedsetisinitspristinestateandisnot owned inanunfairdivisionofthesetsinthesetpinnedL2cache.The by anyprocessor.inadditiontobringingthereferenced issueoffairnessinacquiring ownershipisaddressedby ournext datafrommemory,theowner.eldalsoneedstobeset.Consider approach called adaptivesetpinningdescribedhereindetail.
Relationship: reasoning
Domain: Hardware
Sentence 1: The comparative results are shown in Figure 9 based the areas of the 3T1D, 4T/4TI and 4T1D cells (given by 1162.2, 1304.2 and 1531.2, respectively) as well as the areas of 3T [21], 6T [21], 7T [24] and 8T [25] cells.
Sentence 2: the SRAMs account for a significant area penalty.
Relationship: reasoning
Domain: Hardware
Sentence 1: For part of the noise: based on the fact that differencing two Gaussian variables results in a new Gaussian variable with twice of variance, the noise energy is magnified, which also helps to improve the estimation precision.
Sentence 2: the noise variance can be estimated as: 1 N NG 1 -- m2 2 m m 2 W .= - ()|) k s = s ( y) (| y' ()k y' .
Relationship: reasoning
Domain: Hardware
Sentence 1: Since the distribution of Lg depends on the distribution of space Spoly between adjacent gates, delay tb(e) has a correlation with the delay of the edge corresponding to the adjacent transistor.
Sentence 2: we introduce a correlation between delays tb(e') and tb(e") of edges e' and e" which correspond to transistors with the same type in a logic gate, and denote the coefficient of correlation between these delays by .b(e',e").
Relationship: reasoning
Domain: Hardware
Sentence 1: When custom DM managers are used, their designs are manually optimized by the developer, typically consider­ing only a limited number of design and implementation alternatives due to the lack of formal methodologies to ex­plore the DM management search space.
Sentence 2: designers must de.ne, construct and evaluate new custom implemen­tations of DM managers and strategies manually, which has been proven to be programming intensive (and very time­consuming).
Relationship: reasoning
Domain: Hardware
Sentence 1: Circuit Regs Paths Longest OCSS PB s3271 116 1688 3.38 2.02 1.57 s3384 183 1937 6.53 5.18 3.27 s4863 104 1144 11.46 10.30 6.10 s6669 239 2481 17.39 14.79 4.99 s9234 228 3256 7.38 4.88 4.59 s13207 669 4660 8.80 6.59 5.37 s15850 597 16863 11.02 8.43 5.93 s35932 1728 5113 3.99 3.82 3.36  Note that, in each benchmark circuit, both RCA clock skew scheduling and [5] achieve the same results.
Sentence 2: table 2 only compares their time complexities.
Relationship: reasoning
Domain: Hardware
Sentence 1: In Figure 13, compared with the power consumption of the fault­tolerant bus without any sub-bus partitioning, the power consumed by the bus with parity partitioning without shielding insertion (perm+ spacing + partitionparity)is 3% 13% less.
Sentence 2: parti­tioning parity can reduce the extra power consumption caused by the coupling capacitances of non-adjacent bus lines.
Relationship: reasoning
Domain: Hardware
Sentence 1: The matrix-vector product 0 gg 0 g g y = A · x can be achieved by solving -GT y = CT x or 0T 0 0 TT T -U L y = C x .
Sentence 2: the cost of the algorithm is linear g g 0 in both the moment matching order k and the number of variational parameters n , and almost linear in the number p of circuit nodes.
Relationship: reasoning
Domain: Hardware
Sentence 1: For a single environment the .tness value is de­termined as f = f (2) + f (4) + f (6) + f (8) for even-input circuits and f = f (3) + f (5) + f (7) + f (9) for odd-input circuits, where f (i) is the number of correctly processed testing sequences by the circuit with i inputs.
Sentence 2: the maximum .tness value that we can reach is fmax = 22 + 24 + 26 + 28 = 340 for even-input circuits and fmax = 23 + 25 + 27 + 29 = 680 for odd-input circuits.
Relationship: reasoning
Domain: Hardware
Sentence 1: Coefficients {30093, -2423, 2726, 3140, 1564, 762} are computed at the 4th level whereas the other coefficients are computed in between levels 1-3.
Sentence 2: in case of delay variations where the 4th level outputs are not computed properly, the characteristic of the filter would be severely affected because 30093 is the most important coefficient to determine the filter response.
Relationship: reasoning
Domain: Hardware
Sentence 1: We require that the weights sum up to one, i.e., aj + ßj = 1, in which case the Equation 1 can be seen as an instance of Bayesian model averaging.
Sentence 2: given the action si of node i, on average the node j forwards sj,i si packets, where the probability sj,i changes as a function of available energy and actions of node i.
Relationship: reasoning
Domain: Hardware
Sentence 1: Compared to other emerging non­volatile memories such as Magnetic RAM (MRAM) and Ferroelec­tric RAM (FeRAM), PCRAM memory has excellent scalability, which is critical to the success of any emerging memory technolo­gies.
Sentence 2: much R&#38;D activity in industry, including at IBM, Intel, Hitachi, ST Microelectronics, and Samsung, has been onPCRAM technology [1,3,5,7,9,15,16,18,24].
Relationship: reasoning
Domain: Hardware
Sentence 1: With respect to propagation of delay, we shall say that a full adder does not transfer the generated delay to the adjacent higher order full adder if two current input to a full adder A and B are equal since CarryOut is determined by only A and B without respect to CarryIn.
Sentence 2: if Ai=Bi, n­bit ripple carry adder can be divided into independent subsequent parts that can operate in parallel.
Relationship: reasoning
Domain: Hardware
Sentence 1: Before proceeding, note that the workload prediction is trivial for a leaf PR; it must be equal to its WCEC otherwise the deadline is not met for the worst-case.
Sentence 2: when there is only one PR for a program, the performance level will be adjusted to f = WCEC / T at the program entry where T denotes the deadline or timing constraint, which is identical to applying inter-task DVS methods.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then, the variable pi,j has the following property: if pi,j =a works with clock period PINS(k), pi,j = a also works with clock period PINS(k), where 0 d a d a d ai,j; if pi,j =a does not work with clock period PINS(k), pi,j = a also does not work with clock period PINS(k), where 0 d a d a d ai,j.
Sentence 2: we can use the binary search strategy to find the minimum value of variable pi,j, where the interval of binary search is [0,ai,j].
Relationship: reasoning
Domain: Hardware
Sentence 1: The naïve method to add k > 2 integers is to use an adder tree, i.e., a binary tree of CPAs; a compressor tree (e.g., a Wallace or Dadda Tree) is a circuit that uses carry-save addition to add k > 2 integers: the output is two integers, S (sum) and C (carry) such that S+C is the sum of the k integers.
Sentence 2: a CPA is only required to add S and C, rather than at every level of the tree.
Relationship: reasoning
Domain: Hardware
Sentence 1: Nanoelectronics will potentially change the way computing systems are designed, not only because of the sheer number of devices that will coexist onto the same chip, but also because of the sensitivity of these devices.
Sentence 2: if nanoelectronics is to be employed to build dependable computing machines (a certain contradiction notwithstanding), valuable expertise in design can be drawn from natural sciences.
Relationship: reasoning
Domain: Hardware
Sentence 1: The level shifter provides equal voltages at its emitter terminals to produce equal collector-emitter voltages at the simple current mirror s transistors.
Sentence 2: in addition to the sizing rules of this build­ing block s sub-blocks, the number of transistors in parallel in the level shifter has to be the same as in the simple current mirror, which leads to the following additional sizing rules: FG1: Nls(1) =Ncm(1) (14) FG2: Nls(2) =Ncm(2) (15) 3.3.3 Wilson Current Mirror Like the cascode current mirror, this building block has a higher output impedance than a simple current mirror.
Relationship: reasoning