sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: In addition, modules are capable of performing some logical operations on their input values.
Sentence 2: the module is selected to perform one of the following functions on their input signals: - output = left input (shift right) - output = right input (pass without shift) - output = (left input AND right input) - output = (left input OR right input) - output = (left input XNOR right input) - output = (left input BYTE-WISE-OR right input) - output = (left input BYTE-WISE-AND right input)  The utility of each these operations will be examined during the discussion of the applications in the following subsections.
Relationship: entailment
Domain: Hardware
Sentence 1: Together, these approaches also support performance portability, as currently investigated in the EU FP7 project PEPPHER.
Sentence 2: we consider (1) a library-based approach, here represented by the integration of the SkePU C++ skeleton pro­gramming library with the StarPU runtime system for dynamic scheduling and dynamic selection of suitable execution units for parallel tasks; (2) a language-based approach, here represented by the Of.oad-C++ high-level language extensions and Of.oad compiler to generate platform-speci.c code; and (3) a component­based approach, speci.cally the PEPPHER component system for annotating user-level application components with perfor­mance metadata, thereby preparing them for performance-aware composition.
Relationship: entailment
Domain: Hardware
Sentence 1: This proposal is accepted as the t+1 ' next value (x = x)if a drawn from U(0, 1) satis.es j 't'.
Sentence 2: p (x)Q(x ; x) a< min , 1 , (3) P (xt)Q(x'; xt) acceptance is likely if the proposal state is more probable than the last state.
Relationship: entailment
Domain: Hardware
Sentence 1: EME RGING NON-VOL AT IL E MEM O RY TE C HNOL OGIE S Technology scaling of SRAM and DRAM (which are the common memory technologies used in traditional memory hierarchy) are increasingly constrained by fundamental tech­nology limits.
Sentence 2: the increasing leakage power for SRAM/DRAM and the increasing refresh dynamic power for DRAM have posed challenges for circuit/architecture designers for future memory hierarchy design.
Relationship: entailment
Domain: Hardware
Sentence 1: Figure 5 illustrates an example of the issue and our proposed solution.
Sentence 2: it illustrates the case when x >> 9 is added to x >> 7 when two bit-slices of x are Original Data ( x ) sign data bits b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 sign Input ANDing ( x' ) b12  x' >> 9b11 b11 m MUX x' >> 7 b9 b9 b12 b11 b10 Implementation Figure 5.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.4 Comparisons With Existing Methods In this .nal set of experiments, we compare the proposed ther­mal management method with state-of-the-art convex-based ther­mal management techniques, in the case of time varying workload requirements.
Sentence 2: we have implemented for the compar­isons the Pro-Temp technique described in [5], where we chose the frequency to satisfy the maximum workload requirements, while the maximum chip temperature is taken into account.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION Higher semiconductor technology integration due to ge­ometry scaling opens the door to new market segments.
Sentence 2: technology evolution enables adding some degree of intelligence to any control or measuring engine such as environment sensor applications to monitor wind, sea level, Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: entailment
Domain: Hardware
Sentence 1: During each round of scheduling, if the latency-sensitive queue does not use up its allocated bandwidth, the residual bandwidth is used by the repay credit counter.
Sentence 2: whenever the repay-Credit is greater than 1, and the debtQ is not empty, the CBR pops the debtQ, increments the ............ corresponding to the popped ID, and decrements the repayCredit.Lowla­tency queues can then use their debit credits to extend their service time.
Relationship: entailment
Domain: Hardware
Sentence 1: Based on our earlier experience with placement and x 104 Amount of Redundancy in Number of SRAM Cells (x) Figure 6: The area of a 2-stage 30X1 multiplexer without any redundant SRAM cell(x1), and with 2x, 3x, and 6x additional SRAM cells in stage 1. routing experiments with benchmark circuits in VPR, we observed that typical routing utilization was in the range of 50% - 70% in FPGA [13].
Sentence 2: 30% - 50% resources in routing and connection switches are not being used.
Relationship: entailment
Domain: Hardware
Sentence 1: Or t Cj = ³ ( t)Pij td (3) Ci t () t 0 Max Operation: Let A be the max of arrival time as node a( A) and o a arrival time at node b( Ab ).
Sentence 2: ao = max Aa,Ab) (4) ( The CDF at node o can simply be given by C()t= C()tCb()t(5) o a the CDF of the maximum of two independent random variables is simply the product of the CDF of the two variables.
Relationship: entailment
Domain: Hardware
Sentence 1: Second, since in F2BFLY a .it only takes at most 1 hop in each dimension, an incoming .it that is currently traversing in the row/column dimension will not continue to traverse in the same dimension.
Sentence 2: an incoming .it using the row dimension will either turn to the column dimension or go to the ejection port; an in­coming .it using the column dimension will de.nitely go to the ejection port (it cannot turn to the row dimension with XY-routing).
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we focus on building upon and improving these known techniques through a scalable REC approach, resulting in e.cient design of large-scale datapath networks from the DSP domain.
Sentence 2: we leverage the em­pirical evidence that inexact logic minimization yields error distributions that are (approximately) gaussian and there­fore, minimizing the mean value of these error distributions (when variance is kept constant) will improve the SNR in the context of DSP hardware.
Relationship: entailment
Domain: Hardware
Sentence 1: For case two, the worst-case performance corner may be given by Pmin or Pmax while the best case corner is given by PminGL.
Sentence 2: for case two, it is not possible to saybeforehand on which side the worst-case corner lies because the slope of the graph shown in Figure 7 may be different on each side, i.e., the slope of the curve on the right to PminGL may be higher or lower than the slope to the left of PminGL.
Relationship: entailment
Domain: Hardware
Sentence 1: The configuration of the first row decoder can be any of the four possibilities: 0x, x0, 1x, x1, correspondingly, the second row decoder of subarray 3 must be 1x, x1, 0x, x0, respectively.
Sentence 2: if the first row decoder is 0x, then the second row decoder of subarray 3 must be 1x.
Relationship: entailment
Domain: Hardware
Sentence 1: The procedure outlined in Algorithm 2 is inadequate, however, where a minimum ripple height RHmin has to be observed.
Sentence 2: we have found that a simple search and compare proce­dure is adequate to .nd an RH such that Lo = Lmax .an interval in RH is divided into a number of steps, and the RH at each step is submitted to a procedure executing Algorithm 3.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper we propose the idea of chaining localized streams in order to both partially reconstruct the chronological information in the miss stream and to build longer streams, while maintain­ing a higher miss prediction accuracy derived from localization.
Sentence 2: we apply this idea which we call Stream Chain­ing to a PC localized prefetcher and we show one scheme for chaining streams, which we call Miss Graph prefetching.We show that this scheme captures well common application behavior and we show that it can be easily implemented on a simple extension to the Global History Buffer (GHB) [12], which is a convenient structure to implement various prefetching algorithms.
Relationship: entailment
Domain: Hardware
Sentence 1: In section 3, we will show that the optimal window size of a SEFF is equal to the borrowed time in the preceding pipeline stage.
Sentence 2: in the optimal linear pipeline design, data arrives at the end of the transparency window of the SEFF, and as a result, the output of the SEFF is valid after a data to Q delay with respect to the end of transparency window, i.e., after w + t with respect to the dq clock edge.
Relationship: entailment
Domain: Hardware
Sentence 1: {LTI , NTI }, where LTI , NTI are computed according to the instructions using the output of I (de­noted from now on as uses of I).
Sentence 2: lTI and NTI are computed as the element-wise inclusive-or of the opcode-dependent linear and nonlinear contribu­tions (contLT (J) and contNT(J), respectively) of all the uses J of the output variable of I:  NTI =contNT(J), LTI =contLT (J) .J.uses(I) .J.uses(I) The contributions contNT(J) and contLT (J) take into account the part of the partial decryption function Ef -1 performed by the inversion of J.
Relationship: entailment
Domain: Hardware
Sentence 1: On the other hand, if the back-off factor is increased from one process generation to the next, the delay, noise and slew metrics worsen significantly even when normalized to the (already degraded) optimal metrics achievable in the scaled interconnect.
Sentence 2: while a back-off can improve the buffer count, it can be exploited only once and today s designs have already made use of it.
Relationship: entailment
Domain: Hardware
Sentence 1: Therefore, from the initial partitioning, we find the best mergeable pairs of partitions whose merging will result in a better circuit im- plementation in terms of area and power.
Sentence 2: we compute the goodness of a merging using a cost met- ric which considers the gain of the merging in terms of area and power compared with the area and power before the merging.
Relationship: entailment
Domain: Hardware
Sentence 1: Analyzing 48 recordings from PhysioNet s MIT-BIH Ar­rhythmia[8] database, weestimatedthatanoracle scheme that provided an accurate prediction of the occurrence of each QRS complex would lead to an ideal sensor duty cy­cle of 11.5±3.5% (variation across the traces).
Sentence 2: by turning on the AFE at the right moment and keeping it powered11% of the time, eachQRS complex couldbe cor­rectly detected, extracted and communicated.
Relationship: entailment
Domain: Hardware
Sentence 1: In fact, di.erently from random-based ATPGs, a determinis­tic ATPG needs to exploit the structural information embed­ded in the description of the DUV to explore its state space.
Sentence 2: the SEFSM model is specially suited to be used with ATPGs that generate test sequences by determin­istically activating the enabling functions of the transitions.
Relationship: entailment
Domain: Hardware
Sentence 1: Our target application is to provide an alternative to manual note-taking in multiparty meetings, providing additional functionality to what is available in the typical set of notes.
Sentence 2: since spoken language in­cludes signi.cant useful information besides the words, e.g., speaker identity and emotional a.ect (signi.cantly cued by speaker intonation), enabling search through the complete audio record can be much more useful than a simple tran­scription.
Relationship: entailment
Domain: Hardware
Sentence 1: Since these are also used for route-through connections, this is larger than the number of logical pterms in each logic block.
Sentence 2: pp = P +2 × Wseg + F (1) in addition to the P logical pterms, we may need one physical wire for each signal that routes through the array for bu.ering; there will be at most Op of these.
Relationship: entailment
Domain: Hardware
Sentence 1: The distribution of transactions : total transaction / non-bus transaction types master0 master1 master2 master3 m_type5 70% / 75% 10% / 0% 10% / 0% 10% / 0% m_type6 40% / 75% 40% / 75% 10% / 0% 10% / 0% m_type7 30% / 75% 30% / 75% 30% / 75% 10% / 0% m_type8 25% / 75% 25% / 75% 25% / 75% 25% / 75% -In Table 4, the transaction of the masters with long job length is mostly non-bus transactions.
Sentence 2: the majority of the masters have internal job.
Relationship: entailment
Domain: Hardware
Sentence 1: (1) starting from the state ORIG (S0) : One_S0 = {S0 HBURST==0 ;{S4[=0]}&#38;&#38;{S1[Æ1]}};  (2) starting from the state NSEQ/SEQ (S1) : One_S1 = {S1 HBURST==0 ;{S4[=0]}&#38;&#38;{S1[Æ1]}};   The 1-beat burst transaction is composed of the sequence One_S0 and the sequence One_S1 by using a sequence OR operator.
Sentence 2: one = {{One_S0} | {One_S1}}; Example 2 4-beat burst transaction.
Relationship: entailment
Domain: Hardware
Sentence 1: In our experiments, each of these pro­gramsisexecutedusing8 threadsand, therefore,onetoeight cores can be allocated to each application by our proposed control centric scheme(1 = c i(k)= 8), since it is not bene.cial from the perfor­mance and utilization perspectives to allocate more than eight cores to an application with eight running threads (note that, the number of threads does not change during execution when using METE).
Sentence 2: the number of threads of a running application indi­cates the maximum number of cores that can be allocated to it.
Relationship: entailment
Domain: Hardware
Sentence 1: The difference is that the NoCAlert checkers will raise permanent/prolonged (rather than momentary) assertions upon the occurrence of a permanent/intermittent fault.
Sentence 2: since the NoCAlert checkers raise an exception upon an invariance viola­tion, NoCAlert s performance/accuracy is orthogonal to whether the invariance is temporary or permanent; as soon as the invariance vi­olation commences, NoCAlert will detect it.
Relationship: entailment
Domain: Hardware
Sentence 1: Speci.cally, the set of PI assignments that makes the output value of f stablize no earlier than time t = 0 is characterized by a (no-early) TCF, denoted .f,t .
Sentence 2: a PI as­signment satisfying .f,t makes the output value of f remains unknown (under the .oating-mode assumption) until time t. When the stablization value of f is speci.c to value 0 (respec­tively 1), the corresponding 0/1-speci.ed TCF is denoted as .f=0,t (respectively .f=1,t).
Relationship: entailment
Domain: Hardware
Sentence 1: However, the adver­sary cannot perform attacks that require complete unscru­tinized access to the CPU for extended periods of time.
Sentence 2: this implies that the service provider has organi­zational procedures in place to prevent attacks, but cannot guarantee the absence of a small set of rogue employees.1 We consider denial-of-service, side-channel, and fault injec­tion attacks beyond the scope of this paper.
Relationship: entailment
Domain: Hardware
Sentence 1: With the Stratix-II architecture [2], Altera introduced a new logic architecture, which allows the 6-input LUTs (6-LUTs) to be decomposed into smaller LUTs that share several inputs.
Sentence 2: two 3-LUTs can be organized to compute the carry and save functions of a CSA, which acts as a 3:2 compressor; in conjunction with the carry chain, the logic block can be configured as a ternary CPA.
Relationship: entailment
Domain: Hardware
Sentence 1: CONSTRUCTING PROBABILISTIC REGRESSION SUITES Suppose, for example, we conducted massive simulations with many different parameter sets (speci.cation .les), achieved satis­factory coverage, and would like to maintain only the sets of pa­rameters that are most important.
Sentence 2: from a large repository of parameter sets we wish to select a subset that is as small as possible, yet capable of producing similar coverage.
Relationship: entailment
Domain: Hardware
Sentence 1: We present an automated 3D microarchitecture evaluation flow (MEVA-3D) that can be used to compare and contrast 2D and 3D implementations of a given architecture.
Sentence 2: we make the following contributions in this work: This research is supported by the National Science Foundation under Grant CCR-0096383 and DARPA under Prime Contract DAAH01-03-C-R193 through CFDRC Corporation.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition to the reduced memory tra.c provided by our caching scheme, the ISB enjoys several other signi.cant bene.ts: Improved Prediction Capability: Unlike GHB-based so­lutions (see Section 3), the ISB can use PC localiza­tion, a technique that segregates the prefetcher input into multiple streams based on the PC of the loading instruction, which is known to improve coverage and accuracy [28, 39, 38, 25].
Sentence 2: the ISB can combine PC localization and address correlation be­cause any PC-localized temporal stream is stored con­secutively in the on-chip address cache (see Figure 2), i.e., the localization is performed before physical ad­dresses are translated to structural addresses.
Relationship: entailment
Domain: Hardware
Sentence 1: Although other promising approaches can be considered, the variables used are derived from a clas­sical high-level synthesis procedure.
Sentence 2: among information like loop nesting, number of code lines, input and output counts and size, variables lifeness, control steps, etc., the selected subset only includes the number of control steps, number of control inputs, number of control outputs, number and size of data registers, number and size of mul­tiplexers and number, type and size of operators.
Relationship: entailment
Domain: Hardware
Sentence 1: The goal of this paper is to propose different arrange­ments (simplex and duplex) for a memory system which utilizes RS codes as EDAC; the objectives are to achieve re­silience to both transient and permanent faults and retaining data integrity.
Sentence 2: the duplication of the mem­ory modules (duplex) allows to cope with the occurrence of permanent faults, while the RS coding and the periodic execution of scrubbing allow to reduce the impact of tran­sient faults.
Relationship: entailment
Domain: Hardware
Sentence 1: We can see that the ATCache achieves 10.3% speedup without MAP-I predictor and 11.9% with the predictor while consuming only 47.375kB (without MAP-I) and 48kB with MAP-I (256 entries).
Sentence 2: we are able to do almost as well as tags-in-SRAM while consuming 0.5% SRAM overhead compared to a tags-in-SRAM design.
Relationship: entailment
Domain: Hardware
Sentence 1: [9] Proposed comparison ( 1,949,487 0 +1,949,487 sum 0 347,036 -347,036 C 1,949,487 1,695,501 +253,986 A 1,301,845 0 +1,301,845 .C 0 40,395 -40,395 Total saving +3,117,887 Furthermore, in the proposed SDMP scheme, C value is only required in row operation for the calculation of .C, while in former MP scheme, message C is accessed at both row and column operation.
Sentence 2: in former MP scheme, message C should be accessible by both row and column address, while in SDMP, a row of message C can be stored in a single memory line, thus saving control logic and area.
Relationship: entailment
Domain: Hardware
Sentence 1: We assign a distinct type for each group, Si, i = 1,..., k.We use labels: A,B,C,...,to represent theirtypes.AnI/O port in a group Si possesses the type of Si.
Sentence 2: we say I/O ports of each chip are evenly divided into k groups of size m such that (i) type(S1), type(S2), ...., type(Sk) are pairwise distinct; (ii) size(S1)= size(S2) =...= size(Sk)= m. In terms of the number of terminals per net, two kinds of board­level routing problems (BLRPs) are identified: (i) two-terminal BLRP where all nets are two-terminal nets; and (ii) multiterminal BLRP whereat least onenet hasmorethantwo terminals.
Relationship: entailment
Domain: Hardware
Sentence 1: .. .. 2 ............h .. = .......... = ........ (.... - .... ), (5) where ..........h denotes the graph of the original system, ...... denotes the spanning-tree support graph after scaling, ...... denotes the edge conductance between nodes .. and .. of the original spanning-tree support graph ......,and .. denotes the scaling factor to be found.
Sentence 2: note that the original support graph consumes less power than the original graph, thus the scaling factor is always greater than one.all the wires (edges) of the spanning tree are sized up to form a more conductive spanning-tree support graph, as shown in Fig.3.
Relationship: entailment
Domain: Hardware
Sentence 1: {1,2,...,l}, is assigned a weight wi such that f assumes the value 1 when the weighted sum of its inputs equals or exceeds the value of the function s threshold, T [3].
Sentence 2: l 1 ifi=1 wixi =T +don f(x1,x2,...,xn)= l (1) 0 ifi=1 wixi <T -dof f , Parameters don and dof f represent defect tolerances that must be considered since variations (due to manufacturing defects, tempera­ture changes, etc.)
Relationship: entailment
Domain: Hardware
Sentence 1: In this study, the four key aspects we identi.ed earlier are idealized and the in­struction window size is varied from 128 up to 2048.
Sentence 2: for an instruction window size of 1024, the scheduling window size is 1024, the store queue and register .le are sized ideally, and the rename map table is available instantaneously for branch misprediction recovery.
Relationship: entailment
Domain: Hardware
Sentence 1: Let I+ = I + (0 0 0 0 1)T, where + denotes vector addition.
Sentence 2: in order to have bank locality, the array elements accessed by I equation is m11 = 1 and m12 = -1, which can subsequently be completed to a full data transformation matrix - .... 1 1 it is possible to find an M matrix to satisfy intra-reference bank locality.
Relationship: entailment
Domain: Hardware
Sentence 1: We also validated our recovery approach using a set of real exploits against the selected popular server applica­tions.
Sentence 2: exploit codes or scripts are collected from various   Percentage of Requests After Filtering % Figure 9: L1 instruction cache miss rate 10 1.6  Normalized Service Response Time 8 6 4 2 032-entry 64-entry Queue Entry Size Figure 10: E.ectiveness of Code Origin Check Fil­tering hackers websites or security agent websites.6 we launched remote exploit attacks targeted for the fol­lowing server vulnerability, CVE documented attack CAN­2003-0651 [1] on HTTP server, exploit (VU#196945) [4] on bind daemon, documented exploits (CAN-2003-0466) [1] on FTP server, and documented exploit (CAN-2004-0640) [1] on SSLtelnet daemon.
Relationship: entailment
Domain: Hardware
Sentence 1: This sharing information is collected pro-actively: when coherence activities are initiated on a cache line within a region, we make use of additional wires in the interconnection to collect the sharing status of all regions within the page, including other regions that are not directly affected by the coherence activity.
Sentence 2: the main contributions of this paper are as follows: We propose a snoop traffic filtering technique that makes use of coarse-grained sharing information on the basis of regions within a page, pro-actively collecting the sharing information of all regions within a page during snoop activities on any line within that page.
Relationship: entailment
Domain: Hardware
Sentence 1: As a result, the locality constraints above should be re-written in terms of X (i.e., they need to be re-mapped).
Sentence 2: after the propagation, we re-write the constraints as: )))) 10u0 01u0 Mx = and Mx = 01u110u1 Now, solving Mxfrom these constraints is more dif.cult as Mx is involved in both the equalities.
Relationship: entailment
Domain: Hardware
Sentence 1: Rodrigo Laiola Guimarães CWI: Centrum Wiskunde &#38; Informatica Science Park 123 1098 XG Amsterdam, The Netherlands +31 20 592 93 33 rlaiola@cwi.nl ABSTRACT This thesis aims to analyze, model, and develop a framework for next-generation multimedia authoring tools targeted to end-users.
Sentence 2: i concentrate on the combination of automatic and manual processes for the realization of such framework.
Relationship: entailment