sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: It is important to clarify that at this stage we are interested only in the implication discovery process, while the process of trim­ming the list trying to get rid of weak implications might actually hinder our purpose.
Sentence 2: the authors of [1] consider as weak, those implications that can be included in other implications and implications where the implicant and the implicand can be de­rived from a common node; while these implications can be dis­carded for online error detection, theymight be critical for .nding a path between the primary outputs and the primary inputs.
Relationship: entailment
Domain: Hardware
Sentence 1: In the foregoing discussion, we assume that the pro­cessor includes a simple instruction re-execution mecha­nism, whereby the memory unit can drop an executing load or store and place the instruction back on the scheduler s ready list.
Sentence 2: loads and stores that are unable to complete because of structural con.icts in the SFC or the MDT may be re-executed.
Relationship: entailment
Domain: Hardware
Sentence 1: First, during testing but before fabri­cation2, these dynamic checks will ensure that security vio­lations are revealed to the hardware designers as functional­ity bugs, which the modern design process already has many techniques for detecting and dealing with.
Sentence 2: sapper transforms the problem of detecting security viola­tions during testing (for which there is little support and experience in the modern design process) into the problem of detecting functionality bugs during testing (for which there is a great deal of support and experience).
Relationship: entailment
Domain: Hardware
Sentence 1: While the domain decomposition method has been successfully demonstrated with high efficiency for several practical applications, it is only applicable to a limited set of power grid analysis problems where a direct solver (i.e., Cholesky decomposition) is used.
Sentence 2: the domain decomposition method proposed in [13] becomes inefficient, or even inapplicable, if the multi-grid algorithm [3]-[6] or the randomized algorithm [7]-[8] is used as the core numerical engine for large-scale power grid analysis.
Relationship: entailment
Domain: Hardware
Sentence 1: If a decoder is able to address all 2NA subsets of a set of NA NW, the set of NWs is said to be fully addressable.Given a set of NA NWs and a set of NA MWs, we say the sets are uniquely coupled if each of the NA NWs is controlled by a unique MW.
Sentence 2: each of the NA MWs provides individual control over a distinct NW.
Relationship: entailment
Domain: Hardware
Sentence 1: Instead, let us consider the comparison of WSN channels under a .xed loss function.
Sentence 2: an experiment Ma is better than an experiment Mb for a given loss function L and all possible priors if .p,R * (L, p)=R * b(L, p), and one a could further consider comparing the Bayes risks under a .xed loss function and a .xed a-priori distribution p. Under this relaxed point of view, Sakaguchi [13] showed that, if A = {0,1} and if we adopt the 0-1 loss function L0-1(.,a)=1{.
Relationship: entailment
Domain: Hardware
Sentence 1: Although the space requirements of our implementations are near optimal when a single LL/SC variable is imple- mented, our present algorithms do not extend well when the number of LL/SC variables to be supported is large.
Sentence 2: in order to implement M LL/SC variables using CAS or RLL/RSC instructions, our algorithms re-quire O(M) space per process (which amounts to O(NM) space among all N processes).
Relationship: entailment
Domain: Hardware
Sentence 1: The separation of concerns does not only provide a better the­oretical understanding of existing CAOS languages and synthesis tools such as Bluespec, but it also has many practical advantages: The representation as synchronous guarded actions allows us to carry out many analyses and optimizations known from the syn­chronous domain.
Sentence 2: speci.cation and veri.cation based on temporal logics becomes possible.
Relationship: entailment
Domain: Hardware
Sentence 1: While effec­tive in many cases, such time-borrowing techniques have the inherent weakness of error effect propagation.
Sentence 2: even if a suspicious FF can borrow some time from its successive logic level, the timing slack of this level is reduced and hence some initially non-suspicious .ip­.ops in this level may become suspicious ones and need to be replaced by sequential elements with time-borrowing capability again.
Relationship: entailment
Domain: Hardware
Sentence 1: always arrives earlier than (and is waiting for) ayw., i.e., the next iteration is throttled due to the late completion of the handshake reset phase of the previous iteration, resulting in a bottleneck; the GCP is: (rsv., axv., rxw., ayw., rys.)*.
Sentence 2: if no bottleneck exists, then a stage should process its inputs as soon as they all arrive.
Relationship: entailment
Domain: Hardware
Sentence 1: As can be seen from the .gure, our data recomputation based approach is quite effective for our bench­mark codes, when the on-chip SPM size falls between 1/6th and 3/6th of the total application data.
Sentence 2: there is a certain range for the (To­tal SPM size)/(Total Data Size) ratio for which our approach generates the best results.
Relationship: entailment
Domain: Hardware
Sentence 1: As we are not making any assumptions about the structure of a,we will consider the least-squares estimate *-1 a =(FbmFmb)Fbmy, * where Fbm is the adjoint (conjugate transpose) of Fmb.The stabilityofthisrecoveryiscompletelycharacterized bythe singular values of F * To have con.dence in our estimate mb.
Sentence 2: * a ,we would like Fmb to be well-conditioned.we would like the spectrum (the set of singular values) of F * mb to consist of b non-zero values that are all about the same size.
Relationship: entailment
Domain: Hardware
Sentence 1: In this representation, large se­quences of ones get replaced by (1, 0, -1) Suppose, we start representing k in binary and ks = ks+1 = ks+2 ... = ks+t-1 = 1 and ks+t = 0.
Sentence 2: an expansion for some (t>= 1), with t consecutive ones can be real­ized as 2s(2t - 1) = 2s+t - 2s [7].
Relationship: entailment
Domain: Hardware
Sentence 1: Since the reliability of the ASK-OOK modulation is related to the energy per bit, Eb, spent to reach the receiver s antenna, we can determine the power required by the transmitter for each value of attenuation Ga.
Sentence 2: for the ASK-OOK modulation the bit error rate can be computed as:  Eb BE R = Q (3) N0 where N0 is the transceiver noise spectral density and the Q function is the tail probability of the standard normal distribution.
Relationship: entailment
Domain: Hardware
Sentence 1: There can be at most v 4 max max 2kv4 of them.
Sentence 2: .v min 2kv4 |Fbig |= max (7) Ev4 min Otherwise, the total power (the sum of power over all partitions) is greater than ELv2 2kv4 2kLv2 min max max 2 · = 2 , (8) vmax Ev4 v min min which is obtained assuming that all the functional units have the voltage level vmin .
Relationship: entailment
Domain: Hardware
Sentence 1: It is interesting to note that the communication strat­egy used in our approach lies in-between that of the ba­sic latency-insensitive approach and the recently proposed network-on-a-chip (NoC) approach [1].
Sentence 2: noC s provide a higher level of communication abstraction, where data is organized as packets, and sophisticated protocols handle error recovery and .ow control.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.5 Start After Start (SAS) for duplicable tasks Given two duplicable tasks, A and B, possibly with no data dependence between their replicas, SAS(B,A) is aimed at specifying the level of synchronization ( lockstep ) between the two tasks.
Sentence 2: it specifies the permissible range of the number of replicas by which A s dispatching may advance over B s dispatching.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.ACCURACY In this section, wevalidatethatthe branch-on-random sbehavior is suitablefor instrumentationsampling.We consider thebranch­on-random s sampling suitable if it achieves accuracy similar to or better than software counter-based sampling.
Sentence 2: we demonstrate that no idiosyncrasies of the LFSR s behavior pre­ventit frombeing suitablefor useinsamplingprogram behaviors.
Relationship: entailment
Domain: Hardware
Sentence 1: In an idealized study (Section 2), we prove the ex­istence of cluster assignments and instruction schedules that yield performance almost identical to (within 2% of) the per­formance of an equivalent monolithic machine.
Sentence 2: we demonstrate that penalties observed by extant schemes are not inherent to the underlying hardware, but are entirely an arti­fact of the policies used to manage it.
Relationship: entailment
Domain: Hardware
Sentence 1: Thefirst part de­terminesif aparticularinstanceofmemcopy ormeminit canbe fully/partiallyacceleratedbyRowClone.Thesecondpartinvolves the changes required tothe cache coherence protocol toensure coherenceofdataintheon-chipcaches.Wediscussthesepartsin thissection.
Sentence 2: 4.2.1 Source/Destination Alignment and Size For the processor toaccelerateacopy/initialization operation usingRowClone,theoperationmustsatisfycertainalignmentand sizeconstraints.foranoperationtobeacceleratedby FPM,1)thesourceanddestinationregionsshouldbewithinthe samesubarray, 2)thesource anddestinationregions shouldbe row-aligned,and3)theoperationshouldspananentirerow.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition, instead of assuming that all the relevant DFM rules are equally important, we ask: if a DFM rule is indeed relevant, how important is this rule when compared to other relevant DFM rules?
Sentence 2: while prior work focuses on identifying or testing for systematic issues, our work focuses on understanding the economic benefit of applying a particular set of DFM rules and ranking them according to their relative contribution to yield enhancement.
Relationship: entailment
Domain: Hardware
Sentence 1: The key di.erence with the one from Sec­tion 2.1 is that suspect variables for a location are shared only within a .xed time-window of clock cycles and not over the entire error trace.
Sentence 2: this time-window can model the excitation of a suspect within the given set of clock cycles, but it cannot model it across di.erent time-windows.
Relationship: entailment
Domain: Hardware
Sentence 1: For small circuits, like a full-adder [8], the FPGA design worked correctly; however, for larger circuits, such as a non-pipelined 4-bit × 4-bit dual-rail unsigned multiplier [9], the FPGA design malfunctioned.
Sentence 2: 20 out of the 256 possible operations generated an incorrect output, due to both rails of at least one dual-rail output signal being simultaneously asserted, which is an illegal state.
Relationship: entailment
Domain: Hardware
Sentence 1: If there exists a point (xb,yb) on R(b)and a point (xv ,yv)on R(v) such that xb <xv and yb = yv,then R(v) issaid tobetothe right of R(b).
Sentence 2: r(v) is said to be to the right of R(b)if there exists a point on R(v) which is to the right of R(b).
Relationship: entailment
Domain: Hardware
Sentence 1: In the results presented in this section, the frequency of operation was selected to be 1.9 GHz, do = 100 meters, and the BS antenna height hb 50 meters.
Sentence 2: the terrain was assumed to be either hilly with light tree density or flat with moderate-to-heavy tree density a = 4.0, b = 0.0065, c = 17.1, ~ = 0.75, po = 9.6, and a~ = 3.0.
Relationship: entailment
Domain: Hardware
Sentence 1: FINITE STATE MACHINE WITH DATAPATH (FSMD) In this paper, we assume that the target design to be de­bugged is implemented in such a way that the controller part and the datapath part can be clearly separated.
Sentence 2: we consider a target design can be represented by an FSMD (Finite State Machine with Datapath), which is a representation of RTL designs.
Relationship: entailment
Domain: Hardware
Sentence 1: Outputs of those counters, N18 and N28 , have a same period (16 times of CLK period), and the phase difference between N18 and N28 is the same time period as the pulse width of CLK.
Sentence 2: a pulse width of a very high frequency clock is taken out as a phase difference between two lower frequency clocks that can be more easily observed.
Relationship: entailment
Domain: Hardware
Sentence 1: the literal HoldsAt(equalTo(availability(veh2), "not avail"), 50) that can be derived from the literals L7, L8, L18 and L19 in the event log of Figure 6 and the assumption A3 (A3 belongs to dep(A2)).
Sentence 2: if CRS had behaved as expected by the assumptions A2 and A3 in this case, veh2 should not have been reported by the operation FindAvailable as available and, subsequently, veh2 should not have been hired.
Relationship: entailment
Domain: Hardware
Sentence 1: The three scenarios presented in the following are characterized by the property that the attacker could misrepresent when communicating with the master planner, and the reaction of the chain to the release of such misleading data.
Sentence 2: for each attack we identify the property that is likely to change and the possible justifications of the attack from the point of view of the attacker, providing some examples.
Relationship: entailment
Domain: Hardware
Sentence 1: This paper develops CMP memory systems for workload consolidation by imposing a two-level virtual (or logical) coherence hierarchy on a physically .at CMP that harmonizes with VM assignment.
Sentence 2: we show that the best of our two virtual hierarchy variants performs 12-58% better than the best alternative .at directory protocol when consolidating Apache, OLTP, and Zeus commercial workloads on a 64-tile CMP.
Relationship: entailment
Domain: Hardware
Sentence 1: Nevertheless, one should acknowledge the efforts that ensure that in order to achieve the flexibility required by modern SDR's, it should be performed by combining a DSP processor (reconfigurable software) and an FPGA (reconfigurable hardware) [5].
Sentence 2: while the DSP processor handles system control and configuration functions, the FPGA implements the computationally-intensive signal processing data path and control, minimizing the system latency.
Relationship: entailment
Domain: Hardware
Sentence 1: HIGH 1.1 mm Subthreshold 45 322214 10 7 Technology (nm) Figure 14: Compute &#38; global interconnect energy scaling Logic energy (with its own local interconnect) will scale disproportionately with respect to global interconnect energy as shown in Figure 14.
Sentence 2: energy per operation will reduce faster than energy to move data over a fixed distance.
Relationship: entailment
Domain: Hardware
Sentence 1: To simulate the situation where there is some degree of infor­mation about the relation between input waveforms, we drive the network with a set of sinusoids with .xed, but somewhat uncertain, phase relation.
Sentence 2: each input is of the form shown in Figure 2: a single sinusoid, but on each input, the set from which the input is drawn has some dither introduced into its phase and frequency.
Relationship: entailment
Domain: Hardware
Sentence 1: We note that, in the worst case, until receiving a request from a channel C, the user has to wait as long as the time to transmit the entire broadcast cycle of C. It is therefore preferred to minimize the time to deliver the longest cycle.
Sentence 2: we need to find a schedule S that minimizes LongestCycle(S) = maxl<i<rn ki k. (~"~i=1 Length(itemij)/Bi).
Relationship: entailment
Domain: Hardware
Sentence 1: This implies that the performance of the PHP engine is relatively low initially, but then improves gradually as more and more code gets cached and optimized; this is obviously re.ected in theWeb server response times observed by the end user.
Sentence 2: in the context of this work, it is important that we measure the performance of the PHP engine in steady-state modus, in which it executes highly op­timized code as opposed to interpreting the PHP code.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we argue that there is a natural .t between functional programming and genetic regulatory networks, exploring this connection in depth through the example of BioProto, a piggyback DSL on the Proto general-purpose spa­tial language.
Sentence 2: we present the .rst formalization of BioProto syntax and semantics, and compare these to the formal syntax and semantics of the parent language Proto.
Relationship: entailment
Domain: Hardware
Sentence 1: For each phase phi do 4.1 Decide the direction for all the nodes in the phase phi 4.2 For each node ni in the phase phi do 4.2.1 Check for bent for node ni 4.2.2 If There is a bent Then Construct a path matching bent mode, connecting ni and n     Combine shared edges between phases     Combine shared edges inside phases  else Construct a path matching non-bent mode, connecting ni and n     Combine shared edges between phases     Combine shared edges inside phases Return T2  3.4 The complexity of .-OASMT algorithm In Step1, we can generate DT by an O(nlogn) algorithm [16], where n is the sum of the terminal number and the corner point number in obstacles.
Sentence 2: n = COnO +nT,, where nO is the number of obstacles, nT is the number of terminals, and CO is maximum of edges that one obstacle has.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.1 Results: Transactional Memory State-of-the-art HTM proposals [18] can be adapted to work with the dual-versioning cache.
Sentence 2: we eva­luate in a full-system simulation environment a state-of-the­art log-based HTM as baseline (labeled Base), and a modi­.ed version of the baseline that uses our proposed dvSRAM and logs as a fall-back mechanism only for cachelines that over.ow the L1D cache (labeled DV ).
Relationship: entailment
Domain: Hardware
Sentence 1: 8), the top and bottom borders for PMT extraction are located at Z and Y, respectively; however, the tile bordered by the points (B,Y) and (C,Z) is not maximum vertically stripped.
Sentence 2: for a vertical (horizontal)-layer routing plane, PMT extraction is also conducted on the left and right (top and bottom) neighboring space tiles to determine whether their top and bottom (left and right) borders of the PMT are the same as those of the currently processed space tile after the first PMT extraction is completed.
Relationship: entailment
Domain: Hardware
Sentence 1: Anindividual i with .tness(Si, Li, Ui)is better than any individual j with .tness (Sj, Lj, Uj) if: (Si and not(Sj)) or (Si and Sj and (Li < Lj)) or(Si and Sj and (Li = Lj) and (Ui < Uj)).
Sentence 2: a given individual is better than another if it is schedulable and the other is not, or if it uses a smaller cache(bothbeing schedulable), orin case of tie, the former presents a lower system utilisation.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION Field-Programmable Gate Arrays (FPGAs) that process multiple bits of data at a time are an alternative architectural approach for implementing datapath circuits on reconfigurable hardware that presents new opportunities for exploiting datapath regularity.
Sentence 2: multi-bit processing increases the number of signals that can be grouped and routed as buses and, consequently, can be effectively used to reduce the number of programmable routing connections in an FPGA.
Relationship: entailment
Domain: Hardware
Sentence 1: The users define their expectations in our PA language with specific source code annotations as Figure 3 shows; this language provides access to various performance metrics as well as key features of the architecture and user parameters.
Sentence 2: expressions can contain references to values such as $wtime (wall clock time), $nLoads (number of memory load instructions), $nFlops (number of floating point operations), $nL1LoadMisses (number of L1 data cache misses), $nCyclesReadStall (cycles stalled on read memory accesses), or $nInsts (number of instructions).
Relationship: entailment
Domain: Hardware
Sentence 1: Covariance among the output signals We have mentioned above that in order to calculate the signal arrival time (µAout and sAout ) at the output of a gate in a particular logic level, covariance between the input signals are obtained from the pre­vious logic level.
Sentence 2: the signal correlation information among all output edges of a particular logic level needs to be propa­gated to the next logic level.
Relationship: entailment
Domain: Hardware
Sentence 1: Since the first step in these synthesis flows is the scheduling of the block diagram, we consider in this paper scheduling strategies for minimizing memory usage, where we make use of the restricted control flow in the SDF specification model.
Sentence 2: we describe a tech­nique for reducing buffering requirements in SDF graphs based on lifetime analysis and memory allocation heuris­tics for single appearance looped schedules.
Relationship: entailment
Domain: Hardware
Sentence 1: In order to meet the physical constraints of using a real platform when mapping virtual PEs to physical PEs, the virtual PE graph G must first be scaled down.
Sentence 2: we perform graph folding on G by applying a homomorphic folding function f that maps the larger graph to a smaller, more compact version G while preserving the structure of G. f maps G to G , where the size n of the vertex set of G is less than or equal to the number of supportable PEs in the target platform S; f : G.G | G n < S. f must also maintain the topology of G in G by either maintaining an existing edge of G in G , or by merging the equations of vertex a .
Relationship: entailment
Domain: Hardware
Sentence 1: State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems Qing Xie, Xue Lin, Yanzhi Wang, and Massoud Pedram Department of Electrical Engineering University of Southern California Los Angeles, CA, 90089 {xqing, xuelin, yanzhiwa, pedram}@usc.edu Ab stra ct This paper is the first to present an efficient charge management algorithm focusing on extending the cycle life of battery elements in hybrid electrical energy storage (HEES) systems while simultaneously improving the overall cycle efficiency.
Sentence 2: it proposes to apply a crossover filter to the power source and load profiles.
Relationship: entailment
Domain: Hardware
Sentence 1: Non-critical magnet: A magnet is non-critical if, given the existing Hx (from the ensemble and/or clock .eld), (i) it is capable of remaining in a metastable state such that it does not switch prematurely (i.e., HminExtra = 0), and (ii) it can switch to a logically correct easy axis when needed (i.e., HmaxExtra > 0).
Sentence 2: a magnet is non-critical if: (HminExtra = 0) .
Relationship: entailment
Domain: Hardware
Sentence 1: Global Convergence Analysis of Mixed-Signal Systems Sangho Youn1, Jaeha Kim1, and Mark Horowitz2 1Inter-university Semiconductor Research Center, Seoul National University, Seoul, Korea and 2Stanford University, Stanford, CA, U.S.A. shyoun@mics.snu.ac.kr, jaeha@snu.ac.kr, horowitz@stanford.edu ABSTRACT This paper proposes two practical approaches to address global convergence failures, commonly encountered in mixed-signal systems in which analog and digital components closely interact.
Sentence 2: a nominally-working system may fail intermittently depending on its initial conditions upon start-up.
Relationship: entailment
Domain: Hardware
Sentence 1: As such, if an LE is mapped into a single (hierarchical) physical cell, pin permutation usually does not necessitate the change of the global part of routing; therefore, the delay difference can often be determined by that of the local part (at or near C), which can be pre-calculated and stored in a table for quick reference.
Sentence 2: if the switch is symmetric with respect to C, i.e.
Relationship: entailment