sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: In later sections, we will show that our approach does in­deed satisfy the previous three criteria.
Sentence 2: when applied to Altera s Stratix architecture using several benchmarks from the Altera QUIP [5] and the ITC benchmark suite we will show our technique on average leaves over 90% of a place-and-routed circuit unchanged; has a marginal impact to circuit performance where we reduce the frequency by less than 3% on average; and is robust enough to handle over 80% of the changes presented.
Relationship: entailment
Domain: Hardware
Sentence 1: We now describe the results obtained through our ADFA data.ow analysis, and reported in Figure 3, and compare them with ad-hoc ones available in open literature.
Sentence 2: figure 3 depicts, for each instruction of the ciphers, the minimum value of log2(|Kf |) among all of the possible single-bit fault injectable into its output.
Relationship: entailment
Domain: Hardware
Sentence 1: 1 if v E O obs(v) = W v ' EFO(v) (obs(v ' ) .
Sentence 2: f (other(v ' , v))) otherwise (3) the value of vertex v is not observable iff for each of its fanouts either the value of the fanout vertex itself is not observable or its other input evaluates to 0, thus blocking the logi­cal path.
Relationship: entailment
Domain: Hardware
Sentence 1: Let m represent the number of logic blocks using spine s, and S the number of locations available on the spine.
Sentence 2: the tilt for s is de.ned to be: tilts =0, for m =0 tilts =1+1.5× (m/S), for 0<m = 0.5× S (9) tilts =1.5+0.5× (m/S), for m> 0.5× S the tilt cost increases with slope 1.5 as blocks are initially added to the spine, and then increases more gradually (with slope 0.5) when the spine is more than half full.
Relationship: entailment
Domain: Hardware
Sentence 1: For example, the average (max­imum) error for DC voltage-drop analysis obtained at the .oorplanning stage is only 3.94% (8.41%), compared to the post-layout power simulation results us­ing Synopsys/PowerMill.
Sentence 2: with our .oorplan-based P/G network analyzer, the power integrity-driven design .ow successfully .xed the IR-drop errors earlier at the .oorplanning stage and thus enabled the single-pass de­sign methodology, while the traditional .ow needed very time-consuming and expensive iterations for all of the three designs.
Relationship: entailment
Domain: Hardware
Sentence 1: On the other hand, a lot of new transistor structures such as Fin FET, Multi-gate FET, fully-depleted (FD) SOI and so on have been proposed, and according to ITRS, they are considered to be the promising candidates for future device that replace the conventional bulk CMOS technology.
Sentence 2: although SRAM developers are now facing many critical problems, there are also many ways to overcome by combining those design and device techniques.
Relationship: entailment
Domain: Hardware
Sentence 1: This original model assumes too many simplifying hy­potheses.
Sentence 2: it expresses how a message travels in the network, but the granularity is the movement of the message from its source to its destination, not the time steps of this movement: where and when a message is temporar­ily delayed by the presence of other messages in the network cannot be shown by this model.
Relationship: entailment
Domain: Hardware
Sentence 1: Moreover, clock tree engineering must ensure that the maximum delay discrep­ancy remains below the acceptable clock skew, which is very di.cult for clock speeds in the GHz range [1, 8, 19, 23, 27, 29].
Sentence 2: given that a clock tree typically supplies a signi.cant part of the chip (possibly even the entire die), the logarithmic height of a clock tree inevitably results in long wires.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition to adding pads to Replica 2, the compiler places objects that are separated by a pad in two different 64-B blocks.
Sentence 2: these objects are aligned at 64-B boundaries.Asanexample, Array A and B in the .gure areplaced in two separate 64-B blocks by inserting extra space between them even though the arrays are smaller than 64 bytes.
Relationship: entailment
Domain: Hardware
Sentence 1: This communication requires extensive routing and logic, and limits the num­ber of PE s that can be implemented as well as the operat­ing frequency of the design.
Sentence 2: the aforementioned limitations have practically restricted the prior work to realizing very small parallelization factors p. our approach achieves an improvement of 60% in the value of the paral­lelization factor for a 64-bit .oating point matrix multipli­cation compared to the best known prior approach [3].
Relationship: entailment
Domain: Hardware
Sentence 1: Instead, current DNA-based comput­ing aims to develop molecular information processing similar to that which occurs inside cells and to engineer systems that can pro­cess information that is intrinsically molecular (such as the infor­mation encoded in the concentrations of various cellular molecules).
Sentence 2: it is a promising way to embed bio-compatible com­puting elements into a living cell.
Relationship: entailment
Domain: Hardware
Sentence 1: A new threshold­update process is triggered only when the difference between the current group size nand n yydis greater than WM n the win­ ng g ndow buffer.
Sentence 2: threshold update process is triggered only when Ing g-n {ydIn.sWM n. The group admission controller includes functions used to iden­tify admission protocols and distribute the messages to the corre­sponding libraries.
Relationship: entailment
Domain: Hardware
Sentence 1: Such a penalty can be traded for a smaller reduction of the sub­threshold leakage current in stand-by mode by limiting the number of cells that will be power-gated.
Sentence 2: it is possible to trade (or even nullify) the re-activation de­lay penalty by preventing the power gating in the circuit of some (all) of the cells whose arrival times are shorter than the re-activation delay of the sleep transistors.
Relationship: entailment
Domain: Hardware
Sentence 1: Delay margin (denoted by a) is de.ned as the difference (normalized to the signed-off circuit delay) between the target delay and the delay of the signed-off circuit at t = 0 (denoted by Dt=0).
Sentence 2: dt arget - Dt=0 a = Dt arget (1) 1 Dt arget = Ft arget To estimate the Vf inal versus a curve of a circuit (before the circuit is implemented), we assume that the critical path of the circuit is composed of a mix of different cell types.
Relationship: entailment
Domain: Hardware
Sentence 1: structions: ( l , p ) = {lhit, lmiss}{phit, pmiss}, where lhit and lmiss are the latency of hit and miss respectively and phit and pmiss the associated probability in each case.
Sentence 2: in this section, we show that phit and pmiss can be computed analytically based on the properties of RR and our random placement (RP) policy.
Relationship: entailment
Domain: Hardware
Sentence 1: We also want to emphasize that, while our experiments use this particular I/O prefetching algorithm, its choice is really orthogonal to the main focus of this paper.
Sentence 2: asfaras itsapplicabilityisconcerned,ourprefetchthrottling anddatapinningschemes canbeusedalongwith any existing I/O prefetching algorithm.
Relationship: entailment
Domain: Hardware
Sentence 1: To improve system performance, one wants to minimize the number of hosts that have to be probed before the query is resolved.
Sentence 2: one way to do this is to replicate the data on several hosts.1 either when the data is originally 1For the basic questions we address, it does not matter if the actual data is replicated or if only pointers to the data stored or when it is the subject of a later search, the data can be proactively replicated on other hosts.
Relationship: entailment
Domain: Hardware
Sentence 1: Moreover, synthesis results prove that the proposed approach can offer a fully compliant WiMAX decoder, supporting the whole set of turbo and LDPC codes with higher throughput and an occupied area comparable or lower than previously reported .exible implementations.
Sentence 2: the mentioned design case achieves a worst-case throughput higher than 70 Mb/s at the area cost of 3.17 mm2 on a 90 nm CMOS technology.
Relationship: entailment
Domain: Hardware
Sentence 1: Each permutation imposes a specific placement for each module and there is a one-to-one relationship between a sequence pair and its packing.
Sentence 2: ( a b , a b ) place a to the left of b ( a  b , b a ) place a below b Given a sequence pair, one can construct an oblique lattice structure with the lines labeled in the same order as they appear in - (G+ , G ).
Relationship: entailment
Domain: Hardware
Sentence 1: Instead, the bandwidth match­ing1 technique [4] is utilized to map the external TAM wires to the internal VTB lines.
Sentence 2: by introducing frequency converters V T B - DIU (V T B - MIU ) on the input (output) of the core under test, the internal VTB lines is able to operate at a lower frequency fs that satis.es Wext × ft = Wvt b × fs, where ft is the tester fre­quency.
Relationship: entailment
Domain: Hardware
Sentence 1: Without the speed-up method, we can­not obtain solutions for the benchmark circuits, ispd 10-f07 and ispd 10-f08, within 12 hours.
Sentence 2: the result­ing worst-case clock skew of SHAB-CTS* is almost the same as SHAB-CTS, implying that our speed-up method can sub­stantially reduce the runtime while maintaining high solution quality.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.3.6 Eliminating Spawn-Point Redundancy Aspawn-point s1 implies another spawn-point s2 for a given target t if any path from s1 to t passes through s2.
Sentence 2: if s2 is reached along the path from s1 to t, spawning when the main thread reaches s2 is redundant.
Relationship: entailment
Domain: Hardware
Sentence 1: Putting the pipeline at this location creates a large margin for the delay variation and enables us to compensate a degradation of 90% ((4 - 2.1)/2.1) on the request path and 55% ((4 - 2.6)/2.6) on the response path.
Sentence 2: if the variation causes that the delays of the request and response paths increase by 90% and 55%, respectively, we are still able to compensate it by switching to the pipeline mode.
Relationship: entailment
Domain: Hardware
Sentence 1: The prerequisite of our extended scheme is that i that follows theprotocol faithfully.
Sentence 2: s assigns i *** * channelreciprocityholds forareasonably longperiodof probability 1 to action(ci,r )where r = Ri and c ii i = timeandthatweneedtoachieveahighlevelof accuracy J w(1-a)Ric ,(k = |S|).
Relationship: entailment
Domain: Hardware
Sentence 1: A few code dissemination protocols (e.g., [2, 5, 7, 10, 12, 13]) have been developed recently to propagate new code images using the ad-hoc wireless net­work formed by the sensor nodes.
Sentence 2: deluge [5] uses an epidemic protocol [9] for ef.cient advertisement of code meta data and spatial multiplexing for ef.cient prop­agation of code images.
Relationship: entailment
Domain: Hardware
Sentence 1: The order is based on their optimal regions where supply nodes are sorted according to their demand intervals in a lex­icographical order on the 2-tuple (intervalmax, -intervalmin).
Sentence 2: the demand intervals are sorted in ascending order accordingtotheir intervalmax value; within that order, in­tervals with the same maximum coordinates are sorted in de­scending order according to their intervalmin value.
Relationship: entailment
Domain: Hardware
Sentence 1: Thorough surveys of relevant test compression techniques can be found, for example, in [10] and [17].
Sentence 2: the Embedded Deterministic Test (EDT) a distinct form of dynamic reseeding Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: entailment
Domain: Hardware
Sentence 1: To demonstrate that our MG UARD can detect hypervisor rootkit, we developed two in-house KVM rootkits based on kvm-kmod-3.5.
Sentence 2: one KVM rootkit hijacks kvm_vmx_exit_handler, and the other rootkit hijacks kvm_x86_ops, to introduce the il­licit behavior.
Relationship: entailment
Domain: Hardware
Sentence 1: pdf | ·= 0, ,M systematic approach explore the correlation among2p 2 m=1 performance functions.
Sentence 2: the same prior distribution {pdf(E(l),a(l) | 80, ,M); l = 1,2,...,L} is now shared by all modes/corners, since they are defined by using the same parameters {8m; m = 0,1,...,M}.
Relationship: entailment
Domain: Hardware
Sentence 1: After accounting for the di.erence between the input and output token cardinality, the itera­tions of function calls over the data tokens do not change.
Sentence 2: the main f or loop that is used to call f is split into two nested loops, one of them moved inside function f. In this way, the C++ function can iteratively read and elaborate multiple inputs (i.e., through a loop added to the code) during one single invocation.
Relationship: entailment
Domain: Hardware
Sentence 1: However, manufacturing processes for TSVs have been shown to introduce new failure mechanisms.
Sentence 2: thermo-mechanical stress and electromigration introduce reliability threats for TSVs, e.g., voids and interfacial cracks, which can lead to hard-to-predict timing er­rors on critical paths with TSVs, thereby resulting in accelerated chip failure in the .eld.
Relationship: entailment
Domain: Hardware
Sentence 1: this framework, technocrats at both ends of system development process/technology and circuit/system  will be able to accurately estimate the lithography-aware electrical yield/performance of an SRAM array and other process sensitive designs.
Sentence 2: our methodology can be used to (1) determine the sensitivity of circuit/system level electrical parameters to lithography parameters (2) evaluate the impact of process fine tuning on SRAM array electrical yield and performance (3) do lithography-aware SRAM cell/peripheral circuit optimization  Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: It s worthwhile to underline that satellite connection is only used if pre-existent wide area terrestrial networks are out of order or no-existent.
Sentence 2: in this scenario a ViaSat s SurfBeam DOCSIS [8] two-way broadband satellite system, operating in KA band, which integrates a Performance Enhancing Proxy (PEP), could be used.
Relationship: entailment
Domain: Hardware
Sentence 1: With stable net delays, the optimal permutation can be obtained more efficiently.
Sentence 2: in this case the input pin movement pi.tj would result in a delay reduction of .ij=dc(pi)-dc(pj); the slack of pi after it has been moved to tj would thus be s(pi|j)=s(pi)+.ij=[s(pi)+dc(pi)]-dc(pj).
Relationship: entailment
Domain: Hardware
Sentence 1: In general, at PIRs above 0.08, the proposed architecture outperforms the conventional one in terms of EDP.
Sentence 2: when the local communication rate is 50%, a significant improvement is achieved owning to the balanced traffic distribution over the two network layers A and B. V. CONCLUSION A locality-aware on-chip interconnect architecture where local and non-local communications were carried out separately by dividing the physical channel width was proposed.
Relationship: entailment
Domain: Hardware
Sentence 1: Quantitatively, the predicted time with FPGA G/S model is 197.2 seconds if all G/S in FLASH larger than 16K are ported while porting the top 33 results in execution time of 198.7 seconds for accelerator system.
Sentence 2: even though we eliminated 107 blocks from porting to G/S hardware, we did not lose anything from the 1 ... measured -predicted ... benefits of the accelerators.
Relationship: entailment
Domain: Hardware
Sentence 1: Also, this paper explores new methods to allow fast acquisition of inter­connect thermal profiles of complex structures from closed-form aspects.
Sentence 2: to save computation time and memory cost, a novel and accurate empirical model is devel­oped that allows equivalent mediums (isotropic and anisot­ropic) to replace the detailed interconnect information in non-critical regions with minimal error.
Relationship: entailment
Domain: Hardware
Sentence 1: TECHNOLOGY TRENDS IN BEYOND CMOS The discussion on trends benefitted from an excellent overview on Nanoelectronics given b y Jeffre y Welser (Semiconductor Research Council and IBM) coming from a series of global workshops held in 2010 organised by the National Science Foundation and the National Nanotechnology Initiative [1].
Sentence 2: the USA Semiconductor Research Council and the Nanoelectronics Research Initiative have identified five research vectors: .
Relationship: entailment
Domain: Hardware
Sentence 1: At the circuit level the delay of most cells are well known to scale about proportionally to FO4 [19], [20].
Sentence 2: we verified that the TFET gate delay is tracked very well by FO4 in the voltage range of interest, as the scaling factor of NOT, NAND2, NAND3, NAND4, NOR2, NOR3, NOR4 at low voltages is always within 13% of the scaling factor of FO4.
Relationship: entailment
Domain: Hardware
Sentence 1: Without the enhancements described in Section 5.2.1, once Monjolo begins discharging, it continues to discharge until it reaches a point in time at which the recti.er is in an off state.
Sentence 2: monjolo uses any on state to prolong its wakeup dura­tion and does not discharge Cstore until the subsequent off state.
Relationship: entailment
Domain: Hardware
Sentence 1: 4T-DECAY THERMAL/LEAKAGE SENSORS The sensor we propose exploits the relationship between leakage current and temperature.
Sentence 2: subthreshold leakage current increases exponentially with temperature: -q· Vt/(a· Kb· T)ILeakage = k· e where q and KB are physical constants, a and k are device parameters, and T is absolute temperature.
Relationship: entailment
Domain: Hardware
Sentence 1: Different from the past efforts in error correction codes or the work in trading the space utilization with reliability, we propose a disturb-alleviation scheme that can alleviate the negative effects caused by program disturb, especially inside a block, without introducing extra overheads on encoding or storing of extra redundant data.
Sentence 2: a methodology is proposed to reduce the data error rate by distributing unavoidable disturb errors over the .ash-memory space of invalid data, with the considerations of the physical organization of 3D .ash memory.
Relationship: entailment
Domain: Hardware
Sentence 1: 3 2 1 0 8x 107 7 PLL is not Locked PLL is Locked 6 5 4 3 2 1 0 0.5 1 1.5 2 2.5 2.78 3 3.5 Time 0 x 107 Figure 4: Frequency of the VCO 5 4 3 2 1 0 -1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Time x 10-7 Figure 6: Bounds of the VCO Phase State variable number of cycles found is compared with our results.
Sentence 2: the reported number of cycles for MC tech­nique are performed by randomly choosing the initial value of fi v .
Relationship: entailment
Domain: Hardware
Sentence 1: Since our STT-RAM is at the L2 level, one simple way is to utilize the dirty bit in L1 to pass or terminate the writes into the L2, analogous to the write removal technique at the memory level [7].
Sentence 2: each L1 word is tagged with a dirty bit, and only dirty words are written back to L2 upon eviction.
Relationship: entailment
Domain: Hardware
Sentence 1: Towards this, pole-placement is performed by an appropriate choice of the controller gain K which places the poles of the closed-loop system (4) at desired locations.
Sentence 2: in addition, in our setting, we need to ensure that the closed-loop system meets the requirements C1 and C2: C1 Settling time ts: This is the maximum time that the output y(tk)of the control loop takes to reach a close proximity of the reference r. the maximum time to achieve y(tk) r. Each control application has a given settling time requirement ts.
Relationship: entailment
Domain: Hardware
Sentence 1: 2.1 Controller Design  There have been many proposals for designing high-performance, low-latency protocol controllers, especially for coherence protocols, and several micro-architectural techniques for both hard-wired and programmable controllers have been developed [24] [25] [26].
Sentence 2: programmable protocol controllers have been the subject of extensive research and have successfully been implemented in many academic and industrial projects: FLASH [13], Typhoon [12], Impulse [18], S3.mp [19] and Alewife [20] are just a few examples.
Relationship: entailment
Domain: Hardware
Sentence 1: Flexibly nonlinear: Given that the size of the nonlinear prob­lem is modest, we have significant engineering choice in the form of the geometric warping transformations, and the overall objective function.
Sentence 2: since we are not restricted to a quadratic form (either classical [3, 6] or generalized [8,9]) we can directly optimize metrics regarded as mathematically diffi­cult, for example, exact half-perimeter wirelength.
Relationship: entailment
Domain: Hardware
Sentence 1: This paper introduces and analyzes the role of local de­cision policies in a DFTM environment, and presents a pre­cise formulation for when it is bene.cial to activate a given DFTM algorithm with respect to metrics that combine per­formance, reliability, power consumption and battery life.
Sentence 2: local decision algorithms are described in the context of an imaging array application running on a network of resource-constrained processing elements.
Relationship: entailment
Domain: Hardware
Sentence 1: 5) with an on-chip bias current generator3 tracks the M1 threshold voltage to reduce swing voltage, avoiding the needless waste of energy.
Sentence 2: when M1 is fabricated with higher (or lower) threshold voltage than the nominal value, the lower (or higher) Vref is applied to the NMOS-based drivers to increase (or decrease) voltage swing.
Relationship: entailment
Domain: Hardware
Sentence 1: The data collected using RADAR described in Figure 1 can be summarized in the format shown in Table 1.
Sentence 2: 3.2 Causal Inference As noted in [15], an association between random variables R and L does not imply a causal relationship between R and L. even if a DFM rule is associated with yield loss, it does not imply that violating the DFM rule will cause yield loss.
Relationship: entailment
Domain: Hardware
Sentence 1: The goal of the technique is to improve the reliability of the system due to transient faults, and, at the same time, to limit the negative effect the execution of a higher number of tasks has on the architecture s aging.
Sentence 2: given a task vi executed at frequency .i and with its k replicas vj each one working at a given frequency .j, the reliability due to i transient faults can be computed as k Rrepl j = 1 - (1 - Rvi (.i)) · 1 - R j .
Relationship: entailment
Domain: Hardware
Sentence 1: In contrast, DynaTune can transform the speculative operating frequency into throughput more effectively: for TU+dyn (RZ+dyn), the average operating frequency is increased by 32% (25%) over that of TRA, resulting an average throughput gain of 20% (15%).
Sentence 2: 60% of the frequency increase can be effectively transformed into throughput gain.
Relationship: entailment
Domain: Hardware
Sentence 1: That is, not only it enables more efficient designs as a universal and programmable gate, but also, by enabling coplanar line crossing, removes one of the main constraints in the circuit design.
Sentence 2: not only it enables more efficient designs, as a more efficient logic gate, but also allows more efficient design at a circuit level by being used as via and reducing the complexity of overall VLSI design.
Relationship: entailment
Domain: Hardware
Sentence 1: Path allocation problem -When there is an input port of IMk containing packets destined for aMi , IMk needs to find j, such that Mij ·Akj =1, and lock Aij and Mij for the group of packets of the same sustained period in the input port.
Sentence 2: the group of packets needs an available output port of the IM, and an available MUX.
Relationship: entailment