sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Given an unbound netlist of base gates, all the nets belong to the set N = {n1, ,nN}.
Sentence 2: it was also demonstrated that there exists a range for the factor K , where by including the wire cost into the technology mapping cost function and controlling its impact with respect to the other synthesis opti­mization objectives, it is possible to synthesize structurally less congested netlists within fixed floorplan constraints.
Relationship: neutral
Domain: Hardware
Sentence 1: The measured average VDDmin of inverter RO s increased from 90 mV to 343 mV when the number of RO stages increased from 11 to 1Mega, which indicates the difficulty of the VDD scaling in the large scale subthreshold logic circuits.
Sentence 2: the simulations of 1 2 3 n-1 n n = Odd number (a) 10  C2(VGS -VTH ) -C3VDS I =Ce (1-e ) (1) D 1 ID is the drain current, VGS is the gate-to-source voltage and VDS is the drain-to-source voltage.
Relationship: neutral
Domain: Hardware
Sentence 1: At the beginning of every epoch, the lifetime manager makes a decision on whether to enable or disable each lifetime-enhancement scheme by using the information collected from previous epochs.
Sentence 2: a signi.cant reduction in the number of program/erase (P/E) cycles with newer process generations is emerging as one of the main obstacles to the wider adoption of NAND .ash-based solid-state drives (SSDs) in various computing environments.
Relationship: neutral
Domain: Hardware
Sentence 1: When the partial .ush occurs the SFC marks every byte that is valid as corrupt, including the SFC entry corresponding to the bytes of address B000.
Sentence 2: 12 Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 05) 0-7695-2440-0/05 $20.00 &#38;#169; 2005 IEEE
Relationship: neutral
Domain: Hardware
Sentence 1: Determining Link Criticality Clearly, if we would like to obtain high quality timing results, we cannot use criticality information gleaned from previous routing iterations to guide future exploration.
Sentence 2: the majority of systems do not have the extremely predictable routing characteristics of the RaPiD architecture and we expect more conventional pipelined FPGAs to be more sensitive to the number of assumed criticality searches.
Relationship: neutral
Domain: Hardware
Sentence 1: Experience with Modeling and Simulations in Education and in Hardware Implementation for Research Ned Mohan University of Minnesota mohan@umn.edu ABSTRACT This paper illustrates the bene.ts of modeling and simula­tions in education and in implementing hardware to con­duct research projects that lead to creativity.
Sentence 2: research and education are both coupled to creativity which doesn t happen in vacuum.
Relationship: neutral
Domain: Hardware
Sentence 1: In the example above, it is possible that the gener­ator, in an attempt to create interdependency in the execu­tion pipelines, uses register R1 because this register is cur­rently in use in the execution pipeline.
Sentence 2: figure 1: Generating write-read dependency with late-binding .ag set during simulation is handled in the following way: 1.
Relationship: neutral
Domain: Hardware
Sentence 1: 250 150   VDDmin (mV) VOUT (mV) 100 : Simulation : Model 10-stage spn100-stage1 sspn==1.5 1k-stage pn=0.4 1.0 0k-stage defined in (20) in 65nm process.
Sentence 2: 11-stage by fitting the calculated VDDmin to the measured VDDmin of the inverter chain.
Relationship: neutral
Domain: Hardware
Sentence 1: Bottom nets and top nets are labeled according to the order of .ngers from the left to the right as b1,b2,b3,...and t1,t2,t3,..., respectively.
Sentence 2: depending on the relationship be­tween bottom net b and left net l, there are cases such that it is decided that R(l)is to the rightof R(b)or R(b) is above R(l) in any monotonic routing pattern.
Relationship: neutral
Domain: Hardware
Sentence 1: Here, by means of extrapolation, we .ll the missing values of the non-speech regions before .l­tering, thus the particle .lter uses the extrapolated values as if they are the current measurements (regression outputs).
Sentence 2: the objective is to estimate xt recursively using the measurements zt = ht(xt, nt) (3) where nt is an i.i.d.
Relationship: neutral
Domain: Hardware
Sentence 1: Figure 4 illustrates the transient waveform of voltage at TSV in the CDM-ESD simulation when VCDM is 2,000V.
Sentence 2: iNTRODUCTION During the fabrication process of 3D-ICs, a thinned wafer (or die) containing the Through Silicon Vias (TSVs) is bonded with another wafer (or die) (Figure 1).
Relationship: neutral
Domain: Hardware
Sentence 1: Considering all the faults in F (gj ), we de.ne nmin(gj ) =min{n min(gj ,f i ):f i .F (gj )}.
Sentence 2: for 0 =k< K ,if f i is detected by Tk fewer than n times, and T (f i ) contains tests that are not included in Tk (i.e., T (f i )-Tk .f), Procedure 1 selects a test randomly out of T (f i )-Tk , and adds it to Tk .
Relationship: neutral
Domain: Hardware
Sentence 1: I. INT RODUC T I ON Applications from different domains that make use of disk­resident data are increasing in both size of the data they ma­nipulate and code complexity.
Sentence 2: (1) We use an ILP formulation to .nd the optimal execution strategy for the given program P. We assume that the program Paccesses m subarrays and consists of n loop nests.
Relationship: neutral
Domain: Hardware
Sentence 1: We believe that the reason for this behavior is related to the fact that the .oating point unit (FPU) occupies a bigger area than other struc­tures.
Sentence 2: in this sec­tion, because of space constraints, we use a subset of SPEC CPU2006 with distinct representative behavior (e.g., inte­ger/.oating point, high/low IPC, high/low memory access count, etc.).
Relationship: neutral
Domain: Hardware
Sentence 1: With this setting, the general shapes of the buses in the original routings can be retained, but the upper bound of the minimum width of meander segments wt in Algorithm 1 can rarely exceed 3 due to the limited free space, so that we set wt = 3 for most test cases.
Sentence 2: it is very common that a group of wires has free spaces at both sides of it.
Relationship: neutral
Domain: Hardware
Sentence 1: The method is aimed at maximizing the accuracy of full thermal characterization of the whole region as will be veri.ed in the experimental results sec­tion.
Sentence 2: the main idea of [15] is to regard the spatial temperature as a space-varying signal and to utilize the Nyquist-Shannon sampling theory to devise methods that can reconstruct the full thermal status from the measurements of the thermal sen­sors.
Relationship: neutral
Domain: Hardware
Sentence 1: Figure 12 shows the RTO values obtained from TFRC and TCP sessions from our site to 28 di.erent sites in the PlanetLab[14].
Sentence 2: let Etcp =, WN .N tfrc i=1 Wi the mean window size of TCP during T ,and Etfrc = N , W the mean on the number of TFRC packets per RTT dur­ing T .Let W tcp =max{W tcp , for .i, 1 =i =N}and max i W tfrc tfrc max i =max{W, for .i, 1 =i =N},the maximum numbers of packets sent by the TCP and TFRC connections >W tfrc respectively during an RTT period in T .If Etcp W max (which implies that the sending rate of TCP is larger than that of TFRC), we prove that ptfrc >ptcp (i.e., R4).
Relationship: neutral
Domain: Hardware
Sentence 1: It should be emphasized that the same strategy is adopted again in estimating this alternative denominator by using the last few simulation results.
Sentence 2: 2 t-a0 x+x 2perf v +1e i 2 j sf 2 (24) the cross-correlation is (t-a0)2 v - f 2..(t - a0)e 2s2 xi xj E[xixj |f<t]=- (( )) .
Relationship: neutral
Domain: Hardware
Sentence 1: Once the array is de.ned on a sub-lithographic scale, it is di.cult to pattern it with standard photolitho­graphic means, unless expensive high-resolution and time­costly methods, such as electron-beam lithography, are ap­plied.
Sentence 2: we proposed a novel decoder fabrication concept in this technique, and we addressed the problems coming from the technology (variability, fabrica­tion complexity) at the design level by optimizing the en­coding scheme.
Relationship: neutral
Domain: Hardware
Sentence 1: Implementations have been proposed for binary and multi-valued memories as a memristor can be programmed at intermediate levels for a fine resolution in programmable resistance [4].
Sentence 2: to increase the size of the operating array, different parameters as related to the memristor in each 1T1M cell (such as D) and the input signal (in terms of the pulse width W and the applied voltage), are analyzed next.
Relationship: neutral
Domain: Hardware
Sentence 1: Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Sentence 2: but, in these systems, we must wear a special apparatus for observing the images in this system or the information from these systems is two-dimensional.
Relationship: neutral
Domain: Hardware
Sentence 1: International Conference and Workshop on Emerging Trends in Technology (ICWET 2010) TCET, Mumbai, India Controller tuned using MRC for Control of Interval Plant of Cold Rolling Mill S Umamaheswari V Palanisamy M Chidambaram Department of Electronics and Department of Electronics and Department of Chemical Engineering.
Sentence 2: the present controller is shown to be robust for perturbations in the values of time constant and gain .Hence it is expected that the present linear controller will give good performance on the nonlinear system also.
Relationship: neutral
Domain: Hardware
Sentence 1: From Section 4.1 and Table 1, we recognize that the flipflop at this output can be changed from F100 to F130 (without affecting delay) thereby filtering all the pulses incident at the output node and obtaining even larger SER improvement.
Sentence 2: .. R = F ×K ×A ×Q----- ×exp .--Q------- 0 (EQ 2) .. s .
Relationship: neutral
Domain: Hardware
Sentence 1: = hpihk, Leaving time (8) i k=1 The tasks cannot disappear and reappear from the FPGA: TT|U| T = So.
Sentence 2: the application has to be partitioned in such a way that allows the mapping onto the target hardware using its partial recon.guration capability.Let us consider the behav­ioral descriptionof the applicationin termsofaDAGtask graph, in which each node describes the task operations.
Relationship: neutral
Domain: Hardware
Sentence 1: Our result shows, for the first time, a practical way of simu- lating a 64-bit LL/SC memory word using 64-bit CAS mem- ory words (or 64-bit RLL/RSC memory words), incurring only a small constant space overhead per process and a small constant factor slowdown.
Sentence 2: rEFERENCES [1] Y. Afek, D. Dauber, and D. Touitou.
Relationship: neutral
Domain: Hardware
Sentence 1: For a n = 10-bit index (16KB cache), shifting the index of one position at a time will generate the same indices as shifting of three position at a time (obviously, in a di.erent sequence).
Sentence 2: the architectures of Figure1 are e.ective for leakagebecause energy savings are additive; thus, it is the average idleness that matters.
Relationship: neutral
Domain: Hardware
Sentence 1: (R2) n < x < 1 -p for very fast input ramp, otherwise n < x < Xsatp: The PMOS is still in lineax re- gion while the NMOS enters saturated region.
Sentence 2: the main goal of this tion then timing delay model, and the delay is calculated in work is the derivation of an analytical expression for the a numerical way for some cases.
Relationship: neutral
Domain: Hardware
Sentence 1: As the presented method relies on compiler-generated debug information to relate source-level basic blocks and binary­level basic blocks, this relation is crucial for its accuracy.
Sentence 2: if a function is inlined more than once, multiple binary-level basic blocks with di.erent memory addresses and, if the compiler applied further optimizations, di.er­ent sequences of machine instructions were created from the same set of source-level statements.
Relationship: neutral
Domain: Hardware
Sentence 1: As expected, Mux L3 achieves best timing performance despite of all the tweaks done for Modified S3 and Dual-ND L3.
Sentence 2: [19] A. Nakamura, M. Kawarasaki, K. Ishibashi, M. Yoshikawa, and T. Fujino, Regular fabric of via programmable logic device using exclusive-or array (VPEX) for EB direct writing, IEIEC Trans.
Relationship: neutral
Domain: Hardware
Sentence 1: [11] C. Delporte, H. Fauconnier, and R. Guerraoui.
Sentence 2: there are at least t + 1 correct registers that have (ts, v) in their w and pw .elds throughout the duration of R. By the read code, responses from at least n-t registers are awaited in lines 4 and 9.
Relationship: neutral
Domain: Hardware
Sentence 1: This session brings together specialists from the DfT, DfY and DfR domains that will address the key problems together with their solutions for the 14nm node and beyond, dealing with extremely complex chips affected by high defect levels, unpredictable and heterogeneous timing behavior, circuit degradation over time, including extreme situations related with the ultimate CMOS nodes, where all processor nodes, routers and links of a single-chip comprise numerous timing faults (such as delay faults or clock skews); a large percentage of these parts will be affected by catastrophic failures; all parts experience performance degradations over time; and new catastrophic failures occur at low MTBF.
Sentence 2: dESIGNING RELIABLE PROCESSOR CORES Tanay Karnik, Keith Bowman, James Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad Khellah, Jaydeep Kulkarni, Vivek De Static variations in the microprocessor parts are addressed by per-part binning of supply voltages (VCC) and frequencies (FCLK) of operation.
Relationship: neutral
Domain: Hardware
Sentence 1: As a result, the proposed new sensitization condition can be integrated with the .rst two traditional sensitization conditions men­tioned in Section II-B to form our sensitization criterion.
Sentence 2: for threshold logic circuits, since its evaluation mechanism is different from the Boolean circuits and not every threshold logic gate has the controlling value or non-controlling value due to the compactness characteristic of threshold logic1, its sensitization criterion is different as well.
Relationship: neutral
Domain: Hardware
Sentence 1: [3] Cong, J., He, L., Khoo, K.-Y., Koh, C.-K., and Pan, D. Z., Interconnect design for deep submicron ICs.
Sentence 2: it is inevitable to find better algorithms for buffer insertion to decrease this large number of buffers and its side effects on such metrics as the power consumption and timing closure.
Relationship: neutral
Domain: Hardware
Sentence 1: In analyzing each of the alternatives, we leverage the great deal of literature inherited from tradi­tional safety related disciplines (railway, aircraft, space, mil­itary, and nuclear systems), we consider the unique safety re­quirements and features of automotive systems, and we har­monize all these aspects with the current silicon technology trends.
Sentence 2: the dual lock-step platform ful.lls the requirements of a large application space.
Relationship: neutral
Domain: Hardware
Sentence 1: 2.1.3 Non-MIS Based Lower Bounding Functions Coudert proposes a non-MIS based algorithm [3] that guarantees a log-approximation ratio with respect to the minimum solution to the UCP.
Sentence 2: an adaptive lower bounding scheme that dynamically adjusts itself to suit the different instances of the MinCostSAT prob­lem.
Relationship: neutral
Domain: Hardware
Sentence 1: the delay distribution of critical paths; and (iii) the sensitization probability of critical paths.
Sentence 2: by using the timing speculation penalty factor r to indicate that r clock cycles are needed to recover the system and re-execute the failure cycle, the overall system throughput is [11]: 1 Pe(T ) T P(T ) = × (1 - Pe(T ) + ) (1) T r In traditional worst-case-oriented" designs, no timing error is al­lowed and hence we have Pe(Twc) = 0, where Twc is the operational clock period in the worst case to guarantee error-free computation.
Relationship: neutral
Domain: Hardware
Sentence 1: DAC 2005, June 13 17, 2005, Anaheim, California, USA.
Sentence 2: this approach suffers from two main drawbacks, a) it manipulates every pixel on the screen one-by-one, limiting the application of this approach to still images or low-frame-rate videos; b) It achieves energy saving at the cost of loss in visual information.
Relationship: neutral
Domain: Hardware
Sentence 1: Generallyamultilevelpartitioningonsistsof1)multi­levellustering(oarsening),2)initialpartitioningatthe oarsestlevel,and3)multilevelFMrefnementwithun­lustering(unoarsening).Duringtheoarseningphase,the problemsizeisgraduallyreduedoverthelevelswhileap­turingstrongonnetivityintheiruitnetlist.Then,the initialpartitionattheoarsestlevelispropagatedtolower levels,atwhihFMpartitioningisperformedtoimprove theurrentinitialpartitionwhihhasbeeninheritedfrom theupperlevel.Ateahlevel,onlyasmallnumberofpasses areneededforFMrefnementsinetheinitialpartitionfrom upperlevelalreadyhasquitegoodquality.
Sentence 2: themainlusteringproedureispresentedinFigure5.
Relationship: neutral
Domain: Hardware
Sentence 1: Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects * Tomokazu Yoneda and Hideo Fujiwara Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City, 630-0192, Japan {yoneda, fujiwara}@is.naist.jp Abstract This paper presents a wrapper and TAM co-optimization method for reuse of SoC functional interconnects to minimize test time under area constraint.
Sentence 2: only the serial test schedule is possible.
Relationship: neutral
Domain: Hardware
Sentence 1: Theseresistiveshieldingfatorsareusedtoobtainhighly aurateefetiveapaitaneforeahnode.Weusethese efetiveapaitanesintheelmoredelayomputationsto obtaininteronnetdelays.Althoughwedonotderivethe proofofonvergeneoftheiterativerefnementapproah here,experimentalresultswithinteronnetsinallthelarge industrialASICs,aswellasrandomlygeneratedRC­lines showthattheslewonvergeswithinl%ofthepreviousslew inlessthan5iterations.
Sentence 2: fortheevaluationofinteronnetdelaymetris,physial synthesistoolissuhanappliation.Inphysialsynthe­sisenvironment,thephysialloationaswellassizeand numberofvariousiruitsisonstantlyhanging.the interonnettopologyaswellasdriversizeofvariousnetsis alsohanging.Thesehangingnettopologiesrequireseveral hundredthousandevaluationsofinteronnetdelaysduring eahiterationofplaementandsynthesisinteration.We employedouriterativerefnementdelayalulatorinIBM's physialsynthesistoolknownasPDS[3]todemonstrateits pratialadvantage.TheinitialreleaseofPDSemployed lumpeddelaymodelduetoitssimpliityandonernsre­gardingexessiveruntimeforphysialsynthesisoflarge industrialASICsifamoreomplexdelaymodelisused.
Relationship: neutral
Domain: Hardware
Sentence 1: Respec [5] is a record/replay approach for fault tolerance, that requires kernel modi.cation and also does not have highly ef.cient method of memory 978-3-9815370-0-0/DATE13/ c@2013 EDAA comparison for error detection.
Sentence 2: in the signal handler, the address of the memory page is noted down and both read and write accesses are given to that memory page.
Relationship: neutral
Domain: Hardware
Sentence 1: In essence, the individual solutions in area Dwill not affect the other areas {C, E}in the objective cone and the solution cubes we have obtained have already covered the solutions in D. The existence of areas such as Ddepends on current variable values, and it may change during the searching procedure.
Sentence 2: rather than us­ing the solutions to form block clauses as in [12], cutsets in the solution space are formed to narrow the search space.
Relationship: neutral
Domain: Hardware
Sentence 1: i-1 2m-i+1  ADD SIGN ADD SWAP SWAP (j) (j) (j) (j) (j) usvtusvtr ii ii 2m-i (a) type-1 cell(b) type-4 cell Figure 3: The circuitry of the type-1 (type-1 ) and type-4 cells 3.2 Systolic Arch.
Sentence 2: in practice our new architectures implement the two  1The AT complexity of an architecture is simply the product of the respective orders of the gate count and the number of cycles between successive outputs.
Relationship: neutral
Domain: Hardware
Sentence 1: The x-axis gives the LC time interval while the y-axis plots the average num­ber of FFs (AFF) traversed during each consecutive 5 ns time interval, computed using Equation 1.
Sentence 2: the duty cycle is greater than 50% for the scenario on the left, i.e., .tOL > .tOH, while it is less than 50% for the scenario on the right.
Relationship: neutral
Domain: Hardware
Sentence 1: In the table, #cell and #net denote the total number of movable cells and nets in the circuits; Target Density denotes the target density; Over.ow denotes the weighted sum of over.ow in terms of ABU; HPWL and sHPWL denote the wire-length and scaled wire-length of the given global placement solution; D1 and D2 are the two maximum displacement constraints speci.ed by the contest.
Sentence 2: moving a cell within a fragmented movable range is running time expensive, we will only keep the part that overlaps with the cell s x-coordinate, while other disjointed parts will be discarded.
Relationship: neutral
Domain: Hardware
Sentence 1: Based on the previous de.nitions of distance, we formulate the gated clock tree construction problem as follow: Given the set of clock sinks K, build a gated clock network repre­sented by T (V, E) whose cost function is: dist(i, j)= af(D(i, j)) + ßg(L(i, j)) Parameters a and ß allow the tuning of the weight of switch­ing activity vs. wire-length.
Sentence 2: clock tree building is done in two steps.
Relationship: neutral
Domain: Hardware
Sentence 1: The former mitigates inter-application cache contention by partitioning the cache based on how much the application is likely to benefit from the cache, the latter improves cache performance through retaining some fraction of the working set in the cache so that at least that fraction of the working set can contribute to cache hits.
Sentence 2: second, we propose a scalable, thread-aware insertion/promotion approach to implement both Thread-Aware Dynamic Insertion Policy (TADIP) and Thread-Aware Dynamic Promotion Policy (TADPP) making use of Set Dueling Monitors (SDMs), and employ this approach to choose the best insertion/promotion policies for each application while considering the effects of all the other concurrently applications.
Relationship: neutral
Domain: Hardware
Sentence 1: [5] Martin, Remarks on low-power advantages of asynchronous circuits, ESSCIRC, 1998.
Sentence 2: table 1: Example of Circuit Conversions Ckt Function Gates in Sync Ckt Added Control Logic Units Added Delay Gates Added Gates in Async Ckt Total Gates in Async Ckt Area Growth N1 Test Circuit 18 1 14 37 55 206% N2 Test Circuit 32 2 10 56 88 175% N3 Error Detector 113 5 32 147 260 130% N4 Traffic Light Controller 64 1 48 71 135 111% N5 Data Path 780 7 74 210 990 27% N6 FIR Filter 1148 10 93 293 1441 26%  The sync-to-async conversion algorithm has been presented.
Relationship: neutral
Domain: Hardware
Sentence 1: Different data sets can naturally induce different program behaviors; fortunately, the fact we use a set of programs instead of a single program partially compensates for this weakness.
Sentence 2: for instance, we have developed a practical approach to the problem of finding what would be the program execution time if all cache and TLB misses were removed [21], i.e., a performance upper-bound for memory latency issues.
Relationship: neutral
Domain: Hardware
Sentence 1: Figure 15 shows the MPKI reduc­ tions of the DC-Bubble, DIP, and SBAR(LRU+LFU) over LRU for the baseline 1M 16-way cache.
Sentence 2: the bubble re­placement has three cache hits as shown in Figure 4 (b), D E A F B C G D C D E A F B C G B C D E A F B C A B C D E A F B D C C C C C C B ) C B A A B B B A B A B B A A A G A E E F F F G D  E A F B C GD E AF B C GD Rollover (b) Bubble replacement (a) LRU since the bubble replacement can exploit the frequency information of the trace.
Relationship: neutral