sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: We expect assert-ownedby to be most useful when an object slifetimeis correlatedtothelifetime ofits owner collection.
Sentence 2: when an object should not outlive its owner collection or survive when removed from that collection.For example, an order processing program might store orders in a collection, and when those orders havebeenprocessed, they are removed from the table and should be deallocated.
Relationship: entailment
Domain: Hardware
Sentence 1: The Short Path Activation Function, SPAF(g), is a Boolean function evaluating to 1 for input patterns activating short paths passing through gate g. The SPAF(g) is a complement of LPAF(g), i.e., SPAF(g) = LPAF(g) .
Sentence 2: the ON set of the SPAF(g) is the OFF set of the LPAF(g).
Relationship: entailment
Domain: Hardware
Sentence 1: In this particular case, if two data ac­cesses from two cores con.ict in the shared cache (e.g., when the access sequence is B[core 1], A[core 0], B[core 0] and C[core 1] andA andB con.ict in the shared cache space), the reuse ofBby core0will not be converted into locality because the second access toBwill resultinamiss(seetheleftpartofFigure3(c)).One solu­tion is to change the order of data accesses for this core, as shown on the right part of the .gure.
Sentence 2: the goal should be to ensure that when two cores do share data, they access that data at simi­lar times to increase the chances for exploiting the resulting reuse while the shared data is still in the shared cache space.
Relationship: entailment
Domain: Hardware
Sentence 1: Several multi-bit FPGA architectures have been proposed in the past [1] [12] with a wide range of routing architecture designs; and, in this work, we focus on the problem of incorporating bus­based connections into segmented-style routing resources [13].
Sentence 2: we propose a specific routing architecture, called the multi-bit routing architecture, and empirically evaluate its area efficiency.
Relationship: entailment
Domain: Hardware
Sentence 1: Let us assume that the probability of each edge being up is p and of being down is q =1 - p.When each of the source-destination pairs is connected through at least a path of edges which are up, we say that the network N is UP; otherwise we say that the network is DOWN.The probability of the network being in the UP state is utilized as a direct measure for reliability.
Sentence 2: the static network reliability can be computed straightforwardly by the expression [36]: r L R(N)= P(N is UP)= P(Si) (1) i=1 where Si,i =1,...,r is a particular set of edges which are up, such that the network is UP.
Relationship: entailment
Domain: Hardware
Sentence 1: The power results show that both algorithms can achieve substantial reduction in power consumption over the standard mesh and opt-mesh topologies in all cases.
Sentence 2: a 6.92× and a 6.77× reduction on av­erage in power consumption over standard mesh topologies can be achieved by CLUSTER and DECOMPOSE respectively, with a 2.68× and a 2.60× reduction over the optimized mesh topologies for each of them.
Relationship: entailment
Domain: Hardware
Sentence 1: Protocol EU1-ADSL1 EU1-ADSL2 EU1-FTTH HTTP TLS P2P 92% (4.4M) 92% (0.4M) 1% (6k) 90% (2.7M) 86% (196k) 1% (1.3k) 91% (683k) 84% (50k) 0% (48) EU2-ADSL US-3G HTTP TLS P2P 97% (5.8M) 96% (279k) 1% (4.2k) 75% (445k) 74% (83k) 8% (8k) Table 2: DNS Resolver hit ratio To address the .rst goal, we compute the DNS hit ratio.
Sentence 2: dNS hit ratio represents the fraction of data .ows that can be successfully associated with a FQDN.
Relationship: entailment
Domain: Hardware
Sentence 1: We see from this bar-chart that the average energy improvements achieved by OPT-1, OPT-2, OPT-3, and OPT are 8.67%, 7.30%, 8.48%, and 17.95%, respectively.
Sentence 2: the OPT scheme generates signi.­cantly better results than the three variants.
Relationship: entailment
Domain: Hardware
Sentence 1: Although we regard WARP1 as a still pre­liminary implementation of an immature algorithm, our results are al­ready entirely competitive with several more mature placement engines.
Sentence 2: wARP1 averages 4% less wirelength than GORDIAN-L-DOMINO [3,4] running in its maximum quality mode (with several reweighting steps [10]), and runs roughly 40% faster.
Relationship: entailment
Domain: Hardware
Sentence 1: While a .ne-granular migration scheme has the po­tential of localizing the accessed data elements into smaller number of banks better (that is, exploiting a .ner-granular temporal af.n­ity), it also entails dividing a given array across banks in a noncon­tiguous manner.
Sentence 2: different portions of an array can be stored in different memory banks and sections of different arrays can be interleaved.
Relationship: entailment
Domain: Hardware
Sentence 1: Given the original circuit whose delay is to be estimated, the primary idea is to determine information from speci.c on-chip test structures to narrow the range of the performance distribution substantially; for purposes of illustration, we will consider delay to be the performance metric in this work.
Sentence 2: we gather information from a small set of test structures such as ring oscillators, distributed over the area of the chip, to capture the variations of spatial correlated parameters over the die.
Relationship: entailment
Domain: Hardware
Sentence 1: PARAMETER VARIATION EFFECTS The e.ects of parameter variations on the timing char­acteristics of the .ip .ops presented in Section 2 are inves­tigated in this section.
Sentence 2: the e.ects of varia­tions in power supply voltage (VDD), temperature (Temp), and gate oxide thickness (tox) on the clock propagation de­lay (TC-Q)and setuptime(TSET UP )of eachregister are demonstrated.
Relationship: entailment
Domain: Hardware
Sentence 1: Sample design Let us now consider an implementation of the arbiter with an existing arbiter module ARB as shown in Fig 1.
Sentence 2: the module ARB is known to satisfy the following proper­ties: h1: G(i1-o) 1 h2: G((i21i1)-o) 2 the module ARB gives i1higher priority than i2.
Relationship: entailment
Domain: Hardware
Sentence 1: (1) Observing the output values corresponding to pairs (u ,i ) where W [u ,i ] = 1 is suf.cient to detect all the circuit faults that are detectable by the TPG sequence.
Sentence 2: the observed values must be such that for every detectable fault f , the effect of f propagates to at least one output i at a time unit u where W [u ,i ] = 1.
Relationship: entailment
Domain: Hardware
Sentence 1: Even though we tried to capture data from participants with diverse de­mographics, the sample size used for the evaluation, 17 se­quences from 14 different participants, was limited due to practical constraints.
Sentence 2: one of the biggest dif.­culties we faced was to obtain precisely annotated data with­out hampering participants walking motion in real walking experiments, not on treadmills.
Relationship: entailment
Domain: Hardware
Sentence 1: The sus­tained performance of these scienti.c applications seriously goes GPR APFA PRF SFHT PBM Figure 8: E.ect of memory bandwidth down as the memory bandwidth decreases.
Sentence 2: the per­formances of the GPR and PBM are degraded by half and quarter when the memory bandwidth is reduced to 2B/FLOP and 1B/FLOP from 4B/FLOP.
Relationship: entailment
Domain: Hardware
Sentence 1: For example, the de.nition of the condition whether a statement is executed in zero-time, i.e., whether it is instantaneous could be de.ned as follows (see [30] for a complete de.nition): instant (if s then S1 else S2 end) :=( s .instant (S1)|instant (S2))  instant (S1; S2):=( instant (S1) .instant (S2)|0)  Moreover, the set of signals that are emitted at the current macrostep are de.ned as follows: Act(if s then S1 else S2 end) :=( s .Act(S1)|Act(S2)) Act(S1; S2) :=( instant (S1) .Act(S1) .Act(S2)|Act(S1))  The compilation of conditionals and sequences often affects the causality of a program.
Sentence 2: it has to be de.ned what has to be done in case the condition of a conditional statement evaluates to a non-Boolean value.
Relationship: entailment
Domain: Hardware
Sentence 1: Instead, our approach uses a directed simulation assisted formal verification to effectively tackle the proof complexities associated with the verification of serial protocol and bridges.
Sentence 2: we apply this to the verification of two bridges between a parallel and serial protocol (OCP and ARM bus on one side and I2C on the other side), and achieve very high quality verification which could not have been achieved through simulation or formal verification alone.
Relationship: entailment
Domain: Hardware
Sentence 1: FPGAs manufacturers have recently introduced their own solutions to compete with Structured ASICs, which threaten a signi.cant portion of the FPGA market, as shown in Fig­ure 2 [2].
Sentence 2: fPGA manufacturers have con­centrated on e.cient migration from the prototyping stage, which is often carried out using FPGAs, to volume manufac­turing.
Relationship: entailment
Domain: Hardware
Sentence 1: A solution by the GA is in the form of a binary bit stream, each bit indicates whether there is a con.ict at the root of a tree and which method to use to resolve it.
Sentence 2: a 1 means there is a con.ict and method (III) should be used; a 0 means that there is either no con.ict or we should use the better one of methods (I) and (II) to resolve the con.ict.
Relationship: entailment
Domain: Hardware
Sentence 1: Average segmentation accuracies for 25 songs Precision Recall 72.02% 55.23%  Since we focus on timbre feature and do not consider the detailed musical information such as chord, rhythm, or pitch, the precision is higher than the recall.
Sentence 2: our proposed method consider noticeable timbre variation only within music clip and the number of boundaries tend to be smaller compared to the human perception.
Relationship: entailment
Domain: Hardware
Sentence 1: ap ×Ds ×di, j + ßp ×D2 s ×di2 , j (5) i=1j=1p.ri, j The above problem formulation5 is a quadratic programming problem, which can be solved using classic quadratic program­ming methods.
Sentence 2: we use CPLEX [12] in the experi­mental platform described below.
Relationship: entailment
Domain: Hardware
Sentence 1: subset of its pending operations have been dropped.
Sentence 2: for every X C Spending there exists S' = (SR, S~roc, X), where the states in S~oc are identical to Sproc except for processes with operations in Spending  X; 5 no-WRITE if no processes are executing a WRITE (according to Sp~o~); deceiving if it is both possibly-no-pending and no-WRITE.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.2 Hardware Support for Ordered Commits Auto-parallelizing compilers and directive-based parallel programming models(such asOpenMP) typicallyfocus on regular data-intensive loops with no cross-iteration depen­dencies(DOALL).Speculativeloopparallelization andthread­level speculation[26][18] havebeenproposedinthepastto e.ectively extract parallelism from programs whose execu­tion cycles are mostly spent inside non DOALL loops or inside possibly inter-dependent tasks.
Sentence 2: some approaches based on TM and ordered commits have been proposed in the general purpose domain [12] [23].
Relationship: entailment
Domain: Hardware
Sentence 1: We discuss, in Section III, how to incorporate the above stochastic trap models in circuit simulation, i.e., describe techniques for the joint analysis and simulation of an electronic circuit and a number of traps.
Sentence 2: we describe (i) a stochastic, hybrid, Monte Carlo type simulation algorithm, in Section III-B, for the joint simulation of a circuit described by a set of nonlinear differential equations and a number of traps represented by the .ne-grained Markov chain model, (ii) a stochastic, Monte Carlo type simulation algorithm, in Section III-C, for the joint simulation of a circuit described by a set of nonlinear differential equations and a number of traps represented by the coarse-grained Langevin model.
Relationship: entailment
Domain: Hardware
Sentence 1: Since ..(0)= 0 in this special case, it follows from (4)that: ..(...)= A-1..(...)(8) and .... can be expressed as: .... =emax A-1..(...)(9) ...(...).F where emax is an operator that denotes element-wise maximiza­tion of its vector argument, under the given constraints.
Sentence 2: .... is the result of the for-loop: for(.. =1,...,..){maximize the ....h element of the vector A-1..(...),over all ..(...) .F}.
Relationship: entailment
Domain: Hardware
Sentence 1: If a traversal of a contour is started wth the RU direction and at the point with the smallest y coordinate (if there are multiple points point with the smallest y coordinate, choose the one with the smallest x coordinate), the direction pairs enclosed between parentheses in Table 1 would NOT appear.
Sentence 2: in Table 1, the ways of switching for the direction pairs without and with parentheses are independent.
Relationship: entailment
Domain: Hardware
Sentence 1: The .exibility of a super-gate G is de.ned as the sum of the bene.ts of all the super-gates within the subtree rooted at the super-gate G. The .exibility of a super-gate indicates how much its ATEP can be affected by other super-gates.
Sentence 2: the larger a super-gate s .exibility is, the more probable it is that the super-gate s ATEP will be affected by other super-gates.
Relationship: entailment
Domain: Hardware
Sentence 1: normalized repeater size (w /w ) opt 2 b 1.5 1 0.5 1 0.9 0.8 0.7 B  D  E F p erformance r atio A C power ratio  area ratio 0 0.5 1 1.5 2 2.5 normalized segment length (l/l) crit Figure 6: Minimization of total buffer area and power for a 15% of performance degradation for uniform buffer insertion 0.6 0.5 0.4 0.3 0.2 0.1 2.5 normalized repeater size (w/w ) bopt 2 1.5 1 0.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 number of buffers Figure 8: Normalized relation between performance, buffer area and power as function of the number of buffers 0 normalized segment length (l/l) crit Figure 7: Area and Power vs Performance degradation The closed contour shows all normalized segment length and buffer size combinations resulting in the same performance, in Figure 8 further displays the effectiveness of our trade-off model.
Sentence 2: figure 8 shows along the horizontal axis the number of buffers and along the vertical axis the normalized performance (w.r.t.
Relationship: entailment
Domain: Hardware
Sentence 1: To guarantee convergence, we assume that the two sub­optimizations are ideal.
Sentence 2: we require: 1) that the Vdd optimizer returns the energy optimal supply voltage, Vmin, for a fixed set of gate sizes, W and 2) that the gate size optimizer returns the energy optimal set of gate sizes, Wmin, for a fixed supply voltage, Vdd.
Relationship: entailment
Domain: Hardware
Sentence 1: As depicted in these figures, in general, 2D-HERT is the most efficient optical architecture under various traffic patterns, while ETorus leads to the worst power and delay metrics compared to the optical architectures.
Sentence 2: averaging through different traffic patterns, 2D-HERT ONoC reduces data transmission delay by 18%, 4%, and 70% over OXbar, LR, and ETorus, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: Instead, the device driver can simply issue the L INK command, denoted as L INK(p, l, len), to logically copy data of len LBAs from LBAs l (l + len)ofthe storage to pages p (p + len) of the data buffer.
Sentence 2: when the device driver plans to issue a command L INK(p, l, len), it actually cal­culates the starting memory addresses addrp and addrl (of PCM) for page p and LBA l, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: Since no isolation exists between the clock ring and circuit registers, it is a dif.cult task to extract the clock signals with required skews from a rotary clock ring.
Sentence 2: when the clock pin of a register is attached to the rotary ring interconnect, the clock load induced by the register can change the wave prop­agation behavior, resulting in the variation of the clock skews and rotary oscillation frequencies.
Relationship: entailment
Domain: Hardware
Sentence 1: (3) 66960 three-layer implementations; 3883680 four- layer implementations; and so on.
Sentence 2: (4) _~ 18,2 e(r-~) r-layer implementations, for r _> 2, taking into account the 3 * 2 ~-~ possible combinations of primitives, the six possible key ordering, the 31!/(32 -r)!
Relationship: entailment
Domain: Hardware
Sentence 1: In comparison to Figures 2 and 3, we observe a higher STP improvement over naive scheduling for 6-job mixes (17%)thanfor4-job mixes(11%) forthetwo-threadedSMTpro­cessor; onthefour-threadedSMTprocessor, we achieve an average 25% STP increase for the 12-job mixes compared to 13% for the 6-job mixes.
Sentence 2: similarly, we observe a higher ANTT reduction for 6-job mixes(13%) than for4-job mixes(9%)for the two-threaded SMTprocessor; forthefour-threadedSMTprocessor,the average ANTTgoesdownby 16%forthe12-job mixes compared to12% forthe8-job mixes.the morejobsinthejob mix, the better the probabilistic symbiosis model exploits the potential performanceimprovement through symbioticjob scheduling.
Relationship: entailment
Domain: Hardware
Sentence 1: In this slightly simplified version of the original CMOL FPGAs [43] complete logic gates are implemented in CMOS subsystem while memristive devices are used only to connect selectively CMOS gates.
Sentence 2: figure 8 shows one of the many possible signal routings for NOT, AND, OR, NAND and NOR gates and a D-type flip-flop which were successfully programmed and tested.
Relationship: entailment
Domain: Hardware
Sentence 1: By using two ideas, which are the statistical corner conditions in a single layer and the statistical corner correction between layers, the guardband width from the fast corner to the slow corner decreases by half, compared to that by the conventional corner conditions, in average.
Sentence 2: if the capacitance or resistance variation range is +/-20% in the conventional corner conditions, it shrinks to +/-10% in the proposed statistical corner conditions.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION More and more functional veri.cation [5, 7] is adopted to detect design errors exploiting coverage metrics [3, 11] or high-level fault models.
Sentence 2: some high-level fault models [4, 2] have been recently proposed to include the characteristics of traditional coverage metrics [9] (e.g., statement, branch, condition coverage) and logic-level fault models [1].
Relationship: entailment
Domain: Hardware
Sentence 1: To compare multi-corner and statistical re­sults, we project the statistical slacks to their worst corner values as follows: depending on the sign of each sensitivity, the corre­sponding process parameter is moved to its +3s or -3s corner to convert the canonical slack into a single number.
Sentence 2: 2Some of the placeable objects are large macros or memory blocks, so in this case the larger chip has fewer objects.
Relationship: entailment
Domain: Hardware
Sentence 1: The source driver supplies the desired voltage level (called grayscale voltage) according to the pixel value.
Sentence 2: ideally, the pixel value transmittance, t(X), is a linear function of the grayscale voltage v(X), which is in turn a there are 256 grayscales, then the source driver must be able to supply 256 different grayscale voltage levels.
Relationship: entailment
Domain: Hardware
Sentence 1: To apply our approach, a lightweight algorithm should be available to compute a coarse estimate of the feature, and a closed-form expression or heuristic metric is then used to predict the quality of upper-layer application based on the coarsely estimated features.
Sentence 2: our approach can be applied to structural damage localization [18] and most applications based on time di.erence of arrival (TDOA).
Relationship: entailment
Domain: Hardware
Sentence 1: Encoding the prior information based on coefficient magnitude: Several previous works in the literature have  demonstrated that when approximating a nonlinear function such as pdfE(x) or pdfL(x) in (13)-(14) by a set of appropriately selected basis functions (e.g., wavelet basis), many of the resulting coefficients are close to zero [23].
Sentence 2: these coefficients carry a unique sparse pattern.
Relationship: entailment
Domain: Hardware
Sentence 1: The averages for the 100 workloads used in the experiments in Section 5 are 16.2, 35.9 and 40.0% for LRU, DRRIP and NRR respectively.
Sentence 2: 83.8% of the 1 This example workload is composed of the following applications: gcc, mcf, povray, leslie3d, h264ref, lbm, namd, and gcc  lines stored in the SLLC do not provide any bene.t, and replacement algorithms proposed in the literature are only able to reduce this percentage to about 64.9%.
Relationship: entailment
Domain: Hardware
Sentence 1: The above observation motivates us to place the dies of the same technology process in con.ict-free posi­tions on the reticle so that they may be extracted from the same wafer at the same time.
Sentence 2: we must minimize the horizontal con.ict or vertical con.ict situa­tions for the dies of the same technology process but we are not concerned about the horizontal/vertical con.icts for the dies of di.erent technology processes.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION Interconnect prediction plays an important role in different stages in the design cycle because interconnect delay dominates the path delay in the deep sub-micron era.
Sentence 2: at floorplanning and placement stages design tools need fast yet accurate estimations of the physical parameters (wire length, source to sink Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: entailment
Domain: Hardware
Sentence 1: 6.2 Prioritized NAC In this section, we make several observations that improve the effectiveness of NAC by allowing us to apply the N sets of local optimum read reference voltages in an order that minimizes the latency overhead of NAC.
Sentence 2: we observe that some sets of local optimum read reference voltages provide better error correction capability (as they are associated with neighbor cell values that are more likely to lead to errors) and we prioritize their use when NAC is triggered such that we can reduce the number of steps in NAC correction.
Relationship: entailment
Domain: Hardware
Sentence 1: The universal composition theorem of Canetti [12] states that running the composed protocol p. has essentially the same e.ect as run­ning the protocol p in the F-hybrid model.
Sentence 2: if p securely realizes some ideal functionality G in the F-hybrid model then p. securely realizes G. The security of cryptographic protocols analyzed in the 1An event is negligible in k if it happens with a probability that is less than the inverse of any polynomial in k  Functionality FGKE FGKE proceeds as follows, running on security parameter k, with parties U1,...,Un, and an ideal adversary S. Initialization: Upon receiving a value (new-session, sid, pid) from party Ui for the .rst time (where pid is a non-empty set of distinct user identities), record (sid, pid, Ui) and send this to S. In addition, if there are already |pid|-1 recorded tuples (sid, pid, Uj ) for Uj .
Relationship: entailment
Domain: Hardware
Sentence 1: Our objective is to develop automated compiler support based on the latest advances in polyhedral frameworks (e.g., [12, 38]) to greatly reduce the human design effort currently required to create effectively synthesizable speci.cation of designs using HLS tools.
Sentence 2: we develop compiler support for source-to-source trans­formations to optimize critical resources such as memory bandwidth to off-chip memory and on-chip buffer capacity.
Relationship: entailment