sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: 4.3 Software Support Theminimumsupportrequiredfromthesystemsoftwareisthe useofthe proposed memcopy andmeminit instructions toindi­catebulkdataoperationstotheprocessor.Althoughonecanhave aworking system with just this support, maximum latency and energybenefitscanbeobtainedifthehardwareisabletoacceler­atemostcopyoperationsusingFPMratherthanPSM.Increasing thelikelihoodoftheuseoftheFPMmoderequiresfurthersupport fromtheoperatingsystem(OS)ontwoaspects:1)pagemapping, and2)granularityofcopy/initialization.
Sentence 2: 4.3.1 Subarray-Aware Page Mapping TheuseofFPMrequiresthesourcerowandthedestinationrow ofacopyoperationtobewithinthesamesubarray.to maximizetheuseofFPM,theOSpagemappingalgorithmshould beawareofsubarrayssothatitcanallocateadestinationpageof acopyoperationinthesamesubarrayasthesourcepage.
Relationship: reasoning
Domain: Hardware
Sentence 1: ConsidertheexampleshowninFig.4.failuren(Ms,ME)= 0holdsfornE{1,2,3},beausetheoutputwofMEisa­eptedbyMsaswellasMsanonlywaittilltime5(safety failurefreeness),andtheinputwofMsisgivenbyMEin time,andfortheinputuofME,forexample,(u,8),Msan notwaittilltime8ortheotheroutputwanbeaepted (timingfailurefreeness).
Sentence 2: {MI,ME}hasasafetyfailure(u,6), beauseMI1=(u,6),ME11­cÆ6,butME1==(u,6).failuren(MI,ME)=0foranyn(rememberthatfailurenin­ludessafetyfailures).ForMsmandMI,failuren(Msm ,MI)=0 holdsforanyn,beausewofMIistheonly(enabled)input anditisgivenbysintime.Hene,themirrorproperties Mm defnedbyfailure1,2,3donotholdinthisexample,beausefor nE{1,2,3},failuren(Ms,ME)=0andfailuren(MI,ME)=0 (i.e.,MIdoesnotonformtoMs),butfailuren(Msm ,MI)=0.
Relationship: reasoning
Domain: Hardware
Sentence 1: The cost function is de.ned based upon optimization criteria and is normally related to area and latency constraints in high-level synthesis.
Sentence 2: the following equation is adopted to optimize both area and latency of a scheduled, resource allocated CDFG solution: A L ost=a* (-a)* (1) AnormLnorm where Ais the area needed to ful.ll the scheduled CDFG ap­plication, Anormis the average area, Lis the required latency af­ter scheduling, Lnormis the average latency, and acontrols the weights of area and latency, respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: The falling transition arrives at the output (as rising transition) f at 1.9 fs, even before the rising transition arrives at the input of the nor gate.
Sentence 2: both transitions propagate to f. When there is enough time for the non-controlling tran­sition to settle down, we may have a significant distance between the two transitions that propagate with non-robust test vectors.
Relationship: reasoning
Domain: Hardware
Sentence 1: Early Design Stage Thermal Evaluation and Mitigation: the Locomotiv Architectural Case Tanguy Sassolas*, Chiara Sandionigi*, Alexandre Guerre*, Alexandre Aminot* , Pascal Vivet , Hela Boussetta , Luca Ferro , Nicolas Peltier * CEA, LIST, 91191 Gif-sur-Yvette CEDEX, FRANCE -Email: surname.name@cea.fr CEA, LETI, Minatec Campus, Grenoble, FRANCE -Email: surname.name@cea.fr DOCEA Power, 166 rue du Rocher de Lorzier 38430 Moirans, FRANCE -Email surname.name@doceapower.com Abstract To offer more computing power to modern SoCs, transistors keep scaling in new technology nodes.
Sentence 2: the power density is increasing, leading to higher thermal risks.
Relationship: reasoning
Domain: Hardware
Sentence 1: With the assumption of uniform neutron flux and the same technology generation being used for circuit implementation, the total charge efficiency (Qs) can be assumed to be the same for two circuits.
Sentence 2: the SERs for two circuits with the same technology generation can be related to each other as - Qcritical1 Qcritical2 SER = SER * exp{ } .
Relationship: reasoning
Domain: Hardware
Sentence 1: 5) to the time a full-match is reported at the output (mlso) is 339ps, while for a near-match is 692ps.
Sentence 2: while in the usual, error-free case, the NOR-type CAM is 43% faster than the proposed, its cycle time has to follow the worst case, which is 1.42 times slower than the proposed CAM.
Relationship: reasoning
Domain: Hardware
Sentence 1: hii can be expressed as: .2T ' .2 n -Fkhii = = .F2 .F2 Fk i i Ck + (.k · tk)· k=1 Fuc (r (r-3 .i · ti Fi · (.i · ti) = 2Ci · ·Ci + Fuc Fuc > 0 (24) the inequality hii > 0 holds since Ci, .i, ti,Fuc,Fi are all positive numbers.
Sentence 2: we have hii > 0 for all i, which means all the eigenvalues of HT' are positive and thus HT ' is positive de.nite (denoted as HT ' .
Relationship: reasoning
Domain: Hardware
Sentence 1: NSWi = Ei ×loadi × pn (4) n=j.fi(gj ) where Ei is switching activity of net i, gj is the gate driv­ing net j, fi(g) is the fan-in inputs of the gate g and pn rep­resents the probability that net n is at the enabling value.
Sentence 2: the switching activity of a input-output path q with switching in all intermediate nodes and consisting of nets sequence i .j .k .
Relationship: reasoning
Domain: Hardware
Sentence 1: These paired instructions are used to develop synchronization primitives (e.g., test-and-set, compare-and-swap, fetch-and­increment, fetch-and-add) which emulate a lock needed before entering the CS and thereby providing a higher level synchronization facility for the tasks.
Sentence 2: using these primitives, the application program, with its multiple tasks that share memory, can be designed ensuring mutual exclusivity and consistency.
Relationship: reasoning
Domain: Hardware
Sentence 1: For a given polygon with original edge number n, there exists a lower bound of edge number l, and no simpli.ed polygon version can have edge number lower than that bound.
Sentence 2: for a polygon set, we have the summation of all the polygons lower edge number bounds P1 P3 P2 P1: P2: kmin =i li to be the minimum edge number and the summation of all the polygons original edge numbers k P3: to be = ni max i the maximum edge number.
Relationship: reasoning
Domain: Hardware
Sentence 1: On the other hand, after placement, the location of cells and blocks are fixed and buffers must be placed in whatever leftover space remains and there is no guarantee that buffer distribution would be capable of meeting buffer requirements in various regions of the chip.
Sentence 2: a global plan of buffers must be specified using global information in early stages of physical design and the rest of the design flow must be aware of the planned resources [2].
Relationship: reasoning
Domain: Hardware
Sentence 1: In addition, the operation in each clock cycle has to meet the timing requirements in terms of clock cycle time.
Sentence 2: given the clock cycle time, Tclk, the timing yield of this DFG is computed as: Tclk 0 Tfu(t)dt) and the power yield is computed as yield is computed as ( PL ( Pfu(w)dw).
Relationship: reasoning
Domain: Hardware
Sentence 1: We modify our static analysis algorithm, described in Sec­tion 3.2.1, in order to determine the set of independent RTL signals vi (both sequential and combinatorial) in RTL block B.These vi can be viewed as output signals of a set of independent RTL block Bi.
Sentence 2: the modi.ed static analysis algorithm decomposes the original RTL block B into a set of independent blocks Bi.
Relationship: reasoning
Domain: Hardware
Sentence 1: MOSFET pairs can be connected in parallel in case that the PV panel produces higher where is the number of PV cells connected in parallel in a macro­ is the maximum drain current of a MOSFET.
Sentence 2: .. cell, and ........·3 the required number of MOSFETs per PV macro-cell is the indices of PV macro-cells in PV groupdue to the structural characteristics of the reconfigurable PV panel satisfying ... .. .
Relationship: reasoning
Domain: Hardware
Sentence 1: Recently, we have de.ned the semantics of a statement S by the following control .ow predicates [29] and the set of guarded commands guardcmd (., S).
Sentence 2: inside (S) is the disjunction of the pause labels occurring in S. inside (S)holds at some point of time iff at this point of time, the control .ow is at some location inside S. instant (S) holds iff the control .ow can not stay in S when S would now be started.
Relationship: reasoning
Domain: Hardware
Sentence 1: where u = 1 ,q = 0 4pr 0 ** the coe.cients of gj(k) are calculated for each frequency I point, and the integral fj(r) need to be computed only Although in (4), the Laplace fundamental solution ** is frequency-independent, for the volume integral once.
Sentence 2: the computational time of the frequency-u  0,q 0 I dependent integral e-jkr/r can be greatly reduced for the other frequency points except the .rst one.
Relationship: reasoning
Domain: Hardware
Sentence 1: Assume that we .rst adjust the arrival order for site S1,3 and then carry out the adjustment for site S1,2.
Sentence 2: we adjust for site S1,2 after the adjustment for site S1,3.Since D2, D1 and W1,2 arrive at S1,2 serially based on the estimate of the droplet-route lengths from their sources to S1,2, D1 has Waste Reservoir Waste Reservoir (a) (b) Figure 3: Synchronization for two cross-contamination sites: (a) functional-droplet routes and cross­contamination sites S1,2 and S1,3; (b) synchronization of wash-droplet routing with functional-droplet routing.
Relationship: reasoning
Domain: Hardware
Sentence 1: This also helps break the design-verification loop, replacing one big synthesis-techmap-placement-buffering-routing iteration with a sequence of light iterations, each of which refines the design incrementally, but hopefully leads to the final design without any unpleasant surprises.
Sentence 2: without actually using any CbC structural fabric, this approach embodies the core principles of CbC design.
Relationship: reasoning
Domain: Hardware
Sentence 1: Given that the net­work is still mostly secure when f(x) = ft, we would like to guarantee that, after capturing some nodes, an adversary is still not expected to learn more about the rest of the net­work than she has learned about the area covered by these compromised nodes.
Sentence 2: small scale attacks could only be justi.ed by the value of sensor readings of the area cov­ered by the compromised nodes rather than by the amount of information the compromised nodes can reveal about the rest of the network.
Relationship: reasoning
Domain: Hardware
Sentence 1: Of the resulting 65 pins from the original library, 33 pins are ac­cessible, and 10 are expandable for double-via insertion; 17 pins are accessible and 5 are expandable for rectangle-via insertion.
Sentence 2: the proposed nanometer redundant via-aware library (RVALIB) based on RVLC .ow is then used.
Relationship: reasoning
Domain: Hardware
Sentence 1: For exam­ple, a program with its working set entirely .t into a cache slice will perform better with private caching, while large applications with a high degree of data sharing may per­form better on shared caches.
Sentence 2: researchers have further examined optimizations such as cache block migra­tion [18] and data replication [30] in the context of a shared design to improve data proximity.
Relationship: reasoning
Domain: Hardware
Sentence 1: Unfortunately, these models are too simplistic to capture the complex behavior of the network when running real applications, particularly at high packet injection rates.
Sentence 2: finding better approaches to workload characterization remains a fundamental open problem in multicore system design as precise workload characterization can enable better mechanisms for multi-tasking, routing protocols and priorities, power and memory management, caching - virtually all aspects of the computational infrastructure of multicore platforms [7].
Relationship: reasoning
Domain: Hardware
Sentence 1: Such a NN would take as inputs the current tempera­ture and power consumption of points covered by sensors and provide their future temperatures as outputs.
Sentence 2: by simulat­ing a model in a simulator like HotSpot or by using real-chip data, we can train the NN for temperatures of only those points where sensors are fabricated, and thereby learn the weight ma­trices Ar and Br.
Relationship: reasoning
Domain: Hardware
Sentence 1: For instance, the 32-bit MUX in CMOS logic needs 37 input inverters, 1 load inverters and no sense amp, while the 32-bit MUX in CMDL needs 74 input inverters, 2 load inverters and 1 sense amp.
Sentence 2: we can see from Table II that the input power of CMDL is larger than CMOS, the load power and sense amp power are very small and can be ignored, and actually the logic power of CMDL is smaller than that of CMOS.
Relationship: reasoning
Domain: Hardware
Sentence 1: This method makes use of the fact that to retain a value in the SRAM cell, the source voltage of the cell can be just about 1.5 times of Vt.
Sentence 2: for a 70­nanometer technology based SRAM cell that normally oper­ates at 1.0V, the voltage can be reduced to up to 0.3V when accesses are not required while still retaining the data.
Relationship: reasoning
Domain: Hardware
Sentence 1: Instead, partial ACKs received during Fast Recovery are treated as an indication that the packet immediately following the acknowledged one has been lost, and should be retransmitted.
Sentence 2: when multiple packets are lost from a single window of data, New-Reno can recover without a retransmission timeout, retransmitting one lost packet per round-trip time (RTT) until all of the lost packets from the window have been retransmitted.
Relationship: reasoning
Domain: Hardware
Sentence 1: Especially,afunctiondependingononlyonevariableis calledasingle-variablefunction,denotedbySVF.
Sentence 2: thedecompositionconstructedfromatleastonePDF iscalledapartiallydependentdecomposition,andde­notedPDD[10].Itisworthtonoticethatadisjunctive decompositioncanbetreatedasanon-disjunctivedecom­position,denotedNDD,whenatleastone 0component isaPDF[11].Hereandafter,wemeanforanNDDto 0 beaPDDwhoseatleastonecomponentcanbeab­sorbedinto9withoutincreasingthecostof9,inorderto emphasizethebenefcialPDD.ourobjectiveisto fndtheminimalNDDorPDD.
Relationship: reasoning
Domain: Hardware
Sentence 1: Although the in­put opticalconditionsforpolypatterning mightbedi.erent frompolydesign and devices speci.cation, thepolypattern­inggenerally shows atrendin which theILS of aerialimage hasthe maximal valueasshowninFigure4(b),andinwhich thepoly layoutisthe mostrobustfromthelithographypro­cess variation.
Sentence 2: from the results of Figure 5, we can mathematically formulateanoptimalpitch ofpoly lines with the minimal LER impact as follows: min : s(xL)+s(xR) (8) .N where, s(x)= i ,i =0,...,N i=0 aix where s(xL)is theRMS roughness of theleft edge(xL) of a line, and s(xR)is one of the right edge(xL).
Relationship: reasoning
Domain: Hardware
Sentence 1: In doing this for four test images, results indicated that the knee occurs for FIFOs of 4Kwords for the serial and SAE architectures and for FIFOs of 5Kwords for the modified SAE architecture.
Sentence 2: we consider 4Kwords to be the optimum FIFO size for the serial and SAE architectures and 5Kwords to be the optimum FIFO size for the modified SAE architecture.
Relationship: reasoning
Domain: Hardware
Sentence 1: To calculate the ESR and ESL of CNCAP1, we recall from Section 2.1 that the structure uses 2 CNTs/50nm2, giving 40,000 CNTs per µm2 (20,000 anodes and 20,000 cathodes).
Sentence 2: the ESL of CNCAP1 will be: ESLCNCAP 1 =(4nH  # anodes)(1% Metallic ) (2) ESLCNCAP 1 =(4nH 20,000 )(1 0.33 )=0.6 pH µm2 The ESR of CNCAP1 as a function of RC and the percentage of metallic single wall CNTs is given by (3).
Relationship: reasoning
Domain: Hardware
Sentence 1: This informa­tion is stored in each local cache in the form of a bit vector that indicates, for each source-destination pair, whether the local router is part of the valid route.
Sentence 2: to de­tect misroutes, the local check algorithm iterates through the snapshot entries, obtains the source and destination of each entry, and checks it against the valid paths information (lines 13-16 in Figure 5).
Relationship: reasoning
Domain: Hardware
Sentence 1: It was found in [8] that the CRPs with longer settling times have larger inter-die HDs that approach 50%, while the intra-die HDs increase relatively slowly as the settling times get longer, making the difference between inter- and intra-die HDs larger and larger until some point where the difference reaches its optimum.
Sentence 2: using the method that enrolls only CRPs which stabilize in a proper interval (e.g., a short interval before the optimum point, where the interval inter-die HD is close to 50% and the interval intra-die HD is still relatively low) in a PUF-based protocol would effectively improve the combined performance of uniqueness and reliability.
Relationship: reasoning
Domain: Hardware
Sentence 1: The trace concomitance t(a,b,T ) gives information about how tightly interleaved the executions of two distinct basic blocks a and b in the trace T are.
Sentence 2: for a basic block a we consider all of its consecutive executions e(a), e1(a) in the trace T , for which there exists at least one execution of the block b between the executions e(a) and e1(a); we denote such fact by b .
Relationship: reasoning
Domain: Hardware
Sentence 1: Otherwise, the server should handle responses from multiple tags.
Sentence 2: on the other hand,atag should notrespondbeforeproperly au­thenticating the server sincea query may notbefrom an au­thentic server, but from an attacker who wants to track the tag.theprotocol shouldbea one-roundprotocol, and a tag should authenticate the server without giving any challenge.
Relationship: reasoning
Domain: Hardware
Sentence 1: In the architectural level this critical point is responsibility of the sum operations on wide inputs and of the consequent delay generated by the carry propagation in the ripple carry architecture used in the adders [2].
Sentence 2: the main objective of this work was to increase the JPEG compressor performance through the substitution of the architectures used in the adders, with main focus in the carry lookahead, hierarchical carry lookahead and carry select architectures [4, 5, 6].
Relationship: reasoning
Domain: Hardware
Sentence 1: For example, the instantiation of a NoC proposed in [7] including 6 switches and 4 TGs and 4 TRs uses 7387 Xilinx slices (79% of our device), and its emulation time for 16 million packets on our platform clocked at 50 Mhz takes 3.2 sec.
Sentence 2: with present larger devices used in NoC (e.g.
Relationship: reasoning
Domain: Hardware
Sentence 1: Anumberofassumptionsareneededtounderstandthe pseudocode.Weassumethatvirtualregistersarenumbered andcanbeidentifedbyanintegerindexr.Thevectortsr representsthetimewhenthesingleassignmentEVRris producedrelativetothestartofthatiteration.Likewise, terrepresentstheendofthelifetimeofEVRr(thetime ofthelastuse)relativetothestartoftheiteration.These startandendtimesrepresentthetimethatthedataenters theShiftQinterconnectandthetimeatwhichthedatais lastneededwithintheinterconnect.
Sentence 2: thecalculationofthetimeofproductionmustaccom­modateactualfunctionunitoutputlatency,to,atwhicha destinationoperandrisavailablerelativetothestartofthe operationpthatproducesr.Thatis, m tsr =tschedp+to p where,theoperandristhem thresultoperandoftheop­erationp.Likewise,asourceoperandrisconsumedata timethatisadjustedbytheinputsampletimetirelative tothestartoftheconsumingoperationc.the timeoflastuseiscomputedasthemaxofsuchtimesover allconsumerreferencescr.Thatis, max ter =cr(tschedc+tin) c wheretheoperandristhen th sourceoperandoftheoper­ationc.
Relationship: reasoning
Domain: Hardware
Sentence 1: Similarly, the probability that the size of Partition 1 decrements by one line is also I1 × (1 - I1).
Sentence 2: the size of Partition 1 with a smaller I1 ×(1 - I1) will have less possibility to be deviated away from its target and, hence, its size deviation distribution curve will be more skewed towards x =0, which is better.
Relationship: reasoning
Domain: Hardware
Sentence 1: ti,2 E(Ai) = Pi( fi(t))dt (4) ti,1 where ti,1 and ti,2 are the start and ending times of the execution of task Ji.
Sentence 2: the total CPU energy consumption, ECPU , excluding that in DC-DC converter for N tasks (J1, J2, · · · , JN ) is Initial step: Step 1: Step 2: N. ti,2 N ti,1 ECPU = Pi( fi(t))dt .
Relationship: reasoning
Domain: Hardware
Sentence 1: DDR transmitter buffer driving behaviors and the corresponding currents (normalized) drawn from the power net and sinking into the ground net Unlike the core system, for which the current flowing out of the power net (Icc) is always the same as the current sinking into the ground net (Iss), DDR transmitter (TX) buffer is a single ended circuit with a signal channel connecting to the dual in-line memory module (DIMM) outside the chip.
Sentence 2: as shown in Figure 6, during the stage of writing 1 or 0 , there is a current (DIMM current) flowing out of or into the power delivery system to/from DIMM.
Relationship: reasoning
Domain: Hardware
Sentence 1: Our analysis of several array­intensive applications shows that a signi.cant fraction of com­putations that depend on disk data are of .ltering type, that is, the amount of the input data is larger than that of the out­put data.
Sentence 2: it is possible to reduce the amount of data to be communicated between the disk system and the host system by executing this .ltering type of computations on the disk system.
Relationship: reasoning
Domain: Hardware
Sentence 1: Given the variable degree of 4, the maximum circulant size that can be found without increasing the original code length (9184) of the target .ash memory is 204 ×204.
Sentence 2: a regular (9180,8364) QC-PEG code is designed for our target .ash memory, with variable degree of 4 and check-node degree of 45 (c=45).
Relationship: reasoning
Domain: Hardware
Sentence 1: However, intuitively, one one may expect a greater .eld margin (difference between would expect a logic 1 state to be preferred since Magnet D should experience stronger F-coupling from Magnets B and H0 H1 A .nal observation demonstrates that another factor needs to be A and ) by placing the functional layers close, our C combined.
Sentence 2: when designing pNML circuits, the possibility of a domain wall must be considered.
Relationship: reasoning
Domain: Hardware
Sentence 1: 4(b) then makes N6 and N8 access the register .le in island A, and at the same time N7 access the register .le in island D, generating no access con.ict.
Sentence 2: this results in 5 clock steps and IIC = 3 (IIC from A to C will not be created due to the existing IICs in the routing path A.D.C).
Relationship: reasoning
Domain: Hardware
Sentence 1: Dividing Equation (7) by Equation (5) yields: µ()S DR() sS5 () = (--())(8) µS () () MSsR 5 S5 R If we let adenote the constant s()s/ (), then solving Equation (8) for DR yields our delay estimate for the () ramp response: DR= (1 a)µS+ MS(9) () () a() 2 R2 S2 I Recall from Equation (4) that s()= s+ () () swhich implies that the constant alies between zero and one.
Sentence 2: areflects the amount of trade-off between the Elmore Delay (µS) and the step delay metric MS () ().
Relationship: reasoning
Domain: Hardware
Sentence 1: A truncated multiplier removes S1, S2, and S3 from the partial product matrix causing the total error to be altered.
Sentence 2: the total error for a CCT Booth mul­tiplier is modi.ed by adding an extra term, Eulp to account for removing these bits: Etotal = Ereduction + Erounding + Eulp S-k-1 S-1 X X 1 q +1 -m-n+q 1 -m-n+z Etotal = ll·2+ · 2 42 2 q=0 z=S-k min{ S-k-1 , n 2 -1 } 2 X 3 -m-n+q·2 · 2 8 q=0 The value of 3/8 is the probability mass function that Booth recoding requires sign-extension.
Relationship: reasoning