sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Basic register level clock gating has been employed for decades.
Sentence 2: a deep understanding of the implications of low power design is required to make critical decisions, such as selecting which analog sections are to run at high supply voltages, and the best type of transistor (thin oxide, thick oxide or compound) to be used in order to circumvent one of the main roadblocks in 65nm CMOS technologies the low nominal supply voltage.
Relationship: neutral
Domain: Hardware
Sentence 1: [7] V. Ganapathy, S. A. Seshia, S. Jha, T. W. Reps, and R. E. Bryant, Automatic discovery of API-level exploits, in ICSE, May 2005, pp.
Sentence 2: the scalability of the CEGAR framework directly depends on 1) the ef.ciency of solving the abstracted model and 2) the effectiveness of re.nement.
Relationship: neutral
Domain: Hardware
Sentence 1: CONCLUSIONS This paper presents an effective approach to discover repeating patterns and musical structure from acoustic signals.
Sentence 2: on the helix, the adjacent notes are 7 semitones apart instead of 1 semitone, so we should re-order them to give an appropriate weighting, as 1 w(m) = | P(7m mod 12 ) - P(0) | (10) A where P(m) is the position of m-th note and set as [10] suggested, m7 m7 m P(m) = [sin ,cos , ] (11) 2 22 and A is a normalization coefficient to satisfy w(m) = 1 .
Relationship: neutral
Domain: Hardware
Sentence 1: Our placer formulate maximum displacement constraint Ddisp as: Ddisp max(|xc - xc0| + |yc - yc0|) (2) cEC where C is the set of all movable cell, (xc, yc) is the current position of cell c , (xc0, yc0) is the original position of cell c in the given global placement solution.
Sentence 2: [9] M.-C. Kim, N. Viswanathan, C. J. Alpert, I. L. Markov, and S. Ramji.
Relationship: neutral
Domain: Hardware
Sentence 1: The information contained in the ribosomic genome SH thus defines the logic function of each molecule and its connections to the other molecules in the cellular space by assigning a molecular code NPMDPEF to it.
Sentence 2: one of the most important lessons that can be drawn from nature in the domain of fault tolerance is that the presence of several mechanisms operating together at different levels of complexity provides considerable advantages over any single­level system.
Relationship: neutral
Domain: Hardware
Sentence 1: ARM, Motorola s MPC, Infineon s Tricore), have some similarity with IFRA in that they also store program flow of the software executed on the processor.
Sentence 2: 4.5) 4 4 Dispatch Parity of renamed registers 3 4 Issue Parity of operands 2 4 ALU 3-bit residue of result + ALU error signal 4 2 Branch 3-bit residue of operand 3 2 MUL 3-bit residue of result + MUL error signal 4 2 LSU Address + residue of value 35 2 Commit Events (misprediction, cache/tlb miss, interrupts) + committed bit 5 4 3.2 Failure Detection using Post-triggers In order to ensure that the entire error-to-failure history is captured using reasonably sized FRS s, we assume the presence of early failure detection mechanisms, post-triggers, for the failure scenarios listed in Table 3.2.
Relationship: neutral
Domain: Hardware
Sentence 1: Circuits PBBI [1] LAB (New) # of bu.ers Time(s) # of bu.ers Time(s) Reduction Speed up c432 61 0.4 37 1.5 39.3% 0.26x c499 69 0.7 47 1.2 31.8% 0.58x c880 48 1.9 29 0.7 39.5% 2.71x c1355 143 3.9 78 3.6 45.4% 1.08x c1908 137 16.9 96 7.6 29.9% 2.22x c2670 187 63.2 94 10 49.7% 6.32x c3540 202 85.2 109 21.6 46% 3.94x c5315 269 194.4 164 21 39% 9.25x c6288 508 182 433 149 14.91% 1.22x c7552 282 429.4 208 49.5 26.2% 8.67x Average 36.2% 3x respect to number of bu.ers inserted and the CPU time.
Sentence 2: per­forming this greedy bu.er insertion only on the critical nets prevents it from adding a lot of unnecessary bu.ers.
Relationship: neutral
Domain: Hardware
Sentence 1: Suppose that TFT circuits are on the top surface of the substrate so inward bending compresses the circuit while outward bending stretches the circuit.
Sentence 2: [12] H. Gleskova, S. Wagner and Z. Suo, Failure Resistance of Amorphous Silicon Transistors under Extreme In-Plane Strain, Applied Physics Letters, 1999 Figure 7: DLi map of s38584 (RUB 0.1×0.1, Ap/p0 = -25%).
Relationship: neutral
Domain: Hardware
Sentence 1: In this work, our primary purpose is to carefully de.ne the diagno­sis problem for delay defects and understand what are the key aspects that make the problem different from traditional diagnosis.
Sentence 2: the stuck-at fault model is widely used in many diagnosis algorithms that can often be clas­si.ed into two types: an effect-cause approach and a cause-effect ap­proach [6].
Relationship: neutral
Domain: Hardware
Sentence 1: DYNAMICCAPACITANCECONCEPT Most timing analysis methodologies used in practice in both past and present, pre-characterize and store in libraries the driving behavior of logic gates.
Sentence 2: parameterizing the output current waveform as a function of this instantaneous capacitive load is equivalent to assuming that the gate is described by the one-state nonlinear dy­namical system in Equation (1).
Relationship: neutral
Domain: Hardware
Sentence 1: The wide range of applications (e.g., 3D games, web browsing, video decoding) that are possible to execute on mobile devices complicate the problem of power es­timation.
Sentence 2: then from basic rules of physics [1], Nm(x, y, t) and Nb(t) are related by Nm(x, y, t)= e(x, y)Nb(t) + (1 - e(x, y))Na(x, y), (12) where Na(x, y) is photon re.ection count from the ambient envi­ronment at location (x, y).
Relationship: neutral
Domain: Hardware
Sentence 1: The precise estimation of the area of each cone makes it possible in turn to simply evaluate the latency (and thus the throughput) of any solution.
Sentence 2: if the on-chip memory size is limited (only a few kBs for most of the devices used in the multimedia .eld), the performance is bound by the memory transfers that take place between the off-chip and the on-chip memories at each iteration.
Relationship: neutral
Domain: Hardware
Sentence 1: This turns o. the NFET device and the PFET de­vice operates as a source-follower.
Sentence 2: sUPPLY VOLTAGE (V) measurement with supply voltage reset in 0.1V increments Leakage consumption of a macro with DUT-TYPE B is compared to that of the macro hardware with DUT-TYPE A when in PARK and COLD modes in the plot of Figure 11.
Relationship: neutral
Domain: Hardware
Sentence 1: CML and running in the GHz range was proposed [1].
Sentence 2: the advantages that make CML unique are that it does not require emitter followers at the gate outputs and it can be biased at lower * Both authors have the equilibrium contribution    Route 1: The combinational / sequential logic signal path Route 2: The bypass signal path C F2 F1 Q F3 R S CLK Clear CLB   Figure 1.
Relationship: neutral
Domain: Hardware
Sentence 1: The total coupling energy is calcu­lated for each magnetization con.guration (a total of 25=32 states) based on three di.erent coupling considerations.
Sentence 2: the magnetization state of magnet i, Myi , is set to Ms (resp., -Ms) if bit i of q is 1 (resp., 0), where Ms is the saturation magnetization of the magnet.
Relationship: neutral
Domain: Hardware
Sentence 1: CoLT: Coalesced Large-Reach TLBs Binh Pham* Viswanathan Vaidyanathan* Aamer Jaleel Abhishek Bhattacharjee* * Dept.
Sentence 2: using higher order bits for set indexing increases con.ict misses since more consecutive entries are mapped to the same set.
Relationship: neutral
Domain: Hardware
Sentence 1: First, because of Condition 2,all edges(v1,v2) in EA.nity such that v1 and v2 interfere need to be removed from G. The obtained graph PrePruned G is bipartite.
Sentence 2: we use a heuristic algorithm based on a greedy pruning of edges, where edges with large weights are chosen .rst.
Relationship: neutral
Domain: Hardware
Sentence 1: [2] B. Catanzaro, S. Kamil, Y. Lee, K. Asanovic, J. Demmel, K. Keutzer, J. Shalf, K. Yelick, A.
Sentence 2: first Workshop on Programmable Models for Emerging Architecture (PMEA) at the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT 09), Raleigh, North Carolina, September 2009.
Relationship: neutral
Domain: Hardware
Sentence 1: We have presented a regression based MAX computation technique that can be used to rep­resent each arrival time as a polynomial in the underlying 0.2 0.1 0 Primary Output Arrival Time in ps Figure 4: CDF Result for C880 parameters.
Sentence 2: furthermore, each of these parameters were assumed to have a uniform distribution to see the e.ects of relax­ing the gaussian distribution assumption to consider a more general approach.
Relationship: neutral
Domain: Hardware
Sentence 1: As expected, Figure 10 shows significant correlation for the number of sent messages, ranging from average 5 with the lowest WER levels and decreasing to approx.
Sentence 2: average WER per noise level for native speakers 0.5 0.4 0.3 0.2 0.1 0 Figure 5: Average observed WER levels for artificial noise conditions introduced to collect samples with higher WER; showing 95% confidence intervals.
Relationship: neutral
Domain: Hardware
Sentence 1: Suppose we are mapping a node u in the DFG that has predecessors v1,v2,...vx.
Sentence 2: 11: Speedup of JiTC and extensible processor over the baseline processor and the maximal speedup for extensible processor with unlimited area earlier, we selected 21 benchmark applications from MiBench [15] that all ISEs are implemented as dedicated functional units in the and MediaBench [21] to derive the design of the SFU.
Relationship: neutral
Domain: Hardware
Sentence 1: The read width is set to 64 cells (64 bits for SLC and 128 bits for MLC) and the write width is limited to 16 cells (16 bits for SLC and 32 bits for MLC) due to the large amount of current that is required for SET and RESET operations.
Sentence 2: when an MLC PCM cell degrades to SLC mode, most of the components in the MLC writing scheme become unnecessary.
Relationship: neutral
Domain: Hardware
Sentence 1: The DC power dissipation of M2 and, thereby, the tem­perature sensed by Q1, may vary due to process variations occurring within the LNA.
Sentence 2: if the defect induces a DC power dissipation in M2 that saturates the output of the temperature sensor and through the calibration procedure we succeed to bring the output to the prede.ned value V ref , then the temperature sensor is not able to detect this defect in this mode.
Relationship: neutral
Domain: Hardware
Sentence 1: It should also be noted that it is not a good idea to try to bring the non-local elements to the local SPM and keep them there until they are requested by other processors.
Sentence 2: they can bring (and pro­cess) their data tiles in such a way that whenever one processor needs a non-local array element (to perform some computation), the needed data can be found in some remote SPM.
Relationship: neutral
Domain: Hardware
Sentence 1: The experimental results we present will pro­vide valuable guidance in deciding these eventual design choices.
Sentence 2: this comparison allows GEMS the .exibility to not fully implement a small (complex and infrequent) subset of the SPARC ISA GEMS uses the comparison to make its state consistent with that of Simics in case of a mismatch that would occur with such an instruction.
Relationship: neutral
Domain: Hardware
Sentence 1: The last section draws some conclusions.
Sentence 2: categories and Subject Descriptors B.8.1 [Hardware]: Performance and Reliability Reliabil­ity, Testing, and Fault-Tolerance ;C.4 [Computer Sys­tems Organization]: Performance of systems Fault tol­erance General Terms Reliability  Keywords SEU, Fault detection, Partial Dynamic Recon.guration 1.
Relationship: neutral
Domain: Hardware
Sentence 1: Both these cases result in a hazard-free transition at the gate s output.
Sentence 2: if the delay on path {o,q} (from FF3 to FF4) is less than T-d, FF4 captures the correct value in the next clock cycle in spite of a delay failure existing on p. HT failure of {d,g,k,m} masks the setup-time failure on {p,q}.
Relationship: neutral
Domain: Hardware
Sentence 1: Second, using a spacetime decomposition of computation in the circuit ab­straction, physical-information-theoretic analyses of the global system evolution are performed for the time intervals relevant to each computational step.
Sentence 2: even in this idealized scenario where the particle supply requirements are at their absolute minimum particle-supply accounts for 99% of the lower bound on the dissipative cost, far exceeding that required for implementation of the irreversible computation.
Relationship: neutral
Domain: Hardware
Sentence 1: To deal This work is funded by NSF CAREER Award CCF-0448534, UC Micro #05-111 via Cadence Design System Inc. with more ports, we have more transfer functions and thus more poles and residues to compute.
Sentence 2: i Hierarchical reduction is to eliminate all the variables in x, and transform (9) into the following reduced set of equations: MBB* MBR B bB* x MRB MRRR=, (10) xbR MBB - MBI(MII)-1MIB where MBB* = and bB* = bB - MBI(MII)-1bI.
Relationship: neutral
Domain: Hardware
Sentence 1: The wpscheme is relatively robust to W2W variation since the cache lines in the same cache set are distributed across four different layers.
Sentence 2: categories and Subject Descriptors B.3.2 [Memory Structures]: Design Styles - cache memories General Terms Performance, Design, Reliability Keywords 3D microprocessor, Last-level cache, Narrow-width value, Process variation, Yield 1.
Relationship: neutral
Domain: Hardware
Sentence 1: BRENNAN, S., CHENA, X., DICKINSONA, C., NEIDERA, M., AND ZELINSKY, G. 2008.
Sentence 2: findings also high­light the urge to improve presentation display technology so that the width and quality of the .eld of view better resemble normal viewing conditions.Thiswouldmake theuseofHMDsmore intu­itive and provide more natural viewing and interaction conditions.
Relationship: neutral
Domain: Hardware
Sentence 1: In summary, the use of the functional memory inter­face allows a quick iteration cycle, since changes are car­ried out within minutes, and, due the high simulation per­formance, pro.ling results showing latency cycles, cache hit/miss rates, and bottlenecks in the memory architecture are quickly obtained.
Sentence 2: the resulting binary ex­ecutable has been run on the simulator generated from the LISA model.
Relationship: neutral
Domain: Hardware
Sentence 1: This is because the sensor is self-calibrating: process variations that affect leakage currents also affect the capacity of the cell in a counterbalancing manner.
Sentence 2: compared to previously proposed sensors, the 4T-decay sensor needs only 30 transistors, is an order of magnitude smaller, and consumes at most 221µW at 85o C, fairly low if we take into account its relatively high frequency response of up to 24 MHz.
Relationship: neutral
Domain: Hardware
Sentence 1: In the slave-side arbitration, the arbiters are located in front of each slave port as shown in Figure 2 and the master just starts a transaction and waits for the slave response to proceed to the next transfer.
Sentence 2: rEFERENCES [1] Jian Liang, Swaminathan, S., Tessier, R. ASOC: a scalable, single chip communications architecture.
Relationship: neutral
Domain: Hardware
Sentence 1: After that, testability strategies must be applied to RTL structure to produce a testable circuit [3], and this may produce a circuit that is not area-optimized.
Sentence 2: considering descriptions used for similar problems, the main components of an evolutionary-based high-level synthesis approach are as follows: Chromosome structures that represent candidate scheduling, module binding and register allocation solutions;  Fitness evaluation function that performs the latency calculation, module and register usage rapidly for target of testability improvement;  Genetic operators that alter the scheduling, module binding and register allocation while preserving their dependencies.
Relationship: neutral
Domain: Hardware
Sentence 1: Then, at time tj+1,the n-th sensor reads the real temper-2.5 ature value T(xn,tj+1) and quantizes the prediction error E(xn,tj+1)= T(xn,tj+1) - T.(xn,tj+1), getting the quan­ tized output ET(xn,tj+1), with an scalar quantizer Q.Next, all the sensors send their quantized prediction errors to the BS, which obtains a reconstruction for each temperature T value T(tj+1) by adding these quantized prediction errors to the previously predicted values, that is, TT(xn,tj+1)= T.(xn,tj+1)+ ET(xn,tj+1), n =0,... ,2M (18) Then, the BS starts performing the prediction operation again and the whole process is repeated.
Sentence 2: )is very similar to the PSD of a a .rst-order discrete-time autore­gressive source.
Relationship: neutral
Domain: Hardware
Sentence 1: This tech­nique has primarily been applied to I/O drivers and long intercon­nects [13].
Sentence 2: [13] V. Kursun, R. M. Secareanu, and E. G. Friedman, CMOS Voltage Interface Circuit for Low Power Systems, Proceed­ings of the IEEE International Symposium on Circuits and Sys­tems, May 2002.
Relationship: neutral
Domain: Hardware
Sentence 1: Short Paper: Low-Cost Medium-Range Optical Underwater Modem Feng Lu, Sammy Lee, Jeffrey Mounzer, Curt Schurgers Electrical and Computer Engineering Department University of California, San Diego {f1lu, sjl006, jmounzer}@ucsd.edu, curts@ece.ucsd.edu ABSTRACT Enhancing underwater instruments with networking capa­bilities is opening up exciting new opportunities for remote ocean exploration.
Sentence 2: while for the bit error rate, in each round, the transmitter keeps sending data packets until 6 packets have been successfully detected and received by the receiver.
Relationship: neutral
Domain: Hardware
Sentence 1: [4] C. Bartoschek, S. Held, D. Rautenbach, and J. Vygen: Ef.cient Generation of Short and Fast Repeater Tree Topologies , Proceedings of the International Symposium on Physical Design (2006), 120 127.
Sentence 2: when a new repeater I with input pin p is inserted, we compute RAT (p) as follows.
Relationship: neutral
Domain: Hardware
Sentence 1: In this section, we build upon this observation to introduce two mechanisms that both aim to minimize bit error rate: Neighbor-cell Assisted Reading (NAR) and Neighbor-cell Assisted Error Correction (NAC).
Sentence 2: the variances of conditional distributions of victim cells are close when different values are programmed to their direct-neighbor aggressor cells (e.g., var(xm) is close to var(xn) even if m is not equal to n) and thus are approximately equal to the average variance of all conditional distributions.
Relationship: neutral
Domain: Hardware
Sentence 1: We then discussed several components of our measurement effort measurements of coarse grain characteristics of simulation and analysis jobs running on ALCF resources, synthesis of these measurements into project footprints, early results from new streaming experiments that connect the BG/P simulation resource to the analysis and visualization cluster, and wide-area experiments.
Sentence 2: the principal components of the system to be used as a generic testbed are shown in Figure 3.
Relationship: neutral
Domain: Hardware
Sentence 1: Less severe supply voltage degrada­tion leads to transistor performance degradation, e.g., a 10% sup­ply voltage degradation is responsible for more than 10% transis­tor performance degradation, and the effect is super-linear [15].
Sentence 2: in Section 3, we present two convex programming approaches, i.e., a semide.nite program and a linear program, with an illus­trative example.
Relationship: neutral
Domain: Hardware
Sentence 1: Suppose the variables x1, x2 and x3 are set to be false, true, and false, respectively, so that clause c1 is not satis.ed.
Sentence 2: xi* i,*: ri* occupies p = 4LP(dmax) = 4OPT (dmax)  LPAPX is a 4-approximation algorithm.
Relationship: neutral
Domain: Hardware
Sentence 1: The main reason is that, various parameters of these ANN applications are carefully tuned in order for these applications to achieve less than 1.0% error rates.
Sentence 2: the expression of Cij can be seen as a re.ection of the non-linear summation properties observed in some dendrites [23]: when the weight Wij is low, the contribution is very negative (non-linearity).
Relationship: neutral
Domain: Hardware
Sentence 1: modsi3 proc is an internal function used to implement a software version of the modulus function, sim­ilar to mulsi3 proc,and divsi3 proc.
Sentence 2: finally, Xilinx supports an IP core, the Microprocessor De­bug Module (MDM) that enables the user to perform JTAG based debugging on a con.gurable number of MicroBlaze processors.
Relationship: neutral
Domain: Hardware
Sentence 1: Area and energy es­ timates for cache and SPM are obtained from Cacti [31, 45].
Sentence 2: although objects b1 and b2 are not chosen at the cut-off point for SPM, they can nevertheless .t in SPM by shar­ing space with objects a1 and a2, since (b1,b2) are never live at the same time as (a1,a2).
Relationship: neutral
Domain: Hardware
Sentence 1: A sequence of gates in the net­work which matches the sequence Gi G(i-1) mod m ... G(i-k+1) mod m is replaced with the sequence G(i+1) mod m G(i+2) mod m ... G(i-k) mod m without changing the net­ m work output, where k .
Sentence 2: for example, the second template in Fig.
Relationship: neutral
Domain: Hardware
Sentence 1: Thebody-biasvoltageandfrequencyofeachislandcanbetunedpost-fabricationonaper-diebasistominimizetheleakagepowerdissipationofeachdie.Asdiscussedin[14],itisnotfeasibletoallowforacontinuousrangeofbody-biasvoltageandfrequencyvalues.Instead,asin[14],weassumethatthebody-biasvoltagesandclockfrequenciesarerestrictedtoadiscretesetofuniformlyspacedvalues,controlledbyadigitalinput.Finally,sinceeachis­landonagivendiecanpotentiallyrunatadifferentspeedafterbody-biasing,weassumethatinter-islandcommunicationoccursviapoint-to-pointasynchronousFIFOs[3],whileintra-islandcom­municationlinkscanbefully-synchronous.
Sentence 2: tomeasuretheperformanceofataskgraphT mappedonthesetofPEsP,wedenotetheexecutiontimeoftaskti (1= i = N)onitsPE,M1(pi),by.i.Thecompletion time oftaskti isde­notedby.i andcanbecomputedas.i =.i foreveryinput node inT andas.i = .i +maxj:(tj,ti).E(.j )forallothernodes.Everyterminalnodeti inthetask-graphhasanassociateddead­lineconstraint.i,andtheperformanceconstraintsaremetonlyif.i = .i foreveryterminalnode.Fornotationalsimplicity,intherestofthispaper,wewillassumethateveryterminal node hasthesamedeadlineconstraint..wenotethatourframeworkdoesnotneedthisassumptiontobesatis.ed,andtheresultsaredemonstratedforageneralcaseinwhicheachterminalnodehasadifferentdeadlineconstraint.Thedeadlineconstraintsdescribedabovecanbetranslatedtopath based constraintsbyde.ningasetofallpaths,F= {f1,f2,...,fS },inthetaskgraph.Eachfi (1= i= S)isasubsetoftasksinT thatformapathfromaninputnodeinT toaterminalnode.Giventhesepaths,wecanexpressthedeadlineconstraintsas: .i = .,.j :fj .
Relationship: neutral
Domain: Hardware
Sentence 1: Impact of disable time with small keeper: (a) delay,  (b) energy/operation due to the stronger driving capability of the keeper.
Sentence 2: comparing the lowest energy consumption between baseline (achieved at Vdd=0.6V) and the adaptive design (at 0.3V), 4.4× and 3.6× improvements are still obtained in PS0 and PCHB, respectively.
Relationship: neutral
Domain: Hardware
Sentence 1: y2 = x1 x2 y2 + x1 x2 y2 + x1 "JJ2 "JJ2 "JJ2 ON OFF DC where the ON, OFF and DC sets are ON(R .
Sentence 2: the CPU times highly depend on the .exibility of the relation and on the number of reduce/expand/irredundant iterations performed by gyocro.
Relationship: neutral
Domain: Hardware
Sentence 1: {0, 1}), and (B - 1)(1- e)= 0, andLemma4, wehave: .i +.l* +.e = (a +1)Y +bB +1 = WVR.
Sentence 2: [5] K.IbrahimandE.Strohmaier.CharacterizingtheRelationBetweenApex-Map SyntheticProbes andReuseDistanceDistributions.In ParallelProcessing (ICPP),201039thInternationalConference on,pages353 362,sept.2010.
Relationship: neutral