sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Based on the graphical analysis it is evident that as TSOP54 Testers is increased to its high level, both the mean and the variance of WIP and cycle time decrease.
Sentence 2: as both the percentage of Hot Lots and the Product Mix are set to their high level, it can be ob­served that both the mean and the variance of WIP (and cycle time) increase.
Relationship: contrasting
Domain: Hardware
Sentence 1: Figure 8 illustrates that the three-slot output EBs of the baseline router have 175% more gates than the two-slot out­put EBs, showing how expensive the FIFO logic of the three­slot output EBs is compared to the control logic for two-slot EBs.
Sentence 2: the output EB cell count is practically not a.ected because the dominant portion is the datapath.
Relationship: contrasting
Domain: Hardware
Sentence 1: If all the VPN partitions of the application can be accommodated within the CTT, they are loaded during system setup.
Sentence 2: when this is not possible due to large number of VPN partitions across all the hot­spots, the PIT and CTT have to be initialized with the appropri­ate data just prior to entering the hot-spot, thus sharing CTT space with other hot-spots and processes.
Relationship: contrasting
Domain: Hardware
Sentence 1: This corroborates the position that simply applying error correct­ing codes (ECC) to the words stored within the register .le is a po­tentially valuable tool in protecting against the effects of transient faults occurring in state elements.
Sentence 2: figure 5(b), demon­strates that when transient faults occur in combinational logic, and they manifest as errors in architectural state, multi-bit errors of four bits or more account for more than 45% of the occurrences.
Relationship: contrasting
Domain: Hardware
Sentence 1: Moreover, given the right spacing and isolation between the surface and integrated cir­cuits will signi.cantly reduce the interference.
Sentence 2: for reasonable assumption we should consider that the channel 0 -24 10 -24 -26 -28 10-5 -30 -30   Voltage gain S21 (dB) -32 -32 10-10 -34 -34 -36 -36 10-15 -38 -38 Distance(cm) Distance between transmitter and receiver (cm) SNR(dB) (a) (b) (c) Figure 5: (a) Experiment results showing power decay with distance (b)Measurement vs. calculated voltage gain compari­son for di.erent frequencies (c)Bit-Error-Rate vs. SNR for FDMA/CDMA with 20GHz channel bandwidth divided to 128 subchannel is not noise free.
Relationship: contrasting
Domain: Hardware
Sentence 1: In seismics,6,7 as well as in room acoustics,8 the Kirchhoff dif­fraction approximation has commonly been employed in time-domain methods for edge diffraction.
Sentence 2: as has been shown using the Biot Tolstoy expressions,9 and other accurate methods,10 the Kirchhoff diffraction approximation leads to large errors, not only for low frequencies but also for a)Present address: Department of Telecommunications, Norwegian Univer­ sity of Science and Technology, N-7491 Trondheim, Norway.
Relationship: contrasting
Domain: Hardware
Sentence 1: Of primaryinteresttothis workis a multitudeofrecentmicroar­chitecturalDMRproposals, whichjointogethertwo coresto reliably execute oneVCPU[12,14,19,29,33,38].Two of these in particular suggest that DMR can easily be turned on and off[19,32],however,they do notinvestigatetheis­suesinvolvedindoing so.Thereis nothinginherentin any of theseDMRproposals thatisincompatible with the mod­i.cationsfor mixed-mode executionproposedin thispaper.
Sentence 2: as thispaperdemonstrates, runningsome applica­tionsinDMR mode and someinhigh-performance modeis not asstraightforward asit might .rst appear.
Relationship: contrasting
Domain: Hardware
Sentence 1: The reason why the RACSdecay has a larger energy con­sumption is because dead time intervals of cache blocks get shorter as explained Section 3.1.
Sentence 2: lACS reduces the energy consumption by 13.4% and 23.6% on average over the Privatedecay and RACSdecay, respectively, while keeping the performance almost same as RACSno decay.It is achieved by writing evicted blocks to peer L2 caches in the way that the dead time intervals of cache blocks are kept similar to the RACSdecay scheme, thus reducing the leakage energy consumption.
Relationship: contrasting
Domain: Hardware
Sentence 1: In spite of these challenges, many previous papers have claimed that QCA-based systems could still best CMOS in terms of both power and performance.
Sentence 2: much of this work (a) did not consider the overhead of clocking which is required to drive any computation, (b) looked at electrostatic implementations which inherently limit applica­tion spaces (due to low operating temperatures [1]), or (c) looked at a molecular implementation [24] for which there is no proven device that can be deterministically placed and where functional correctness will be subject to small placement variations, stray charges, etc.
Relationship: contrasting
Domain: Hardware
Sentence 1: A Novel Technique to Improve Noise Immunity of CMOS Dynamic Logic Circuits Li Ding University of Michigan, Ann Arbor  lding@eecs.umich.edu ABSTRACT Dynamic CMOS logic circuits are widely employed in high per­formance VLSI chips in pursuing very high system performance.
Sentence 2: dynamic circuits are inherently less resistant to noises than static CMOS gates.
Relationship: contrasting
Domain: Hardware
Sentence 1: Under the additional assump­tion that all blockages are disjoint rectangles, they re.ne their construction further, obtaining approximation guaran­tees of 5 a and 2s a for s = 4 with graph size O(l) and 4 2s-1 O(ls-2), respectively, where a is the performance guarantee of a Steiner tree algorithm in graphs.
Sentence 2: their results are predominantly of theoretical interest, since even their 2-approximation algorithm would be very slow in practice due to the quadratic size of the Hanan grid.
Relationship: contrasting
Domain: Hardware
Sentence 1: RELATED WORK HW-SW partitioning is an extensively studied problem with a plethora of approaches, including many KLFM-based approaches (Kernighan-Lin/Fiduccia-Matheyes, [15], [14]) such as [8], [11].
Sentence 2: existing work often does not consider the special chal­lenges posed by dynamic recon.guration partial RTR imposes more physical constraints that need to be incorporated explicitly.
Relationship: contrasting
Domain: Hardware
Sentence 1: In Figure 10 (a), the region out­lined by blue lines can insert two ground .lls.
Sentence 2: if the ground .lls are placed as Figure 10 (b), no .oating .lls can be inserted in F1.if the two ground .lls are placed as Figure 10 (c), d f 1 can be inserted.
Relationship: contrasting
Domain: Hardware
Sentence 1: CACTI[34,40]isatoolthat hasbecomewidely used in the computer architecture community by architects ei­ther directly for modeling of SRAM based caches and plain memories, or indirectly through other tools such as Wattch[7].CACTI5.0[35]was amajorrevisionofCACTI overcomingseveral limitationsofearlierversions.First,the technology models of earlier versions were largely based on linear scaling of a0.8µmprocess.
Sentence 2: as scaling has progressed to nanometer dimensions, scaling has be­comemuch lesslinear.Tobettermodelthis,thebasetech­nology modelinginCACTI 5.0was changedfromsimple linear scaling of the original CACTI 0.8µm technology to models based on the ITRS roadmap.
Relationship: contrasting
Domain: Hardware
Sentence 1: In fact, any many-core chip design that stresses off-chip bandwidth (e.g., Tilera TILE100) would yield similar results.
Sentence 2: processor designs with a handful of large cores (e.g., Intel Westmere) would see less benefit from die-stacked caches as they cannot utilize the available mem­ory bandwidth due to their low degree of on-chip parallelism [6].
Relationship: contrasting
Domain: Hardware
Sentence 1: On the contrary, in the scan approach, the controllability and the observability of the circuit are improved by modifying the common flip flop: the so­called scan cells allow writing and reading the content of the memory element during the test apply, and are connected to compose a scan chain.
Sentence 2: as a serial process is required to load and upload the scan chain, that approach requires onerous application time and heavy ATE requirements in terms of storage needed for test data and test application program.
Relationship: contrasting
Domain: Hardware
Sentence 1: The limitation of us­ing the trace enable signal is that, for system-level veri.cation involving multiple processor cores asynchronously, the realis­tic behavior of the normal function may not match with the behavior under the trace, because the Debug/Trace Interface may introduce additional cycle overhead.
Sentence 2: such issue should be solved using a higher level debug/trace technique which deals with the asynchronous interaction among differ­ent cores.
Relationship: contrasting
Domain: Hardware
Sentence 1: 2.2 The Aegis Error Recovery Scheme Aegis s partition scheme can separate any two faults in the same group into two di.erent groups using a re-partition, or switching to a di.erent partition con.guration.
Sentence 2: it does not ensure that two faults that were originally in dif­ferent groups are not placed into the same group after the re-partition.
Relationship: contrasting
Domain: Hardware
Sentence 1: However, this is incorrect since Steinke s algorithm tries to reduce energy consumption by increasing the number of ac­cesses to the energy ef.cient scratchpad.
Sentence 2: cASA  adpcm (1 kByte ) 64 128 256 3398.37 1694.71 224.55 3261.04 2052.12 856.83 3779.80 2702.20 1480.59 -4.2 17.4 73.8 10.1 37.3 84.8 29.0 44.1 g721 (4.7 kBytes) 128 256 512 1024 7493.75 6640.65 4941.53 2106.53 8011.68 6510.00 4951.91 3033.11 8343.61 6734.41 5616.16 4707.76 4.0 -2.0 0.2 30.6 10.2 1.4 12.0 55.2 8.2 19.7  mpeg (19.5 kBytes) 128 256 512 1024 7554.88 7521.28 3904.27 3400.70 10364.46 9744.85 9502.60 3518.72 10918.01 8624.61 5189.06 5261.94 27.1 22.8 58.9 3.4 30.8 12.8 24.8 35.4 28.0 26.0 Table 1.
Relationship: contrasting
Domain: Hardware
Sentence 1: activation) mechanism should be non-trivial, and a HTH should not be activated accidentally when not desired by the adversary, much current research e.ort is also being spent on the study of triggering mechanisms by means of HTH in an IC.
Sentence 2: all of these works deal with the classical attack model of HTHs, which relies on the untrust­worthiness of the current semiconductor business practices.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is because our generator uses the full 24×17 multiplier size, and because we choose our operand decomposition specifically to minimize the DSP block count.
Sentence 2: 1200 1000 800 Asym Sym CoreGen Naïve OperandBitwidthWfor 64 x W Multiplier  Asym Sym CoreGen Naïve 50 40 DSP48Es Combinational Delay (ns) LUTs DSP48Es Combinational Delay (ns) LUTs 600 30 400 20 200 10 0 0 17 24 32 48 64 96128 17 24 32 48 64 96128  Operand BitwidthWfor Wx W Multplier 30 Figure 15: 64 × W multiplier LUT usage Asym Sym CoreGen Naïve Figure 11: W × W multiplier DSP48E usage Asym Sym CoreGen Naïve 25 20 15 10 5 1500 1000 0 0 17 24 32 48 64 96128 17 24 32 48 64 96128 OperandBitwidthW for 64 x W Multiplier OperandBitwidthWforWx WMultiplier Figure 16: 64 × W multiplier combinational delay CoreGen breaks down the multiplier using 28 16 12 8 4 0 Figure 12: W × W multiplier LUT usage Asym Sym CoreGen Naïve 17 24 32 48 64 96128 OperandBitwidthWfor Wx W Multiplier symmetric 17×17 multiplications for most of the partial products.
Relationship: contrasting
Domain: Hardware
Sentence 1: This circuit, opportunely con.gured, can test a portion of the FPGA, therefore, by re-con.guring it multiple times, the entire FPGA is cyclically analyzed.
Sentence 2: o.-line testing can not be applied in all those scenarios which are highly fault-sensitive and characterized by hard real-time constrains, such as in space and avionic applications.
Relationship: contrasting
Domain: Hardware
Sentence 1: In addition, the global arbiter designed using Verilog and then synthesized using Synopsys Design Compiler and mapped onto the PDK 45nm technology library to calculate its area (0.0114mm2), added to it the TxRx estimated area (0.0438mm2).
Sentence 2: the value of RF-I s transmission line with a pitch of 12µm considered to be routed through the chip (NoC size 6×4) as (U) shape passing through all nodes to calculate its area [8].
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, a mission critical system with a single FPGA must meet guaranteed speci.cations, so in­creasing the average throughput over many varying devices is not much use the slowest must still meet the speci­.cations.
Sentence 2: a data centre with many FPGAs that share a workload could make power savings and performance gains since it is the average e.ciency and throughput of the devices that will determine the performance of the whole cluster.
Relationship: contrasting
Domain: Hardware
Sentence 1: DESIGN OF DUAL-RESIDUE MULTI-STEP A/D CONVERTER  A. Time-Interleaved Sample-and-Hold The sampling rate of a system is further increased by a using time-interleaved technique [16], where a higher sampling rate is obtained by running the system in parallel, although at different clock phases.
Sentence 2: in the front-end S/H, where the clock is used to sample a continuous time signal, any deviation of the sampling moment from its ideal value results in an error voltage in the sampled signal equal to the signal change between these two moments.
Relationship: contrasting
Domain: Hardware
Sentence 1: The adaptive fragmentation scheme proposed in [2] and the dynamic rate adaptation algorithm proposed in [3] control the fragment size and modulation level, respectively, in order to improve the overall throughput.
Sentence 2: the criteria adopted by these algorithms for enhancing the throughput are not suitable for WPAN applications because, in this case, reducing the energy consumption is more important than maximizing the throughput.
Relationship: contrasting
Domain: Hardware
Sentence 1: When the 4x density and zero cell leakage advantages of STT-RAM over SRAM are con­sidered, one can expect STT-RAM caches to consistently achieve very good results.
Sentence 2: looking at Figure 3 which compares the L2 cache miss rate of an HP cache with that of STT-Area and TFET caches, one can see that only 4 out of 10 benchmarks (calculix, dealII, gamess,and omnetpp) have a signi.cant reduction in their miss rates.
Relationship: contrasting
Domain: Hardware
Sentence 1: Graph automorphism-based datapath extraction and ILP-based bitstacking selection are proposed to amend the existing HPWL-driven place­ment [23].
Sentence 2: datapath consideration in logic synthesis phase alone is not suf.cient [16], and restricting timing optimization (e.g., sizing/buffering) on datapath can degrade the overall quality of HW [5], [25].
Relationship: contrasting
Domain: Hardware
Sentence 1: Inductive supply noise in the form of 1st and 2nd droop occuring at relatively lower frequencies has tradition­ally been dominant in digital integrated circuits.
Sentence 2: recent integration trends, including three-dimensional integration through chip-stacking [6] and the deployment of multiple voltage domains using integrated low drop out regulators (LDOs) [11], have resulted in increased amplitude and frequency content of supply noise.
Relationship: contrasting
Domain: Hardware
Sentence 1: where (.. 0 ) (2) 2(G .u(x,t))2 (G .u(x,t))2 2 Equation (1) shows that FE(x,t) is a function of u(x,t).
Sentence 2: u(x,t) itself is a function of FE(x,t) as described by (2).
Relationship: contrasting
Domain: Hardware
Sentence 1: The case-splitting strategy can be reused, due to the facts that (i) the motivation for each individual case-split is architecture­based rather than implementation-speci.c, and (ii) the de.nition of the case-splits is done in terms of the reused reference FPU in­stead of the real FPU.
Sentence 2: more overlap cases can now lead to cancellation in the event of denormal operands.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, a 512MB Footprint Cache requires around 3MB of tags, which, while not trivially small, is still feasible to be implemented on-chip.
Sentence 2: the improvements in die-stacked DRAM technology have already pushed the feasible DRAM capacities up to several GBs (e.g., Micron s 4GB Hybrid Memory Cube [22]).
Relationship: contrasting
Domain: Hardware
Sentence 1: However, as will be shown in Sections II-B and III, the length a crack can grow from an originating TSV depends heavily on the locations of the nearby TSVs due to the superposition of thermo-mechanical stress, and its value can be large or even dif.cult to calculate when complicated TSV placement structures present.
Sentence 2: as the probability of crack initiation is low, it would be a waste of chip area to set the KOZ to (a) (b) Fig.
Relationship: contrasting
Domain: Hardware
Sentence 1: A LEAP computation engine is an array of specialized hardware Table 4: Latency Comparison (ns) Application SWSL PLUG LEAP Ethernet forwarding 0.582 0.504 0.392 IPv4 1.753 0.504 0.392 IPv6 5.473 2.331 1.813 Ethane 1.200 0.504 0.392 DFA 0.373 0.756 0.588 Table 5: Power Estimation (W) units connected via a crossbar, resulting in near-ASIC performance.
Sentence 2: such performance comes at a price in terms of ease of development and generality.
Relationship: contrasting
Domain: Hardware
Sentence 1: Thepaper[4]proposesanewkindoffoorplancalledmo­saicfoorplan.Amosaicfoorplanissimilartoageneral non-slicingfoorplanexceptthatitdoesnothaveanyun­occupiedroom(Figure1(a))andthereisnocrossingcutin thefoorplan(Figure1(b)).ArepresentationcalledCorner BlockList(CBL)isproposedtorepresentmosaicfoorplan.
Sentence 2: thisrepresentationhasarelativelysmallsolutionspaceof O(n!23n)1andthetimecomplexitytorealizeafoorplan 1In[4],thepaperclaimswithoutproofthatthesizeofsolu­tionspaceforCornerBlockListisO(n!23n/n1:5).webelievethatthecorrectsizeofCBLsolutionspaceshould be (n!23n).IntheCBLalgorithm,thecornerblocklist (S,L,T)areperturbedrandomlyandindependentlyinthe simulatedannealingprocess.Therearen!combinationsfor A C D B A C B D (a) (b) Figure1:Structuresthatcannotberepresentedin amosaicfoorplan fromitsrepresentationislinear.somecornerblock listdoesnotcorrespondtoanyfoorplan.Asaremedyto theweaknessthatsomenon-slicingstructurescannotberep­resented(e.g.,Figure1(a)),CBLisextendedbyincluding dummyblocksofzeroareainthesetofmodules.Inorder torepresentallnon-slicingstructure,O(n 2)ofsuchdummy blocksareused,whichhaveincreasedthesizeofthesolution spacesignifcantly[9].
Relationship: contrasting
Domain: Hardware
Sentence 1: Firstly, as M increases, there is more chance of generating a bigger antichain and secondly, the algorithm is likely to diverge further from the optimal chain decomposition with more events.
Sentence 2: the increase is gradual and even with 25, 000 events, we are able Events to timestamp events using 35 components which is a reduction of a factor of about 3 over vector clocks.
Relationship: contrasting
Domain: Hardware
Sentence 1: The other way for a thread to achieve speedup using MTP, without a large Sp, is to have a modest Sp, but a steep speedup curve and a gradual slowdown curve, so that the speedups accumulated in multiple expanding partitions exceed the slowdown in one shrinking partition.
Sentence 2: achieving a modest Sp along with a steep speedup curve requires only a small amount of extra capacity, in which case CC is likely to achieve the same effect be­cause the LRU policy is better at .ne-turning cache allocation to achieve speedups (example shown in Figure 7).
Relationship: contrasting
Domain: Hardware
Sentence 1: i i ; i i i ; 60 .... ~ .... i ..... i .... ;,-----',, .... i .... i--- I I I t I I I ; ; i ; i ; /( 40 ----: .... .... -';----5~i-i--i---- i ;- I;-- .... "~ .... i..... ; .... ~-- -- 0 --20 --~-----~--';---'14;ii ql.... +'-; --ii .... ii .... i----i .... .... -40 .... i .... ; .... i .... i... i.. .i .... i .... 5 10 15 20 25 30 35 40 Number of Users Figure 3: Comparison of power usage interference which further reduce the power level required to transmit the packets that have close deadlines.
Sentence 2: note that, when the number of MHs is small (less than 20), the adaptive scheme requires more power than the fixed scheme.
Relationship: contrasting
Domain: Hardware
Sentence 1: The results show that the ef.ciency of U5 decreases by around 25% (from 167% lifetime improvement to 127%) when different primary input SPs are used for the mapping phase and the delay degradation calculation.
Sentence 2: this has negligible effect on the ef.ciency of the methods with the fewer SP samples (less than 1% decrease in the lifetime improvement of NU2W).
Relationship: contrasting
Domain: Hardware
Sentence 1: Constructing Current-Based Gate Models Based on Existing Timing Library Andrew B. Kahng, Bao Liu and Xu Xu CSE and ECE Departments, UC San Diego, La Jolla, CA 92093-0114 {abk,bliu,xxu}@cs.ucsd.edu Abstract Current-based gate modeling achieves a new level of ac­curacy in nanoscale design timing and signal integrity analy­sis.
Sentence 2: to generate current-based gate models requires additional pre-characterization of the gate, e.g., in the form of a new or an extended timing library format.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this case, it is worth noting for example, that the hardened ver­sion provided applying SWIFT-R only to the register set A - D - E - F would be an interesting choice from the soft­ware side, because it o.ers high reliability (98.18% are un­ACE faults in FTUnshades) and at the same time, its code and execution time overheads results are acceptable, ×1.79 and ×1.70 respectively.
Sentence 2: these decisions must be strictly connected with the requirements of every speci.c application.
Relationship: contrasting
Domain: Hardware
Sentence 1: By multi-mode we mean that part of the cache can be used for FIFO-based caching of data for media processors, while the remainder of the cache can be used for 2nd level caching or even 1st level caching for CPUs, with standard caching and pre-fetching mecha­nisms.
Sentence 2: the latter mode of caching lies beyond the scope of this paper.
Relationship: contrasting
Domain: Hardware
Sentence 1: We de.ne an incremental elaboration function to be one that elaborates the resources of design d incrementally: gd(Xc,Xn,Hc)= Hn (4) The incremental sets can be expressed as: R = fd(Xc)-fd(Xn) and S = fd(Xn)-fd(Xc) (5) Hn can now be produced by removing R from Hc and adding S: Hn =(Hc - R) .
Sentence 2: s (6) we do not want to determine the sets R and S as described in equation 5 because this would require a com­plete evaluation of fd(Xn) and fd(Xc).
Relationship: contrasting
Domain: Hardware
Sentence 1: Infact, c4, vpr, and parser, have perfect outputs in the con­servative con.guration.
Sentence 2: mpeg2 and rayshade have a few runs with degraded results (about 33% for mpeg2 and 4% for rayshade), but as we show later in the section, the degra­dation is marginal.
Relationship: contrasting
Domain: Hardware
Sentence 1: Argus [7] and iSWAT [8] are based on the same guiding principle as the URISC checker core, i.e., fault detection using low-overhead hardware.
Sentence 2: argus and iSWAT can only be used for fault detection, while the URISC co-processor, by virtue of being Turing complete, can be used both to detect faults (this work) and to recover from faults when they occur (as shown by [10]).
Relationship: contrasting
Domain: Hardware
Sentence 1: This technique movespagesfrom main memory inthelocal com­puter to memory in other computers of the cluster, aiming that retrieving those remote pages will be faster than re­trieving them fromharddisk.Previousstudieshaveproved that,evenonaregularEthernetnetwork,aremote memory access madeacrossthenetworkisslightlyfasterthanalocal disk access [12].
Sentence 2: remote swap presents the same drawback as traditional swap, which is not only a.ected by disk latency, but it also su.ers from software latency, that is, the time required by the operating system to swap mem­ory pages.
Relationship: contrasting