sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Figure5showsmultiplierperformanevs.supplyvoltage forbothtehnologies.Therangeofpointsateahvalue ofVddtoombinationsof(Vdd.V orrespondsvariousVwell) andVfromtoStandard Vwellranging(0,0)(.4,.4).CMOS runsat136MHzatVdd=3.3V.LowthresholdCMOSruns at188MHzatVdd=2.0V,136MHzatVdd=1.3Vandat 40MHzatVdd=0.4V.
Sentence 2: inlowthresholdCMOS,thekeytoahieveminimumpower attherequiredperformaneistohoosetheoptimumra­ 40 20 0 0 0.511.522.53 3.5 V [V] dd Figure5:Multiplierfrequenyvs.supplyvoltage forstandardandlow-Vihimplementation 0.4 0.35 0.3  0.25 Optimum P/P leakagetotal 0.2 0.15 0.1 0.05 0 Frequency [MHz]Frequency [MHz] Figure6:Optimumsupplyandwellvoltagesvs.fre-Figure7:Optimumratioofleakagepowertototal quenyforlow-Vihimplementation powervs.frequenyforlow-Vihimplementation  tioofleakagepowertototalpower.Forexample,forthe multipliertorunat40MHz,oneanhoosetheasupply voltagerangingfrom0.37to0.6V.Althoughalowersupply voltagemayseemadvantageous,itrequiresverylowthresh-oldswhihinturnmakesleakagepowertoolarge.Figure6 showsthesupplyandwellvoltageswhihresultinminimum totalpoweratthegivenfrequeny.Valuesareguaranteed tobeoptimumonlyinthefrequenyrangebetween12and 171MHz.Namely,athighestfrequeniesitismoreeÆient torunathighersupplyandthresholdvoltages.sinewelimitedoursupplyvoltageto2V,theonlywayto ahievethehighestfrequeniesistorunatmaximumsupply voltageandlowestthresholds.
Relationship: contrasting
Domain: Hardware
Sentence 1: Moreover, the latch in Figure 2 is often shared with an existing scan latch/.ip-.op in the datapath, which further reduces the test cost.
Sentence 2: any two Figure 2: A Mux-based Scan C-Element multiplexer-based scan elements connected in series cannot capture the circuit response at the same time, hence they cannot be enabled at the same time and are, thus, connected to different scan enable signals.
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Domain: Hardware
Sentence 1: Self-Calibration Technique for Reduction of Hold Failures in Low-Power Nano-scaled SRAM Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, and, Kaushik Roy School of Electrical and Computer Engineering, Purdue University, IN, USA {ghosh3, sm, keejong, kaushik}@ecn.purdue.edu ABSTRACT Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays.
Sentence 2: due to process variation, a higher source voltage can significantly increase data flipping in standby mode (Hold Failures) resulting in faulty memories.
Relationship: contrasting
Domain: Hardware
Sentence 1: The 2nd level DTLB on the Itanium 2 processor contains 128 entries, covering only a megabyte of virtual space when using 8KB virtual pages.
Sentence 2: the processor supports up to a 4GB virtual page, and most operating systems support large virtual page allocation (1MB+) in both memory management APIs, static/global data allocation, and instruction page allocation.
Relationship: contrasting
Domain: Hardware
Sentence 1: By utilizing virtual channel .ow control (Fig­ure 14(b)), buffers are partitioned into multiple VCs, which allow packets to pass blocked packets.
Sentence 2: with the 100 use of high-radix routers and the .attened butter.y topology, the additional wire resources available can be used to over-80 come the blocking that can occur as shown in Figure 14(c).
Relationship: contrasting
Domain: Hardware
Sentence 1: Unfortunately, the simulation speeds of this detailed microarchitectural framework are slow; hence we cannot use it to run full Linux distributions with the memory allocation behavior necessary to study CoLT on suf.ciently long-running, large-data ap­plications.
Sentence 2: while this simulator does not maintain virtual­to-physical address translations, it does observe the performance ef­fects of TLB misses by tracking the allocated virtual pages.
Relationship: contrasting
Domain: Hardware
Sentence 1: The distribution of a sum of lognormals is not known to have a close form in general.
Sentence 2: one can compute its mean and variance by E(S)= u1 (4) var(S)= u2 - u12 (5) where u1 and u2 are the .rst and the second moments de.ned and computed as N X u1 = E(S)= E(Ik) (6) k=1 NN XX u2 = E(S2)= E(IkIl) k=1 l=1 NN XX = (Cov(Ik,Il)+ E(Ik)E(Il)) (7) k=1 l=1 Once the mean and variance (and correspondingly the two mo­ments) are obtained, Wilkinson s method [11, 12] can be adopted 1The detail of this is not the primary concern in this paper.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is because of using dual-rail than the similar one in the ASPIN design since it has ex­ data encoding in asynchronous router, the area of the bu.er, tra transistors to prevent Metastability.
Sentence 2: reported crossbar switch and speci.cally routing unit is about two throughput of Asynchronous to Synchronous interface in the times larger in asynchronous router than in synchronous proposed design is less than similar component of ASPIN ar­ router.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, the number of multi-node relations hARhh around an OR gate Ywith ninputs , 2, ..., ncan be as wnGlhARRw hlnXwnGlhw hRnn wnGlhw hlnXwnGn hwnGlhenRh large as 2... nY, where hn represents the number of single-node implications of the node .
Sentence 2: since the primary multi-node relation for the OR gate is suf.cient to deduce all such multi-node relations, they do not help in increasing the necessary assignments for any fault.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4(e), by using CWS the energy consump­tion was reduced by up to 23% of that by using the other congestion-aware algorithms on a NoC with a size varying from 4×4 to 8×8.
Sentence 2: when the size of NoC increases, the improvement of energy consumption using the the CWS was thus lowered.
Relationship: contrasting
Domain: Hardware
Sentence 1: The functionali­ties provided by the TPM allow to securely bind (sensitive) data to a speci.c platform meaning that the data is only accessible when the underlying platform has the valid and desired con.guration.
Sentence 2: there are several issues to deal with: .rst, actual TPM chips are currently mainly available for workstations and servers and rather for speci.c domain applications, in particular barely not for embedded systems.1 Second, TPM speci.cations are continuously growing in size and complex­ity, and there is still no published analysis on the minimal TPM functionalities that are practically needed.
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Domain: Hardware
Sentence 1: FRAMEWORK As explained in Section 2, to improve the small delay defect screening capability of a test pattern, the timing can be adjusted such that the path delay affected by a pattern is relatively close to the clock period (pattern slack near zero).
Sentence 2: the perfor­mance degradation due to IR-drop effect also needs to be consid­ered to avoid any good chips failing the test.
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Domain: Hardware
Sentence 1: Because there are no multipliers, any sort of LinearCongruentialGeneratororMultiplyRecursive Generator is impossible, and the 256 byte memory (which must also contain the instructions) makes a classic Lagged Fibonacci generator impossible.
Sentence 2: the SR does con­tain a basic set of binary linear operations, such as shifts, exclusive-or, and bit-wise and.
Relationship: contrasting
Domain: Hardware
Sentence 1: Therefore, at node j,waveform W4 and W5 will be removed because of the negative sign in the occurrence probability of W4.Only W1, W2 and W3 will be left which is exactly as algorithm I.
Sentence 2: the node k mask tags are false for waveforms W1..4 so that they will be removed, leaving only waveform W5.
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Domain: Hardware
Sentence 1: As a re-sult, reducing component temperature also tends to extend com-ponent, and therefore, system lifetime.
Sentence 2: temperature-aware task mapping fails to capture at least two importance classes of factors that also influence system life-time: core properties, such as power density, supply voltage, and circuit geometry; and, system architecture, such as the organiza-tion of the communication architecture and the distribution of slack.
Relationship: contrasting
Domain: Hardware
Sentence 1: Though the same virtual tags can be mapped to the different TLB entry, they will not be indexed to the same set in the cache since the VIVP cache is indexed by the index bits from the virtual addresses.
Sentence 2: when the size of the virtual tag bits is larger than that of VPN bits, different virtual tags can be mapped to the same TLB entry, which collapses the cache integrity, because of the remaining virtual tag bits.
Relationship: contrasting
Domain: Hardware
Sentence 1: As dis­cussed earlier, the timing error is detected by re-sampling the output at a speci.ed period later than the clock edge and comparing it with the original output in [5].
Sentence 2: if the data, which should be the result of the next clock cycle, comes too early through short paths and arrives at the shadow latch before the rising of the delayed clock, it will overwrite the previous data that should be stored in the shadow latch.
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Domain: Hardware
Sentence 1: Introduction The hand-crafted fully-custom application-speci.c inte­grated circuit (ASIC) design methodology usually deliver­ies chips with lower power consumption, 5 to 8 times higher speed [3] and more compacted chip layouts than conven­tional standard ASIC design method.
Sentence 2: automatic standard ASIC design .ow enables more ef.­cient design process.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this case also,M1 starts out in the linear-region, and enters the saturation region when the node voltage at a rises above V NMOS .
Sentence 2: in this dsat case, the PMOS transistor M2 of INV1 also turns on (in saturationmode) when the voltage of node a reaches VDD + |VTP| (here VTP is the threshold voltage of the PMOS transistor) because the VGSof M2 becomes smaller than VTP.
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Domain: Hardware
Sentence 1: 4 Related Work There exists a large body of work on techniques, which effectively use the structure of the circuit to perform branch-and-bound search.
Sentence 2: they suffer from two signi.cant drawbacks a) They cannot systematically avoid re-entering previously explored decision spaces, and b) They are signi.cantly slower on hard combinational problems than state-of-the-art SAT solvers implemented speci.cally for solving a problem in a single time-frame.
Relationship: contrasting
Domain: Hardware
Sentence 1: (8+dlog2ndictionarye) bits,wherendictionaryisthenumberofmemoryentriesof thedictionary.Similarly,thememoryrequirementsforthe indexarenindex.dlog2ndictionaryebits,wherenindexisthe numberofmemoryentriesoftheindexanddlog2ndictionarye isthenumberofbitsrequiredtoaddressthedictionary.
Sentence 2: lZWInsoftware-basedapplications,onlytheindexis consideredinthecalculationofthecompressionratio.Inad­dition,statisticalencodingschemesareutilizedforfurther compressingtheindex.Asaresult,intypicalLZWappli­cations,superiorcompressionratios(i.e.,10;20%)have beenachievedbyusingcommerciallyavailablesoftwarepro­grams(e.g.,compress.gzip).suchcommercial programsarenotapplicabletoourcompressionproblem.
Relationship: contrasting
Domain: Hardware
Sentence 1: Clearly, the MRF implementation of logic functions requires many transistors.
Sentence 2: as our simulations will demon­strate, the MRF implementation provides signi.cant advantages over standard, minimum-transistor CMOS designs with respect to noise immunity, fault tolerance (e.g., imperfect threshold voltage Figure 2: A circuit for encoding the clique function of two logic variables de.ning an inverter (total transistor count is 20, as compared to two for standard CMOS inverter) control), and low-voltage operation (e.g., VDD ~ VTH of the tran­sistors).
Relationship: contrasting
Domain: Hardware
Sentence 1: With a loosely coupled approach, mesochronous synchronizers would have required an over­sizing of switch input bu.ers for full throughput operation which would have o.set their inherently lower number of bu.er slots with respect to dual-clock FIFOs.
Sentence 2: such augmented input bu.ers do not dominate NoC area since other components (especially the output bu.ers, sized to 6 slots in this architecture) play a major role.
Relationship: contrasting
Domain: Hardware
Sentence 1: On average, be­cause most benchmarks only utilize a small portion of the off-chip bandwidth, both traditional dual-core con.guration and the Orthrus architecture closely match the performance of the baseline: 12.0% slowdown for the dual-core, 2.2% slowdown for Orthrus with sym­metric cores, and 2.7% slowdown for Orthrus with asymmetric cores.
Sentence 2: for a bandwidth-sensitive benchmark such as mcf,  Parameter Baseline Dual-Core Orthrus Symmetric Orthrus Asymmetric Frequency 3GHz Processing Cores 14-issue OoO 24-issue OoO 24-issue OoO 14-issue OoO &#38; 11-issue in-order Checks None Coarse-grained Fine-grained Fine-grained L1 caches (I$/D$) (32B Block) 4-way 64KB/64KB Core1: 4-way 64KB/64KB Core2: 4-way 64KB/64KB Core1: 4-way 64KB/64KB Core2: 4-way 64KB/64KB MAP: 2-way 32KB Core1: 4-way 64KB/64KB Core2: 2-way 32KB/32KB MAP: 2-way 32KB L1 latency 2cycles L2 cache (64B Block) 2-MB uni.ed, 8-way, 14 cycle latency DRAM Latency: 50 ns, Bandwidth: 8GB/s Table 2.
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Domain: Hardware
Sentence 1: × nsurf × p(r - r )(BPI × TPI) oi In reality, even this Cmax is not completely usable be­cause: (i) Outer tracks can hold more sectors due to their longer perimeters.
Sentence 2: allocating storage on a per­track basis would require complex channel electronics to accommodate different data rates for each track [3].
Relationship: contrasting
Domain: Hardware
Sentence 1: The introduction of the Wide I/O DRAM standard now provides a platform for integrated processor and 3D-stacked memory design-space exploration to derive future high-performance and extremely energy-ef.cient embedded SoCs and server systems, helping meet both the green [6] and exascale computing goals [7].
Sentence 2: the key missing link required to facilitate the exploration of these opportunities is an accurate system-level power model targeting Wide I/O 3D-DRAMs that is: (a) easily integrable with system­level SoC design .ows and (b) enables design-time 3D-DRAM energy estimation in future DRAM-stacked SoC architectures.
Relationship: contrasting
Domain: Hardware
Sentence 1: Adiabatic design is based on a slow charge and discharge of a capacitive load using a time-varying clocked power supply, usually realized by resonant LC-based oscillators.
Sentence 2: state-of-the-art models for energy estimation in adiabatic gates [2] are not as accurate and generic as the model proposed in this paper, as described in detail in Sec.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is be­cause all the iterations in this set access the same set of disks, and the remaining disks can be placed into a low-power mode during these accesses to save power.
Sentence 2: it is also important to de­termine a good execution order for different Ip,T s. In Sections 5.1 and 5.2, we present scheduling schemes, where the problem is con­sidered from single processor s perspective and multi-processors perspective, respectively.
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Domain: Hardware
Sentence 1: A pro­cessing order Pf is feasible if, for each circuit block b in Pf ,all sub-circuit blocks of b have been processed before b in Pf .For example, the POT order in Figure 3, , is a feasible processing order, in which {F} is processed before C, {F, C, D} are processed before A, and so on.
Sentence 2: since a sub-circuit block can be referenced repeat­edly, it is not necessary to detect its ESD paths whenever it is Figure 3: An example hierarchical-circuit topology tree.
Relationship: contrasting
Domain: Hardware
Sentence 1: As an example, in 0.13µm CMOS technology, supply voltage can not be greater than 1.3 volts and conventional cascode configurations could be unacceptable.
Sentence 2: for 0.18µm CMOS technology, since supply voltage is not that small, cascode configurations are quite practical and for our simulation purposes in this paper, we have used conventional cascode circuits satisfactorily.
Relationship: contrasting
Domain: Hardware
Sentence 1: Recently, [13] and [18] discuss a complete .lter synthesis of TCS and RNS implementations of both programmable and constant-coef.cient FIR .lters.
Sentence 2: in either work, the multiplication by constant was implemented with a lookup table and neither exploits other properties of the RNS but the simple coef.cient decomposition inherent to RNS representations.
Relationship: contrasting
Domain: Hardware
Sentence 1: ensure that the system operates at the right frequency, the delay of such a global wire is distributed over several clock cycles by in­serting memory elements such as edge-triggered .ip-.ops [2, 3].
Sentence 2: it has been noted that this approach, which is referred to as wire-pipelining henceforth, can alter the functionality of a cir­cuit [4] by arbitrarily changing the latency differentials along the paths in the circuit.
Relationship: contrasting
Domain: Hardware
Sentence 1: The instability caused by randomness gives us opportunities to .nd better Given a set of cells (circuit elements) and the nets that solutions through the multiple runs.
Sentence 2: as pointed connect these cells, the circuit partitioning problem is to out very recently [1, 2], a lack of stability ironically yields partition these cells into several disjoint blocks (subcircuits) a critical weakness in ECO situations for large scale designs of speci.ed sizes such that the number of interconnections including the reiteration of placement procedures for timing between blocks is minimized.
Relationship: contrasting
Domain: Hardware
Sentence 1: However, even though such self-assembly based fabrics may be feasible in the next decade, they are not ready for large-scale fabrica­tion today.
Sentence 2: in this paper, a hybrid CMOS/NAnoTUbe REcon.gurable architecture, called NATURE, is presented, which can be fabricated with CMOS-compatible manufac­turing processes and leverage the bene.cial aspects of both technologies immediately.
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Domain: Hardware
Sentence 1: Application of Hybrid NEMS-CMOS in Dynamic Circuits Due to near zero leakage characteristics of NEMFETs, these devicesare ideal for low-power applications.
Sentence 2: since NEMFET devices have relatively low ON current characteristics compared to their CMOScounterparts, it is more desirable to build hybrid NEMS-CMOS circuits to combine good characteristics of each type of devices.
Relationship: contrasting
Domain: Hardware
Sentence 1: The checksum provided by the CRC computation will be the value of the state variable x(n).
Sentence 2: the mathematical formulation of a scrambler is: x(n1)=Ax(n); y(n)=Cx(n)du(n); where Cis a kxkmatrix which selects the state bits com­bined to the data stream (usually only one bit in the diagonal is used) and dis a single-1 vector in the form [100J, used to select the state bit to be correlated to the input stream.
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Domain: Hardware
Sentence 1: So the bamboo structure increases reliability, and in order to exploit this, wire widths are deliberately kept so narrow that a bamboo structure is maintained; also, the wire material can be J (T) / J(T = 25°C) max max selectively annealed during IC processing in order to support Temperature T [Celsius] bamboo formation.
Sentence 2: -40 0 25 60 80 100 125 150 175 the maximum wire width possible for a bamboo   structure is usually too narrow for signal lines of large-magnitude 0,1 currents in analog circuits or for power supply lines.
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Domain: Hardware
Sentence 1: Modelling and Analysis of the Split Phase Multi-Channel MAC Approach Abdelaziz El Fatni University of Toulouse, INSA 135 Avenue de Rangueil 31400 Toulouse, France abdelaziz.elfatni@insa-toulouse.fr ABSTRACT The throughput of wireless networks can be improved signif­icantly by using multiple channels communications in MAC protocols.
Sentence 2: due to the multi-channel environment, a novel issue must be addressed in MAC protocols which is called the channel assignment.
Relationship: contrasting
Domain: Hardware
Sentence 1: Conventional systems execute the cross-correlation algorithm on the re­ceiver, whose implementation has a running time of O(n 2) in the time domain (TD-CC) and O(n log n) in the frequency domain (FD-CC).
Sentence 2: due to no hardware divide or .oating point support on WSN nodes, additional signal pro­cessing platforms have to be added.
Relationship: contrasting
Domain: Hardware
Sentence 1: Moreover, if the node can prove that it will not be able to provide the line, it will skip the snoop operation, forwarding the request directly to the next node in the ring.
Sentence 2: any protocol using a ring as an interconnection network (either logical or physical) needs to send its snoop requests through it, forcing all requests to visit every node, which obviously means the loss of any possibility of parallelism with the snoop requests, thus increasing transaction latency.
Relationship: contrasting
Domain: Hardware
Sentence 1: An important advantage of on-chip multiprocessing from the software perspective is that such an architecture is very well suited for high-level parallelism; that is, the parallelism that can be exploited at the source level (loop level) using an optimizing com­piler.
Sentence 2: the parallelism that can be exploited by single processor superscalar and VLIW machines are low level (instruction level).
Relationship: contrasting
Domain: Hardware
Sentence 1: The discrete probability density function for Pij is time obtained during simulation with the execution times in c. If no job of the process under investigation .nished during the time TG, then the simulation is run for another hyperperiod TG with the same execution times in c. The size of the initial population is chosen to be n(TG) .
Sentence 2: g we have introduced a lower bound of 50 mem­bers and an upper bound of 3000 members.
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Domain: Hardware
Sentence 1: This separation made it possible that this comparator can operate at a lower supply voltage (VDD) and have a more stable offset voltage over wide common-mode voltage (Vcom) ranges.
Sentence 2: since it requires both clk and clkb for its operation, high accuracy timing of clkb is required because the output-latch has to detect the voltage difference at Di nodes at very limited time.
Relationship: contrasting
Domain: Hardware
Sentence 1: A weight, w1, for maximum amplitude and, w2, for foot strike time will assign up to w1/(w1+w2) of the assigned epochs to samples for the maximum amplitude metric and up to w2/(w1+w2) of the assigned epochs to samples for foot strike.
Sentence 2: fewer epochs may be assigned to a metric, if only those many valuable samples may be obtained.
Relationship: contrasting
Domain: Hardware
Sentence 1: Tosumup,byusinga2x2-JoinwithtwoCBs,wean onstrutanydual-raillogifuntionf(bothfandf) oftwointermediatefuntions.Therefore,fromtheon­ventionallogipointofview,weanonsiderthis2-input sub-iruitasa2-inputLUT(look-uptable).
Sentence 2: thereisanotherusageofa2x2-Join,i.e,weonsider makingmultiplefuntionsfromasingle2x2-Join.For example,weanmakeANDandXORfuntionsoftwo inputsbyusingasingle2x2-Join,threeCBsandthree SPLsasshowninFig.5.Indeed,weanmakeallthe possiblesixteen2-inputfuntionsatthesametimeby asingle2x2-JoinswithmanyCBsandSPLs.sineweusedual-raillogi,wedonotneedtoonsiderthe polarityoftheinputsandtheoutputsofthefuntions, andtherefore,itisenoughtoonsiderthefollowingfve funtionswithrespettoinputsh1andh2:f1=h1·h2, f2=h1·h2,fs=h1·h2,f4=h1·h2andf5=h1Eh2.
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Domain: Hardware
Sentence 1: INTRODUCTION The Semiconductor Industries Association (SIA) roadmap [1] predicts that complementary metal-oxide semiconductor (CMOS) chips will continue to fuel the need for high-performance systems for another 10 15 years.
Sentence 2: advancements in the material sci­ence and device community have enabled the creation of nanoscale devices (RTDs, QCA, to name a few) that have novel structures and properties.
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