sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Exploiting Locality to Ameliorate Packet Queue Contention and Serialization Sailesh Kumar John Maschmeyer Patrick Crowley Washington University Washington University Washington University Computer Science and Engineering Computer Science and Engineering Computer Science and Engineering St. Louis, MO 63130-4899 St. Louis, MO 63130-4899 St. Louis, MO 63130-4899 +1-314-935-4306 +1-314-935-7551 +1-314-935-9186 sailesh@arl.wustl.edu Jrm5@cec.wustl.edu pcrowley@wustl.edu ABSTRACT Packet processing systems maintain high throughput despite rela­tively high memory latencies by exploiting the coarse-grained parallelism available between packets.
Sentence 2: multiple processors are used to overlap the processing of multiple packets.
Relationship: entailment
Domain: Hardware
Sentence 1: As can be seen in Figure 5(a), caching shared data (cache data) has a different impact depending on the bench­mark.
Sentence 2: radix and Matrix feature signi.cant  x 108 no_cache no_cache.SB cache_data cache_data.SB cache_all    77 x 10x 1015 15 Execution Time [ns]  2 10 5 0 10 5 0 0 4 816 4 816 4 816 #PE #PE #PE (a) FFT (b) LU-1 (c) LU-2 8 76 x 10x 10x 103 15 2  Execution Time [ns]  1.52 1 10 5 0 1 0.5 00 4 816 4 816 4 816  #PE #PE #PE (d) Radix (e) Matrix (f) Norm Figure 6.
Relationship: entailment
Domain: Hardware
Sentence 1: Performance summary on Quick Sort N Prop D EMM Explicit Sec MB Sec MB 3 P1 27 64 55 >3hr NA 3 P2 27 30 44 >3hr NA 4 P1 42 601 105 >3hr NA 4 P2 42 453 124 >3hr NA 5 P1 59 6376 423 >3hr NA 5 P2 59 4916 411 >3ht NA Note that property P1 depends on both the array and the stack, while property P2 depends on only the stack for correctness.
Sentence 2: for P2, the contents of the array should not matter at all.
Relationship: entailment
Domain: Hardware
Sentence 1: (7) h The derivative of a function f(t) in its BPF representation (f(t)=f(T m)f(m)(t)) can now be computed by d d f(t)= [fT f(m)(t)] =fT D(m)f(m)(t).
Sentence 2: (8) (m) (m) dt dt d f(t)is also a linear combination of BPFs dt with the coef.cient vector being D(T m)f(m).
Relationship: entailment
Domain: Hardware
Sentence 1: Applying the above algorithm, we have Bins = {"A" }, Bin2 = {"B',"C"} and Bin1 = {"D","E',"F" }.
Sentence 2: "A" is broadcast on channel 3 (the fastest chan-nel), {"B","C" } on channel 2 ("B" is before "C" in each cycle), and {"D","E',"F"} on channel 1 - the lowest ("D" is transmitted before "E" which is before "F').
Relationship: entailment
Domain: Hardware
Sentence 1: m m-1 But since g(a)= a+gm-1a+...+g0a0 = 0, it follows that aM = gm-1aM-1 + ...+ g0aM-m.Hence, ( ) M-1 M-m+2 M-m+1 y = xm-2a+ ...+ x1a+ x0a ( ) M-1 M-m+1 M-m + gm-1a+ ...+ g1a+ g0axm-1.
Sentence 2: yi = xi-1 + xm-1gi for i =1,...,m -1and y0 = xm-1g0.
Relationship: entailment
Domain: Hardware
Sentence 1: +1,j + 1) then must follow, completing the induction.
Sentence 2: this shows that t .,i1 = t0 +2(W - 2)d+ and hence, by using (1), t .,i1 - t .,i = (i ' - i)d- +2(W - 2)e. Overall, since i and i ' >i were arbitrary, from the two cases and symmetry for i ' <i, we conclude that .
Relationship: entailment
Domain: Hardware
Sentence 1: Hence, in practice, any delay vector D of length n + 1 will be considered to contain m bins (where m is some constant and divides n + 1), where (n +1)/m succes­sive elements are equal.
Sentence 2: if o =(n +1)/m, di = dj if Li/oJ= Lj/oJ.
Relationship: entailment
Domain: Hardware
Sentence 1: Figure 9 shows that our proposed scheme can seamlessly work around both the one huge ob­stacle and the small obstacles; the system continues to gen­erate periodic waves sweeping the area outside the holes in coverage created by the obstacles.
Sentence 2: the wake sensors sweep the obstacle along its boundary and form aclosed wave pattern as soon as they pass the obstacle, so that the intruders nearby any obstacle can be detected.
Relationship: entailment
Domain: Hardware
Sentence 1: SAT-based BMC with EMM and PBA  The dependency of the property on any memory module for a given depth i is determined easily by checking whether a latch corresponding to the control logic for that memory module (the logic driving the memory interface signals) is in the set LRi.If no such latch exists in the set LRi, we do not add the EMM modeling constraints for that memory module.
Sentence 2: we abstract out that memory module completely.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.1 Route Planning for Wash Droplets with­out Capacity Constraints If the assay preceding the washing operation leaves a small amount of contamination, we may assume that only one wash droplet is su.cient to absorb the residue left by the assay.
Sentence 2: we assume that the wash droplet does not become saturated while removing residues, and hence, capacity constraints need not be considered.
Relationship: entailment
Domain: Hardware
Sentence 1: For ex­ample, if March C-is transformed into a transparent word­oriented March C-for testing an Nx32-bit memory, then test complexity (TCP+TCM) of Scheme 1 [12], Scheme 2 [13], and the proposed scheme is 90N, 260N, and 50N, respectively.
Sentence 2: time complexity of the transparent word-oriented test transformed by the proposed scheme is only about 56% or 19% time complexity of the transpar­ent word-oriented test converted by Scheme 1 or Scheme 2, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: Among these memory technolo­gies, ReRAM has been demonstrated with excellent scala­bility beyond the 10nm technology node [17] and with the capability of high density due to multi-level cells (MLC) and cross-point array structures.
Sentence 2: since the MLC ReRAM memory structure has reliability advantages over the cross-point ReRAM structure (see Section 2.A), it has recently been studied extensively.
Relationship: entailment
Domain: Hardware
Sentence 1: n  (C1,..., Cn,w)= C where C = (C, X),C = Ci, i=1 E Pr[X = c|c .
Sentence 2: c]= Pr[Xi = c] × w(Ci) .i,c.Ci the set of GBTs in C is the union of all the GBTs in C1,...,Cn.
Relationship: entailment
Domain: Hardware
Sentence 1: We formulate the problem as an optimal stopping time problem for the attacker.
Sentence 2: we formulate the problem as a Best-Choice Problem (also known as the Sec­retary Problem ), in which the adversary is presented with a time series of system states (obtained by sensors) and has Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage, and that copies bear this notice and the full ci­tation on the .rst page.
Relationship: entailment
Domain: Hardware
Sentence 1: We compare the results of our pin assignment algorithms amongst each other with a special emphasis on the results of the pin assignment algorithm of Section 4.4.This is reasonable because the algorithm of Section 4.4 finds the optimal pin assignment with respect to a linear objective.
Sentence 2: when optimizing SHPWL and AVG Flylines, the generated pin assignment is the global optimum with respect to either SHPWL or AVG Flylines.
Relationship: entailment
Domain: Hardware
Sentence 1: From experimentation, with the TREC-9 collection and creating five document clusters, it has been found that the coverage of all terms, minus the stop words, for each cluster by using the terms from the centroid document are 93%, 96%, 98%, 94% and 93%.
Sentence 2: the terms from the centroid documents cover at least 93% of all the terms within their respective clusters.
Relationship: entailment
Domain: Hardware
Sentence 1: In standard mirroring, each disk is mirrored to k- 1 other disks, so if one disk fails, only k-1 disks can carry the load of the failed disk.
Sentence 2: each of these k- 1 disks should carry 1/(k- 1) workload of the failed disk, so the reconstruction workload is bounded by 1/(k- 1).
Relationship: entailment
Domain: Hardware
Sentence 1: By forcing FlatFractal to take the same actions as TreeFractal, we ensure that Flat­Fractal s sub-systems inherit observational equivalence from TreeFractal s sub-systems.
Sentence 2: though the state with the sharer list contains complete global information, Flat­Fractal cannot use the global information (as a conventional directory might) to deviate in its actions from TreeFractal s logical hierarchy s actions.
Relationship: entailment
Domain: Hardware
Sentence 1: PROPOSED ARCHITECTURE In order to propose a power-ef.cient FPGA architecture based on NVM technologies, designers encounter several im­portant design decisions.
Sentence 2: the power ef.ciency of NVM technology used as the con.guration bits, the power consumption of the NVM PCs, and the integration of the NVM PCs with the FPGA resources are of decisive design importance.
Relationship: entailment
Domain: Hardware
Sentence 1: In this work, we model the problem of improving local­ity, i.e., reducing interaction distance, of a given quantum circuit by graph theory.
Sentence 2: we use the minimum lin­ear arrangement (MinLA) problem in graph theory to .nd optimized local quantum computation, in terms of the to­tal synthesis cost or latency, in architectures with qubits arranged in a line.
Relationship: entailment
Domain: Hardware
Sentence 1: For example, as shown in Figure 2, the distribution of wires according to wire length is different for 3-D ICs using varying numbers of device layers.
Sentence 2: it is expected that for a typical custom-logic circuit with a modest number of device layers, the wire-length distribution will be shifted away from long, global wires towards having more short, local wires, thus lowering the total overall wire length and hopefully also the delay and energy consumption of the circuit.
Relationship: entailment
Domain: Hardware
Sentence 1: While such designs enable better energy ef.ciency and higher bandwidth than the traditional low-swing signaling generated by simply lowering power supply voltage, they require dif­ferential wiring, clocked sense ampli.ers and an additional power supply voltage.
Sentence 2: the additional power supply dedicated only to the NoC low-swing datapath can be a substantial system overhead in multicore processor design.
Relationship: entailment
Domain: Hardware
Sentence 1: Figure 4 and Table 1 show some of the possible scheduling in­stances, with different combinational resource and register alloca­tions.
Sentence 2: solutions (a) to (d) allocate exactly one register for each combinational operation, whereas solutions (e) and (f) al­low combinational propagation of data thus requiring less registers and cycles (traded off by a possibly longer cycle time).
Relationship: entailment
Domain: Hardware
Sentence 1: In the latter, monitoring input signals are demultiplexed, based on an address bit, to one of two out­ put channels.2 The arbitration node then combines input monitoring signals onto one output monitoring signal, as shown in Fig.
Sentence 2: recent studies still predict signi.cant challenges, and short­comings, under extrapolated technology trends, in terms of system latency, throughput and power [19, 18].
Relationship: neutral
Domain: Hardware
Sentence 1: METHODOLOGY As described in Section 2, both delay and power dissipa­tion are functions of segment length l and repeater size s.It is well known that delay optimal values of l and s exist [4].
Sentence 2: the total length of the bus is L and the interconnects have resistance r per unit length, bulk capacitance cb per unit length, and coupling capacitance cc per unit length.
Relationship: neutral
Domain: Hardware
Sentence 1: This work concerns the practical use of carbon nanotube in digital memories, in particular this paper presents a simple yet effective hybrid word-line/bit-line design solution that aims to complement metal wire with CNT in order to well leverage the low resistance property of CNT and meanwhile embrace the drawbacks inherent in CNT.
Sentence 2: the effective length of copper word-line/bit-line is reduced by half and hence the effective resistance of the word-line/bit-line is reduced by 4.
Relationship: neutral
Domain: Hardware
Sentence 1: The effectiveness of X-.lling is determined by the number and the characteristic of X-bits.
Sentence 2: we sort these true non-essential fault candidates by removal gain(tf, v) and remove fault with the maximum removal gain(tf, v).The removal of true non-essential fault continues until no region has WSA larger than the threshold value or no true non-essential fault can be removed.
Relationship: neutral
Domain: Hardware
Sentence 1: [3] Y. Zorian, D. Gizopoulos, C. Vandenberg and P. Magarshack,  Guest Editors Introduction: Design for Yield and Reliability , IEEE Trans on Design &#38; Test of Computers, vol.
Sentence 2: if there is no object intersecting with DRW(i,j), we add a vertex vi,j to the conflict graph.
Relationship: neutral
Domain: Hardware
Sentence 1: INTRINSIC NBTI VARIABILITY AWARE RUNTIME TECHNIQUES TO MANAGE STATISTICAL PIPELINE PERFORMANCE A pipeline is designed to accommodate stages of equal delay.
Sentence 2: the interface trapping induced PMOS Vt degradation (.Vt it) is modeled as shown in Equation 2 in accordance with the reaction diffusion theory, while the hole-trapping (.Vth) mechanism saturates at nominal voltages within tens of milliseconds [1].
Relationship: neutral
Domain: Hardware
Sentence 1: [17] C. Kulkarni, F. Catthoor, and H. de Man.
Sentence 2: this is not always true, since increasing the hit ratio past a point comes at the cost of bringing substantially more data into the levels closer to the CPU (e.g, by increasing the cache line size, or through prefetching [21]), resulting in useless or redundant fetches, and increased memory traf.c.
Relationship: neutral
Domain: Hardware
Sentence 1: By moving the mechanical handle, which contains the webcam that records the scope's interior, users are invited to make their own video.
Sentence 2: literally translating the physical human gesture into a digital language, she draws a conceptual link between mass culture, technological mediation and psychological processes.1 Osciloscopiando, is part of the series of works, Recycling Junk , a body of work that shows the beauty, harmony, and symmetry of discarded electronics.
Relationship: neutral
Domain: Hardware
Sentence 1: The tuning consists of two parts, i.e., the reduction of the policy sizeby utilizing aspeci.cpolicy writing tool[10], and the tuning of kernel and userland by removing unneeded functions and redundant permission checks from the ker­nel, by reducing .le size by removing features unnecessary for embeddeddevices, andby reducing memory usageby re­moving unnecessarydatastructuresfromthekernel.
Sentence 2: proper inter­faces for the hardware accelerators should be added and the related function calls in the SELinux code need to be modi.ed accordingly.
Relationship: neutral
Domain: Hardware
Sentence 1: [6] Y. S. Dhillon, A. U. Diril, A. Chatterjee, and A. D. Singh, Analysis and optimization of nanometer CMOS circuits for soft-error tolerance, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.
Sentence 2: for SER reduction, it is not efficient to track the change in the soft error rate of a circuit by re-computing it every time.
Relationship: neutral
Domain: Hardware
Sentence 1: Furthermore, consider a 2-way set-associative instruction cache to which the basic blocks B2and B10(address range: 76-88) would map as shown in (b).
Sentence 2: the cache activity (at the gran­ularity of a cache sub-bank) is altered in such a way that any circuit-level leakage-reduction technique can pro.t from it.
Relationship: neutral
Domain: Hardware
Sentence 1: For example, with t1 = 00001111 and t2 = 10101001 (considered above) we obtain dif f (t1,t2) = {-1, 0, 2, 5, 6}.
Sentence 2: there are also circuits for which the test vector chains are unable to reach 10­detections for all the faults.
Relationship: neutral
Domain: Hardware
Sentence 1: 3 ()V ×--W (V ) PV ~expI q.V mkT () sleep SB SB sleep 0 D DD SB (3) ()af ()++C C PV ~2*..WW V 2 switching SB sleep nmos drain INT SB .. where, I0 is the current of an 1µm NMOS at Vgs=0, Vds=VDD and Vbs=0, m is the sub-threshold swing factor, .D is the DIBL coefficient, Cdrain is the drain capacitance of an NMOS, CINT is the interconnect capacitance connected to source-line , a is the transition activity (~1%) and f is the frequency of operation.
Sentence 2: for the chip at .Vtinter = -140mV (Fig.
Relationship: neutral
Domain: Hardware
Sentence 1: The signal FoN to[d] collected by the current switch is a 3-bit vector to denote link status along the other three directions except d and is transmitted to the neighbor along d. Figure 3: Fault information transmission mecha­nism.
Sentence 2: as the CMOS tech­nology scales down to the nanometer domain, smaller fea­ture size, lower voltages and higher frequencies increase the number of occurrence of intermittent and transient faults, besides manufacturing defects and wear out e.ects which lead to permanent faults are also inevitable [1].
Relationship: neutral
Domain: Hardware
Sentence 1: This graph is called the potential reachability graph.
Sentence 2: 5(a) is more compact, since the a+ b+ y- a+ b+ y-  x+ r+ s- x+ y+ b-  r+ y+ b- x- b- y+ s+ b- y+ x- s+ r- a- y- b+  a- y- b+ y- (a) (b) (c) Figure 5: Example with unsolvable CSC con.ict.
Relationship: neutral
Domain: Hardware
Sentence 1: As Vddsup increases the PMOS transistors leakage is reduced, so that the amount of reverse body bias that can be applied to the nmos transistors can be increased, continuing until a maximum value of Vddsup and V is reached.
Sentence 2: power would not be saved by actively raising Vss and consequently, no power is wasted on circuitry to drive Vss high.
Relationship: neutral
Domain: Hardware
Sentence 1: The e.ects of variations in temperature are presented in section 3.2 and the variations in gate oxide thickness are discussed in section 3.3.
Sentence 2: the e.ects of varia­tions in power supply voltage (VDD), temperature (Temp), and gate oxide thickness (tox) on the clock propagation de­lay (TC-Q)and setuptime(TSET UP )of eachregister are demonstrated.
Relationship: neutral
Domain: Hardware
Sentence 1: Note that in radix-2 and radix-4 designs, if the butter.ies in Figure 1 are used without modi.cation, multiplication by j still involves a complex multiplier.
Sentence 2: the split-radix algorithm is based on successively decomposing an N-point DFT into an N/2-point DFT and two N/4-point DFTs as follows: N .
Relationship: neutral
Domain: Hardware
Sentence 1: For instance; in the case of an 8-input OR gate, for a UNG value of 0.273 then for the new proposed technique we need a keeper ratio of 3 and we will have a delay of 2.294e-11 and a power consumption value of 3.678µW.
Sentence 2: it can also be seen from figure 5 that at any given value of power consumption, the new proposal has a higher UNG compared to that of Standard OR domino.
Relationship: neutral
Domain: Hardware
Sentence 1: As shown from the large gap that separates the singular values into subsets of large and small singular values, we can conclude that we may need only 30 paths to predict remaining paths with very high accuracy.
Sentence 2: rEPRESENTATIVE PATH SELECTION In this Section, we consider representative path selection 100 0 10 Normalized Singular Values A (b)(a) for a given error tolerance E. -1 -1 1010 4.1 Exact Selection Normalized Singular Values of A -3 -3 10 10 We .rst consider exact selection with E =0.
Relationship: neutral
Domain: Hardware
Sentence 1: How­ever, (12) is not a method that .nds the .rst multipath component, but a method that .nds the largest multipath component.
Sentence 2: the channel model can be rewritten as Lp-1 h(t)= Q aj d(t - jTc - t), (8) j=0  where Lp (= LK) is the number of paths; aj is the channel coe.cient of the j-th multipath; and t is the channel prop­agation delay.
Relationship: neutral
Domain: Hardware
Sentence 1: 2x2-Join2x2-Joinhasfourinputsandfouroutputsas showninFig.3,anditgeneratesonepulseatone ofthefouroutputsdependingontheombinationof inputpulses.Therelationshipbetweeninputsand outputsaredesribedinTableI.Forexample,ifit reeivestwopulsesat.tand.t,thenitgeneratesa pulseattheoutput11.Notethattheoutputpulse isnotdependentonthearrivalorderoftheinput pulses.
Sentence 2: obviouslyourframeworkannotdealwiththeaboveus­ageofCBs.Itshouldbenotedthatsuhasituationdoes nothappensofrequentlybythefollowingreason.Sine wetakedual-railsheme ifwegeneratef=h1+h2we alsoneedtogeneratef i.e.
Relationship: neutral
Domain: Hardware
Sentence 1: IEEE Transactions on VLSI Systems, 6(4):677 686, 1998.
Sentence 2: 2.1 Representation Transformation A set of bahavioral blocks are grouped as tasks to describe the .ow of the data stream, the design can be de­scribed as the tuple G= ,where T consists of a set of task graphs, and Eis the set of dependency edges between task graphs which ensure correct sequencing or paralleling E.T ×T.
Relationship: neutral
Domain: Hardware
Sentence 1: In the algorithm, tags are randomly assigned to time slots of a frame and when two or more tags collide in a slot, the collisions will be resolved by another DFSA algorithm while the other tags in the next slots will wait.
Sentence 2: rFID tag anti-collision algorithms will play an important role in the IoT, since a large number of nodes is expected in this new paradigm.
Relationship: neutral
Domain: Hardware
Sentence 1: Within this context, unipolar operation executes the programming/erasing by using short/long pulses, or by using high/low voltage with the same voltage polarity.
Sentence 2: [11] E. Linn, R. Rosezin, C. Kugeler, and R. Waser, Complementary resistive switches for passive nanocrossbar memories, Nature Materials, 2010.
Relationship: neutral
Domain: Hardware
Sentence 1: RELATED WORK TheprimarycontributionofthispaperistheEAF-cache,alow­complexitycacheinsertionpolicythatmitigatesthenegativeimpact ofbothcachepollutionandthrashing,bydeterminingthereusebe­haviorofamissedblockbasedontheblock sownpastbehavior.
Sentence 2: ourApproach:Topreventcachepollution,onewouldliketo predictthereusebehaviorofamissedcacheblockandprevent low-reuseblocksfrompollutingthecachebychoosinganappro­priatecacheinsertionpolicy.Assuch,wetakeanapproachsimilar topriorwork,butunlikepriorworkwhichpredictsthereusebe­haviorofagroupofblocks,wepredictthereusebehaviorofeach missedblockbasedonitsownpastbehavior.Unfortunately,keep­ingtrackofthebehaviorofallblocksinthesystemwouldincur largestorageoverheadandlookuplatency.Weeliminatethishigh costbytakingadvantageofthefollowingobservation:Ifablock withhighreuseisprematurelyevictedfromthecache,itwilllikely beaccessedsoonaftereviction.Ontheotherhand,ablockwithlow reusewillnotbeaccessedforalongtimeaftereviction.Thisob­servationindicatesthatitissufficienttokeeptrackofasmallset ofrecentlyevictedblockstopredictthereusebehaviorofmissed blocks blocksevictedalongtimeagoareunlikelytohavehigh reuse.Toimplementthispredictionscheme,ourmechanismkeeps trackofaddressesofrecentlyevictedblocksinahardwarestructure calledtheEvicted-AddressFilter(EAF).Ifamissedblock saddress ispresentintheEAF,theblockispredictedtohavehighreuse.Oth­erwise,theblockispredictedtohavelowreuse.
Relationship: neutral
Domain: Hardware
Sentence 1: 3.1 Pattern Generation BSC (PGBSC) As mentioned before, two test vectors are needed for each of the six integrity faults.
Sentence 2: the most important ones are: crosstalk (signal distortion due to cross coupling effects between signals) [3] [4], overshoot (sig­nal rising momentarily above the power supply voltage) [5], re.ection (echoing back a portion of a signal), electro-magnetic interference (re­sulting from the antenna properties) [7] and signal skew (delay in ar­rival time to different receivers) [8].
Relationship: neutral
Domain: Hardware
Sentence 1: Briefly, PbO is dissolved in oleic acid and heated to 150°C.
Sentence 2: the layered device consisted of a 40 nm poly(3,4­ethylenedioxythiophene) (PEDOT): poly(styrenesulfonate) (PSS) spin-coated on an ITO-coated glass slide and annealed at 120°C for 30 min in vacuum.
Relationship: neutral