sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: = (e - 2)ln v 2 0.01/3 min1/2, 2 =16 × 0.71 × 6.40 = 72.7 As described in [20], the modeler de.nes number of simulation traces which are required to achieve a given (c, d)-approximation.
Sentence 2: in most cases time limits are more important than the number of traces and a.ects the values of c and d. time limit is set for simulation and the con.dence interval is computed based on the generated traces.
Relationship: entailment
Domain: Hardware
Sentence 1: Table 1: Experimental Data #nets initial C D F COST data1 data2 data3 data4 data5 316 192 160 160 160 175 418 252 250 271 316 192 160 168 164 356.45 620.00 414.30 434.73 406.14 847.45 1230.30 826.30 852.73 841.14  3.6 Via assignment method Our via assignment method is a greedy-based heuristic.
Sentence 2: the method gives an initial via assignment and mod­ify the current via assignment by the modi.cation with the maximum gain among all EXCs, ROTs, and MSEQs under the monotonic and detour-preventive condition.
Relationship: entailment
Domain: Hardware
Sentence 1: For example, in Figure 5, the bold path s1ls2ls4ls7ls10 shows the wakeup scheduling Scheduling (A) where the time duration 't(s1, s2) is zero meaning that sleep transistors (S1, S2) are the initial group to be turned on.
Sentence 2: s1ls2 is a redundant edge.
Relationship: entailment
Domain: Hardware
Sentence 1: We then use this as a starting value for our evaluation, and estimate during simulation the impact that an increasing number of break-even cycles has on the performance of the power-gated design.
Sentence 2: we force the FSM to re­main in a state (see Section 2) for an increasing number of cycles, ranging from 10 to 100, and then evaluate the number of clock cy­cles the FSM remains in lower states.
Relationship: entailment
Domain: Hardware
Sentence 1: Furthermore, we demonstrate that this cost reduction is adaptive to both the extent to which the individual node subscriptions correlate, and the amount of information about the other node subscriptions available to each node.
Sentence 2: in the worst case sce­nario when subscriptions are completely uncorrelated or un­known or both, the message dissemination costs are no worse than those of name-independent DHT systems.
Relationship: entailment
Domain: Hardware
Sentence 1: pe2Ode( pei) ODE Binding constraint: valid( pe2Type( pei), ode2Type(oi)) = true Each ODE has been mapped to one PE.
Sentence 2: the objective is (minimize cycles per step): Min {max (CompCost(pe2Type(pei), pe2Ode(pei))) + CommCost} the objective is to allocate a valid set of PEs (satisfy the FPGA resource constraint), and to find a valid mapping from ODEs to PEs (satisfy the ODE binding constraint) such that the throughput of the system is maximized.
Relationship: entailment
Domain: Hardware
Sentence 1: Thus from the point of view of conserving energy it is desirable that the nodes do not perform receive operations during the sleep state.
Sentence 2: the results highlight the importance of developing ef.cient mecha­nisms which enable the receivers to wake-up just-in-time (possibly for a short period of times) to receive packets from their neighbors, or to develop ef.cient mechanisms to synchronize sleep schedule of neighbors.
Relationship: entailment
Domain: Hardware
Sentence 1: Further, let the mu­tual inductive coupling of a signal pin to its neighbor s neighbor be expressed as k2 (likewise k3, k4, etc.).
Sentence 2: we assume that kx = 0for x > p. if p = 3, then we ignore the induc­tive cross-talk due to the 4th neighbor and beyond, by setting k4 = k5 = ... = kn = 0.
Relationship: entailment
Domain: Hardware
Sentence 1: Theorems 1 and 2 provide a theoretical foundation for any work-maximizing, DVFS control policy.
Sentence 2: the theo­rems specify the speed levels needed and indicate that it is advantageous in terms of maximizing the work completed to alternate between the high and low speeds while allowing the chip to reach the maximum temperature at the end of every high speed application interval.
Relationship: entailment
Domain: Hardware
Sentence 1: Table 3: Results using SNDRs with an upper bound on track cost of 7. testcase track cost capacitance reduction (%) reduction (%) aes_cipher_top 53.8 12.15 eth_top 46.8 13.14 jpeg_encoder 48.1 12.37 mc_top 49.1 12.45 mpeg2_top 52.5 12.14 tv80s 48.0 11.49 usbf_top 48.1 11.11 wb_conmax_top 49.7 13.16 wb_dma_top 52.7 14.28 Last, to assess the potential for area recovery using various SNDRs, we perform an additional study using a set of SNDRs which main­tains track cost less than the original .xed NDR.
Sentence 2: we explore reduced-area SNDRs of (1W2S), (2W4S) and (3W6S).
Relationship: entailment
Domain: Hardware
Sentence 1: Deciding When to Launch Attacks on Process Control Systems Marina Kroto.l Hamburg University of Technology 21079 Hamburg, Germany  ABSTRACT We introduce a new problem formulation for understanding the threats and vulnerabilities of process control systems.
Sentence 2: we consider an adversary that has compromised sensor or actuator signals of a control system and needs to identify the best time to launch an attack.
Relationship: entailment
Domain: Hardware
Sentence 1: Dynamic Adjustment Figure 3: F Measures as scaled with window size for average and for different users as test subjects As shown in Figure 3, different curves result from leaving speci.c users out of the training in a cross-validation setting of the data set in [8], using different window size each time.
Sentence 2: the way in which an individual user might perform particular actions either conforms to the model or shows their necessity in the training set for a more robust model for other users.
Relationship: entailment
Domain: Hardware
Sentence 1: In the .rst case the number of steps taken to advance to node k from k-1 is 1, however in the second case the number of steps required is 1+ Tk (one step to reach node 0 and Tk steps to reach node k from node 0).
Sentence 2: this means the average number of steps taken from node k - 1 to node k is the average of 1 and 1+ Tk.1+ (1 + Tk) Tk = Tk-1 + .
Relationship: entailment
Domain: Hardware
Sentence 1: A congestion pattern in PS0 pipelines involves a pattern of adjacent stages in alternating states of precharge and precharge-release, since the pipeline has a capacity of only 50%, hence ackk+1 = 0 and ackk+2 = 1.
Sentence 2: a right vector of alternating values, 101, is a signa­ture of congestion.
Relationship: entailment
Domain: Hardware
Sentence 1: Since fetching the entire cache block for bypassed data with little spatial locality will cause cache pollution and extra traffic, they used small lines (equal to the element size) for the buffers and optionally fill in consecutive blocks when spatial locality is detected.
Sentence 2: they are using a single buffer to serve the purpose of both a victim cache (for scalar data) and a prefetch buffer (for stream data).
Relationship: entailment
Domain: Hardware
Sentence 1: Although interconnection network design has matured over the years with respect to multiprocessor architectures, NoC design comes with a different .avor because of the area, en­ergy and reliability constraints in deep sub-micron design.
Sentence 2: vulnerability of the NoCs to increased prob­ability of permanent/hard faults resulting from accelerated aging effects and manufacturing/testing challenges in deep sub-micron design makes reliable communication a major challenge.
Relationship: entailment
Domain: Hardware
Sentence 1: Later on as ap­plying EP within each subcircuit, the wirelength would not become a big concern, because this is only a locally packing exploration among a small number of modules.
Sentence 2: in the spirit of DDM,in­stead of deferring the decision on the slicing tree structure among all modules in the circuit, .rst we .x the high-level slicing tree structure among the subcircuits by partitioning, and then defer the decision on the slicing tree structure among the modules within each subcircuit.
Relationship: entailment
Domain: Hardware
Sentence 1: The results support our prior conclusions for the MaxBIPS policy, showing the effectiveness of CMP power management with adaptive global policies.
Sentence 2: maxBIPS, which can tailor each core s power mode dynamically with respect to local workload variations under the global power budget con­ 6.1.1 Trends under CMP Scaling Comparing our policy results across different CMP scales shows important trends.
Relationship: entailment
Domain: Hardware
Sentence 1: 2.3 Control-Independence Architectures to AlleviateFetchCriticality Inaprogram .owgraphwesaythat oneinstruction X post­dominates another instruction A iff all paths through the .owgraph from A to the exit pass through X [7].
Sentence 2: x postdominatesA if X isguaranteedto execute af­ter A executes, regardless of intervening control decisions.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper we focus on the issues related to the choice of a suitable set of samples of the cross-correlation function Rxy(mi), i=1,..,n, as DUT signature, and, at the same time, to the definition of an effective classification procedure [5-6].
Sentence 2: we make the choice of the DUT signature on the basis of the sensitivities of the cross-correlation samples to the circuit specifications sj, expressed in terms of the partial derivatives wij =wRxy (mi)/wsj.
Relationship: entailment
Domain: Hardware
Sentence 1: The above messages along the aggre­gation hierarchy logically build a commitment tree which en­ables the authentication operation in the next phase.
Sentence 2: once the base station receives the .nal commitment, it veri.es the coherence of the .nal counts, c1, c2,..., cb, with the number of nodes in the network, N. the BS performs P the following sanity check: ci = N. A simpli.ed version of the aggregation-commit phase is illustrated in Figure 1 with an example of a small network.
Relationship: entailment
Domain: Hardware
Sentence 1: For the purpose of predicting the two types of power supply noise, characteristic of an interposer, such as LSI package and PCB, is conventionally used [8].
Sentence 2: because package interposer is in between the LSI and the PCB, the power supply voltage .uctuation on the LSI and the conducted noise are estimated from the re.ection and the transmission characteristics of Z-parameter of the pack­age interposer, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.1 (Micro-) Architecture Platforms Integrated circuits used for embedded systems will most likely be developed as an instance of a particular (micro-) architecture platform.
Sentence 2: rather than being assembled from a collection of independently developed blocks of silicon functionalities, they will be derived from a speci.c family of micro-architectures, possibly oriented toward a particular class of problems, that can be extended or reduced by the system developer.
Relationship: entailment
Domain: Hardware
Sentence 1: As the application program is .xed, there exists a lot of .exibility in choosing an optimal design for the application in ques­tion.
Sentence 2: customized processors [4, 6] and con­.gurable system-on-chip platforms [1] provide the designer of an embedded system with the opportunity to con.gure the memory subsystem for a particular application.
Relationship: entailment
Domain: Hardware
Sentence 1: Register prefetching will be able to reduce overall cache tra.c only if the prefetched values are used more than once after be­ing brought into the prefetch bu.er.
Sentence 2: though prefetching employs spatial locality in bringing values closer to the processor, the actual utility (in terms of reducing cache tra.c) depends on temporal locality of the prefetched values.
Relationship: entailment
Domain: Hardware
Sentence 1: The link ma­ t At the same time, the weight for both timing delay and resources trix is given by the equation 4 where the values are the conditional probability of B becoming either hardware or software given that A has occurred.
Sentence 2: p (HWb|SW a) gives the prob­ability of module of node B becoming a hardware given that the module of node A is software.
Relationship: entailment
Domain: Hardware
Sentence 1: If the circuit can be placed in a known standby state, as described earlier, this delay impact may be avoidable if high-Vt and thick-oxide devices are carefully assigned.
Sentence 2: a recent approach combining sleep state assignment and Vt assignment was proposed [12], however, this approach does not consider gate leak­age current and as such cannot minimize total leakage current in 90nm technologies and beyond.
Relationship: entailment
Domain: Hardware
Sentence 1: Rint = .l (W0 T0 ) (11) Cint and Rint are affected in different ways by W and T, as illustrated by (10) and (11).
Sentence 2: cint increases while Rint decreases with increasing W and T. This relationship implies that for small W and T, interconnects are resistance dominated while for large W and T interconnects are capacitance dominated.
Relationship: entailment
Domain: Hardware
Sentence 1: Thus, an extensive set of gate-level power simulations (VCS/PowerCompiler) is launched within a Test­bench Generation suite, specifically tuned to fulfill the many requirements imposed by the STBus protocols and, at the same time, to sensitize the node under a wide range of traffic workloads.
Sentence 2: the test-benches can be configured in terms of average latency per master request and slave response and type of operations to be performed on the bus.
Relationship: entailment
Domain: Hardware
Sentence 1: 2, as well as for the BIST controllers in [16] (for multi-port static RAMs), in [17] (for the Motorola high performance microprocessor e500 core) and in [8] (for Intel/HP McKinley microprocessor cache testing), none of them is generally Fault Secure with respect to its possible internal faults.
Sentence 2: for all these schemes, the critical block is the output comparator.
Relationship: entailment
Domain: Hardware
Sentence 1: The rate of Vc increase using the proposed active-decoupling circuit is also always slower than that using the conventional counterpart.
Sentence 2: the proposed active-decoupling circuit improves the substrate-noise suppression from 3.6 to 6.6 times as compared to the conventional active-decoupling circuit when the 1 GHz noise-source amplitude increases from 100mV to 500mV.
Relationship: entailment
Domain: Hardware
Sentence 1: This meshing scheme then holds the smallest .lament width at the skin depth, and adjusts the ratio between adjacent .laments so as to .t the .laments inside the given width w. More precisely, given a conductor of width w and N, the number of desired .laments, the ratio r between adjacent .laments satis.es () Nf2 -1 r 2d , even N, {r -1 w =( ) (2) (N.1) f2 -1 r (N.1)f2 2d +drodd N. r -1 , While EM-1 and EM-2 perform excellently in terms of model and simulation accuracy and are widely used in practice, we will show that signi.cant savings in computation can be realized with alternate meshing schemes, at negligible loss in accuracy.
Sentence 2: conventional EM schemes are an over-kill.
Relationship: entailment
Domain: Hardware
Sentence 1: Experimental results on a set of industrial circuits show that by adding slack and FOM sensitiv­ities, we are able to obtain better results for not just timing-driven placement, but also the physical synthesis optimization after it.
Sentence 2: considering the FOM sensitivity to explicitly guide the net weight generation, we can further improve the .nal FOM mea­surement without deteriorating the worst slack and wire length.
Relationship: entailment
Domain: Hardware
Sentence 1: a geomet­ric parameter (p), for instance the width of a conductor, the thickness of each metal layer or the height of dielectrics.
Sentence 2: this dimensional sensitivity can be computed by assembling the as­sociated panel sensitivities: .Cij =Sk,ij (8) .p k.Sp where Sp is the set of panels incident to the geometric param­eter p. these are the panels that show displace­ments according to the parameter variation.
Relationship: entailment
Domain: Hardware
Sentence 1: As demonstrated by the above example, for con.gurations composed of only k-LUTs the problem consists of .nding which function inputs are mapped to which k-LUTs (if many k-LUTs exist).
Sentence 2: partitioning the function inputs into groups corresponding to the k-LUTs (without determining the individual mapping onto the k-LUT pins) guarantees the existence of a solution.
Relationship: entailment
Domain: Hardware
Sentence 1: The organization of the data array section of one of the 512KB cache structures 2.2 Con.gurable Cache Operation With these modi.cations, the cache behaves as a virtual two-level, physical one-level non-inclusive cache hierarchy, with the sizes, associativities, and latencies of the two lev­els dynamically chosen.
Sentence 2: we have designed a single large cache organization to serve as a con.gurable two-level non-inclusive cache hierarchy, where the ways within each subarray that are initially enabled for an L1 access are varied to match application characteristics.
Relationship: entailment
Domain: Hardware
Sentence 1: Experimental results based on three real-world circuit designs show that our P/G network analyzer is accurate enough and very ef.­cient.
Sentence 2: with our .oorplan-based P/G network analyzer, the power integrity-driven design .ow successfully .xed the IR-drop errors earlier at the .oorplanning stage and thus enabled the single-pass design methodology.
Relationship: entailment
Domain: Hardware
Sentence 1: In conditional slack matching, however, whenever a re-convergent fanout is formed between the two modes, far less number of buffers are needed because the gap values can accommodate for large differences between arrival times in different modes.
Sentence 2: it shows we achieve a 14% reduction of slack­matching buffers with 8 nodes and a reduction of 32% of slack­matching buffers with 64 nodes.
Relationship: entailment
Domain: Hardware
Sentence 1: Schematic representation of our aging sensor.
Sentence 2: starting from the monitored signal (Si), by means of a proper delay block (namely, a simple NOT gate), we generate an additional signal Ci that, together with the monitored signal (Si), provides: 1) a codeword belonging to the two-rail code (i.e., a no alarm indication), that is (O1,O2) = (1,0) or (0,1), if signal Si is stable during guardband TM (i.e., when TWC=1); 2) a two­rail non codeword (i.e., an alarm indication), that is (O1,O2) = (0,0) or (1,1), if undesired transitions of Si occur during the guardband TM (i.e., when TWC=1).
Relationship: entailment
Domain: Hardware
Sentence 1: Algorithm 1 NSGA Algorithm 1: pop .GenerateInitialPopulation 2: if generation =max generation then 3: rank .NonDominatedRanking(pop) 4: fitness .FitnessAssignment(pop, rank) 5: for i = 1 to N step 2 do 6: parent1 .Selection(pop, fitness) 7: parent2 .Selection(pop, fitness) 8: (child1, child2) .Crossover(parent1, parent2) 9: newpopi .Mutation(child1)  10: newpopi+1 .Mutation(child2) 11: end for 12: pop .newpop 13: generation .generation +1 14: end if 15: final rank .NonDominatedRanking(pop) 16: NonDominatedSolutions .popi, .i .final ranki =1 17: return NonDominatedSolutions  3.1 Pareto-optimal Solution A solution is called Pareto-optimal solution, if there exists no other solution for which at least one of its criterion has a better value while values of remaining criteria are the same or better.
Sentence 2: one can not improve any criterion without deteriorating a value of at least one other criterion.
Relationship: entailment
Domain: Hardware
Sentence 1: The basic idea of the MSR multiplier [10, 9] is the following: ab = a(b0 + b1a + b2a2 + ···bm-1am-1) = ab0 +(aa)b1 + ···+((···((aa)a) ···a)bm-1.
Sentence 2: the sum can be computed using an m-stage ap­proach.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that the scope of an LE only needs to be determined prior to the calculation and application of the pin permutation on it; following the topological order, it is possible to dynamically define a hierarchical LE according to the already optimized input slacks to a logic cluster.
Sentence 2: if we want to group two LUTs Ls and Lt as in the preceding paragraph into an LE, the best practice would be to choose Ls to be the driver of the most critical input of Lt, since this gives an opportunity to move the most critical pin off Ls and onto Lt, which is likely to reduce the nominal cell delay of the pin (and thus may improve its slack).
Relationship: entailment
Domain: Hardware
Sentence 1: One can observe from Table 1 that we are able to .nd link l2 « l1, because of which a2 is less than a1 and so are the skew variations.
Sentence 2: experiment 2: The aim of this experiment is to observe the e.ect of the link on the delays of the sinks within a sub­tree, for example, sink delays in subtree Ti.this experiment demonstrates the Scenario 1 in the quali­tative analysis.
Relationship: entailment
Domain: Hardware
Sentence 1: As shown in Eq(7), an ideal alternative distribution should simulate only the failure cases and follow the original distribution in that region.
Sentence 2: the perfect and ideal alternative distribution is nothing but PDF (xi |f<t)=PDF (xi,f <t)/Prob (f<t).Byusingthe bivariate Gaussian distribution, .. 2(f-a0)2 2xi.xi (f-a0) .x + - .
Relationship: entailment
Domain: Hardware
Sentence 1: Our .rst result is that there exists an algorithm that can compute an o-Pareto set for a system of n components, whose number of queries is independent of the size of the exact Pareto set (which could be arbitrarily large).
Sentence 2: 1 the number of queries depends only on the number of components n, their range a and the desired accuracy o. THEOREM 3.1.
Relationship: entailment
Domain: Hardware
Sentence 1: The maximum local clock skew (MLCS) of a clock tree T , de­noted as MLCS(T ), is de.ned to be the largest LCS in the entire tree: MLCS(T ) = max |ti - tj |.
Sentence 2: (1) MD(i,j)=L the ISPD 10 contest requires that the 95th percentile of MLCS(T ), denoted as 95%MLCS(T ), be kept below a user-speci.ed LCS constraint C under power-supply variations and wire-width variations.
Relationship: entailment
Domain: Hardware
Sentence 1: The reduced parasitics for interconnects can further significantly simplify the circuit and power distribution network design for high perform­ance applications.
Sentence 2: massive amounts of inexpensive storage currently supplied by Magnetic Hard Disks can potentially be supplied by flash memory located within the same chip, eliminating the multiple communication hierarchies from the chip to off-chip caches to board-level traces to cables and back.
Relationship: entailment
Domain: Hardware
Sentence 1: We use DN-Hunter to not only provide real-time traf­.c visibility and policy controls, but also to help gain better understanding of how the dynamic web is or­ganized and evolving today.
Sentence 2: we show many other applications of DN-Hunter including: (i) Spatial Discovery: Mapping a particular content to the servers that actually deliver them at any point in time.
Relationship: entailment
Domain: Hardware
Sentence 1: Then the MODC set for its fanin edges are: MODC(yi,f )=(yc =i)UMODCf MODC(yc,f )=MODCf Intuitively, the control variable has to be evaluated in order to do the multiplexer assignment, therefore its MODC directly inherits from node f ; a data variable is blocked from the output of f ,if itis de-selected by the control variable.
Sentence 2: for a predicate or expression node f =f (y1,,yn), where all inputs are data variables, we have: MODC(yi,f )=MODCf an expression node is a trigger node if and only if all of its fanouts are trigger nodes.
Relationship: entailment
Domain: Hardware
Sentence 1: If we can capture the spatial signature of each wafer with an accurate model, and further automatically partition all wafers into different groups based on such spatial signatures where each group carries a similar spatial signature, it would provide important insights to help process engineers for yield improvement.
Sentence 2: process engineers can rely on the information to prioritize different yield improvement strategies and focus on the variation sources associated with significant yield loss.
Relationship: entailment