sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Because these 5 faults bits are detected by parity bits P0-P4 of the class 0 word, and parity bits P5-P7 also detect the presence of faults, the faults detected by P5-P7 must be due to bit flips in bits 5-7 of byte 0 of the class 0 word.
Sentence 2: faults in the class 0 word are located.
Relationship: reasoning
Domain: Hardware
Sentence 1: Local times of all threads are not allowed to deviate from another by more than the lookahead tla .
Sentence 2: a time limit tlim,i is introduced as de.ned in equation 1. ti = tlim,i = min tj + tla (1) 0=j <n Every thread i is allowed to simulate without synchro­nization until it needs to process an event ei with a trigger timestamp ttrigger,ei beyond tlim,i .
Relationship: reasoning
Domain: Hardware
Sentence 1: Since we have 256 sets in our im­plementation, this results in an additional 512-bits added to our L1 cache.
Sentence 2: even though we introduce a minimal amount of extra storage, by adding a dynamic mechanism that allows a set to re-lookup into a prede.ned secondary set, we e.ectively double the size of the given set without needing to double the hardware.
Relationship: reasoning
Domain: Hardware
Sentence 1: Perez et al [37] experimentally compared twelve of the recent and/or well known prefetching schemes using the SPECcpu2000 benchmarks, and found that the Global History Buffer (GHB) with its PC/DC (program counter/ delta correla­tion) variant [25] scheme works the best among the twelve prefetchers.
Sentence 2: the GHB-PC/DC scheme, which is essentially an address-based correlation prefetcher, was selected as one of the comparison points.
Relationship: reasoning
Domain: Hardware
Sentence 1: 5.1 Private Slave Creation The necessary condition to make a slave interface j pri­vate [1] to a master interface i is that 1: m =i crmj = 0: m ==i If the above relationship holds, slave j need not be con­nected to any other master than i.
Sentence 2: i should be able to access j without waiting to be granted the bus.
Relationship: reasoning
Domain: Hardware
Sentence 1: 450 Refresh Intervals 400 (Write Overhead) 1 (50.0%) 350 Sub-region Memory index block size Figure 8: Two-Level Security Refresh (Within a bank) SRC triggers an inner-level, sub-region refresh, the sub-region SRC atomically performs a swap operation of two RMAs inside the sub­region.
Sentence 2: every ri writes to a given sub-region (where ri is the security refresh interval of the inner-level sub-region Se­curity Refresh) will trigger one new refresh operation in the sub­region.
Relationship: reasoning
Domain: Hardware
Sentence 1: IV IV Tin p Tinp Tin p The bistability property is preserved if the peak current of the NDRL is under the current through the NDRD around VL +V = V -VB /2 .
Sentence 2: the constraint is given by, bias pp ( + b (V - (V -VB /2)) + b (V - (V -VB /2))2) fb L 01 out p 2 out p (6) +FFL (s0 + s1(Vout - (Vp -VB /2 ) ) - fD (h0 + h1(Vout - (Vp -VB / 2 )) +hV - )2 ( - (V VB /2 ) ) + FF (t + t (V - (V -VB /2 ) ) > 0 2 out p D 01 out p An analogous reasoning can be performed to obtain a new expression associated to the bistability problem when the input + low voltage decreases to =V (see Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: As nesting is not allowed, Jj can either execute a lcs or a gcs.
Sentence 2: the local blocking time of a job Ji is bounded by: Bi1(wi(q)) =max(.j LR,.j GR) (6)  tj .lplU (i) lplF (i); if(i==F ) with tj .lpl(i); if(i==U)||(i==A) The .rst clause above captures the case where ti is a .nished task.
Relationship: reasoning
Domain: Hardware
Sentence 1: Similarly, the remaining data of the two A rows and the two B columns are streamed to the two processing elements in pairs, pro­ducing a series of intermediate results (cxx 2 and cxx3 ).
Sentence 2: after N=4 steps, the correct .nal result for the c11, c12, c21, c22 is calculated by the PEs and is ready to be loaded by the master processor.
Relationship: reasoning
Domain: Hardware
Sentence 1: This recon.guration delay is quite signi.cant on commercial architectures with column-based RTR capability as an example, recon.guration delay for a convolution task on the XC2V3000 device is greater than task execution time for a 256X256 image.
Sentence 2: a dynamic task as described above can be represented by 0 a 5-tuple (ai, rti, eti , fi 0 , bw0 i ), where ai is the task area, rti is the recon.guration delay, f0 is the maximum allowable task clock fre­ i quency (obtained from placement and routing data), et0 is the task i execution time at clock frequency f0, and bw0 is the task band­ i i width requirement at frequency fi 0 .
Relationship: reasoning
Domain: Hardware
Sentence 1: 2.3 Simulation Results for LVSC Domino Logic Allsimulationresultsinthissectionarebasedona0.18 fmCMOSprocess.Thehighandlowsupplyvoltageare 1.5Vand1.0V.Figure3showsthedelaytimevariationac­cordingtotheinputarrivaltimediferencefor2-inputAND gate.VDDHconvdenotestheconventionaldominologic  gatesareintheprechargephaseduringthestandbymode.
Sentence 2: 80  Isubinthestandbymodeisdeterminedbybothstacked NMOSevaluationtransistorsandthePMOStransistorof outputinverter.Figure4showsIsubincreaseinLVSCscheme 70  forseveraldominologicgates.Todrivelargefanout,stage ratiobetweendynamicpartandstaticpartofdominologic gateisusuallygreaterthan2andthestaticoutputinverter Delay time [ps] 60 ofdominologicisusuallyhigh-skewedforhighspeedopera­tion.Furthermore,Isubofstackedtransistor(NMOSevalu­ ationtransistor)ismuchlessthanthatofnon-stackedtran­ 50 40 Figure3:Delaytimevariationsaccordingtothe inputarrivaltimediferencefor2-inputANDgate 30 sistor[2].theincreaseinIsubbylowVtNMOStran­sistorinthecriticalpathservesrelativelysmallportionof thetotalstaticpowerconsumptionsincelargePMOStran­sistorofoutputinvertermainlycontributestotalIsub.As aresult,theperformanceofdominologicgatecanbeim­provedbyapplyinglowVttoNMOStransistorinthecritical pathwithsmallamountofincreaseinIsub.
Relationship: reasoning
Domain: Hardware
Sentence 1: In order to reduce DRAM refresh energy, in our work, data in DRAM decay over time, which is a popular method in reducing cache leakage power [8].
Sentence 2: after a long idle period elapses since last reference, DRAM data are evicted (and, if dirty, written back to PRAM) and the corresponding DRAM area, i.e., the corresponding DRAM row does not need to be refreshed, which reduces DRAM refresh energy.
Relationship: reasoning
Domain: Hardware
Sentence 1: Given Slowdownlimit, the goal of the performance-guarantee algorithm is to ensure that the underlying energy management al­gorithm does not slow down the execution beyond this acceptable limit.
Sentence 2: there are two key components to the performance­guarantee algorithm  (1) estimating the actual slowdown due to energy management, and (2) enforcing that the actual slowdown does not exceed the speci.ed limit.
Relationship: reasoning
Domain: Hardware
Sentence 1: The detection of an SDF at gate g with size s necessitates the existence of a sensitized path from an input i to an output o of the circuit going through g and having an accumulated fault-free delay greater than or equal to tobs - s. Intuitively, a sensitized path is composed of gates with off-path input(s) set to values which allow the propagation of transitions from the on­path input(s) to the output of the gate.
Sentence 2: a transition launched at i can reach gate g; the SDF will result in different waveforms for the faulty and the fault-free circuit; and these differences could propagate through the remainder of the path from g to o and may be observed.
Relationship: reasoning
Domain: Hardware
Sentence 1: Comparing equations 1 and 6, due to the presence of bends, if the same pressure drop is applied on a straight and a bended micro-channel of the same length, the bended channel will have lower .uid velocity, which leads to a lower cooling capability.
Sentence 2: to provide su.cient cooling, we will need to increase the overall pressure drop that the pump delivers, which results in increase of pumping power.
Relationship: reasoning
Domain: Hardware
Sentence 1: In a checkpoint/recovery system, the release of a check­point is an irreversible action.
Sentence 2: the system must  Table 2: Cost of combined bug and defect detection Mechanism Flip-Flops Covered Area Overhead Power Overhead Online Design 39K Flip-Flops Bug Detection (bug detection) + 15.15% 6.8% Online Hardware 262K Flip-Flops Defect Detection (defect detection) after system repair, the system state is rolled back to the last checkpoint for re-execution as described in [7].
Relationship: reasoning
Domain: Hardware
Sentence 1: LLC parameters number of sets S 2048 sets associativity W 8 way line size B 64B LLC size S × W × B 1MB ECC FIFO parameters tag size log2(S × W ) 14 bits the coalesce bu.er size m 6 T1EC size per cache line T1 see Section 4 T2EC size per cache line T2 see Section 4 T2EC FIFO size k see Section 3.2 Others DRAM bandwidth BW 5.336GB/s eager write-back period Tewb 106 cycles processor clock clock 3GHz with light-weight correction).
Sentence 2: we do not provide dedicated on-chip storage for the T2EC and instead write this redundant information into a FIFO structure allocated inDRAM(Figure1).
Relationship: reasoning
Domain: Hardware
Sentence 1: Comparedto these approachesthatintroduce the .nalOperatingSystemonly atlowlevelInstructionSet Simulators(ISS)basedplatforms, wepropose,in thispaper a hardware executable model able to handle a real Operat­ingSystem veryearlyinthedesign .ow.
Sentence 2: animportant partoftheOperatingSystem canbe validatedon suchnative platform.
Relationship: reasoning
Domain: Hardware
Sentence 1: If one-unit flow is injected along the direction of this cycle, Flow network: Residual graph: flow (7,0,1) 1 -: undetermined (12,1,1) 3 3 (7,3,3) 3 35 5 (-10,-,-2) (a) Flow network: 1(7,1,1) (12,0,1) 3 (7,2,3) 3 5  (b) then this negative cycle can be removed, and the optimal solution is found.
Sentence 2: if there exists a negative cycle inside the residual graph, we can reduce the wire area by modifying the flow on each edge within this cycle.
Relationship: reasoning
Domain: Hardware
Sentence 1: Ideal candidates occur very rarely during nor­mal execution, minimizing overhead due to false positives, but al­ways manifest in the wake of a fault.
Sentence 2: to maximize the overhead-to-coverage tradeoff the experiments in Section 5 eval­uate a Shoestring implementation that only considers instructions that can elicit the second category of fatal, ISA-de.ned exceptions as potentially symptom generating.
Relationship: reasoning
Domain: Hardware
Sentence 1: xn, while the output set describes all pos­ = d = sible tuples of functions f , f, fI de.ning a P-circuit for f. From De.nition 1, we can observe that the sets f|xi =p  I = d= and f|xi d I must be always contained in fand f, =p respectively.
Sentence 2: all points in f|xi =pI are associated to the output 100, and all points in f|xidI are associated to the =p output 010 of Rf.
Relationship: reasoning
Domain: Hardware
Sentence 1: (ii) Extruded Dielectric Insulated Power Cables: There are two major types of extruded dielectric insulation  Cross-linked polyethylene (XLPE) or Tree­retardant cross-linked polyethylene (TR-XLPE)  Ethylene propylene rubber (EPR)   Now a days, because of their number of advantages XLPE power cables are most commonly used throughout the world.
Sentence 2: the aim of this paper is to develop mathematical model of XLPE insulation of 132 kV power cable.
Relationship: reasoning
Domain: Hardware
Sentence 1: Suppose that the write endurance of PCM is 10N .
Sentence 2: the free seg­ment list only needs N+1 buckets, and all the free physical seg­ments linked to bucket ihave their remaining write counts between 10i and 10i-1 +1,where 0 = i= N. free physical segments linked to bucket Nare the youngest ones.
Relationship: reasoning
Domain: Hardware
Sentence 1: Dually, if CurrKey is a vertex of one of the eight top-level mini-cubes, then S = E =2k-1 .
Sentence 2: the value of S can be com­ 2 puted by observing that on each axis the distance between CurrKey and the root (obtained through distAxis) must be an exact multiple of S. F iterates over each axis and recursively halves the length of the mini-cube edge un­til it exactly divides the distance from CurrKey to the root key coordinate along that axis (lines 5 6).
Relationship: reasoning
Domain: Hardware
Sentence 1: R d VDD - ( Vth,p +.Vth,NBTI ) T In the case of power-supply variations, maximal NBTI-impact (affected repeater fraction = 1) increases form ~6% at 1.1V to ~10% at 0.9V.
Sentence 2: from the NBTI perspective, nominal or below nominal channel-length devices operating at a high VDD Fig 8 Performance variation due to variation in Temperature Fig 9 Performance variation due to variation in VDD 5.
Relationship: reasoning
Domain: Hardware
Sentence 1: ....... i-'~.-~ ...... i ........ i..,-.._-,~:=~;~.....i ...... i ...... simulated users.
Sentence 2: 440 minutes of unidirectional o.~ ......... : ......... : ......... '- ......... '- ......... '- ......... '- ........ :-... -'~....~ ....... ] ....... voice data, stored in 96 speech files, obtained within the 48 bi-directional conversations from the MOS tests, was i  o~ o.2 o.3 o..i o.s o~ ~.7 o.a o.9 ~ .i mean siler¢~ I~n~h [$] analyzed and the results presented in this chapter.
Relationship: reasoning
Domain: Hardware
Sentence 1: Second, allowing very large currents through M1 initially will cause power supply bounce (noise on the VDDL node the node VDDL is shown in Figure 6(a)) due to the large current transient at the start of wake-up.
Sentence 2: m1 is sized adequately to facilitate a rapid rise of VVDD while ensuring the noise on the power supply rail is not significant.
Relationship: reasoning
Domain: Hardware
Sentence 1: Inside SBox, old_mask is used to select the upper part, where the data are the values from the MA address of SBox (address is masked by 0), or the lower part, where the data are the values from the complement of the MA address of SBox (address is masked by 1).
Sentence 2: the final 32:1 selector can use the high bits of the masked address MA (MA) to select the final output.
Relationship: reasoning
Domain: Hardware
Sentence 1: The CPI due to off-chip misses for R-NUCA is on average within 17% of the shared design s for server workloads, while the private design increases the off-chip CPI by 72%.
Sentence 2: r-NUCA delivers both the fast local access of the private design and the large effective cache capacity of the shared design, bridging the gap between the two.
Relationship: reasoning
Domain: Hardware
Sentence 1: One other caveat with regard to these numbers is that they are overly conservative because they count store operations that may not be necessary because the promoted variable is not actually defined in the promotion region.
Sentence 2: several of the Category Benchmark mirvcc -O2 mirvcc -O2 with function level promotion Reduction in Loads % Reduction in Stores % Reduction in Loads % Reduction in Stores % compress 18.9 12.8 36.6 14.2 gcc 1.3 -2.7 1.6 -5.5 go 1.3 -1.8 1.9 -5.2 ijpeg 0.3 -0.4 0.3 -0.4 SPECint95 li 6.5 2.2 8.1 2.6 m88ksim 0.8 0.0 3.8 -0.2 perl 0.0 0.0 1.5 -0.1 vortex -1.7 -3.1 -1.1 -5.8 ammp 4.6 -0.1 4.7 -0.1 art 13.6 12.2 13.6 12.2 SPECfp2000 equake 4.6 -0.1 4.7 -0.1 mesa 0.5 0.0 0.5 0.0 bzip 5.3 -0.4 7.3 -1.4 gcc 2.0 -2.5 2.3 -5.0 gzip 24.2 12.2 31.4 18.1 SPECint2000 mcf 6.8 1.2 6.9 1.2 parser 14.0 -0.5 16.9 0.5 vortex -1.7 -3.1 -1.1 -5.8 vpr 7.8 -4.4 13.2 -6.3 Table 4.
Relationship: reasoning
Domain: Hardware
Sentence 1: We next derive the optimal values of parameters (TT H ,Sj ) for an oracle-based power management policy.
Sentence 2: total energy dissipation of the PMC if it is transitioned to a low-power state S j, during an idle time duration Tidle (> Tt r,S j ) consists of energy dissipation during transition and energy dissipation in the low power state S j, i.e.,: E[P¯,Sj,Tidle ] = Pt r,Sj Tt r,Sj + PS j (Tidle - Tt r,Sj ) = (Pt r,Sj - PSj )Tt r,S j + PS j Tidle (1) for each state Sj, E is a non-decreasing function of Tidle .
Relationship: reasoning
Domain: Hardware
Sentence 1: Then, nodes which have di.erent values in MAs(nt = sa0) and MAs(nt = sa1), and are not in the transitive fanout cone of nt are the substitute nodes.
Sentence 2: only two logic implications are required to identify the substitute nodes for nt : one is for the stuck-at 0 fault test on nt and the other one is for the stuck-at 1 fault test on nt .
Relationship: reasoning
Domain: Hardware
Sentence 1: ,, , -         - Fig.4.2x2-JoinUsage:SingleFuntion.Fig.5.2x2-JoinUsage:MultipleFuntions.
Sentence 2: toa2-ANDjXORell.anylogiiruiton­sistingofonly2-inputnodesanbemappedtoair­uitonsistingofonly2-ANDjXORells.Thus,ourlogi synthesisstartswithairuitonsistingofonly2-input nodes.Thisinitialiruitanbegeneratedbyonven­tionallogidesigntools,suhasSIS(ASystemforSe­quentialCiruitSynthesis)[13].Forexample,byusing astandardsriptofSIS,weanobtainairuitonsist­ingof2-inputANDs,2-inputXORs,andNOTs.Then, weanmapthisiruitnaturallyintooneonsistingof 2-ANDjXORells.Notethatfouroffveoutputsofeah 2-ANDjXORellisnotused(i.e.,redundant)atthismo­ment,however,theredundantoutputsareveryusefulin ouroptimizationproedurementionedinthenextsetion.
Relationship: reasoning
Domain: Hardware
Sentence 1: In general, ECC correction and generation logic consists of trees of exclusive-or gates [20] which have delay on the same order as the 32-bit comparison for squashing.
Sentence 2: fSSS for sub-ECC-word stores can be implemented in an ECC-protected L1 data cache for simply the cost of a few extra gates which should not increase the ECC logic s critical path.
Relationship: reasoning
Domain: Hardware
Sentence 1: sp) (5) p s A collision set COL(P1, s1, P2, ss) is called collision-free, if and only if COL(P1, s1, P2, s) =Ø holds.
Sentence 2: processes P1 and P2 s can share global resources in states s1 and s, if COL(P1, s1, P2, s) ss is collision-free.
Relationship: reasoning
Domain: Hardware
Sentence 1: As the total i boundary tiles from the seed (x-coordinate) and the total j boundary tiles from the seed (y-coordinate) are required, then the following computational steps must be performed for assessing a tile at (i, j): (1) Calculate i×jtimes the F() function, (2) Calculate i×(j-1) times the N() function, (3) Calculate (i - 1) × j times the W() function.
Sentence 2: for aggregation of a tile to an empty site, all tiles between that site and the seed should be aggregated .rst, i.e.
Relationship: reasoning
Domain: Hardware
Sentence 1: The rate equations of RCAT now become: y1a = µ1/3= x1/3,y1b = x12/3,y1c = x2/3 and x1 = .1 = y1, where y1 = y1a + y1b + y1c, x12 = y12 and x2 = y2.
Sentence 2: (x1 + x12 + x2)/3= x1 = x12 = x2 and so the condition for product-form in Proposition 1 becomes x1 = x12 = x2 = y1 = y12 = y2 = µ1µ2/µ12 The condition can therefore be satis.ed, giving the uncon­ditional product-form p(n1,n2,n3,n4,n5) .
Relationship: reasoning
Domain: Hardware
Sentence 1: Moreover, level shifters need to be inserted at the boundaries between low-Vdd and high-Vdd, caus­ing extra area, delay and power penalty.
Sentence 2: it is desired that cells of different supply voltages are grouped into a small number of voltage islands (each having a single Vdd), so that the increase of design cost and the demand for level shifters are limited.
Relationship: reasoning
Domain: Hardware
Sentence 1: The constraints of (11) in logical effort notion are similar tothose in [2], i.e., the delay constraint can be expressed as, n Delay (p + h ) = T 16 = .i=1 0 i while the input capacitance constraint can be written as, n C1 = CL / .
Sentence 2: hi = Cmax 17 i=1 problem (11) is a minimization of a posynomial function with posynomial inequality constraints that can be easilysolved in polynomial time [11].
Relationship: reasoning
Domain: Hardware
Sentence 1: Indeed, a subsequent search for a fourth signi.cant parameter for these benchmarks further increasesef.ciencybya modest8to10 percent, putting ef.ciencybetween 39.4 and 71.7 percent of poten­tial.
Sentence 2: we expect much more comprehensive spatial adaptivity is required to close thegap for these benchmarks, drawing on in­cremental ef.ciencyimprovements from additional parameters as well as synergies between these parameters.
Relationship: reasoning
Domain: Hardware
Sentence 1: Circuit LUTs FFs  alu4 500 0 apex4 1,078 0 cps 524 0 dalu 323 0 ex1010 1,112 0 ex5p 557 0 misex3 257 0 pdc 609 0 seq 1,193 0 spla 229 0 industry1 1,511 2,128 industry2 1,654 1,278 industry3 2,818 368 industry4 2,942 1,262 industry5 8,676 5,507 industry6 4,895 318 circuit s primary input signals, the static probabilities of the circuit s internal signals can be computed using well-known probabilistic techniques [27].
Sentence 2: simulation is not a re­quirement for the use of our optimization approach and we expect that the approach could be incorporated into EDA tools that automatically perform the proposed leakage opti­mization.
Relationship: reasoning
Domain: Hardware
Sentence 1: 4.2 Arch2: FPGA using lithographic wires and molecular switches Arch1 described in the previous subsection needs decoders for addressing the nano-wires, which increases the complex­ity of the fabrication process.
Sentence 2: we also explore an FPGA, which uses conventional lithographic metal wires as the interconnect, with molecular switches at their cross­points (as in the previous architecture).
Relationship: reasoning
Domain: Hardware
Sentence 1: Continuing this process, we will .nally obtain a Primitive Saturated Global Routing (PSGR) GR0.Any detailed routing of GR0 will induce a detailed routing of GRby simply deleting the edges representing the nets of size two in GR0 which are obtained by combining the unequal singletons in GR.
Sentence 2: in the designing of SBs, we need only consider PSGRs and kPMSGR (k-way primitive MSGR).
Relationship: reasoning
Domain: Hardware
Sentence 1: Case 2: Now suppose A has at least two cubes and A and B have a common factor.
Sentence 2: let A=(X1 +X2 +···+ Xa)(Y1 + Y2 + ...Yb)and B =(X1 + X2 + ··· + Xa)(Z1 + Z2 + ...Zc).
Relationship: reasoning
Domain: Hardware
Sentence 1: 3.3.3 Identifying a session end HPMM cannot distinguish between a long network out- age and the end of a transmission just on base of observing multicast traffic, since it has no knowledge of when a multi- cast session ends.
Sentence 2: when a previously monitored group exists in routing tables (or with current IGMP sub- scriptions) but without recent traffic, a fault report is sent, and then afterwards only every few minutes unless packets begin flowing again.
Relationship: reasoning
Domain: Hardware
Sentence 1: Given the limited number of pins available in a probe setup, the original 4 bit output has been multi­plexed on two pins so that the LSBs and the MSBs are se­lected at di.erent clock phases.
Sentence 2: sampling speed in the acquisition system has been doubled since sampling  Figure 3: Chip microphotograph (The ADC core without cali­bration registers is 420×50 µm2).
Relationship: reasoning
Domain: Hardware
Sentence 1: For each pair 88 h (f)=Avh (1) + p i=1 1 h-12 88 h (i+1) -h (i)AvAvAva,b.S, s ' [a]= s ' [b].
Sentence 2: jmax j=i-:+1 p  p :-1 i=1 i ' ' max +1) =|S| :(j) - N:(j =1+ NN:(j) 1 - .
Relationship: reasoning
Domain: Hardware
Sentence 1: It is important to emphasize: it is not surprising that limiting power consumption also conserves en­ergy; what is surprising is that power consumption can be limited with small enough performance degradation over a wide parameter space to make it better than techniques explicitly designed to con­serve energy without excessive performance degradation.
Sentence 2: a major advantage of using our power-limiting approach is that we can limit power consumption and conserve substantial energy at the same time.
Relationship: reasoning
Domain: Hardware
Sentence 1: DATA RETENTION VOLTAGE Despite maximizing static power savings, lowering the core-cell array supply voltage too far, in DS mode, may result in data retention faults (DRFs) [8].
Sentence 2: a question remains on the lower bound of the voltage level at VDD_CC, in DS mode, that still ensures data retention in all core-cells of the array, which is referred to as data retention voltage in DS mode (DRVDS).
Relationship: reasoning