sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: B. Kahng and Q. Wang, Implementation and Extensibility of an Analytic Placer, IEEE Transactions on Computer-Aided Design 24(5) (2005), pp.
Sentence 2: in our imple­mentation, we use r0 to choose long nets for more accurate minimization, and we decide the value of r0 according the grid spacing Wg.
Relationship: neutral
Domain: Hardware
Sentence 1: General Terms Algorithms, management, measurement, performance, design, experimentation, languages  Keywords Cache architecture, prefetching, garbage collection, mark-sweep, prefetch-on-grey, buffered prefetch, depth-.rst, breadth-.rst 1.
Sentence 2: in stark contrast, BP-4 (second and fourth bars) shows noticeable mean speedup for both GC-intensive benchmarks and overall, with marginal speedup for FSD 3 (1.57% GC-intensive and 1.17% overall) but signi.cant speedup at FSD 10 (6.25% GC­ intensive and 4.47% overall).
Relationship: neutral
Domain: Hardware
Sentence 1: Approach Multi Cycle Write No Half Success V = 500mV  Figure 16.
Sentence 2: with VSUPPLY = 500mV, VWWL_HIGH = 500mV, and VWWL_LOW = 390mV, the operating frequency with no failures is 64MHz and the average and maximum number of write cycles for the array is 2.25 and 3, respectively.
Relationship: neutral
Domain: Hardware
Sentence 1: However, as for the net G13, although insertion dSFF on the net G12 can improve its transition probability, the transition probability of the net G9 become smaller than TPth.
Sentence 2: in fact, when the number of the insertion points is small, the flip-flops can be removed and only one 2-to-1 MUX is inserted for a selected net.
Relationship: neutral
Domain: Hardware
Sentence 1: In the ith sub-adder, errors occur when (1) the LSB part of the result (SUMi[k - 1: 0]) has all 1 values (probability P = 21 k ) and (2) the LSB part ([k - 1:0])ofthe (i +1)th sub-adder produces a carry bit (prob­ 1 11 111 ability P = + · + · · + ...).
Sentence 2: we have tested our approximate adder on a real application a Gaussian smoothing .lter used in [6].
Relationship: neutral
Domain: Hardware
Sentence 1: IMPACT OF PROCESS VARIATION IN CACHES 2.1 Cache Leakage Power Microprocessor performance has been improved by increasing the capacity of on-chip caches.
Sentence 2: furthermore, we show that compared to a conventional design, an adaptive cache architecture resilient to process variations can even achieve an improvement on application performance in conjunction with a 6X lower leakage despite the effects of process variation.
Relationship: neutral
Domain: Hardware
Sentence 1: Note that in the case that a droplet stays at its original location, cell (x,y)does not necessarily need to be activated and all the neighboring cells of (x,y) must be deactivated, as demonstrated in [3].
Sentence 2: note that both rule #1 and #2 state that the cells diagonally we do not need to explicitly handle the dynamic .u-adjacent to cell (x,y) cannot be activated at time t+1.
Relationship: neutral
Domain: Hardware
Sentence 1: Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors* Karin Strauss Xiaowei Shen Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu  Abstract Snoopy cache coherence can be implemented in any physical network topology by embedding a logical unidirectional ring in the network.
Sentence 2: these algorithms require re­quests to use the ring, which limits performance.
Relationship: neutral
Domain: Hardware
Sentence 1: Write time (ns) of proposed TCAM cell vs supply voltage at 32nm technology As for the search time, the simulation results in Table 1 show that the search time at 32nm is less than at 45 and 65nm; however at the same scaling, the simulation results show that the search time is slower at a higher supply voltage.
Sentence 2: as mentioned previously, during the search operation, if the TCAM cell is in state 0 or 2 , VX will increase from 0V to VDD at a rate dependent on the memristance range.
Relationship: neutral
Domain: Hardware
Sentence 1: Experimental results demonstrate the effectiveness of our method, and confirm that existing noise analysis approaches based on linear superposition of the propagated and crosstalk-injected noise can be highly inaccurate, thus impairing the sign-off functional verification phase.
Sentence 2: the noise injected on a victim net by adjacent aggressor nets through coupling capacitances is typically computed with network Model Order Reduction (MOR) techniques [3][5], or analytical macromodels that capture the relevant physical parameters of the noise waveform [6], and by assuming a linear model of both the aggressor and the victim driver cells (the Thevenin-equivalent circuit for the aggressor drivers, and the holding resistance for the victim driver).
Relationship: neutral
Domain: Hardware
Sentence 1: Impact of interconnect variations on termediate, s =3w) the clock skew of a gigahertz microprocessor.
Sentence 2: if we focus on the worst-case delay of a stage that consists of a driving gate loaded with interconnects and fan-out gates, it is necessary to consider not only interconnect variations but also transistor varia­tions at the same time.
Relationship: neutral
Domain: Hardware
Sentence 1: Each FSM is mapped to an RTOS task that performs state dependent processing, for example, measurement control, physical channel configuration etc.
Sentence 2: also timing F g r e3 SW ar c h t ec t r e  The L1 SW performs tasks like idle mode and power save operation, measurement and data channel control, tracking and synchronization control, protocol data processing through the protocol stack API and configure appropriate registers in the HW.
Relationship: neutral
Domain: Hardware
Sentence 1: This is ap­parent because the three schemes all add more tag ways as shown in Figure 6.
Sentence 2: iNTRODUCTION The embedded/portable computing systems are becoming more powerful to increase performance and to run a variety of programs; typical processors used in smartphones, tablet PCs, and smart TVs employ dual-issue superscalar proces­sors and L2 caches as shown in Table 1.
Relationship: neutral
Domain: Hardware
Sentence 1: The scattering characteristics of a cylindrical shell with a hemi-spherical cap on one end are calculated by BEM and Finite Element Method considering the coupling effect between the elastic shells and the interior filler [2].
Sentence 2: figures 2, 3, 4 display the receiving directivities of each channel of the sensors at different frequencies when the sensors are installed forward, laterally and vertically.
Relationship: neutral
Domain: Hardware
Sentence 1: In the case of (2,2) one cube C1 in one of the exact ex­pressions of g K must be equal to one cube C2 in one of the ' ' exact expressions of g L .
Sentence 2: the following theorem constrains the weight of a function g comprising three arbitrary cubes of (3) to w(g) = 3, under the stated assumptions.
Relationship: neutral
Domain: Hardware
Sentence 1: Once the values are latched, column-level commands, such as read (RD) and write (WR), are applied to the open (activated) row and the speci.ed address regions are accessed.
Sentence 2: cHARM or­ganizations with main-memory access frequency oblivious mapping (con.gurations with su.x O in Figure 11) result in smaller performance improvement than AR×N.
Relationship: neutral
Domain: Hardware
Sentence 1: (31) l LG-1CKCr l-1 5 CMmgu We notice that in the above procedure, G-1 l can be e.ciently computed using the LU of G while other ma­ trix computations are performed directly since the dimen­ |Y21|(1/ohm) 4 3 sions of involved matrices or vectors are small.
Sentence 2: for the full model with link insertions, two reduced order models are considered.
Relationship: neutral
Domain: Hardware
Sentence 1: (Re­call the discussion above, where a low base rate implies there are few attack packets exposed to the risk of being misclas­si.ed as F N .)
Sentence 2: for example, at one con.guration, T P = 0.8, F P = 0.1, while at another con.guration, T P = 0.9, F P = 0.2.
Relationship: neutral
Domain: Hardware
Sentence 1: We propose to partition the cache by allocating one parti­tion to each processor-set (processor partition), thereby en­couraging constructive sharing among threads of the same application and alleviating the impact of con.ict misses in the cache due to the impact of interactionsbetween memory references of di.erent applications in the cache.
Sentence 2: in a similar manner, Figure 5(b) plots results of varying the EnforcementInterval for cache partitioning of the same mix (Mix1) in the range of 1 Mil­lion -100 Million cycles.
Relationship: neutral
Domain: Hardware
Sentence 1: Also note that when the a a b b 9 9 (a) c (b) c Figure 6.
Sentence 2: oc t 8 Oc t 1  Qu ad 1 Quad 4 Oc t 2 Oc t 7 u Oc t 3 Oc t 6 Qu a d 3 Qu ad 2 Oc t 5  Oc t 4  Figure 2.
Relationship: neutral
Domain: Hardware
Sentence 1: 2when compared to a excitation only testfor a stuck-atfault 3NotethatORgate s side-inputis checkedfor valuesinbothcycles L1 #define legal (insn_input == add) || (insn_input == sub) L2 if ( legal&#38;&#38;(m==0)&#38;&#38;(p==0)) begin L3 wait(1);  n  n p x,1 p L4 if ( legal&#38;&#38;(m==1)&#38;&#38;(n==1)&#38;&#38;(p==0))begin 0,1  L5 ASSERT_FALSE; L6 end L7 end (a) (b) (c) Figure2:Illustrationoffunctional mapping.
Sentence 2: the synthesized OR1200 cpu core had nearly 16000 combinationalgates and approximately1600 sequential ele­ments.
Relationship: neutral
Domain: Hardware
Sentence 1: Since each switching block preserves the track assign­ment from the connection block where a 2-pin net comes from before it gets routed to another connection block, then we only need to impose exclusivity constraints once for each pair of 2­pin nets that belong to different multi-pin nets and that pass together through several connection blocks.
Sentence 2: in this representation, an ITE operator ITE(i, t, e) takes three arguments: a Boolean variable i, such that if i is true then the ITE selects the then-argument t and otherwise the else­argument e, where the then- and else-arguments are either ITE subtrees or domain values that appear as leaves of the tree.
Relationship: neutral
Domain: Hardware
Sentence 1: One important issue is that because of the recon.gu­ration penalty, multiple copies of a task may not be able to start at the same time therefore, individual execution time (workloads) of the multiple copies may vary.
Sentence 2: while it is possible to .t our applications onto suitably sized target devices, we assume for experimental purposes that the resource constraint is less than the aggregate size of all tasks.
Relationship: neutral
Domain: Hardware
Sentence 1: Eall = Ecache + Etable = Ectag + Ecdata + Ecoutput + Ecdecoding + Etdecoding + Etdata + Etoutput For highly associative caches, with the way mask design, the number of tags needed to be checked is dynamically decided by the mask.
Sentence 2: mangione-Smith, The Filter Cache: An Energy Ef.cient Memory Structure, MICRO, 1997.
Relationship: neutral
Domain: Hardware
Sentence 1: Tera­mac consists of 65,536 LUTs (Look Up Tables) distributed among 864 FPGAs and connected via crossbars in a fat­tree network [17].
Sentence 2: the conscious design decision to out-wire Rent s Rule (Teramac used Rent s Rule exponents of 2/3 to 1, as opposed to 1/2 to 2/3) allowed the system to function normally despite defects in 10% of logic cells and 10% of interchip interconnects.
Relationship: neutral
Domain: Hardware
Sentence 1: It means that most of the 16 4x4 modes were the same and choose only one 16x16 mode is better, since it will generate less modes information.
Sentence 2: the application of the proposed heuristic resulted in an average increase of 5.02% in the bit-rate and an average decrease of 0.255dB in the image quality (PSNR).
Relationship: neutral
Domain: Hardware
Sentence 1: The accuracy and precision varies from eye to eye like this because the eye tracker s pupil measure­ments depend on its estimate of the camera-pupil distance, which is a.ected by errors in the eye tracker s calibration to each eye s corneal shape.
Sentence 2: there were 84 dilations with du­ration less than 30 seconds with starting diameters and end­ing diameters that were both measured with the two instru­ments simultaneously.
Relationship: neutral
Domain: Hardware
Sentence 1: Aside from the internal active hardware metering that only exploits design modi.cations (sequential or combinational) for lock embedding [3], other methods of active metering based on inclusion of external cryptography circuits were introduced [10, 19, 18, 20].
Sentence 2: they may not be reproducible for average customers who may not have an access to the fuses without depackaging and invasively probing the chips.
Relationship: neutral
Domain: Hardware
Sentence 1: In contrast to these SOI-based optical NoC architectures, we propose a novel polymer-based optical ring bus (ORB) based opto-electric communication architecture that does not require the complexity of network interfaces and packet routers.
Sentence 2: it can be seen that the ORB architecture provides a performance speedup over traditional all­electrical bus-based communication architectures for UDSM technology nodes.
Relationship: neutral
Domain: Hardware
Sentence 1: n Suppose that the total amount of computation is L = i=1 ci and the amount of available slack is S = D - L. If the total WCET of the selected tasks is X,we have X = L and X = S. After reserving X amount of slack for recovery (in the form of re-execution), the remaining slack (S - X) couldbeusedto scale down the processing frequency for the selected tasks.
Sentence 2: for real-time embed­ded systems where reliability is as important as energy ef.ciency, reliability-cognizant energy management becomes a necessity.
Relationship: neutral
Domain: Hardware
Sentence 1: [9] A. Gordon-Ross, P. Viana, F. Vahid, W. Najjar, and E. Barros.
Sentence 2: n Cache hit[cj(b,n)] = L(b,d) (2) d=1 We can estimate the cache miss rate of a given cache con.gura­tion cj(b,n) for a sequence T by subtracting the result of Cache hit from the total size of the sequence of addresses |T |(Equation 3): |TT|-Cache hit[cj(b,n)] Miss rate[cj(b,n)] = (3) |TT| Any fully-associative cache con.guration cj(b,n) within the de­sign space de.ned by the boundaries 0 = b = bmax and 1 = d = dmax can be estimated by using the Locality Table L. just one single-pass simulation of the application (or trace T ) is neces­sary to generate the entire contents of L.  5.
Relationship: neutral
Domain: Hardware
Sentence 1: The performance of CCWS is sensitive to the size of the victim tags and the locality score cutoffs and is not as effective on the kernels that are not highly cache sensitive.
Sentence 2: when the SM frequency is reduced by 15%, the most affected kernels are compute kernels and they move signi.cantly into quadrant 4 losing performance while saving energy (Figure 1b.
Relationship: neutral
Domain: Hardware
Sentence 1: For example, if Cmin = 4, Cmax = 13, C1 = 6, CN = 10, and N = 26 di.eren­t voltage levels, the total time Ttotal = Tcalib + Tmeas = 29tcalib + W * 3tmeas.
Sentence 2: by controlling the select signals C[0], C[1], ..., C[K - 1], the delay of the entire line becomes recon.gurable.
Relationship: neutral
Domain: Hardware
Sentence 1: Experimentalresultsshowthatoursequenepairevalu­ationalgorithmisindeedveryfast-weaneasilyevaluate amillionsequenepairswithinoneminutefortypialinput sizeofplaementproblems.Comparedtothe(nlogn)al­gorithmin[16],weahieved7Xspeeduponaverageforall theMCNCbenhmarkplaementproblems.Wealsoom­paredFAST-SPwithblokplaementalgorithmsbasedon O-tree[12,13]andB*-tree[14]onMCNCbenhmarkprob­lems.
Sentence 2: ).Notethattheoordinatesofablokaretheoor­dinatesofthelower-leftorneroftheblok.ifw(i)= widthofbloki, S(X.VY)isthex-oordinateofblokb, .
Relationship: neutral
Domain: Hardware
Sentence 1: The power-gate controllers that send control signals to L1and L2 cache arrays in our technique impose a very small overhead in terms of the logical complexity involved: for L1cache arrays, eight states are needed in total to model the length of a Stall between warp scheduling stage and memory stage in both active.sleep and sleep.active procedures.
Sentence 2: university of South Florida Tampa, Fl.
Relationship: neutral
Domain: Hardware
Sentence 1: EDP T =(tturn on + tturn off ) × (Poff leak + Pon leak) m-1 × (Rblock - i × Rconcur) (3) i=1 where m = IRblock/Rconcurl.
Sentence 2: [13] M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi.
Relationship: neutral
Domain: Hardware
Sentence 1: There are two basic scheduling modes that SystemC Compiler can use to synthesize a behavioral model: Cycle-.xed: the timing of the description is strictly preserved, that is, all blocks of instructions between two witstatements are scheduled to be executed in a single clock cycle, if possible; Superstate-.xed: the scheduler can split sequences of instructions to be executed in a single clock cycle over many cycles; the I/O semantic is preserved.
Sentence 2: note that, while the unbalanced if can never be scheduled, what­ever the I/O scheduling mode chosen, this structure can be scheduled in superstate-.xed mode.
Relationship: neutral
Domain: Hardware
Sentence 1: Lower left corner is more preferable (HetJ: Heterojunction, HomJ: Homojunction, gnr: GrapheneNano-Ribbon, Bis: Bilayer pseudospin).
Sentence 2: state-of-the-art FinFETtechnologies continue to demonstrate superior performance thansteep slope devices in application domains demanding peak singlethreaded performance.
Relationship: neutral
Domain: Hardware
Sentence 1: The .rst sub-route connects the wash reservoir (WR)to S4,5, and the second sub-route con­nects S4,5 to the waste reservoir (WS).
Sentence 2: 3(a), instead of using two wash droplets W1,2 and W1,3 to clean two cross­contamination sites S1,2 and S1,3, we append one wash droplet to each of functional droplets D1, D2 and D3.
Relationship: neutral
Domain: Hardware
Sentence 1: There is a hyperpath between two RCs when there is at least one timing path connecting a register output in the origin RC to a register input in the destination RC.
Sentence 2: new models need to dynamically predict the next state of the system based on the software it is running and the environmental conditions it is placed in, and be aware of the non-determinism present due the phys­ical variations.
Relationship: neutral
Domain: Hardware
Sentence 1: TABLE I. PARAMETERS OF THE KEY CIRCUIT COMPONENTS Component Name Parameters M0 M1 M2 M3 RS Cg CS 3µm / 20µm 20µm / 1µm 0.5µm/15µm 0.5µm/15µm 400KO 10pf 1pf   Fig.
Sentence 2: when the proposed circuit is used in the WuRx architecture shown in Figure 1 (b), its driver circuit has to be modeled by a current source as shown in Figure 4 (b).
Relationship: neutral
Domain: Hardware
Sentence 1: Mult/Div, 4 FP ALU, 2 FP Mult/Div Branch predictor 2K-entry, combined, 3-cycle misprediction penalty Issue/Commit width 4 instructions per cycle Memory Hierarchy L1I cache 64KB, 64B blocks, 4-way, LRU, 1 cycle hit latency L1D cache 64KB, 64B blocks, 4-way, LRU, 1 cycle hit latency L2 unified cache 1MB, 128B blocks, 4-way, LRU, 10 cycles hit latency, 100 cycles miss penalty DTLB/ITLB 128 entries, fully set associative  3.2 Virtual execution environment Jikes RVM is a research Java virtual machine developed at IBM T. J. Watson Center [3].
Sentence 2: since idle units consume only 10% of their peak power, energy is less sensitive to pipeline stalls than execution time, resulting in the lower power dissipation during garbage collection.
Relationship: neutral
Domain: Hardware
Sentence 1: [3] P. Zimmerman, G. Nicholas, B. D. Jaeger, B. Kaczer, A. Stesmans, L. Ragnarsson, D. P. Brunco, F. E. Leys, M. Caymax, G. Winderickx, K. Opsomer, M. Meuris, and M. M. Heyns, High performance Ge pMOS devices using a Si-compatible process flow, IEDM Tech.
Sentence 2: (1,1) (0,1) (1,0) (0,0) Input Pattern (A,B) (b) Fig.
Relationship: neutral
Domain: Hardware
Sentence 1: Other challenge with LS design involves (a) tight area budget as the LS should fit within the array with minimum area overhead, (b) the LS transistors should be protected to avoid reliability degradation due to NBTI, PBTI and HCI [4] and (c) reducing the leakage of the LS to alleviate the burden from charge pump and save standby power.
Sentence 2: note that the leakage of the waked up LSs is higher than that of sleep mode LSs and therefore they will present extra load to the CP.
Relationship: neutral
Domain: Hardware
Sentence 1: Defnition6.BoundaryonstraintGivenablokb, itmustbeplaedononeofthefoursides:ontheleft,onthe right,atthebottomoratthetopofthefnalpaking.
Sentence 2: [3]M.SarrafzadehandC.K.Wong.AnIntrodutiontoVLSI PhysialDesign,MGrawHill,1996.
Relationship: neutral
Domain: Hardware
Sentence 1: Figure 1: Example of SoC .oorplan withWideIOTSV interfaces Networks-on-Chip (NoCs) have been proposed as a scalable in­terconnect for on-chip communication [5].
Sentence 2: having access to mul­tiple ports, requires the SoC to be able to ef.ciently use them to achieve the overall bandwidth requirement.
Relationship: neutral
Domain: Hardware
Sentence 1: RELATED WORK To the best of our knowledge, the coupling relation between scheduling and register allocation was not really addressed in the synthesis community, except in an exact non-scalable ILP formu­lation such as that of Wilson et al [33].
Sentence 2: 5C-2  Figure 9: Soft Scheduling Cycle Count Relative to List Scheduling With Chaining Enabled on Optimized PowerStone 6.
Relationship: neutral
Domain: Hardware
Sentence 1: This may be useful in reducing the average pressure on L2 links by restricting a signi.cant fraction of communication to be intra-group.
Sentence 2: [4] G. Faanes, A. Bataineh, D. Roweth, T. Court, E. Froese, B. Alverson, T. Johnson, J. Kopnick, M. Higgins, and J. Reinhard, Cray cascade: A scalable hpc system based on a dragon.y network, in High Per­formance Computing, Networking, Storage and Analysis (SC), 2012 International Conference for, Nov 2012.
Relationship: neutral
Domain: Hardware
Sentence 1: (v, u) ./E * } 3 l e t succ-T (r) b e t h e s u c c e s s o r o f r i n -T 4 c(8, succ * (8)) : = c I 5 r : = 8 6 w h i l e (succ-T (r) !
Sentence 2: a prefetch for the replaced item, denoted as ps3 , is inserted at the program point (r2, r1).
Relationship: neutral
Domain: Hardware
Sentence 1: Acomparisonwiththeexperimentalresultsfortheaver-agewirelengthsoneachlayer(Figure3)indeedrevealsthat thissimplemodeloverestimatestheviaimpact.However, themoreinterestingresultisthatthissimplemodelseems tointroducetheefectsofthewirelengthinamannercon­sistentwiththegeneraltrendoftheexperimentalresults.
Sentence 2: we then present a thorough analysis of the assumptions underlying these models; based on this analysis, we discuss requirements for predictors of routing resources within models of achievable routing.
Relationship: neutral
Domain: Hardware
Sentence 1: REFERENCES [1] Moshe (Maury) Bach, Mark Charney, Robert Cohn, Elena Demikhovsky, Tevi Devor, Kim Hazelwood, Aamer Jaleel, Chi-Keung Luk, Gail Lyons, Harish Patil, and Ady Tal.
Sentence 2: the network-trace approach fails to re­alistically evaluate application performance, because the timing of packet generation, which depends on on-chip network conditions, is assumed before the actual simulation of the network.
Relationship: neutral
Domain: Hardware
Sentence 1: More enhanced models are still being developed to ensure true broadband nature.
Sentence 2: () 2 x 2-(x 2 -1) 2-x J(x)=3(1- x )e - 10- xe 5 (17) -(x+2)2 - 3e +x If sparsity index SPindex of the .t is de.ned as Number of RV s SPindex = (18) Size of training sample then it turns out to be 0.04 with only 4 RVs.
Relationship: neutral
Domain: Hardware
Sentence 1: 4 (a), in the coarse-grained approach at least one nonlinear Newton iteration is performed at t4 af­ter the solution at t3 has fully converged.
Sentence 2: in Table 2, we list the runtimes and speedups (w.r.t serial BE) of six coarse-grained WavePipe schemes, which are 2­thread backward pipelining, 2-thread forward pipelining, 3­thread one-backward-one-forward pipelining, 3-thread two­forward pipelining, 4-thread two-forward-one-backward pipe­lining, and 4-thread three-forward pipelining, respectively.
Relationship: neutral