sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: We consider an o.ine attack scenario in which an attack­er can physically access the device that contains the AES cipher and the phase change memory array after the device has been used for encrypting data.
Sentence 2: the seasoning e.ect can be observed as well by an increase of the minimum programming voltage and on a modi.cation of the I aA¸SV characteristics of the PCM array as shown in .Figure 2(B).
Relationship: neutral
Domain: Hardware
Sentence 1: [8] T. Miyamori and K. Olukotun.
Sentence 2: considering that a typical DRAA has 8 * 8 PEs with 16 memory buses distributed over the PEs, MPEG kernel is a very large loop (127 PE-operations and 64 memory operations) and should be divided into several loops for ef.cient mapping anyway.
Relationship: neutral
Domain: Hardware
Sentence 1: In order to optimize peak temperature, it was necessary to tightly integrate .oorplanning, wire modeling, power pro.le gen­  [1] L.-T. Yeh and R. C. Chu, Thermal Management of Microelectronic Equipment: Heat Transfer Theory, Analysis Methods, and Design Practices.
Sentence 2: in order to determine the dct wang 73.6 70.7 68.2 68.5 102.0 101.3 97.5 108.1 0.81 0.70 0.68 0.68 68.7 59.8 59.1 60.1 101.2 109.8 116.0 108.0 0.64 0.42 0.43 0.42 66.3 57.6 57.9 58.1 0.58 0.39 0.40 0.39 thermal pro.le of our system, we integrated our original work, a 70.4 89.1 0.70 59.8 102.8 0.44 58.3 0.41 compact chip-package thermal model [13], into TAPHS.
Relationship: neutral
Domain: Hardware
Sentence 1: Definition 1: For any module x in L (i.e., x is a module with the left boundary constraint), x is said to have the Ib-property in a sequence-pair (GH,G L) if for each module y in B (i.e., y is a module with the bottom boundary constraint), the inequality pos(GH,y) pos(GH,x) holds.
Sentence 2: our algorithm was always able to generate placements of even better quality for 2 test cases (i.e., ami49 and random1), and of the same or comparable quality for 5 test cases (i.e., apte, xerox, hp, and ami33, random2).
Relationship: neutral
Domain: Hardware
Sentence 1: Considering just the workload sets where performance differences are most noticeable, ATLAS provides 16.4% higher instruction throughput than FR-FCFS, while PAR-BS increases it by 14.3% and our proposal outperforms FR-FCFS by approximately 17% on average.
Sentence 2: when we increase the critical distance, the aging process accelerates causing critical requests that reach the controller to compete with a greater number of requests already queued, thus also reducing the average waiting time in the queue, which consequently improves fairness.
Relationship: neutral
Domain: Hardware
Sentence 1: Kim,andW.Ye.Energy-drivenintegrated hardware-softwareoptimizationsusingSimplePower.
Sentence 2: wealsofoundthatusingacombinationofeightblockbufers andfoursub-banks,theenergyconsumedin4K(16K)data cachecouldbereducedonanaverageby88%(89%).Thus, suchhardwaretechniquescanreducetheenergyconsumed byprocessorswithon-chipcaches.ifweconsider theentirememorysystemincludingtheof-chipmemoryen­ergyconsumption,theenergysavingsfromthesetechniques amounttoonly4%(15%)whenusinga4K(16K)datacache.
Relationship: neutral
Domain: Hardware
Sentence 1: As such, every transis­tor on a charging/discharging path in.uences the gate-delay vari­ability.
Sentence 2: in a conventional worst-case timing analysis, the device characteristics are usually assumed to be uni­form within a chip, whereas in fact considerable intra-chip varia­tion may be present [1, 2], potentially degrading product yield[2, 3, 4].
Relationship: neutral
Domain: Hardware
Sentence 1: System Transformation for Time-Varying Coeffcients 1 T mn = the spatial domain of die, T (x, y, z, t) can be approximated by T (x, y, z, t) as T (x, y, z, t)= TT  T T (x, y, 0, 8)dxdy .x.y Since the generated bases are completely ortho-normal in n.ym.x NMy-1 NMx-1 ip(2m +1) lp(2n +1) cos , (19) = Kil cos2M2N l=0 i=0 N 1-My NMz-1 NMx-1 .ilq(t)filq(x, y, z), (14) where q=0 l=0 i=0 = where .ilq(t) is the time-varying coeffcient, Nx, Ny,and Nz Kil NMz-1 Cilq T Pil .Nilq (20) , are truncation points in x-, y-, and z-directions, respectively.
Sentence 2: the power density and temperature distribution of a 1cm×1cm chip with one million functional blocks.
Relationship: neutral
Domain: Hardware
Sentence 1: Based on visual feedback, we developed two post­processing techniques, peak congestion saturation and blending, which help to emulate the spreading of congestion and routing with a channel width constraint as well as the interaction of nets caused by long wires in the architecture.
Sentence 2: the results are plotted in Figure 17.  a = 3, N = 50 a = 4, N = 50 REAL Figure 16: Blending of CLBs that share common nets, using a peak saturation of 75%.
Relationship: neutral
Domain: Hardware
Sentence 1: For SFDM, as a result, the fixed value is very close to the middle value of 1 and 4.
Sentence 2: extendedComputeTree applies Breath-First Search (BFS) to traverse the CFSM and expands it into a tree structure, named ComputeTree or CT. Once a transition edge is traversed, it is copied and appended along with the tail node into CT, while cycle count is incremented by one and recorded on the tail node.
Relationship: neutral
Domain: Hardware
Sentence 1: Categories and Subject Descriptors B.8.2[Performance and Reliability]: Performance Anal­ysis andDesignAids;I.6.m[Simulation and Modeling]: Miscellaneous  General Terms Performance, Design, Algorithms 1.
Sentence 2: once we as- Benchmark sume an increased latency of only 1 cycle in order to re.ect this increased complexity, the picture changes.
Relationship: neutral
Domain: Hardware
Sentence 1: In every region Ri, we will .nd the point vj .V which has the shortest rectilinear distance (dv ' ivj ) from ' ' vi and the rectangular area covered by vi and vj has no obstacles. '
Sentence 2: yang, Ef.cient Obstacle-avoiding Rectilinear Steiner Tree Construction , Proceedings ISPD, 2007.
Relationship: neutral
Domain: Hardware
Sentence 1: By instructing the DAQ system to read the voltage on an input channel at regular time intervals, we determine how the voltage varies over time.
Sentence 2: our workload is comprised of the following activities: a human browsing web pages stored on the Itsy, (the web activity); a human playing a chess game against the Itsy Pocket Computer (the chess activity); and a human play- ing a chess game, then browsing a web page, then using a calculator, (the composite activity).
Relationship: neutral
Domain: Hardware
Sentence 1: In this work, we present a new fixed-point iteration algorithm that uses this "exact" representation of the model to compute an approxi- mation of the probability vector and of the desired measures.
Sentence 2: <il) (3) Raggr[i, j] represents the stationary rate at which the original CTMC goes from gi to gj given that it is in Ci.
Relationship: neutral
Domain: Hardware
Sentence 1: Instead of grouping the adjacent source lines, the source lines of same color property for adjacent two sub-pixels, namely R1-R2, G1-G2, and B1-B2 are grouped to form the charge groups.
Sentence 2: the charge-recycling method [1] and the charge-conversation method [2] can reduce the AC power by 50% for the case of the uniform color pattern(for a pixel, the color data of R, G, B sub-pixels are equal).
Relationship: neutral
Domain: Hardware
Sentence 1: Forthe test cases of r1 to r5, the wire length costs due to link insertion in our new algorithms (Link-RDand Link-MST) are reduced from around 7-8% to only 1.2% as the number of clock sinks increases from 267 to 3101.
Sentence 2: mST BASED LINK INSERTION ALGO-RITHM WITH RULE BASED DELETION The MST based node pair selection algorithm is an al­ternative graph theoretical approach to the min-matching based node pair selection algorithm proposed in [1].
Relationship: neutral
Domain: Hardware
Sentence 1: Ideally, we would like the computed label to be equal to the optimal mapping depth, that is, label(v)=label*(v) for every node v in the network, as in the case with the FlowMap algorithm for k-LUT mapping.
Sentence 2: on average, the total number of macrocells in the mapping solution may be reduced by a factor of 6% after the above packing process.
Relationship: neutral
Domain: Hardware
Sentence 1: In Section 2, we introduce the global routing problem, along with basic algorithms.
Sentence 2: as routers continue to push toward open-source platforms, it will become easier to plug-and-play with di.erent archi­tectural models (e.g., internal solution representations) with combinations of design decisions (e.g., choices in congestion functions, routing algorithms, and termination criteria).
Relationship: neutral
Domain: Hardware
Sentence 1: Although the NWC and narrow-width detection logic themselves consume power, the proposed mechanism reduces the power consumption in two ways: (a) the L2 cache is not accessed if a load request is a data hit in the NWC but is a miss in DL1, and (b) the NWC suppresses write-back on a write request if it is detected as a narrow-width silent store.
Sentence 2: we discuss related work in Section 6 and provide concluding remarks in Section 7.
Relationship: neutral
Domain: Hardware
Sentence 1: Since the feasible set is a polyhedron, the polyhedron de.ned by points A, B, C and D coincides with the feasible set exactly.
Sentence 2: if we solve the problem for parameters p1,p2,...,pk, any point in the convex hull de.ned by p1,p2,...,pk will be inside Fp, and thus corresponds to a solvable problem.
Relationship: neutral
Domain: Hardware
Sentence 1: Our proposed solution involves: -Acquire Signature from Camera or Scanner -Signature Preprocessing -Feature Extraction -Signature Classification 2.1 Signature Preprocessing Any image-processing application suffers from noise like touching line segments, isolated pixels and smeared images results in poor recognition and verification rate.
Sentence 2: various measurement have been calculated from the shape that are parameter, area, minimum enclosing rectangle, rectangularity measure, circularity measure and form factors.
Relationship: neutral
Domain: Hardware
Sentence 1: Notethisarrange­mentdictatesthattheprechargeandeval­uatecyclesbere­versedwithregardtotheclock.Thatis,clockbeinghighcor- VSS respondstoprechargeandclockgoinglow Figure 4: NMOS keeper.
Sentence 2: unintendeddropinthechargeatthedynamicnodeduringtheevaluationcycle.Thisinturncausestheoutputinvertertoturnonslightlywhichgreatlyincreasespowerconsump­tion.
Relationship: neutral
Domain: Hardware
Sentence 1: ACKNOWLEDGEMENTS This work supported, in part, by the National Science Foundation grants C-CR0306325 and CCF-0541150.
Sentence 2: [2] Ogras, U.Y., et al It's a Small World After All: NoC Performance Optimization via Long-Range Link Insertion, IEEE Transactions on VLSI, 14(7), 2006.
Relationship: neutral
Domain: Hardware
Sentence 1: Prefetchers based on dead-block prediction can mitigate the prob­lem caused by early prefetched lines displacing useful data in the cache.
Sentence 2: for instance, com­mon stride prefetchers [2, 4] and the predictor in [12] separate the stream of misses according to the PC of the missing memory ac­cess instruction, which we call PC localization and is an instance of execution context localization.
Relationship: neutral
Domain: Hardware
Sentence 1: [12] J. D. Ma and L. He, Formulae and application of interconnect estimation considering shield insertion and net ordering, in ICCAD, 2001.
Sentence 2: our table used in the paper con­tains 100 entries, with crosstalk voltage values from 0.10V to 0.20V, which is about 10% ~ 20% of the supply voltage Vdd (1.05V for the ITRS 0.10µm technology [9]).
Relationship: neutral
Domain: Hardware
Sentence 1: To evaluate different con.gurations that have been syn­thesized and listed in Table 2, we de.ned a cost function that takes into account the previous scenarios and considersthe consequences in terms of area and performance: costf = p1 · Tcnm + p2 · Tonm + p3 · Tm (5) The function costf(·) evaluates the different perfor­mance indexes with a corresponding probability for differ­ent cases.
Sentence 2: the time required for a matching operation is not constant; it can be linear in best casesbutexponentialinworst ones.
Relationship: neutral
Domain: Hardware
Sentence 1: The 6-bit LFSR is clocked every cycle and the output is shared by all 64 output function blocks (only one such block is shown on the left of Figure 3), so that all bit positions select a unique and different encoded majority function every cycle.
Sentence 2: the LFSR polynomial can be discovered in 2n cycles, where n is the order of the LFSR polynomial.
Relationship: neutral
Domain: Hardware
Sentence 1: 1, the output of the circuit due to second-order nonlinear behavior can be computed for any input excitation, provided that this excitation is not too large such that the assumption of weakly nonlinear behavior is not violated.
Sentence 2: as shown in Figure 3, second-order nonlineari­ties produce a third-order nonlinear response by combining at their controlling terminals a second-order signal with a first-order signal to produce a third-order nonlinear cur­rent.
Relationship: neutral
Domain: Hardware
Sentence 1: Wehaveprovedthata setupofsupervisedincrementaladap­tationappliedto MLLR-based models providesabetterper­formance for identi.cation tasks compared to a setup where adaptation is not used.
Sentence 2: the proposed approach is promising for authentication pur­poses, even when the amount of data available for training is limited.
Relationship: neutral
Domain: Hardware
Sentence 1: Alternatively, the performance of regular topologies can be significantly improved with minimal impact on area and energy consumption by adding application-specific long­range links [3] or radio frequency interconnections (RF-I) [4][5].
Sentence 2: in sum, the RG-MWFES algorithm has three innovations: (i) network reachability is guaranteed, (ii) edge weights and criticality are properly and efficiently updated, and (iii) the algorithm simultaneously considers both network power consumption (by minimizing the need for channel splitting) and performance (by maximizing application-specific frequently used communication paths).
Relationship: neutral
Domain: Hardware
Sentence 1: Our models generate energy estimates that are within 4.2% of those measured by de­ tailed power simulations, making the models valuable mechanisms Percentage of Cache Energy 25 20 15 10 5 0 Depth for rapid energy estimates during architecture exploration.
Sentence 2: our experiments with benchmark programs (Section 5.3) indicated a negligible dif­ference in modeling error of the energy estimates, by the incorpo­parameter, and we do not discuss the implications further.
Relationship: neutral
Domain: Hardware
Sentence 1: In SVT buffers, if the active devices are LVT and the off-state devices are HVT then we achieve the optimal trade-off between leakage and power since the LVT devices ensure shorter propagation delays while the HVT devices result in lower leakage power.
Sentence 2: figure 4 shows that for every application, the total power is reduced in the SVT bus case.
Relationship: neutral
Domain: Hardware
Sentence 1: 3 shows, with reference to a 4th order Butterworth filter, the diagrams of the cross-correlation function Rxy and of its partial derivatives with respect to Av,Q and fc.
Sentence 2: in the master circuit a time constant is adjusted by controlling one or more component values with a tuning control signal, which is then passed to the matched slave filter, whose frequency response is then properly adjusted in order to process the true input signal.
Relationship: neutral
Domain: Hardware
Sentence 1: Moreover, the means and standard deviations (µbk, sbk) of total background throughput in Scenarios 0 to 2 in Table 2 where we find out that HCLC does not much sacrifice other background traffics and preserves fairness to them.
Sentence 2: rEFERENCES [1] Chao-Lieh Chen, IEEE 802.11e EDCAQoS Provisioning with Dynamic Fuzzy Control andCross-Layer Interface, the 16th InternationalConference on ComputerCommunications and Networks,Honolulu,Hawaii USA, Aug. 13 -16,2007, pp.766-771.
Relationship: neutral
Domain: Hardware
Sentence 1: If the causes of routing issues can­not be determined or mitigated, the die size or number of routing planes might be increased leading to added cost.
Sentence 2: since the coordinates of all pins in a group are known, a bloat per unit area can be calculated to .nd bloat in speci.c regions, and help answer the question of whether bloat is mostly local or a pervasive global issue.
Relationship: neutral
Domain: Hardware
Sentence 1: When a new candidate path S is found, if the current path set has less than nnumber of paths, this new path will always be added into the path set with the possibility of creating a new bucket; if the current path set already has npaths, one and only one path (maybe this new path itself) that a.ects the last bucket s PCM the least will be discarded from the last bucket, and the last bucket may be removed if it thus becomes empty.
Sentence 2: the selected paths need to cover the entire process space.
Relationship: neutral
Domain: Hardware
Sentence 1: If the defective CRT-combination S =CRT(Sp,Sq)mod N is disclosed, the scheme is completelybroken as gcd(Se - m, N)= q.
Sentence 2: we make use of several hardware features employed on realistic smartcards to argue that the e.ects of such a precise intrusion are not completelypre­dictable for an adversary.
Relationship: neutral
Domain: Hardware
Sentence 1: If blocks with low reusability do not ex­istatthe bottomofLRU stacks ofpeer caches,itchecksif there are caches with a smaller memory demand and writes the evicted blocks to them.
Sentence 2: privateno decay Table 2: L2 Cache and Memory Energy Parameters Private L2 Dynamic read 0.11 nJ Dynamic write 0.01 nJ Cache Leakage power 1802 mW O.-Chip Dynamic read/write 2nJ Memory Standby Power 50 mW Table 3: Evaluated Schemes Privateno decay a cache decay policy is not used a cache sharing technique is not used RACSno decay a cache decay policy is not used a cache sharing technique is used considering reusability Privatedecay a cache decay policy is used a cache sharing technique is not used RACSdecay a cache decay policy is used a cache sharing technique is used considering reusability LACS a cache decay policy is used a cache sharing technique is used considering reusability &#38; leakage energy and RACSno decay are the schemes which do not use the cache decay technique.
Relationship: neutral
Domain: Hardware
Sentence 1: The BER perfor­mance of the NC-OFDM transceiver slightly improves relative to the 0% curve as power of nulled subcarrier can be redistribued to active subcarriers to improve sig­nal SNR.
Sentence 2: following the P/S conversion, the baseband MC-CDMA signal, s(n), is then passed through the transmitter RF chain, which ampli.es the signal and upconverts it to the desired cen­ter frequency.
Relationship: neutral
Domain: Hardware
Sentence 1: [12]J.ParkP.Diniz.Automatisynthesisofdatastorage andontrolstruturesforfpga-basedomputing engines.InFCCMOO,Napa,CA,April2000.
Sentence 2: mostoftheexeutiontimeofthePPIalgorithmisspentin omputingdot-produtsbetweenthepixelsandtheskewers.
Relationship: neutral
Domain: Hardware
Sentence 1: 1 914.945.4531; E-mail: chenjia@us.ibm.com ABSTRACT Carbon nanotubes (CNTs) are novel quasi-one-dimensional materials with excellent electrical properties in addition to their remarkable mechanical strength, thermal conductivity and chemical inertness.
Sentence 2: oxidizing and redox-active molecules are introduced to modify the work­function of the source and drain electrodes of CNTFETs and, correspondingly, of their SBs.
Relationship: neutral
Domain: Hardware
Sentence 1: There are several types of on chip bus proposals such as AMBA from ARM [3], PLB crossbar switch from IBM [4], Wishbone from Silicore [5], silicon backplane from Sonics Inc. [6] and so on.
Sentence 2: both AHB masters and slaves are fully compatible with AMBA AHB protocol [3] and modeled with VHDL at the behavioral level.
Relationship: neutral
Domain: Hardware
Sentence 1: It is possible to use a deterministic test generation procedure to gen­erate a test t ./ T det(f ) for f by constraining the test generation procedure to use only vectors out of V and avoid tests that are already in Tdet(f ).
Sentence 2: one may expect a decompresser that can apply an n -detection test set to be larger than one required for a conventional compacted one-detection test set.
Relationship: neutral
Domain: Hardware
Sentence 1: When a new algorithm is to be executed, the con.guration bit stream of this algorithm may give rise to logic which may .t in the set of free frames, speci.ed by the Free Frame 1 Frames are a prespeci.ed number of Logic Blocks and the relevant Switch Blocks of and FPGA List.
Sentence 2: a block diagram of the co­processor  2.2.
Relationship: neutral
Domain: Hardware
Sentence 1: We consider a set of n lists of tasks (T1,T2,..Tn) and a set of n lists of PEs (P1,P2,..Pn) All tasks in a list Ti must be allocated to one or more PEs in the corresponding list of PEs Pi..
Sentence 2: oD320 OD640 PAR 8x8 - 4 streams Pattern Recognition MPSoC OD320 OD640 OD320 OD640 PAR 16x16 - 4 streams PAR 8x8 - 8 streams OD320 OD640 PAR 16x16 - 8 streams [6] V. Suhendra, C. Raghavan and T. Mitra, Integrated scratchpad 30.00% Bidding-based Improvement memory optimization and task scheduling for MPSoC architectures , 25.00% in Proc.
Relationship: neutral
Domain: Hardware
Sentence 1: Furthermore, even though the graph is three-colorable, coloring a three-colorable graph with four colors is NP­complete [8], and thus three-coloring a three-colorable graph is also NP-complete.
Sentence 2: after the second and the third independent sets are constructed as illustrated in Figures 12(c) and (d), vg is left as a remaining vertex.
Relationship: neutral
Domain: Hardware
Sentence 1: Figure 1: .2(consistency) versus iteration.
Sentence 2: for the input .j , the total measured leakage (Imeas(.j )) can be written as: leak K Imeas k ..j leak (.j )+ E(.j )= Ileak(qjk) (1) k=1 where E(.j ) is the measurement error for the input .j , qjk is the input at the gate Gk after applying .j to the primary inputs, and Ileakk (qjk) is the leakage of gate Gk with qjk as its inputs.
Relationship: neutral
Domain: Hardware
Sentence 1: For the i'-th H0 cell (for i' = L +1, ...,Nu), the output of the correlator (with a code delay of t1,i' = t1,i' + d1)is given by t 1,i' +(j+1)Ts ys¯i' (j)=r(t)x1 (j)(t - t 1,i' )dt t 1,i' +jTs Ns-1 K M v = Pkak,l' Rw(lts + dk)+ nw (8) n=0 k=1 l'=-M Since we let Tc « Tw in our design, the collisions of di.erent users pulses occur in a more random pattern than the case of Tc Tw.
Sentence 2: using the noncoherent squared-law combining the DV for the ith CG (with i =1,..
Relationship: neutral
Domain: Hardware
Sentence 1: However in case of downstream contention these empty FLITS can be dropped.
Sentence 2: if we look at the latency per byte for these 1kB transfers we can see that they are 11 times more ef.cient than the smaller transfers generated by the Video core (1.1 ns/byte for HDMI and 12.2 ns/byte for the Video in UC4), which explains why the larger latency of the HDMI core does not impact the system performance.
Relationship: neutral
Domain: Hardware
Sentence 1: controller functions by comparing the reference input to the current water temperature(System Output)and based on the obtainedError value, the rates of the hot and cold .ows are modulated.
Sentence 2: in METE, to ensure the stability of the system, we .rst need to .nd the poles of each application controller and then determine the parameters of the controller in such a way that the poles are placed within the unit circle.
Relationship: neutral
Domain: Hardware
Sentence 1: In Figure 2(a), the word0 is 32-bit narrow-width value and the number of 0 sin the fault bits is 2 .
Sentence 2: in this paper, we assume that the L2 cache (LLC) is 8-way set­associative with 64-byte line size and the total capacity is 1MB (each layer has 256KB data array size).
Relationship: neutral