sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: , km-1) bits, contain­ing nonlinear terms, hence it may be an effective target to perform DFA, and in such a case to provide a lower bound on the computational capabilites needed to exploit it.
Sentence 2: the quick increase in the number of bits depending nonlinearly is to be as­cribed to the combined effect of the bitwise diffusion of DES into its S-boxes, while the large amount of instructions which are not vulner­able at the end of the cipher are to be ascribed to the .nal unkeyed permutation present in the DES design.
Relationship: neutral
Domain: Hardware
Sentence 1: For those works that have used ADBs in clock tree synthesis, their objective is to minimize statistical variation of clock skew under a single power mode domain, and as yet the problem of using ADBs for clock skew optimization in multi­ple power modes has not been intensively investigated.
Sentence 2: aDB2 should be retained and the delay value on ADB2 is set to a2 = LATv -LAT2 = 14 -7 = 7 by following Eq.
Relationship: neutral
Domain: Hardware
Sentence 1: Since G2 has a large fanout of 4, the duration of the discharge current is long (260 psec), while the duration of the discharge current in G1 is short due to the small fanout of 2 (120 psec).
Sentence 2: [2] S.Sirichotiyakul et al., Stand-by Power Minimization through Simulataneous Threshold Voltage Selection and Circuit Sizing, Proc.
Relationship: neutral
Domain: Hardware
Sentence 1: The only way in which DVATSC can impact performance is by increasing interconnection network congestion due to token exchanges, sending the physical address of a PTE along with the translation, and the periodic aggregation of signatures at a central verifier.
Sentence 2: a core that is requested to flush its TLB is unlikely to know which translations, if any, are actually being modified by the MRF that triggered the flush.
Relationship: neutral
Domain: Hardware
Sentence 1: Equation (23) implies that the projection charges are linearly proportional to the point charge, hence it easily follows that the projection charges for the charge distribution bj(Er) is t () .
Sentence 2: (22) In light of (19) and (20) we have (.¯g)t = .pf¯t (Ers)F-1 , (23) the projection charges for a point charge.
Relationship: neutral
Domain: Hardware
Sentence 1: Algorithm 1 Abortable inc&#38;read implementation Shared variables and initial values: Rj = -1 for j =1..n Code for process pi: procedure INC&#38;RE AD() 1: for j .1 to n do 2: countj .RE AD(Rj ) 3: if countj = .then return .
Sentence 2: processes that use objects of type TQA can ap­ply the original operations of T without padding them with unique ids (recall that this padding is required to use objects of type Tqa).
Relationship: neutral
Domain: Hardware
Sentence 1: To minimize the total sleep transis­tor area, smaller sleep transistors are used for the gates on non-critical paths, exploiting their timing slacks or in other words the maximum tolerable voltage drops.
Sentence 2: the following instance will reveal that the simple idea has little e.ect in reducing sleep transistor area for the DSTN connecting all clusters due to the interdependence of voltage drops.
Relationship: neutral
Domain: Hardware
Sentence 1: Direct Cache Access for High Bandwidth Network I/O Ram Huggahalli Ravi Iyer Scott Tetrick Intel Corporation Intel Corporation Intel Corporation ram.huggahalli@intel.com ravishankar.iyer@intel.com scott.tetrick@intel.com  Abstract Recent I/O technologies such as PCI-Express and 10Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms.
Sentence 2: the small percent of I/O write traffic can be sufficient to demonstrate visible performance gains for SPECWeb99 and TPC-W since it affects performance critical data read misses.
Relationship: neutral
Domain: Hardware
Sentence 1: Werefertothisaspatternfragmentation.Because ofpatternfragmentation,afourinstructionpattern mightavoidbeingdetectedwhenusingthefllunit.
Sentence 2: 3.InthepicoJava-IIwehavetocheckforpatterns andperformfoldingforasequenceofbytecodes, nomatterhowmanytimesitisexecuted.How­ever,usingthefllunitwereplacethepattern withthesynthesizedRISC-styleinstructionand storeitintheDB-Cacheline,andthenwecanis­suethesynthesizedinstructionwhenthepattern isrepeated(assumingwehaveaDB-Cachehit).
Relationship: neutral
Domain: Hardware
Sentence 1: Rather than taking a theoretical approach, in this paper, our approach is to consider a commonly used o.-the­shelf radio -CC2420, (considering the acceptance it has received in the community) and attempt to design MAC protocols that can provide 1ppm or less error probabilities within deadlines ranging in 5-50ms.
Sentence 2: fTDMA and FTDMA-B thus form the ends of a continuum in FTDMA-H with µack = 1 and µack = 0 respectively.
Relationship: neutral
Domain: Hardware
Sentence 1: Linear discriminant analysis (LDA) was used for dimensionality reduction and a classi.er using a linear decision function was able to discriminate the three classes with accuracies of 100% (low workload), 94.7% (me­dium workload), and 97.4% (high workload).
Sentence 2: this is an approach not suited for many real-world applications, as data is used for normalization which is not in general available to an online recognizer (at a given time data not yet recorded would have to be used for calculation of mean and standard deviation).
Relationship: neutral
Domain: Hardware
Sentence 1: Our survey alsoindicatesthat min­imizing authentication time is extremely important to many users,implying thatthe use ofPINs orbiometrics(whether on the card or on the reader) would also be on the obtrusive end of the usability spectrum and would hence violate our goal of maintaining a consistent usage model.
Sentence 2: in many cases it is su.cient to maintain an approximately consistent usage model.
Relationship: neutral
Domain: Hardware
Sentence 1: It can be veri.ed that the experimental probability of success of an endpoint receiving an RTP packet is within 15% of the analytical value obtained by modeling the system with a two­state Markov process.
Sentence 2: quality degradation is larger for a .xed awhen pvaries than when avaries for a .xed p. As expected the performance obtained by repetition FEC is better than that of XOR FEC specially for values of alarger than 5%.
Relationship: neutral
Domain: Hardware
Sentence 1: Another role of the wake-up radio is that based on network intelligence to select a specific harvester unit to be used at a given time in order to maximize efficiency.
Sentence 2: pOWER CONSUMPTION  Devices Consumption (3.3V) Active Sleep Wake up radio 300nW 300nW MCU SPU (1Mhz) 1.29mW 5uW  POWER CONSUMPTION.
Relationship: neutral
Domain: Hardware
Sentence 1: The first parent (P1) chromosome of the nodal string (this string is defined later in section II.B) is encoded based on the load factor a(oi) of each operation from the ASAP schedule.
Sentence 2: the GA based DSE initiates with a novel seeding process for parents as proposed in this paper which guarantees that the final solution will be optimal/near optimal.
Relationship: neutral
Domain: Hardware
Sentence 1: In the example shown in Figure 1(a), if l5 is scheduled to time 6 and l4 is schedule to time 7, leakage waste is completely eliminated, but the re­sulting placement is not feasible due to the single recon.gu­ration limitation.
Sentence 2: [19] P.-H. Yuh, C.-L. Yang, and Y.-W. Chang.
Relationship: neutral
Domain: Hardware
Sentence 1: [5] C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan, First-Order Incremental Block Based StatisticalTiming Analysis , Proc.
Sentence 2: (8) Equation (7) and (8) show that equation (6) is closed with respect to statistical operations, ADD and MAX.
Relationship: neutral
Domain: Hardware
Sentence 1: On the other word, is it possible to employ the EDC/ECC code to a data block larger than the data access granularity in L1-cache without requiring extra data accesses to check/update the EDC/ECC?
Sentence 2: to detect or correct SEMUs, it is necessary to use interleaved EDC/ECC or employ more powerful ECC codes, e.g., Double Error Correction-Triple Error Detection (DEC-TED), Single Nibble Correction-Double Nibble Detection (SNC-DND) and Reed-Solomon (RS) codes [4].
Relationship: neutral
Domain: Hardware
Sentence 1: When R is not high, equation (1) could approximately simplify as Dual-beam interference equation [9]: (3)   The Fourier transform of equation (3) is: (4)   Obviously, the pulse position is proportion to the cavity length as: (5)   Since different pulses correspond to different sensors, to measure each pulse shift can calibrate the strain of each HCPBF sensor immediately.
Sentence 2: to be confused with the interference of noise and cross talk, the original signal needs to be filtered and smoothed.
Relationship: neutral
Domain: Hardware
Sentence 1: While PMOS and NMOS devices show similar levels of mobility shifts, the threshold voltage reductions for PMOS are much lower than for NMOS.
Sentence 2: thus the leakage power of a gate under unequal changes in threshold voltages of n transistors of a gate can also be computed using a .rst order Taylor series expansion as: n Lstr t .Lgate str L0 =+ .V (12) i=1 .Vthi0 gate gate thi where Lstr is the leakage power of a gate under STI-induced stress gate and L0 is the nominal leakage power of the gate under no stress.
Relationship: neutral
Domain: Hardware
Sentence 1: The hold relationship is verified as follows: Data from source clock edge that follows the setup launch edge must not be latched by setup latch edge and data from the setup launch edge must not be latched by the destination clock edge that precedes the setup latch edge.
Sentence 2: in this description the launch edge is that clock pulse which releases new data from the source register, and the capture edge is it s counterpart one cycle later at the destination register.
Relationship: neutral
Domain: Hardware
Sentence 1: Faults in the address generation unit will be considered only when it is exercised; i.e., in load and store instructions.
Sentence 2: the bit min and bit max .elds indicate the amount of pruning per­formed by the known-outcome pruning techniques faults in the bits between bit min and bit max are pruned and their predicted outcome is recorded in the expected outcome .eld.
Relationship: neutral
Domain: Hardware
Sentence 1: To limit the growth of the new BAST, any con.icted PBS in the previous table has to distribute a maximum load to the PBS in the current table, while not violating the con.ict con­straints.
Sentence 2: a high communica­tion CG, or a CG with high number of cores will potentially increase the number and size of the newly produced BAST.
Relationship: neutral
Domain: Hardware
Sentence 1: Increasing geomet­rical complexity would imply using smaller primitives and even­tually would fall outside the validity domain of GA.
Sentence 2: right: Average MUSHRA scoresand95% con.denceintervalsasa functionofbudget.Notehowperceivedqualitydoesnotvarylinearlywiththe processingbudget and also varies depending on the type (i.e., sparseness) of the sounds.
Relationship: neutral
Domain: Hardware
Sentence 1: 1 Introduction On-chip cache memories are one of the most power hungry components of microprocessors.
Sentence 2: (1)N N P where .a, .a, .tag, .tag, and .are the energy N N P consumption per cache-way access, the number of ways accessed per second, the energy consumption per tag mem­ory access, the number of tags accessed per second, and the power consumption of the MAB, respectively.
Relationship: neutral
Domain: Hardware
Sentence 1: The early approaches (such as [6]) to providing buffers for the nets that require them was through the use of pre-planned buffer blocks fitted into channels and other dead space between design blocks.
Sentence 2: the utility of buffer blocks decreases as the detours required by nets in order to access these blocks become an increasingly large fraction of the desired inter-buffer separation itself, leading to significant performance degradation.
Relationship: neutral
Domain: Hardware
Sentence 1: When increasing the cache size from 64 bytes to 128 bytes, both algorithms move a bubblesort routine being on the initial WC-path onto the I-cache.
Sentence 2: the node weight wv represents the context-speci.c WCET of function v for a single execution of v.The edge weight we = w(x,y) denotes an upper bound of how many times execution .ow passes from x to y in a context.
Relationship: neutral
Domain: Hardware
Sentence 1: [24]M.Roncken.Defect-orientedtestabilityforasynchronous IC's.ProceedingsoftheIEEE,87(2):363.375,Feb.1999.
Sentence 2: fig.7showsthecurrentpeaksofboththesynchronous andtheasynchronous80C51at3.3V,wheretheasyn­chronousversionisrunningataspeedthatis2.5times higherthanthesynchronousone(thesynchronousone runsat10MHzandtheasynchronousoneataspeedcor­respondingto25MHz..Despitethefactthatthefgure doesnotgiveafairimpressionoftheaveragepowerbe­ingconsumed,itclearlyshowsthatthecurrentpeaksof theasynchronous80C51areaboutfvetimessmallerthan thoseofthesynchronousone.
Relationship: neutral
Domain: Hardware
Sentence 1: [Cl-min : Cl-max ], the larger the number of entries in the LUT, the more accurate the delay estimation [4].
Sentence 2: we demonstrate that the regression coe.cients ob­tained using bilinear and linear interpolation (for back-to­out and front-to-out arcs respectively) are constant over the entire characterization space, thereby enabling LUT-free static timing analysis.
Relationship: neutral
Domain: Hardware
Sentence 1: Two mechanisms can be identi.ed to change the power dissipation: .rst, the excess losses require a division into a larger number of seg­ments, which increases the total driven capacitance; and second, the edge rate degradation at the output of each segment will change receiving-buffer short-circuit and leakage currents for the worse.
Sentence 2: 1 is assumed to be large compared to the spacing s. the capacitance to ground will be neg­ligible compared to the coupling capacitance.
Relationship: neutral
Domain: Hardware
Sentence 1: Since the relationship between the switching time and the PMC size is not precisely known and for simplicity of analysis the switching time is made to be linearly dependent with the CF volume.
Sentence 2: [5] X. Guo, C. Schindler, S. Menzel, and R. Waser, Understanding the switching-off mechanism in Ag+ migration based resistively switching model systems, Appl.
Relationship: neutral
Domain: Hardware
Sentence 1: SurfaceFit(data[t]) end for (tmin, AMATmin) .
Sentence 2: in this scheme, L3 Cache 1×(6MB; 64 ways; 256B line; 20 cycles) Off-Chip Latency 200 cycles we partition only the L3 caches, and each L2 cache is shared by all cores that access it.
Relationship: neutral
Domain: Hardware
Sentence 1: ACM Transactions on Mathematical Software, 32(1):1 16, 2006.
Sentence 2: performance(GSample/s) E.ciency(MSample/joule)  CPU GPU MPPA FPGA CPU GPU MPPA FPGA Uniform 4.26 16.88 8.40 259.07 15.20 140.69 600.00 8635.73 Gaussian 0.89 12.90 0.86 12.10 3.17 107.52 61.48 403.20 Exponential 0.75 11.92 1.29 26.88 2.69 99.36 91.87 896.00 Geo Mean 1.42 13.75 2.10 43.84 5.07 114.55 150.21 1461.20   Relative Mean Performance Relative Mean E.ciency  CPU GPU MPPA FPGA CPU GPU MPPA FPGA  CPU 1.00 9.69 1.48 30.91 1.00 9.26 18.00 175.14 GPU 0.10 1.00 0.15 3.19 0.11 1.00 1.95 18.92 MPPA 0.67 6.54 1.00 20.85 0.06 0.51 1.00 9.73 FPGA 0.03 0.31 0.05 1.00 0.006 0.05 0.10 1.00 Table 6: Comparison of absolute performance and e.ciency of RNGs across platforms.
Relationship: neutral
Domain: Hardware
Sentence 1: We investigate a large set of GPGPU benchmarks, and find that on average, all SPs in a GPU core are idle during 35% of the total execution time, and the case that the SPs are partially idle appears in 11% of the execution time.
Sentence 2: the execution of a branch instruction in the warp may cause warp divergence, threads in a diverged warp have to execute in serial fashion which greatly degrades the performance.
Relationship: neutral
Domain: Hardware
Sentence 1: The difference (2.05ns) is quite signi.cant be­cause the longest wire (9.0mm) in 3D is much shorter than that (14.6mm) in 2D.
Sentence 2: power consumption of 3D ICs is ex­pected to be greater than 2D ICs in general unless few TSVs are used in 3D ICs or TSV capacitance is small (e.g.
Relationship: neutral
Domain: Hardware
Sentence 1: Since the number of retention registers exactly matches the total number of data values that should be alive at control step Cpg,the objective of operation scheduling is to .nd a schedule that mini­mizes the number of data values that are alive at control step Cpg.
Sentence 2: these group variables allow us to continue to use the ILP formu­lation in the previous section with only slight modi.cation.
Relationship: neutral
Domain: Hardware
Sentence 1: Traditionally, hardware reliability was only a concern for high-end systems (e.g., HP Tandem Nonstop and IBM eServer zSeries) for which applying high-cost redundancy solutions such as triple mod­ular redundancy (TMR) was acceptable.
Sentence 2: the I-cache port is busy for more than 50% of cycles for 3 benchmarks and is free only if the instruction fetch queue (IFQ) is full.
Relationship: neutral
Domain: Hardware
Sentence 1: (2)Fault transformation: The multiple fault f m is represented by a single stuck-at-1 fault fs on the fanout stem k. This pair of transformations is called MS (multiple-to­single) transformation, and a circuit model obtained by transforming a circuit C with a multiple fault f m is called MS-model (of C) based on f m .
Sentence 2: next, an MS-TEM Cms(S,FS) and its single fault set FCms(S,FS) were obtained from C(S) and FCm (S), and a test set for MS-TEM Cms(S,FS) was generated by using a single stuck-at fault combinational ATPG based on [5].
Relationship: neutral
Domain: Hardware
Sentence 1: Accelerating High-level Bounded Model Checking Malay K Ganai and Aarti Gupta {malay | agupta } at nec-labs dot com NEC Laboratories America, Princeton, NJ USA 08540 Abstract: SAT-based Bounded Model Checking (BMC) has been found promising in finding deep bugs in industry designs and scaling well with design sizes.
Sentence 2: references [1] A. Biere, A. Cimatti, E. M. Clark e, M. Fujita, and Y. Zhu, "Symbolic model checking using SAT procedures instead of BDDs," in Proceedings of the DAC, 1999.
Relationship: neutral
Domain: Hardware
Sentence 1: The main computation requires considerations such as choosing the variables to represent system state, whether and how to replay the computation, microarchitec­tural issues (pipelining), and environmental issues (input/output latency or stalling, or consistency and coordination with other modules).
Sentence 2: optimizations for performance or area are still possible, such pipelining or transferring checkpoints to main memory instead of dedicated registers.
Relationship: neutral
Domain: Hardware
Sentence 1: DESIGN DECISIONS While early OOO implementations had a central register update unit (RUU) for bookkeeping, most modern imple­mentations decentralize the information and have a sepa­rate reservation station, ROB, and register .le to improve throughput in the presence of speculation.
Sentence 2: at some point the ROB will be full and no new primary instructions will be issued.
Relationship: neutral
Domain: Hardware
Sentence 1: Assuming the maximum variability to be 3s, the Spec Violation Metric is defined as: 3s SVM =# SP (1) # SP where SVM is the Spec Violation Metric, #SP3s is the number of significant points in the 3s variability range, and #SP is the total number of significant points.
Sentence 2: a larger differential bit line voltage decreases the chances of an erroneous read.
Relationship: neutral
Domain: Hardware
Sentence 1: 5.Ifalltestshavebeenapplied,shiftoutallfaultefects fromthescanforest,endtheprocedure.Otherwise, gotostep3.
Sentence 2: fig.3presentsanexamplecircuitofthescanforest architecture.Thecircuitcontains3scanfip-fops.Every twoofthemdonothaveanycommonsuccessorinthe combinationalpartofthecircuit.allthreescan fip-fopsaredrivenbythesamescan-insignal.Outputsof thescanfip-fopsareconnectedwithanexclusive-ortree asshowninFig.3.Anytestvectorofthefullyscanned circuitcanbeappliedwithtwotestcycles.Fourtestcycles Figure4:Testcircuitofthescannedcircuitwiththe scanforestarchitecture.
Relationship: neutral
Domain: Hardware
Sentence 1: INTRODUCTION With high switching frequencies, fast signal transition time and low resistivity copper technology in modern VLSI designs, on-chip interconnects often exhibit transmission line behavior.
Sentence 2: is then extracted from the waveform as the signal slope at t=trin/2+tf, where tf is the time of flight, (LC)1/2 (here L Vouti  trouti Vdd Capacitive noise Aggressor current Ii Time trin/2+tf 0 Figure 2.
Relationship: neutral
Domain: Hardware
Sentence 1: As a result, even if the number of backtracking is O(m), the ML-OAPDRFST construction may still take O(mn log n) time in the worst case rather than O(m) time, and thus their whole algorithm would take at least quadratic time.
Sentence 2: more­over, since the last three steps of the algorithm are the same, we conclude the following by Theorem 4.
Relationship: neutral
Domain: Hardware
Sentence 1: As a result, the output transition region is very narrow, as seen in Fig 2.
Sentence 2: and Eshraghian, K., Principles of CMOS VLSI design: A system perspective, Addison-Wesley, 1992, 2nd edition [4] White, J.K., and Vincentelli, A.S., Relaxation techniques for the simulation of VLSI circuits, Kluwer, Norwell, 1987 [5] Sakurai, T., and Newton, A. R., A simple MOSFET model for circuit analysis, IEEE Trans.
Relationship: neutral
Domain: Hardware
Sentence 1: In an n-well process, widely used in current technology, all NMOS transistor bodies are connected to ground through the substrate, whereas the PMOS transistor bodies can be connected either directly to Vdd or to the virtual supply vsup.
Sentence 2: the drive current degradation due to the lower mobility of the node voltages in the circuit become close to Vdd or ground, including the virtual ground (vgnd) or virtual supply (vsup), in the case of PMOS or NMOS gating, respectively.
Relationship: neutral
Domain: Hardware
Sentence 1: Layer 4-7 switches can read application-level information in packet headers such as Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Sentence 2: each PE employs a di.erent TSL, which is optimized for a speci.c function.
Relationship: neutral
Domain: Hardware
Sentence 1: [18] performed a per-frequency and core CPU power characterization of two di.erent blade servers.
Sentence 2: nemesis is aDell Precision T3500 with an Intel Xeon W35304-core processor, 4 GB of RAM, 2 hard drives (a 2 TB Seagate Barracuda XT and a 3 TB Seagate Barracuda), a 1 Gigabit Ethernet card integrated in the motherboard, and a separate Ethernet card with two 1 Gigabit ports.
Relationship: neutral
Domain: Hardware
Sentence 1: Similarly, a minimum hyperplane is obtained via an element-wise minimum of the coe.cients and the o.sets.
Sentence 2: eXPERIMENTAL RESULTS The algorithm in section 4.3.4, along with the computations from section 4.3.3, have been implemented in C++.To solve the required linear programs, we used Mosek [10].
Relationship: neutral
Domain: Hardware
Sentence 1: loss 12.43 3.75 1.8 0.73 0.24 0.07 0.00 s38584 coverage 77.91 89.29 93.22 95.07 96.06 96.29 96.44 cov.
Sentence 2: different con.gu­rations of a space compactor may result in different percentages of responses being observable.
Relationship: neutral
Domain: Hardware
Sentence 1: REFERENCES [1] L. Aksoy, E. Costa, P. Flores, and J. Monteiro.
Sentence 2: {0, 1}.. (2) In (1), .... in w is an integer value associated with each of .. variables .... ,1 =.. =.., in the cost function, and in (2), A·x =b denotes a set of .. linear constraints where b .Z.. ×Z.. and A .Z.. .
Relationship: neutral