sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Extensively studied in [8] by TCAD simulations, such an approach demonstrates the ability to reach the same level of performances than FinFET LSTP transistors at 22-nm technology node for a slight area overhead of 8%.
Sentence 2: the circuit-level opportunities compensate the initial limitations, such as the increase of parasitic capacitances, found at the device level.
Relationship: reasoning
Domain: Hardware
Sentence 1: Asa voltageprogrammingpixel,thedriving transistor must supply a certain amount of currentdeterminedbytheOLED optical e.ciency, for a given gate voltage regardless of the OLEDbias.
Sentence 2: thedrivingtransistor of the2Tpixel showninFigure1isbiasedin a way thatit remainsin strong saturation for the entire range of the gray-scale OLED op­eration.
Relationship: reasoning
Domain: Hardware
Sentence 1: peak_current_Z1; We have the results that peak_current_Z1 = 2*c, S1,1 = 1, S1,2 = 0, S3,1 = 1 and S3,2 = 0.
Sentence 2: as a result, we have TC1 = d1, TC2 = d2, TC3 = d1, TC4 = d2, TC5 = d2, TC6 = d2 and the peak current is 4*c. the peak current is reduced from 6*c to 4*c. We further reduce the peak current by re-scheduling zone Z2 under TC1 = d1, TC2 = d2, TC3 = d1 and TC5 = d2.
Relationship: reasoning
Domain: Hardware
Sentence 1: In this context, we also uncover a new opportunity in reliability driven routing in an hNoC, by demonstrating that a substantial portion of the data packets routed in the network are non-critical (i.e., system performance is insensitive to their latency).
Sentence 2: utilization in centrally placed buffered routers can be reduced by minimizing non-critical packets routed through them.
Relationship: reasoning
Domain: Hardware
Sentence 1: For example, instead of being restricted to chip peripherals, I/O cells now can be placed anywhere on the die, and the placement of I/O cells also needs to consider the bump locations on the package in order to minimize the number of extra die layers for con­necting I/O cells to the bumps.
Sentence 2: the traditional timing-drivenI/O placement formulation [2,3,4,5] with­out considering package design issues is no longer applicable.
Relationship: reasoning
Domain: Hardware
Sentence 1: We estimatethespa­tiallocality of apageby averaging the number of words used in each fetched cache line for that page.
Sentence 2: we can es­timate the average tra.c for fetching a line from a page as follows: The costfor a coarse-grained access(64B) is73B:64B data, 8B ECC, and 1B for control.
Relationship: reasoning
Domain: Hardware
Sentence 1: This increase in delay is, however, quite small (and hence negligible) in the region to the left of the line that is marked by Z.
Sentence 2: from Figure 5(b) and (c), we conclude that for a given output load, we should use the minimum W0 value that does not result in a significant delay increase (i.e., move us to the right of line Z), which, in turn, may cause a required arrival time constraint violation.
Relationship: reasoning
Domain: Hardware
Sentence 1: It is desirable to distribute the total power P to maximize the minimum capacity of each hop channel.
Sentence 2: the optimum power allocation problem for a dual-hop MIMO relay channel can be formulated 1 .. 2 ..1 .. 2 .. C. max min CP ,CP (7) ... ... 2 ..1 .. PP ..1 .. where P .P2 .P.
Relationship: reasoning
Domain: Hardware
Sentence 1: (4) If we execute loop nest Lj on the embedded processor, all the dirty data that may be accessed by Lj must have been writ­ten back to the disk.
Sentence 2: we have the following con­straint: m (1-Hj)+Di,j Ji,k (Rk,j +Wk,j )=1, .i, j.
Relationship: reasoning
Domain: Hardware
Sentence 1: The optimized LTPS TFT system can have many other applications due to its better performance (compared to standard TFT) --low cost and ease to fabricate on flexible substrate.
Sentence 2: high performance and/or ultra low power electronics designed using the proposed TFT can be integrated together on the same substrate with display (say, System­On-Panel) opening up plethora of many new applications.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, the device placement problem in a biochip differs from the classical circle packing in the following two aspects: (i) The layout of a digital micro.uidic biochip consists of a discrete electrode array; hence the devices (which are represented by the centers of the corresponding circles needed to be packed) are constrained to lie on integer grid points, and (ii) for two devices da and db, the radius of the C(da,db) circle 2 , depends on the device pair.
Sentence 2: the de.nition of tangency of two circles should be modi.ed as follows.
Relationship: reasoning
Domain: Hardware
Sentence 1: An expression of the form {X}k means that message X is encrypted using the key k. Kerberos, as speci.ed in [7], is a full-featured protocol whose messages can have a size of several kilobytes, which poses a problem for sensor networks since radio communication drains the nodes battery.
Sentence 2: we conduct our energy evaluation with a lightweight version of the Kerberos protocol with short messages as summarized below (see [4] for details).
Relationship: reasoning
Domain: Hardware
Sentence 1: Here we describe in detail the characteristics of multi-level memristor operations: 2.1.1 Multi-level Memristor Reads As the number of bits being stored in a single memristor increases, the ADC must distinguish between more values, and the range of resistive values mapping to a single digital value decreases.
Sentence 2: more precise read operations require longer latency.
Relationship: reasoning
Domain: Hardware
Sentence 1: I where f(x) is the PDF for IREAD distributed normally with µ=µI and s=sI as above, and F(x) is the CDF of IREAD.
Sentence 2: p2, P3, and P4 are examples of the order statistics of IREAD and equal to I1k:1, I1k:2, and I1k:1k.
Relationship: reasoning
Domain: Hardware
Sentence 1: The .uctuations from the nominal value are consistent across the power grid, and it has been shown that frequency .uctuations measured at locations physically far apart but connected on the same power grid have a similar value [3] [10].
Sentence 2: the ENF signal recorded at any location in the network of the power grid can serve as a rep­resentative signal for the ENF in the area covered by the power grid.
Relationship: reasoning
Domain: Hardware
Sentence 1: Of course, the wire length of the net, as a conventional metric, also needs to be min­imized.
Sentence 2: the weighted sum lwp + alp is a good con + ßnsp cost metric to minimize when we route a single net, where lwp , lp con and nsp denote the wire length, the con.icting wire length and the number of stitches produced by the path p computed, respectively, and a and ß are user de.ned parameters that specify the relative importance between them.
Relationship: reasoning
Domain: Hardware
Sentence 1: Excessive power levels during test may: (1) cause struc­turaldamagetothesiliconorpackage,and(2) causea large voltagedropthat maylead toerroneousdatatransferin test mode, thus invalidating test and leading to yield loss [11].
Sentence 2: peak and averagepowerreduction methodologies targeting compression-based scan designs are of paramount importance, which has led to the development of numerous techniques in recent years [4, 5, 6, 7, 8, 15].
Relationship: reasoning
Domain: Hardware
Sentence 1: Error/Fault Recovery: The concurrent error detection scheme allows detecting errors induced by temporary faults affecting processing nodes, routers or links as soon as they occur.
Sentence 2: instruction replay (a mature technique already used in some commercial microprocessors like the IBM Power 6 processor [12]) or message retransmission for faults affecting links and routers, will be used to recover from temporary faults at low area, performance and power penalties.
Relationship: reasoning
Domain: Hardware
Sentence 1: (A4 xor B4) has 25% probability of evaluating to 1.
Sentence 2: the throughput of the variable-latency adder is on average 1/(0.75*4+0.25*8)=0.2 whereas the simple 6-bit ripple carry adder has the throughput of 1/(1*6)=0.167.
Relationship: reasoning
Domain: Hardware
Sentence 1: If there is no guard bits with the adder for storing the supplementary bits due to an over.ow then this constraint must be taken into account for determining the common binary-point po­sition.
Sentence 2: in order to avoid over.ow the common binary­point position mc is de.ned as follows mc =max (mx,my,mz) { mx' = mc (3) my' = mc  m' = m zc If there is guard bits with the adder, the word-length of the inputs and output are di.erent.
Relationship: reasoning
Domain: Hardware
Sentence 1: For example, a con­servative policy that always gives prefetch commands lower priority than regular commands may unnecessarily block prefetch commands behind regular commands that cannot issue due to con.icts in the memory system.
Sentence 2: rather than dictate a particular policy at design time, Adaptive Scheduling uses feedback to dynamically select from one of .ve policies in order of decreasing conservativeness: Only issue a command from the LPQ (1) if the CAQ is empty and the Reorder Queues are empty, (2) if the CAQ is empty and the Reorder queues have no issuable commands, (3) if the CAQ is empty, (4) if the CAQ has at most 1 entry and the LPQ is full, (5) if the .rst LPQ entry has an earlier times­tamp than the .rst CAQ entry.
Relationship: reasoning
Domain: Hardware
Sentence 1: Consider first the effect of a local event e for level k: Since e is independent of all other levels, we know that e , xe((~,ik,Z)) = ~ × x;(,k) × and the rate of e is W~[ik,jk] for each jk E 2d~(ik).
Sentence 2: for each state in C(p, ik), we know that event e is enabled, and leads to states in C(p, jk) for jk E X~(ik).
Relationship: reasoning
Domain: Hardware
Sentence 1: From the results presented in Table 2, we can conclude that our approach is particularly strong in the .ne locali­sation of the segment boundaries: we outperform Kaiser &#38; Peeters system for a tolerance of 0.5 s. However, increasing the tolerance to 3 s has a much larger bene.cial e.ect on their performance than on ours.
Sentence 2: their results for a tolerance of 3 s is signi.cantly better, especially the
Relationship: reasoning
Domain: Hardware
Sentence 1: Total delay of n-stage pipeline system is: ttotal-delay = tdcycle,1+tdcycle,2+· · · +tdcycle,N , where N= n or n+1 for n even or odd, respectively.
Sentence 2: total de­ 2 lay is: ttotal-delay = tcrit,1+tcrit,2+· · · +tcrit,n + n × tD-Q, where tcrit,i is the critical path delay in stage i.
Relationship: reasoning
Domain: Hardware
Sentence 1: In the following equations, M P I is misses per instruction, AP I is accesses per instruction, C P Ibase is the base CPI of the CPU, and C P Imemory is the CPI added due to miss penalties.
Sentence 2: m P I M P C = C P I M P A(p) * AP I M P C (p) = C P Ibase + C P Imemory M P A(p) * AP I M P C (p) = C P Ibase + M P A(p) * AP I * M issP enalty (3) Equation 3 determines MPC as a function of cache size with a given MPA curve.
Relationship: reasoning
Domain: Hardware
Sentence 1: wi i=1 p1 = and p0 = 1-p1 m Thus, the steady state probabilities of the states of the Markov source are set to be equal to the mean value of the bit probabilities of the tests in T. It should be noted that in computing the mean value the positions where all tests have Xs are ignored.
Sentence 2: the state transition probabilities, p01 and p10, of the Markov source are set to: .1 (1- wi)wi + 1 .1 wi(1- wi + 1) i=m-1 i=m-1 and p01= p10= (m -1) ·p 1(m -1) ·p 0 the method of [12] sets the transition probabilities of the Markov source after setting the values of the steady state probabilities.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since the functional units consume more values than theyproduce, there are fewer inputs to the crossbar than outputs from it, and thus the crossbar is not square.
Sentence 2: the cost to add an output port to the functional unit (or attaching another device to the crossbar) is signi.cantly more expensive than adding an input port, primarily due to the high number of capacitive loads within the crossbar.
Relationship: reasoning
Domain: Hardware
Sentence 1: This gate .ips the value of (n + 1)st qubit if and only if the control lines are all one (positive controls).
Sentence 2: action of the multiple-control Toffoli gate may be de.ned as follows: xi(out) = xi(i < n + 1), xn+1(out) = x1x2 · · · xn .
Relationship: reasoning
Domain: Hardware
Sentence 1: EFL re­lies on the fact that time-randomised (Evict-on-Miss) caches used in conjunction with PTA remove the dependence of ex­ecution time and WCET on the actual addresses accessed by the program.
Sentence 2: by controlling when each core is allowed to evict lines from the LLC and by appropriately producing LLC evictions at analysis time, EFL e.ectively obtains trust­worthy and tight WCET estimates.
Relationship: reasoning
Domain: Hardware
Sentence 1: fi+l, (3) or fi+x (1 - pl) (1 - q)T.ni = 1-- (1-- q)T'ni+x fi (4) for i = 0,...,I--2.
Sentence 2: given a set ofpi and Ri values, it is simple to calculate R using the recursion in (4) and equation (2).
Relationship: reasoning
Domain: Hardware
Sentence 1: Other mitigat­ing factors include the fact that the adaptivity logic is only activated on accesses to the L2 cache, and that the timing of the adaptivity logic is off the critical path of the L2 cache and therefore can be implemented with lower-power and/or less leaky transistors.
Sentence 2: overall, we consider it unlikely that power will be a concern, or even a net overhead.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, we can think of them as aborted operation executions that do not cause a state transition, and can order them arbitrarily among the critical path nodes, with the resulting sequence still conforming to type Ta initialized to s. By (2), nodes on the critical path are in timestamp order.
Sentence 2: if we order all nodes in the dependency forest by increasing times­tamp, the resulting sequence conforms to type Ta initialized to s. This sequence also satis.es the second requirement of a lineariza­tion, i.e., respecting the order of non-concurrent operation execu­tions.
Relationship: reasoning
Domain: Hardware
Sentence 1: The result classi.cations of theinjection experimentsin this work are basedonthefactthat only user-visible corruptions really matter.From an architecture perspective, this idea of failure may seem inaccurate, but it is consistent with recent symptom-based work and is the most appropriate in the context of evaluating our current work.
Sentence 2: the main motivation behind our solution is that the cost of ensuring reliability canbe reducedbyfocusing onhiding onlythefaultsthat arenoticeable bythe end user at run-time.the metric ofimportanceis not the number of faults that propagate into the microarchitectural state, butratherthepercentage offaultsthat actuallydo resultin user-visible failures.
Relationship: reasoning
Domain: Hardware
Sentence 1: First, RAID does not re­use the same RS check symbol intended for erasure correc­tion for error detection.
Sentence 2: it does not exploit the strong detection capability of RS check symbols (i.e., the ability of a single RS check symbol to guarantee detection of single-symbol errors and to provide high detection cover­age of double-symbol errors), as does Multi-ECC.
Relationship: reasoning
Domain: Hardware
Sentence 1: When o.-chip bandwidth is more constrained, as in our 8-core con.gura­tions,AGMSiseven morebene.cial andimportant:System throughput increases are 85% with ECC and 116% without ECC.
Sentence 2: we conclude that adapting access granularity willbe moree.ectiveinfuturesystems,whereo.-chipband­width is relatively scarce.
Relationship: reasoning
Domain: Hardware
Sentence 1: In theory, the chip-level oxide thickness mean is equal to the sample mean of all the sites, denoted as xN+n0 : 1 xN +n0 =(s0 × [1]n0 ×1 + uxu |s=s0 × [1]N×1 ) (16) N + n0 The deviation between xN +n0 and uchip is primarily due to the estimation error and may degrade the analysis e.ectiveness.
Sentence 2: we can perform a re.nement step iteratively to reduce the deviation to a negligible level, i.e.,tomake uchip xN+n0 by repeatedly replacing uchip in (13) with xN+n0 and then computing xN+n0 with (16).
Relationship: reasoning
Domain: Hardware
Sentence 1: While the power draw of a TCXO during temperature compensation is high, as Figure 3 illustrates, TCXO manufacturers recognize that temperature measurement and compensation can be done relatively infrequently since temperature is a relatively slow varying process in many environments.
Sentence 2: the duty­cycling of the temperature measurement circuitry dramati­callylowers theaveragepowerdrawof thesedevices,making their power draw viable for many sensor network applica­tions.
Relationship: reasoning
Domain: Hardware
Sentence 1: This is further divided into two cases: one is when all tasks have completed their execution in each of their periods and are waiting for their next arrival times while residing in the delay queue (L20) and the other when all tasks except the active task have completed their execution (L23).In the .rst case, we can bring the processor into a power-down mode because there are no tasks that need it.Furthermore, we know how long the processor will be idle because the task at the head of the delay queue is the .rst on that will require the processor (recall that the delay queue is ordered by the tasks release times).This is the key ingredient of LPFPS.
Sentence 2: we set a timer to expire at the next release time of the head of the delay queue and then put the processor into power-down mode.Because, there is a delay overhead to wake up from power-down mode, the timer actually should be set to expire earlier by that amount of delay (L21).
Relationship: reasoning
Domain: Hardware
Sentence 1: If we can achieve the condition that gate, drain and source of the transistors in the NMOS logic tree are all low as shown in Figure 3(b), there will be no gate leakage in the NMOS logic tree.
Sentence 2: for gate leakage suppression, inputs and outputs of every Domino stage in a Domino stage chain should be low in standby mode, while high Vt devices also need to be turned off to suppress subthreshold leakage.
Relationship: reasoning
Domain: Hardware
Sentence 1: For our proposed statistical regression, however, the moments E(f) and {E(f·.yn); n = 1,2,...,N} are related to the same performance function f(.Y).
Sentence 2: instead of considering the estimators {an~; n = 0,1,...,N} as independent operations, it is possible to identify the interaction between these estimators and utilize it to improve accuracy.
Relationship: reasoning
Domain: Hardware
Sentence 1: Al­though fault-tolerant methods have been studied for long time, most of the proposed solutions are targeted to deal with a single fault at a time, and the occurrence of multi­ple simultaneous faults may lead to silent error propagation.
Sentence 2: a fundamental challenge for nanoscale circuits is the improvement of the traditional methods and the develop­ment of new ones, allowing correct operation of the circuits in presence of multiple transient faults [8, 9].
Relationship: reasoning
Domain: Hardware
Sentence 1: In DAC12 contest, global routers BFG-R and NCTU-GR 2.0 are used to evaluate placement solutions.
Sentence 2: we use BFG-R and NCTU-GR 2.0 to get two global routing results G1 and G2 for each placement solution, and then compute congestion penalty PWC(GP) by averaging PWC(G1) and PWC(G2).
Relationship: reasoning
Domain: Hardware
Sentence 1: Actually, the oscillator phase noise L(.f) downconverts the nearby channels to baseband noise [8].
Sentence 2: in the worst case (strongest out-of-band signal and weakest in-band signal), the following condition applies, where B is the channel bandwith : 1 L(.fch ) = (9) B · DR with B = 200kHz, the phase noise at 500kHz from the carrier should not exceed -108dBc/Hz.
Relationship: reasoning
Domain: Hardware
Sentence 1: A particle strike occurring during the off-period of clock causes an SEU that .ips the output of the latch instantly and thus causes a soft error, which could affect the functionality of the block.
Sentence 2: the Window of SEU Vulnerability (WOUV) for a positive latch is the time period when the latch is storing a value, i.e., its off-period.
Relationship: reasoning
Domain: Hardware
Sentence 1: 5.1 Functional-Unit Rearrangement Since the energy of a set of functional units is dominated by the unit whose mapped voltage is the maximum (see De.nition 1), one heuristic is to avoid spreading high-voltage units into the clusters after partitioning.
Sentence 2: our approach is to .rst rearrange functional units into a non-decreasing order sorted by their mapped voltages.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since a versatile DMFB is requested to carry out a series of associated chemical and biological reactions, a set of automation algorithms, such as synthesis and routing [7] [12], are essential for speeding up the design process, reducing the manual effort, and improving the design quality.
Sentence 2: the design automation for DMFB has been becoming an emerging topic recently, and the related research works are proliferating.
Relationship: reasoning
Domain: Hardware
Sentence 1: Phase change memory (PCM) [7], [8], resistive RAM (RRAM) [9], [10] and spin transfer torque magnetic RAM (STT-MRAM) [11], [12] are three candidates in the emerging non-volatile memory (NVM) technologies.
Sentence 2: they are CMOS­compatible, and can be stacked on the top of the CMOS circuit­ s. the logic-in-memory applications that integrate the above memories in the logic circuits, as shown in Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: We assume that memory locations are assigned consecu­tive addresses, starting at 0, in level order.
Sentence 2: the level j(x) containing address x is uniquely determined by the 1 j(x)-11 relation s + ...+ s<x = s + ...+ sj(x).Letusnow de.ne a(x), the access time to location x,asthe worst-case duration of the interval from the time when a request tar­geted to location x is submitted to M to the time when the response to that request is inserted into MQ.
Relationship: reasoning
Domain: Hardware
Sentence 1: * For the sake of contradiction, we assume that an optimal r is not reached yet.
Sentence 2: by Lemma 3 and m(x0) = xk-1, we have r *(xk-1) - r(xk-1) = r *(x0) - r '(x0) after r(x0) is increased to r '(x0) due to any of (1)-(4).
Relationship: reasoning
Domain: Hardware
Sentence 1: Although NEMS devices have extremely low OFF current, a NEMSdevice does not offer as high ON current as CMOS transistors do.
Sentence 2: for the first time, we propose the idea of hybrid NEMS-CMOS technology where near zero-leakage characteristics of NEMS can be combined with high ON current of CMOS transistors to simultaneously achieve ultra low-power and high performance operation.
Relationship: reasoning
Domain: Hardware
Sentence 1: Illustration of Generalized Predictor Figure 7 shows the results of experiments performed us­ing our limit study infrastructure for piecewise linear branch predictors with a constant history length of h =63and varying n and m such that their product is always 65,536.
Sentence 2: the number of elements in the W array is kept at a constant 64× 65, 536= 4MB, but the .rst and second di- Percent Mispredicted mensions of the W array are varied to represent different points in the space of neural predictors.
Relationship: reasoning
Domain: Hardware
Sentence 1: With the nootion of end-user programmability being introduced to DMFFBs, control-flow constructs present exciting, new possibilities for microfluidic applications.
Sentence 2: when control-floww is introduced, synthesis (Figure 2) will need to be performedd online since the order of assays (biochemical reactions) to bee executed is no longer deterministic, but instead dependent on liive-feedback from the DMFB [2][13].
Relationship: reasoning