sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: In a broader context, it is hoped that the availability of a robust body-driven current mirror will pave the way for increased use of body-driven circuits for analog signal processing.
Sentence 2: below 5 µA the current mirror will become somewhat non-linear (large-signal); however, this condition will only occur when the amplifier is slewing, which is already a non-linear operating region.
Relationship: neutral
Domain: Hardware
Sentence 1: Thus for a given retiming, the number of registers on each wire is given by: wr,uv = wuv + r(u) - r(v) (1) This equation simply expresses that in addition to the origi­nal registers on euv, which is denoted by wuv, r(u) registers are moved onto the wire and r(v) registers are removed.
Sentence 2: doing so may introduce a glitch on the signal that feeds the asynchronous lines.
Relationship: neutral
Domain: Hardware
Sentence 1: Deadlocks in a NoC can be alleviated by introduction of additional vir­tual channels (or bu.ers) in the routers, and breaking the cycles [4].
Sentence 2: iP library constraints: The NoC router and network to core interface library places constraints in terms of sup­ported tra.c classes, bandwidth constraints on ports, and arity constraints on routers.
Relationship: neutral
Domain: Hardware
Sentence 1: There were inserted 128 stuck at one and 128 stuck at zero faults in a random single node (ranging from 0 to 7) at a random instant of the clock cycle in a 2x2 bit multiplier that could occur during the propagation or the observation time.
Sentence 2: because scrubbing does not interrupt the normal device operation, the original bitstream values cannot be loaded in the flip-flops and embedded memory structures, as these cells are constantly being updated by the application.
Relationship: neutral
Domain: Hardware
Sentence 1: We consider the topology depicted in Figure 1.
Sentence 2: this simpli.es p= K QT ( a) c .Given the form of B?i ~ 1 +2s2), inv, it can be found that pi.KN (|pi|2 K where pi is the i th component of p. The noise-only case is found by setting pi = 0 in the above.
Relationship: neutral
Domain: Hardware
Sentence 1: [11] N. Park, B. Hong, V. K. Prasanna, Tiling, block data layout, and memory hierarchy performance , in IEEE Transaction on Parallel and Distributed Systems, pp.640-654, vol.14, i.7, July 2003.
Sentence 2: a write request from processor on one addressing is simultaneously accompanied with an update request on its orthogonal addressing throughout all cache levels to maintain the cache coherence.
Relationship: neutral
Domain: Hardware
Sentence 1: A correct execution of the transformations can be guaranteed by embedding the whole derivation process into a theorem prover, as it is done in the formal synthesis approach: Circuits are speci.ed by means of terms and formulae within a theorem prover and they are only modi.ed by transformations, whose correctness has been proved in the theorem prover.
Sentence 2: in M. Lorenzetti, editor, Proceedings of the 31st Conference on Design Automation, pages 491 496.
Relationship: neutral
Domain: Hardware
Sentence 1: Subsequent pointer assignments update the reference list as the analysis pass continues for­ward through the CFG.
Sentence 2: as previously stated, for R-NUCA we only implement the features relevant to the comparison, namely the classi.cation of data as shared or private at the  / +LW 9LUWXDO $GGUHVV / +LW    7/% / 7/% 0LVV 0LVV 7/% +LW   3DJH 7DEOH Figure 11: Retrieving Owner Information During Address Translation page level.
Relationship: neutral
Domain: Hardware
Sentence 1: 3.2 Switching Power Reduction 3.2.1 Low Power Flip-flop Design In many VLSI chips, the power dissipation of the clocking system, including the clock distribution network and flip-flops, is often the largest portion of the total chip power consumption.
Sentence 2: to compensate for such performance degradation, low Vt is applied to the NMOS transistors in the critical path.
Relationship: neutral
Domain: Hardware
Sentence 1: However, the function unit of Scatter/Gather is located in a processor rather than on-chip network side.
Sentence 2: [5] N. Tanabe, Y. Ogawa, M. Takata, K. Joe : " Scaleable Sparse Matrix-Vector Multiplication with Functional Memory and GPUs", Euromicro PDP'2011 , pp.
Relationship: neutral
Domain: Hardware
Sentence 1: Ma [10] provides an algorithm to simplify the address generation of twiddle factors and reduce the number of twiddle factors to the minimum.
Sentence 2: [3] K. Tanno, T. Taketa, S. Horiguchi, Parallel FFT Algorithms Using Radix 4 Butterfly Computation on an Eight-Neighbor Processor Array , Parallel Computing, Vol.
Relationship: neutral
Domain: Hardware
Sentence 1: The tool could, then, gather this information over the execution of an application and attribute performance problems to certain instructions statistically.
Sentence 2: noticeably, six counters (fma, fpu0, fpu1, inst, ld, st) are highly correlated as Table 4 confirms with values greater than 0.99. fma fpu0 fpu1 inst ld st tlb.miss fma 1.0000000 0.9986839 0.9985139 0.9997846 0.9997262 0.9992478 0.3598753 fpu0 0.9986839 1.0000000 0.9946780 0.9987720 0.9987540 0.9984938 0.3576571 fpu1 0.9985139 0.9946780 1.0000000 0.9984684 0.9984306 0.9980825 0.3621886 inst 0.9997846 0.9987720 0.9984684 1.0000000 0.9999964 0.9998370 0.3612941 ld 0.9997262 0.9987540 0.9984306 0.9999964 1.0000000 0.9998803 0.3614241 st 0.9992478 0.9984938 0.9980825 0.9998370 0.9998803 1.0000000 0.3625394 tlb.miss 0.3598753 0.3576571 0.3621886 0.3612941 0.3614241 0.3625394 1.0000000  Table 4: Correlation matrix for UMT on 288 tasks with raw data from 7 counters.
Relationship: neutral
Domain: Hardware
Sentence 1: [7] I. M. Elfadel, A. Dounavis, H-M. Huang, M. S. Nakhla, H-M. Huang, A. E. Ruehli, and R. Achar.
Sentence 2: when grounded wires are placed in the middle of each power bay, the 12-line bus will have the ca­pacitance and impedance extraction structures shown in Fig­ure 3 (a) and (b), respectively (the C4 pads are not shown for lack of space).
Relationship: neutral
Domain: Hardware
Sentence 1: The design must foresee this situation through an adequate margin between the bias point and the maximum and minimum voltage which the MCAS and MCS transistors will operate in the saturation region and the differential switch pair operating in the triode region [4].
Sentence 2: a recommended margin in the literature is Sq( f ) > 10 · St ( f ), it is a resolution that loose an amount of 0.069 bits.
Relationship: neutral
Domain: Hardware
Sentence 1: [13]B.ZhouandT.Yoneday"Verifationofasynhronousir­uitswithboundeddelaymodely"(inJapanese)IEICEjournaly Vol.J82­D­IyNo.7ypp.819­833y1999.
Sentence 2: intuitively,asafetyfailureoursifaftertraexonemod­uleMksendsanoutputwattimeT,butsomeothermodule annotreeivetheorrespondinginput.Wedonotregard (w,T)asasafetyfailureofMifisnotatraeofM,orif aftertraesomemoduleMJofMmustadmitsomesymbol w .beforeT(i.e.,ifMannotwaittilltimeTafter):inthis ase,theevent(w .
Relationship: neutral
Domain: Hardware
Sentence 1: The total number of pins per package has however historically grown at a much lower rate, growing as the e th root of current over the last 30 years (Figure 8).
Sentence 2: (1) for example, a single JEDEC DDR3-2133 standard memory, having a bus clock of 1066 MHz DDR clock (double-data-rate fmem = 2133 MHz), and 64-bit transfers(Nmembits = 64), the peak available bandwidth is 17.06 GB/s.
Relationship: neutral
Domain: Hardware
Sentence 1: 4.2.5 ImplicationsonMulticoreProcessors Sofar ourdesign andevaluationhavefocused on a single-core sys­tem.Asdescribed inSection 3.1,T2ECinformation is exclusively accessed by a DRAM controller and not shared among multiple processor cores.
Sentence 2: if the T2EC is not in the cache, correction requires an additional DRAM access to fetch the redundant information.
Relationship: neutral
Domain: Hardware
Sentence 1: Theprob­lem is that the current XCXT algorithm does not work in such a scenario since it is based on the fact that both crys­tals have the same speed and thus time resolution (minus their drift, which we calculate in the algorithm).
Sentence 2: commer­cially available TCXOs with similar stability can cost over 10 times as much and consume over 20mW.
Relationship: neutral
Domain: Hardware
Sentence 1: The mean cosine similarity across all chord segments in the evaluation set is considered as a quality measure for the considered chroma extractor.
Sentence 2: similarly, the annotated chord label is con­verted to a 12-dimensional target chroma vector Vt consist­ing of ones and zeros indicating whether the corresponding 1http://labrosa.ee.columbia.edu/matlab/chroma-ansyn/ 2http://users.jyu../~lartillo/mirtoolbox/ chroma coincides with that of a note of the annotated chord.
Relationship: neutral
Domain: Hardware
Sentence 1: Statistic Default Hierarchical Direct Average 0.024 0.078 0.062 Median 0.062 0.069 0.047 Variance 0.00 0.002 0.001  menu that one of the student from WSP track got while calling to Direct.
Sentence 2: sub-options of same parent option) but not across the levels (i.e.
Relationship: neutral
Domain: Hardware
Sentence 1: In this case, the SR latch will incur all the penalties of an ETDFF implementation (opening the latches on the critical path) and, in fact, the latency of the SR latch is close to that of an ETDFF-based ASU (350 ps).
Sentence 2: self-resetting latches are controlled by two separate events: one for opening the latches to pass data items and one for closing them to store the data items.
Relationship: neutral
Domain: Hardware
Sentence 1: The second parameter, the transition bandwidth, is the range in which the signal at­tenuation varies from maximum to minimum.
Sentence 2: as in many other scenarios of computer and communication security, the existence of adversaries raises a serious concern regarding the security of the ENF-based time stamp and makes it crucial to understand and address possible vulnera­bilities in ENF analysis against anti-forensic actions.
Relationship: neutral
Domain: Hardware
Sentence 1: For the squashed threads, we clear their LMDT bits and invalidate their dirty and forwarded L1 lines.
Sentence 2: the acknowledgment from GMDT0 speci.es the new assignment of chunks to nodes or, possibly, that the assignment of chunks is as be­ 3Although the GMDT may temporarily keep some outdated Store bits set for the non-speculative chunk, correctness is still guaranteed: if a read from a successor is directed to the chip running the non-speculative chunk due to one of these outdated Store bits, the request will be bounced back to memory as if the requested line had just been displaced from the caches.
Relationship: neutral
Domain: Hardware
Sentence 1: the design requires a column of BRAMs that is as wide as one less than the number of write ports, to provide suf.cient internal readports to support writing.
Sentence 2: in the design, each write port has its own bank of two BRAMs, and writes for each are copied to both BRAMs i.e., corresponding locations in all of the BRAMs in a bank always have the same value.
Relationship: neutral
Domain: Hardware
Sentence 1: In [5], stochastic processes are used for generating transaction sizes and transaction de­lay using several statistical laws (Poisson, Exponential, and Normal).
Sentence 2: the tra.c can be characterized by two aspects: 1) spatial or topological distribution, describing the source-destination communication; and 2) temporal or tra.c nature, .tting the tra.c generation rate with a statistical distribution.
Relationship: neutral
Domain: Hardware
Sentence 1: The OS page handler then moves the referenced page into the cache from off-chip memory.
Sentence 2: the hardware-based approach is 1.42× faster than our software­based method,given1KBpagesizeand256KB cachesize,at theexpenseof 300,000 additionalgates, almost four times the size of an ARM7EJ-S processor core.
Relationship: neutral
Domain: Hardware
Sentence 1: As the counterpart, if the task instances have already good fault detectors (e.g., in the case of curve d), the system reliability will be improved more smoothly by inserting more redundancy, i.e., both DUF s and SDCs can be eliminated at the same time.
Sentence 2: the total budget can be distributed to individual tasks so that each task ti has a local deadline bi.
Relationship: neutral
Domain: Hardware
Sentence 1: Leakage comparisons for 2-Way NOR with UTB GeOI and SOI devices at (a) Vdd = 1.0V and (b) 0.5V.
Sentence 2: the Two-Way NOR with (A,B) = (1,1) shows smallest leakage than the Two-Way NOR with other input patterns.
Relationship: neutral
Domain: Hardware
Sentence 1: Eliminating the requirement of separate input replication mechanisms Previous redundancy based methods [7], [14] require input replication mechanisms such as a load value queue, because a value can be changed by another thread in the system between the time it is read by the .rst thread and it is read by the second thread.
Sentence 2: in FaulTM, there are no con.icts between the original and the backup reliTXs, because the backup reliTX is only for validation of error-free execution and it does not modify shared memory.
Relationship: neutral
Domain: Hardware
Sentence 1: Next, it applies the analytical equations (26) and (33) to calculate the second-order statistics E(|5i||5j|) where i,j E {1,2, ,N}, and then the noise power E(52) in (12).
Sentence 2: [9] J. Jaffari and M. Anis, Adaptive sampling for efficient failureprobability analysis of SRAM cells, IEEE ICCAD, pp.
Relationship: neutral
Domain: Hardware
Sentence 1: TIMING CONSTRAINTS In most synthesis applications (as opposed to the verification applications), it is necessary to introduce constraints on the minimum and maximum combinational path delays.
Sentence 2: some potential consequences of register minimization must be addressed for synthesis flows: 1) timing of the design is affected, and bounds must be placed on the lengths of the longest and shortest combinational paths to ensure that register setup and hold times are met, and 2) initialization of the sequential machine is affected, and if registers are retimed backward, the existence of an equivalent initial state is jeopardized without additional initialization logic.
Relationship: neutral
Domain: Hardware
Sentence 1: Otherwise, OAM labels it as Non-LLC-obstruction.Then during the following exeP eriod, this process is treated as the OAM detection result until the next period starts.
Sentence 2: due to the leakage energy reduction, an 8Mb STT-RAM L3 can save around 90% total energy compared to an SRAM L3 cache with the same capacity.
Relationship: neutral
Domain: Hardware
Sentence 1: .=SER These errors may or may not be noticeable or important to the user.
Sentence 2: their technique adds an extra cost to the design that is proportional to N (in NMR) for 1 Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 05) 1530-1591/05 $ 20.00 IEEE specific resource.
Relationship: neutral
Domain: Hardware
Sentence 1: If there is a hit data are served as usual and replacement infor­mation is updated conveniently.
Sentence 2: figure 8: Overhead of the 2 extra MSHR entries with respect to the L1+MSHR cache system (L1 is 4-way 64byte/line 1 R/W port, MSHR has 4 entries) as long as some instructions hit in L1 or the VC/MSHR/EB/WCBintheWCETestimation,ourap­proach provides bene.ts.
Relationship: neutral
Domain: Hardware
Sentence 1: While status signal is ON and there are .its waiting for dispatch, the upstream router keeps on .it transmission.
Sentence 2: the results are normalized to those of 1 kB page size, ex­cept for the workloads where internal SSD tra.c load sat­urates for small page sizes; in these cases (marked with *), the smallest page size (>1 kB) with unsaturated results is used for normalization.
Relationship: neutral
Domain: Hardware
Sentence 1: That is, every subbank has its own speed, irrespective of the slowest subbank speed.
Sentence 2: rEFERENCES [1] A. Agarwal, B. C. Paul, H. Mahmoodi, A. Datta, K. Roy, A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies, IEEE Transactions on Very Large Scale Integrated Systems, vol.
Relationship: neutral
Domain: Hardware
Sentence 1: In Proceedings of the Eighth IEEE Euromicro Workshop on Parallel and Distributed Processing (EURO-PDP 2000), pages 406 413, Rhodos, Greece, Jan. 19 21, 2000.
Sentence 2: as an example of the area reduction resulted from using networkpartitioning, Figure2showsa mesh implementation of 16-node application before and after partitioning.
Relationship: neutral
Domain: Hardware
Sentence 1: Since COL[1] is selected, the power lines of cell C5 and C13 are in floating state while the word-line is in off-state.
Sentence 2: when the input data of SRAM is high, the bit-line is connected to the upper bit-line pair with the higher voltage and the complementary bit line is connected to the lower bit-line pair with the lower voltage.
Relationship: neutral
Domain: Hardware
Sentence 1: [2] Candès, E.J., Romberg, J.K., and Tao, T. Stable signal recovery from incomplete and inaccurate measurements.
Sentence 2: is related to the width of the Gaussian For each data window, a binary search based algorithm is used to find the minimum measurement size M such that the reconstructed signal from CS operation meets the accuracy requirements.
Relationship: neutral
Domain: Hardware
Sentence 1: set of rates (which depends on the packet size, e.g., < 950 Mbps for 1470-B packets).
Sentence 2: 1 represents the consumption of 100 160  2.133 GHz 1 Core 2 Cores 4 Cores95 150 1.867 GHz 140 130 Pmin(l) 1.467 GHz 12080 1.2 GHz Power Consumption PBC [W] Power Consumption PBC [W] Efficiency d [AC/J] Power Consumption PBC [W] C 110 100 9065 800 2 4 6 8 10 12 0 1 2 0 1 2 3 4 0 1 2 3 4 5 6 7 8 9 Load l [ACPS] Load l [ACPS] × 109 x 109 (a) Survivor (a) Minimal power.
Relationship: neutral
Domain: Hardware
Sentence 1: CONCURRENT ERROOR DETECTION To detect a difference in values between the data stored in the SRAM and the PMC, Concurrennt Error Detection (CED) is employed; a dual-rail checker is uutilized by connecting two XOR gates in parallel as shown in FFig.
Sentence 2: the ON state rresistances of M1 and M7 are less than the resistance of the PMCC; so, the voltage at D is at 0V.
Relationship: neutral
Domain: Hardware
Sentence 1: Our theory, however, generalizes [6] in that (7.1) extends (8.5) to arbitrary coupled topologies and to finite ramp sources.
Sentence 2: because of admissibility properties (a) and (b), we can say that, for any admissible fi, gV z max d DD 1 v R » , if D >> t12 (5.5) D since the maximum value of the integral in (5.4) is approximately (but always somewhat less than) 1 for such functions and rise times.
Relationship: neutral
Domain: Hardware
Sentence 1: In such cases, SystemC ultimately represents a parallel programming approach such as an approach using POSIX threads, with the added benefit of supporting circuit-style spatial connectivity, but the drawback  Figure 1: SystemC-on-a-Chip allows a designer to emulate SystemC descriptions on various supported development platforms.
Sentence 2: the SystemC libraries are large and require OS support, thus limiting the number of platforms that could support the SystemC-on-a-Chip framework.
Relationship: neutral
Domain: Hardware
Sentence 1: As shown on the rightmost path through the .owchart, we begin by generating an implication set and removing all implications dom­inated by others (and possibly other low quality implications as well) to form a compressed set of implications.
Sentence 2: because we are not performing an exhaustive cir­cuit simulation, it is possible that this relationship may not hold for some other unsimulated input combination.
Relationship: neutral
Domain: Hardware
Sentence 1: Mm Defnition4GivenasetM={Ml,,Mn}ofmodules, whereMk =(Ik,0k,Tk),andanothermoduleMO =(IO,0O, TO),apseudotimingfailureof{MO}MwithrespettoMO isafnitetraex=(w,T),wherewEIO,suhthatM1= ,MO1=x,andlatCst(,w,MO)=latCst(,u,MO)holdsfor somereallimitedoutputuofMO.
Sentence 2: [Mirrorproperty]MeonformstoitsspeifationMs,if Me{Msm}isfailure­free.
Relationship: neutral
Domain: Hardware
Sentence 1: State-scan technique also uses a higher amount of memory to store the different faulty states to evaluate.
Sentence 2: 67 / 5.3 kbits 3,836 (227%) 859 (300%) 4,162 (255%) 1,032 (380%) [2] P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza, M. Violante.
Relationship: neutral
Domain: Hardware
Sentence 1: These branches are insensitive to the previously mentioned 100% 100% 98% 96% 96%  Branch Prediction Hit Rate 94% 92% 90% 94% 92% 90% 88% 88% 86% 86%  Connecting Data Transfering Clossing Connecting Data Transfering Clossing Flow Live (N-th Pkt) Flow Live (N-th Pkt) (a) Branch Prediction -Tra.c without (b) Branch Prediction -Tra.c with aggregation level high aggregation level Figure 5: Branch prediction study through packet .ow life tra.c properties (see Section 4).
Sentence 2: [18] C. Kruegel, F. Valeur, G. Vigna, and R. Kemmerer.
Relationship: neutral
Domain: Hardware
Sentence 1: L. The dual control network is a single point of failure, since the cor­rect con.guration of the system depends on its capability to safely deliver information from switches to the controller and vice versa.
Sentence 2: at every usage session, the user is informed about whether the fault-tolerance logic has its full re­covery capability from transient faults at runtime, or whether it is degraded by permanent faults to some extent.
Relationship: neutral
Domain: Hardware
Sentence 1: The height of the display screen above the floor is dgd, the distance between the central axes of the two projectors is dpp, the distance from the projector to the display surface is dpd, and the horizontal distance between the observing position and the central axis of the display is reye.
Sentence 2: the prototype system discussed in our previous papers [1] uses a commercial variable angle display (Barco Baron) [9] as a horizontal table in combination with active time­sequential stereoscopic glasses (Stereographics CrystalEyes3) [10], thus making the system relatively complex and expensive.
Relationship: neutral
Domain: Hardware
Sentence 1: Instead we solve an appropriate linear relaxation to provide a lower bound on the integer optimum and then employ a technique called randomized rounding to round the solution to the linear relaxation, which is typically fractional, to an integer solution.
Sentence 2: f (6) In terms of linear constraints we have - cube_1 - f =-1 - z - f =-1 cube_1 + z + f = 1 (7) We have now introduced all the constraints needed to explain the logical behavior of the gate.
Relationship: neutral
Domain: Hardware
Sentence 1: An open-source ieee 802.15.4 mac implementation for tinyos 2.1, February 2011.
Sentence 2: table 3 reports on the numbers of network elements needed to cover at least 60% or 80% of the monitoring area, while in Table 4, assuming the same number of SNs as in Table 3, the focus is on the resulting coverage.
Relationship: neutral
Domain: Hardware
Sentence 1: Base on this observation, we propose the following non-minimum length encoding scheme: For n ROs with frequency ROi (i=1,2, ,n), we define its code as a k-bit string sgi =d(1,2)d(1,3) d(1,n)d(2,3) d(2,n) d(n-1,n) (2) where k=n(n-1)/2, d(i,j) = 0 if ROi < ROj and d(i,j) = 1 otherwise.
Sentence 2: block size k=6 in IBS and fth = 2.6x standard deviation in KSC (see Figure 5 and Figure 6).
Relationship: neutral
Domain: Hardware
Sentence 1: Finally, in the futuristic International Space Station (ISS), spacecrafts and airplanes, high-speed Internet access that is required for scientific and leisure purposes also calls for high-speed inter-spacecraft communication links.
Sentence 2: without the fiber dispersion and fiber nonlinearity, performance comparison between NRZ and RZ formats is necessary to determine which format can achieve better performance for LIC systems.
Relationship: neutral