sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Similar results are also shown for another set for c499 in table 3 where we have a 7% probability of worst case cross-talk.
Sentence 2: in this work, we provide a graphical probabilistic causal model for the input space for ef.cient estimates of the switching Table 2: Joint Probability Switching Estimate for Nodes 300 and 330 of C432 for(a) 60K vectors (b) for compression ratio =40 State 00 01 10 11 State 00 01 10 11 00 0.06 0.19 0.19 0.54 00 0.05 0.19 0.19 0.56 01 0 0 0 0 01 0 0 0 0 10 0 0 0 0 10 0 0 0 0 11 0 0 0 0 11 0 0 0 0 (a) (b) Table 3: Joint Probability Switching Estimate for Nodes 557 and 558 of C499 (a) 60K vectors (b) for compression ratio =40        (a) (b) models that not only models singleton switching but also models joint switchings of neighboring nodes.
Relationship: reasoning
Domain: Hardware
Sentence 1: At any .ip-.op in a circuit, the setup time constraint like (1) should be met.
Sentence 2: the setup time constraint for a circuit can be written as CF : max { qi +.ij + sj }= T .. DF = T (2) i,j where the maximum is performed with all .ip-.op pairs with a direct edge in the reduced timing graph.
Relationship: reasoning
Domain: Hardware
Sentence 1: Although the high frequency response is highly localized, the mid­low frequency currents (1-2 GHz) dissipate outward from the source to affect several gates.
Sentence 2: when there are multiple switching sources of current, the high frequency transients of each gate will only have local impact around the gate while the mid-low frequency transients will have additive impact at every neighboring gate, overwhelming each gate s localized high frequency effect in amplitude.
Relationship: reasoning
Domain: Hardware
Sentence 1: In this way, a three-level prefetcher with stream chaining can predict not only the expected next misses from the current memory access instruction but also the expected next misses from the expected next memory access instructions to miss in program order.
Sentence 2: such a prefetcher has an extra level of .exibility and can adapt to situations both in which missing mem­ory accesses from the same static instruction are too far apart and in which missing accesses from static instructions consecutive in program order are too near.
Relationship: reasoning
Domain: Hardware
Sentence 1: Inthenexttwosub­setions,weuseadatadependenetest problemtoillustratehowtoonstrutaQueryGenerator andaPropertyCheker.
Sentence 2: 3.2.7 Generating Demands Anewdependenetest,alledtheoffet­lengthtest[20], hasbeendesignedtodisprovedatadependenesinloops whereindiretlyaessedarraysarepresentandtheindex arraysareusedasofsetarraysandlengtharrays,suhas theoffset0 andthelength0 inFig.3.Theoffet­length testneedsarraypropertyanalysistoverifytherelationship betweentheoffetarraysandthelengtharrays.theoffet­lengthtestservesasaquerygenerator.
Relationship: reasoning
Domain: Hardware
Sentence 1: This simulation set is performed with Atalanta RTOS, Version 0.1, which does not support processor-to-processor communication/synchronization (e.g., semaphores, message­passing) for the tasks running on different processors.
Sentence 2: atalanta Version 0.1 cannot support preemption of longCS locks, and so our simulation treats all locks as short CS locks.
Relationship: reasoning
Domain: Hardware
Sentence 1: It is interesting to note that the worst case condition occurs at high voltage, and not at low voltage, since the decrease in cur­rent and dI/dt more than offsets the reduced voltage swing.
Sentence 2: volts 2 1 the design of the power grid (to evaluate R) and the package (to 0  evaluate L) only needs to consider one operating voltage, which is 60 80 100 120 140 160 180 200 220 240 260 maximum VDD.
Relationship: reasoning
Domain: Hardware
Sentence 1: Suppose that after merging, the best Q value with the cost t, denoted by Qt, is obtained by choosing ai and bj.
Sentence 2: qt =min{Q(ai),Q(bj)} and i + j = t. We claim that after merging, the best Q for cost t + 1, denoted by Qt+1, must be the maximum Q between min{Q(ai+1),Q(bj)} and min{Q(ai,bj+1)}.
Relationship: reasoning
Domain: Hardware
Sentence 1: To extract TSV-to-TSV coupling capaci­tance accurately, an approach considering only the closest neighbor  (4) or limiting the maximum target distance to calculate coupling ca­ pacitance cannot be used.
Sentence 2: we propose an algorithm that [] µL Pi0Pj0 Pi0(r + tox ) Lsi,ij = ln 2p where Pi0 is the pitch between the victim TSV (#0), and the ag­gressor TSV(#i) and Pij is the pitch between two aggressor TSVs (#i, and #j).
Relationship: reasoning
Domain: Hardware
Sentence 1: An m:n counter can count bi by connecting it to 2i inputs.
Sentence 2: an m:n counter can implement the functionality of an M-bit GPC g, provided that: k -1 i m=.mi 2 (3) i=0 In the FPCA, both M and m are constant for GPCs, and m > M. an m:n counter can implement many different GPCs.
Relationship: reasoning
Domain: Hardware
Sentence 1: The dynamic power and clock wirelength resulting from the proposed .ow is 10% and 18% less than that resulting from Reference Flow 2 , respectively, while the signal net wirelength resulting from both .ows are still quite similar.
Sentence 2: the proposed gated clock network power optimization with simultane­ous CG cloning and FF merging is very effective in reducing both dynamic power and wirelength of the gated clock network.
Relationship: reasoning
Domain: Hardware
Sentence 1: The decoder tries to obtain the u n with the re­ceived syndrome bits and given side information y n.Ifthe decoding fails, that is, u n u n = , the decoder requires the encoder through the feedback channel to transmit the more r syndrome bits.
Sentence 2: if the decoding succeeds, then the decoder transmits the u n to the encoder to reconstruct the source x n. the transmitted syndrome bits of the l-th it­eration is de.ned as uF (l) , where F (l) = {si :1 =i =rl}.If the decoding succeeds with the rl syndrome bits, the com­pression rate R is determined as rl/n.
Relationship: reasoning
Domain: Hardware
Sentence 1: Circuits reported in Tables 4 and 5 feature a wide range of X-fill rates starting from 0.001% (C6) and getting close to 5% (C4).
Sentence 2: the resultant increase in a pattern count signifi­cantly varies from less than 1% for circuits with a low X-fill rate (C6) up to as much as 300%, if a design sees a high percentages of X s (C1 and C4).
Relationship: reasoning
Domain: Hardware
Sentence 1: When Vdd and Vt change, we can calculate delay values for the ten longest paths under new Vdd and Vt lev­els, and choose the largest one as the new critical path delay.
Sentence 2: the FPGA delay can be calculated as follows: 3.1 Overview In this section, we evaluate four FPGA hyper-arch classes: Class1, Class2, Class3, and Class4 (see Table 4).
Relationship: reasoning
Domain: Hardware
Sentence 1: The 2meanGaussianrandomvariableswithvariance sw the corresponding noisy ECG signal is q = q0 + w. (14) To quantify performance, the following quantities have been considered: 6Independent identically distributed.
Sentence 2: .two curves almost overlap and the SNR gain in this case is as high as GSNR =14.5dB.
Relationship: reasoning
Domain: Hardware
Sentence 1: The n-bit state machine can control the cache so that it takes n2 - 1 hops to enter the state of the opposite action, for example, from State +1; increasing a way to State -1; decreasing a way or vice versa, and stay in the inter­mediate state, State 0, in the transition period.
Sentence 2: as long as the change in distribution of references is highly ir­regular across time, the state machine stays in State 0, and instructs the cache not to take any resizing action.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that in this case, it is unrealistic to predict the precise time of the completion of the execution of O (due to the physical distribution of component services and/or network communication delays).
Sentence 2: the EC formula that is automatically extracted for invoke does not specify an upper limit for the time variable t2 that signifies the time of the completion of O (the range of t2 is specified as R(t1, t2) in the relevant formula of Figure 3).
Relationship: reasoning
Domain: Hardware
Sentence 1: Em Ea  ibmpg2 0.75 0.05 0.44 0.06 0.08 1.42 72 < 1e< 1e -5 -5 ibmpg6 9.49 0.76 2.89 0.67 1.29 15.4 406 < 1e< 1e -5 -5 ibmpgnew1 9.07 0.69 2.79 0.58 1.16 14.6 349 < 1e< 1e -5 -5 ibmpgnew2 9.36 0.62 4.28 0.69 1.17 16.4 495 < 1e< 1e for boundary currents, and Step 2 updates the solutions for internal nodes.
Sentence 2: the convergence of this iterative error reduction scheme can be guaranteed.
Relationship: reasoning
Domain: Hardware
Sentence 1: Furthermore, since |si+t-dj|·c « Cap(dj), (6) can 2 be rewritten as: t(si +t,Rjk) |si +t -dj |·r ·Cap(dj)+constj .
Sentence 2: (7) the function COST, which is the sum of the total delay from set S to registers in set D under matching F and transformation t, is as a weighted total wirelength from tapping points to subtree roots.
Relationship: reasoning
Domain: Hardware
Sentence 1: If one optimally grows s * (i.e., adding Fsmall to it in an optimal fashion), the resulting solution would have the peak power at least p(OP Ts *,continuous), since the optimal continuous solution (computed using linear programming formulation) gives a lower bound on any solution growing from s * .
Sentence 2: the difference between p(OP Ts *,continuous) and p(OP T ) is only bounded by the rounding error in dynamic programming.
Relationship: reasoning
Domain: Hardware
Sentence 1: q e4.6 r F e n 4.4 u T 4.2 4 Vcont(V)  Phase noise and frequency tuning range are both critical VCO specifications and these are closely correlated to each other.
Sentence 2: to evaluate VCO performance with phase noise and power consumption as well as frequency tuning range (FTR), we propose a new figure-of-merit (FOMT) as shown in Equation 10. .
Relationship: reasoning
Domain: Hardware
Sentence 1: However, if scaling down the metal dimensions brings large bene.ts in design quality, process engineers are willing to invest efforts towards it.
Sentence 2: the purpose of this metal dimension reduction study is to explore the interconnect design space for maximizing the bene.t of MI-T; extreme scalings (> 20%) may not be manufacturable with the technology node due to lithography limitations, chemical mechanical  Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: According to reading and programming strategy in MLC .ash memory, the largest .Vth in an MSB page is given by µ2 - µ0 (i.e., from state S0 to S2), whereas µ1 - µ0 (i.e., from state S0 to S1) yields the largest .Vth in an LSB page.
Sentence 2: before TVR is applied, the programming time for an MSB page is 22 · tstep according to equation (14), where tstep is the time for one ISPP step.
Relationship: reasoning
Domain: Hardware
Sentence 1: PODC01 Newport Rhode Island USA Copyright ACM 2001 1-58113-383-9/01/08...$5.00 limited to individual protocols; there has been no frame- work for reasoning about the semantics of quorum variables as a family.
Sentence 2: while linearizable operations have been straightforwardly achieved for some types of quorum sys- tems (notably the dissemination quorum systems of [4]), there have been no tools available for generalizing these so- lutions or for exploring the limits of their applicability to other types of quorum systems for which such operations have been significantly more difficult to achieve (e.g., mask- ing quorum systems, [3]).
Relationship: reasoning
Domain: Hardware
Sentence 1: Radix-2 Radix-4 Split-Radix N Mj Mnt Mtot Mj Mnt Mtot Mj Mnt Mtot 32 15 34 49 N/A 23 26 26 64 31 98 129 5 76 81 57 72 72 128 63 258 321 N/A 135 186 186 256 127 642 769 21 492 513 313 456 456  The other multiplier input is controlled by hard-coded twid­dle factor lookup tables.
Sentence 2: we can modify the tables v to replace 1 or -1 values with twiddle factor values from the previous cycle.
Relationship: reasoning
Domain: Hardware
Sentence 1: In the alternative tuning approach, a digital word is employed to switch on or off a set of analog unit element devices, which determine the time-constant to be tuned [4], and the accuracy of the tuning system is correlated to the quantization of the component whose value has to be adjusted.
Sentence 2: the length (number of bit) of the control word typically corresponds to the achievable system accuracy.
Relationship: reasoning
Domain: Hardware
Sentence 1: The overall impedance of two parallel RC circuits is determined as (Reff _ n + 1 ) //( Reff _ p + 1 ) , and simplified as sC sC eff _ n eff _ p R R 1 eff _ n eff _ p + +higher _ order _ terms R + s C eff _ n Reff _ p ( eff _ n +Ceff _ p ) For first-order hand calculations, the higher-order terms are negligible.
Sentence 2: the overall effective capacitance is the sum of the two individual decoupling capacitances, and the overall effective resistance is the parallel combination of the two individual effective resistances.
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, gM (v6)can be determined without using the other part of M if M is monotonic.
Sentence 2: 3.5 Construction of cost graph We construct a cost graph for via assignment V .It rep­resents MSEQs begun with a via and the via is denoted by vs.In cost graph G, the gain of a MSEQ corresponds to the length of a directed path in G. For convenience, a dummy via is placed to a node if no via is assigned to the node in V. a MSEQ begun with vs is represented by a sequence of vias as (vs, vi, vj, vk, ..., e)where eis a dummy via.
Relationship: reasoning
Domain: Hardware
Sentence 1: (    , !% - .-% (' Figure 4: Temperatures on each of the four die on a4-die stacked3DIC an integer adder is stacked on an integer multiplier, only one of them might be active based on the application re­quirements.
Sentence 2: distributing the power of each of the 3D circuit blocks uniformly among the stacked die is a conser­vative power density model.
Relationship: reasoning
Domain: Hardware
Sentence 1: On average over all the phases, TaPT reduced the exploration time from 142 seconds to 6 seconds, with the longest and shortest exploration reductions being from 321 seconds to 13 seconds and from 25 seconds to 1 second, respectively.
Sentence 2: on average, TaPT reduced the exploration time by 96%, translating to a 25 times speedup in exploration time.
Relationship: reasoning
Domain: Hardware
Sentence 1: For the considered example, the initial nonlinear system is stable.
Sentence 2: jacobians of f at all lin­ Figure 5: Errors in output computed by TPWL models gen­erated with different MOR procedures (micromachined switch example); N = 880; intermediate Krylov model order qi = 96; 5.5-volt step testing and training input voltage.
Relationship: reasoning
Domain: Hardware
Sentence 1: The DC power dissipation of M2 and, thereby, the tem­perature sensed by Q1, may vary due to process variations occurring within the LNA.
Sentence 2: as in mode DC-TS, we need to de.ne the intervals in which CALN and CALP must be varied in this step, in order to .x the output of the temperature sensor to V ref .
Relationship: reasoning
Domain: Hardware
Sentence 1: The following experiments were then carried out: A. Validation of Dynamic Circuit Style The dynamic circuit style presented in Section II was evaluated with the xnwFET devices in HSPICE.
Sentence 2: vDD for Device #2 was chosen at 0.8 V. VDD for Device #3 was chosen at 1 V. The latter has a positive VTH of around 0.23 V. when these n-type devices are used for pulling up circuit nodes, the voltage at the node will not reach the full VDD but a value close to (VDD -VTH) [19].
Relationship: reasoning
Domain: Hardware
Sentence 1: According to 1 , the weight of the document in position i i2 in the priority ordering is: c+i 1 1 1 wX (d) = c1dx = c1- (1) c+i-1 x2 c + i - 1 c + i where c1 is a normalization factor to ensure that the sum is 1. c is another parameter that moves the function in order to give more or less weight to the high priority documents.
Sentence 2: stating that the total sum weight is one:  8 1 1 c1 dx = c1 = 1 c x2 c c = c1.
Relationship: reasoning
Domain: Hardware
Sentence 1: The size of the .nal inverter stage is typically about 1000× [11] that of a minimum sized inverter in the process tech­nology, due to the large load (typically 25pF to 50pF [12]) that the output driver is rated to drive.
Sentence 2: the .nal stage of the output driver is typically implemented as a multi-.ngered de­vice (with typically 10s of .ngers connected in parallel) for layout ef.ciency.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thehighhardwareefficiency is achieved by the proposed direct 2-D transformalgorithmwhich can compute one 4x4 block of the 2-D transforms in H.264 every two cycles without using transpose memory or registers.
Sentence 2: the proposed efficient multi­transform coding design can perform HDTV 1080i and digital cinema video formats when operated at 50 MHz and 100 MHz, respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: First note that after the wire ordering procedure in section 4.2, /i; (overlapped and adjacent wire length between wire Wi and W;, refer to section 2.I) becomes a constant for a given pair of wires.
Sentence 2: the yield models (3), (4) and (5) in section 2.2.I can be written as: o (is pio ' POF=-FgPOF=-GgPOF="d i ii; iiii Wi i;  s where ei g fi g Yi , Fi and Gi are positive constants for a given pair of wires.
Relationship: reasoning
Domain: Hardware
Sentence 1: On the other hand, if the same store instruction was executed in the reference model, the next instruction executed in the reference model would be a modified instruction because there is no concept of pipeline in the reference model.
Sentence 2: if a self-modifying code is executed, the In struct ion c o m m it Inst ruct io n L o ca l store a r ra y a cce s s  Timing issue Cha nnel reg is t er a c cess of t h e logic   reference model cannot continue executing the same sequence as the actual logic.
Relationship: reasoning
Domain: Hardware
Sentence 1: For example, when sensor s fails, we expect a change in the relative behav­ior of classi.er C (S, S - s) and classi.er C (S - s, S - s).
Sentence 2: we calculate the F-score of each of these classi­.ers with respect to the original classi.er C0 to measure the similarity between their outputs.
Relationship: reasoning
Domain: Hardware
Sentence 1: For acyclic sequential circuits, it is also known that test patterns with 100% FE can be generated in practical test generation time on the time expansion model (TEM) [1].
Sentence 2: we expect that, for an RTL circuit, we can achieve 100% FE in practical test generation time if there exists a TEM such that the number of time frames required for any testable fault is bounded by a linear function of the number of reg­isters in it.
Relationship: reasoning
Domain: Hardware
Sentence 1: Comparing EQ25 and EQ26, the only difference lies in Ileak,M and tdly.
Sentence 2: we introduce a statistical adjustment factor Astat to consider both statisti­cal terms: · tdly I leakM = -------------------------------------------(EQ 27) Astat NI leak 0 td, nom Since subthreshold swing is a function of Vdd (a quadratic function serves as a good estimation), the closed-form expression for nominal Vmin,nom in [4] is no longer accurate.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that the system performance with the hybrid DRAM/PRAM shown in Figures 10 and 12 is conservative since, as mentioned in Section 6.1, we did not scale down the PRAM read latency at advanced technologies.
Sentence 2: with a scale down of read latency at those technologies, further performance improvement can be obtained with the hybrid DRAM/PRAM main memory.
Relationship: reasoning
Domain: Hardware
Sentence 1: The measurement results are investigated using 16 sample chips.
Sentence 2: the energy consumption is less than 10 pJ / access at 0.5 0.7 V. Technology 40 nm bulk CMOS Macro size 0.566 mm x 0.976 mm Macro configuration 256 Kb (16Kb x 2 x 8), 16 bits/word Cell size 0.706 .m (logic rule) # of cells/BL 16 (RBL), 128 (WBL) Density 463 Kb/mm2 X decoder, WL driver 16-Kb memory cell array with local read circuits Address buffer Y decoder, selector, IO circuit WBL/WBLN Global RBL   CLE  WWL RWL RDE DRN WWL RWL WWL RWL RDE DRN WWL RWL YS Input Output Readout 4.
Relationship: reasoning
Domain: Hardware
Sentence 1: A signature is made in step 13 from the encrypted backup package .le for external checks.
Sentence 2: in steps 14 to 16, the loopperforms an encryp­tion of the backup session key ksbkp using each publickey of backup HSM s certi.cates, creating as many encrypted ses­sion keys as backup certi.cates there exist.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thesimulatedwaveformsof ourproposed circuit areshown inFig.5 whereNis 5.As in transitionsfromhigh tolow, n1 is pulled up to VDDH to ensure the diode transistors stack is able to sink current from VDDH.
Sentence 2: both intp and intn rise to within 10% of their corresponding steady statevoltageinafewhundred ns(FO4delay at 0.3Vinthis technology is 18ns).
Relationship: reasoning
Domain: Hardware
Sentence 1: , {niwi,thiemo}@sics.se¶ more intensive due to the weak GPS signal strengths (about 20 dB below the noise level); and Doppler frequency shifts ( 4.2 kHz) caused by the satellite motion (and receiver move­ment on the ground) [4].
Sentence 2: the .rst factor makes it dif.cult to duty-cycle the GPS receiver for saving energy; while the second necessity introduces the need for a sophisticated CPU for complicated computations.
Relationship: reasoning
Domain: Hardware
Sentence 1: and often can lead to a solution that suffers from sub-optimalityin terms of overall wirelength.
Sentence 2: let n be the global placement iteration number and M be itsupperbound2 andde.ne p(n)as the alignment weight schedule function for each iteration n. The following equation for p(n)is proposed: 8 2 8n M > 0 = n< < M2 4 8(n-M M p(n)= 1- 2 )2 = n = 3M (4) > M2 44 : 8(n-M)2 3M <n = M M2 4 To minimize hard constraints during the initial stages of global placement,p(n)graduallyincreasesduringtheinitialiterations and to minimize large constraint changes during the .nal stages, the functiondecreases towardzero atthelastiteration.
Relationship: reasoning
Domain: Hardware
Sentence 1: Those combinations span a wide range of operating points sufficient to cover the voltage ranges over which one plans to simulate.
Sentence 2: given the circuit topology of Figure 10, Kirchoff s current law (KCL) at the output node can be expressed as an ODE: dVin Ip - In + (Cm ) - I(Zint) - I(Zout) dVout dt = .
Relationship: reasoning
Domain: Hardware
Sentence 1: Due to the multi-rail encoded data and explicit handshake-based event-ordering, the authors in [3] proved that any failure by a sin­gle stuck-at fault in the PCHB circuit either deadlocks the circuit or produces an illegally dual-rail encoded output (X 0X1= 11 ).
Sentence 2: fail-stop behavior can be implemented by adding a checker (NAND gate) onto each output of a PCHB circuit.
Relationship: reasoning
Domain: Hardware
Sentence 1: Speci.cally in the gate sizing optimization problem, as the probability of failure of constraint satisfac­tion increases, the utility of the improvements in the ob­jective functions as a result of the failure of the constraint decreases rapidly.
Sentence 2: a stricter notion of utility func­tiongivenbyVonNeumann andMorganstern[16] for .i is identi.ed in this situation.
Relationship: reasoning
Domain: Hardware
Sentence 1: In the best case, if C (combinational logic C+ and C-) is selected to route to the next Basic Cell and no signals are routed to other Cells, the entire D-FF stage and the Output stage can be shut down.
Sentence 2: the number of ON current trees is reduced to 9 (7 CML MUXs, one emitter follower pair).
Relationship: reasoning