sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: They present a method for behavioral matching of an unknown sub-circuit against a library of abstract components but assume that methods are available to generate sub-circuits from the unstructured netlist.
Sentence 2: our set of solutions is complementary to theirs because: (a) we target different kinds of components for reverse engineering and (b) we analyze an unstructured netlist as opposed to sub-circuit matching.
Relationship: reasoning
Domain: Hardware
Sentence 1: Evidently, the transfor­ mbfenf mation X yis such a transformation.
Sentence 2: the initial c block word 00can be obtained from the more power ef.cient code mben word 000by utilizing the transformationX ffy, thus effectively c eliminating both bit transitions associated with the initial word 00. cc Let s consider now the block word 0.
Relationship: reasoning
Domain: Hardware
Sentence 1: In other words, the probabilities in (1) and (2) are very small.
Sentence 2: to obtain accurate estimates For example, in a typical scenario, assuming a con.dence level of 95%, Tm = 100 ppm, and E = 0.1, it turns out that Nmc = 3.8 · 106 which is clearly a prohibitively large number of simulations.
Relationship: reasoning
Domain: Hardware
Sentence 1: Compared with the conventional two-way set associative caches, which have almost the same miss rate as our efficient cache, the energy consumption of the two-way set associative cache is on average 20% and 15% more than a direct mapped cache.
Sentence 2: our efficient cache can achieve almost the same miss rate but consume 30% and 23% less energy than a conventional two-way set associative cache at cache size of 4 Kbyte and 8 Kbyte, respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: A study proposed a methodology that per­forms full-chip TSV-to-TSV coupling analysis [3], but the analysis may not have been accurate because the analytical model they used overestimated the coupling capacitance.
Sentence 2: in this paper, we study the multiple TSV-to-TSV cou­pling effect inside 3D ICs on a full-chip level.
Relationship: reasoning
Domain: Hardware
Sentence 1: So most of high-precision arithmetic is accomplished by software emulation, such as the QD library [13] that solves a Double-Double (DD) pre­cision addition by using 8 double precision additions and a comparison, and it solves a DD-multiplication by using 9 double precision multiplications and 15 double precision ad­ditions [7].
Sentence 2: the performance of DD or QD (Quad-Double) precision arithmetic, using software, drops process­ing time by a factor of 5-25, compared to 64-bit .oating­point.
Relationship: reasoning
Domain: Hardware
Sentence 1: When only inter-die vari­ation is considered, all gate lengths within a particular die become perfectly correlated.
Sentence 2: the gate length of gate i, only consid­ering die-to-die variation, can be expressed as: LgiLnom i where Lnom,i is the nominal value for gate i, .Ldie-to-die is a single random variable that is applied to all gates in the circuit, and sdd is the global gate sensitivity to changes in .Ldie-to-die.
Relationship: reasoning
Domain: Hardware
Sentence 1: When putting ek back to CQG, qk must also be properly set to ensure that (7) still holds for any newly generated cycle C derived from C by just replacing ed with ek.
Sentence 2: it follows that (7) is guaranteed to hold for every such cycle C if the following inequality can be satisfied: qk ck tqd cd (or qk tck + qd cd) (9) minimal queue size of an edge removed by edge unification previously can be derived using (9).
Relationship: reasoning
Domain: Hardware
Sentence 1: In the integrated layered multi-crossbar structure, the wordlines and local bitlines are connected to the top and bottom electrodes of two di.erent vertical bipolar switches.
Sentence 2: a page can be n times larger in size, where n is the number of the layers employed; however, because of the vertically-connected shared resource, only half of a target page can be activated simultaneously [5].
Relationship: reasoning
Domain: Hardware
Sentence 1: After Sj multiplica­tions, the operand from matrix A will be changed by a new one, which requires a read operation from FIFOA to regis­ter TA (see Figure 5(a)).
Sentence 2: the second and the third counter are employed to calculate the local load and store addresses of C. besides the MAC unit, the structure of the PE only employs several counters and a comparator, and can be fully parameterized for an arbitrary matrix size by a few numbers: pid, Si, Sj and P. 5.
Relationship: reasoning
Domain: Hardware
Sentence 1: Block Placement by Sequence Pair Asequenepairisapairofsequenesofnelementsrepre­sentingalistofnbloks.Thesequenepairstrutureisa­tuallyameta-grid,whihimposestherelationshipbetween eahpairofbloksasfollows: (,)=biistotheleftofbj(1) (,)=biisbelowbj(2) 0-7803-6634-4/2001/$10.00 &#38;#169; 2001 IEEE 4 2 6 5 4 1 2 3 6 5 (a) (b) Figure1:(a)ObliquegridforSequenepair(, )givingtherelativepositionsofthebloks;(b) theorrespondingpaking.Thedimensionsforthe6bloks are:1(4x6),2(3x7),3(3x3),4(2x3),5(4x3),and6(6x4).
Sentence 2: asanexample,fgure1illustratesthegridandthepak­ing.givenasequenepair(XVY),thehor­izontalrelationshipamongbloksfollowsahorizontalon­straintgraphGh(VVE),whihanbeonstrutedasfollows: 1.V={Sh}{th}{viii=1V...Vn},whereviorre­spondstoablok,Shisthesourenoderepresenting leftboundary,andthisthesinknoderepresentingright boundary; 2.E={(ShVvi)ii=1V...Vn}{(viVth)ii=1V...Vn} {(viVvj)iblokiistotheleftofblokj}; 3.Vertexweight=widthofblokiforvertexvi,but0 forShandth.
Relationship: reasoning
Domain: Hardware
Sentence 1: Assuming the output waveform is linear between x = Xlp and x = xl, the output voltage is approximated by u2q = VL,2q(X) = px + q t where p = VL,2(Xlp) and q = VL,2(XlV) -- pzlp.
Sentence 2: xl = (1--q)/p since it satisfy condition u2q(xl) = 1.
Relationship: reasoning
Domain: Hardware
Sentence 1: This problem can be cast into the following ILP formulation: 8 P > Minimize rtot = m ri, such that > i=1  Skew(TR, R,T ) = B > : 0 = ri = rmax , .i This apparently simple formulation hides the actual com­plexity of the problem behind the constraint on the skew, which is in fact de.ned in terms of MAX/MIN operators, and cannot be transformed directly into a linear constraint.
Sentence 2: we expand the skew constraint into a set of in­equalities according to its de.nition, i.e., in terms of path delays.
Relationship: reasoning
Domain: Hardware
Sentence 1: Caches Misses Distribution with Control In­ dependent Accesses It can be concluded from these performance results that our simple control speculative mechanism (SCM) is an e.ec­tive way of reducing the number of wrong-path loads (25% on average) without any performance penalty.
Sentence 2: since overall energy consumption is dependent on perfor­mance and power (E nergy = Power * P erf ormance), our mechanism e.ectively involves energy saving, because it de­creases dynamic power by reducing the number of wrong­path instructions executed without losing performance.
Relationship: reasoning
Domain: Hardware
Sentence 1: Our scheme is based on the observation that instead of using the network for sending subsequent requeststoawrite-busySTT-RAMbank, where theywill be queued until the bank is free, the network should serve requests to idle cache banks to hide the write latency.
Sentence 2: we selectively grant network resources to the cache requests for ac­cessing idle STT-RAM banks by prioritizing these requests over requeststobusy banks.Weexaminethe cache access distributions of different commercial and server workloads and observe that on an average, it is possible to delay 17% (up to 27%) of accesses to an STT-RAM bank for giving priority to other cache accesses, and thereby hide the memory latency.
Relationship: reasoning
Domain: Hardware
Sentence 1: Moreover, because the majority of the existing tools is based on the optimization of one single objective function, the optimum that is found is depending on the a priori choice of the weighting coef.cients used to combine the different ob­jectives.
Sentence 2: the methodology presented in this paper is based on the hierarchical use of powerful Multiobjective Evolution­ary Algorithms (MOEA) [7]: Through their inherent parallelism, these EA are well suited in handling the hierarchical decomposition of large systems.
Relationship: reasoning
Domain: Hardware
Sentence 1: Gates that lies close to each other share a common intra-die delay variable.
Sentence 2: the delay of gate k is X dk = dnorm,k + dl,s +.drandom,k 0<l<m, s intersects k where dnorm,k is the nominal delay of gate k and drandom,k represents the random variation of delay of k. In our ex­periments, the delay random variables .dl,s for segments are uniform distributions and the delays of dnorm,k are sam­pled under a normal distribution (an internally built library based on Monte-Carlo SPICE).
Relationship: reasoning
Domain: Hardware
Sentence 1: This heuristic is similar to the one employed in [5] for the area minimization under delay constraints, where in spite of such a division of gate-areas at multiple fanout points, ad­dition of the gate-areas due to points on area-delay curve at primary outputs generates the gate-area for an entire solution.
Sentence 2: employing simple algebraic operations such as addition and multiplication, two-dimensional congestion maps can be cre­ated during the matching phase.
Relationship: reasoning
Domain: Hardware
Sentence 1: Although there are prob­ably a few only processes today that saturate an 100G link, this may not be the case in the near future; in addition, in a multi-VM, multi-tenant DCN environment, any link may easily become congested.
Sentence 2: it is traditionally, but even more so today [5], largely agreed that the network should be able to slice its capacity in order to enable isolated and well-secured services to users.
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, we model our DPT-GC objective on a sub-pattern, not on a tile because the overlap length should not be treated as a penalty for the objective.
Sentence 2: for a sub-pattern Ps, its DPT-GC objective fgc(Ps) can be formulated as follows:  LL  fgc(Ps)=w i - Lox(Ps) - wi  ti .Ps ti .Ps  LL + h i - Ly(Ps) - , o hi ti .Ps ti.Ps y o where Lx(Ps)and Lo(Ps) are the required overlap lengths in the x-and y-directions for the sub-pattern, respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: i=1 In an incompletely speci.ed function, when the function value fi is don t care, the value of the function can be either 0 or 1.
Sentence 2: for such inputs, the characteristic function is inde­pendent of the values of output variables yi.Let fi d denote the don t care set, then we have y¯i( fi 0(X) .
Relationship: reasoning
Domain: Hardware
Sentence 1: Moreover, recent work on using silicon nitride has shown the possibility of designing multi-layer 3D integration of photonic layers with layer-to-layer optical losses as low as 0.1 dB [5].
Sentence 2: with an emerging technology such as photonic interconnects, it is essential to realize that the hardware cost of designing large scale fully photonic networks requires a substantial investment.2 energy, hardware and architecture limitations could force future de­signs to limit the number of photonic components at the on-chip level.
Relationship: reasoning
Domain: Hardware
Sentence 1: Under PVT varia- Design B: tions V, the reachable performance space P of feasible design Design C: variables D is: Performance1 P = F(D,V) (1) (a) Performance space When the process variations are small, the mean values of performance distributions are near to the nominal perfor­ mances, since the performances P can be linearly approx­ imated to the process parameters within acceptable error.
Sentence 2: we can .nd Pareto-fronts at di.erent yields around the nominal Pareto-front.
Relationship: reasoning
Domain: Hardware
Sentence 1: (TRANSFailure =(S (C R)) 13. if SCTime  ()= Tns) then 14. execute input port event 14. elseif .
Sentence 2: (TRANSFailure =(M (C R)) 15. if SCTime ()= TN)then 16. execute input port event  it results in the failure of the node which is passing on the data packet further to the next node and causes loss of data packet.
Relationship: reasoning
Domain: Hardware
Sentence 1: This indicates that the crucial point is not only the high resolution in the low periodicities, but also the way coe.­cients are spaced throughout the whole periodicity range.
Sentence 2: the combination of avoiding 1.33-and 4-times tempo overestimation by using the NSGT is considered to be an important .nding for the improvement of beat tracking sys­tems.
Relationship: reasoning
Domain: Hardware
Sentence 1: (b) Time divided round robin based arbitration  Table 2: Weights for Each Task Operation k Path(1) Path(2) Path(3) Path(4) 1 CVIF 1.944 1.944 1.944 1.944 2 VLD 1.2 1.2 1.2 1.2 3 RZD 2.4 2.4 4 IQ 4 4 5 IDCT L 7.7916 7.7916 6 IDCT C 7.7916 7.7916 7 MC 0.030375 1.09375 8 DVIF 10 10 3 RISC 1.2 2.4 4 MC 0.030375 0.06075 5 MC 1.09375 1.09375 6 DVIF 10 10 Total 35.157575 36.220950 15.468125 16.698500 In this case, each module can access to each bus within a given time slice tslice by turn.
Sentence 2: if di.erent n modules access the same bus at the same time, WCET x;i of the bus data transfer bti is Ixi/tslicel× tslice × n. We set the time constraint x;i to bti.
Relationship: reasoning
Domain: Hardware
Sentence 1: In other our model predicts a reduced voltage of 4 9 VDD which is corroborated by words, crosstalk discharge does not involve any of the nodes that partici­the Hspice simulation shown in Figure 6. pate in charge sharing.
Sentence 2: the charge loss due to crosstalk is indepen­dent of the charge redistribution due to charge sharing.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since we assume that nodes communicate via multi-hop routing protocols to save energy, these blind spot nodes are rendered e.ectively useless since they cannot transmit their sensed data to the data aggregation centers for further processing.
Sentence 2: at any given point of time, the number of useful nodes in the network depends not only on the nodes that are not already dead, but also on those that are not blind spots.
Relationship: reasoning
Domain: Hardware
Sentence 1: To specify such constraints, we de.ne an attribute type to each vertex of the kernel graph K and the number of shared resources, type t, within a row in C as St.
Sentence 2: if we de.ne that Vit ={v|.j, fV (v)=pij .v.type = t},then .i, |Vit|= St. Utilized CGRA Rows We de.ne UR as the set of CGRA rows that are utilized in mapping the application K onto the CGRA C. Thus UR ={Pi|.j, pij .
Relationship: reasoning
Domain: Hardware
Sentence 1: Output operations are performed in the last clock cycle of the macrostate, while read operations can be assigned to any instruction belonging to the macrostate.
Sentence 2: given the number nof clock cycles required to execute a macrostate at the RT level, the behavioral test vector applied to such a macrostate at the behavioral level must be repeated ntimes in order to synchronize its outputs with the start of the execution of the instructions of the next macrostate.The value nrepresents the number of clock cy­cles necessary to produce the same output value on the out­puts of the RT-level representation obtained after one clock cycle on the behavioral-level description.
Relationship: reasoning
Domain: Hardware
Sentence 1: In addition to the amplification, they make it possible to use a complementary version of the output-latch stage of the previous ones.
Sentence 2: the positive (regenerative) feedback based on PMOS transistors M8 and M9 was replaced with the NMOS transistors M6 and M7, which increases the output drive current at the same area since the drive current of a NMOS transistor is larger than that of the PMOS transistor at the same width.
Relationship: reasoning
Domain: Hardware
Sentence 1: 2.1 Fractal coherence protocolsFigure  1 shows an example of a tree hierarchy where two two-core systems are composed to form a four-core system such that the interactions between each cache and its parent (an external entity) in the two-core system are identical to the interactions of each two-core system with its parent (an external entity) in the four-core system.
Sentence 2: sub-systems 1, 2, and 3 in Figure  1 are observationally equivalent to each other and to the entire system.
Relationship: reasoning
Domain: Hardware
Sentence 1: This is because of two reasons: 1) when executing qsort, MorphCore does not spend a signi.cant amount of time in InOrder mode (only 80% of execution time runs more than 2 threads active as showninFigure8), and2) evenwhenmorethan2threads are active, only 50% of the time are 6 or more threads active (data not shown in Figure 8).
Sentence 2: morphCore does not get much opportunity to achieve higher throughput.
Relationship: reasoning
Domain: Hardware
Sentence 1: This implies that any (4,W )-PSGR can be decomposed into a union of 4PMSGRs of densities 1 or 2, and these 4PMSGRs can then be regrouped into bWW2c (4,2)-PSGRs and (W%2) (4,1)-PSGR.
Sentence 2: we need only de­sign a (4,2)-USB and a (4,1)-USB.
Relationship: reasoning
Domain: Hardware
Sentence 1: Furthermore they should take into account the dependency, the in.uence of the number of contributing nodes in the application pro­ http://dx.doi.org/10.1145/2512921.2512931  cessing, since the higher is this number the faster is the pro­cessing and, consequently, the better is the MCS application performance.
Sentence 2: the main contribution of the paper is a model for the quantitative assessment of MCS application performance, stochastically characterizing their processing times through generic distributions and taking into account the e.ects of the node interactions on the job application performances.
Relationship: reasoning
Domain: Hardware
Sentence 1: Unlike traditional designs, whose operating points (supply voltage/frequency) are determined from worst­case corner analysis, RBD allows more aggressive operating points by instrumenting circuits with the capability to detect and recover from the ensuing timing errors.
Sentence 2: rBD im­proves energy-e.ciency by eliminating guard bands that are traditionally used to deal with variations and enabling circuits to operate at lower voltages.
Relationship: reasoning
Domain: Hardware
Sentence 1: Observations showed that many older users wouldavoid the exhibit if it was not clear how to use it.
Sentence 2: whileinstructions were initially offered on posters beside the exhibit,and later as pre­recorded voice­overs, the best solution was foundto be an instructional screensaver that triggers if the video feedfrom the handheld has not changed significantly for 30 seconds. if the exhibit is unused for 30 seconds, the screensavershows a video of the exhibit being used, which is visible from thelarge LCD panels directed towards bystanders.
Relationship: reasoning
Domain: Hardware
Sentence 1: For robustness analysis, we are interested in the minimum distance from the nominal point to any point within the range D at which timing is violated.
Sentence 2: we are interested in the minimum distance to the boundary of C, obviously provided that S(X)fails somewhere inside D. 2) Normed distance to a hyperplane: We want the mini­mum distance to the boundary of the convex polytope C de­.ned by the set of nlinear constraints in (11), Sj(X)=0, .j.
Relationship: reasoning
Domain: Hardware
Sentence 1: This means that overall execution time of this process will be eventually limited by the bank-level parallelism of PCM, not by computation.
Sentence 2: a group of PCM cells will fail after the following (line-.ll latency+write-back latency) period: (2 × # of segments × # of possible writes in parallel ×PCM write endurance), where 2 accounts for the worst-case la­tency due to potentially unsynchronized rotation between the mali­cious code and actual hardware.
Relationship: reasoning
Domain: Hardware
Sentence 1: Now, our ex­pectation that there will be an interruption at time T+1is the correlation function p(T+1).
Sentence 2: the expected value of Xtat time T+1given the history of testing up to time T is: EfXtj~xg xT+EfWT+1j~xgxp(T+1)(24) () xT+1+ r+xT;nT g(T+1)(25) .+G(T) xf(T+1) where (can be set such that p(t)-1at time t-1: 1 (--1:44 (26) ln(2) We use the stopping criterion similar to that in [23, 12] and not only for the next unit of testing time tbut also for the remaining expected coverage ( i.e.
Relationship: reasoning
Domain: Hardware
Sentence 1: These approximations are justi.ed by prior stress analysis data [2], [5], which have shown the correlation between the stress patterns predicted by 2D analytical techniques and the actual 3D stress patterns.
Sentence 2: while 3D models are required to capture effects such as TSV fatigue, 2D models are suf.ciently accurate to model effects of stress within the silicon, which is the subject of this work.
Relationship: reasoning
Domain: Hardware
Sentence 1: From this figure, it can be noted that (a) total standby power reduces rapidly with VSB due to reduction in memory leakage but at high VSB s, the power increases due to high transition energy consumption; and, (b) the leakage and transition energyof sleep transistor increases with GSize (=Wsleep/Wnmos) at high VSB corners.
Sentence 2: for each GSize we get a corresponding value of VSB where maximum power saving can be attained (Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: For the same PD length of 6 bits, the B-Cache at MF = 8 and BAS = 8 has a higher miss rate reduction than the design of MF = 16 and BAS = 4.
Sentence 2: we conclude that for the B-Cache, the design with MF = 8 and BAS = 8 is the best for the cache sizes of 8kB, 16kB, and 32kB.
Relationship: reasoning
Domain: Hardware
Sentence 1: Gustavo Sanchez, Diego Noble, Luciano Agostini Universidade Federal de Pelotas Grupo de Arquiteturas e Circuitos Integrados Pelotas, Brazil +55 (53) 3275 7432 {gfsanchez, dvnoble, agostini}@inf.ufpel.edu.br high computational cost, especially for high resolution videos which demands larger search windows.
Sentence 2: it is important to explore new solutions which bring a good tradeoff between objective quality, measured in Peak-to-Signal Noise Ratio (PSNR), and complexity.
Relationship: reasoning
Domain: Hardware
Sentence 1: In the PCM/DRAM hybrid memory, the DRAM plays the role of last level cache where the tags are managed at the granularity of DRAM row (4KB).
Sentence 2: in case of DRAM cache miss, a 4KB victim line is evicted (if dirty, after being written back to the PCM) and a new line is fetched from the PCM to the DRAM.
Relationship: reasoning
Domain: Hardware
Sentence 1: How­ever, pointers take up O(logN) storage, where N is the num­ber of nodes in the network, and a parent-child relationship in the list or tree does not necessarily map to a neighbor­ing tile relationship in the physical network.
Sentence 2: the number of actual hops required for a message to traverse the list/tree from the root to any of the leaves is bounded from above by DlogN , where D is the diameter of the network.
Relationship: reasoning
Domain: Hardware
Sentence 1: (Avoiding nested handler invocations) It is worth noting that the access of instr-count[2] within the handler of proc 1 will cause a miss, since the variable instr-count[2] will be in exclusive state in proc 2.
Sentence 2: the value of instr­count[2] will .nally be obtained via a data value reply from proc 2.
Relationship: reasoning
Domain: Hardware
Sentence 1: level 3() y9{ ,y10} y11,y12{ },{ }= level 4() y13,y14{ }= ¦ 4 Cell Library Construction All decomposition functions gi in the algorithm are selected as functions from a cell library.
Sentence 2: to guar­antee feasibility of a support-and depth-reducing decompo­sition the cell library must be suf.ciently complete.
Relationship: reasoning