sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Theconventionalapproachtoaddressthelocalityprob­lemforcaches(thatis,theproblemofmaximizingthenum­berofcachehits)istoemploycompileroptimizationtech­niques[8].Currentcompilertechniquesgenerallyworkunder theassumptionofafxedcachememoryarchitecture,and trytomodifytheprogrambehaviorsuchthatthenewbe­haviorbecomesmorecompatiblewiththeunderlyingcache confguration.However,thereareseveralproblemswiththis method.First,thesecompiler-directedmodifcationssome­timesarenotefectivewhendatadependencespreventnec­essaryprogramtransformations.Second,theavailablecache spacesometimescannotbeutilizedefciently,becausethe staticconfgurationofcachedoesnotmatchdiferentrequire­mentsofdiferentprogramsand/orofdiferentportionsof thesameprogram.Third,mostofthecurrentcompilertech­niques(adaptedfromscientifccompilationdomain)donot takeenergyissuesintoaccountingeneral.
Sentence 2: 4.3.2 Group-Reuse Analysis Groupreusesonlyexistamongreferencesinthesameuni­formreferenceset.Group-temporalreuseoccurswhendifer­entreferencesaccessthesamedatalocationacrosstheloop iterations,whilegroup-spatialreuseexistswhendiferentref­erencesaccessthesamecacheblockinthesameordiferent loopiterations.Algorithm2inFigure5exploitsasimplifed versionofgroupreusewhichonlyexistsinonelooplevel.
Relationship: neutral
Domain: Hardware
Sentence 1: It was experimentally determined that the polynomial of Vdd0.3 approximates the dependency of capacitance on voltage with a reasonable level of accuracy.
Sentence 2: a key feature of a power element is that it does not store power or energy numbers, instead stores the physical parameters (e.g., switching capacitance, resistances, current sources or effective leaking device width) that can be used to compute power at any process, temperature, and voltage condition.
Relationship: neutral
Domain: Hardware
Sentence 1: Permission to make digital or hard copies of part or all of this work or personal or classroom use is granted without fee Permission to make digital or hard copies of all or part of this work for provided that copies are not made or distributed for profit or personal or classroom use is granted without fee provided that copies are commercial advantage and that copies bear this notice and the not made or distributed for profit or commercial advantage and that full citation on the first page.
Sentence 2: currently 3.6 Mbps and around 1.5 Mbps are the common peak bit rates provided by mobile providers for downlink and uplink correspondingly.
Relationship: neutral
Domain: Hardware
Sentence 1: 6.2.3 Power savings with drowsy hybrid cache To generalize the evaluation of the hybrid drowsy cache option yet maintain a reasonable power comparison, we as­sume .xed static power of zero in the drowsy mode and only vary the wake-up and sleep transition time.
Sentence 2: the large write energy of MRAM and PRAM, in particular, suggests the need for special power-aware techniques beyond those required for SRAM and eDRAM.
Relationship: neutral
Domain: Hardware
Sentence 1: Static non-uniform cache architecture(S-NUCA)[25] andPri­vate[11] cachesrepresentthetwo endsof the cacheorganization spectrum.
Sentence 2: for eachcacheblock, bj , L3 Figure 5: Comparing Migration Policies -Performance speedup relative to the system with O2000P cache +CSPNoC keeps track of the L2 banks that have copies of bj .
Relationship: neutral
Domain: Hardware
Sentence 1: 4.ACCURACY In this section, wevalidatethatthe branch-on-random sbehavior is suitablefor instrumentationsampling.We consider thebranch­on-random s sampling suitable if it achieves accuracy similar to or better than software counter-based sampling.
Sentence 2: once again, jython performspoorlywiththecounters,but nowitis easiertoseethat pmd also showssomeof this pathologicalbehavior.
Relationship: neutral
Domain: Hardware
Sentence 1: We present the system in a test smart home browsing sce­nario, in which users browse/monitor the conditions (e.g., temperature, and CO2) and manage all the network devices within the house.
Sentence 2: we focus on a user s daily routines and satisfy the users demand by implementing a longest com­mon subsequence-based (LCS-based) learning algorithm to predict the next possible events.
Relationship: neutral
Domain: Hardware
Sentence 1: In [6], a simulation based analysis of the e.ect of the pres­ence of metal interconnects on the antenna characteristics is performed.
Sentence 2: the large reduction in the transmission gain is due to very high inter­ference from the metal structures e.ectively shielding the receiving antenna from the electromagnetic surface waves, which is the dominant mode of wave propagation (as ex­plained in Section 2).
Relationship: neutral
Domain: Hardware
Sentence 1: The last column shows the associated area overhead.
Sentence 2: some algorithm is needed to find the insertion scheme that maximizes Given a circuit with M DFFs, find a assignment {nj} (1=j=M) to replace the jth DFF by an SDT-DFF with nj delay units so that total Robustness Function defined in equation (2) is maximized, subject to timing constraint as defined in equation (5) and area constraint as defined in equation (6).
Relationship: neutral
Domain: Hardware
Sentence 1: For example, an integer set of (27 - 1,211 - 1,213 - 1,215 - 1,216 - 1,217 - 1) can be used as the moduli of an RNS.
Sentence 2: each digit yi of the mixed-radix number representation is a num­ber in lmi and satisfying 0 = yi < mi.
Relationship: neutral
Domain: Hardware
Sentence 1: Although we can generate a 3D result with the consideration of minimizing LD violation by apply­ing this method, as shall be seen in Section 7.2, this method su.ers from the lack of consideration on via count mini­mization, and therefore, its performance on total wirelength is not satisfactory.
Sentence 2: to calculate the virtual demand vde(ti) for LD type ti, our pseudo layer assignment method follows the sorted order to decide how many nets which have been routed through e and have LD types appearing before ti can be assigned to their preferred layers.
Relationship: neutral
Domain: Hardware
Sentence 1: 2 while (there exists more than one component) do 3 For each .... if both ends of .are in the same current component then color it RED and delete it from .. 4 If ......then goto Step 6 else if ......then color it BLUE and goto Step 6 else color them GREEN.
Sentence 2: ..... 1 Partition the edges of .into equivalence classes ............s. t. two distinct edges are in the same class iff they have the same edge cost.
Relationship: neutral
Domain: Hardware
Sentence 1: 3.2.1 Example Hereweusethetyperulestoshowthat speci.cpartsoftheexample programin the previous section are well-typed.We don tshow the entire type derivation,but wedo showhow both the T-GOTO and T-FALL rules are used.
Sentence 2: the rule must translate type t, valid for the target state, into an appropriate type t ', valid for the source state.
Relationship: neutral
Domain: Hardware
Sentence 1: HRI 11, March 6 9, 2011, Lausanne, Switzerland.
Sentence 2: the authors would like to especially thank Dr. Cindy Bethel, Autum Casey, Doug Dooley and David Hanson for their assistance with the design, Jessica Gonzales and Vasant Srinivasan with the production of the video, and Brittany Duncan, Jessica Gonzales, Victoria Groom, Josh Peschel, and Jesus Suarez for their helpful discussions.
Relationship: neutral
Domain: Hardware
Sentence 1: The values of iDD and iSS supply currents were sampled at 2 ps intervals, and the power was cal­ .N 1 iDD(k)+iSS(k) culated as P =(VDD - VSS) , were the Nk=1 2 sum is extended to the N supply current samples.
Sentence 2: the advantage of this structure in terms of power consumption is that, for a given input assignment, only two paths are switched.
Relationship: neutral
Domain: Hardware
Sentence 1: In [3] and [4] the authors argue that .ne­grained adaptive biasing and voltage interpolation based tech­niques can be applied to processors instrumented with recovery mechanisms to help mitigate the impact of within-die param­eter variations.
Sentence 2: for this step, we make the simplifying assumption that system performance loss due to N di.erent components is linearly additive.
Relationship: neutral
Domain: Hardware
Sentence 1: As can be seen, even when no principal components is utilized, the root mean square error is down to 0.5 from full s. That is due to the part of extracting the average variations of each pixel column to detect the mura­induced e.ects.
Sentence 2: if the pro.le of the random parameterisdecomposed to a weighted sum of theprincipal components,thedimension oftheoriginaldata(dimension being the number of sub-pixels for each process parameter) can be signi.cantly reduced in the PCA coordinate system by eliminating the less important principal components.
Relationship: neutral
Domain: Hardware
Sentence 1: To reproduce these .ndings, we designed a 22nm 6T SRAM cell (using the BSIM3 model, with parameters obtained from [27]) and studied its non-stationaryRTN patterns using MUSTARD.
Sentence 2: each trap has two possible states; so the system of N traps has 2N possible states, which can be encoded using N bits (with one bit per trap, where 0 denotes empty and 1 denotes .lled).
Relationship: neutral
Domain: Hardware
Sentence 1: If the metadata is stored alongside data in the same pages, then 29 blocks (and their metadata) could be stored per page (as in [4]).
Sentence 2: it does so by comparing the number of bits set to true against a con.gurable threshold level, T. If the number of set bits is = T, then the way is classi.ed as big, else classi.ed small.
Relationship: neutral
Domain: Hardware
Sentence 1: (i.e., c1908 s125), leads to timing violations at room tem­perature (i.e., D 25 = 2.53ns > Dnom).
Sentence 2: we show how the slack made available by over-constraining the synthesis can be exploited more e.ectively to reduce leakage, while guaranteeing tim­ing compliancy at the temperature corners provided by the technology library.
Relationship: neutral
Domain: Hardware
Sentence 1: [5] C. Claus, J. Zeppenfeld, F. Muller, and W. Stechele, Using partial-run­time recon.gurable hardware to accelerate video processing in driver assistance system, in Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE), 2007.
Sentence 2: the low device utilisation per­mits aggregation of another function on to the same hardware, which can run in complete isolation.
Relationship: neutral
Domain: Hardware
Sentence 1: An example that demonstrates the incremental re.nement capability of our algorithm is followed.
Sentence 2: lvr r0cvr w(evr ) = (6) lvl r0cvl )+ r0c0 (l2 -l2 )+ (dvl -dvr 2 vlvr w(evl ) Dv = {(dv,cv)} can be written with a single variable w(evl ) as l2 vl r0 c0 lvl r0 cvl dv(w(evl )) = dvl ++ , (7) 2 w(evl ) cv(w(evl )) = cvl + cvr + lvl w(evl )c0 + l2 vr cvr r0c0 .
Relationship: neutral
Domain: Hardware
Sentence 1: 5.3 Bank Idleness Analysis To better understand the energy behavior of memory banks, we identi.ed the most widely-used low-power mode.
Sentence 2: first, we gradually decay from one mode to another (i.e., to get to power-down, we go through standby and nap), though one could have directly transitioned to the .nal mode if we had a good estimate.
Relationship: neutral
Domain: Hardware
Sentence 1: Transition aware global signaling (TAGS) receiver reduces repeater count by generating its fast output signal at 30% swing of its slow input signal [9], which reduces power consumption as well.
Sentence 2: m5 3­mm 219.2 3 159.6 150.9 31.1% 1 66% 126.6 20.6% 4­mm 286.1 4 193.2 211.4 26.1% 1 75% 133.1 31.1% 5­mm 353.6 5 226.8 304.5 13.8% 1 80% 161.7 28.7% GLOBAL M6 6­mm 229.8 2 180.6 169.6 26.1% 1 50% 183.4 ­1.5% 8­mm 293.3 3 231 217.6 25.8% 1 66% 192.1 16.8% 10­mm 356.9 4 281.4 296.8 16.8% 1 75% 236.9 15.8% 0.5 Repeater  Assumer 1 Repeater Assumer  0.9 0.4 0.8 Average Energy (pJ) Average Energy (pJ) 0.7 0.6 0.5 0.3 0.2 0.4 0.3 0.1 0.2 0.1 0 0.05 0.1 0.15 0.2 Activity Factor (a) 0.25 0.3 0 0.05 0.1 0.15 0.2 Activity Factor (b) 0.25 0.3 Figure 7.Average energy (including clocking) per cycle for (a) 4­mm intermediate M5 wire, (b) 8­mm global M6 wire.
Relationship: neutral
Domain: Hardware
Sentence 1: Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Sentence 2: the addressing of tagless SRAMs makes them dif.cult to work with: Contiguity in the address space must be preserved, and distance between objects must be preserved.
Relationship: neutral
Domain: Hardware
Sentence 1: The C can be approximated by assuming that the capacitor is formed between a cylindrical CNT and an infinite planar electrode plate.
Sentence 2: is the displacement of CNT s elastic tip, E is the Young s Modulus, and I is the moment of inertia 4 4 and it can be expressed from I = f( d1 -d2 ) 64 , where d1 is the outer diameter and d2 is the inner diameter of the CNT.
Relationship: neutral
Domain: Hardware
Sentence 1: For a circuit with |G| gates and a layout with g spatial correlation grids, the complexity of our X cj.yj + e.z = µ + BT X + CT Y + e.z (2)D = µ + i=1 j=1 approach is O(g|G|), similar to the Gaussian case in [1].
Sentence 2: the number of independent non-Gaussian variables is the same as the number of cells in a circuit.
Relationship: neutral
Domain: Hardware
Sentence 1: Figure 3 shows the plots and it is clear that ARM Cortex-A9 takes the least amount of time compared to both PowerPCs and hence it can claim to be very e.cient.
Sentence 2: the TMAP mapping algorithm is de­scribed in [2] and can be integrated with the conventional Xilinx tool .ow which is explained in [1].
Relationship: neutral
Domain: Hardware
Sentence 1: [11] Young-Bae Ko and Nitin Vaidya.
Sentence 2: for the link caching algorithms, path optimality differs for the Link-NoExpand Link-Adapt-l.25 algorithms; these algorithms deliver a greater frac- tion of packets along optimal routes (path optimality 0) than do the other caching algorithms, yet also deliver a greater fraction of pack- ets along routes 6 and 7 or more hops longer than optimal than do the other algorithms.
Relationship: neutral
Domain: Hardware
Sentence 1: Design and Analysis of Thin-BOX FD/SOI Devices for Low-Power and Stable SRAM in sub-50nm Technologies Saibal Mukhopadhyay, Keunwoo Kim, and Ching-Te Chuang IBM T. J. Watson Research Center, Yorktown Heights, NY-10598 @us.ibm.com ABSTRACT This paper demonstrates viable device design options for low­leakage and robust SRAM in sub-50nm FD/SOI technology.
Sentence 2: if the leakage target is maintained by co-optimization of body-doping and back-gate bias instead of co-optimization of body-doping and   Maxmimum Ioff / Nominal Ioff 20 15 10 5 160 3 10 Maximum Ioff / Nominal Ioff 140 2 10 120 1 10 0 10-20 Peak doping density [ x1e17 1/cm^3] Peak doping density [x1017 1/cm3] (b) (a) (c)  Peak Halo doping [x1017 1/cm3] workfunction, a larger reduction in RDF can be obtained.
Relationship: neutral
Domain: Hardware
Sentence 1: This proves that the heuristic 1 is sometimes a bit of mis­leading, and the importation of the randomicity to heu1 can actually improve the performance.
Sentence 2: given a set of atomic propositions AP, the original model M can I II III IV Figure 1: An spurious counterexample be de.ned as a four-tuple M = (S,S0,R,L),where S is the set of states; S0 .S is the set of initial states; R .S ×S is the transition relation; and L : S .2AP is the labeling function.
Relationship: neutral
Domain: Hardware
Sentence 1: Ifthe cache memoryandthe victim cache are accessed sequentially, data that should be hold in a faulty L1 cache line is available in the RVC.
Sentence 2: load misses and store misses3 are kept in miss state handleregisters(MSHRforshort).Thoseregistersgroup requests to the same cache line to avoid issuing redun­dant requests to the upper level of the memory hierar­chy,and store thedatawhen theyarrivebecause thebus is typically narrower than a cache line.
Relationship: neutral
Domain: Hardware
Sentence 1: To reduce the bitline leakage power, we can employ a gated bitline precharge (or bitline isolation) technique.
Sentence 2: bzip2, gcc, mcf, parser, vpr, applu, art, galgel, lucas, and swim nearly the half of the entire SPEC2K workloads show negligible or no performance losses while achieving more than 80% leakage power reduction for the combined technique.
Relationship: neutral
Domain: Hardware
Sentence 1: In order to extract the maximum bene.t from the limited on-chip SPM space available, researchers considered the different data alloca­tion and SPM management strategies.
Sentence 2: these advantages include power/energy ef­.ciency, reduced cost, better performance, and real-time predictability, which are all vital metrics for today s embedded applications and sys­tems [3, 2, 15, 19, 4].
Relationship: neutral
Domain: Hardware
Sentence 1: After applying fnite difference schemes (For simplicity, we use the backward-Euler method.)
Sentence 2: rEFERENCES [1] T. -Y. Wang and C. C. -P. Chen, "Thermal-ADI: A Linear-Time Chip-Level Thermal Simulation Algorithm Based on Alternating-Direction Implicit (ADI) Method," in TVLSI, vol.
Relationship: neutral
Domain: Hardware
Sentence 1: 2) Modeling Battery Cycle Life: Rechargeable battery s cy­cle life (L) has a non-linear correlation with Depth-of-Discharge (D) of each cycle, which can be modeled with equation u1(1- L = u2(DR )u0e DD R ), where DR is the Depth-of-Discharge D corresponding to the rated cycle life (e.g.
Sentence 2: the impact is tolerable since WSN is usually not very performance critical.
Relationship: neutral
Domain: Hardware
Sentence 1: It works with highly-associative cache designs, like skew­associative caches [22] or zcaches [21], which have good analytical properties, namely, they provide a high-quality set of replacement candidates independently of the workload s access pattern.
Sentence 2: pCik=1 Sk 1 Ai = (4) P Si R· m k=1 Ck Stability: Depending on the sizes and churns of the partitions, sim­ply adjusting their apertures may not be enough to maintain their sizes.
Relationship: neutral
Domain: Hardware
Sentence 1: While support for composite devices has started appearing in computer operating systems like Linux and Microsoft Windows, it is poorly provided in smartphones and completely absent in pre-boot environments like the basic input/output system (BIOS) of computers.
Sentence 2: the management station can always reach a powered-on smartphone that is without Internet connectivity using a text message delivered through the short message service (SMS) component of the WWAN infrastructure.
Relationship: neutral
Domain: Hardware
Sentence 1: How­ever, the problems that led to the emergence of structured ASICs have not been solved and have in fact become more complex.
Sentence 2: first, we are inter­estedindelay variation withdifferent con.gurability choices rather thanactualperformance of thecircuit.Thenumberof routinglay­ers only affects the interconnect and this effect is captured in the average netdelay.
Relationship: neutral
Domain: Hardware
Sentence 1: 4: Repeat steps 5 to 9 till the decap solution converges or the total iteration number reaches the limit; 5: Use Latin hypercube (LHS) sampling method to generate M samples {C1,C2,...CM } from the N(µt-1,st-1) distribu­tion, and use acceptance-rejection approach to select K fea­sible samples that satisfy the constraints in (7); 6: For each circuit block, distribute the decap values to each candidate node based on the sensitivity values calculated in step 1; 7: Run transient power grid analysis for each sample and select top (best) Nelit samples (the samples that give the smallest noises).
Sentence 2: instead of using the abso­lute sensitivity values for decap budgeting, we can use the relative sensitivity information to assign the decap values within each circuit block.
Relationship: neutral
Domain: Hardware
Sentence 1: For the iir, a quick visual inspection of the assembly code reveals simple straight loop structures that are easily handled by the LMA, and since the LMA controller has less state than the DLB, it results in slightly less power.
Sentence 2: loop bu.ering techniques have been proposed [1, 3] for cap­turing such instruction loops in small bu.ers, thus reducing Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: neutral
Domain: Hardware
Sentence 1: [17] M. M. Gourary, S. G. Rusakov, S. L. Ulyanov, M. M. Zharov, K. Gullapalli and B. J. Mulvaney, A New Approach for Computation of Timing Jitter in PLL , in Proc.
Sentence 2: numerical procedures of timing jitter computation at the transistor level have been investigated in detail for autonomous circuits [8].
Relationship: neutral
Domain: Hardware
Sentence 1: It seems that for synthesizing large functions our approach has better potential than previously reported algorithms due to using decision diagrams as a basic representation of reversible functions, instead of truth tables or PPRM.
Sentence 2: permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: neutral
Domain: Hardware
Sentence 1: While sparse regression has been successfully applied to many practical applications, it still requires a large number of (e.g., 103) sampling points to fit a high-dimensional performance model [8].
Sentence 2: define the prior distribution for the late-stage model coefficients {aL,m; m = 1, 2, ..., M} by (12)-(13) and (25).
Relationship: neutral
Domain: Hardware
Sentence 1: Shao-Yun Fang Graduate Institute of Electronics Engineering National Taiwan University Taipei 10617, Taiwan yuko703@eda.ee.ntu.edu.tw  Wei-Yu Chen Graduate Institute of Electronics Engineering National Taiwan University Taipei 10617, Taiwan cweiyu@eda.ee.ntu.edu.tw Yao-Wen Chang Department of Electrical Engineering National Taiwan University Taipei 10617, Taiwan ywchang@cc.ee.ntu.edu.tw ABSTRACT Electron beam lithography (EBL) has shown great promise for photomask fabrication; however, its successive heating process centralizing in a small region may cause a severe problem of critical dimension (CD) distortion.
Sentence 2: then, the length of the shortest v edge in an optimal sub-Hamiltonian path is d2 + d2, where dr sr is the distance between the two sub.eld rows.
Relationship: neutral
Domain: Hardware
Sentence 1: It utilizes a basic description of the implemented algorithm which is created in early phases of the design .ow and requires only little extra work for the designer who spends most of the time in full-custom optimizations.
Sentence 2: the observed differences can be summarized as follows: negative weights in columns due to subtraction  shifted addends  addends are added into multiple columns if the underlying multiplication algorithm is sound all these differences will cancel out each other.
Relationship: neutral
Domain: Hardware
Sentence 1: Further, if TSVs have di.erent diameters or di.erent re­sistances than nominal, this would lead to di.erences in the associated thermal hot spots in the liquid, as explained in Section 4.
Sentence 2: by applying a test pattern to the TSVs of the die under test, we can detect the defective TSVs immediately by compar­ing the measured thermal-pro.le with the thermal-pro.le of the die with good TSVs.
Relationship: neutral
Domain: Hardware
Sentence 1: The FPD industry has been dominated by the liquid crystal displays (LCDs), which are advancing so rapidly that it seems difficult for other technologies to compete in the marketplace, despite all the enthusiasm and innovation emerging from research laboratories in both universities and industry for decades.
Sentence 2: the reduced power dissipation will also be able to lead to a lower temperature, resulting in a longer lifetime, especially important for large size displays [3].
Relationship: neutral