sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: 6.1 Subject Demographics Allofourtestsubjetswerebetweentheagesof15to35 forthefollowingreasons: therearealargenumberofpeopleinthisagegroupin andaroundauniversity;  peopleofasimilarageseemtohavesomeommon musialtastes.ItwouldhavebeendiÆulttoprovide enoughmusiforagroupwithdisparatemusialtaste withoutthetasktakinganunreasonableamountof time.
Sentence 2: theseondandthirdquestionsgavesomeinformationon thewaythepeoplewerelisteningtomusi.Toquestion 2manypeoplegaverelatively'lukewarm'responses(e.g.
Relationship: neutral
Domain: Hardware
Sentence 1: In conditions that the transitive fanout is excessively large and contains several hundred POs, we limit the number of POs kept to under 50.
Sentence 2: here, we will constrain each duplicated pin e. Since in CircuitConstrain, only satis.able assignments to e and X are consistent with a suit­able global function Fc(X)by proposition 3.4, constraining e to 0 or 1 provides a means to constrain the input X to the offset and on­set for Fc(X).
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Domain: Hardware
Sentence 1: [16] J.Hu, R.Marculescu, Energy-Aware Mapping for Tile-based NOC Architectures Under Performance Constraints , ASP-DAC 2003, Jan 2003.
Sentence 2: the minimum bandwidth for di.erent routing functions (DO -Dimension Ordered, MP -Minimum-path, SM -Split­tra.c across Minimum-paths, SA -Split-tra.c across All  600   BW (MB/s) 600 200 200 Disp (a) E.ect of Routing (b) Area-Power Exploration Figure 9: Design Space Exploration of a Topology Figure 11: SystemC Snapshot paths) is shown in Figure 9(a).
Relationship: neutral
Domain: Hardware
Sentence 1: [19] S. C. Woo, et al., "The SPLASH-2 programs: characterization and methodological considerations," in ISCA, S. Margherita Ligure, Italy, 1995, pp.
Sentence 2: since the home tile assignment policy used by the authors is not clearly indicated, we implement VH optimistically assuming perfect home tile placement, where the tile that makes the most accesses to a memory region is assigned to be the home tile for that specific region of the addresses.
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Domain: Hardware
Sentence 1: INTRODUCTION The supply voltage of CMOS circuits has been decreas­ing with technology scaling so as to manage active power consumption.
Sentence 2: for each circuit with its mixed allocation obtained in the third column, we simulate it with SPICE at nine different pro­cess corners (combination of best, nominal, worst D2D corner of low-and high­ respectively) at each of three different temperatures (25, 75, and 125 ) totaling 27 simulations, and list its maximum and minimum leakage at the .fth column.
Relationship: neutral
Domain: Hardware
Sentence 1: This e.ect is quite strong for single logic gates, causing a spread of 10X in some cases.
Sentence 2: a better approach, which we employ, is to .rst characterize every cell for all its in­put states; then, based on this pre-characterized data, and for the given frequency of use distribution for cells, .nd the signal probability setting which maximizes the mean leakage, e.ectively .nding the maximum of a plot such as Fig.
Relationship: neutral
Domain: Hardware
Sentence 1: Power Analysis To estimate the power consumption of the router mentioned previously, the following steps were performed: 1) synthesis by Synopsys Design Compiler, 2) place and route with buffer in­sertions at CTS using Synopsys Astro, 3) post place-and-route simulation by Cadence Verilog-XL to obtain switching activ­ity information of the router, 4) power analysis based on the switching activity using Synopsys Power Compiler.
Sentence 2: we selected .ve matrix computation pro­grams from NPB: Block Tridiagonal solver (BT), Scalar Pen­tadiagonal solver (SP), Conjugate Gradient (CG), Multi-Grid solver (MG), and large Integer Sort (IS).
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Domain: Hardware
Sentence 1: Each new iteration at time trequires a new set of variables Vbtand Vat.In this way, the number of variables needed grows with the num­ber of iterations of the .xed point procedure.
Sentence 2: columns 2 to 5 in this table list the statistics of the circuits, namely the number of primary inputs, primary outputs, registers and size, in literals.
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Domain: Hardware
Sentence 1: REFERENCES [1] IEEE Standard for Information technology, IEEE Std 802.3-2008, Section One , December 28th, 2008, Available at http://cisco.tu-sofia.bg/uploads/Additional/802.3.pdf.
Sentence 2: furthermore, SoCs have nowadays greatly advanced [3], [4] and started incorporating microprocessors as well as small FPGAs.
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Domain: Hardware
Sentence 1: The third approach places most points out of O, but tends to make the two classes too separable and overestimates P. All the ap­proaches have been experimentally evaluated and mixtures have been considered as well.
Sentence 2: the task is to approximate the performance function based on the knowledge of the training set, so that a point in the input space not part of the training set could be correctly classi.ed.
Relationship: neutral
Domain: Hardware
Sentence 1: The transmitter and the receiver were .xed at a constant separation distance of 5 m. The transmit power was varied such that the received SNR were recorded within the limits: [0-5) dB, [5-10) dB, [10-20) dB, [20-30) dB.
Sentence 2: the ranging process was performed with the receiver con.gured to record for 0.03 s -just long enough to capture the ranging signal along with its multipaths.
Relationship: neutral
Domain: Hardware
Sentence 1: [4]L.S.Nielsen,C.Niessen,J.Spars0,andK.vanBerkel.
Sentence 2: buffer Contents: Unprocessed Work Data Shifting Direction:  Period w[n] w[n-1] w[n-2]Wt r 0 63 16  1  109 16 2  142 32 3  120 64 4  58 48 5  11 11 Figure3:QRSAlgorithmSampleCalulations aslightlymodifedversionoftheaveragingtehnique.The modifationwasneessarybeausetheaveragingtehnique of[1]produesnon­integerratevalues(non­normalized), whihareimpratialiniterativeomputations.Therefore wemodifytheratealulationof[1]byseletingonlythe integerpartoftherate.thisleadstobuferover­fows,andanadditionalomparisonstepisneessarytopre­ventbuferover­fows.Theequationsusedforthemodifed averagingtehniquearegiveninEquations8,9,and10.
Relationship: neutral
Domain: Hardware
Sentence 1: Categories and Subject Descriptors B.8.1 [Performance and Reliability ]: Metrics Reliabil­ity, Testing, and Fault-Tolerance  General Terms Reliability  Keywords Crossbar array, reliable mapping, nano-PLA 1.
Sentence 2: if using the local mapping algorithm the output can be mapped into the candidate CM2, the output is removed from the unmapped list.
Relationship: neutral
Domain: Hardware
Sentence 1: C1, C2, and C3 are any arbitrary constants as log(1-Prob(SV )) long as C3 < 0, C2 <C3 ××(|AV |+1), log(1-Prob(LEH)) C2×log(1-Prob(LEH))-log(1-Prob(SV )) and C1 < ×(|AV |+1).
Sentence 2: as shall be seen later in this section, the problem addressed in [9] cannot exactly target on maximizing via yield.
Relationship: neutral
Domain: Hardware
Sentence 1: In this section, we limit our discussion to prior work at the circuit level.The .rst wave of research efforts in approximate circuit design focused on speci.c manual designs for simple arith­metic components such as adders [8], [12] [14] and multi­pliers [15].
Sentence 2: the maximum error magnitude, given in Equation 1, is de.ned as the absolute difference in magnitude between the outputs of the original and approximate circuits.
Relationship: neutral
Domain: Hardware
Sentence 1: As discussed in Section 2, the low cutoff frequency fL is determined by R and C2, while C1/C2 is constant.
Sentence 2: si FinFET Neural Amplifier HTFET Neural Amplifier Frequency [Hz] Frequency [Hz] HTFET Neural Amplifier 10-7 divider network (Rb) at Vcommon=Vout.
Relationship: neutral
Domain: Hardware
Sentence 1: Thus the domain of lattice values are T i = (0, 1, ··· , |M0|), for a marked graph, G =(V, E, M0).
Sentence 2: this algorithm has linear­time complexity in the program size and experimental results in­dicate that anyloss of accuracydue to this technique is negligible (< ±1%); the bene.t is a reduction in total design cycle time from several hours to a matter of seconds.
Relationship: neutral
Domain: Hardware
Sentence 1: We compare the results of our pin assignment algorithms amongst each other with a special emphasis on the results of the pin assignment algorithm of Section 4.4.This is reasonable because the algorithm of Section 4.4 finds the optimal pin assignment with respect to a linear objective.
Sentence 2: figure 1 (a) shows a pin assignment task for a graphics processor unit (GPU) placed on an AGP (Accelerated Graphics Port) board.
Relationship: neutral
Domain: Hardware
Sentence 1: TheMergeablecache .rstsplitstheaddressintotwoparts -the vTag and thePPID whichisthen expanded toprocess .ags.
Sentence 2: not only does the Mergeable cache decrease the number of DRAM accesses due to L2 misses, when a merged line is evicted from the L2 cache, that data is transmitted to DRAM in a single transaction.
Relationship: neutral
Domain: Hardware
Sentence 1: Applied to routability-driven global placements, Abacus improves the routed wirelength by 1% compared to Tetris.
Sentence 2: during the clustering, the iterative calculation of ec(c), wc(c), and qc(c) is done in the functions AddCell (line 24-26) and AddCluster (line 29-31).
Relationship: neutral
Domain: Hardware
Sentence 1: Tools like Ubertooth[5,6,7] canbeusedtodeterminetheMAC ad­dress of undiscoverabledevices, which canin turnbefedinto FTS4BT[2], a commercialproductthatis ableto synchro­nize with victimBluetoothdevices,follow theBluetoothfre­quency hopping sequence, and thereby sni.
Sentence 2: a set of character sequences based on a cursor clicking topology can be derived.
Relationship: neutral
Domain: Hardware
Sentence 1: As shown in Figure 14, when m is doubled, throughputs increase by roughly a factor of 1.2 for non-pipelined designs and by roughly a factor of 2 for pipelined designs.
Sentence 2: each GF(2m) multiplier takes in an m-bit block bji multiplies it with an arbitrary m-bit coefficient cj and produces a (2m - 1)-bit extended form polynomial.
Relationship: neutral
Domain: Hardware
Sentence 1: [2] M.K.Qureshi,J.Karidis,M.Franceschini, V. Srinivasan, L. Lastras, and B. Abali, Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling, in Proceedings of MICRO 09, 2009, pp.
Sentence 2: 1: Check current mapping state.
Relationship: neutral
Domain: Hardware
Sentence 1: Likely, the word1 is 16-bit narrow-width value and the number of 0 s in the fault bits is 1 , fitting well into the dedicated cache word subblock.
Sentence 2: according to our simulation results, the ratio of narrow-width values is significantly high (over 75% ofaccessed data in the L2 cache, on average), encouraging the exploitation of the narrow-width value feature in LLCs.
Relationship: neutral
Domain: Hardware
Sentence 1: The main advantage of the proposed circuit is that, using autozero offset cancellation, very small input offset voltage can be achieved, even for all the MOS devices be implemented in its minimum size defined by the technology.
Sentence 2: a High­Speed Low­power CMOS Comparator using Auto­ Zero Offset Cancellation technique Sandro A. P. Haddad University of Brasília Faculty of Gama (UnB­FGA) PO Box 8114, CEP: 71405­610 Gama, DF, Brazil sandrohaddad@unb.br ABSTRACT A high­speed, small­area and accurate CMOS comparator for low­power applications is presented.
Relationship: neutral
Domain: Hardware
Sentence 1: prof. Maria Marinova, PhD, Department of Computer Systems and Technologies, Technical University of Sofia, branch Plovdiv, e-mail: m_marinova@tu­plovdiv.bg prof. V. Lazarov, European Polytechnic University, e-mail: vladimir.lazarov@epu.bg
Sentence 2: if an execution pattern involves many more instruction fetches than data fetches, then the cache will tend to fill up with instructions, and if an execution pattern involves relatively more data fetches, the opposite will occur.
Relationship: neutral
Domain: Hardware
Sentence 1: Since it is not feasible to do an Iddq measurement for every possi­ble memory content, only those cases are considered where the coupled cells are adjacent.
Sentence 2: proceedings of the Design,Automation and Test in Europe Conference and Exhibition (DATE 03) 1530-1591/03 $17.00 &#38;#169; 2003 IEEE
Relationship: neutral
Domain: Hardware
Sentence 1: Our results with the MCNC91 benchmark suite show that the incorporation of Crossbar Cells into standard MOSFET cells provides a significant reduction in circuit area (4X) and power (3X) at the same lithographical level, with comparable speed, if the circuits are optimized for area.
Sentence 2: (6) int fet on Then we can rewrite (6) as r , t =t (1+ 2P nwp n) ; (7) LH max int, p io , R on p the delay of a crossbar logic circuit is O(n).
Relationship: neutral
Domain: Hardware
Sentence 1: 4 Summary and Future Directions This work presents our preliminary studies for minimizing the transmission and energy overhead of utilizing Miracast service on smartphones.
Sentence 2: the num­ber of frames required to satisfy the dynamicness of a dance-genre music video can be very different from that of a video-based lec­ture, in which the instructor (mostly) stands still in the center of a blackboard.
Relationship: neutral
Domain: Hardware
Sentence 1: The second problem is that the goal of the genetic al­gorithm was to obtain the best possible performance; that is, to make the system schedulable minimising the system utilisation at the same time.
Sentence 2: in B. Ribeiro, R. F. Albrecht, A. Dobnikar, D. W. Pearson, and N. C. Steele, editors, Adaptive and Natural Computing Algorithms, pages 462 465.
Relationship: neutral
Domain: Hardware
Sentence 1: [9] G. Li and N. R. Aluru, J. of MEMS, 11(3), 245-254, 2002.
Sentence 2: when non-linearity comes in (due to large deformation), the resonant frequency is found to increase for the .xed-.xed beam cases with gaps 2.0µm and 4.0µm.In these cases, the spring-hardening effect due to mechanical forces is larger than the spring-softening effect of the electrical forces.
Relationship: neutral
Domain: Hardware
Sentence 1: Various mode change andresource arbitration protocols, and corresponding timing analysissolutions were proposed for either multi-mode or multi-core real­time applications.
Sentence 2: the WCRT of a task ti is given by the largest response time Ri of any of the q activations (q=1..Qi, Qi =min{q=1|wi(q)<d-(q +1)}) that i lie within the MTBW wi(q), i.e.
Relationship: neutral
Domain: Hardware
Sentence 1: For instance, [16] presents a Figure 5: IGF area estimation  Figure 7: IGF throughput (image size: 1024x768) 20-iterations convolution with a 3x3 kernel working on a Xilinx Virtex-II Pro at 13.5fps with 1024x768 images, and at less than 5fps with Full-HD images, while our architecture achieves, on the same FPGA, up to 35fps on Full-HD images.
Sentence 2: when performing two subsequent itera­tions, the intermediate results produced by the .rst one have to be stored (typically in an on-chip memory for performance reasons), since they will be the input to the second iteration.
Relationship: neutral
Domain: Hardware
Sentence 1: We observe that triple-Vth reduces leakage with respect to dual-Vth (without biasing) by ~ 8% on average.
Sentence 2: the primary reason for leakage variability reduction due to gate-length biasing is that due to the short channel e.ect, variations in gate-length translate to smaller leakage varia­tions when the gate-length is larger.
Relationship: neutral
Domain: Hardware
Sentence 1: When applying all stochastic algorithms concurrently, the yield loss is re­duced to 5pp10K (a 10X reduction) with the mean delay re­duced by 6.2% and the standard deviation reduced by 7.5%.
Sentence 2: is the tradeoff parameter between timing and connection, with a value of 0.75 adopted in T-VPack.
Relationship: neutral
Domain: Hardware
Sentence 1: For input transients with duration smaller then 2.5 times tp, the output voltage does change less than VDD /2, i.e., the transient pulse is not propagated to the (n+1)th stage.
Sentence 2: if the current induced by the particle strike is high enough the on-transistor can not balance the current and a voltage change at the node will occur.
Relationship: neutral
Domain: Hardware
Sentence 1: But, what is important to note here is that, while a small degradation in the fair speedup metric (e.g., below 1) is tolerable (although not preferred as we would like to maximize the fair speedup metric), we cannot tolerate any degradation above a certain threshold (QoSTh).
Sentence 2: 2.1 Metrics of Interest In this paper, we use three metrics (similar to those used in [6] and [26]): (1) A weighted speedup metric (WS) that quanti.es the improvement in overall system throughput (across di.erent applications of the multiprogrammed work­load); (2)Afair speedup metric (FS) that balancesbothper­formance and fairness; and (3) A QoS metric that measures theper applicationperformance degradationwithrespect to the baseline (equal resource share) case.
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Domain: Hardware
Sentence 1: In the algorithm of [2], the number of shifts is allowed to be at most bw + 1, where bw is the maximum bit-width of the constants to be implemented.
Sentence 2: iNTRODUCTION Multiplication of a variable by a set of constants, generally known as Multiple Constant Multiplications (MCM), is essential in many Digital Signal Processing (DSP) applications such as, digital Finite Impulse Response (FIR) .lters (illustrated in Figure 1), Fast Fourier Transforms (FFT), and Discrete Cosine Transforms (DCT).
Relationship: neutral
Domain: Hardware
Sentence 1: Overall speaking, Stage 1 focuses on the overall optimization of the total delay and via count of all nets, it can get relative good result for all nets for delay and via count, but may ignore the bad delays of some long nets.
Sentence 2: available: http://archive.sigda.org/ispd2008/contests/ispd08rc.html [8] M. Cho, K. Lu, K. Yuan, and D. Z. Pan, BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router, Proceedings of International Conference on Computer-Aided Design, pp.
Relationship: neutral
Domain: Hardware
Sentence 1: To keep the gain high by using larger value resistors, the cur­rent .ow needs to be reduced.
Sentence 2: 4 shows the measured output power versus input power and the measured input-referred 1-dB compression point (IP1dB) is -17.8 dBm, while the output-referred 1-dB compression point (OP1dB) is -5 dBm.
Relationship: neutral
Domain: Hardware
Sentence 1: Notice that, in all three cases, the raised hy­ (i) (i) perplane Dhas a constant term .= P,and .= 0, for i 0 j 1 = j = n. Recall also that the peak corner is at the origin Cp =(0,0,··· ,0), thus for each of these cases: Di (Cp)= .0 (i) = P (27) Therefore, the raised hyperplane Di satis.es the third criterion of section 3.4.1 for all the three cases.
Sentence 2: the true reason for this is the exponential complexity of traditional corner analysis.
Relationship: neutral
Domain: Hardware
Sentence 1: Thissolutionisnotoptimalfromthepowerdissipationview­point.Assume,forthesakeofillustration,thatthedynamic accessprofleisthatshowninFigure1(b).Asmallsubsetof theaddressesintherangeisveryhot"(i.e.,ithaslarger(i) valuesforallitsaddresses).Apower-optimalpartitionedmem­oryorganizationisshowninFigure1(c).Itconsistsofthree memoriesandamemoryselectionblock.Tworelativelylarge cutscontainthetopandbottompartoftherange,whilethehot addressesarestoredintoasmallmemory.Theaveragepower inaccessingthememoryhierarchyisdecreased,becausealarge fractionofaccessesisconcentratedonasmall,power-efcient memory.
Sentence 2: theydescribedapartitionedSRAMmodel(calledsegmented confguration),whichisanalogoustoours,andstudiedpower modelingforpartitionedmemoriesindetail[14].they didnotproposeanyautomaticsearchtechniquesforfndingop­timalpartitioning:Theyjustfocusedonprovidingdesignspace explorationsupporttosystemdesigners.
Relationship: neutral
Domain: Hardware
Sentence 1: Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Sentence 2: several studies [5, 7, 8, 21, 25] suggest less efficient detections to trade-off against not requiring additional loads.
Relationship: neutral
Domain: Hardware
Sentence 1: In order to extract the lifetime information for global vari­ables, we initially add up individual liveness intervals inter­vals (i.e., total cycles of read-to-read and write-to-read peri­ods) for each global memory address that is accessed during the program execution.
Sentence 2: soft errors can potentially lead to system failure only if element s stored value is live at the time of fault strike.
Relationship: neutral
Domain: Hardware
Sentence 1: p minn (soj + sij Xi), exact PSTA j=1i=1 (8) where nis the number of hyperplanes that de.ne the piecewise planar surfaces of the max and min operations, and -1 = Xi = 1 for all i. III.
Sentence 2: timing graphs for (a) Inverter, and (b) 3-input OR gate the novelty of this paper is in its proposed appli­cation, where we extend the use of such distance metrics to the timing veri.cation of large logic circuits, which, to our knowledge, was never done before.
Relationship: neutral
Domain: Hardware
Sentence 1: Givenafullyspecifedsoftwarepipelineschedule,hard­warecostsmaybefurtherdecreasedwhenageneralregister flestructureisreplacedbyacustomizedShiftQthatisspe­cializedtoaspecifcrepeatingcomputationalpattern.In addition,suchShiftQsmayalsobespecializedinbitwidth aseachregisterelementwithintheShiftQneedstobeonly aswideasthewidestoperandthatitmustsupport.
Sentence 2: 5.3 Results TheloopacceleratorsdesignedbyPICO-NPAarenon­programmable,highlyspecializedhardwarestructuresde­signedtoexploitveryhighlevelsofinstruction-levelpar­allelism(ILP)intheapplications.Therangeofthrough­putachievedintheapplicationsreportedherewasfrom1 op/cycleforfratII=8,to128ops/cycleforatmcellatII=1.
Relationship: neutral
Domain: Hardware
Sentence 1: [67] E. Wenzel, M. Arruda, D. Kistler, and F. Wightman, Local­ization using non-individualized head-related transfer func­tions, J. Acoustical Soc.
Sentence 2: the analytical func­tions indicate approximations in Medwin s assumptions for second-and higher-order diffraction.
Relationship: neutral
Domain: Hardware
Sentence 1: In FPGA device families such as Xilinx Virtex [26][27] and Altera FLEX [2], a 4-LUT with 16 memory cells is used to implement a sum output bit of a 1-bit addition; in ATMEL AT40K devices [4], Altera Stratix family [3] or Low-Power FPGA from Berkeley University [9], 16 con.guration bits in total are used to implement a 1-bit addition, i.e.
Sentence 2: the commercial FPGAs are characterized in the following way: Xilinx Virtex: Npins=28, Altera Stratix: Npins=53, Atmel AT40K: Npins=6.
Relationship: neutral
Domain: Hardware
Sentence 1: 6 X 9 0 0 0 0 ror beyond the inherent error from RTL macromodels.
Sentence 2: first last value data FSM Controller 1 Power Model + >1 reg_mid reg_c0 reg_c1 reg_c1 reg_first reg_last reg_out Registers Power Model Bus1 Bus2 Bus3 addr out Power Aggregator Power Power Power Power Model Model Model Model Power Strobe Generator Total Power Figure 1: An example RTL circuit enhanced for power emulation Power strobe generation is similar to clock generation and is done sep­arately for each clock domain in the design.
Relationship: neutral
Domain: Hardware
Sentence 1: 2.1 Self-Reverse Bias (SRB) This method, which is schematically shown in Figure 1, is one of the important approaches in reducing the subthreshold leakage current during Standby mode.
Sentence 2: a. Khaki-Firooz Microsystems Technology Labs., Massachusetts Institute Of Technology khaki@mtl.mit.edu During the standby mode of the operation, the subthreshold power consumption is the most important component.
Relationship: neutral
Domain: Hardware
Sentence 1: DEVICE AND CIRCUIT MODELING 2.1 FPAA Device Modeling A .oating-gate element is a polysilicon layer that has no contacts to other layers; this .oating-gate can be the gate of a MOSFET and can be capacitively connected to other layers.
Sentence 2: inter-CAB/intra-column intercon­nect limitations have to be adjusted accordingly.
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