sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Another way to deal with this problem is to assign a high cost to the misclassi.cation of the minority class and a low cost to the misclassi.cation of the majority class while trying to maximize the overall ac­curacy.
Sentence 2: it is desirable to have a metric that gives high prediction accuracy over the minority class, while maintaining reasonable accuracy for the majority class.
Relationship: entailment
Domain: Hardware
Sentence 1: In comparison to most of the previous SPM related work, our ap­proach is based on the recomputation of off-chip data, needed by the current computation, by using the data that currently resides in on-chip SPMs, instead of fetching it from off-chip memory, if doing so is bene­.cial in terms of performance.
Sentence 2: we substitute recomputation for off-chip data access.
Relationship: entailment
Domain: Hardware
Sentence 1: Our main goal is to verify whether M0 behaves exactly as M1.This means that for all possible input sequences, M0 and M1 produce the same sequences of output values and eventually, when the re­spective reset states are re-visited, they are visited with the same storage element values.
Sentence 2: for every computation from the reset state back to itself of one FSMD, there exists an equiv­alent computation from the reset state back to itself in the other FSMD and vice-versa.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we face the previously described problems by pre­senting an automatic High Level Synthesis (HLS) .ow that, given a processing algorithm, generates a set of hardware implementations that are Pareto-optimal with respect to cost and performance (mea­sured as throughput).
Sentence 2: the .ow: 1) takes a high level description (C language) of the algorithm as input, 2) systemati­cally analyses data dependencies between elements of subsequent iterations, 3) generates synthesizable VHDL descriptions of all the cones that are best suited to custom .ne-grained programmable de­vices (e.g., FPGAs), 4) ef.ciently explores the cone architecture solution space with a minimum number of synthesis runs.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper we present techniques for the transformation of behav­iors of selected hardware blocks into equivalent software imple­mentations.
Sentence 2: we describe SOFTENIT, a methodology for softening of SoC hardware, that takes as input, a partitioned and mapped system description, and generates a modi.ed system architecture in which the fraction of system functionality imple­mented using embedded software is signi.cantly boosted.
Relationship: entailment
Domain: Hardware
Sentence 1: = The product Zi, j(t)= Vi(t) ·Vj(t) of two orthogonal basis noise bits is orthogo­nal to Vk(t) (k = 1, 2, ··· , M).
Sentence 2: this property was used [3] to realize a logic hyperspace.(Zi, j(t),Vk(t)) =0 DEFINITION 3.
Relationship: entailment
Domain: Hardware
Sentence 1: 5 7 9 11 13 15 17 19 21 LAB:Medium Memory Block In the initial version of LUT RAM, the focus was entirely on low cost, and consequently as much functionality as reasonably possible was left in soft logic.
Sentence 2: the Stratix III device included 2 flip-flops per ALM, or 20 per LAB, which was just sufficient for the write data registers.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.5 Hardware Output Control DataSafe hardware checks to see whether copying the data to another memory location or output device is allowed, or whether writing to memory locations within the SDC is allowed, according to the hardware tags.
Sentence 2: hardware checks if a memory location to be written to is a memory-mapped output device, and enforces output control according to the tag of the word being written.
Relationship: entailment
Domain: Hardware
Sentence 1: Architectural design decisions that reshape the slack dis­tribution by devoting less area to regular structures or mov­ing regular structures o. the critical path can enable more overscaling and increase energy e.ciency for timing spec­ulative processors.
Sentence 2: additional overscaling enabled by architectures with smaller regular structures can outweigh the energy bene.ts of regularity when designing a resilience-aware architecture.
Relationship: entailment
Domain: Hardware
Sentence 1: Since set-associative caches can avoid the thrashing problem of direct-mapped caches, MSA exploits this idea and activates more ways only when it can be identi.ed the situation has occurred that a piece of code repeatedly alternates between accessing different locations that map to the same cache set [20].
Sentence 2: mSA increases the number of active ways of a cache block only if the data of current miss has be accessed before within the time window.
Relationship: entailment
Domain: Hardware
Sentence 1: Moreover, considering the relationship between soft error rates, critical charge, supply voltage and the number of particles in the cosmic rays [14, 19, 30], we proposed an exponential fault rate d(1-f) model: g(f)= .0101-fmin where the exponent d (> 0)is a constant, indicating the sensitivity of fault rates to DVFS.
Sentence 2: reducing the supply voltage and frequency for energy savings re­sults in exponentially increased fault rates.
Relationship: entailment
Domain: Hardware
Sentence 1: Design space of the dual-element memory cell is studied and it shows that the trade-o.s among the energy, speed, and distingushi­ablility should be explored for di.erent design objectives.
Sentence 2: we show that under the energy-driven optimiza­tion, the proposed dual-element memory achieves the same programming speed and distinguishability as conventional single-element memory but the energy consumption can be reduced by up to 80%.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that, to avoid being trapped in local optimal points, we use e-greedy to select the coarse grid lines for p × q partitioning.
Sentence 2: we set up a probability parameter e (e.g., e = 10%), and hence we have the probability of e to select a grid line randomly, instead of the one with largest metric de.ned in Eq.
Relationship: entailment
Domain: Hardware
Sentence 1: While previous work has proposed new security mechanisms for control systems, few of them have explored new and fundamen­tally different research problems for securing control systems when compared to securing traditional information technology (IT) sys­tems.
Sentence 2: the sophistication of new malware attacking control systems malware including zero-days attacks, rootkits cre­ated for control systems, and software signed by trusted certi.cate authorities has shown that it is very dif.cult to prevent and detect these attacks based solely on IT system information.
Relationship: entailment
Domain: Hardware
Sentence 1: (2) When valid pages of the two blocks are written back to the caching bu.er (with new primary and over.ow blocks), they are written back in an LRU fashion.
Sentence 2: valid pages in the over.ow block are written back to the bu.er earlier than those in the primary block, and valid pages in the over.ow block are written back to the bu.er from the bottom to the top of the over.ow block.
Relationship: entailment
Domain: Hardware
Sentence 1: (15) i=1 I(.j) × w(.j , µ , s) It is obvious that the calculation of si depends on the optimization result µ from (14).
Sentence 2: the poten­tial error from the optimization of µ can propagate into the computation of si and lead to completely misleading result­s, which is especially undesired because the performance of importance sampling is highly sensitive to the sampling dis­tribution.
Relationship: entailment
Domain: Hardware
Sentence 1: As can be seen in Figure 6, RALM NSEL reduces the energy consumption by 63.7% and 22.6% on average over BASELINE and DECAY, respectively.
Sentence 2: for MPGdecoder and MPGencoder, RALM NSEL can reduce the energy consumptionbyupto 19.3%and 44.2%overDECAY while the SPLASH2benchmarks show smaller reduction.
Relationship: entailment
Domain: Hardware
Sentence 1: The GCM is a graphical speci.cation language that was devel­oped to to aid designers in creating SBML models of genetic cir­cuits by providing a method of describing them at a higher level of abstraction.
Sentence 2: in a GCM, only important species and their in.uence upon each other are represented which greatly re­duces the model size.
Relationship: entailment
Domain: Hardware
Sentence 1: This transistor is identi.ed by measuring the increase in the total average leakage, Lkg, with respect to the delay reduction, D, of the critical path when such a change is made.
Sentence 2: we evaluate D Cost = (8) Lkg The transistor with the minimum (most negative) cost pro­vides the largest delay reduction for the smallest increase in leakage power, and is selected for assignment to ToxLo.
Relationship: entailment
Domain: Hardware
Sentence 1: We used a single test template that speci.es the scenario requirements as is.
Sentence 2: the test template speci.es that the .rst instruction is a load (from the set of loads in the experiment) and  TABLE I EFFORT AND SUCCESS RATE FOR THE THREE GENERATION SETTINGS Setting Stream Basic Expert Test templates 1 1 7 Effort 10 min 10 min 3 hours Success Rate 97% 59% 92% the second instruction is a store whose memory operand has the same address as the memory operand of the load.
Relationship: entailment
Domain: Hardware
Sentence 1: Compared to Table 4, the boundaries for both global/intermediate and intermediate/local are reduced due to the reduced number of long interconnects.
Sentence 2: a higher portion of random in­terconnects can be assigned to the global and intermediate layers Table 7: Modules and their correspondent microarchitecture, gate count, and power under different repeater and .ip-.op insertion models.
Relationship: entailment
Domain: Hardware
Sentence 1: For this hierarchy, we also see that ordering provides less bene.t over grouping the performance of L1 and L2 grouping with ran­dom ordering (L1 &#38; L2 + RO) is very similar to recursive schedule.
Sentence 2: conv and mmm, which exhibit sensitivity to order­ing on the Throughput Processor, now barely bene.t from order­ing.
Relationship: entailment
Domain: Hardware
Sentence 1: For a total BRAM count of NB at the system level, there is a tradeo.
Sentence 2: between the number of instantiated CCs, NC C , and the number of BRAMs, R, allocated per CC: R = L NB J. NC C Unlike traditional graph coloring implementations where the number of colors (resource units), R, is a .xed constraint, the number of allocated BRAMs per CC, in TDGC, can range across a set of values that ful.ll the previous constraint on R. by modifying the CTA region schedule we can generate di.erent HRG con.gurations that have di.erent Algorithm 2: TDGC Flow overview Input: HRG: Gin, Throughput: TPci Output: New HRG: Gout 1 arrs .
Relationship: entailment
Domain: Hardware
Sentence 1: All arithmetic for these GF(2)-linear RNGs is performed modulo 2 and can be implemented very ef.ciently in hardware using elementary bit-wise operations such as exclusive-ORs (XORs), bit­masks and shifts.
Sentence 2: we focus on GF(2)-linear RNGs with extremely long periods ( 219937 -1, although we de.ne long as 21024) and proven statistical properties.
Relationship: entailment
Domain: Hardware
Sentence 1: Low-power Dual-element Memristor Based Memory Design Dimin Niu , Yiran Chen , Yuan Xie Pennsylvania State University, University Park, PA Seagate Technology, Bloomington, MN, USA {dun118, yuanxie@cse.psu.edu} yiran.chen@seagate.com ABSTRACT Recently, the emerging memristor device technology has at­tracted signi.cant research interests due to its distinctive hysteresis characteristic, which potentially can enable novel circuit designs for future VLSI circuits.
Sentence 2: char­acteristics such as non-volatility, non-linearity, low power consumption, and good scalability make memristor one of the most promising emerging memory technologies.
Relationship: entailment
Domain: Hardware
Sentence 1: Figure 8: Maximum Allowable Headroom in Synthetic Applications Table 2: DIMSim Performance Analysis for JPEG and H264 Benchmarks rations are simulated for a higher miss rate.
Sentence 2: when much earlier time for smaller miss rate hence the signi.cant vari­the given miss rate is smaller, only a few large cache con.gurations ations in the simulation time.
Relationship: entailment
Domain: Hardware
Sentence 1: , n}, we denote v(S) as the game surplus if played by coalition S. Shapley value de.nes the only way to distribute the the grand coalition surplus v(N) among the n players that satis.es four simple axioms: E.ciency, Symmetry, Dummy, and Additivity [1].
Sentence 2: the share received by player i, fi(v), is uniquely given by v(S .
Relationship: entailment
Domain: Hardware
Sentence 1: STATISTICS OF TA The mean and variance of TA can be obtained using a numerical di.erentiation of HA(s).
Sentence 2: the cdf is de.ned as FTA (T)=Pr(TA <T), which is the probability of acquisi­tion given an allowed search time T. when TA >T, the acquisition failed within the given time T. An accurate cdf evaluation formula using the Gamma approximation [2] is given by 1 FTA (T)= G(a,T/b) (31) G(a) 2 where a= TA/s2 , b= s2 /TA,and G(x,y)is the incom- TA TA plete gamma function.
Relationship: entailment
Domain: Hardware
Sentence 1: Hence multiple vias are often used, whereby the geometry of the via array is very significant: Multiple vias must be organized such that the resulting current Attention must also be paid to bends in interconnects.
Sentence 2: 90-degree corner bends must be avoided, since the current density in such bends is significantly higher than that in oblique angles of, for example, 135 degrees (Figure 8)    Figure 8.
Relationship: entailment
Domain: Hardware
Sentence 1: On the other hand, architectural optimizations can be used to increase the e.ciency of a design that employs error resilience.
Sentence 2: one would make di.erent, sometimes counterintuitive, architectural design choices to  Figure 6: The goal of a gradual slack [18] or soft processor [16] design is to transform a slack distribution characterized by a critical wall into one with a more gradual failure character­istic.
Relationship: entailment
Domain: Hardware
Sentence 1: While these previous works propose useful solutions, in this paper we focus more on the synthesis problem.
Sentence 2: given this temperature inversion e.ect, we propose a new synthesis strategy for multi-Vth circuits that will au­tomatically produce temperature-invariant designs, thereby guaranteeing that the circuit will meet speci.ed timing con­straints for all allowable operating temperatures.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.3 Bundling the 3-pin Nets For a 3-pin net with pins p1, p2 and p3, we know its x wire length follows: H P W Lx = max(xp1 , xp2 , xp3 ) - min(xp1 , xp2 , xp3 ) = (|xp1 - xp2 | + |xp2 - xp3 | + |xp3 - xp1 |)/2 Its y wire length has the same property.
Sentence 2: the HPWL of a 3-pin net is equal to half of the sum of the Manhattan distances between every pair of pins in this net.
Relationship: entailment
Domain: Hardware
Sentence 1: We only consider pre­dicting the values of load instructions that have -in the past-satis.ed the equation: -MaxAV D = AV D(L) = MaxAV D where MaxAV D is a constant set at the design time of the AVD predictor.
Sentence 2: in order to be identi.ed as an address load, the data value of a load instruction needs to be close enough to its effective address.
Relationship: entailment
Domain: Hardware
Sentence 1: To support full predication, every instruction has a condition as an additional 978-3-9810801-8-6/DATE12/ c @ 2012 operand, which de.nes the predicate of the instruction.
Sentence 2: the instruction is executed if the predicate is true (i.e., the condition is met); otherwise, the instruction is suppressed.
Relationship: entailment
Domain: Hardware
Sentence 1: from RTL simulation to gate­level simulation), and also before and after a series of continuous design changes at the same abstraction level.
Sentence 2: except the very 1st simulation, there are three kinds of earlier simulation prior to the current simulation; i) higher-level simulation, ii) same-level simulation before a design change, and iii) same-level simulation without any design changes.
Relationship: entailment
Domain: Hardware
Sentence 1: To keep the analysis time manageable, only the critical area with a radius equal to half the pitch of the corresponding layer is used since this quantity is proportional to the weighted critical area for most defect sizes of interest.
Sentence 2: radii of 0.08µm are used for metal layers 2-6, while radii of 0.15µm are used for the metal layers 7 and 8.
Relationship: entailment
Domain: Hardware
Sentence 1: Also, Fig.9 shows that the error in the measurements decreases as M increases, achieving sensitivities of fractions of dBm very quickly.
Sentence 2: because of this important feature, the evaluator does not limit the dynamic range of the 100 120 140 1000 2000 3000 4000 5000 6000 7000 8000 9000 FFT bin Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: Experimental results reveal thatthe newly proposed algorithmis ca­pableof enhancing detailed routing routability.
Sentence 2: gDRouter reduces number of unassigned global segments by 90% for ISPD98 [3] derived testcases and around 60%for ISPD05/06 [4,5] derived test­cases with 2.9× runtime overhead.
Relationship: entailment
Domain: Hardware
Sentence 1: The number of exe­cution cycles is a positive contributor for the high-end server for three benchmarks though, namely kmeans, specjbb and x264.
Sentence 2: the high-end server bene.ts signi.cantly from the larger caches and branch predictor as well as the larger width com­pared to the low-end server for these workloads.
Relationship: entailment
Domain: Hardware
Sentence 1: The proposed work relaxes this assump­tion in order to push the boundaries of achievable energy­e.ciency.
Sentence 2: most algorithmic low-power ap­proaches focus on heuristics to reduce the number of macro- Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: entailment
Domain: Hardware
Sentence 1: As mentioned previously, if the solution L generated by the ba­sic SDS is not optimal, we only need to shape the intersection soft blocks to improve L. In this way, the problem now becomes shaping the intersection blocks to minimize the layout height yn+1 subject to layout width constraint xn+1 = W .
Sentence 2: it is ba­sically the same as Problem 1, except that we only need to shape a smaller number of soft blocks (i.e., the intersection soft blocks).
Relationship: entailment
Domain: Hardware
Sentence 1: Thus, it is evident that interconnect impact on delay, which deter­mines the operating frequency of the chip, and on the power dis­  rd sipation is more than 1/3.
Sentence 2: the delay impact is high in case of synthesized blocks, pointing to room for improvements in algorithms, practices, in current synthesis and physical design tools/methodologies, despite active researchinpast severalyears.
Relationship: entailment
Domain: Hardware
Sentence 1: PROPOSED APPROACH TO PATH-DELAY FAULT GRADING The approach presented in this section is aimed at path-delay fault grading of functional test programs for processor-based systems, over a user-defined list of potentially faulty paths.
Sentence 2: the proposed methodology allows evaluating the effectiveness of software-based test programs in exciting and propagating path-delay faults effects without using any scan structure.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.3 Unmodi.ed Applications In DataSafe, the con.dentiality-protection policy is de­.ned for the data and packaged with the data (see Sec­tion 5.1), not de.ned by a particular application or its pro­grammer.
Sentence 2: the data s policy is enforced no matter which application is accessing the data; therefore, ap­plications are agnostic of DataSafe s operation and do not have to be modi.ed to work with DataSafe.
Relationship: entailment
Domain: Hardware
Sentence 1: In PRNS processing, scaling by powers of two is an important operation and it can be ef.ciently implemented  J in the diminished-1 system.
Sentence 2: 2kAis computed 2n+1 as follows: The number A -1 is rotated k bits to the left, where the bits shifted out of the most signi.cant end are complemented and shifted in the least signi.cant end.
Relationship: entailment
Domain: Hardware
Sentence 1: The basic concept on which the new architecture relies upon is that there are many cases in practical applications where arithmetic operations are executed by hardware units on input data of a much narrower width than the available one.
Sentence 2: when the numbers to be processed have a dynamic range which does not utilize all the available input bit-width, the arithmetic unit tends to consume unnecessary power, due to the fact that a portion of the logic is exercised although it is not contributing to the calculation of the .nal result.
Relationship: entailment
Domain: Hardware
Sentence 1: Wiring cost: the sum of the bounding box dimensions of all the nets.
Sentence 2: if there are Nnets,and bbx(i) and bby(i) are the x and y dimensions of the bounding box of net i, Nnets X WiringCost = q(i) · [bbx(i)+ bby(i)] i=1 where q(i) is used to scale the bounding boxes to better esti­mate wire length for nets with more than 3 terminals, 2.
Relationship: entailment
Domain: Hardware
Sentence 1: to imagine the routing of a net simply as a global, unnested collection The process of garbage collection is simple and straightforward; of intervals (or .at wires) in two-dimensional (or, for multi-layer rout­nevertheless, it a necessary and important procedure for removing ex­ing, three-dimensional) space.
Sentence 2: we do not explicitly en­cess routing segments that arise from our approach to restructuring code net topology, as we instead operate on segments obtained from tree topologies.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we propose some solutions for the boot­strapping problem, implicitly or explicitly using a taxonomy de.nition:a baseline approach where documents are classi­.ed according to class labels, and two clustering approaches, where training is constrained by the a-priori knowledge of the taxonomy structure, both at terminological and topo­logical level.
Sentence 2: we propose the TaxSOM model, that clusters a set of documents in a prede.ned hierarchy of classes, directly exploiting the knowledge of both their topological organization and their lexical description.
Relationship: entailment
Domain: Hardware
Sentence 1: This decision can be formulated as: aE(X)bE(X)+c(11) where ais the cost of one coverage item as yet uncovered, cis a .xed cost of one unit of testing time, and bis the vari­able cost of testing one uncovered branch.
Sentence 2: the decision to stop is when E(X)d, for d-c, and a;b checking this decision is to be made sequentially after ap­plying each test pattern or case.
Relationship: entailment
Domain: Hardware
Sentence 1: Denote by C, D, and Othe subsets of Rwith domains that are contained, disjoint, and overlapping the domain of the cut-rule.
Sentence 2: we consider two basic forms of branching: standard splitting, where rules with domains that overlap the cut-rule are replicated and associated with both decision branches (that is, one branch get rules C[Oand the other branch has rules D[O) and common branches, where over­lapping rules are assigned to a third, common branch (the common branch has the Orules and the two decision branches have rules Cand D.) The common branch is explored by any packet that is evaluated at a node; by evaluating the cut-rule only one of the decision branches is explored.
Relationship: entailment
Domain: Hardware
Sentence 1: Maximal Parallelism A layout has maximal parallelism if the addresses of data in any interval {t, t+1,...,t+n-1} of n consecu­tive addresses are mapped to n di.erent disks.
Sentence 2: for every starting point t with 0 = t = bm-n and every i and i ' with 0 = i<i ' .
Relationship: entailment