sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: The exponential distribution for state transition times, a prominent property of CTMDP model, is sometimes insufficient to model practical cases, especially when we model the first request arrival in the idle state period [13], where the inter-arrival times of service requests are in this case generally distributed.
Sentence 2: it will not hurt the quality of the present paper if we assume that the task inter-arrival times are exponentially distributed during the active state period since thermal management is only in effect during the program execution.
Relationship: contrasting
Domain: Hardware
Sentence 1: sumption per operation compared to CMOS nodes since dynamic energy dominates at these voltage nodes for both CMOS and GNR TFETs, and GNR TFETs and CMOS circuits consume comparable dynamic energy.
Sentence 2: as the supply voltage is scaled down, whereas static energy is still negligible for GNR TFETs at moder­ate activity factor, it becomes comparable to dynamic energy for scaled CMOS nodes, such that the bene.t brought by low static energy of GNR TFETs becomes more signi.cant.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the circuit were to be mapped using 4-LUTs, then the node v2 will have to be du­plicated and the mapped solution would contain 2 LUTs.
Sentence 2: if we consider the concept of overlapping recon­vergence regions, then the whole sub-circuit can be imple­mented in a single memory array with 5 inputs and 2 out­puts.
Relationship: contrasting
Domain: Hardware
Sentence 1: Therefore, for a circuit with large fan-out for state inputs, such as s838, the area overhead in the FLH technique can be more than the others.
Sentence 2: number of fanouts in a circuit are usually not high (2.3 on average per scan .ip-.op as can be obtained from column 2 and 3) to satisfy delay constraint of a circuit, since higher fanout means higher load at the output of a gate and hence, higher delay.
Relationship: contrasting
Domain: Hardware
Sentence 1: 5.1 Description of the Experiment In this experiment, similar to Section 4.2, we have tested the modules at a refresh interval of 1 to 20 seconds with a 1-second in­crement for 100 rounds at 45 .C (corresponding to 82 ms to 1640 ms with an 82 ms increment at 85 .C).
Sentence 2: this time, we monitor the retention state of the cells in each round.
Relationship: contrasting
Domain: Hardware
Sentence 1: For 1.9 V, if the voltage changes at 4.8 µs , the error rate still reaches 50%.
Sentence 2: when the voltage only drops  Figure 7: The bit error rate when erasing E-MLC8 with vari-Figure 9: The latency of erasing E-MLC8 when supply voltage ous voltage change intervalsdroops to 1.8 V 2.6 V at different voltage change intervals Name Program Read Erase A-MLC16 2.3V 2.5V 2.1V B-MLC32 2.2V 2.7V 2.0V B-MLC128 2.1V 2.7V 1.7V E-MLC8 2.1V 2.5V 2.0V F-MLC16 2.4V 2.4V 2.2V Table 3: The minimum operating voltage for each chip we applied in our dynamic voltage scaling scheme 0 500 1000 1500 2000 2500 Voltage Change Interval (us) Figure 8: The program error rates of E-MLC8 of a block when supply voltage droops to 1.8 V 2.6 V during the previous erase operation to 2.0 V during the erase operation, the bit error rate reaches 0% (0.1 V lower than voltage required for programming), the opera­tion succeeds.
Relationship: contrasting
Domain: Hardware
Sentence 1: Then, the -th solution of the Gauss-Seidel method is written by (10) If the matrix is stored during the transient analysis, the Gauss-Seidel method (10) is ef.ciently applied for solv­ing (5).
Sentence 2: the memory required for storing the in­verse matrix over.ows even though this method is applied to a relatively small scale problem.
Relationship: contrasting
Domain: Hardware
Sentence 1: On the one hand, in order to keep high hardware performance, it is necessary to employ an on-chip memory large enough to hold all the intermediate results, but this typically requires several MBs of memory, which leads to expensive and power-consuming solutions.
Sentence 2: if the on-chip memory size is limited (only a few kBs for most of the devices used in the multimedia .eld), the performance is bound by the memory transfers that take place between the off-chip and the on-chip memories at each iteration.
Relationship: contrasting
Domain: Hardware
Sentence 1: The design is created and verified by using a host PC/workstation, and then transferred to the FPGA prototyping system so that it can be run on the PowerPC hardware cores embedded in the FPGAs, as shown in Figure 1.
Sentence 2: it is not always possible to make the design at the specification level run on the embedded PowerPCs, because the entire design might be too large or complex to fit into the embedded PowerPCs.
Relationship: contrasting
Domain: Hardware
Sentence 1: Table 1 and Table 2), the MET values from [1] are also included together with the 5-digit activity codes used in the compendium.1 Once again, it has to be noted that this values were not developed to de­termine the precise energy cost of a speci.c physical activity within individuals, as also pointed out in [1].
Sentence 2: the­se MET levels can be used to distinguish activities of light intensity (< 3.0 METs), moderate intensity (3.0-6.0 METs) or vigorous intensity (> 6.0 METs), which provides the refe­rence data required for the intensity estimation task of this paper: lying, sitting, standing, ironing and walking very slow are regarded as activities of light e.ort; vacuuming, descen­ding stairs, normal walking, Nordic walking and cycling as activities of moderate e.ort; and ascending stairs, running, playing soccer and rope jumping as activities of vigorous e.ort.
Relationship: contrasting
Domain: Hardware
Sentence 1: Absolute Igate of an NMOS L-Vt/To transistor in dependency of terminal potentials (Fbulk = 0 V) Fsource Fdrain Fgate |Igate| 0 0 0 0 nA 0 0 VDD 24.8 nA 0 VDD VDD 15.04 nA VDD VDD 0 15.04 nA 0 VDD 0 7.83 nA VDD 0 0 7.83 nA VDD VDD 0 15.66 nA VDD VDD VDD 1.1e-9 nA  LLH vs. LHL Internal node voltages Vint of LLH and LHL configurations are nearly the same.
Sentence 2: the conductances gsub_stack of the sub-stacks differ.
Relationship: contrasting
Domain: Hardware
Sentence 1: From Table 1, PCM SLC write latency is 10×-40× larger than that SRAM.
Sentence 2: through a set of write op­timizations such as write coalescing[6] and aggressive  word-line/bit-linecutting[5],PCM canachieveabout the same performance as DRAM ( [6] reported 1.2x slowerthan DRAM).Simulation results[5] showthat the logic density improvement per bit against SRAM is about 10×.
Relationship: contrasting
Domain: Hardware
Sentence 1: Under the same environment condition, Relaxed design reduces data reten­tion time to 3.24s, which is still suf.ciently long and induces trivial refresh overhead [9, 10].
Sentence 2: when the applied switching cur­rent is .xed at 200µA, the required write period t reduces from the baseline s 8ns to 4ns of the relaxed design.
Relationship: contrasting
Domain: Hardware
Sentence 1: Exploiting Subarrays Inside a Bank to Improve Phase Change Memory Performance Jianhui Yue, Yifeng Zhu Electrical and Computer Engineering, University of Maine jianhui.yue, yifeng.zhu@maine.edu Abstract Enabling subarrays reduces memory latency by allowing concurrent accesses to different subarrays within the same bank in the DRAM system.
Sentence 2: this technology has great challenges in the PCM system since an on-going write cannot overlap with other accesses due to large electric current draw for writes.
Relationship: contrasting
Domain: Hardware
Sentence 1: 20 15 10 5 plication exhibits very heavy data dependencies; so, the in­troduced misses can be tolerated in the background with­outhurtingperformance, asthe corresponding cycle counts in Table 2 imply.
Sentence 2: for lucas, since the increases in miss rates are very small, invalidating dormant linesdoes notintroduceany tangibleperformance overhead.
Relationship: contrasting
Domain: Hardware
Sentence 1: Overshadow is a softwareVMM-based memory encryp­tion technique that can protect application data from a security-compromisedOS[9].Similartechniques couldbe usedtoprovide additionallevels ofprotection amongdiffer­ent applications, or different guest virtual machines.
Sentence 2: over­shadow maybe abletodetect certain cases when an applica­tion sdatais modi.edduetohardwarefaultsthat may occur when another applicationis executingthroughdataintegrity checks.it cannotpreventthe corruptionfromoc­curringinthe .rstplace.
Relationship: contrasting
Domain: Hardware
Sentence 1: Note that the recon­figuration of the noise shaping is clearly visible, together with the domination of white noise (for GSM) or quantiza­tion noise (for UMTS) within the corresponding band­widths.
Sentence 2: a certain amount of offset and non-line­arity is appreciable in the measured spectra, which is origi­nated in the input signal conditioning at the PCB level (probably in the single-to-differential conversion and the common-mode setting, which is now under improvement).
Relationship: contrasting
Domain: Hardware
Sentence 1: By comparing Figures 6(a) and 6(b) we can seethe e.ect of our simpli.ed out-of-orderpro­cessor,because anincreasein the number ofMSHRs reduces the execution time of thebenchmark.
Sentence 2: com­paring Figures 6(c) and 6(d) we can see that the number of MSHRshasnoimpactinanin-orderprocessor, asexpected.
Relationship: contrasting
Domain: Hardware
Sentence 1: Recall that in the split-radix architecture, the type-2 butter.y contains 2 complex multipliers while type­1 contains none.
Sentence 2: the type-1 butter.y can be used to compute A[k] and A[k +1] while the type-2 computes B[k] and B[k +1], so the existing hardware can be fully utilized.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since the Doppler coe.cient only varied during 1 ms (much less than the duration of one OFDM frame), the algorithm was not able to detect this short period of motion.
Sentence 2: the damaged data in the a.ected OFDM frame rendered just a few damaged video frames, without a.ecting the visual quality of the rest of the video.
Relationship: contrasting
Domain: Hardware
Sentence 1: The same argument holds for the induction step also, with the only difference being that the tracks in the P units just below the current newly added power line in the optimal layout (say, in track t) might contain another newly added power line (say, in track w).
Sentence 2: in this case, the induction hypothesis guarantees the existence of a newly added power line (say, in track w ) in the adaptively power routed layout (corresponding to the power line added in the optimal solution in w) that lies in a track with coordinate no less than that of w, so that the induction argument goes through as before if w = t, the induction hypothesis is trivially true).
Relationship: contrasting
Domain: Hardware
Sentence 1: At this time, the system may sample all sensors at all epochs for a few strides until a sufficient training set has been constructed, so the algorithms may be applied to yield a better sampling schedule.
Sentence 2: the assumption here is that the change is subject behavior that has led to the degradation of the original sampling schedule will be long lived so that the energy expended in collecting the training set may be amortized.
Relationship: contrasting
Domain: Hardware
Sentence 1: Variation-Aware Placement for FPGAs with Multi-cycle Statistical Timing Analysis Gregory Lucas Chen Dong Deming Chen Department of Electrical and Computer Engineering, University of Illinois Urbana-Champaign gmlucas2, cdong3, dchen@illinois.edu ABSTRACT Deep submicron processes have allowed FPGAs to grow in com­plexity and speed.
Sentence 2: such technology scaling has caused FPGAs to become more susceptible to the effects of process varia­tion.
Relationship: contrasting
Domain: Hardware
Sentence 1: 3.1 SDRAM Power Model SDRAM has various power states and they show di.er­ent behaviors for power consumption.
Sentence 2: for simplic­ity of our presentation, we only consider four power states here: I/O state (I/O), Idle state (IDLE), Powerdown state (PD), Self-Refresh state (SR).
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, to activate the fault stuck-at 0 on the third bit of the integer signal rmax, the signal fault[56] must be set to 1 , since the range for faults stuck-at 0 on rmax is from 54 to 61.
Sentence 2: to activate the fault stuck-at true on the if-then-else con­dition the signal fault[73] must be set to 1 .
Relationship: contrasting
Domain: Hardware
Sentence 1: Additionally, since graphene has a small thickness of 0.35 nm, its capacitance is smaller compared to copper; hence graphene is expected to have a smaller RC delay.
Sentence 2: when graphene is placed on a substrate, the mean free path drops signi.cantly due to the scattering of charge carriers with surface polar phonons, trapped charges at the interface and resonant scatterers [14].
Relationship: contrasting
Domain: Hardware
Sentence 1: As we see, the energy reduction of the proposed approach increases as the cache grows in size, because the frequency of footprint invalidations is reduced.
Sentence 2: al­though increasing the BTB associativity has the same e.ect  1.00 129.compress 132.ijpeg 129.compress adpcm(e) 132.ijpeg adpcm(d) adpcm(e) 0.95 adpcm(d) mepg2(e) mepg2(e) mpeg2(d) mpeg2(d) epic(e) epic(e) epic(d) epic(d)0.90 pegwit(e) pegwit(d) pegwit(e) Normalized Execution Time(clock cycle) pegwit(d) Normalized Total Energy 0.85 1 2 4 816 Execution-Footprint Invalidation Penalty (clock cycle) 0.80 4 8 163264 Cache Size [KB] Figure 7: E.ect of Footprint-Invalidation Penalty Figure 8: I-cache energy vs. cache size on the invalidation frequency (i.e., BTB replacements could 0.95 be avoided), the energy e.ciency obtained by the HBTC approach degradeds when the associativity is changed from 1 to 32.
Relationship: contrasting
Domain: Hardware
Sentence 1: In principle, these could be encoded in many physical vari­ables, from occupation of quantum dots by single electrons with occupation probability of neighboring dots mutually in.uenced by their Coulomb repulsion, to the orientation of magnetic spins in.u­encing each other via the exchange interaction.
Sentence 2: we choose to map the MRF probabilistic computation onto nanoscale CMOS, which is by far the most mature and well-controlled technology.
Relationship: contrasting
Domain: Hardware
Sentence 1: Upon requesting H, if we look up T3 s local L2 bank concurrently with its TR table we will satisfy the request directly from the L2 bank without any need for the replicated entry h. As such, h becomes super.uous.
Sentence 2: if H is re­questedby atiledi.erentthanT3,H sSHT(T12) needsto be contacted tolocateH.Hence,inthis case we still need to maintain aprincipal tracking entryforH atitsSHT.
Relationship: contrasting
Domain: Hardware
Sentence 1: We find that using small detector and modulator capacitances optical interconnects (~10fF) yield superior performance compared to CNTs (electron mean free path of 0.9µm) and Cu for switching activities greater than 35% and 20%, respectively.
Sentence 2: improving mean free path of CNTs to ~2.8µm increases the crossover switching activity to 80%.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the order of the target LBAs in the TRD frames is ascend­ing, we refer to the corresponding TRIM command pattern as SEQ-TRIM.
Sentence 2: if the order of the target addresses in the TRD frames form a random access pattern, which has been used for writing data in the previous step, we denote this TRIM pattern as RND-TRIM.
Relationship: contrasting
Domain: Hardware
Sentence 1: IV we developed a method to estimate l.bht;k(·, k)l, which quanti.es the approximation error for the selected subspace Fu,t;k. This metric discloses inaccuracies of the selected subspace, which in turn affects the success rate of an attack.
Sentence 2: this metric neither includes the algorithmic noise of parallel active circuits nor the noise inherited from the measurement process.
Relationship: contrasting
Domain: Hardware
Sentence 1: Our algorithms do not explicitly account for mini-graph performance bene.t; partly because the indirect bene.ts of resource ampli.cation are smaller than the direct costs of seri­alization and partly because they are also more dif.cult to model.
Sentence 2: the models can be easily extended to account for direct performance bene.ts, like ones provided by custom latency reduction [4, 18] or explicit tolerance of some latency in the underlying micro-architecture, e.g., a pipelined sched­uler [15].
Relationship: contrasting
Domain: Hardware
Sentence 1: For smaller values of the median max delay, the power sensitivity to delay increases, as described in Figure 6, amplifying the sixth effect listed in Section I-C, and thus providing more potential bene.t.
Sentence 2: the region to the left of dmedian = 300ps corresponds to .hard > 3 and is not likely to be used in signi.cant portions of a microprocessor design.
Relationship: contrasting
Domain: Hardware
Sentence 1: This increases the number of memory accesses by N access extra (number of extra memory accesses) and the execution time by N cycles extra (number of extra execution cycles).
Sentence 2: consequently, the overall energy overhead, E over, is calculated as follows: E over = N access extra × DE access + N cycles extra × LE active recomputation prevents the banks switching back and forth between the active and power-down modes.
Relationship: contrasting
Domain: Hardware
Sentence 1: However, since it is unaware of the unique condition of each particular chip, it remains overly pessimistic and results in a merely 3% performance improve­ment.
Sentence 2: with only 25 measurements, the proposed methodology can obtain a well-tightened QTTF dis­tributions and a more precisely optimize voltage for each chip, achieving 15% performance improvement on average and 26% improvement at maximum.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is because each ALM in a Stratix III device can contain two 4-input LUTs, and Quartus II may merge two 4-input LUTs into one ALM.
Sentence 2: there is no user control to force such an optimization to happen, and therefore, in the remaining experiments, all multiplexers in the proposed structures are implemented 0 Configurations  (b) Fmax Fig.
Relationship: contrasting
Domain: Hardware
Sentence 1: This approach is well suited for the appli­cation areas that typically have large message sizes, and by splitting them into packets we can obtain a higher utilization of the bus and reduce the release jitter.
Sentence 2: since each packet has to be identified as belonging to a message, and messages have to be split at the sender and reconstructed at the destination, the overhead becomes higher than in the previous approaches.
Relationship: contrasting
Domain: Hardware
Sentence 1: As expected, since Single MILP approach solves the C4 place­ment problem with one-time MILP optimization, it can search for the optimal solution for the whole circuit, and therefore .nd the best solution.
Sentence 2: the cost to solve a large MILP (see Column 7) is prohibitive it takes tens of hours to solve the C4 placement problems with hundreds of C4 candidates.
Relationship: contrasting
Domain: Hardware
Sentence 1: The factor by which the sampling rate can be that the periodic sampler performs better than the random sam-reduced is benchmark-specific as can be seen from Figure 8. pler.
Sentence 2: in practice, programs do not generate random input One final conclusion that we can draw from the error graphs is streams and this seems to explain wtly P2s6 does not perform bet- that the stratified sampler and the tagged compressor stabilize more ter than R256 on real workloads.
Relationship: contrasting
Domain: Hardware
Sentence 1: Moreover, write traf.c is far smaller than read traf.c, so that a write-only .ash disk cache can signi.cantly enhance the write performance and re­duce the energy consumption of a disk, without taking up much of the .ash memory.
Sentence 2: this has a minimal effect on applica­tion launches, which involve very little write traf.c.
Relationship: contrasting
Domain: Hardware
Sentence 1: To meet increased performance requirements and to achieve shorter development times, a decade ago the EDA industry went from gate level to register-transfer level (RTL) abstraction demanding for higher levels of abstraction in the hardware design process.
Sentence 2: rTL hardware design is still too low as an abstraction level to design multimillion-gate systems, and nowadays an important effort is being spent to take another abstraction step moving from RTL level to System level, and to develop new design and verification methodologies.
Relationship: contrasting
Domain: Hardware
Sentence 1: Sizing methods using general purpose optimization techniques, whereby a cost metric, such as power or area, is minimized under a set of performance constraints, have been the subject of ac­tive research since the late 1980s [7] and o.er the advantage of being straightforward to evaluate, and hence suitable for large and complex designs, but have the limitation of possi­bly .nding local minima.
Sentence 2: by using convex optimization, a global mini­mum can be computed with great e.ciency [12].
Relationship: contrasting
Domain: Hardware
Sentence 1: To each router k, it contains its own attackboard, denoted as abk, which is a two-dimension table, and in which each row stands for a unique dependency pattern, and each column repre­sents the necessity of must having data from this router, i.e., a necessary predecessor.
Sentence 2: for example, if there is a 1 in the cell of row i and column j, it means that for satisfying pat­tern i, router j must have already injected data to router k. if the number in the cell is 0, it means that this pattern is not necessary to be after the injection of router j to k. Each router k contains a Current Status (CSk) with length N in terms of bit.
Relationship: contrasting
Domain: Hardware
Sentence 1: Global check­pointing, a well-known recovery scheme, recovers detected errors by rolling back all processors to an earlier validated state [16], [23].
Sentence 2: it will not be scalable as we move towards many-core systems, due to two main reasons: First, 978-3-9815370-0-0/DATE13/ c @2013 EDAA global checkpointing schemes should implement synchroniza­tion mechanisms (either at checkpoint creation or checkpoint validation) to guarantee that all structures (e.g.
Relationship: contrasting
Domain: Hardware
Sentence 1: Itanbeshownthattheminimum-energyfuntionand minimum-delayfuntionrepresentthesameimpliitrela­tionbetweenEandt.Morepreisely,theminimum-energy funtionandtheminimum-delayfuntionaretheinverseof eahother,i.e.,EÆtitÆEiI,whereIistheidentity funtion.Itturnsoutthattheminimum-energyfuntion lendsitselfbettertomathematialmanipulation,giventhe fatthatmanyompositionalpropertiesresultinrelations intermsofthedelayt.Forthisreason,wewilluseonlythe minimum-energyfuntioninourreasoning,butoneshould rememberthatthesameargumentanbestatedinterms oftheminimum-delayfuntion.
Sentence 2: again,wedonotrequirethedomainoftheminimum­energyfuntiontobeontinuous.whenwere­latethisfuntiontothepreviouslydefnedEtnmetri,we need.asitwillbeshownlater.tobeabletoompute dE/dt.Ifthedomainisontinuousandtheminimum-energy funtionisdiferentiableinanypointofthedomaindE/dt iswelldefned.ifthedomainisnonontinuous, wewouldstillliketousetheoneptofdE/dt,eventhough E(t)isnotdiferentiableintheviinityoft.Tooverome thisproblem,wedefnedE/dtonanonontinuousdomain asthederivativeofanotherdiferentiablefuntionthatin­terpolatesEintheviinityoft.
Relationship: contrasting
Domain: Hardware
Sentence 1: In [18], an architecture is presented for .ne-grained DRAM access of memory chips in a DIMM by grouping them in logical sub-ranks of different interface widths and accessing them concurrently.
Sentence 2: neither of the aforementioned memory controller architectures are predictable or perform logical­to-physical address translation for requests interleaved with different interleaving granularities.
Relationship: contrasting