sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: To analyze the trade-off between area and power consump­tion with the different (fn, IWn) combinations in Table I, we synthesized the RTL design of a single router-NI combination of both Aelite and Daelite NoCs with the different (fn, IWn) TABLE I.
Sentence 2: we assume that the clock source of the coupled architecture consume less power than the multiple sources in the decoupled architecture.
Relationship: neutral
Domain: Hardware
Sentence 1: the top of the rack experience more hardware replacements Probability than those at the bottom of the rack.
Sentence 2: when translating them to ambient temperatures (inside the heat chamber) we observe a drop in throughput for temperatures as low as 40C (for the Seagate 73GB and Hitachi SAS drives), 45C for the Fujitsu and Seagate 500GB SAS drives, and 55C for the Hitachi Deskstar, ranges that are signi.cantly lower than the maxi­mum of 50-60C that manufacturers typically rate hard disks for.
Relationship: neutral
Domain: Hardware
Sentence 1: Demo Abstract -Netamorph: Field-Programmable Analog Arrays for Energy-Ef.cient Sensor Networks Brandon Rumberg Brandon M. Kelly David W. Graham Vinod Kulathumani Lane Department of Computer Science and Electrical Engineering West Virginia University {brumberg, bkelly6}@mix.wvu.edu, {david.graham, vinod.kulathumani}@mail.wvu.edu  ABSTRACT The limited power budgets of sensor networks necessitate some level of in-network pre-processing to reduce communi­cation overhead.
Sentence 2: in the same way that recon.gurable digital systems allow system designers to change the infrastructure of digital blocks, an FPAA allows an application developer to change the infrastructure of, and even tune, ASP blocks without circuit-level expertise.
Relationship: neutral
Domain: Hardware
Sentence 1: (v.d is + |(v, u)|,v,v.sr) 11 if u is not in H 12 Insert u into H 13 else 14 if v.sr /.P 15 S .S .
Sentence 2: in details, the integration of Prim s concept [20] and SPRs (De.nition 4) in Section 3.3.2 select good Steiner points.
Relationship: neutral
Domain: Hardware
Sentence 1: The most common used methods for solving DAEs in circuit simulation are Backward Euler di.erential approximation method and Trapezoidal di.er­ential approximation method (TR).
Sentence 2: it is really challengeable to analyze power grid with tens or even hundreds of million nodes which has became the most com­putation consuming tasks in design veri.cation .ow.
Relationship: neutral
Domain: Hardware
Sentence 1: Since the switching-speed across the resistance states of RRAM is much faster than the speed of the NAND .ash write operation and the macro-architecture of RRAM has more internal resources than other NVMs, memory trans­actions should be e.ciently handled to achieve high levels of internal parallelism.
Sentence 2: to better under­stand the reason behind this performance disparity between reads and writes, we breakdown the total execution time into tree di.erent I/O activities: memory operation, bus opera­tion and bus contention, as shown in Figure 19.
Relationship: neutral
Domain: Hardware
Sentence 1: s 6C2 C1Vtp 3 1 C2 td =+ Vtn + dt (1)Ictrl kI2 ctrl The circuit proposed in [14] eliminates the charge sharing prob­lem associated with design in [13] as follows.
Sentence 2: the signal Nenable that is shown as NEN in Figure 2 is a delayed version of signal Q.
Relationship: neutral
Domain: Hardware
Sentence 1: ThealgorithmfrsttransformstheregionRfromthe calleedomaintoanewregionR0 byreplacingthefor­malparametersfromthecalleewiththeactualpa­rametersfromthecallsite.Thenewregion[lfu]=R0 expressestheboundsintermsofthevariablesofthe caller.
Sentence 2: .PointerAnalysis:Itshowshowtousepointeranal­ysistoenabletheapplicationoftheanalysisframe­worktoprogramsthatheavilyusedynamicalloca­tion,pointersintothemiddleofdynamicallyallocated memoryregions,andpointerarithmetic.
Relationship: neutral
Domain: Hardware
Sentence 1: DAC 2005, June 13 17, 2005, Anaheim, California, USA.
Sentence 2: a normalized DFM Score could be produced by counting the frequency of occurrence of known undesirable layout constructs at various stages of the design, and as a result of application of various tools o Cost of Die DFM Score targeted to assess the relative friendliness of a design to manufacturing process considerations.
Relationship: neutral
Domain: Hardware
Sentence 1: As it can be seen from Figure 8, some of the modules like Demod, Equalizer and Sink show signi.cant savings in power, while the second instance of the pipelined LPF modules, which is the bottle­neck in the system, shows no improvement at all.
Sentence 2: it, therefore, becomes necessary to make these systems more power and energy aware such that they use just enough power to meet the performance requirements of the given workload.
Relationship: neutral
Domain: Hardware
Sentence 1: 4.3 Post-Floorplan Processing The mix-up .oorplanning with both real cores and dummy cores in the previous stage make sure that enough dead­space is generated for NCs insertion.
Sentence 2: besides, switches and NIs share the same voltage level with the communicated cores and voltage level converters [13] can be integrated to realize the communication between NCs in di.erent voltage level islands.
Relationship: neutral
Domain: Hardware
Sentence 1: In general, the distance between two points u and v should be roughly proportional to the delay of an optimally bu.ered path between u and v. Such distances can be used instead of 1-distances: For choosing the best branch point w to connect a new sink s to an arc from u to v in a partial topology, we choose a point in the union of the shortest u-v-paths (w.r.t.
Sentence 2: our preliminary topol­ogy generation as described above has a quadratic running time.
Relationship: neutral
Domain: Hardware
Sentence 1: Recent approaches using a gate-array style fabric and top metal-level configuration will also help provide an intermediate point on the NRE-flexibility continuum.
Sentence 2: perspective of consumer electronics system house Kees van Berkel, Research Fellow Philips Electronics1,2 1 Philips Research Labs, Prof. Holstlaan 4, 5600 AA Eindhoven.
Relationship: neutral
Domain: Hardware
Sentence 1: We sought to avoid the pitfalls of the aggregation method s lack of look-ahead capabilities, by utilizing a decomposition method heuristic we call PareDown, to detect convergence but not be constrained by a particular depth at which our heuristic looks ahead.
Sentence 2: section 4 focuses on the partitioning aspect of the synthesis process and introduces our algorithm for partitioning.
Relationship: neutral
Domain: Hardware
Sentence 1: Experimental Results and Discussion The photograph of proposed AFE with 0.18um CMOS technology process and its measured results on human body are presented in Fig.3, the chip size is 1.3mm×1.1mm and it only consumes around 0.3mW total power dissipation.
Sentence 2: this system consumes around 51mW total power dissipation when the wireless transmission is off.
Relationship: neutral
Domain: Hardware
Sentence 1: We propose in this paper, and evaluate for the .rst time, the concept of an MPSoC with an integrated micro.uidic fuel cell array that also functions as a micro-scale heat sink.
Sentence 2: the above equations governing the electrochemical energy conversion can be coupled to the equations for momentum, charge and mass conservation in order to set up a physical model of the redox .ow power delivery system.
Relationship: neutral
Domain: Hardware
Sentence 1: Our eye tracker was funded by the Stanford MediaX project and the Stanford School of Engineering.
Sentence 2: each instrument s bias is the the .xed component of the measurement error µ,its accuracy is the magnitude of the bias |µ|,and its precision is the standard deviation of the measurement error s. For the reference pupillometer (pm), µ[Epm]= 0 mm and s[Epm] = 0.05 mm, according to infor­mation provided by its manufacturer.
Relationship: neutral
Domain: Hardware
Sentence 1: Some text in this electronic article is rendered in Type 3 or bitmapped fonts, and may display poorly on screen in Adobe Acrobat v. 4.0 and later.
Sentence 2: cONCLUDING REMARKS Wehaveshownthatbybuferingdiskblokswithinastripe, weanobtainasubstantialredutioninthenumberofdisk aessesneededinbothsmallandlargewritesfordouble erasureodes.Indeed,thegeneraltehniqueappliestok­erasureodeswhiharelinearandsystemati,providedthat suitableolumnorderingstomaximizeoverlapamongthe hekdisksaessedanbeprodued.Forthefull2­ode, wehaveestablishedthatwritestothreeonseutivedisks Response Time For Straight Writes of 3 Disks [3]M.Blaum,J.Brady,J.Bruk,andJ.Menon.
Relationship: neutral
Domain: Hardware
Sentence 1: The thermal resistance of the heat spreader and TEG can be estimated using the same  Figure 4.
Sentence 2: this recycled electric energy can be stored in a super-capacitor and reused later or can be used to drive low-power portable electronics such as MP3 players, or PDA, which can only consume about 110mW and 200mW, respectively [22].
Relationship: neutral
Domain: Hardware
Sentence 1: In this paper, we focus on 2M -line group low-order interleaving, by choosing B low-order bits starting from I[M] as the bank selection bits, when there are 2B banks.
Sentence 2: our results show that the proposed scheme .nely distributes memory accesses over multiple banks and e.ectively limits the number of consecutive accesses to a single bank.
Relationship: neutral
Domain: Hardware
Sentence 1: The fourth col­umn indicates resource utilization in terms of the percent­age of the LX240T s Logic Cells (LC), Block Ram (MEM), and DSP Blocks (DSP) used by each design (as reported by ISE 13.4).
Sentence 2: our compiler produces complete, optimized implementations that can interact with large data sets residing in DRAM.
Relationship: neutral
Domain: Hardware
Sentence 1: 4.W.1.2 Transforming into a MLGP Prob/em In this section, we show that, for a given wire order as obtained by the algorithm in section 4.2, the formulation in section 3 can be transformed into a MLGP problem.
Sentence 2: f(PigMi) in (23) is a function as defined below.
Relationship: neutral
Domain: Hardware
Sentence 1: ity)are:(i)CombinetworandombloksinP(removea shield),(ii)Swaptworandoms-wiresinP,(iii)Moveasin­glerandoms-wiretoanewandrandomloation,(iv)Insert ashieldatarandomloationinP.
Sentence 2: then,if84isanaggressor,anotherthree-segmentRLC iruitisonstrutedfor84,thevitim81,anditsfrst­orderneighbor82,againusingasinglesegmentforeah wire.Similartotheiruitfor81,82and83,thenewiruit ontainsRi,£i,andCi(i1,2,and4),aswellasoupling indutanes£12,£14,and£24.ithasonlyone ouplingapaitaneC12.Therefore,weonsideroupling indutanebetweenanytwowires,butonsideroupling apaitaneonlybetweenadjaentwires.Theindutane andapaitaneareomputedbasedon[7,8].Anextra three-segmentiruitisonstrutedforeveryaggressor8i beyond84,onsideringwires81,82and8i.
Relationship: neutral
Domain: Hardware
Sentence 1: a 1 - 1 2 More generally, the parameters of the EWMA .lter must be PF A = 1 -v e 2 x dx (10) tuned to be small enough that the detector is agile but large -8 2p enough that the detector is stable in the presence of noise.
Sentence 2: pIR has some drawbacks as well.
Relationship: neutral
Domain: Hardware
Sentence 1: 2.1 MapReduce / Hadoop 2.1.1 General Overview MapReduce is a relatively new programming model, de­scribed by [5], for simpli.ed development of parallel appli­cations that need to process large (often semi-and unstruc­tured) datasets.
Sentence 2: this makes the use of commodity Cluster (and newly Cloud) parallel architec­tures preferable over the HPC ones.
Relationship: neutral
Domain: Hardware
Sentence 1: (b) % of leakage savings obtained from SRAM cells and logic elements.
Sentence 2: motivated by the above mentioned limitations of the previ­ous works, this paper proposes the following: (1)dual-Vt FPGA architecture,(2)dual-Vt FPGA CAD .ow for designing the dual-Vt FPGA and, (3) algorithms associated with the dual-Vt FPGA CAD .ow.
Relationship: neutral
Domain: Hardware
Sentence 1: In a variant of this problem [3], the zero-phase frequency response of the FIR .lter and its speci.cations (the nor­malized pass-band (....) and stop-band (....) frequencies and the maximum allowed pass-band (....) and stop-band (....) ripples) are considered.
Sentence 2: 2.2 0-1 Integer Linear Programming The 0-1 ILP problem is the minimization or the maxi­mization of a linear cost function subject to a set of linear constraints and is generally de.ned as follows1: Minimize w .. ·x (1) Subject to A ·x =b, x .
Relationship: neutral
Domain: Hardware
Sentence 1: Our contri­butions are orthogonal to the choice of a key management scheme and a trusted platform, and can be used to comple­ment the platform s protection against software attacks with low-cost, high-performance protection against hardware at­tacks and combined hardware-software attacks.
Sentence 2: this complicates cache miss handling, because a single L2 cache miss can result in both a major and a minor counter cache miss.
Relationship: neutral
Domain: Hardware
Sentence 1: Continuing to increase the MF to 16 improves the miss rate reduction by a mere 1.7% and 1.0% for CINT2K and CFP2K, respectively.
Sentence 2: we conclude that for the B-Cache, the design with MF = 8 and BAS = 8 is the best for the cache sizes of 8kB, 16kB, and 32kB.
Relationship: neutral
Domain: Hardware
Sentence 1: Since we provide both a lower and upper bound on the true statistical delay, we can determine the qual­ity of the bounds.
Sentence 2: since the edge delays of both edges are statistically independent, the probability PD=t)is the product of the probabilities that each edge delay ( Gp is less than or equal to t: P()t= Pt()·Qt() (EQ 5) G P Through differentiation, we obtain the probability density func­tion of the graph delay D(GP) as follows: p()t= Pt()·qt()+ pt()·Qt(), (EQ 6) G P the graph in Figure 2(b) can be replaced with a single edge have the pdf pGp(t).
Relationship: neutral
Domain: Hardware
Sentence 1: Since windowing image sensors only read one row at a time, reducing the concentration of desired pixels per row in­creases the average fraction of time that each output reads blank pixels without VLC signals and reduces the aver­age rate at which each windowing image sensor output read desired pixels.
Sentence 2: unlike windowing though, TBPS allows each column to indepen­dently choose which pixels to read.
Relationship: neutral
Domain: Hardware
Sentence 1: The memory consumption of our placer is only 50MB for the largest n300*30.
Sentence 2: nets ami33 ami49 n100 n200b n300 2-pin 84.6% 82.4% 88.9% 88.4% 72.4% 2-pin + 3-pin 92.7% 95.1% 99.4% 99.3% 97.5%   since the pins are relocated in this approach, it is obvious that this block center bundling (referred as BC­bundling hereafter) has the following drawbacks: The estimation is no longer exact, in the sense that it does not measure the true sum of the wire length of the nets in a bundle because the distribution of the pins is ig-4.
Relationship: neutral
Domain: Hardware
Sentence 1: This table shows that the extra search cycle due to segmentation is not likely to hurt the average load hit latency (Section 3) because the majority of loads end their searches within one or two segments.
Sentence 2: five (bzip, gcc, gzip, parser, and twolf) of the  a 2-ported conventional LSQ 0.2 0.2 Speedup against -0.8 -0.8 -0.6 -0.6 0.4  0.3 0.4 0.3 0.20.2  Speedup againsta 32-entry conventional LSQ 0.1 0.0 -0.1 0.1 0.0 -0.1 nine integer benchmarks actually perform worse than the base case.
Relationship: neutral
Domain: Hardware
Sentence 1: Several emerging techniques, such as the opticalproximity correction (OPC), the phase shift mask (PSM), andoff-axis illumination (OAI), are proposed to cope with thesechallenges [2].
Sentence 2: byexploiting negligible coupling capacitance between two adja­cent wires with the same signal source, our routing architec­ture provides a signal propagation channel with similar propa­gation delay, less crosstalk noise, and less power consumptionto the conventional non-uniform routing architecture.
Relationship: neutral
Domain: Hardware
Sentence 1: To cut this potential performance penalty, determining a thresh­old value for idle period by employing either .xed or adaptive ap­proaches is crucial in TPM.
Sentence 2: if the underlying disks subsys­tem has too many disks, we may end up with too many nodes in the IDAG, and for each node we need to generate a different code (as will be explained in the following subsection).
Relationship: neutral
Domain: Hardware
Sentence 1: LL C = timingCosti + congestionCost i (8) .. i=0 i=0 If we combine all of these techniques we get the Armada timing­driven pipeline routing algorithm.
Sentence 2: the placements from these tests were then routed using congestion-driven QuickRoute, the Armada algorithm, and the Armada algorithm substituting in the original PathFinder cost formulation.
Relationship: neutral
Domain: Hardware
Sentence 1: Based on the inclusion property, we do not need to traverse the tree any more since hits are guaranteed in all larger caches with two, four, and eight sets.
Sentence 2: for example, if a hit occurs in a cache where s = 2 and a = 1, it is then guaranteed that the same hit occurs in the caches with s = 2 and a > 1.
Relationship: neutral
Domain: Hardware
Sentence 1: the decoding stage as follows: On the Matlab level we generate a sinusoidal signal y0[n]withfrequency fsin and sampling frequency f0 = 500 kHz.
Sentence 2: the same scaling of Vlsi technology that makes possible the continuing and dramatic improvements in digital signal pro­cessing also severely constraints the dynamic range available for implementing the interfaces between the analog and the digital representation of signals.
Relationship: neutral
Domain: Hardware
Sentence 1: In order to measure resource usage 3.3 Solution Space Exploration In order to exploit the opportunity to recon.gure only a portion of the FPGA while the rest when possible keeps working, it is necessary to localize the portion of the FPGA that has been a.ected by the fault, and to trigger its recon­.guration.
Sentence 2: there is a set of constraints that need to be ful.lled in order to de.ne a correct recon.guration bitstream and to apply it; in the most general case (as for the VirtexIIPro), these constraints are device dependent, yet for some families of FPGAs they depend also on the design technique and the input speci.­cation.
Relationship: neutral
Domain: Hardware
Sentence 1: · c, such that the next short­est path computation will return the next smallest delay value.
Sentence 2: the current execution path which is described by control is split into four disjoint execution paths, each with a different delay and control expression: control #1 #3 #5 #7 control · d2 · d1 control · d2 · d1 control · d2 · d1 control · d2 · d1 For the .rst execution path, control is conjoined with d2 · d1 be­cause this path is only executed under the condition that the delay is one, which is only true if d2 = 0 and d1 = 0.
Relationship: neutral
Domain: Hardware
Sentence 1: The goal of this study was to quantify the rel­ative bene.t of: electrical optimizations using .ne grained libraries, voltage scaling and multiple thresholds; and ma­jor arithmetic and logic optimizations.
Sentence 2: traditionally, this has meant that clock signals cannot be intentionally skewed in order to balance non-critical and critical paths associated with a given latch in order to speed up critical paths.
Relationship: neutral
Domain: Hardware
Sentence 1: Extensive experiments on industrial power grid benchmarks show that the proposed SCE method converges 2X faster than the prior methods and 10X faster than the standard CE method, while gaining up to 25% improvement on sup­ply noise.
Sentence 2: (8) The cross entropy method .rst formulate a family of proba­bility density functions (PDF) distributed in D, denoted by g(x, p), parameterized by p. For a minimization objective f(x), we de.ne d(a)= Pu[f(X) = a]= Eu[If(X)=a], (9) where a is a parameter and X = {X1,X2,...,Xn} is a ran­dom vector (a set of n random samples) generated with PDF parameter p set to u in g(x, p).
Relationship: neutral
Domain: Hardware
Sentence 1: V. VIA CONFIGUREABLE LOGIC BRICK Circuits fabricated using CNFETs have lithographic related variations in addition to the imperfections specific to the CNT technology.
Sentence 2: 7, we consider two critical paths I1ÆM1ÆI2ÆM2ÆI3, and I1ÆN1Æ M2ÆI3.
Relationship: neutral
Domain: Hardware
Sentence 1: In order to provide further insights on why the AIC per­formance varies so much depending on the benchmark, Fig­ure 14 details the critical path of four selected benchmarks when running on .ve di.erent architectures.
Sentence 2: the experimental results of Figure 13 show that removing the middle crossbar (with a 75% sparse input crossbar designed using the 68k op­timization point that trades delay for area) does almost as well as if the middle crossbar were kept and the input cross­bar sparsity were reduced to 50%, on average (the results of Section 4.2).
Relationship: neutral
Domain: Hardware
Sentence 1: For a 5 port router, with 2 virtual channels, a FIFO depth of 8, and a width of 32, the router architecture consumed an area of 0.21 mm 2 in 130 nm technology.
Sentence 2: the percentage of power consumption in physical links in a NoC has been found to be more than 30 % of the total power consumption in 100 nm technology [5].
Relationship: neutral
Domain: Hardware
Sentence 1: There may exist many variations of this exploit.
Sentence 2: for data fetch, authen­then-fetch requires three conditions to be satis.ed before the data fetch can be issued to the bus: 1) the fetch instruction itself be authenticated; 2) the fetch address be authenti­cated; 3) all the data or previously executed instructions for which the data fetch has data or control dependency be authenticated.
Relationship: neutral
Domain: Hardware
Sentence 1: Afterthe unitization, the possible SGPs and CGPs for each partition can be divided into two disjoint subsets, the internal con­.icts/stitches SGPi/CGPi which are inside the same par­tition and external con.icts/stitches SGPe/CGPe crossing the boundary of di.erent partitions.
Sentence 2: [5] M. Drapeau, V. Wiaux, E .Hendrickx, S. Verhaegen, and T. Machida.
Relationship: neutral
Domain: Hardware
Sentence 1: Similar loops where eachiteration carries adatadependencewith another iteration ataprecisedistance canbeparallelizedby synchro­nizing threads so that the dependent iteration (consumer) waits for its predecessor (producer) to update the shared data element before accessing it (DOACROSS).
Sentence 2: since extensive data alignment may lead to memory waste, rather than au­tomatically and silently aligning all OpenMP shared ob­jects, weprovideadirectivetocontrolalignment ofkeydata items.
Relationship: neutral
Domain: Hardware
Sentence 1: VLSI Layout and Packaging of Butter.y Networks  Chi-Hsiang Yeh Behrooz Parhami, E.A.
Sentence 2: inanl-levelhierarchicallayout,alevel-imodule,i=1,2,:::,l, consistsoflevel-(i;1)modulesasbasiccomponents,inter­connectedbylevel-iwires,whereeachlevel-0moduleisa networknodeandthesinglelevel-lmoduleistheresultant l-levelhierarchicallayout.Wecanvieweachlevel-(i;1) moduleasasupernode;thenthelevel-imodulebecomesa multilayerlayoutwithrulespresentedintheprevioussec­tion.themultilayerlayoutmodelisaspecialcase ofthehierarchicallayoutmodelwithasinglelevelofhier­archy.Aswehavetospecifytherangeofnodesizesinthe multilayerlayoutmodel,wehavetospecifythemaximum areawithinandthemaximumsizeofalevel-imoduleforall i;asanetworknodehasdegreeatmostd,wehavetospecify themaximumnumberofpins(orlinks)allowedforlevel-i modulesforalli.Moreover,theminimumwirewidthsmay bediferentatdiferentlevels.Notethattheremaybemore thanonetypeoflevel-imodulesallowedforsomei.These parametersareimportantforcomputingthefnalcostof thehierarchicallayout,whichmaybedeterminedbyafunc­tionoftheresultantarea,volume,and/orthenumbersof level-imodulesforsome/allvaluesofi.Notethatifacer­tainlevelisarea-limited,wemayconcentrateonlayoutat thatlevel.Similarly,ifareaandvolumearelessimportant atacertainlevel,wemainlyfocusonthepackagingcon­straintsand/orthemaximumwirelengthsothatpartition ofnetworksand/orthearrangementofnodesbecomemore importantissuesatthatlevel.
Relationship: neutral