sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: From this, we obtain the conditional distribution of p, using Theorem 3.1, as: ¯ PDF(pcond)= PDF (p|(dt = dr)) ~ N(µ¯p, Sp) (10a) -1 -1 T t tt µ¯p = AtS(dr -µt)and S¯p = I-AtSA(10b) where I represents the identity matrix, which is the uncon­ditional covariance matrix of p. The result (10) tells us that given the condition dt = dr, the mean and covariance matrix of pcond are no longer 0 and I.
Sentence 2: the entries in pcond can no longer be perceived as principal components.
Relationship: entailment
Domain: Hardware
Sentence 1: As we have addressed the challenge of extracting the four W s, deeper and interesting structures can be explored in the re­lationship between two or more of these W s. We begin to study these relationships by tackling the combination of who and what in broadcast news.
Sentence 2: we seek to address the question of who said what, that is, naming speaking persons and determining their respective quotes.
Relationship: entailment
Domain: Hardware
Sentence 1: Add4 Add4 Add4 Add4Ramp Ramp Ramp Ramp sinkphase0 phase1 phase2 phase3 time (b) Figure 9 : Non-FRDF vs. FRDF implementation In all cases, strict execution is assumed.
Sentence 2: a block can start its invocation after all its inputs are valid and finish its invocation after all its outputs are valid.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.1 Strategy for Combinational Blocks Combinational circuits may exhibit different degradation levels in each PMOS transistor because different inputs for the circuit can lead to different inputs at the gate of PMOS transistors.
Sentence 2: it may happen that some PMOS transistors degrade practically 100% of the time because they have a 0 at their gates most of the time, whereas some others may hardly degrade because they have a 1 at their gates.
Relationship: entailment
Domain: Hardware
Sentence 1: .i : tri .Tr, .m, n, x, y : rstm,rstn .Rst, tx,ty .T , such that tx = gent (tri), ty = reqt (tri), rstm = genr (tri)and rstn = reqr (tri).
Sentence 2: tx, ty, rstm and rstn represents the generated, required cycles and the gen­erating, requiring register stations of tri, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: The STA/LTA [14, 31] or Bayesian [28] methods can be used to detect the earthquake onset time.
Sentence 2: the Bayesian earthquake detection approach [28] developed in our previous work is based on in­network signal processing and decision fusion, in which local decisions of sensors are fused and onset time is estimated at the coordinator, and sent back to each sensor.
Relationship: entailment
Domain: Hardware
Sentence 1: We graphically represent the impact of operation pa­rameters on power consumption and energy e.ciency in Fi­gures 2 and 3 respectively for Nemesis and Erdos (results for Survivor are similar to the ones shown for Nemesis and are omitted).
Sentence 2: figures 2(a) and 3(a) report all possible .tting curves for the power consumption measure­ments, plus a curve marking the lowest achievable power consumption at a given load.
Relationship: entailment
Domain: Hardware
Sentence 1: N), the composition of the two af.ne relations is (1,f+pf1,pp1) II: c II an af.ne relation between c and c. c. D Another useful notion is synchronizability, which allows to guarantee the existence of a data.ow-preserving way to make two af.ne clocks synchronous.
Sentence 2: a .nite-size buffer protocol can be de.ned to synchronize such clocks.
Relationship: entailment
Domain: Hardware
Sentence 1: If this condition is satis.ed, it means that thebusis e.ectively addressingthismemoryand therequest can be satis.ed.
Sentence 2: the data value S in data w iswrittenattheproperlocation(in caseof S in STORE) or the stored value is returned on S o data r (enabling also the S o Ready signal) when a load (S in LOAD) is required.
Relationship: entailment
Domain: Hardware
Sentence 1: For example, video codecs, which are increasingly included in wireless devices such as mobile phones, utilize large data footprints and signi.cantly su.er from cache thrashing [1].
Sentence 2: in mobile phone systems, where power and area e.ciency are paramount, smaller, less-associative caches   Figure 1: Example of Cache Thrashing Reductions are typically chosen.
Relationship: entailment
Domain: Hardware
Sentence 1: on making parallel software portable with good performance and energy e.ciency, similar to the impact of the IEEE­754 standard had on portability of numerical software.
Sentence 2: we believe SHOT will lead to much larger im­provements in portability, performance, energy e.ciency of parallel codes than recent architectural fads like opportunis­tic turbo modes, transactional memory, or recon.gurable computing.
Relationship: entailment
Domain: Hardware
Sentence 1: ALTERNATE QUERY-ABORTABLE TYPE In this section we describe and show how to implement TQA a natural variant of the query-abortable type Tqa.Like Tqa, type TQA is strong enough to support the implementation of obstruction-free and pausable types, but it is simpler and slightly easier to use than Tqa.
Sentence 2: processes that use objects of type TQA can ap­ply the original operations of T without padding them with unique ids (recall that this padding is required to use objects of type Tqa).
Relationship: entailment
Domain: Hardware
Sentence 1: The workshop co-organizers: R. Iris Bahar: Brown University, Srinivas Katkoori: University of South Florida, Patrick H. Madden: SUNY Binghamton, Diana Marculescu: Carnegie Mellon Uni­versity, and Igor L. Markov: University of Michigan contributed signi.cantly to the consolidation of this material and preparation of this talk.
Sentence 2: patrick Madden and Igor Markov provided particularly valuable material and insights based on their considerable work in the area of de­signing contests and developing appropriate benchmarking in EDA [1].
Relationship: entailment
Domain: Hardware
Sentence 1: Now, the code fragment shown in Figure 3(b), written in a pseudo-language, accesses the data blocks 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, and 15, under the block struc­ture given in Figure 3(a).
Sentence 2: when this loop nest is executed, the order in which data blocks are accessed is 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that, as the number of cores sharing an L2 cache increases, theperformance improvement achievedbyCCS reduces due to the increased con.icts across the threads of di.erent applications.
Sentence 2: over the course of execution, the likelihood that the bottleneck threads from di.erent applications share a common cache increases, which, in turn, a.ects the e.ectiveness of CCS.
Relationship: entailment
Domain: Hardware
Sentence 1: On the other hand, x is the human interpretation of the register X.
Sentence 2: clearly, the vector (xm-1,...,x1,x0)represents xwith respect to a shifted poly­ { } aM-m nomial basis (SPB) ,...,aM-2,aM-1 .x and x collapse into each other in this case.
Relationship: entailment
Domain: Hardware
Sentence 1: Using com­mercial database transactions, we demonstrated that sub­threads can be an important part of an iterative approach to tuning the performance of speculative parallelization.
Sentence 2: we showed that sub-threads can be used to re­duce transaction latency, speeding up three of the .ve TPC-C transactions considered by a factor of 1.9 to 2.9.
Relationship: entailment
Domain: Hardware
Sentence 1: The greater the vari­ability of theindividualsintheinitialpopulation,thebetter the results are.
Sentence 2: for GAs with initialisation type 1, since all the individuals are identical at the beginning, the contribu­tion made by selection and crossover operators is negligible; thus the mutationis responsiblefor the evolution of thepop­ulation.
Relationship: entailment
Domain: Hardware
Sentence 1: 5 R-Schedules and the Schedule Tree As shown in [10], it is always possible to represent any single appearance schedule for an acyclic graph as (iLSL)(iRSR) (EQ 1) where SL andSR are SASs for the subgraphs consisting of the actors in SL and in SR , and iL andiR are loop fac­tors for iterating these schedules.
Sentence 2: the graph can be partitioned into a left subset and a right subset so that the schedule for the graph can be represented as in equation 1.
Relationship: entailment
Domain: Hardware
Sentence 1: Then, in optimizing procedure p(during the top­down phase), we consider the layout of the array (instance) with the largest weight.
Sentence 2: depending on the weights (of thesamearray) in p 0and p 00, we select the memory layout to use in determining the loop transformations in p. The second way of resolving such a con.ict is to employ a com­piler technique called procedure cloning.
Relationship: entailment
Domain: Hardware
Sentence 1: In particular, we propose that the steering logic considers predicted source operands to be mapped in all clusters only when the workload imbalance is higher than a given threshold (that we set empirically to DCOUNT=16 and DCOUNT=8, for a 4-cluster and a 2-cluster configura­tions, respectively).
Sentence 2: if the workload is very well balanced, the steering does not rely on value predic­tion to improve workload balance, since it may increase the communication requirements.
Relationship: entailment
Domain: Hardware
Sentence 1: On the contrary, if t is no larger than the minimum arrival time a1,then .f,t is a tautology (but .f=1,t and .f=0,t are not necessarily tautologies).
Sentence 2: .f,t =v,t equals constant 1, and furthermore .fcan be simpli.ed to f .¬v by .f=v,t =(f .¬v)..f,t.Observe that, =v,t-di in Equation (10), .giand ¬lit(gi) are always present together in a clause with ¬lit(gi)= gi.v.When .gi,t-di =1, =v,t-di since .gi = gi .¬v, this clause must be satis.ed due to (.gi =v,t-di .¬lit(gi)) = ((gi .¬v) .
Relationship: entailment
Domain: Hardware
Sentence 1: Due to the performance limitation of ILP method, we cannot obtain results in reasonable time (~hours) for (3) Assume columni (corresponding to pattern Pi) and columnj (corresponding to pattern Pj) be two columns in the constraint matrix B. Columni dominates columnj if for each row k, if Bkj = 1, then Bki = 1.
Sentence 2: if the faults detected by pattern Pi form a superset of the faults detected by pattern Pj, pattern Pi dominates Pj such that Pj can be removed.
Relationship: entailment
Domain: Hardware
Sentence 1: (1) i.e j.e e.E Now, let 1 = p. Then, the p-clique reads: C Lp (x) :=C Lp(x) =wij|xi - xj|p.
Sentence 2: (2) N e e.E e.Ei,j.e in this notation the 2-clique is the tradi­tional clique which can be replaced by a sparse model, the star.
Relationship: entailment
Domain: Hardware
Sentence 1: This is the reason why, in the context of this paper, we are particularly interested in formal veri.cation methods by Bounded Model Checking (BMC) [3] or Interval Prop­erty Checking (IPC) [15, 14] which are based on satis.ability (SAT) solving and a bounded system model.
Sentence 2: the operation­oriented methodology of IPC provides us with the basis for a fairly simple but effective abstraction mechanism.
Relationship: entailment
Domain: Hardware
Sentence 1: Hence the vector potential contribution is just R ' w(p2 - p1 ) GA (r, r) dr, and this only requires a simple scalar integral over the source triangle.
Sentence 2: similarly, Galerkin testing of the vector potential using a divergence-free basis function requires only a scalar integral over each observation p1 p2 rooftop p - p2 Figure 2: Divergence-free basis function w + V v for each shape i, initialize si to the vector (0, 0, 0) for each rooftop i with coe.cient wi let j be the index of the shape for rooftop i let pc be rooftop i evaluated at shape j s centroid sj + sj + wipc R R de.ne matrix As by As(i, j ) = j GA , where the i integrals are scalar integrals over shapes i and j multiply componentwise: u + Ass u is an array of vectors.
Relationship: entailment
Domain: Hardware
Sentence 1: Our goal is to design systems where even if attackers manage to bypass some basic security mechanisms, they will still face several control-speci.c security devices that will minimize the damage done to the system.
Sentence 2: we need to in­vestigate how to recon.gure and adapt control systems when they are under an attack to increase the resiliency of the sys­tem.
Relationship: entailment
Domain: Hardware
Sentence 1: We note that while the results of our instruction-dropping scheme show that we can effectively reduce committed errors by 1 2 orders of magnitude even with selective error checking, this approach does not necessarily allow for fewer ECC checkers to be active with­out hurting performance.
Sentence 2: while the 8-wide processor went from requiring 4 5 ECC checkers with full fault protection to 2 checkers with an order of magnitude reduction in committed faults, for a 4-wide machine, about the same number of checkers are needed.
Relationship: entailment
Domain: Hardware
Sentence 1: The performance of the optimized applications can be further improved upon as illustrated by the latter two bars, but un­tuned and optimized applications have similar performance characteristics in the limit as the untuned versions.
Sentence 2: for the tuned applications that we studied, the max­imum bene.t of any fancy coherence protocol is strictly less than 2x, and assuming communication cannot be eliminated, probably less than 1.3x.
Relationship: entailment
Domain: Hardware
Sentence 1: Our second contribution is to demonstrate, through extensive experiments, that a 3D L2 memory architecture generates much better results than the conventional two-dimensional (2D) designs under different number of layers and vertical (inter-wafer) connections.
Sentence 2: our experi­ments show that a 3D architecture with no dynamic data migration generates better performance than a 2D architecture that employs data migration.
Relationship: entailment
Domain: Hardware
Sentence 1: Combining Equations 2, 3, 5 and 7 yields X X aavgHPWLni Cn + aei HPWLei CeV 2f (8) ni.N ei.E By substituting aei in terms of wei (Equation 6), Equation 8 can be rewritten as X X aavgHPWLni Cn + aavgwei HPWLei CnV 2f ni.N ei.E (9) Let K be aavgCnV 2f, M = N.E and the weight value of signal net ni be wni = 1.
Sentence 2: then, X Psw = PN + PE = Kwmi HPWLmi (10) mi.M our techniques capture the switching-power minimization problem, which can be solved by any high­quality wirelength-driven placer capable of net weighting.
Relationship: entailment
Domain: Hardware
Sentence 1: Power/temperature reduction techniques: Since temper­ature and supply voltage highly affect both BTI and HCI, a power reduction technique which reduces the overall temper­ature can be used to improve the lifetime.
Sentence 2: it is shown in the literature that power gating [29, 30], dynamic voltage and frequency scaling [31, 32], and adaptive body biasing [33] can alleviate aging.
Relationship: entailment
Domain: Hardware
Sentence 1: The validity of this assumption, however, is questionable with the ever-decreasing feature size of today s VLSI technology and the ever-increasing cir­cuit operational frequency.
Sentence 2: when functional intercon­nects such as network-on-chip (NoC) are reused as TAMs, even if they have passed manufacturing test beforehand, failures caused by electrical noise such as crosstalk and transient errors may happen during test data transfer and make good chips appear to be defec­tive, thus leading to undesired test yield loss.
Relationship: entailment
Domain: Hardware
Sentence 1: In this PLL example, the entropies of the nodes and their dependencies were measured with 256, 36-ns long simulations, while the worst-case lock-time of the PLL was as long as 8-µs.
Sentence 2: a brute-force method of running 8-µs long simulations with 256 random initial conditions would take 200× longer time.
Relationship: entailment
Domain: Hardware
Sentence 1: Using Lin-Kernighan Algorithm for Look-up Table Compression To Improve Code Density Talal Bonny and Joerg Henkel University of Karlsruhe Chair for Embedded systems Karlsruhe, Germany {bonny,henkel}@informatik.uni-karlsruhe.de ABSTRACT The presented work uses code compression to improve the design e.ciency of an embedded system.
Sentence 2: we present a method and architecture for compressing the so­called Look-up Tables that are necessary for the de-compression process.
Relationship: entailment
Domain: Hardware
Sentence 1: Second, because transmissions occur on the slot basis, and a uniform slot length is adopted across the network, the start time of tsP,i : Ni sends  ti PROBE trP,i+1: Ni+1 receives .ti=tsA,i+1-trP,i+1  tsA,i+1: Ni+1 sends ti ACK PROBE  trA,i : Ni receives  TRIGGER  ACK TRIGGER  Figure 2: Slot length estimation the .rst slot must be synchronized on all nodes.
Sentence 2: each node needs to align its transmission timeline to match others.
Relationship: entailment
Domain: Hardware
Sentence 1: Energy-Ef.cient Bus Encoding for LCD Displays Alberto Bocca* Sabino Salerno* *  Politecnico di Torino Torino, ITALY ABSTRACT This paper presents a low-power bus encoding technique suitable for the digital interface to a Liquid Crystal Dis­play (LCD).
Sentence 2: we focus on interfaces that are compliant to the Digital Visual Interface (DVI) standard, in which the three color channels are serially transmitted to achieve high bandwidth.
Relationship: entailment
Domain: Hardware
Sentence 1: Using conservative values for the number of trajectory samples and nearest neighbors required for interpolation (s = 1000, k =5), tells us that the number of groups that we would have to handle would be ~1013.This brute force approach would obviously create groups of points that are spatially located far from each other and hence would never be used.
Sentence 2: they will not be the k nearest neighbors for any given point in the state-space.
Relationship: entailment
Domain: Hardware
Sentence 1: For a logic function with density d (edge ratio of inclusion to exclusion) and size n × m, each mapping trial in the solution space is valid with probability: )dnm(1 - rc)(1-d)nm pv =(1 - ro (1) where dnm is the number of inclusions and (1 - d)nm is the number of exclusions in the LBG.
Sentence 2: when ro = rc, pv =(1 - r/2)nm .
Relationship: entailment
Domain: Hardware
Sentence 1: Conven-tional standard cell libraries and conventional logic synthe-sis tools are used, as the new asynchronous logic circuits are generated in a so-called de-synchronization manner.
Sentence 2: the circuit is transformed to an asynchronous version in a plug-compatible manner, meaning that the asynchronous circuit functions in exactly the same way as the synchronous version, with flip-flops in the same positions within the cir-cuitry.
Relationship: entailment
Domain: Hardware
Sentence 1: Energy-Aware Computation Duplication for Improving Reliability in Embedded Chip Multiprocessors * G. Chen, M. Kandemir, and F. Li Computer Science and Engineering Department Pennsylvania State University e-mail: {guilchen,kandemir,feli}@cse.psu.edu Abstract Compilers designed for current embedded systems must be capable of addressing multiple constraints such as low power, high performance, small memory footprint and form fac­tor, and high reliability at the same time.
Sentence 2: optimiz­ing for one constraint should be performed carefully, consider­ing its impact on other constraints.
Relationship: entailment
Domain: Hardware
Sentence 1: According to Step 1 of algorithm, the packet will first follow that path leading to a node where Row Numbers of Present and Destination addresses are same.
Sentence 2: if (Row Numbers of Source and Destination are different) { for (i = log2 M; i >= 1; i --) { if (ith bit position of the Row Numbers of Source and Destination are different) {       k = i; break ; } } Route upwards by k hops in Column Tree. }
Relationship: entailment
Domain: Hardware
Sentence 1: To derive PERI, we use the principle of the skewness, i.e., the relative difference between the mean and the median.
Sentence 2: the Pearson Skewness [14] is defined as µ2 /s6 , and the Pearson Skewness Coefficient [14] is 3 defined as (µ M)s. The skewness and the skewness / coefficient are proportional, i.e., (µ M)s.µ32 /s6.
Relationship: entailment
Domain: Hardware
Sentence 1: We exploit this trend towards FPGA-based acceler­ator design and propose a data path con.gurable stream architecture that focuses on separated design strategies for computing and memory .ows.
Sentence 2: we introduce our work on accelerating a large-scale scienti.c application, called EMAN [3], which is an open source software package for single-particle 3D reconstruction from Cryo-electron mi­croscopy images, onourcustomizedFPGA accelerator card.
Relationship: entailment
Domain: Hardware
Sentence 1: Inside our model, that will mean that from among all neighbors of a router i, the one that sends the largest amount of tra.c, say router j, should have a higher determining impact on the status of router i.
Sentence 2: if a router is sur­rounded by routers with increased tra.c (i.e., higher bu.er utilization, status High in Fig.1), its status will likely be in­.uenced toward having a lot of tra.c too.
Relationship: entailment
Domain: Hardware
Sentence 1: We aim at introducing a reliability-related analysis, dif­ferent from validation and veri.cation, based on the fun­damental concept of fault model that has to be de.ned at the various abstraction levels, possibly deriving a relation between them.
Sentence 2: we extend our preliminary work[2] onthe mechanisms forcarrying outdependability analysis(inrelationtothepossiblefault models) toclassify faults in TL descriptions and to provide guidelines to de­rive them when the system is speci.ed at a high abstraction level.
Relationship: entailment
Domain: Hardware
Sentence 1: Hence, a uniquemaximal transformation (with respect to partial signature vectors),TC (which will be canonical) can be identified among T1, T2, ,Tl,.
Sentence 2: the maximal transformation(s) has the maximal partial signature vector with respect to the lexicographical ordering p discussed in section IV, among the transformations T1,T2, ,Tl.
Relationship: entailment
Domain: Hardware
Sentence 1: ECE, The Ohio State University 2015 Neil Ave., Columbus OH 43210 hwangsu@ece.osu.edu ABSTRACT In this paper we propose a novel method for communication over underwater acoustic channels for which the product of delay-spread and Doppler-spread is large, such as those per­taining to the surf zone.
Sentence 2: we propose the use of pulse-shaped multicarrier modulation to convert the dou­bly dispersive channel into an inter-carrier interference (ICI) channel with small ICI spread.
Relationship: entailment
Domain: Hardware
Sentence 1: The PIRATE NoC-IP is composed of a set of parameterized modules, such as interconnection elements and switches, to generate di.erent network topologies.
Sentence 2: the PIRATE Noc-IP is supported by a synthesizable RTL generator of the con.g­urable NoC-IP core, an automatic power characterization .ow, and a cycle-based NoC simulator for the dynamic pro­.ling of power and performance at the system-level.
Relationship: entailment
Domain: Hardware
Sentence 1: IN,t(b ' (x)i) t(a ' (x)i+n) The above lemma de.nes necessary and su.cient condi­tions for two components P and Q so that if they are con­nected by an nF if o, they can perform the same behavior as when they are put in an arbitrary asynchronous network.
Sentence 2: all read actions of component Q from x can be delayed at most for n more write actions of P on the same variable (thus, preventing bu.er over.ow).
Relationship: entailment
Domain: Hardware
Sentence 1: Workload prediction is incorporated in this work to provide partial information about service request (SR) state for the RL algorithm.
Sentence 2: an online naïve Bayes classifier [14] is selected as the workload predictor because of its relatively high prediction rate, as well as the fact that the partial information it provides contains certain degree of certainty due to the use of posterior probability in such algorithm.
Relationship: entailment