sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: As transistors 2 and 3 are physically located close to each other (both in the PRAM peripheral circuit), they are likely to share a similar variation due to correlation.
Sentence 2: we assume variations exhibit correlation between transistors 2 and 3, lower current and this observation is consistent with [22], which designs low power PRAM using a ring type contact to achieve a minimum programming current.
Relationship: reasoning
Domain: Hardware
Sentence 1: E such that t(v) <t(u)+ d(u, v) - (w(u, v)+ r(v) - r(u))T. Due to (4), it implies that t1(v) <t(u)+ d(u, v) - (w(u, v)+ r1(v) - r(u))T or fd(v) <t(u)+ d(u, v) - (w(u, v)+ r1(v)+1 - r(u))T Since t1(v) = T ,itisalwaystrue that t1(v) <t(u)+ d(u, v) - (w(u, v)+ r1(v) - r(u))T, which contradicts (6).
Sentence 2: the solution to (4) is also a solution to (1)-(3).
Relationship: reasoning
Domain: Hardware
Sentence 1: This surface is dynamically updated with the newly-observed (sL2,sL3) values and the corresponding d values to adapt to the dy­namic modulations in thread behavior.
Sentence 2: if a thread is allocated the same (sL2,sL3) ways at two di.er­ent points during its execution, we update the surface with the most recently-observed d value (for that allocation pair).
Relationship: reasoning
Domain: Hardware
Sentence 1: Flip-Flops X are used to hold the partial result, while .ip-.ops N, T, GZ, and BN are used to hold the quan­tities N, 2N, B, and 2B +2N, respectively.
Sentence 2: multi­plexer X-Mux can drive into the adder one of the quanti­ties 0, B, N,or B + N, while multiplexer Z-Mux can do the same with quantities 0, 2B, 2N,or 2B +2N.
Relationship: reasoning
Domain: Hardware
Sentence 1: The idea of partition-based placement is rooted in the assumption that loosely connected cells can be placed farther away.
Sentence 2: if the worst-case intra-level delay of this sub-region is less than the inter-level delay, or more generally the intra-level connection cost is less than inter-level connection cost, inter-level partitioning should be done and partitioned sub-circuit should be assigned to different levels.
Relationship: reasoning
Domain: Hardware
Sentence 1: This graph in turn reveals which simpler patterns can be covered by a complex instruction during code gen­eration, again by applying the appropriate identity operands to its inputs.
Sentence 2: these simpler patterns need not be im­plemented as individual instructions if the complex pat­tern is chosen for implementation provided that the pos­sibly slower execution and the cost of applying the identity operands can be afforded.
Relationship: reasoning
Domain: Hardware
Sentence 1: Ensemble of LDPC codes using design method I. FER 0.73 0.67 G0 G1 G2 G3 G4 G5 G6 G7 G8 Size 2560 1311 206 19 0 0 0 0 0  A limitation of the design method I is that the performance for higher puncturing (code rate above 0.8 for a rate 0.5 mother code) is not good enough to support the code rate over 0.8.
Sentence 2: the other design method needs to be considered for designing an ensemble with subset codes, which has good FER performance at higher rate above 0.8.
Relationship: reasoning
Domain: Hardware
Sentence 1: Also for ultra-low power nanomagnetic logic (NML), although it is operating at relatively low clock frequencies, the Landauer heat can make the difference between a battery life of a month or several years.
Sentence 2: the heat cost of logical irreversibility is important, and there are three main approaches to keep the heat density in allowable limits: a) decreasing the logic density, b) bringing down the operating frequency, and c) developing at least partially reversible logic structures.
Relationship: reasoning
Domain: Hardware
Sentence 1: For the baseline 1MB cache, LRUincursan MPKIof136,both LIP and BIP incuran MPKIof 115 (17% reduction over LRU), and OPT incurs an MPKI of 101 (26% reduction over LRU).
Sentence 2: both LIP and BIP bridge two­thirds of the gap between LRU and OPT without extra storage.
Relationship: reasoning
Domain: Hardware
Sentence 1: of Informatics Aristotle University of Thessaloniki Thessaloniki, Greece panagakis@aiia.csd.auth.gr  ABSTRACT Speech signals convey information not only for speakers identity and the spoken language, but also for the acqui­sition devices used during their recording.
Sentence 2: it is reasonable to perform acquisition device identi.cation by analyzing the recorded speech signal.
Relationship: reasoning
Domain: Hardware
Sentence 1: We instead use a simpler metric, as in [4], the absolute value of kurtosis, de.ned as 4 2 |kurt(vi)| = |E[vi ] - 3E[vi ]2| (11) When vi is Gaussian, the above metric reaches its minimum value: 0.
Sentence 2: maximizing nongaussianity is equivalent to maximizing the the absolute value of kurtosis.
Relationship: reasoning
Domain: Hardware
Sentence 1: Similarly, the robust strategy improves the gate leakage dissipation by 15.5% at the 99th percentile, as illustrated in Figure 7.
Sentence 2: the robust method can utilize the partial Cumulative Probability 0.92 0.91 0.90 1.0 1.1 1.2 1.3 1.4 1.5 1.6 Subthreshold Leakage Current (normalized) Figure 6.
Relationship: reasoning
Domain: Hardware
Sentence 1: Additionally, the ratio between the total number of tasks M that are running on the given on-chip system and the number of cores N also play a role in the decision of CU-AB, because having more tasks than cores provides more opportunity to achieve thermal balance between the cores.
Sentence 2: we define a run-time parameter, called DyBal, which is dynamically re-adapted if M changes allowing more task migrations when dealing with several tasks; see Eq.8.
Relationship: reasoning
Domain: Hardware
Sentence 1: Because of the exponential relation between the leakage current (static power) and the device dimensions, the leakage current variation distribution is approximately lognormal.
Sentence 2: power consumption ex­hibits multiplicative variation, i.e., pu = fupu0 , where pu 0 and pu are nominal power and real power consumption of the gate gu, respectively, and fu is the scaling factor.
Relationship: reasoning
Domain: Hardware
Sentence 1: On the other hand, the energy consumption of our proposal is about 0.6% of the total energy footprint for a compa­rable in-order processor, using a CACTI [24] ap­proximation.
Sentence 2: our proposed technique can deliver most of the same bene.ts with regard to resolving memory stalls, but at a fraction of the energy consumption and area utilization of an out­of-order processor.
Relationship: reasoning
Domain: Hardware
Sentence 1: THE ROLE OF AUTOSYMMETRY Tounderstandtheroleofautosymmetrifuntionswe mustomparethemwiththesetofallpossiblefuntions.
Sentence 2: k-0123456789101112Tot #funt365ll672954l433927l6245828l8942 %funt38.9l2.37.6lO.l4.34.64.l2.9l.72.46.23.Ol.9lOO #AC 264 82 55 54 23 35 2l lO 2 O O O O 546 #A O 5 4 5 9 7 l6 9 l4 24 58 28 l8 l97 #* lOl 29 l3 36 9 l 2 8 O O O O O l99 Avg(TA/Tc) l.Ol O.63 O.42 O.37 O.32 O.27 O.O7 O.OO4 O.OOOl - - - - - Table2:Distributionofk-autosymmetrifuntionsintheEspressobenhmarksuite.#funtarethetotalnumbersof funtions(singleoutputs)foranyvalueofk,and%funtaretheorrespondingperentages.Theotherrowsreportthe numberofk-autosymmetrifuntionssynthesizedwiththenewAlgorithm.,andwiththepreviousbestAlgorithm C(#AC);synthesizedwith.only(#A),sineCdidnotterminate;notsynthesizedatallsinebothalgorithmsdid notterminate(#*).Avg(TA/Tc)istheaverageoftheratioTAandTcarethetimesrequiredbythetwoalgorithmson ThetotalnumberofBooleanfuntionsofnvariablesis NF=22n ,orrespondingtoallthewaysasubsetofpoints anbehosenin{0,1}n .Thisisahugenumber,however, duetotherandomnessoftheabovegeneratingproessvery manyofsuhfuntionsdonotorrespondtoanysignif­antiruit.Autosymmetrifuntionsarejustasubset oftheabove.Byaountingargument(omittedherefor brevity)weaninfatprovethatautosymmetrifuntions areNA =(2n -1)22n.l .forinreasingn,au­tosymmetrifuntionsonstituteavanishingfrationofall thefuntions,asNA/NFgoestozeroforngoingtoinfnity.
Relationship: reasoning
Domain: Hardware
Sentence 1: We refer to cache lines that are not referenced between insertion and eviction as zero reuse lines.
Sentence 2: figure 1 shows that for the base­line 1MB 16-way LRU-managed L2 cache, more than half the lines installed in the cache are never reused before getting evicted.the traditional LRU policy results in inef.cient use of cache space as most of the lines installed occupy cache space without contribut­ing to cache hits.
Relationship: reasoning
Domain: Hardware
Sentence 1: A table is mapped to certain banks, and the table-to-bank mapping is avail­able in the query optimizer.
Sentence 2: if the table inter-access time is T , and the resyn­chronization time is Tp (assuming less than T ), then the optimizer can transition the associated modules into a low-power mode (with a unit time energy of Ep) for the initial T - Tp period (which would consume a total [T - Tp]Ep energy), activate the module to bring it back to the active mode at the end of this period following which the module will resynchronize before it is accessed again (consuming TpEa energy during the transition assuming that Ea is the unit time energy for active mode as well as during the transition period).
Relationship: reasoning
Domain: Hardware
Sentence 1: The B*-tree is partic­ularly suitable for representing a .oorplan/placement with mixed-size blocks, like the blocks and the I/O buffers for the .ip-chip design; further, it does not have the cell height and the row placement constraints, imposed by the classi­cal placement algorithms.
Sentence 2: we shall take advantage of the nice prop­erties of the B*-tree to develop our algorithm for .ip-chip placement.
Relationship: reasoning
Domain: Hardware
Sentence 1: It means that there is a vt assign­ment solution with the cost P satisfying T.(2) .> 1+ E.In this case, it means that there exists a constraint which can­not be evaluated to 1 in the optimal solution.
Sentence 2: there is no vt assignment solution with the cost P satisfying T. and D(gi)+ci,j + (3) 1 <.
Relationship: reasoning
Domain: Hardware
Sentence 1: For short distances (i.e., hundreds of micrometers), the path over the TSV and M1 (e.g., the TSV path) exhibits a lower impedance as compared to the path consisting of M6 and the stack of vias.
Sentence 2: most of the current flows through the TSV path resulting in a substantially smaller voltage drop as compared to the circuit shown in Figure 4b.
Relationship: reasoning
Domain: Hardware
Sentence 1: Papers, Figure 13: Active power comparison at 110oCbe­tween (a) ZBB (0.55V), DBB (0.5V) and TABB (0.5V), and (b) ZBB (0.4V), ODBB (0.35V) and TABB (0.35V).
Sentence 2: for high temperature operation, TABB is an attrac­tive FBB scheme with Vfbb = Vdd at near-room tempera­tures and progressively decreasing Vfbb at higher tempera­tures.
Relationship: reasoning
Domain: Hardware
Sentence 1: When variations are modeled as RVs, it is common to think of the bounds Xmax and Xmin as being the ±3s limits of the i i normal distribution of Xi.In other words, if s2 is the variance i of Xi then Xmax =+3si and Xmin = -3si.For any normal i i distribution with mean µ and variance s2,the interval µ ± 3s covers 99.73% of the distribution: Fµ,s (µ +3s) - Fµ,s (µ - 3s)= F(3) - F(-3) = 0.99731 (3) where Fµ,s (·) is the cdf of the normal distribution with mean µ and variance s2,and F(·) is the cdf of the standard normal distribution (i.e., the normal distribution with a mean of 0 and a variance of 1).
Sentence 2: for all practical purposes, almost all of the distribution lies within the ±3s limits.
Relationship: reasoning
Domain: Hardware
Sentence 1: Hence, runahead execution is not able to paral­lelize two long-latency cache misses if the load instruction generat­ing the second miss is dependent on the load instruction that gener­ated the .rst miss.1 These two misses need to be serviced serially.
Sentence 2: the full-latency of each miss is exposed and the latency tolerance of the processor cannot be improved by runahead execu­tion.
Relationship: reasoning
Domain: Hardware
Sentence 1: (15) a i.NMOS which can also be expressed in the Weibull scale [1] as (()) L()ß 1 -Pr(ckt) .it W =ln -ln fail (t)=ln Pr(i)ai a i.NMOS () L t = ß ln +ln Pr(i).iß ai.
Sentence 2: (16) a i.NMOS the failure probability of a large digital circuit also follows the Weibull distribution, and has the same slope ß as a single device.
Relationship: reasoning
Domain: Hardware
Sentence 1: The store operation termination was added because with coherent L1 caches, a store would cause an exclusive access in one of the caches, effectively invalidating it from the others.
Sentence 2: in Figure 4, the pro.ler would begin at the current memory access LD 4, and travel back noting that load LD 2 and store ST 1 accessed the same block.
Relationship: reasoning
Domain: Hardware
Sentence 1: The junction temperature T1 and T2 can be estimated as: T1 =QR 11 +(Q1 +Q2)Re (12) T 2 =QR 22 +(Q1 +Q2)Re Hence, the general term of the equation for calculating junction temperature by considering inter-heat source correlation can be estimated as: i = ii +(Q1 +Q2 +Q3 +.... +Qn) e (13) TQR R Re =R1// R2 // R2 // .......// Rn Where Ti is the junction temperature of ith heat source, Qi and Ri are the heat generated by the ith heat source and the thermal resistance along the heat dissipation path for the ith heat source before the heat from different sources merge together.
Sentence 2: based on Equation (8), it is possible to calculate the thermal resistance of each intermediate layer.
Relationship: reasoning
Domain: Hardware
Sentence 1: From Figure 8, the actual capacitance between two CNTs will be the series equivalent of two CQ and CC.
Sentence 2: the net capacitance between two opposite polaritynearest neighbor CNT electrodes in CNCAP1 is: -1 CaF()+1 400aF =14.5aF =+1 400 1 15.6aF NET With four parallel CNET capacitors for every anode, we have a total capacitance per unit area of: 4(14.5aF)/50nm2 or 58aF/50nm2.
Relationship: reasoning
Domain: Hardware
Sentence 1: The prediction given by (17) is actually the optimal continuous-time causal LMMSE predictor for a conti nuous-time (non-bandlimited) Gauss-Markov source hav­ing a PSD with the same shape as the PSD of ßm(t), but without the bandlimitedness.
Sentence 2: the predic­tion given by the Green s Theorem makes use only of the immediate previous sample as in a Gauss-Markov process.
Relationship: reasoning
Domain: Hardware
Sentence 1: Similarly, the workload of a RF after the image region partition, the processing region binding, and the template binding is defined to be the sum of products of rows of each assigned processing region and the number of assigned corresponding templates.
Sentence 2: it is clear that the image region partitioning, the processing region binding, and the template binding is a way to partition the GTM workload among the selected RFs.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, while pre­defined blocks have ease of use advantages, they may result in more blocks in a network, resulting in larger network size, higher cost, and increased power consumption.
Sentence 2: we have developed capture, simulation and synthesis tools that enable a user to specify a network using pre­defined blocks (representing a behavioral description) and to simulate that network to verify correct behavior, and that automatically synthesize an optimized network using programmable blocks with automatically generated software.
Relationship: reasoning
Domain: Hardware
Sentence 1: Unlike other studies that use single temperature to measure the leakage power of the IC, we used the high spatialresolution temperatureof theprocessor to estimate the leakage power.
Sentence 2: assuming the IC surface is divided into an m× n grid, the total leakagepower of the processor is calculatedby: mn we use our sensory circuit to measure), and the information Pleakage = ·· N[i,j] Ileakage[i,j] Vdd regarding heat dissipation in the corresponding temperature i=1 j=1 range for cooling down, which can be precisely calculated based on the Newton s law of cooling.
Relationship: reasoning
Domain: Hardware
Sentence 1: 5.1 The Hierarchical Layout Model Aparallelcomputeristypicallybuiltfromseveralchips onaboard,multipleboardsinacabinet,andseveralsuch cabinetsinterconnectedtogether.Modulesateachlevelof thepackaginghierarchyhavetheirrespectivecharacteristics intermsofthenumberofpins,maximumarea,minimum wirewidth,maximumallowablewirelength,andthenum­berofwiresperlink[2].Inwhatfollows,weconsiderthe casewhereseveralnodes(processors,routers,andassociated memorybanks)ofanetworkareimplementedonasingle chip,ormoregenerally,asinglemodule(e.g.,chip,board, wafer,ormulti-chipmodule(MCM)),andseveralmodules areusedtobuilttheparallelarchitectureorahigher-level module.Sincethenumberofavailableof-modulepinsper node,inadditiontolayoutarea,isoneofthemajorcon­straintslimitingtheperformanceandthenumberofpro­cessorsthatcanbeputonamodule,efcientpartitionis crucialtoobtainingefcienthierarchicallayouts.
Sentence 2: inanl-levelhierarchicallayout,alevel-imodule,i=1,2,:::,l, consistsoflevel-(i;1)modulesasbasiccomponents,inter­connectedbylevel-iwires,whereeachlevel-0moduleisa networknodeandthesinglelevel-lmoduleistheresultant l-levelhierarchicallayout.Wecanvieweachlevel-(i;1) moduleasasupernode;thenthelevel-imodulebecomesa multilayerlayoutwithrulespresentedintheprevioussec­tion.themultilayerlayoutmodelisaspecialcase ofthehierarchicallayoutmodelwithasinglelevelofhier­archy.Aswehavetospecifytherangeofnodesizesinthe multilayerlayoutmodel,wehavetospecifythemaximum areawithinandthemaximumsizeofalevel-imoduleforall i;asanetworknodehasdegreeatmostd,wehavetospecify themaximumnumberofpins(orlinks)allowedforlevel-i modulesforalli.Moreover,theminimumwirewidthsmay bediferentatdiferentlevels.Notethattheremaybemore thanonetypeoflevel-imodulesallowedforsomei.These parametersareimportantforcomputingthefnalcostof thehierarchicallayout,whichmaybedeterminedbyafunc­tionoftheresultantarea,volume,and/orthenumbersof level-imodulesforsome/allvaluesofi.Notethatifacer­tainlevelisarea-limited,wemayconcentrateonlayoutat thatlevel.Similarly,ifareaandvolumearelessimportant atacertainlevel,wemainlyfocusonthepackagingcon­straintsand/orthemaximumwirelengthsothatpartition ofnetworksand/orthearrangementofnodesbecomemore importantissuesatthatlevel.
Relationship: reasoning
Domain: Hardware
Sentence 1: How­ever, we cannot assume the origin does not move, because the camera is much closer (close-capturing) to the violin compared with the right hand situation and the movement of violin during playing must be considered.
Sentence 2: we set a 50 by 50 square area in pixels around the initial ori­gin, and use a motion estimation technique to .nd the best match positions (xf0,i,yf0,i) of this region in the following frames, and obtain the trajectory of the origin (Xf0,Yf0).
Relationship: reasoning
Domain: Hardware
Sentence 1: In contrast, when the data lifetime of the cache block exceeds 7ms, the data block should be placed in the RRAM-based cache to reduce (a) Redundant bit-writes discarding by RSE scheme, (b) Avoid access conflicts based on Sequential tag-data access Figure 6: A non-volatile SRAM last-level cache leakage power from the SRAM-based cache.
Sentence 2: using only one cache type for different cache blocks is impractical.
Relationship: reasoning
Domain: Hardware
Sentence 1: Symbol 2 following symbol a has the fastest rising edge and symbol 8 following symbol 0 has the slowest rising edge.
Sentence 2: lev2 -vth lev8 -fvmin DDJ = t · ln( ), (13) lev2 -fvmax lev8 -vth  where fvmax is the .nal voltage of symbol a and fvmin is the .nal voltage of symbol 0.
Relationship: reasoning
Domain: Hardware
Sentence 1: Similarly, the effective switching capacitance Cef,i may also be different for each task Ti.
Sentence 2: the total energy consumption of task Ti at frequency f will depend on task characteristics and it can be modeled as: Ei =Ps · Di +(Pind,i +Cef,i fm)· ti(f) (9) where Di is the time period allocated to task Ti.
Relationship: reasoning
Domain: Hardware
Sentence 1: We generated 100 static traces for each system3and for each static trace, we generated 100 random cache con.gurations.
Sentence 2: for each of 100*100 = 10,000 cache con.g­urations, we ran cycle-accurate behavioral simulation of the sys­ 3To generate a static trace, we choose a random cache con.guration and run cycle­accurate simulation of the system.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, in scenarios where dark silicon can be used pro.tably, decreasing area in lieu of exploiting it would certainly decrease system costs, but these decreases in area would have much more catastrophic e.ects on sale price, if it results in compromised performance or functionality relative to the competition.
Sentence 2: the shrink­ing chips scenario is likely to happen only if we can .nd no practical use for dark silicon.
Relationship: reasoning
Domain: Hardware
Sentence 1: In a fully associative cache with optimal re­placement the data that is implicitly prefetched can stay in the cache long enough to be used (since it is not replaced by other, less critical data), but in a direct-mapped cache it might be replaced before it is used.
Sentence 2: we have presented a survey of techniques aiming at reducing con.ict misses and cache organizations that support variable block sizes and fetch large blocks if there is su.cient spatial locality and small blocks if not.
Relationship: reasoning
Domain: Hardware
Sentence 1: The rea­son is that leakage is set by fundamental principles of de­vice physics, and is limited to a sub-threshold slope of 60 mV/decade at room temperature; that is, in the typical case, a reduction of 10× for every 60 mV that the thresh­old voltage is above the Vss, which is determined by prop­erties of thermionic emission of carriers across a potential well.
Sentence 2: although innovations like Intel s FinFET/Tri-Gate transistor, high-K dielectrics, etc, represent signi.cant achievements maintaining sub-threshold slope close to their historical values, they still remain within the scope of the MOSFET-imposed limits and are one-time improvements rather than scalable changes.
Relationship: reasoning
Domain: Hardware
Sentence 1: The slope starts to saturate at a higher ambient index value, and reaches an ambient refractive, implying that employing the proposed cladding structure can expand the operational range of the TFBG sensor.
Sentence 2: it indicates that the refractive index sensor with enhanced sensitivity can be used to measure small changes in index of the surrounding medium; here, the resolution of the refractive index measurement is of the order of 10-4.
Relationship: reasoning
Domain: Hardware
Sentence 1: = 1 Kvco = 55 MHz/V (td + tp)= 3nS Fs = 80 MHz Q= 8 tdn f = 250pS F = 10 tdn r = 300pS Prescalar fc = 0.5 MHz tup f = 300pS sdiv = 0.055 × Tvco tup r = 250pS CP/PFD non-linearities are primarily responsible for the in-band noise in a type-II frac-N PLL [9].
Sentence 2: close attention was paid to improving the linearity of the CP and the PFD.
Relationship: reasoning
Domain: Hardware
Sentence 1: (7)  Note that EievYi~(j,i)eECll(j,i) = E(i,j)eeyycll(i,j), and Eiev Yi E(j,i)eE coo (j, i) : E(i,j)EE yjCoo (i, j).
Sentence 2: cF = ~iev [yicl(i)+ yico(i)] + ~(i,j)eE [yjclI(i,J) +.~jcoo(i,j)-F YiyjcoI (i, j) -YiYjCll (i, j) + YiYjcto(i, j) -- YiYjco0(i, j)].
Relationship: reasoning
Domain: Hardware
Sentence 1: pairs (yi, ci), i = 1 to n. Then the control variates estimate EFCV[Y ] of E[Y ] is:  n n EFCV[Y ] = 1 yi - ß1 ci - E[C](15) n n i=1 i=1 where ß is a constant that has to be determined.
Sentence 2: eFCV[Y ] is unbiased [11] and thus its MSE is equal to its variance given by: n c Var(Y ) Cov(Y, C ) Var(C) Var EFCV(Y ) = -2ß +ß2 (16) n n n The value of ß which minimizes the variance in (16) is given by: Cov(Y , C )ßoptimal = (17) Var(C) which leads to the following optimal variance: n c Var(Y ) n c Var EFCV(Y ) = 1 - Corr2(Y , C ) (18) n if Y and C are highly correlated, a signi.cant vari­ance reduction can be achieved for expected value estimation.
Relationship: reasoning