sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: 1.2 1 ) 0.138 -0.275 1.77 ß = 0.742 + 0.0129R - 0.0287C + 0.443 (C R t (13) Wt tt 0.8 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Interconnect W idth (m) x 10-7 Figure 7: Stage Delay vs. Interconnect Width  3.2 Determining Performance Corners PECAN uses PminGL to find the performance corners of a stage.
Sentence 2: the location of PminGL in relation to the range Pmin to Pmax determines the location of the performance corners.
Relationship: entailment
Domain: Hardware
Sentence 1: WIRELESS INTERCONNECT ANALYSIS The electromagnetic radiation e.ects of the wireless in­terconnect system on a die are investigated using an FEM­based full-wave simulation analysis.
Sentence 2: the wire­less interconnect system is analyzed for the coupling of the transmitting and receiving antennas as well as the (unde­sirable) coupling between the transmitting antenna and the metal interconnects.
Relationship: entailment
Domain: Hardware
Sentence 1: The bene.t of parameterized states is that Caisson can synthe­sizeasingle logic circuit that can safelybe usedat multiple security levels.
Sentence 2: the data being operated on (the Caisson reg­isters) musthave distinct types,but the logic operating on thedata (theCaissonstates)canbe parameterizedoverthetypesofthedata, making the synthesized circuit much more ef.cient.
Relationship: entailment
Domain: Hardware
Sentence 1: hw count sw count  random 100 95 90 85 80 fop antlr bloat lusearch xalan jython pmd luindex average lected forimplementationease.
Sentence 2: thevariationthatwe observedin eachoftheseexperimentswas not statistically signi.­cant relativetothedistributionof resultsachievedfrom initializing theLFSRwith differentvalues.
Relationship: entailment
Domain: Hardware
Sentence 1: Since a RS-repeater can store up to two .its, the distributed storage on a channel of K RS-repeaters is equal to 2 · K. But, the fact that a relay station contains the logic implementing the low-level .ow control mechanism makes it possible to reduce the size of the downstream queue to a minimum value that is always as if K = 0.
Sentence 2: (Qmin = 1) is su.cient when combining RS-repeaters with the ack/nack .ow control mechanism.
Relationship: entailment
Domain: Hardware
Sentence 1: For the call graph example in Figure 2(c), a typical cloning (assuming p 0and p 00demand different layouts for the same array) creates two versions of p(denoted p.and p..in Figure 2(d)), one for each layout.
Sentence 2: the loop transformations in p.are applied assuming a column-major memory layout for the array while they are applied in p..under a row-major memory layout.
Relationship: entailment
Domain: Hardware
Sentence 1: Although the graphical approach based on structural controllability theory offers a general tool for directed networks, the approach fails if the assumption of independence of free link parameters and non-symmetry of the structural matrices is violated [10].
Sentence 2: the graphical approach can not be applied to any arbitrary complex network with structure and con.gurations of the link weights where the parameters (-i.e., the elements of the systems matrices) are not independently varying.
Relationship: entailment
Domain: Hardware
Sentence 1: While it is perhaps not necessary to reach the limits of the operating range, it is important to reproduce the conditions that can be found in a real deployment during the hottest and coldest times of the year.
Sentence 2: the testbed should be able to reach values up to 70-75.C, as experiences from outdoor deployments have shown that the on-board temperature of sensor nodes that are exposed to direct sunlight or are embedded into transparent packaging can reach extremely high values [7], [8], [9], [18].
Relationship: entailment
Domain: Hardware
Sentence 1: Under the condition xi > 0, i =1,...,N,we .nd that (17) can be rewritten as N L yi xi-1=0.
Sentence 2: (18) xi i=1 If the ratios yi , i=1,...,N, are decreasing in i, then by virtue of xi (18) there must exist some kwith 1=k<N such that yi -1=0,i=1,...,k xi and yi -1=0,i =k+1,...,N. xi xi = yi for i =1,...,k and yi = xi for i = k +1,...,N. We now readily obtain the comparison x .
Relationship: entailment
Domain: Hardware
Sentence 1: This paper illustrates a number of techniques, all based in the bio-inspired camp, that provide varying degrees of dependability over and above standard designs.
Sentence 2: three different techniques are considered: using FPGAs and continuous evolution to circumvent faults as and when they occur, using FPGAs and ideas from developmental biology to create designs that possess emergent fault tolerant properties, and finally we consider a novel ASIC, designed and built with bio-inspired systems in-mind, and show how this too can cope with unexpected events during operation.
Relationship: entailment
Domain: Hardware
Sentence 1: This is be­cause, after inserting the .rst link link a, the values of ru and Ru,u used in equation 2 will change for every sink, re­sulting in changed the values of the a and ß for all possible links.
Sentence 2: hence, the new values of a for link d might be lower than that of link c as a result of which it might be better to choose link d. even though link c is better than link d for the initial clock tree, link d might be­come better after the insertion of the .rst link.
Relationship: entailment
Domain: Hardware
Sentence 1: xi are the optimization variables obey­ing the implicit positive constraint, i.e., xi > 0.
Sentence 2: a standard form GP must satisfy the following con­ditions: the objective must be posynomial (and it must be minimized), the equality constraints can only have the form of a monomial equal to 1, and the inequality constraints can only have the form of a posynomial less than or equal to 1.
Relationship: entailment
Domain: Hardware
Sentence 1: Then, the CLR = 15ps -7ps = 8ps.
Sentence 2: obviously, CLR is different from nominal clock skew because clock skew on 1V is 15ps -12ps = 3ps while clock skew on 1.1V is 2ps.a solution that may have larger clock skew under conven­tional skew de.nition but with smaller CLR is still favorable.
Relationship: entailment
Domain: Hardware
Sentence 1: The mapping between the coordinates and the blocks is en­sured by variable MMap for the storage blocks, and variable PMap for the processor cores.
Sentence 2:  MMapx,y,z,m : indicates whether coordinate (x,y,z) is assigned to storage block m.  PMapx,y,z,p : indicates whether coordinate (x,y,z) is as­ signed to processor core p. The distances between a processor core and a storage i=1 j=1 Storage blocks should be mapped to the chip based on the co­ordinate and dimensions of the corresponding storage block.
Relationship: entailment
Domain: Hardware
Sentence 1: Then, the genetic algorithm (GA) is applied to each F-Table in order to put 'don't cares' (*~s) in appropri- ate places using the T-Tables.
Sentence 2: the F-Table evolves into the E-Table (i.e., the Evolved-Table) by adapting itself to the training case records of the T- Tables (Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: the two current sensor measurements) from the 1K Trojan-free chip instances to train our classi.er.
Sentence 2: we are solving a 1-class classi.cation problem, where our objective is to train a classi­.er to enclose the region of acceptable (trusted) functionality without any data of unacceptable (untrusted) functionality.
Relationship: entailment
Domain: Hardware
Sentence 1: It should be noted that the artifacts only model the aspects of the fabric that are essential to partial recon.guration.
Sentence 2: the con.guration bitstreams are replaced by simulation-only bitstreams, possible con.guration ports are represented by an ICAP artifact, and the part of con.gu­ration memory to which each recon.gurable region (RR) is mapped is substituted by an Extended Portal.
Relationship: entailment
Domain: Hardware
Sentence 1: As a concrete ex­ample, consider the ideal mixing operation mmm zt) =xt)yt) h (5)mmmm where xt) =cos 2 f1t)and yt) =cos 2 f2t), with f1 =1GHz and f2 =f1 q10kHz.
Sentence 2: the two tones f1 and f2 are very closely spaced, with the difference tone f1 qf2 =10kHz being much smaller.
Relationship: entailment
Domain: Hardware
Sentence 1: We have found that the ideal formal means for representing the trade-off inherent in probabilistic power­performance optimization is the probabilistic power-delay Pareto set, or just probabilistic Pareto set (PPS).
Sentence 2: the PPS are the solutions to the power-performance optimization problems under uncertainty that have the general form such as: min Q a() P st.. Pr{ D < Do} = ß This problem minimizes the value of the power at a high quantile (a) of the power distribution subject to a probabilistically defined timing constraint which is to be met with the probability (confidence level) of ß.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that for PCM designs, the number of physical segments is usually larger than the number of virtual segments, so that there are always some free physical segments in free segment list unless too many physical segments are worn out.
Sentence 2: if there are too many free physical segments whose remaining write counts are no more than the discarding threshold Td, the PCM device should be considered a worn-out device and should be replaced.
Relationship: entailment
Domain: Hardware
Sentence 1: SMT processors have the advan­tage of dynamically trading o. instruction-level parallelism (ILP) for thread-level parallelism (TLP).
Sentence 2: hardware resources that are partially unoccupied due to insu.cient single-thread ILP (for example due to long-latency opera­tions, control and data dependences, etc.)
Relationship: entailment
Domain: Hardware
Sentence 1: Moreover, in our proposed method, we require that the mutual in­ductance values between neighboring wires remain the same.
Sentence 2: we require the multi-band entries of L to match those of L. The solution that we describe relies on the elegant structure of the inverse of block-tridiagonal matrices which provides a compact parametrization for matrices with block-tridiagonal inverses.
Relationship: entailment
Domain: Hardware
Sentence 1: As well as being ultimately scalable to gate lengths in the order of 10nm, and offering low power consumption [23], double gate devices exhibit a number of characteristics that make them well suited to reconfigurable architectures.
Sentence 2: they can theoretically be built on top of other structures in three-dimensional layouts and they do not require additional structures such as body contacts and well structures that enlarge traditional CMOS layouts.
Relationship: entailment
Domain: Hardware
Sentence 1: It is assumed (or hoped) that, if a non-visual interface is successful in enabling information manipulation, exploration and provides access to functionality in ways which are coherent in the above senses, then effective collaboration can emerge as a natural benefit.
Sentence 2: if the same relationships between manipulable interface elements are available to both sighted and blind users, then there are no barriers to effective collaboration at least not on interface design grounds.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.1 Multipumping Implementations Since multipumped memories multiplex ports over time, the or­der of read/write operations must be carefully managed: violating the precedence of reads and writes would break the external ap­pearance of them occurring at the same time.
Sentence 2: writes must be performed at the end to avoid Write-After-Read (WAR) violations where an earlier internal write updates a value before it has been read by a subsequent internal read.
Relationship: entailment
Domain: Hardware
Sentence 1: Canonical loadings measure the contribution of the origi­nal variables in the canonical components by computing the correlation between gesture parameters X (or audio descrip­tors Y) and its corresponding canonical components XA (or YB).
Sentence 2: we compute the gesture parame­ter loadings lx i,h =(corr(xi, uh)) for 1 = i = m1, 1 = h = N (and similarly ly for audio descriptors).
Relationship: entailment
Domain: Hardware
Sentence 1: Unfortunately, not properly accounting for leakage power at RTL or above might result in highly subop­timal designs from a power perspective, since decisions taken in the early design stages play a signi.cant role in determining .­nal performance and power .gures.
Sentence 2: it cannot be ne­glected that leakage and dynamic power reduction are sometimes con.icting requirements.
Relationship: entailment
Domain: Hardware
Sentence 1: Next, we eliminate those outputs that are 0 (1) with probability P> |0.5- d| for speci.ed d. Finally, we eliminate outputs that can be predicted by other outputs with certainty greater than a speci.ed threshold (Section VIII).
Sentence 2: we transmit a maximal independent set of outputs that are not often 0 (1).
Relationship: entailment
Domain: Hardware
Sentence 1: For example, as depicted in Table 4, faults F1 and F2 cause the response 111, so either fault F1 or F2 should be made unlikely in order to diagnose the cause of the erro­neous response.
Sentence 2: if a circuit generates the failure response 111, the failure can be diagnoed accurately if either either F1 or F2 are made improbable.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that Phase 1 used a word­level arrival times of input addends during the CSA-tree allocation.
Sentence 2: if there is an n-bit addend X = (xn-1, xn-2 ···x0), Phase 1 uses max{D(xn-1), D(xn-2) ··· D(x0)}as the value of D(X).
Relationship: entailment
Domain: Hardware
Sentence 1: Note that some implementa­tions of simple gates were evolved at the transistor level [5, 8, 19]; however, as mentioned above, the evolutionary design of more complicated digital circuits directly at the transistor level is currently outside the capabilities of commonly avail­able computers.
Sentence 2: langeheine [8] argues that the evolutionary design of the XOR gate is di.cult.
Relationship: entailment
Domain: Hardware
Sentence 1: This choice not only reflects the balancing criteria that the overall runtime should be optimized for a given quality level, but also the fact that the choice of a faster, but less efficient, placement algorithm may increase the runtimes of the router, as it must accommodate a more difficult placement.
Sentence 2: tradeoffs made in placement or routing individually may not necessarily translate into corresponding tradeoffs overall.
Relationship: entailment
Domain: Hardware
Sentence 1: 1) Device characteristics: A MOBILE switches to the monos-ai table or bistable mode of operation depending upon its bias voltage, VCLK , which oscillates between 0V and VDD [9].
Sentence 2: monostable if VCLK < 2VP VOUT =metastable if VCLK 2VP (3) bistable if VCLK > 2VP , where VOU T and VP are the MOBILE output voltage and the RTD peak voltage, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: Out-of-Order -checks for all possible out-of-order execu­tions of commands from the same CP.
Sentence 2: a com­mand that was sent from source si after a command that was sent from source sj in the same CP is responded  Model # Tasks Sim Overhead [sec] Ratio Name (Legal) Simple Auxiliary Commands 256 206 4 51.5 Command­ 240 225 9 25 Response (112) (50) (5.6) Out-of­ 576 711 21 33.9 Order (192) (125) (6) Table 2.
Relationship: entailment
Domain: Hardware
Sentence 1: 0.1 [4] Patwari, N., and Wilson, J. Spatial models for human motion-induced signal strength variance on static 0 links.
Sentence 2: iEEE Transactions on Information Forensics  Figure 9: Confusion matrix when two receive devices are utilised we have considered feature samples from two individuals only and the study was conducted only on a single day.
Relationship: entailment
Domain: Hardware
Sentence 1: Definition 3: (VOT Inverter) A Variable-Output-Threshold (VOT) inverter is the combination of a normal CMOS inverter and a ST inverter, with the function depending on the value of a control signal, say Z.
Sentence 2: a VOT inverter operates in two different modes (1) normal mode, and (2) Schmitt-Trigger (ST) mode.
Relationship: entailment
Domain: Hardware
Sentence 1: In addressing this problem, we note that simply allocating an application s thread data to the closest MC may not be op­timal since it does not take into account queuing delays, row-bu.er con.icts, etc.
Sentence 2: we focus on place­ment strategies which incorporate: (i) the communication distance and latency between the core and the MC, (ii) queu­ing delay at the MC, and (iii) DRAM access latency which is heavily in.uenced by row-bu.er hit rates.
Relationship: entailment
Domain: Hardware
Sentence 1: Attracted by the promise of CGRAs, more than a dozen CGRAs including XPP [2], PADDI [4], PipeRench [9], KressArray [13], Morphosys [18], MATRIX [20], and REMARC [21] were proposed over the past decade.
Sentence 2: the ADRES CGRA has been shown to achieve power ef.ciency of 60 GOps/W in 32 nm CMOS technology [3].
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we observe that exploiting the mathematical property of idempotence in programs allows the bene.ts of both speculative execution and precise state to be achieved with minimal power or complexity overhead in the hardware.
Sentence 2: we show how programs can be constructed in a special way, such that execution is always restartable over some interval of instructions, regardless of the order in which those instructions issue or retire.
Relationship: entailment
Domain: Hardware
Sentence 1: Brej and Garside at­tempted to solve the problem of preemption [1, 2], but their approach had signi.cant drawbacks.
Sentence 2: their approach did not ap­propriately address a metastability issue: the handshake control in a pipeline stage can become metastable if the stage receives a data token and an anti-token nearly simultaneously.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition, take any finite or infinite run in which all participating processes terminate, and reorder the output sets $1,6:2, ... by set inclusion to get R1, R2, ....
Sentence 2: it is required that for every such sequence R, [Rll <_ k and for all i, [Ri+II-IR/I _< k. no snapshot contains more than k "new" ele- ments.
Relationship: entailment
Domain: Hardware
Sentence 1: Insertion of LUTs for synchronization of computations These circuit architectures, which we call memory-based computing in this paper, are intended to process data stream coming from the storage areas, and so they should be located close to the storage areas with lots of ports or connections.
Sentence 2: the data transfer bandwidth between memory-based computing units and data storages should not be bottlenecks.
Relationship: entailment
Domain: Hardware
Sentence 1: For each non-biased branch captured in A, the function hashes the branch address, the address of the non­biased branch and its distance in the history recorded in P to select a row and uses its depth in A to map to a column in Wm.
Sentence 2: for every non-biased branch of every path, the predictor tracks the correlation of that branch in conjunction with its recorded distance in the history.
Relationship: entailment
Domain: Hardware
Sentence 1: 2 Yield Limitations The continuous advancements in semiconductor process technology are not without limitations.
Sentence 2: these large embedded memories in combination with the process Permission to make digital or hard copies of part or all of this work or personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: entailment
Domain: Hardware
Sentence 1: Therefore, rather than modeling the access cost of each block request individually, we model the access cost of each sub-sequence B k,l =(bk,...,bl ) (k < l), which is taken from the application launch sequence B, such that (pk,..., pl )=(0,1,...,1,0).
Sentence 2: the requests bk and bl are met by the HDD, while bk+1,...,bl-1 come from the .ash memory.
Relationship: entailment
Domain: Hardware
Sentence 1: The predictor keeps track of the tendency of a given branch in a given position in the history to agree with the outcome of B.
Sentence 2: for ev­ery component of every path, the predictor tracks the corre­lation of that component with the outcome of B.Tomake a prediction, the correlations of each component of the cur­rent path are aggregated to form a prediction.
Relationship: entailment
Domain: Hardware
Sentence 1: If the latency L of the initial schedule is greater than the desired latency (bound) Ld, then we iteratively reduce L by allocating a new resource (typically a less reliable one) to a node until we reach to Ld.
Sentence 2: we pick the slowest node on the critical path (Note that selecting a node which is not on the critical path will not help us reduce the initial latency value), and use a faster but potentially less reliable version for it.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition to that, if we have an even faster memory (called Level 3), the element U[i][k]can be transferred to this memory (just before the lloop) and can be used from there throughout the execution of the l loop.
Sentence 2: at a given time, one row of array Ucan be in Level 2 SPM and one element from this row can be in Level 1 SPM (the fastest level).
Relationship: entailment
Domain: Hardware
Sentence 1: As long as a physical SCORE compute page is larger than one of our placement engine processing elements (~400 LUTs as described in the previous section), a SCORE device is capable of performing inter-page placement on itself.
Sentence 2: we can directly configure the physical SCORE device to be a placement engine that is exactly large enough to place the set of pages that can run on the physical device in a single SCORE timeslice.
Relationship: entailment
Domain: Hardware
Sentence 1: One key .nding of our study is that contrasting to what one would hope, the recent, best-in-class academic placers, with the exception of FastPlace, are not signi.cantly faster than VPR.
Sentence 2: when the number of clusters in the netlist is less than 50K, VPR can outperform Capo both in terms of runtime and QoR 4 .
Relationship: entailment
Domain: Hardware
Sentence 1: WIRELESS INTERCONNECT ANALYSIS The electromagnetic radiation e.ects of the wireless in­terconnect system on a die are investigated using an FEM­based full-wave simulation analysis.
Sentence 2: the wire­less interconnect system is analyzed for the coupling of the transmitting and receiving antennas as well as the (unde­sirable) coupling between the transmitting antenna and the wire interconnects.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.2 Representing and Manipulating the Coars­est Base It is easy to extend the representation for the coarsest decompositions to a representation for the coarsest base: it is su.cient to apply the aforementioned transformations modulo equivalence classes.
Sentence 2: wheneverweneedto update the coarsest decomposition for a slice p,we recur­sively update the representants of the slices linked by the .eld p->cb.
Relationship: entailment
Domain: Hardware
Sentence 1: A PCPG device, which is implemented with many parallel transistors and on/off signal buffers, is similar to the largest component (i.e., the pass device between VI and VO) of a typical LDO VR, as illustrated in Figure 2.
Sentence 2: an LDO VR can be implemented by augmenting a PCPG device with feedback control circuitry comprised of an error amplifier, an analog-to-digital converter, and a reference voltage generator.
Relationship: entailment
Domain: Hardware
Sentence 1: Smaller tiles result in greater power saving as more sig­nals are pipelined.
Sentence 2: when leakage power is signi.cant (.F= 0.1%), pipelining through repeater optimization and voltage scaling is more effective at reducing the inter-tile wire power, since pipelining is more effective at saving leakage power (Section 3.3).
Relationship: entailment