sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: The node voltages are treated as deterministic variables in the range of supply voltages with some margin added to account for the overshoot and undershoot.
Sentence 2: the total current through the capacitances (at the output) at any instant of a transient simulation is equal to the DC current for the corresponding instantaneous voltages i.e, Idc(Vi(t),Vo(t)) = Iload(t)+ Iparasitic(t) (1) where Idc(Vi(t),Vo(t)) is the DC output current at instanta­neous input voltage (Vi(t)) and output voltage (Vo(t)) at time t. Iload(t) is the current through the output load capacitor, and Iparasitic(t) is the current through the parasitic capacitances, at time t. For a large load capacitance, Iload is much larger than Iprasitic because the current is divided in the ratio of the capacitances.
Relationship: neutral
Domain: Hardware
Sentence 1: Charge accumulation is performed via a voltage to frequency converter circuit, sim- Sender and Receiver CPU at 208 MHz 450 400 350 300 250 200 150 100 50 0Time (sec) Sender and Receiver CPU at 208 MHz Power (mW) Power (mW) 60 50 40 30 20 10 0 Time (sec) Figure 9.
Sentence 2: nAND reads are more expensive, power-wise than NOR reads: in fact, NOR reads don t cause any discernable dif­ference above NOR s idle power dissipation.
Relationship: neutral
Domain: Hardware
Sentence 1: BACKGROUND 2.1 TFT Mobility Change under Bending There are three popular types of TFT technologies: amorphous silicon (a-Si) TFT, polysilicon (poly-Si) TFT, and organic TFT (OTFT).
Sentence 2: inward bending results in compressive strain while outward bending results in tensile strain.
Relationship: neutral
Domain: Hardware
Sentence 1: MLP-Aware Replacement using an Existing Cost-Sensitive Replacement Policy We proposed the SBAR mechanism to implement a MLP­aware cache replacement policy.
Sentence 2: comparison of LRU, LIN, and SBAR for the ammp benchmark in terms of: (a) the average cost of misses, (b) the number of misses per 1000 instructions, and (c) IPC.
Relationship: neutral
Domain: Hardware
Sentence 1: The reset wire is shared by all data wires to specify the start of the data transmission (before the transmission of a cache block); the number of clock cycles between the reset signal and a bit-.ip on a data  Figure 3: Illustrative example of three communi­cation techniques: (a) parallel, (b) serial, and (c) DESC.
Sentence 2: every data chunk contains at most one bit from each data segment; similarly, each parity chunk contains one parity bit from each segment.
Relationship: neutral
Domain: Hardware
Sentence 1: This is because these benchmarks show small percentages of cache lines .tting 32B but most cache lines are compressed well; the 32B L2 cache lines can capture larger than 32B uncom­pressed data, which increases the probability of a particular word to hit in the L2 cache.
Sentence 2: these compressed 32B cache lines can be exploited to design a smaller L2 cache than the conventional L2 cache without noticeable performance hit in three ways.
Relationship: neutral
Domain: Hardware
Sentence 1: Previously reported high-accuracy thermal sensor designs either benefit from analog-friendly, large-feature size manufacturing processes [3],[4] or from MEMS techniques [5] which have yet to be integrated in high scale to a high volume digital CMOS processes.
Sentence 2: this imposes certain limits on how far the sensing structures can be placed with respect to the thermal sensor core in order to ensure the voltage drop is within acceptable levels.
Relationship: neutral
Domain: Hardware
Sentence 1: This means that the packet rate is constant until the throughput reaches its maximum.
Sentence 2: reducing the number of the Table 3: Specs of machines for the performance eval­uation Router CPU Intel(R) Core(TM) i7 M620 (2.67GHz, dual core) Memory 8GiB, DDR3 (1333MT/s) NIC Adapter Intel(R) 82577LM (1 port) register access will improves the forwarding throughput.
Relationship: neutral
Domain: Hardware
Sentence 1: LISA core Bus interface SystemC Phase bus Instruction Accurate (IA) model LISA2TLM CycleAccurate Functional API API Transfer  Transaction RTL pins API + Debug API about manually developing and re.ning TLM and RTL SoC modules in combination with their intercommunication [7, 8].
Sentence 2: this estimation is already relatively good and ob­tained almost for free , without modifying the instruction ac­curate processor model developed in section 4.1.
Relationship: neutral
Domain: Hardware
Sentence 1: Cheng and Lin extended van Ginneken s algorithm to allow b buffer types in time For modern design libraries that contain hun­dreds of buffers, it is a serious challenge to balance the speed and performance of the buffer insertion algorithm.
Sentence 2: considerany three can­didates a,  in such that < < For any buffer type B, if then 2 Proof: From the definition of convex pruning, we have If then  Lemma 4 implies that for any buffer type if candidate a maximizes among its previous and next consecu­tive candidates in then a maximizes among all candidates in Function identifies  from and generates new candidates = 1,.. .
Relationship: neutral
Domain: Hardware
Sentence 1: On subsequent accesses to a private block, the processor will .nd it in its L1 cache (in case of no eviction), so no additional directory access will be done.
Sentence 2: we simulate a 16-tile CMP with 2-cycle, 64KB, 4-way L1 instruction and data caches, and a shared (NUCA) LLC cache with 512KB and 8-way per tile.
Relationship: neutral
Domain: Hardware
Sentence 1: By the de.nition, an ESD connected component (ECC) of a constrained graph contains only np-vertices, and for each np­vertex in the ECC, there is always a path leading to every other  Non-pad vertex Pad vertex Non-constrained edge Constrained edge Figure 5: The constrained graph constructed from the netlist in Figure 1, using the construction methods pre­sented in Section 3.2.1. np-vertices in the ECC by nc-edges.
Sentence 2: the p-vertex, A, detects no ESD connected component, since all the np-vertices have been visited.
Relationship: neutral
Domain: Hardware
Sentence 1: The experimental results show that our algorithm reduces worst-case skew by up to 5X compared to the existing zero-skew based approach ZST/DME [2, 3] with small (up to 1%) wirelength overhead.
Sentence 2: using this time-variant thermal power as input, the transient-temperature T (ti,nj) over the chip is calculated at di.erent time-instant ti for each node nj in the grid.
Relationship: neutral
Domain: Hardware
Sentence 1: We can also observe from the figure that decreasing the size of subblocks, increases the area overhead of the FDM.
Sentence 2: our investigation indicated that while in these benchmarks the miss rate increased slightly due to cache effective size L1-L2 Performance degradation due to sacrifice line/blocks L1-L2 Performance degradation due to extra cycle Figure 11.Performance degradation of applying FFT-Cache for (a) L1 (b) L2 and (c) L1 and L2 at the same time.
Relationship: neutral
Domain: Hardware
Sentence 1: Ar­biters at each router in a packet s path are not aligned, and a packet may incur the worst-case delay at every hop.
Sentence 2: 2.2 Notion of Time TDM (and FDM) (virtual)-circuit switching treat the en­tire NOC as a single shared resource with a single arbiter.packets wait only at the ingress network inter­faces (NI) until their TDM slot, after which they progress without contention to the egress NIs, with minimal latency.
Relationship: neutral
Domain: Hardware
Sentence 1: Figure 3: The case that the DRAM bandwidth is the bottleneck  4.1 Selective caching Selective caching is a technique that a programmer explic­itly speci.es thedata withlocality of reference so as to selec­tively cache them.
Sentence 2: furthermore the number of memory accesses is reduced and the .op/total byte ratio is increased.
Relationship: neutral
Domain: Hardware
Sentence 1: [3] Y. Cai, B. Liu, J. Shi, Q. Zhou, X. Hong, Power Delivery Aware Floorplanning for Voltage Island Designs, in Proc.
Sentence 2: the given .oorplan con­tains .ve circuit blocks operating at two speci.c supply voltages, three blocks in the left voltage island and two in the right one, and the wires interconnecting the blocks are shown.
Relationship: neutral
Domain: Hardware
Sentence 1: Manufacturing variability further reduces the available noise margin, which may eventually lead to failure of decoding logic values.
Sentence 2: 5, Case(a),(b),(c),(d) represent the following cases: a) V1= VDD, V2= VDD, Vout=0.1VDD, b) V1= VDD, V2=Gnd, Vout =0.9VDD, c) V1= Gnd, V2= VDD, Vout=0.9VDD, d) V1= Gnd, V2= Gnd, Vout =0.9VDD.
Relationship: neutral
Domain: Hardware
Sentence 1: Experimental results on several testcases indicate that our methods achieve 10%-31%(20% on average) clock divergence reduction and between 16-64ps skew reduction (1.6%-6.4% of cycle time for a 1GHz clock) with less than 0.5% increase in bu.er area/wirelength compared to ex­isting CTS algorithms.
Sentence 2: their delays across other corners will be di.erent, mainly because of the di.erence in the intercon­nect lengths and bu.er sizes.
Relationship: neutral
Domain: Hardware
Sentence 1: The proposed 3-input non-volatile AND gate, (a) type 1, (b) type 2. this scheme, the TE of MTJA is pulled to ground when the writing mode is .nished (MP11 is turned on by the low WE).
Sentence 2: when the resistance in the positive branch is higher than that in the negative branch, the output Y is 1 ; when the resistance in the negative branch is higher, the output Y is 1 .
Relationship: neutral
Domain: Hardware
Sentence 1: Gate AND OR XOR Input MTJs 2 2 2 Reference MTJs 2 2 4 Write energy 285fJ/bit 285fJ/bit 285fJ/bit Read energy 4.35fJ 4.35fJ 8.72fJ Read speed 160ps 160ps 320ps TABLE V. COMPARISON BETWEEN THE PROPOSED 2-INPUT NON-VO LATILE AND AND THE CONVENTIONAL CMOS 2-INPUT AND GATE .
Sentence 2: they are partially non-volatile and will lose information when they are powered off.
Relationship: neutral
Domain: Hardware
Sentence 1: Variation Vector Equation (5) can be rewritten in a compacted vector format as X r + ß * X ~L(µX , aX , ßX )= µX + a * X g (6) where * means transpose and r = [R1, ··· ,RN ]* ~N(0, I) g = [G1, ··· ,GM ]* ~N(0, Sg) (7) are mutually independent local variation vector and global variation vector respectively.
Sentence 2: applying the generally accepted Gaussian assumption, we .rstly disclose that the MAX operation can be approximated by linear supposition of its inputs.
Relationship: neutral
Domain: Hardware
Sentence 1: Networks-on-Chip (NoCs) is a promising paradigm to handle the increasing on-chip communication complexity [2, 3] and reliability issues [4, 5, 6].
Sentence 2: system Requirements The proposed simulator has been successfully tested on Linux/i386 and i686 system with four processors and Linux cluster consisted of IBM cluster nodes (each with dual Intel Itanium two processors), GCC version 3.4.6 and java version 1.4.2 are required to compile the source codes (in standard C and MPI) and interface source codes (in Java), respectively.
Relationship: neutral
Domain: Hardware
Sentence 1: These statistics can then be used by an invocation of the AM algorithm to refine the accuracy assignments for use in the next simulation iteration.
Sentence 2: as shown in [12], this cost function leads to an optimal assignment for block i along a simple chain of  %/~- (2) to achieve a specified output delay tolerance e. Also derived in [12] are simplifications of (2) to obtain compact, single- calculation expressions.
Relationship: neutral
Domain: Hardware
Sentence 1: [46]D.SanchezandC.Kozyrakis.TheZCache:Decouplingways andassociativity.InMICRO,2010.
Sentence 2: first,notremovingacacheblockaddressfromtheEAFensuresthat theEAFbecomesfullevenwhenathrashingworkingsetfitsinto thecacheandtheEAFtogether.Second,oncetheEAFbecomes full,itsgetscleared.Thesetwochangestogetherenabletheperi­odicclearingoftheEAF.Suchperiodicclearingresultsinonlya fractionoftheblocksofathrashingworkingsettogetpredicted ashigh-reuseblocks,retainingonlythatfractioninthecache.This improvesthecachehit-rateforsuchaworkingset,andtherebymit­igatesthrashing.
Relationship: neutral
Domain: Hardware
Sentence 1: It results in an interconnected com­pact block representation, where the sets of q-dominant poles for compact blocks have minimum overlap between them.
Sentence 2: ckt  [2] HiPRIME BSMOR TBS build sim build sim build sim build sim  ckt1 0.44s 0.08s 0.15s 1.02s 0.12s 0.08s 0.09s 0.08s ckt2 2.19s 1.24s 0.54s 1min:42s 0.63s 1.18s 0.11s 1.02s ckt3 1min:17s 1min:51s 5.76s 2hr:48min:20s 1min:2s 1min:38s 1.62s 1min:32s ckt4 34min:58s 21min:32s 47.3s > 2day 4min:54s 11min:42s 20.7s 11min:23s ckt5 4hr:43min:18s 1day:5hr:11min 2min:42s > 2day 1hr:45min 1day:1hr:36min 2min:8s 1day:18min ckt6 NA NA NA NA NA NA 6min:16s 1day:1hr:29min     Table 2: Comparison of runtime under the similar accuracy of the method in [2], HiPRIME, BSMOR and TBS.
Relationship: neutral
Domain: Hardware
Sentence 1: M92/41(May 1992), Department of Electrical Engineering and Computer Science, University of California, Berkely, CA, USA [24] Spars, J., Furber, S., Principles of Asynchronous Circuit De­sign -A Systems Perspective Kluwer Academic Publishers, Hardcover ISBN 0-7923-7613-7, 2001 [25] Theodoropoulos G., Woods, J. V., Occam: An Asyn­chronous Hardware Description Language?
Sentence 2: the last decade has witnessed an explosion of in­terest in asynchronous design techniques, which do not rely on global clocks but achieve synchronization by means of localized synchronization protocols between the commu­nicating subsystems.
Relationship: neutral
Domain: Hardware
Sentence 1: We test several baud rate combinations to determine the limits of our current combination of iPhone 3G and the Texas Instruments MSP430F1611.
Sentence 2: given the typical battery size of 1200 to 1400 mAh found on several generations of iPhones, and at a nominal 3.7 V, we estimate a battery life of 10 to 11 hours of continuous opera­tion if the screen is turned off.
Relationship: neutral
Domain: Hardware
Sentence 1: Exploiting Narrow-Width Values for Improving Non-Volatile Cache Lifetime Guangshan Duan and Shuai Wang State Key Laboratory of Novel Software Technology Department of Computer Science and Technology Nanjing University, Nanjing, Jiang Su, China Email: guangshan duan@smail.nju.edu.cn, swang@nju.edu.cn  Abstract Due to the high cell density, low leakage power consumption, and less vulnerability to soft errors, non-volatile memory technologies are among the most promising alternatives for replacing the traditional DRAM and SRAM technologies used in implementing main memory and caches in the modern microprocessor.
Sentence 2: the experimental results show that our proposed schemes can improve the lifetime of the non­volatile caches by 245% on average.
Relationship: neutral
Domain: Hardware
Sentence 1: All pre­vious recon.guration algorithms, either off-chip [31, 45, 46] or on­chip [1, 8, 17, 41], are limited to the granularity of a bidirectional link, if not any coarser.
Sentence 2: as can be noted from the .g­ure, uDIREC consistently leads to more than 3× completely con­nected networks between 25 and 50 faults, when compared to Ari­adne, beyond which the probability of still having a completely connected network is near-zero.
Relationship: neutral
Domain: Hardware
Sentence 1: The first presentation of this special session, titled Memcomputing: a brain-inspired computing paradigm and given by Prof. Pershin from University of South Carolina, focuses on a memcomputing paradigm that employs two-terminal electronic devices with memory (memelements), namely, memristive, memcapacitive or meminductive systems [1], to store and process information at the same physical location.
Sentence 2: of Design, Automation &#38; Test in Europe, 2014.
Relationship: neutral
Domain: Hardware
Sentence 1: In suchcase, the coloring ofthe neighborhoodfea­tures need to be reconsidered to avoid unnecessary stitches likeFig.3(d)and enable optimal solutioninFig.3(e) or(f).
Sentence 2: 8(b) showsthenormalCGP cases, where aPCGPis colored identically and unconnected.
Relationship: neutral
Domain: Hardware
Sentence 1: We recommend that you print the file for best legibility.
Sentence 2: anetworkwithareaAundertheThompsonmodelcanbe laidoutwithareanolargerthanAunderthemultilayer 2-DgridmodelwithL=2layers,sotheformercanbe viewedasaspecialcaseofthelatter.Note,however,that wemayderivelayoutsunderthetwo-layer2-Dgridmodel withareasmallerthantheThompsonmodel.Inthemulti­layer3-Dgridmodel,thenodesofthegraphareembedded inLAlayersofthe3-Dgrid.TheseLAlayersarecalled activelayers"anddonotneedtobeconsecutivelayers.
Relationship: neutral
Domain: Hardware
Sentence 1: [5]Adiseno, M. Ismail and H. Olsson, A Wide-Band RF Front-End for Multiband Multistandard High-Linearity Low-IF Wireless Receivers, IEEE JSSC, SC-37(9), Sept. 2002, pp.
Sentence 2: there is a trade-off between the gain, input matching, power and noise figure.
Relationship: neutral
Domain: Hardware
Sentence 1: The architecture model is given in fig.3, it has been implemented on a FPGA Vir- tex 800 with the free soft IP LEON [11] which communicates with HW modules (for instance a DCT accelerator) through the arnba bus.
Sentence 2: a task can be scheduled if the response time RT/of ~ is such as : VTj E hp(i), 3R~ < Di with RT/ *C where hp(i) is the set of SW tasks whith a higher priority than task i.
Relationship: neutral
Domain: Hardware
Sentence 1: INTRODUCTION  Traditionally, the processing elements in networks are either ASICs or variations of general-purpose processors.
Sentence 2: the module is selected to perform one of the following functions on their input signals: - output = left input (shift right) - output = right input (pass without shift) - output = (left input AND right input) - output = (left input OR right input) - output = (left input XNOR right input) - output = (left input BYTE-WISE-OR right input) - output = (left input BYTE-WISE-AND right input)  The utility of each these operations will be examined during the discussion of the applications in the following subsections.
Relationship: neutral
Domain: Hardware
Sentence 1: Biased-LGat e Selection The key question in our methodology is the value of LGat e for each transistor in the cells.
Sentence 2: in a resizing setup (described below) with a delay constraint, the leakage bene.t over the whole design can decrease as the number of instances which can be replaced by their biased version (slower but less leaky) is reduced.
Relationship: neutral
Domain: Hardware
Sentence 1: This paper introduces a novel placement .ow with clock-tree aware .ip-.op merging and MBFF generation, and proposes the corresponding algorithms to simultaneously mini­mize .ip-.op power and clock latency when applying MBFFs during placement.
Sentence 2: experimental results based on the IWLS­2005 benchmark show that our approach is very effective in not only .ip-.op power but also clock latency minimization without degrading circuit performance.
Relationship: neutral
Domain: Hardware
Sentence 1: If A(XIl+xl)is the original reference and A0(X0Il+xl0)is 0 the transformed reference, we have X0=MAXand xl= MAxl+mlA.
Sentence 2: if the base addresses of ar­rays Aand Bhappen to map on the same cache line, a miss rate of 100% is possible due to the data cache con.icts be­tween these two array references (i.e., inter-array con.icts).
Relationship: neutral
Domain: Hardware
Sentence 1: 4.3 Impact of Utilization on Performance A prior study [20] of a particular two-level architecture found that as utilization is increased, performance declines.
Sentence 2: this routing network primarily receives input from a dedicated global signal (e.g., clock) distribution network, but also receives input from a few of the ordinary external signals and muxes used to drive the LUT inputs.
Relationship: neutral
Domain: Hardware
Sentence 1: 1.2-v supply, 100-nw, 1.09-v bandgap and 0.7-v supply, 52.5-nw, 0.55-v subbandgap reference circuits for nanowatt cmos lsis.
Sentence 2: if a voltage propor­tional to ft is attached to the source terminal of M2, with the right proportionality factor F (if2) adjusted (using the current mirror aspect relation K1), the equality of (5) can be satis.ed.
Relationship: neutral
Domain: Hardware
Sentence 1: The Output Buffer which operates in high speed region is needed for the test, because PLL output clock operates in GHz region.
Sentence 2: high-Speed point-to-point links are used for application, Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: neutral
Domain: Hardware
Sentence 1: Speci.cally, if the instruction hits in the cache, then it is directly passed to the processor with the signal C HIT; otherwise, this instruction needs to be fetched from the main memory.
Sentence 2: all these works focused on the SPM-only architecture, in which all the instructions or data that are not stored in the SPM have to be fetched from the main memory.
Relationship: neutral
Domain: Hardware
Sentence 1: The output from this modi.ed CACTI 6.0 indicates that the optimal organization em­ploys a bank size of 4MB for the .rst 16MB of the cache and a bank size of 8MB for the remaining 16MB.
Sentence 2: a few other extensions of CACTI can also be found in the literature, including multiple different versions of e-CACTI (enhanced CACTI).
Relationship: neutral
Domain: Hardware
Sentence 1: Grids in the first row Case d: Similar to case c, for the rest of the grids in the first column (where 1<i<m and j=1), the routes enter from the bottom of the grid, and leaves from either the top or the right hand side of the grid.
Sentence 2: the probabilistic usage matrix Definition 5: Assume the pins are located at the lower left and upper right corners of the bounding box, we define the probabilistic usage matrix P for a two-pin net that covers a m×n mesh as follows: (Pm () ()1 Pm1 )L Pm,n Pmn).
Relationship: neutral
Domain: Hardware
Sentence 1: The approximate algorithm considers the odd constants that are not included in the current ready and target sets and can be implemented with the elements of the current ready set as possible intermediate constants, as seen on the lines 7-10 of the algorithm.
Sentence 2: this experiment clearly indicates that the approximate algorithm that guarantees the mini­mum solution on more instances is indispensable to ensure the minimum solution of the MCM problem.
Relationship: neutral
Domain: Hardware
Sentence 1: Natalie deremijenko Center for Advanced Technology New York University 715 Broadway, # 1208 NY, NY 10003 USA +1 212 998 3382 nat@cat.nyu.edu EXISTING APPLICATIONS Sound transduction through bone conduction has been used for more than 50 years in subjects with certain types of hearing impairment.
Sentence 2: the structure was designed as to magnify the vibration in the plastic surface, leaving the transducer free to vibrate on the side where the rod was attached.
Relationship: neutral
Domain: Hardware
Sentence 1: In the baseline open-page address mapping scheme, the memory system can be denoted as r:l:b:n:k:z where the lower case letter is the binary log­arithm of the upper case letter.
Sentence 2: in this paper we present a new approach from the most inner ring, to enable programmable, high speed, continuous mon­itoring and response of system integrity of interest.
Relationship: neutral
Domain: Hardware
Sentence 1: Sub-array con.guration: As the smallest component in architec­ture construction, a sub-array in Figure 4(b) can signi.cantly affect the overall performance of the entire architecture.
Sentence 2: restricted by the theoretical limit of 9F 2, further shrink­ing memory cell size and hence improving performance and power consumption in STT-RAM is dif.cult [6].
Relationship: neutral