sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Observe from Figure 4(a) that since Hcub synthesizes target constants once at a time by including intermediate constants, the intermediate con­stants included for the implementation of target constants in the previous iterations of Hcub may not be shared in the implementation of the target constants in later iterations, although Hcub is particularly designed for this case.
Sentence 2: in each iteration of the approximate algorithm, an intermediate constant that can be implemented with the elements of the current ready set is added to the ready set.
Relationship: contrasting
Domain: Hardware
Sentence 1: According to the semiconductor industry as­sociation s economic forecast, the growth for DSP processors will continue to grow at an increasing rate [1].
Sentence 2: as Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: contrasting
Domain: Hardware
Sentence 1: 2s2 P(Xi = x | Zp > t ) =  i (34) v erfc v t 2psi 2sp The expected value is found from the integral: Z 8 E{Xi | Zp > t } = xP(Xi = x | Zp > t )dx (35) -8 Unfortunately, this is unsolvable analytically.
Sentence 2: by inspection of (34), it may be noted that the function P(Xi = x | Zp > t ) is approximately Gaussian in shape.
Relationship: contrasting
Domain: Hardware
Sentence 1: On the other hand, statistical timing analysis (STA) that characterizes timing delays as statistical random variables o.ers a better approach for more accurate andrealistic timing prediction.
Sentence 2: 2.1 Quadratic Timing Model to realize the full bene.t of STA, one must ad­dress a challenging issue that gate/wire delays in a circuit couldbe correlatedsince two delays might be a.ectedby the same parameter variation such as voltage supply uncer­tainties, gate channel length variations, wire geometry vari­ations,...,etc.
Relationship: contrasting
Domain: Hardware
Sentence 1: Ideally a smaller capacitance on LBLB node is required to reduce the glitch; therefore N > M is desirable for glitch reduction (Figure 12(b)).
Sentence 2: for the same total LBL capacitance (LBLA + LBLB), the best delay is obtained if a significant fraction of the total LBL capacitance is discharged by the early arrival of UWL before SFWL is turned ON.
Relationship: contrasting
Domain: Hardware
Sentence 1: Most large-scale P2P systems are asynchronous in nature, i.e., constant on-line presence is not assumed or required from peer nodes.
Sentence 2: one extreme of P2P systems covers more tradi­tional, synchronous group communication systems such as Spread [29], Totem [1] or Horus [25] where scalability is typically limited, membership awareness is total and group membership requires con­stant on-line presence of each peer.
Relationship: contrasting
Domain: Hardware
Sentence 1: As we see from the .gure, by sacri.cing a maximum of 3× in energy, one can achieve up-to40× improvementinperformance over theMEPpoint.
Sentence 2: designing NT circuits to meet a precise performance target is a very challenging goal, mainly because minimal varia­tions ofdevice thresholds maylead to massiveperformancedegra­dations, and traditional worst-casedesign would impose unaccept­able margins.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is made possible using real-time memory subsystems [6] [8] that bound the memory access time by .xing the memory access parameters at design-time and employing predictable arbitration, such as Time Division Multiplexing (TDM) and Round-Robin, using bus-based interconnects for resource sharing.
Sentence 2: statically scheduled TDM NoCs [9] [15] solve the scala­bility issues with the traditional bus-based approaches [16] for accessing shared resources in larger multi-processor platforms.
Relationship: contrasting
Domain: Hardware
Sentence 1: Comparison between the size of the input (P) and the utilization (%) suggests that our algorithm is scalable for memory bus and global bus utilizations while the PE utilization becomes poorer with a larger input size.
Sentence 2: considering that a typical DRAA has 8 * 8 PEs with 16 memory buses distributed over the PEs, MPEG kernel is a very large loop (127 PE-operations and 64 memory operations) and should be divided into several loops for ef.cient mapping anyway.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, Tinman, a gene related to heart devel­opment in most species, is highly speci.c.
Sentence 2: pax-6 (the gene supposedly controlling the development of sight across species) and the gene Dorsal use wildcards in their binding signatures, represented by K (G or T), Y (C or T), M (C or A), W, etc.
Relationship: contrasting
Domain: Hardware
Sentence 1: If I1 is a move but does not depend on I0,itisI1 s input register from the map table.
Sentence 2: these .rst two cases are identical to I0 s. there are also two other possiblities:  If I1 is a move and depends on I0 and I0 is not a move, then it is I0 s output register.
Relationship: contrasting
Domain: Hardware
Sentence 1: Yung-Chih Chen and Chun-Yao Wang Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan {ycchen, wcyao}@cs.nthu.edu.tw  these SAT-based approaches due to the expense of observability don t care computation and SAT solving calls.
Sentence 2: the ATPG-based approach [5] is much faster, although its capability is not as good as that of the SAT-based approaches for circuit minimization.
Relationship: contrasting
Domain: Hardware
Sentence 1: It is worth noticing in Fig.7 that the non-hardening scheme bene.ts signi.cantly from added hardware redundancy of 2 × 3 as well (due to the enlarged solution space of mapping), compared to the case of no hardware redundancy.
Sentence 2: when the crossbar area is increased, the non-hardening scheme cannot take full advantage of the extra rows / columns.
Relationship: contrasting
Domain: Hardware
Sentence 1: However, prior art did not investigate applica­tions of socket overloading, but focused on avoiding socket overload at the receiver and at reducing the processing la­tency of incoming packets, and the evaluations were with benign tra.c.
Sentence 2: in this work we study socket overloading as an attack technique and investigate its ap­plicability for di.erent purposes, e.g., as a side-channel for discovery of client-side ephemeral port.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since AES has a large number of nodes, it is intuitive to expect an increase in speedup by increasing the allowed number of AFUs and I/O constraints.
Sentence 2: it is interesting to note that con­trarily to our expectation, for a smaller number of allowed AFUs (= 1), the speedup could not scale with relaxing I/O constraints (as shown in the .rst plot of Figure 6).
Relationship: contrasting
Domain: Hardware
Sentence 1: However, during sleep mode, the Vddv can get close to Vss result­ing in p-n junction current in the header, which is a disadvantage in terms of sleep mode leakage.
Sentence 2: biasing the substrate of current switch to its source has an advantage in sleep mode leak­age; the n-well of the header needs to be isolated from that of logic gates, which is an area overhead.
Relationship: contrasting
Domain: Hardware
Sentence 1: 1.2 Metrics to score or represent congestion Visual inspection of congestion plots (a region-wise color-coded map marking out the hot spots with the greatest contention for wiring resources) often serves as a .rst order method to compare the routability of different design points.
Sentence 2: optimization tools and designers also require a single metric that can accurately score or represent the design congestion.
Relationship: contrasting
Domain: Hardware
Sentence 1: As SMS is effective in capturing regular and irregular access patterns, row buffer hit ratio increases to 30%.
Sentence 2: its row buffer hit ratio is limited as it targets only memory accesses that are critical to performance (i.e., load-related traffic), ignoring store-trig­gered memory reads and memory writes (store misses are hidden through store buffers whereas LLC writebacks are not on the critical path of the processor).
Relationship: contrasting
Domain: Hardware
Sentence 1: Consequently, according to Property 4, when we encounter a pair of tightly connected HAs (i.e., Case 1) we apply HA-merge to the HAs and produce a merged FA in a form like trans2 in Figure 5(a).
Sentence 2: if two HAs are not tightly connected as shown case2 org in Figure 5(b), we do not directly merge the two HAs 4Note that CSAi is the CSA created at the i-th iteration of the partial-greedy-CSA method.
Relationship: contrasting
Domain: Hardware
Sentence 1: Digital CMOS Logic Operation in the Sub-Threshold Region* Hendrawan Soeleman and Kaushik Roy Purdue University Department of Electrical and Computer Engineering West Lafayette, IN 47907, USA {soeleman, kaushik} ~ecn.purdue.edu ABSTRACT Numerous efforts in balancing the trade-off between power, area and performance have been carried out in the medium performance, medium power region of the design spectrum.
Sentence 2: not much study has been done at the two extreme ends of the design spectrum, namely, the ultra-low power with acceptable performance at one end~ and high perfor- mance with power within limit at the other.
Relationship: contrasting
Domain: Hardware
Sentence 1: Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches Xiuyuan Bi, Zhenyu Sun, Hai Li Polytechnic Institute of New York University 6 Metrotech Center, Brooklyn, NY, USA Email: xbi01@students.poly.edu Abstract Using the spin-transfer torque random access memory (STT-RAM) technology as lower level on-chip caches has been proposed to minimize leakage power consumption and enhance cache capacity at the scaled technologies.
Sentence 2: programming STT-RAM is a stochastic process due to the random thermal .uctuations.
Relationship: contrasting
Domain: Hardware
Sentence 1: Therefore, to ensure back-to-back execution of a load and its dependents (and even their children), instructions depending on a load are speculatively issued as early as possible with the assumption that the load will hit in a cache and the data will be available in a known and .xed number of cycles.
Sentence 2: if the load takes longer or does not provide the data in a given latency, the specula­tively-issued instructions must be squashed and reissued.
Relationship: contrasting
Domain: Hardware
Sentence 1: Overlapping runahead periods may be bene.cial for per­formance, because the completion of load A may result in the availability of data values for more instructions in runa­head period 2, which may result in the generation of useful prefetches that could not have been generated in runahead period 1.
Sentence 2: if the availability of the result of load A does not lead to the generation of new load ad­dresses that generate prefetches, the processor will execute the same N instructions twice in runahead mode without ob­taining any bene.t.
Relationship: contrasting
Domain: Hardware
Sentence 1: Offset Errors in Back-end Stages When a non-zero offset is considered in the model (5) and none calibration is applied, no additional distortion ap­pears because an offset in ADC2 is directly translated to an offset in the complete ADC.
Sentence 2: in the proposed  Za ENOB Za ENOB 1 Ideal Direct Indirect e1 ·a1 = 20%  1  1112  0.99 1010 0.95 0.98 9 8 0.97 8 0.9 6  0.96 7 0.95 0.85 4 6  0.94 0 5 10 15 0 5 10 15 0 5 10 15 0 5 10 15 normalised time 6 normalised time 6 normalised time 6 normalised time 6 x 10x 10x 10 a) b) Fig.
Relationship: contrasting
Domain: Hardware
Sentence 1: Power Model Power dissipation in CMOS circuits can be divided into two major components P P P (1) dynamic leakage There is a third component, short-circuit power that results from a direct-path current when both the pull up and pull down networks are simultaneously on while inputs switch.
Sentence 2: short-circuit power is usually small compared to the other two components of total power, and also is expected to become even less significant as technology scales down [3].
Relationship: contrasting
Domain: Hardware
Sentence 1: Some accesses can freely proceed in parallel: a thread can access its own private data without holding the deterministic token (1) and it can also read shared data without holding the token (2).
Sentence 2: in order to write to shared data or read data regarded as private by another thread, a thread needs to wait for its turn in the deterministic total order, when it holds the token and all other threads  Figure 6.
Relationship: contrasting
Domain: Hardware
Sentence 1: As we can .nd from the .gure, when both genuine and Trojan-dormant chips are tested under the same operation conditions, the average power consumption of Trojan-dormant chips is fully overlapped with that of genuine chips.
Sentence 2: figure 10 shows that 16 out of the total 18 Trojan-infected chips have measurable gaps when the inserted Trojan is turned on or muted, which gives the measurement noise and circuit status differences that will be used for cali­bration.
Relationship: contrasting
Domain: Hardware
Sentence 1: 6.3 Exponential Distribution The FPGA community has not shown as much interest in the exponential distribution as the Gaussian distribu­tion, mainly because most FPGA-based Monte-Carlo simu­lations have been discrete-time based.
Sentence 2: as FPGAs become larger and more capable, complete discrete-event simulationsin .eldssuch asbiochemistry[7] and credit-risk analysis[23] arebeing acceleratedby moving thewholeap­plication into the FPGA.
Relationship: contrasting
Domain: Hardware
Sentence 1: User-Controllable Coherence for High Performance Shared Memory Multiprocessors * Collin McCurdy and Charles Fischer Computer Sciences Department University of Wisconsin-Madison 1210 West Dayton Street Madison, WI 53706 {cmccurdy, .scher}@cs.wisc.edu ABSTRACT In programming high performance applications, shared address-space platforms are preferable for .ne-grained computation, while distributed address-space platforms are more suitable for coarse-grained computation.
Sentence 2: currently only distributed address-space systems scale beyond the low hundreds of processors.
Relationship: contrasting
Domain: Hardware
Sentence 1: As pointed  out by Ekman and Stenstr¨ om [9], such extra 2-3 cycles on a main memorylatency has very limited impact on the overall performance of the system.
Sentence 2: when a P-page descriptor is missing, the P-page descriptor must be brought back in the UCT cache from the memory, thus resulting in a signi.cant longer memory access time.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, if the soft error .ipped an upper bit in the result of Ib and instruction 2 was an AND that masked the upper bits, the fault would never be visible to instruction 4, reducing its ability to man­ifest a symptom.
Sentence 2: instruction 1 would still consume the tainted value and potentially write it out to memory, corrupting sys­tem state.
Relationship: contrasting
Domain: Hardware
Sentence 1: V. ARC HITECT URAL A DDIT IONS F OR FU RTH ER IMPROVE M E NT Through asymmetric pipelining and pseudo multi-banking, AVICA becomes free of the process variation-induced access time failures.
Sentence 2: some benchmarks, especially integer benchmarks, show nontrivial performance hits as will be shown in section 6.
Relationship: contrasting
Domain: Hardware
Sentence 1: 13 - Discharging current for the interconnect capaci- tance and gate capacitance between signal line and  power grid.
Sentence 2: the currents I 1 and 12 form current loops thourght the package and grid decoupling capacitances, while 13 forms a current loop from the driver output, through the grid and back, as modeled in the traditional loop inductance approach.I 1 and 12 significantly impact the effective inductance seen by the signal net.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the number of inputs or outputs is too large, the write or read instruction will dominate the number of cycles required to execute the custom instruction.
Sentence 2: if the large cus­tom instruction can be divided into several smaller custom instructions, and the execution cycles of the large custom in­struction is greater than the sum of the execution cycles of the small custom instructions, the division can improve per­formance without signi.cant cost.
Relationship: contrasting
Domain: Hardware
Sentence 1: One obvious method is to inject the fault into the node of the circuit and simulate the circuit for different input vectors and for different fault originating locations (nodes), in order to find whether the fault propagates [32].
Sentence 2: this approach becomes intractable for larger circuits and larger number of inputs and thus Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the memory accesses are concentrated on and near the most recently used entries, the mechanism knows that the local­ity of reference is very high and there is room to decrease the number of ways activated to .t the current locality.
Sentence 2: if the accesses are widely distributed from the most recently used entries to the least recently used ones, the mechanism understands that more ways are needed to improve the performance as long as the resources are avail­able.
Relationship: contrasting
Domain: Hardware
Sentence 1: The majority of previous gradient-based statistical inference approaches employ the .at space approximation of the conjugate gradient [28][29] [30], based on the rationale that the minimization of functions on a Riemannian manifold is locally equivalent to the minimization on an Euclidian space (since every Riemannian manifold can be isometrically embedded in an Euclidean space).
Sentence 2: as the statistical space is a curved manifold, most of the Euclidean space operations become unde.ned.
Relationship: contrasting
Domain: Hardware
Sentence 1: 5.3 System-Level Effects of Low-Level Design Decisions At the microhotplate design level, using a controlled-current or a controlled-voltage source to drive the heater is an implementation detail, with circuit-level concerns typically deciding the choice of one over the other.
Sentence 2: we found that such decisions could sig­nificantly impact system-level behavior, with integrated SystemC modeling of the MEMS device helping both to detect such behavior and to ensure optimal design.
Relationship: contrasting
Domain: Hardware
Sentence 1: proposed a line-paring scheme which divides the parallel MLC into read-fast-write-slow and write-fast-read-slow re­gions [17].
Sentence 2: the parallel MLC [13] is sensitive to process variations and has poor reliability, while the series MLC structure [9] demonstrates overwhelming bene.ts in read and write reliability and great potential in commercial usage [10].
Relationship: contrasting
Domain: Hardware
Sentence 1: Dynamic voltage and frequency scaling (DVFS) [11][15] exploits system­level workload variations in applications and scales the operating +  frequency and the supply voltage accordingly to reduce energy correction  dissipation, when the datapath is not fully loaded.
Sentence 2: the performance requirements of its predefined frequency-voltage  pairs need to be met for a wide range of process, voltage, temperature, and delay variations.
Relationship: contrasting
Domain: Hardware
Sentence 1: For optical interconnects, this performance metric is constant as the increase in the number of multiplexed channels linearly increases the power and does not change the latency.
Sentence 2: for the Cu and CNT technology, the compound metric increases at lower bandwidth density, and decreases at the higher values because of various competing factors: At low values, as bandwidth density increases, power dissipation reduces, but is compensated by an increase in the latency (Figure 5).
Relationship: contrasting
Domain: Hardware
Sentence 1: On the one hand because they enable a system designer to fully exploit the hardware s capabilities: A lot of building blocks can be integrated, their interconnection for a speci.c application is performed adap­tively by the network.
Sentence 2: maybe the most important argument in favour of Networks-on-Chip is that the concept of interconnection architecture recon.guration is complementary to both hardware and software recon.gu­ration in each building block.
Relationship: contrasting
Domain: Hardware
Sentence 1: As the evolu­tionary algorithm (EA) can be implemented in the same FPGA in case of these applications, a fast con.guration interface can be established connecting the con.guration memory of VRC with chromosomes of EA.
Sentence 2: implementations of VRCs are rela­tively expensive in terms of gates used because interconnec­tion circuits of VRCs are based on area-expensive multiplex­ers.
Relationship: contrasting
Domain: Hardware
Sentence 1: In the presence of VIs, not only can cores run on optimal voltages with minimal overhead to reduce chip power dissipation, but the on­chip interconnection network can also exploit VIs to reduce communication power.
Sentence 2: vIs complicate the problem of NoC synthesis, requiring designers to revisit the problems of VI partitioning, core to die mapping, and routing path allocation so that both computation and communication power can be minimized.
Relationship: contrasting
Domain: Hardware
Sentence 1: Redundant link insertion to minimize open defect is another technique proposed in [29].
Sentence 2: these works have a few drawbacks: (a) one single defect size is considered, rather than a defect size distribution [26], [27], (b) the trade-off between open and short defects due to .xed routing area is ignored [26], [27], [29] [31], (c) localized/greedy optimization is performed, which may be suboptimal [29], [30], [32] [34], (d) wire adjacency information is not available for accurate critical area estima­tion [28], [35].
Relationship: contrasting
Domain: Hardware
Sentence 1: For this work, we used the .rst hits from a Google search; we did not select for accuracy.
Sentence 2: we listened to ex­ 1In previous work on transcribing multiparty meetings, we found that a one hour meeting could take upwards of 20 hours for a human to transcribe and there is no reason to think that a sitcom would be qualitatively di.erent.
Relationship: contrasting
Domain: Hardware
Sentence 1: Thehardware must also respect regionboundaries(as enforced by memoryfences), andit additionallydetects con.icting accesses tothesame memorylocation(i.e.,accesses whereatleast oneisa write)from concurrently executing regions.Ifsuch a region con.ict is detected, the hardware throws a memory-model exception and the detected con.ict is a witness to a data race in the source program.
Sentence 2: if there are no region con.icts, then the executionis region-serializable  equivalent to an executionin which each regionis executed atomicallyin someglobal sequential order consistent with the per-thread order of regions and hence SC.
Relationship: contrasting
Domain: Hardware
Sentence 1: The proposed solution is fundamentally di.erent from [7, 11, 12, 17, 18, 19] in that mapping is no longer done prior to routing but instead during it.
Sentence 2: we compare UMARS only to [7], and a more extensive comparison with traditional algorithms [11, 12, 17, 18, 19] is of value.
Relationship: contrasting
Domain: Hardware
Sentence 1: 3.3.7 BoundingBoxUpdate In the serial VPR program, bounding box update is done in­crementally(except when neededto eliminate round-off error) as partof theswap costevaluationfunction.
Sentence 2: intheparallel program, each thread calculatesitsincrementalbounding boxcost based onstaledatawhich containsimprecisedataabout allblocks that are not located within its private region.
Relationship: contrasting