sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: The objective function (1) seeks to minimize the sum of CS values, and consequently, constraint (4) will be met in a way that minimizes the CSi,j values.
Sentence 2: cSi,j will be set to exactly 1 only for those cases where a load of clock i is used in column j; otherwise, CSi,j will take on value 0.
Relationship: entailment
Domain: Hardware
Sentence 1: US I N G IN C R E M E N TA L QBF F O R BMC O F IN C O M P L E T E DE S I G N S In this section we present an application for incremen­tal QBF solving, namely proving unrealizability of a safety property P in an incomplete design (those containing so­called blackboxes) using BMC.
Sentence 2: we prove the existence of a path of length k violating P no matter how the blackboxes are implemented.
Relationship: entailment
Domain: Hardware
Sentence 1: Then, in lines 7-18, at each iteration, the algorithm system­atically generates new candidate set partitions starting from the set partition chosen from the previous iteration.
Sentence 2: in the .rst iteration, the algorithm starts with the initial set par­tition P0 = {{e1},{e2},...,{en}} with ngroups, each group containing exactly one edge.
Relationship: entailment
Domain: Hardware
Sentence 1: (3) Using sweep line and interval tree, detect conflicts between polygons by finding overlapping pairs of rectangles that belong to different polygons and record the conflict edge pairs.
Sentence 2: fig.3 the conflict graph is derived from the conflicts between features In AltPSM, we can remove all phase conflicts by assigning opposite phases to each pair of adjacent nodes in the conflict graph G. This can be formalized as bipartization (making 2-colorable, or equivalently, ensuring no odd cycles ) of the conflict graph G. if the conflict graph G is not bipartite, we must delete enough edges such that no odd cycles exist in the remaining modified conflict graph.
Relationship: entailment
Domain: Hardware
Sentence 1: The results can then be used to identify high priority sensors and to invest a given security budget in the most cost-effective way.
Sentence 2: 4.1 Attack models We consider the case when the state of the system is measured by a sensor network of p sensors with measurement vector y(k)= {y1(k),...,yp(k)}, where yi(k) denotes the measurement by sen­sor i at time k. All sensors have a dynamic range that de.nes the domain of yi for all k. all sensors have de.ned mini­ min max mum and maximum values .k, yi(k) .
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION 3D integrations, the mixed-technology stacking is especially attrac­tive for stacking MRAM memory on top of CMOS logics, pro- Magnetic Random Access Memory (MRAM) has been consid­viding a mean to mount MRAM layer on top of logic layers, so ered as one of the most promising universal memory technologies that designers can take full advantage of the attractive bene.ts that due to its non-volatility, fast speed, zero standby power, and high MRAM provides.
Sentence 2: the integration of MRAM with mi­ density.
Relationship: entailment
Domain: Hardware
Sentence 1: on-period) duration distribution G, we show that the asymptotic tail distribution of the response times is dom­inated by the heavier one of the residual service time and the residual session duration.
Sentence 2: the waiting time dis­tribution is asymptotically equal to the tail distribution of the residual service time if the latter is heavier than that of the residual session duration time.
Relationship: entailment
Domain: Hardware
Sentence 1: Although there has been extensive research on low-power ME [3, 4, 16], related work does not provide run-time adaptivity.
Sentence 2: state-of-the-art low- Permission to make digital or hard copies of all or part of this work for per­sonal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: entailment
Domain: Hardware
Sentence 1: It turns out that our distributed switch arbiters generated by RAG lead to significant area and delay improvements when compared with other switch arbiters such as PPA and PPE.
Sentence 2: rAG can be used to generate a switch arbiter for a 128x128 terabit switch which, assuming as stated in [5] that the critical path is the switch arbitration logic, achieves throughput 1.9X higher than PPA and 2.4X higher than PPE for the same 128x128 configuration.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we make the new observation that knowing (or, more broadly, distinguishing) the value programmed in the immediate-neighbor cell makes it easier to determine the value stored in the flash cell that is being read.
Sentence 2: one can classify the threshold voltage distribution of flash memory cells into multiple threshold voltage distributions based on the logical value of the immediate-neighbor flash cell and use the appropriate "classified" (or, conditional) voltage distribution (and the corresponding read reference voltage values associated with it, called the "local optimum read reference voltages") to more accurately determine the value of the cell that is being read.
Relationship: entailment
Domain: Hardware
Sentence 1: This result also im­plies that the maximum achievable throughput of an energy ef.­cient sensor network is always less than that of a normal ad hoc network.
Sentence 2: the reduction in channel contention due to the nodes periodically switching over to sleep state is outweighed by the longer delays incurred due to the nodes not being able to Figure 4: Maximum achievable effective throughput versus probability that a node is active.
Relationship: entailment
Domain: Hardware
Sentence 1: The major feature that differentiates it from all the previous RO-based schemes is that we equip each TSV s output inverter with variable thresholds.
Sentence 2: sometimes a TSV s output inverter behaves like a normal CMOS logic inverter, while at some other time its 0Æ1 and  1Æ0 thresholds are made different, by switching it to a Schmitt-Trigger inverter as will be detailed later.
Relationship: entailment
Domain: Hardware
Sentence 1: To accommodate this, we decided to try a multifocal mapping function consisting of a sum of sigmoids.
Sentence 2: we mapped time t to 11 x(t,ta,tb)= s(t,ta)+ s(t,tb)= + 1 + u-v*(t-ta ) 1 + u-v*(t-tb ) Figure 6: Gantt chart with two .sheye zooms.
Relationship: entailment
Domain: Hardware
Sentence 1: 100W/cm2 for force-air cooling, 1 10W/cm2 for am­bient cooling), not transistor integration density, is the key limitation for computations [12].
Sentence 2: we cannot a.ord to turn on all the transistors that we can integrate onto an integrated circuit [15], a phenomenon now termed Dark Sil­icon [29, 10].
Relationship: entailment
Domain: Hardware
Sentence 1: 5.3 Optimizing Acknowledgments based on MAC characteristics Due to processing constraints in sensor systems, as well as the ine.ciency of copies in FLASH memory, we choose to compress the traditional layered protocol architecture to reduce data copies and management overhead.
Sentence 2: impala uni.es the session-based transport control with the timeslot-based media access control.
Relationship: entailment
Domain: Hardware
Sentence 1: (1) 2(1 - .T ) However, unlike the systems with exponentially distributed service times, the output from an M/D/1 system is no longer a Poisson process: the time between two consecutive outputs is guaranteed to be greater than or equal to the service time value T .
Sentence 2: a constant-time server produces a de-randomization of the Poisson process, thus reducing the degree of randomness of the inter-arrival times, which is the main cause of contention delays at the input queue.
Relationship: entailment
Domain: Hardware
Sentence 1: Previous works have observed that there exists a corre­lation between the concept of idleness exploited in power management strategies and aging.
Sentence 2: the hard­ware implementation of a low-power state (i.e., voltage scal­ing for dynamic power and power/ground gating for static power) can be leveraged to reduce NBTI-induced aging [4, 5].
Relationship: entailment
Domain: Hardware
Sentence 1: From Theorem 4 it follows that Smx < Sx and hence the sensitivity bound Smx can be used to prune gate x before its perturbation front reaches the sink node.
Sentence 2: if at any time during the propagation of the front for gate x the bound Smx become less than a previously computed sen­ sitivity Si of gate i, gate x can be eliminated from further consider­ation.
Relationship: entailment
Domain: Hardware
Sentence 1: With superposition, the problem of generating input vectors for characterizing a system is dramatically simplified since the output response is simply the sum of the contributions from each of the analog inputs: N Y=c + La· X (1) ii i=1 where li denotes the partial gain from the input Xi to the output Y and c is a DC offset.
Sentence 2: a linear system is completely described by a set of gains, li's, which can be determined by a set of test vectors whose size grows linearly with the number of inputs, N. Said differently, the result surface for a linear system is smooth, so it doesn t take many points to completely characterize it.
Relationship: entailment
Domain: Hardware
Sentence 1: 3, the trans­fer gate TG1 is removed as in the previous approach and a second additional pass-transistor PT2 is inserted and con­nected in-between the memory logic and the output of the .ip-.op itself.
Sentence 2: pT2 will increase the perfor­mance of the entire circuit, since it acts as a sense-ampli.er which o.sets the memory logic by its metastability when the .ip-.op is re-activated or de-activated, leading to faster sleep-in and sleep-out operations.
Relationship: entailment
Domain: Hardware
Sentence 1: TABLEI LOK-UPPERIODFOR OPTIMIZEDLF'sPARAMETERCAsE LokUpConventionalPLLPhaseAdjustPLL Frequeny 7.11fse 6.08fse Phase 3.82fse 2.73fse TABLEII LOK-UPPERIODFOR UN-OPTIMIZEDLF'sPARAMETERCAsE LokUpConventionalPLLPhaseAdjustPLL Frequeny 18.60fse 16.09fse Phase 8.67fse 6.49fse Forallases,thelok-upperiodisimprovedby10to30%.
Sentence 2: theredutioninthelok-upperiodismorethan2fs fortheun-optimizedLFparameters,whihorresponds tomorethan400lokylesofthePLL.Fig.10and Fig.11showtheunloksignalleveloftheonventional andtheproposedPLLforun-optimizedLFparameters, respetively.ThesefguresshowtheproposedPLLhas Unlock Signal Level (V) 5 4 3 2 1 0 0 10 20 30 40 50 60 Time (usec) Fig.10.UnlokSignalTransitionofConventionalPLLwith Un-optimizedLFParameters Unlock Signal Level (V) 5 4 3 2 1 0 0 10 20 30 40 50 60 Time (usec) Fig.11.UnlokSignalTransitionofPhaseAdjustPLLwith Un-optimizedLFParameters shorterlok-upperiodthantheonvetionalPLLforini­tialfrequenyloking.Thephaselokingstartsat40fs asthereferenelokinvertsitsphase(shiftsphaseby theamountof)atthismoment.TheonventionalPLL leavesthelok-uponditionafteritmeetsthetheondi­tiononetime.Thelok-upstabilityisimprovedinthe proposedPLLbeauseitneverleavesthelok-upondi-tiononeitmeetstheondition.Fig.12andFig.13 Frequency (MHz) 220 215 210 205 200 195 190 185 180 175 170 1015202530 3540455055 60 Time (usec) Fig.12.FrequenyTransitionofConventionalPLLwith Un-optimizedLFParameters showthetransitionofthefrequenyoftheonventional PLLandtheproposedPLLforthesameun-optimized LFparametersasinFig.10andFig.11,respetively.In Frequency (MHz) 220 215 210 205 200 195 190 185 180 175 170 1015202530 35404550 55 Time (usec) Fig.13.UnlokSignalTransitionofPhaseAdjustPLLwith Un-optimizedLFParameters theproposedmethod,thefrequenylok-upprofleisim­proved.Theamountoffrequenyovershootissuppressed intheproposedPLL.Fig.14showsthe"DelayControl Delay Contorl Bits 9 8 7 6 5 4 3 2 1 0 0 102030405060 Time (usec) Fig.14.DelayControlBitTransitionofPhaseAdjustPLLwith Un-optimizedLFParameters Bits"valuefortheVDintheproposedmethod.The "DelayControlBits"areontrolledappropriately.whenthephasedeviationofthePLLlokfromthe targetreferenelokislarge,thevalueismodifedfre­quently.Asaresult,theproposedmethodimprovesnot onlythePLL'sfrequenyandphaselok-upperiodbut alsothePLL'sstability.
Relationship: entailment
Domain: Hardware
Sentence 1: This section describes the logic architecture of the Altera Stratix II FPGA (the same basic architecture was kept for the subsequent Stratix III as well).
Sentence 2: the existing carry-chains propagate through all 8 cells at a time; the carry chain in our proposed logic block, in contrast, propagates only through 2 at a time, thereby increasing flexibility and reducing delay.
Relationship: entailment
Domain: Hardware
Sentence 1: Given the correlations we observed be­tween errors in the previous subsections, an interesting question is whether it is possible to predict an increased likelihood of future multi-bit or chipkill errors based on the previous error behavior in the system.
Sentence 2: one might speculate that prior repeat er­rors, which likely indicate hard errors, will increase the probability of later multi-bit or chipkill errors.
Relationship: entailment
Domain: Hardware
Sentence 1: SYSTEM DESIGN 2.1 Mote Design and Placement Designing our mote involved several mundane, but practical issues including proper design of vent holes and internal circuitry to provide optimal air-.ow and sensor response, optimal placement of the internal patch an­tenna, etc.
Sentence 2: from interviewing several .eld operators of building management systems, we learned that traditional temperature sensors that are mounted on walls often are o. by a degree in Celsius or more compared to the actual ambient air temperature1.We designed our motes to have their sensors elevated some­what from the surface they are installed on, and e.ec­ 1this applies even when both sides of the wall are inside the building, which implies that the temperature di.erence is due to convection, not conduction 421  Figure 1: Layout of the 99-node deployment tively mitigated this phenomenon.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that this somewhat unorthodox de.nition results in non-deterministic monotonic virtual counters.
Sentence 2: the value of a particular virtual counter C is guaranteed to always increase, but can increase by unpredictable amounts, since operations on other virtual counters can cause the global counter to increment in between increment requests for C. This is not a problem, however, since for detecting forking and replay attacks as described in Sect.
Relationship: entailment
Domain: Hardware
Sentence 1: It is understood that similar discussion ap­plies to subtraction and minimum operations, as well.
Sentence 2: given D1 and D2 in the form of (4), X D1 = d01 + (ai1Xi + bi1Xi 2) + ar1Xr1 + br1Xr2 1, (8) X D2 = d02 + (ai2Xi + bi2Xi 2) + ar2Xr2 + br2Xr2 2, (9) we want to compute D = D1 + D2 or D = max(D1, D2) such that the resulting D can be represented as (4).
Relationship: entailment
Domain: Hardware
Sentence 1: The aspect ratio of the modules is allowed to vary in the design, providing significant power/access time/area tradeoffs.
Sentence 2: each block (B0 through B15 in Figure 1) is a factor of 16X smaller than the traditional memory configuration; as a result, bit- and word-lines are reduced by a factor of 16X, dramatically reducing dynamic power consumption during access of a particular memory location.
Relationship: entailment
Domain: Hardware
Sentence 1: Such co­operation and competition engendered by oscillatory nonlinear dynamics can produce complicated and beautiful spatio-temporal patterns of collective behavior.
Sentence 2: pattern formation arising from the nonlinear interaction of many individual cells in biochemical systems is a fascinating and extensively noted phenomenon (e.g., [6] [8]) for example, an important issue in developmental biology is understanding the formation of spatial patterns in the embryo.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paradigm, though programmers can write code assuming inde­pendent execution of threads, the actual execution is in SIMD fash­ion to match the SIMD architecture.
Sentence 2: a modern GPU comprises a set of streaming multiprocessors (SMs), within which a batch of the threads, referred to as warp in CUDA or wavefront in OpenCL, is executed in a lock-step manner.
Relationship: entailment
Domain: Hardware
Sentence 1: PERFORMANCE RESULT The testing sessions have been carried out by sending audio and video streaming, remote monitoring and bulk data on different ports in order to verify the different treatment operated on different traffic flows.
Sentence 2: real audio and video traffics have been captured by means of ZTI Sniffer Module, and replayed by ZTI IP Generator Module that also performs remote monitoring and FTP bulk data traffics with user­defined patterns.
Relationship: entailment
Domain: Hardware
Sentence 1: As can be seen, SD+GPD (points with both a perfor­mance loss and cost increase) provides larger MTTF ben­e.t than SD or GPD alone.
Sentence 2: at the extreme point, a guaranteed loss of 50%or an actual loss of 15% in performance (performance value of 0.5in Figure 7(a) and 0.85in Figure 7(b)), coupled with a cost 2.25times the base cost, provides an average MTTF 4.16times better than base MTTF.
Relationship: entailment
Domain: Hardware
Sentence 1: In particular, the focus of the four papers included here is centered on the ideas of communication , platform-based de­sign , schedulability analysis , and architecture exploration as foundations of ef.cient design for complex (possibly recon.gurable or distributed real-time) systems of the future.
Sentence 2: these articles cover issues speci.c to both design methodologies and CAD tools for system-on-chip (SOC) communication infrastructure design, wireless (and ad-hoc) network design, and automotive electronics.
Relationship: entailment
Domain: Hardware
Sentence 1: ACKNOWLEDGMENTS We would like to thank the anonymous reviewers and the Com­puter Architecture Group at Cambridge University for their con­structive comments and suggestions.
Sentence 2: we would like to thank Arnab Banerjee and Robert Mullins for their insightful discussions, Christophe Dubach and Timothy Jones for providing valuable feedback, and Kate Aufses for her assistance editing the .nal paper.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.2 Scenario Two: Set S is not given andthe elements are not duplicable In Scenario One, when solving the optimization problem, the  2n-1 minimal difference i=0 ziri -q is actually a function of q, which we denote as h(q).
Sentence 2: 2Nn-1 h(q) = min ziri -q .
Relationship: entailment
Domain: Hardware
Sentence 1: In this way, we can iteratively update the Elmore delay targets for each sink to compensate the errors.
Sentence 2: we sequentially use a quadratic function akx+bkx+kas our approximation func­tion, where ak,bk, and kare the respective new coef.cients for next iteration and new xis the Elmore delay target.
Relationship: entailment
Domain: Hardware
Sentence 1: The ADC is made up of 4 multi-bit stages and in­cludes digital calibration circuits to enhance performance.
Sentence 2: the Digital-to-Analog sub-Converter (DAC) errors are canceled with the DAC Noise Cancelation (DNC) technique [21] and the .rst stage Sample-and-Hold Ampli­.er (SHA) errors are corrected through a Gain and Distor­tion Error Correction (GDEC) algorithm as in [22].
Relationship: entailment
Domain: Hardware
Sentence 1: For further reduc­ing the pipeline stages, a double speculation that performs the RC, VA, and SA operations in parallel is possible, however it would de­grade the overall performance because of frequent mis-speculations and retries.
Sentence 2: 2.2.2 Look-ahead Router The look-ahead routing technique removes the control dependency between the routing computation and switch allocation in order to perform them in parallel, by selecting the output channel of the i-th hop router in the (i - 1)-th hop router.each router performs the routing computation for the next hop (NRC).
Relationship: entailment
Domain: Hardware
Sentence 1: Various researches [4, 6, 26] have focused on solving this problem, but most of them concentrate on the allocation of CPU and network bandwidth, little attentions have been paid to alleviate disk I/O performance interference among virtual machines, which is a critical factor in determining the overall performance of I/O applications running in virtual machines.
Sentence 2: once an I/O intensive application starts to run, the I/O performance of co-located applications residing in other virtual machines will be seriously injured.
Relationship: entailment
Domain: Hardware
Sentence 1: Through the evolutionary process into the E-Table, some rows in some F-Tables are ex- pected to be changed to match unknown case records whose categories are not identified.
Sentence 2: through the evolutionary process, each E-Table is ex- pected to obtain generalization capability to catego- rize the unknown case records; i.e., the rules behind each category are expected to be embedded in the E-Table automatically.
Relationship: entailment
Domain: Hardware
Sentence 1: Our prior work has shown the viability of energy harvesting en­ergy meters [4].
Sentence 2: we have shown that the energy emit­ ted from many electrical loads is roughly proportional to the energy consumed by that load, and that by harvesting this side-channel en­ergy, it is possible to intermittently power sensors whose activation interval (and in turn packet transmission period) approximately en­codes the underlying energy use.
Relationship: entailment
Domain: Hardware
Sentence 1: All these processor subsystems quasi-continuously face state changes at run-time and we are concerned with state changes which affect the temporal behavior of the executing tasks.
Sentence 2: it is the case for task preemptions: when a task resumes its execution (after being preempted), for example, the cache(s) will display a state which is different from its state at the time the task got interrupted.
Relationship: entailment
Domain: Hardware
Sentence 1: The end-to-end perturbation for HPMs is either within or close to the standard deviation of the executions without HPMs.
Sentence 2: end-to-end perturbation is 2.77% for Cyc and 0.11% for InstCmpl, which is less than the standard deviation for executions without HPMs: 2.92% for Cyc, 0.23% for InstCmpl.
Relationship: entailment
Domain: Hardware
Sentence 1: Efficient ILP solvers are now readily available, both commercially and in the public domain.
Sentence 2: for our experiments in Section 5, a public domain ILP solver (2) Assume rowi (corresponding to fault fi) and rowj (corresponding to fault fj) be two rows in the constraint matrix B. Rowi dominates rowj if (A) for each column k, if Bjk = 1, then Bik = 1, AND (B) if fi needs to be covered Ci times and fj needs to be covered Cj times, then Cj t Ci   fault fi is detected at least Ci times whenever fault fj is detected Cj times.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that, these percentages are valid for each nest of each ap­plication.
Sentence 2: in each loop nest, the same percentage of TABLE IV STAT I S T I C S W H E N 20% OF T H E I DL E P RO CE SSORS ARE USE D FOR COMPUTAT ION DUPL ICAT ION .ASC O M PA R E D T O TABL E III, WE HAVE MORE CYCL E S AND MORE E N E R GY CONSUMPT ION HE RE DUE TO DUPL ICAT ION .
Relationship: entailment
Domain: Hardware
Sentence 1: However, there is still a chance that a transient error can strike during execution of an unduplicated computation, which cannot be detected by our approach.
Sentence 2:  TABLE I MAJOR SIMULATION PARAMETERS AND THEIR VAL UE S.   Parameter Value Number of Processors 8 8KB L1 Instruction Cache 2-way associative 32 byte blocks 8KB L1 Data Cache 2-way associative 32 byte blocks 1MB L2 Cache 4-way associative 64 byte blocks L1 Dynamic Energy Consumption 0.16 nJ/access L2 Dynamic Energy Consumption  0.65 nJ/access r 0.1 Reactivation Latency 4cycles Off-Chip Memory Energy  6.32 nJ/access Off-Chip Memory Access Latency 80 cycles On-Chip Bus Arbitration Delay 5cycles Replacement Policy Strict LRU while we increase the resilience of execution against soft er­rors, the number of errors we actually detect is another matter, and depends on error injection rate, error injection pattern, and other factors.
Relationship: entailment