sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Typically, these collection tools instrument MPI programs with the MPI pro.ling layer (PMPI), and record communication operation details (e.g., message type, size, source/destination, and timestamp) during the pro­gram execution.
Sentence 2: as the applications scale up (in terms of both the number of processes and the problem size), the volume of communication traces increases dramatically.
Relationship: contrasting
Domain: Hardware
Sentence 1: The original HDL descriptions of b04 and b09 contain a high number of nested conditions, respectively, on 8 bit­sized and 1 bit-sized signals and registers.
Sentence 2: ex and b00 contain conditional statements where one branch has probability 1- 232 1 of being satis.ed, while the other has probability 232 1 .
Relationship: contrasting
Domain: Hardware
Sentence 1: Until recent years, there are a few research projects which focused on developing parallel FMM algorithms on GPUs [8, 9].
Sentence 2: existing GPU-based FMM methods merely exploit parallel computation of multipole and local expan­sion coe.cients on-the-.y during each sparse matrix-vector multiplication (SPMV), without optimizing the GPU data structures or algorithm .ows according to the latest GPU hardware properties, which can not be directly deployed for e.cient acceleration of GPU-based 3-D capacitance extrac­tion programs.
Relationship: contrasting
Domain: Hardware
Sentence 1: Figure14:Givenafxednumberofiterationsto route,theprobabilityofsuessfulroutinginreases withthenumberofrelaxednets AlgorithmRelax Iets(netlistN) begin ConstrutGr(VrVEr); R:0; whilethereisanodevwithSv:Lvdo begin relaxnetv; R:R{v}; reomputeslakforpathsontainingv; end.
Sentence 2: returnR; end Figure1 :AlgorithmRelax Iets  relaxationmustensurethattheperformaneoftheiruit doesnotdegrade.itiseasytoseethatbyusing informationaboutthefowofsignalsintheiruit,thisre­laxationanbedoneinsuhawaythattheperformane oftheiruitdoesnotdegrade.Thisisdonebyidentifying asubsetofnetsthatdonotlieonthelongestpath,and togetherdoesnotinreasethetotaldelay.Todothis,we frstonstrutagraphGr(VrVEr)whereeahnEVrisa net,and(uVv)EErifnetupreedesnetv.Foreahnode vinthegraph,wefnditsslak,Sv,whihisthediferene betweenthelongestpathofthegraphandthelongestpath throughthenet.LettheinreaseindelaybeLvwhennet visrelaxed.AlgorithmRelax  Ietsgivesaheuristitofnd thesetofnetstorelaxthatwillnotdegradetheperformane oftheiruit.Moresophistiatedmethodsthatinreasethe numberofnetsrelaxedanbeemployed.
Relationship: contrasting
Domain: Hardware
Sentence 1: If violators of MinIA constraints have enough spacing around them, then the violations can be easily .xed by inserting same-Vt .ller cells, thereby increasing the width of the implant area.
Sentence 2: when the spacing is insuf.cient, we must change cell size/Vt or perturb the placement, such that the implant layer region of the narrow cell can match up with an adjacent (abutting) implant layer region.
Relationship: contrasting
Domain: Hardware
Sentence 1: An Erroneous Case is detected by a parity tree if and only if the parity tree comprises an odd number of bits bi that detect the Erroneous Case at any speci.c time-step between 1 and p. We note that the problem may be mod­elled as an NP-complete minimum cover problem, for which several heuristics exist [15].
Sentence 2: expanding the error detectability table to explicitly represent all possible parity functions for each latency step is infeasible, since there is an exponential number of alternative parity combinations.
Relationship: contrasting
Domain: Hardware
Sentence 1: For typical designs, Vmin was shown to fall around 300mV resulting in a frequency of operation in the hundreds of kHz range [3][4].
Sentence 2: many ultra-low power applications, such as active RFIDs, sensor networks and implantable medical devices require substantial lower operating frequencies, ranging from 100 s to 1000 s of Hz or even less [5].
Relationship: contrasting
Domain: Hardware
Sentence 1: In this scenario, the traditional paradigm for hardening systems is based on either the adoption of speci.c fault tol­erant architectures([3,4])orthe exploitationof application­level reliability-orientedpolicies([5,6]).
Sentence 2: the for­mer strategy constitutes a rigid solution with high costs, while the latter introduces signi.cant time overheads if ap­plied in a straightforward manner, especially if the applica­tion scenario allows for a selective hardening approach for a limited .nal overhead ([7, 8]).
Relationship: contrasting
Domain: Hardware
Sentence 1: Application Speci.cation, Mapping and PSM For further de.nitions of application scenarios, as well as proofs for boundedness and deadlock-freedom of markov­based scenario-aware data.ow graphs we refer to [20].
Sentence 2: the execution time eta of an actor a depends not only on the application scenario, but also on the power mode of the resource a is actually executed in.
Relationship: contrasting
Domain: Hardware
Sentence 1: For the same example as shown in Section 3, if the arrival time for a design is required to be 100, then obviously solution (A) is the best choice, as it satis.es the required arrival time constraints without any uncertainty.
Sentence 2: if the arrival time is required to be 200, then solution (D) would be the best choice, as this gives the highest probability to satisfy the design requirement.
Relationship: contrasting
Domain: Hardware
Sentence 1: Thus, the following statements about power consumption and delay can be extracted from the results on Table 2: - The full adders designed with pass transistor logic styles (cmos_26, cpl, cpl_sr, Ours_1 and Ours_2) exhibit less delay than the other ones, what can be expected from the fact of reduced internal parasitic capacitances as stated in [7] for these logic styles.
Sentence 2: - the full adders designed upon the logic structure shown in Figure 1 (bay_10a, bay_10b, bay_14a, bay_14b, bay_16, full_rest, tran_funct, wey_chow) have larger propagation delays (around or exceeding 1 ns) as expected, due to the internal XOR/XNOR gates that generate intermediate signals having an extra delay, used to control the output blocks.
Relationship: contrasting
Domain: Hardware
Sentence 1: A few extreme points deviate from the line though, meaning that the pre­dictor error is not accurately estimated for those con.gura­tions.
Sentence 2: the relative error between the value esti­mated during cross-validation and the e.ective one is small (less than 2%), which means that the model predicts accu­rately the area at those points.
Relationship: contrasting
Domain: Hardware
Sentence 1: Assuming a mechanism capable of such .ne-resolution diagnosis, an ef.cient recon.guration scheme can potentially shield against many NoC faults, disabling only a sin­gle unidirectional link for each fault.
Sentence 2: existing on-chip, topology-agnostic route-recon.guration solutions [1, 41] fail to ex­ploit this opportunity as they can operate with bidirectional links only.
Relationship: contrasting
Domain: Hardware
Sentence 1: There have been other research results that describe attempts at modeling routability during: the technology independent phase of synthesis, the logic extraction stage, by using topological information such as the fanout range [10], or via a companion placement of the logic net­ work nodes [9].
Sentence 2: placement of the logic nodes (which represent the Boolean equations) does not correlate well with the physical placement of a mapped gate level netlist, and congestion is mostly considered only during physical design, either at the glo­bal placement level or during incremental placement updates with­in resynthesis procedures [12][13][14].
Relationship: contrasting
Domain: Hardware
Sentence 1: {javed.absar, francky.catthoor}@imec.be Abstract An effectively designed and ef.ciently used memory hierarchy, composed of scratch-pads or cache, is seen today as the key to obtaining energy and performance gains in data-dominated embedded applications.
Sentence 2: an unsolved problem is how to make the right choice between the scratch­pad and the data-cache for different class of applications?
Relationship: contrasting
Domain: Hardware
Sentence 1: The critical path of the decoder, for this example, is also changed from the 3-input NAND gates to the 2-input NAND gates.
Sentence 2: we should point out that the B-Cache s 4×16 NPD is much slower than the 4×16 decoder in the original direct-mapped cache with a subarray size of 512 bytes as shown in Table 1.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, in Figure 7, the edge connecting vBLUE on the left bound­ary and vRED on the top boundary (shown in dashed line) will be removed.
Sentence 2: this does not work as vBLUE on the left bound­ary can still reach vRED on the top boundary by taking a detour as shown by the solid edges in Figure 7.
Relationship: contrasting
Domain: Hardware
Sentence 1: Using recency-based prefetching (in its presented form) directly for caches is likely to be awkward, because of the relatively higher miss rates, and much .ner granularity of data caches.
Sentence 2: such a prefetcher, while bene.ting TLB performance, might also be used to guide or .lter data cache prefetches from a multiple of more conventional prefetching algorithms -thereby improving ef.ciency and lowering the prefetch bandwidth requirement.
Relationship: contrasting
Domain: Hardware
Sentence 1: If a user has, for example, a full set of phone number, email address, and OSN ID of a mutual contact, but the only mutual entry is this last ID, it can be concluded that the other user s tie to that contact is not as strong.
Sentence 2: if both users share several di.erent phone numbers or email addresses of one contact, they both appear to be strong ties to that contact, which can enhance their mutual trust.
Relationship: contrasting
Domain: Hardware
Sentence 1: To resolve this problem, some forward recovery methods adopt triple-modular redundancy (TMR), in which three identical copies of a program are executed and majority voting are executed before critical operation, then the corrupted value can be corrected via other two consisten­t versions .
Sentence 2: these techniques have evident impact on runtime performance and storage overhead, which may be prohibitively high in some situations, especially for real-time applications and embedded systems.
Relationship: contrasting
Domain: Hardware
Sentence 1: The experiments also show just a straight 6%, 4%, and 2% performance loss against a 16-read port register file.
Sentence 2: because the access time of the 32-entry 8-r/8-w fully-associative memory is slower than one of the 512-entry 8-r/8-w register file that we are trying to replace with 50% reduction of register file read ports using OPB s and OPRQ s 50% reduction of register file read ports using OPB/OPRQ/DWQ 16R/8W 8R/8W 8R/8W/8OPB 8R/8W/16OPB 8R/8W/32OPB 16R/8W 8R/8W 8R/8W/8DWQ 8R/8W/16DWQ 8R/8W/32DWQ 100% 100% 90% 90%  Normalized IPC 80% Normalized IPC 80% 70% 70% 60% 50% Figure 6.
Relationship: contrasting
Domain: Hardware
Sentence 1: (the number of parallel repetitions of Protocol 4), the number of rounds is constant, the total number of bits transmitted is O(k.lg p), and a non­conforming party is caught with probability at least 1-2-. .
Sentence 2: even if it were less e.cient, since it need only be executed when cheating takes place, and all cheaters can be caught with high probability, the cost of detection when amortized over many rounds is essentially zero.
Relationship: contrasting
Domain: Hardware
Sentence 1: 3.2 Cluster Placement The logic clusters are then mapped on the CMOL tile fab­ric (one cluster per tile) using VPR tool [4,5].
Sentence 2: the original linear congestion cost function [4] is modi.ed, since it was not adequate for CMOL FPGA where connections within the connectivity domain are not limited by CMOS resources.
Relationship: contrasting
Domain: Hardware
Sentence 1: If there is little within-die variability, testing is straightforward: each die can be characterised by measuring the delay of a localised test structure.
Sentence 2: if within­die variation is a signi.cant part of overall delay variability, the test coverage must be either exhaustive, or at least su.­ciently comprehensive to enable statistically reliable bounds on the slowest element in the die.
Relationship: contrasting
Domain: Hardware
Sentence 1: Based on above analysis, if performance has a higher pri­ority in the design, we should choose threshold of 1000Mbps Throughput (Mbps) 980 960 940 920 900 880 860 800 900 80000700001000 600001100 500001200 4000030000 Threshold (Mbps) 1300 1400 20000Window size (cycle) Figure 9: Throughput under different design point with TDVS proportional to the workload, which makes TDVS and EDVS almost the same.
Sentence 2: this is not really the case in the NPU model.
Relationship: contrasting
Domain: Hardware
Sentence 1: While the last reference (or "last touch") to C 1 may occur well in advance of the refer- ence to C2, the block frame in the cache holds C1 until C2 is moved from the prefetch buffer into the frame upon a processor reference.
Sentence 2: predicting the last touch to C1 would allow replacing C1 by C2 in the corresponding block frame earlier.
Relationship: contrasting
Domain: Hardware
Sentence 1: The next step is to .nd out the actual move­ment range of a cell c. It is found by removing the parts of the displacement range that overlap with the critical bins.
Sentence 2: moving a cell within a fragmented movable range is running time expensive, we will only keep the part that overlaps with the cell s x-coordinate, while other disjointed parts will be discarded.
Relationship: contrasting
Domain: Hardware
Sentence 1: After the data transfer .nishes, according to the value of a speci.c bit in register MDIC, the device determines whether to .re an interrupt.
Sentence 2: static void set_mdic(E1000State *s, int index, uint32_t val) { ... ... s->mac_reg[MDIC] = val | E1000_MDIC_READY; set_ics(s, 0, E1000_ICR_MDAC); } Figure 4: Excerpt of e1000 virtual device Figure 4 shows how the virtual device responds un­der such the scenario by invoking the function set_MDIC.
Relationship: contrasting
Domain: Hardware
Sentence 1: As shown in Figure 3, we have PMIN(GOCSS(ex1)) = 10 under the clock skew schedule in which Thost = 0, TC1 = 5, TC2 = 5, TC3 = 5 and TC4 = 4.
Sentence 2: with an analysis to Figure 2, we find that the cycle consisting of S-edge es(host,R3) and S-edge es(R3,host) determines the lower bound of sequential timing optimization, and we have PB(ex1) = (11+Ts,3+1+Ts,host)/2= 7.
Relationship: contrasting
Domain: Hardware
Sentence 1: The TFET ST-1 SRAM shows improvement in the read-upset probability compared to the 8T TFET SRAM due to the use of the Schmitt-Feedback.
Sentence 2: due to its weak pull-up, the cell is still prone to variation-induced upsets, causing its VCC-min to be large compared to the CMOS SRAM cells.
Relationship: contrasting
Domain: Hardware
Sentence 1: In Figure 1 (a), existed bus-driven .oorplanning algorithms connect m3 and m5 by simply one vertical bus.
Sentence 2: by considering the actual positions of the bus pins in Figure 1 (b), the bus pins of these two modules may not be passed by only one vertical bus and the wirelength is much longer than the simpli.ed estimation.
Relationship: contrasting
Domain: Hardware
Sentence 1: (2), the objective can be written by: aknki .. M in xip · lp (3) i=1 p=1  4.2 Uni.ed Modeling for MPER By solving the previous problem, the median points for di.erential pairs and the shortest paths for pins to median points can be determined.
Sentence 2: the paths of median points to boundary cannot be guaranteed as all pairs com­pete for the limited routing resource, especially with single signals considered.
Relationship: contrasting
Domain: Hardware
Sentence 1: Finally, to avoid the price of direct-mapped organization, which is particularly high for page-based designs, Unison Cache is organized as set-associative, colocating all the pages of a set in the same DRAM row.
Sentence 2: instead of serializing tag and data accesses or fetching all the ways at the same time, Unison Cache relies on highly accurate way prediction, increasing neither the cache hit latency nor the amount of transferred data.
Relationship: contrasting
Domain: Hardware
Sentence 1: To achieve this, we invalidate the suitable dormant cache lines, i.e., we turn their valid bits o. if a su.ciently long time period has 1 Actually, we conducted experiments with all the bench­mark codes in the SPEC2000 suite.
Sentence 2: for the sake of clarity of graphs, we present only a subset of our results (i.e., for 12 bechmarks).
Relationship: contrasting
Domain: Hardware
Sentence 1: According to theorem 6, the steady state throughput of each guarded transition t must satisfy the following inequality: d(t)· T h(t)= .
Sentence 2: a(p)· m(p) p.t and each simple transition t must ful.ll: d(t)· T h(t)=m(p) for every preset place p. t. the average steady state marking m is neces­sarily a solution of the state equation: m = m0 +C· s, s=0 One can combine the above constraints on the throughput and on the average marking, to build a Linear Programming Problem (LP) that maximizes a parameter f, corresponding to the TGMG throughput (one scalar variable suf.ces since the throughput of all transitions is the same): Maximize f: d(t)· f= .
Relationship: contrasting
Domain: Hardware
Sentence 1: I1 I2 I3 I4 I5 I6 O1 Crossbar B I'1 O2 I'2 O3 I'3 Permutation Crossbar A O4 I'4 Crossbar O5 I'5 O6 I'6 defect-free matching whereas k2 defect-free crosspoints are needed for a biclique.
Sentence 2: figure 4 compares the yields of .nding a k × k biclique in an n × n UCB in the presence of switch open defects (up to 20% defect density) for various values of n and k. the probability of .nding a defect-free matching in a PCB (for any arbitrary k inputs to any arbitrary k outputs in an n × n PCB) is always 100% when up to 30% of switches are defective (open defects).
Relationship: contrasting
Domain: Hardware
Sentence 1: Furthermore, the average leakage decreases slowly for Tox > 17°goes be- A, and increases sharply as Tox low 17° A.
Sentence 2: the delay of the inverter (as will be seen by the experiment in Figure 2) increases linearly with Tox, so that using a value of ToxHi of over 17° Aresults in a larger delay with no appreciable savings in the leakage.
Relationship: contrasting
Domain: Hardware
Sentence 1: THE RATCHET ALGORITHM The previous section alludes to one possible algorithm for theoptimization of a disjunctive timing graph: generate every possiblesolution S, evaluate its cost, and return the best solution.
Sentence 2: when considering even moderately-sized problems, the computa­tional expense of this brute-force procedure may be prohibitivelyexpensive.
Relationship: contrasting
Domain: Hardware
Sentence 1: As seen in ef.cient manual RTL implementations of these algorithms, it is crucial to minimize the communication gran­ularity, pipeline the data-dependent blocks, and duplicate compute units to improve both throughput and latency.
Sentence 2: existing HLS tools fail to enable intra-block parallelization and inter-block pipelining when the data access patterns are complex [23, 17] and although advanced commercial tools support these optimiza­tions, they are not always able to ef.ciently identify the opportunity and transform source code to enable such optimizations.
Relationship: contrasting
Domain: Hardware
Sentence 1: mkPipelineFIFO method Action issue(UOP uop) p1.enq(uop) let r = Valid(p1..rst().read in()) rule stage1 when r w1 and r= w2 = let uop = p1..rst() uop = uop.read() p2.enq(uop) p1.deq() rule stage2 w1 := p2..rst().write in addr() p3.enq(p2..rst().add()) p2.deq() rule stage3 w2 := p3..rst().write in addr() p3..rst().write() p3.deq() (b) An example microarchitecture (Bluespec pseudocode) Figure 2: Architecture &#38; Microarchitecture (a)the logic fordecoding an instruction intoa µop sequence, (b)the encoding ofthe µop,(c)hardwareneeded tomuxthe right data to each resource, and (d) control needed to route each µop to the appropriate resources.
Sentence 2: microarchitectural control is visualized as if superimposed over the resource graph.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since the sensor nodes have no time synchronization with the beacon nodes, the absolute values of these times bear no useful in­formation.
Sentence 2: the time di.erence of arrivals can be t=0 BN-1 Received signal  time t11 t12 t13 (b) (a) Figure 3: (a) An example of multipath re.ections, and (b) corresponding signal received at SN from BN-1.
Relationship: contrasting
Domain: Hardware
Sentence 1: TABLE III COMPARISON OF YENSS VS MONTE CARLO FOR OSCILLATOR YIELD partial number of method accuracy yield HB simulations speedup Monte Carlo 10% 0.0976 40 Monte Carlo 1% 0.1190 2841 1×  YENSS 2 levels 1% 0.1235 24 118× 3 levels 0.2% 0.1252 45 63× 4 levels 0.1% 0.1261 106 27× 5 levels <0.1% 0.1266 323 9× Finally, we consider the variability of the threshold voltages of all six MOS transistors in the ring oscillator, and calculate the partial yield, In this example, we sample 105 points using Monte-Carlo method, but only 103 points lie in the acceptable region, which makes it extremely inaccurate, and meanwhile takes too much time.
Sentence 2: 3 iterations of YENSS takes 362 seconds, and get the partial yield 0.0759%, which has a much better accuracy than Monte-Carlo.
Relationship: contrasting
Domain: Hardware
Sentence 1: 2.2 TDoA Techniques and Systems Time-difference-of-arrival systems require both speed of light (RF) and speed of sound (ultrasonic) hardware fron­tends, but provide an order of magnitude improvement in ranging accuracy over pure RF systems.
Sentence 2: they are susceptible to obstacle interference, since ultrasonic signals do not propagate through most physical objects.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the weighted degree of node .. approaches one, it indicates that node .. has only one dominant edge.On the other hand, if the weighted degree of node .. approaches four, it indicates that node .. has four equally critical edges.
Sentence 2: 4.2 Iterative Critical Node Selection In [5], an e.cient method was proposed to .nd the crit­ical nodes in a spanning-tree support graph based on the weighted degree of each node in the graph, such that the ultra-sparsi.er support graph can be subsequently built by adding extra edges to these nodes.For example, if a node has a weighed degree that is greater than a user-de.ned threshold value, the node is considered critical and sub­sequently selected for adding edges.in [5], the threshold value is determined empirically for handling the mesh-structured circuits.As a result, it still remains chal­lenging to measure the quality of the resultant ultra-sparsi.er support graph for a given threshold value.
Relationship: contrasting
Domain: Hardware
Sentence 1: Another possible approach, borrowed from a different scenario, [18] relies on adaptive techniques, designed to simultaneously estimate both the position and the statistical signal model.
Sentence 2: we also are improving the Bayesian filtering stage by using both Multiple Hypothesis Tracking (MHT), [19] and the Interacting Multiple Model (IMM) approach,[11] in order to take into account possible changes in the kinematic model (e.g.
Relationship: contrasting
Domain: Hardware
Sentence 1: CONCLUSIONS Asynchronous microengines are an attractive design alter­native for the realization of high-performance application­speci.c programmable controllers.
Sentence 2: because of the requirements imposed by the asynchronous design paradigm, using existing standard cell libraries for the ASIC imple­mentation of asynchronous microengines proves to be rel­atively complex and time consuming, and results in larger and slower systems than necessary.
Relationship: contrasting