sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Nevertheless, wirelength minimization is still taken into account but in a biased man­ner; that is, whenever a feasible candidate .oorplan is gen­erated, wirelength minimization becomes meaningful and thus its wirelength will be computed and used for decid­ing whether the candidate .oorplan should replace the best .oorplan or not.
Sentence 2: unnecessary wirelength calcula- 2QO RQH VZDS +RW%ORFN &#38;ROG%ORFN &#38;ROG%ORFN +RW%ORFN D   2QO RQH VZDS +RW%ORFN &#38;ROG%ORFN &#38;ROG%ORFN +RW%ORFN E 7ZR URWDWHV DQG RQH VZDS  +RW%ORFN &#38;ROG%ORFN &#38;ROG%ORFN +RW%ORFN F  Figure 5: (a) and (b) Only swap the two blocks.
Relationship: reasoning
Domain: Hardware
Sentence 1: In this paper, interconnect wires are modeled as a distributed RC network and we adopt the Elmore delay model.
Sentence 2: an interconnect w is annotated by the corresponding resistance R(w)and capacitance C(w).A buffer bi in the buffer library is de.ned by its load capaci­tance C(bi), intrinsic delay T (bi)and output resistance R(bi), while W (bi) represents the buffer cost which can be either buffer area or power.
Relationship: reasoning
Domain: Hardware
Sentence 1: In order to estimate the blocking length (Bdest ) and the waiting time (Wdest ) per .it at the input of the destination node, we can consider only the contention probability without considering the buffer full probability at the next node.
Sentence 2: equations 16, 15, 18 and 19 can be changed to Pcon Pc .dest = )(1-Pc) Phold dest (r)= (1 -.dest ).r+1 dest (1-Pcon PD 1 .dest Bdest = rPhold dest (r) Wdest = r=1 (1-Pcon )(1-Pc) 1-.dest Now, we have all the parameters to estimate the average latency using Equation 3.
Relationship: reasoning
Domain: Hardware
Sentence 1: Once the temperature of the processor reaches the initial trigger temperature, the thermal manager is awakened to consider the conditions and issue a thermal management decision (i.e., a system state-changing command), ensuring that the critical temperature threshold is not exceeded.
Sentence 2: the CTMDP model of the chip temperature includes a set of temperature states H = {h1, h2, , hc, hc+1} and a generator matrix Gtemp, where c+1 is the number of states that are possible with a thermal sensor.
Relationship: reasoning
Domain: Hardware
Sentence 1: pTcoh.ß x (x) (15)+ p6fd,k,span-i = Doppler step of 250 Hz in the acquisition s search-space leads a2 · exp1+erf 2a3   to the maximum residual carrier frequency o.set of |125|Hz.
Sentence 2: in the worst case (i.e.
Relationship: reasoning
Domain: Hardware
Sentence 1: The latencies of way locator lookup are smaller than those associated with looking up large SRAM tag stores [5] (6 cycles for 1MB, 7 for 2MB and 9 cycles for 4MB in CACTII 22nm).
Sentence 2: while the techniques employed in the Bi-Modal Cache are well-known, they are orchestrated in an effective manner to design a .exible DRAM cache organization that achieves signi.cant performance and that can continue to bene.t with scaling DRAM cache size.
Relationship: reasoning
Domain: Hardware
Sentence 1: In our case, this length is the same as the minimum global wire length.
Sentence 2: for a wire of length l, the number of repeaters on that wire is: 0, if l < l crossover nrepeater(l) = (2) rC ow (4) Where, Sopt =0.58 RC w nmos and Cnmos = Cg(2. )
Relationship: reasoning
Domain: Hardware
Sentence 1: QUANTITATIVE ANALYSIS The goal of this section is to study the bene.t of the multi­channel communications of the Split Phase Approach (SPA) in terms of the network throughput with respect to the sin­gle channel MAC protocol IEEE 802.11 DCF (Distributed Coordination Function) [15].
Sentence 2: we consider two STPN compact models: (i) Model1: the compact model of the SPA described in the .gure 8.
Relationship: reasoning
Domain: Hardware
Sentence 1: due to its exponential dependency on the threshold voltage, and the subthreshold leakage current is smaller in a footer than in a header due to the smaller size of a footer with the same delay penalty.
Sentence 2: a footer is superior to a header in terms of its 0.90 own leakage current as well as in terms of input gate leakage (Vdd ) current.
Relationship: reasoning
Domain: Hardware
Sentence 1: On the other hand, considering the high design and debugging cost of using FPGAs, we ar­gue that it is not a cost e.ective way to implement some kernels of EMAN on FPGAs, such as 3D-FFTs, heuristic particle selection and etc.
Sentence 2: theperformanceof the FPGA-based accelerator will be dictated to a large extent by the ability to evaluate, extract and o.oad the most ben­e.cial parts of the application.
Relationship: reasoning
Domain: Hardware
Sentence 1: Given any type T , UT.Tqa yields an im­plementation of Tqa, the query-abortable counterpart of T .To de­scribe UT.Tqa , we .rst prove that every type T has a queriable counterpart Tq such that Tqa =(Tq)a, i.e., Tqa is the abortable counterpart of Tq.
Sentence 2: given any type T (with an associated APPLYT procedure) we can derive an implementation of Tqa in two steps: (a) we .rst use the given APPLYT procedure to derive an APPLYTq procedure for type Tq, and (b) we then use APPLYTq in any universal construction for abortable types, such as UT.Ta described in Section 5.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since ui((ci,R i),(c-i,R-i)) = w(1 -a)Ri.i(R i,R-i)-ci < w(1 -a)Ri.i(Rfi ,R-i)-ci = ui((ci,Rfi ),(c-i,R-i)), player i will gain more utility if it reports a false trans­ f mission rate Rrather than Ri.
Sentence 2: truthfully i following the protocol is not a NE.
Relationship: reasoning
Domain: Hardware
Sentence 1: Verifying that a protocol is correct and deadlock- and livelock-free entails checking that all reachable system states are valid (e.g., only a single writing core at a time).
Sentence 2: as the number of system components (e.g., caches) and the complexity of the protocols increase, both the number of reachable system states and the number of interleavings among protocol actions increase exponentially (i.e., the state space explosion problem).
Relationship: reasoning
Domain: Hardware
Sentence 1: We express this as: Va =max A-1Hi (9) i.V(IF ) where V(IF ) denotes the set of vertices of IF .
Sentence 2: va can be computed in two steps: 1) Solve A-1Hi at all vertices of IF and let S be the set of solution vectors 2) Va(j)is the maximum value of the jth component of all vectors in S. Alone, however, this procedure is insu.cient, since the number of vertices in IF may be too large [4].
Relationship: reasoning
Domain: Hardware
Sentence 1: Contrary to the case in an SP-Domino gate where the pull-up device has to be adequately sized to charge the large capacitance on the dynamic node, most of MP1 s initial current drive will be utilized to quickly charge up the much smaller capacitance on DYN1 as the current drained by the isolation transistor MN1 would be limited by its near-zero drain-to-source voltage.
Sentence 2: the sizing  Figure 6: Simulated waveforms of a SSPD 16-bit dynamic multiplexer.
Relationship: reasoning
Domain: Hardware
Sentence 1: If either G ' 2 or G ' 3 is not the minimum restricted pre.x graph, a smaller pre­.x graph for G ' 1 can be obtained by substituting G ' 2 or G ' 3 to the minimum one, which con.icts with the assumption that G ' 1 is minimum.
Sentence 2: both G ' 2 and G3 ' should be the minimum restricted pre.x graphs and the principle of optimality holds.
Relationship: reasoning
Domain: Hardware
Sentence 1: In [28] a low energy MPEG-4 FGS streaming [29] policy us­ing a client-feedback method is presented, where the client decod­ing aptitude in each timeslot is communicated to the server, and the server subsequently determines the additional amount of data in the form of enhancement layers on top of the MPEG-4 base layer.
Sentence 2: the server adjusts its data rate based on the feedback val­ue from the client.
Relationship: reasoning
Domain: Hardware
Sentence 1: MEMORY BANDWIDTH VERSUS PIN COUNT IN INDUSTRY-STANDARD MEMORY INTERFACES peak, available The peak available memory bandwidth, Bmem , for a pro­cessor, is a function of the memory bus clock (fmem), the number of bits on the memory bus (Nmembits), and the number of on-chip memory controllers (NMC): peak, available Bmem = fmem · Nmembits · NMC.
Sentence 2: (1) for example, a single JEDEC DDR3-2133 standard memory, having a bus clock of 1066 MHz DDR clock (double-data-rate fmem = 2133 MHz), and 64-bit transfers(Nmembits = 64), the peak available bandwidth is 17.06 GB/s.
Relationship: reasoning
Domain: Hardware
Sentence 1: Lemmas 1 and 2 (equations 8-9) indicate that the nodes visit ratio and the forwarding probabilities averaged over all possible instances of the topologies are similar to the visit ratios and forwarding prob­abilities of an average topology where each node has a number of neighbors equal to the average case.
Sentence 2: as a result of these two lemmas, one may derive the remaining set of model parameters (ef­fective packet arrival rate and number of packets traversed) by con­sidering the average case topology.
Relationship: reasoning
Domain: Hardware
Sentence 1: If the input switches from 0000 -0101 at time t = 0: output i will switch at times t =6, 11; j at t =9, 12; k at t =8, 10; and l at t =7, 12.
Sentence 2: the left side will be faster for the left output (i switches before k), while the right side will be faster for the right (l switches before j).
Relationship: reasoning
Domain: Hardware
Sentence 1: Here, we use a simple naming convention for these functions based on where they are executed: SW (software) and HW (hardware) functions.
Sentence 2: rD_IMGS, GET_LABEL, and WR_DISP belong to SW functions since they are mapped to be executed in the host processor, and COM_COST and STRM_TRWS belong to HW functions for their implementation on FPGAs.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, functional memory simulation is not appropri­ate to exploit parallelism, that is, parallel or pipelined mem-ory architectures.
Sentence 2: once a processor/memory ar­chitecture is found that roughly meets the initial design cri­teria, the model can be re.ned to a cycle-accurate model, which is used to collect the desired pro.ling data of the mi­croarchitecture.
Relationship: reasoning
Domain: Hardware
Sentence 1: (6) i=1 To solve this optimization problem, the conductance matrix G, with GV = I, needs to be known according to Equation (1).
Sentence 2: we use the following equations to express the conductance for each possible TSV position i: gtsvi = g1xi1 + g2xi2+... + gnxin (i = 1, 2, ...M ) xi1 + xi2+... + xin = 1 (7) xi .
Relationship: reasoning
Domain: Hardware
Sentence 1: registers (RT ) page size 25 µs 80 µs 200 µs 3 µs 2KB command signal latency (C) 3 cycles Table 2: Parameters in virtual device simulation cycles (RT ).
Sentence 2: we can .nally formulate page mode read­/write access times of NAND .ash memory in page mode, as shown in Table 1.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that the battery is not the only contributor to the weight, the current single channel prototype weighs approx­imately 30 to 40 g. However, using off-the-shelf components, a single channel system including the ampli.ers could be reduced to 10 g, which is the weight of the EZ430-RF2500.
Sentence 2: reducing the number of channels will also reduce overall device weight.
Relationship: reasoning
Domain: Hardware
Sentence 1: (42) v (b)1+ 2 <.< 4  For this category, Z(s) has complex poles and decreases monotonically with frequency.
Sentence 2: zmax = R.As in section 4.2, the maximum worst-case voltage noise can be calculated and the ratio is V 1 -1 (s)tan 1 e .
Relationship: reasoning
Domain: Hardware
Sentence 1: (17): .perf = a · Hhit + ß · Nhit (17) where a and ß are user de.ned weights, Hhit is the hotspot detection accuracy and Nhit is the non-hotspot detection accuracy.
Sentence 2: .perf represents the weighed summa­tion of hotspot and non-hotspot detection accuracies.
Relationship: reasoning
Domain: Hardware
Sentence 1: Under the assumption of the path delays being random vari­ables, the a-percentile of a path delay can be written as za[Dp] = µ(Dp) + zas(Dp) 1 2 the optimal solution does not lie in the new feasible region.
Sentence 2: this transformation results in considerable reduction in the complexity at the cost of slight degradation in the quality of the solution.
Relationship: reasoning
Domain: Hardware
Sentence 1: 1) Error Accumulation: The error signals can be summed up using accurate adders and thus, the accumulated error can fully compensate the inaccurate product; however to reduce complexity, an approximate error accumulation is introduced.
Sentence 2: consider the observation that the error vector of each approx­imate adder tends to have more 0 s than 1 s. the probability that the error vectors have an error bit 1 at the same position, is quite small.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since GNRs may have a low subband, the approximation is not always accurate.
Sentence 2: we need to derive an expression valid for all possible E. Since (3) cannot be solved directly, we approximate f(E) with an exponential function when EF < EC = 0, a step function when EF - EC > 3kT , and a smoothing function in between.
Relationship: reasoning
Domain: Hardware
Sentence 1: 6, the coupling energy (of the ground state), Ei,j , is an increasing function of |Cyy,i.j |(and |Cyy,j.i|) of the con.icts related to the hotspots.
Sentence 2: increasing |Cyy,i.j | (and |Cyy,j.i|) of the con.icts related to the hotspots increases the coupling energy of the con.icts related to the hotspots.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3.2.2 Generating Points of DP-curves with Level Shifters To calculate the accumulated delay di and power .i of ablock bi, including the delay and power of bi, we need to simultaneously consider the contribution of delay and power from level shifters.
Sentence 2: di and .i are calculated by di = di + di + xij · ds, (6) and .i = .i + pi + xij · ps, (7) where xij is a 0-1 variable indicating whether a level shifter is needed from block j to block i (1 if needed; 0, otherwise), di (pi) is the delay (power) of bi,and ds (ps) is the delay (power) of a level shifter.
Relationship: reasoning
Domain: Hardware
Sentence 1: Type Speci.cation 1 Ascend stair step 45 stairs/min 2 Ascend stair step 60 stairs/min 3 Ascend stair step 75 stairs/min 4 Walk on treadmill 3 miles/hour, incline: 0% 5 Walk on treadmill 3 miles/hour, incline: 1.5% 6 Walk on treadmill 3 miles/hour, incline: 3% 7 Walk on treadmill 4 miles/hour, incline: 0% 8 Walk on treadmill 4 miles/hour, incline: 1.5% 9 Walk on treadmill 4 miles/hour, incline: 3% 10 Run on treadmill 6 miles/hour, incline: 0% 11 Run on treadmill 6 miles/hour, incline: 1.5% 12 Run on treadmill 6 miles/hour, incline: 3% tion while the proposed architecture is worn on-body was not feasible due to the cost prohibitive issues.
Sentence 2: we synthesized the proposed architecture using CAD tools and measured the power consumption of individual screen­ing blocks.
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, assuming the IC surface is divided into an m× n grid, the total leakagepower of the processor is calculatedby: mn we use our sensory circuit to measure), and the information Pleakage = ·· N[i,j] Ileakage[i,j] Vdd regarding heat dissipation in the corresponding temperature i=1 j=1 range for cooling down, which can be precisely calculated based on the Newton s law of cooling.
Sentence 2: r can be where N[i,j] and Ileakage[i,j] denote the number of gates and the leakage current in each block of the grid.
Relationship: reasoning
Domain: Hardware
Sentence 1: Cg = Cgi +2 × COL (3) COL = W × CGDO (4) if VS-D =0 then, Cgi = W×L×Cox Cg,0 = W×L×Cox+2×W × CGDO (5) if VS-D = VDD then, Cgi = W×L×Cd Cg,V DD = W×L×Cd+2×W × CGDO (6) Cmax CR = (7) Cmin Since, Cmax = Cg,0 (8) and, Cmin = Cg,V DD (9) CR = Cg,0 (10) Cg,V DD CR = L× Cox+ 2 × CGDO (11) L× Cd+ 2 × CGDO  Once the comparison starts with the given models, the ca­pacitance change will not a.ect the circuit s decision due to cross-coupled inverters in the VcTL gate.
Sentence 2: these capacitance changes are not modeled.
Relationship: reasoning
Domain: Hardware
Sentence 1: (Recall that the fortuitous detection of defects given the detection of a targeted fault is analogous to the detection of a non­targeted fault given the detection of a targeted fault).
Sentence 2: for our experiments, we can consider two defect spaces: a defect space in which all defects correspond to stuck-at faults, and a defect space in which all defects correspond to the more difficult-to-detect transition faults.
Relationship: reasoning
Domain: Hardware
Sentence 1: We were able to use a fast functional simulator (sim-profile)because obtaining the profile does not require a cycle-accurate sim­ulation.
Sentence 2: furthermore, the profile information only needs to be col­lected once (unless the application or processor core is changed).the simulator s runtime was sufficiently fast for ourpurposes (profile simulations took less than 25 minutes per bench­mark to complete.)
Relationship: reasoning
Domain: Hardware
Sentence 1: Note also that the presence of higher harmonicsin the input, together with corresponding harmonics in theoscillator s PPV, facilitate mth sub-harmonic lock indicatingthat nonlinearity is useful for SHIL.
Sentence 2: the Adlerized SHILequation (20), together with computational tools for determiningthe PPV s harmonics [17], provides concrete design guidelinesfor utilizing SHIL.
Relationship: reasoning
Domain: Hardware
Sentence 1: Symbolic execution is a well-known technique [21] that has traditionally been employed for testing pur­poses, which consists in executing the algorithm by propagating symbolic expressions rather than the actual values of the variables.
Sentence 2: after executing the algorithm from iteration i to i + m, the output is not the numeric value of fi+m, but a set of equations that relate each element of fi+m to a subset of elements of fi.
Relationship: reasoning
Domain: Hardware
Sentence 1: 1. r X(, ) () ij X(, ) X cij i j , 1,...,16 (1) ij (, ) , Additionally, because of Dependency (b), the HT and IDCT com­putations have to stall until the coefficients from the AC path and the DC path are available, respectively.
Sentence 2: our novel contribution proposes an AC/DC-path decoupling scheme that overcomes this dependency while still being correct.
Relationship: reasoning
Domain: Hardware
Sentence 1: 2.3 RF-MOST modelling At the start of the design, no RF-models for the MOS­transistors were available.
Sentence 2: a transistor subcircuit has been constructed using the following approach ([9]): From the available BSIM3-models an intrinsic MOST model is derived by setting all junction-areas to zero;  The junctions are added as diodes in the RF-MOST subcircuit, resulting in higher accuracy of the junction capacitor values for low .nger numbers;  Source, drain and substrate resistors are added to the subcircuit;  A layout-related coupling capacitor between source and drain is added;  A physical gate resistance is added.
Relationship: reasoning
Domain: Hardware
Sentence 1: Itis alsoworth noting thatinconventionalcustomcircuit design, optimizationfrequently takestheform ofminimizing the area subject to a delay constraint.
Sentence 2: such a form is not as useful for FPGA-based optimization again because the performanceoftheFPGAisnotknownuntilusercircuits are implemented ontheFPGA.theabsolutevalueof any delay constraint would not be informative.
Relationship: reasoning
Domain: Hardware
Sentence 1: Compared with un-terminated scheme (as shown in Figure 3(a)), resistive termination im­proves the bandwidth by alleviating the ISI, but lowers the swing of output signal and adds power consumption in the termination.
Sentence 2: a non-tapered inverter chain (as shown in Figure 3(b)) is devised to amplify the received signal and recover it back to digital level.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3.3 Delay Elements From equation (4) and Figure 6, one can see that increasing the transparency window of the i th soft-edge FF-set puts more rigid constraint on the hold time condition for the i th stage of the pipeline.
Sentence 2: if needed, delay elements may be utilized in the minimum-delay path(s) to alleviate the hold time constraint violation.
Relationship: reasoning
Domain: Hardware
Sentence 1: During the search all problems are feasible except the last one.
Sentence 2: note that the constraints corresponding to total_leakage <= C -1 are tighter than the ones corresponding to total_leakage <= C.every solution of iteration i+1 is a solution of iteration i.In every iteration, the SAT solver produces many conflict clauses during the search for the answer.3 We use this fact to speedup the search by using the conflict clauses that are generated during the ith iteration and adding new clauses to them to model the (i+1)th iteration.
Relationship: reasoning
Domain: Hardware
Sentence 1: N, ifa K-LUT t ' is generated for t during the mapping phase, then the level of t ' in the mapping solution is no more than g(t) and l(t), the depth of the optimal mapping solution for Nt.
Sentence 2: since any mapping solution for N induces a solution for Nt, g(t) and l(t) are also the minimum depths for the K-LUT generated for t in and mapping solution of N. the mapping solution of N is optimal and requires O(n + m) time [2].
Relationship: reasoning
Domain: Hardware
Sentence 1: 8C-1 AVS-Aware Power-Gate Sizing for Maximum Performance and Power Efficiency of Power-Constrained Processors Abhishek Sinkar and Nam Sung Kim Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI 53705 e-mail: sinkar@wisc.edu Abstract -Power-gating devices incur a small amount of voltage drop across them when they are on in active mode, degrading the maximum frequency of processors.
Sentence 2: large power-gat­ing devices are often implemented to minimize the drop (thus the frequency degradation), requiring considerable die area.
Relationship: reasoning
Domain: Hardware
Sentence 1: In addition, the twofigures-of-merit (FOMs) commonly employed to evaluate the modulator Power W performance are also included; namely, FOM1 Power W() 2DR bit()2BW Hz()· --­---­---­---­--­---­---­---­---­--­---­---­-­-1012·= (1) FOM2 2kT 322DR bit()2BW Hz()··---­---­--­---­---­---­--­---­---­---­---­--­---­---­---­- ·= (2) () Note that FOM1 specially accountsfor the power con­sumption, whereasFOM2 stresses on the modulator reso­lution.
Sentence 2: the smaller FOM1 and the larger FOM2 , the better performance of the S.modulator.
Relationship: reasoning
Domain: Hardware
Sentence 1: The Cake is a Lie: Privilege Rings as a Policy Resource Sergey Bratus, Peter C. Johnson, Michael E. Locasto Ashwin Ramaswamy, Sean W. Smith Department of Computer Science Computer Science Department George Mason University Dartmouth College Fairfax, VA, USA Hanover, NH, USA mlocasto@gmu.edu {sergey,pete,ashwinr,sws}@cs.dartmouth.edu  ABSTRACT Components of commodity OS kernels typically execute at the same privilege level.
Sentence 2: the compromise of even a single component undermines the trustworthiness of the entire kernel and its ability to enforce separation be­tween user-level processes.
Relationship: reasoning
Domain: Hardware
Sentence 1: 2.1 Addressing Cache Pollution Observation:Ifacacheblockwithhighreuseisprema­turelyevictedfromthecache,thenitwilllikelybeaccessed soonaftereviction.Ontheotherhand,acacheblockwith littleornoreusewilllikelynotbeaccessedforalongtime aftereviction.
Sentence 2: theaboveobservationindicatesthattodistinguishblockswith highreusefromthosewithlowreuse,itissufficienttokeeptrack ofasetofrecentlyevictedblocks.Basedonthis,ourmechanism augmentsacachewithastructurethattrackstheaddressesofre-centlyevictedblocksinaFIFOmanner.Wecallthisstructurethe Evicted-AddressFilter(EAF).Onacachemiss,ifthemissedblock addressispresentintheEAF,itislikelythattheblockwaspre­maturelyevictedfromthecache.thecachepredictsthe blocktohavehighreuse.Ontheotherhand,ifthemissedblock addressisnotpresentintheEAF,theneithertheblockisaccessed forthefirsttimeoritwasevictedfromthecachealongtimeago.
Relationship: reasoning