sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: The layout of the SFC diagram of Figure 1 is such that, for any given step or transition, membership of one these modes is represented as membership of an identi.able region of the graph (one of the regions N , A or F above).
Sentence 2: a conceptual aspect of the artifact (membership of some behavioural mode) is directly captured by a rep­resenting relation in the diagram with matching logical properties (membership of a spatial region in the plane).
Relationship: reasoning
Domain: Hardware
Sentence 1: Optimiza­tion re-weights each spring, thus changing the placement of the control points after a standard quadratic placement solve.
Sentence 2: an outer nonlinear optimization loop adjusts the weights on the edges, while an inner quadratic loop solves for the locations of the control points after each weight perturbation, and computes the appropriate gate location changes under some as-yet-to-be-described warping transformation.
Relationship: reasoning
Domain: Hardware
Sentence 1: This result is not a surprise when we consider that just 18% of dynamic instructions are loads and 23% are dictor does not incur performance degradation in vortex and stores.
Sentence 2: even though the load buffer removes the searches required for detecting a load-load order violation from the queue, the load queue still has a signi.cant number Table 3 shows the accuracy of our store-load pair predic­of searches from stores for detecting store-load order viola­ tion.
Relationship: reasoning
Domain: Hardware
Sentence 1: Notethat,incontrasttothemostofthepreviousworkin reuseanalysis(e.g.,[12]),thisapproachissimpleandcom­putesreuseinformationwithoutsolvingasystemofequations.
Sentence 2: 4.4 Simulating the Footprints of Reuse Spaces Thenextstepinourapproachistotransformthosedata reusesintorealdatalocalities.Astraightforwardideaisto makethedatacachelargeenoughtoholdallthedatainthese reusespacesofthearrays.Notethatdatawhichareoutof reusespacesarenotnecessarytobekeptincacheafterthe frstreferencesincethereisnoreuseforthosedata.Asdis­cussedearlier,thecacheinterferencescansignifcantlyafect theoverallperformanceofanest.theobjectiveofour techniqueistofndanear-optimalcacheconfguration,which canreduceoreliminatethemajorityofthecacheinterferences withinanest.Aninformaldefnitionofanear-optimalcache confgurationisasfollows: Definition1.Anear-optimalcacheconfgurationisthe possiblysmallestcacheinsizeandassociativitywhichachieves anear-optimalnumberofcachemisses.And,anyincreasein eithercachesizeorassociativityoverthisconfgurationdoes notdeliverfurthersignifcantimprovement.
Relationship: reasoning
Domain: Hardware
Sentence 1: Both MAX and AVG incur a signi.cant percentage of synchronization slowdowns.
Sentence 2: if the individual thread slowdown estimation does   SUM W/O EM MAX AVG 1.4 1.2  normalized execution time 1 0.8 0.6 0.4 0.2 0 (a) Performance (b) Energy (c) Lock contention (d) Synchronization slowdown Figure 3: Extending the previous synchronization-oblivious performance guaranteeing scheme with the three slowdown aggregation methods (with 10% slowdown limit).
Relationship: reasoning
Domain: Hardware
Sentence 1: The total execution time for this mapping is 7 cycles since the data from Op2 takes 1 cycle to reach Op4 and data from Op4 takes 1 more cycle to reach Op6.
Sentence 2: we have to take the data communication overheads /* Schedules operations in basic block currBB */ ScheduleBB(currBB, PE List , currCycle) 1: A .
Relationship: reasoning
Domain: Hardware
Sentence 1: That is, the signal propagation to this common point is identical for both clock and data, and thus does not warrant any early-late split.
Sentence 2: the credit for a hold test with one data path dp sharing a sub-path with clock path cp is: H old L E C (dp)= at (C P )-at (C P ), (15) where C P is the point when cp and dp diverge (Figure 4).
Relationship: reasoning
Domain: Hardware
Sentence 1: These are respectively the set of events which a method mEMavailable to a connection eEEcan be set in waiting for, and the set of events it can raise.
Sentence 2: the rate of Explicit Synchronization ESyn(xNy), xNyE(ENM)between two connection method pairs is de.ned as ESyn(xNy)=Iset(x)nsset(y)I Note that ESyn(xNy)=ESyn(yNx).
Relationship: reasoning
Domain: Hardware
Sentence 1: Concept and Design of a Cognitive Radio Prototyping Platform Christian Kocks Alexander Viessmann Andrey Skrebtsov Department of Communication Department of Communication Department of Communication Technologies Technologies Technologies University of Duisburg-Essen University of Duisburg-Essen University of Duisburg-Essen Duisburg, Germany Duisburg, Germany Duisburg, Germany info@kommunikationstechnik.org info@kommunikationstechnik.org info@kommunikationstechnik.org Guido H. Bruck Department of Communication Technologies University of Duisburg-Essen Duisburg, Germany info@kommunikationstechnik.org ABSTRACT The increasing demand for higher data rates in communi­cation systems requires an e.cient utilization of the limited frequency spectrum resource.
Sentence 2: cognitive radio as­pects are of utmost interest.
Relationship: reasoning
Domain: Hardware
Sentence 1: 2(n-1)^2 links with 3-bit width and v2a average length for transferring congestion status from agents to local routers (diagonal links).
Sentence 2: the total wiring overhead of CATRA method is: OverheadCATRA = 4(n)(n-1)a + 12(n-1)(n-2)a + 2((n-1)^2)(v2a) + 6((n-1)^2)(v2a) On top of that, in n×n mesh network, given a channel width of 128 bits [14][15], the wiring requirements for transmitting data packets is: OverheadDataPackets =2×128×(n)(n-1)a .
Relationship: reasoning
Domain: Hardware
Sentence 1: Crossbar and MUX/DEMUX Faults: In the proposed RoCo router architecture, a decoder (DEMUX) is used to guide a .it into a group of path-sensitive queues, and a mul­tiplexer (MUX) is used to direct a winning .it to the cross­bar input.
Sentence 2: the MUXes and DEMUXes all lie on Figure 7.
Relationship: reasoning
Domain: Hardware
Sentence 1: As showninFigure8, whenprocessingmultipletime steps, for each extratime stepprocessed, we need an extralayer of halo.
Sentence 2: to process three time steps in one pass, for a decomposed block of size nx × ny × n, we need to stream in nx × ny × n points toget(nx - 6d)× (ny - 6d)× n results (d denotes the number of points on each side of the center point of the stencil).
Relationship: reasoning
Domain: Hardware
Sentence 1: The increase in average delay comes from the fact that the tra.c to or from some nodes, other than those on thebound­ary,inaspeci.cpartition needs morehopstoreachthe desti­nation nodes in other partitions.
Sentence 2: minimizing the inter-partition tra.cbyusing ASNoC-FM makes the in­creasein theaverage delayminimum.
Relationship: reasoning
Domain: Hardware
Sentence 1: If T m is a Monte Carlo estimate of Tm obtained using Nmc simula­ tions, then it is easy to show [10] that Tm is distributed as N (Tm, s2 ) with variance mc 2 smc = Tm(1 - Tm)/Nmc.
Sentence 2: (3) Tm is contained with con.dence 100 · (1 - a)% within the interval i i i i = Pr{.
Relationship: reasoning
Domain: Hardware
Sentence 1: Introduction Even for well-tested deployed systems, undetected errors may lead to catastrophic failures similar to the failures of Therac-25 de­vice [18] and Ariane 5 .ight [19].
Sentence 2: safety-critical embed­ded systems typically used in medical, nuclear, and automotive do­mains require compliance with standards that recommend the use of software monitors to detect anomalies in the development and production phases (e.g., ISO-26262 [7] for automotive functional safety and DO-178C [8] for airborne systems).
Relationship: reasoning
Domain: Hardware
Sentence 1: Now the number of substrings of length W that have precisely k l's is given by (~).
Sentence 2: assuming W to be even, and using elementary combinatorics, the average transition activity per word for a bitline is therefore given by, W w W -k + 1) x (~) Ek~=o k x (kw) + Ek=~+l( T W+l r W = 2w ,  Y_-o x + Ego' + x 214, , ----W W  :12w × (7::)+ 1 + T × 2 W (w + a)2 W-' -"7' × 2 w there is a net reduction in switching activity over transmitting the uncoded bits.
Relationship: reasoning
Domain: Hardware
Sentence 1: For a given level j,a run of length tj is a sequence of run congested wavefronts based at times (t +1,...,t + tj ), run preceded by a non-congested wavefront based at time t.It is clear that the tj time steps during which an IP is queued in Qj must be part of a run, whence an upper bound on the length of any run is also an upper bound on the waiting time tj .
Sentence 2: we turn our attention to the length of a run.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3.4.3 Proof of Correctness We will now prove that, for each of the three cases under con­sideration, the raised hyperplane meets the criteria speci.ed in section 3.4.1.
Sentence 2: notice that, in all three cases, the raised hy­ (i) (i) perplane Dhas a constant term .= P,and .= 0, for i 0 j 1 = j = n. Recall also that the peak corner is at the origin Cp =(0,0,··· ,0), thus for each of these cases: Di (Cp)= .0 (i) = P (27) the raised hyperplane Di satis.es the third criterion of section 3.4.1 for all the three cases.
Relationship: reasoning
Domain: Hardware
Sentence 1: As soon as a mapper is suspected to be failing, a new map task will be delivered to replicate the failed one; 2. replicate intermediate data when there are intermedi­ate outputs that have already been validated (by the central server) and some of the mappers that reported these results take too long to answer to the central server probes.
Sentence 2: nodes might be used to repli­cate intermediate data to compensate other mappers that die while waiting for the reduce phase to start.
Relationship: reasoning
Domain: Hardware
Sentence 1: To simul­taneously minimizebothareaandrouting-induced parasiticsoncriti­cal current/signal paths, we shall generatetheplacement withmono­tonic current paths, asshown inFigure3(c), which has the following advantages: SmallerlayoutareacomparedwiththeplacementinFigure3(a);  Simpler routing topologies and shorter interconnecting wire­lengthforcriticalcurrent/signalpathscomparedwiththeplace­ment in Figure 3(c).
Sentence 2: the placement based on monotonic current paths re­sultsinlessrouting-inducedparasiticsoncriticalcurrent/signalpaths and better circuit performance.
Relationship: reasoning
Domain: Hardware
Sentence 1: In order to simplify WCET computation when studying pipelined processors, we want to guarantee hits or misses for each memory access.
Sentence 2: even if we know the memory addresses of the further memory accesses, the cache behavior cannot be predicted exactly; it may be that the unknown memory access has trashed the cache line we planned to reuse; it may be that it has actually brought the data we are going to access.
Relationship: reasoning
Domain: Hardware
Sentence 1: Essentially, leading-edge , real designs embody high-value intellectual property of their creators, and cannot be easily released; old or arti.cial benchmarks potentially drive CAD research in stale or wrong directions.
Sentence 2: when real benchmarks are released to the academic research community, their in.uence can be enormous, as was seen with the ISPD98 partitioning benchmark suite from IBM [2].
Relationship: reasoning
Domain: Hardware
Sentence 1: The result would be a speedup of n for RAID 10, m a speedup of 1 for RAID 1 (since n = m), and a speedup of n for RAID 0 (due to m = 1).
Sentence 2: the speedup factor, which arises when w is growing due to an increased spare capacity, should equal to that of a single SSD.
Relationship: reasoning
Domain: Hardware
Sentence 1: External servers can authenticate with the system using an open, webservice API in order to request layers of data either contained or referenced by the system (in KML/KMZ, ArcGIS, image, or other defined formats), and provide new layers and/or services to the system in a publish/subscribe model.
Sentence 2: the system described here is really a federated system for data sharing, processing, modeling/simulation, and visualization.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, the U-SVL and L-SVL circuits respectively generate a slightly lower supply voltage VD (=VDD-vn<VDD) and a relatively higher ground-level voltage VS (=vp>0V), where vn and vp are the total voltage drops of all nRSm and all pRSm, respectively.
Sentence 2: the back-gate biases (VBGs) {i.e., source voltages (Vs)} of both the cut-off pMOSFETs and the nMOSFETs in the stand-by load circuit are increased and are given by vn and -vp, respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that, the access frequencies of the blocks have changed; specif­ically b4 and b7 are accessed 184 times; b5 and b6 are accessed 200 times; and others are accessed between 21 and 25 times.
Sentence 2: b4, b5, b6 and b7 are mapped to SPM1, SPM2, SPM3 and SPM4, respectively, as can be observed in Figure 3.
Relationship: reasoning
Domain: Hardware
Sentence 1: For example, in cases where our .ow fails to reduce cost G0 .I R to Gopt opt = w* G0 , design quality in terms of IR-drop reduction .I R .I R .I R is not ensured.
Sentence 2: additional PG-TSV sites are required, and the .oorplanner is recon.gured to increase deadspace.
Relationship: reasoning
Domain: Hardware
Sentence 1: Moreover, due to routing congestions, the number of available TSVs for Power/Ground (P/G) nets is limited.
Sentence 2: it becomes a challenging task to deliver enough current to all parts of the 3D stack while guaranteeing high power integrity for the stable operation of 3D-ICs, i.e., low voltage drop in DC components (IR-drop) and low voltage .uctuation in AC components (Ldi/dt).
Relationship: reasoning
Domain: Hardware
Sentence 1: In order to enable quick access to each sub-function, only a restricted segmentation of the original function is allowed.
Sentence 2: each sub-function segment must ful.ll B - A seg(k) = seg(k - 1) + , (9) 2hk with A, B as start and end point of the function, seg as sub­function start point, k as segment index (seg(0) = A) and hk .
Relationship: reasoning
Domain: Hardware
Sentence 1: Examining the set of vertices {v, e,f,g, h, u}, it is easy to be convinced that whatever is the color assignment adopted for such vertices, the colors f(u) and f(v) must be assigned to two adjacent vertices among {v, e, f, g, h, u}.
Sentence 2: namely, f(u) and f(v) must appear in one of the following pair of vertices: u and h, or v and e, or f and g. one further dummy edge between vertices u and v must__be added to M, as shown in Figure 8__.=.
Relationship: reasoning
Domain: Hardware
Sentence 1: .. and row are Multiple columns and rows can be simultaneou may cause superfluous electrode activation, yysimulated annealing, which run in minnutes or tens of seconds; in droplet movement [28].
Sentence 2: once a route for aa direct-addressing DMFB is computed, each droplet-actuation ccycle is serialized across multiple droplet-actuation cycles, resultting in prolonged routing times and increased algorithmic complexxity.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note, the crosstalk is the most signi.cant at the center line (victim line) when all the outer lines (aggressor lines) are switching from logic 0 to logic 1.
Sentence 2: the maximum crosstalk can be readily determined by choosing the larger value between the negative peak and the positive peak,  nn() ffI MAX sik skj · vsj · Tk t- f(n) , k=1 j=1 nn ff () I sik skj · vsj · Tk tf0(n) + d(n) .
Relationship: reasoning
Domain: Hardware
Sentence 1: Much like prior work [7], [3], we .nd that hit rates do not signi.cantly improve with higher associativity.
Sentence 2: given the cost of implementing high set associativity (multiple tag comparisons, and maintaining recency infor­mation), we argue that a reasonably modest associativity is good enough to capture any additional cache hits to be  Figure 3: Latency Reduction with Bi-Modal Cache combination of high DRAM cache hit rate, way locator hit rate, and high RBH in the metadata bank combine to achieve a lower LLSC miss latency than all the other schemes.
Relationship: reasoning
Domain: Hardware
Sentence 1: 17We ensure that identical input .les (Liberty, netlist, SDC and SPEF) are provided to both tools, such that slack miscorrelation is due to delay and timingcalculation only.
Sentence 2: in Experiment 3 we do not use, e.g., Cadence Ostrich [33] to perform parasitic correlation with golden SPEF from Synopsys StarRC [36], in which case the design implementation tool s (D1) parasitic estimation may be another source of miscorrelation.
Relationship: reasoning
Domain: Hardware
Sentence 1: This model repre­sents the majority of cases in which an existent RTL bus is reused and transactors are exploited to bridge the ab­straction gap between the TLM and RTL modules.
Sentence 2: a Master-transactor, translates TLM master calls into se­quences of RTL signals for the bus and viceversa, while a Slave-transactor translates RTL signals of the bus into TLM function calls for the slave and viceversa.
Relationship: reasoning
Domain: Hardware
Sentence 1: Among the representative mappings, there is a min­imum contention across the threads of di.erent applications in Map-1, since the threads that belong to the same applica­tions share common L2 slices in this mapping.
Sentence 2: as can be observed from Figure 4(a) the speedups achieved when using Map-1 are not as high as those obtained with other mappings.
Relationship: reasoning
Domain: Hardware
Sentence 1: For digital circuits, aging effects are a function of the environment, as well as the use patterns [15][16].
Sentence 2: for analog circuits, which mainly operate in the small signal domain, aging is mainly a function of the bias conditions, which makes it more or less independent of input patterns.the aging process can be approximated with respect to temperature, humidity, and other environmental conditions [17][18].
Relationship: reasoning
Domain: Hardware
Sentence 1: However, for microchannels with small hydraulic diameter diameter, Dh, the Reynolds number (Re = .vDh/µ with density ., velocity v and viscosity µ) is suf.ciently small to result in co-laminar .ow of the two electrolyte streams which prevents convective mixing [13].
Sentence 2: no membrane is needed which implies simpler fabrication of .ow cells.
Relationship: reasoning
Domain: Hardware
Sentence 1: Unlike CoLT-FA however, our set-associative L2 TLB can now also handle coalesced entries (albeit with smaller levels of coalescing permissible by its choice of index bits).
Sentence 2: coLT-All brings in as much of this coalesced entry as possible into the L2 TLB, unlike CoLT-FA which brings just the requested translation.
Relationship: reasoning
Domain: Hardware
Sentence 1: At the same time, it also makes cache resizing slow to the change in the locality.
Sentence 2: if we want to make the control more conservative in performance, an n-bit asym­metric state machine as shown in Figure 4(b) could work .ne in which it slowly moves to State -1 (down-sizing), but quickly back to State +1(up-sizing) without a grace period spent in State 0, when the locality suddenly gets DT2 D>T2 D>T2 D>T2 (a) N-Bit Symmetric State Machine DT2 (b) N-Bit Asymmetric State Machine Figure 4.
Relationship: reasoning
Domain: Hardware
Sentence 1: Table I gives the name of the circuit, the statistics for the circuits (the number of cores, #core; the number of pads, #pad; the number of hyperedges, #hyp; the number of 2-pin nets), the number of rings constructed for detection, |Rt|, and the number of rings constructed for diagnosis, |Rd|.
Sentence 2: |Rt| is the testability­driven cost in the preprocessing stage, and |Rd|-|Rt| is the additional cost for the postprocessing stage.
Relationship: reasoning
Domain: Hardware
Sentence 1: The yield Y for chips with individually adjustable supply volt­age in the interval of voltage variations [.Vmin, .Vmax]is expressed as the probability that there exists supply volt­age in this interval such that both the timing and power constraints are satis.ed: Y =Prob(..V |S(.V, .L, .X) > 0,P (.V, .L) <Plim, .Vmin < .V< .Vmax) (16) This formula correctly de.nes yield of the chips with in­dividually adjustable Vdd, but it is not helpful for actual calculation.
Sentence 2: we transform it to an integral that is more suitable for computation.
Relationship: reasoning
Domain: Hardware
Sentence 1: Assume that the data is brought into the cache line at t4 by prefetching, and at the same time the cache line is transitioned to the SP mode.
Sentence 2: the cache line will consume full leakage power only during the period [t3,t4], instead of [t3,t6], and consume low leakage power during the period [t4,t7], resulting in leak­age energy saving.
Relationship: reasoning
Domain: Hardware
Sentence 1: Figure 1(b) illustrates the resulting voltage-drop map after applying the voltage-drop optimization shown in Fig­ure 1(a); the block densities in bins g3,4 and g4,3 might exceed the density constraint, due to the moved blocks (through the voltage drop force).
Sentence 2: the density spread­ing forces of analytical placement would push the blocks in bins g3,4 and g4,3 back to non-congested regions, for exam­ple, g3,3 in Figure 1(b).
Relationship: reasoning
Domain: Hardware
Sentence 1: 5.3.3 Detection function of .ngers motion As discussed at the beginning of this subsection, we could use the fast speed of .ngers motion to indicate onset timing.
Sentence 2: we derive the .rst derivative Rfj of Rfj,1 = j = Detection Function of Right Hand (Bowing) Motion - Radius Detection Function of Audio-Only  Detection Function of Right Hand (Bowing) Motion - Angle 0.4 0.2 0 Detection Function of Left Hand Index Finger (F1) Motion - Radius 1 0.5 0 Detection Function of Left Hand Middle Finger (F2) Motion - Radius 1 0.5 0 Detection Function of Left Hand Ring Finger (F3) Motion - Radius 1 0.5 0 Detection Function of Left Hand Little Finger (F4) Motion - Radius 1 0.5 0 Fused Detection Function of Video 1 0.5 0 16 17 18 19 20 21 Time (Second) Figure 6: The intra-model data fusion of video.
Relationship: reasoning
Domain: Hardware
Sentence 1: 38.2 SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects Qiang Xu , Yubin Zhang and Krishnendu Chakrabarty Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA {qxu,ybzhang}@cse.cuhk.edu.hk; krish@ee.duke.edu ABSTRACT The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic.
Sentence 2: prior work on test infrastructure design for core-based system-on-a-chip (SOC) has mainly focused on minimizing the test time for core-internal logic.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note, that in this case initial pattern (b1,b2, ..., bn) was greater than (a1,a2, ..., an), so the most signi.­cant binary digit of (b1,b2, ..., bn) equal one was greater than the most signi.cant one digit of (a1,a2, ..., an).
Sentence 2: it will be taken as the control (when a control is needed) for all corresponding Fredkin and To.oli gates except the last To.oli gate, for which the control will consist of all unit digits of (a1,a2, ..., an).
Relationship: reasoning
Domain: Hardware
Sentence 1: As illustrated in the Figure 4, the sum is an L-bit register with dot in the position (2r+2|e1|), where the most signi.­cant bit is in the position L. The product of mant(Ai) * mant(Bi) is located between position from (2exp+M - 1) and 2exp .
Sentence 2: as illustrated in line 4 of the algorithm in Figure 3, the .rst part of sum in the right of 2exp can be copied directly to new sum.
Relationship: reasoning