sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Improved Procedure Placement for Set Associative Caches Yun LiangTulika Mitra Advanced Digital Sciences Center School of Computing Illinois at Singapore National University of Singapore eric.liang@adsc.com.sg tulika@comp.nus.edu.sg ABSTRACT The performance of most embedded systems is critically depen­dent on the memory hierarchy performance.
Sentence 2: higher cache hit rate can provide signi.cant performance boost to an em­bedded application.
Relationship: entailment
Domain: Hardware
Sentence 1: This hierarchical switch arbiter is a distributed switch arbiter whose individual 2x2 and 4x4 SAs operate in parallel with one another.
Sentence 2: the upper level switch arbiters (relatively located at the right side of Figure 5) arbitrate the ORed requests from the lower level switch arbiters in Figure 5, while a internal BA of a lower level SA grants one request regardless of an ack signal from the higher level.
Relationship: entailment
Domain: Hardware
Sentence 1: Thereafter, the U-method, which uses a unique input/output (UIO) sequence to verify the ending state of each transition besides testing each transition at least once, is widely used in protocol conformance testing.
Sentence 2: this method involves deriving UIO sequences for each state of M. A UIO sequence for a state of M is an I/O behavior that is not exhibited by any other state of M. the test sequence u is regarded to be a UIO sequence for state (1 == if and only if si in) 1 jn, ji.
Relationship: entailment
Domain: Hardware
Sentence 1: We see that, on average, considering all levels in the hier­archy (L1+L2+L3+L4) bring 21.8% and 12.7% improvement over the L1+L2 and L1+L2+L3 versions, respectively.
Sentence 2: for the best results, it is necessary to consider the entire cache hi­erarchy in distributing loop iterations among cores.
Relationship: entailment
Domain: Hardware
Sentence 1: The Extended Greedy heuristic does not have a bounded perfor­mance ratio on general instances: it is east to construct contrived instances on which it does not perform well.
Sentence 2: it is motivated, how­ever, by particular observed properties of our .lters data: One prop­erty is that our .lter instances have long commutative stretches (rules that have the same action commute).
Relationship: entailment
Domain: Hardware
Sentence 1: We note that the side-channel nature of the DFA allows to attack the three DES executions separately, starting from the last one.
Sentence 2: from a DFA standpoint, it is possible to attack the Triple-DES cipher through simply retrieving the secret-key of the last DES instance, peeling away the effects of its encryption, and repeating the procedure for the other instances.
Relationship: entailment
Domain: Hardware
Sentence 1: For any given disk request that requires accessingtheplatters(i.e., cannotbe servicedfrom the disk cache), the access time of the request is serial­ized through the seek, rotational latency, and data trans­fer phases.
Sentence 2: although the arm and spindle assem­blies are physically independent electro-mechanical sys­tems, they are used in a tightly coupled manner due to the way thatdisk accesses areperformed.
Relationship: entailment
Domain: Hardware
Sentence 1: To carry out the proposed feature measurements, we intro­duce 4 types of feature-centric operators constructed under Table 1: Hotspot signature measurement operators operators operation description (features to measure) fcorn(·) corner information: CV(convex) / CC(concave) fext(·) external inter fragment distances fint(·) internal inter fragment distances fmisc(·) miscellaneous information  9A-1  Effectiv e radius Fragmen t a t i on based  (a) (b)  centered at each fragm e nt conte xt char acteri z a t ion Figure 3: Fragmentation based hotspot signature extraction the shared object environment of [16], as shown in Table 1.
Sentence 2: operator fmisc(·) requests extra information regarding Frag, such as fragment orientation (X or Y axis) and the length of Frag, etc.
Relationship: entailment
Domain: Hardware
Sentence 1: Com­pleteness is achieved by refining abst(X) to eliminate such cases.
Sentence 2: if X* denotes an assignment of values to variables such that ** * abst X lprop X 0 and conc X 0 then X* represents a spurious counterexample that must be eliminated from the space of consistent assignments in the abstract model (line 9).
Relationship: entailment
Domain: Hardware
Sentence 1: Note that the numbers of latches, gates, and inter-cell connections for the ar­chitecture with distributed control in [8] assume all three control signals are computed in the control cells.
Sentence 2: the modi.cation mentioned in [8, Section 3.2.2], which computes one control sig­nal locally and leads to a minor improvement, was not re.ected in Table 1.
Relationship: entailment
Domain: Hardware
Sentence 1: The .nal logic equation for the enable signal is thus as follows: enable = (l XNOR b) &#38; (f XOR l) &#38; (d XNOR b) (1) Interestingly, the above logic implementation of the latch enable may glitch in a particular scenario; however, those glitches are com­pletely harmless.
Sentence 2: when an idle pipeline stage (with its latch disabled) receives an antitoken from its right neighbor, the current stage s latch may temporarily become enabled (for a certain combination of gate and wire delays), even though it is ideally sup­posed to stay disabled.
Relationship: entailment
Domain: Hardware
Sentence 1: Lemma 1: A monomial candidate_p1 computed in (1) is a good candidate to be added to p1 if 1) those monomials produced by candidate_p1u p2 and have the highest complexity, are found in existing_mon.
Sentence 2: the complexity of those monomials found in existing_mon should be greater than that of monomials which do not exist in existing_mon and 2) those monomials produced by candidate_p2up1 and have the highest complexity, are found in existing_mon.
Relationship: entailment
Domain: Hardware
Sentence 1: A memory trace s is said to be serial if, for all indices i, we have op(i)=R implies both lw(s,i,addr(s(i)))= 0 and val(s(i))=val(s(lw(s,i,addr(s(i))))).
Sentence 2: in a serial trace each read action returns the value of the last write action to the same address2.
Relationship: entailment
Domain: Hardware
Sentence 1: Assuming there is no preference in binding operations to resources, the probability of an operation v to be bounded to resource rT(~,),~ is ~ .
Sentence 2: aT{v} 1 p((vi,rT(~i),j) E Ebi,~a ) --(1) a~-(~)  The probability that a DFG edge be mapl)ed to a resource connection edge can be derived from Equation 1 as follows: 1 (z) (IT( vl )aT(vj ) Lemma 2.
Relationship: entailment
Domain: Hardware
Sentence 1: 6.2 Performance Analysis Moving from the coverage analysis results, performance limits of the communication protocol have been evaluated by focusing on the WSN Patch level, i.e., the portion of the EMMON network below the gateway.
Sentence 2: using the previously referred toolset, several scenarios were iden­ti.ed based on all the combinations of the input parameters in Table 1.
Relationship: entailment
Domain: Hardware
Sentence 1: The objective of this flow is to faacilitate fast assay synthesis while minimally compromising the quuality of results.
Sentence 2: we show that a virtual topology, whhich constrains the allowable locations of assay operations such ass mixing, dilution, sensing, etc., in lieu of traditional placement, can significantly speed up the synthesis process without significcantly lengthening assay execution time.
Relationship: entailment
Domain: Hardware
Sentence 1: 2b) Apply Fairness-Rule: If the ratio Smax/Smin >a,thenSTFM decreases unfairness by prioritizing requests of thread Tmax with largest slowdown Smax.
Sentence 2: dRAM commands are pri­oritized in the following order: 2b-1) Tmax-.rst: Ready commands from requests issued by Tmax over any command from requests issued by other threads.
Relationship: entailment
Domain: Hardware
Sentence 1: For indication, CPU time of 10 GA generations (500ms) is 181 seconds and simulating 100 chromosomes for 500ms alone (with­out GA) takes 177 seconds, which means that GA accounts for less that 3% of the CPU time.
Sentence 2: the energy harvester has a large storing capacitor of 0.22F and even for one chromosome, simulating the voltage across it with time step of 0.1ms for 100 seconds takes almost 10 min­utes.
Relationship: entailment
Domain: Hardware
Sentence 1: Functional interdependency is found when an infrastructure requires in order operating adequately that another infrastructure operates well.
Sentence 2: in the case of ICT infrastructures, functional interdependency is found with respect to the following interdependent infrastructures called lifelines: electric grid to power sites, water supply for cooling of large centers, and roads for delivering fuel for gensets and deploying portable gensets to distributed sites.
Relationship: entailment
Domain: Hardware
Sentence 1: V. SIMULATION RESULTS We examine the performance of the logic hardening scheme, represented by yield, de.ned as the percentage of successful logic mappings in a number of trials.
Sentence 2: we use the metric of RunTime-Constrained (RTC) yield [28], by setting a runtime upperbound for searching for a logic implementation in the experiments, and gathering yield data over 104 defective crossbars.
Relationship: entailment
Domain: Hardware
Sentence 1: The increase in the number of MTs due to ghosting may be thought of as increasing the effective area of the overlay, from the point of view of paging.
Sentence 2: if Ns MTs are registered with the overlay, we say the effective area is As = Ns/.. We are interested in the ghosting ratio As/Ao = Ns/No, which is always greater than or equal to one for a convex region.
Relationship: entailment
Domain: Hardware
Sentence 1: This is due to the fact that if dik is the same for two canonical forms X and Y , the PDF of the statistical min(X, Y ) is virtually indis­tinguishable from the PDF of the input which has smaller mean, independent of the tightness probability.
Sentence 2: as long as x0 <y0, it does not matter if x0«y0 or x0 y0, the PDF for the statistical min(X, Y ) is essentially the same as the PDF for X.
Relationship: entailment
Domain: Hardware
Sentence 1: Although the physical cell size is comparable to that of the SRAMs and the 7 '5$0 WHUQDU *175$0¶V GHQVLW EHQHILW FRPHV IURP the fact that it stores more than one bit per cell (log3/log2 bits per cell).
Sentence 2: ternary GNTRAM showed a density­per-bit benefit of up to 1.68x vs. scaled 6T CMOS SRAM, 1.77x vs. gridded 8T CMOS SRAM and 1.42x vs. the 3T DRAM in 16nm technology node.
Relationship: entailment
Domain: Hardware
Sentence 1: The reduction matrix needs to be composed of individual Krylov subspaces for only these k trajectory points and not for all the points in the model.
Sentence 2: the for loop in Algorithm 1 needs to run for i = {1, 2, ..., k} instead of i = {1, 2, ..., s} (where s is the number of trajectory samples in the models, typically on the order of 10,000-100,000).
Relationship: entailment
Domain: Hardware
Sentence 1: The state set C :={s|prop(s)=1} (3) is called induction commitment.
Sentence 2: based on the above de.nition the inductive step for proving prop can be formulated as a bounded reachability check using the image operator as follows: we check whether only states in C are reachable from Hk in k +1 clock cycles.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we adopt the three-stage mixed-size placement ap­proach because it is robust to handle macro orientations and pre-placed macros, .exible to consider various routability constraints, and easy to be integrated into an industry design .ow.
Sentence 2: we focus on the second stage, macro placement, which is the key to determine the placement quality for this approach.
Relationship: entailment
Domain: Hardware
Sentence 1: In spite of the above bene.ts, which may or may not be present under the entropy loss function de.ned in Ap­pendix B since it does not consider the detector as part of the communication channel, we see that these bene.ts would vanish if the a-priori information, cost assignments, and de­cision space T are known precisely.
Sentence 2: such bene.ts stand on the weaknesses of the Bayesian method.
Relationship: entailment
Domain: Hardware
Sentence 1: Today it is perfectly feasible to design a multiprocessor System-on-a-Chip on FPGA platforms.
Sentence 2: soft processors on FPGAs (e.g., MicroBlaze from Xilinx [22] and NIOS /NIOS II from Altera [20]) offer a higher level of abstraction and present new options to the embedded designers.
Relationship: entailment
Domain: Hardware
Sentence 1: Introduction The growing demand for embedded computing platforms, mobile systems, general-purpose handheld devices, and dedicated servers coupled with shrinking time-to-market windows are leading to new core based system-on-a-chip (SOC) architectures [1][2][3].
Sentence 2: microprocessor cores (a.k.a., embedded processors) are playing an increasing role in such systems design [4][5][6].
Relationship: entailment
Domain: Hardware
Sentence 1: Furthermore, as long as task t1F executes during the transition phase, none of the tasks t2U and t4U will experience blocking from t3A.If t3A would have higher priority than t1F then t3A s execution would not wrongly be delayed by lower priority tasks.
Sentence 2: the AUTOSAR spinlock-based arbitration strategy inherently avoids the problems identi.ed in case of using priority ceilings for LRs [4], [6].
Relationship: entailment
Domain: Hardware
Sentence 1: Our technique reduces the power consumption, because a) the low temporal data is processed on the data filtering engine before it is placed onto the high capacitance system bus, and b) the conflict misses caused by low temporal data are reduced resulting in fewer accesses to the L2 cache.
Sentence 2: we show that our technique reduces the bus accesses in representative applications by as much as 46.8% (26.5% on average) and reduces the overall power by as much as 15.6% (8.6% on average) on a single-core processor.
Relationship: entailment
Domain: Hardware
Sentence 1: Inparticular,recentlyproposed memory modelsforC++0x[9] andJava[30] arebased on thedata-race-free-0(DRF0) memory model[1].These models require that aprogrammer explicitly clas­sify shared-memory variables into synchronization and data.1 The intentionis thatprogrammers use synchronization variables for all inter-threadcommunication and thatthere are nodata races ondata variables.
Sentence 2: two threads in the program are not al­lowed to concurrently access the same data variable unless both accesses are reads.For suchdata-race-freeprograms,DRF0guar­antees SC.Toprovide thisguarantee, DRF0 requires the language runtime to execute synchronization accesses in SC order with few optimizations.Onthe otherhand,the runtimeis allowedtoperform most sequentially valid (i.e., correcton a single threadinisolation) optimizations in synchronization-free regions of the program.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition, there is a fundamental tradeoff between the service time of a battery equipped with fans and the cycle life of the same battery.
Sentence 2: as the fan speed is increased, the power dissipated by the fan goes up and hence the full charge capacity of the battery is lost at a faster rate, but at the same time, the battery temperature remains lower and hence the battery longevity increases.
Relationship: entailment
Domain: Hardware
Sentence 1: To characterize the shadowing effect, a log-normal distribution is used to describe the slowly-varying local mean.
Sentence 2: 1 (ln x -ln Osi )2 psi (x)= v exp-0 =i =n 2pssi x 2s2 si (7) where Osi is the area mean power; ssi is the standard deviation of shadowing.
Relationship: entailment
Domain: Hardware
Sentence 1: BUS ENCODING USING TEMPORAL REDUNDANCY In the proposed temporal redundancy based (n,m,k)­encoding scheme, the original n-bit data packet to be trans­mitted is encoded into two ( n ) *m-bit data packets, where k m< k, and transmitted over two consecutive cycles.
Sentence 2: the n-bit data is split into ( n )number of k­ k bit data blocks.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.2 Guarantees Using I/O remotely at the device .le boundary impacts three expected behaviors of .le operations: reliability of con­nection, latency, and trust model.
Sentence 2: remote I/O in­troduces the possibility of disconnection between the process and the driver, adds signi.cant latency to each .le operation due to wireless round trips, and allows processes and drivers in di.erent trust domains to communicate.
Relationship: entailment
Domain: Hardware
Sentence 1: Fast simulation having on-demand replay capability Since the number of flipflops and latches in a  5A-5 design is typically much larger than the number of inputs, the benefit of our method is obvious.
Sentence 2: the dumping overhead for saving those two groups of signals (state values, input values) at the first simulation is greatly reduced, compared to the methods in [7, 8].
Relationship: entailment
Domain: Hardware
Sentence 1: However, we choose to model it as we originally presented for two reasons: .rst, the mapping of the architecture to the network is more intuitive; and second, this allows for the easy extension of breaking the energy cost down by stage.
Sentence 2: if we had an estimate of the energy cost for each stage of the .oating point ALU, we would instead assign non-zero weights to all four links F, P, U, FP4, in order to increase the accuracy of the model.
Relationship: entailment
Domain: Hardware
Sentence 1: This means that if there is noise added to the samples, the reconstruction (2) will give us the associated oversampling gains.
Sentence 2: the total noise in the reconstruction will be  -0.95 -0.6 -0.8 -1 log10 (.e ) -1 -1.2 -1.4 -1.6 log10 (.e ) -1.05 -1.1 -1.15 -1.2 -1.8 -2 -1.25 1234 5 678910 123 45 678 910 (a) b =10,m =10,n = 1000 (b) b =10,m = 100,n = 10000 Figure 4: Log-spectrums of A = RmF *SF TF *R* b .
Relationship: entailment
Domain: Hardware
Sentence 1: Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes Junwhan Ahn*, Sungjoo Yoo§, and Kiyoung Choi* junwhan@snu.ac.kr, sungjoo.yoo@postech.ac.kr, kchoi@snu.ac.kr *Department of Electrical and Computer Engineering §Department of Electrical Engineering Seoul National University, Seoul, Republic of Korea POSTECH, Pohang, Republic of Korea ABSTRACT The Hybrid Memory Cube (HMC) is a 3D-stacked DRAM architecture designed for substantially improved memory bandwidth.
Sentence 2: its I/O interface achieves up to 320 GB/s of external bandwidth through high-speed serial links.
Relationship: entailment
Domain: Hardware
Sentence 1: These problems are uniquely QCA-driven since QCA circuits are inherently pipelined at the gate level, and the timing of sig­nal delivery requires that all the signals for a given gate ar­rive simultaneously.
Sentence 2: each QCA wire inherently holds state information for a clock cycle because the wire is constructed from QCA devices, and the state is held in the position of the charge on two devices which are physically in­teracting.
Relationship: entailment
Domain: Hardware
Sentence 1: Handling Mixed-Criticality in SoC-based Real-Time Embedded Systems * Rodolfo Pellizzoni, Patrick Meredith, Min-Young Nam, Mu Sun, Marco Caccamo, Lui Sha University of Illinois at Urbana-Champaign Urbana, IL 61801-2302 {rpelliz2, pmeredit, mnam, musun, mcaccamo, lrs}@illinois.edu ABSTRACT System-on-Chip (SoC) is a promising paradigm to imple­ment safety-critical embedded systems, but it poses signi.­cant challenges from a design and veri.cation point of view.
Sentence 2: in a mixed-criticality system, low criticality applications must be prevented from interfering with high criticality ones.
Relationship: entailment
Domain: Hardware
Sentence 1: P8 n-11 Note that npr = when 0 <pr < 1. n=1 (1-pr)2 If AMG achieves speedup S in fault-free execution in a particular parallel environment then the slowdown due to faults equals E(1 X) .
Sentence 2: the .nal speedup in a faulty environment is E(SX) = S(1 - pr).
Relationship: entailment
Domain: Hardware
Sentence 1: (6) In view of the sensitivity of x2 with respect to the changes of x0, (6) indicates that x2 s perturbation can be traced back to x0 along two paths: x2 is directly affected by x0, and x2 is also affected indirectly by x0 via x1.
Sentence 2: dx2 .x2 dx1 .x2 = + , dx0 .x1 dx0 .x0 where the two partial derivatives are .x2 a1 .x2 a2 J-1 J-1 = 2 C1, = 2 C0, .x1 h2 .x0 h2 and dx1/dx0 is calculated previously in (5).
Relationship: entailment
Domain: Hardware
Sentence 1: Process variations For any given vector, we characterize delays of paths in benchmark circuits using realistic delay values and under realistic levels of process variations supplied by the vendors for the fabrication process in the form of technology files.
Sentence 2: we use an industrial 65nm technology and use the delay model, including inter- and intra-die variations, provided by the foundry which fabricates chips using this technology.
Relationship: entailment
Domain: Hardware
Sentence 1: Dropping every conjunction that has c or more variables creates the legal c-DNF e D. When dropping a conjunction, the DNF circuit may change its output from 1 to 0 on an input that contains this conjunction.
Sentence 2: this means that for all inputs x e {0, 1} n we have eD(x) <_ eC(x) (proving part 1).
Relationship: entailment
Domain: Hardware
Sentence 1: Thus, if the operations between s and t mimic those between u and v, they will store scaled versions of polynomials computed m-dj-1 x(j-1)(z) by the EEA as well.
Sentence 2: s and t contain z m-dj-1 x and z (j)(z) respectively at the start of Step EEA.2(j), m-dj xm-dj x and they contain z (j)(z) and z (j+1)(z) respectively at the end of Step EEA.2(j).
Relationship: entailment
Domain: Hardware
Sentence 1: TARGET MP-SOC ARCHITECTURE In this paper, we describe the application of the pro­posed power and performance exploration methodology to a domain-speci.c .exible MP SOC architecture oriented to­wards networking applications derived from the StepNP plat­form.
Sentence 2: our target con.gurable MP SOC archi­tecture includes the following modules (see Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: Implementations comparison: Ourprimarygoal is to compare the potential speedup that can be achieved by the di.erent platform implementations, without taking into ac- Table 2: Slices versus XtremeDSP slices proportion    FPGA Available Slices Slices / XtremeDSP RUs Fit V4FX40 9267 193 3 V4FX60 15923 124 5 V4FX100 32819 205 10 V4FX140 53811 280 13 count the overhead of the initial data transfers between the GPP main memory and the GPU main memory.
Sentence 2: we assume that all data are already residing in the GPU main memory.
Relationship: entailment
Domain: Hardware
Sentence 1: For the SA+RP-RR con.gurations we observe that few num­ber of ways is enough to provide average performance close to that of the FA-RR cache and to that of LRU+modulo caches.
Sentence 2: 8-and 32-way SA-RP+RR cache designs provide performance comparable to state-of-the-art cache designs (12% and 10% slowdown respectively), and acceptable design cost (largely below unaffordable large fully-associative caches) while enabling PTA.
Relationship: entailment
Domain: Hardware
Sentence 1: DRM, on the other hand, is a technical solution being implemented in mobile devices by mobile handset manufactures at the behest of members of the digital media supply chain.
Sentence 2: dRM is a system for protecting the copyrights of..[files] circulated via the Internet or other digital media by enabling secure distribution and/or disabling illegal distribution of the data [Webopedia 2004] DRM is a means by which content providers can prevent illegal distribution of copyrighted media files and thus protect revenue streams by encrypting and packaging media files, with rules that dictate the playback/distribution of the file.
Relationship: entailment