sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Elements in the vector objToStore are stored in the bufer 1Some compilers and ISAs generate specialized code so thatcertain copies bypass the cache.
Sentence 2: for instance, Intel s C com­piler and libraries will use a non-temporal store for mem­cpy() if the size of the data moved is larger than 256KB [9].shorter instances of copying continue to lead tosigni.cant cache data duplication.
Relationship: contrasting
Domain: Hardware
Sentence 1: That work uses a Utility Monitoring Circuit (UMON) [13] for adapting insertion policy in the shared LLC by col­lecting run-time miss rate information of the individual appli­cations with different associativity.
Sentence 2: the use of UMON comes at the cost of additional hardware overhead, which requires per-core storage overhead of 7.4 KB, altogeth­er leading to a 29.6 KB storage overhead for a quad-core sys­tem.
Relationship: contrasting
Domain: Hardware
Sentence 1: STT-MRAM has no leakage from the memory cell and a comparable read speed as SRAM.Recently proposed Multi-level cell (MLC) STT-MRAM [7, 8, 9, 10] can store multiple bits per cell, reduce per-bit cost, and make STT-MRAM even more attractive for constructing large and low power onchip caches.
Sentence 2: while MLC STT-MRAM improves density, it has almost doubled read and write latencies.
Relationship: contrasting
Domain: Hardware
Sentence 1: This happens because with consensus, even if multiple clients contend on who will become the leader and be the .rst to recon.gure the system, all other clients .nd out about changes to the con.guration only after the consensus algorithm has reached a decision, and then, a single new con.guration exists.
Sentence 2: in the consensus-free approach writers see all Figure 2: Average recon.g latency.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the transactional execution completes success­fully (transactional commit), then memory operations per­formed during the transactional execution appear to have occurred instantaneously, when viewed from other proces­sors.
Sentence 2: if the processor cannot complete its transac­tional execution successfully (transactional abort), then the processor discards all transactional updates, restores archi­tectural state, and resumes execution.
Relationship: contrasting
Domain: Hardware
Sentence 1: The reason for this behavior is that when power is scarce, cores in the homogeneous CMOS system are forced to operate at very ine.cient operating conditions when compared to TFET cores employed in our hetero­geneous processor.
Sentence 2: the homogeneous TFET processor still su.ers from the limited maximum fre­quency of TFETs, which signi.cantly degrades sequential region performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: Considering the second generation HMC prototype provides 160 GB/s with a single HMC [4], the actual bandwidth available to the CPU is fairly limited and the high bandwidth bene.t of the HMC cannot be fully utilized with the PCN or hybrid network.
Sentence 2: with the MCN, all processor bandwidth can be used to access local HMCs and the throughput is improved by up to 1.5× for MCN UGAL.
Relationship: contrasting
Domain: Hardware
Sentence 1: PRET DRAM Controller: Bank Privatization for Predictability and Temporal Isolation* Jan Reineke Isaac Liu Hiren D. Patel University of California, Berkeley University of California, Berkeley University of Waterloo Berkeley, CA, USA reineke@eecs.berkeley.edu Berkeley, CA, USA liuisaac@eecs.berkeley.edu Waterloo, Ontario, Canadahdpatel@uwaterloo.ca Edward A. Lee University of California, Berkeley Berkeley, CA, USA eal@eecs.berkeley.edu  Sungjun KimColumbia University New York, NY, USAskim@cs.columbia.edu ABSTRACT Hard real-time embedded systems employ high-capacity memories such as Dynamic RAMs (DRAMs) to cope with increasing data and code sizes of modern designs.
Sentence 2: memory controller design has so far largely focused on improving average-case performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: The main idea of MSV is to apply different voltages on circuit blocks or islands to meet the min­imum necessary supply requirements.
Sentence 2: multiple voltages Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: contrasting
Domain: Hardware
Sentence 1: For instance, if the buffer size is chosen arbitrarily to be 2.8K, then Markovian analysis would predict a buffer over.ow probability of about 10-2.
Sentence 2: nonMarkovian analysis based on the Norros formula would predict an over.ow probability about one order of magnitude higher, which matches the simulation results very well, as can be observed in Figure 8.
Relationship: contrasting
Domain: Hardware
Sentence 1: Therefore (5) is simpli.ed as: Ai (Ai -Aj ) += -lIi (9) Ri0 Rij A vector potential current source I i can be de.ned as: Ii = lIi (10) which is controlled by the electrical current Ii.
Sentence 2: integrating (2) along z-direction at the h-.lament surface Si leads to the following inductive electro-potential drop at ai: .Ai l = -Vi (11) .t Consequently the voltage-controlled vector potential voltage source Vi is de.ned as: Vi = Vi/l (12) The VPEC model for two h-.laments includes following components [1] (see Fig.
Relationship: contrasting
Domain: Hardware
Sentence 1: The left .gure in (a) shows the case when the iterations that accessAandB are assigned to two cores with no af.nity, whereas the right one illustrates a potential con.ict if the iterations that do not share data are assigned to cores with cache af.nity.
Sentence 2: if two iterations do share data, it is better to assign them to cores that have af.nity at some cache (see the right part of Figure 3(b)).
Relationship: contrasting
Domain: Hardware
Sentence 1: Other workhas shownaudible soundcan be a goodresourcefor localizing devices.
Sentence 2: most of the previous workuses on-device loudspeakers to actively emit known .nite­lengthrepeatablesignals, suchas chirpsorpeaks[9, 17,20].This approach can be intrusive and sometimes annoying ifthe systems require frequent location updates of their de­vices.
Relationship: contrasting
Domain: Hardware
Sentence 1: Optimization of a TDM NoC in terms of area and power consumption was done in [21] by coupling with a memory interface and removing the buffers and .ow control by implementing a Direct Memory Access (DMA) access table inside a NI.
Sentence 2: the approach is speci.c for DMA clients and is not applicable for clients with diverse requirements on bandwidth and/or latency.
Relationship: contrasting
Domain: Hardware
Sentence 1: Still, the current parser imposes some restrictions on in­put language.
Sentence 2: for example, macros entangled with other expressions or statements do not parse correctly, like below: if ( #ifdef SPECIFIC_ARCH foo() #else    foo.c  int counter = 0;    func  counter++;    Figure 2: A sample aspect bar() #end ) baz(); according to our observations, such a hacky code is rarely used in products, because it degrades maintainability and readability.
Relationship: contrasting
Domain: Hardware
Sentence 1: Each of the transforms is carried out by a local method that produces a value thatis consumedby another method.The composition of methods in this way lends itself well to pipeline paral­lelism where each of the .ve methods is concurrently oper­ating on different (but successive) macroblocks in the same color channel as illustrated in Figure 4.
Sentence 2: the in­ troduction of pipeline-parallelism in an imperative language is intrusive, requiring the incorporation ofbuffering stages between method-calls or the use of other schemes that ul­timately obfuscate the program.
Relationship: contrasting
Domain: Hardware
Sentence 1: BPDG: BLOCK PREFERENCE DIRECTED GRAPH The substrate noise model in Section II-B is one of the most compact models with high scalability and accuracy.
Sentence 2: it is still computationally expensive to perform a substrate noise estimation even with such an ef.cient model during simulated annealing-based .oorplanning, because every noise estimation after a movement requires the accurate location of every block (substrate noise is exponentially sensitive to geometric distance [5], [14], [15]), whereas area and wire­length can be calculated approximately.
Relationship: contrasting
Domain: Hardware
Sentence 1: On the hard­ware platform depicted in Figure 2, most functions making up a specific application are therefore implemented as software tasks, without the benefit of hardware acceleration to increase their op­erating speed.
Sentence 2: this necessity for many software tasks is actually beneficial for the demonstration of autonomic workload balancing, as migration of tasks for workload balancing becomes more complex and interesting with an increasing number of migratable tasks.
Relationship: contrasting
Domain: Hardware
Sentence 1: Note that, if the memory con.guration de­.ned in had been used, then the platform would have had to be operated at 133 Mhz and 1.1 V, which would have led to higher power consumption.
Sentence 2: if the platform was oper­ated at 118 Mhz (the optimum speed for ), it would have led to a total CPU utilization of 104.1%, resulting in failure to meet perfor­mance requirements.
Relationship: contrasting
Domain: Hardware
Sentence 1: It is interesting to notice that the .rst three con.gu­rations (tickless-100, non-tickless-100 and tickless-1000) do not show any signi.cant variation.
Sentence 2: the last con.g­uration, non-tickless-1000, has a power consumption 2.75% higher than the rest, with a slight increase in temperature.
Relationship: contrasting
Domain: Hardware
Sentence 1: (3) t - u w - (2t - u) If u = t - 1, then for n large enough, (3) is less than ` ´ M(n, k, t) = n-t , and hence |B| = M(n, k, t).
Sentence 2: w-t if u = t, then |A1 n A2| = t, which implies A is t-intersecting.
Relationship: contrasting
Domain: Hardware
Sentence 1: noise from aggressor m on the noiseless event v at node l and a new noisy event vn at l is computed and scheduled.
Sentence 2: during the computa­tion, the noise alignment is constrained by the timing window at node k. if the optimal aggressor input alignment time taiopt > t, as shown in Figure 6(b), there exists ambiguity as to whether the aggressor can transition at the optimal time, since the time window at k could end before taiopt.
Relationship: contrasting
Domain: Hardware
Sentence 1: Mehdi B. Tahoori Karlsruhe Institute of Technology Karlsruhe, Germany mehdi.tahoori@kit.edu chip as well as increasing costs associated with photolithog­raphy fabrication.
Sentence 2: exploiting Carbon NanoTubes (CNTs) and semiconductor Nano Wires (NWs) based on bottom-up self-assembly fabrication is a promising alterna­tive for current CMOS technology.
Relationship: contrasting
Domain: Hardware
Sentence 1: INTRODUCTION Reliability and yield analysis of embedded SRAM memory mod­ules are critical to designs of modern microprocessors, 3D-ICs, and mixed-signal SOCs.
Sentence 2: nanoscale SRAM designs are greatly challenged by prohibitively high computational cost due to the extremely large number of repeated SPICE simulations consid­ering parametric variations [1 4].
Relationship: contrasting
Domain: Hardware
Sentence 1: However, the problem of determining MDDV is very different from determining minimum leakage vector in many aspects: Cost Function: The optimization objective of MLV problem is simply the algebraic sum of all leakage power values of in­dividual gates.
Sentence 2: the optimization objective of MDDV is to reduce delay through the circuit which depends on rela­tive delay among competing paths thus more dif.cult to op­timize.
Relationship: contrasting
Domain: Hardware
Sentence 1: 8 Conclusion Our surveys revealed that all tested bezel sizes had a signi.cant impact on overall depth perception especially in the near .eld compared to non-bezeled projections.
Sentence 2: bezels seem to help, or at least do not interfere, with counting tasks by partition­ing the viewspace despite the less pleasing subjective appeal of the stereoscopic images.
Relationship: contrasting
Domain: Hardware
Sentence 1: Many previous works have discussed small-scaled examples and showed that for earlier technology nodes, an RLC based on-die model does not deviate much from an RC model [3, 4].
Sentence 2: for 32nm microprocessor, due to the higher metal stacks and larger design size, the metals wires on the top metal layer (tm) can be longer than 1 millimeter with a larger current loop.
Relationship: contrasting
Domain: Hardware
Sentence 1: (1- p )(1- p ) + (1- p ) (1- p ) - (1- p ) (1- p ) vw vwvw Next, as an external redundant wire with four wire segments with length l1 , l2, l3 and l4 and three vias is added onto the L-type wire to construct a local cycle, the connecting probability, Pext (l ,l ,l ,l ) , of the local cycle can be obtained as L 1234 l +l 3 l +l +2l +2l 42l +2l +2l +2l 12 1234 1234.
Sentence 2: (1- p )(1- p ) +(1- p ) (1- p ) -(1- p ) (1- p ) vwvw vw it is assumed that a U-type wire, Ul1, l2, l3, is constructed by three wire segments with length l1, l2 and l3 and two connecting vias.
Relationship: contrasting
Domain: Hardware
Sentence 1: When operated in ss corner, the drain current at 0.4 V varies to 0.1308 µA, a change of 78.58% compared to the current in the tt corner.
Sentence 2: if we boost the VGS to 0.8 V, then the drain current at 0.8 V is 52.23 µA in ss corner, a change of 37.18%.
Relationship: contrasting
Domain: Hardware
Sentence 1: It is important to note that entries in the same PC localized miss stream are ordered chronologically, but two chronologically con­secutive misses will not necessarily belong to the same miss stream.
Sentence 2: thus, if a prefetching algorithm issues a number of prefetching re­quests based on a PC localized stream, each prefetched data item for a dynamic instance PCni is expected to be used in following instances PCni +1 to PCni +d,where d is the degree of prefetching, and before memory accesses from some other PCj 2.an indeterminate number of memory accesses can appear between the prefetch trigger at PCni and the use of the prefetched data by PCni +1 to PCni +d, as long as these requests are not classi.ed in the same localized stream of PCi.
Relationship: contrasting
Domain: Hardware
Sentence 1: On the one hand, our results indicate that increasing the number of WDM channels alone can have a large performance impact for bus-intensive applications in the CMP con.guration stud­ied.
Sentence 2: other CMP organizations (e.g., a larger number of cores) may require other organizations that present very di.erent power/performance/complexity chal­lenges (e.g., number of modulators, power and bandwidth requirements at the nodes, etc.).
Relationship: contrasting
Domain: Hardware
Sentence 1: (1399 mWatts = 25% of the range between the lowest possible budget, 1176 mWatts, and the highest possible budget, 2067 mWatts, plus the lowest budget.
Sentence 2: out of these 1399 mWatts, the difference between the accessing and active power consumptions, 867 mWatts, is reserved to allow a chip to be activated.
Relationship: contrasting
Domain: Hardware
Sentence 1: When F is very low (in the order of 0.1%), all the protection mechanisms reduce the probability of incurable fault-occurrence (IFO) in the protected router by a factor of six, which corresponds actually to the ratio N/NB.
Sentence 2: when F increases above 10%, the ROBUST design provides considerably higher reliability improvement than the BulletProof and Vicis, which drop considerably.
Relationship: contrasting
Domain: Hardware
Sentence 1: The inclusion of a scheduler into MSim provides the users with the full tool chain, which can transparently transform normal application executable (e.g., the one compiled by gcc that is unaware of memcomputing) into the one that utilizes the potential memcomputing resources.
Sentence 2: the scheduler itself is optional and users have the freedom to make use of the MSim s microarchitecture level simulation engine indepen­dently if desired.
Relationship: contrasting
Domain: Hardware
Sentence 1: HLS tools also allow the exploration of different micro-architectures since the creation of RTLs with different latency/throughputs and hence different control/computation structures is now much easier.
Sentence 2: the use of HLS creates the need for an automated flow to ensure the correctness of the synthesizable SLM that is the input to HLS and the RTL generated from HLS.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is due to the large reduction in sleep transistor area Time (secs) [Log Scale] 100 10 1 G1 G2 G3 G4 G5 G6 G7 G8 G19 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G24 G20 G25 G21 G26 G22 G27 G23 G28 (3247 to 153).
Sentence 2: the BP technique produces large gnd reductions in the sleep transistors total area.
Relationship: contrasting
Domain: Hardware
Sentence 1: PC / PC EVAL PC / F F F EVAL EVAL (a) (b) (c) Figure 1: Dynamic function blocks: (a) Footed with separate controls (b) Footed with uni.ed control (c) Non-footed pipeline protocols, and the models are then placed in a partial or­der.
Sentence 2: there are several key differences between our work and theirs.
Relationship: contrasting
Domain: Hardware
Sentence 1: To complete a benchmark involving interprocessor communication, topology (a) re­quired, as expected, less clock cycles, with about a 10% advantage due to lower access latency towards shared de­vices.
Sentence 2: 11x11 ×pipes switches have a maximum working frequency of approximately 780 MHz, while 5x5 switches can reach 925 MHz (a 19% gain).
Relationship: contrasting
Domain: Hardware
Sentence 1: CICA Porto Alegre, 90035-190, Brazil +55 51 33167036 Sevilla, 41012, Spain +55 51 33163382 erika@inf.ufrgs.br +34 955 056 666 andradejr@eletro.ufrgs.br luba@imse.cnm.es ABSTRACT Analog BIST and SoC testing are two topics that have been extensively, but independently, studied in the last few years.
Sentence 2: current mixed-signals systems require the combination of these subjects to generate a cost-effective test solution for the whole SoC.
Relationship: contrasting
Domain: Hardware
Sentence 1: [7] suggest tying commonly­gated .ip-.ops together by fake nets; this biases the placer to place such .ip-.ops closer together, hence reducing the wiring overhead of gating logic.
Sentence 2: the possible in­crease of signal wire length (not counting the fake nets) is not mentioned in [7], and no empirical data on realistic bench­marks are given.
Relationship: contrasting
Domain: Hardware
Sentence 1: Kumar et al [5] present a technique to bridge mismatches using supervisory control theory, while Tivoli et al [7] present adaptor synthesis, where an adaptor is generated to control a multi-component real-time system such that given timing as well as functional requirements (expressed as automata) are met.
Sentence 2: these approaches are also inapplicable to SoC construction.
Relationship: contrasting
Domain: Hardware
Sentence 1: Another set of work migrates the write-intensive cache blocks to other cache lines in the same/different cache set or in the SRAM in order to reduce the average write frequency of the STT-RAM cache lines [4].
Sentence 2: there exist intrinsic limitations in both approaches, which cannot be resolved independently The static optimization decisions are made at compile time without run-time information, thus compiler may generate misleading hints to the hardware.
Relationship: contrasting
Domain: Hardware
Sentence 1: By over-sampling the input signal, S. ADCs achieve high per­formance through noise-shaping.
Sentence 2: oversampling Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: contrasting
Domain: Hardware
Sentence 1: the output node of buffer S) of sinks 1 and 16 are practically independent of each other.
Sentence 2: if the link a is added between the sinks 8 and 9, even the nominal delays of sinks 1 and 16 become somewhat corre­lated due to the fact that both the sinks now have more than one source to sink paths and both sinks share the S .
Relationship: contrasting
Domain: Hardware
Sentence 1: From Figure 7(a), we can see that CORONA outperforms all net­work due to its enormous channel bandwidth of 2.56 Tbps as compared to PROPEL which provides only 0.16 Tbps, a 16X reduction.
Sentence 2: pROPEL o.ers only 15% lower throughput than CORONA with a signi.cant reduction in optical hardware and network cost.
Relationship: contrasting
Domain: Hardware
Sentence 1: Therefore, the key reason that the native system runs fast is that it performs in-place updates to the real in-memory data, without explicitly dupli­cating the data like logging or COW does.
Sentence 2: in-place updates are hard to implement in most previous NVRAM­based persistent memory designs [12, 13, 44, 45], which main­tain persistence in a single-level memory.
Relationship: contrasting
Domain: Hardware
Sentence 1: Nowadays, the ma jor drawback for going asynchronous is that they are di.cult to design, and oppo­site to the synchronous counterpart, the level of maturity of existing CAD tools for asynchronous design is still insu.­cient.
Sentence 2: in the last ten years several research groups around the world have developed CAD tools for the synthe­sis and veri.cation of asynchronous circuits which represents the .rst step in .ling the gap [1, 17, 20, 10, 5].
Relationship: contrasting
Domain: Hardware
Sentence 1: Sinan Kaptanoglu Actel Corporation 2061 Stierlin Court Mountain View, CA 94043 sinan.kaptanoglu@actel.com because it provides both a high quality CAD flow and a parameterized routing architecture generator, which are convenient for architecture studies.
Sentence 2: the experimental approach could be time-consuming and the results obtained are limited by the CAD tool and the benchmark suite.
Relationship: contrasting
Domain: Hardware
Sentence 1: 10), in spite of the fact that components due to SCE and NWE have been removed.
Sentence 2: comparisons of the s of VT mismatch (.VT) of neighboring devices in an ensemble to the sVT of these same devices demonstrate that these intrinsic fluctuations, including components not dependent on area, are random across the entire range of device dimensions and body bias values, for both NMOS and PMOS (Figs.
Relationship: contrasting
Domain: Hardware
Sentence 1: Both IF .lters are of 2-pole Tchebyscheff type, and using a combi­nation of SMDs, integrated capacitors and integrated resis­tors, the performance is borderline.
Sentence 2: keeping the IF .lters inside the MCM has the advantage of less noisy signals since the long lines going out and in the MCM are suppressed.
Relationship: contrasting
Domain: Hardware
Sentence 1: The AduC84x was a good all-round option with five parameters tops in their field compared to the rest, but in terms of the afore-mentioned accuracy parameters, the MSP430 had more: the best ADC sampling rate (2730 Hz) and reference-voltage drift (18 ppm/ºC), which were crucial for accuracy.
Sentence 2: its gain-drift (15 ppm/ºC) and offset-error (± 2mV) parameters are the worst by comparison, but with calibration the offset error could be overcome, and the gain can be kept to a minimum.
Relationship: contrasting
Domain: Hardware
Sentence 1: In Figure 10(a), {v1,v2,v3}are the third kind elements of the horizontal CLS s. If not consid­ering them as parts of s, we have U (s)= {e2} and D(s)= {e1}.
Sentence 2: even C(U(s))=1=C(D(s)), moving s up must add a new via connection, v4, to make all line segments connected, which increases cost as shown in Figure 10(b).
Relationship: contrasting