sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Specifically, the PPS are the solutions to the power-performance optimization problems under uncertainty that have the general form such as: min Q a() P st.. Pr{ D < Do} = ß This problem minimizes the value of the power at a high quantile (a) of the power distribution subject to a probabilistically defined timing constraint which is to be met with the probability (confidence level) of ß.
Sentence 2: here, a quantile function is defined as an inverse of the cumulative distribution function: a() = min{ p | Pr( P = p) = a} QP PPS encodes design solutions that lead to minimum power and delay at a given yield.
Relationship: reasoning
Domain: Hardware
Sentence 1: The connection on M1 requires vias from pins A and B to M1 and routing over the A and/or B positions on M2 or higher layers will be possible.
Sentence 2: in case of the U-V con­nection, vias must be made from the pin positions to M4; no wire on M1, M2, or M3 can cross over the positions of pins U and V. direct short connections at lower layers are more desir­able.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, given that datacenters consume several billion kilowatt hours of energy every year [50], it has been shown that the 3-year operating energy costs of today s datacenters equal thecapital acquisitioncosts[33].
Sentence 2: it may now be acceptable to incur a slightly higher cost-per-bit whenpurchasingDRAM aslong asitleads to signi.cantly lower energy footprints during operation.
Relationship: reasoning
Domain: Hardware
Sentence 1: We also assume that all currents sources are positive, with refer­ence directions away from the grid, into the circuitry below it.
Sentence 2: in general, we will assume that certain local and global constraints are speci.ed, which may be represented succinctly as: 0 =Ui(t) =Ic, .t (1) Given such constraints, one can formulate the veri.cation problem as: under all current waveforms that satisfy the constraints, check if the grid voltages satisfy the user speci­.cation, i.e., check if the grid is safe.
Relationship: reasoning
Domain: Hardware
Sentence 1: As function A does not .t completely into the cache anymore, e Sc  2.3 Categorization of Cache Behavior it gets removed fromwhen loading function D. form: instead of using a next pointer to determine the posi­tion where replacement is done, we arrange the cache blocks according to their age of loading.
Sentence 2: when a replacement is done, the new blo cks are added at the place of youngest age.
Relationship: reasoning
Domain: Hardware
Sentence 1: Now the lengths of the k wires have to add up to m, while the lengths of the (n - k)wires have to addup to (1/.
Sentence 2: - 1)m. Without loss of generality, let us take the k wires out of n that are at logic 1 and index them from 1 to k.Also the (n - k) wires that are at logic 0, are indexed from (k +1) to n. the numerator in Eqn.
Relationship: reasoning
Domain: Hardware
Sentence 1: (ii) The Table 2: Insertion and Promotion (Reuse) Strategy (a) Demand Request (b) Prefetch Request  State of Memory Access Map Init / Waiting Prefetch Access Insert Reuse Mostly 7 Mostly 7 0 No Update 6 0 State of Memory Access Map Init / Waiting Prefetch Access Insert Reuse Mostly 7 Not Appear No Update Not Appear Not Appear Not Appear implementation cost is reasonable because it shares a data structure with DA-AMPM.
Sentence 2: pA-MAIP does not con.ict with the DA-AMPM because it only refers the mem­ory access map.
Relationship: reasoning
Domain: Hardware
Sentence 1: 4), and correspondingly decreases the AND, OR, and NOT gates that would have otherwise be used to represent the eliminated equations as disjunctions of conjunctions of formulas.
Sentence 2: the increase in the number of ITE-trees by 2.5 51×, with the average depth of ITE-trees more than doubling for most of the bench­marks, and the maximum depth usually increasing by 2 13×.
Relationship: reasoning
Domain: Hardware
Sentence 1: There­fore, A is the most yield-preferred, followed by B, and then C. For the same reason, we have the priority order of D, E, F. Ev­ery redundant-cut via has a fat version with a higher priority.
Sentence 2: we have 6 fat redundant-cut vias with the highest priority, and 6 normal redundant-cut vias, plus 1 fat single-cut via with the lowest priority, 13 yield-preferred vias in total in the candidate list.
Relationship: reasoning
Domain: Hardware
Sentence 1: Furthermore, compared with the ARM10 executing at 325 MHz, the MicroBlaze warp processor is on average 1.3X faster while requiring 26% less energy.
Sentence 2: while the MicroBlaze warp processor is not the fastest nor the lowest energy alternative, the MicroBlaze warp processor is comparable and competitive with existing hard-core processors, while having all the flexibility advantages associated with soft-core processors.
Relationship: reasoning
Domain: Hardware
Sentence 1: In a BWT every node has degree three except the root of each tree (which has degree two).
Sentence 2: a BWT has 2(2n+1 - 1) nodes for a binary tree of height n. strings of m > plog2 2(2n+1 -1)l bits are required to represent each node uniquely (minimum m is n + 2).
Relationship: reasoning
Domain: Hardware
Sentence 1: Furthermore, since the variations in W1 and W2 and the mean values are same, we must have s1 = s2.
Sentence 2: it then follows that for all vectors u =[u1,u2], which characterize the uncertainty ellipsoid, we have (P1/2 u)1 = (P1/2 u)2 and the variational term in (20): K1(P1/2 u)1 K1W10 (P1/2 u)2 - =0 W2 W20 20 the ellipsoid uncertainty model easily captures the effects of correlations between random variables and incorporates the same in the optimization procedure.
Relationship: reasoning
Domain: Hardware
Sentence 1: A typical micro­architecture re-configuration latency, the duration between the time a decision is made to change the micro-architectural configuration and the time of actual configuration, takes up to tens of clock cycles [16].
Sentence 2: a state transition time in the CTMDP model of the processor takes t(s, s ) time (= max (tDVFS, tARCH)), where tDVFS is the transition time of dynamic voltage and frequency scaling (DVFS), and tARCH is the micro-architecture transition period, when system transits from state s to s .
Relationship: reasoning
Domain: Hardware
Sentence 1: acell)g(acell, a) 9. acell · w(., acell, a, M, A)] .
Sentence 2: (25) from (23), (24) and (25), the node capacity grows with the number of receiving antennas M. Furthermore, because the terms in these equations do not depend on n, the node capacity does not decrease with n. Note that our channel matrix Hj (i) incorporates the decay with distance, i.e., (1+rj 1 (i))a , which is the large scale representation of the channel.
Relationship: reasoning
Domain: Hardware
Sentence 1: The variations of Vdd and T for the whole chip are within ±10%.
Sentence 2: for the purpose of circuits timing analysis, we select .ve representative operating conditions with di.erent combinations of Vdd and T , i.e., high Vdd and high T (HH), low Vdd and low T (LL), high Vdd and low T (HL), low Vdd and high T (LH), normal Vdd and normal T (NN).
Relationship: reasoning
Domain: Hardware
Sentence 1: Besides, having the principal tracking entry h at T12 becomes also redundant when H is a resident of T12.
Sentence 2: in particular, upon accessing T12, if we look upits L2bank andTR tableconcurrently wewouldhit at the L2 bank directly without any need for the principal entry h. a .rst optimization (O1) for CE wouldbenottocacheany tracking entry(principal or replicated) for a cache block that is mapped to its SHT and to always lookup concurrently the L2 bank and the TR table at the SHT.
Relationship: reasoning
Domain: Hardware
Sentence 1: In case of packet loss, if the attacker still count to N, a wrong packet will be dropped.
Sentence 2: for example, in a N = 12 video 0 0 50 100 150 200 250 stream, if a B-frame is missing, the cycle will become N = 11. frame sequence number by counting to N, the dropped packet will not be an I­frame packet and this chain effect will continue and affect the the Figure 7: local peaks with different neighborsize above algorithm, we collect 666 video traces ([2]) with different following packets.
Relationship: reasoning
Domain: Hardware
Sentence 1: However,itismuhlesslearwhatanintuitiveandgenerally aeptabledefnitionoftimingfailureouldbe.Inthispaper, wedefneanddisussseveralalternatives.
Sentence 2: foruntimediruits,themirroringisjustswappingthe inputsandtheoutputsofamodule.But,itismuhmore ompliatedfortimediruitsifthedefnitionofthemirror­ingin[1]issimplyextended,anditseemsdiÆulttoobtain animplementationofsuhamirrormodule.inthispa­perwedefneitbyinput/outputswappinginthesameway astheuntimedase.Then,oneofthemainproblemsisthat themirrorpropertydoesnotholdingeneral.Dependingon thehosendefnitionoffailure,itmayormaynotbepossible toimplementaonformanehekingproedurebymirroring.
Relationship: reasoning
Domain: Hardware
Sentence 1: The number and the depth of the cones in the actual architecture has to be tailored to the algorithm to be implemented, since the dependencies can signi.cantly vary from algorithm to algorithm.
Sentence 2: multiple instances of the template may exist, and each one is uniquely characterized by: (1) the size of the output window of each cone; (2) the number of levels in which the computation is divided or, equivalently, the number of iterations that are performed at once by each cone.
Relationship: reasoning
Domain: Hardware
Sentence 1: The local clock wires and buffers contribute 5% and 7%, respectively, of total dy­namic andglitchpowerin clocktrees, whereas the sequentials con­tributeto23% ofthetotaldynamicpowerindatapath.
Sentence 2: in case ofpower optimization for datapaths, itisimportant topay at­tentionto combinationallogic as well andtherefore,those are often designed with more manualinterventions than synthesizedblocks.
Relationship: reasoning
Domain: Hardware
Sentence 1: 2.1 Via-First TSV In the via-.rst method, TSVs are fabricated before the transistors are patterned in silicon, i.e., prior to front-end-of-line (FEOL) [9, 10].
Sentence 2: tSVs fabricated with the via-.rst technique do not pass through the metalization layers, as depicted in Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: Assuming Kwire >> KILD, if the wires in a wire layer are in the direction of y, then the heat transfer along the wires causes a significant heat flow in y di­rection.
Sentence 2: the thermal conductivity in y direction of combined ILD layer and wire layer can be expressed as: (t +t ) (16) K K..tf eff , y wire wire wire ILD wire where fwire is the volume fraction of wires in the wire layer.
Relationship: reasoning
Domain: Hardware
Sentence 1: For instance, as b1 and a1 are all under the control of predicate b0 <a0 in Figure 1(a), c0 de.ned as b0 <a0 is the iSel of two ITEs a1 and b1 shown in F .
Sentence 2: enforc­ing constant constraints on iSels of F can be regarded as restricting the execution on a subset of control-.ow paths in the program.
Relationship: reasoning
Domain: Hardware
Sentence 1: The exact approach is also based on set sampling, and uses a number A of ATD structures representing the A di.erent associativities from 1 to A.
Sentence 2: in the exact approach, we use a group of A ATD structures, {ATD(1), ATD(2),  Figure 4: The COOP architecture: the grey boxes are the major extra hardware logic required by COOP on top of the SLLC with 1-bit RRPVs.
Relationship: reasoning
Domain: Hardware
Sentence 1: 2.2 When the ack comes from a different node to the one provided by the sharing code associ­ated with the memory line, it means that some­thing preceding this ack took place.
Sentence 2: a message is sent to the source of the ack, in­forming that the ack could not be observed at that time and a re-send for the message must be performed.
Relationship: reasoning
Domain: Hardware
Sentence 1: The first sequence corresponding to input = 0 , as discussed previously, consists of 673 0 s, 579 1 s and 8747 2 s. The second input sequence consists of 945 0 s, 8160 1 s and 895 2 s. The third input sequence consists of 9523 0 s, 429 1 s and 47 2 s.  Seq for input = 0 Seq for input = 0 Seq for input = 1 Out Seq for input = 1 Out Seq for input = 2 Seq for input = 2 Seq for input = 3 Input Input (a) (b) Fig.
Sentence 2: 10 Stochastic computational model for (a) a ternary inverter (b) a quaternary inverter each sequence can be described by the following expression: (11) ).
Relationship: reasoning
Domain: Hardware
Sentence 1: All ranges shall be translated and normalized to the interval [0,1].
Sentence 2: a translation vector v(t) has to be calculated to move the lower bound of the nd extended state space variable ranges ri to 0 and to scale them to the interval [0,1] by factors .i: )-1 .i = (ri -ri(19) []T v(t) = -r1 · .1 .
Relationship: reasoning
Domain: Hardware
Sentence 1: This is relatively large overhead and it causes signif­icant throughput degradation because the register access is blocking operation.
Sentence 2: reducing the number of the Table 3: Specs of machines for the performance eval­uation Router CPU Intel(R) Core(TM) i7 M620 (2.67GHz, dual core) Memory 8GiB, DDR3 (1333MT/s) NIC Adapter Intel(R) 82577LM (1 port) register access will improves the forwarding throughput.
Relationship: reasoning
Domain: Hardware
Sentence 1: The minimum adder-step realization of a target constant ti in­cludes ilog2S(ti)l operations in series, where S(ti) denotes the num­ber of non-zero digits of ti in its CSD representation.
Sentence 2: hence, for a target set, T = {t1,...,tn}, the minimum adder-step of the MCM operation [11] is computed as: min_delayMCM = max{ilog2S(ti)l} (2) ti the optimization of the number of operations problem un­der a delay constraint can be de.ned as follows: DEFINITION 2.
Relationship: reasoning
Domain: Hardware
Sentence 1: It can be seen that the leakage current increases exponentially when the effective voltage over the cell exceeds one Vth of the transistors (i.e., 0.4V when it is affected by body effect) as predicted in [7].
Sentence 2: the nominal voltage drop over the cell is chosen to be close to Vth, keeping the drive and load transistors in weak inversion region.
Relationship: reasoning
Domain: Hardware
Sentence 1: The memory module without redundancies contributes to yield only if all its comprising cells satisfy the target delay.
Sentence 2: the timing-yield of the original memory module is: (R×C) Y0 =Pcell (3) In presence of N redundant columns, the memory module still contributes to yield as long as at most N columns out of the C+N available columns violate target delay.
Relationship: reasoning
Domain: Hardware
Sentence 1: Nev­ertheless, the function calls are provided with timing annotations.
Sentence 2: put, peek and get functions are still called with the polling mechanism, in which a delay or a latency is explicitly expressed for each call (i.e., nb put(const REQ&#38;, sc time&#38;), nb peek(RSP&#38;, sc time&#38;), nb get(RSP&#38;, sc time&#38;)).
Relationship: reasoning
Domain: Hardware
Sentence 1: The number of the pulse rotations and the .nal output value of the bu.er after the pulse vanishes depend on the di.erence between the rise and fall delay of a bu.er, whereas the oscillation period of a simple ring oscillator depends on the sum of the rise and fall delay[5].
Sentence 2: we can calculate the rise and fall delays of a bu.er and can monitor the process variabilities of PMOS and NMOS devices independently.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3.2 Morphing P-T-VPack for Fault Tolerance In the optimization for fault-tolerance, the fault rate at a global interconnect is proportional to the average sensitivity of SRAMs along its routing.
Sentence 2: to minimize the overall fault rate (shown in (2)), a fault-tolerant clustering should encapsulate in­terconnects with high sensitivities inside CLBs, which results in a very similar objective to power-aware clustering.
Relationship: reasoning
Domain: Hardware
Sentence 1: while the value of REF2 (reference voltage level for the second comparator) is kept at a value between VDD/2 and VDD (~ |Vth,p|+Vth,n).
Sentence 2: when VVDD reaches the value of REF1, MSSTART goes high and when VVDD reaches the value of REF2, MSEND goes high.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then, the .rst two lines of the truth table can be embedded with respect to reversibility as shown in the rightmost col­umn of Table 1(a), but no unique embedding for the third truth table line is possible any longer.
Sentence 2: an additional output (and therewith an additional circuit line with con­stant input) must be added as depicted in Table 1(b).
Relationship: reasoning
Domain: Hardware
Sentence 1: Since the maximum value of kw corresponds to the maximum number of inputs of a logic gate, we may assume hmax = kw so that the time needed in addition of a vertex w to Front is O(kw hmax).
Sentence 2: the total time complexity is O(m hmax), since no vertex is added to Front more than once and .w.V kw = m, where m = |E| is the number of edges of a given circuit graph G=(V,E).
Relationship: reasoning
Domain: Hardware
Sentence 1: With the redundant condition checking, 2. is scheduled before 4. schedulings, which implicitly checks the enabledness (since a symbolic behavioral state includes the information of symbolic suspended statuses).
Sentence 2: for SystemC designs, we can now 16 schedulings are detected as redundant and our formal engine will define a simplified and straightforward independence relation as then have to execute the symbolic simulation for the remaining 8. follow, where .... is the set of all possible suspended locations of Assume processes (wait statements and entries of processes) and .(...)
Relationship: reasoning
Domain: Hardware
Sentence 1: SIGMETRICS 2000 6K)0 Santa Clara, California, USA &#38;#169; 2000 ACM 1-58113-194-110010006...$5.00 such as automatic memory management, a support for mul- tithreading, the existence of architecture-neutral intermedi- ate codes (bytecodes), etc.
Sentence 2: it is very interesting to see whether Java applications share similar characteristics with the traditional applications or not.
Relationship: reasoning
Domain: Hardware
Sentence 1: To model the fact that nets with higher degree have more probability to be combined, we define a 2m-element weight vector W(n) to associate this probability with the degree of newly generated nets.
Sentence 2: for the combination of external i-terminal net from m blocks with j-terminal net from another m blocks, there are P ·m ·De ( j) m m W (i +j -2) ·P ·m ·De (i) · m+1m m .
Relationship: reasoning
Domain: Hardware
Sentence 1: Spare cores Due to our methodology, comparing runs using sep­arate commercial workload checkpoints with different numbers of OS-visible VCPUs is impractical.
Sentence 2: for the throughput exper­iments, we model spare cores using the overcommitted technique with oracle spin detection and without charging overhead for stor­ing, migrating, or switching VCPU state.We do properly simulate a sevenprocessor system with our microbenchmarkforlatency and fairness experiments, since our microbenchmark(discussedbelow) is very regular andisdominatedby user code.
Relationship: reasoning
Domain: Hardware
Sentence 1: Recall that we have normalized the variation range of every parameter to [-1,1], and have considered 14 parameters.
Sentence 2: if a slack fails somewhere in the parameter space, then its robustness r must fall between rmin =0 and rmax (based on L2-norm), where: 14 rmax =(±1)2 3.74 (24) i=1 Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: Currently, 0% we exploit this recon.gurability in order to guarantee parametric Application level real time constraint system yield.
Sentence 2: we can still use faulty chips or components Figure 7: The energy overhead associated to pro­ that would have to be discarded, because they do not meet the cess variability between the corner-point implemen­ parametric speci.cations.
Relationship: reasoning
Domain: Hardware
Sentence 1: Clock divider Gate-level model Transistor-level model Mismatch Clock-to-output time Output goes low-to-high 15.4 14.5 +6.2 % Clock-to-output time Output goes high-to-low 21.3 20.0 +6.5 %  ¯ Q switches only after U1, U3 and U5.
Sentence 2: the fact that the low-to-high propagation delay is almost for the high-to-low transistion, the critical twice high-to-low propagation delay can be theoretically ex-path goes through 4 components (U1, U3, U5 and U4) instead plained.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since .= 0, 1 = j = n, for all raised hyper­ j planes, then .j = 0for 1 = j = n.Given that 0 = Yj = 2, for 1 =j =n it is easy to see that for any corner Cin the modi.ed t system of coordinates, 1 =t =2n , D(C) =P and equivalently F t DF (Ct) = P for any corner Ct in the original system of coor­dinates.
Sentence 2: the output delay hyperplane satis.es the second criterion of section 3.1.1.
Relationship: reasoning
Domain: Hardware
Sentence 1: The first function stringToArray takes a string from the file (file_in.txt for our example) that contains the size N (8 for the example above) following by N data items and converts the string (composed by 9 lines for our example) to an array of N unsigned integers with the data items.
Sentence 2: for our example, there are 8 elements in the array with data items (12345678, 87654321, 38627, 0, 398213329, 77, 11, 89) shown above.
Relationship: reasoning
Domain: Hardware
Sentence 1: We note that the results for design I12 in Table I differs from the results for the rest of the designs since this design required significant rework (size reduction) toward the end of the project; however the clock pin locations were maintained, and additional wire was required to connect these pins from their original locations to the new locations of the clocking circuitry.
Sentence 2: this result is not expected to reappear in future designs.
Relationship: reasoning
Domain: Hardware
Sentence 1: The MUX of position i connects the data input/output di to the regular unit Ui, if this unit is fault-free, and to one of the k units Ui+1, Ui+k if Ui is faulty.
Sentence 2: each of the signals R0, R1, Rn-1 is used to enable the counter of one of the MUXes and it is also used as entry to the equations (1), (3).
Relationship: reasoning
Domain: Hardware
Sentence 1: The target architectures do not have data or instruction cache, but have multiple external memories feeding a single FPGA in parallel; internal to the FPGA, signi.cant instruction-level parallelism is exploited on the computation.
Sentence 2: although this is a novel com­puting platform, it nevertheless shares commonalities with more conventional ones in which either multiple memories feed a single or multiple functional units in parallel.
Relationship: reasoning
Domain: Hardware
Sentence 1: On the other hand, another possible way, compatible with the computational intelligence techniques is to contribute to the efficiency of variation-aware analog sizing by developing more efficient MC-based yield estimation techniques.
Sentence 2: this paper focuses on a fast, accurate and general MC-based yield estimation technique for analog circuits with a reasonable accuracy requirement (high-sigma yield estimation is out of the scope of this work, as in variation-aware analog sizing we often require a reasonably good accuracy).
Relationship: reasoning
Domain: Hardware
Sentence 1: However, the problem is that there may not be suf.cient PMs of smaller types to cover all the parts of all the virtual memories.
Sentence 2: an estimation of the number of smaller PMs (which are required for the rest of so­lution) is needed; if this estimation is larger than the smaller PMs available, the algorithm should use more of the current type with the penalty of creating leftover, which is discussed in the third step.
Relationship: reasoning