sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Increasing spare lines further increases endurance of baseline to 9% (for 640K lines) and 25% (for 6.4M lines) at the overhead of 0.16GB and 1.6GB respec­tively.
Sentence 2: relying only on spare lines to mitigate endurance related wear-out is ineffective and more expensive than wear lev­eling.
Relationship: reasoning
Domain: Hardware
Sentence 1: Only this part of matching needs to be regenerated and remapped in the next iteration.
Sentence 2: when m =1, the expected number of retries to map one input to one output is l1/(1 - d)l,sincetheprobability of.nding adefect-freeswitchis 1 - d. we can use the following recursive formulation for Ng (m): 1+ Ng (md),m> 1 Ng (m)=1 (3) l 1-d l,m =1 Applying the recursive formulation k times, we have Ng (m)= k + Ng (mdk).
Relationship: reasoning
Domain: Hardware
Sentence 1: So, inverter-1x cannot be swapped by inverter-2x changed to dijk which is the change in the delay of gate j and two or vice versa and each one of them has their own individual adjacent arcs in path i when it is swapped by version k. Figure 2 shows a gate which is in two different timing paths.
Sentence 2: .. ... ... ...... .. .
Relationship: reasoning
Domain: Hardware
Sentence 1: 2n-4 +2n-3 + k-1 26i+2 - k-2 26i+5 for n =6k +3,k = 1 i=0 i=0 Figure 1: The distribution of signi.cant bits in 18-1 2n-1+1 available much earlier than the output Xh of the 3-moduli converter.
Sentence 2: the residues x2, x4 as well as the cor­rective constant (available at the design time) can be added separately and scheduled in parallel to the computation of Xh, thus forming a new component L " 4, so that each of ad­ditions needed to obtain L " 4 and Xh requires three operands only.
Relationship: reasoning
Domain: Hardware
Sentence 1: Although a route on layer 2 may detour even if a via assignment is detour-preventive, the route is expected to be short and seldom detour.
Sentence 2: the wire length of a net on layer 2 is evaluated only by the Manhattan distance between the via vi and the ball bi of the net, which is denoted by d(vi) and de.ned as follows.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then, even if the soft constraint that CMP2 is scheduled earlier than MUL2 is not satis.ed, MUL2 may still be avoided if it is scheduled after CMP1.
Sentence 2: an exact eval­uation of the energy saving for such a soft constraint will require a full pro.ling of all possible value combinations in a group of con­dition operations.
Relationship: reasoning
Domain: Hardware
Sentence 1: Increasing the number of pictures from a variety of aspects of the object can solve the problem; however, a bottleneck of data volume will be encountered.
Sentence 2: we propose a system based on the image-basedrendering (IBR) technique and stereoscopic display for multipleusers that allows multiple groups of users at remote locations tonaturally share a 3D image of a real object (Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: So if w(v) <_ zoos, by Lemma 1, mc(v) _< ~ + w(v) < 2~sD [] It is possible to construct a weighted hexagon graph where the greedy algorithm uses 7Ds/3 channels, while an optimal assignment using D3 channels exists.
Sentence 2: the performance ratio of the greedy algorithm is at least 7/3.
Relationship: reasoning
Domain: Hardware
Sentence 1: Add Wire : To propagate a solution .v at position v to an up­stream position uwith no branching point in between, the new so­lution .u can be computed as C(.u)[i]= C(.v)[i]+ Ce[i], W(.u)= W(.v), (1) Q(.u)[i]= Q(.v)[i] - De[i], where e =(u,v) and Ce[i] denotes the capacitance of edge e in layer i and De[i] denotes the Elmore delay of edge ein layer i for 1 = i = t. Clearly, in a solution, C,Q will be updated only for wires at the same layer.
Sentence 2: no wire tapering is allowed which it is desired as shown in [12].
Relationship: reasoning
Domain: Hardware
Sentence 1: Activatingtheabnormalpredicates in this core and allowing at most one of them to become 1 does notyielda correction forboth outputs: if gate D is changed, only the upper output is corrected; if gate C is changed, only the lower output is corrected.
Sentence 2: a next unsat core is returned as shown inFigure 3(b).
Relationship: reasoning
Domain: Hardware
Sentence 1: Experimental results show that an updated {16] set of test sequences obtained after removing a flip-ltop l}om the scan chain detects all or most of the detectable circuit faults, and that only small numbers of faults require any test generation.
Sentence 2: all or most of the faults are detected by a test set generated [171 for a circuit with a higher level of scan, for which the test gen- eration complexity is lower.
Relationship: reasoning
Domain: Hardware
Sentence 1: In addition, C3 and C9 are dominated by C18, and these equivalence classes include the faults 11/1 and 15/0 from f obs .
Sentence 2: considering the equivalence classes with dominance rela­tions to the ones dominated by Cobs provides a way by which to ensure that faults from f obs would be included in the set of candidate faults.
Relationship: reasoning
Domain: Hardware
Sentence 1: While this may seem to be an obvious result of datapath decomposition, both our explorations, as well as the results of other authors [18] show that such advantage often comes with major area/power consumption penalty.
Sentence 2: the more important conclusion from Table II is that RNS-based implementation yields uniformly higher performance at no or moderate area/power penalty, often along with a signi.cant improvement in power ef.ciency measured as Power-Delay product.
Relationship: reasoning
Domain: Hardware
Sentence 1: 7(a)), the conventional architecture achieves a minimum power con­sumption of 324µW at (Vdd-crit =1.35V , Vb =0.5V ), while the ISR-ANT architecture achieves a minimum power con­sumption of 128µW at (Vdd =0.95V , Vb =0.3V ).
Sentence 2: the EC block operates at lower voltage, Vdd-EC =0.6V .ISR-ANT achieves power-reduction of 60% over the conventional system.
Relationship: reasoning
Domain: Hardware
Sentence 1: (001, 000)) for the corresponding PDF on c246x of the circuit (a).
Sentence 2: g = off( f ), because, from De.nition 5, L(P) is obtained bymoving all the inverters on P to the primaryinput of P. if a vector pair whose second vector is v is applied to C, all the off-input of P meets the condition of 3.3.
Relationship: reasoning
Domain: Hardware
Sentence 1: DVSAM operates by aggressively trying to consume, at any given time, all the aging guard-band that would be otherwise available.
Sentence 2: the design assumes the existence of aging sensor cir­cuits that reliably measure the guard-band available at all times [2, 7, 17, 18, 20, 28, 31] (Section 4.3.2).
Relationship: reasoning
Domain: Hardware
Sentence 1: As one can see from Section II, the reluctance realiza­tion process introduces additional nodes and different cir­cuit elements.
Sentence 2: we need to measure the simula-  1.4 1.2 1.0 0.8 0.6 0.4 eral analysis tools, modi.cations on those tools to handle reluctances are avoided.
Relationship: reasoning
Domain: Hardware
Sentence 1: V. To express this as a linear program, we have a constraint dt(v)= dt(u)+Cu,v to denote that the cost of shortest path from any node v to destina­tion t is less or equal than the shortest path from node u plus the cost of a direct path from u to v. The destination node t initially re­ceives a value dt(t)=0.
Sentence 2: we can obtain the following linear programming formation: minimize L.v.V dt(v) subject to dt(v) dt(t) = dt(u)+Cu,v ,.{u,v}.
Relationship: reasoning
Domain: Hardware
Sentence 1: The passive subgrid is .rst isolated from the rest of the grid by removing (i.e., make into an open-circuit)the connections from all port nodes to ex­ternal nodes.
Sentence 2: the isolated subgrid can be represented in the ..-domain by: ([ ][ ])[ ] G22 G23 C...... 0 ........(..) + .. G.. 23 G33 0 C...... ........(..) [] ........(..)+ .. ' (..) = (28) 0 v .... - .. 1 () ......1 = vv .... ...... .... ..+ .. 01 1 v ...... - 1 ......2 = (v) (30) .... ...... .... v ..+ .. 01 1 (v v)2 ...... .... .... + .... 1 11 ...... = v ...... .... .. 11 .... .... where ..and ..are the (.., ..)..h elements of M0 and M1, 01 respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: The number of scan chains in DBIST mode can be larger than the num­ber of scan chains in deterministic ATPG mode, on the average, by a factor of 20 - 30, because DBIST chains do not require tester pins.
Sentence 2: clenbist is, on the average, 20 - 30 times smaller than Clendet.
Relationship: reasoning
Domain: Hardware
Sentence 1: The degradation ofbene.tin L2cache misses observedby vpr in Figure 4 is also due to con.icts in non-merged data.
Sentence 2: several applications could bene.t even more from a hybrid scheme thatdynamicallydividesthe cacheintotwo segments -one that performs merging and another that uses conven­tional addressing.
Relationship: reasoning
Domain: Hardware
Sentence 1: First,theworkingsetcanbelargerthantheaggregatesizeofthe blockstrackedbythecacheandtheEAFtogether.Weshowthatthis casecanbehandledbyusingthethrash-resistantbimodalinsertion policy[35]forlow-reuseblocks,whichensuresthatafractionof theworkingsetisretainedinthecache.Second,theworkingset canbelargerthanthecachebutsmallerthantheaggregatesize oftheblockstrackedbythecacheandtheEAFtogether.Inthis case,thrashingcanbemitigatedbyrestrictingthenumberofblocks predictedtohavehighreusetoavaluesmallerthanthenumberof blocksinthecache.WefindthatimplementingEAFusingaBloom filterenablesthiseffectbyforcingtheEAFtobeperiodicallycleared whenitbecomesfull.DoingsoresultsintheEAFpredictingonly aportionoftheworkingsettohavehighreuse,therebymitigating thrashing.WedescribetherequiredchangesthatenabletheEAF tomitigatethrashingindetailinSection2.3,andevaluatethem quantitativelyinSection7.4.
Sentence 2: ourmechanismcanreducethenegativeimpactofboth cachepollutionandthrashingusingasinglestructure,theEvicted-AddressFilter.
Relationship: reasoning
Domain: Hardware
Sentence 1: 4 illustrates a simpli.ed model of bonding and package parasitics for two adjacent wires [4].
Sentence 2: the instantaneous current iDD due to digital switching of logic gates produces a voltage drop, which af­fects the on-chip digital supply VDD, and propagates to the adjacent wires through both capacitive coupling due to the capacitance between wires C and inductive coupling due to the mutual inductance represented by K. the analog on-chip voltage v(t) is no more equal to the external voltage vs, but it results to be a function of the voltage vs and of the digital switching current iDD and its derivative: « diDD v(t)= f vs,iDD, .
Relationship: reasoning
Domain: Hardware
Sentence 1: In fact, the relative area of memories in a cluster is de.ned by the con.guration, but it usually ranges between 50%-60% for the best con.gurations as seen in our tests.
Sentence 2: the lowest metal layers will typically have no space for routing, while the upper layers will have up to 60% of space available, thereby making over-the-cell routing possi­ble.
Relationship: reasoning
Domain: Hardware
Sentence 1: Unfortunately, there still lacks an approach that fully satisfy the mobile system requirements: the main categories of memristor state tuning circuits are either using multiple voltage pulses to step-by-step tune the memristor, which limits the tuning accuracy (e.g., ~ 5-bit precision in [19]) or using several resistors as reference, which incurs a high hardware cost such as a large number of reference resistors (for example, an 8­bit precision state tuning circuit needs about 256 resistors as reference [20]).
Sentence 2: we introduce a feedback circuit with minor hardware cost to program the memristor accurately and guarantee the accuracy of the network parameters.
Relationship: reasoning
Domain: Hardware
Sentence 1: Conductor or core is made of stranded copper or aluminium, XLPE insulation is extruded type excellent insulation and the metal sheath is typically of copper or aluminium or steel strips and is solidly earthed at both ends of the cable.
Sentence 2: cylindrical capacitor with XLPE insulation (dielectric) is formed between the high voltage conductor and the earthed metal sheath [4].
Relationship: reasoning
Domain: Hardware
Sentence 1: We note that due to the technology library used for synthesis of the benchmarks in our simulations, direct comparison with other existing algorithms by looking at the reported SRR values from the related publications was inaccurate.
Sentence 2: we also implement the following two trace selection algorithms for comparison: 1) METR: metric-based [6]1, and 2) SIM: simulation-based [3].
Relationship: reasoning
Domain: Hardware
Sentence 1: Such con.guration allows a very high electrical resistance (......) from .. to .. , and a very low resistance path from .. to .. (......).
Sentence 2: the output at .. follows the signal at ...On the contrary, when .. = 0 , the central graphene becomes p­type, forming a low resistive pp junction on the left; this makes the output at .. to follow ...
Relationship: reasoning
Domain: Hardware
Sentence 1: More im­portantly, the optimal placement HPWL of the new netlist has a value no less than the original netlist s optimal HPWL.
Sentence 2: by executing the placer on the new netlist, we can use any deviation of the new HPWL from the original HPWL as a lower bound on the deviation from optimal results for the new netlist.
Relationship: reasoning
Domain: Hardware
Sentence 1: Compared to existing architectures for GF (p) arith­metic units, we can state that our AU implementation re­quires 19.995µs per point addition at k = 160 bit occupying about 2,660 slices of our FPGA.
Sentence 2: our implementation provides a better performance at a smaller area cost with respect to [14, 15] and a competitive design concerning the architecture of [4] when balancing the di.erences between the varying FPGA types.
Relationship: reasoning
Domain: Hardware
Sentence 1: When the reference path delay is assumed to have a certain Iratio and the potential critical path delay is totally due to logic, this delay margin can be derived from [Margin + (1 - Iratio)] * [tdl]+ Iratio * [tdi] V=Vmin V=Vmin 1.0 * [tdl]+0 = 1 V=Vmin where [tdl]and [tdi]are logic and intercon­ V=Vmin V=Vmin nect delays at the minimum supply voltage respectively.
Sentence 2: the delay margin can be expressed in terms of Iratio as tdi Margin = Iratio 1 - tdl J.
Relationship: reasoning
Domain: Hardware
Sentence 1: t; (/ w;#(vpup)+ jpq) j=1 tahj C pJ t; Ap fjp )#.
Sentence 2: w2 pj=1 ta j C pJ we have  t; fjpAp j=1 ta jC pJ wp# t; (vpup)+ jpq j=1 tahj C pJ where outG(vJ={ule(v,uJEE(GJ}.
Relationship: reasoning
Domain: Hardware
Sentence 1: Notice that vertices in V0(KnHGi ) can be thought of as being in .m',since (m-ml) of their coordinates are 0.
Sentence 2: computing the vertices of V1(Kn HGi ) follows easily from V0(Kn HGi ): compute the vertices of V0(KnH)in .m', then for each such Gi vertex, set every coordinate corresponding to a current source not included in Gi to its local constraint value, yielding the vertices of V1(KnH)in .m .
Relationship: reasoning
Domain: Hardware
Sentence 1: Each entry has a read and a write signature of size 1024 bits to cap­ture the addresses accessed in a region.
Sentence 2: in addition, each entry contains a valid bit, a regionDone bit, RBI-begin, RBI-end, completedOpCount, totalOpCount (10bits eachsince there are 544 region buffer entries which is also the maximum number of memory operations in a coalesced region), and starting and ending program counter values ofa region(64bits each).a signature buffer with17 entriesis of size4.60KB.
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, if one considers a t0 < t, such that v(t) is insensitive to v(t0), then one may assume that v(t0) = 0 without a.ecting the voltages at time t. As a matter of fact, we can assume that at all time t'= t0,wehave v(t')= 0.
Sentence 2: thus, the grid can be assumed safe at all times before t0 without a.ecting the grid safety at time t. for any grid, we can assume that it was safeatsomenumber of timesteps k in the past.
Relationship: reasoning
Domain: Hardware
Sentence 1: For the three design examples described in Section 5, the average CPU time was 12.9 minutes using our Matlab implementation of the proposed method on a Windows machine with a dual-core 2.4 GHz AMD Opteron processor and 2 GB of RAM.
Sentence 2: the proposed automated design methodology provides a computationally feasi­ble means for generating tunable IMNs that would otherwise be intractable to realize using manual design techniques.
Relationship: reasoning
Domain: Hardware
Sentence 1: This efficient solution to the component integration problem presents a unique combination of features: x It implements a unified approach for the component integration that eases the integration of heterogeneous components for MPSoC design and validation at the system level by automating the integration of basic interface components for the generation of different interface sub-systems; x It provides an environment that is able to accommodate components having different interfaces and granularities and to handle complex interface sub-systems by composing user-extensible open-library components; and x It provides an automatic process for component reuse and integration, so that designers are free from the tedious and error-prone work of manual wrapper coding for each new architectural solution.
Sentence 2: they can concentrate on more critical design problems where their expertise is essential.
Relationship: reasoning
Domain: Hardware
Sentence 1: Once again, note that a rank-1 wire (e0,2,1,0) is connected to a rank­0 input of GPC2, and that a rank-2 wire (e1,2,0,1) is connected to a rank-1 input of GPC2.
Sentence 2: gPC is correctly summing bits produced by other GPCs, in consecutive columns.
Relationship: reasoning
Domain: Hardware
Sentence 1: This advantage has also been recently con.rmed for CNTFETs at a channel length of 15nm [30].
Sentence 2: since DG-CNTFETs are a type of SB-type CNTFET, it is reasonable to believe that DG-CNTFETs will maintain these advantages and out­perform scaled CMOS at 32nm and beyond.
Relationship: reasoning
Domain: Hardware
Sentence 1: Compared to a parallel radix-4 design, the lower part of the L-shaped butter.y has the same critical path delay, but a parallel radix-4 design takes only log4N cycles to complete, whereas the approach in [9] takes log2N cycles (or 1 fewer with rescheduling).
Sentence 2: the approach will generally have lower throughput than a parallel radix-4 design.
Relationship: reasoning
Domain: Hardware
Sentence 1: Introduction As manufacturing technology advances and supply voltage is lowered, circuit speed is becoming more sensitive to man­ufacturing variability, operating environment, such as supply voltage and temperature, and aging due to NBTI (negative bias temperature instability) and HCI (hot carrier injection).
Sentence 2: timing margin of a chip varies chip by chip due to manufactur­ing variability, and it also depends on its operating environment and age.
Relationship: reasoning
Domain: Hardware
Sentence 1: THEOREM2.2.AlgorithmSmall­Knowledgeperforms broadastinginO(D(l+log(n/D)))rounds.
Sentence 2: pROOF.Firstweneedtoprovethatbytransmittinga­ordingtotheassignedtransmissionnumbersinaninformed tilet,allnodeswithinrangeofatleastonenodeinthistile getthesouremessageatleastone.IfonenodeisinsetA andtheotherinsetBthentheydonottransmitsimultane­ously,henethesesetsanbetreatedseparately.Itislear thatallnodeswithinrangeofatleastonenodeintiletare withinrangeofatleastonenodeofAUB.Also,anynodes withinrangeofexatlyonenodeoftiletreeivethetrans­missionsinetheyareunafetedbyollisions.Ifanodevis withinrangeofatleasttwonodesfromAortwonodesfrom B,thesenodeshaveonseutivebordernumberswithintheir setandheneatleastoneofthemhasatransmissionnum­berdiferentfromtheothers.nodevhearsa uniquenodeinsomeround.
Relationship: reasoning
Domain: Hardware
Sentence 1: jEAi jEAi Moreover, the error may propagate forward along a timing path and accumulate to include all the maximum delta delays induced from all the aggressors.
Sentence 2: the error bound for a noisy longest path delay is equal to difference between the upper bound and the lower bound of ending net s switching window of the path: max min .tmax max min e(xi)<xi -xi .
Relationship: reasoning
Domain: Hardware
Sentence 1: This is largely because most formal meth­ods rely on intimate knowledge and explicit manipula­tion of some underlying, generic model and are typically less concerned with user-oriented representations.
Sentence 2: given a system expressed as diagram d and a property p, traditional approaches typically consist in: (1) ob­taining some behavioural model M(d)of d,such as a function, a transition system, etc.
Relationship: reasoning
Domain: Hardware
Sentence 1: Nowadays, to meet the increasing demand for computing capacity, various parallel computing architectures emerge, bringing more stringent requirement on the throughput (e.g., Tera-Hertz) of on-chip interconnects.
Sentence 2: the so­called throughput-centric interconnect designs [8], such as Networks-on-Chip (NoC) [9], have become necessary and hold more research attention.
Relationship: reasoning
Domain: Hardware
Sentence 1: At anytime, a single table entry represents only one line in a group.
Sentence 2: a handshake between the table entry and the cache line is needed and it is established as the following: (1) each cache line contains a table-entry-valid (tev) bit that indicates if the information in the corresponding table entry belongs to the line, and (2) each table entry keeps a link that remembers which line in a group is currently being linked, e.g.
Relationship: reasoning
Domain: Hardware
Sentence 1: To further reduce the runtime, we propose a DILP formulation that casts the original routing optimization problem into a decision problem.
Sentence 2: we rede.ne the objective function as follows: Minimize : 1 (32) Instead of directly searching the original objective function within the .xed maximum available set Tmax and Pmax, the DILP de­termines a feasible solution only within the minimal routing re­sources.
Relationship: reasoning
Domain: Hardware
Sentence 1: the shield signal) has propagated a sufficient distance along the bus to prevent pulse evaporation.
Sentence 2: the T1 and T2 phase of clock are determined by data signal arrival instead of shield signal arrival; that is, T1 = (D1_rep + D_hb2 + T_setup) and T2 = (D2_enc + D_hb1), respectively (these parameters are shown in Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: =0 /* Sn-1 has been corrected in Qn-1 */ compute the period estimate: Te = Pn - Pn-1 correct the amplitude : Qn = Qn + C(1/Te) done return Qn Figure 3.
Sentence 2: the Static Correction Algorithm a basic static correction in order to take into ac­count frequency changes due to an internal clock allows one to mount successfully a DPA attack.
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, for each variable u, we have the following constraint: n (Formula 1) .x u,i = 1. i1 = If two variables have overlapping lifetimes, they cannot share the same register.
Sentence 2: if both variable u and variable v have overlapping lifetimes, we have the following constraint for each register Ri: xu,i + xv,i = 1.
Relationship: reasoning
Domain: Hardware
Sentence 1: First, we .nd all biconnected components in G(D,E1).For each biconnected component recognized, we replace the vertices (de­vices) in the component with a single super-vertex while preserv­ing all external edges.
Sentence 2: as shown in Figure 4, G(D,E1) can always be viewed as a set of trees, on which each node can be a vertex (device) or a super-vertex (biconnected component).
Relationship: reasoning
Domain: Hardware
Sentence 1: (10) 4 d1 4 d2 For an LSB page, however, misreading errors are around V read1 and V read1 0 2 .
Sentence 2: the calculation of RBER is |.4| |.5| revised as: RBERLSBpage 1 |.0| 1 |.1|4 d0 4 d1 = Q0( )+ Q1( ) 1 1 (11) + Q2( )+ Q3( ).
Relationship: reasoning