sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: The plaintext P is typically gen­erated from a shorter string (in our case ID) by padding it with random bits until it is the size of n. The RAM e.cient variant of the Rabin scheme does away with the modular reduction step, replacing it with an addi­tion of a random multiple of the divisor.
Sentence 2: proceedings, Part I, LNCS, volume 4277, pages 372 381, Graz, Austria, October 2006. http://snurl.com/wiprFR.
Relationship: neutral
Domain: Hardware
Sentence 1: (Our experiments show that for some benchmarks CapoV pro­duces slightly shorter wirelength than CapoW, which is probably because the additional merge-and-repartition it­erations are helpful to optimize wirelength (as well as tim­  Fig.
Sentence 2: there can be either too many VddL cells, causing trouble to timing closure, or too few VddL cells, wasting slack that can be otherwise traded for power saving.
Relationship: neutral
Domain: Hardware
Sentence 1: In this step, we move the column having the same bit value B, where B .
Sentence 2: the product terms without column e are divided into two scopes according to the value of the .rst column e, and the larger scope (P 1 ~ P 6) is .rst used for determining the order of the remaining columns.1 1 These two scopes need to adopt the same column ordering when mapping.
Relationship: neutral
Domain: Hardware
Sentence 1: Y. Charlie Hu, Alan Cox and Willy Zwaenepoel Department of Computer Science Rice University Houston, Texas 77005 {ychu, alc, willy}@cs.rice.edu Abstract We demonstrate that data reordering can substantially improve the performance of .ne-grained irregular shared­memory benchmarks, on both hardware and software shared-memory systems.
Sentence 2: [7] S. Carr, K. McKinley, and C.-W. Tseng.
Relationship: neutral
Domain: Hardware
Sentence 1: 7 (a), at t=0 s the equivalent conductance (synaptic weight) of the couple of memristors connected to the input X1 is G1 =G1+-G1- = 900 nS higher than those of input X2 (G2= -100 nS) and Bias (Gb=100 nS).
Sentence 2: adaptive switching circuits, IRE WESCON Convention Record, pp.
Relationship: neutral
Domain: Hardware
Sentence 1: The experimental results show that VCM is a good alternative to traditional DRAM chip on multicore architecture because it can not only improve performance but also reduce unfair­ness.
Sentence 2: based on this, we further implement the state of the art scheduling algorithms on VCM, in­cluding FR-FCFS [4], PARBS [2], and ATLAS [1].
Relationship: neutral
Domain: Hardware
Sentence 1: 3.1 Increased Inter-buffer Separation Since the signal propagation speed versus inter-buffer separation curve is rather flat around the optimum separation, one of the most widely used techniques to reduce the buffer requirements within a design is to use inter-buffer separations that are larger than the optimal separation.
Sentence 2: the above result implies that, if the back-off factor is kept constant across process generations, the number of buffers scales at the same (supra­linear) rate as with optimal inter-buffer separation.
Relationship: neutral
Domain: Hardware
Sentence 1: [3] Benbakhti, B., Kalna, K., Chan, K., Towie, E., Hellings, G., Eneman, G., Meyer, K. D., Meuris, M., and Asenov, A.
Sentence 2: intel s adoption of FinFET technology at the 22nm CMOS technology node [12] has invigorated the interest in their optimization and scaling.
Relationship: neutral
Domain: Hardware
Sentence 1: This means that a transient upset in the combinational logic in a FPGA will be latched by a storage cell, unless some detection technique is used.
Sentence 2: cONCLUSIONS This work presents a new technique for upset detection and voting that combines duplication with comparison (DWC) with time redundancy for the user s combinational logic in SRAM­based FPGAs.
Relationship: neutral
Domain: Hardware
Sentence 1: Figure 3 brie.y describes a greedy Partition Pre.x/Mask Output Port 0 000X/1110 001X/1110 1 2 1 010X/1110 011X/1110 1 2 2 100X/1110 101X/1110 3 2 3 110X/1110 111X/1110 3 2  Table 1.
Sentence 2: for 4 splitting bits, there are not enough cache sets to accommodate the split of suf.­cient number of partitions such that the miss ratio could be further reduced.
Relationship: neutral
Domain: Hardware
Sentence 1: This information could easily be conveyed by one of the bits in the .eld, or by an additional con.gura­tion register, since the FPGA keeps track of whether it is operating in a low-or high-resolution mode.
Sentence 2: by pro.lingtheCC1000radiochip,theFTSPdevelopersdeter­minedtheprecisetiming with which theseinterruptsarrive, allowingthemtoinferamoreaccurateoverall messagetime­stamp.
Relationship: neutral
Domain: Hardware
Sentence 1: In Proceedings of the 14th International Conference on Application-speci.c Systems, Architectures and Processors, The Hague, The Netherlands., 2003.
Sentence 2: peak runtime improvements of 2.70x (SNU-RTludcmp), 1.46x and 2.85x (both SNU-RTFFT) are seen, for transformations alone, ISE alone and the combination of the two, respectively.
Relationship: neutral
Domain: Hardware
Sentence 1: ThePlayoutSeletorinformsMusiRendererof hoie,andMusiRendererfethesontentfromLoal ContentStore.
Sentence 2: contentHandlingTheCaheControllerholdsmeta­dataforitemsontheahe,streamsabouttobeome availableandreliablydownloadablefles.Thedata heldwouldhavetoinludeareliabilityrating,and/or retrievaltime,whihwouldbetakenintoaountby thePlayoutSeletorandCaheController.Inthease ofadesirableitemofmusiwithalowreliabilityrat­ing,itwouldberequestedandahed.Oneonthe ahe,itwouldbethesameitemofmusiwithaper­fetreliabilityrating.alongdownloadtime  wouldleadtothepossibilitythatthemusiisnota goodmathbythetimeitisavailable.TheCaheCon­trollerwouldthenhavetomakeadeisionregarding theprobabilityofitbeomingplayableinthefuture.
Relationship: neutral
Domain: Hardware
Sentence 1: 4.2 IEEE 802.15.4a Demonstrator Whereas commercial 2.4 GHz IEEE 802.15.4 radio mod­ules are readily available for purchase, UWB IEEE 802.15.4a radios are still under product development [3].
Sentence 2: (SPAWC), Cannes, France, July 2006.
Relationship: neutral
Domain: Hardware
Sentence 1: A certain fraction of this total will end up being placed in the way and we estimate this fraction as the ra­tio of the size of the neighborhood to the size of the whole design.
Sentence 2: for example, in Fig 3.1, for net I10, we have Nh1 (I10) = {I6,I7,I9,I11 ... }and Nh2 (I10) = {I14,I3,I4 ... }.
Relationship: neutral
Domain: Hardware
Sentence 1: Conventional clock designs have placed emphasis on seeking zero clock skew, since the clock skew sets a lower bound on clock cycle time.
Sentence 2: (M(n1 ),M(n2)) between M(n1) and M(n2) is the set of points with the minimum sum of Manhattan distances to M(n1) and M(n2), i.e., .
Relationship: neutral
Domain: Hardware
Sentence 1: The bit is set when the relevant load issues, and the bit is reset when the relevant load commits or is invali­dated due to misspeculation.
Sentence 2: finally, our results show that a one-ported load/store queue using all our techniques com­bined improves performance on average by 6% and 23%, and up to 15% and 59%, for integer and .oating-point bench­marks, respectively, over the two-ported conventional load/ store queue.
Relationship: neutral
Domain: Hardware
Sentence 1: of Informatics Kyushu University 6-1 Kasuga-Koen, Kasuga, Fukuoka 816-8580 JAPAN murakami@i.kyushu­u.ac.jp 129.compress ABSTRACT 100 This paper proposes a history-based tag-comparison scheme for reducing energy consumption of direct-mapped instruc­ tion caches.
Sentence 2: when the microprocessor fetches an instruction block, if the corresponding footprint is valid, the two conditions for dynamic tag-check omission are satis.ed.
Relationship: neutral
Domain: Hardware
Sentence 1: (5)isrewrittenas; aVoffaWIaW'aWIaW(7) 1I'·I·aW(8) a·aW (9) Usingthismodel,weananalyzethevariationonsidering theorrelationbetween(andVthaswellastheimpat bySTIstress.Alloefientsandparametersusedinour experimentsareonludedinTable5.
Sentence 2: itisknownthattheSTIstressontributestothemobility ofaMOSFETasformulatedin MO k1[LOD/k.
Relationship: neutral
Domain: Hardware
Sentence 1: In this .gure, the leaf nodes are not multipliers, but subtrees.
Sentence 2: according to Equation 3 and Equation 4, the overhead in our design only depends on len(i)(i =0, 1,... ,n -1) and k. when k is .xed, the performance of our design is only affected by the number of nonzero elements on each row, and not by the distribution of the nonzeros among the columns.
Relationship: neutral
Domain: Hardware
Sentence 1: The semantic of this communication protocol preserves the sequence of unidirectional non-blocking function calls.
Sentence 2: put, peek and get functions are still called with the polling mechanism, in which a delay or a latency is explicitly expressed for each call (i.e., nb put(const REQ&#38;, sc time&#38;), nb peek(RSP&#38;, sc time&#38;), nb get(RSP&#38;, sc time&#38;)).
Relationship: neutral
Domain: Hardware
Sentence 1: We then present a hierarchical framework called hierarchical B*-trees (HB*-trees) which can simultaneously optimize the place­ment with both symmetry islands and non-symmetry modules and dynamically update the rectilinear shape for the modules in a symmetry island.
Sentence 2: in Figure 7(b), the horizontal and (a) (b) 4.1 HB*-tree Representation  hierarchy node contour node Figure 6 shows an HB*-tree for the placement in Figure 2(a).
Relationship: neutral
Domain: Hardware
Sentence 1: of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN 46556, U.S. {ypliu,yanghz}@tsinghua.edu.cn*, shu@nd.edu Abstract Automatic C-to-RTL (C2RTL) synthesis can greatly bene.t hardware design for streaming applications.
Sentence 2: algorithm 1: Function minFeasibleNodeInOPEN() input : {OPEN}, {CLOSED} 1 repeat 2 V=nodeWithSmallestEstimationInOPEN(OPEN); 3 for every child node (Q) of V do 4 if Q.area + V.accumulatedArea <Aref then 5 return V; /* Case I */ 6 end 7 end 8 if V has parent nodes other than P in CLOSED then 9 Set the node with the smallest gas V s previous node; 10 Update g(n), ga(n) and h(n);/* Case II */ 11 else 12 Remove V from OPEN; /* Case III */ 13 end 14 until; several nodes representing different parallelization degrees and add a throughput weight to each arrow.
Relationship: neutral
Domain: Hardware
Sentence 1: For each register Ri, we use the notations TRi(H) (TRi(L)), SRi(H) (SRi(L)), and HRi(H) (HRi(L)) to denote its clock arrival time, its setup time, and its hold time at the high voltage level (the ULV level), respectively.
Sentence 2: there are only local wires in our LP (since each global wire has been divided into local wires by assuming that pseudo gates are in between).
Relationship: neutral
Domain: Hardware
Sentence 1: In systems that have well defined communication patterns and usually operate on massive sets of data, the latency and energy cost for configuring the fabric can be amortized by setting up the routing path ahead of time or by sending multiple chunks of data once the path is established.
Sentence 2: 3.4 Selective LRG and MRG In this scheme LRG update is applied to a selective section of inputs.
Relationship: neutral
Domain: Hardware
Sentence 1: size of one BF (bits) error detected total number of errors Error Coverage Total overhead 1K 3211 3662 87.6% 32% 512 2908 3326 87.4% 16% 256 3010 3461 86.9% 8% 128 3130 3669 85.3% 4% 64 4276 3507 82% 2% TABLE II RESULTS OF FAULT INJECTION EXPERIMENTS FOR THE SECOND ARCHITECTURE As expected, even with a large Bloom Filter, the error cov­erage is less than 100%, due to the aliasing of the modular operation.
Sentence 2: 1 When no false positive occurs, the set of Bloom Filters provides a one-hot encoded word as output, while with the occurrence of a false positive in some of the Bloom Filters that does not correspond to the requested key, the output word has multiple bits to 1.
Relationship: neutral
Domain: Hardware
Sentence 1: In the worst-case, when cost restrictions are not imposed during scheduling, we observed that bu.ering is required for up to eight in-.ight critical tasks.
Sentence 2: categories and Subject Descriptors B.8.1 [Hardware]: Performance and Reliability Reliabil­ity, testing, and fault-tolerance; C.3.3 [Computer Sys­tems Organization]: Special-purpose and Application-based Systems Real-time and embedded systems * Meyer is now with the ECE dept.
Relationship: neutral
Domain: Hardware
Sentence 1: The moment of iner­tia for a simple prismatic beam is given by, I = 112 Wh, e r3 r and substituting yields, knL 2 E hr f= ------------- ------------(6)n 2S UL2 12 At first glance, this expression appears to be sufficient for analytical evaluation.
Sentence 2: a manhattan brick mesh of the 3D device was created and har­monic analysis was performed.
Relationship: neutral
Domain: Hardware
Sentence 1: INTRODUCTION As the complexity of Systems-on-Chip (SoC) increases, traditional bus-based interconnects become limited in terms of ef.ciency and performance.
Sentence 2: connection setup and tear-down The con.guration network supports setting up and tearing down communication channels, con.guring and reading back credit information, and con.guring the buses adjacent to the network.
Relationship: neutral
Domain: Hardware
Sentence 1: By this equation, when the cou­pling capacitance between an aggressor and a victim in a certain pitch is 1x, the victim will see 8x coupling capacitance when there are eight aggressors in every direction.
Sentence 2: despite the far aggressor has less than 50% capacitance of the close aggres­sor, Vfar reduces by only 40mV.
Relationship: neutral
Domain: Hardware
Sentence 1: Everything is done transparently to the user/developer.
Sentence 2: the network topology can be modi­.ed (remotely activating or deactivating only a subset of the underwater nodes), the settings of the selected protocol and experiment parameters can be tuned (policies to be fol­lowed by each device; which node has to act as collection point, if any; which nodes have to generate data; what traf­.c load has to be used, etc.
Relationship: neutral
Domain: Hardware
Sentence 1: The VC cache can prevent the bitlines from being discharged in accessing 0 , such that the power dissipated in accessing 0 is much less than the power dissipated in accessing 1 .
Sentence 2: compared to the baseline conventional cache implemented with the way-prediction, the use of VC cache can result in roughly 18%~22% reduction in total cache power consumption during a read access, and reduces the total cache power consumption during a write access by about 36%~40%.
Relationship: neutral
Domain: Hardware
Sentence 1: 4.1.2 FPGA Implementation and Results of AES Implementation choices are not detailed in this paper.
Sentence 2: [36] W. Yu, R. Qiu and J. Fritts, Evaluation of Force 0.02 0.04 0.08 0.1 0.15 0.2 Extracted 29 39 40 40 40 40 Only detected 4 1 0 0 0 0 Not detected 7 0 0 0 0 0  Motion-JPEG2000 for Video Processing, Department Table 7: Gaussian attack of Computer Science, Washington University in St. Louis, Technical report, November, 2001, [Online] Available: http://citeseer.ist.psu.edu/yu01evaluation.html  APPENDIX A.
Relationship: neutral
Domain: Hardware
Sentence 1: In Figure 7(a), time frame T3 is dominated by T6 because MIC(C1,T6) is larger than MIC(C1,T3) and MIC(C2,T6) is larger than MIC(C2,T3).
Sentence 2: given the MIC(Ci,Tj) information, we use EQ(3) to estimate Lemma 2: The increasing number of time frames leads to smaller MIC(STi,Tj): IMPR_MIC(STi) for all i.
Relationship: neutral
Domain: Hardware
Sentence 1: For example, when the maximum congestion is 2, the sub-intervals are {[2, 1.9), [1.9, 1.8), [1.8, 1.7),..., [1.1, 1)}.
Sentence 2: the solution quality of FGR is much worse than other routers on 6-layer designs in which it only solves 3 of 8 benchmarks [3] [4] Computer-Aided Design of Integrated Circuits and Systems, vol.
Relationship: neutral
Domain: Hardware
Sentence 1: 2p4 0 <y<m (m-1)(n-1)(n+m-4) (5) For paths with more than four bends, we approximately consider them as four-bend paths: ' ' Dtp4 Dt 4+(x, y)= p4 4(x, y) p4 =1 - p1 - p2 - p3 As shown in Figure 1, each path with more than four bends Figure 1: Example of transforming a four-bend path to a six-bend path.
Sentence 2: the Do(xi,yj ) wire density for the line segment xi,yj is .
Relationship: neutral
Domain: Hardware
Sentence 1: [2]S. Narendra, J. Tschanz, A. Keshavarzi, S. Borkar, V. De, Comparative Performance, Leakage Power and Switching Power of Circuits in 150 nm PD-SOI and Bulk Technologies including Impact of SOI History Effect, in Proc.
Sentence 2: pch = - -- - - 100 d ref delays of the leading edge in experiments with the pulse width set to 250 ns, 500 ns or 1,000 ns (note, the smaller values of pulse delays, e.g., 300 ns, are not relevant for the 500 ns and 1000 ns pulse width experiments).
Relationship: neutral
Domain: Hardware
Sentence 1: Duxbury [5] (software) and Embosser (hardware) Duxbury is a software that will convert text into Braille.
Sentence 2: figure 5 ADA requirement for aisle space More than 24 in length must be 36 minimum Less than 24 must be 32 minimum  Figure 6 ADA Requirement for wheelchair turnaround must be 60 minimum in diameter 3.4 Training 3.4.1 Faculty and Staff Training on interaction skills, etiquette, and operational procedures, was prepared and provided by the Adaptive Technologist with assistance from Disability Services and the Assistant Director of SCS.
Relationship: neutral
Domain: Hardware
Sentence 1: Shortcomings of the techniques S1 &#38; S2: In the afore­mentioned conventional PDN design methods, the optimiza­tions of the TSV-placement and TSV-sizing are performed independently.
Sentence 2: in this work, we assume that a via-last approach is used in 3D-ICs fabrication, in which routing issues are more severe compared to the via­.rst approach.
Relationship: neutral
Domain: Hardware
Sentence 1: To derive PERI, we use the principle of the skewness, i.e., the relative difference between the mean and the median.
Sentence 2: as shown in [12], the ft() PDF t µ M 1 Ft() CDF 0.5 t Figure 1 The PDF and CDF of a random variable t impulse responseht() is greater than or equal to zero over allt and y 8= 1 .
Relationship: neutral
Domain: Hardware
Sentence 1: The Galaxy S3 Android device API allows binary or detailed analog-to-digital proximity measurements, which can be used to detect di.erent surrounding placement environments.
Sentence 2: speci.cally, we compute the percentage below a small distance |{i|di<DT h1}| threshold Pclose = , percentage between a N small distance threshold and a medium distance threshold |{i|DT h1=di<DT h2}| Pnear = , and percentage above a N |{i|di=DT h2}| large distance threshold Pf ar = .
Relationship: neutral
Domain: Hardware
Sentence 1: As the increasing number of the external pins on LSI boundary is slower than the increase of the size of an LSI, the number of scan Corporate Semiconductor Development Division Matsushita Electric Industrial Co., Ltd. 1, Kotari-yakemachi, Nagaokakyo, Kyoto 617-8520, Japan Tel:+81-956-9511 Fax:+81-953-5018 e-mail:{yosimura, ohta}@mrg.csdd.mei.co.jp  FFs on a scan path connected to the external pins increases relatively.
Sentence 2: (Definition 1 : Fault Detection Probability) The fault detection probability PD (POi) at a primary output POi is defined as the rate of the number of signal lines which are reachable from a primary output POi to the total number of signal lines in a circuit, provided that when a signal line l which is reachable from POi is reachable to k primary outputs, signal line l is calculated with 1/k.
Relationship: neutral
Domain: Hardware
Sentence 1: by independent software vendors, ISV), and 2) can they be integrated in a larger system without any unexpected side e.ects to application or system.
Sentence 2: cost is the area (estimated by the design .ow) in 90 nm of a NOC running at 500 MHz with 32 TDM slots, and includes local busses, NIs, and routers.
Relationship: neutral
Domain: Hardware
Sentence 1: Categories and Subject Descriptors C.0 Computer Systems Organization, GENERAL, Hardware/software interfaces C.3 Computer Systems Organization, SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS, Microprocessor/microcomputer applications C.5.3 COMPUTER SYSTEM IMPLEMENTATION, Microcomputers D.2.9 Software, SOFTWARE ENGINEERING, Management K.3.1 Computing Milieux, COMPUTERS AND EDUCATION, Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Sentence 2: had we chosen to use Boot Camp rather than Parallels, we would have been forced to buy two Deep Freeze licenses.
Relationship: neutral
Domain: Hardware
Sentence 1: Moreover, the increase of nonlinearity or scaling of write current can also reduce the energy consumption and area overhead of the cross-point array.
Sentence 2: the following sections V B1 V B2 V B3 V Bn RV Vwm V wm V wm-1Vwm-1 Vw1 V w1 RVVB1 VB2 VB3 VBn  Figure 1: The circuit model of the cross-point array.
Relationship: neutral
Domain: Hardware
Sentence 1: For example, it appears likely that the combination of poor current drive (even at the ballistic limit where contact resistance dominates) and low gain, as well as physical issues such as the increasing difficulty in achieving alignment between process layers [9] will tend to favour modular or locally connected architectures.
Sentence 2: [33] McFarland, G.W., CMOS Technology Scaling and its Impact on Cache Delay, PhD thesis, Electrical Engineering,Stanford University, 1997.
Relationship: neutral
Domain: Hardware
Sentence 1: com/products/logic/design_comp_cs.html.
Sentence 2: rAG can be used to generate a switch arbiter for a 128x128 terabit switch which, assuming as stated in [5] that the critical path is the switch arbitration logic, achieves throughput 1.9X higher than PPA and 2.4X higher than PPE for the same 128x128 configuration.
Relationship: neutral
Domain: Hardware
Sentence 1: From the given stage in the Petri net, either the left transition or the right transition may .re.
Sentence 2: by comparison, the Table 4: Effect of varying if-/else-computation latencies Nif Nelse Normalized Throughput 2 2 0.86 2 4 1.12 2 6 1.29 2 8 1.42 2 10 1.51 baseline MOUSETRAP implementation obtained an execution time of 3.2µsec and energy consumption of 33 × 104 units; these num­bers do not vary with the branch probability because this baseline implementation does not use the new approach of this paper, and therefore cannot preempt wasteful computation.
Relationship: neutral
Domain: Hardware
Sentence 1: These logic optimizations are based on the physical information generated by the initial global placement.
Sentence 2: fengShui 100 90 100  100100 90 80 90 90 80 70 80 80 70 60 70 70 60 60 50 60 50 50 40 50 40 40 30 40 30 20 30 30 20 10 20 20 10 0 10 10 0 0 0 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 % Whitespace in Bins % Whitespace in Bins % Whitespace in Bins % Whitespace in Bins (A) (B) (C) (D)  Figure 2: A histogram for local whitespace in design ckt4 from IBM with 74% whitespace.
Relationship: neutral
Domain: Hardware
Sentence 1: Of the commercial applications, the ECDC implemen­tation is not able to improve the performance of either SPECjbb2000 or TPC-B.
Sentence 2: lepak and Lipasti identi.ed another source of unneces­sary communication, caused by writes that either overwrite a value with the value already resident at that memory location [23], or revert a location s value to a value that previously ex­isted at that location [24].
Relationship: neutral
Domain: Hardware
Sentence 1: Let T =(OP,RES,Q,d) be a type and s .Qbe a state of T. H conforms to type T initialized to s, if there exists a sequence of states s0,s1,s2,... such that s0 = s, and for each i = 1, (si-1,opi,j,si,resi) .
Sentence 2: the nodes on the critical path form a sequence that conforms to type Ta initialized to s, since we can think of the unsuccessful nodes on the critical path as aborted oper­ation executions that cause a state transition.
Relationship: neutral