sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Ideal sense ampli.ers output a 0Vor 5Vas a result of the logic functions.
Sentence 2: by deliberately mismatching the transistors in the sense ampli.er so that it has a small, Bout Dif  A B C R 4 T1=R 1+R 2+R 3 T2=R 4+R 5+R 6 D if =T1-T2 T3=R 1+R 2 T4=R 4+R 5 B out=T3-T4 0 0 0 L LLL LLL 0 LL LL 0 0 0 1 L LLH LLL 1 LH LL 1 0 1 0 L LH L LLL 1 H L LL 1 0 1 1 H LH H H LH 0 H H H L 1 1 0 0 L H LL LLL 1 LL LL 0 1 0 1 H H LH H LH 0 LH H L 0 1 1 0 H HHL HLH 0 HL HL 0 1 1 1 H HHH HLH 1 HH HL 1 BCA  Figure 4: 1-bit spintronic subtractor using MTJs and its truth table S0/D0 Figure 9: n-bit spintronic adder/subtractor using .rld-driven MTJs positive Voffset, a di.erence of zero will be considered to be negative di.erence.
Relationship: contrasting
Domain: Hardware
Sentence 1: Leakage Power [W] 0.002 0.0015  A4:Combination of System Parameters Using the analysis presented in Table 4 in Section 5.1, it is now possible to estimate the impact of the three system pa­rameters viz., capacity (C), frequency (F) and width (W), on DRAM current consumption.
Sentence 2: when a combina­tion of system parameters di.er between two DRAM memo­ries, the in.uence all the concerned system parameters must be taken into account.
Relationship: contrasting
Domain: Hardware
Sentence 1: Lastly, we notice that for the very low 10%-populated crossbar, AAPack 6.0 no longer packs e.ciently requiring 27% more CLBs than AAPack 7.0.
Sentence 2: aAPack 7.0 only runs 2.4-fold faster than AAPack 6.0 for this architecture because the sparsity of the crossbar causes AAPack 7.0 to invoke detailed rout- Table 5: Comparison of AAPack 7.0 vs AAPack 6.0 across di.erent architectures.
Relationship: contrasting
Domain: Hardware
Sentence 1: For each in­verter cell,thep:n size ratio was chosen tobe1:1because of symmet­ricpmos and nmostransistors.
Sentence 2: fora3-inputNANDgate,the p:n size ratio was chosen tobe1:3,because thethreepmos transistors are connectedinparallel, whilethe3 nmostransistors are connectedin series, as shown in Figure 3.
Relationship: contrasting
Domain: Hardware
Sentence 1: VTn) (12) VDD = 1+.ß a ( -) where k is obtained through (13), -aVDD / U 1-e k = ln( ) (13) -ßVDD / U 1-e Equation (12) is a non-linear equation, it is impossible to solve it analytically.
Sentence 2: for given a and ß, k almost remains constant when VDD is swept in the sub-threshold region (see Fig.
Relationship: contrasting
Domain: Hardware
Sentence 1: In particular, word-level decision diagram based tech­niques [6, 9] share this problem due to the explicit word-level fea­ture, which makes them incapable of representing bit-level errors appearing in a gate-level netlist.
Sentence 2: when posed in the equiv­alence checking setting, modern equivalence checking methodol­ogy is often capable of .nding a counterexample for inequivalence quickly, and thus providing a convenient solution to this design er­ror problem.
Relationship: contrasting
Domain: Hardware
Sentence 1: Realizing Near-True Voltage Scaling in Variation-Sensitive L1 Caches via Fault Buffers Tayyeb Mahmood Soontae Kim tayyeb@kaist.ac.kr kims@kaist.ac.kr Department of Computer Science Korea Advanced Institute of Science &#38; Technology Daejeon, South Korea ABSTRACT Voltage scaling can be applied to cache memories to reduce their energy consumptions.
Sentence 2: reduced supply volt­age to the cache memories increases defective SRAM cells due to process variations, which will decrease their yields and performance nullifying the bene.ts of voltage scaling.
Relationship: contrasting
Domain: Hardware
Sentence 1: For this purpose, today s microprocessors incor­porate a multitude of sophisticated micro-architectural fea­tures, such as multiple instruction issue, dynamic schedul­ing, out-of-order execution, speculative execution, and dy­namic branch prediction.
Sentence 2: in order to sustain performance growth, future superscalar microprocessors must rely on even more complex architectural innovations.
Relationship: contrasting
Domain: Hardware
Sentence 1: INTEGRATION OF GATED CLOCK TREE INTO INCREMENTAL PLACEMENT As we introduced the motivation in Section 1.2, previ­ous works only construct and optimize the gated clock tree topology, the gates are always inserted after the placement.
Sentence 2: they do not consider and discuss the suitability of the gates positions, since the optimal gates positions may have already been occupied by other cells or it will incur a lot of overlaps.
Relationship: contrasting
Domain: Hardware
Sentence 1: Adaptivevoltage scaling (AVS) after manufacturing testing is another optionto mitigate yield loss [9].
Sentence 2: employing multiple voltagedomains on a chip to mitigate WID variations (such as core-to-coreFmax and Pleak variations in multicore processors) is verychallenging in practice due to the increased cost of 1) design,verification, and testing time [10] as well as 2) voltage regulatorsand decoupling capacitors [11].
Relationship: contrasting
Domain: Hardware
Sentence 1: We remark that AvgRE, REStDev and CC are evaluated on the entire set of data collected in .M, hence, they represent global measures of in-sample accuracy.
Sentence 2: the RMSRE has been separately evaluated for each bench- mark, to represent the accuracy that a designer may obtain from the models when they are used to estimate the power consumption of a given controller under different workload conditions.
Relationship: contrasting
Domain: Hardware
Sentence 1: 5.7% 1,735.9% Tx/trans (rel) 7.6% 1,301.9% As a sanity check, we can compare this implementation with a call­by-value implementation as used by more wide-spread compilers; Ocaml v3.10 computes fib(36) on the same CPU in 0.6 seconds, substantially better than Algol60 and Marst.
Sentence 2: the overall throughput of the FPGA remains higher.
Relationship: contrasting
Domain: Hardware
Sentence 1: RTL Power Optimization with Gate-level Accuracy Qi Wang Sumit Roy  Cadence Design Systems, Inc   Calypto Design Systems, Inc 555 River Oaks Parkway, San Jose 95125 2903  Bunker Hill Lane, Suite 208, SantaClara 95054 qwang@cadence.com    sroy@calypto.com ABSTRACT Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power.
Sentence 2: because of inadequate power and delay information, the power optimization transformations applied at the RTL may cause unexpected results after synthesis, such as worsened delay or increased power dissipation.
Relationship: contrasting
Domain: Hardware
Sentence 1: Available IP s range from soft blocks, where in general a RT level netlist is available, to hard blocks where everything is .xed up to mask design.
Sentence 2: one has to make the SoCs Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: contrasting
Domain: Hardware
Sentence 1: In order to maintain high circuit performance, the threshold voltage must be scaled down along with the power supply voltage.
Sentence 2: it has been shown that for a minimum size NMOS transistor in a0.25µm technology, lowering the threshold voltage from 0.5V to 0.3V multiplies the o.-current of the transistors by a factor of 170 [1].
Relationship: contrasting
Domain: Hardware
Sentence 1: an optimal amount of SRAM by periodically dumping the We see no reason why simple counter management logic largest counter in SRAM to DRAM.
Sentence 2: cannot be deployed (either as a stand-alone chip with inter- it is di.cult to implement LCF at high speeds faces to external DRAM or within a forwarding processor) because of the need to have logic that selects the largest using our LR(b) algorithm.Given that SRAM contributes a SRAM counter to evict.
Relationship: contrasting
Domain: Hardware
Sentence 1: However, the minimum output voltage is limited to V = V + 2 ·V , being Von the amount of VGS (out ) min T on that exceeds VT. Obviously, Vout(min) can be reduced with the increase of the transistors aspect ratios and gate-source voltage adjustment.
Sentence 2: using TSTs, we can obtain a small minimum excursion with less silicon area.
Relationship: contrasting
Domain: Hardware
Sentence 1: Therefore, only the local evaluation of the local­ity based on metric Dat each time is suf.cient to control the cache in this case.
Sentence 2: in the case of the SPECint95 benchmarks with highly irregular and time-variant behav­ior of the locality as shown in Figure 2, more bits can provide more appropriate cache con.gurations in terms of performance/resource-usage.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is mainly because the 3 ns skew constraint reserves more feasible solutions during clock network construction, which helps to obtain a low energy clock network.
Sentence 2: using relaxed skew bound of 10 ns cannot hold this bene.t, since it allows larger clock skew thus requires more buffers for tighter slew to reach a similar Fmax as 1 ns or 3 ns skew bound.
Relationship: contrasting
Domain: Hardware
Sentence 1: Moreover, the area demand of P/G TSVs, which can lead to routing congestion, should also be taken into account.
Sentence 2: there is a potential con.ict between IR-drop and area demand: using bigger and more P/G TSVs can reduce the IR-drop at the expense of an increased area demand, i.e., increased routing complexity and the possibility of routing congestion.
Relationship: contrasting
Domain: Hardware
Sentence 1: The scattering characteristics of a cylindrical shell with a hemi-spherical cap on one end are calculated by BEM and Finite Element Method considering the coupling effect between the elastic shells and the interior filler [2].
Sentence 2: due to the different sizes of the scattering surfaces and the different directions of arrival, the installation position of the vector sensor has a great influence on the measurement results.
Relationship: contrasting
Domain: Hardware
Sentence 1: Wn Wp Cin TRL_WC 4.3 8.0 4.73 TRL_A1 2.3 3.7 2.31 TRL_A2 1.8 3.1 1.88 As expected, the use of larger transistors does not guarantee a better result on delay propagation in the ring oscillator (i.e., minimum oscillating period) due to the increase in input capacitances observed in each stage.
Sentence 2: power dissipation always increases with the transistor width.
Relationship: contrasting
Domain: Hardware
Sentence 1: The CPA attack results for the threshold in [10], [12] on FPGA are not Un p r ot ec t e d s i n g l e- Unp r ot e c t ed available due to some mismatching in modesbetween the ASIC core and the available FPGA experiment system.
Sentence 2: the threshold implementation should be considered safe given the attack results of [12].
Relationship: contrasting
Domain: Hardware
Sentence 1: Typically, a ranges from 0.05 to 0.4, The rationale of changing wuv is that when PDuv is small, i.e., PDuv = PDth, it is a good metric for .nding .ip-.ops for merg­ing.
Sentence 2: if it becomes large, i.e., PDuv > PDth, it implies that distant .ip-.ops are clusteredtogether, and from this point, consid­ering LDuv along with PDuv is more effective in .nding .ip-.ops for merging.
Relationship: contrasting
Domain: Hardware
Sentence 1: For Vth s s/µ, the 1999 ITRS [17] gave a design target of 0.06 for year 2006 (although no solution existed); however, the projection has since been discontinued.
Sentence 2: kahng [19, 20] reckons that the ITRS variability projections (for at least the gate-length parameter that he examines) are too op­timistic.
Relationship: contrasting
Domain: Hardware
Sentence 1: P0 P1 P2 P3 P4 PG0 012 345 678 91011 121314 PG1 048 3711 61014 913 2 1215 PG2 0714 310 2 613 5 918 12411 PG3 010 5 313 8 6111 9414 1272 PG4 01311 3114 642 975 1210 8 Table 1: 15-input XOR network construction (S = 3, B = 5) The attainment of a lower compression ratio thus requires a smaller value of S. A smaller value of S also implies that the network needs fewer numbers of XOR gates, which in turn reduces the hardware and performance cost of the network.
Sentence 2: a smaller value of S degrades the randomness of the network, as the network construction approach delivers a bit overlap ratio of 1/S.
Relationship: contrasting
Domain: Hardware
Sentence 1: Furthermore, as the temperature is lowered, the decreased values of r0 and r in (18) give extra room for further reduction in the power for a given allowed delay penalty by increasing l and/or decreasing s. Note that since the reduced repeater power also results in a decrease in the power consumed by the logic blocks, the optimal values of l and s that minimize the repeater power also leads to the largest leakage power reduction from the logic blocks.
Sentence 2: as mentioned in Section 2.3, there is a possibility that the steady-state temperature is not reached due to thermal runaway, which can further restrict the solution space of l and s in addition to the delay constraint.
Relationship: contrasting
Domain: Hardware
Sentence 1: The output slew rate of the CMOS bu.er depends on both the input slew and the load capacitance [19].From Equa­tions (1) and (2), the e.ective load capacitance seen by the bu.er output depends on the slew at the bu.er output.This factor introduces a chicken-egg problem which is addressed in [19] using an iterative delay evaluation technique.
Sentence 2: 3.2 Backward propagation of slew In order to consider the node slews during the clock tree synthesis, we need to calculate the signal slew rate during the bottom-up topology generation phase of the DME [8, 17] algorithm.by de.nition, the slew rate at a child node can be calculated only when the slew rate at theparent nodeisknown.Forexample, in Figure(3), the slew rate at node a can be obtained only when the slew rate at node v is known.An e.cient method for obtaining the transition times at the nodes of the clock tree for a given transition time at the source node has been proposed in [19].
Relationship: contrasting
Domain: Hardware
Sentence 1: However, even if simulation performance is much higher on these platforms, checking the functional correctness of a complex system, such as a processor design, presents many new challenges: Mapping checkers to acceleration platforms: Many software­based checkers designed for microprocessor validation are expected to execute in lock-step with the RTL or gate-level simulation of the processor model.
Sentence 2: acceleration platforms can only simu­late synthesized logic descriptions.
Relationship: contrasting
Domain: Hardware
Sentence 1: The .rst (which is partly used in [19]) is to (a) make a tempo assumption Tz, (b) use the column corresponding to Tz in fharmo(t, Tz), fspecbal(t, Tz), (c) sample the four fea­tures sets fi(t) at lags t corresponding to the sub-harmonics and harmonics of Tz, (d) measure the likelihood of the result­ing combination of sampled-features and tempo assumption.
Sentence 2: this method was found very costly.
Relationship: contrasting
Domain: Hardware
Sentence 1: Additionally, a larger num­ber of MPPR cores per FPGA increases the demand for a large output bu.er.
Sentence 2: this can easily be avoided by reducing the size of the distinguished point set D. A direct consequence are longer search trails for distinguished points and, thus, collisions of two or more cores requesting a bu.er lock at the same time will become extremely unlikely.
Relationship: contrasting
Domain: Hardware
Sentence 1: DOMINO: A System to Detect Greedy Behavior in IEEE 802.11 Hotspots * Maxim Raya, Jean-Pierre Hubaux, Imad Aad Laboratory for computer Communications and Applications(LCA) School of Computer and Communication Sciences EPFL, Switzerland {maxim.raya, jean-pierre.hubaux, imad.aad}@ep..ch ABSTRACT The proliferation of hotspots based on IEEE 802.11 wireless LANs brings the promise of seamless Internet access from a large number of public locations.
Sentence 2: as the number of users soars, so does the risk of possible misbehavior; to pro­tect themselves, wireless ISPs already make use of a number of security mechanisms, and require mobile stations to au­thenticate themselves at the Access Points (APs).
Relationship: contrasting
Domain: Hardware
Sentence 1: The equal duration of the reset and evaluate phase on the right side of the pipeline can be seen for stage 4 in Figure 3 where the path traversed by N4 = 0 on the reset network loop (i.e., stage 4 in the reset phase) is the same as the one traveled by N4 = 1 (i.e., stage 4 in the evaluate phase).
Sentence 2: the evaluate phase of stage n-1 has to wait on the arrival of the reset phase from stage n to the latch-enabling AND gate in order for data to flow from the former to the latter.
Relationship: contrasting
Domain: Hardware
Sentence 1: The MMTk barriers full checks are much simpler than those usedbyBartok in termsof theirbehavior,andregister pressure.
Sentence 2: as we show below, other GC algorithms are more complex than classical generational GC, and the table-based lookups performed by Bartok are common with other applications e.g., implementations of thread-local heaps with each thread s local data placed on a separate set of pages.
Relationship: contrasting
Domain: Hardware
Sentence 1: M8) provides better robustness then M1 vias, when we pack as much as vias on the landing pad.
Sentence 2: in terms of failure time vs. block area ef.ciency, higher metal layer is not as good as lower metal 3Here we use the terminology local via as a via in the BEOL metal layers (V1 V9 ), to differ from the TSV.
Relationship: contrasting
Domain: Hardware
Sentence 1: Note that this optimization requires stream address generation logic in the processor pipeline (akin to HEAVYWT) to rename consume instructions to the correct queue addresses to index into the stream cache.
Sentence 2: this is still better than HEAVYWT, since SYNCOPTI shares the L3 bus, while HEAVYWT requires extra interconnects connecting the cores to the synchronization ar­ray, which can be expensive [12].
Relationship: contrasting
Domain: Hardware
Sentence 1: Name ofArraysSize(KB)Count tomcatv Specfp95 9 1194,868,048 nasa7/btrix Specfp92 294,31244,430,039 nasa7/mxm Specfp92 3 12047,168,707 nasa7/vpentaSpecfp92 9 1142,274,945 adi Livermore 6 2416,062,860 dtdtz(aps) PerfectClub171,60542,119,337 bmcm(wss) PerfectClub11 12689,539,244 psmoo(tfs) PerfectClub1 20416,955,980 eflux(tfs) PerfectClub5 29712,856,306 Table1:Programsusedintheexperiments.
Sentence 2: iedfora4Kcachewithvariousassociativities.Thisresult showedthatincreasingthenumberofsub-banksfromoneto twoprovidesanenergysavingof45%forthedatacacheac­cesses.Anadditional22%savingisobtainedbyincreasing thenumberofsub-banksto4.Itmustbeobservedthatthe savingsarenotlinearasonemayexpect.Thisisbecausethe energycostofthetagarraysremainsconstant,whilethere beingasmallincreaseinenergyduetoadditionalsub-bank decoding.Wefoundthatforblockbuferingaddingasingle blockbuferreducedtheenergybyupto50%.Thisre­ductionisachievedbycapturingthelocalityofthebufered cacheline,therebyavoidingaccessestotheentiredataar­ray.accesspatternsinmanyapplicationscanbe regularandrepeatingacrossavariednumberofdiferent cacheblocks.Inordertocapturethisefect,wevariedthe numberofblockbuferstotwo,four,andeightaswell.We observedthat,forthemxmbenchmark,anadditional17%(as comparedtoasinglebufer)energysavingcanbeachieved usingfourbufers.
Relationship: contrasting
Domain: Hardware
Sentence 1: Based on the transmission line theory above, non-monotonic driver output waveforms should ideally be modeled as multi­piecewise linear waveforms to capture plateaus and multiple reflections.
Sentence 2: it is shown in [2] that reflections and other transmission line phenomena become important only when the source impedance of the driver is less than or comparable to the characteristic line impedance.
Relationship: contrasting
Domain: Hardware
Sentence 1: Other works [8] [9] [10] exploit binary translation to convert sequential code compiled for single-issue processors into code executable on VLIW architectures.
Sentence 2: we are not aware of any previous work combining binary manipula­tion and FPGAs for providing support in the design of com­pletely con.gurable application-speci.c processing elements.
Relationship: contrasting
Domain: Hardware
Sentence 1: 5.5 Using High-LevelPerformance Targets The settling time is the time in which the system output get close enough to the targets (for instance, 5% of their values) So far we have assumed that the performance target accommo­dated by METE are in terms of IPCs.
Sentence 2: depending on the application domain, higher level performance metrics (like the num­ber of transactions per second) may be speci.ed to METE in a .ex­ible manner.
Relationship: contrasting
Domain: Hardware
Sentence 1: Finally,theratioofthetotalavailabletracklengthwithin layeritothesupplied(nominal)tracklengthonthelayer, whichwecalltheutilizationfactorUi,canbewrittenas Ui=Tr(1;vi): (1) Ofcourse,sinceallmodelsfocusontheresourcesusedfor signalnets,theresourceusedforpower/groundandclock distributionmustbeleftoutoftheestimatedavailablere­sources.Thisleadstoanotherfactor,thefractionofrouting resourcesusedforsignalnetsonly,whichwedefnehereas thesignalnetfractionsi(onlayeri).ThischangesEqua­tion1to Ui=Tr(1;vi)si: (2) 2.2 Review of Existing Models Sai-HalaszThefrstmodeltoaccountfortheefects ofrouterefciencyandviaimpactwasusedbySai-Halasz [15]topredictperformancetrendsinmicroprocessors.The modelassumesthatpowerandgroundwirestakeup20%of eachlevel(si=0:8),thattheroutingefciencyis40%and thateachlayerblocks12%to15%ofthewirecapacityof alllayersunderneathitifthewirepitchesareequal.Ifthe pitchesdifer,thisfactorhastobereducedbytakingthe ratioofthepitchesintoaccount.ForNllayers(numbered from1toNl,goingbottomtotop),theviaimpactfactor onlayeriinSai-Halasz'modelisdefnedtobe Nl Xpi 1;vi=0:85pk, (3) k=i+1 wherepxisthewirepitchonlayerx.
Sentence 2: theSai-Halaszmodelhasbeenusedbyanumberofother researchersintechnologyextrapolation"topredictfuture achievabledesign[10;11;17].sinceitisbased onlyonfactorsforgooddesignpractice"andattemptsto ensurearoutabledesign,ittendstoberatherpessimistic abouttheavailableresources.
Relationship: contrasting
Domain: Hardware
Sentence 1: Figure 4: Simplifying re-parameterization for proof of Lemma 5 Thus, the decision rule described in Equation (10) will de­sign the domains for two hybrid systems, Hc and Hcc,which automatically satisfy Conditions (7), (8), and (9).
Sentence 2: sk it is not guaranteed that = R2 for either Hc or Hcc.
Relationship: contrasting
Domain: Hardware
Sentence 1: Hence, conventional dual-Vt designs that did not consider junction BTBT while assigning high-Vt, was extremely effective in saving leakage in submicron technologies.
Sentence 2: in a 50nm device, the junction BTBT leakage increases significantly with small change in Vt and becomes comparable to subthreshold leakage at Vt = 0.3V, which is only 100mV higher than the low-Vt (Figure 3b).
Relationship: contrasting
Domain: Hardware
Sentence 1: It may provide an even  larger power saving as all the repeaters are removed, with low power pulse generate circuits being used Interconnect width (Pm) 0.20 2.4 0.30 1.6 0.25 2.0 Cutoff region 1.2 0.40 Cutoff length instead.
Sentence 2: a longer wire delay is 0.8 0.50 Power ratio R p expected due to the longer transmission distance.
Relationship: contrasting
Domain: Hardware
Sentence 1: To overcome the intrinsic ine.ciency of electri­cal interconnects, researchers have leveraged recent devel­opments in chip photonics to design novel optical network­on-chip (NoC).
Sentence 2: existing optical NoCs are mostly based on passively switched, channel-guided optical inter­connect in which large amount of power is wasted in heating the micro-rings and maintaining the optical signal integrity.
Relationship: contrasting
Domain: Hardware
Sentence 1: Several on-chip interconnect architectures have been proposed that leverage photonics for future multi-processors.
Sentence 2: most of them are bus-based, such as Cornell hybrid electrical/optical interconnect architecture [2], Firefly [3] which proposes the implementation of reservation-assisted single­write-multi-read buses, and HP Corona crossbar architecture [4] which is in fact several multiple writer, single reader buses.
Relationship: contrasting