sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Exploration of Pipelined FPGA Interconnect Structures Akshay Sharma Katherine Compton Electrical Engineering  Electrical &#38; Computer Engineering University of Washington Northwestern University Seattle, WA  Evanston, IL akshay@ee.washington.edu kati@ece.northwestern.edu ABSTRACT In this work, we parameterize and explore the interconnect structure of pipelined FPGAs.
Sentence 2: we explore the effects of interconnect register population, length of registered routing track segments, registered IO terminals of logic units, and the flexibility of the interconnect structure on the performance of a pipelined FPGA.
Relationship: entailment
Domain: Hardware
Sentence 1: Using the covariance matrix, and the underlying probability distributions of the variables in X, samples of the corre­lated non-Gaussian variables are generated and are given as inputs to the ICA module, which produces as output, the estimates of the matrices A and W. For a speci.c grid, the independent compo­nents of the non-Gaussian random variables must be computed just once, and this can be carried out as a precharacterization step.
Sentence 2: iCA need not be recomputed for different circuits or different placements of a circuit.
Relationship: entailment
Domain: Hardware
Sentence 1: of Informatics, Japan kei@nii.ac.jp ABSTRACT We consider the recognition of activities from passive enti­ties by analysing radio-frequency (RF)-channel .uctuation.
Sentence 2: we focus on the recognition of activities by active Software-de.ned-radio (SDR)-based Device-free Ac­tivity Recognition (DFAR) systems and investigate the lo­calisation of activities performed, the generalisation of fea­tures for alternative environments and the distinction be­tween walking speeds.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we assume that intended circuits for scan-based BIST insertion are logic-intensive circuits.
Sentence 2: the application-dependent circuits targeted in this paper require LE re­sources rather than memory resources, which are another resources embedded on FPGAs and can be con.gured to provide various memory functions such as RAM, ROM, FIFO buffers and shift registers without using LEs.
Relationship: entailment
Domain: Hardware
Sentence 1: lR=0 returns an element b .Bn with P yrgn(b) = P r.R r s optn(y), where optn(y) := infb.Bn n(b) and s = r.R yrg 1 is a constant.
Sentence 2: we assume that we can optimize linear functions over each Bn e.ciently with an approximation factor s. This is indeed true in our case: Theorem 1.
Relationship: entailment
Domain: Hardware
Sentence 1: 1A-2 Behavioral Synthesis with Activating Unused Flip-Flops for Reducing Glitch Power in FPGA Cheng-Tao Hsieh+, Jason Cong++, Zhiru Zhang++, Shih-Chieh Chang+ +Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan ++Computer Science Department, University of California, Los Angeles, USA cthsieh@gmail.com, {cong, zhiruz}@cs.ucla.edu, scchang@cs.nthu.edu.tw ABSTRACT In this paper we discuss optimizing the interconnect power of designs implemented in FPGA platforms.
Sentence 2: we reduce the glitch power on interconnects associated with the output of functional units in a design.
Relationship: entailment
Domain: Hardware
Sentence 1: Reliability Aware NoC Router Architecture Using Input Channel Buffer Sharing M. H. Neishaburi McGill University Montreal, QC, Canada mh.neishabouri@mail.mcgill.ca ABSTRACT To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both dynamic virtual channel allocations and the rational sharing among the buffers of different input channels.
Sentence 2: in the case of failure in routers, the virtual channels of routers surrounding the faulty routers can be totally recaptured and reassigned to other input ports.
Relationship: entailment
Domain: Hardware
Sentence 1: Notice that, the TaxSOM model overcomes the baseline approach for all measures and taxonomies.
Sentence 2: the relative coverage of TaxSOM is always greater than baseline; Directories Arch Biol Cook News Heal Relative Coverage Baseline TaxSOM 81.40 88.62 40.75 79.52 67.27 83.84 90.00 98.28 78.25 79.30 Average Coverage Baseline TaxSOM 2.12 2.76 0.99 1.93 3.42 7.42 5.00 6.39 7.25 8.37 Macro F1 Baseline TaxSOM 57.64 58.54 33.77 70.19 28.69 47.07 33.90 39.01 32.43 33.05 Table 2:Stand-alone comparison of the TaxSOM model versus the baseline approach.
Relationship: entailment
Domain: Hardware
Sentence 1: Our goal in this paper is to examine the asymptotic behav­ior of the response time tail distributions under both LRD arrival processes and general (light-tailed or subexponen­tial) service times.
Sentence 2: we consider LRD/GI/1 queues, where the arrival process is long-range dependent (LRD) and the service times are independent and identically dis­tributed (i.i.d.)
Relationship: entailment
Domain: Hardware
Sentence 1: However, recent content formats including the H.264/AVC video standard [8], AAC [1], and the Scalable to Lossless (SLS) audio coder [9] pose significant scalability problems for generic adaptation via BSDL.
Sentence 2: bSDL cannot efficiently describe numerous structures which are prevalent in these formats, and the description tools which are available lead to a processing time which increases relative to the bitstream duration according to O(n2).
Relationship: entailment
Domain: Hardware
Sentence 1: cells containing more than one ALU, in the state-of-the-art.
Sentence 2: the PACT-XPP cells [18] (like the RAC we overview in Section 2) support conditional operations within one clock cycle, and the Flexible Compu­tational Component [10], while targeted more speci.cally to DSP kernels, is similar to the RAC in size and set of allowed operations.
Relationship: entailment
Domain: Hardware
Sentence 1: Our technique is compared to the previous technique in [8], and the same experimental setup, testcases and technology library from [8] are used in this paper.
Sentence 2: it includes 10 small testcases with 50 to 100 functional units, 5 large testcases with 500 to 5000 functional units, and a technology library consisting of .ve voltage levels.
Relationship: entailment
Domain: Hardware
Sentence 1: As CMOS processes are typically getting more and more optimized for the needs of digital circuitry, this trend can influence the future milestones for analog design.
Sentence 2: cMOS technologies are being developed to improve digital switching speeds, lower the supply voltages, and reduce transistor geometries to increase the packing density of digital circuits, where all these modifications can negatively impact analog and mixed-signal circuit performance by reducing the input voltage swings and the linearity over the range of operation as well as information loss caused by charge injection induced by the digital part.
Relationship: entailment
Domain: Hardware
Sentence 1: These results clearly show that fault sim­ulation is not a proper approach for SER estimation of sequential circuitsand theestimated values aresigni.cantly lowerthanactual values.
Sentence 2: if reliability parameters are obtained using faultsimulations,theactualreliabilityrequirementsmaynotbemet and this may result incatastrophes in criticalapplications.
Relationship: entailment
Domain: Hardware
Sentence 1: A grid is said to be robust if, for every node k, the steady state voltage drop at k over all possible currents satisfying (5) is less than a given threshold vth.Let vub(p.t) be the vector of upper bounds on the peak voltage drop at time point p.t, de.ned in [6].
Sentence 2: we will denote vub(.t)by Va.From [6], we have that, as p tends to in.nity, vub(p.t)convergesto: « V8 = I + G-1 CVa (10) .t for all .t = 0.
Relationship: entailment
Domain: Hardware
Sentence 1: Using incremental solving in BMC, only one SAT instance, which changes with every call of the solver, is used for all calculations.
Sentence 2: parts of the formula are removed (e. g. by adding the transition relation Ti,i+1 and related property Pi+1, the property Pi has to be removed), and thus derived clauses originating from removed parts are invalid in later solver calls.
Relationship: entailment
Domain: Hardware
Sentence 1: As discussed above, it is not possible for VOU T to equal VOU T ,N L. Therefore, when considering both conduction loss and parasitic switching loss [9], it should be as optimally close to VOU T ,N L as possible.
Sentence 2: for a given VIN , the optimal VOU T can be de.ned as: VOCR = KOCR * VOU T,N L. (4) Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under Check Valery A. Vardanian and Liana B. Mirzoyan STaR Lab, Institute of Informatics &#38; Automation Problems, Armenian NAS Yerevan 375044, Armenia, E-mail: valery@ipia.sci.am Abstract A heuristic design-for-checkability method based on observation point insertion in the Circuit Under Check (CUC) is proposed to increase the error detection ability of Concurrent Checkers (CC).
Sentence 2: at least 99% of error detection is obtained for parity checkers and almost all ISCAS 85 benchmark circuits by inserting 2-5 groups of observation points compacted by parity trees.
Relationship: entailment
Domain: Hardware
Sentence 1: This means that the new programcriticalpath should notbe worsethanthe original path(thatpassedthroughdispatchnode ofthe spawnee).
Sentence 2: the only reason why it could be worse off than theoriginalpath,couldbeifit .owsthroughoneof theEE edges that aredelayeddue to the act of spawning.
Relationship: entailment
Domain: Hardware
Sentence 1: Al­though in this case the obtained performance is closer to the high-level estimations, link pipelining techniques may have a great impact over the implementation cost, thus requiring a new metric to asses the real e.ectiveness of link pipelining techniques.
Sentence 2: we have considered the area e.ciency metric, de.ned as throughput/area, which correlates the throughput improvement with the area cost that has been paid to achieve that.
Relationship: entailment
Domain: Hardware
Sentence 1: In the worst case, vortex shows the 3.84% performance loss with 31% leakage saving.
Sentence 2: bzip2, gcc, mcf, parser, vpr, applu, art, galgel, lucas, and swim nearly the half of the entire SPEC2K workloads show negligible or no performance losses while achieving more than 80% leakage power reduction for the combined technique.
Relationship: entailment
Domain: Hardware
Sentence 1: While specialized and accelerator architectures tackle the energy e.ciency problem by augmenting conventional pro­cessors [11, 18, 22, 24, 40], this paper investigates whether fundamental ine.ciencies in the processor core itself can be eliminated.
Sentence 2: we consider the overheads aris­ing from speculative execution, including branch prediction, memory dependence prediction, and execution in the pres­ence of hardware faults or exceptions.
Relationship: entailment
Domain: Hardware
Sentence 1: However, MLS only issues one prefetch for each stream and always attempts to traverse the stream chain to .nd new streams.
Sentence 2: we can consider the conventional stride prefetcher is a special case of the TAS prefetcher that never goes width in .nding prefetch candi­dates, while the MLS prefetcher is another special case of TAS prefetcher that never goes depth in .nding prefetch candidates.
Relationship: entailment
Domain: Hardware
Sentence 1: In this work, unlike the previous works which have solved the ADB minimization problem heuristically or locally optimally, we propose an elegant and easily adoptable solution to over­come the limitation of the previous works.
Sentence 2: we propose an O(n log n) time (bottom-up traversal) algorithm that (1) optimally solves the problem of minimizing the num­ber of ADBs to be inserted with continuous delay of ADBs and (2) enables solving the ADB insertion problem with dis­crete delay of ADBs to be greatly simple and predictable.
Relationship: entailment
Domain: Hardware
Sentence 1: For example, if two cells ci, cj are assigned with p-th and q-th coloring solutions, respectively, then LUT(i, p, j, q) would store the minimum distance re­quired when ci is to the left of cj .
Sentence 2: if two colored cells can be legally abutted to each other, the corresponding value would be 0.
Relationship: entailment
Domain: Hardware
Sentence 1: As shown in figure 4, The FIR filter using CSHM consists of one precomputer and M Select units and Final adders (S &#38; A) s, where M represents the number of taps in FIR filter.
Sentence 2: we can easily notice from the figure that the precomputer outputs are shared by all the S &#38; A s. the computations ak x, k = 0, 1, 2 .8, are performed only once for all k's and these values are shared by all the Select units for generating ck x, i=0, 1, 2, 3, .
Relationship: entailment
Domain: Hardware
Sentence 1: We do believe that there is potential to further improve the critical path delay, which would require much more aggressive synthesis algorithms that are speci.c to the new logic chain.
Sentence 2: this would require a new logic decomposition algorithm that recognizes the cas­caded structure of the logic chain; such an algorithm could be integrated with a technology mapper to make better use of the logic chains than the relatively naive and greedy chain­ing heuristic described here; this is an important research direction that is currently left open for future work.
Relationship: entailment
Domain: Hardware
Sentence 1: Recall that a voltage partitioning algorithm is a fully polynomial time approximation scheme (FPTAS) to the NP-hard voltage partitioning problem if it can compute a voltage partitioning solution with peak power always within a 1+ E factor of the optimal voltage partitioning solution and it runs in time polynomial in n and 1/E for any E> 0.
Sentence 2: it is a linear time approximation scheme if it runs in time linear in n (while usually nonlinear in 1/E).
Relationship: entailment
Domain: Hardware
Sentence 1: This method performs a directional search along the orthogonal Arnoldi vectors which span the Krylov subspace of A.
Sentence 2: given an initial guess x0 and cor­responding residual r0 = b - Ax0, orthogonal vectors {q1, q2...,qm}are generated with the property that they span Sm, the solution search space at iteration m. Sm = x0 + s pan {r0,Ar0, ..., Amr0} = x0 + .
Relationship: entailment
Domain: Hardware
Sentence 1: MOTIVATION OF THE TLM ANALYSIS The adoption of a TLM level of abstraction in the modelling of a digital system poses new problems that should be addressed by EDA tools [2].
Sentence 2: the higher abstraction level implies that the models described at the TLM level can represent functional descriptions of the system prior the hw/sw partition and even before the choice of the target architecture.
Relationship: entailment
Domain: Hardware
Sentence 1: However, unlike in the ISF, they can be regarded conversely.
Sentence 2: it represents a pair of ISF s. If (hi,1 .hi,0)(hj,1 .hj,0)= 0 holds for any (i,j) where i = j, i =1,...,m and j =1,...,m, then the SPFD represents 2m ISF s. The ISF s can be represented a functional expres­sion in Table 1 where 0 or 1 can be assigned to ai in g for each i =1,2,...,m. Like MSPF s and CSPF s in the Transduction Method, SPFD s are used to determine whether wires can be removed or replaced.
Relationship: entailment
Domain: Hardware
Sentence 1: The percentage of misspeculated load instruc­tions avoided is between 4% (eon ) and 67% (gzip) and the average is 26%.
Sentence 2: the number of reduced wrong­path loads is signi.cant for benchmarks vpr and twolf in which the number of loads are reduced by 30 and 20 mil­lions respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: A partial solution state can be de.ned as the quar­tet {Sc is the un- H , SV ,last_layer, extra_bend_count},where SV ordered set of vertical segment IDs, and Sc is the unordered set of H pairs of horizontal segment IDs and partial wirelengths.
Sentence 2: while the lengths of the vertical segments are discrete, the lengths of the horizontal segments are continuous variables.
Relationship: entailment
Domain: Hardware
Sentence 1: 2.3.3Peak-picking After the above procedures, picking the onsets, , is reduced to the identification of local maxima above the defined threshold, which can be summarized as [17]:  (18) 3.APPLICATIONS TO HCI It is possible to use the onsets obtained with any of the methods described above to create more general algorithms that can be used in specific high-level processing of music, like, for instance,easier music-similarity discovery [6].
Sentence 2: successful onset detection can be an important first step in the improvement of the current music recommendation systems, facilitating the user's work in finding new and unknown music that he will probably like.
Relationship: entailment
Domain: Hardware
Sentence 1: Dynamic energy consumption is split into energy due to computation and energy for data transfer.
Sentence 2: edyn = Ecomp+Exf er = D·(EP Bcomp+EP Bxf er ), where EP Bcomp is the average energy spent on processing a single byte of input and EP Bxf er is the average energy spent on data transfer per single byte.
Relationship: entailment
Domain: Hardware
Sentence 1: In order to be generated, the initial LFSR state should be updated according to the solution of the system (i.e., assuming Gauss-Jordan elimination, all the variables belonging in the pivot columns of the system should be re­placed by linear expressions of the free variables).
Sentence 2: if system svi,j = t is solvable, then test cube t can be encoded at the corresponding position of the search space.
Relationship: entailment
Domain: Hardware
Sentence 1: PRIORITY ASSIGNMENT STRATEGIES OF PROCESSING ELEMENTS 3.1 Overview This section explores the PASPL problem in a more un­restricted fashion.
Sentence 2: we would consider two cases in this section: (1) an approach to verify the feasibility of a bus transaction graph, and (2) an approach to reduce the number of priorities for each PE to meet the deadlines of a bus transaction graph.
Relationship: entailment
Domain: Hardware
Sentence 1: Therefore, the GHB-PC/DC scheme, which is essentially an address-based correlation prefetcher, was selected as one of the comparison points.
Sentence 2: two dif­ 45% 40% 35% 30% 25% 20% 15% 10%  % Performance Improvement BW = 3.2GB/s BW = 6.4GB/s BW = 9.6GB/s 5% 0% -5% Prefetch Degree Figure 8: Effect of available memory bandwidth on epoch-based correlation prefetcher performance.
Relationship: entailment
Domain: Hardware
Sentence 1: , the p,k p+1,k added (P +1)th finger can increase system performance only if the following condition holds.
Sentence 2: 42 2 2 A2F + A F +8(AF+ 2PB)(P+1)A B 2 h + h > P+1,1 P+1,2 2{AF +2PB} - A (17) Compare Equ.
Relationship: entailment
Domain: Hardware
Sentence 1: 2b-3) Oldest-.rst: Ready commands from older requests over those from younger requests.
Sentence 2: sTFM uses either the baseline FR-FCFS policy (if the level of unfairness across threads with ready requests is ac­ceptable), or a fair FR-FCFS policy in which requests from the most slowed-down thread receive highest priority.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition, the destina­tion variable points to the same set of unde.ned val­ues as the source.
Sentence 2: if A:=Bis executed and the unde.ned .ag of Bis set, then the unde.ned .ag of Ais set, Ais added to the unde.ned value set of B, and Ais set to point to the same unde.ned value set as B.
Relationship: entailment
Domain: Hardware
Sentence 1: This paper deals with the problem of clock tree construction, which we re­fer to as clock tree synthesis (CTS).
Sentence 2: we ad­dress the following important questions that arise in CTS: (1) What are the factors that can a.ect the robustness of the clock tree solutions; (2) Can clock tree structures meet the skew requirements in the presence of variations?
Relationship: entailment
Domain: Hardware
Sentence 1: In the example of Figure 2.b three cells (namely 1, i and l) have been chosen by the seed-selection algorithm and, as a result, two test vectors are generated by each one of them, starting from the same initial seed.
Sentence 2: each seed is expanded to the predetermined number of test vectors (which is equal to 6 in our example) in different test phases (hence the name multiphase).
Relationship: entailment
Domain: Hardware
Sentence 1: The second contribution is the investigation of perceptual is­sues related to clustering and premixing, based on pilot user studies we conducted.
Sentence 2: we investigate the in.u­ence of visuals on audio clustering for audio-visual scenes, and propose a modi.ed metric taking into account the indica­tion that it is probably better to have more sources in the view frustum.For scalablepremixing, weevaluated the different metrics which can be used, including recently developed per­ceptual models, such as the audio saliencymap [Kayser et al.
Relationship: entailment
Domain: Hardware
Sentence 1: Interestingly, using this tool to program in par­allel the nodes over the USB tree we were able to save 66% in programming time with respect to a classical serial pro­gramming.
Sentence 2: in the DEMMON1 deployment, it took around 30 minutes to serially program a patch com­posed by 100 nodes, while with this tool the programming time reduced to no more than 10-12 minutes.
Relationship: entailment
Domain: Hardware
Sentence 1: The key idea to guarantee privacy is obfuscated program execution in hardware; to evaluate an arbitrary in­struction, Ascend gives o. the signature of having evalu­ated any possible instruction.
Sentence 2: for an arbitrary ' batch program P , any two encrypted inputs x and x(the user s private query), and any two sets of public input y and y' (server s public data), Ascend guarantees that from the perspective of the chip s input/output (I/O) pins P (x, y) ' ' is indistinguishable from P (x, y), therefore satisfying the criterion for oblivious computation [14].
Relationship: entailment
Domain: Hardware
Sentence 1: Due to the huge potential variances in device characteris­tics, microarchitectures can no longer be designed with an egalitarian view of hardware resources.
Sentence 2: .xed parameter leakage models and optimizations will become in­creasingly less e.ective because they can only target the fraction of chips which have no imperfections, ignoring the ma jority of chips which have signi.cant on-chip variations.
Relationship: entailment
Domain: Hardware
Sentence 1: The procedure is based on the idea that n-to-1 multiplexers are generally decomposed and implemented by smaller muxes ordered in a tree structure [1]; therefore, in order to minimize the probability that a fault occurred in a crossbar cannot be traced it is important that the registers are assigned following the rules reported in Table I.
Sentence 2: it is mandatory that registers encoded with a bit string having Hamming distance equal to 1 are assigned with different logic values, in order to detect stuck-at faults that occur on the selection of a register in both writing or reading operations.
Relationship: entailment
Domain: Hardware
Sentence 1: We make the following observations: If there is a finite state-path of length m+1 where q=true in all the m+1 states, then this finite segment is also the prefix to an infinite path where q is globally true (a witness loop).
Sentence 2: if there is no path from initial states I(s) of length m+1 where q is true in all the m+1 states, then the property F(¬q) is proved correct.
Relationship: entailment
Domain: Hardware
Sentence 1: For on-chip and on-board applications, it is im­portant to be able to estimate the effect for single wires rather than complete transmission lines, and with a rectangular rather than cir­cular cross-section.
Sentence 2: wires with high aspect ratios Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: entailment