sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: We directly connect p3 to s2 by a horizontal line from p3 since it is in the Steiner range of s2.
Sentence 2: in Figure 3 (b), since p3 is not in the Steiner range of s2, we would connect p3 to one of endpoints in s2 with a shorter wirelength, which is pa.
Relationship: contrasting
Domain: Hardware
Sentence 1: Sharing FPUs is not a new idea per se: for instance, the high performance Bulldozer architecture from AMD shares a .oating point unit among multiple instruction fetch pipelines [3], and sim­ilar solutions have been adopted in the past by complex out-of-order superscalar processors [4].
Sentence 2: in radical departure from high-performance architectures which im­plement sharing with complex HW queues, reservation sta­tions, speculative execution support, we developed a stream­lined, ultra-low overhead solution, with minimal area over­head (which tightly correlates with leakage), tailored to low­complexity, single-issue in-order execution pipelines.
Relationship: contrasting
Domain: Hardware
Sentence 1: Note that these speed-ups are obtained not because computations are parallelized (tiles are run in sequential), not only because the communications are pipelined (this is also the case in the original versions), but (i) because DDR requests are reorganized to get successive accesses on the same row as much as possible, (ii) because some communications overlap computations, and (iii) because some data reuse is exploited.
Sentence 2: to achieve this, there is a (moderate) price to pay in terms of hardware resources, in addition to the local memories involved to store the data locally.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4.1 Write Endurance While wear-leveling has been studied for resistive memo­ries, speci.cally PCM [22][7], it was in the context of hybrid main memory.
Sentence 2: our application is di.erent in terms of latency requirements (replacement of SRAM), frequency  Figure 2: Neural predictor prediction and training Figure 4: MPKI for SPEC CPU as the size of the perceptron table increase from 29 rows to 218 rows.
Relationship: contrasting
Domain: Hardware
Sentence 1: Resistivity (ohm-cm) 0.01 0.1 1 10 Skin depth (um) @ 50 GHz 22.5 71.2 225 711 Rational Function Fit Method (RFFM): Computation of the Substrate Green s Function: A straight-forward approach to evaluate the substrate Green s function is to use numerical integration techniques [11].
Sentence 2: this approach is computationally too expensive to handle complex VLSI interconnect configurations typically An alternative method for evaluating the substrate Green s function involves approximating the substrate contribution by a rational function which can be integrated analytically [14].
Relationship: contrasting
Domain: Hardware
Sentence 1: The software consists of three separate program parts: Module A: Mutual authentication based on AES  Module B: PIN veri.cation  Module C: Balance transaction  The AES key management, encryption and decryption was purely carried out in software.
Sentence 2: this software part was spared from fault simulations throughout this work, since in real security microcontrollers, the AES will be computed by speci.c hardware circuits protected by hardware counter­measures [19].
Relationship: contrasting
Domain: Hardware
Sentence 1: Compared to single core design, CMPs provide throughput improvement for multi­threaded and multiprogrammed workloads.
Sentence 2: since manyon-chip platform resources, such as the lowest level on-chip cache andoff-chip bandwidth, are sharedby all the processor cores, the performance and throughput of pro­ *This work is supported in part by the National Science Foundation through grant CNS-0406306 and CCF-0347425, and by gifts from Intel.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since the RC logic checks the message header and is typically very small comparedtootherlogicssuchasarbiters,itisbesttoput them in the same layer where the header information resides; we can avoid feeding the header information acrosslayers,therebyeliminatingtheareaoverheadsfrom inter-wafervias.Inthispaper,wefixthenumberofVCs perPCtobe2andevaluatetheincreaseinRClogicarea andpower.Thechoiceof2VCsisbasedonthefollowing design decisions: (i) low injection rate of NUCA traffic (ii) to assign one VC per control and data traffic, respectively (iii) to increase router frequency to match CPUfrequency,and(iv)tominimizepowerconsumption.
Sentence 2: the proposed technique is not limited to this configuration.
Relationship: contrasting
Domain: Hardware
Sentence 1: The ISS-SystemC communication is sim­pli.ed by using these new ports.
Sentence 2: the original implementation of the GDB-Kernel mecha­nism requires the de.nition of ad hoc processes (ISS PROC) to use iss in and iss out ports, and a heavy modi.­cation of the kernel to manage ISS PROC activation.
Relationship: contrasting
Domain: Hardware
Sentence 1: According to the roo.ine model shown in Figure 2, it is expected that the peak sustained performance improves by 10% due to 10% increase in the .op/total byte ratio.
Sentence 2: in CFD, the computational e.ciency increases by only 6% due to the decrease in cache hit rate from 51.3% to 46.2%.
Relationship: contrasting
Domain: Hardware
Sentence 1: METHODS 3.1 LPCWT response model To investigate the e.ect of the real, non-ideal, LPCWT circuit it wouldbepossible toperform a co-simulation be­tween Cadence (for the LPCWT circuit) and Matlab (for theremainderof the algorithm).
Sentence 2: cadence time do­main simulations require a large amount of processing time, signi.cantly limiting the amount of EEG data that could be used to validate the algorithm.
Relationship: contrasting
Domain: Hardware
Sentence 1: The architecture description is modi.ed to evaluate the performance and code size of the applications used in subsection 4.1 and 4.2.
Sentence 2: the modi.cation is non­  3.5 800 1.2 700 3 1 600 2.5 0.8 500 400 2 0.6 300 Cycle count Cycle count (normalized to 1­IPB) reference Code size Code size (normalized to 1­IPB reference) (normalized to 1­IPB) Cycles (million) 1.5 0.4 200 0.2 1 100 0 0.5 0 (a) Reference performance and code size 1­IPB) 1.2 3.5 1 3 Figure 9: Results of MPSoC DSE the following context: A H.264 baseline decoder application is parallelizedby software developersintoa scalable applica­ tion, i.e., engaging more processors can improve theperfor­ mance of the application.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since the number of blocks in each cache region is region By dividing the SRAM into smaller sub-arrays, we can in­ crease the total number of defective bit-cells that can be repaired without using too many spares in each sub-array.
Sentence 2: in­,creasing the number of sub-arrays also increases the intercon­ there is a one-to-one mapping relation between blocks in one cache region and all sets in the cache.
Relationship: contrasting
Domain: Hardware
Sentence 1: This gain can also be confirmed by the bandwidth reduction in these cases (shown in Figure 9).
Sentence 2: in the cases where greedily satisfying the first buffer requests will severely reduce the available space for subsequent requests that may more efficiently use the buffer space, BiN-Dyn behaves considerably worse compared to the first three schemes, as can be seen in the 2P/4P cases with large input sizes.
Relationship: contrasting
Domain: Hardware
Sentence 1: The total memory power becomes comparable to the processor power on applications with high memory de­mand(Figure6(c)).
Sentence 2: sincetheperformance ofthese applications varies less than before as the number of rank subsets changes, the energy-delay product improves less as multiple subsets are used: 0.8% onSPLASH-2 with2,12.1% on SPEC CPU 2006 with 4, and 7.9% on PARSEC with 4 rank subsets all compared to the con.guration utilizing a low-power mode but no rank subsetting.
Relationship: contrasting
Domain: Hardware
Sentence 1: During the stage 2 hold phase, there can be some downward glitching due to CSG between do21 and do32, in this scheme the parasitic capacitance CGD to do11 does not hurt logic 1 integrity, since do11 is actually precharging during the stage 2 hold phase.
Sentence 2: in this sequencing scheme, logic 0 glitching is an important consideration.
Relationship: contrasting
Domain: Hardware
Sentence 1: Technology scaling also gives rise to new error sources: For instance can the e.ects of neutrons (which have formerly only been a concern with memories) now cause upsets in logic elements and low power/low capacitance buses as well [9].
Sentence 2: the main source for errors on buses will be crosstalk, which can lead to increased delay or cause voltage glitches on wires [4].
Relationship: contrasting
Domain: Hardware
Sentence 1: The pixels in both Figure 1(b) and Figure 1(c) do not numerically match with the ones in Figure 1(a).
Sentence 2: the primary difference between these two .gures is that in Figure 1(b) only few of pixels are incorrectly computed thus causing an impercep­tible difference while in Figure 1(c), a large slice of pixels are incorrectly calculated causing a perceptible change.
Relationship: contrasting
Domain: Hardware
Sentence 1: Finally, adding dictionary-based compression (denoted CPACK+Z), increases the average compression ratio to 3.9 and the decompression latency to 9 cycles (see section 5.1) [9].
Sentence 2: because multi-megabyte LLCs already have relatively long access times (e.g., 30 cycles) and very high miss penalties (e.g., greater than 150 cycles and ~60 nJ), the benefit of higher compression ratio has the potential to outweigh the longer decompression pipeline.
Relationship: contrasting
Domain: Hardware
Sentence 1: That work uses a Utility Monitoring Circuit (UMON) [13] for adapting the cache replacement policy in the shared LLC by tracking run­time miss rate information of the individual applications.
Sentence 2: the use of UMON comes at the cost of additional hardware overhead for maintaining shadow tags (a shadow tagis similar to a regular cache structure except that it only con­tains the tag array).
Relationship: contrasting
Domain: Hardware
Sentence 1: While, pre-silicon veri.cation, which val­idates the RTL description of a design, is e.ective for indi­vidual components [6], system-level validation is spotty at best, given the limited scalability and performance of the tools available.
Sentence 2: post-silicon validation o.ers the high performance necessary to investigate the correctness of system-level functionality in depth and expose complex bugs.
Relationship: contrasting
Domain: Hardware
Sentence 1: Our fanout-distribution based 123456 Circuit Ours Length 1 Xilinx-like Length Ours Length 1 Xilinx­like 1 0.47 1.00 .25 2 0.18 - 0.125 4 0.35 - 0.375 quarter­long - - 0.25 architecture (our architecture is tuned for each circuit based on that particular circuit s fanout distribution) achieves overall area that is almost identical to that achieved by the previous architecture (in 2 cases, we achieved slightly smaller area).
Sentence 2: when we place and detail route the test circuits on a Xilinx-like architecture, an increase of 11% in the overall area is observed.
Relationship: contrasting
Domain: Hardware
Sentence 1: The maindrawback of these controllersis that their applicability is limited to single applications whose memory behavior can be exactlyspeci.ed atdesign time, whichis typically not the case in MPSoCs.
Sentence 2: note that such an application­speci.ccontrollercanexploitlocality,since knowledgeabout the exact memory access trace enables rows to be opened and closed in an optimal manner, resulting in a highly e.­cient, although very restrictive solution.
Relationship: contrasting
Domain: Hardware
Sentence 1: Moreover, multi­core architectures favor simpler and smaller cores, which limits the opportunity to exploit the available ILP with wide-issue cores.
Sentence 2: special-purpose hard­ware accelerators that are located outside the core can im­prove a thread s performance by eliminating control and memory bottlenecks (e.g., advanced branch predictors and data prefetchers), but they often result in signi.cant chip area additions and additional complexity.
Relationship: contrasting
Domain: Hardware
Sentence 1: 1 µ = L w¯m (8) M m 1 2 2 T S= Swm - µ)( ¯(9)L + ( ¯wm - µ) M m m Many machine learning driven IR systems use a point es­timate of the parameters at di.erent stages in the system.
Sentence 2: we are estimating the posterior distribution of the variables at the E step.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is a consequence of the good matching between the wavelength parallelism of space-routed ONoCs and the bit parallelism of electronic NoCs.
Sentence 2: wavelength-routed ONoCs (WRONoCs) are fundamentally different from electronic and space-routed optical networks, since they inherently deliver full connectivity (i.e., contention-free and potentially parallel communication between every master and every slave) while sharing the bandwidth of optical paths between multiple communication flows.
Relationship: contrasting
Domain: Hardware
Sentence 1: Information-.ow tracking has been a central idea to the security community for decades, yet since the introduction of the commer­cially unsuccessful Intel iAPX 432 in 1982, it has not seen sup­port in commercial microprocessors.
Sentence 2: as transistor bud­gets continue to increase, many have argued that tagging is a nat­ural, and minimally intrusive way of enforcing information-.ow policies on modern CPUs.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this case, we can define the logic values of the r-th bit as j2p(2r-1) f0t Lr (t) =e (2) j2p2rf0t Hr (t) =e (3) In this case, the highest frequency in the system will be the sum of all the utilized harmonics from 1 to 2N, that is, N(2N+1)f0, which is scaling with N2.
Sentence 2: this system will be degenerated because of the frequency-overlapping when forming the hyperspace vector.
Relationship: contrasting
Domain: Hardware
Sentence 1: While it is believed that the yield loss due to system­atic sources is greater than that due to random defects during the technology and process ramp-up stage, the systematic yield loss can be largely eliminated when the process becomes ma­ture and systematic variations are extracted/compensated.
Sentence 2: the random defects which are inherent due to manufacturing limitations will still be there even for mature fab­rication process [17].
Relationship: contrasting
Domain: Hardware
Sentence 1: Line Delay [psec] Glitch Peak [V ] Length SPICE TWA SPICE TWA 1mm 10.7 9.5 2.452 3.0690 2mm 18.9 16.9 2.4743 2.9691 5mm 113 93.5 2.2505 2.5470 10mm 258.4 299.9 1.8435 2.0068  Up to now, we considered only the typical cases in which the input signals switch from logic 0 to logic 1.
Sentence 2: there are other cases in which some of the input signals may switch from logic 0 to logic 1 while rest of them switch from logic 1 to logic 0.
Relationship: contrasting
Domain: Hardware
Sentence 1: Column RS1 and RS2 shows the area of the resource sharing only approach using a .xed module selection.
Sentence 2: column Combined uses the full library for module selection, and also combines the resource sharing approach as described in Section 5 cost of the synthesized pipelines decreases as the through­put constraint is relaxed.As the d constraint is reduced the module selection process can select lower area cost circuit modules that operate at a higher initiation interval.Further, with a larger number of cycles in a pipeline stage, there is more chance to share an allocated module.reduc­ing d does not necessarily reduce the area of the circuit.The ability of the scheduling/module selection/resource sharing algorithm to .nd a lower area cost solution depends on the circuits in the module library.
Relationship: contrasting
Domain: Hardware
Sentence 1: ThedarkerregioninFigure5meanshighertempera­ture.Tomaketheroutingwirelear,thetemperature proflesareonlyshowninthebloks.Figure5(a)shows theresultswithoutonsideringvariation.Tomakethe omparisonfair,weusetemperatureprofletoalulate themeandelayvalue.Systemivariationsarealsoon­sidered.InFigure5(b),allvariationsareonsidered andtheshortestpathisfoundbysolvingtheSSPprob­lem.ItislearthatthepathinFigure5(b)intelligently avoidsthehotspots.
Sentence 2: 5.2 Time Analysis Itisalwaysaonerntopredittheiruitperfor­maneaurately.Preisetiminginformationisneeded foriruitoptimizationtomeettheyieldortoavoid overdesign.Timinganalysisonsideringvariationsis extensivelystudiedreently.Path­basedorblok­based algorithmshavebeenproposedtofndthestatistial longestpathsandthedelaydistributions.Path­based approahesusuallydependonstatitimertofndouta setoflongestpathandidates,andthenthestatistial approahesanbeperformed[10,11].Blokbasedal­gorithmsangetthedelaydistributionsbypropagating therandomvariables.theyneedpath­based analysistofndoutthelongestpaths[12,13].
Relationship: contrasting
Domain: Hardware
Sentence 1: However, the curve drops steeply at k =6.
Sentence 2: this is because more than 30% of the rows contain 6 nonzeros, making 6 the best value for k. It would be de­sirable if an algorithm is designed to analyze the sparsity structure 0.9 0.7 0.5 0.3 0.1 k Figure 3: Overhead analysis for sparse matrix lns3937 len(i1) Overhead Figure 4: Improved architecture for the design of each speci.c matrix and .nd the optimum k. such an algorithm may not contribute to the overall performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: By assigning double-via costs to the routing graph, they formulated the problem as a multi­ob jective maze routing problem and applied Lagrangian relax­ation to solve it.
Sentence 2: they only consider the redundant via at the detailed routing stage, their cost modeling for the num­ber of vias is not accurate enough, and the high time complexity of Lagrangian relaxation limits the feasible problem size to be within hundreds of nets.
Relationship: contrasting
Domain: Hardware
Sentence 1: P-channel SF works for voltage ranging from below 0 V to Vdd-Vthp, where Vddand Vthp are the supply voltage and the threshold voltage of P-type MOSFET, respectively.
Sentence 2: n-channel SF works for voltage rang­ing from above Vdd to Vthn, where Vthn represents the threshold voltage of N-type MOSFET.
Relationship: contrasting
Domain: Hardware
Sentence 1: Flexible Transmission Gate Design 4.1.1 Motivation If the VSUBVT rail is always kept at a subthreshold voltage, using an NMOS power switch is optimal since a near minimum sized transistor would provide the target frequency requirement.
Sentence 2: if the rail connecting the header to the component needs to be a flexible and encompass a wide range of VDDs, the NMOS fails as a power switch above VT due to the VT drop seen across the NMOS.
Relationship: contrasting
Domain: Hardware
Sentence 1: For an MTCMOS design, the header/footer switches and retention .ip-.ips are imple­mented in high-Vt transistors, such that their leakage current can be lowered during the sleep mode.
Sentence 2: the power-gated logics are implemented in low-Vt transis­tors, such that their performance can be increased during the active mode.
Relationship: contrasting
Domain: Hardware
Sentence 1: N receive M transmit M channels M independant antennae estimates  Figure 1: The proposed noise whitener attempts to counteract the .ltering e.ect imposed on the AWGN channel noise The standard method of noise whitening is based on the Cholesky decomposition of the covariance of the noise at the output of the equaliser.
Sentence 2: this method requires arithmetic divisions and square roots, operations that are preferable to avoid in hardware due to their complexity.
Relationship: contrasting
Domain: Hardware
Sentence 1: Basic Scheme of a two level LSQ based on ExecutionLocality  3.2 Epoch-based Load/Store Queue We propose to partition the LSQ based on Execution Lo­cality[6].Forhigh-localitymemoryreferenceswekeepa .rst high-locality LSQ, while low-locality references occur in the low-localityLSQ.Low-localityaddress calculations are more latency tolerant.
Sentence 2: store-load forwardings from low­localitystores tohigh-localityloads are critical.
Relationship: contrasting
Domain: Hardware
Sentence 1: High assurance and life-critical systems, such as aircraft control systems and implantable cardioverter­de.brillators and also systems used in banking and the mili­tary, all require strong guarantees about their security prop­erties.
Sentence 2: designing systems with provably strong security properties can be extremely challenging and costly; just assessing the assurance of the resulting system can cost upwards of $10,000 per line of code [3].
Relationship: contrasting
Domain: Hardware
Sentence 1: Exploring the direction of node 1, which has a latency of 0.3 cycles, would get 0.15 * 10 =3.3 points.
Sentence 2: growing toward 0.15+0.30 node 10, we would get nearly all ( 0.15 *10 = 10) the points 0.15+0 allotted for latency.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since the redundant path and TGs in the TFU will be exactly reused by the 2D redundant clock tree, TFU can be constructed with little area overhead, while increasing the yield rate as much as that of the double-TSV technique [5] that requires too many new TSVs.
Sentence 2: to be practically effective in using TFUs, a number of important issues that have not been fully or never been addressed should be resolved.
Relationship: contrasting
Domain: Hardware
Sentence 1: Because of the complexity of the FIFO description, the compiler could not derive optimal annotations in the modular flow, or rule schedules in the flat flow.
Sentence 2: by allowing the designer to alter the annotations of the FIFO module (something he only has to do once and can then reuse in all processor designs), we were able to achieve optimal schedules in all modular compilations.
Relationship: contrasting
Domain: Hardware
Sentence 1: Hence, asserting a pair contract requires .rst asserting its component contracts.
Sentence 2: to obtain completeness, it would be su.cient to seq these computations together: asrt_too_strict (Pair c f) =  (x, y) -> let x = asrt_too_strict c x y = asrt_too_strict (f x ) y in x seq y seq (x , y ) this implementation would be more strict than necessary as evidenced by the divergence of the following contract assertion.
Relationship: contrasting
Domain: Hardware
Sentence 1: Recovering from RIB has a higher penalty than recover­ing from IQ because RIB recovery is not selective and the distance from the recovery stage to the resolution stage (forwarding check in STB2) is larger [3].
Sentence 2: the to­tal cost computed as the number of forwarding misspecula­tion multiplied by the misspeculation penalty, may be lower than the degradation of stalling dispatch when IQ is full.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since Fx is a 0-approximation of Fy, the fault Y stuck-at 0 will always violate the self-testing property as X=1, Y=1 is the only input vector that can test Y stuck-at 0.
Sentence 2: for Y stuck-at-0, the input to the checker becomes X=1, Y=0, which is a valid codeword and so can­not detect the fault.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is a reasonable assumption for the 0.25µm-or older technologies.
Sentence 2: the critical .eld depends on Vgs in the 65nm-technology, and the BSIM3v3 SPICE model [1] uses 2vsat Ua Ub Ec = [1 + (Vgs + Vt)+ t2 (Vgs + Vt)2], (2)µ0 tox ox to specify this dependency.
Relationship: contrasting
Domain: Hardware
Sentence 1: 1) Integrated placement and routing approach (IPR) 2) ROOSTER followed by FastRoute2.0 (ROOSTER + FR2.0) 3) Routability-driven FastPlace followed by FastRoute2.0 (R-FastPlace + FR2.0) 4) FastPlace followed by FastRoute2.0 (FastPlace + FR2.0) For Routability-driven FastPlace, we follow the framework of IPR.
Sentence 2: instead of applying global routing to get accurate routabilityinformation, we simply construct rectilinear Steiner minimal Steiner trees(RSMT) to break multi-pin nets into 2-pin nets and use probabilisticcongestion model to get the congestion map.
Relationship: contrasting