sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: As shown in Fig.7(a), dead space blocks 2 and 1 are the dead space above and right to block a respectively(Some channels are left as the minimal distance constraints between blocks).
Sentence 2: during the packing process, when the ith block Mi is packed, according to the given CBL, it will cover NMi blocks{BC1 BCNMi} from top( if Li = 0) or from right (Li=1).
Relationship: reasoning
Domain: Hardware
Sentence 1: Low swing operation on the en­tire clock tree without any modi.cations at the sink level would lead to negative impacts on clock slew, skew and logic path tim­ing.
Sentence 2: a previous approach considers to use level shifters at the last level of the clock tree, assuming the overhead of level shifters, in order to keep the signal integrity for logic path timing at the sink level [6].
Relationship: reasoning
Domain: Hardware
Sentence 1: On the other hand, similar to the situation on an obstacle-free plane, no vertex can be in Quad1 of another vertex in the same active group, as there should not be any obstacle within each active region.
Sentence 2: we can implement the active vertex set Av based on a hierarchical balanced binary search tree, i.e., the active regions can be maintained by a balanced binary search tree while the active group in each region is maintained also by one balanced binary search tree, linked from that region.
Relationship: reasoning
Domain: Hardware
Sentence 1: More precisely, a miss occurs at time tif Rt is not in St.
Sentence 2: we de.ne recursively the time indices {.k,k =0,1,...}by .0 =0; .k+1 :=.k +µk+1,k =0,1,... and µk+1 :=inf{ =1,2,... : R.k+ .S.k+ } with the convention µk+1 = 8if either .k = 8or if .k is .­nite but the set of indices entering the de.nition of µk+1 is empty.
Relationship: reasoning
Domain: Hardware
Sentence 1: To .nd P(g:a.a'), the procedure .rst marks n every line in the circuit that participates in a path, which also includes g. For this purpose, the procedure marks every line h such that there is a path from g to h. This is done by traversing the circuit forward starting from g.In addition, the procedure marks every line h such that there is a path from h to g. This is done by traversing the cir­cuit backward starting from g. For a line h, rch(h) =1if there is a path from h to g or from g to h, and rch(h) =0 if there is no such path.
Sentence 2: the set of lines with paths from or to g is denoted by C. C ={h:rch(h)=1}.
Relationship: reasoning
Domain: Hardware
Sentence 1: Two 1-bit registers are used for implementing each ABP circuit (one in the sender and one in the receiver for storing the cur­rent level); faults a.ecting them can cause the execution of a fake request or the loss of a request.
Sentence 2: the e.ects on external communication can be represented with fake and phantom calls, while other function call mutations do not correspond to any possible e.ect of a physical fault.
Relationship: reasoning
Domain: Hardware
Sentence 1: Even though the expected value of (5) gets larger with .2 , E {|H[k]|2} = |H1[k]|2 + .2|H2[k]|2 > |H1[k]|2 (6) the bound (4) is exponential and a strictly convex function of (5), so {|H|2} = E|H|2 {f |H|2 } f E|H|2 (7) (|H|2 d2 ) e where f(|H|2)= exp - 4s2 is the argument of the ex­pected value in the PEP bound.
Sentence 2: performance can get worse as illustrated in Figure 2, which shows the result of simulating an echo over an AWGN channel for di.erent CNR values2 .
Relationship: reasoning
Domain: Hardware
Sentence 1: It is important to emphasize again that although AutoPilot pro­vides these directives for intra-and inter-block optimizations, these optimizations can not always be applied with the default data ac­cess patterns and AutoPilot is unable to identify the optimization opportunities to enable them through transformations.
Sentence 2: the importance of this work is not just that we generate the AutoPilot directives that are already available, but that we automatically im­prove the number of situations in which the directives can be used.
Relationship: reasoning
Domain: Hardware
Sentence 1: In the case of the given ap­plication, no energy-keeping elements were used.
Sentence 2: the result of the equation system is a simple formula: eqn1: The Current-/Voltage Converter eqn2: The Transmission line eqn3: The Voltage-/Current Converter eqn4: The Calibration eqn5: The Measurement bridge eqn6: The Constant Current Source Table 1: Modules and Equations res5 := ul31 = -0.1512858586e-1*Rpdr +0.1512858586e- 1 * Rmdr +0.1599159916 * ul11 +0.8400840084 * ul21 In the next step, BeCom generates models, which imple­ment found solutions, and the analyzed composition.
Relationship: reasoning
Domain: Hardware
Sentence 1: Similar to our LL-MAB model, MCPI is calculated by MAB Wait Cycles divided by Retired Instructions.
Sentence 2: when running at frequency f, one can predict the CPI at frequency f as shown in Equation 1. f' CPI(f')=CCPI(f)+MCPI(f)× (1) f Because this model predicts periodic CPI rather than whole-program execution time (which our previous work demonstrated), we tested its prediction accuracy on single­threaded versions of the 52 benchmarks from our three test suites.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that any area saved by FPU sharing is used to add more .ne-grain cores, taking into account the interconnect and core area as above.
Sentence 2: two competing trends will in.uence performance: (1) an increase in the number of cores will mean more exploitation of parallelism and (2) an increase in FPU sharing may mean worse per-core per­formance due to the overhead of sharing.
Relationship: reasoning
Domain: Hardware
Sentence 1: RM -­ -­ 0.3165 412 295 According to the results presented in [12] and corroborated by Table 1, regular deterministic test routines present the best trade­off between test time and test memory.
Sentence 2: considering only the test requirements of time and memory, a test program composed of three regular deterministic test routines could be considered as the best choice for the Femtojava processor.
Relationship: reasoning
Domain: Hardware
Sentence 1: Epochs can end either as a result of a coherence request another node s Request-ReadOnly (if epoch is Exclusive), another node s Request-ReadWrite, or this node s Writeback-Exclu­sive or as a result of silently evicting a Shared block from its cache.
Sentence 2: inform-Epoch traf.c is propor­tional to coherence traf.c plus some extra traf.c for oth­erwise silent evictions of Shared blocks, instead of being proportional to load/store traf.c as in DVSC-Direct.
Relationship: reasoning
Domain: Hardware
Sentence 1: By replacing the parameters in Equation (7) with the values given in Equation (5), the pole of each application controller s transfer func­tion would be: z = aik - c × k1 - w × k2 - m × k3, (8) assuming that, in Equation (7), B is (cwm)and K is a vector with three elements, k1, k2 and k3 .
Sentence 2: to ensure stability of our system, the Kvalues are determined such that |z|< 1in Equation (8).
Relationship: reasoning
Domain: Hardware
Sentence 1: Since low distortion architectures require analog circuits, which process the quantization noise only, they end up having low output swing in analog building blocks.
Sentence 2: the Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: reasoning
Domain: Hardware
Sentence 1: Current (in A) 0.009 0.010 The philosophy behind using two cosine terms is that one cosine term would produce a basic decaying sinusoid (as in the triangular case) and the other would account for the deviations from the decaying sinusoid that are seen at low Hamming distance.
Sentence 2: the variable time period Ti is used with only one of the two cosine terms, the one which is aimed at generating the decaying sinusoid.
Relationship: reasoning
Domain: Hardware
Sentence 1: COMPACT S/D CONTACT MODEL The lithography variation could vary the S/D contact shape, area and even distance from gate line, which causes the performance degradation as we see in Section 2.
Sentence 2: we should take the impact of S/D contact variation on the that we get an accurate S/D contact resistance by exhibiting both the horizontal distance weighting factor and the shape weighting factor of the vertical direction.
Relationship: reasoning
Domain: Hardware
Sentence 1: However,[15]does not address thedifference or similarity betweenrealdesignsandeyechartcircuits.
Sentence 2: in[15],the eyechart circuitsarebuiltfromthreebasictopologies chain,mesh and star andthe resultingtopologiesdiffer substantiallyfromthose of real designs in terms of Rent parameter, path length and other param­eters.1 the eyecharts may be helpful in measuring subopti­mality ofheuristics,butdo nothave clearimplicationsforheuristic performance on realdesigns.
Relationship: reasoning
Domain: Hardware
Sentence 1: Both the Guaranteed Integrity (GI) and Minimum La­tency (ML) modes can be implemented with one code, us­ing the property that every SEC code can also work as DED code: The same codewords are used for transmission, the en­coder is identical and the DED code just uses the .rst part of the decoder block.
Sentence 2: these two services o.er the same bandwidth to the application, but di.erent protection char­acteristics.
Relationship: reasoning
Domain: Hardware
Sentence 1: For applica­tions such as mobile phones and PDA, .ip-.ops need to consume very little power and operate at high speed [5].
Sentence 2: lowering the power consumption of .ip-.op and Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies arenot made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: reasoning
Domain: Hardware
Sentence 1: The large bias of stored bits toward zero [7] has been the motive in [1] to design asymmetric SRAM cells that employ higher Vth for the transistors that leak when the cell stores 0.
Sentence 2: such asymmetric cells dissipate far less leakage in the 0 state; the delay penalty is minimized by Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: reasoning
Domain: Hardware
Sentence 1: As [19] pointed out that 5% IR drop in supply voltage may slow down circuit performance by as much as 15% or more.
Sentence 2: iR drop is a .rst-order e.ect and can no longer be ignored during the design process, and it is desired to consider the P/G network synthesis during early physical design (e.g., .oorplanning) for reliable circuit operation.
Relationship: reasoning
Domain: Hardware
Sentence 1: Again, to make the ASF-B*-tree of a 2D symmetric placement automatically symmetric-feasible, the representative of a symme­ try pair must abut one of the symmetry axes, and that of a self­symmetry module must abut both symmetry axes.
Sentence 2: we have left-boundary, bottom-boundary, and corner constraints for with 2D symmetry.
Relationship: reasoning
Domain: Hardware
Sentence 1: Basically, it depicts the acceleration scaling problem, when only a part can be accelerated due to communication overhead or sequential dependencies in distributed processing.
Sentence 2: if we denote the percent of code that can be accelerated by p, the acceleration acc of a multiprocessor is given by: 1 A(N, p) = p (1 - p) + N Using ten cores, will give us an ideal acceleration of ten.
Relationship: reasoning
Domain: Hardware
Sentence 1: Figure 8: Basic refresh procedure Dual-Retention PCM Chips As mentioned in Section 2, PCM s retention capability is re­lated to the width of the target bands.
Sentence 2: to provide two write modes with different retention guarantees to the memory controller, as shown in Figure 6, a PCM chip in­cludes two sets of resistance parameters (i.e., target bands and read boundaries), which correspond to the two reten­tion levels for working memory and persistent store.
Relationship: reasoning
Domain: Hardware
Sentence 1: When performing CG cloning, T EL and T CG can­not be changed due to .xed fEN and enable logic locations, and gate delay.
Sentence 2: the control-path timing constraint can be derived, as seen in Equation (3), where Ti en is determined by the wirelength from the enable logic to gi, and Ti gclk is determined by the wirelength from gi to all its fanout .ip-.ops and the number of total fanout .ip-.ops.
Relationship: reasoning
Domain: Hardware
Sentence 1: Trace Preconstruction Quinn Jacobson Sun Microsystems 901 San Antonio Road Palo Alto, CA 94303-4900 408 616-5655  quinn.jacobson@sun.com ABSTRACT Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets.
Sentence 2: their performance may suffer due to capacity and compulsory misses.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3.5 Line-Level OD3P Up to now, we assumed that each line of a page is equipped with ECP-6 to tolerate 6 permanent bit failures, and when the .rst line encounters the 7th bit failure, the line and hence the corresponding page is marked as faulty.
Sentence 2: the .rst line failure invalidates a page, while other lines of the page may be far from their lifetime limits.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, Figure 6 shows that the lateral stress7 behavior near the interface of the two nitrides is compressive under  1.16 1.14 1.12 the tensile nitride (NMOS side) and tensile under the compressivenitride (PMOS side).
Sentence 2: if possible, it would be beneficial tomove the PMOS active area into this region of tensile stress and the NMOS away from the region of compressive stress.
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, for simplicity, in the rest of this presentation, we will use PCM for our discussion.
Sentence 2: when slacks are represented as a functional form of the underlying process parameters .Xk as done in most recent statistical static timing analysis (e.g., in linear form [10], or in quadratic form [14]), the authors of [11] have shown that the PCM as shownin (6) canbe computedinlinear time O(mn)and space O(n)withthe number of layers m typically much smaller than n. we use PCM as a metric to guide our path selection such that the selected n paths have the maximum PCM (or equivalently, the maximum TQM).
Relationship: reasoning
Domain: Hardware
Sentence 1: R0= P---------- --------, -----------­ = [] ------------------------ PN e u'.p 2 y .. 2pfclock IPD Rp OSR Note that the average power of the jitter-induced noise at the output of the .S modulator is a decreasing function of the OSR which is the ratio between the sampling frequency, fs, and the passband .fBW.More­ over, the output noise power is directly proportional to the power of the time-derivative of the input signal.
Sentence 2: the .S modula­tor will exhibit more noise for high-frequency and higher amplitude input signals.
Relationship: reasoning
Domain: Hardware
Sentence 1: should be above a minimum value to guar­antee enough distinguishability for the whole cell;  The programming voltage should not exceed a maximum voltage;  For memristor, the read speed is much faster than write speed.Therefore, the operation speed mainly depends on the write speed.
Sentence 2: the write speed should be lower-bounded;  Finally, the energy consumption for read and write a memory cell should not exceed certain power budget.
Relationship: reasoning
Domain: Hardware
Sentence 1: Furthermore, by introducing a phase in between the shift clocks used for different clock domains, the number of .ip-.ops that latch values at the same time will be limited to the number of .ip-.ops per clock domain, thus avoiding the excessive voltage drop on power/ground lines.
Sentence 2: in this paper, we propose a power-constrained wrapper for cores with multiple clock domains, by extending the design pro­cedure from [21], so that different clock domains can use distinct shift clock signals.
Relationship: reasoning
Domain: Hardware
Sentence 1: In this case, the cascade of latches only increases the e.ective Tmet.
Sentence 2: our formula for the MTBF of multi-stage syn­chronizers can be expressed as:   SiTmet,i c2 e MTBF = (15) Fd *Fc *c1 Although this is clearly not the case for sequences of master­slave .ip-.ops, we use it as a worst-case bound.
Relationship: reasoning
Domain: Hardware
Sentence 1: ThediferencebetweenLoadBalancedRadixsortandour algorithmisthatwepartitionthefrontierbucketsintoa setofsmallerbucketsandassignadiscretenumberofthose smallbucketstoeachofthetwoprocessorwhiletheLoad BalancedRadixsortjustdividesthefrontierbucketintotwo parts.
Sentence 2: pCS-Radixsortdoesnotachieveaperfectload balancebutimprovestheperformanceofLoadBalanced Radixsortbecausewefocusonsolvingthethreemainprob­lemsofRadixsort.
Relationship: reasoning
Domain: Hardware
Sentence 1: [17].Thisscheme(referredto asSvin[23])detectsreusebasedonoperandvaluesandwas showntobethebestperformingschemewithlargebufer sizes.InSodaniandSohi'sstudy,theprocessorisassumed tohaveafxed-sized12-portedreusebuferandbufersizes from0.5KBto12KBareconsidered.Aninstructionentry inthereusebuferstoresthesourceanddestinationoperand valuesandpartofthePCtoidentifytheinstruction.When aninstructionisdecoded,itssourceoperandvaluesarecom­paredwiththoseintheinstructionreusebuferentrycorre­spondingtothisinstruction.Ifthereisamatch,theresultis directlyreadfromthebuferandtheexecutionstageisby­passed.Loadandstoreaddressesaswellasloadvaluesare storedintheinstructionreusebufer.Toensureconsistency ofdata,onastore,theimplementationin[23]requiresafully associativelookupofthereusebuferforpossiblematching entries.
Sentence 2: instructionreusebuferimplementationwithrecon­fgurablecaches.Whenimplementinganinstructionreuse buferasapartitionofareconfgurablecache,weneedto makeafewchangestotheabovedesigntoaddress(i)the limitednumberofportsforthecache(4cacheportsvs.12 portsintheinstructionreusebufer),(ii)thelargerSRAM sizesandtheinabilitytoperformassociativelookups,and (iii)increasedlatencies(weassumethatthecacheaccess takes2cyclesasopposedtoonecycleforasmallerdedicated instructionreusebufer).ourimplementation oftheSvschemeonlystoresvaluesforarithmeticandlogical instructionsandaddressesformemoryinstructions.Other instructionvalues(includingbranchoutcomesandloadval­ues)arenotstoredintheinstructionreusebufer.This reducesthenumberofaccessestotheinstructionreusepar­tition.Forafurtherreduction,onahitintheinstruction reusebufer,wedonotupdatethestateinformationforre­placements.Thebuferishoweverupdatedonmisses.For eachinstruction,westoreasmanyentries(setsofvalues)as ftinthecacheline(with64-bytecachelines,fveentriescan bestoredandassociativelycheckedforeachinstruction).
Relationship: reasoning
Domain: Hardware
Sentence 1: The three steps can be combined to obtain the factorization P = JTHJ.
Sentence 2: 3.2 Transforming Linear System (Step 2) 3.2.1 Overview Given the matrix J, we can construct an orthogonal trans­formation F .sN×N (described later in this section), such that W FJ = , 0 where W .sn×n.T P = JHJ () =(FJ)T FHFT(FJ) [ ](T) W = WT 0 FHF, 0 where FHFT can be represented as T P × FHF= , ×× in which P is sparse (we show this property later).
Relationship: reasoning
Domain: Hardware
Sentence 1: 2.4 Customized Value Pro.ling Oursystemcanbecustomizedinvariousways.Inpartic­ular,ausermayspecifywhatinformationtocapture,how totransformitintovaluesamplesthataremergedintothe profledatabase,andhowtoformatvaluesforreporting.
Sentence 2: todothis,theuserwritesadynamicallyloadablecus­tomizationmodule,whichisloadedbyDCPI'suser-mode daemon.Viathisplug-in"module,usersmayspecifywhat shouldbecapturedbytheinterpreterforeachinstruction opcode.Oneoptionistocapturenothingforparticular opcodes,butusuallysomebasicinformationiscollected,in­cludingthePCandthe32-bitinstructioncode.Inaddition, usersmayopttorecordoneormoreofthefollowing:content ofanexplicitlynamedregister,theinstruction'soperand orresult,amemoryoperand'svirtualaddress,andthela­tencyofloads.Foreachinstruction,thecapturedvalues formavaluetuple.eachtimetheinterpreterruns, itgeneratesatuplesequencefortheinterpretedinstruction sequence.
Relationship: reasoning
Domain: Hardware
Sentence 1: Maximizing Data Reuse for Minimizing Memory Space Requirements and Execution Cycles * M. Kandemir, G. Chen, and F. Li Computer Science and Engineering Department Pennsylvania State University e-mail: {kandemir,gchen,feli}@cse.psu.edu Abstract Embedded systems in the form of vehicles and mo­bile devices such as wireless phones, automatic banking machines and new multi-modal devices operate under tight memory and power constraints.
Sentence 2: their performance demands must be balanced very well against their memory space requirements and power consumption.
Relationship: reasoning
Domain: Hardware
Sentence 1: map Example2:ConsiderthecircuitofExample1.Ta­ble3showsorderingoftestvectorsfromwhichthe setsT0,andT1aredetermined.InTable4,thetest sequenceTS =ft1t2t4t3t5t6t7gisshownwhich isobtainedbychoosingconsecutivevectorsalternat­inglyfromT0andT1.Thecorrespondingoutputsof Ctosatisfythedesiredcheckerinputsareshown map incolumn4.Assignmentofcounterstatestothetests andthetruth-tabledescribingtheoutputsofCare map Table3:Orderingoftestvectors Tests 1st-stage compactoroutputs N1(Z) Testset partition z1 z2 z3 z4 t1 t4 t5 t7 0001000101011001 1 12 2 T0 t2 t3 t6 011110111111 3 34 T1 Table4:TestsequencingandtherequiredoutputsofC map Test sequenceTS 1st-stage compactoroutputs Requiredcheckerinputs Requiredoutputs ofCmap z1 z2 z3 z4 h1 h2 h3 h4 g1 g2 g3 g4 t1 t2 t4 t3 t5 t6 t7 0001011100011011010111111001 0000111100001111000111110000 0001 1000 0001 0100 0101 0000 1001 Table5:Counterstatesandthetruth-tableofC map TestsequenceTS Assignedcounterstate Outputs ofCmap b3 b2 b1 g1 g2 g3 g4 t1 t2 t4 t3 t5 t6 t7 000001010011100101110 0100001 00000010100000 1 0 1 0 1 0 1 | 111 d dd d showninTable5,whichleadstothefollowingBoolean .. functionsfortheseoutputs:g1 =b2b3+b1b2b3;g2 = +... b1b2b1b2b3;g3 =0;g4 =b1.
Sentence 2: 3.2.3Comparatorandthecodechecker WeuseaspecialCMOSgatetoimplementthecode checkerasshowninFig.6.Asobservedin[10],this codecheckercanadmitlargefan-in.Intestmode, allthepinputstothechecker,wouldbeeither0 (8t2T0),or1(8t2T1).Inthefrstcase,allthe p-MOS(n-MOS)transistorsatthefrstlevelofthe CMOSgatewillbeON(OFF),andinthesecond case,theywillbeOFF(ON).application ofTStotheCUTwillgenerateaperiodicoutputse­quence010101...atz,intheabsenceofanyfault.
Relationship: reasoning
Domain: Hardware
Sentence 1: For this case, the energy consumption of the spare is: AT 2 i (15) E (T ) = CVfAT when - AT = d SPR i effMAXMAX i i i .i It can be seen from the above discussion that in Cases 1, 2, and 3 we have considered the di values that are respectively in the ranges ATi/.i=di, ATi/.i-ATi<di<ATi/.i, and ATi/.i-ATi=di.
Sentence 2: in the above three cases, we have in fact considered the di values in the range ATi/.i-ATi=di.
Relationship: reasoning
Domain: Hardware
Sentence 1: Sangho Ahn School of Information and Communication Engineering, Sungkyunkwan University, South Korea dkstkdgh12@skku.edu  * Seokho Yoon School of Information and Communication Engineering, Sungkyunkwan University, South Korea syoon@skku.edu In UWB systems, the received signal must be .rst syn­ chronized with a locally generated template for data demod­ ulation.
Sentence 2: the synchronization is one of the most important steps for UWB systems.
Relationship: reasoning
Domain: Hardware
Sentence 1: This is veri.ed by plotting the similar diagrams in Figures 11, 12, and 13 which depict the number of the tokens (dif-  and four) while the number of LSAs must increase to reach the number of routers in the area (4 in our model), and it remains constant in the number of routers in the area.
Sentence 2: the MaxAge vulnerability exists in OSPF proto­col, and an external attacker can exploit it.
Relationship: reasoning