sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Our SoftUPS application is built using custom-developed HomeOS driver for the iPS, and utilizing drivers for their En­viR bases station.
Sentence 2: by not requiring a battery backup our solution has no losses, no recurring cost, and unlim­ited .exibility in device operation (within a power-budget), while still providing utilities with the intended e.ect of load reduction.
Relationship: neutral
Domain: Hardware
Sentence 1: In this approach, the mathematical repre­sentation of the amplitude spectrum of the received signal Xn in frequencydomainis assumed tobe apiecewise Nth orderpolyno­mial signal expressed asfollows: K L Xn = .k[nk-1 ,nk]pk(n -nk-1 )+En (7) k=1 where .k[nk-1 ,nk]isthe characteristicfunction,pk(n)is anNth order polynomials and En is the additive corrupting noise.
Sentence 2: sPECTRUM SENSING TECHNIQUES 3.1 Matched Filtering Matched .lter is the optimum detector of a known signal in the presenceofadditiveGaussiannoise.Itisthelinear .lterthat max­imizes the SNR of the output.
Relationship: neutral
Domain: Hardware
Sentence 1: We de.ne the literal set L as L ={li} ={x¯1,x1,x¯2,x2,...,x¯n,xn,},i=1,2,...,2n Accordingly, the cofactor set F is de.ned as F ={fi} ={fx¯1 ,fx1 ,fx¯2 ,fx2 ,...,fx¯n ,fxn ,},i=1,2,...,2n Shannon Expansion can be implemented by simply using aMUX with xi as the select bit and the positive and negativecofactors connected to the positive and negative MUX inputs,respectively.
Sentence 2: fx .. 13003100 f .. y¯ W6×8 = .
Relationship: neutral
Domain: Hardware
Sentence 1: We .nd that, for a speci.c in­terval, a real-time schedule using the lowest constant speed is not necessarily the optimal choice any more in minimizing the peak temperature.
Sentence 2: in what follows, unless otherwise speci.ed, we assume that (i) Gk (or G(vk))isa positive, monotonic in­creasing, and convex function of k (or vk), respectively and (ii) B > 0.
Relationship: neutral
Domain: Hardware
Sentence 1: For each occurrence of e1 in time interval [0, 10], the inner formula F[0, 5]e2 must be satis.ed assuming that the occurrence time of e1 is time 0 for F[0, 5]e2.
Sentence 2: the best place to stop the simulation is not always clear and depends heavily on the model and the properties.
Relationship: neutral
Domain: Hardware
Sentence 1: In this paper, we critically evaluate these methodologies from a rare fail events perspective and propose the CDF matching approach as a comprehensive and efficient methodology for accurate statistical leakage modeling of independent and identical variability sources.
Sentence 2: -3 -4 -4 1 CDF/ inverse CDF P, (1-P) -5 -6 -7 -5 n=2 Log10(Probability) 0 -1 -2 -3 Ysy -4 -4 -5-3-11 3 5 Yfw -5 .
Relationship: neutral
Domain: Hardware
Sentence 1: 4.2.1 High-level Approximation Models Any approximate com­puting technique can be thought of as introducing errors in the computations that are being approxi­mated.
Sentence 2: our primary contribution is the analysis and characterization of inherent application resilience present in a suite of 12 widely used applications from the domains of recognition, data min­ing, and search.
Relationship: neutral
Domain: Hardware
Sentence 1: The technology independent subnetlist was recombined with the sequential and multi-output combinational cells, and this new netlist was placed with Silicon EnsembleTM, in order to generate the initial placement for the congestion-aware technology mapping approach presented in [15], and summarized in Section 3.
Sentence 2: on Computer Design, pages 206-210, October 1997.
Relationship: neutral
Domain: Hardware
Sentence 1: For the elimination of the redundant ADBs in the buffered clock tree, initially, a sorted list of all the ADBs can be obtained by using a topological sorting in the corresponding ADB-connection graph.
Sentence 2: if a buffer, Bi, connects to a set of p flip-flops with their latencies, d1, d2,.., and dp, and a set of q buffers, B1, B2,.., and Bq, with their latency ranges, [l1, u1], [l2, u2],.., [lq, uq], as illustrated in Figure 2(b), a feasible set of buffers inside the clock sub-tree can be replaced with a set of ADBs and the delay values of the inserted ADBs can be assigned to minimize the latency skew at the buffer, Bi.
Relationship: neutral
Domain: Hardware
Sentence 1: As we can see 1, MAP-I provides 5.4% speedup and a full tags-in-SRAM design gives 11.8% speedup over the baseline.
Sentence 2: subsequently other works [14, 15] proposed miss predictors to achieve the same e.ect as a MissMap, but with signi.cantly lesser SRAM overhead (in the order of a few kilobytes).
Relationship: neutral
Domain: Hardware
Sentence 1: The rationale is simple if the measured data access time to two back-to-back accesses a1 and b0 is longer than that to another back-to-back ac­cesses a2 and b0, we can conclude that a1 and b0 are located within the same bank while a2 and b0 are accessed in parallel from differ­ent banks.
Sentence 2: so far, we have laid out a logical basis for the two-level Secu­rity Refresh scheme.
Relationship: neutral
Domain: Hardware
Sentence 1: Problem 1:Given Wand the test set parameters for each core, determine the TAM width and a wrapper design for each core, and a test schedule for the SOC that minimizes the total testing time, such that the total number of TAM wires utilized at any moment does not exceed W. .
Sentence 2: precedence and power constraints in the test schedule and test preemption were not considered.
Relationship: neutral
Domain: Hardware
Sentence 1: Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Sentence 2: chip-to­chip variations can cover signi.cantly wider limits within the op­erating range, and therefore it is not practical to apply margining techniques to this type of variations.
Relationship: neutral
Domain: Hardware
Sentence 1: of Posts and Telecommun., Nanjing 210003, China yuewenjing@sjtu.edu.cn; {zby, cuijw}@njupt.edu.cn  ABSTRACT In cognitive radio systems, cooperative spectrum sensing can detect the presence of the primary user accurately.
Sentence 2: [6] F. F. Digham, M. Alouini and M. K. Simon, On the Energy Detection of Unknown Signals Over Fading Channels, IEEE Transactions on Communications, vol.55, no.1, pp.21-24, Jan. 2007.
Relationship: neutral
Domain: Hardware
Sentence 1: accesslatency fordataaccessesthathitintheon-chip cache -due to communication over theNoC.Private caches,onthe otherhand, enjoyfasterhitdata accesslatencybut sufferfromlow capacityuti­lizationduetodata replication.
Sentence 2: similarly, data replication is not used in thelastlevel cacheof the state-of-the-artNoC-Cacheco-designed system[7] which we compare with.
Relationship: neutral
Domain: Hardware
Sentence 1: A survey of boolean matching techniques for library binding.
Sentence 2: the sec­ond column gives the leftover bits, and the third column gives the leftover percentage with respect to the size of the virtual memories, while the fourth column gives the mux cost when the leftover is minimized, and the runtimes in the last column stand for the map­ping multiple VMs onto multiple PMs.
Relationship: neutral
Domain: Hardware
Sentence 1: The largest cause, once again, is synchronization overhead, and furthermore, it takes as long to speculatively perform a placement move as it does to fully evaluate it, limiting speedups when the acceptance rate is high.
Sentence 2: we refer to this tuned version of the algorithm as pipe7, since it allows seven moves to exist at a time, one being evaluated and six being speculatively proposed.
Relationship: neutral
Domain: Hardware
Sentence 1: We extend our prior work on the Mat ´ e vir­tual machine (a tiny bytecode interpreter) [15], generaliz­ing its simple VM into an architecture for building appli­cation speci.c virtual machines (ASVMs).
Sentence 2: if a thread accesses a resource it does not hold (e.g., it incorrectly released it) the VM trig­gers an error.
Relationship: neutral
Domain: Hardware
Sentence 1: In traditional resource-constrained scheduling, priority functions like nodes on critical path .rst are applied uniformly to all nodes.
Sentence 2: [7] B. Jeong, S. Yoo, S. Lee, K. Choi, Hardware-Software Cosynthesis for Run-time Incrementally Recon.gurable FPGAs , ASPDAC, 2000.
Relationship: neutral
Domain: Hardware
Sentence 1: Inside SBox, old_mask is used to select the upper part, where the data are the values from the MA address of SBox (address is masked by 0), or the lower part, where the data are the values from the complement of the MA address of SBox (address is masked by 1).
Sentence 2: [10] Information and Physical Security Research Group in YOKOHAMA National University, available at http://ipsr.ynu.ac.jp/circuit/index.html [11] Kocher, P., Jaffe, J., and Jun, B.
Relationship: neutral
Domain: Hardware
Sentence 1: Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi and Sani R. Nassif Department of EE, Texas A&#38;M University, USA, IBM Austin Research Laboratories, USA, Department of ECE, Carnegie Mellon University, USA Abstract Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs.
Sentence 2: proposed to construct variational models by fitting the projection vectors over the samples taken in the variational parameter space.
Relationship: neutral
Domain: Hardware
Sentence 1: In the simu­lations, a thicker-oxide for 2.5 V PMOS transistor from the IBM 130 nm CMOS process was used, with a long channel L = 40 µm and W = 1 µm.
Sentence 2: the necessity of trimming due to high process variability which impairs the transistors behaviours, together with the electrical pa­rameters variations also present in the electrodes fabrication [12], limit the practical implementation of this approach, es­pecially in biomedical applications for which multi-channel circuits are required.
Relationship: neutral
Domain: Hardware
Sentence 1: 5.2.2 Retiming With all large delays pipelined, the target clock period becomes 1.75ns, the delay from the input .ip-.op of a logic block to its output register, giving a clock rate of 570 MHz.
Sentence 2: similar to Amalgam s RC, global communication is performed by a vertical global bus which gives the architecture a direction of computational .ow.
Relationship: neutral
Domain: Hardware
Sentence 1: FLOW-BASED BOUND-FEASIBILITY COMPUTATION LetQ={QiI1:i:n}bethesetofnonstraining retangles,eahofwhihorrespondstoamodule.
Sentence 2: [15]M.R.Garey,D.S.Johnson,Computersand Intratability:AGuidetotheTheoryof NP-Completeness.NewYork:W.H.Freemanand Co.,1979.
Relationship: neutral
Domain: Hardware
Sentence 1: While the maximum VDD may be only 1.2V in a 0.10µm process technology, the VT will be ~0.35V yielding an achievable energy efficiency improve­ment, VDD2/VT2, still in excess of 10x.
Sentence 2: in addition, a methodical design approach must ensure that no sig­nal is ever floating for more than a half-cycle to prevent functional errors.
Relationship: neutral
Domain: Hardware
Sentence 1: Theload capacitance is the sum of the input capacitance of the next re­peater, ci, and the ground (cg) and coupling (cc) capacitances of the wire driven.
Sentence 2: [16] which accounts for crosstalk-induced delay: dw =rw(0.4cg + .2 i cc +0.7ci) (9)  3B-1 where dw, rw, cg, cc and ci respectively denote wire delay, wireresistance, ground capacitance, coupling capacitance, and input ca­pacitance of the next-stage repeater.
Relationship: neutral
Domain: Hardware
Sentence 1: A graph G = (V, E) maintained as a graph circuit is a collec- tion of gates (representing the vertices V) and wires connect- ing the gates (representing the edges E).
Sentence 2: if, for every active vertex v, the host maintains an edge incidence set Iv of the edges entering and leaving v, deletion of v may be performed in O(1I~[) steps) In practice, it is possible to use the capa- bility of contemporary RCHW arrays (e.g., [12]) to write an SThe incidence sets I can be maintained on a conventional VO vl V2 V3 VO vl V2 v3 I 1 _. o 1  .
Relationship: neutral
Domain: Hardware
Sentence 1: Wethendiscussanalternativethatdoesnotrelyoncache associativity.
Sentence 2: thisrequiresamoregeneralcachedesignthatallowsmul­tipleaddressinputsintoandmultipledataoutputsoutof thecache,requiringcaretokeepthesemultiplepathsfrom contendingwitheachother.Someofourdesigndecisions mayactuallyincreasethepowerconsumptioninthecache arrays.Second,weperformadetailedtiminganalysiswith theCACTIanalyticalmodeltodeterminetheimpactofour designoncacheaccesstime.Albonesi'sevaluationisfocused onpowerdissipation.Third,weevaluatetheperformance beneftsofthereconfgurablecacheorganizationforinstruc­tionreuse[23]formediaprocessing.weshowthat cachestoragecanbeusedtoimprovecomputationspeedfor mediaprocessing.Albonesifocusesonshuttingofpartsof thecachetosavepower,andfocusesonSPECbenchmarks.
Relationship: neutral
Domain: Hardware
Sentence 1: CRBcast is a two-phase broadcasting protocol.
Sentence 2: in Figure 2, the fraction of nodes that successfully receive a particular packet (denoted by R1) and np = 2000 packets (denoted by Rnp) are shown for the topology T. We also depicted R1 np, which is a lower bound for Rnp by Lemma 1.
Relationship: neutral
Domain: Hardware
Sentence 1: A sliding window bu.er object is instantiated for 2048 image width and 5x5 window size in Line 7, then used in Lines 10 and 13.
Sentence 2: increasing image resolutions make it ever more di.cult to obtain su.cient throughput from external SDRAM frame bu.ers while providing sim­ple, low-latency memory resources for the data path.
Relationship: neutral
Domain: Hardware
Sentence 1: Size C880 18.3ns 2103 58.05 3.34 1270.24 1000 C1355 22.8ns 505 220.81 5.12 4803.06 2000 C2670 33ns 2253 591.5 21.47 8283.27 1590 C7552 30.8ns 971 337.86 211.51 87666.4 9714 s1488 14ns 703 4.65 1.3 1695.26 1000 s5378 18.5ns 2102 205.98 74.01 74318.2 7345 s9234 40.5ns 290 226.31 61.55 152892 7974 s38417 39.5ns 2880 639.15 350.04 452032 7800 Table 1 shows related data from the experiments.
Sentence 2: these are results of simulating 1000 sample chips.
Relationship: neutral
Domain: Hardware
Sentence 1: Example of FIR Canonical Filter of 5 taps scheme IN_tr0 R0_tr0 R1_tr0 R2_tr0 R3_tr0 C2_tr0 C4_tr0 C1_tr0 C3_tr0 C5_tr0 pad OUT_dr0    check0 IN_tr1 R0_tr1 R1_tr1 R2_tr1 R3_tr1 Upset detection and C1_tr1 C5_tr1 C2_tr1 C3_tr1 C4_tr1 voter block check1 OUT_dr1     pad Figure 12.
Sentence 2: sRAM-based FPGAs are uniquely suited for remote missions, because they can be reprogrammed by the user as many times as necessary in a very short period.
Relationship: neutral
Domain: Hardware
Sentence 1: A high sensitivity process-sensor has been proposed in [6] utilizing the extremely high process-sensitivity of MOS transistors operating in sub-threshold.
Sentence 2: since the process-sensor output varies by ~0.7% per mV variation in NMOS threshold­voltage, the worst-case temperature variation will reduce the accuracy of the sensor by ~5mV of the NMOS Vth.
Relationship: neutral
Domain: Hardware
Sentence 1: Also note how with the BS design, the throughput reduction is almost negligible for the output period of 4 cycles to 7 cycles.
Sentence 2: when the buffer is considered full, that is, there is only one free buffer space left, in a thief buffer and if it needs to receive more .its, the buffer stealing mechanism is activated to steal the unused free buffer space in victim buffers.
Relationship: neutral
Domain: Hardware
Sentence 1: Other Design Options Local DMDC In our implementation, the end check reg­ister is a global register in that there can be multiple unsafe stores in-.ight and they all update the register as they issue (can only increase the checking window size).
Sentence 2: dMDC still uses the conven­tional approach of ruling out dependence or coherence vi­olation through address and timing information, albeit with approximations.
Relationship: neutral
Domain: Hardware
Sentence 1: For exam­ple, by using operator-based MOR, the number of time-points or harmonics used for periodic time-varying discretization can be dy­namically changed at each Krylov reduction step; indeed, one can switch between time-and frequency-domain discretizations, if so desired, without any code changes necessary at the upper level (i.e., the operator-LPTV-MOR routine) of the procedure.
Sentence 2: manual abstraction needs to be aided by extensive nonlinear simulation; parameters of interest, such as poles, may not be easy to obtain; and man­ual abstraction may miss important nonidealities, especially those relating to interactions between sub-systems.
Relationship: neutral
Domain: Hardware
Sentence 1: Percent­age of 0, 1, and 2 input operand ready instructions, on an average, is 14.3%, 45.4%, and 40.3%, respectively, for a Figure 4.
Sentence 2: 978-3-9810801-3-1/DATE08 &#38;#169; 2008 EDAA  2 Related Work As process variation can signi.cantly impact perfor­mance, several circuit-level and architectural-level tech­niques have been proposed in the literature to minimize the performance loss.
Relationship: neutral
Domain: Hardware
Sentence 1: In this section we quantify the impact of these delay reductions on the over­all performance of application designs implemented in such FPGA.
Sentence 2: logic Density Improvement 2.80 LB- SRAM + RR- SRAM PT 61% Un occupied 39% % LB 37% RR 44% 19% Memory 2.60 Switch 2.40 CMOS LB- SRAM + RR- SRAM PT 84% 16% % Memory Figure 5: Logic density improvement of 3D-FPGA Switch as a function of the normalized con.guration mem- Unoccupied  ory cell size.
Relationship: neutral
Domain: Hardware
Sentence 1: Copyright 2012 ACM 978-1-4503-1244-8/12/05...$10.00.
Sentence 2: in density-reduction-oriented layer assignment for the LA-4 problem, the 4 buses, A, E, G and K, to the top and bottom boundaries and the 3 buses, B, F and I, to the left and right boundaries can be assigned on the first layer.
Relationship: neutral
Domain: Hardware
Sentence 1: Execu­tion time is calculated as a product of clock length and the number of clock cycles taken.
Sentence 2: what differentiates EPIC and superscalar proces­sors is the way that this parallelism is discovered: Super­scalar processors use logic to schedule instructions at run­time, while EPIC processors rely on compilers that can stat­ically expose parallelism at compile time.
Relationship: neutral
Domain: Hardware
Sentence 1: In a commercial FPGA however, in addition to LUTs, other types of hardware structures are usually present.
Sentence 2: the SRAM con.guration cells can be slowed down and their leakage reduced or elimi­nated using previously-published low-leakage memory tech­niques (e.g., [10]) or by implementing memory cells with high-VTH or long channel transistors.
Relationship: neutral
Domain: Hardware
Sentence 1: The average error of µ and s for the 30-segment RC ladders is presented in Table 2.
Sentence 2: i 2 } E (.X i )=E µsX i ) E .X i )=E (µsX ) (6) C in CFO form can be approximated as: m m C .. a b +µ.a b .+.
Relationship: neutral
Domain: Hardware
Sentence 1: Shared memory, the in­terconnect between processing elements, and I/O interfaces are all accessed by multiple processing elements, making the contention for shared resources a signi.cant in.uence on the overall system performance and an important modeling consideration.
Sentence 2: the MESH performance advantage would especially be ev­ident with large and more complex models where the pro­hibitively large ISS simulation and model generation times would hamper rapid design exploration.
Relationship: neutral
Domain: Hardware
Sentence 1: Next,afterfndingthebestloationsofallofthepseudo­pins ofthetwo­pinnets,weapplyaMSTalgorithmtooptimally onnetthesepseudo­pinsthatlieontheboundarytoensure theireletrialequivalene.Thefnalpinassignmentould orrespondtoanyofthepointsonthisMST,sinetheywill beequivalentintermsofroutingongestion.
Sentence 2: =kNY (10) thedistributionofthoseinteronnetionsisnot symmetrialalongthefouredgesofthebin.Thenumberof wiresoriginatingfrombinSandrossingrightboundarye, denotedasIs-c,shouldbeproportionaltoareaA2,andan beexpressedas A2 Is-c =Is (11)2Ablok TheaboveformulaarisesfromthefatthatSgets4bound­aries,andtheareaofSismuhsmallerthanthetotalarea oftheblok.Similarly,wehave A1 .
Relationship: neutral
Domain: Hardware
Sentence 1: In Xilinx Virtex FPGAs, in general, an addition/subtraction performed on two ..-bit operands requires .. 4-input LUTs [12].
Sentence 2: also, the constraints of the 0-1 ILP problem are obtained by .nding the Conjunctive Normal Form (CNF) formulas of each gate in the network and expressing each clause of the CNF formulas as a linear inequality, as described in [17].
Relationship: neutral
Domain: Hardware
Sentence 1: [11] Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, and M. J. Wain­wright, Design of LDPC decoders for improved low error rate per­formance: quantization and algorithm choices, IEEE Trans.
Sentence 2: practical performance of LDPC codes can be far from their theoretical limit for two reasons: (1) a practical code s block length is limited to hundreds to thousands of bits to meet latency and complexity constraints; (2) practical decoder implementations introduce non­idealities, such as finite word length and fixed-point quantization effects [11].
Relationship: neutral
Domain: Hardware
Sentence 1: Note that track shifting (TS2) and data management (HBWBR) are executed si­multaneously and are independent to each other.
Sentence 2: compared with array-style random access memory, including STT-RAM, integrating tape-style racetrack memory faces several unique design challenges: (1) To effectively utilize the stripe struc­ture, new circuit layouts and optimizations are necessary.
Relationship: neutral
Domain: Hardware
Sentence 1: As alter­natives to static CMOS are deployed to permit overall speed/power performance gains, layout automation and physical veri.cation (e.g., automated extraction of novel active and passive structures from lay­out) will be needed.
Sentence 2: most of today s design technology crises veri.cation, embedded software and system-level design, enabling of power management at the architectural and operating­system levels, analog/mixed-signal synthesis and reuse, design for test lie elsewhere.
Relationship: neutral
Domain: Hardware
Sentence 1: IN T RO D U C T I O N There is today little doubt on the fact that a high­performance and cost-effective network-on-chip (NoC) can only be designed in nanoscale technologies under relaxed syn­chronization assumptions.
Sentence 2: after the output channel request, RE QOut , makes a transi­tion, the data register and latch L5 are made opaque.
Relationship: neutral
Domain: Hardware
Sentence 1: Only one out of the .ve circuits has timing slack reduction of 16 ps.
Sentence 2: the region constrained by the two lines that have the k-values in the middle among ki p0, ki p1, kpj 0, kpj 1 for positive slope edges and the two lines that have the k-values in the middle among kni 0, kni 1, knj 0, knj 1 for negative slope edges is the merging region MRv for the newly merged cluster Gv.
Relationship: neutral
Domain: Hardware
Sentence 1: For example, pattern (a, b, c, d, e) = (1, 1, 1, 0, 0) has the delay of 2.
Sentence 2: we have the following cases: (1) the Boolean function LPAF1 states that long paths of gate h and gate k are sensitized; (2) LPAF2 states that a long path of gate h is sensitized and a short path of gate k is sensitized with k to be a non-controlling value, k=1; (3) LPAF3 states that a long path of gate k is sensitized and a short path of gate h is sensitized with h=1.
Relationship: neutral
Domain: Hardware
Sentence 1: INTRODUCTION The demands of modern power electronics converters for high power, high density and high efficiency have raised opportunities for the new high speed, wide bandgap power semiconductor devices such as silicon carbide (SiC) MOSFETs [1]-[4].
Sentence 2: as long as a better SiC MOSFET model is available, the prediction of the switching energy can be improved.
Relationship: neutral