sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Versatile Implementation As shown in section 3, optimisation within a system like MOODS relies on the following elements : transforms, the cost function and an algorithm.
Sentence 2: as regards testability, we assume that every computed result has to be verified, and, ideally, faults need to be detected before they corrupt the primary outputs, so that any possible recover y mechanism will be able to react in time.
Relationship: neutral
Domain: Hardware
Sentence 1: Experiments with real-world vulnerabilities and test programs demonstrate that the layoutdiversi.cationon Orthrus can detectabroad rangeof attacks exploiting vulnerabilities such as buffer over.ows, format string bugs, and dangling pointers.
Sentence 2: in Proceedings of the 38th IEEE/IFPF International Conference on Dependable Systems and Networks, Dependable Computing and Communications Sympo­sium, 2008.
Relationship: neutral
Domain: Hardware
Sentence 1: However, for various reasons in­cluding power dissipation and wire delays, many computer architects believe that Moore s law, which predicts that com­puting power will double every 18 months, will cease to hold sometime in the near future.
Sentence 2: 4.2.1 Local Correctness Figure 4 illustrates a situation that causes DTW to be locally incorrect.
Relationship: neutral
Domain: Hardware
Sentence 1: TaskA(mappedinPE1) TaskB(mappedinPE2) Send() Receive() pipe[i].status=USED TaskStatus=WAITING  pipe[i].status=WAITING_ACK TaskStatus=READY 4 pipe[i].status=EMPTY Figure 1 Communication protocol to exchange data packets.
Sentence 2: the variation observed in the results is mostly induced by the OS s task scheduling scheme.
Relationship: neutral
Domain: Hardware
Sentence 1: In some benchmarks, such as B6, coupling-aware TSV placement alone (CA) can come close to matching the improvement o.ered by CA+SI, and in others, such as B3, shield insertion alone (SI) can do the same.
Sentence 2: fWL is a force that pushes a TSV towards the netbox, with magnitude linearly proportional to how far a TSV is outside the netbox.
Relationship: neutral
Domain: Hardware
Sentence 1: Many of these students perform assessment, tests and homework writing using the Braille medium.
Sentence 2: bCBC is assigned using the following formula BCBC = dot1*25 + dot2*24 + dot3*23 + dot4*22 + dot5*21 + dot6*20, where dotX is one if the dot exists or zero if it doesn t. 4.4 Braille to Text Translation Once the binary coded Braille cell has been determined, the task of converting to literary text is dependent on the type of Braille code being scanned.
Relationship: neutral
Domain: Hardware
Sentence 1: [8] A. Tabbara, B. Tabbara, R. K. Brayton, A. R. Newton, Integration of retiming with architectural floor planning , Integration the VLSI journal, 29, pp 25-43, 2000 [9] C.-Y.
Sentence 2: the formulation in [9] does not consider flip-flop (FF) minimization, which is important in practical applications.
Relationship: neutral
Domain: Hardware
Sentence 1: An invariant holds if all states of all paths of length k starting from the initial states satisfy the invariant, and there is no simple path of length k + 1 starting at an initial state or leading to a failure state, and not going through any other initial or failure states.
Sentence 2: the other option is to continue the search for a shortest counterexample, but to disable the check for termination, which is usually rather time-consuming.
Relationship: neutral
Domain: Hardware
Sentence 1: We exploit External Don t Cares (EDC) optimization with the idea that already reached states can work as EDC con­ditions for further reachability steps (Care = ¬EDC = ¬Reached).
Sentence 2: not only di.erent redundancies are related/implied each other (so it might be unnecessary to prove all of them), but a given circuit can be recomputed and highly compacted, after a subset of ITE redundancies is known.
Relationship: neutral
Domain: Hardware
Sentence 1: This is relatively large overhead and it causes signif­icant throughput degradation because the register access is blocking operation.
Sentence 2: in summary, the current general-purpose computers theo­ritically achieves high-throughput, 10Gbps for example, packet Table 1: Specs of machines for the bottleneck anal­ysis (1GbE) Transmitter CPU Intel(R) Core(TM) i3 330M (2.13GHz, dual core) Memory 4GiB, DDR3 (1333MT/s) NIC Adapter Intel(R) 82577LM (1 port) [3] processing and forwarding, but it is known di.cult to achieve it.
Relationship: neutral
Domain: Hardware
Sentence 1: An architecture that has only segments of length 1 will use the fewest tracks per chan- nel, but because each pair of segments will have to be connected by a routing switch (we are using subset switches), high fanout nets will require several of such segments, slowing down the cir­ 2.00E+00 cuit considerably.
Sentence 2: the intent is to keep a low ratio of used pins to total number of pins in the logic cluster.
Relationship: neutral
Domain: Hardware
Sentence 1: The 57 mm (95 mm) baseline presently set in our MeshEye mote (prototype) allows for a maximum perceived depth of 8.74 m (14.5 m) in theory, which we deem adequate for indoor and limited outdoor usage.
Sentence 2: to qualify a positive match and remove objects outside the joint FoV, the maximum cross-correlation value has to be sufficiently close to the center autocorrelation value of the object s ROI, which may be expressed as t t max C (u, v) = 0.75A (0,0).
Relationship: neutral
Domain: Hardware
Sentence 1: As the RF wakeup circuit described in Sections 3.3.2 and 5.3.3 has been demonstrated to be sensitive to mW-level transmissions from small, easily integrated radios, it could be gies (AutoID2005), pages 187 192, Buffalo, NY, Oct. possible for proximate CargoNet tags to wake one another up 2005. via RF when one tag encounters an exceptional event worth reporting that doesn t necessarily contain a common environ­mental sensor stimulus.
Sentence 2: in response to DHS initiatives and the quest for greater visibility, numerous companies have proposed and released solutions.
Relationship: neutral
Domain: Hardware
Sentence 1: Ideally, the write operation is completed by pulling down X1.Q to a voltage level lower than the thresh­old of X1.M2.
Sentence 2: simulation results show that when X0.R5 = 0.8kO, the voltage of SA.B cannot be charged high enough to pull down the output signal and a logic 1 is mistakenly read out from the cell.
Relationship: neutral
Domain: Hardware
Sentence 1: In order to reduce the amplitude of the high-frequency spectral content, we need to increase the rise/fall times.
Sentence 2: [14] W. J. Condley, X. Hu, and M. R. Guthaus, Analysis of high-performance clock networks with RLC and transmission line effects, ACM/IEEE in­ternational workshop on System level interconnect prediction, pp.
Relationship: neutral
Domain: Hardware
Sentence 1: ConfereneonComputer-AidedDesign(ICCAD);1999 [11]FabioSomenzi;"CUDD:CUDeisionDiagram Pakage";UniversityofColoradoatBoulder; http://vlsi.olorado.edu/-fabio/CUDD/
Sentence 2: withtheurrentrestritionto13hannelsthisalgo­rithmanstillimprovethelayoutforomplexintra­ell routingswhenitisusedinellgenerators.
Relationship: neutral
Domain: Hardware
Sentence 1: In VLSI circuits, crosstalk a.ects mutual inductance as well as inter-wire capacitance.
Sentence 2: figure 4: Noise voltage waveforms for capacitive, inductive, and capacitive+inductive coupling for a Transmission line Typical values of R, L, and C for di.erent wire lengths and for 90nm technology node have been extracted for long (10mm) and local (1mm) interconnects from Arizona s State University Predictive Technology Model (PTM) [14] and are summarized in Table 1.
Relationship: neutral
Domain: Hardware
Sentence 1: Having a smaller protected region signi.cantly reduced the TE overhead by improving the IV cache hit-rate.
Sentence 2: trusted Platform Module (TPM) from Trusted Computing Group (TCG) [8], Next Generation Se­cure Computing Base (NGSCB) from Microsoft [15], and Trust-Zone from ARM [2] incorporate some of the mechanisms simi­lar to the ones in our processor architecture.
Relationship: neutral
Domain: Hardware
Sentence 1: Addi­tionally theimpactof thecontextof theaudio .les(such as noise, music, etc) on the classi.cation should be evaluated, because we can not exclude for our tests that the classi.ca­tion performance is in.uenced by pure context features.
Sentence 2: the idea to use the attribute selection as a pre-processing step was discarded and in the rest of the work it is only used to identify the most signi.cant features for selected tests.
Relationship: neutral
Domain: Hardware
Sentence 1: Varicap Threshold Logic Samed Maltabas Martin Margala Ugur Cilingiroglu University of Massachusetts University of Massachusetts Yeditepe University Lowell Lowell EEE Department ECE Department ECE Department Istanbul, Turkey MA,USA MA, USA 34755 01854 Samed_Maltabas@ student.uml.edu 01854 Martin_Margala@uml.edu ucilingiroglu@yeditepe.edu.tr ABSTRACT Inthispaper, ahighly compact novelThresholdLogic(TL) Gateapproach called Varicap TL(VcTL) isproposed and described.
Sentence 2: [7] K.A.C.Bickersta., M.Schulte, and Jr.E.E.Swartzlander.
Relationship: neutral
Domain: Hardware
Sentence 1: Our technical goal is to demonstrate a new class of PUFs that preserves all advantages of PPUFs but requires each party in a wide class of security protocols to conduct only a single cycle computation.
Sentence 2: matched Public PUF: Ultra Low Energy Security Platform Saro Meguerdichian and Miodrag Potkonjak Computer Science Department University of California, Los Angeles {saro, miodrag}@cs.ucla.edu Abstract Hardware-based physically unclonable functions (PUFs) leverage intrinsic process variation of modern integrated circuits to provide interesting security solutions but either induce high storage requirements or require signi.cant resources of at least one involved party.
Relationship: neutral
Domain: Hardware
Sentence 1: Device scal­ing results in lower operating voltages, which in turn reduces the energy required to cause a voltage pulse at the output of a logic gate or invert the value stored within a sequential element.
Sentence 2: further, mounting demand for em­bedded microprocessors in a wide array of safety critical appli­cations, ranging from automobiles to pacemakers, compounds the importance of addressing the soft error problem.
Relationship: neutral
Domain: Hardware
Sentence 1: Based on -2 SPICE simulation, node na has a voltage in a range -3 of 100-200mV, and Ijunc,na under such a low bias is 14 over one order of magnitude smaller than scenario 1 and can be safely ignored, leaving the Isub relatively unchanged.
Sentence 2: dAC 2007, June 4 8, 2007, San Diego, California, USA.
Relationship: neutral
Domain: Hardware
Sentence 1: Our proposed method builds a hierarchical correlation model [1].
Sentence 2: the delay of gate k is X dk = dnorm,k + dl,s +.drandom,k 0<l<m, s intersects k where dnorm,k is the nominal delay of gate k and drandom,k represents the random variation of delay of k. In our ex­periments, the delay random variables .dl,s for segments are uniform distributions and the delays of dnorm,k are sam­pled under a normal distribution (an internally built library based on Monte-Carlo SPICE).
Relationship: neutral
Domain: Hardware
Sentence 1: Due to the ef.cient utilization of dynamic recon.gurability, the algorithm leads to a highly compact placement.
Sentence 2: starting from this intermediate con.gu­ration, the second stage uses low temperature simulated annealing (LTSA) [Chen and Chang 2005; Sechen 1988] to re.ne the placement, in order to enhance fault tolerance.
Relationship: neutral
Domain: Hardware
Sentence 1: {}0 {}1 i i Together, the coefficients a and b determine the variance of x and the correlation of x to the chip-level component of variation: Var x 2 2{} {}= a Var y{}+ b Var z = V i iii i Most importantly, the above formulation allows us to parsimoniously represent the relation of correlation between nodes.
Sentence 2: 5 RESULTS The algorithms described in Sections 3 and 4 have been implemented in C, and have been run on Windows PC with CPU 2.4 GHz and 512 MB memory.
Relationship: neutral
Domain: Hardware
Sentence 1: Furthermore, the remaining 2.6%, with latencies of more than 10,000 instruc­tions could not be exploited without being accompanied by heavy­weight, software-based checkpointing (and its attendant costs).
Sentence 2: whenever Shoestring encounters a loop it forces the depth-.rst traversal to backtrack when the dis­tance between the instruction currently being processed and the instruction at the bottom of the loop exceeds Slat.
Relationship: neutral
Domain: Hardware
Sentence 1: Copyrights for components of this work owned by others than ACM must be honored.
Sentence 2: (14) si si i=1 i=1 let us consider that S is utilized to estimate the incremental electrical variable vector all the time as kk k k j j-1 Msi .xsi = b j + Nsi .xsi , (15) i=1 i=1  Figure 3: The e.ect of inconsistent bases in incremental tran­sient analysis.
Relationship: neutral
Domain: Hardware
Sentence 1: Exploiting Subarrays Inside a Bank to Improve Phase Change Memory Performance Jianhui Yue, Yifeng Zhu Electrical and Computer Engineering, University of Maine jianhui.yue, yifeng.zhu@maine.edu Abstract Enabling subarrays reduces memory latency by allowing concurrent accesses to different subarrays within the same bank in the DRAM system.
Sentence 2: initially, each bank s CB is set as the maximal current provi­sion for a bank.
Relationship: neutral
Domain: Hardware
Sentence 1: DMA Access: Designing our FW, there was an argue whether to use the DMA for a short amount of data transfer or to let CPU do it; both are known to have a certain amount of overhead in our system, while their difference was unknown in a quantitative way.
Sentence 2: as shown in the figure, since the runtime of a function is not stationary but variable over time, short-term simulation (as in RTL simulation) or a taking snapshot of a function-call instance (as in logic analyzer) is not sufficient to capture the true nature of the function.
Relationship: neutral
Domain: Hardware
Sentence 1: It is noteworthy that, in the case of s5378, s9234, and s13207, when budget increases from 1.5% to 2%, neither MSE nor adjusted error can be improved simply by imple­menting one more RCRP.
Sentence 2: note that, as observed from our results shown in Section 5, selective workload sampling is not always necessary for ev­ery circuit especially if the simulation and analysis indicates so in the design stage.
Relationship: neutral
Domain: Hardware
Sentence 1: This last phase will be dealt with in future research.
Sentence 2: if there is a vertex v of the con.ict graph left, then v corresponds to a match S, such that none of the nodes of S is a node ofa matchofaMNOMS cor­responding to an already chosen approximate MIS (other­wise v would have been removed as (a neighbor vertex of) a vertex contained in one of the chosen approximate MISs).
Relationship: neutral
Domain: Hardware
Sentence 1: Thus, it is required to re.ect lithographic LER in the design stage.
Sentence 2: sincetheRMS rough­ness, s, is represented as a polynomial function or a piece­ wise linear function which considers the impact of pattern of position, x, measures the steepness of the image in the pitchonlithographyprocess, we canget a newPSDfunction transition from bright to dark of aerial image light as shown which takes the neighboringpatternpitchinto consideration in Figure 3.
Relationship: neutral
Domain: Hardware
Sentence 1: The ON and OFF current of the molecular crossbar can be found as follows: (2) where n is the dimension of the array.
Sentence 2: rEAD-OUT SCHEMES FOR THE CROSSBAR In this section, two read-out schemes are proposed and two figures of merit for these two schemes will be used to investigate their effectiveness for a CNTFET-based crossbar memory.
Relationship: neutral
Domain: Hardware
Sentence 1: Power consumption results Microprocessor Versions Non-Protected TMR TMR+TR+CWSP Leakage Power Consumption (µ W) 0.2440 0.3645 + 49.39 % 0.5024 + 105.90 % Total Power (mW) HNO Benchmark 3.3294 4.1148 + 23.59 % 5.0403 + 51.39 % Total Power (mW) HLC Benchmark 3.3929 4.1657 + 22.78 % 5.0160 + 47.84 % Total Power (mW) HLB Benchmark 3.3945 4.1672 + 22.76 % 5.0169 + 47.79 % Total Power (mW) AOR Benchmark 3.6037 4.3930 + 21.90 % 5.3720 + 49.07 % Total Power (mW) ALO Benchmark 3.5181 4.2995 + 22.21 % 5.2253 + 48.53 %  5.
Sentence 2: golden values could be defined for each benchmark.
Relationship: neutral
Domain: Hardware
Sentence 1: Where instead the interconnect delay plays a role is in determining area of the hardware barrier, since the place-and-route tool operates aggressive repeater in­sertion to sustain performance over long links.
Sentence 2: moreover, the mutual interference between the two traf.c .ows has to important negative impli­cations to performance: .rst, it degrades QoS of applications; second, it fails to provide ultra-low latency synchronizations.
Relationship: neutral
Domain: Hardware
Sentence 1: The driving needs of these solutions are an EDA framework for resonant clock design that uses novel clock synthesis schemes to construct the resonant clocks as well as completely resonant clock distributions to maxi­mize power savings.
Sentence 2: the loss of the transmis­sion lines attenuates the amplitude of the waves and hence, intro­duces a residual traveling wave that leads to some clock skew.
Relationship: neutral
Domain: Hardware
Sentence 1: The cell current is basically controllable by adjusting the cell voltage, Vcell .
Sentence 2: (1) The luminance of the OLED is approximately proportional to the root mean square (RMS) value of Icell , IRMS, which is calculated as ton IRMS = max(Icell), (2)ton +tof f where ton and tof f are the switch turn on and off durations in a PWM period, respectively.
Relationship: neutral
Domain: Hardware
Sentence 1: IEEE/ACM International Conference on Computer-Aided Design (IC-CAD) 2012, November 5-8, 2012, San Jose, California, USA Copyright oc2012 ACM 978-1-4503-1573-9/12/11... $15.00 [13], [14], [15], [5], dynamic programming (DP) [16], [17], [15], multi-direction search [18], brand-and-bound [19], sensitivity-based heuristics [20], [21], [22], [23] and hybrid approaches [19], [5], [17], [9].
Sentence 2: in more complex situations, considering level 3 may help improve estimation quality, e.g.
Relationship: neutral
Domain: Hardware
Sentence 1: [3] Cassioli, D., Scotti, S., Mecozzi, A., A time-domain computer simulator of the nonlinear response of semiconductor optical amplifiers , IEEE Journal of Quantum Electronics, vol.
Sentence 2: in this study, the inclusion of an optical pre­amplifier in the OLT receiver is justified by the receiver sensitivity degradation caused by the increase of data rate to 10 Gbit/s.
Relationship: neutral
Domain: Hardware
Sentence 1: Given NML and NMR, the noise margin of a cell can be expressed as: NM =Min(NM L , NM R ) (6) The above noise margin metric is different from SNM because it characterizes a cell s stability under the assumption that only side of the cell is disturbed by external noise.
Sentence 2: newton, "Alpha-power law MOSFET model and its applications to CMOS inverter," JSSC, 1990, pp.
Relationship: neutral
Domain: Hardware
Sentence 1: Each core consists of at least one block and each block bij.B is characterized by: pidle(bij): idle power, parmin(bij): minimal parallelization degree, and parmax(bij): maximal parallelization degree; Rsource = {r1, r2,..., rp} is a .nite set of test sources; Rsink = {r1, r2,..., rq} is a .nite set of test sinks; : maximal allowed power at any time;  pmaxT ={t1, t2,..., to} is a .nite set of tests, each consisting of a set of test vectors.
Sentence 2: [6] for power consumption is assumed.
Relationship: neutral
Domain: Hardware
Sentence 1: By multi-mode we mean that part of the cache can be used for FIFO-based caching of data for media processors, while the remainder of the cache can be used for 2nd level caching or even 1st level caching for CPUs, with standard caching and pre-fetching mecha­nisms.
Sentence 2: for the CPA we have the case in which 20 individual streams require access to background mem­ory.
Relationship: neutral
Domain: Hardware
Sentence 1: Floating­pointinstrutionsareusuallyperformedbya speifarithmetiunit.Atafuntionallevelofab­stration,thisunitisnotdistinguishablefromanin­tegerALU.Forthisreasonthe&#38;Lisusedtomodel theseoperationsalso.
Sentence 2: therehasbeenarelevantresearhefortinthe pastyears,toidentifypossibleanalysismethodologiesapa­bleofevaluatingthesoftwarepowerybavoidingtheuseof EDAtoolsdevelopedforthehardwaretoanalyzethearhi­teturalbloksomposingthemiroproessor.Infat,this proessistime­onsumingandproduesdatadiÆulttobe properlyinterpretedwithoutfurtheranalysisofthemodule orrelations[1;2;3].Reentlypromisingapproaheshave beenproposed,workingattheinstrution­level,basedon theharaterizationoftheInstrutionSetviaasetofphys­ialmeasurementswhenthemiroproessorisexerisedwith longrunsofthesameinstrutions[4;5;6].Nevertheless, despitethesestrategiesgenerallyproduegoodresultsespe­iallyintermofrelativepreision,thevalidityofthemodels andthesignifaneoftheexperimentaldataaretypially notjustifedunderastatistialviewpointandtheneedof performinganexhaustivesetofmeasurementsrepresentsa majorobstaleinextendingtheanalysistowardsnewmi­roproessors.
Relationship: neutral
Domain: Hardware
Sentence 1: For the same example as shown in Section 3, if the arrival time for a design is required to be 100, then obviously solution (A) is the best choice, as it satis.es the required arrival time constraints without any uncertainty.
Sentence 2: of (Lt,Tt) obtained from (1) and (2) via the multivariate transformation technique, we intro­duce two new random variables X and Y as follows: X = c; (7) Y = r; (8) Lt = Ln + c·li; (9) 1 Tt = Tn -r·li ·Ln - ·r·c·li 2 .
Relationship: neutral
Domain: Hardware
Sentence 1: If any source of variations can be tracked by SPDFT, the power associated with that guardband can be reduced under BTWC conditions.
Sentence 2: 3.1 Deriving Instruction Sequences to Test Potentially-Critical Paths SPDFT routines are instruction sequences that test for tim­ing slack on the paths in a processor and produce outputs that are checked against the known correct outputs for the in­struction sequences.
Relationship: neutral
Domain: Hardware
Sentence 1: Although not presented in this paper, we have already used the same system for solving the heat diffusion equations describbed in [15], while our overall approach is suitable forr other similar applications for which custom hardware is utilizzed, such as the calculation of flying object s optimal noise reduuction paths [23].
Sentence 2: the exact FD methods implemented are the explicit and the Crank-Nicholson schemes.
Relationship: neutral
Domain: Hardware
Sentence 1: From the results presented in Table 2, we can conclude that our approach is particularly strong in the .ne locali­sation of the segment boundaries: we outperform Kaiser &#38; Peeters system for a tolerance of 0.5 s. However, increasing the tolerance to 3 s has a much larger bene.cial e.ect on their performance than on ours.
Sentence 2: geoffroy Peeters STMS IRCAM-CNRS-UPMC 1, Place Stravinsky 75004 Paris, France geoffroy.peeters@ircam.fr trices [1], obtained by comparing some low level acoustic feature, like MFCC s or chromas, to time-delayed copies of itself.
Relationship: neutral
Domain: Hardware
Sentence 1: The intra-iteration constraint here means that the starting address in region E or F should be already computed in region A (or B), which guarantees that VNFUs have to start only after all the check-to-variable messages in the same column passed by CNFU are already available.
Sentence 2: note that received data are retrieved in z memo­ries while c memories store the hard decision of soft output sgn(Lqj ) used for parity checking in the following iteration.
Relationship: neutral