sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: To obtain high efficiency, DC-DC converters using a fixed pulse-width modulation (PWM) and divided switches with current control (DSCC) have been reported [4], [5].
Sentence 2: these reported converters cannot realize a high packing density on board and easy implementation to VLSIs, because these converters need additional off-chip components of inductance, capacitance, and pn-diode on board.
Relationship: contrasting
Domain: Hardware
Sentence 1: Although most recent works report very aggressive .gures of merit in pixel power consumption, ranging from 460pW/frame.pixel [4] up to 84pW/frame.pixel [7], it has to be pointed out that these works only refer to imagers where the vision processing is accomplished outside the chip and typically takes a large power consumption.
Sentence 2: a vision sensor embeds a custom image pro­cessing and can tolerate a larger consumption at chip-level, in exchange for reduced external computational resources.
Relationship: contrasting
Domain: Hardware
Sentence 1: Con.g Best Median Width 4 6 ROB / IQ / LSQ 152 / 32 / 48 96 / 56 / 72 RF /Read/Write 136 / 4 / 1 72 / 4 / 3 Bpred / BTB / Br 16K / 2K / 8 1K / 2K / 24 I/D/U cache 64K / 8K / 4M 16K / 128K / 1M  gzipwupwiseswimmgridappluvprgccmesagalgelartmcfequakecraftyfacereclucasfma3dparsersixtrackeonperlbmkgapvortexbzip2twolfapsi AVG ulations that achieves around 10%.
Sentence 2: using only 32 training simulations per benchmark allows it to .nd the minimum after a total of 135 simulations per benchmark.
Relationship: contrasting
Domain: Hardware
Sentence 1: Low Power Test Generation for Path Delay Faults using Stability Functions M.M Vaseekar Kumar ECE Department, Southern Illinois Univeristy Carbondale,IL 62901 vaseekar@engr.siu.edu ABSTRACT 1 A recent work describes an ATPG for path delay faults that limits the power dissipated by the test patterns to a given bound.
Sentence 2: the power dissipated by the inter­mediate patterns while applying the test patterns in a se­quence is not considered.
Relationship: contrasting
Domain: Hardware
Sentence 1: of Information Technology University of Pisa, Italy University of Milano, Italy annab@di.unipi.it ciriani@dti.unimi.it, cordone@dti.unimi.it ABSTRACT Multi-level logic synthesis yields much more compact ex­pressions of a given Boolean function with respect to stan­dard two-level sum of products (SOP) forms.
Sentence 2: minimizing an expression with more than two-levels can take a large time.
Relationship: contrasting
Domain: Hardware
Sentence 1: Cheung1 and Wayne Luk2 1Department of Electrical and Electronic Engineering 2 Department of Computing Imperial College London {t.mak, p.cheung}@imperial.ac.uk wl@doc.ic.ac.uk Kai Pui Lam Department of Systems Engineering &#38; Engineering Management The Chinese University of Hong Kong kplam@se.cuhk.edu.hk ABSTRACT Dynamic routing is desirable because of its substantial improve­ment in communication bandwidth and intelligent adaptation to faulty links and congested traf.cs.
Sentence 2: implementation of adaptive routing in a network-on-chip (NoC) system is not triv­ial and further complicated by the requirements of deadlock-free and real-time optimal decision making.
Relationship: contrasting
Domain: Hardware
Sentence 1: It is based on the following observation: take the NAND2 gate for example, the worst leakage current (454.50 nA for a 0.18µm technology) hap­pens when both its inputs are logic 1 at the standby mode.
Sentence 2: if we replace it by a NAND3 gate and let the additional input signal to be 1 at active mode and 0 at standby mode (this can be trivially achieved by the complement of the SLEEP signal), then the in­put to this NAND3 at standby mode will be {110} which yields 94.87nA leakage current, a reduction of about 80%!
Relationship: contrasting
Domain: Hardware
Sentence 1: C(b) · tc is tight , it can be easily violated dependening on the values of Lr(1)max and Lr(2)min.
Sentence 2: if Lr(1)max < Lr(2)min is guaranteed,  forbidden ' (a) · tc (a ) · tc clock r2 (b) · tc +.r(2) max (a) SRV-based register assignment ' (a) · tc (a ) · tc +.r(1) min clock  r2 tc (b) · tc +.r(2) max (b) Backward-Data-Direction (BDD) clocking ' (a) · tc +.r(1) max (a ) · tc clock  (b) · tc +.r(2) min (c) Forward-Data-Direction (FDD) clocking Figure 2: (a) Ensuring the hold timing constraint by SRV-based register assignment.
Relationship: contrasting
Domain: Hardware
Sentence 1: It can be seen from Figure 2 that con.guration #16 has the best IPC and con.guration #18 has the best cycle time.
Sentence 2: con.guration #24 has the best performance in terms of BIPS, underlining the fact that it is important to look at both the architectural and physical design spaces together to draw conclusions on the overall performance of any microarchitecture.
Relationship: contrasting
Domain: Hardware
Sentence 1: CONCLUSIONS AND FUTURE WORK Asgeneral-purposeprocessorscontinuetobeusedforan increasingnumberofapplicationdomains,itisimportant toensurethatarchitecturalfeaturesthatuseasignifcant fractionoftheon-chiptransistorsareusefulformostsuch applications.Mostcurrentgeneral-purposeprocessorsde­votethelargestfractionoftheon-chiptransistorstocaches.
Sentence 2: severalimportantapplicationsdonotexploitlarge caches.Forexample,mediaprocessingapplicationsoften fndlargecachestobeinefectiveduetotheirstreaming dataaccessesandlargedatasets[19].Astheseapplications increaseinimportance,currentgeneral-purposesystemde­signphilosophywillforceatradeofbetweenresourcesfor mediaprocessingandotherapplicationdomains.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this case,Chang s work foundthe Xtobe false,while our analysis showedthat the bufferwas notable to eliminate the X.
Sentence 2: since the repair code we produced may eliminate the false Xs at earlier cyclesifthe conditions match,we actually eliminated140 false Xs out ofthe 201Xsproven tobe falsebyChang s .ow, 15 more than the 125false Xs identi.edin our .ow.
Relationship: contrasting
Domain: Hardware
Sentence 1: TECHNIQUES TO REDUCE REGISTER VULNERABILITY FACTOR There are a number of research e.orts on improving re­liability of various system components of processors in the literature, such as the techniques to address soft errors for main memories [3, 12], caches [7, 8], and the datapath [9, 10, 11].
Sentence 2: little work has been done to explore the impact of soft errors on register .les, which is accessed very frequently and thus can signi.cantly impact the system reli­ability if not protected.
Relationship: contrasting
Domain: Hardware
Sentence 1: Also note that in direct-mapped caches, tags can be put into drowsy mode without undue performance impact or implementation complexity (see Section 2).
Sentence 2: using a direct mapped data cache instead of the 4-way asso- ciative one has its own costs: miss rates on our benchmarks are approximately tripled, which--aside from the perfor- mance penalty--can significantly impact the total energy consumption of the processor.
Relationship: contrasting
Domain: Hardware
Sentence 1: On a cache miss, however, the miss detection will not reveal until near the end of the access, therefore updating the LAB can only be done after the current access.
Sentence 2: this will not impact the performace since the next cache access will not bene.t from the current miss anyway (we do not attempt to re.ect the cache re.ll in the set bu.er).
Relationship: contrasting
Domain: Hardware
Sentence 1: Introduction Dynamic Random Access Memory (DRAM) has been used as main memory for decades due to its high-density, high­performance and low-cost.
Sentence 2: dRAM technologies are Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: contrasting
Domain: Hardware
Sentence 1: For benchmarks that do not bene­.t from compression (e.g, leslie3d, GemsFDTD, and hmmer), all compression schemes degrade performance compared to the base­line.
Sentence 2: b.I has the lowest performance degradation with its low 1-cycle decompression latency, and never degrades perfor­mance by more than 1%.
Relationship: contrasting
Domain: Hardware
Sentence 1: trend generally matches that of (6) in Figure 3.
Sentence 2: at t = 9 Although the method of [5] claims reduction of all power in particular, the power savings of 60% are still 12% short of the including the clock-tree power by 50% when t = 1, the actualpredicted value from (5) and (6) for two reasons: The first is the power savings would be less because the clock-tree must be kept effect of extra clock cycles, as described in Section 2.5, and the active for the controlling state machine.
Relationship: contrasting
Domain: Hardware
Sentence 1: 2.ONSET DETECTION METHODS The history of onset detection using computers can be traced back to the 1980's when several algorithms, such as the one presented by Schloss [34] in 1985, were proposed to find the beats in music signals composed solely of percussion.
Sentence 2: only in 1994 Muroaka and Goto [19] proposed the first algorithm 1 Bello[3] and Klapuri [24] both define the transient as a short-time interval in which a significant energy change occurs in the signal.
Relationship: contrasting
Domain: Hardware
Sentence 1: Modified Covering Matrix Dmn Since the size of matrix Dmn is large, though much smaller than that of Cmp, we borrow techniques from logic synthesis (essentiality [20], row and column dominance [10, 21], partitioning [10, 11] or Gimpel s reduction [10] method) to first try to simplify the problem and afterwards solve the reduced problem.
Sentence 2: in our case, the elements of matrix Dmn are free to take any positive integer value, so, it is necessary to extend the definitions and the techniques of essentiality and dominance before they can be applied to our problem.
Relationship: contrasting
Domain: Hardware
Sentence 1: Heneweantransformtheolumnorderingproblemfor odestoanedgeorderingproblemforgraphs.
Sentence 2: wehaveexaminedtheexisteneofoptimaledgeorderings forsmallvaluesofd[8].Whend=3,theaessostfor aspeifsubgraphisatleast3,andatmost6.Aess ost3ourswhenthreeonseutiveedgesindueatri­angle;onlytrianglesyieldthisminimum.when {ci,ci+l,ci+2}formsatriangle,{ci.l,ci,ci+l}annotalso formatriangleunlessn=3,sineci.l=ci+2isneessary ifbotharetriangles.Nowwhenthreeonseutiveedgesdo notformatriangle,thefewestvertiesinduedisfour,whih anberealizedbyapathorastaronthreeedges.Figure 4showsthefrsttriangleandthefrststaroftheladderor­deringforK;.Theseorrespondtothefrsttwowindows.
Relationship: contrasting
Domain: Hardware
Sentence 1: Conversely, classic source code pro.lers encompass­ing Source-Level Performance Estimation (SLPE) [16, 13, 18] utilize machine-independent optimizations pro­vided by the host compilers to resemble the optimiz­ing target compilation process for the sake of accuracy.
Sentence 2: the accuracy is still prohibitively limited, es­pecially for VLIW architectures and Application Spe­ci.c Instruction-set Processors (ASIPs), which are re­grettably the main areas where accurate pro.ling is needed.
Relationship: contrasting
Domain: Hardware
Sentence 1: Hence, the computational cost can be only O(MN log2 MN), where M, and N are numbers of divisions in the power density map along x-, and y-directions, respectively.
Sentence 2: the convergent rate of their formulation is not fast enough because the generated cosine series based on time-independent Possion's equation [6] can not fully capture the transient characteristics of original heat equations.
Relationship: contrasting
Domain: Hardware
Sentence 1: Among other seven cases, one for example is T2=(x5, x6 ,x2,x1,x4,x3).
Sentence 2: it can be seen that: f (T -1) = f (x , x , x , x , x , x1) = x2 x x + x2 x1x + x x x + x x1x , 1 53642 15 3 216 24 f (T -1) = f (x , x , x , x ,x , x2 ) = x1x x + x1 x2 x + x x x + x x2 x .
Relationship: contrasting
Domain: Hardware
Sentence 1: Adding metal layers for reference planes will add sig­ni.cant manufacturing cost to the chip compared to con-  ventional CMOS technology.
Sentence 2: the International TL Drivers &#38; TL Drivers &#38; Receivers Receivers Technology Roadmap for Semiconductors already TL Link projects, for the year 2010, integrating four reference planes into high performance chips to provide inductive shielding and decoupling capacitance [14].
Relationship: contrasting
Domain: Hardware
Sentence 1: Over the last thirty years, CMOS has been the dominant technology with a steady shrinking in feature size [4].
Sentence 2: the quantum effects at such reduced feature size and the limitations in fabrication technology present serious hurdles in the nano ranges; new active devices such as Carbon Nano Tube FETs, Quantum-dot Cellular Automata (QCA) and Single Electron Transistors (FETs) have been proposed as emerging technologies [6].
Relationship: contrasting
Domain: Hardware
Sentence 1: II.TheTangramFramework A.Handshaketechnology ThedesignoflargescaleasynchronousICsdemandsa timingdisciplinetoreplacetheclockregimethatisused inconventionalVLSIdesign.Wehavechosenhandshake signaling[25]astheasynchronoustimingdiscipline,since itsupportsplug-and-playcompositionofcomponentsinto systems,andisalsoeasytoimplementinVLSI.Analter­nativetohandshakingwouldbetocomposeasynchronous  Active - Passive .
Sentence 2: fig.1.Handshakechannel:abstractfgure(top)and implementation(bottom) fnite-statemachinesthatcommunicateusingfundamen­talmodeorburst-modeassumptions.attempts tousethispathtodesignindustriallysizedcircuitshave suferedfromseverereliabilityandinterfaceproblems[9].
Relationship: contrasting
Domain: Hardware
Sentence 1: IfseveralLUTsareclusteredintoonelogicblock,signalsharing amongLUTscanbeexploited.Sincetheinterconnectinsidethe logicblocksarehardwiredlocalinterconnectcanbemadevery fastandefciently.Thisimprovesroutabilityanddecreasesthe loadontheroutersignifcantly.Ontheotherhand,itisnotfeasi­  Some text in this electronic article is rendered in Type 3 or bitmapped fonts, and may display poorly on screen in Adobe Acrobat v. 4.0 and later.
Sentence 2: printouts of this file are unaffected by this problem.
Relationship: contrasting
Domain: Hardware
Sentence 1: In order to improve the loopback observability, the authors proposed to .rst characterize the TX using a subsampling architecture based on Periodically Nonuniform Sampling of second order (PNS2).
Sentence 2: as presented, the approach required external (off-unit, off-radio, off-board or off-chip, according to the level of integration) computing capability (still, at reduced cost w.r.t.
Relationship: contrasting
Domain: Hardware
Sentence 1: Inthe 90nm library that we used, this would mean that SSTA wouldhave to keep track of thousands of random variables for CD varia­tion alone, which is unacceptable.
Sentence 2: in our work we hypothesized that since there are two main underlying compo­nents of CD variation, exposure and defocus, CD could be mod­eled as a function of ~2 components.
Relationship: contrasting
Domain: Hardware
Sentence 1: Although microelectromechanical systems (MEMS) is a relatively young .eld compared to integrated circuits, reliability studies for MEMS have received considerable attention [McCluskey 2002].
Sentence 2: due to signi.cant 687 differences in the actuation principles underlying digital micro.uidics and MEMS, these reliability enhancement techniques cannot be directly used for the design of micro.uidics-based biochips.
Relationship: contrasting
Domain: Hardware
Sentence 1: Figure 5 brings out this fact more clearly by showing that the dynamic power of repeater reduces signi.cantly whereas leakage power of repeater in­creases for smaller technology nodes.
Sentence 2: the leakage power is a small fraction of overall power of repeater in Fig­ure 5 or interconnect in Figure 4 because we consider a work­load with high activity factor in these con.gurations.
Relationship: contrasting
Domain: Hardware
Sentence 1: Those applications, most of whose working set .ts in the RLDRAM memory, bene.t from this organization showing higher bene.ts compared to our scheme.
Sentence 2: the loss in performance is due to many accesses to the LPDRAM - since the top 7.6% of pages only account for a maximum of 30% of all accesses for any of the programs.
Relationship: contrasting
Domain: Hardware
Sentence 1: Even though the previous works can consider the clock skew constraint on every power mode, it would be highly likely that the resulting clock tree uses a substantially long wirelength or there is no clock tree that satis.es the clock skew constraint on every power mode.
Sentence 2: post-silicon tuning (e.g., [4, 5, 12, 9]) such as inserting Adjustable Delay Buffers (ADBs) is a widely used method to deal with the timing problem caused by process and environment variations.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since then, there has been some works analyzing the characteristics of the NoC considering the many mechanisms, protocols and design options available for implementing NoC architectures and proposing techniques to improve its quality [1], [15], [3] and [6].
Sentence 2: there have been some proposals of tools to choose the best platform configuration and to map applications to the target NoC architec­ture.
Relationship: contrasting
Domain: Hardware
Sentence 1: Seminal work by Sigl, Doll and Johannes in the early 1990s developed a linearization tech­nique that represents the linear wirelength objective on graphs by a dynamically-weighted quadratic objective [25].
Sentence 2: the modeling of multi-pin nets remained inaccurate, and the research community has largely replaced quadratic optimization by much more cumbersome and slow non-convex optimization techniques ten years later [7,10,16].
Relationship: contrasting
Domain: Hardware
Sentence 1: Underestimation that might occur due to neglecting the impact of variability or, in some cases, due to inaccurate modeling of reconvergence may result in inadequate protection or hardening choices.
Sentence 2: grossly overestimating error rates that can occur due to ignoring electrical and timing masking effects results in overly conservative protection and hardening techniques, and consequently, in overdesigning with higher performance penalty, power or area cost.
Relationship: contrasting
Domain: Hardware
Sentence 1: Consider variable e2 in the subtree under e1 = 1, switching from e2 = 1 to e2 = 0 without .nding a satisfying assignment does not imply that (¬e2) has been learned.
Sentence 2: it is possible to learn about non-root variables in some circumstances, as shown by Lemma 2.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4.1 Logic Synthesis and Technology Mapping There have been many recent attempts to integrate logic synthesis and technology mapping with placement (that approximate global routes by bounding boxes or trees) (e.g., [10,11]).
Sentence 2: although this physical synthesis tries to comprehend the capacitive load of wires, the metrics that drive it are still the traditional literal or gate counts and fanout-based wire load metrics, sometimes augmented with estimated wirelengths.
Relationship: contrasting
Domain: Hardware
Sentence 1: Table I reports the size of binaries and con.guration bit­streams, obtained with our approach (multi-objective) and with We can observe that the overhead in terms of binary size is lower than 4%.
Sentence 2: the bit-stream overhead is consider­able higher in our case (25% for INCAR and 50% for WFS) since there is the need to store all the CCU implementations required by the selected operating points.
Relationship: contrasting
Domain: Hardware
Sentence 1: He wanted to avoid jump cuts and the best way of doing this was being able to know which types of shots were available - Going from a wider shot to a closer one looks pretty as oppose to jumping between medium shots.
Sentence 2: he acknowledged that a lot of modern editing actively employs jump cuts as stylistic device, so, from the automatic authoring perspective, a reliable awareness of the shot type would allow it to have rules that could enforce a conventional styles of editing or move towards a modern style of editing, depending on the preferences of the end-users.
Relationship: contrasting
Domain: Hardware
Sentence 1: [11]pioneeredthestudyoferasure­resilient odesforlargediskarrays.Theyexaminedstruturalon­ditionswhihguaranteehigherasureorretionapability, athemewhihispursuedin[4,7].Theyalsoundertook ananalysiswhihrevealstheneedformultipleerasureor­retionwhenthenumberofdisksis'large'.Theyshowed thatanarrayofonethousanddiskswhihprotetsagainst oneerror,evenwithperiodidailyorweeklyrepairs,hasa lowerreliabilitythananindividualdisk.Theiranalysisas­sumesthaterasuresaredetetedwhentheyour;thetruth fordiskarraysisworsenediftherearelatentsetorfaults, whihmayremainundetetedforlongperiods;see[1].As arraysgrowinsize,theneedforgreaterredundanywithout aredutioninperformanebeomesapparent.
Sentence 2: reliabilityisevidentlyamajoronern.thetrade­ofbetweenreliabilityandperformanehastypiallybeen resolvedinfavorofperformane,andonsequentlymulti­pleerasuresystemsareoftendismissedasnotommerially viable.Mosturrentlyavailablesystemshandleonlyone diskfailure[16].Improvementsintheperformaneofre­onstrutionhavebeenthesubjetofanexellentanalysis [20],butitisthe'poor'performaneofbasireadandwrite operationsinafault­freeenvironmentwhihhavelimited thepratialuseofmultipleerasuresystems.Wetherefore fousonhowthehoieoferasureode,andthemanner inwhihitisused,afetsperformaneofbasioperations, espeiallyinfault­freemode.
Relationship: contrasting
Domain: Hardware
Sentence 1: Navid Aziz and Farid Najim explored two operating modes of high performance and low power FPGA block and reported reduction in leakage power by 53% [4].
Sentence 2: in recent years increasing demand of battery operated handy devices and emerging IC applications such as distributed sensor networks, RFIDs, medical devices, etc., are trusted for inflexible power budgets.
Relationship: contrasting
Domain: Hardware
Sentence 1: This im­plies that a two-party key exchange protocol that satis.es SK-security preserves its security under arbitrary protocol composition.
Sentence 2: katz and Shin [24] de.ne an ideal functionality for the task of GKE in the UC frame­work and show that this notion of UC-security is strictly stronger than the game-based notions for GKE.
Relationship: contrasting
Domain: Hardware
Sentence 1: Another input signal to PFE is bias voltage Vbsf given to SF.
Sentence 2: a waveform acquisition kernel includes a reference level gen­erator (VG) supplying Vref from a 10-bit R-2R ladder, a sampling timing generator (TG) providing Tck from a 10­bit variable step delay generator, and a data processing unit (DPU) producing a series 10-bit digital word from Dout.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4.1 System Partition After the DIA system is converted to the abstracted sys­tem, this method picks up variables from X that are involved in linear transitions to form a subset XL and variables that are involved in nonlinear transitions to form a subset XNL.
Sentence 2: if variables in XL and XNL are independent with each other, then XL n XNL there often exist variables in = f. XL correlated to variables in XNL.
Relationship: contrasting
Domain: Hardware
Sentence 1: As also stated in the literature, we expect that in a planetary environment there exist areas that receive steadier sunlight; thus, solar power generation on a stationary site would be more efficient than on the peripatetic robots, which would potentially work in a shadowed and dusty environment.
Sentence 2: our methodology also works in the case where a site co-locates with another or in the case where all of them co-locate in one place.
Relationship: contrasting
Domain: Hardware
Sentence 1: One solution to this would be to .nd at ci the worst-case slacks for paths originating at a number of startpoints, and then to estimate the slacks at cj for paths originating from each of these.
Sentence 2: such a solution is not necessary mainly because the estimates of worst-case slack from s. will be close enough to the actual worst-case slacks and will still provide good endpoint coverage as our results will show.
Relationship: contrasting