sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Since the biased branches B or C and D execute only on one of the program paths to the Branch E, the weights associated with Branches B or C and D along the two program paths will develop strong correlations to in.uence the prediction decision of the Branch E [1].
Sentence 2: it is not dif.cult to observe that it is the non-biased Branch A that steers the control .ow through either the Branch B or the Branches C and D that subsequently leads up to the Branch E. As a result, the change in the direction of the Branch A provides suf.cient evidence to cause a change in the direction of the Branch E. In other words, the control .ow through either the Branch B or the Branches C and D in the two program paths merely reinforces the prediction decision of the Branch E that can independently be established by correlating only with the non-biased branch A.
Relationship: contrasting
Domain: Hardware
Sentence 1: Inter-Region Level In the architecture assumed in this section, the power grid is sized su.ciently such that as long as each region draws no more than Imax tile, it can supply enough current to turn on all regions on the chip simultaneously assuming there is no other activity.
Sentence 2: in practice, there will be other  66 65 64 63 62 61 60Imax_tile (mA) supported in power grid Figure 13: Leakage power in on-state for baseline [5] Leakage power whenregion is on (µW) and proposed intra-region architectures The results are reported assuming a region with R =4 and Imax tile = 400 µA.
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Domain: Hardware
Sentence 1: INTRODUCTION  As device dimensions shrink from one technology generation to the next and we approach the physical and economic limits of process shrinks, 3D IC technology offers an alternative that reduces critical wire lengths, achieves higher densities with existing technology nodes, and enables heterogeneous integration.
Sentence 2: a major issue with 3D ICs is that on-chip temperature variations can be signi.cant as ever more circuitry is packed in per unit footprint.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since OBLIDO does not involve any coordination among the processors the total of n 2 jobs are performed (counting multiplicities).
Sentence 2: it was shown [2] that if we count only the job executions such that each job has not been pre- viously performed by any processor, then the total number of such job executions is bounded by Cont(kO), again count- ing multiplicities.
Relationship: contrasting
Domain: Hardware
Sentence 1: Instead of directly com­paring the synthesized RTL with the sequential description, we develop an intermediate pipeline reference model.This model provably preserves the semantics of the sequential description.
Sentence 2: our model generation algorithm is parameterized by pipeline parameters, whose values are ob­tained from the synthesis tool; this ensures that the struc­ture of the generated model is similar to that of the synthe­sized RTL, and enables internal operation mapping between the reference model and the RTL.
Relationship: contrasting
Domain: Hardware
Sentence 1: This syn­chronization can be achieved without locks: the producer checks the .ag, produces the data, and sets the .ag; the consumer checks the .ag, consumes the data and resets the .ag.
Sentence 2: this lock-free mechanism relies on the premise that accesses to data and .ag shall not be reordered, either by hardware or software (e.g., due to a programmer mis­take).
Relationship: contrasting
Domain: Hardware
Sentence 1: As shown in the table, if we select the function with the most soft­ ware cycles (on the MIPS determined using LEAP) for accelera­ tion, function buf getb will be synthesized to hardware, resulting in 63,337 cycles of actual reduction versus a pure-software imple­mentation.
Sentence 2: by choosing the function that has the highest estimated cycle reduction, function YuvToRgb will be synthesized to hardware, leading to an execution time reduction of 327,308 cy­cles.
Relationship: contrasting
Domain: Hardware
Sentence 1: In T9, the MONITOR generates a SIGCF as the original CFI was supposed to cause a change in the control .ow to a basic block other than the basic block under the current basic block in memory (e.g., the jump CFI).
Sentence 2: if the original CFI was such that the basic block under the current basic block in memory is a valid tran­sition, then the attack may not be detected (e.g., the branch CFI).
Relationship: contrasting
Domain: Hardware
Sentence 1: This would be a good metric to use because it is quantitative; it would allow one to conclude, for example, that S2 is more robust than S1 whenever d2 >d1.
Sentence 2: in the general case where several parameters are varying, and where parameterized timing quantities are piecewise planar surfaces, each with a different set of sensitivities, things can get more complicated.
Relationship: contrasting
Domain: Hardware
Sentence 1: A. Noise-resilient control scheme The 3-phase control scheme cannot be made functional with faster devices, owing to logic 0 glitching effects described previously.
Sentence 2: since control schemes are driven externally and do not have any nanoscale customiza­tion, it is possible to alter them without imposing new manu­facturing requirements, alleviating noise effects and enabling  3-phase sequencing scheme.
Relationship: contrasting
Domain: Hardware
Sentence 1: Automatic Test Bench Generation for Validation of RT-level Descriptions: an Industrial Experience F. Corno, M. Sonza Reorda, G. Squillero Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy http://www.cad.polito.it/ Abstract In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design productivity is greatly enhanced.
Sentence 2: in the new design flow, validation still remains a challenge: while new technologies based on formal verification are only marginally accepted, standard techniques based on simulation are beginning to fall behind the increased circuit complexity.
Relationship: contrasting
Domain: Hardware
Sentence 1: For task management on MPU, due to the thick OS layer with large context switch overhead, the kernel response time plus the IPC overhead contributes almost 54% of the total execution time.
Sentence 2: for task management on DSP, the kernel response time plus the IPC overhead has been reduced from 23,040µs to 4,609µs compared to the MPU due to lightweight kernel on DSP and reduced interactions between the MPU and the DSP.
Relationship: contrasting
Domain: Hardware
Sentence 1: The algorithm described here is capable of handling non-perfectly nested loops as well as non-affine access functions by virtue of focusing only on which dimensions of each array are accessed by each array reference.
Sentence 2: and due to its simplicity the current algorithm implementation cannot capture notions such as sections of arrays (e.g., a tile or a row) or the direction in which the data is accessed.
Relationship: contrasting
Domain: Hardware
Sentence 1: It can be seen from Figure 2(b) that the system has to operate at di.erent energy levels to obtain the target quality for di.er­ent parts of the data set.
Sentence 2: static scaling results in roughly constant energy, leaving the designer with an un­desirable choicebetween excessive errors(ifthe scaling level isdetermined aggressively) or sub-optimal energy savings(if the scaling level is determined conservatively).
Relationship: contrasting
Domain: Hardware
Sentence 1: AtransitioncontrollablenoisesourceshowninFig.1 wasdevelopedforthispurpose.Thecircuithasamulti­phaseclock(Ck[0:10])generator,whichconsistsofodd delayelementsinseries,andamatrixofnoisesource blocks.ThedelayelementhasbiasvoltagesVnandVp forregulatingriseandfalldelay,respectively.Inverseor non-inversetransitionamongtheadjacentnoisesource blocksareselective.Thenumberofnoisesourceblocks tobeactivatedbyCk[0:10]canbe0to15,whichissetby addresssignalsx[0:3]with2Xweights.Finally,thecircuit cangeneratesubstratenoiseswithcontrolledtransitions insize,inter-stagedelay,anddirection.Thenoisesource blockincludes30invertersoperatinginparallel.Each inverterhasa50fFloadcapacitoragainstthesubstrate, whichcorrespondstoinputcapacitancesoftwologicgates Some text in this electronic article is rendered in Type 3 or bitmapped fonts, and may display poorly on screen in Adobe Acrobat v. 4.0 and later.
Sentence 2: printouts of this file are unaffected by this problem.
Relationship: contrasting
Domain: Hardware
Sentence 1: Wormhole switches can be con.gured to contain very small bu.ers.
Sentence 2: it is well known that this switching tech­nique may decrease the network utilization if a .it from a given packet is blocked in a bu.er, problem which can be solved by intro ducing virtual channels in the input and out­put ports, at the cost of increased bu.ers size [3].
Relationship: contrasting
Domain: Hardware
Sentence 1: From Simulink to NoC-based MPSoC on FPGA ¨ Francesco Robino, Johnny Oberg Department of Electronic Systems Royal Institute of Technology (KTH), Sweden Email: {frobino,johnnyob}@kth.se Abstract Network-on-chip (NoC) based multi-processor sys­tems are promising candidates for future embedded system platforms.
Sentence 2: because of their complexity, new high level modeling techniques are needed to design, simulate and synthesize embedded systems targeting NoC-based MPSoC.
Relationship: contrasting
Domain: Hardware
Sentence 1: 1 depicts the TI OMAP platform where a real-time kernel called DSP/BIOS [3] incorporated with the DSP/BIOS Link (or Linux DSP Gateway) [4] provides software layer abstraction on DSP and complete IPC (Inter-processor communication) mechanism.
Sentence 2: although the MPU is suitable for task management, the frequent interaction between the MPU and the DSP will significantly affects the DSP utilization due to slow MPU response time incurred by the thick OS layers.
Relationship: contrasting
Domain: Hardware
Sentence 1: This trend makes it more attractive to consider using field-programmable gate array (FPGA) platforms, which may provide comparable raw performance and more flexibility at a lower cost for many applications.
Sentence 2: the shrinking feature size predicted in Moore s law has resulted in an explosive growth in functionality and the amount of computing Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: contrasting
Domain: Hardware
Sentence 1: The important point we want to make is that we can not use such techniques indiscriminately for all SPM lines since doing so can increase power consumption dramatically.
Sentence 2: we demonstrate that proper use of such techniques can lead to further performance improve­ments over the case where we only exploit the variable la­tency SPM through latency-aware data placements, and this performance improvement comes at the expense of little ex­tra power consumption.
Relationship: contrasting
Domain: Hardware
Sentence 1: 2, if we do not consider the resistance of the link, adding a link between node b and node c will be better than adding a link between node a and node b, since node a and node b share some parts of their paths from the source and the delay difference will be smaller.
Sentence 2: if the distance between node b and node c is larger than the distance between node a and node b, it will be difficult to say which link is better.
Relationship: contrasting
Domain: Hardware
Sentence 1: Such complex algorithms have traditionally been implemented on high-performance computing clusters and multiprocessor systems [5], and recently, with the emergence of multicore and manycore architectures, on clusters and workstations equipped with such CPUs.
Sentence 2: there has been a tremendous amount of effort in designing efficient systems that can take advantage of the inherent parallelism opportunities of such algorithms; one of the most powerful supercomputers in the world (IBM Blue Gene) has been designed with the objective of performing large scale protein folding simulations [6].
Relationship: contrasting
Domain: Hardware
Sentence 1: Currently, the frequency of such transient faults is low typically less than one fault per year per thousand computers [20] making fault-tolerant computers attractive only for mission-critical applications, such as online transaction processing and space programs.
Sentence 2: future microprocessors will be more prone to transient faults due to their smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins.
Relationship: contrasting
Domain: Hardware
Sentence 1: The mobility of the present device is far superior to that of amorphous silicon (typically 1.0 cm2/Vs) and is the highest ever reported for flexible organic transistors prepared on plastic films with polymeric gate insulators, to the best of our knowledge.
Sentence 2: an operating bias of 40 V is not realistic for artificial skin applications; however, the device is still functional with a relatively large mobility (0.1 cm2/Vs) when an 8-V operating bias is applied.
Relationship: contrasting
Domain: Hardware
Sentence 1: However, if we examine the effect for individ­ual benchmarks, then we see that the impact of increasing Ævaries signi.cantly.
Sentence 2: for example, for 179.art, 183.equake and 188.ammp, reducing Æresults in lower 1with no sig­ni.cant impact on p. for 164.gzip and 197.parser, the reduction in pis very signi.cant.
Relationship: contrasting
Domain: Hardware
Sentence 1: Equation 10 can therefore be re-written as minimize f(x) = max{AI (k), AE (k)} (11) k D. Solution Approach The objective function in Equation 11 is convex (proof is omitted for space limitations) and is solved using CVX, a package for specifying and solving convex programs [14], [15].
Sentence 2: to use this tool, the objective and the con­straint functions needs to be modi.ed into disciplined convex programming.
Relationship: contrasting
Domain: Hardware
Sentence 1: Directory-based protocols have the advantage that co­herency request is sent only to the remote caches which have the requested data.
Sentence 2: as a coherency request is processed as two bus transactions in directory-based proto­cols -one to access directory, another to access owner cache, if we simply apply it to shared bus-based MPSoCs, the num- Copyright 2007 ACM 978-1-59593-605-9/07/0003 ...$5.00.
Relationship: contrasting
Domain: Hardware
Sentence 1: IN T RO D U C T I O N In recent years, on chip networks have become a standard solution for connecting systems on chip (SoC) and chip multiprocessors (CMPs) with tens to thousands of processing elements.
Sentence 2: as those systems continue to scale in size and complexity, the cost of communication between distance cores, in terms of delay and subsequent throughput congestion along the routed path, continues to increase.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the minimum time to wait is too small there will be many packet collisions mostly with the retransmission of data and the ACK packet itself, this leads to an increased number of retransmissions.
Sentence 2: if the mini­mum time before retransmission is too large than if a packet is not received the transmitter is waiting needlessly long to resend the data leading to low throughput and a high round trip time (RTT) even though very few retransmissions are needed.
Relationship: contrasting
Domain: Hardware
Sentence 1: ATPG for Noise-Induced Switch Failures in Domino Logic Rahul Kundu and R. D. (Shawn) Blanton Center for Silicon System Implementation ECE Department Carnegie Mellon University Pittsburgh, PA 15213-3890  Abstract Domino circuits have been used in most modern high-performance mi­croprocessor designs because of their high speed, low transistor-count and hazard-free operation.
Sentence 2: with technology scaling, domino circuits are increasingly susceptible to switch failures due to various noise sources that include crosstalk, charge sharing and leakage.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4 Iterations CT Figure 3: Iterative looping with partial loop unrolling archi- tecture block diagram of thirty-one 128-bit registers that would be required for a fully pipelined architecture~ resulting in a reduction of the area required for the implementation.
Sentence 2: implement- ing the thirty-two rounds of the algorithm in asynchronous logic severly hampers the overall clock frequency of the sys- tem.
Relationship: contrasting
Domain: Hardware
Sentence 1: Interest­ingly, a mode change from default to biased modes has no latency overhead, compared to the biased mode latency, because recon.gu­ration takes place in parallel to processing the .it.
Sentence 2: mode changes from biased to default mode does incur overhead: the incom­ing .it is stalled while recon.guration takes place.
Relationship: contrasting
Domain: Hardware
Sentence 1: From (8) we can get E V +s VO,avg N C +1 O,avg IPH (VPH )- Iamp 1 V PH= - 2 + 2 · (11)N +1 (N +1) (N +1) fclk C + C C + C SE SE N N In order to lower the value of VPH, we should minimize VO,avg.
Sentence 2: for the integrate-and-dump method, Vmax, Vmin, and VO,avg, are all greater than the fully-charged battery voltage.
Relationship: contrasting
Domain: Hardware
Sentence 1: 1074-1083. sometimes prevents the procedure from distinguishing all [6] A. Veneris, R. Chang, M. S. Abadir and S. Seyedi, "Functional the fault pairs that can be distinguished with fully-Fault Equivalence and Diagnostic Test Generation in Combina­ speci.ed tests.
Sentence 2: the use of test cubes also allows tional Logic Circuits Using Conventional ATPG", Journal of Electronic Testing: Theory and Applications (JETTA), vol.
Relationship: contrasting
Domain: Hardware
Sentence 1: (MHz) 25 80 135 33.33 65 115 Throughput (Mbits/s) 500 3200 5400 1333 2600 4600 Slices / LUTs 278 / 555 275 / 459 330 / 547 352 / 772 583 / 957 706 / 1283 Flip Flops / BRAMs 172 / 0 134 / 0 197 / 0 478 / 10 240 / 0 358 / 0 some certain advantages such as being directly compatible with most available IPs including GPP [7].
Sentence 2: the competition of the connected modules to access the bus introduces arbitrary latencies.
Relationship: contrasting
Domain: Hardware
Sentence 1: In order to further reduce the wire latency and power consumption, transmission-line (T-line) e.ects of on­chip wires have been utilized by adopting fat top layer wires driven by low impedance [3].
Sentence 2: the Inter-Symbol In­terference (ISI) due to the resistive loss severely limits the bandwidth of such T-line schemes and equalization concepts have been applied to alleviate the ISI and push for higher throughput density [7].
Relationship: contrasting
Domain: Hardware
Sentence 1: In the remainder of this paper, unless stated otherwise, when we mention footprint vector for an array and a loop position, we mean the com­bined footprint vector (that is, the contributions of all references are taken into account).
Sentence 2: it should be stressed that we still need multiple footprint vectors for each array as we need to repre­sent the array traversal in each loop direction.
Relationship: contrasting
Domain: Hardware
Sentence 1: On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu University of Massachusetts at Amherst Abstract Scaling of transistor feature size over time has been facilitated by corresponding improvement in lithography technology.
Sentence 2: in recent times the wavelength of the optical light source used for photolithography has not scaled in the same rate as that of the minimum feature size of the transistor.
Relationship: contrasting
Domain: Hardware
Sentence 1: This work discusses several approaches to e.ectively man­age NBTI impact, focusing on di.erent micro-architectural components, namely bu.ers and arbiters.
Sentence 2: [7] does not exploit the information on actual NoC tra.c between each router pair, hence it does not catch the possibility to aggressively reduce NBTI degradation as well as to perform a NBTI/performance trade-o..
Relationship: contrasting
Domain: Hardware
Sentence 1: In both the CIM and Nahalal layouts, sequential search may take a long time to complete, the worst case occurring when all banks are searched.
Sentence 2: we observe that Nahalal has an advantage in average search time (as well as average power dissipation) thanks to its more predictable placement of shared lines, as we now explain and is confirmed in simulations in the next section.
Relationship: contrasting
Domain: Hardware
Sentence 1: 3.4 TO-MSI: an example coherence protocol Conventional coherence protocols assume that each line present in a cache has an entry in both the tag and data Figure 3: Functional description of the TO-MSI example coherence protocol arrays.
Sentence 2: a reuse cache needs a coherence protocol able to deal with lines that have entries in the tag array but not in the data array.
Relationship: contrasting
Domain: Hardware
Sentence 1: The way in which the extra edges are to be added to semi-eulerize and subsequently, the identi.cation of an Euler path depends on the choice of the source and sink ports.
Sentence 2: the graph model of an M × N mi­cro.uidic array can be semi-eulerized simply by exploiting its regular structure as demonstrated in 1(b), with dashed line representing extra edges, for a 5 × 5 array shown in Figure 1(a).
Relationship: contrasting
Domain: Hardware
Sentence 1: Even through self-heating of wires plays a very important role in the electro-migration lifetime of the metal wires [1], during the placement stage, we do not have the exact infor­mation about the location of the wires and we will ignore the self-heating of the wires at this stage.
Sentence 2: it is potentially possible to take this into account during a later stage of placement using the congestion information, though this is beyond the scope of our work.
Relationship: contrasting
Domain: Hardware
Sentence 1: Figure 4(b) shows the tree topology generated by MMM­3D.Notethat s1 is merged with s3 and then with s2 be­cause s3 is physically much closer than s2.As a result, two unstable TSV-bu.ers shall be inserted, which then causes propagation delay imbalances on both of the two subtrees, thereby allocating two normal bu.ers, one between x2 and s3 and the other between x3 and s4.
Sentence 2: if the sinks partitioned by die layers, and then partitioned by (x,y)-coordinates, the resulting tree topology needs one TSV, as shown in Figure 4(c).
Relationship: contrasting
Domain: Hardware
Sentence 1: Without on-chip inductance, the voltage .uctuations are almost the same even though Trvaries.
Sentence 2: figure 5 shows that the voltage .uctuation with on-chip induc­tance changes and the peak values are 5.6mV, 10.3mV, and 16.4mV, which are almost in inverse proportion to Tr2.
Relationship: contrasting
Domain: Hardware
Sentence 1: the Mitsubishi announcements [16] and the IRAM initiative of U.C.Berkeley [17]).
Sentence 2: these solutions provide a one­time drop after which the widening energy-delay gap be­tween the storage and the logic will keep on progressing, due to the unavoidable evolution of the interconnect contri­butions relative to the arithmetic and control logic.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this way, our solution provides a low­cost,high-coverage solutionfor soft errorsin embedded microproces­sors targeted for the consumer electronics market.
Sentence 2: unlike the high-availability IBM and HP servers that can provide provable guarantees oncoverage,thisworkprovides only opportunistic cover­age, andistherefore not suitablefor mission-critical applications.The contributions of this work are asfollows: A software solution which does not need any user annotations in the application to generate reliability-aware code and works on applications writtenin a variety oflanguages.
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