sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: With a data structure representing a reverse time vector clock1, and using pointers to actually link nodes rather than simply keeping timestamps, the time complexity for applying rule R7 to each store S in the graph is now O(k) instead of O(n+e)where k is the total number of processors, n is the number of nodes, and e is the number of edges.
Sentence 2: in the TSO memory model, program order does not imply memory order since a load can overtake its preceding stores.
Relationship: contrasting
Domain: Hardware
Sentence 1: Copyright 2009 ACM 978-1-60558-522-2/09/05...$5.00.
Sentence 2: zhi-Wei Chen Institute of Engineering and Science, Chung-Hua University, Hsinchu, Taiwan, R. O. C. several researches[7] consider redundant via insertion for yield improvement in the post-routing stage.
Relationship: contrasting
Domain: Hardware
Sentence 1: Allofthe modi.cationstotheCDPprotocol(Figure7) improveor maintain performance acrossmostbenchmarks.
Sentence 2: the1-2.ipoptimizationsometimes slightlydegradesper­formance, asit may holdbacksomeloadslongerthannec­essary.the 0-1and 1-2 optimizationsinteractin a favorable way.
Relationship: contrasting
Domain: Hardware
Sentence 1: One such sensor only sent a message when motion started or ended, so when a message was lost, there would be an inde.­nitely long period of misbehavior due to the incorrect motion state, and lack of access to raw motion events inhibited our ability to verify ground truth occupancy.
Sentence 2: .NET Gadgeteer can be used to build custom devices for the home, without HomeOS.
Relationship: contrasting
Domain: Hardware
Sentence 1: INTRODUCTION The demands of modern power electronics converters for high power, high density and high efficiency have raised opportunities for the new high speed, wide bandgap power semiconductor devices such as silicon carbide (SiC) MOSFETs [1]-[4].
Sentence 2: the problem accompanying the faster switching speed is the more severe high-frequency ringing in the switching transients, due to the influence of the circuit parasitic impedances.
Relationship: contrasting
Domain: Hardware
Sentence 1: The increase in the tra.c load prevents the sensor-wise policy to employ VCs di.erent from the most degraded one to steer new pack­ets, since we have an high probability that all the VCs are busy at the same time.
Sentence 2: the rr-no-sensor approach is independent of this aspect, since new packets are assigned to VCs in a round-robin fashion.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, when the compaction ratio is about 30 in Table 4, we find that the compactor with column weights five or seven is better than the compactor with weight three.
Sentence 2: when we performed the above experiment on D3, for which the percentage of unknown values is much higher than for D1, we found that the compactor with column weight three is better than the compactor with weight seven when the compaction ratio is near 30.
Relationship: contrasting
Domain: Hardware
Sentence 1: Statistically, holding 50% of the time values inverted would produce 50% degradation for each PMOS in the bit cell [1][4].
Sentence 2: operating in inverted mode 50% of the time may be expensive in terms of delay because a XNOR gate must be introduced in the read/write data paths to invert/deinvert data when operating in inverted mode [12].
Relationship: contrasting
Domain: Hardware
Sentence 1: It is because FV ratios are not increased much with shorter frequent values.
Sentence 2: the number of data blocks in a PRAM memory line is increased and more bits are used to store the encoded bit, as we discuss in subsection III-C. On the contrary, for applications with low frequent-value locality, the highest improvement of lifetime happens when we use 64Bit or 32Bit as the FV length.
Relationship: contrasting
Domain: Hardware
Sentence 1: The REFSM presents a very simple state transition graph (STG); it is composed of a unique state and n transi­tions, one for the slice of code executed when reset=1, and one for each alternative of the case statement (e.g., Figure 2 (a) shows the REFSM corresponding to the sequential cir­cuits described by the code of Figure 1).
Sentence 2: it has been shown that a REFSM can be di.culty traversed, be­cause of the presence of conditional statements on its up­date functions.
Relationship: contrasting
Domain: Hardware
Sentence 1: While the contribution of data movement with the 40 MHz interface keeps growing as the slab size increases, with a 1333MHz bus clock, data movement for all RRAM systems accounts for a small fraction of the total execution (under 20%).
Sentence 2: while an RRAM with 40MHz de­votes only 20% of the total I/O time to handling memory operations, an RRAM employing 1333 MHz spends most of its time in handling the memory operations, irrespective of the slab size employed, which in turn allows the RRAM to exhibit true resistive switch performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: However, mod­ern technology scaling has led to multiple CPUs on a single chip and very fast and e.cient busses, which makes snoopy­based hardware coherence the primary means for providing cache coherence in modern microprocessors.
Sentence 2: be­cause data are not written to the instruction cache in Har­vard architectures, and because instruction writes are not as common as data writes, snoopy-based coherence for in­structions is still not e.cient for instruction caches.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the system already has built-in security mechanisms, then the external monitoring of security requirements adds yet another layer of security checking which is independent from the system and therefore makes it more fault tolerant [5], especially if it is possible to control the system when violations are detected.
Sentence 2: even in cases where control cannot be applied, our approach can help by providing the basis for detecting more violations than the system itself, logging violations, and using the sophisticated reasoning capabilities of the monitor to analyse specific dynamic event patterns, e.g., for cases like denial of service attacks.
Relationship: contrasting
Domain: Hardware
Sentence 1: A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level Norbert Fr¨ohlich and Volker Gl¨ockel and Josef Fleischmann Institute of Electronic Design Automation Technical University of Munich 80333 Munich, Germany   Norbert.Froehlich,Volker.Gloeckel,Josef.Fleischmann}@ei.tum.de Abstract Simulation is still one of the most important subtasks when designing a VLSI circuit.
Sentence 2: more and more el­ements on a chip increase simulation runtimes.
Relationship: contrasting
Domain: Hardware
Sentence 1: As such, these algorithms are able to opportunistically com-bine results from different Route Discoveries and from other routing information learned from packets forwarded or overhead, in order to more often find the shortest route that exists.
Sentence 2: the many unused links that these algorithms can keep in the cache also at times are a liability; many of these links may be broken, increasing the number of packets that must be salvaged multiple times, and thus increasing the total hop count for salvaged packets that are ultimately successfully delivered.
Relationship: contrasting
Domain: Hardware
Sentence 1: REDUCING TMR OVERHEADS BY COMBINING HARDWARE AND TIME REDUNDANCY The TMR technique is a suitable solution for FPGAs because it provides a full hardware redundancy, including the user s combinational and sequential logic, the routing, and the I/O pads.
Sentence 2: it comes with some penalties because of its full hardware redundancy, such as area, I/O pad limitations and power dissipation.
Relationship: contrasting
Domain: Hardware
Sentence 1: Using those plots, empirical formulas for optimized values of repeater size and interconnect length were obtained using curve-.tting.
Sentence 2: their delay formula is valid only for 50% delay and is applicable only if the ratio of total line capacitance to load ( ) capacitance ch and the ratio of source resistance to total line resistance c0k ( ) rs are between 0 and 1. krh We now present a new approach of optimizing repeater sizes and inter­connect lengths which does not suffer from the limitations of the approach of [22, 21].
Relationship: contrasting
Domain: Hardware
Sentence 1: The Annotations Table associates each tran­sition with a guarded command, of the form guard -> action_list, which indicates the message that triggers the transition and the ef­ 3For an early proof-of-concept study, we used a design of the dat­ing service that abstracted the process whereby a caller selects a matching caller by a function that simply returns a reference to an arbitrary caller [13].
Sentence 2: this simpli.cation is unrealistic and, in eliminating a crucial autonomous role and thus a major source of asynchrony, also signi.cantly reduces the complexity of both the service logic and the required synchronization.
Relationship: contrasting
Domain: Hardware
Sentence 1: Previous results from bitstream fault injection [6] and radiation ground testing presented in [7] showed that the use of TMR in Virtex FPGAs has confirmed the efficacy of the TMR structure combined with scrubbing to recover upsets in the FPGA architecture.
Sentence 2: the TMR technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a meaningful increase in power dissipation.
Relationship: contrasting
Domain: Hardware
Sentence 1: CONCLUSION Recently, optically recon.gurable gate arrays (ORGAs) have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs.
Sentence 2: conventional ORGAs have no programmable capability after fabrication because, to reprogram ORGAs, the holographic memory must be disassem­bled from its ORGA package, reprogrammed outside of the ORGA package using a holographic memory writer, and implemented onto the ORGA package with high precision that is beyond the level of manual assembly.
Relationship: contrasting
Domain: Hardware
Sentence 1: In [31] [34] Smolyak s algorithm produces nested sparse grids because all random parameters are assumed uniformly distributed (and thus Clenshaw-Curtis rule is used for all .... s).
Sentence 2: smolyak s algorithm generates non­nested sparse grids when non-nested 1-D quadrature points are used for some parameters (since many random parameters with non-uniform distributions may not be effectively handled by the Clenshaw-Curtis rule).
Relationship: contrasting
Domain: Hardware
Sentence 1: As we pointed out in the introduction, the issue with RTO -0.6 -0.8 0 0.02 0.04 0.06 0.08Average loss event rat 0.1 0.12 0.14 e (ptfrc) Figure 15: The loss event rate di.erence ratio of TFRC and TCP in the same experiments as in Fig­ure 14. ratios are much higher than those predicted in Figure 13, especially under a low loss event rate region for the 10 ms network, and under a high loss event rate region for the 500 ms networks.
Sentence 2: simulation runs over the other de­lay networks tend to show less throughput di.erence ratios than the predicted.
Relationship: contrasting
Domain: Hardware
Sentence 1: Inthisexample,CSTG4andCSTG5cannotbemergedto­getherbecauseinputsofthemergedclusterwillexceed3.
Sentence 2: (B)Slack-time(ST)relaxation.Ifapproach(A)fails, STrelaxationisthenextapproachtotry.Thisapproach attemptstoformareducedclusterRCSTG4asaseparate newPLA.RCSTG4isthesubclusterofCSTG4thatexcludes anysharednodeswithotherclusters.Inourcase,RCSTG4 onlycontainsonenode,G4.BecauseRCSTG4issmaller thanCSTG4,itmaybefurtherpackedwithotherclusters later.severalstrictcriterianeedtobeveri.ed.
Relationship: contrasting
Domain: Hardware
Sentence 1: Interestinglyenough,althoughitwasexpectedthatall programswouldimprovetheirperformancewhengoingfrom 4-wayissueto8-wayissue,arc2dshowsthatthisisnotal­waysthecase.Aswewillseeinsection3.4,thisperformance lossismostlyduetotheinteractionoflargestrideswiththe longerlinesizeoftheSS-8architecture.
Sentence 2: 3.4 Performance Breakdown by Regions Theresultsjustshowninsection3.3indicatethatthe SSVarchitectureseemstobeamorecostefectiveoptionto executenumericalandmultimediaworkloads.itis clearthatthevectorunitonlyhelpsspeedingupthosepor­tionsofanapplicationthatcanindeedbevectorizedand doesnothingforscalarregionsoftheapplication.There-fore,wewouldliketobeabletopresentseparateEIPCre­sultsforthevectorandthescalarregionsofeachprogram.
Relationship: contrasting
Domain: Hardware
Sentence 1: The probability approaches 1 very quickly for radix-64 router which explains the poor performance of high­radix routers for the greedy algorithm using 1-.it pack­ets.
Sentence 2: the probability gradually approaches 1 for radix-8 router, With a packet size of 8-.its in a radix­64 router, the probability is reduced and behaves very similar to a radix-8 router with 1-.it packets.
Relationship: contrasting
Domain: Hardware
Sentence 1: In the example shown in Figure 1(a), if l5 is scheduled to time 6 and l4 is schedule to time 7, leakage waste is completely eliminated, but the re­sulting placement is not feasible due to the single recon.gu­ration limitation.
Sentence 2: one can observe that if we could delay the execution of v4 to time 11, l4 and l5 could be sched­uled to occur right before v4 and v5.
Relationship: contrasting
Domain: Hardware
Sentence 1: Without upsizing, and without guidelines for CNT process improvements, ........ can reach 80% for the OpenSparc T2 core modules, assuming current state-of-the-art processing parameter values: ...... = 0.50, ..m = 1%, ..R = 5%.
Sentence 2: ........ can be reduced to less than 1% with processing parameter improvement and minimal upsizing (.... = 5%), as shown via trial-and-error (Table 7).
Relationship: contrasting
Domain: Hardware
Sentence 1: They modified the ISA of processors and used special instructions to support the fine-grained synchronization.
Sentence 2: this method is not feasi-ble in the scope of blade enclosure: 1. each blade runs in separat-ed OS domain, while previous work is done for full-system shared memory machine; 2. commercial processor (such as X86 proces-sors) cannot work with the customized memory system, a custom-ized processor with special instruction set architecture (ISA) must be developed.
Relationship: contrasting
Domain: Hardware
Sentence 1: Similarly, the stress condition for the region GS of TR3 is VG = VIN 3 =1 and VS = VPN 2 =0.The condition VS = VPN 2 =0 results that VIN1 =1, and ( VIN 3 , VIN 4 )=(0,0),(0,1), or (1,1).
Sentence 2: the derived vectors ( VIN1 , VIN 3 , VIN 4 )=(1,0,0) and (1,0,1) have VIN 3 =0 that conflicts the generated condition VIN 3 =1.
Relationship: contrasting
Domain: Hardware
Sentence 1: Bench BC PC-2 PC-3 mark max avg max avg max avg ami33 41.6 24.0 5.6 1.8 5.0 1.8 ami49 19.0 6.3 3.3 0.8 5.8 1.4 n100 44.8 33.9 28.9 18.9 32.0 20.6 n200 46.1 34.3 25.0 16.8 27.2 17.9 n300 14.5 10.0 6.4 3.6 21.7 13.4  Several interesting points can be observed from the result: BC-bundling has an obvious speedup over the conven­tional estimation method, especially when the interconnec­tions scale up.
Sentence 2: its huge error (41.6% maximal and 24.0% average for ami33 ) results in a much longer wire length.
Relationship: contrasting
Domain: Hardware
Sentence 1: As they are aimed to implement many di.erent designs, a large number of routing switches is used in order to obtain .exible inter­connections, and look-up tables (LUTs) are used for logic, as they are capable of implementing any logic function for the given number of inputs.
Sentence 2: this type of archi­tecture prevents optimized design implementations because Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: contrasting
Domain: Hardware
Sentence 1: Therefore, the mean current of both types and no m-CNT removal, a mean delay reduction of nearly 30% of CNTs after etching are: can be observed by simulation.
Sentence 2: this mean delay benefit cannot be utilized in a practical design because m-CNTs µ ( I 8 I (x)[1- e (x)] fsd (x)dx (3.5) 0 .
Relationship: contrasting
Domain: Hardware
Sentence 1: These large overheads for providing an afterward on-demand 100% signal Design: Percentage of dumped signals(%) Simulation time (sec) 0 % (No dump) 322 AES10 10 % 662 20 % 884 40 % 1,335 80 % 2,233 100 % (full dump) 2,687 In the other experiment, we measured the size of the simulation state checkpoint file and the dump visibility can be hardly justified even if high overhead for a real SOC industrial design, containing visibility is absolutely required.
Sentence 2: if support about 18M gates.
Relationship: contrasting
Domain: Hardware
Sentence 1: We attempted to use several commercially available formal verification tools and found that they can generate some impressive results for a designer interested in verifying a single circuit.
Sentence 2: to avoid the vast number of false errors, the user is required to either restrict the operation of synthesis to verification safe operations (similar to forbidding compiler optimizations and instruction re-ordering to ensure ease of debugging in a software debugger), or annotate the netlist with many properties of the synthesis operations.
Relationship: contrasting
Domain: Hardware
Sentence 1: State-based Steganography in Low Bit Rate Speech Ke Zhou and Jin Liu School of Computer, Wuhan National Laboratory for Optoelectronics Huazhong University of Science and Technology Wuhan, 430074, China raidkick@263.net, geneleocn@gmail.com  Hui Tian College of Computer Science and Technology National Huaqiao University Xiamen 361021, China cshtian@gmail.com Chunhua Li * School of Computer, Wuhan National Laboratory for Optoelectronics Huazhong University of Science and Technology Wuhan, 430074, China li.chunhua@hust.edu.cn  ABSTRACT Commonleast signi.cantbit(LSB) relevant steganography methods in speech frames often base on bits evaluation by certainspeechquality evaluationcriterion and togetherwith some coding and embedding strategies to enhanceimpercep­tibility and e.ciency.
Sentence 2: some embedding capabili­ties and security strategy are neglected.
Relationship: contrasting
Domain: Hardware
Sentence 1: Our approach is to extend hardware reloaded TLBs with a prefetching1 scheme based on a novel heuristic.
Sentence 2: before 0 100 200 300 400 execution time (seconds) Using the stack algorithm we can determine the miss rates of describing the prefetching technique, we provide, in the next section, a background into the kind of history information our hardware heuristic algorithms exploit.
Relationship: contrasting
Domain: Hardware
Sentence 1: The threshold voltage characterization process, discussed above, is quite slow because the threshold voltage of each device must be measured and extracted individually.
Sentence 2: we can speed up the VT scatter characterization by exploiting the fact that the drain current (IDS) of a device is a function of voltage overdrive (VGS  VT) and not of gate-to-source voltage (VGS) and threshold voltage (VT) separately.
Relationship: contrasting
Domain: Hardware
Sentence 1: A data owner wants the sensitive data to be accessed and used by authorized users according to the data s as­sociated security policy.
Sentence 2: authorized users or ap­plications can maliciously or inadvertently compromise the con.dentiality of the protected data by distributing (or leak-  Secondary Recipients DataSafe Encrypted Data Plaintext Data Transformed Data Authorized  Not Authorized Data Owner Network/Disk port  Authorized inter-machine Non-DataSafe secure transfer Authorized Machine Primary Recipient Not Authorized Figure 1: DataSafe architecture protects data con­.dentiality across machines (new and legacy) and users (authorized and not authorized).
Relationship: contrasting
Domain: Hardware
Sentence 1: However, the increase in Hi-ECC s dynamic power pushes its total power to 58% of SECDED s total power.
Sentence 2: using a 512-entry RALT (HER) decreases the number of 1KB line accesses significantly, and the total power for Hi-ECC with RALT becomes 39% of the total power of SECDED (including the extra power due to RALT accesses).
Relationship: contrasting
Domain: Hardware
Sentence 1: Several works have achieved better resilience by weakening the model in di.erent ways by adding syn­chrony [4]; by storing signed self-verifying data [24, 25]; or by assuming that processes never fail and providing solutions that may block inde.nitely if they do fail [3, 25].
Sentence 2: t < n/4 is the best resilience achieved thus far for wait-free constructions in the model considered herein.
Relationship: contrasting
Domain: Hardware
Sentence 1: We would simply .nd which hyperplane is the one that achieves the measured delay for the given process setting and silicon errors.
Sentence 2: for a chip such as our sample (C)(C) chip C, the particular process point X(C) =(X,...,Xp )is 1 typically not known, and of course neither are any of the error terms ei,ki ,1 = i = n,1 = ki = qi.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, when the snapshot interval is increased from 10 cycles to 50 and a 100 cycles, we observe an increase in the simulation speed of bitcomp tra.c by a factor of 3 and 7, respectively.
Sentence 2: as explained in Section 5.2, a larger snapshot interval reduces the observability of in-.ight packets and the ability to reconstruct their paths.
Relationship: contrasting
Domain: Hardware
Sentence 1: Veri.able Resource Accounting for Cloud Computing Services Vyas SekarPetros Maniatis Intel Labs Intel Labs ABSTRACT Cloud computing offers users the potential to reduce operating and capital expenses by leveraging the amortization bene.ts offered by large, managed infrastructures.
Sentence 2: the black-box and dy­namic nature of the cloud infrastructure makes it dif.cult for them to reason about the expenses that their applications incur.
Relationship: contrasting
Domain: Hardware
Sentence 1: in [17] show that worst-case timing degradation occurs when critical paths experience a long DC BTI stress (i.e., transistors are always under BTI stress).
Sentence 2: assuming a DC BTI stress may be too pessimistic: a typical CMOS circuit usually switches during operation, and exhibits an AC BTI stress (i.e., transistors experience alternate BTI stress and recovery phrases).
Relationship: contrasting
Domain: Hardware
Sentence 1: Basically, the balance of wire congestion at a via is contained by the local gain of the via.
Sentence 2: .F (v2)and .F (v7)are also countedin gM (v6)since .F (v2)and .F (v7) are changed by M but v2 and v7 are not contained by M. The via assignment V around v6 and that obtained by applying M are shown in Fig.
Relationship: contrasting
Domain: Hardware
Sentence 1: Together, these works set out a number of ideas for device architecture, .oorplanning, and place-and-route.
Sentence 2: a number of technical gaps still exist, ranging from clock and power *Work partially supported by Cadence Design Systems, Inc., the California MICRO program, the MARCO Gigascale Silicon Research Center, NSF MIP-9987678 and the Semiconductor Research Corporation.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this scenario, substantial energy gains can be achieved when multiple cores execute the same phases of an application (e.g., conditioning in Figure 1) on multiple acquired inputs, as demonstrated by the authors of [11] and [8].
Sentence 2: these synchronization approaches do not provide the nec­essary .exibility to perform parallel processing of streams on multiple cores, while also supporting producer-consumer relationships among cores.
Relationship: contrasting
Domain: Hardware
Sentence 1: (8) Compute impulse response h(t) in (6) with residues ark m = f and poles br.
Sentence 2: j=1 Clearly, one needs to .nd an e.cient mapping between pa- the k-th order moments of random rameter space and performance space to obtain the stochas­ variable x can be written as: tic circuit behavior.
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