sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: This suggests that BLE is more suscep­tible to bursty packet loss, in which case BLE requires a larger window, or human wait time, for the proximity detection to be re­liable in the grey zone.
Sentence 2: inside the white zone, BLE has a smaller con.dence interval than 802.15.4, possibly because BLE employs forward error correction rather than error detection.
Relationship: contrasting
Domain: Hardware
Sentence 1: 2) The SECDED BFP model: as in DRM BFP model, the parity in SECDED changes in the presence of an odd number of bit .ips in a memory write.
Sentence 2: the model of SECDED is more complex because, in a non-standard Hamming Code, the quantity qp(·) of bits covered by a parity bit varies.
Relationship: contrasting
Domain: Hardware
Sentence 1: In line with our CEP approach, current trends require BAM to extend processing functionality and call for a tighter alignment of BPM and CEP in business process analytics: There is (1) the drive to provide richer types of observation which necessitates more event processing functions such as event pattern detection and (2) the need to provide more online observations when data comes from multiple event sources [5].
Sentence 2: even when this information is retrieved, business processes remain static and cannot be changed dynamically to adapt to the actual scenario [8] and therefore require guidance for translating insight into action.
Relationship: contrasting
Domain: Hardware
Sentence 1: By comparing greedy and greedy-return methods, Figures 7 and 8 show that when the divergence degree is low, such as with a di­vergence degree of 8, the greedy-return method can usually provide better performance.
Sentence 2: with increase in divergence degree, the greedy-return method may introduce additional overheads by excessively scheduling the threads in the return branch.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, for the 5-port router, if its frequency is set to be 1.5GHz, then only the four-stage pipeline with a peak frequency of 1.78GHz can be fast enough.
Sentence 2: if we reduce the router frequency to 1.0GHz, then both four-stage pipeline and three-stage pipeline can meet the frequency demand, but we will choose three-stage pipeline to maximize the router performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4.2.3 Hiding Decryption Latency Overheads We have discussed what criteria can be used to predict a page as inert and encrypt it, and what criteria can be used to decrypt it.
Sentence 2: with the decryption threshold, for each page that is predicted inert and encrypted, there are  2500 lbm 2000 1500 1000 500 0 0 5000 10000 15000 20000 25000 30000 35000 (a) 25000 sphinx 20000 15000 10000 5000 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 (b) Figure 5: Distribution of accesses to previously en­crypted (inert) pages.
Relationship: contrasting
Domain: Hardware
Sentence 1: As can be seen, depending on the stress temperature, NBTI can result in an fMAX degradation of up to 8.8% in 3 years (at 125°C).
Sentence 2: as the operating temperature is lowered down to 25°C, the degradation process significantly slows down [3,20] and results in only 3.3% reduction of fMAX.
Relationship: contrasting
Domain: Hardware
Sentence 1: The comparator of Figure 3(b) is energy efficient as long as the 8 bit segments are random, since mismatches dominate in all four blocks.
Sentence 2: it may not be energy efficient in the case when some of the 8 bit blocks match often, as some of the DMCs will frequently detect a match and dissipate energy even when the complete arguments do not match.
Relationship: contrasting
Domain: Hardware
Sentence 1: Indeed, if everyfunctionalunit was contin­uously utilized throughout the lifetime of theprogram, such instruction duplication would amount to an IPC reduction of at least 50%.
Sentence 2: due to the intelligent and e.cient implementation of our system, the duplicated instructions are able to dynamically recuperate idle hardware resources and achieve improved overall IPC while doing double the number of computations.
Relationship: contrasting
Domain: Hardware
Sentence 1: APPLICATIONS ManyproblemsinCADforVLSIanbeformulated toSSPproblemwhenvariationsbeomeaonern.We willherebriefydisussitsappliationstomazerouting, timinganalysisandbuferinsertionunderparameter variations.
Sentence 2: 5.1 Maze Routing Mazeroutingistofndtheshortestpathwithmin­imumlengthinagridroutingproblem.Traditionally, edgeweightsareassignedasreal-valuednumberbyost funtion.parametervariationsmakeitne­essarytomodeltheedgeweightsasrandomvariables.
Relationship: contrasting
Domain: Hardware
Sentence 1: The micro-controller s mini OS maintains a Frames in the FPGA which are currently not used to realize any logic and are thus potentially programmable without any inter­vention to the functions currently being executed, called the Free Frame List.
Sentence 2: if the Free Frame list is insuf.cient for the logic that the new algorithm s function is to realize, or is empty, some functions from the FPGA have to be erased so as to accommodate the logic necessary for the functions of the new algorithm whose execution has been requested by the host PC.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the temperature exceeds T_activation + 5 °C, however, clock gating is initiated regardless of whether the lowest frequency and voltage have been reached.
Sentence 2: if the thermal control system has an idea of the maxi­mum frequency that can be set without crossing the higher thermal thresholds, these severe performance penalties (e.g., clock gating) can be avoided altogether.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the pipeline ends up stalling upon an L2 miss, the power of the unused circuits would be reduced already by clock gating, reducing VSV s opportunity.
Sentence 2: vSV has at least two advantages over clock gating: (1) clock gating cannot reduce power of used circuits while VSV can, and (2) clock gating cannot gate all unused circuits if the clock gate signal s timing is too tight [10].
Relationship: contrasting
Domain: Hardware
Sentence 1: This formulation guarantees that the algorithm will return a 1University of Toronto, ECE Department, Toronto, ON M5S 3G4 ({briank, veneris}@eecg.toronto.edu) 2University of Toronto, CS Department, Toronto, ON M5S 3G4 superset of the error locations that would have been found in the concrete model.
Sentence 2: the need for a high error cardinality for the method to work inevitably has a direct impact on its performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: Subsequently, if the travel/arrivaltime is critical,theVehicle-to-Vehicle(V2V) networksshouldprovideadvise/guidancetothe mobileunits regarding possible re-routings.
Sentence 2: in order for this to happen, the interest for the particular query needs to be disseminated in a manner that will ensure that the entities that could provide the answer are aware of it.
Relationship: contrasting
Domain: Hardware
Sentence 1: By comparing the input signal with fan-out point waveform, we can get the values of delay and signal slew over the whole circuit, as illustrated in Figure 1.
Sentence 2: based on most ofthe proposed gate models, the fan-out point waveform can not be deduced directly from the gate input signal since the gate model is not apriori.In the gate interconnect gate (sink) input signal  driving point fan-out point Figure 1: A gate drives its interconnects and re­ceivers (sinks).
Relationship: contrasting
Domain: Hardware
Sentence 1: Furthermore, a research of social scientists confirmed the importance of the SNs in provisioning of social support among community members [52], in structuring unrests and other political conflicts [43], in analysis of the immigration processes [40], as well as in studying internal processes within companies [30].
Sentence 2: in the beginning of 2000s SNs experienced a proliferation grounded on an advent of ICT-enabled SNSs.
Relationship: contrasting
Domain: Hardware
Sentence 1: Implementation of an Embedded Sensor Network for the Coordination of Slocum Gliders for Coastal Monitoring and Observation * Ryan N. Smith Jnaneshwar Das Hordur Heidarsson Robotic Embedded Systems Robotic Embedded Systems Robotic Embedded Systems Laboratory, USC Laboratory, USC Laboratory, USC ryannsmi@usc.edu jnaneshd@usc.edu heidarss@usc.edu  Arvind Pereira Gaurav S. Sukhatme Robotic Embedded Systems Robotic Embedded Systems Laboratory, USC Laboratory, USC menezesp@usc.edu gaurav@usc.edu ABSTRACT Autonomous Underwater Vehicles (AUVs) are revolutioniz­ing oceanography through their versatility, autonomy and endurance.
Sentence 2: they are still an underutilized tech­nology.
Relationship: contrasting
Domain: Hardware
Sentence 1: Constraint relaxation essen­tially re.nes optimization steps at the expense of slower con­vergence.
Sentence 2: after a certain point, increasing constraint factor would only slow down optimization at very little decap  Sensitivity (VxS/F) Sensitivity Change Versus Decoupling Capacitor Values x 10-5 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 Decoupling Capacitor Values (F) x 10-7 As for optimization ef.ciency, QP [17, 19] has a higher complexity and slower convergence rate than LP.
Relationship: contrasting
Domain: Hardware
Sentence 1: On one hand, it showed that the even 25% latency penalty over delay optimized repeaters, which saved 80% of repeater power, was very less compared to non-repeated wires.
Sentence 2: it pointed to about 8 times clock period latency even with delay optimized repeaters at 35 nm, leading to a possibility of further power dissipation due to deeper pipelining.
Relationship: contrasting
Domain: Hardware
Sentence 1: Wirelength minimization can be considered an indirect way to reduce routing congestion as total wirelength is equal to totalrouting demand.
Sentence 2: a placement with small wirelength may be Permission to make digital or hard copies of all or part of this work for personalor classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: contrasting
Domain: Hardware
Sentence 1: The works in [2] and [4] motivate the approximation of the Max as a normal distribution, and apply the closed-form formula from [11] to approximate the mean, variance and covariance of the Max of two normal random variables.
Sentence 2: since we also require the Min as well, in STAC, we developed a PCA-based technique that can work for both Max and Min.
Relationship: contrasting
Domain: Hardware
Sentence 1: Theresults inFigure7demonstrate that when the Zhang-Zhang protocol is used, the overall system throughput canbenegatively a.ectedby anyofthesethreetypesof cheatingbehavior.
Sentence 2: whenourschemeisused to completely suppress cheating, the achieved through­put is always close to the above maximum throughput of Zhang-Zhang protocol, regardless of the number of cheating users.
Relationship: contrasting
Domain: Hardware
Sentence 1: 1.3 Our Solution If we want to immediately detect forking attacks and replay at­tacks whenever a critical operation needs to be performed, then one solution is to use a trusted third party that is always online, and that can be trusted to correctly maintain the clients dedicated counters.
Sentence 2: if we do not want to, or cannot, assume any trusted third parties, then this solution is not possible.
Relationship: contrasting
Domain: Hardware
Sentence 1: Other NVM candidates such as spin-torque-transfer magnetic random access memory (STT-MRAM) [10] and phase change memory (PCM) [11] can also be used.
Sentence 2: they have some undesirable features: the resistance of STT-MRAM is relatively low(afew kilo Ohm), and PCM has a well-known time-dependent resistance drift (even without voltage stress) problem.
Relationship: contrasting
Domain: Hardware
Sentence 1: The VCMESH, SMT, and DSR depend on solving variants of the Steiner Tree Problem which is well known to be NP-complete.
Sentence 2: both the spanning tree enumeration algorithm and the DSR formulation are able to exactly solve SMT and SHSR solutions on actual networks by: (1) limiting the initial search space with preprocessed routes equal to or below a hop-limit and (2) using branch-and-bound within each algorithm implementation to further narrow the search space.
Relationship: contrasting
Domain: Hardware
Sentence 1: The amount of change is quite small compared with the clock power saving.
Sentence 2: the input (respectively output) tim­ing slack of a .ip-.op is the maximum allowable wire delay between the .ip-.op and its fanin (respectively fanout) gate without timing violations; the wire delay bound can be ex­pressed as an e.ective wirelength1 bound as follows: 0 <Lfi(i) = Sfi(i), 0 <Lfo(i) = Sfo(i), .i, (4) where Sfi(i)(respectively Sfo(i)) is the input (respectively output) slack.
Relationship: contrasting
Domain: Hardware
Sentence 1: For the reception side, we sized the data VC based on the round-trip latency in order to allow uninterrupted commu­nications, ending up with 15-slot DC FIFOs.
Sentence 2: for the control VCs we decided to keep small 5-slot DC FIFOs because they can already .t two complete packets and we do not expect to send many back-to-back control packets with the target cache-coherence protocol.
Relationship: contrasting
Domain: Hardware
Sentence 1: On-Chip Characterization of Molecular Electronic Devices: The Design and Simulation of a Hybrid Circuit Based on Experimental Molecular Electronic Device Results Nadine Gergel-Hackett*, Garrett S. Rose , Peter Paliwoda , Christina A. Hacker*, and Curt A. Richter* *Semiconductor Electronics Division National Institute of Standards and Technology Gaithersburg, Maryland 20899 {nadinegh, christina.hacker,  curt.richter}@nist.gov ABSTRACT The focus of the .eld of molecular electronics primarily has been limited to the development of molecular electronic test devices and the characterization of electron transport through organic molecules.
Sentence 2: in order for molecu­lar electronic technology to be realized, it is probable that these devices will have to .rst be integrated with tradi­tional CMOS components and circuits.
Relationship: contrasting
Domain: Hardware
Sentence 1: [16] proposes another approach, taking the fact that the maximal delay of channel taps stays within the length of cyclic prefix (CP), so that the noise subspace and the channel subspace can be decoupled by IFFT.
Sentence 2: in the null­subcarrier modulated OFDM systems as CMMB, the reconstructed CIR has the energy leaked into the delay paths longer than the CP length [17].
Relationship: contrasting
Domain: Hardware
Sentence 1: 4NAND and 4NOR), because stacking and paralleling transistors worsen the balance of the strength of nMOS and pMOS and hence the logic threshold voltages deviate from half VDD.
Sentence 2: vDDmin(RAND) decreases as the number of inputs of the logic gates increases, because stacking and paralleling transistors decreases the transistor variations.
Relationship: contrasting
Domain: Hardware
Sentence 1: To reduce the performance overhead of error correction for permanent faults, we observe that if only one codeword in the checksum group contains a bad symbol (e.g., due to a symbol fault or a row fault), one can retire the page con­taining the bad symbol to prevent future expensive accesses to the same bad codeword.
Sentence 2: if multiple codewords in the checksum group contain errors (e.g., when a device develops a serious device-level fault such as a bank fault), simply retiring/disabling all pages with errors can signi.­cantly reduce the total usable memory capacity.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this Minimize S21IT 2 case, gradient-based optimization methods may fail to converge to the global minimum.
Sentence 2: if the .xed .lter design is used as Subject to S11IT =S11IC, S11OT =S11OC the start point for the optimization process, the tunable .lter opti- S22IT =S22IC, S22OT =S22OC mized using gradient-based techniques will converge to the optimal S21IT =S21IC, SPT =SPC solution.
Relationship: contrasting
Domain: Hardware
Sentence 1: For future work, it is very much worthwhile to use the NIOS C2H acceleration compiler and see how much it will impact the energy dissipation using NIOS IIe.
Sentence 2: to enrich our research with more information, it is important to involve other processors which come with their own embedded HW multiplier and other architecture rather than sufficing with a simple RISC processor.
Relationship: contrasting
Domain: Hardware
Sentence 1: In that sense, there is only one BOL repair corner.
Sentence 2: dual Supply Case- Multiple Repair Corners: in dual supply memory designs, different cells fail at different (Vdd, Vcs) combinations; so it is possible to obtain different candidate T0 BOL repair corners corresponding to different (Vdd, Vcs)T0 combinations that satisfy redundancy quota requirement.
Relationship: contrasting
Domain: Hardware
Sentence 1: In summary, the use of the functional memory inter­face allows a quick iteration cycle, since changes are car­ried out within minutes, and, due the high simulation per­formance, pro.ling results showing latency cycles, cache hit/miss rates, and bottlenecks in the memory architecture are quickly obtained.
Sentence 2: functional memory simulation is not appropri­ate to exploit parallelism, that is, parallel or pipelined mem-ory architectures.
Relationship: contrasting
Domain: Hardware
Sentence 1: The cache covers  HARDWARE manages this movement of data Address space includes only primary memory (and memory­mapped I/O) NON-TRANSPARENT addressing TRANSPARENT addressing EXPLICITLY MANAGED contents TRANSPARENTLY MANAGED contents Figure 1: Transparent caches versus tagless SRAMs.
Sentence 2: the addressing of tagless SRAMs makes them dif.cult to work with: Contiguity in the address space must be preserved, and distance between objects must be preserved.
Relationship: contrasting
Domain: Hardware
Sentence 1: This sug­ 300 250 200 150 A 100 B 50 C 0 Write Pulse Width (ns) Figure2: Write currentvs.writepulsewidthfordifferentMTJretentiontime gests that, inTAmode, shorter pulse width is bene.cial in reducing write latency and energy without hampering the read latency and energy.
Sentence 2: in PS mode, write current goes up rapidly as we reduce the write pulse width and minimum write energy of the MTJ can only be obtained at some particular write pulse width in this region, as shorter write pulse width with optimal write cur­rent can still provide necessary write energy to switch.
Relationship: contrasting
Domain: Hardware
Sentence 1: There are lots of other simulators aiming at large-scale system evaluation, typical examples include Graphite[9], Hornet[10], GEMS[12], GEM5[11], COTSon[13], etc.
Sentence 2: these simulators either do not use component-based method, losing high flexibility, or do not support parallelization, leading to very slow simulation speed.
Relationship: contrasting
Domain: Hardware
Sentence 1: Similarly, in MC2, the tag side of the cache (tag SRAM array, comparators, decoder and write demultiplexer) is connected to nominal Vdd.
Sentence 2: mC2 s the data side (data array, error detect/correct logic, decoder and write demultiplexer) is run on a separate Vdd that can be aggressively scaled down.
Relationship: contrasting
Domain: Hardware
Sentence 1: Our intention was to make this language as simple and comprehensible as possible, since the templates will be cre­ated and handled by the users of StressTest.
Sentence 2: in spite of the simplistic structure the template language we developed retains the ability to e.ciently describe di.erent sets of instruction sets, or, more generally, interface trans­actions, with varied interaction rules.
Relationship: contrasting
Domain: Hardware
Sentence 1: The ESD voltage ratio between the HBM and MM ESD robustness of CMOS IC products were around ~10 in the submicron (1.0 ~ 0.5 µ m) CMOS processes [12], [13].
Sentence 2: typically, a CMOS IC product, which has a HBM ESD robustness of 2 kV, can sustain a MM ESD robustness of 200 V. this ratio has been approached to about 15 ~ 20 in the deep-sub-micron fully-salicided CMOS processes [14].
Relationship: contrasting
Domain: Hardware
Sentence 1: The weight of arc from (P E (3, 2), a) to (P E(4, 2), d) should to be increased by 2 6 .
Sentence 2: the weight of arc from (P E(4, 2), d) to (P E(3, 2), a) is only increased by 1 because one register is to be released when d is executed.
Relationship: contrasting
Domain: Hardware
Sentence 1: f970801 f970701 80 100 80 60  percent different percent different 60 40 40 20 20 0 0 truncated bits truncated bits f960323 f970620 truncated bits truncated bits Figure4:DiferentclassifcationratesforAVIRISdatacubes.Theseshowresultsforthesamefourimages andthesame16experimentsperimageasthevariances.Apixelisclassifedasdiferentifitendsupina diferentclassthanthecaseof0bitstruncated,2extra BothexperimentsshowedthattheManhattanmetricis betterthantheMaxmetricfork-means.Inthedatadepen-dentexperimentwithAVIRISdata,wefoundthatclusters producedusingtheManhattandistancemetricwereslightly lesscompactthantheclustersproducedbytheEuclidean metric.Thetotalwithin-classvariance,fortheAVIRISdata cubeswemeasured,increasedfrom2%toslightlyover30% forManhattanvs.Euclideandistance,withmostofthe imagesexhibitinglessthana6%increase.
Sentence 2: 3.2 Input Data Truncation ImplementingtheManhattandistanceresultsinsignif­icantsavingsindatapatharea,andthusallowsformore parallelisminareconfgurableimplementation.giventhesizeofthedatasetbeinginvestigated,moredras­ticmeasureswereconsideredtofurtherreducethesizeof thecalculationofeachpixel.
Relationship: contrasting
Domain: Hardware
Sentence 1: Because traces are orthogonal in adjacent layers, traces in layer N+1 and layer N-1 will not affect the inductance of traces in the current layer N [7].
Sentence 2: there may be parallel traces or ground planes in layer N+2 and/or layer N-2 which can affect the inductance in layer N. We consider wide ground traces which can be treated as a local ground plane in layer N+2 and/or N-2.
Relationship: contrasting
Domain: Hardware
Sentence 1: Concatenative sound synthesis [5], musical mosaicing [10], or the audio query guided assemblage system [1] can be used to resynthe­ size an audio stream from parts of another, or to concatenate clips from an audio library according to a user-supplied list of audio events.
Sentence 2: these systems require complex user input and in general do not preserve macroscopic song structure.
Relationship: contrasting
Domain: Hardware
Sentence 1: Pages 5 and 8 are also the neighbors of Page 6, hence, we prefer buffering those pages in anticipation that Page 6 will also be read due to sequential access.
Sentence 2: when Page 5 is read between Pages 3 and 6, two more neighbor pages are added to the NAC­buffer (i.e., Pages 7 and 10).
Relationship: contrasting
Domain: Hardware
Sentence 1: By al­locating higher-order bits to more reliable segments power consumption can be signi.cantly reduced with an (almost) undetectable degradation of the video quality.
Sentence 2: they are still based on expensive SRAMs and lack .exibility since the segment con.guration, speci.ed by the number of seg­ments and their error rates, is .xed at design time.
Relationship: contrasting
Domain: Hardware
Sentence 1: Intuitively,animplementationonformstoaspeifation ifitansafelyreplaethespeifationinanypossibleen­vironment.Thatis,theimplementationmaynotfailunless thespeifationallowsafailureinthesameontext.Inor­dertohekthispropertydiretly,wewouldhavetoon­sidertheountlesspossibleenvironments,whihisimpossible.
Sentence 2: foruntimediruits,thespeifationitselfformsa "mostgeneralenvironment":theimplementationonformsto thespeifationiftheompositionofimplementationandthe mirrorofthespeifationisfailurefree.Weallthisprop­ Some text in this electronic article is rendered in Type 3 or bitmapped fonts, and may display poorly on screen in Adobe Acrobat v. 4.0 and later.
Relationship: contrasting