sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: .LCAV, ESL École Polytechnique Fédérale de Lausanne,Lausanne (Switzerland)name.surname@ep..ch ABSTRACT Chip designers place on-chip sensors to measure local tempera­tures, thus preventing thermal runaway situations in multicore pro­cessing architectures.
Sentence 2: thermal characterization is directly dependent on the number of placed sensors, which should be mini­mized, while guaranteeing full detection of all hot-spots and worst case temperature gradient.
Relationship: contrasting
Domain: Hardware
Sentence 1: As shown in this table, although the bus throughput of the CACHE-only model is almost the same as that of the SCIMA-SMP for 0-cycle latency, it greatly degrades as the latency increases.
Sentence 2: the SCIMA-SMP model is less in.uenced by latency because of the large gran­ularity of the data transfer.
Relationship: contrasting
Domain: Hardware
Sentence 1: Even though OPT1 results in higher junction BTBT leakage compared to low-Vt design, it saves more than 55% of total leakage.
Sentence 2: in 25nm technology, due to significant increase in junction BTBT, dual-Vt design using CONV results in negligible leakage saving, while OPT1 results in only 14% leakage saving (Figure 4c).
Relationship: contrasting
Domain: Hardware
Sentence 1: The same is true of the undershoot at t=25 ms. At t=40ms, the controller sets the heater current to 0, immediately dropping microhotplate power to 0.
Sentence 2: surface temperature follows a decaying expo­nential as it cools off, finally stabilizing at 30ºC, since that was set as the ambient room temperature in the simulation.
Relationship: contrasting
Domain: Hardware
Sentence 1: The high resolution of the ADC makes necessary to accumulate a high number of samples and then a long test time.
Sentence 2: a precise production test can help to validate the design of a high-performance ADC, reduce the number of wasted parts, and enable the calibration, so it is necessary to develop methods for accurately characterizing the specification of high­resolution and also high-speed ADCs.
Relationship: contrasting
Domain: Hardware
Sentence 1: INTRODUCTION TheadvancesintheInternetandwirelesscommunication makebattery-operateddevicesmuchmoreversatilethan ever.Ononehand,suchadvancesbringmoreandmore newandcomplexapplications(e.g.,multimedia,distributed computingandsimulation).Ontheotherhand,theyalso challengesomeofthetraditionalsystemdesignphilosophies.
Sentence 2: forexample,becauseofthelimitationofbatterylife,itis morerealistictodesignfortheoptimalbeneftfromlimited resources(suchasenergyandCPUtime)ratherthandesign tomeetalltheapplications'requirements.little workhasbeenreportedatthisendfromtheCADsociety.
Relationship: contrasting
Domain: Hardware
Sentence 1: Summary: Software level techniques alleviate or comple­ment hardware level techniques or are deployed when hard­ware redundancy is prohibitive.
Sentence 2: software-level reli­ability techniques do not ensure 100% correct execution and require hardware-level support, thus motivating the need for cross-layer reliability (see also Section 3.1) to provide a better tradeo.
Relationship: contrasting
Domain: Hardware
Sentence 1: For the purpose of evaluation and since we want to have a single ISA system, based on the availability of the data on the power, area, and other characteristics of microprocessors, we use an EV6 (DEC Alpha 21264 [20]) for the baseline cores.
Sentence 2: for the animator core, we select a simpler core like the EV4 (DEC Al­pha 21064) or EV5 (DEC Alpha 21164) to save on the overheads of adding this extra core to the CMP system.
Relationship: contrasting
Domain: Hardware
Sentence 1: This may be due to the fact that it operates on a sequence-pair formu­lation, in which a small perturbation may cause a module to be moved signi.cantly from its original position.
Sentence 2: fLOORIST achieves legality and 0% overlap on all in­stances, preserving the length of most individual wires (and thus global interconnect length) far better than the other legalizers while remaining competitive in runtime.
Relationship: contrasting
Domain: Hardware
Sentence 1: Of all the memory references made, those in the spike with recency 4000 (for 8KB pages) constitute around 0.5% -which we can read directly from the graph.
Sentence 2: if we consider only those accesses with a recency value greater than a modest TLB size (say 20 entries), we see that the spike at recency 4000 dominates the other accesses with a probability almost two orders of magnitude higher.
Relationship: contrasting
Domain: Hardware
Sentence 1: C for 108 seconds (~3 years) indicate that a Vth compensation of 0.2V can almost preserve the WRITE and HOLD stability of the fresh device even after 3 years, while for the READ stability the compensation mechanism is less effective.
Sentence 2: the READ Static Noise Margin (SNM) experiences an insigni.cant decrease over the 3 years time span in the presence of a Vth compensation, while without compensation it decreases by a x4 factor.
Relationship: contrasting
Domain: Hardware
Sentence 1: Within (12), de.ne f(t)= f ·(t +a(t)) to represent the phase of the VCO, which is only true if the VCO free-running frequency is a constant.
Sentence 2: if the VCO control voltage switches within {vci }, and the free-running frequency varies within {fi}, the phase of the VCO can be generalized to be T f.(t)= f (t)·v 1 (f0(t)+f(t))·bb(t).
Relationship: contrasting
Domain: Hardware
Sentence 1: (1) Here, D'is the newly updated page of D0.represents XOR 0 operation.
Sentence 2: if more than half of the pages in a stripe are updated together, the parity page is calculated differently: for example, assume the pages D0 ~ D2 are respectively updated to D0'~ D', new parity page D'is generated as: 2 p D' = D' D' D' D3.
Relationship: contrasting
Domain: Hardware
Sentence 1: Therefore, estimating the short-circuit current is important to design high-speed VLSI s. Much effort has been devoted for the extraction of accurate, analytical expressions for timing models of basic circuits.
Sentence 2: previous works in the short-circuit power estimation area have not entirely or exactly reflected gate-to-drain coupling capacitance and the short channel effect [2][3][4][5].
Relationship: contrasting
Domain: Hardware
Sentence 1: Analysis and Mitigation of Variability in Subthreshold Design Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester {bzhai, hansons, blaauw, dennis}@umich.edu, University of Michigan, Ann Arbor, MI ABSTRACT Subthreshold circuit design is a compelling method for ultra-low power applications.
Sentence 2: subthreshold designs show dramati­cally increased sensitivity to process variations due to the exponen­tial relationship of subthreshold drive current with Vth variation.
Relationship: contrasting
Domain: Hardware
Sentence 1: Here it is assumed that the threshold voltage of each transistor in the SRAM cell can be adjusted independent of other threshold voltages by changing the channel doping, which is deemed to be a safe assumption because in an SRAM cell the channels of the transistors are not too close to each other [14].
Sentence 2: in the Simulation Results Section it will be shown that even if only one threshold voltage is used inside the cell, power reduction can be considerable.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4.2 Race Conditions Most race conditions in our extended protocol can be han- dled in the same way other similar race conditions are handled in the baseline protocol without ReVive - by serializing accesses to the same memory line and sending negative acknowledgments to avoid deadlocks and livelocks.
Sentence 2: some race conditions are related to error recovery and need to be carefully considered.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since 0.043 seconds are required to perform one error cor­rection at level 2 recursion, it will take approximately 16 hours to complete the factorization of a 128 bit number.
Sentence 2: assuming success of all the gates, the circuit is re­peated on average 1.3 times [56], so the total time to factor a 128 bit number would be around 21 hours.
Relationship: contrasting
Domain: Hardware
Sentence 1: Althoughsymptom-baseddetectionisinexpensive,the amount of cov­erage that canbe obtainedfrom a symptom-only approachis typically limited.To address thislimitation, we make use of the second area of prior research, software-basedinstructionduplication[26,27].With this approach, instructions are duplicated and results are validated within a single thread of execution.This solutionhas the advantage of being purely software-based, requiring no specialized hardware, and can achieve coverage of more than 90%.
Sentence 2: the overheads in terms ofperformance andpower arequitehigh since alargefraction of the applicationis replicated.
Relationship: contrasting
Domain: Hardware
Sentence 1: (2) e.E vi,vj .e,i<j vi,vj .e,i<j The advantage of using the quadratic wirelength ob jective is that its unconstrained minimizer can be obtained by solving a positive de.nite linear system of equations.
Sentence 2: it over-penalizes the long nets which gives a bad half-perimeter wirelength placement solution.
Relationship: contrasting
Domain: Hardware
Sentence 1: As an example consider the expression E = ac + ad + bc+ bd,Using the brick p1 = a + b or p2 = c + d the number of gates can be reduced from 7 to 4 as discussed in the previous section.
Sentence 2: the introduction of brick p2 in presence of p1 reduces the number of gates only from 4 to 3.
Relationship: contrasting
Domain: Hardware
Sentence 1: Instead of one agent formulating test sequences for the multi-processor sys­tem based on coverage or collision metrics, we chose to create a set of simpler agents cooperating with each other.
Sentence 2: for simplicity reasons, agents don t have an understanding of the full system FSM and instead use a dichotomic .nite-state machine (DFSM) to represent their perspective of the proto­col and coverage.
Relationship: contrasting
Domain: Hardware
Sentence 1: While steep-slope devicesmay offer superior performance at suf.ciently low voltages,state-of-the-art CMOS FinFET technologies continue to offer 978-3-9815370-2-4/DATE14/&#38;#169;2014 EDAA superior peak performance on highly sequential, latency-boundcomputations.
Sentence 2: we shall show that, for tasks withthread or data parallelism, with .xed, real-time performancedemands, or with tight thermal constraints, adding steep-slopedevices to the chip designer s tool chest extends the rangeof realizable designs in fundamental ways.
Relationship: contrasting
Domain: Hardware
Sentence 1: The caller of a paused operation on an object can access this object again only by resuming the paused operation.
Sentence 2: with an abortable or query-abortable object, the caller of an aborted operation is not restricted in any way: it may reap­ply the same operation, but if applying a different operation on the object better suits its objectives, it is free to do so.
Relationship: contrasting
Domain: Hardware
Sentence 1: In [22], the typical clock frequency for a single pipeline stage in commercial microprocessor working in super-threshold regime lies in the range of 15~44 F04 delay, depending on specific design differ­ences.
Sentence 2: since microprocessors working in the subthreshold regime prefer shallow pipeline (more F04 delay in a single pipeline stage) to mitigate variability[23], higher F04 delay is observed in low voltage microprocessor, for instance ~400 F04 delay of a single pipeline stage from [9].
Relationship: contrasting
Domain: Hardware
Sentence 1: Of course, it is quite difficult to compensate precisely the effect of the non-linearities of the operational amplifiers, and therefore, the best solution is to integrate operational Vdd amplifiers with sufficient high DC gain and settling to make this phenomenon negligible.
Sentence 2: optimizing operational amplifiers for fast settling-time and high DC gain is a non­simple task, since both the aspects leads to contradictory demands: high-gain requirement leads to multistage designs, whereas the high unity-gain frequency requirement calls for a single-stage design.
Relationship: contrasting
Domain: Hardware
Sentence 1: Oneadvantageofcluster-basedlogicblocksisthatmanynets canberoutedlocallyinsideacluster,whichmakefasterinter­connectcomparedtogeneral-purposeinterconnectbetweenlogic blocks.Sincepartoftheinterconnectisinternallyrouted,less numberofnetsarelefttoberoutedamongtheclustersbythe router.
Sentence 2: iV.Routability SincemostofanFPGA'sareaanddelayisduetorouting,it isimportanttoconsidertheroutabilityofthedesigninearlier stages.Technologymapping,clusteringandplacementcanafect theroutability.Byperformingactualrouting,routabilitycould beincorporatedintoearlyCADstages.thisisavery slowprocess.Alsotheactualroutingcostisveryinsensitiveand thusisapoorcostfunction.Thereforeweconsiderroutabilityin earlystagesbyusingpredictorsofroutability.
Relationship: contrasting
Domain: Hardware
Sentence 1: But if the DFG contains a lot of highly concurrent equal operations with a distance of two, it is bene.cial to implement similar FUs, able to exe­cute that operation, in one FPGA.
Sentence 2: a lot of differ­ent non-concurrent operations on the critical path force the implementation of FUs, which can execute the different operations, in one FPGA.
Relationship: contrasting
Domain: Hardware
Sentence 1: If all we need is just a large number of particles, but with similar timescales, we can use Barnes-Hut tree algorithm or Fast Multipole method to reduce the calculation cost per timestep from O(N2) to O(N log N) or O(N).
Sentence 2: it is very di.cult to achieve high e.ciency with these algorithms when the timesteps of particles vary widely.
Relationship: contrasting
Domain: Hardware
Sentence 1: Computingker­nels, which contain statelessloops(such as vector addition) only, canbeimplemented as simplearithmetic modulesthat operatesonacontinuesdata .ow.
Sentence 2: itisstill need to maintain registers and loop counters for stateful loops with loop-carrieddependency(vector summation) and someini­tializationlogics(image .lters).
Relationship: contrasting
Domain: Hardware
Sentence 1: On one hand, gate delays of G and Gc in Figure 3(b) are both shorter than the delay of G in Figure 3(a) because of driving less load.
Sentence 2: denoting the delay of a gate G driving a total load of C (including the net capacitance and the pin capacitance of the fanout gates) as tG|Cload=C, the total delay decrease can be calculated as: dtG = tG - max{t , t } (3) Cload =CN G ' G Cload =CN CCload =CN C delays of driving gate G1 and G2 are increased because of the additional input capacitance of Gc.
Relationship: contrasting
Domain: Hardware
Sentence 1: Theirapproachusesanactualexecutiontraceasthestart­ingpointforsymbolicexecution.Theprogramtraceis systematicallyreplacedwithstatisticalparametersandthe efectsmeasured.Ourapproachissimilar,butusesanexe­cutionratherthantracedrivenmodel.Efortsarecurrently underwaytoreconcilethetwoapproaches.
Sentence 2: adiferentapproachtostatisticalperformancemodel­ingwasusedin[NS94].Aperformancemodelwascon­structedbasedontheinteractionsbetweenmachineand programparallelism.Thisworkextendedanearliermodel presentedin[Jou89].Withthesemodels,benchmarksare analyzedandperformanceisestimateddirectlybyappli­cationofaformularelatingprogramandmachineparal­lelism.Thissameresearchgroupcontinuedtheirstatis­ticalmodelingworkin[NS97].AsetofMarkovmodels wereconstructedtorepresentmachinebehaviorwhileex­ecutingaspecifcbenchmark.Thesemodelswherethen linkedtogetherandperformanceestimated.Thisapproach ismoreabstractthanthedirectsymbolicexecutionmethod presentedhere,andtheauthorsfocusonmoreidealma­chinemodels.extremelyaccurateperformance estimatesareachieved.
Relationship: contrasting
Domain: Hardware
Sentence 1: Among our benchmark programs, JESS and JACK have similar character- istics as Scheme programs in the sense that they have few frequently-referenced long-lived objects and that most ob-jects are allocated rather linearly and short-lived.
Sentence 2: when comparing the miss ratio curves of JESS and JACK to other Java applications in figure 3, we do not see any signif- icant benefit of direct-mapped caches in these applications.
Relationship: contrasting
Domain: Hardware
Sentence 1: When the speci.cation of the converter was given by an algorithm written in Verilog, we had a FPGA with 695 4­input LUTs and 70.7 ns delay for Xilinx Virtex XCV150-6 (260pin).
Sentence 2: when the speci.cation of the circuit was given by a BDD, and then each node of the BDD is replaced by a multiplexer, we had a FPGA with 1659 4­input LUTs and a 33.1 ns delay.
Relationship: contrasting
Domain: Hardware
Sentence 1: One can generate a similar diagram using transient simu­lation: the transient waveform for a long sequence of bits is simply shifted and overlaid.
Sentence 2: the need to analyze extremely low bit-error-rates for modern high-speed serial links makes transient simulation impractical; bit sequences of lengths in the trillions are needed to generate an eye dia­gram with su.cient probability resolution to accurately as­sess low BERs.
Relationship: contrasting
Domain: Hardware
Sentence 1: Resizing the paths which are sensitive to NBTI e.ect can reduce the e.ect of the path delay increase due to NBTI on the whole circuit.
Sentence 2: it will increase the area cost, reference [11] has demonstrates that delay degradation due to NBTI e.ect can be o.set using gate sizing (8.7% average circuit size increase).
Relationship: contrasting
Domain: Hardware
Sentence 1: This approach will not reduce the startup latency for the very first FAST message of an UDP packet, because the first lookup will still imply the three cycle penalty.
Sentence 2: as the decompressor can always process one field per cycle and is hence much faster than the microcode engine, the FIFO in between the two units will already contain the new branch address as soon as the microcode engine is finished with the first FAST message.
Relationship: contrasting
Domain: Hardware
Sentence 1: Metallic CNTs can be removed by selective chemical etching [Zhang 06].
Sentence 2: such etching can introduce significant variations in CNFET circuits [Deng 07]  P + d o p e d S e m i c o n d u c t i n g V d d C o n t a c t * C N T s f o r s o u r c e &#38; d r a i n L i t h o g r a p h i c P i t c h ( 6 4 n m = 4 . )
Relationship: contrasting
Domain: Hardware
Sentence 1: Implicit Learning By Signal Grouping The incremental learn-from-con.ict strategy involves explicitly se­lecting a correlated pair of signals, assigning their values in the way that it will most likely to cause con.icts, and then utilize the SAT solver to accumulate learned clauses (learned gates).
Sentence 2: in implicit learning, signal correlations are used to in.uence the decision variable selection and variable value assignment.
Relationship: contrasting
Domain: Hardware
Sentence 1: It M T J,mean M T J,mean is because that the driving ability of the NMOS transistor is quickly saturated when Vgs reduces.
Sentence 2: the ratio between the standard deviations of the MTJ write currents, i.e., s0.1 /s1.0 , slightly increases when the NMOS transistor IM T J IM T J size grows.
Relationship: contrasting
Domain: Hardware
Sentence 1: To alleviate this issue, in [4] coordinated accesses to instruction and data memories, enabled by a smart crossbar interconnect that supports broadcasting, is proposed.
Sentence 2: the bene.t of broadcasting (up to 40.6% active power sav­ings [4]) relies on lockstep execution of algorithm parts that can be carried out using the single instruction multiple data (SIMD) processing paradigm.
Relationship: contrasting
Domain: Hardware
Sentence 1: It is based on the fact that, under inversion bias, gate leakage through SiO2 for PMOS transistors is an order of magnitude lower than that of NMOS transistors [19].
Sentence 2: the PMOS transistors in the logic tree of a P-type Domino have to be up sized to achieve the same performance as N-type Domino, due to lower mobility.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the execution time of Pa2 is small, then Pb1 is preempted by Pa3, resulting in a certain response time of Pb1.
Sentence 2: if the execution time of Pa2 is large, then it takes longer time for Pa3 to become ready for execution, and consequently Pb1 has time to .nish its execution without any preemption from Pa3, thus resulting in a smaller response time.
Relationship: contrasting
Domain: Hardware
Sentence 1: For Canny and Fluid, the computation time of hardware acceler­ators (Column 8) in the Molen with NoC slightly increases com­pared to the original Molen (Column 4) because some hardware accelerators have to send their results to more than one local mem­ories.
Sentence 2: the accompanied reduction in the communication time results in a lower overall execution time.
Relationship: contrasting
Domain: Hardware
Sentence 1: STT-RAM Designs Supporting Dual-port Accesses Xiuyuan Bi1, Mohamed Anis Weldon2 and Hai Li1 1Department of Electrical &#38; Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA 2Department of Electrical &#38; Computer Engineering, Polytechnic Institute of NYU, New York, NY, USA Email: {xib5, hal66}@pitt.edu, mweldo01@students.poly.edu Abstract The spin-transfer torque random access memory (STT-RAM) has been widely investigated as a promising can­didate to replace the static random access memory (SRAM) as on-chip cache memories.
Sentence 2: the existing STT-RAM cell designs can be used for only single-port accesses, which limits the memory access bandwidth and constraints the system performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: As it can be seen, merely computing independently and multiplying the logical masking and electrical/latching-window masking probabilities leads to a huge error in the probability of latching the glitch, which can be as large as 3100%.
Sentence 2: for smaller glitch duration (80ps), the average error is not very large, due to the fact that most glitches are electrically masked, and therefore, separate and unified methods give similar results.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, when N=2 we can dedicate one SDM to each of the four possible insertion policies (00, 01, 10, 11) and use the best insertion policy out of the four for the remaining sets of the cache.
Sentence 2: the number of SDMs increases exponentially with the number of concurrently executing applications making this brute­force approach impractical.
Relationship: contrasting
Domain: Hardware
Sentence 1: However, as the number of users soars, so does the risk of possible misbehavior; to pro­tect themselves, wireless ISPs already make use of a number of security mechanisms, and require mobile stations to au­thenticate themselves at the Access Points (APs).
Sentence 2: iEEE 802.11 works properly only if the stations also respect the MAC protocol.
Relationship: contrasting
Domain: Hardware
Sentence 1: Our results show that the PCM/DRAM hybrid main memory with a modest DRAM size can give comparable performance to that of the DRAM only main memory.
Sentence 2: the hybrid memory with small DRAMs or large footprint programs can suffer from performance degradation due to the long latency of both PCM writes and write preemption penalty, which requires architectural innovations for exploiting the full potential of PCM write performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: Few ADLs allow architecture explo­ration on multiple abstraction levels, that is, the designer is enabled to thoroughly explore the processor s instruction set before elaborating alternative implementations of the mi­croarchitecture.
Sentence 2: a .exible choice of the abstrac­tion level is not only a requirement for the speci.cation of the processor core, but also for the memory attached to it.
Relationship: contrasting