sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: However, On­chip decaps are typically manufactured using MOS transistors, and excessive on-chip decaps would not only consume on-chip area, but also cause more leakage power, low yield and lower resonant frequency [1].
Sentence 2: as long as power supply noises are constrained, decaps should be minimized, especially when the white space (WS) left after placement and routing is limited.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, to save additional resources and to preserve traces, an implementation cannot arbi­trarily merge a sequence of iterations into a single one, but only a sequence of iterations that is caused by different non-con.icting actions.
Sentence 2: an implementation is assumed to .re a subset of actions of the CAOS model in each step, such that the choice of the subset guarantees the desired property by construction.
Relationship: reasoning
Domain: Hardware
Sentence 1: For digital circuits, behavioral modeling can be performed with high-level description languages such as VHDL or Verilog, but these languages are not appropriate for a right behavioral description of analog systems, since the analog characterization is composed not only of the function that the circuit has to perform, but also the second-order non­idealities intrinsic to analog operation.
Sentence 2: a suit­able analog high-level description language with enough resources to implement those second-order effects must be used to create correct behavioral models of analog circuits.
Relationship: reasoning
Domain: Hardware
Sentence 1: When the FPGA is programmed with the con.guration bit stream of a particular algorithm, if occupies a certain number of Frames1.
Sentence 2: an algorithm s logic may occupy either a set of contiguous frames or a set of non-contiguous frames on the FPGA , as predetermined by the area con­straints on the FPGA during the programming of the same.
Relationship: reasoning
Domain: Hardware
Sentence 1: For example, powering on Routers 4 and 5 in Figure 4(a) has larger performance benefits than powering on Routers 0 and 1, as the former provide a shortcut to route packets that would otherwise be detoured through 9->13->12->8.
Sentence 2: taking the placement of bypass paths and routers into account, additional performance gains can be obtained.
Relationship: reasoning
Domain: Hardware
Sentence 1: The conversion of SDFGs to HSDFGs can easily be adapted though.
Sentence 2: a naive MCM analysis leads to enumerating all simple cyclesof the HSDFG and collecting the expressions in the DCMS.Also, the state-space method of [7] cannot be directly usedfor parametric throughput analysis, but it can be generalized.In the remainder, we introduce two variations of the existingmethods and one new method for calculating the throughputof a parametric SDFG.
Relationship: reasoning
Domain: Hardware
Sentence 1: The replication cache based approaches, however, can improve the loads with replica by 22.7% more than ICR on average (note that it can even 100% loads with replica by counting in the replicas in the L2 cache).
Sentence 2: the repli­cation cache scheme can trade a small area overhead to enhance data reliability more signi.cantly than the ICR approach.
Relationship: reasoning
Domain: Hardware
Sentence 1: For example, assuming two layers L1 and L2, if the .nal width of packed modules of L1 is larger than the .nal width of packed modules of L2 and the height of L1 is smaller that of L2, a signi.cant portion of chip area is wasted due to the need for the layer dimensions to match for manufacturing.
Sentence 2: care must also be taken in both stages of our algorithm so that the dimension of each layer will be 0.0 0 (b) Vdd = 0.9V Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: Indeed, when the optimization formulation is stripped of these constraints, it is observed that the worst-case waveforms matches the RPT­generated ones, but, as expected, these waveforms overestimate maximum voltage drop with respect to their constrained counterparts.
Sentence 2: this technique has the clear benefit of offering less pessimistic predictions, and broader user­characterization of current waveforms than is possible with RPT.
Relationship: reasoning
Domain: Hardware
Sentence 1: value 1 in ci, is high enough to meet all synchronization requirements before any activation;  processor frequency values: a global causality problem (between different projected clocks) also arises when a processor P2 executing a data consuming task, is active very often before the required activations of a processor P1 executing a data producing task.
Sentence 2: the choice of processor frequencies must satisfy the global causality.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3.5 Global Buffer Re-Placement As mentioned in Section 3.2, placing bu.ers in the cur­rent level would change temperature distributions and a.ect bu.ers placed in the previous levels.
Sentence 2: after con­structing a clock tree topology level-by-level, we perform global optimization to simultaneously adjust all bu.er locations un­der the same clock tree topology.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, when the other bench­marks are able to detect that the current .ow is a safe connection, they leave the packet out of tracking the .ow state.
Sentence 2: there are two types of application ac­cording to the processing behavior along a networking con­nection, namely: the applications that the main stateful processing is concentrated on the .rst packets of the connec­tion (e.g.
Relationship: reasoning
Domain: Hardware
Sentence 1: We consider that [5] has 5 multiplexers 5:1 in each router, whereas our proposal has one 5:1 multiplexer and 4 multiplexers 2:1.
Sentence 2: adNoC uses only 8 multiplexers 2:1, whereas [5] uses 20 multiplexers 2:1 (4 for each multiplexer 5:1, in each channel), which increases power in at least 26.88.W for each router and 0.32mW for all network.
Relationship: reasoning
Domain: Hardware
Sentence 1: Consider two cores that have af.nity at cache L. The chances for experiencing destructive interactions in the cache space are higher if these cores do not share data, as this will typically increase the number of distinct data elements that compete for the limited cache space.
Sentence 2: if two iterations (that belong to a parallel loop) do not share data, it is better to assign those iterations to cores that do not have af.nity at any cache (if possible).
Relationship: reasoning
Domain: Hardware
Sentence 1: Level Converter Design for Sub-threshold Logic As discussed in the previous section, conventional static level INB converters cannot be applied for communication between sub­ (b) Level conversion fails in ultra low voltage input due to weak pull down Fig.
Sentence 2: 2 Failure mechanism of conventional level converter when applied to sub-threshold logic in our dynamic converter design, we assumed that a high voltage clock would be delivered through an extra clock path.
Relationship: reasoning
Domain: Hardware
Sentence 1: Sp} = {0,4,5} corresponds to a recovery sequence {xi}0=i=6 = {1000110}.
Sentence 2: the read-optimal and balanced recovery schemeis symbols d1,3 , d2,3 , d3,3 are recoveredby rowparity, and symbols d0,3 , d4,3 , d5,3 are recoveredbydiagonalparity.
Relationship: reasoning
Domain: Hardware
Sentence 1: Figure 3(d) shows an improved optimal-timing CSA-tree structure, which we call cir­cuit3, produced by our algorithm under the general CSA timing model.
Sentence 2: the timing of circuit3 (=11) is shorter than that of circut1 (=13), and the interconnects in circuit3 are still as regular as that in circuit1.
Relationship: reasoning
Domain: Hardware
Sentence 1: While the assumption of deterministic service times is valid in the case of network routers serving .xed-size pack­ets, or is a reasonable approximation when the packet sizes have small variance, such an assumption is hardly justi­.ed in the case of Web servers where, in addition to the long range dependency of the arrival process, requests vary largely in their sizes and service demands, often having non­traditional (subexponential) tail distributions, [1, 10, 12, 17, 23].
Sentence 2: how would the performance be in.uenced by the LRD input process and the non-traditional service time distributions remains an open question, important both in theory and practice such as Web server performance and QoS concerns.
Relationship: reasoning
Domain: Hardware
Sentence 1: Whenever one or more of the coe.cient values slip outside its individual hyper-cube we get a di.erent set of coe.cients that re.ects a detectable fault.
Sentence 2: equation (4) describes a hypercube for all parameters that correspond to either good machine values or undetectable parameter faults [1, 4, 10]: ai,min <ai <ai,max .ai, 0 = i = n (4) This paper is organized as follows.
Relationship: reasoning
Domain: Hardware
Sentence 1: In this region, the process cannot be checkpointed due to the atom­icity property of communication operations (i.e., the mes­sage can have only one of two distinct states, sent/received and not sent/not received ).
Sentence 2: in order to obey the atomicity property, upon receiving a checkpoint signal, the process should delay the signal until it transits either to the non-critical section state, if the process is com­ing from a non-critical section state, or to the non-critical, Ckpt.-unsafe state, otherwise.
Relationship: reasoning
Domain: Hardware
Sentence 1: The reduced current demand in dual VDD circuits proves useful here since it becomes feasible to use lesser decoupling capacitors for each of VDDL and VDDH as compared to the single VDD case.
Sentence 2: for Cblk (and similarly for others), we have, Cblk CblkH CblkL , and (1) CblkH / CblkL I (VDDH ) / I(VDDL) where, CblkH/CblkL are the decoupling capacitances attached to VDDH/VDDL, and I(VDDH)/I(VDDL) are the current demands on VDDH/VDDL respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: The expected value of the sum of these error Etotal is computed by assuming that each bit in A, B and P has an equal probability of being one or zero.
Sentence 2: the expected value of the total error is the sum of expected reduction error and the expected rounding error as Etotal = Ereduction + Erounding S-k-1 S-1 X X 1 1 -m-n+q -m-n+z Etotal = (q +1) · 2+ · 2 4 2 q=0 z=S-k where S = m + n - r [14].
Relationship: reasoning
Domain: Hardware
Sentence 1: If z in (3) is taken as 95%RI , the 95th percentile of RI , we can show that 95%RI is no less than 95%RD, the 95th percentile of RD.
Sentence 2: 95%RI = 95%RD, (4) which can be also written as: 95%RD = a · 95%RI , (5) where a takes a value between 0 and 1.
Relationship: reasoning
Domain: Hardware
Sentence 1: Overall AF overhead is the same in both schemes, as in scheme ES av  the two bitstream average activity factors  there are two parallel encoders/decoders, each  (a1=a2) encoding/decoding one bit ever y cycle, while in scheme SE there is one encoder/decoder encoding/decoding two bits ever y cycle.
Sentence 2: the best encoder/decoder location will depend on which one provides higher reduction in activity factor.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3 Operations and data path of HS cell It can be see that the state related to S1 is only propagated to the MUX-DFFs of cell 4, cell 2 and cell 0 whose index number is even, while the state related to S2 is only propagated to the MUX-DFFs of cell 3, and cell 1 whose index number is odd.
Sentence 2: the scan chain can be divided into two logical scan chains.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, the complete set of direct implications associated with A = 1 is: {(A,1,0), (H,1,0), (B,1,0), (C,1,0), (D,1,0), (I,1,0), (J,1,-1)} b) Indirect Implications: Although C = 1 or D = 1 do not imply anything on gate F individually, together, they imply F = 1.
Sentence 2: indirectly, A = 1 would imply F = 1 (shown as a dashed line in Figure 1).
Relationship: reasoning
Domain: Hardware
Sentence 1: In this case, after all the free pages are consumed, most pages are likely to have been updated multiple times.
Sentence 2: gC can .nd   60 80 0 1020304050 0 1020304050 Response time (ms) Response time (ms) 100 40 100 0 Residual lifetime (%) 20 40 (a) 0-10% LPN is reserved (b) 0-100% LPN is reserved 40 Figure 2: Analytical model of residual lifetime Figure 3: Read latency of the Intel 320 SSD victim blocks with a high percentage of invalidated pages, decreasing the number of valid pages copied and increasing the GC e.ciency.
Relationship: reasoning
Domain: Hardware
Sentence 1: The only di.erence of this traversal from the one in Sec­tion 3.3 is that the starting arrival timing from the primary input k is ak, which is unknown until this module is integrated into a hierarchical design.
Sentence 2: an arrival time item from k to a latch j becomes to aj = ak + Dkj + Ckj T (35) If this arrival time is propagated a latch stage further, the corresponding delay shift can be merged with the right side of (35) by adding the random variables and the coe.cients of T separately.
Relationship: reasoning
Domain: Hardware
Sentence 1: Instead of speci.cally designing a set of rules for dynamic con.guration of resizable caches in SMT proces­sors, we apply GAs: we want to obtain new con.gurations that can improve the IPC results.
Sentence 2: we consider an individual of the population as a sequence of con.gurations to be applied at speci.c inter­vals when running a given benchmark on the previously de­scribed SMT architecture.
Relationship: reasoning
Domain: Hardware
Sentence 1: Equation (28) is similar to (22); the only di.erence being that the voltage drop (Vi - Vj) in the RC cases shifts to the voltage drop minus the Ldi/dt drop.
Sentence 2: the RC model in Figure 2(a) can be modi.ed and becomes a new RLC model,which is showninFigure 2(b).
Relationship: reasoning
Domain: Hardware
Sentence 1: This is true because slow adders have longer critical paths and the change in current drawn by the gates due to process variation averages out; resulting in small s/µ.
Sentence 2: for tolerance to process variation, RCA and  7C-5   S31 S19 ... S12 S0 activation (a) (b) Delay variation in C2SA adder (Nominal Voltage) KS Adder 0.12 Delay variation in BK adder (Low Voltage) 0.02  0.02 00 0 0.5 11.5 2 01234 Delay (ns) Delay (ns) Delay (ns) Delay variation in BK adder (Nominal Voltage) 0.14 0.1 0.08 0.06 0.12 0.1 0.08 # of occurences # of occurences 0.06 0.04 0.04 0 01234567    (c) (d)  s (ps)   and 64-bit adders and corresponding area overhead BK are the best choice.
Relationship: reasoning
Domain: Hardware
Sentence 1: (ri[0]·Ci) (8) i=1 i=1 i=1 The first term of equation (8) expresses the doubling of Xn, which is the correlation value between the n-bit signal ri[n:1] and Ci.
Sentence 2: the correlation value Xn+1 can be rewritten according to (7) and (8) as L L L Xn+1 = 2·Xn + .
Relationship: reasoning
Domain: Hardware
Sentence 1: That is, it is impossible that for any vj , .n i n .1 i G1(vj ) = 1, but G1(vk ) = 0.
Sentence 2: because number of 1 = i  we are given G1(.n) = G2(.n), that means i i .............. G1(vj ) = G2(vj ) for all vj , we can conclude ............. .
Relationship: reasoning
Domain: Hardware
Sentence 1: For example, if a 3-bit vertical fault occurs in the first bit of byte 0 of the first three rows (left array), the fault affects bit 0 of byte 0, bit 0 of byte 6 and bit 0 of byte 7 of R1 and R2 (right array).
Sentence 2: by adding two registers and two barrel shifters to a parity-protected cache with 8 interleaved parity bits, CPPC has the potential to correct all spatial MBEs contained in an 8*8 square.
Relationship: reasoning
Domain: Hardware
Sentence 1: (Note, that for prime moduli, one needs at least r multiplications to compute such a polynomial. )
Sentence 2: polynomial rr Q(x,y)=xiyi-P(x,y) i=1 i=1 o(1) can be computed also with only t= r homogeneous mul­tiplications: trr Q(x,y)= bij xicij yi, (1) j=1i=1 i=1 and it has the following properties: (i) the coe.cients of the xiyi terms equals to 1, for i = 1,2,...,r, (ii) any other coe.cient is 0 modulo at least one prime­power divisor of m.  In particular, for m = 6, the coe.cient of any xiyj (where i= j ), is either 0, or 4 or 3 modulo 6.
Relationship: reasoning
Domain: Hardware
Sentence 1: The BMAP/G/1 queue: A tutorial.
Sentence 2: in Performance Evaluation of Computer and The term pij (k - 1,k)= P [Qk = j|Qk-1 = i] denotes the probability that the process makes a transition from state i at period k - 1 to state j at period k. This probability is obtained from the arrival load A and given that A is the same in all the periods, then the pij (k-1,k) does not depend on the period k. we can represent pij (k - 1,k) as pij and Eq.13 is reduced to: X P [Qk = j]= P [Qk = i] · pij (13) i Communication Systems, Joint Tutorial Papers of pij is known as the one-step transition probability.
Relationship: reasoning
Domain: Hardware
Sentence 1: (1) y x+1 that each bit in the stream is one is P (X = 1) = .
Sentence 2: a real 2 NN x -x + e 22 e number x = -1 is represented by a stream of all zeros and a real number x = 0 is represented by a stream of bits that have probability 0.5 of being one.
Relationship: reasoning
Domain: Hardware
Sentence 1: yondbasicblocksisdoneandwhatisrevealedhere isbynomeanstheboundonavailableparallelismin thewholeapplication.
Sentence 2: 302 InstructionsExecutedinParallel benchmark 1 2 3 4 5 db 90.12 9.88 0.00 0.00 0.00 javac 93.41 6.28 0.17 0.00 0.00 jess 92.05 7.95 0.00 0.00 0.00 mpeg 94.70 5.30 0.00 0.00 0.00 mtrt 91.22 8.78 0.00 0.00 0.00 Table3:Percentageofinstructionsexecutedinpar-allelwhenusingaDB-Cacheof128entries Table3showsthepercentageofinstructionsthat canbeexecutedinparallelforthepicoJava-IIwitha fllunitandDB-Cache(of128entries).Itisseenthat 90-94%oftheinstructionsareexecutedwithoutbeing pairedwithotherinstructions.Javacisonebench­markinwhichweseeanegligiblesmallpercentofthe instructionsbeingexecutedatarateof3instructions percycle(0.17%).Weneversee4or5bytecodes beingexecutedinonecycle,becauseofthedepen­denciestothestack.Thisimpliesthatinthelimited windowweareinvestigating,mostoftheinstructions haveadependencytothestack,andislimitingthe executionwidthevenifweareabletodecodeupto 5instructionsinonecycle.Sincethereisoneunique stack,anoperationwhichexpectsanoperandfrom thestackmustwaitanddependonthepreviousload orwrittenbackdatatobestoredintothestack.This causesaseverelimitationtotheinstructionlevelpar­allelismthatcanbeexploited.itwewillbe notbepossibletogainmuchperformancebyadding resourcestoexecutemorethan2instructionsinone cycle,withoutalleviatingtheconstraintsimposedby thestack.
Relationship: reasoning
Domain: Hardware
Sentence 1: Similarly, this process con­tinues untilthelast shiftfrom n-1ton whichhas(n-k+1)k swaps.
Sentence 2: for each elementlike k in set P ' , there are 70 60 50 40 30 20 10 Network Size Figure 4: The impact of network scale on the opti­mal proxy number in PFS.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3.2.4 Simple Reverse Query Propagation Inase5,thenodenisastatementotherthana..state­ment,adonode,a...statement,oraproedurehead.In thisase,theefetofexeutingnodenanbederivedby examiningnalone.QueryPropsimpleusesthesameframe­workasQueryPropinFigure6withSummarizebeingre­plaedbySummarizeSimpleNode,whihalsoistheinter­faebetweentheQuerySolverandthePropertyCheker(see Set.3.2.8).
Sentence 2: .......1.InFigure8,statementsst1andst2aresim­pleassignmentsofarraya().Thepropertytobehekedis a(i)=i*(i-1)/2.Hene, SummarizeSimpleNode(st1)=(ill=0,Gen=[n:n]) SummarizeSimpleNode(st2)=(ill=[1:1],Gen=0) afterthepropagation,forstatementst1wehave: anykilled=false,setionremain=[1:n-1].
Relationship: reasoning
Domain: Hardware
Sentence 1: These blocks, known as function- nodes, not only indicate which state-variables are related but also how they are related.
Sentence 2: more specifically, a function node f that has links to state-variables X and Y assigns a weight f( X= x, Y= y | m) to any outcome X = x, Y = y given a measurement m. function-nodes define constraints (or interdependencies) between state-variables.
Relationship: reasoning
Domain: Hardware
Sentence 1: Synthesisofzpusingcounterstates Forefcientlogicsynthesis,thecharacteristicfunction zpmaybeimplementedinaslightlydiferentfashion.
Sentence 2: wechooseasetofcolumnsrandomlyfromtheRM, andtreatthemsimilartodistinguishingcolumnsfor designingCmap.Todefnez,wekeeptheremaining pcolumnsofRM,andthentoeachrowY0(ti)ofthere­ducedRM,weaddthecounterstateb1b2:::bdlog2ke representingthetestti.Thetruthtableisthende­fnedasbefore.Thisapproachalsopreserveszero­aliasing.thesizeoftheinputsetofvariables defningzcanbeappropriatelychosentoftinavail­ p ablelogicsynthesistools,providingusoptionsfora fexibledesignbychoosingthesizeofp.Inthelimit­ingcase,nodistinguishinglinesmaybeused,i.e.,the second-stagecompactorisnotrequired.Allthemout­putsoftheCUTalongwiththecounterbitswillde­fnez,andsingle-outputcompactionwillbeachieved.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, with the IC technolo­gies advancing, when the driver impedance does not dom­inate the metal resistance ofinterconnect any more, these models begin to su.er inaccuracy problem.
Sentence 2: some techniques are proposed to improve the above gate model by turning the step voltage source into a time-varying piecewise one and choosing the value ofthe series resistor more elab­orately.
Relationship: reasoning
Domain: Hardware
Sentence 1: {} where {0,1,2, ,(j-1),j}config(k-1)(odd) denote all of the elements within the maximum length odd configuration of nodes, and {0,1,2, ,(j-1),j}config(0)(even) denote the all of the elements within the minimum length even configuration of nodes, and vice versa for the terms {0,1,2, ,(j-1),j}config(k-1)(even) and {0,1,2, ,(j­1),j}config(0)(odd).
Sentence 2: the nodes within the graph of the largest odd (even) configuration and the smallest even (odd) configuration are not mutually exclusive.
Relationship: reasoning
Domain: Hardware
Sentence 1: 18(b) that not only the EDP contours and iso-performance curves shift but also the design space gets restricted by thermal constraint that cannot be predicted by traditional evaluation.
Sentence 2: if electrothermal couplings are (i) standard technique, (ii-iv) temperature aware technique with only variable interconnect resistance (ii), only variable driver resistance (iii) and variable interconnect and driver resistances (iv).
Relationship: reasoning
Domain: Hardware
Sentence 1: However, we .nd that this compact design has poor fault-tolerance capability; its FTI is only 0.0833, which implies that most cells in this micro.uidic array are not C-Covered (there are only 10 cells that are C-Covered, as highlighted in Figure 19).
Sentence 2: if a cell becomes faulty during .eld operation, there is a low probability that the biochip can tolerate this fault via recon.guration.
Relationship: reasoning
Domain: Hardware
Sentence 1: The number of voltage option decreases at each schedule point as we move from 0 to ...... ;for this reason, it makes sense to build the decision tree backwards from ...... .
Sentence 2: the root of this tree represents the choice of voltage to be used from .... to ...... , the .rst level represents the choice of voltage ....-1 to ....,and so on,until the last level in which the voltage from 0 to ..1 is selected.
Relationship: reasoning
Domain: Hardware
Sentence 1: According to [24], metal width (W ), ILD thickness (H), and metal thickness (T ) signi.cantly a.ect two major performance parameters resistance (R)and ca­pacitance (C).
Sentence 2: if we want to capture the variations of resistance and capacitance, we have to model the variability of these physical parameters (that is, the variability of metal width, ILD thickness, and metal thickness) .rst.
Relationship: reasoning
Domain: Hardware
Sentence 1: fin = 40.00 MHz |A(fin)| = 1.00 Ain = 1.00 mV PSS fu = 40.00 MHz Cc = 2.84 pF PM = 60.00° In practice, due to parameter variations, the value of the on-chip compensation capacitor Cc is not exactly the same as the nominal value of 2.84 pF.
Sentence 2: the phase margin and unity gain frequency deviate from the ideal values.
Relationship: reasoning