sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: We use an oracle predictor to transform misspeculated loads to NOP instructions at the issue stage, avoiding data cache accesses down the wrong path, and thus any possible im­pact of them on processor performance.
Sentence 2: either the possible bene.cial e.ects due to wrong-path prefetching or detrimental e.ects caused by cache pollution are avoided.
Relationship: entailment
Domain: Hardware
Sentence 1: Unlike the previous works, our approach can guar­antee the close proximity of symmetry modules and signi.­cantly reduce the search space based on the symmetry-island formulation.
Sentence 2: the packing time for an ASF-B*­tree or an HB*-tree is the same as that for a plain B*-tree (only amortized linear) and much faster than previous works which need at least loglinear time.
Relationship: entailment
Domain: Hardware
Sentence 1: MATCHING FOR NPN-EQUIVALENCE Given two functions f(xx) and g(xy), optionally with their care-conditions fc(xx) and gc(xy), respectively, we decide whether f and g can be NPN-equivalent under the care-conditions.
Sentence 2: this problem can be divided into two subtasks by deciding whether f and g or whether f and ¬g are NP­equivalent.
Relationship: entailment
Domain: Hardware
Sentence 1: Since WPAN devices are typically operated in energy­constrained environments, they must be able to operate with much lower average power consumption than the existing wireless network components.
Sentence 2: because of the limited battery life associated with each device, as well as the difficulty involved in performing frequent battery replacement for a very large number of devices scattered over a large area, such as in the case of wireless sensor network applications, energy efficient operations constitute a mandatory requirement for WPAN devices.
Relationship: entailment
Domain: Hardware
Sentence 1: The existing communities are repeat­edly bi-partitioned in a depth .rst manner.
Sentence 2: in the example, at the next level in bi-partitioning, nodes in community 0 are split into communities 0 and 2, while nodes in community 1 (assuming that communities 0 and 2 cannot be split further) are split into com­munities 1 and 3, and may yield a chromosome such as The .tness function (network modularity) is computed after every partitioning.
Relationship: entailment
Domain: Hardware
Sentence 1: However, most of the previously proposed Trojan structures are constructed to evade conventional functional/structural testing so that Trojan­infected designs can pass commercial testing and be delivered to end-users.
Sentence 2: ample research has been conducted in order to enhance Trojan detection methods during the IC supply chain, but this research has focused primarily on enhancing the robustness of detection against Trojan designs that show a speci.c power pro.le.
Relationship: entailment
Domain: Hardware
Sentence 1: It turns out that very often there are only a few sets of ranges that occur in the output packets, and we can draw them by assigning each of them a unique real color 1.
Sentence 2: if we .nd that bytes 0 32 for many of the outgoing frames are in.uenced by bytes 24 25, we would assign the incoming range 24 25 a color (gray in this case) and draw both 24-25 of the incoming frames gray, and all the bytes of the outgoing frame in.uenced by 24 25 in gray as well.
Relationship: entailment
Domain: Hardware
Sentence 1: Let the Boolean variable Ej,i,w,r denote the address comparison of the read port r at depth i, and the write port w at depth j, defined as Ej,i,w,r=(Addri,r=Addrj,w).
Sentence 2: then the forwarding semantics of the  memory can be expressed as: (Ej,k,w,r.WEj,w.REk,r..0:p<W .j<i<k(¬Ei,k,p,r.¬WEi,p)) -(RDk,r =WDj,w) (3) data read at depth k through read port r, equals the data written at depth j through write port w, if the addresses are equal at depth k and j, write enable is active at j for the write port w, read enable is active at k for the read port r, and for all depths strictly between j and k, no data was written at the address location Addrk,r through any write port.
Relationship: entailment
Domain: Hardware
Sentence 1: It just means that the upper bound on block aspect ratios guaranteed by the analysis here for the given algorithm is at least 3.
Sentence 2: consecutive-pairwise area bounds tighter than 2 (e.g., ai/ai+1 = 1.5) are not guaranteed to reduce the maximum aspect ratio below what can be attained with ai/ai+1 = 2.
Relationship: entailment
Domain: Hardware
Sentence 1: In the general case, if transitions occur on several inputs, or a transition propagates along several reconverging paths, then the derivative .y/.xi may depend on the influence of other transitions which may result in a glitch at y.
Sentence 2: the value of the function .y/.xi = f (x1, x2, ... xi -1, ... xi +1, xn) depends in this case on the literals where values are nondetermined (unknown), and the calculation of .y/.xi is impossible.
Relationship: entailment
Domain: Hardware
Sentence 1: To avoid the thorny issues of dealing with and reporting on oth­ers data, a different approach for researchers studying attacks on anonymization is to focus on the anonymization techniques rather than the anonymized data.
Sentence 2: the researchers can re-apply the anonymization used by a particular data provider, but to data 4This is not always true, as some data providers (partially)anonymize using keys that they subsequently discard [8].
Relationship: entailment
Domain: Hardware
Sentence 1: V. CUSTOMIZING CAC H E LINE TURNOFF FOR PREFETCHED LINES Until this point in our experimental evaluation, all the cache lines are treated exactly the same way, whether they have been brought into the cache through prefetching or through a normal load operation.
Sentence 2: a prefetched cache line is put in SD power mode if it is not touched during the decay interval.
Relationship: entailment
Domain: Hardware
Sentence 1: {0,1,2,3,4,5}t , where r zj = bijxi mod 6 (2) i=1 that is, simply a linear combination, determined by (1), for j =1,2,...,t. Or, in matrix notation, where B = {bij }denotes an r ×t matrix with entries {bij }of equation (1): z = xB mod 6.
Sentence 2: certainly, di.erent x s may lead to the same z,since t = o(1) r << r, for large enough r. Now, from (1), polynomial Q(x,y) with any substitution o(1) of the y s can be computed from the t = r values of z. i .... (i) plugging in y=(0,0,..., 1 ,0,...,0), we will get modulo 6 the following polynomial: xi +4(xi1 + xi2 + ···+ xig )+3(xj1 + xj2 + ···+ xjk )(3) where di.erent indices denote di.erent numbers.
Relationship: entailment
Domain: Hardware
Sentence 1: We can see that, while the savings we achieve generally reduce as we increase the capacity of the client-side cache, the results are still good.
Sentence 2: evenwith thelargest client cacheweused, our .ne grain scheme achieves about 14.6% average improvement in execution latency with 8 clients and 9.1% improvement with 16 clients.
Relationship: entailment
Domain: Hardware
Sentence 1: However, the effective supply voltage of SRAM cell does not become near zero immediately when the sleep transistor is turned off.
Sentence 2: the effective supply voltage gradually de­creases.IfthepowergatedSRAMcellwakesup beforeitseffec­tive supply voltage reaches a threshold, the states of SRAM cells automatically recover.IfthepowergatedSRAMcellwakesupbe­fore its effective supply voltage reaches a threshold, the states of SRAM cells automatically recover.
Relationship: entailment
Domain: Hardware
Sentence 1: The results with thisscheme,giveninFigure21, areobtainedusingtracesfrom ourapplications.This hypotheticalschemeeliminates harmful prefetches in an optimal fashion.
Sentence 2: for each prefetch, it determines whether it will be harmful or not, and if it will be harmful,that prefetchis dropped.For easeof comparison, Figure21also reproducesthe resultswith ourscheme(the.ne grainversion).Wecan seefromtheseresultsthatthedifference between our scheme and the optimal one is not too much in theseapplications(theaveragedifferencebeing 3.6%).
Relationship: entailment
Domain: Hardware
Sentence 1: It is the boundary when the task starts generating requests for a device which could have been idle previously.
Sentence 2: it is the largest msuch that w((t,mn +1) prw (t,m )andw((t,mv) n w((t,ma+e1) -ihw (t,ma++1)for task t. w((t,mv)is a subset of w (t,ma ,1)whilew((t,mb+11)is not a subset of w((t,mv).
Relationship: entailment
Domain: Hardware
Sentence 1: The number of scanned APs for a day was 367 at least and 1,573 at most, and the number of rows in the database was 50,160 at least and 248,700 at most.
Sentence 2: the average amount of data for a day is 4.5MB to 22.3MB, which is a reasonable cost considering that the data storage of recent mobile devices is at least 4GB.
Relationship: entailment
Domain: Hardware
Sentence 1: Recent advances in applying statistical inference and optimiza­tion heuristics have enabled qualitatively new capabilities in mi­croarchitectural analysis.
Sentence 2: three fundamental advances have dramatically lowered the cost ofearly-stage performance and power estimation: (a) sophisticated sampling of instruction traces and design spaces, (b) predictive modeling to reduce the reliance on detailed simulation, and (c) heuristics for combinatorial opti­mization.Each technique in isolation is insuf.cient for analyzing microarchitectural adaptivity.
Relationship: entailment
Domain: Hardware
Sentence 1: Table 1 Circuit Information # Gates 600k # FFs 35,566 # Scan Chains 64 # Clock Gating Elements 984 Gated FFs Rate (%) 82.9 # Vectors CCx4 3,700 CCx8 3,755 CCx16 3,896 Test Coverage (%) CCx4 85.7 CCx8 85.7 CCx16 85.7 CCx4, CCx8, and CCx16 have 16, 8, and 4 external scan inputs, respectively, for the 64 internal scan chains.
Sentence 2: the compression ratios for CCx4, CCx8, and CCx16 are 4x, 8x, and 16x, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: We se­lected enough pilots such that the total number of fault injections we had to perform for validation (for pilots and the population) was over one million for each of control-and store-equivalence (1,378,000 for control and 1,093,000 for store) across all fault mod­els.
Sentence 2: for validating control-equivalence, we performed approximately 1,092,000 and 286,000 injections for integer regis­ter and address generation unit fault models respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.2 Validating the setup Duplicating a Web 2.0 workload is a signi.cant effort and in­volves .ne-tuningvarious software settings and con.gurations that necessitates propervalidation.Wevalidated ourexperimental frame­work both functionally and with respect to behavior and timing.
Sentence 2: we automatically veri.ed whether the .le sizes returned bythe duplicatedworkload matchthe.le sizes observedinthereal workload.
Relationship: entailment
Domain: Hardware
Sentence 1: Even though these approaches take into account temperature variations across various regions of the chip, they do not account for varia­tions over time.
Sentence 2: they optimize clock distri­bution for a given (non uniform) temperature pro.le, but they cannot account for the fact that such a pro.le can greatly change during system operation, depending on envi­ronmental conditions and workloads.
Relationship: entailment
Domain: Hardware
Sentence 1: F nodes are special operators in compiler transformations and are widely used in resolving conditional branches in a number of compilers, and used to postpone computation of control .ow to run time.
Sentence 2: a F node is introduced in a basic block which has multiple predecessors; the values of variables in a F node for a speci.c execution are given by the speci.c block which actually precedes the node in that execution.
Relationship: entailment
Domain: Hardware
Sentence 1: The method in [13] can reduce capture power for the UMC (Universal Multi-Casting) test compression architecture, which is a form similar to the Illinois Scan architecture.
Sentence 2: these methods cannot be applied for IR-drop reduction in general broadcast-scan-based test compression, which usually uses a more complex compressor composed of such gates as XOR, MUX, invertors, etc.
Relationship: entailment
Domain: Hardware
Sentence 1: As for SAs, we verified that the 48% of all possible SAs may result in the generation of a Pass, rather than a Fail, at the BIST structure output, with a detrimental effect on the microprocessor test quality and effectiveness.
Sentence 2: these are the SA1 possibly affecting node oi (i= 1, ., 32) and noj (j= 1, ., 4) and the SA0 affecting node nak (k= 1, ., 8) (Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: Because SAR algorithm has an open loop characteristic which means it cannot track the environmental variations, we used another strategy to make the system in a closed loop when the SAR control finished.
Sentence 2: the control unit continues the tracking procedure by adding or subtracting C[5:0] by 1 at a time because keeping the circuit in close loop guarantees the clock generator is still locked to reference clock.
Relationship: entailment
Domain: Hardware
Sentence 1: For both CWC and MLWC, we give a randomized 2O(log* n)­approximation algorithm respectively, where log * n is the iterated logarithm of n with base 2.
Sentence 2: log * n is the number of times the logarithm function must be iteratively applied to n before the result is less than or equal to 1.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.4 Circuit-Level Evaluation In order to evaluate the impact of contact routing on de­sign, we design a ring oscillator using a modi.ed 45 nm standard cell library as shown in Figure 9.
Sentence 2: this ring oscillator consists of 47 fanout-1 stages of 4X in­verter cells.5 We then repeat the design with standard cells that utilize contact-level routing.
Relationship: entailment
Domain: Hardware
Sentence 1: Since the bits computed by PE(1, 1) affect only the bits of PE(2, 1) and PE(2, 2), the bits computed by PE(2, i) (i = 3, 4, · · · , m - 1) are all zeros and hence these PEs can be eliminated.
Sentence 2: only PE(2, 1) and PE(2, 2) are nec­essary among the m - 1 rightmost PEs in the second row.
Relationship: entailment
Domain: Hardware
Sentence 1: We now consider a more diverse range of workload types: we consider all possible two-benchmark work­load mixes and determine the potential bene.t from heterogeneity; this is to study how sensitive a heterogeneous datacenter is with respect to its workload.
Sentence 2: for each possible two­benchmarkworkload mix, we determine the cost reduction through heterogeneity relative to homogeneous datacenters, see Figure 4.
Relationship: entailment
Domain: Hardware
Sentence 1: The latency, however, is only a couple of cycles for the individual components, but due to the distributed nature of the inter­connect, thebest-case round-trip forareadoperationfrom the ARM to the SRAM in Figure 2 (running at 200 MHz and the network at 500 MHz), is in the order of 30 processor cycles.
Sentence 2: the logical and physical modularity comes at the price of increased latencies.
Relationship: entailment
Domain: Hardware
Sentence 1: ( d, if io MAX wi(k)= wi(k-1)+ (2) -d, if io MIN, where wi(k)is the eviction weight of core i at the kth time interval, and MIN and MAX are the sets of minimum and maximumrankvalues,respectively,receivedby theL2 Man­agers.
Sentence 2: eviction weights at the kth interval are com­puted using the rank values as well as the eviction weights used at the(k-1)th interval.
Relationship: entailment
Domain: Hardware
Sentence 1: Given that the latency and size parameters of a DRAM cache are so widely different from traditional caches, and the technology constraints are disparate, we must be careful about the implicit optimizations that get incorpo­rated in the architecture of the DRAM cache.
Sentence 2: we point out that DRAM caches are much slower than tra­ditional caches, so optimizations that exacerbate the already high hit latency may degrade overall performance even if they provide a marginal improvement in hit rate.
Relationship: entailment
Domain: Hardware
Sentence 1: The lack of order in test vector application constitutes an aspect ex­ploitable in test compression literature.
Sentence 2: in combination with the sizable number of unspeci.ed bits in test cubes, especially prevalent in large SOCs, stitching the test vectors together in a ben­e.cial order promises to provide signi.cant reductions both in test vector application time and in test volume, a signi.cant issue by it­self for today s costly ATEs, achieving these reductions essentially at no hardware cost.
Relationship: entailment
Domain: Hardware
Sentence 1: From the performance comparison, it can be seen that our method has much higher precision than the other two.
Sentence 2: 77.6% of the extracted snippets are overlapped with the ground truths, our algorithm performs well on nearly 80% of music, while Logan s selection is 2.5 2 1.5 only 41.9%, only slightly better than the random method, which is 1 about 32%.
Relationship: entailment
Domain: Hardware
Sentence 1: The work proposed in this paper is orthogonal with the majority of the schemes mentioned; most of the authors concentrate on the high­level protocols, the topology and the interfaces that should be used in an efficient NoC while we propose an innovative way for the core interconnection network within such a framework.
Sentence 2: the majority of the proposed NoC schemes can be applied on the top of our buffered-crossbar architecture.
Relationship: entailment
Domain: Hardware
Sentence 1: ture can not only provide a framework for incorporating existing adaptive solutions, but can also enable novel adap­tations and applications that can signi.cantly expand the scope and utility of the cellular infrastructure (Section 2).
Sentence 2: we develop a meta-architectural model of cel­lular systems and show that emerging applications may not necessarily require restructuring the network and its com­ponents, but a change in the way information is observed, gathered and used.
Relationship: entailment
Domain: Hardware
Sentence 1: (4) signals of multiplexers, we can determine which adder units are combined together as groups, operating as an individual sub-adder.
Sentence 2: the problem of recon.guring GDA adder into a certain mode is just equivalent to the problem of combining adder units into certain sub-adders: the more e.ort we pay, the less accuracy loss we su.er from.
Relationship: entailment
Domain: Hardware
Sentence 1: DSN allows the user to specify an application using a high-level declarative lan­guage, Snlog, which is subsequently fed to a compiler which builds a runtime query processor that executes on each node.
Sentence 2: snlog, is a modi.ed version of Datalog [20] that is able to specify certain physical properties such as where tuples are stored and sent.
Relationship: entailment
Domain: Hardware
Sentence 1: Enforcing De.nite Detection at Circuit Outputs: To estab­lish de.nite detection of the fault according to equation (1) of section II, we need to constrain the solution space by limiting the detecting outputs to a single .xed one.
Sentence 2: for all possible assignments to the X-sources, the fault effect must be observable at one particular output.
Relationship: entailment
Domain: Hardware
Sentence 1: PROJECTION-BASED ANALYSIS We propose a projection-based analysis algorithm that is facilitated by exploring the underlying sparse structure of the leakage analysis problem.
Sentence 2: we propose the following methodology, which includes: 1) a two-step iterative algorithm for quadratic leakage modeling; 2) a quadratic model compaction algorithm for leakage distribution estimation; and 3) an incremental analysis algorithm for locally updating the leakage distribution.
Relationship: entailment
Domain: Hardware
Sentence 1: Figure 5 shows 1000 Monte-Carlo simulation results for the c3540 circuit.
Sentence 2: self-compensated, dense + iso, and original + iso library options meet timing requirement at all randomly chosen defocus points the two optimization strategies suggested in Sections 4.2.1 and 4.2.2 demonstrate appreciably tighter distributions than the self-compensated cell-based approach.
Relationship: entailment
Domain: Hardware
Sentence 1: Another key observation is that, due to the relatively small number of active users in steady state, the impact of opportunistic schedulers that take advantage of fast fad­ing is much more limited than one would expect from the analysis of a static scenario with a .xed user population.
Sentence 2: the cell capacity does not much di.er from that obtained with a simple round-robin scheduler, especially for large cells.
Relationship: entailment
Domain: Hardware
Sentence 1: Unfortunately, the relation E(4, 5) cannot be resolved as eas­ily; no other pairwise relationship between modules 4 and 5 can be introduced without either violating some other non-overlap con­straint, or extending the layout beyond the given .xed outline.
Sentence 2: the edges corresponding to the relations in the set {L(4, 5), R(4, 5), A(4, 5), B(4, 5)} are in con.ict with the current constraint graphs, and hence we must perform some modi.cations before we can repair this particular violated constraint.
Relationship: entailment
Domain: Hardware
Sentence 1: However, increasedmobility not only improves the drain current in the saturation regime of MOSFET operation, but it also increases the subthreshold leakage cur­rent.
Sentence 2: short-channel MOSFET saturation drain current, ID,sat, has a sub-linear dependence on mobility, µ0, while the subthresh­  2 1 0 Ion (normalized) Figure 1.
Relationship: entailment
Domain: Hardware
Sentence 1: The objective of this paper is to propose a design that improves not only the logging over­heads but also the recovery performance for DBMSs over MLC (and SLC) .ash memory, where the low reliability and the partial-programming constraints of the MLC .ash mem­ory must be considered.
Sentence 2: a logging mechanism with start, update and end log blocks are proposed to sup­port e.cient transaction recovery in joint considerations of both wear-leveling and garbage collection over .ash memory.
Relationship: entailment
Domain: Hardware
Sentence 1: Thus, consider the idea that designing an amplifier immune to electromagnetic interference would be sufficient to guarantee the immunity of the entire circuit of a voltage reference.
Sentence 2: the amplifiers are designed to achieve a high power supply rejection ratio (PSRR) and low distortion, because it was considered the only or, at least, the main responsible of the overall voltage reference immunity degradation in the presence of interference of these works.
Relationship: entailment
Domain: Hardware
Sentence 1: However, since the code fragment in Figure 2 does not exhibit any data dependence, the processors do not have to stick to the same tile processing order; that is, they do not have to process their data tiles in the same order.
Sentence 2: they can bring (and pro­cess) their data tiles in such a way that whenever one processor needs a non-local array element (to perform some computation), the needed data can be found in some remote SPM.
Relationship: entailment
Domain: Hardware
Sentence 1: For an N-vertex tree T and an integer a = a0, T can be laid out into M(l(N),2t(T)+ a),where l(n) 26n is Ca -16a if n> Ca2 , a-2 otherwise.
Sentence 2: t can be laid out into M(l(N),t(T)+ a) if T is binary.
Relationship: entailment
Domain: Hardware
Sentence 1: We have shown [7] that ANT technique re­duces the drop in SNR over a noiseless system from 11dB to 2dB for a value of perr as high as 10-3 .
Sentence 2: the ANT based system improves the SNR by 9dB when each .lter output bit is being .ipped at an average rate of once every 1000 samples independent of each other.
Relationship: entailment
Domain: Hardware
Sentence 1: The computation of their param­eters remains tractable and a remarkable corpus of techniques is available in this matter.
Sentence 2: gaussian mixtures are conveniently amenable to in­cremental estimation of their parameters, as further data is made available for a given speaker; 3. they can lead to a tree structure, that will enable speeding up speaker matching, compared to exhaus­tive search.
Relationship: entailment