sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: However, such improvements will add additional complexity to the control, and hence are not considered.
Sentence 2: according to Equation 3 and Equation 4, the overhead in our design only depends on len(i)(i =0, 1,... ,n -1) and k. when k is .xed, the performance of our design is only affected by the number of nonzero elements on each row, and not by the distribution of the nonzeros among the columns.
Relationship: reasoning
Domain: Hardware
Sentence 1: f T ( j), (2) i - 1 ss i=1 j=i where n states the degree of associativity, s the number of sets, and f T is the derivate of the estimated curve.
Sentence 2: because T (Fe(x)) = T (FT (x)), local deviations are .ltered away and a more accurate estimate is obtained for set­associative than for fully associative cache.
Relationship: reasoning
Domain: Hardware
Sentence 1: C. Writability vs. Half Select Disturb in Bit-Interleved 8-T SRAMs In a 6-T SRAM, half select disturb is nearly identical to read disturb if bit-lines of unselected columns are floated.
Sentence 2: half select disturb is unlikely to happen with appropriately sized 6-T SRAM if write assist method is not applied.
Relationship: reasoning
Domain: Hardware
Sentence 1: All the parameters are defined in more detail in [13].
Sentence 2: in multi-coupled lines, the time domain step response of the i-th line can be represented by n vt() s b p ()t (6) i .ik k k k =1 where pk ( )t is the TWA-based 3-pole response of the k­th mode which can be determined by using (3), (4) and (5) [17].
Relationship: reasoning
Domain: Hardware
Sentence 1: However,latch-baseddesignhas several drawbacks that make it suitable only when circuit performance is very stringent.
Sentence 2: instead of using latches, we stick to the FF-basedparadigm, but using a special version ofFFin which the clock edge ofthe masterlatchisdelayed so asto create a window of transparency instead of a hard boundary for capturing the data.
Relationship: reasoning
Domain: Hardware
Sentence 1: COMPUTATIONAL COMPLEXITY 11 12 -c ).s1 +(c ).r1 + e1.z1 U = 11 12 Considering the steps to generate the ICA mixing matrix A,the PCA transform, and the moments of the independent components i2 -b i1 (c i2 -c i1 ).ri + e2.z2 P P n m (b).si + = µ2 + i=2 j=2 The above representation of the max operation ensures that the ran­dom variables U and V involved in the max operation, max(U, V ), are statistically independent as they do not share any variables.
Sentence 2: from Equations (15) and (17), we can write Amax = W + T .
Relationship: reasoning
Domain: Hardware
Sentence 1: The power spectral density of thermal noise in the DAC output node is described by 16 ILSB St ( f )= KT · (2N -1) · RL · + 8KT · RL (5) 3 Vov When the quantization noise is smaller than the thermal noise the converter resolution is not equal to the bits number because the thermal noise magnitude exceeds the smallest conversion le­vels.
Sentence 2: it is not possible to include these levels into DAC resolution.
Relationship: reasoning
Domain: Hardware
Sentence 1: The conventional techniques[1-3] input bias conditions and faulty sites even for the same collected for evaluating soft error rates of the gate-level combinational cir-charge q.
Sentence 2: we can define a SET instance(SETi) in a gate cuits take the effects of electrical, logical and temporal masking g as an object, which have a specific pulse width, fault type( 0 or for such transient faults into account.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, if we remove the load-hit predictor al­together and only wake up dependents when the load data is returned, we get a 7% and 3% slowdown for integer and .oating-point applications, respectively.
Sentence 2: we con­clude that using a load-hit predictor and simply stalling the pipeline is a good design alternative that obtains most of the advantages of load-hit speculation without the necessity of supporting load-hit mis-speculation recovery.
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore,ourproedureensuressatisfatoryperformane ofthepowergridwhileutilizingjustenoughroutingre­soures,sothattheresouresavailabletosignalroutingare maximized.
Sentence 2: 4.1 Power grid wire removal heuristic AsstatedinSetion2,theongestionismeasuredinpro­portiontotheoverfowvalueoneahtileedge.Allpower wiresthatlieinongestedregionsarepotentialandidates forremoval,exeptthosethatliewithinhotspotswherethe voltagedroopissignifant.Therationalebehindthisisthat wheneverapowerwireisremoved,theperformaneofthe overallgridisompromised,andthisisallthemorenotie­ableifthiswirelieswithinahotspot.wedefne apowerwireasritialiftheworst­asevoltagedroopon itisbeyondsomespeifedthresholdVPth.Critialwires arenotandidatesforremovaleveniftheylieinongested regions.
Relationship: reasoning
Domain: Hardware
Sentence 1: The user s constraints are given by knowing that MEXP does the following hypothesis: the TPU reads the elementary input data in p cycles, with p the number of elementary input data needed to calculate each output data;  for each output datum, the time that the TPU spends to read the input is preponderant with respect to the time spent to calculate the output.
Sentence 2: the minimum temporal performances of a TPU is min(TP )= p × (size of Output Image).
Relationship: reasoning
Domain: Hardware
Sentence 1: Shao-Yun Fang Graduate Institute of Electronics Engineering National Taiwan University Taipei 10617, Taiwan yuko703@eda.ee.ntu.edu.tw  Wei-Yu Chen Graduate Institute of Electronics Engineering National Taiwan University Taipei 10617, Taiwan cweiyu@eda.ee.ntu.edu.tw Yao-Wen Chang Department of Electrical Engineering National Taiwan University Taipei 10617, Taiwan ywchang@cc.ee.ntu.edu.tw ABSTRACT Electron beam lithography (EBL) has shown great promise for photomask fabrication; however, its successive heating process centralizing in a small region may cause a severe problem of critical dimension (CD) distortion.
Sentence 2: sub.eld scheduling which reorders the sequence of the writ­ing process is needed to avoid successive writing of neigh­boring sub.elds.
Relationship: reasoning
Domain: Hardware
Sentence 1: As shown, at the end of the access data are served and the replacement stack of the cache holds the same information as in the baseline case.
Sentence 2: we can guar­antee the same behavior with one exception: all misses in a set with at least a faulty cache line (those that would have happened in the baseline and those caused by faulty cache lines) observe a deterministic latency increase2 to access the RVC before proceeding to the upper memory levels.
Relationship: reasoning
Domain: Hardware
Sentence 1: Although we computed and report the means in anal­ysis results, we opted for non-parametric statistical test­ing for assessing the signi.cance of all di.erences since we neither can assume nor could prove normally distributed samples.
Sentence 2: the signi.cance of di.erences mentioned throughout the paper were assessed by the Wilcoxon signed­rank test (p< 0.05).
Relationship: reasoning
Domain: Hardware
Sentence 1: So, the area penalty of tapering is minimal and less than 2% in our test circuits (layouts omitted for brevity).
Sentence 2: we conclude that instead of increasing N (stack height) from 2 to 5, and incurring a larger area penalty, the same amount of leakage power saving (=2X) can be obtained by optimally tapering the 2-header stack.
Relationship: reasoning
Domain: Hardware
Sentence 1: Second, S/DC filters redundant prefetches by recording the last prefetched address for stride patterns and comparing the new predicted address with earlier generated addresses in the prefetch queue and prefetch filter for other patterns.
Sentence 2: it reduces the bandwidth requirements and energy consumption S/DC: A Storage and Energy Efficient Data Prefetcher Xianglei Dang, Xiaoyin Wang, Dong Tong, Junlin Lu, Jiangfang Yi, Keyi Wang Microprocessor Research &#38; Development Center, Peking University, Beijing, China {dangxianglei, wangxiaoyin, tongdong, lujunlin, yijiangfang, wangkeyi}@mprc.pku.edu.cn This work was supported by the National High Technology Research and Development Program of China (No.
Relationship: reasoning
Domain: Hardware
Sentence 1: GiventhenumberofShiftQcellsascomputedaboveand theshift setjofeachcelltocontroltheshifting,ahardware ShiftQstructureasshowninFigure4caneasilybebuilt.
Sentence 2: 4.2 ShiftQ access EachEVRreferenceintheloopischaracterizedbyits EVRindexrandarelativeiterationdistancedwhich identifesthevalueofEVRrproducedditerationsago.The ShiftQcellpositionatwhichthisvalue(rd)isstoredis notfxed,butitmayshiftdownasnewlyproducedvalues displaceoldones.weneedtocomputethecell positionholdingavalue(rd)withintheShiftQatanygiven time.Sinceeachconsumerreferenceaccessesthevalueat afxedtimetcrelativetothestartoftheiteration2 ,this cellpositionisfxedforeachconsumeroperation.Wecan computethispositioneasilyusingthestatevariablesofthe ShiftQasshowninFigure7.Foraconsumerreferenceat timetcreferencingtheEVRvalue(rd),thisEVRmust havebeenproducedattimegivenby, tp=tsr;d.II Thefighttimeofthevalue(rd)sinceitsproductionisthen simplytc;tpwhichisusedtosearchfortheappropriate cellposition.ThepseudocodeshowninFigure7attempts tosearchfortheEVRrineachmodulocyclesofevery ShiftQcellstartingfromthezeroth.Thefrstcellinwhich thefighttimereachesthedesiredvalueisreturned.
Relationship: reasoning
Domain: Hardware
Sentence 1: of freedom-K 3 5 6  9,800 9,850 9,900 9,950 10,000 10,050 10,100 10,150 10,200 Number of Ones 5) Non-Overlapping Template Matching Test: The purpose of this test is to detect sequences with too many occurrences of a given aperiodic pattern.
Sentence 2: the 4-bit Template input Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: Firstly, for transceiver we assume that the active area calculated in [5, 21, 22] is theonlypart scaled down when wemoveto 45nm tech­nology, while the passive part is remain the same since the channels frequency range remain the same.
Sentence 2: pro­jected transmitter area is (3062µm2) per sub-channel, while projected receiver area is (125µm2) per sub-channel(active  5.2 Power estimation A router static and dynamic power is calculated using Orion 2.0 [24,25] model, as well as power dissipation for wire links is calculated for x (3.6mm)and y (5.2mm)direction.
Relationship: reasoning
Domain: Hardware
Sentence 1: Afterthegatheringloopisexeuted,allthearrayelements insetionx[1:q]aredefned,thevaluesofthearrayele­mentsinarraysetionx[1:q]areinjetive,andthelower boundofthevaluesofthearrayelementsinsetionx[1:q] is1andtheupperboundisp.
Sentence 2: withthisinformationavailableatompile­time,theom­pilernowisabletodeterminethatthereisnodatadepen­deneinloopdojandarrayindO)anbeprivatizedinloop dok.theompileranhooseeithertoparallelize loopdokonly,parallelizeloopdojonly,parallelizeboth, orparallelizeloopdokandvetorizeloopdoj,depending uponthearhitetureonwhihtheoderuns.
Relationship: reasoning
Domain: Hardware
Sentence 1: INTRODUCTION Because of the increasing clock frequencies, the use of high­performance design styles, like domino logic and pass-transistor logic, and the growing importance of the wiring coupling capacitance with respect to the gate and interconnect ground capacitance, the crosstalk-induced noise has become one of the limiting factors of the performances and functionality of large VLSI digital designs.
Sentence 2: static Noise Analysis (SNA) is a crucial task in the sign-off verification phase of the top-down ASIC design flow [1][2][3].
Relationship: reasoning
Domain: Hardware
Sentence 1: Since V[Ki]hits bwe have: OKi*S)modMd = Ki*a*2s =Oqi*2m+i*2s)where qiis the least integer such that Mdivides Ki*Sproducing remainder d. Therefore, 2m.sOqi*+i) Ki = a Also, by de.nition, for K1, distance dl2s .
Sentence 2: = * 2m.sOq1*+l) = K1 a where q1is the least integer such that aevenly divides q1*2m.s+ l. THEOREM 5.3. ir tHitOVVb)Ki OK1*i)mod2m.s .
Relationship: reasoning
Domain: Hardware
Sentence 1: D, 0 = t = Tmax (18) Note that even if constraint (16) makes st(i, t)tobe0 or 1 when droplet di doesn t stall within time t - 1 to t. Due to the constraint (14) and (15), the lower bound of the number of cells that must be deactivated in B is 11 when droplet di moves.
Sentence 2: to satisfy constraints (14), (15), and (18), the value of st(i, t) is restricted to be 0 only.
Relationship: reasoning
Domain: Hardware
Sentence 1: From this plot, we observe a maxima for CBB when 5e+14 4.5e+14 4e+14 3.5e+14 3e+14 L2(µm)  Cross-bar Bandwidth Figure 4: CBB for Varying w12 and s12 h12 = 300nm.
Sentence 2: we utilize this value of h12 for the interconnect structure.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thesefeatures are supportedbyspread spectrum(SS) techniques such asfrequencyhopping(FH).In anFH adhoc network,thephase ofhopping sequence,i.e.,FH-codephase istypicallyderivedfromthelocal clock reading of each node.
Sentence 2: network-wide time synchronization is needed in ordertogetthe nodesto simultaneously switch tothe same frequency channel, i.e., hop synchronously.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3, the estimated TTD value W d increases in proportional to d. Moreover, if W d is larger than a half symbol duration, then a sign of W d is inverted due to the effect of arc-tan operation.
Sentence 2: we have to normalize each estimated TTD value depending on co­  W 1(error) W derror) W d2 W d1 Sign comparison d 2(  W W W d 2d 3d 0 .NFFT/2 0 W W W W d1 d2 2( rr) o derode1( rrr) 0 .NFFT/2 0 Figure 4.
Relationship: reasoning
Domain: Hardware
Sentence 1: For example, a small size driver may not be able to drive the given load and cause malfunction; lower frequency will affect the circuit performance; low-k dielectric has very limited ability to reduce current density, and also affects other reliability problems such as Time-Dependent Dielectric Breakdown (TDDB).
Sentence 2: the typical EM correction is done by increasing the wire width or adding extra straps or vias for redundancy; such an approach gives a good compensation of EM and requires less additional design effort.
Relationship: reasoning
Domain: Hardware
Sentence 1: This makes it di.cult to determine a 4As a notation convention in machine learning and statistics, any symbol with a hat represents an estimate, instead of actual values or functions uni.ed, convex analytical function that spans the wide range of frequency/voltage values ranging from the TB to NTC modes of operation, which is required to e.ciently determine the optimal operating point and is the goal of this work.
Sentence 2: as an alternative to a physics-based model, we propose to learn a less complex function f that behaves like f. The model-learning procedure can be separated into two phases: training phase and validation phase.
Relationship: reasoning
Domain: Hardware
Sentence 1: Pass/Fail samples in the performance space   2.2 Step 2 Fail Force Computation The Fail samples close to Pass samples are more important because those Fail samples that leave the specifications too much are not likely to be the next nominal point.
Sentence 2: each Fail sample (Xi,k) is modeled as a force that is inversely proportional to its distance between the next nominal design point (Nk), as shown in (4).
Relationship: reasoning
Domain: Hardware
Sentence 1: For the second condition, tDATA(1)+tCK(2) would place the nominal data arriving at the boundary of tW, L and tW(k),M. For a TB 2-cycle interconnect, the delay range from clock skew and jitter for tW(1) equals tCK(1) tCK(2).
Sentence 2: tW(1) in a TB 2-cycle interconnect is expanded from (10) as: tW(1) =tW + tCK(1) - tCK(2) (21) Parameter tW represents the portion of the TW dedicated to data delay averaging such that tW=msDATA(1) DATA(2) in (21).
Relationship: reasoning
Domain: Hardware
Sentence 1: The fad­ing coe.cients can also be given in matrix notation, i.e., fms,j (i) = (Fj (i))ms.
Sentence 2: fj (i) is a M × Li matrix of complex variates whose columns are independently nor­mally distributed with mean vector 0 and covariance ma­trix .j (i) = IM .
Relationship: reasoning
Domain: Hardware
Sentence 1: The leakage minimization problem can be stated as that of minimizing the value of Ltotal which is a function of input vector and also variables X s and Y s. The leakage minimization has to be performed under the delay constraint illustrated in Figure 10.
Sentence 2: the minimization algorithm should take into account the values of the output of both circuits in Figures 3 and 10 as depicted in Figure 11.
Relationship: reasoning
Domain: Hardware
Sentence 1: This approach can be a good .t for our proposed CNTFET SRAM bitcell to improve its short circuit unrelia­bility compared to other SRAM designs since our proposed design contains asymmetric structure.
Sentence 2: we employ metallic CNTs removal technique to improve the probability of functional transistors in our proposed CNTFET SRAM bitcell, which is further detailed in the following.
Relationship: reasoning
Domain: Hardware
Sentence 1: Analyzing the bins count for each SE over bistream just four SE types ( coded_block_flag, coef_level, sig_coef_flag and last_sig_flag) account for more than 93% of all bins, for all types of macroblocks (I, B and P).
Sentence 2: was decided to perform a deeper analysis of the behavior of these SE types to improve the gain in the binary arithmetic decoder engine (BAD).
Relationship: reasoning
Domain: Hardware
Sentence 1: Finally, in the third set of experiments, we have mea­sured with our trace-based emulation framework the latency of packets through the network.
Sentence 2: the graph on the right 5 Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 05) 1530-1591/05 $ 20.00 IEEE  Figure 4.
Relationship: reasoning
Domain: Hardware
Sentence 1: (4), we can see that the current induced in each conductor segment in this case is equal to each element in the column jof the Kmatrix.
Sentence 2: we can rede.ne the element of Kmatrix as: the element Kijis the current .owing through the ithconductor when the magnetic vector potential drop along all conductors, except the jth, are set to zero, and the magnetic vector potential drop along the jthconductor is raised to unit potential.
Relationship: reasoning
Domain: Hardware
Sentence 1: From Norton s theorem, the modi.ed grid will exhibit the same voltage response at external and port nodes as the original grid.
Sentence 2: ... .F: ........(...)= ........(...) ........(...)= ........(...) so that: emax(........(...)) =emax ( ........(...)) (26) ...F ...F emax(........(...)) =emax ( ........(...)) (27) ...F ...F any veri.cation that we will do below on the external nodes in the modi.ed grid will also verify the same nodes in the original grid.
Relationship: reasoning
Domain: Hardware
Sentence 1: The hitrate for the RACB (when VCS=4, VCB=1) is around 30% higher than the fully and exact matching computation reuse technique (when VCS=16, VCB=23) without noticeable quality degradation.
Sentence 2: partial and approximate matching has a higher energy savings potential than conventional approach even if they have the same ratio of PRACB/PALL.
Relationship: reasoning
Domain: Hardware
Sentence 1: In this case, in input state 10 , node N is connected to the supply voltage, and therefore, its voltage is Vdd ; when input B changes to 1 , node N floats and some current is injected into it through the gate-drain capacitance of M4 and thus, the voltage of N increases by .V1.
Sentence 2: right before the 00 transition at the inputs, the voltage of N is Vdd+.V1.
Relationship: reasoning
Domain: Hardware
Sentence 1: ; ,0,0,0)T ,anupperbound dexlowerboundvectorof il=(0 Name Arrays Nests BriefDescription  adi.c 6 2 AlternateDirectionIntegral aps.c 17 3 MesoscaleHydroModel bmcm.c 11 3 MolecularDynamicofWater efux.c 5 6 MeshComputation tomcat.c 9 8 MeshGeneration tsf.c 1 4 Array-basedComputation vpenta.c 9 8 NasaAmesFortranKernel wss.c 10 7 MolecularDynamicsofWater  Table1:TheArray-basedBenchmarksUsedinthe Experiments.
Sentence 2: themaximumvalueofbitsinLBMindicatesthenumberof interferenceamongdiferentarraysinthenest.itisthe leastassociativitythatisrequiredtoavoidthisinterference.
Relationship: reasoning
Domain: Hardware
Sentence 1: (14) 2 It is easy to verify that the mapping between (c,r,Ln,Tn) and (X,Y,Lt,Tt) is a one-to-one mapping.
Sentence 2: the Jacobian is given by g .c .c .c .c .X .Y .Lt .Tt .r .r .r .r .X .Y .Lt .Tt g g J = .Ln .Ln .Ln .Ln .X .Y .Lt .Tt g .Tn .Tn .Tn .Tn g .X .Y .Lt .Tt 1 000 0 100 = -li 0 10 g 1 ·Y ·l2 t -1 ·l2 g g g 2 i li ·L2 ·X Y ·li 1 i =1.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that, in this detour situation, the estimated distance from SC to SN should be the summation of MD(SC ,ST 1), MD(ST 1,ST 2), and MD(ST 2,SN ), instead of MD(SC ,SN ).
Sentence 2: before really creating a bridge to SN , we check whether the distance from SC to its second closest unvisited switch is shorter than this estimated distance to SN .
Relationship: reasoning
Domain: Hardware
Sentence 1: Since there are a total of 72 × 4 = 288 additions in MIX and 18 × 8 = 144 additions in subkey addition, the probability of the complete attack is given by 2(-1.415)×288+(-0.28)×144 =2-448,giv­ing a complexity of 2448.The 512-bit key has 8 words of 64-bits and the three leftmost bits in each key-word are assumed to be known in the attack model, the effective key-length is 8 × 61 = 488 bits.
Sentence 2: according to the attack of [21], instead of 2488 attack complexity of random guessing, one has 2448 attack complexity.
Relationship: reasoning
Domain: Hardware
Sentence 1: Motion-compensated temporal prediction (Inter-mode) provides the highest compression efficiency, but it also comes at the highest computational cost.
Sentence 2: for some applications requiring low-latency and high quality (like pocket cameras, digital video capturing, automotive, camcorders, movie backups, or high-end cinema), only in-frame spatial prediction is used due to its smaller computational workload and a smaller power footprint.
Relationship: reasoning
Domain: Hardware
Sentence 1: A weighted metric is di.cult to measure online because knowing how some thread would fare if it had some greater portion of the cache is impossible to know without o.ine pro.ling, which can be inaccurate when inputs vary, and typically does not capture time-varying program behavior, or online sampling, which may be impractical if it requires running each of many threads alone sequentially in order to achieve unperturbed samples.
Sentence 2: it is useful to .nd what we term policy metrics, online measurable metrics that serve as proxies for evaluation metrics and can be used to drive policy decisions that yield good performance with respect to the performance target.
Relationship: reasoning
Domain: Hardware
Sentence 1: The difference between two neighboring lines is de.ned as ej = bj - bj+1 and the temporal variation between two consecutive lines is de.ned as .ej = ej -ej = .bj -.bj+1.
Sentence 2: + - Then, the power dissipated when loading or un-loading a 1 V 2 capacitor Cg is given by E0 = Cg the power 2 dd.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, in this case the CAD tools might be enhanced for the dual-Vt FPGA architecture.
Sentence 2: the dual-Vt FPGA CAD .ow is meant for evolving a dual-Vt FPGA architecture, and the various steps in this CAD .ow might need to be changed a little to suit a speci.c archi­tecture.
Relationship: reasoning
Domain: Hardware
Sentence 1: To accomplish this, its usage may not exceed (1 - q).
Sentence 2: that is, a virtual channel buffer is not re­quired if:  (P(VCn = TRa |VCn-1 = TRb)) < (1 -q) (7) a,b to optimize the number of VCBs in the .rst step, we use a multi-objective mapping function during NoC mapping considering the worst case concurrent transactions and it provides 100% QoS.
Relationship: reasoning
Domain: Hardware
Sentence 1: If we assume the DWF to be 16 as in the origi­nal paper, we found that our side-channel attack needs to .gure out 32 physical addresses adjacently located in the region, because a 1 × K memory line can be written times for one rotation period.
Sentence 2: dWF it takes around 17.5 minutes to fail one PCM mem­ory line.2 In sum, our side-channel attack exploits the deterministic mapping pattern of the randomized RBSG to fail PCM cells ef.­ciently.
Relationship: reasoning