sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: For example the set {(x + y)[5 : 0] = 0001, (x+ y)[7 : 3] = 00100} can be proven inconsistent using our algorithm, by applying the same reasoning on the uninterpreted term (x + y).
Sentence 2: our algorithms improves the congruence closure algorithm by giving explicit interpretation to the extraction operation.
Relationship: entailment
Domain: Hardware
Sentence 1: Some optimal non­monotonic routes can be found in linear time within the bounding box b that minimally contains p by (i) employing duplex-edge re­laxation and (ii) echo-relaxation if the relaxation succeeded in the direction opposite to node ordering (from a greater-numbered node to a smaller-numbered node).
Sentence 2: in the forward-going node or­dering, if a backward edge at node v(x, y) results in a smaller-cost route, we forward-propagate the smaller cost through all recently­relaxed edges incident to v. Figure 1 illustrates .nding an optimal route with three distinct monotonic segments in one BF pass.
Relationship: entailment
Domain: Hardware
Sentence 1: There are several types of on chip bus proposals such as AMBA from ARM [3], PLB crossbar switch from IBM [4], Wishbone from Silicore [5], silicon backplane from Sonics Inc. [6] and so on.
Sentence 2: aMBA of ARM is conventionally used in a number of systems because it is a good architecture for applying embedded systems with low power [7].
Relationship: entailment
Domain: Hardware
Sentence 1: By Parseval s theorem, the signal energy can be estimated in the frequency domain by summing squared frequency mag­nitudes.
Sentence 2: given a DFT vector of the acceleration mag­nitude signal mj where the magnitude of each coef.cient is taken (|M(f1)|, ..., |M(fN )|), the energy is N n xE = |M(fj )|2 .
Relationship: entailment
Domain: Hardware
Sentence 1: Together, these compo­nents comprise a high quality factor, or high-Q, LC-tank as a preci­sion reference for the clock oscillator.
Sentence 2: a significant focus of thiswork has been to develop these components in a manner that iscompatible with commercial CMOS manufacturing processes.a simple maskless post-process has been developed torelease the micromachined components without damaging theactive electronics.
Relationship: entailment
Domain: Hardware
Sentence 1: Both transistors are still in the linear region, but the channel resistance is modified.
Sentence 2: ceff _ overall Ceff _ n // Ceff _ p = Ceff _ n +Ceff _ p (6)  Reff _ overall (Reff _ p + Ron _ n ) //( Reff _ n + Ron _ p ) R R on _ n on _ p R // R = (7) on _ n on _ p R +R on _ n on _ p where Ceff_n, Ceff_p, Reff_n and Reff_p are the intrinsic effective capacitances and resistances, respectively, and Ron_p and Ron_n are the channel resistance of the two transistors.
Relationship: entailment
Domain: Hardware
Sentence 1: There are two potential advantages of a unified cache: (1) For a given cache size, a unified cache has a higher hit rate than split caches because it balances the load between instruction and data fetches automatically.
Sentence 2: if an execution pattern involves many more instruction fetches than data fetches, then the cache will tend to fill up with instructions, and if an execution pattern involves relatively more data fetches, the opposite will occur.
Relationship: entailment
Domain: Hardware
Sentence 1: We then present a hierarchical framework called hierarchical B*-trees (HB*-trees) which can simultaneously optimize the place­ment with both symmetry islands and non-symmetry modules and dynamically update the rectilinear shape for the modules in a symmetry island.
Sentence 2: the overall time complex­ity for packing an ASF-B*-tree or an HB*-tree is the same as (1) (Group (2)) listed below, while that with 2D symmetry must satisfy either of the four equations in Group (3) or Group (4).
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we first analyze memory latency reduction opportunities in a 3D main memory system with Wide I/O by taking better advantage of 3D integration technology and quantify their benefit.
Sentence 2: redesigning the DRAM to memory controller synchronizers and placing the address, command, and data pads closer to the DRAM banks can decrease 3D main memory latency by 24.7%.
Relationship: entailment
Domain: Hardware
Sentence 1: Characterizing CMP Working Sets To understand the potential bene.ts and costs of replication, this section analyzes the sharing behavior of cache blocks during their on-chip lifetime; that is, the interval from when a miss brings a block on chip until it is replaced.
Sentence 2: the study simulates an eight-processor CMP executing various commercial and scienti.c workloads under the Solaris 9 operating system.
Relationship: entailment
Domain: Hardware
Sentence 1: (16) Since .. ' is increasing we may reparametrize the family using the mean ...
Sentence 2: to the NEF above corresponds a family .... such that for each pair (.., ..) satisfying .. ' (..)= .. we have .... = ..... Now, the circuit variable .. is a random variable from NEF and it can be reparametrized by the mean .. as follows .. (.., ..)= ....(..)(..)= ....(..)= ......(..(..).. - ..(..(..)))h(..).
Relationship: entailment
Domain: Hardware
Sentence 1: We concentrate on the third solution in this paper by planning the global location of buffers in the floorplanning stage and use this plan as a constraint in the detailed placement stage.
Sentence 2: in the floorplanning stage, a global map of buffer requirements in various regions of the chip is estimated and in the detailed placement phase, the distribution of buffers are managed to be fit in the estimated buffer requirement map.
Relationship: entailment
Domain: Hardware
Sentence 1: William R. Eisenstadt Jongin Shim ECE Department ECE Department University of Florida, Hanyang Univ., Ansan, Gainesville, FL32603, Kyungki-Do, Korea USA, 352-392-4946 +82-31-400-5179 wre@tec.u..edu jishim@giga.hanyang.ac.kr and level of integration of the VLSI circuits so dramatically increase, the signal integrity degradation due to the inte­grated circuit interconnects becomes one of the critical issues [2]-[7].
Sentence 2: long interconnect line length and tight phys­ical spacing signi.cantly degrade the signal integrity due to signal delay, crosstalk, ringing, and glitches [5].
Relationship: entailment
Domain: Hardware
Sentence 1: The two-stage algorithm can easily quantify the impact of setting a gate to high Vth on the extent to which other gates in the circuit can be assigned to low Vdd.
Sentence 2: we can independently judge the impact of Vth and Vdd assignment on total power, something that is difficult to achieve in a flow that simultaneously assigns low Vdd and high Vth as in [7].
Relationship: entailment
Domain: Hardware
Sentence 1: To exploit this property, we in­troduce a scheduling step at the beginning of the treatment of each audio frame.
Sentence 2: we maintain a list of sound events pro­posed by the physics engine (which we call TempSoundsList) and a Figure 5: Effect of temporal scheduling; computational peaks are delayed, the slope of increase in computation time is smoothed out and the duration of peaks is reduced.
Relationship: entailment
Domain: Hardware
Sentence 1: This advantage comes partly from ef.cient .ne-grain pipelin­ing [4] and pipeline optimization techniques which balance asynchronous pipelines to prevent stalls and starvation.
Sentence 2: slack Matching is a problem unique to asynchronous design generally de.ned as adding a minimum number of pipeline buffers to an asynchronous circuit to achieve a given performance target [5][6].
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION Flash memory recently gains a lot of attention in serving as a storage-system alternative (e.g., [1, 3, 4, 8]) or as caches for hard disks.
Sentence 2: windows ReadyBoost [6] lets users use a removable .ash memory device to improve system * Supported in part by research grants from Taiwan, ROC National Science Council under Grants NSC95-2219-E-002­014 and NSC 95R0062-AE00-07.
Relationship: entailment
Domain: Hardware
Sentence 1: Similarly, when fine robotic motion is needed, if the speed of the robot has not been set sufficiently slow, the current position of the robot often drops out of the desired trajectory.
Sentence 2: in the teaching method using a force/torque sensor, if the speed of the robot has been set to fast, the robot does not follow the movement of the operator but leads the movement of the operator.
Relationship: entailment
Domain: Hardware
Sentence 1: User Person who interacts with the product Goal Intended outcome Task Activities required to achieve a goal Product Part of the equipment (hardware, software and materials) for which usability is to be specified or evaluated Measure (noun) Value resulting from measurement and the process used to obtain that value  Usability engineering, also called User Centered Design (UCD), is a methodology for designing technology products/services such that they meet usability objectives.
Sentence 2: usability engineering or UCD is a set of activities that need to be taken so as to ensure usability in an ICT product/service design/development [5].
Relationship: entailment
Domain: Hardware
Sentence 1: The most important use of this dynamic model in our frame­work is to predict the performance of a thread if allocated certain number of L2 and L3 ways.
Sentence 2: using the ob­served (sL2,sL3) values, we can .t a surface that represent the d values under various cache (way) allocations and use this surface to predict the performance of the thread if allocated (sL2,sL3), i.e., sL2 L2 ways and sL3 L3 ways.
Relationship: entailment
Domain: Hardware
Sentence 1: Sustainable Multi-Core Architecture with on-chip Wireless Links Jacob Murray, Partha Pande, Behrooz Shirazi School of Electrical Engineering and Computer Science Washington State University {jmurray, pande, shirazi}@eecs.wsu.edu ABSTRACT Current commercial systems on chip (SoC) designs integrate an increasingly large number of pre-designed cores and their number is predicted to increase significantly in the near future.
Sentence 2: molecular-scale computing will allow single or even multiple order-of-magnitude improvements in device densities.
Relationship: entailment
Domain: Hardware
Sentence 1: To compute the overhead of characterization we investigated several well-known testing algorithms, including MARCH B, MARCH SS, GALPAT, and pseudo-random algorithms for testing Active Neighborhood Pattern Sensitive Faults (ANPSFs) [11][13].
Sentence 2: we considered a deterministic (100% coverage) ANPSF algorithm and a pseudo-random coupling fault detection technique with 99.9% coverage.
Relationship: entailment
Domain: Hardware
Sentence 1: It is possible that the communication characteristics of this new sub-computation is different from the original computation; however, in this paper, a conservative approach is adopted and all communi­cation is assumed to be uniform.
Sentence 2: if two processors, Pi,j and Pk,l , communicate in mapping generated by phase one and if in the new mapping Pi,j is split into Pm,n and Po,p; then, in the new mapping, it is assumed that Pm,n and Po,p communicate with Pk,l and no quali.cation about the communication is made.
Relationship: entailment
Domain: Hardware
Sentence 1: (3) Rl2 + rpu2 + rpv2 Rl2 +( .2 )rpu2 +( .3 )rpv2 .1 .1 Therefore, if we choose .1 = .2 and .1 = .3, we will be able to satisfy (3).
Sentence 2: l2 can be made more e.ective than l1 by selecting a much smaller link than the minimum length link l1 between all sink pairs of subtrees Ti and Tj .
Relationship: entailment
Domain: Hardware
Sentence 1: (10) Vt |Bk-1 ,Bk That the bits are uncorrelated and equally likely to be a zero or a one yields a simpli.cation for a pair of terms in the above pair of equations.
Sentence 2: f k-1 (v|1, 1)P (Bk =1|Bk-1 =1)= Vt |Bk-1 ,Bk 1 fV k (v|1) t |Bk 2 f k-1 (v|0, 0)P (Bk =0|Bk-1 =0)= V |Bk-1 ,Bk t 1 fV k (v|0), (11) t |Bk 2 whereweexploited thefactthatif Bk = Bk-1 , there is no edge between the kth and k - 1th bit.
Relationship: entailment
Domain: Hardware
Sentence 1: Copyright 2012 ACM 978-1-4503-1492-3/12/10 ...$15.00.
Sentence 2: various recon.gurable or even evolvable hard­ware models promising scalable distribution of parallel pro­cessing tasks have emerged [21, 14] Typical recon.gurable hardware implementations sepa­rate the memory and combinational component through the use of look-up tables (LUTs) where arbitrary logic functions are performed by looking up their values in fast memory [6] grouped usually in blocks of SRAM.
Relationship: entailment
Domain: Hardware
Sentence 1: To find a good metric for estimating the balance of excitation, we need to consider how to maximize the probability of detection for an unmodeled defect with arbitrary detection requirements.
Sentence 2: if we have no knowledge about what type of defect is present, then we cannot say with certainty that any particular site should be equal to either a one or a zero to excite that defect.
Relationship: entailment
Domain: Hardware
Sentence 1: As can be seen from Table 1, even with the presence of some boundary-constrained modules, our algorithm could still obtain placements of very high quality.
Sentence 2: our algorithm was always able to generate placements of even better quality for 2 test cases (i.e., ami49 and random1), and of the same or comparable quality for 5 test cases (i.e., apte, xerox, hp, and ami33, random2).
Relationship: entailment
Domain: Hardware
Sentence 1: Thirdly, the end-to-end delay of a connection gives a global 50 40 30 Transmission Probability Figure 15: Delay of the dynamic (K =1) and static (K =0) cases for K=4 (Connections b and c of the asymmetric network of .gure 11) 70 vision on the stability of nodes that forms this connection.
Sentence 2: it is mainly a.ected by the waiting time on the 65 forwarding intermediate queues.
Relationship: entailment
Domain: Hardware
Sentence 1: After the root sets are computed, we compute the MFFS that is below the k-feasible cut.
Sentence 2: the MFFS can be cov-ered by the EMB regardless of whether I input(MFFS(m-root))[> k. the MFFS(m-root) below the cut is guaranteed to be k-feasible because only k inputs in the cut set are needed to generate the MFFS outputs.
Relationship: entailment
Domain: Hardware
Sentence 1: Evolving software architectures in such scenarios is very challenging [6, 21].
Sentence 2: existing methods and tools for identifying and evaluating suitable architectural changes were devised for use as part of o.-line Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: entailment
Domain: Hardware
Sentence 1: We demonstrated quantitatively that previously proposed DVFS performance predictors, designed with an over-simpli.ed view of the memory system (e.g., assuming a constant access latency or disregard­ ing prefetching), generate inaccurate performance predictions and lose out on potential energy savings.
Sentence 2: we have shown that the commonly used linear DVFS performance model breaks down in the presence of prefetching because it does not account for .nite memory bandwidth.
Relationship: entailment
Domain: Hardware
Sentence 1: As no explicit bit-.eld speci.cation is given in its SE-MANTICS section, the expression shares the speci.cation of the operands.
Sentence 2: the addition of two operands (a, 0, 32) and (b, 0, 32) results in the 3-tuple (c, 0, 32), where c is the re­sult of the 32-bit addition of a and b.
Relationship: entailment
Domain: Hardware
Sentence 1: 30.0% In the near future, we will focus on finding an Sp eed up 20.0% 10.0% 0.0% arbitrator to decide whether to select helper threaded or in-thread cache prefetching optimizations based on profitability analysis.
Sentence 2: since some programs sped up by helper threading can also be sped up by in-thread prefetching, the dynamic optimizer may favor in-thread optimization when the other on­ -10.0% Figure 11.
Relationship: entailment
Domain: Hardware
Sentence 1: The following observation is immediately inferred from the above theorem: The delay of each path in the optimal solution from the primary input node s to primary output node t is equal to T. Now that the distance of every node to the destination is independent of the path taken, let ti be a variable assigned to each node vi that represents its distance to t. We call ti the distance variable of node vi.
Sentence 2: ti is the delay of the system from node vi to the output.
Relationship: entailment
Domain: Hardware
Sentence 1: This ratio drops to 10.8%, 4.4%, 0.4%, and 0.06% after 10, 100, 1,000, and 10,000 cycles after going into the AR state, respectively.
Sentence 2: if we wait long enough, it is likely that contents of a given physical register are dead, and thus can be used for holding the duplicate of an active register.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION Recently, ultra low voltage (ULV) operations, where the supply voltage of CMOS circuits is scaled down to near or below the threshold voltage (VT) of transistors, have gained a significant amount of attention due to 5-20× energy savings.
Sentence 2: uLV operations can benefit many energy-constrained applications such as implantable medical devices, remote surveillance systems, wireless sensor networks, and mobile electronics [16].
Relationship: entailment
Domain: Hardware
Sentence 1: When a new fault is detected in a group already containing a fault in the current partition con.guration, a re-partition, or selecting another partition con.guration in the set, is required to resolve the fault collision.
Sentence 2: the minimal requirement on any partition scheme is to ensure separation of two faults in a group into two di.erent groups by switching to another partition con.guration.
Relationship: entailment
Domain: Hardware
Sentence 1: Such a computation can be performed in constant time for all the networks, except for binary trees which require log- arithmic time in the number of vertices.
Sentence 2: the 0 1 2 3 4 5 6 'bit 1 0 1 0 I" 1 W 1 2 '2 1 0 1 2 S -1 -1 3 1 3 -I Table 3: The vectors bit, W, and $ computed by the Tree-6-L(2, 1, 1)-coloring algorithm to color ver-tex u = (6, 43).
Relationship: entailment
Domain: Hardware
Sentence 1: An Efficient Approach to Generic Multimedia Adaptation Joseph Thomas-Kerr Ian Burnett Christian Ritz W hisper Laboratories, School of Electrical Computer and Telecommunications Engineering, University of W ollongong, W ollongong NSW Australia 2522 +61 (2) 4221 3065 joetk@elec.uow.edu.au i.burnett@elec.uow.edu.au chritz@elec.uow.edu.au ABSTRACT This paper addresses efficiency issues identified in the Bitstream Syntax Description Language used by the MPEG-21 generic multimedia adaptation framework.
Sentence 2: when used to adapt modern content formats such as H.264/AVC, AAC, and SLS, the time required for processing increases exponentially relative to the duration of the bitstream.
Relationship: entailment
Domain: Hardware
Sentence 1: For example, if the simulation trace records values of (1,1,1,1,0) fori2[0] (the first bit of i2), while the mapping function given by([0] AND [1]) evaluates to (0,0,1,1,1), the differ­ence in evaluated and expected outputs is captured by (1¯ 0, 1¯ 0, 1¯ 1, 1¯ 1, 0¯ 1) = (1,1,0,0,1).
Sentence 2: the likelihood oferror in estimation due to the use of this mapping function is 0.6.
Relationship: entailment
Domain: Hardware
Sentence 1: Since db performs insertions and deletions between sorts the set sizes used in two di.er­ent sorts may be di.erent and thus di.erent sorts will have slightly di.erent behavior; (ii) Our sampling frequency was not high enough to take at least one sample for every change in set size.
Sentence 2: if we did not have a sample at set size of 5081 we could not con.rm that the IPC did indeed start to drop at 5081.
Relationship: entailment
Domain: Hardware
Sentence 1: We predicted that leakage would get much higher for optimized 0.18 and 0.13 um technologies and therefore designed the library to combat this increase.
Sentence 2: for the design of wide domino nodes and array and register file structures, we went with segmented bit-line architecture and disallowed circuits with large numbers of parallel pull downs (except PLA waivers).
Relationship: entailment
Domain: Hardware
Sentence 1: Tbase(t)= Execution time without any energy management until the same point in the program.
Sentence 2: delay(t)= Absolute increase in execution time due to en­ ergy management = t - Tbase(t) Delay(t) Delay(t)  Actual percentage slowdown = *100 = *  t-Delay(t) Tbase 100 The constraint that must be ensured by the performance-guarantee algorithm is Actual slowdown = Slowdownlimit.Delay(t) * 100 = Slowdownlimit t - Delay(t) So conceptually, the only unknown to be determined is the delay.
Relationship: entailment
Domain: Hardware
Sentence 1: DYNA M IC RE C O N FI G U R AT I O N O F T H E VR-TO-CO RE NE TW OR K Modern VRs exhibit high peak power ef.ciency with a spe­ci.c load current value, but their ef.ciency drops dramatically under adverse load current conditions, as addressed in the pre­vious section.
Sentence 2: a state-of-the-art VR powering a set of cores may have low conversion ef.ciency when there is a mismatch between the VR characteristics and the load condition of the cores.
Relationship: entailment
Domain: Hardware
Sentence 1: Thus, as we recall (33), this comparison will not hold if we can show that Ca(N)Na · min p *a(i)<1.
Sentence 2: (47) i=1,...,N In each case, we show under the appropriate conditions on M and N that (47) indeed holds for large enough values of a.To do so, we shall have repeated use for the next elementary lemmas where asymptotic equivalence is de.ned as follows: For mappings f(a) f,g :IR+ .IR, we write f(a)~g(a)if lima.8 g(a) =1.Ca(N)~1.
Relationship: entailment
Domain: Hardware
Sentence 1: In practice, the appropriate value of M should be determined by exploring the trade-offs between the accuracy of thermal monitoring and the overhead of circuit design.
Sentence 2: if a lot of temperature sensors are used (i.e., M is large), we can achieve high accuracy of thermal map estimation; however, the design overhead (e.g., the silicon area and the power consumption associated with the temperature sensors and their peripheral circuits) is also large.
Relationship: entailment
Domain: Hardware
Sentence 1: POST-SILICON TUNING eL , (28) +  In this section, we further extend BMF to the application of m=1 post-silicon tuning.
Sentence 2: we focus on the problem of where eL denotes the modeling error: tuning policy generation with consideration of large-scale process eL 2 ...... 1 Gauss(0,s) () eL 2 pdf · - (29) shift over time.
Relationship: entailment
Domain: Hardware
Sentence 1: This paper quantifies general-purpose overheads, exploring a series of customizations that reduce overheads to achieve ASIC-like efficiency.
Sentence 2: we consider three broad strategies: (1) techniques to exploit instruction- and data-level parallelism, such as VLIW and SIMD, (2) techniques to customize instructions by fusing complex, frequently occurring instruction sub-graphs, and (3) techniques to create application-specific data storage with fused functional units.
Relationship: entailment
Domain: Hardware
Sentence 1: The number of clusters is added by one, if the next point causes a sharp transition in the error curve.
Sentence 2: we propose to use the following quantity to measure the transition rate: 26 ()=log y -log()-[]()-log y , (26) ( ) y log y ( ) s c [] c +1 c cc -1 where yc-1, yc and yc+1 are the values of the evaluation metric at x = c-1, x = c and x = c+1, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: For this, we consider equivalent for logic synthesis (although this might not be perfectly true in every case) any factorization that di.ers only in the way a subexpression is factorized.
Sentence 2: two descrip­  getPareto (function f=(E1, E2)) { tions are not equivalent for us if at least one of the CSEs Set S= f; shared by two or more functions in one of the descriptions Set F= f; is di.erent from all CSEs in the other description.
Relationship: entailment