sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Moreover, be­cause the manufacturing cost is proportional to the number of routinglayersusedfor both chipsand packages, a good I/O placement not only helps to achieve design closure, but also reduces the number of layers.
Sentence 2: because of the ever-increasing requirement for functionality, the number of I/O cells in a single die keeps increasing, rendering tradi­tional manually tuned I/O placement extremely di.cult.
Relationship: contrasting
Domain: Hardware
Sentence 1: Actually, property coverage is still an open issue and a not sedimented subject.
Sentence 2: simulation based functional veri.ca­tion techniques [11, 10, 24] show the following problems:  By this technique it is not possible to distinguish be­tween hard to detect faults, which represent hard to verify states in the functional interpretation, and the real design errors because in both cases the faults re­sult undetected.
Relationship: contrasting
Domain: Hardware
Sentence 1: The third and last tile is the Input tile; this tile consists of a vertical wire to connect the two horizontal wires at the other end, such that the memory loop is formed.
Sentence 2: it is di.erent from the Output tile, because prior to transfer­ring data, the old memory state must be multiplexed with the input data (this is dependent on the Write control sig­nal).
Relationship: contrasting
Domain: Hardware
Sentence 1: It can also be seen that all three classi.ers perform well in identifying a browsing circuit, as their F-measure for the browsing class rangesfrom0.83forBayesNetsto0.97forFT.FTandLMT classi.ers also performvery wellin identifyingBitTorrent circuits.
Sentence 2: theyboth achieve around 0.71 for the streaming class.
Relationship: contrasting
Domain: Hardware
Sentence 1: Assuming that the threshold voltage is a continuously varying parameter, the optimum threshold voltage to satisfy both the Ron-req and Wmax constraints is given by: L VtX = Vdd - (6) µn * Cox * Ron * Wsleep So intuitively, we can achieve the required on-resistance Ron-req with a lower value of Wmax and with a lower threshold voltage VtX .
Sentence 2: the constraint on VtX is VtL = VtX = VtH .Here VtL and VtH are the low threshold and high threshold voltages of the transistors present in the design library.
Relationship: contrasting
Domain: Hardware
Sentence 1: For both the read and write cache, we initially select a block to be evicted using an LRU pol­icy on disk cache capacity misses (for the read cache) or capacity writes (out-of-place writes that need to .rst erase blocks, for the write cache).
Sentence 2: if this block wear out exceeds that of the newest block by a predetermined thresh­old, then the block corresponding to the minimum wear out (newest block) is evicted to balance the wear-level.
Relationship: contrasting
Domain: Hardware
Sentence 1: Main application of TVP was mixed-signal/RF/analog circuits and it was used there for mixers and switched­capacitor .lters.
Sentence 2: if appropriately adapted, TVP is highly applicable to analysis and optimization of power supply network and substrate noise analysis, i.e., reduction of large digital logic blocks for SSN and IR drop prediction purposes, as we develop and demonstrate here.
Relationship: contrasting
Domain: Hardware
Sentence 1: In PriSM, the replacement process has two steps: (1) Partition-Selection: choose a partition according to the pre-calculated eviction probability distribution and then (2) Victim-Identi.cation: choose the victim that belongs to the partition selected by the partition-selection step.
Sentence 2: there is a possibility of abnormality that no replacement candidate belonging to a partition identi.ed by the partition-selection step.
Relationship: contrasting
Domain: Hardware
Sentence 1: For this case, if the connected VWS is .xed by diode insertion, the collected charges of Ci can be discharged through the inserted diode, and thus will not cause any antenna violations.
Sentence 2: if the connected VWS is .xed by jumper insertion, the collected charges may still cause the antenna violation, since jumper insertion will not create any discharging paths.
Relationship: contrasting
Domain: Hardware
Sentence 1: Recognizing that the impact of the coupling of TSVs is non-negligible, many studies have reported methodolo­gies for reducing TSV-to-TSV coupling [3] [5] [2].
Sentence 2: these studies have mostly focused on the impact of TSV-to-TSV cou­pling on only single TSV-pair cases and not on multiple TSV-pair cases [5].
Relationship: contrasting
Domain: Hardware
Sentence 1: The algorithm described in [7] compresses the supply currents of M current sources into C compression sets, with a higher compression than a single-cycle for a single compression set, assuring also a user-specified error bound.
Sentence 2: this algorithm can result in a high number of compression sets, which is not acceptable for our optimization, as the number of compression sets is highly dependent on the temporal locality and periodicity of the currents across different clock cycles.
Relationship: contrasting
Domain: Hardware
Sentence 1: Categories and Subject Descriptors B.0 [Hardware]: General; B.4 [Hardware]: In­put/Output and Data Communications; H.5.m [Information Interfaces and Presentation (e.g., HCI)]: Miscellaneous General Terms Design, Human Factors, Measurement Keywords Air Quality Sensing, Mobile Participatory Sensing  1 Overview Data about air quality could enable important advances in medicine, science, and policy.
Sentence 2: only limited air quality readings are currently available.
Relationship: contrasting
Domain: Hardware
Sentence 1: An exhaustive search on di.erent 4-bit to 6-bit mappings was done and none of the mappings could eliminate Class 5 and Class 6 crosstalk on all of the three above-mentioned transition  Figure 2: Data transmission Figure 1: Bench-mechanism usedinthe TCS mark-wise CTV coding technique for both address and data buses points.
Sentence 2: the TCS encoding given in Table 2 satis.es the following theorem.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, in Cholesky with 20% slowdown limit, AVG signi.cantly violates the performance guarantee, de­grading the performance by up to 120%.
Sentence 2: sUM method is very conservative and under 10% slowdown limit it can always guarantee the performance degradation within 3%, but as we will show in the next subsection, it does not e.ectively save energy consumption.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example in Figure 2, if CAC (1,1) receives a grant, then no other CAC in row 1 (CACs (1,j)) and column 1 (CACs (i,I)) can be granted.
Sentence 2: if CAC (1,1) is not granted, then the priority is passed on to the CACs in its row and column, in the positive-x- and positive-y-direction respectively.
Relationship: contrasting
Domain: Hardware
Sentence 1: In contrast, if a misprediction is detected in the OXU, the misprediction penalty is increased by the number of the stages of the IXU, which is usually four or .ve, because its pipeline length is prolonged.
Sentence 2: more than 50% of instructions are executed in the IXU (Section VI), and thus, the total penalty is reduced.
Relationship: contrasting
Domain: Hardware
Sentence 1: requiring a minimum space between any shifter and the cell boundary) can be verified using DRC techniques.
Sentence 2: guarantees of composability by placing buffer space around cell boundaries become increasingly costly in terms of density: the economic requirement for phase composability arises because it becomes meaningless to waste several line pitches around each cell boundary and significantly effect design density purely in the interest of composability (the alternative is a very narrow process window which is also economically bad).
Relationship: contrasting
Domain: Hardware
Sentence 1: This is avoided by Globally Asynchronous Locally Synchronous (GALS) [2] architectures, where di.erent parts of a chip are clocked by di.erent clock sources &#38; clock trees.
Sentence 2: using independent and hence unsynchronized clock domains gives away the advantages of global synchrony and thus requires non-synchronous cross-domain communication mechanisms or synchronizers [4, 13, 21].
Relationship: contrasting
Domain: Hardware
Sentence 1: For instance the authors of [17], present design methodologies for partitioning an NoC architecture into multiple VFIs and assigning frequency, supply voltage, and threshold voltage levels to each VFI according to given performance constraints at design time.
Sentence 2: there have been many works that propose hardware-based approaches to dynamically change the frequencies and potentially voltages of a VFI system driven by a dynamic workload [6][9].
Relationship: contrasting
Domain: Hardware
Sentence 1: Floorplan awareness allows to account for speci.c .oorplanning techniques that optimize wiring of a given topology, and therefore leads to more conservative estimations of the wiring overhead.
Sentence 2: this is still far away from real-life, wherethepost-layout report of total wire length gives only a 10% overhead of the 4-hypercube wiring with respect to 2D mesh one and a 43% with respect to the 2-ary 2-mesh.
Relationship: contrasting
Domain: Hardware
Sentence 1: As long as x1 is unknown, the two one-time pads are ob­served by an attacker as independent random pads, assum­ing the hardness of the Decisional Di.e-Hellman problem.
Sentence 2: if x1 is known to an attacker (which will be the case when he is a strong attacker), the two one-time pads are equivalent, which violates its one-time use.
Relationship: contrasting
Domain: Hardware
Sentence 1: While due to the econom­ical development, in recent months a similar development among network providers in general (and especially mobile and core net­work operators) has occurred, this is not necessarily true for content providers as well.
Sentence 2: independent of market consolidation or fragmentation, any trend will have an in.uence on daily commu­nication in terms of the number of parties participating in a commu­nication.
Relationship: contrasting
Domain: Hardware
Sentence 1: The switching current is independent of the edge rate, so the cur­rents of interest are the short-circuit and leakage currents.
Sentence 2: our simulations do not show any signi.cant change in power dis­ 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 TL/R Figure 7: fk[R(f )L(f )C] and fh[R(f )L(f )C] as a function of TL/R.
Relationship: contrasting
Domain: Hardware
Sentence 1: Copyright 2002 ACM 1-58113-475-4/02/0008 $5.00 Most reported four-quadrant low voltage analog multipliers used cascoded differential input circuit to obtain larger output swing, but the architectures of the multipliers turned out to be more complicated.
Sentence 2: due to the complexity of the involved circuitry, they generally do not achieve a bandwidth wider than few tens of megahertz.
Relationship: contrasting
Domain: Hardware
Sentence 1: SPICE-like cir­cuit simulators, which are widely used in LSI design, em­ploy the Newton-Raphson (NR) method for solving mod­i.ed nodal (MN) equations.
Sentence 2: the NR method or its variants often fails to converge to a solution un­less the initial point is su.ciently close to the solution.
Relationship: contrasting
Domain: Hardware
Sentence 1: Tangible User Interfaces for 3D Clipping Plane Interaction with Volumetric Data : A Case Study Wen Qi Department of Industrial Design University of Technology Eindhoven Eindhoven, The Netherlands w.qi@tue.nl ABSTRACT Visualization via direct volume rendering is a potentially powerful technique for exploring and interacting with large amounts of scienti.c (i.e., volumetric) data.
Sentence 2: the available two-dimensional (2D) interfaces make three-dimen­sional (3D) manipulation with such data di.cult.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4C-2 Total Power Optimization Combining Placement, Sizing and Multi-Vt Through Slack Distribution Management * Tao Luo, David Newmark , and David Z. Pan Department of ECE, University of Texas at Austin, Austin, TX Advanced Micro Devices, Austin, TX tluo@ece.utexas.edu, david.newmark@amd.com, dpan@ece.utexas.edu ABSTRACT Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down.
Sentence 2: power and timing are often con.icting objectives during optimization.
Relationship: contrasting
Domain: Hardware
Sentence 1: Thisrequiresamoregeneralcachedesignthatallowsmul­tipleaddressinputsintoandmultipledataoutputsoutof thecache,requiringcaretokeepthesemultiplepathsfrom contendingwitheachother.Someofourdesigndecisions mayactuallyincreasethepowerconsumptioninthecache arrays.Second,weperformadetailedtiminganalysiswith theCACTIanalyticalmodeltodeterminetheimpactofour designoncacheaccesstime.Albonesi'sevaluationisfocused onpowerdissipation.Third,weevaluatetheperformance beneftsofthereconfgurablecacheorganizationforinstruc­tionreuse[23]formediaprocessing.Thus,weshowthat cachestoragecanbeusedtoimprovecomputationspeedfor mediaprocessing.Albonesifocusesonshuttingofpartsof thecachetosavepower,andfocusesonSPECbenchmarks.
Sentence 2: althoughwehavefocusedmainlyonreconfgurablecache organizationsforgeneral-purposeprocessors,theyareappli­cabletodigitalsignalprocessorsaswell.Therecentlyan­nouncedTexasInstrumentsTMS320C62xxseriesofproces­sorsincludesupportformemorysystemsthatcanbeconfg­uredascacheormemorydependingontheapplication.As discussedinSection5,reconfgurablecachescanbeusedfor suchapurposeaswell.ourreconfgurablecache organizationisgeneralenoughtoincludeotherapplications fortheSRAMarraysincludinginstructionreuse.
Relationship: contrasting
Domain: Hardware
Sentence 1: A lookup-table-based circuit-level simulator was implemented in [11], and an accurate physics-based compact model was developed in [12] using device-dependent curve­.tting.
Sentence 2: a major drawback of device-dependent models, either based on lookup tables or heavily-.tted equations, is that whenever the need to simulate a new device with a different design parameter arises, a complete set of device simulations are required to rebuild the model.
Relationship: contrasting
Domain: Hardware
Sentence 1: Furthermore, combinational cycles (called false paths in this setting) occur in high-level synthesis of circuits by sharing common subexpressions [42].
Sentence 2: as an example, consider the following equation (taken from [22]) where a system is to be implemented with large subsystems f and g: y = if c then f(g(x)) else g(f(x)) end The cyclic equation system shown in Figure 1 requires only one instance of f and one instance of g. any acyclic version requires at least two instances of f and g. Malik [22] was the .rst who presented algorithms for the elimination of combinational cycles.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4.2 Results analysis Surprisingly, Hadoop performed worse than we expected at the beginning of our evaluation, demonstrating not only a bad absolute performance, but also a quite poor scalabil­ity (over compute nodes), especially for a larger .le, see the analysis chart in Figure 6.
Sentence 2: the MPI imple­mentation demonstrated a good scaling on the whole range of the tested parallel con.guration.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, for an AHB slave monitor, a transfer has an address phase followed by a response phase: idle_trans -> (idle &#38; HSEL &#38; HREADY) , okay_resp; busy_trans -> (busy &#38; HSEL &#38; HREADY) , okay_resp; nonseq_trans -> (nonseq &#38; HSEL &#38; HREADY) , resp; seq_trans -> (seq &#38; HSEL &#38; HREADY) , resp; (HSEL indicates this slave is selected; HREADY is the handshake that indicates the address phase is complete.)
Sentence 2: the address and response phases are pipelined, so that the response phase of one transfer occurs at the same time as the address phase of the next transfer.
Relationship: contrasting
Domain: Hardware
Sentence 1: One goal of the quantization strategy for a cell, then, is to ensure that for every possible delay value determined by PV, at least one quantum is reachable by increasing delay from device aging.
Sentence 2: even to achieve this single goal, quanta placement is a non­trivial optimization problem, since the delay distribution and aging possibilities follow complex correlated PV and aging models that vary from gate to gate.
Relationship: contrasting
Domain: Hardware
Sentence 1: Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations Qin Tang, Amir Zjajo, Michel Berkelaar and Nick van der Meijs Circuits and Systems, Delft University of Technology e-mail: qintang@ieee.org Abstract To increase the accuracy of static timing analysis, the traditional nonlinear delay models (NLDMs) are increasingly replaced by the more physical current source models (CSMs).
Sentence 2: the extension of CSMs into statistical models for statis­tical timing analysis is not easy.
Relationship: contrasting
Domain: Hardware
Sentence 1: Design of Cyberphysical Digital Micro.uidic Biochipsunder Completion-Time Uncertainties in Fluidic Operations* Yan Luo , Krishnendu Chakrabarty , and Tsung-Yi Ho Electrical &#38; Computer Engineering Department, Duke University, Durham, NC 27708, USA Computer Science and Information Engineering Department, National Cheng Kung University, Tainan, Taiwan E-mail: {yan.luo, krish}@duke.edu; tyho@csie.ncku.edu.tw ABSTRACT Cyberphysical digital micro.uidics enables the integration of .uid­handling operations, reaction-outcome detection, and software­based control in a biochip.
Sentence 2: synthesis algorithms and biochip design methods proposed in the literature are oblivious to completion-time uncertainties in .uidic operations, and they do not meet the requirements of cyberphysical integration in digital micro.uidics.
Relationship: contrasting
Domain: Hardware
Sentence 1: RELATED WORK Forenergyefciency,schemeshavebeenproposedtoprech­argeonlyselectedportionsofthecaches.Forexample, wecouldemployaprechargingmechanismcalleddelayed precharging,whereprechargingisdelayeduntiltheaddress isgenerated.Theloworderaddressbitscanbeusedtodis­ablethecachebanksthatwillnotbeaccessed[5].Thus,only selectedbanks(onefromeachway)needtobeprecharged.
Sentence 2: thedelayedprechargingincreasesthememoryac­cesslatencyandincursaperformancepenaltyforbetter energyefciency.Alpha21164andthephasedcacheinthe SH3processor[8,5]usetechniquesthatprechargeandac­cessonlyselecteddataarraysforenergyefciency.Instead ofaccessingthetaganddataarraysinparallel,theaccess tothedataarrayisdelayedbyfrstprobingthetagarrays toselecttheappropriateset-associativewayinthedataar­ray.Then,thetaghitlinecanbeusedtoactivateonlyone dataarrayamongthediferentways.Thedelayedselective accessofthedataarraysalsoincursadditionallatencies.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is because, allowing the .ip-.ops at PS(1) to be fully controllable assumes all the states are possible at that boundary and hence guarantees ¬s is an invari­ant.
Sentence 2: pre-image computations usually have exponential complexity and it will be infeasible to compute them even for a 2PODEM backtraces from a given objective (say, Xv)and makes decisions on the primary inputs to justify it (i.e.
Relationship: contrasting
Domain: Hardware
Sentence 1: Then with constraint (7), all the other pcrq s are forced to be 0 automatically except for those of sites around (r * ,q * ).
Sentence 2: if the model is with centroid-based con­straints, pcrq s of sites far from (r * ,q * ) may still be nonzero because fractional pcrq may easily satisfy the centroid-based constraints.
Relationship: contrasting
Domain: Hardware
Sentence 1: and 2CS Dept., University of Virginia, 351 McCormick Road, Charlottesville, VA 22904 USA 3Grandis, 1123 Cadillac Court, Milpitas, CA 95035 USA 1,23 {an2z, cws3k, vm9u, gurumurthi, mircea}@virginia.edu, Eugene.Chen@grandisinc.com Abstract Spin-Transfer Torque RAM (STT-RAM) has emerged as a potential candidate for Universal memory.
Sentence 2: there are two challenges to using STT-RAM in memory system design: (1) the intrinsic variation in the storage element, the Magnetic Tunnel Junction (MTJ), and (2) the high write energy.
Relationship: contrasting
Domain: Hardware
Sentence 1: (10) In a traditional scheme, c3 would be obtained from c2 with a second AOI gate.
Sentence 2: noting that e2 = p2 · c1 and d3 = g3 +g2 +e2, the carry d3 can be obtained from c1using: d3 = a3 · b3 + a2 · b2 +(a2 + b2) · c1 (11) In domino logic, the implementation of (10) has a similar delay as (11) because the nfet stack height is equal in both gates.
Relationship: contrasting
Domain: Hardware
Sentence 1: tvn Property 4 shows that if the noise pulse is aligned earlier than its optimal alignment taiopt, the impact of the noise on the delay of the vic­ tim will be reduced and hence tvn = tvnopt.
Sentence 2: if the alignment of the noise is later than the optimal alignment taiopt, the noise will not impact the delay of the victim and hence tvn = tv.
Relationship: contrasting
Domain: Hardware
Sentence 1: The IEEE 1588 Precision Timing Protocol, for example, was developed because NTP, the de facto Inter­net time synchronization standard, was not precise enough for industrial measurement and control systems.
Sentence 2: iEEE 1588 requires sub-microsecond accuracies, a level of precision not attainedbyprior work[5,6],but well within the reach of current technology at a power draw that is di­gestible to many low-power wireless sensor network applica­tions.
Relationship: contrasting
Domain: Hardware
Sentence 1: The .rst issue is caused by the fact that data can only be read and written to an SSD in multiple of a .ash page (usually 2 or 4 KiB) because .ash pages are the atomic data transfer units from the perspective of .ash chips and the SSD controller.
Sentence 2: most operating systems work with 512 byte sectors as atomic unit because hard disks used to have sectors of this size for several decades.
Relationship: contrasting
Domain: Hardware
Sentence 1: BIST Design Optimization for Large-Scale Embedded Memory Cores * Tzuo-Fan Chien1, Wen-Chi Chao2, Chien-Mo Li1,2, Yao-Wen Chang1,2, Kuan-Yu Liao2, Ming-Tung Chang3, Min-Hsiu Tsai3, and Chih-Mou Tseng3 1Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan 2Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan 3Global Unichip Corporation, Hsinchu, Taiwan  ABSTRACT Built-in Self Test (BIST) is a crucial technique for testing embedded memory cores in a System-on-Chip (SoC).
Sentence 2: there is not much published work on BIST design optimization for multiple memory cores in the SoC designs.
Relationship: contrasting
Domain: Hardware
Sentence 1: Researchers have also proposed various approaches to optimize delay yield by tuning VDD/VT or choosing gates of di.erent drive strengths, for example in [7].
Sentence 2: functional yield was not consid­ered until [8][9], which address unsatisfactory VOH and VOL in sub-threshold inverters whose output levels are degraded by leaking devices, such as in a register .le.
Relationship: contrasting
Domain: Hardware
Sentence 1: Also the trees constructed by [10] do not consider the gate overlap between tree gates and non-tree gates, a re­placement/legalization step has to be applied to resolve the overlap issue.
Sentence 2: the placement step also changes non­tree gates and the wirelength measurement on restructured trees after re-placement/legalization can not directly re.ect the tree restructure quality.
Relationship: contrasting
Domain: Hardware
Sentence 1: Assume TSV2 is not faulty, and when TSV1 is also not faulty, TG2 will disconnect the redundant path from TSV2, and TSV2 s downstream capacitance will be calculated from wire in black dotted lines.
Sentence 2: when TSV1 is faulty, both TG1 and TG2 are turned on, and the   (b) TSV pairing (a) Dependency (c) Capacitance (d) Skew Fig.
Relationship: contrasting