sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: On Effective and Ef.cient In-Field TSV Repairfor Stacked 3D ICs* Li Jiang , Fangming Ye , Qiang Xu , Krishnendu Chakrabarty , and Bill Eklow§ Department of CS&#38;E, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong Deptartment of ECE, Duke University, Durham, NC §Cisco Systems, San Jose, CA  ABSTRACT Three-dimensional (3D) integration based on through-silicon-vias (TSVs) is rapidly gaining traction for industry adoption.
Sentence 2: manufacturing processes for TSVs have been shown to introduce new failure mechanisms.
Relationship: contrasting
Domain: Hardware
Sentence 1: As shown in Figure 8(b), these two operations are originally scheduled to be executed during dif­ferent time segments, hence the overlap of their corresponding modules will not lead to resource con.icts.
Sentence 2: if the start andstoptimeof OA are delayed due to a previous operation, and OA cannot be completed before the start of OB , then the over­lap of their corresponding modules will lead to resource con.icts.
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Domain: Hardware
Sentence 1: We can see from Figure 5 that between terminal sizes 20 and 100, the ratio is the high­est, meaning that the error is highest.
Sentence 2: from the Ckt Total Error (%) I/O Error (%) #Nets ErrN 4 alu4 apex2 bigkey dsip misex3 pdc s298 s38417 seq spla 2.95 -19.68 -21.45 11.08 4.49 13.44 -5.15 -32.42 4.66 -0.68 -2.24 29.10 34.47 -4.07 6.77 -14.70 0 -4.84 13.24 -14.34 1299 1616 1699 1367 1170 4051 1837 5955 1522 3329 223 262 8 3 227 524 94 451 228 361 Totals Average -11.6% -12.4% 23845 - 2194 - Table 1: Estimation of Bounding Box Spans plot below it, we can notice that these nets constitute less than 3% of the total number of nets.
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Domain: Hardware
Sentence 1: However, this de.nitely requires an excessive run time when the problem size is large.
Sentence 2: from the fact that each reschedule changes the execution order locally, causing a small change of edge weights in the access graph, and a path cover solution with a minimum C value for the previous sched­ule has already been known, it is natural to ask whether there is a way to .nd a path cover with a minimum C value for the current schedule rapidly by exploiting the previous path cover solution.
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Domain: Hardware
Sentence 1: The CDF graph in Fig­ure 10(a) illustrates that DTW(Sum)performs the best by far while TAM and FUS perform similarly to each other.
Sentence 2: figure 10(b) illustrates that DTW(Sum)is the best across all benchmarks while TAM and FUS beat each other for six benchmarks each.whenTAM beatsFUSitis usuallybya signi.cant amountandthus between thesetwo techniquesTAM is preferable.
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Domain: Hardware
Sentence 1: 3.1 OFFAS: OFFline Adaptive Scheduling For a task set TS whether is schedulable from a set of inequality, we want to get the maximum computation time Ci of ti (denoted as maxCi), by setting Ci as a variable.
Sentence 2: under the situation that ti is schedulable, we can get the maximum value from a list inequalities.the tasks with a higher priority extended computation time will a.ect the tasks with a lower priority.We must make sure that those tasks with a priority lower than ti are schedulable.So we must to compute the minimum value of all tasks with priority not higher than ti, then the maxCi is found.
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Domain: Hardware
Sentence 1: This new prop­erty makes PCM more competitive and considered as the suc­cessor of the NAND .ash technology, which also has the MLC capability but does not have an easy scaling path to reach higher densities.
Sentence 2: the MLC capability of PCM comes with the penalty of longer programming time and shortened cell lifetime compared to its single-level cell (SLC) mode.
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Domain: Hardware
Sentence 1: RTL Analysis and Modi.cations for Improving At-speed Test Kai-Hui Chang Hong-Zu Chou Igor L. Markov Avery Design Systems, Inc. Avery Design Systems, Inc. University of Michigan, Andover, MA, USA Andover, MA, USA EECS Department changkh@avery-design.com hzchou@hotmail.com Ann Arbor, MI, USA imarkov@umich.edu  Abstract At-speed testing is increasingly important at recent technology nodes due to growing uncertainty in chip manu­facturing.
Sentence 2: at-speed fault coverage and test-ef.cacy suffer when tests are not robust.
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Domain: Hardware
Sentence 1: In terms of static de­sign choices, this could lead to relatively simpler cores (and more cores per die over time), supported by thermal-aware .oor pl an­ning.
Sentence 2: that alone is not suf.cient; because, in order to deal with and exploit workload variability, improved methods for dynamic redistribution of power are needed to meet power and ther­mal envelopes, without giving up performance.
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Domain: Hardware
Sentence 1: In general, we require the slack S to be positive: S = RT - AT = 0 (3) In nominal static timing analysis, all the above timing quantities (AT , RT , S) are computed under the assumption that process and environmental parameters -and consequently timing arc delays which depend on these parameters -are .xed, typically at either their nominal or corner values.
Sentence 2: due to the increasing signi.cance of variability, parameterized static timing analysis (PSTA) techniques have emerged, with the goal of handling parameter variations as part of the timing analysis step.
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Domain: Hardware
Sentence 1: Nonetheless, in those use cases where only few cores have to run at high clock rates, they are appealing for the reduced operating speeds of many of their clock domains.
Sentence 2: their successful exploitation requires a proper up­grade of the power management and NoC mapping strate­gies (and, above all, their co-optimization) to work around slow intermediate network hops, although the performance­power trade-o.
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Domain: Hardware
Sentence 1: With 2-3X increase in power consumption and 2-3X improvement in time delays, the PDP of both technologies is shown to be the same in figure 10 for static logic style but it is still higher with dynamic logic style.
Sentence 2: if we compare the proposed dynamic logic cell in this work with the DRLC-7T from [12], it is clear that the POS-DRLC cell offers the minimum power consumption and it is also single­stage structure which has a direct impact on time delay and latency compared to a two-stage cell (DRLC-7T).
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Domain: Hardware
Sentence 1: The ad­vantages of this approach is that the timing of the cache can change with its con.guration while the main processor clock remains unaffected, and that no clock synchronization is necessary between the pipeline and cache/TLB.
Sentence 2: because a constant two-stage cache pipeline is maintained regardless of the cache con.guration, cache bandwidth degrades for the larger, slower con.gurations.
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Domain: Hardware
Sentence 1: Some literature discuss interconnect-related variations such as those in capacitance (C) and time constant (RC)of interconnects [2, 3].
Sentence 2: if we focus on the worst-case delay of a stage that consists of a driving gate loaded with interconnects and fan-out gates, it is necessary to consider not only interconnect variations but also transistor varia­tions at the same time.
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Domain: Hardware
Sentence 1: In recent years, several approaches have been proposed for optimizing either delay, power, or crosstalk noise in the presence of process variations by employing techniques like gate sizing, bu.er insertion, wire sizing, dual threshold volt­age assignment etc.
Sentence 2: due to device and interconnect scaling, a barrier has been reached where a change in one de­sign parameter signi.cantly impacts the other parameters, and hence, they can no longer be optimized separately.
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Domain: Hardware
Sentence 1: A discussion of parallel FIR .lters employing number theoretic transforms (NTTs) is given in [7].
Sentence 2: to the best of our knowledge the implications of using RNS on performance of MCM and constant-coef.cient .lters in general have not been suf.ciently studied yet, though such possibility was mentioned in [6], [18].
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Domain: Hardware
Sentence 1: Since we do not have a di.erentiable function relating the delay and area for an ar­chitecture, we approximate the elasticity as: % change in delay elasticity = .
Sentence 2: (2) % change in area When the elasticity is -1, meaning a 1% area increase achieves a1%performanceimprovement, the trade-o.be­tween area anddelayiscertainlyinteresting.based onconversationswith acommercialFPGA architect[4],we will viewthetrade-o.s as interesting whena3% areain­creaseisrequiredfora1%delay reduction(anelasticity of -1/3) and whena1% areaincreaseimprovesdelayby3% (an elasticity of -3).
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Domain: Hardware
Sentence 1: Faulty entries, basically randomly distributed, should be then disabled [23, 1] or replaced by error detection and correction schemes [23, 4].
Sentence 2: albeit all those disable­based and correction methods are e.ective from an average performance perspective and provide functional guarantees, they su.er from a common problem, i.e., they do not provide strong timing guarantees required for worst-case execution time (WCET) estimation as needed for critical applications in our target market [22].
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Domain: Hardware
Sentence 1: Thus, the number of blocks needed and the sup­ply voltage setting must be chosen at low temperature.
Sentence 2: 0.0001 1e-05 1e-06 1e-07 Power (W)  Supply Voltage (V) Figure 3: E.ect of Supply Voltage on Dynamic Power and Leakage Power 0.1 80 Figure 2: Organization of Temperature Dependent Deactivation 70 60 if we consider what happens at higher temper­ atures which invariably will be encountered during circuit operation, two facts are obvious: 1) the number of blocks 50 Number of BlocksPower (W) 0.01 40 30 would often be larger than needed, and 2) the circuit would be dissipating more power than needed.
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Domain: Hardware
Sentence 1: The semiconductor industry has made major research and development investments in low-k dielectric materials in response to this urgency.
Sentence 2: low-k materials suffer from poor mechanical and thermal properties, and achieving dielectric constants below 2 Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
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Domain: Hardware
Sentence 1: It can be demonstrated that, in presence of a mismatch 'C1 between C1a and C1b, the relationship between Vsamp and Vin is given by V samp 'C C p3 C p2 C p1 1 #1 .
Sentence 2: (2) V C 8C in 1 1 because the parasitic capacitances are much lower than C1, simulations have showed that the total harmonic distortion can be kept well under 90dB even in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 04) 1530-1591/04 $20.00 &#38;#169; 2004 IEEE the case of mismatches as high as 1% (at 5V).
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Domain: Hardware
Sentence 1: This de.nitely simpli.es the implementa­tion of the initial model as well as the subsequent HW/SW partitioning.
Sentence 2: these approaches are heterogeneous from the simulation point of view, since HW and SW can be executed by using di.erent simulators: the SystemC si­mulation kernel for the HW components and an ISS for the SW programs.
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Domain: Hardware
Sentence 1: Theobjetiveofthispaperistodemonstratehowguaranteed servies(bothper-fowandlass-based)anbesupported usingtheproposedBBarhiteture,despitethefatthatno QoSstatesaremaintainedatorerouters.Wefousonguar­anteedserviespartlybeausetheseserviesarewell-defned andunderstood,andpartlybeauseaunifyingorestate­lessframework.thevirtualtimereferenesystem[20].has beendevelopedthatprovidesaQoSabstrationofthedata planeforsupportingguaranteeddelayandrateservies.Us­ingguaranteedserviesasexamples,weillustratehowad­missionontrolanbeperformedusingtheproposedBB arhiteturewithouttheassistaneoforerouters.Inpar­tiular,wedevelopapath-orientedapproahtothedesign ofeÆientadmissionontrolalgorithmsundertheproposed BBarhiteture.Weestablishthattheproposedbandwidth brokerarhitetureisapableofsupportingguaranteedser­vieswiththesamegranularityandexpressivepower(ifnot more)astheIntServ/GuaranteedServiemodel,despitethe fatthatallQoSreservationstatesareremovedfromore routersandmaintainedsolelyatthebandwidthbroker.This isahievedwithoutthepotentialomplexityandsalability problemsoftheIntServmodel.
Sentence 2: thebandwidthbrokerapproahtoQoSprovision­ingintroduesasetofnewissues.Inpartiular,thesala­bilityoftheBBarhiteture.itsabilitytomanagealarge numberofQoSontrolstatesandproessalargevolume ofuserfowQoSrequests.isanimportantissuethatmust beinvestigated.Topartiallyaddressthisissue,inthispa­perwealsoonsiderthesupportofoarse-grainlass-based guaranteedserviesusingtheproposedBBarhiteture.Via fowaggregation,thenumberofQoSstatesmaintainedby theBBanberedued,andtheomplexityofadmission ontroloperationsanbelowered,therebyenhaningthe proessingapaityoftheBB.intheontextof guaranteedservies,(dynami)fowaggregationanhavean 1 undesirabletransientefetthatmayresultindelaybound violation,ifproperareisnottaken.Weillustratehowthis problemanbesolvedusingrelativelysimplemehanisms undertheproposedBBarhiteture.
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Domain: Hardware
Sentence 1: With reference to the three-line bus in Figure 4, for the intermediate line for level­signaling as opposed to pulse-signaling a 010 pattern followed by a 101 pattern results in worst-case coupling as a result of alter­nate bus lines switching in opposite directions.
Sentence 2: for pulse­signaling this critical pattern (in view of the high energy associ­ated with it) simply cannot occur by construction.
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Domain: Hardware
Sentence 1: Thus, using the result of Proposition 2 [8], the set of polynomials G1 = { f1,..., fs} is a Gr ¨obner basis for J.Note q q that G0 = { x1 - x1,...,xd - xd } is a Gr¨ obner basis for J0.
Sentence 2: we have to compute a Gr ¨obner basis of J + J0 = q q .
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Domain: Hardware
Sentence 1: Priorworkhasproposedcompiler-basedtechniques(e.g.,[10,42, 54])tomitigatethenegativeimpactofpollutionandthrashingby eithermodifyingthedatalayoutorbyprovidinghintstothehard­ware e.g.,non-temporalload/storeinx86[14].
Sentence 2: the scopeofsuchtechniquesislimitedtocaseswherereuseand/or localityofaccessescanbesuccessfullymodeledbytheprogram­mer/compiler,whichoftencorrespondstoarrayaccesseswithin loopnests.OurEAF-cacheproposalcanpotentiallyimproveper­formanceforamuchbroadersetofmemoryaccesses,andhence complementsthesecompiler-basedtechniques.
Relationship: contrasting
Domain: Hardware
Sentence 1: We compared our method against the SAT-based timing-aware ATPG tool PHAETON [18] (based on our re-implementation, which might not directly re.ect the actual performance of the original tool) and a commer­cial ATPG tool for TDFs.
Sentence 2: attempts were made to have a fair setting on the commercial tool for comparison.
Relationship: contrasting
Domain: Hardware
Sentence 1: The approach appears to provide valuable bene.ts: optimizations to complex designs can be evaluated directly in hardware, at speeds hundreds of times faster than sim­ulation, with e.orts apparently limited only to the devel­opment of the new components.
Sentence 2: current FPGA toolchains that allow quick deployment of system-on-chip designs still have troubles when implementing multiproces­sor designs.
Relationship: contrasting
Domain: Hardware
Sentence 1: AnN­impliantisanon­homogenouspassimpliantwho oversboth0'sand1'sintheKarnaughmap,butallthe1's werepreviouslyoveredbyotherimpliants.Thisdoesn't neessarilymeanthatnoneofthe0'sarepreviouslyovered, theonlyrequirementisthatatleastonemintermwasleft unoveredbypreviouslyhosenimpliants.Itspassvariable isaliteral,butasinglebranhmadeofNMOStransistorsis requiredtoimplementit.Thereasonbehindthisisthatonly "good"0'shavetobepassedbythisimpliant,sinepassing the"good"1'sisalreadytakenareofbypreviouslyhosen impliants.So,aredundantPMOStransistorsbranhis eliminated.SamedefnitionforP­impliants,forwhomall 0'swerealreadyovered,andisimplementedbyasingle PMOStransistorsbranh.NotethatN­andP­impliants anonlybedefnedduringtheminimizationproess,after theKarnaughmaphasbeenpartlyovered.
Sentence 2: itisworthnotiingthatN­andP­impliantsrequireonly asingletransistorbranhtoimplement,sameasforthe homogenousimpliants.homogenousimpliants passaonstant,either0or1,sotheydon'taddextraa­paitiveloadtotheinputsignalassoiatedtoapassvariable.
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Domain: Hardware
Sentence 1: INTRODUCTION In the context of nanoscale CMOS computing architectures, the quadruple mastery of power, performance, cost and reliability appears almost as impossible as squaring the circle.
Sentence 2: the emergence of four-terminal devices, with complementary intrinsic properties, responds to device-level expectations with favorable benchmark figures against Si-CMOS transistors, and shows the potential to provide novel logic blocks for digital architectures.
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Domain: Hardware
Sentence 1: The model retains its accuracy because determination of the delay, area, and power are carried out using low level circuit estimation of resistance and capacitance of intercon­nect components such as wires, repeaters, bu.ers, and .ops using HSPICE[3].
Sentence 2: these and other technology and voltage dependent parameters are precomputed for di.erent technology nodes and voltage steps.
Relationship: contrasting
Domain: Hardware
Sentence 1: {fwchen, chensl}@cs.nthu.edu.tw,g9662586@oz.nthu.edu.tw, tingting@cs.nthu.edu.tw  Abstract To guarantee that an application speci.c integrated circuits (ASIC) meets its timing requirement, at-speed scan testing becomes an indispensable procedure for verifying the per­formance of ASIC.
Sentence 2: at-speed scan test suffers the test-induced yield loss.
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Domain: Hardware
Sentence 1: The last of these, for exam­ple, constitutes a significant drawback for piezoelectric FBAR resonators, for which resonance frequency is determined by thick­ness rather than lateral dimensions, making it difficult to specify multiple frequencies on a single-chip via CAD layout.
Sentence 2: the frequencies of the capacitively-transduced devices in Table 1 are governed by one or more lateral dimensions, allowing a de­signer to specify a frequency via CAD layout, and more impor­tantly, allowing automated specification of a larger circuit of resonators with varying frequencies, all on a single chip.
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Domain: Hardware
Sentence 1: A small amount of PF (10%-20%) provides adaptivity for higher load balancing and resource utilization for each individual benchmark, while larger amounts of PF begin to starve the system of the improved performance ef.ciency of the ASIC ABBs.
Sentence 2: even the small performance improvement initially seen with the addition of PF is not enough to counterbalance the reduction in power-ef.ciency as ASIC ABBs are replaced by PF.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4.3, a.ecting the con.ict miss probability.
Sentence 2: since the LRI policy chooses the M slot to be evicted in a periodic manner, we will eventually be able to evict these With a probability roughly equal to (1 - e - c 1 )k (0.024 for stale key-value pairs and also cleanup their G slots.
Relationship: contrasting
Domain: Hardware
Sentence 1: The Fully-Bu.ered DIMM (FBDIMM) architecture [12] is characterized by non-uniform access time to DRAM banks, which is similar to CHARM from the viewpoint of a mem­ory controller.
Sentence 2: an increase in latency and power consumption incurred by Advanced Memory Bu.ers in FB-DIMM limits its applicability compared to CHARM.
Relationship: contrasting
Domain: Hardware
Sentence 1: Addition network In fact, the number of speci.ed carries in column 2, 2 c=1, cannot be observed on the physical carry signals x C1,1 and C1,2 using BCP.
Sentence 2: a key observation is that the structure of the addition network can be rearranged us­ing commutative and associative laws such that BCP spec­ 2 i.es ccarries.
Relationship: contrasting
Domain: Hardware
Sentence 1: It is possible to partition C into a sub­set C0 that consists of all the stuck-at 0 faults in C , and a subset C1 that consists of all the stuck-at 1 faults in C .
Sentence 2: we note that fault collapsing can remove more stuck-at 0 or more stuck-at 1 faults, depending on the cir­cuit.
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Domain: Hardware
Sentence 1: [2] views the chip-wide variation as a stochastic process and proposes using the Karhunen-Loéve Expansion (KLE) to extract a small set of uncorrelated random variables, which can then be used as parameters for the gate timing models.
Sentence 2: the approach is restricted to a theoretically simple, but physically unrealistic, cor­relation kernel, and no generic method is proposed to handle any realistic kernel extracted from process data (e.g., as per [1]).
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Domain: Hardware
Sentence 1: Naturally, such protection tricks work as a placebo effect, and do not provide any information on the EMF they represent cultural fears.
Sentence 2: some artists have explored the playful side of exposing ambient signals for example, Haruki Nishijima runs around with a butterfly net antenna to catch and archive broadband RF background, and Toshio Iwai sonified modulation in common background lighting using a portable device made by connecting an amplified photodiode to a speaker in his 2001 installation called Photon.
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Domain: Hardware
Sentence 1: The best re­sults are obtained with the UDDC-B with an average tra.c reduction (using the geometric mean) by a factor of 1.85 for 4kB caches.
Sentence 2: compared to the DDC and the UDDC-A, this organization has the largest tag implemen­tation cost, since every smaller block needs to be tagged.
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Domain: Hardware
Sentence 1: Delft University of Technology Postbus 5031, 2600 GA,Delft TheNetherlands  ABSTRACT In this paper, we compare the architectural perspectives of theWaveFieldSynthesis(WFS)3D-audioalgorithm mapped on three di.erent platforms: a General Purpose Processor (GPP), aGraphicsProcessorUnit(GPU)and aFieldPro-grammableGateArray(FPGA).Previousrelated work re­veals that, up to now, WFS sound systems are based on standard PCs.
Sentence 2: on one hand, contemporary GPUs consist of many multiprocessors that can process data con­currently.
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Domain: Hardware
Sentence 1: Until recently, a unified model that can handle the most common phenomena that designers care about hasproven elusive.
Sentence 2: with the recent invention of an electrical, current source-based cell model applicable to timing and noise flows by Croix and Wong in [5], and extensions of this model by other researchers [6]-[11], a unified, electrical model for handling most of these effects isin sight.
Relationship: contrasting
Domain: Hardware
Sentence 1: This implies at least k-miss-competitiveness (of these two) relative to any online algorithm.
Sentence 2: pLRU(4) and PLRU(8) are not k-miss-competitive relative to LRU(4) and LRU(8), respectively, for any k. This is the investigated k. We have proven the generalization to arbitrary k by hand (see [3]).
Relationship: contrasting
Domain: Hardware
Sentence 1: Hybrid memory units such as the GPU s shared, con­stant, and texture memories present access patterns that are unfa­miliar and unintuitive to programmers and thatfavor speci.c, spe­cialized mappings.
Sentence 2: code optimized for specialized access patterns may not perform well or be portable across multiple ven­dors platforms and different hardware generations.
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