sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Also, all the other contending flows of Fi may have to send a packet before this flow.
Sentence 2: the total delay for a packet from Fi to reach the input buffer of the first switch is given by: ui0 = MAX (Ui0 ,U0I(x))+ .x U0I(x), with x = 1 ... z0(i, 0) (3) j For the subsequent hops, ui can be calculated similarly: jj ui = MAX (Ui , Uj I(x))+ .x UjI(x) with x=1 ... zc(i,j),1= j= hi (4) Please note that, if there is no contention for the flow, then the above equation reduces to uij = Uij .
Relationship: reasoning
Domain: Hardware
Sentence 1: We have chosen these sizes because as Table 3 shows, the storage overhead for the L2 cache con­.guration considered is about 7kB for the static SBC and about 13 kB for the dynamic SBC.
Sentence 2: the 8kB and the 16kB victim caches are larger than the static and the dy­namic SBC respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: Secondly, if h(x) is admissible, meaning that it never overestimates the actual cost from the current node to the target node, then A* search is optimal.
Sentence 2: for the Manhattan routing (i.e., only horizontal and vertical connections allowed), h(x) is usually set as the Manhattan distance from any visiting node to the target, because it is the smallest possible distance between any two points in the Manhattan space.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then, we consider partial ii differentiation of (with respect to xjand j, giving the optimality conditions of CS.
Sentence 2: for l<j<ni, () ; ;; ; (/ xj#f 2 ek lxj x ;; ;;;;; kjkj kj () ;; + wjw)# (8) ;;;;; kjkj () ; ;; ; (/ Yj#f2eklYj Y ;; ;;;;; kj kjkj () ;; + hh)# (9) j ;;;;; kjkj ii where leldenotes the number of the pins of e. kkIn Equation (8), there are niequations with nivariables.
Relationship: reasoning
Domain: Hardware
Sentence 1: At the same time, replicating a block in adjacent L2 slices offers virtually no latency benefit, as multiple replicas are one network hop away from a core, while having just one copy nearby is enough.
Sentence 2: replication should be done at a coarser granularity: R-NUCA logically divides the L2 into clusters of neighboring slices, replicating instructions at the granularity of a cluster rather than in individual L2 slices.
Relationship: reasoning
Domain: Hardware
Sentence 1: We .nd that the simulation of these applications need at best 3.5 hours (for cache block size of 64 bytes) and at worst 4.5 hours (for cache block size of 4 bytes) to .nish.
Sentence 2: we use Dinero IV to simulate 75 different cache con­.gurations (varying set size and associativity) with cache block size of 64 bytes for each SPEC CPU2000 application.
Relationship: reasoning
Domain: Hardware
Sentence 1: 0 No signal in this cone is A D observable due to the B controlling value present at one of D s inputs  As stated in the theorem, if it can be guaranteed that a signal/fault does not re-converge with itself in a higher time frame or does not become observable/testable even after recombination, it can safely be marked as unobservable or untestable.
Sentence 2: we propagate unobservability backwards across time frame boundaries, and declare a signal as unobservable only if it is truly unobservable in accordance with our theorem.
Relationship: reasoning
Domain: Hardware
Sentence 1: 2.Instate1ofDtheinterfaemustsuppressthe beltunfastenedinputofD.
Sentence 2: (0, 0) ignition / [in_park], chk_belts (1, 1) break V toggle_cruise /  cruise / (2, 2) Fig.3.interfaeforarontroller TheinterfaeforthisexampleisshowninFigure3.Any transitionoftheinterfaehasaninputidentialtothe inputofthetransitioninFbeingsimulatedbyDinthat stepandanhavetwokindsofoutputsassoiatedwith thetransition.Thefrstkindofoutputsorrespondsto generatingtheinputsofD(foring)andweenlosethese outputsin'[]'todenoteforingoutputs.Theothersetof outputsoftheinterfaearetheoutputsofDthatmustbe hidden.Theinterfaeanalsodisableextratransitionsin DnotmathingF.Inthisexample,theinterfaedisables thetransitiontriggeredbybeltunfastenedfromstate1of D. Thisexampleillustratestheneedforadaptingageneri devieDtomathafuntionFbyonstrutinganin­terfaeandomposingitwiththedevie.given arbitrarypairsFandDwhiharesynhronousprograms themainissueistodeidewhethersuhaninterfaeex­istsandifso,todeterminetheinterfae.Inthenext setion,weformalisethismathingproblembyrepresent­ingFandDasinput­outputbooleanautomata(IOB) [6](whiharemodelsofsynhronousprograms)andthen formalisingtheinterfaegenerationquestion.
Relationship: reasoning
Domain: Hardware
Sentence 1: The generation of cell level compact model exploits the fact that the Fourier conduction equation with constant thermal properties is a linear elliptic boundary value problem.
Sentence 2: the average temperature of the cell level model can be uniquely written as: 6 T = aT + a aq (1) avg .ff 0 f =1 where the coefficients af determine the influence of the six boundary temperatures of the cuboidal domain of cell on Tavg.
Relationship: reasoning
Domain: Hardware
Sentence 1: Initially, the logic value stored in cell q of the LFSR is represented by the binary variable aq.
Sentence 2: the initial state {E1(1), E2(1), , Ek(1)} of the LFSR consists of k variables, {a1, a2, , ak}, where k is the LFSR length and E1(1)=a1, E2(1)=a2, , Ek(1)=ak.
Relationship: reasoning
Domain: Hardware
Sentence 1: To scale to 64K nodes, the .attened butter.y requires two additional di­mensions, each of size 16, while the dragon.y, with its ef­fective radix of 256, connects all of the groups in a single, large dimension.
Sentence 2: while both topologies provide the same amount of global bisection bandwidth, the dragon.y requires only half the number of global cables compared to the .at­tened butter.y.
Relationship: reasoning
Domain: Hardware
Sentence 1: Figure 1: Combined Active and Passive Safety (CAPS)  Categories and Subject Descriptors Photo: Bosch  B.8 [Performance and Reliability]: Reliability, Testing, and Fault Tolerance; C.4 [Performance of Systems]: Re­ medical aids, industrial production and cars, their risk of liability, availability and serviceability failure increases, which may threaten human lives or physical conditions.
Sentence 2: the evaluation of safety is a crucial General Terms topic in several areas, especially for automotive electronics.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, if we change the processing sequence to -a2 = {1,2,4,3,6,5},we have the storage locations of the stems as -g2 = {1,2,1,2,2,1},V =2, in which we only need 2 storage spaces for simulating these six stems instead of 3.
Sentence 2: a different ordering might result in a different storage requirement.
Relationship: reasoning
Domain: Hardware
Sentence 1: Both signal am­plitude noise and jitter magnitude must comply with spe­ci.c requirements in the communication standards for a certain BER level.
Sentence 2: jitter generation, transfer, mea­surement and testing have been a subject to numerous stud­ies [3, 5, 16, 2, 14, 9, 1, 6, 8, 7, 15].
Relationship: reasoning
Domain: Hardware
Sentence 1: Inthispaper,weproposeastrategywhereanoptimizing compilerdecidesthebestcacheconfgurationforeachnest intheapplicationcode.Morespecifcally,inthispaper,we makethefollowingcontributions.First,wepresenttechniques foranalyzingthedatareusepropertiesofagivenloopnest andconstructingformalexpressionsofthesereusepatterns.
Sentence 2: second,wedevelopalgorithmstosimulatethefootprintsof arrayreferences.Oursimulationapproachismuchmoreef­fcientthanclassicalcycle-basedsimulationtechniquesasit simulatesonlydatareusespace.Third,wedevelopanopti­mizationalgorithmforcomputingtheoptimizedcacheconfg­urationsforeachloopnest.Wealsoprovideaprogramlevel algorithmforselectingdynamiccacheconfgurations.Wefo­cusonthebehaviorofarrayreferencesinloopnestsasloop nestsarethemostimportantpartofarray-intensivemedia andsignalprocessingapplicationprograms.Inmostcases, thecomputationperformedinloopnestsdominatestheex­ecutiontimeoftheseprograms.thebehaviorofthe loopnestsdeterminesbothperformanceandenergybehavior ofapplications.Previousresearch[8]showsthattheperfor­manceofloopnestsisdirectlyinfuencedbythecachebehav­iorofarrayreferences.Also,recently,energyconsumptionhas becomeanimportantissueinembeddedsystems[9].Conse­quently,determiningasuitablecombinationofcachememory confgurationandoptimizedsoftwareisachallengingproblem inembeddeddesignworld.
Relationship: reasoning
Domain: Hardware
Sentence 1: To reduce the simulation effort required for com­puting the quality metric of a modi.ed test sequence, we only consider faults that are detected up to n0 times by Tcpi , for a constant n 0 <n .
Sentence 2: we compute the sets Fm over a subset of the faults that have 1 =ndet(f ) =n0 before the modi.cation, and we use these sets to determine whether a modi.cation of Tcpi is acceptable.
Relationship: reasoning
Domain: Hardware
Sentence 1: Otherwise, we could not decode the obtained re­sults correctly.
Sentence 2: theSEP interpreterexecutesthe programinan en­codedfashion and thereby generates encoded outputs which are checked by another (standard) hardware unit, e. g. an FPGA which implements the checker whose task it is to de­termineifthe generatedoutput consistsofvalidcodewords.
Relationship: reasoning
Domain: Hardware
Sentence 1: The offset O and the mantissa L varies, due to the overall data path size.
Sentence 2: lNSI is realized with an overall data path size of 16 bit while LNSI I and LNSI I I are realized with 18 bit, which refer to L = 9, Q3.12 and L = 11, Q3.14, respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: When two methods are called from one rule then it must appear as if the external rule (together with the methods it calls) executes atomically with respect to the rules inside the module.
Sentence 2: if we do not know if the enabled methods are being called from a single or from multiple rules (because both would be valid executions), then the scheduler must assume that they are being called from a single rule and schedule all internal rules to either occur before or after the methods.
Relationship: reasoning
Domain: Hardware
Sentence 1: In fact we show in an experiment that ignoring these factors during GR and just considering local congestion is not e.ective in (a) (b) # of global nets: 8 non-uniform # of local nets: 0 1 0 1 0 3 0 1 0 1 1 11412 00002  (c) (d) (e) Figure 1: Binning to create non-uniform gcells.
Sentence 2: after decomposition, each net consists of two n n pin locations: (Tn = {p1 , p 2 }).
Relationship: reasoning
Domain: Hardware
Sentence 1: Speci.cally, setting e0 to 0 constrains all possible assignments of X0 to the offset of Fc, while setting e1 to 1 constrains all possible assignments of X1 to the onset of Fc.
Sentence 2: due to these constraints, a satisfying assignment to .gure 9 will .nd a minterm pair assign­ment to variables X0 and X1 that respectively map to the offset and onset of function Fc.
Relationship: reasoning
Domain: Hardware
Sentence 1: Looking at the same numbers in a different way, in Fig­ure 4, all points are contained between the 30% and 80% contours if .Linter =-1s.
Sentence 2: in this range, Isub is greater than Igate by one order of magnitude on average, and thus the variation of L can have a large effect on the total leakage as Isub is exponentially depen­dent on L. ignoring spatial correlation results in a substantial under-estimation of the standard deviation, and thus the worst-case full-chip leakage.
Relationship: reasoning
Domain: Hardware
Sentence 1: If there exists a node in the sys­tem whose only communication path is through a node with the L0 algorithm enabled, for example, due to failures in its other links, then such a node will be effectively disconnected from the network.
Sentence 2: rather than greedily enabling local decision algorithms to minimize consumption of local energy resources, devices must take into consideration the role they play in the system as a whole.
Relationship: reasoning
Domain: Hardware
Sentence 1: pTherefore, the total decoding time tfds offiis given by tfd)ffpi==tPh 1tcn fp1+dtPntfpi =fhkh/f f)dPt+/fffsdPw wdi The total time needed to decompress the codeword is given by fpdtnfpfp ti)ltfit1+dtfds ofi hphtfhkh =/ffTf,+E/ffsdPc+wdi/ffsdPw hh 1fhpk+i =+(1) f f1fE­ where f f)dfpPw=-fpf f1fhE.fp fphk Let E1EEpcEbe the absolute frequen­cies of the members of the tthgroup.
Sentence 2: the decompres­sion time ,fp for the runs belonging to ptthgroup is given by t hkh fp1fhp+difp ,==+)Eit n f f1fEnon­t t 1hp p1 hkhp =fEfit1+f+)Ef dititnn f f1fEntn-nonp Let us assume that Pd is the largest group.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that operation 1 can be sched­uled at a later cycle, but these choices will only increase the schedule time of operation 2, and are not shown in the ta­ble.
Sentence 2: the best schedule time for operation 2 is cycle 1 and can be achieved by scheduling operation 1 on either FU B or FU C. The possible schedule times for the operation pairs 1 3 and 1 4 look similar to Table 1, and the best schedule times for operations 3 and 4 is achieved by scheduling oper­ation 1 on either FU B or FU C. Algorithm 3 will re­turn the FLASH RANK of 1 for both FUs B and C, and the scheduler can assign operation 1 to either FU B or C. As­sume the scheduler chooses function units in alphabetical order and assigns operation 1 to FU B.
Relationship: reasoning
Domain: Hardware
Sentence 1: If we consider Texas Instrument s MSP430F5438 low-power microcontroller executing [16 bit, 50 Hz] DTW operation with 1 MHz clock, the power consumption of the microcontroller measures at 410 µW.
Sentence 2: our proposed GDMM will exhibit a 99.7% power reduction compared to the microcontroller scenario.
Relationship: reasoning
Domain: Hardware
Sentence 1: Any undirected graph G has a natural distance metric on its vertices, with the distance between any pair of vertices given by the shortest path between them in G. Graph em­bedding maps the vertices of G into a chosen metric space, typically to preserve certain properties such as edge lengths (i.e., distances) by minimizing distortion.
Sentence 2: iC place­ment has a natural correspondence with graph embedding into a chosen two-dimensional metric space representing the chip surface.
Relationship: reasoning
Domain: Hardware
Sentence 1: In this approach, the control unit throttles the WAKEUP signal propagation and dynam­ically controls the wakeup sequence When a high volt­age drop is detected as shown in Figure 4.
Sentence 2: the possibility of the occurrence of excessive voltage drop is reduced signi.cantly, even without raising the VDD level, widening power nets, and permanently prolonging the wakeup time.
Relationship: reasoning
Domain: Hardware
Sentence 1: As the procedure in Section 4.1 allows only one droplet routing during a certain time interval, and the one in Section 4.2 intentionally stalls the departure of a droplet to enhance routability, the routing resources are under low utilization, creating a large number of timing vi­olations.
Sentence 2: by rerouting each droplet in a greedy manner, we can increase the resource utilization, satisfy tim­ing constraints, and improve fault-tolerance without hurting routability.
Relationship: reasoning
Domain: Hardware
Sentence 1: A larger LT or UT saves more energy but incurs a higher slowdown (larger LT implies more aggressive transitions to lower speeds while a larger UT implies lazier transi­tions to higher speeds).
Sentence 2: similar to memory, PD dynam­ically adjusts LT and UT based on the predicted access count and available slack in the next epoch, to reduce energy consumption while only using the available slack.
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, addition of new search function that searches from tail to head can reduce number of searches.
Sentence 2: we can con­clude that when the tagis atthe Xth way of a cache setin thebigger cache where X> (A/2),depending on the value of X, tail tohead searching can reduce the number of ways searchedinside a set ofthe smaller cache from one to (A/2).
Relationship: reasoning
Domain: Hardware
Sentence 1: According to our results, for such a RACB, the hit rate of region reuse can reach 70% without causing noticeable quality degradation.
Sentence 2: with the (Pmem+Ppip)/PALL to be 3/4 and VCS to be the critical sequence, (so that k/N=4/16=0.25), based on Equation (2), we can obtain 55.9% of region execution power savings by applying the RACB technique.
Relationship: reasoning
Domain: Hardware
Sentence 1: Pre-charging of the OR-Plane is done be setting its inputs (product lines) and its outputs to GN D. 3) OR-Plane evaluation; In this phase, the outputs of the OR-Plane are calculated.
Sentence 2: the connection be­tween the AND-Plane and the OR-Plane is established trough the FETs between these two planes.
Relationship: reasoning
Domain: Hardware
Sentence 1: The main disadvantage of this approach is the same as the one encountered in [1] namely, data in each memory cell is stored using a closed QCA wire loop (which is partitioned into four clocking zones).
Sentence 2: also this memory design needs a large number of clocking zones, thus complicating the un­derlying CMOS circuitry for providing the required clocking signals.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since G2 has a large fanout of 4, the duration of the discharge current is long (260 psec), while the duration of the discharge current in G1 is short due to the small fanout of 2 (120 psec).
Sentence 2: for every gate in the circuit, a vector is constructed that carries information about the delay of the gate (when the peak occurs), the fanout of the gate (the duration at which the current lasts) and the magnitude of the current in each time slot.
Relationship: reasoning
Domain: Hardware
Sentence 1: Many low-and medium-end testers are not equipped with advanced port scalability features, which allow groups of chan­nels to be driven at different data rates.
Sentence 2: the proposed core  on-chip high-speed clock (e.g., from PLL) instead of the tester and, Virtual Test Bus 16FF Virtual Test Bus consequently, the proposed technique is particularly relevant when Virtual Core 1 used in conjunction with low-speed testers.
Relationship: reasoning
Domain: Hardware
Sentence 1: From the addi­tive schemes discussed in the previous paragraphs, the expo­nential El-Gamal scheme suffers from high decryption over­heads since it requires computing a discrete logarithm.
Sentence 2: the best candidate for HEROIC is the Paillier scheme, where the modular multiplication of the ciphertexts corresponds to modular addition of the plaintexts.
Relationship: reasoning
Domain: Hardware
Sentence 1: Further­more, delay of the bu.er at each stage is twice the bu.er delay in the previous stage.
Sentence 2: if each MUX has a delay of tx and the minimum-sized bu.er has a delay of tb, the minimum and maximum delay that RDL can provide are tmin RDL=K * tx + m * tb and tmax RDL=K * tx + (2K - 1+ m) * tb, respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since the subsequence already assigns types to three frames, when evaluating the min-and max­conditions we only have to assign types to the remaining 9 frames keeping in mind the types already used in the sub­sequence.
Sentence 2: some min-conditions are totally (min 2 I-frames out of 12 frames) or partially (min 6 B-frames out of 12 frames) ful.lled by the subsequence.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since equation (1) is separable into F(x, y) = F(x) + F(y), we can optimize F(x) and F(y) separately.
Sentence 2: the objective function F(x) and F(y) can be minimized by solving the following system of linear equations: Qx + dx = 0 (2) Qy + dy = 0 Equation (2) gives the solution to the unconstrained problem of minimizing the quadratic function in equation (1).
Relationship: reasoning
Domain: Hardware
Sentence 1: The well accepted value of is 80%.
Sentence 2: we denote the cumulative workload completion by   and formulate the ATMB problem as follows: Given: battery pack specification [        ], fan specification [          ], load profile distribution   ; Find: fan speed over the time,    ,     , is the off-state of the fan and is the stopping time for -th discharge process; Maximize:        , where is the largest cycle index number such that    ; Subject to: (1)     , the subscription stands for full cycle SoH degradation; (2)      ,     , where  is the battery power capability.
Relationship: reasoning
Domain: Hardware
Sentence 1: Every two tree levels, we double the number of switch widths we must accommodate across the width.
Sentence 2: the width of the tree of capacity N becomes: log2(N)/2 v M W = N × O(22i)p 2i i=0 log2(N)/2 v M p-1 = N O 2i (9) i=0 For p < 1, this is a receding geometric sum, so we have v W=O( N).
Relationship: reasoning
Domain: Hardware
Sentence 1: This is because the pulse width at the NAND-gate is determined by the time di.erence between the QM transition and the QS transition.
Sentence 2: by sub­tracting a latch delay from both, pulse width is determined by the time di.erence between the D transition and the clock falling edge, hence half clock cycle is added to .tg1 (.tg2).
Relationship: reasoning
Domain: Hardware
Sentence 1: Since WS(base)= N 1 1= N, we de.ne normalized weighted speedup as ratio of WS to N. The weighted speedup metric can be misleading as an ob­jective metricbecause it canbe optimizedby disproportion­ately favoring a single application, thereby hurting fairness and QoS.
Sentence 2: we use normalized weighted speedup for comparison purposes only and not as a metric to search for the most suitable partition.
Relationship: reasoning
Domain: Hardware
Sentence 1: This is because at the start of the wake-up, the sleep transistor operates in the saturation region as the circuit power supply, called as the virtual VDD (VVDD) node, has been discharged to a steady state value near GND.
Sentence 2: the large amount of instantaneous current that flows through the sleep transistor at the moment of wake-up initiation generates inductive noise and can disrupt the normal functioning of neighboring circuits.
Relationship: reasoning
Domain: Hardware
Sentence 1: High­order moments of circuit behavior f are .rst estimated by Point Estimation (PE) method to e.ciently characterize the high-order moments E(fk) by weighted-sum of a few sam­pled simulations.
Sentence 2: one can signi.cantly improve the e.ciency and accuracy of APEX [2] without the need to assume RSM inputs.
Relationship: reasoning
Domain: Hardware
Sentence 1: The value of current function at q (= mN+1) quadrature points is obtained by SPICE DC analysis For single input switching, we have only two variables Vin and Vout.
Sentence 2: the third order univariate Legendre s polynomials and the corresponding third order bivariate or­thogonal polynomials can be represented as, G3(.1)= {1,.1, (3.12 - 1), (5.13 - 3.1)} G3(.2)= {1,.2, (3.22 - 1), (5.23 - 3.2)}G3(.1,.2)= G3(.1) .
Relationship: reasoning
Domain: Hardware
Sentence 1: Nevertheless, we know that, the larger the (gm/ID)ra­tio, the more e.cient, in a power consumption sense, our transistor will be.
Sentence 2: if we solve the relaxed geometric program with only constraint (9) in it, it is reasonable to assume that the optimization problem will always .nd its solution with the largest (gm/ID) ratio posible, since those Figure 3: Common-source ampli.er circuit.
Relationship: reasoning
Domain: Hardware
Sentence 1: · = · = t2 E(Ai)=Pi(si(t))dt (3) t1 where t1 and t2 are the start and ending times of the exe­cution of task Ji.
Sentence 2: the total energy consumption Etot for the N tasks (J1,J2,··· ,JN )is N t2 Etot = Pi(si(t))dt.
Relationship: reasoning
Domain: Hardware
Sentence 1: The second set of constraints (C2), enforces each application to be realizable by the selected functional units.
Sentence 2: for each application MPk, all operations of type OPj , must be implemented by at least one selected functional unit FUa: C1 : .a, xai =1 i C2 : .k,.j, Okj Lij xai =1 a i Not only must each of the applications be realizable, but the throughput constraint for each application should be met.
Relationship: reasoning