sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: In a traditional adder, one is supposed to compute the product MiMi-1 ···M0 in order to compute the carry bit ci.
Sentence 2: in our adder we assume that no carry propagates more than k-bit position for some k. Hence, in our adder, one needs to compute only the product MiMi-1 ···Mi-k+1 to compute the carry bit ci.
Relationship: contrasting
Domain: Hardware
Sentence 1: Based on ML-OASG, they developed a 4-step algorithm to solve the ML-OARSMT problem.
Sentence 2: mL-OASG could not be suitable for the OAPDST problem due to its edges, that is, ML-OASG not only allows hori­zontal and vertical edges in the same layer but also uses slant edges.
Relationship: contrasting
Domain: Hardware
Sentence 1: Fajardo et al [10] propose an system where cores and accelerators share a common L2 SRAM, called Buffer-Integrated-Cache (BIC).
Sentence 2: accelerators are not tightly-coupled at L1, and their    Interconnect area scaling  350 300 250 200 150 100 50 0  # cores 4 8 16 32 Fig.
Relationship: contrasting
Domain: Hardware
Sentence 1: On average, roughly 50% of pages are accessed more than 100 times after they are predicted as inert.
Sentence 2: for applica­tions which showed a large percentage (> 40%) of accesses to encrypted pages (lbm, milc, sjeng, soplex, sphinx), a much larger percentage of pages (> 80% on average, and at least 64%) are accessed more than 100 times.
Relationship: contrasting
Domain: Hardware
Sentence 1: Many related works place small sensors on mobile devices to extract gait for a variety of purposes such as context extraction[8], [5], activity recognition[1], [9], [3], personal positioning[4] and person identi.cation[6].
Sentence 2: since most papers adopt the wearable computer approach, they require several sensors to be .xed to speci.c parts of the user s bodies to achieve a high degree of accuracy.
Relationship: contrasting
Domain: Hardware
Sentence 1: Looking into the future, we note that in regular algorithms, the dependence graph is data oblivious (the butter.y graph of FFT is an example) and so inexactness can be exposed and managed by the compiler.
Sentence 2: the dependence graph of irregular algorithms is depen­dent on values known only at run-time, and so inexactness must be managed almost entirely by the run-time system.
Relationship: contrasting
Domain: Hardware
Sentence 1: Neighborhood tran­sistors in the same die can make a simple circuit, such as an inverter, to become faster or slower or consume more or less energy hence leading to a variability cloud in the En­ergy/Delay (E/D) space with the nominal point centered in it.
Sentence 2: even when such effects are expected to man­ifest also in a similar way for more complex modules like SRAMs, this is not the case.
Relationship: contrasting
Domain: Hardware
Sentence 1: reduction ratio (%) 0 10 20 30 40 .rst metal local metals intermediate metals global metals 70/65 70/70 140/140 400/400 63/59 63/63 126/126 360/360 56/52 56/56 112/112 320/320 49/46 49/49 98/98 280/280 42/39 42/42 84/84 240/240 to the minimum feature size of the technology node.
Sentence 2: if scaling down the metal dimensions brings large bene.ts in design quality, process engineers are willing to invest efforts towards it.
Relationship: contrasting
Domain: Hardware
Sentence 1: HiJackuses the audiointerface toprovidepower and setup a bidirectional data communication link with external sens­ing attachment.
Sentence 2: it is designed speci.cally based on the iPhone s audio interface characteristics and it is not  Figure 3: Di.erent modules of MELOS node clear if it can be easily extended to be generally applicable on all phones, including low cost phones.
Relationship: contrasting
Domain: Hardware
Sentence 1: The commonly employed evidence lower bound bound in variational inference, denoted as LXY (q), is a function of both sets of hidden variables (the intermediary nodes X and output nodes Y ).
Sentence 2: for our circuit settings, this bound is not suitable, because of its associated convergence speed drawbacks and its strong simplifying assumptions (speci.cally, it neglects the correla­tions between the intermediary nodes X and the output nodes Y ).
Relationship: contrasting
Domain: Hardware
Sentence 1: Bitcoin does not explicitly require personal identifying in­formation to perform transactions, which makes it highly use­ful for performing irreversible transactions with third-parties that you may not want to share physical address information with.
Sentence 2: the public record of the transactions can po­tentially allow identities to be de-anonymized by determined parties, even if users follow the practice of using a di.erent address for every sum of money that is received.
Relationship: contrasting
Domain: Hardware
Sentence 1: As a result, design C1-d3 with depth-3 sequential patterns and an 8-bit selec­tor (which gives, on the average, full controllability of 16% of scan chains) needs four times more test patterns than in a no­compaction mode.
Sentence 2: circuit C4-d0 (here a 12-bit selector provides similar scan chain controllability) requires a 1.3x pattern count increase despite a higher X-fill rate than that of design C1-d3.
Relationship: contrasting
Domain: Hardware
Sentence 1: The performance Figure 6: Kernel (2): Relationship between cache hit rate and relative memory bandwidth  1 2 4816 Stride Figure 7: Kernel (1): E.ciency of stride loop of Case2 is comparable to that of the 4B/FLOP system when the cache hit rate is 66%, because the bandwidth of each data is the 4/3B/FLOP on average.
Sentence 2: in Case3, both Y(i) and Z(i) are provided from the memory, and the bandwidth of both Y(i) and Z(i) isa1B/FLOP at the vector register.
Relationship: contrasting
Domain: Hardware
Sentence 1: But caches are widely managed in hardware because of the high overhead of OS interven­tion for every L2 cache miss (the disadvantages of software managed caches (SMCs) [3, 6, 8, 12] are further explained in Section 5).
Sentence 2: hardware cache manage­ment minimizes the performance impact but it does not o.er policy .exibility.
Relationship: contrasting
Domain: Hardware
Sentence 1: However,as we saw earlier, the use of multiple arms and the SPTF scheduling algorithmleadsto a signi.cantdecreasein the rotationalla­tency, which results in a largeperformanceboost for Web­search, allowing the intra-disk parallel design to surpass theperformance ofMD, while consumingroughlyan order of magnitude less power than MD.
Sentence 2: the sharp reduction in the rotational latencies provided by the HC-SD-SA(n)designsforTPC-Cleads to alarge reduction in thepower consumption.
Relationship: contrasting
Domain: Hardware
Sentence 1: As the 306 Figure 3: The MorphCore microarchitecture number of SMT threads increases from 1 to 8, the performance of the out-of-order core increases signi.cantly at 2 threads, but starts to saturate at 4 threads, because the performance is limited by the peak throughput of the core.
Sentence 2: the performance of the in­order core continues to bene.t from more threads (which allows it to better tolerate long latency operations and memory accesses).
Relationship: contrasting
Domain: Hardware
Sentence 1: Simulink HDL Coder [5] generates synthesizable RTL code from Simulink models.
Sentence 2: the generated RTL code has a close 1-to-1 correspondence with the Simulink model, hence different micro-architectures in hardware require very different Simulink models, thus defeating the separation between functionality and architecture that is essential for true model-based design.
Relationship: contrasting
Domain: Hardware
Sentence 1: 3.1 The evaluation property For both structures, the circuit parameters have been sized in order to make the structure operate as follows: when the positive + high input voltage,Vin + , is at a high logic level, Vin =Vin (and - low consequently Vin =Vin ), the quantizer must give a high logic V + level of the positive output, .
Sentence 2: when + low - high out =V and =V , the output must be low.
Relationship: contrasting
Domain: Hardware
Sentence 1: It is further complicated by the fact that racy accesses could be executed arbitrarily far away from each otherintime,whichimpliestheneedforperforming con.ict detection across events like cache evictions, context switches, etc.
Sentence 2: dRFx hardware isinherently simpler as it requires that we track memory access state and perform con.ict detection over only the uncommitted,bounded regions.
Relationship: contrasting
Domain: Hardware
Sentence 1: The second technique, observability don t care based cube selection, relaxes the constraints for cube selection using local observability don t cares.
Sentence 2: this relaxation may result in the inclusion of minterms outside the feasible subspace, which does not guarantee  Exact cube selection Don t-care-based cube e b selection f ya b c d  Solution 1 a b e f  c a Solution 2 cde f  (a) (b) (c) Figure 1: Example circuit (a) and approximate logic circuits for (a) using the two cube selection algorithms (b) and (c).
Relationship: contrasting
Domain: Hardware
Sentence 1: The pginv instruction operates in a similar fashion to an in­struction that invalidates a single cache line, such as the ARM mcr icimvau [1] system control instruction, i.e., it takes as an argument the virtual address of a memory lo­cation to be invalidated.
Sentence 2: unlike the mcr icimvau instruction it is meant to invalidate the entire page that contains the line for the given address.
Relationship: contrasting
Domain: Hardware
Sentence 1: A placement with the maximal channel area is called MCA(Maximal Channel Area)-placement.
Sentence 2: v1 3 v3 2 dummy channel vd 1 vd  vt (a) h-const graph (b) dummy vertical channels vd vd 1/3 1/3 7 1/36 5 v2 2 1 1/2 1 vs vt 3 v3 1/6 1 vdv1 vd 1/3 1/6 (c) modified h-const graph (d) vertical channel label Figure 4: How to determine coe.cient a it is not su.cient only to optimize the primary ob­jective.
Relationship: contrasting
Domain: Hardware
Sentence 1: For high pixel density and/or large-area displays, the use of in-pixel com­pensation circuits, such as 6TFT+2Cap [14], is limited by small area and yield considerations.
Sentence 2: ex­ternal calibration usesthedisplay non-uniformity character­izationdata storedin an embeddedmemory to modulate the input video signals.
Relationship: contrasting
Domain: Hardware
Sentence 1: The instruction C was originally fetch-critical because of the mispredicted branch A. Spawning removed the exe­cution of mispredictedbranchA as well asfetch ofinstruc­tionsbetweenA andCfrom the criticalpath.
Sentence 2: spawning D from A, shown in Fig­ure 4(c), is an unpro.table spawn that violates Rule 2 for spawn success.
Relationship: contrasting
Domain: Hardware
Sentence 1: Theorem 3.3: (H and W initial seed) The H and W functions of value as F to guarantee M aj(Fa, Fb, Fc) = F .
Sentence 2: equation 3 respect the condition in Equation 2. for the remaining input combinations, F and Fa have the same value Proof: (H.F ) + (W .F ) condition from Equation 2 reduces Fa' and only one function between Fb and Fc must assume the same to (FFa .F ) + (FF .F ).
Relationship: contrasting
Domain: Hardware
Sentence 1: The empty corner rectangle property is also proposed in [6].
Sentence 2: let uw and vw denote two perpendicular segments sharing a common end point w. Then no other points of the RSMT can lie in the interior of the smallest axis-aligned rectangle R(u,v)containing u and v. when there are blockages and virtual pins, we only need to consider points in V and can project on uw and vw without intersecting with any blockages.
Relationship: contrasting
Domain: Hardware
Sentence 1: Our proposed fault injection mechanism uses a entirely dif­ferent approach and do not change the memory contents of any of the process in simulation including the centralised scheduler.
Sentence 2: the design of our implementation is very close to ORCHESTRA [5] where we insert an inter­mediate layer between any two layers of protocols, to inter­rupt all the messages between them and faults are driven by scripts.
Relationship: contrasting
Domain: Hardware
Sentence 1: The reduction of energy consumption by re-directing the data path to use an energy ef.cient smaller structure like a buffer more frequently has been prevalent for quite some time [9].
Sentence 2: like it has been shown in our paper, for NVM caches, the aim of such a secondary structure is to .lter the writes to the NVM cache and help mitigate their negative impact.
Relationship: contrasting
Domain: Hardware
Sentence 1: Packing can be carried out effectively because the utilization of LB and SM used tiles is almost same value as LUT utilization.
Sentence 2: higher utilization results of 48.8 % in SM only used tile and of 59.6 % in SMUX show that plural FPGA tiles which have connectability each other are not able to be placed closely, as a result, the cases increase that the FPGA tiles are placed to the distance farther than wire segment length of 4.
Relationship: contrasting
Domain: Hardware
Sentence 1: (4) Then the corresponding interpolant corresponds to an im­plementation of fA.
Sentence 2: to derive fB we perform a similar computation, but now with CA the clause set of f(XA,XB,XC ) .¬fA(XA,XC ) (5) and CB the clause set of ¬f(XA,XB,XC ).
Relationship: contrasting
Domain: Hardware
Sentence 1: From Figure 20 and Figure 21, we note that the array-partitioning-based method achieves both a smaller number of control pins and a shorter bioassay completion time than the cross-referencing-based method.
Sentence 2: the array-N×M grid by cross-reference EWOD driving scheme and pressure-contact packaging , in IEEE MEMS Conference, pp.
Relationship: contrasting
Domain: Hardware
Sentence 1: Typically,logic BIST for ASICs introduces about 20% area overhead and some performance degradation.
Sentence 2: bIST for FPGAs is a free lunch with no area overhead or delay penalties,since the entire FPGA is config­ured only for BIST,and all the BIST logic disappears when the FPGA is no longer under test.
Relationship: contrasting
Domain: Hardware
Sentence 1: Conclusions and future research directions Critically viewed, both architectures have their advan­tages and disadvantages.
Sentence 2: we consider the follow­ w = 8 16 24 32 XOR-network add-on-xDistr 370 1886 698 1813 1023 1813 1570 1742 For the XOR-network based architectures, the area over­ head is linearly dependent on the size of the test bus.
Relationship: contrasting
Domain: Hardware
Sentence 1: 2.1 Simulation The simulation of neuron networks once they are com­plete is a comparatively mature .eld, with accepted pro­grams such as GENESIS[18], NEURON[19] and others[20], as covered in a review of eight such programs.
Sentence 2: these programs do not cover the physics of long range inter­neuron chemical cues (neuromodulators), nor do they model how these networks are grown.
Relationship: contrasting
Domain: Hardware
Sentence 1: When the data lifetime of the cache block is less than 7ms, the data block should be placed in SRAM-based cache to reduce dynamic energy of the RRAM-based cache.
Sentence 2: when the data lifetime of the cache block exceeds 7ms, the data block should be placed in the RRAM-based cache to reduce (a) Redundant bit-writes discarding by RSE scheme, (b) Avoid access conflicts based on Sequential tag-data access Figure 6: A non-volatile SRAM last-level cache leakage power from the SRAM-based cache.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this case, apsi achieves an average IPC of 1.49 while parser achieves an average IPC of 0.88, in­dicating the prioritization of apsi over parser.
Sentence 2: note that the SHARP control architecture is resilient enough to keep the performance of parser fairly high as compared to thespeci.edreference IPC.Ifa disproportionate biasis used to prioritize one application over the other, the FSI policy starts approaching the SD policy.
Relationship: contrasting
Domain: Hardware
Sentence 1: [12] use 3D VLSI to mount a large STT-RAM L2 NUCA over core layer and suggest using a small SRAM write buffer for L2 cache or select 1-way in SRAM line to service write-stressed data to fill the latency gap imposed by utilizing STT-RAM technology.
Sentence 2: this paper does not concern non-uniform wear-out of STT-RAM lines.
Relationship: contrasting
Domain: Hardware
Sentence 1: Previously proposed asynchronous FPGA architectures [5, 9, 12, 18] based on clocked programma­ble circuits were not e.cient at prototyping pipelined asyn­chronous logic and did not demonstrate signi.cant advan­tages over clocked FPGAs.
Sentence 2: recent work by the authors has developed programmable asynchronous circuits that are inherently pipelined, e.ciently implement asyn­chronous logic, and are competitive with clocked circuits [21].
Relationship: contrasting
Domain: Hardware
Sentence 1: In this alternative, the round complexity increases by 2, but again when O(k) anonymous messages are transmitted the ratio of protocol messages to anonymous messages is O(k)and the ratio of protocol bits to anonymous bits is O(k3); and any member of the sending group who fails to forward anony­mous messages is caught.
Sentence 2: this alternative is not secure against non-participation.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since both JIT optimizer and JIT optimized code stress the level­one data cache, during a JIT optimized system execution, hardware units in the execution engine are more likely to be idle and thus dissipate less power than an un-optimized system.
Sentence 2: being memory bound and with low ILP, the garbage collector dissipates less power than the application code, but rarely affects the average power of the latter.
Relationship: contrasting
Domain: Hardware
Sentence 1: When the recognizer cooperates with a placer to iteratively improve routability, the recognizer can be tuned to rapidly report unroutable regions but sacrifice a little recognition rate.
Sentence 2: to discover whether some hard-to-route cases among a set of placements that are widely used to be the global routing benchmarks are unroutable, the recognizer can be tuned to spend a longer runtime to yield a better recognition rate.
Relationship: contrasting
Domain: Hardware
Sentence 1: itythatawireisblockedshouldbemonotoneinthenumber oftrackintersectionsitmustcrossaswellasintheproba­bilitythataviablocksoneofthoseintersections.Ifthevias areuniformlydistributedoverthearea,theviafllratef equalstheprobabilitythatanintersection(orwiresegment) isblockedbyavia.Sinceanywireoflengthlsegmentsoc­cupiesl+1trackintersections,10theprobabilitythat Pnb thewireisnotblockedcanbeestimatedas l+1 =(1;f)(7) Pnb becausenoneoftheintersectionsmaycontainavia.Ifwe retaintheassumptionofothermodelsthatawirecannotbe routedifitsshortestpathisblocked(i.e.,wedonotallow rippleefects),theviaimpactfactorforawireoflengthl couldbeestimatedtobe l+1 vi(l)=1;Pnb =1;(1;f): (8) Ofcourse,thisnewviaimpactmodelisfartoosimple.It doesnotevenacknowledgethatlongerwireshavemorepos­sibilitiesforfndingashorterroute(whichdecreasesvi(l)).
Sentence 2: acomparisonwiththeexperimentalresultsfortheaver-agewirelengthsoneachlayer(Figure3)indeedrevealsthat thissimplemodeloverestimatestheviaimpact.themoreinterestingresultisthatthissimplemodelseems tointroducetheefectsofthewirelengthinamannercon­sistentwiththegeneraltrendoftheexperimentalresults.
Relationship: contrasting
Domain: Hardware
Sentence 1: Also due to the bu.ers, the CMS engine occupies more area.
Sentence 2: to make the CMS engine operate at the same clock frequency as the DMA engine, we can simply pipeline the CMS engine  Application execution time 512x512 2D data arrays 90 80 54.9  80 70 70 60 60 50 50 CMS % improvement over FRFCFS  CMS % improvement over FRFCFS 40 30 20 10 40 30 20 10 0 0 Application memory bytes per FLOP Figure 11: Application execution time improvement of CMS compared to FRFCFS (uncoordinated).
Relationship: contrasting
Domain: Hardware
Sentence 1: When a back to back instruction needsincurs a stall, because each instruction has operands that require reading from the slow entries from either or both of the two ports.
Sentence 2: a stall, the forwarding data is propagated through the forwarding path2 rather than forwarding path1.if we can identify the problem and steer the register ac-All the additional control signals are generated in parallel with cess from the slow port to the fast port before entering the register wake-up and selection in the issue queue, so they will not add to.le read stage, we can avoid stalls.
Relationship: contrasting
Domain: Hardware
Sentence 1: Therefore, we get: (,1 x2,..., xn | yl) .j Prob x j | Prob x ==( y =l) , and we compute the MAP class of y as follows: n yMAP =arg max Prob y ( =l) ·.Prob ( xj | y =l ) lj =1 In the original algorithm, the prior and conditional probabilities are obtained by performing Maximum Likelihood estimation on the whole data set.
Sentence 2: in this work we have to implement the predictor in an online fashion.
Relationship: contrasting
Domain: Hardware
Sentence 1: 5.For each selected critical node, pick top few most crit­ical edges (with largest weights) in the original graph and add them to the spanning-tree support graph to build the .nal ultra-sparsi.er support graph.
Sentence 2: 4.3 Energy-based Spanning-Graph Scaling As discussed above, using the ultra-sparsi.er support graph instead of spanning-tree support graph, the preconditioner can better approximate the original system.the number of extra edges that are added to build the ultra­sparsi.er can not be very large, since excessively adding ex­tra edges will result in drastically increased computational and memory cost in matrix factorizations.Thus the to­tal power dissipation of the tree-like support graph can still be much less than the original graph.It has been shown = .... = .... that if .... ..........h .. ..........h .. (............h ).., ..........h ..-approximates ..........h [7].To further improve the qual­ity of the support graph approximation without increasing computational and memory cost during the matrix factor­izations, a novel energy-based support graph scaling scheme is proposed such that: .
Relationship: contrasting
Domain: Hardware
Sentence 1: It is well-known that a common 2-to-1 MUX usually consists of two 2-input ANDs, one 2-input OR and NOT, so the area of one 2-to-1 MUX must be larger than that of 2-input AND/OR.
Sentence 2: if the 2-to-1 MUX is implemented by using transmission gate logic, the area overhead can be reduced.
Relationship: contrasting
Domain: Hardware
Sentence 1: Low dropout (LDO) linear regulators are slightly inferior to DC-DC converters in terms of power efficiency, but more suitable for integration compared to DC-DC converters in terms of the small area, fast load transient response, and off-chip-component-free feature.
Sentence 2: it is well known that LDO regulators are negatively affected by a trade-off between feedback stability and fast load transient response.
Relationship: contrasting
Domain: Hardware
Sentence 1: Theauthorsanalyzethehierarchystructureofanetlistand representthefanoutdistributionbyageneratingpolyno­mialofnetdegrees.Theresultingrecursiveequationscan betransformedintothelogisticequation.Althoughthere isnoclosedformsolutionforthelogisticequationingen­eral,closedformexpressionsfor2-and3-terminalnetsare presented.Theseexpressionsareclosetoapower-law,espe­ciallyforlargecircuits;thisagreeswithanempiricalpower­lawwithexponent;3observedbytheauthors.1 Observations.Wemakethefollowingobservations.First (asindependentlynotedin[10],p.104),wenotethatthe 1Themodeltakestwoparametersasinputs:(i)theRent exponentpcharacterizingthenetlisttopology,and(ii)an internal/externalterminalnumberratiofcharacterizingthe partitioning(largerfmeansmoreinternalterminalsateach hierarchylevel).
Sentence 2: zarkesh-HamodeldependsonTnet(i)beingthesamein boththeN-gatecircuitandthe(N;1)-gatecircuit,for alliN.suchanassumptionmaynotbevalid.
Relationship: contrasting