sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: To gain e.ciency we concentrate on a weaker goal, k-anonymity: the adversary is able to learn something about the origin or destination of a particular message, but cannot narrow down its search to a set of less than k par­ticipants.
Sentence 2: k-anonymity guarantees that in anetwork with n honest participants, the adversary is not able to guess the sender or recipient of a particular message with probability non-negligibly greater than 1/k,where k is a constant smaller than, but otherwise not related to n. We show that, in our adversarial model, there exists a k­anonymous communication protocol that is far simpler and more e.cient than any known fully anonymous communi­cation protocol.
Relationship: entailment
Domain: Hardware
Sentence 1: To ensure complete identi.cation capability while keeping compu­tational time low, we run checker 1, checker 2 and checker 3 in a con­secutive manner.
Sentence 2: if a more ef.cient checker (e.g., checker 1) .nds out a redundant input for a particular signal with un-activated products/sums, we mark it as a suspicious HT-affected signal and move to process the next signal of interest.
Relationship: entailment
Domain: Hardware
Sentence 1: While it is periodic for any odd modulus mi, odd moduli with small period P(mi) and half­period HP(mi) parameters typically enjoy low implemen­tation costs [17].
Sentence 2: for every non-negative integer k,j :k<n, the low-cost moduli 2n -1 and 2n +1 enjoy k+nj 2=|2k|2n-1,n=2 (2) k+nj 2=|(-1)j2k|2n+1,n=1.
Relationship: entailment
Domain: Hardware
Sentence 1: The main reason is that even if logic function is the same at both an MT cell and a high-Vth cell the number of pins is different from each other.
Sentence 2: a high-Vth cell for NAND2 has two input pins (A and B) and an output pin (Z), while an MT cell for NAND2 has three input pins (A, B and MTE) and an output pin (Z).
Relationship: entailment
Domain: Hardware
Sentence 1: The universal MSR multiplier produces 0 1 M-2 M-1 a b = a(B0a+ B1a+ ...+ BM-2a+ BM-1a) = aB0 +( aa)B1 + ···+((···(( aa)a) ···a)BM-1.
Sentence 2: the universal MSR multiplier produces the product a b of the register values a and b.
Relationship: entailment
Domain: Hardware
Sentence 1: Each of the (m + n) net requires at least a cost of 2R.Since the TSV assignment solution completed the routing of all nets, each net must have achieved the minimum cost of 2R.With wirelength 2R, there must be no detour of any routing of the bridges.
Sentence 2: a net can only be assigned to the bridge bti (or bfi) on every die.
Relationship: entailment
Domain: Hardware
Sentence 1: The authors observe that the application-speci.c nature of the embedded processors and the tight area, power dissipation, and latency/throughput constraints in embedded systems often demand a highly ef.cient and fully automated architecture exploration methodology.
Sentence 2: they show that ADL-driven design space exploration and software toolkit generation strategies present a viable solution to this prob­lem, providing a systematic mechanism for a top-down design and validation of complex systems.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that f (k - 1) <= f , for all k. In the case where CD fC (k - 1) < fD , we know that f (k -1) = fC (k - 1) , and from Equation (2), f(k) > f (k - 1) since r(k) = 1 > rref .
Sentence 2: both f (k) and fC (k) will increase monotonically until fC reaches fD .
Relationship: entailment
Domain: Hardware
Sentence 1: Our simulations show that IPStash is both fast and power efficient com­pared to TCAMs.
Sentence 2: iPStash devices built in the same technology as TCAMs can run at speeds in excess of 600 MHz, offer more than twice the search throughput (>200Msps), and consume up to 35% less power (for the same throughput) than the best commer­cially available TCAMs when tested with real routing tables and IP traffic.
Relationship: entailment
Domain: Hardware
Sentence 1: 18.78 0.74 7.42 160.24 2.31 Second, the estimation error of the entropy method does not quickly decrease, if we use more than 9 sensors.
Sentence 2: finally, Table 1 shows the runtime for different methods to deploying 9 sensors for thermal monitoring is a good choice to determine the sensor locations for our experiment in Figure 1.
Relationship: entailment
Domain: Hardware
Sentence 1: However, unlike the traditional sparse regression approach that fits the sparse performance model based on the simulation data at a single stage only (e.g., post-layout simulation data), BMF attempts to identify the underlying sparse pattern by re-using the early-stage data (e.g., schematic-level simulation data) in order to efficiently fit a late-stage (e.g., post-layout) performance model.
Sentence 2: bMF consists of the following two major steps: (i) statistically defining the prior knowledge of the sparse pattern based on the early-stage simulation data, and (ii) optimally determining the late-stage performance model by combining the prior knowledge and very few late-stage simulation samples.
Relationship: entailment
Domain: Hardware
Sentence 1: We chose to solve this problem by using the granularity of the loop iteration, for any of the loops in the program.
Sentence 2: given an arbitrary loop in the program (which may very well be surrounded by other loops), our technique will compute the mini­mal on-chip buffer size requirement and associated communications to execute one iteration of this loop, while exploiting the reuse be­tween consecutive iterations of said loop.
Relationship: entailment
Domain: Hardware
Sentence 1: Our Contributions: In this work, we adopt the Minimum Cross Entropy (MCE) method from the statistics community to develop a complete and general statistical methodology called Cross Entropy Minimization for SRAM, to give quick and 978-3-9810801-8-6/DATE12/ c .2012 EDAA accurate evaluation of SRAM designs.
Sentence 2: we .rst mathematically formulate the failure of SRAM cells in a way such that IS can be applied to it, and the MCE method is then applied to determine the optimal practical distribution for IS.
Relationship: entailment
Domain: Hardware
Sentence 1: The goal of the simulation experiments reported below is to study the impact of the sample on the overall perfor­mance of the Median computation protocol.
Sentence 2: we verify the results we obtained via analysis, in Section 5.2, about the inter-relationship among parameters, such as er­ror bound E, sample size S, and the number of buckets b in the histogram.
Relationship: entailment
Domain: Hardware
Sentence 1: [15] only provides an estimation of the number of operations for Algorithm 3, so we can use it as a lower bound O on the number of operations required by Algorithm 1.
Sentence 2: when the precision is set to 10-6, this lower bound is given approximately by 12 times the product between the maximum jump to left and the maximum jump to right, that is: O 12 ·L ·S =12[A(B -1)-1]·S 12 ·A ·B ·S .
Relationship: entailment
Domain: Hardware
Sentence 1: (Henceforth, the dimensional sub­scripts in the transfer functions or association operator are sometimes omitted when they are obvious from context.)
Sentence 2: an interesting property [1] is that if H(s1, ··· ,sn) canbe writtenas F (s1 + ··· + sn)G(s1, ··· ,sn), then by (7) H(s)=A (F (s1 + ··· + sn)G(s1, ··· ,sn)) =F (s)A (G(s1, ··· ,sn)) = F (s)G(s).
Relationship: entailment
Domain: Hardware
Sentence 1: Py (18) Since z and y are independent, their mean and variances will add in a convolution.
Sentence 2: µx = µz µy+ (19) sx 2 = sz 2 + sy 2 (20) Since P, C, Pand Care known, their mean and xxy y variances can be computed from their PDFs (or their piecewise linear CDF).
Relationship: entailment
Domain: Hardware
Sentence 1: Asshown inFig.6-(a),on average,DESAoffers twice asmuch reliabilityastheconventional BMSoverthebattery slife­ 100 10-2 time.
Sentence 2: a DESA-managed battery pack to be used for 10 years is 3× more reliable than the conventional BMS-managed 10-4 one,whosereliabilityisonly26%.
Relationship: entailment
Domain: Hardware
Sentence 1: Natalie deremijenko Center for Advanced Technology New York University 715 Broadway, # 1208 NY, NY 10003 USA +1 212 998 3382 nat@cat.nyu.edu EXISTING APPLICATIONS Sound transduction through bone conduction has been used for more than 50 years in subjects with certain types of hearing impairment.
Sentence 2: eases where profound damage to the middle and/or outer ear exists, usually classified as "conduction loss", but where the cochlea is still intact are good candidates for the use of hearing aid devices that use this technology.
Relationship: entailment
Domain: Hardware
Sentence 1: Es­pecially as the process technology advances below 90nm, the leakage power consumption becomes dominant in the to­tal power dissipation, thus reducing the leakage power con­sumption is an important design goal for low-power CMPs.
Sentence 2: since most CMPs employ a large L2 cache, reducing the leakage power consumption of the L2 cache is critical in realizing low-power CMPs.
Relationship: entailment
Domain: Hardware
Sentence 1: Given a partial candidate voltage partitioning solution s, adding small functional units into s could increase the maximum voltage v(Fi(s)) at some partitions, which will signi.cantly increase the peak power and thus make the approximation ratio dif.cult to control.
Sentence 2: even if one computes the optimal solution for Fbig and the optimal solution for Fsmall , patching these two solutions together could still lead to much worse result.
Relationship: entailment
Domain: Hardware
Sentence 1: For each NTPT in the system, we use a dedicated tile to simu­late its behavior, such as tracking outgoing tra.c and up­dating the communication pattern register.
Sentence 2: if we are going to evaluate NTPT on a CMP with n tiles, we will use n extra tiles in TILE64 for simulating the be­havior of corresponding NTPTs.
Relationship: entailment
Domain: Hardware
Sentence 1: The key characteristic of these sensors is that they are non-intrusive, that is, they are not electrically connected to the RF circuit, and, thereby, they do not degrade its performances.
Sentence 2: the presence of spot defects is detected by a temperature sensor, whereas the performances of the RF circuit in the presence of process variations are implicitly predicted by process sensors, namely dummy circuits and process control monitors.
Relationship: entailment
Domain: Hardware
Sentence 1: If da and db denote two devices to placed on the chip, we draw two circles each with radius C(da 2 ,db) , centering at da and db.
Sentence 2: if these two disks are disjoint, i.e., non-overlapping, then the distance between their centers will be no less than C(da,db).the corresponding separation constraint will be satis.ed.
Relationship: entailment
Domain: Hardware
Sentence 1: Without retiming, the rate optimal unfolding factor is upper bounded by the least common multiple of the delay counts of all cycles in DFG.
Sentence 2: if we unfolded the DFG Gby f= m(D( )), V EG, we can always get a DFG with the optimal execution rate P(GI)=T( r)/D( r).
Relationship: entailment
Domain: Hardware
Sentence 1: The sensitivity is quanti.ed as a weight parameter.
Sentence 2: for a data set .. = {..1,..2, ..., .... } with .. sam­ples, where each sample .... = {..1,..2, ..., .... } consists of .. variation parameters, ReliefF starts with a .. -long weight vector ,.. , of zeros, and iteratively updates .. .
Relationship: entailment
Domain: Hardware
Sentence 1: This is in contrast with the design of commodity SSD intended for serving vari­ous workloads covering a large spectrum of characteristics in terms of request operation (read or write), request size, and request locality.
Sentence 2: because of .ash s out-of-place data update, in the design of commodity SSD substantial at­tention has been paid to the optimization of logic for effec­tively serving small writes, which are associated with ex­pensive garbage collection operations and carry a signi.cant performance implication.
Relationship: entailment
Domain: Hardware
Sentence 1: While process innovations are in the foundations of this evolution, power dissipation, quality, yield and reliability issues may become the showstoppers.
Sentence 2: rapidly increasing defect densities and fault model complexities; extreme static and dynamic PVT variability; cross talk; accelerated aging and device degradation; and increasing soft error rates; bring us in a domain where traditional DfT, DfY, and DfR approaches could not work.
Relationship: entailment
Domain: Hardware
Sentence 1: This type of questions can be ef.ciently answered by Statistical Model Checking [3, 2, 5], the technique we use for verifying analog circuit models simu­lated by SPICE.
Sentence 2: randomly sampled system traces are sequentially generated using SPICE and passed to a trace checker (see Section II for a brief description of the checker) to determine whether they satisfy a given speci.cation, until the desired statistical strength is achieved.
Relationship: entailment
Domain: Hardware
Sentence 1: 3T +T -x ox ox Si BOX Si c where VFB is the flat-band voltage in the front gate, fF is the film-Fermi potential, NA(eff)is the effective channel doping density, eox is the front-gate oxide permittivity, and xc is the inversion-charge centroid (0 < xc < TSi).
Sentence 2: a negative back-bias increases the device threshold voltage, whereas a positive bias reduces it [11].
Relationship: entailment
Domain: Hardware
Sentence 1: For instance, the rule which says that only paths that contain solely HVT cells are allowed to have a delay which is longer than D. (but shorter than Dnom) nom can be relaxed.
Sentence 2: we could allow paths which contain a mix of HVT and LVT cells to have a delay longer than D. at Tnom; obviously, if we do so, we need to make nom sure that the delay of that path at Twc is still below Dnom.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that the matrix ATA .RK.K is much smaller than the matrix A .RN.K where K << N in our application.
Sentence 2: unlike the QR decomposition that is performed on a large-size matrix A, the Cholesky decomposition in (24) is applied to a small-size matrix ATA and, hence, can be efficiently computed with low computational cost.
Relationship: entailment
Domain: Hardware
Sentence 1: Our future plans also include switching to a newly-avail­able GPS chip which o.ers quicker .xes at lower energy costs and increasing the number of sensors on the collar.
Sentence 2: we are currently testing XYZorientation sensors that will assist the biologists in collecting data about the zebra s activities: a collar low to the ground is likely eat­ing, while other patterns regarding how the head is raised may be mined for information on the zebra s social behavior, vigilance towards predators, and so forth.
Relationship: entailment
Domain: Hardware
Sentence 1: Through considerations of this type, corner analysis has been applied for many years to design chips that are robust in the face of process variability.
Sentence 2: when variations are modeled as RVs, it is common to think of the bounds Xmax and Xmin as being the ±3s limits of the i i normal distribution of Xi.if s2 is the variance i of Xi then Xmax =+3si and Xmin = -3si.For any normal i i distribution with mean µ and variance s2,the interval µ ± 3s covers 99.73% of the distribution: Fµ,s (µ +3s) - Fµ,s (µ - 3s)= F(3) - F(-3) = 0.99731 (3) where Fµ,s (·) is the cdf of the normal distribution with mean µ and variance s2,and F(·) is the cdf of the standard normal distribution (i.e., the normal distribution with a mean of 0 and a variance of 1).
Relationship: entailment
Domain: Hardware
Sentence 1: Experimental studies presented in Section 5 indicate that our proposed framework outperforms the best known prior work [9] that focuses on the same problem of VI-aware regular NoC synthesis.
Sentence 2: our framework generates solutions that have lower network traffic by up to 60%, and lower power dissipation by up to 11% compared to solutions generated by using the approach from [9].
Relationship: entailment
Domain: Hardware
Sentence 1: In particular, we use dynamic instantiation that creates a new class X_channel (where X represents bus protocol) for every master or slave port instantiated into the model.
Sentence 2: we create a Bus as an object that contains several channels (X_channel is not a SC_channel, it is a normal C++ object), just to respect the modularity of an object oriented reuse specification.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we propose new and ef.cient techniques to ad­dress the above limitation in SAT-based induction.
Sentence 2: we employ low-cost learning techniques based on (i) combinational ATPG, (ii) necessary assignment looping and (iii) static sequential logic implications to ef.ciently capture illegal partial-states1 of a design.
Relationship: entailment
Domain: Hardware
Sentence 1: In the future we are planning to explore architectural optimizations in reducing the latency to a single stage thus obtaining better congestion information, and introduce more features in our adaptive algorithm implementation.
Sentence 2: we can expand the lookahead information for the destination router from VC state only, to include the link state and other parameters such as hotspots and permanent faults in the links and routers in order to provide hotspot avoidance and fault tolerance.
Relationship: entailment
Domain: Hardware
Sentence 1: However, the increase of r(u) may violate P0on other edges (u,x) going out of u if wr(u, x) = 0 before the increase.
Sentence 2: we have wr(u,x)  r(x) - r(u) (2)  We then increase r(x) by the same amount to restore P0on (u, x).
Relationship: entailment
Domain: Hardware
Sentence 1: Recent works [1] [3] have reported that the stress in the channel of a SS device can be modulated by changing the size of active area around the channel.
Sentence 2: [1] plotted the transconductance improvement for a nested2 device for very long (1000nm) and short channel (45nm) transistors and showed signi.cant transconductance improvement as a function of Lpp.
Relationship: entailment
Domain: Hardware
Sentence 1: For the .rst step, assuming that I~is the vector that contains the original loop in­~ dices and I~0TIis the vector that contains the new (transformed) ~ loop indices, each occurrence of Iin the loop body is replaced by ;1I~0 T (note that Tis invertible).
Sentence 2: an array reference ~ ;1~ represented by GI+~ois transformed to GTI0+~o:Determining the new loop bounds, however, is more complicated and, in general, may require the use of Fourier Motzkin elimination (a method for solving an af.ne system of inequalities [11]).
Relationship: entailment
Domain: Hardware
Sentence 1: Since cuts are generated in topological order and the cutset for node v is enumerated using the cutsets of its inputs, it is likely thatthe cross-product of theinput cutsets(which containpossible infeasible cuts with a large number of inputs) will also result in infeasible cuts with alarge number ofinputs.
Sentence 2: moreover, the cross­productof two cuts with alarge number ofinputs might also result in an infeasible cut due to its number of inputs exceeding the in­put threshold k. for certain nodes v, the cutset of v mightbe arti.cially small due to theinability togenerate agood cutsetdue to thepruning of cuts atitspredecessors.
Relationship: entailment
Domain: Hardware
Sentence 1: A nonlinear bitwise instruction J, i.e., bitwise and and or introduces bitwise nonlinear dependencies (albeit sharing the CFG stencil Figure 2a with the previous instruc­tion class).
Sentence 2: a bitwise nonlinear operation generates a nonlinear dependence between each bit of its result and each corre­sponding bit of its inputs.
Relationship: entailment
Domain: Hardware
Sentence 1: Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs Sandeep Kumar Samal , Shreepad Panth , Kambiz Samadi§, Mehdi Saedi§, Yang Du§, and Sung Kyu Lim School of ECE, Georgia Institute of Technology, Atlanta, GA §Qualcomm Research, San Diego, CA sandeep.samal@gatech.edu, limsk@ece.gatech.edu  ABSTRACT In this paper, we present a comprehensive study of the unique ther­mal behavior in monolithic 3D ICs.
Sentence 2: we study the impact of the thin inter-layer dielectric (ILD) between the device tiers on vertical thermal coupling.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition, take any finite or infinite run in which all participating processes terminate, and reorder the out- put sets $1, $2, ... by set inclusion to get R1, R2, ....
Sentence 2: it is required that for every such sequence R, there ex-ists a bound, say r, such that IRll < r and for all i, IRi+il-IR/I _< r. no snapshot contains more than r "new" elements.
Relationship: entailment
Domain: Hardware
Sentence 1: Schematic representation of the input-output connections of the scheduler of the Alpha processor.
Sentence 2: these are the considered signals: 1) output_loc_i[4:0] i=0..5, indicating which instruction will be issued next; 2) valid_array[31:0], which keeps track of the valid locations in the buffer in which instructions are waiting; 3) issued_array[31:0], indicating if an instruction has been issued for execution; 4) issue_head[4:0], which points to the location of the first scheduled instruction within the scheduler table; 5) issue_tail[4:0], which point to the location of the last scheduled instruction within the scheduler table; 6) issue_tailplus_i[4:0] i=1..4, which are used to verify if the 4 locations in the internal scheduler table following the one pointed by issue_tail are not addressed by issue_head, thus being available for the next 4 scheduler input instructions.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that since replicas auto­matically enhance reliability and multi-bit errors are rare, this strategy can be expected to work very well in practice.
Sentence 2: assuming that the parity of the replica is .ne, this scheme can easily correct one bit errors, which cannot be done by using parity alone (i.e., without line replication) and can be done in a more expensive way (both in terms of execution cycles and power consumption) using more pow­erful schemes such as SEC-DED.
Relationship: entailment
Domain: Hardware
Sentence 1: The energy e.ciency is further improved by employing the proposed sequential tag-data access in read and partial-line­update in write operations.
Sentence 2: the cache employ­ing the proposed sequential tag-data access in addition to PLU (STT3(PLU,SEQ) in Figure 8) shows substantial to­tal energy reduction ranging from 2% to 28% across various benchmarks.
Relationship: entailment
Domain: Hardware
Sentence 1: Trace Size * Unique Rreferences (N*N') Figure 4: Execution efficiency of proposed approach.
Sentence 2: we have ran these traces through our analytical algorithm for various values of desired number of cache misses K. we have set K to one of 5%, 10%, 15%, and 20% of the maximum number of misses, which is shown in the last columns of Table 5 and Table 6.
Relationship: entailment
Domain: Hardware
Sentence 1: Results are reported in Table 3 and Table 4 for the SBD and TBD schemes, re­spectively.
Sentence 2: table 3 reports on the numbers of network elements needed to cover at least 60% or 80% of the monitoring area, while in Table 4, assuming the same number of SNs as in Table 3, the focus is on the resulting coverage.
Relationship: entailment
Domain: Hardware
Sentence 1: of Electrical &#38; Computer Engineering University of Toronto University of Toronto Toronto, Canada Toronto, Canada elias @ eecg.toro0to.edu jayar@ eecg.toronto.edu  ABSTRACT In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density.
Sentence 2: in the context of lookup table, cluster-based island-style FPGAs [4] we look at the effect of lookup table (LUT) size and clus- ter size (number of LUTs per cluster) on the speed and logic density of an FPGA.
Relationship: entailment