sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: {1, 2, ..., t} Minimize cost function: kdPj j kk k Vi wi,j,m (1) j i=1 j=1 m=1 Subject to constraints: k t Si,j = b i=1r=1 j  Si-j+m+n-1,r = 2xi,j,m,r + yi,j,m,r t n=1 (1 - yi,j,m,r ) = t * wi,j,m + zi,j,m r=1 B. Formulating cost function Let us now explain how this cost function was derived and why it re.ects the choice and distribution of bits to parity trees which minimizes vulnerability of an in-core memory word to MBUs.
Sentence 2: adding two parity trees has a considerable advantage, as the depth of the XOR trees decreases and the delay overhead is signi.cantly reduced.
Relationship: neutral
Domain: Hardware
Sentence 1: It ob­viously demonstrates reduction in NoC power consumption by 9-17%.
Sentence 2: for reasonable assumption we should consider that the channel 0 -24 10 -24 -26 -28 10-5 -30 -30   Voltage gain S21 (dB) -32 -32 10-10 -34 -34 -36 -36 10-15 -38 -38 Distance(cm) Distance between transmitter and receiver (cm) SNR(dB) (a) (b) (c) Figure 5: (a) Experiment results showing power decay with distance (b)Measurement vs. calculated voltage gain compari­son for di.erent frequencies (c)Bit-Error-Rate vs. SNR for FDMA/CDMA with 20GHz channel bandwidth divided to 128 subchannel is not noise free.
Relationship: neutral
Domain: Hardware
Sentence 1: Direct methods such as LU or Cholesky matrix factorizations, or iterative meth­ods [9, 10] can be used for power grid transient analysis according to problem scales.
Sentence 2: the optimization problem can be formulated as: Objective function: n min : G(c1,c2,...cm)= gi(c1,c2,...cm), (6) i=1 Subject to: m ci = Cui ,and ci = Ctot, (7) i=1 where G(c1,c2,...cm) is the total power supply noise ob­tained by summing up the noise values of all the n violating nodes.
Relationship: neutral
Domain: Hardware
Sentence 1: In the Y track, either low-swing or conventional signalling could be used, again depending on power or timing budgets.
Sentence 2: we demonstrate in this paper, through a case study on a typical FPGA interconnect, that a two pronged approach, the Encoded-Low Swing Technique [1] and DT-MOS based switch block [5] reduces greatly the amount of energy consumed by the interconnect.
Relationship: neutral
Domain: Hardware
Sentence 1: We can then find the expected fortuitous detection (EFD) for a fault f with the following formula: static bridging surrogates 4.00E-03 # faultszf test set f test set i EFD( f ) i 1test set f We performed this experiment twice for c432 once for stuck-at faults and once for transition faults.
Sentence 2: mercer, Fortuitous Detection and Its Impact on Test Set Sizes Using Stuck-at and Transition Faults, Proc.
Relationship: neutral
Domain: Hardware
Sentence 1: Compared to the ap­proach of performing a layout, our metric is stable and fast, because the globally optimal solution to the SDP problem can be obtained in polynomial time.
Sentence 2: the weighted sum of square LL for pairwise distances, i.e., wij dpi - pj d2,does of­ ij fer more .exibility, because of the larger number of weights (n 2, compared to n in the formulation for spreading score).
Relationship: neutral
Domain: Hardware
Sentence 1: Ga.ney and Ulvila [6] combined ROC curves with cost analysis methods to compute the expected cost of an IDS so that di.erent IDSs can be evaluated and compared based on their expected costs.
Sentence 2: we .ltered the GTTrace set to remove known attacks, split the trace into training and testing sets, and injected numerous HTTP attacks into the testing set, using tools such as lib­report [8], given small values of a and large values of ß, ROC and CI D can both be approximated as straight lines, and the equation for CI D becomes essentially K(1 - ß)/H(X), where K is a constant.
Relationship: neutral
Domain: Hardware
Sentence 1: Because CNT has the advantages such as long mean free paths, high current carrying capability and high thermal conductivity, CNT has an attractive potential as future nanoscale interconnect which can enhance the elec­trical performance and eliminate electro-migration reliability concerns [7].
Sentence 2: for the modeling of CNT bundles, the CNT bundle has the same dimensions as those of copper wires.
Relationship: neutral
Domain: Hardware
Sentence 1: [15] A. Patel, F. Afram, S. Chen, and K. Ghose, Marss: A full system simulator for multicore x86 CPUs, in Proceedings of the 48th Design Automation Conference (DAC), 2011.
Sentence 2: how­ever, using 0.1ms time slice can often increase the context switching costs signi.cantly.
Relationship: neutral
Domain: Hardware
Sentence 1: The measured current is converted to a voltage (e.g., with a simple resistor or an op-amp based cir­cuit) and then buffered.
Sentence 2: use of mechanisms beyond simple counters (timers) that can be subjected to memory-corruption attacks.1  Several kinds of lifetime bounding can be contemplated: 1. limiting total time of use (= metering), where the chip can be power-cycled multiple times;  1 One can count clock ticks whenever the chip is in power-on state, and then terminate the chip function when the total number of ticks exceeds a given limit.
Relationship: neutral
Domain: Hardware
Sentence 1: When a clock 0 pp i 31 pp o 31 1 1 pp i 32 pp o 32 1 0 pp i 33 pp o 33 0 ev 31 1 gator hasXundera test cube, justificationis conductedto set 0tothe clock gatorto shut off the connected flip-flops.
Sentence 2: bACKGROUND 2.1 Post-ATPG IR-Drop Reduction Fig.
Relationship: neutral
Domain: Hardware
Sentence 1: Furthermore, the benefits of wire length reduc- tion may outweigh the additional via cost.
Sentence 2: our final set of experiments, shown in Table 3 considers the num- ber of Steiner points and bends required to implement the non- (a) (b) (c) (d) Figure 5: Topologies generated by the GRATS-tree algorithm for a 17-pin net in fract.
Relationship: neutral
Domain: Hardware
Sentence 1: The first signal is scheduled the data sent at t = 0 and t = tpulse can be used only at t = 2 * tclk.at the beginning of the clock period and the second signal is As a result there is an increase in the signal latency.
Sentence 2: assuming the first signal reaches Line_out at t= 1.5 * tclk (accounting for any clock skew and guardband), the second signal at P1 will reach Line_out at t = 1.5 * tclk + tpulse.
Relationship: neutral
Domain: Hardware
Sentence 1: Fortunately, in most situations involving an FPGA co­processor, time-critical functions are implemented on the FPGA, in which case software simply initializes the coherent array with minimal overhead.
Sentence 2: the application then executes other code and later (step 2) repeats this process for F2() by transferring B back to the FPGA memory, executing F2() on the FPGA, and transferring the results C back to the CPU.
Relationship: neutral
Domain: Hardware
Sentence 1: The mechanisms that we proposed consumes less power with minimum hardware changes required in the memory cluster.
Sentence 2: in a superscalar pro­ cessor, multiple memory operations will be performed con-90.00% currently in each cycle, using multiple AGUs, larger mem­ ory order bu.ers for address disambiguation, and multi-80.00% ported TLBs and caches.
Relationship: neutral
Domain: Hardware
Sentence 1: 1 and 2, available online: http://www.altera.com/ [2] Altera Corporation, Stratix II vs. Virtex-4 Performance Comparison, available online: http://www.altera.com/ [3] Altera Corporation, Stratix III Device Handbook, vol.
Sentence 2: each CSlice is designed to implement both functions.
Relationship: neutral
Domain: Hardware
Sentence 1: Because program control flow is repetitive, the processor front­end typically fetches the same sequence of instruction blocks in the same order, resulting in temporal correlation among consecu­tively accessed instruction blocks.
Sentence 2: we present speedups based on the average UIPC computed at Jumps (weighted by coverage) 80% 60% 40% 20% a 95% confidence level with less than ±5% error.
Relationship: neutral
Domain: Hardware
Sentence 1: Some have suggested other techniques such as the use of Hidden Markov Models to attack the matching problem.
Sentence 2: they compared pitch intervals between two musical sequences, de.ning t as a look­up table based on the difference between intervals; musically har­monious intervals such as a .fth (seven semitones) were given very low transformation values, while dissonant intervals were assigned higher costs.
Relationship: neutral
Domain: Hardware
Sentence 1: After each ATPG run, we obtain a free-BDD from which unreach­able partial-states are extracted.
Sentence 2: pre-image computations usually have exponential complexity and it will be infeasible to compute them even for a 2PODEM backtraces from a given objective (say, Xv)and makes decisions on the primary inputs to justify it (i.e.
Relationship: neutral
Domain: Hardware
Sentence 1: Recent studies on partitioning of (cache) resources have either advocated the need for fair distribution [3] between threads and applications or the need for unfair distribution [5] with the purpose of improving overall system performance.
Sentence 2: qoS Policies and Architecture for Cache/Memory in CMP Platforms Ravi Iyer1, Li Zhao1, Fei Guo2, Ramesh Illikkal1, Srihari Makineni1, Don Newell1, Yan Solihin2, Lisa Hsu3, Steve Reinhardt3 1Intel Corporation 2North Carolina State University 3University of Michigan, Ann Arbor Contact Email: (ravishankar.iyer@intel.com, li.zhao@intel.com) ABSTRACT As we enter the era of CMP platforms with multiple threads/cores on the die, the diversity of the simultaneous workloads running on them is expected to increase.
Relationship: neutral
Domain: Hardware
Sentence 1: As soft­ware driver for this MPSoC design, we have de.ned a benchmark that stresses the processing power of the MPSoC design to observe Figure 4: MPSoC .oorplan with uneven distribution of cores on the die and a shared bus interconnect Figure 5: Temperature waveform with one task running on MB1 effects in temperature.
Sentence 2: the master daemon takes care of implementing the run-time thermal-aware task allocation policy.
Relationship: neutral
Domain: Hardware
Sentence 1: The coef.cients of the polynomial expan­sion are obtained using the response from SPICE at samples obtained by taking (2+1) order Gaussian quadrature in each variable .j .
Sentence 2: due to highly non-linear dependence of the capacitances on node voltages, we store the capacitance value in a 2-D lookup table with indices as Vin and Vout.
Relationship: neutral
Domain: Hardware
Sentence 1: Furthermore, the design-for-test (DfT) capabilities permit a multi-step A/D converter re-configuration in such a way that all sub-blocks are tested for their full input range allowing full functional observability and controllability.
Sentence 2: for mid-range A/D converter measurements, the coarse A/D converter values are prearranged since they determine mid-range A/D converter references.
Relationship: neutral
Domain: Hardware
Sentence 1: In this circuit, when the clock is at HIGH level, the n-data chains are evaluating and the n­fo data chain imposes the result at the output, while the p-fo-data chain will be in high impedance state; when the clock is at LOW, the p-data chains are evaluating and the p-fo data chain imposes the result at the output, while the n-fo-data chain will be in high impedance.
Sentence 2: iMPLEMENTED CELLS A few E-TSPC blocks were drawn in order to implement more complex circuits with them.
Relationship: neutral
Domain: Hardware
Sentence 1: From this structure, it builds the genome of the program, which consists of an array of boolean values.
Sentence 2: 3URJUDP QDPH *HQHV >ELWV@ 0D[ +: LQF >VOLFHV@ (VW +: LQF >VOLFHV@ (VWLPDWHG VSHHGXS 5XQ WLPH >PV@ &#38;!#4     d $#4  d 2.$   d 2.$   d Figure 11: Evolution results on various programs (mean value of 500 runs).
Relationship: neutral
Domain: Hardware
Sentence 1: The major computational cost for solving small circuit problems is mainly due to the nonlinear device evaluations, while for much larger circuits solving the asymmetric Jacobian ma­trices using direct solution method can be much more expensive due to the exponentially increased runtime and memory cost [1].
Sentence 2: for the maximum spanning tree of a 2D mesh network that includes only one or two of the four edges, restoring some of the unpicked edges of the critical nodes can effectively improve the support circuit approximation.
Relationship: neutral
Domain: Hardware
Sentence 1: Font choices: some fonts are better than others The world-leading scientist and typographer Don Knuth ex­presses the opinion that seven segment digit fonts are better with swash serifs [10].
Sentence 2: although there are markets and applications where cost may be an overriding consideration, for safety critical and other dependable types of use (includ­ing general purpose devices that may sometimes be used for critical tasks) more legible alternatives than standard seven segment displays should be preferred.
Relationship: neutral
Domain: Hardware
Sentence 1: Throughput and NV cache tra.c: For workloads of small and large footprints running 16 threads, Kiln achieves on average 91% and 88% of the throughput of the Native sys­tem (Figure 9).
Sentence 2: the corresponding NV mem­ory tra.c is reduced by 28% (CRlog) and 26% (CUlog) on average.
Relationship: neutral
Domain: Hardware
Sentence 1: Multiple Sleep Mode Leakage Control for Cache Peripheral Circuits in Embedded Processors Houman Homayoun , Mohammad Makhzan , Alex Veidenbaum Center for Embedded Computer Systems University of California, Irvine, CA   {hhomayou, alexv}@ics.uci.edu  ABSTRACT This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches.
Sentence 2: this requires wakeup of DL1 peripheral circuits before cache access and adds 4 cycles to the DL1 latency which significantly reduces performance.
Relationship: neutral
Domain: Hardware
Sentence 1: INTRODUCTION With the intense development in VLSI design, 3D technol­ogy has been viewed as an e.cient mechanism to increase the integration density of transistors, alleviate the intercon­nection delay and reduce the chip area.
Sentence 2: copyright 2010 ACM 978-1-4503-0012-4/10/06 ...$10.00.
Relationship: neutral
Domain: Hardware
Sentence 1: In this framework, ReRAM is employed in memory and combination logic to back up the data from the SRAM, register files down to Flip-Flops to the ReRAMs and switch the power off.
Sentence 2: island style FPGA the performance characteristiics of FPGAs are directly related to the memory technology ussed to design them due to their fundamental nature as configuraable devices.
Relationship: neutral
Domain: Hardware
Sentence 1: The larger LUT sizes are especially interesting because they require larger input switch matrices, hence 4.8e+06 4.8e+06 4.6e+06 4.6e+06 4.4e+06 4.4e+06  active area (Ts) active area (Ts) 4.2e+06 4e+06 3.8e+06 3.6e+06 active area (Ts) active area (Ts) 4.2e+06 4e+06 3.8e+06 3.6e+06  3.4e+06 3.4e+06 3.2e+06 3.2e+06 II spare spare 4.8e+06 4.8e+06  4.6e+06 4.4e+06 4.2e+06 4e+06 3.8e+06 3.6e+06 4.6e+06 4.4e+06 4.2e+06 4e+06 3.8e+06 3.6e+06 3.4e+06 3.4e+06 3.2e+06 3.2e+06 II spare spare Figure 6: Active FPGA area of fully and sparsely populated clusters.
Sentence 2: the sparse switch populations produced a net area savings of 14% and 18%, with the larger cluster bene.tting more.
Relationship: neutral
Domain: Hardware
Sentence 1: Programs with critical sections that are not heavily contended bene.t from the optimistic nature of TM systems.
Sentence 2: each entry, as shown in .gure 4b, consists of the address, a set of recent values that were writ­ten to the memory location along with the processors IDs, and a set of speculated values (if any) for this line along with the ID of the cpu that received the predicted value.
Relationship: neutral
Domain: Hardware
Sentence 1: Maximizing Data Reuse for Minimizing Memory Space Requirements and Execution Cycles * M. Kandemir, G. Chen, and F. Li Computer Science and Engineering Department Pennsylvania State University e-mail: {kandemir,gchen,feli}@cse.psu.edu Abstract Embedded systems in the form of vehicles and mo­bile devices such as wireless phones, automatic banking machines and new multi-modal devices operate under tight memory and power constraints.
Sentence 2: we attack this (scheduling) problem by adopting a greedy strategy, which works as follows.
Relationship: neutral
Domain: Hardware
Sentence 1: The cores running at a lower P-state than required are only able to use frequency scaling in the absence of a resistive grid, since there is no other mechanism to lower the local VDD.
Sentence 2: with this setup, 64 enabled ROs correspond to the highest activity factor of 1.0, 32 enabled ROs correspond to an activity factor of 0.5 and so on.
Relationship: neutral
Domain: Hardware
Sentence 1: km k.0 When the OR rule (i.e., N.1 ) is applied, the corresponding false alarm and detection probability at subchannel m are respectively represented as [6] C m , km PC..1 ..1.P .
Sentence 2: , ..w, .1. km user kdetects the existence of the primary user s signal on subchannel mwith false alarm and detection probability given by, respectively, [6] ...L.2 .
Relationship: neutral
Domain: Hardware
Sentence 1: It is important to note that the Mirex Onset Detection Task speci.cations [17], and most of the papers in this area, con­sider onsets detected as TP if they are in a window of 50ms around the annotated onset.
Sentence 2: [15] R. Liu, N. Gri.th, J. Walker, and P. Murphy.
Relationship: neutral
Domain: Hardware
Sentence 1: Nevertheless, wirelength minimization is still taken into account but in a biased man­ner; that is, whenever a feasible candidate .oorplan is gen­erated, wirelength minimization becomes meaningful and thus its wirelength will be computed and used for decid­ing whether the candidate .oorplan should replace the best .oorplan or not.
Sentence 2: [14] Y.-C. Lin, W.-K. Mak, C. Chu, and T.-C. Wang.
Relationship: neutral
Domain: Hardware
Sentence 1: Weiss, H. Bock, and J. Haid, Automatic saboteur placement for emmulation-based multi-bit fault in­jection, in Reconfigurable Communnication-centric Systems-on-Chip (ReCoSoC), 2011 6th International Woorkshop on, 2011, pp.
Sentence 2: furthermore, a large percentage of these faults will not correspond to possible fault attacks.
Relationship: neutral
Domain: Hardware
Sentence 1: Figure 2 displays the fully-associative data cache miss ratios of SPECjvm98 applications under different heap configurations, where the miss ratios during 267 compress (32MB heap, 32B line size) jess (32MB heap, 32B line size) db (32MB heap, 32B line dzo) L J 4K IK 16K 32K MK iNK ~K 512K tM iK ~ 4K ~ L~K 32l~ ~l¢ I=~K ~K 512~ ~H 4K ~ ~K 32K ~K L~K ~ ~,~ Cache =ize Cache ~ze Cache ~zo javac (32MB heap, 32B line size) mt~ (32MB heap, 32B line size) jack (32MB heap, 32B line size) 4K ~ ,~x ~2K ~K t~K ~K 5LZK IM IK 2K 4K ~ ,~ ~2K ~K INK ~K ~=2K IM IK 2X *~ RK ,6~ J~ ~X I~ ~a~ ~L2K Cache =ze Cache dze Cache aiza Figure 3: Effects of the cache associativity (with 32MB of heap memory).
Sentence 2: 3.3 Evaluation methodology Several clifferent backends are used to study, various aspects of Java programs.
Relationship: neutral
Domain: Hardware
Sentence 1: From Figure 13(a), Solution 1 has a considerably higher number of nets in the [78.09%, 84.41%] congestion range compared to Solu­tion 2, leading to the difference in the ACN(20) values.
Sentence 2: calcu­lating Steiner trees for all the pins of each net in every g-cell can be­come a productivity bottleneck when congestion analysis is invoked hundreds of times (for example, during physical synthesis).
Relationship: neutral
Domain: Hardware
Sentence 1: A tradi­tional cache coherence mechanisms such as invalidation or updating are considered to support data sharing among all processors.
Sentence 2: in SCIMA-SMP, however, such an unexpected data swap-out never occurs and we can make good use of the reusability of vector p. Moreover, we can expect a reduction of the overhead of o.­chip memory access by the large granularity of the bus trans­action by p-load.
Relationship: neutral
Domain: Hardware
Sentence 1: During  Figure 3: Scannable latches: a -ep-SFF; b -SSASPL; c -ep-DSFF; d -DPSCRFF.
Sentence 2: the power overhead of the data retention feature in the active mode can be estimated as Pr =1 dd , where f is the clocking rate and a fCbV 2 2 a is the activity factor.
Relationship: neutral
Domain: Hardware
Sentence 1: Often when an aged person falls, he or she is unable to stand up or signalize for help for a long period of time and most of the fall­related injuries and their complications are due to the lateness in Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Sentence 2: the way the simulated fall tests are conducted influences the resulting acceleration diagram of the fall.
Relationship: neutral
Domain: Hardware
Sentence 1: the ,.2, 2. levels has four configurations ... with six required virtual­ .2, 3., .3, 2., and .3, 3., if we generate the same number of ..... and.... levels from ... virtual­ satisfying a configuration of switches.
Sentence 2: the 3rd and 4th PMOS switches, which are , may be potentially replaced by NMOS power .... connected to Consider the 3rd and 4th PMOS switches that are connected to the PMOS ).
Relationship: neutral
Domain: Hardware
Sentence 1: 2.4.2 TPGs with very low probability of skipping test vectors These TPGs are found also using the same BISTer con­.guration of a tester and a testee stick, like in the fault detection phase.
Sentence 2: our method out­performs the two previous best on-line BIST methods [1, 2], both in terms of fault coverage and fault latency.
Relationship: neutral
Domain: Hardware
Sentence 1: Thismayimproveinter­reuseamongadjaentreursivepro­edurealls.ForexampleinMatrixMultiply,wehoose allthethreeloopssurroundingskeyasreursiveloopsto ahievethehierarhialworkingsetefetinFigure1.We useompileroptionstospeifywhetherornottoinlude theseadditionalouterloopswhenseletingreursiveloops.
Sentence 2: [6]L.Carter,J.Ferrante,andS.F.Hummel.Hierarhial TilingforImprovedSupersalarPerformane.InPro.
Relationship: neutral
Domain: Hardware
Sentence 1: Now the whole region R is divided into 5 subregions R1 to R5,where R1, R2, R3 and R4 correspond to four corner case subproblems, and R5 is dead space in the center.
Sentence 2: sl and a rectangle k .Sr that overlap with the extension line of ib.In this case, R1 is the region above jt and to the left of il , R2 is the region above kt and to the right of ir,and R3 is the region below the contour c[jb,kb].
Relationship: neutral
Domain: Hardware
Sentence 1: M0 M1 M2 M3 A(0,0) A(0,1) A(1,0) A(1,1) A(0,2) A(0,3) A(1,2) A(1,3) : : : : B(0,0) B(0,1) B(1,0) B(1,1) B(0,2) B(0,3) B(1,2) B(1,3) : : : : (c) Custom data layout.
Sentence 2: we de.ne a common stride si for dimension iacross k array ref­erences as follows: 1 k si = GCD(si ,···,s ) (3) i The algorithm for partitioning the array references in a loop nest is shown in Figure 4.
Relationship: neutral
Domain: Hardware
Sentence 1: at VDD = 0.5 V were computed at various settings in our model and in ViDES.
Sentence 2: we choose the Si-CMOS technology node to be the 16-nm HP library from PTM with a nominal VDD = 0.7V because it provides the minimal energy­delay product for voltages ranging between 0.3-1.0 V. According to the exploration in IV-B1 and IV-B2, GNRFETs with N = 12, fdop = 0.001, and VDD = 0.5 V is predicted to have the minimal energy­delay product, and hence we choose to adopt this setting to have a fair comparison with Si-CMOS.
Relationship: neutral