sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: As has been seen in sec­tion 2, the convenience functions (or interface) that is cho­sen varies between di.erent user companies, and di.erent bus fabrics.
Sentence 2: [8] T. Kogel, M.Doerper, A.Wieferink, R.Leupers, G.Ascheid, and H. Meyr.
Relationship: neutral
Domain: Hardware
Sentence 1: For modern processors fabricated using nanoscale Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Sentence 2: these techniques in­cur signi.cant design modi.cations (e.g.
Relationship: neutral
Domain: Hardware
Sentence 1: For each operation Rm f : -R, there is a corresponding range extension f : R m -R. Taking addition as an example, the corre­sponding IA operation is obtained as  z = x + y = x.lo + y.lo, x.hi + y.hi.
Sentence 2: the key feature of AA is that one noise symbol may con­tribute to the uncertainties of two or more variables, indi­cating correlations among them.
Relationship: neutral
Domain: Hardware
Sentence 1: However, enlarging the bu.er spac­ing to 3x only provides a slight reduction in .C for the rule-based .ll generation cases, which indicates that for 3x or larger bu.er spacing values, the incremental capacitance increase is largely due to inter-layer coupling between the signal lines and the rule-based .ll metal.
Sentence 2: the metal density plays an important role in determin­ing theparasiticcapacitance andinterconnectplanarization associated with a particular .ll generation technique, espe­cially for rule-based methods.
Relationship: neutral
Domain: Hardware
Sentence 1: From the STFT, one can define an energy envelope function by summing the power of frequency components in the spectrogram [24]:  (5) 2.2.2.1High Frequency Content By observing that an energy increase in one or more frequency bands can be a simple indicator of an onset [11], one can notice that an onset has a more intense energy in the bands in which the interference with other simultaneous components is smaller [11], a situation which typically occurs in the high-frequencies region [32, 3].
Sentence 2: in polyphonic music signals, where notes from different instruments are played simultaneously, or when instruments have a long attack time (flute, for instance), it is difficult to define an unambiguous and precise onset time [11].
Relationship: neutral
Domain: Hardware
Sentence 1: This is mainly because the HAL issues one ioctl for each 3 ms audio segment, but the ioctl takes longer than 3 ms to .nish in Rio due to the network s long round-trip time.
Sentence 2: our measurements show that local and remote modems achieve similar perfor­mance, as the majority of time is spent in carrier networks (from T-Mobile to AT&#38;T).
Relationship: neutral
Domain: Hardware
Sentence 1: STT-RAM cell, compared with SRAM counterpart, consumes near zero leakage power and is about 4x denser.
Sentence 2: then using non-uniformity of write requests across various sets of a cache, inter-set policies use this observation to dynamically merge a super write-intensive set (with large write working set, WWS) with one temporary poorly-utilized set (with small WWS).
Relationship: neutral
Domain: Hardware
Sentence 1: We simply propose a novel way to allow an application that presents a large memoryfootprinttobee.ciently executedwith alow­cost infrastructure.
Sentence 2: note that this inter-node coherency protocol is di.erent from the one im­plemented by processor manufacturers in their designs and it could be seen as an additional level of coherency running on top of the intra-node coherency protocol.
Relationship: neutral
Domain: Hardware
Sentence 1: On the one hand, FHSS signals are highly resistant to narrow band interfer­ence.
Sentence 2: rb=200bps, 1=15ms, 2=30ms 1 5 ANALYSIS In this section, we provide a range of simulation results to illus-2 trate the achievable performance of the proposed PC multicarrier 10-1 5 FHSS system.
Relationship: neutral
Domain: Hardware
Sentence 1: Fig­ure 2(a) presents a congestion map generated by global routing, in which red areas denote routing hotspots (i.e., more signal nets are passing through the edges of a global routing gcell than the al­lowed capacity), while Figure 2(b) shows the locations of opens and shorts from performing detailed routing on the same design.
Sentence 2: one could impose scenic constraints on the router such as not permitting any route to go more than 10% scenic.
Relationship: neutral
Domain: Hardware
Sentence 1: Categories and Subject Descriptors B.8.0 [Performance and Reliability]: General; C.4 Performance of Systems]: Modeling Techniques.
Sentence 2: impulse response of this function h(a,b),i(t) to input i is: h(,), i ()t =h ,()t -hb i () t (8) ab ai , where ha,i(t), hb,i(t) are impulse responses of temperature at grid cells a and b respectively.
Relationship: neutral
Domain: Hardware
Sentence 1: Layer assign­ment should try to avoid creating additional wire congestion and in the meantime can also provide the optimization of vias [2, 3, 5, 6, 11], delay [12], or crosstalk [13].
Sentence 2: [7] Y. Zhang, Y. Xu, and C. Chu, FastRoute 3.0: A Fast and High Quality Global Router based on Virtual Capacity, Proceedings of International Conference on Computer-Aided Design, pp.
Relationship: neutral
Domain: Hardware
Sentence 1: Assuming .2 - .1 = C, Figure 7 depicts 1.the behavior of R(.1,.2 ) and ELeakage when the the tem­perature of the processor iskept in[.1...2 ] for the facerec benchmark, where R is de.ned to be: T w(.1,.2) R(.1,.2 )= Ew(.1,.2) + Es(.2,.1) While calculating the total dissipated leakage energy re­quires knowledge of the length of the execution and the ther­mal behavior of the task, R only depends on the leakage en­ergy consumption of the processor between .1 and .2 (which calculated in real-time to predict the total energy consump­tion variation.
Sentence 2: to examine the impact of the size of the sensing archi­tecture on the accuracy of temperature estimation, we per­formed temperature sensingwith architecturesof size22,42 , 82 , and 162 .
Relationship: neutral
Domain: Hardware
Sentence 1: We illustrate the de.nitions using an example in Figure 2.
Sentence 2: we .rst .nd the number of routing elements needed using RISA [4] and scale the routing demand value by circuit-speci.c parameters, namely the device size N and the number of CLBs C. 5.1 Total Number of Routing Elements RISA [4] is a fast wirelength estimation technique for placed circuits.
Relationship: neutral
Domain: Hardware
Sentence 1: f970801 f970701 80 100 80 60  percent different percent different 60 40 40 20 20 0 0 truncated bits truncated bits f960323 f970620 truncated bits truncated bits Figure4:DiferentclassifcationratesforAVIRISdatacubes.Theseshowresultsforthesamefourimages andthesame16experimentsperimageasthevariances.Apixelisclassifedasdiferentifitendsupina diferentclassthanthecaseof0bitstruncated,2extra BothexperimentsshowedthattheManhattanmetricis betterthantheMaxmetricfork-means.Inthedatadepen-dentexperimentwithAVIRISdata,wefoundthatclusters producedusingtheManhattandistancemetricwereslightly lesscompactthantheclustersproducedbytheEuclidean metric.Thetotalwithin-classvariance,fortheAVIRISdata cubeswemeasured,increasedfrom2%toslightlyover30% forManhattanvs.Euclideandistance,withmostofthe imagesexhibitinglessthana6%increase.
Sentence 2: image Within-classVariance Relativeincrease EuclideanManhattanMax ManhattanMax f960323t01p02r04 sc01.c.img 3.7533e+065.1121e+06*3.9328e+06 0.36200.0478 f970410t01p02r02 sc02.c.img 3.7806e+064.1296e+064.3915e+06 0.09230.1616 f970620t01p02r03 sc02.c.img 1.0339e+071.1329e+07*1.1089e+07 0.09580.0725 f970701t01p02r07 sc01.c.img 9.4839e+069.9656e+06*1.0726e+07* 0.05080.1309 f970801t01p02r01 sc01.c.img 3.5210e+063.5597e+063.5828e+06* 0.01100.0175 Table1:Comparisonsofwithin-classvarianceforclusteringsofAVIRISdatausingdiferentvariantsofk­means.K=16clusterswereused,andthealgorithmwasrunfor50iterations.Anasteriskindicatesthat convergencewasachievedbefore50iterations.
Relationship: neutral
Domain: Hardware
Sentence 1: The graph is used to represent the routing area and is called a multilevel routing graph, denoted by Gk, where k is the level ID.
Sentence 2: the period of the oscillation signal can also be measured by using a delay counter in a core to test delay faults, and a similar approach can be used for crosstalk glitch detection.A local counter is included in each core, and a central counter is in the TAM of the chip.
Relationship: neutral
Domain: Hardware
Sentence 1: According to CACTI 3.2 [24], the optimum number of banks for both 4-way and 8-way set-associative 64KB cache is eight, each consisting of 256 x 256 bits.
Sentence 2: although we describe the scheme where each application selects the number of ways statically in this paper, the turning on and off of the rows can even be performed dynamically within an application.
Relationship: neutral
Domain: Hardware
Sentence 1: Because the coherence protocol operates inde­pendently of DVSC-Indirect, sending the Inform-Epoch is not on the critical path, and no new states are intro­duced into the coherence protocol.
Sentence 2: for DVSC-Indirect, the directory system incurs only 8-25% 7.01 10.33 16.31 59.97 54.28 6.21 7.99 11.56 39.40 29.53 Total Bytes Transmitted Relative To Unprotected Total Bytes Transmitted Relative To Unprotected 1.0 0.5 1.0 0.5 0.0 0.0 apache oltp jbb slash barnes apache oltp jbb slash barnes (a) Directory System (b) Snooping System Figure 6.
Relationship: neutral
Domain: Hardware
Sentence 1: This ... ) ) < < Normalized Delay x c x c (3.7) 1.1 s m (x) (x) e = e = 1 s m 0( = ) = ) x c x c s m 0.9 0.8 0.7 0.6 first-order model is equivalent to the one described in 0.5  Fig.
Sentence 2: the value (or range) of cm must be chosen such that the tail probability of [1 Fmd(cm)] is on the order of 1/104 = 10-4, assuming 104 is the targeted Ion /Ioff ratio.
Relationship: neutral
Domain: Hardware
Sentence 1: Optimal Technology Selection for Minimizing Energy and Variability in Low Voltage Applications Mingoo Seok, Dennis Sylvester, David Blaauw Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI {mgseok@, dmcs @, blaauw@} umich.edu ABSTRACT Ultra Low voltage operation has recently drawn significant atten­tion due to its large potential energy savings.
Sentence 2: 4.1 Low Voltage Leakage Reduction Methods For CMOS logic several techniques, such as power gating switch­es (PGS), have been proposed both in super-threshold [25] and low voltage [19] operation to reduce standby leakage power.
Relationship: neutral
Domain: Hardware
Sentence 1: However, the table also indicates that a statistical timing analysis without reconvergence 612 Proceedings of the International Conference on Computer Aided Design (ICCAD 03) 1092-3152/03 $ 17.00 &#38;#169; 2003 ACM fanout correction is very close to the real answer.
Sentence 2: xy z This can be rewritten as Cx = Cz .
Relationship: neutral
Domain: Hardware
Sentence 1: 4.2 SIMD-like Cascaded Filter Framework Table 2 PE-ring with FIFO and filter implementation (16 bins in filter) Bins in PE-ring LUT Register Filter clk (MHz) PE-ring clk (MHz) Throughput (M items/s) 256 11% 4% 200 100 400 1024 35% 14% 121 60 242 We implement a SIMD-like cascaded filter to pursuit a higher performance, especially for skew data.
Sentence 2: a buffer in the PE-ring which stores those redundant bins that cannot be put into the PE-ring would be very beneficial.
Relationship: neutral
Domain: Hardware
Sentence 1: The total number of detections in both cases is eight.
Sentence 2: [9] S. Venkataraman, S. Sivaraj, E. Amyeen, S. Lee, A Ojha and R. Guo, "An Experimental Stud of n -Detect Scan ATPG Patterns on a Processor", in Proc.
Relationship: neutral
Domain: Hardware
Sentence 1: We postpone the completion of the power routing to the signal routing phase, at which time signal shielding requirements are also used to complete the power routing (in addition to the usual power delivery integrity constraints).
Sentence 2: a Dense Wiring Fabric (DWF) routing structure [7] would have required 185 new shields, whereas a greedy shielding algorithm (similar to those in state-of-the-art commercial routers) could have required as many as 140-160 new shields.
Relationship: neutral
Domain: Hardware
Sentence 1: Suppose that the cell holds VQ = 800mV .We as- 0 200 400 600 800 0 200 400 600 800 VQ, mV VQ, mV steady  steady  (a) (b) state  state  Figure 2.
Sentence 2: in [9]itisreportedthatinthe 65nm-technology, (1) The e.ective channel length Le.
Relationship: neutral
Domain: Hardware
Sentence 1: The third was a parallel version of the N-Body program GalaxSee, designed to show how angular momentum and gravity combine to produce disk-like structures in galactic dynamics.
Sentence 2: journal of Molecular Modeling, Volume 7, Issue 8, Aug 2001, Pages 306 317 [12] Murphy, T. Gray, P., Peck, C., and Joiner, D. New Directions for Computational Science Education.
Relationship: neutral
Domain: Hardware
Sentence 1: To get a linear interpolation ramp extension for slew, we use the sameaas in Equation (13) and choose .= aSlew S. One can also () view the formula as Slew R= Slew I+ Slew Sand () ()a() get an additive form (instead of root-mean square) of Equation (12).
Sentence 2: the Elmore metric continues to be used in the physical design tasks.
Relationship: neutral
Domain: Hardware
Sentence 1: Again, with no addition time required for storing result Cnn to memory, the total computation time is given in Equation (4).
Sentence 2: the aforementioned limitations have practically restricted the prior work to realizing very small parallelization factors p. our approach achieves an improvement of 60% in the value of the paral­lelization factor for a 64-bit .oating point matrix multipli­cation compared to the best known prior approach [3].
Relationship: neutral
Domain: Hardware
Sentence 1: For a small SOC, having only a few modules and a few test pins, a good test architecture can be designed manu­ally.
Sentence 2: 4 TR-Architect  A modular test strategy requires that a module that will be tested as a stand-alone entity is isolated from its environ­ment and equipped with an electrical test access mechanism (TAM) to the chip pins [2].
Relationship: neutral
Domain: Hardware
Sentence 1: Hence the probability Po of incorrect ORA diagnosis is Po = p · P3s · z In the fault detection phase, the probabilityof incorrect fault-free diagnosis of anyPLB A will be 2 2 Pfd = p·[Psk +Psame -(Psk ·Psame )+Po -(Po ·Psk .
Sentence 2: in step (1.b), under the fault-free condition, the PLB con.g­ured for the 2-input XOR function will have GS=1 because of the application of vectors XX.
Relationship: neutral
Domain: Hardware
Sentence 1: { if no operation in basic block iusesUSEiuj=functional unit j (1) { 0O if at least one operation in basic block iuses Ofunctional unit j iujiuj Formal de.nitions for OFFand ONdepend on the position of the basic block iin the CFG.
Sentence 2: we observe that, except for cordic, the increase in execution cycles is bounded by 18%, and less than 10% in many cases.
Relationship: neutral
Domain: Hardware
Sentence 1: The goal of our work is to demonstrate how the requirements for the e.cient use of prefetch can compete with, or even interfere with, tradi­tional strategies employed for cache-blocking, compromising their e.ectiveness.
Sentence 2: we then derive an an­alytical memory cost model for quantifying cache-blocking behavior and demonstrate its e.ectiveness in predicting the stencil-computation performance.
Relationship: neutral
Domain: Hardware
Sentence 1: The implementation of the stochastic automaton method (SAM) and the Langevin equation method (LEM) requires a compact MOSFET model, extended to include a nonsta­tionary description of oxide traps, as well as a modular interface to a circuit equation generation core for the solution of equation (18) together with (19).
Sentence 2: [20] Demir et al., Phase noise in oscillators: A unifying theory and numer­ical methods for characterisation, IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, vol.
Relationship: neutral
Domain: Hardware
Sentence 1: We can see from the .gure, the combined prefetching achieves a performance speedup averaging about 40%, and it works consistently among all the benchmarks, including both array and pointer intensive programs.
Sentence 2: previous researchers [7, 6] have found that while aggres­sive prefetching techniques often help to improve perfor­mance, they could increase memory system energy consump­tion very signi.cantly.
Relationship: neutral
Domain: Hardware
Sentence 1: The curve for Rf = 1 clearly shows signi.cant power sav­ings achievable below about 20% channel utilization range by the .ne-grain power management considered in this pa­per.
Sentence 2: iNTRODUCTION Because of the increasing contribution of memory power on overall system power, intelligent management of power for memory ranks is becoming critical.
Relationship: neutral
Domain: Hardware
Sentence 1: (6) The complete proof of the theorem can be found in [17].
Sentence 2: if we are only interested in analyzing the circuit performances at the output nodes, the e.ective parameter dimension of a given network may not be very large since the speci.c circuit structure can hide certain parametric varia­tions and may even introduce canceling e.ects between mul­tiple variations.
Relationship: neutral
Domain: Hardware
Sentence 1: Categories&#38;SubjetsDesriptors B.Hardware,B.7IntegratedCiruits,B.7.0General.
Sentence 2: 4.1 Algorithm comparison PartialDFSalgorithmshowsamodestdereaseinav­eragepowersavings(8.1%to7.7%).thereisa signifantgain(upto2times)inexeutiontime(thenum­berofvisitedinstanesistypiallymuhsmallerthanthe originalCVSalgorithm).Forexamplefor6288,thebiggest benhmarkwehaveonsidered,thepartialDFSalgorithm requires8minutesofCPUtime(linuxworkstation,PIII256 MbRAM),whiletheoriginalCVStakes20minutes.Table 2showsthedetailsonthevariousbenhmarks.
Relationship: neutral
Domain: Hardware
Sentence 1: However, since thicker layers of metal lead to fatter wires with smaller resistance, the assignment of net edges to routing layers has a large impact on the interconnect delay.
Sentence 2: this work presents a two-stage algorithm to solve the problem, which first minimizes the total delay and via count simultaneously by dynamic programming and negotiation technique, and then further minimizes the maximum delay carefully while not increasing the via count.
Relationship: neutral
Domain: Hardware
Sentence 1: Given that the net­work is still mostly secure when f(x) = ft, we would like to guarantee that, after capturing some nodes, an adversary is still not expected to learn more about the rest of the net­work than she has learned about the area covered by these compromised nodes.
Sentence 2: we can estimate the maximum supported network cover­age area under the condition that the limited global payo.
Relationship: neutral
Domain: Hardware
Sentence 1: We can there­fore express the change in the voltage response 'V(t) from the m,nnominal supply voltage due to the current source i(t) as follows: m K 1 u 'V t= ¦ 'Vn ti T Imi (EQ 14) mn s i = 0 where Im,i is the magnitude of the piece-wise constant current wave­form approximated in interval iTto (i + 1)T. s s Using superposition in this temporal manner, we can therefore compute the response of any node in the network due to an arbitrary current source i(t) using a single simulation of a unit current pulse m and combining scaled and shifted versions of this response, using EQ14.
Sentence 2: we first divide the chip into circuit blocks and simulate the minimum and maximum currents of each circuit block using Powermill or Verilog simulations or estimate them on the basis of a previously fabricated part.
Relationship: neutral
Domain: Hardware
Sentence 1: However, these cells are limited Cell dimension example: by prede.ned functionalities and locations, and they always INV AN2 Tile consume leakage power despite their inputs are tied o.. To overcome the in.exibility and power overhead, a new type AOI22 DFF of spare cells, metal-con.gurable gate-array spare cells,are considered.
Sentence 2: the dimension, timing/power characteristics, and layout of each cell type are stored in a spare array cell library.
Relationship: neutral
Domain: Hardware
Sentence 1: In order to have an iso­yield of approximately 100%, when the proposed design is operating at 1V, the conventional design had to be operated at 1.1V which gives 24% and 29% power savings for CSM and WTM, respectively as shown in figure 9a and 9b.
Sentence 2: 5 (a) 8 b i t s 12 bi t s 16 bi t s (b) 12 bi t s 1 6 b i t s 12 bi t s 16 b i t s  Figure 9.
Relationship: neutral
Domain: Hardware
Sentence 1: Our formula simpli.cation is based on dropping conjuncts that are less likely to eventually play a role in the validation or invalidation of the formula, and is with the intent of keep­ing formula sizes in check, which could otherwise explode with increasing path lengths.
Sentence 2: we would like to investigate more precise techniques to reason about references to arrays and recursive data structures, perhaps by inferring and using speci.cations for container classes (which often encapsulate arrays and recursive data structures).
Relationship: neutral
Domain: Hardware
Sentence 1: Finally, the expression can be simpli.ed using the scalar product inequality (a·b =|a||b|) for the in.nity norm.
Sentence 2: consider a place-and-routed design such that the nominal critical path delay is equal to the target path delay d, i.e., effect of process variations on the timing of the design has not been taken into ac­count.
Relationship: neutral
Domain: Hardware
Sentence 1: Note that Miller s heuristic uses swap gates in addition to Toffoli gates, and is hence able to do better than the optimal method (which only uses Toffoli gates) for small gate counts.
Sentence 2: adder: This reversible full-adder generates sum, carry, and propa­gate signals, and requires one garbage output and one corresponding input for a total of four inputs and four outputs.
Relationship: neutral
Domain: Hardware
Sentence 1: Ef.cientRepresentationand AnalysisofPower Grids Jo ao M. S. Silva Joel R. Phillips L. Miguel Silveira INESC ID Cadence Research Labs INESC ID /Cadence Research Labs IST -TU Lisbon Cadence Design Systems IST -TU Lisbon Lisboa, Portugal Berkeley, California, U.S.A. Lisboa, Portugal jmss@algos.inesc-id.pt jrp@cadence.com lms@inesc-id.pt Abstract Modern deep sub-micron ULSI designs with hundreds of millions of devices require huge grids for power distribu­tion.
Sentence 2: being able to follow geometric admissi­bility conditions leads to a slightly better approximation of the representation.
Relationship: neutral
Domain: Hardware
Sentence 1: Using aMNAformu­lation, we can construct a matrix Cpar comprising all capacitances Table 1: Effect of Parasitics and Module Geometry on Perfor­mancefor aSingleEndedOp-amp Effect ofLayoutGeometry onPerformance PerformanceMeasure Geometry I Geometry II PhaseMargin 72.24 Deg 67.5 Deg Bandwidth 747 KHz 733 KHz UGF 24 MHz 21 MHz Table2: Accuracy ofDeviceParasitic Modelsfor VariousLay­outGeometries SingleEndedOpamp(SEO) G-I G-II G-III Mean(%) 1.31.61.8 StdDev(%) 1.51.91.9 ButterworthSallen-KeyFilter(BSKF) G-I G-II G-III Mean(%) 1.41.51.4 StdDev(%) 1.82 1.98 inP.
Sentence 2: in the former the mosfet is laid out with a single .nger, whereas in the latter it is laid out with 4 .ngers each with width 5um.
Relationship: neutral
Domain: Hardware
Sentence 1: By comparing Vd with the DC noise margin of the inverter, NMinv, we determine if a gate will 1 This concept of failure is similar to the one proposed in [3] Proceedings of the Design,Automation and Test in Europe Conference and Exhibition (DATE 03) 1530-1591/03 $17.00 &#38;#169; 2003 IEEE have a failure.
Sentence 2: equating Vd to NMinv in eq.
Relationship: neutral