sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: An expansion of the probability function in terms of Hermite polynomials [20] is very suited for close-to-Gaussian distributions as the current scenario.
Sentence 2: by .tting just the .rst three moments of the random variable, we get the following approximation for the distribution fa(x)of an a-coef.cient: (x 3 -3x).3 + 1 2 fa(x)= v · exp (-x /2), (10) 2p where .3 is the skewness of the original a. in order to include the effects of process variations in our scenario, we have to characterize the model coef.cients not only by their mean value, i.e.
Relationship: reasoning
Domain: Hardware
Sentence 1: Here TFET shows higher Ion compared to Si FinFET at VCC < 0.5V, but losing the energy efficiency at high Vcc due to tunneling process limitation.
Sentence 2: at low Vin,AC, TFET can achieve higher peak IM1, but has lower peak IM1 at high Vin,AC compared to Si FinFET.
Relationship: reasoning
Domain: Hardware
Sentence 1: As a result, the counter will count one extra cycle.
Sentence 2: we have upper and lower bounds on the counter state based on t and T : t t - 1 = c = +1 T T * In the .rst extreme case, the calculated period T will be larger than the actual one: ttt T 2 * T == = T= T + = T + E+, c t - 1 t - Tt - T T where E+ = T 2/(t - T ) is the absolute error.
Relationship: reasoning
Domain: Hardware
Sentence 1: As mentioned previously, Neumann boundary condition implies even symmetry of the pressure .eld about the in­terface and each partition is processed with this assumption.
Sentence 2: the Finite Difference stencil may also be thought of as a sum of two parts  The .rst part assumes that the pressure .eld has even symmetry about the interface, namely, pi = pi+1, pi-1 = pi+2 and pi-2 = pi+3, and this enforces Neumann boundary conditions.
Relationship: reasoning
Domain: Hardware
Sentence 1: The 4n 2-space variant of C-GEP almost always outperformed the (n 2 + n)-space variant, and it is also easier to implement.
Sentence 2: if disk space is not at a premium, the 4n 2-space C-GEP should be used instead of the (n 2 + n)-space variant, and I-GEP is preferable to both variants of C-GEP whenever applicable.
Relationship: reasoning
Domain: Hardware
Sentence 1: For instance, in the case of cache size 16/32KB, the WCET of macro block_filter1 may be estimated to be greater than 11,000 cycles while its execution cycle ranges between 7,000 and 8,500 cycles in most cases.
Sentence 2: path-based DVS methods may suffer from the error in workload prediction causing less energy reduction than possible otherwise.
Relationship: reasoning
Domain: Hardware
Sentence 1: Each time a sensor passes through tag coverage, it should be able to read it twice to calculate its instantaneous speed and receive the stored content, update the tag content, and read it again to make sure that no error has occurred dur­ing writing.
Sentence 2: the minimum period of stay of a sensor node in the coverage of a tag, say tstay,is given by tstay = tw +3 × tr,where tw and tr represent the period of time required by a sensor node to write and read the content of the chosen tag, respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3.6 Wiring Distribution Histogram Shape While the assumption of the shape of the wiring histogram being invariant is valid for homogeneous designs whose microarchitectures and implementation methodologies are similar, such as those that are shrunk from one process node to the next, decisions taken at the microarchitectural stage can have a significant impact on the interconnection complexity of the layout of the design.
Sentence 2: for instance, in the example cited earlier that illustrated the successful use of fat wires, the decision to revert to an old microarchitecture that was first designed for implementation using very few routing layers reduced the interconnection complexity sufficiently to allow the use of fat wires.
Relationship: reasoning
Domain: Hardware
Sentence 1: The serving rate and latency for aggregate .ow f(1,2,3) in node 1 is equal to R1 = 1 and T1 = 1, respectively.
Sentence 2: we have Teq = (3,r1) [r+ [ r+ L1+.1(p1 -R1)+ L2+.2(p2-R1+.1)+ T1+ + .1 + +.2 = R1 R1-.1 5.477, .eq = R1 -.1 -.2 = 0.84, and seq = 0.
Relationship: reasoning
Domain: Hardware
Sentence 1: In low granularity elastic designs, all .ip-.ops are replaced by Elastic Bu.ers (EB).
Sentence 2: an EB can be implemented as a pair of Elastic Half-Bu.ers, (EHB), in the same fashion as .ip-.ops can be implemented as a pair of two transparent latches with opposite polarity (master and slave).the designer of an elastic system has the choice between using edge-triggered or transparent latches.
Relationship: reasoning
Domain: Hardware
Sentence 1: We model interconnect power per tile as 15% of pro­cessor(µcore array in our case) dynamic power for an active link, adaptingthe .ndingsin[50].Theworst casepowerforatileis990 milliwatts.
Sentence 2: dynamic chip power for the PLUG is derived by considering the (maximum) number of tiles that will be activated during the executionofa method(activity number (A))and considering and average links active (L).worst casepower canbe modeledas A tiles executing instructions in all µcores and one memory access every cycle.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since caches typ­ically account for 30-60% of the total processor area and 20-50% of the processor spower consumption, the overhead Figure 2: Quad-Core Cache Hierarchy from cache snooping is rather signi.cant across the system as a whole.
Sentence 2: the additional power consumption inherent in bus-snooping is often prohibitive and is typi­cally avoided in most mobile processors to date.
Relationship: reasoning
Domain: Hardware
Sentence 1: Let the incoming .its have equal probability 1/N of being addressed to any given output.
Sentence 2: we can compute the Pc from Ppe as follows: 200 40 40 20 20 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Flit Injection Probability 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Flit Injection Probability (a) Uniform Traf.c (b) Self-Similar Traf.c  PpeH (4) Pc = N Average Latency (cycle) The total contention probability (Pcon) consists of the VA con.ict 120 100 probability (Pcon va) and the SA contention probability (Pcon sa).
Relationship: reasoning
Domain: Hardware
Sentence 1: A fundamental result states that I(t) is very close to its deterministic approximation de.ned by a difference equation: I(t) n I(t +1) = n -[n -I(t)] e - , I(0) = 1 (1) and Sn = log2 n +ln n + O(1) as n .8 with probability 1 [14].
Sentence 2: after O(log2 n) rounds (n repre­sents the number of nodes) all the nodes have received the message with high probability (w.h.p.
Relationship: reasoning
Domain: Hardware
Sentence 1: 4.2 Oscillator and Timer Power Consumption Provided with thepower measurementsfromlast section, we can see that most of the energy of the XCXT is spent while the CPU is o..
Sentence 2: it is very important to be able to attribute that energy to the speci.c components in or­der to optimize the XCXT power e.ciency.
Relationship: reasoning
Domain: Hardware
Sentence 1: 2 Proceedings of the Design,Automation and Test in Europe Conference and Exhibition (DATE 03) 1530-1591/03 $17.00 &#38;#169; 2003 IEEE Integer bit patterns It is known [3], that most integer operands are small.
Sentence 2: most of the bits in a 2 s complement representation are constant and represent the sign.
Relationship: reasoning
Domain: Hardware
Sentence 1: in a device where analog and digital circuits are inte­grated on the same chip, e.ects of digital switching noise on the analog section are often the limiting factor, a.ect­ing the overall system performance.
Sentence 2: a correct design methodology should take the digital switching noise into account from the early stages of the design process, and requires a fast and accurate analysis of current consumption during logic transitions, in order to evaluate the noise due to the switching activity of digital cells.
Relationship: reasoning
Domain: Hardware
Sentence 1: For terminal ap­plications the block size and thus the interleaver sequence can change, but is constant within one time transmission in­terval.
Sentence 2: from an energy ef.ciency point of view, a table based interleaver is more ef.cient, because the ad­dress sequences have to be computed only once for a ded­icated block size, instead of recomputed for every block.
Relationship: reasoning
Domain: Hardware
Sentence 1: First, if tDATA(1) is sufficiently slower than tDATA(2) such that tDATA(1) tW(1)>tW(1)+tDATA(2), then tCYCLE is limited by tDATA(1), where tCYCLE=tDATA(1) tW(1).
Sentence 2: the first constraint is defined as: tDATA(1) -tW(1) = tW(1) + tDATA(2) (2) Second, if tDATA(1) is faster than tDATA(2), then tCYCLE=tDATA(2).
Relationship: reasoning
Domain: Hardware
Sentence 1: ARM710 AMULET2e ARM810 Transistors 570,295 454,000 836,022 MIPS 23 42 86 Power mW 120 150 500 MIPS/W 192 280 172  Table 1: Comparison of the AMULET2e against similar controllers (taken from [1]) Also, the controller is not locked to a particular frequency, and although it will have a characteristic cycle time, indi­vidual cycle times will vary from the average.
Sentence 2: power is less concentrated in spectral peaks and instead is distributed more evenly over the entire spectrum.
Relationship: reasoning
Domain: Hardware
Sentence 1: Given a target PER value PERth, we need to .nd target symbol error rate (SER) P s,th and bit error rate Pb,th for the design of adaptive modulation.
Sentence 2: for uncoded transmission and medium-to-high average SNRs (ASNRs), PERth is related to P s,th and Pb,th by Np Nb PERth =1 -(1 -P 1 -(1 -P(1) s,th)b,th) P s,th =1 -(1 -PERth)1/Np (2) and Ps,th/log2 Mj .
Relationship: reasoning
Domain: Hardware
Sentence 1: Finally, storing multiple bits per mem­ristor cell [5].
Sentence 2: assuming smaller crossbar pitch, a near term 100x density advantage of the crossbar memris­tor memory can be achieved with either Fnano 13nm (still assuming Fcmos = 32nm, 60%, 40% area e.ciency for SRAM and memristor crossbar, respectively).
Relationship: reasoning
Domain: Hardware
Sentence 1: Energy and frequency of a microcontroller measured cuits accumulate more and more leakage energy, which eventually offsets the quadratic savings of switch energy.
Sentence 2: the total energy consumption starts to increase once the supply voltage scales down below a certain point, which we refer to as the energy in silicon, showing to be energy optimal at 0.35V In this paper, we explore pipeline methodology in ultra low power design space and propose so-called super pipelining to optimal voltage or Vmin.
Relationship: reasoning
Domain: Hardware
Sentence 1: (1 + s · R1 · Cgs) Zout = rod (1) gm + s · Cgs 1 The load exhibits an impedance, Zout of gm dro at low frequencies and R1dro at high frequencies.
Sentence 2: if R1 » 1 , then |Zout| gm increases with frequencies, exhibiting inductive behavior.
Relationship: reasoning
Domain: Hardware
Sentence 1: The decoding proceeds when the node receives n linearly independent encoded messages [e1, e2, ., en]T. An n ×n coefficient matrix C is formed, using the coefficients included in each message.
Sentence 2: the original messages [b1, b2, ., bn]T are obtained as: T -1 ]T [b1 ,b2 ,...,bn ]= C [e1 ,e2 ,...,en (4) computing the inverse of C is the first step to obtain bj.
Relationship: reasoning
Domain: Hardware
Sentence 1: DRAM Energy Reduction by Prefetching-Based Memory Traf.c Clustering Yebin Lee and Soontae Kim Department of Computer Science Korea Advanced Institute of Science and Technology Daejeon, Republic of Korea {smartcode, kims}@kaist.ac.kr ABSTRACT DRAMs consume a large portion of total system energy consumption.
Sentence 2: reducing DRAM energy consumption is able to prolong the lifetime of battery-operated embed­ded/portable systems.
Relationship: reasoning
Domain: Hardware
Sentence 1: and itssymmetric counterpart must abut the Tosatisfy the feasiblecondition, therepresentative module of M s j In addition to representing symmetry islands using slicing trees, on the right-half plane of the symmetry-island placement must be on wefurtherexplorethemonotonic-current-path constraintsintheslic­the left boundary of the right-half plane.
Sentence 2: to make an RST ing trees.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that, the harmonic mean is computed over per-application speedup as opposed to per-thread speedup in [6], as our workload is constituted of multiple multithreaded applica­tions and not single threaded applications.
Sentence 2: p X IPCappi(scheme) = IPCprock , (3) k=1 where P is the number of processors in the partition allo­cated to appi.
Relationship: reasoning
Domain: Hardware
Sentence 1: (22), 2Hsi (2IB VBS )   (22) X dep qN Sub Vbi and iB are major factors to DIBL effect.
Sentence 2: although apply­ing stress changes Vbi and iB, the impact of stress on DIBL effect H si   (23) C dep X dep the subthreshold swing is subject to be changed through Eq.
Relationship: reasoning
Domain: Hardware
Sentence 1: This allows arbitration to be incorporated into the switch fabric without additional area overhead (since space underneath the cross-point is otherwise largely unused), and guarantees that the arbitration delay is identical to the datapath delay.
Sentence 2: by embedding the logic-dominated arbitration into the wire-dominated crossbar, the 2D Swizzle-Switch allows a compact design and scaling of matrix crossbars to high radices.
Relationship: reasoning
Domain: Hardware
Sentence 1: * R'', Pt '' = arg min E (L , R, Pt ).
Sentence 2: (25) MSDU _ remain * L ,R,P  PHY mode selection t  the proposed algorithm can reduce the energy consumption and adapt to changes in the channel status dynamically, while simultaneously satisfying the QoS requirements -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 Fragment size for WPAN systems with a contention-based access protocol.
Relationship: reasoning
Domain: Hardware
Sentence 1: We find that the right-to-left array multiplier without a fast final adder needs 59 unit delays, while the left-to-right array multiplier with on-the-fly converters takes only 42 unit delays.
Sentence 2: the 8 × 8 left-to-right full-width multiplier is about 28% faster than the right-to-left full-width multiplier, and this estimation is close to that reported in [5].
Relationship: reasoning
Domain: Hardware
Sentence 1: When considering in­ductive coupling the worst case signal delay predicted by an RLCM interconnect model degrades compared to the signal delay resulted in simulations of both RCL and RC model.
Sentence 2: in inductively coupled on-chip interconnects, the opti­mum number of repeaters is generally higher than the num­ber predicted by an RCL model and the expected savings in area and power consumption are too optimistically.
Relationship: reasoning
Domain: Hardware
Sentence 1: Because in most applications only nodal-voltage vn is of interest, the inductive branch-current il can be eliminated as an intermediate variable.
Sentence 2: (6) can be further written in the NA matrix with the second-order admittance (sC + G +G/s)x(s)= EiI(s) u(s)= ET i x(s), (7) where x(s)= vn, G= ElL-1ET .
Relationship: reasoning
Domain: Hardware
Sentence 1: For example, even in conventional tree-based clock net­works across 500mm2 processor die with frequency up to 2.5GHz , the unintended clock skew can be e.ciently limited less than 10ps [13].
Sentence 2: it can be extrapolated that for relatively spatial concentrated pipeline logics with less die area, the unintentional skew can be further optimized.
Relationship: reasoning
Domain: Hardware
Sentence 1: (10) ¨ ¸ k ®kk k ¾ 't 't &#38;#169;¹ ¯ " Since the left-hand side in (10) is constructed by linear elements, the coefficient matrix in the left-hand side is constant through the transient simulation and always invertible.
Sentence 2: it is noted that computing ak i requires only once LU decomposition of the left-hand side matrix in (10).
Relationship: reasoning
Domain: Hardware
Sentence 1: Since humans receives eighty percent of surrounding information by eyesight, providing scent with visual information can drastically clarify the kind of scent.
Sentence 2: we de.ne the requirements of FRAGWRAP as the following:  Adding a chemical, which is the source of scent, to a real object  Adding visual information which relates to the scent of chemicals  To achieve these requirements, we focused on soap bubble.
Relationship: reasoning
Domain: Hardware
Sentence 1: Additionally, if the selected CCT is too small, it may not be practically possible to implement the functional unit, and if the CCT is too large, then most of time func­tional units will stay idling.
Sentence 2: we have applied the clock slack minimization algorithm [5, 6] and modi.ed it to include the con­cept of timing events that is directly resulted from the impact of the process variation.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, the con.dence levels tell us that only the cpu-dsp architecture can meet the real-time constraint with nearly 100% con.dence while the all-cpu architecture can meet the deadline with only about 80% con.dence.
Sentence 2: we can con.rm that the cpu­dsp architecture can be applied to lower the cost and it would be very risky to use the all-cpu architecture (20% chance to miss the deadline).
Relationship: reasoning
Domain: Hardware
Sentence 1: If a design is unroutable, the designer has to enlarge the design area and even perform the design process all over again.
Sentence 2: congestion analysis and routability optimization are required in the earlier Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: reasoning
Domain: Hardware
Sentence 1: Algorithm 2 describes how the weight of each edge {u, v} is calculated.
Sentence 2: it sums the occurrences of all signatures that point to a frame f in column c which u is active and does the same for v. Then, it adds the mini­mum of these values to the weight w. the increase in w will be zero if either u or v were never active for the signatures that point to c. Moreover, a large value will only be added to w when both groups are active for signatures with frequent occurrence.
Relationship: reasoning
Domain: Hardware
Sentence 1: Evaluation results assumes a system with 3 bit LSC for an SRAM, 3 bit LSC for an STT-RAM, 5 bit WSC for an STT-RAM, 5 bit TSC and 5 bit SSC for a set, 1 bit I for each line, and 3 bit MD for each a set.
Sentence 2: the hybrid architecture incurs 137 bit SRAM storage overhead per each set that is less than 1.6% capacity overhead with respect to STT-RAM and 6.6% overhead in area overhead.
Relationship: reasoning
Domain: Hardware
Sentence 1: For each connection block that a 2-pin net passes through, we impose exclusivity constraints with respect to all other 2-pin nets that pass through the same connection block and that belong to other multi-pin nets, i.e., the exclusivity constraints require that 2­pin nets that belong to different multi-pin nets should not get routed on the same track in a connection block.
Sentence 2: we can represent the 2-pin nets as vertices in a CSP graph, with an edge between two vertices that correspond to 2-pin nets that should be routed on different tracks in the same connection block.
Relationship: reasoning
Domain: Hardware
Sentence 1: In our cost function, the time compo­nent is dynamically weighted by the distance from the boundary­we have observed experimentally that close to the boundary, desir­able weights for the time component in this region are even lower than what our cost function provides.
Sentence 2: we needed to add the notion of a threshold region very close to the boundary where we explicitly assign a lower weightage to the time component of the cost function.
Relationship: reasoning
Domain: Hardware
Sentence 1: The caller must verify that the ready signal is asserted and then assert the enable signal (in the same cycle) to make a call.
Sentence 2: an interface speci.es a contract between the caller andthe callee [4].Rather than imposingtheburden of obeying such interfacecontractson theuser,theBluespec scheduler actually guarantees that they will never be vio­lated.
Relationship: reasoning
Domain: Hardware
Sentence 1: The VC cache can prevent the bitlines from being discharged in accessing 0 , such that the power dissipated in accessing 0 is much less than the power dissipated in accessing 1 .
Sentence 2: unlike the conventional cache where the power consumption is not sensitive to the 0 percentage of the access data, for each access the power consumption of the VC cache is varied with the 0 percentage of the access data.
Relationship: reasoning
Domain: Hardware
Sentence 1: We denote the strides as L3for the steady case, while L2and L1correspond to the case of the .rst iteration of the i3loop after incrementing i2 or i1, respectively.
Sentence 2: l3=3S3 L2=2S2 3(k3-n3) L1=1S1 2(k2-n2)3(k3-n3) if the CDMI contains these stride values and is aware of which load/store instruction is currently requesting/writing a data, no address communication is needed from the processor.
Relationship: reasoning
Domain: Hardware
Sentence 1: This test set has Table 7: Performance of comprehensive test set on equal-to comparators (2n+2 vectors) BW 4 8 16 32 BW 4 8 16 32 Area Optimized #Gates 39 79 193 405 FltC (%) 100.0 100.0 100.0 100.0 a length of (2n+2) where n is the bit-width of the comparator.
Sentence 2: it is linearly growing with size but still can be derived at runtime.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, for a max scaling factor f, the corresponding supply voltage is Vdd = f ×V = max f. Regarding frequency, for a small threshold voltage Vt, the circuit delay becomes 1 / Vdd = 1/ f. Let us now return to the application reliability derived previously.
Sentence 2: the reliability of a single process, scaled with a factor f is: .
Relationship: reasoning
Domain: Hardware
Sentence 1: The key enabler for PEPSE is the lim­ited ability of compilers to extract suf.cient ILP (instruction level parallelism) to fully utilize the parallelism afforded by some archi­tectures such as the Itanium Processor Family (IPF).
Sentence 2: once an application is optimized and scheduled, our compiler-orchestrated prefetching system is allowed to steal any remaining resources to embed speculative address precomputation within program regions that are likely to bene.t from prefetching.
Relationship: reasoning
Domain: Hardware
Sentence 1: At the same time, upgrading test vector memory for 16 channels from 7 M to 14 M would cost only USD 1,500.
Sentence 2: if we double the test vector memory for all 512 chan­  nels, it will cost around (512/1 x15=USD 4 .For this money, the increase in test throughput is 27%.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3 (b), the sub­sequent switching sequence of the proposed method can be adopted with both top-plate input and bottom-plate input ADC structures, and it is more e.cient than that of the con­ventional one.
Sentence 2: for a 3 bit case, the conventional switching procedure consumes 8.75C V 2 while the proposed method DD does only 1.75C V 2 the proposed method requires DD .
Relationship: reasoning
Domain: Hardware
Sentence 1: It is hoped that most functions appear­ing in practical circuits can be realized by a well designed macrocell.
Sentence 2: due to the wide variety of macrocells possible, e.cient general algorithms are not known for macrocell mapping.1 we focus here on a speci.c macrocell architecture used in a commercial FPGA and illustrate how factor cuts may be used to signi.cantly improve the quality of mapping.
Relationship: reasoning
Domain: Hardware
Sentence 1: It is expected that the CNCAP will be used in integratedcircuits near the end of the International TechnologyRoadmap for Semiconductors (ITRS) with operating voltages of 0.5V [2].
Sentence 2: if we let the maximum voltage drop across the CNTs be 100mV, we can approximate the worst case CNT resistance as: RkO+µµ) =O =(6.45 )(11 m 1.6 m +100mV 25µA 14.5k For our short CNTs, the contact resistance, RC, at the top and bottom of each CNT could be very important.
Relationship: reasoning