sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: This result drives more and more people to work on neuromorphic computational paradigms beyond digital logic by replicating the brain s extraordinary computational abilities.
Sentence 2: the contem­porary neuromorphic system s research is mostly con.ned to algorithm .eld, while the hardware implementations are still built upon the traditional CPU/GPU/FPGA systems, which usually consumes a large volume of memory and computing resources [5], [6].
Relationship: contrasting
Domain: Hardware
Sentence 1: As opposed to native simulation or com­piledsimulation[14,26],binarytranslation usesthe exact address for instructions fetch and data accesses.
Sentence 2: the target in­structions arefetchedfrom memory only once,fortranslation,be­foretheir .rstexecution.The simulator always executesthegener­atedbinaryhost code storedintheTranslationCache.So,to accu­ratelyaccountforthese accesses,inthiscon.guration, wemodeled theinstruction cache as apuredirectory, such that a simple array accessindicatesiftheinstruction wouldin realitybeinthe cache.
Relationship: contrasting
Domain: Hardware
Sentence 1: If a digital core has micro-farad off-chip-capacitors on the power system as shown in Figure 1(a), the current surge is somewhat covered by the capacitors.
Sentence 2: with on-die decoupling capacitance of only a few nano-farads, the electrical charge of the on-die capacitor is not sufficient to cover the current surge; therefore, the power supply voltage of the digital core droops severely, as shown in Figure 2.
Relationship: contrasting
Domain: Hardware
Sentence 1: The constraint corresponding to the objective value will become, nn LL ¯ (s.i + s.i -s.i)si = b (.¯i +¯.i -.i)si (18) i=1 i=1 Here, theparameter b corresponds to the coe.cient of variation.
Sentence 2: in this work, the modeling does not consider the randomness in the objective function parameters, and hence this constraint is not utilized at all.
Relationship: contrasting
Domain: Hardware
Sentence 1: With monolithic counters, the .rst counter that over.ows causes re-encryption of the entire memory, so the rate of advance of the fastest-advancing counter controls the re-encryption rate for all blocks in the main memory.
Sentence 2: with our split counters, the re­encryption rate of a block is determined by the rate of ad­vance of the fastest-advancing counter on that page.
Relationship: contrasting
Domain: Hardware
Sentence 1: In the distance range of LSI (H=1 10pm), the coupling capacitance re­mains almost constant, which means that the coupling capacitance arises mainly from a parallel-plate capacitance at the intersection.
Sentence 2: in the distance range of system LCD circuits (H=1000pm), the coupling capacitance does not converge within 5000pm, because the ground plane locates far way, and then 3D effects of coupling capacitance become prominent.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is expected because Adjacent fill fills X-bits for shift-in power reduction only, which may result in excessive shift-out power dissipation.
Sentence 2: the computational time of S-filling is longer than Adjacent fill because we need to calculate the transition probability in test responses, but it is still acceptable: for the largest ISCAS 89 benchmark circuit, s38584, S-filling takes less than 10 minutes to finish with a 2GHz PC with 1G RAM.
Relationship: contrasting
Domain: Hardware
Sentence 1: While there is a signi.cant reduction in the energy consumed, such large drops in performance are generally unacceptable.
Sentence 2: the loss in performance for memory and cache kernels is small, while the energy ef.ciency improves signi.cantly, pushing the kernels into quadrant The primary reason for this behavior is the large periods of inactivity of the compute resources.
Relationship: contrasting
Domain: Hardware
Sentence 1: Itshouldbenotedthatforagivencircuit,theestimation becomesharderasthenumberofregionsincreases.Bench­marksibm03,ibm04andibm14showthetrend.Aglobal routerusesdetourstoavoidroutinginacongestedarea.
Sentence 2: whenregionsarelarge,thedetoursforcongestedspotsina givenregionarestillcountedastheroutingdemandforthis region.ifregionsaresmall,thedetourscontribute routingdemandtoneighboringregions,whichmakesesti­mationdifcult.Ingeneral,estimatesoflargeregionsare moreaccuratethanthoseofsmallregions.Thissuggests thatdesignersuseactualglobalroutingtogetcongestion informationatlatertop-downplacementstages.
Relationship: contrasting
Domain: Hardware
Sentence 1: When we began the work, we intended to use state-of-the-art PD, including fieldwork, scenarios, mock-up, prototypes and Future Laboratories with their 'close-to-real-life' exploration of new designs.
Sentence 2: as it turned out, the different kinds of reports from fieldwork, scenarios, mock-ups and prototypes did not function well as 'reminders' or 'guidelines' in our daily work.
Relationship: contrasting
Domain: Hardware
Sentence 1: We expect that the load by Thread1 should return the value C written by Thread2, because that appears to be the value of the most recent write (in causal order, according to the Power ISA s weak ordered memory model).
Sentence 2: this code snippet does not guarantee when the tlbie instruction will be observed by Thread2 and thus Thread2 could continue to operate with the old translation of VA1 to PA1.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this system, we choose to log the error and continue execut­ing, so that we retain the semantics of the program without any assertions.Wediscuss our error reporting schemeinSection2.7.
Sentence 2: for future work we would like to explore the other options above, as well as a programmatic interface that would allowtheprogrammertotestthe conditionsdirectly andtake action in an application-speci.c manner.
Relationship: contrasting
Domain: Hardware
Sentence 1: One possible approach for main­taining correct memory state, suggested by Paceline, is to re-fetch the cache-lines that are accessed during the last checkpointed inter­val into the L1 cache of the leader core [16].
Sentence 2: since this might happen often for a dead core, we need a low-cost resynchro­nization approach that does not require substantial book keeping.
Relationship: contrasting
Domain: Hardware
Sentence 1: On the one hand, such matrix multiplications make the SATD more expensive than SAD.
Sentence 2: for both inter and intra prediction, the PSNR and bit-rates resulting from SATD are better than those resulting from SAD [12, 2] because, as stated in [27], considering 4x4 blocks, two among four base functions of H4×4 are the same as for the integer DCT used in H.264/AVC.
Relationship: contrasting
Domain: Hardware
Sentence 1: Latch-based ASUs are very common in asynchronous micro­pipelines [12, 4, 3, 13] since they are fast: the latches are nor­mally open, and thus eliminate the control overheads associated with opening them.
Sentence 2: precisely because of this, glitches are allowed to pass through the latch, leading to large energy con­sumption overheads.
Relationship: contrasting
Domain: Hardware
Sentence 1: Therefore, at least one of the four minterms {m3,m4,m5,m6} is contained in function f.However, no matter which minterm belongs to f ,the value of f z * able set Sa and can be respectively mapped to a pair of availableboolean functions {AND, NAND, OR, NOR, XOR, XNOR}.As both of the expansion variable and its complement can be fedas the select bit of the MUX, the order of the boolean functionpairs can be exchanged.
Sentence 2: since each input branch ofthe MUX can only implement four of the six boolean functions({AND, NAND, XOR, XNOR} for negative branch and {OR, ** or fno ¯¯ yx longer stays equal to 3, which contradicts the assumption wehave.
Relationship: contrasting
Domain: Hardware
Sentence 1: Thus, if thermals drive your shrinking chip strategy, it is much better to hold your frequency constant and increase cores by 1.4× with a net area decrease of 1.4× than it is to increase your frequency by 1.4× and shrink your chip by 2×.
Sentence 2: there is a concern that even without shrinking chips, the power-density of hotspots is still increasing exponentially, and could be a concern.
Relationship: contrasting
Domain: Hardware
Sentence 1: Given a 4 M key sorting problem (which is 32 MB data), the con.guration 27ms )-1 overhead is considerable (1 + = 46% of 32 MB·2 s/2 GB the total time.
Sentence 2: given a 400 M key problem (which is 3.2 GB data), the con.guration overhead can be neglected.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is due to the fact that operation rescheduling could impact the e.ciency of the Lx s instruction compres­sion mechanism, leading to an increment of cache misses.
Sentence 2: in some cases (fir2 and matrix) the instruction cache misses are reduced since, due to the particular struc­ture of the code, the rescheduling algorithm can lead to a more regular code in terms of instruction cache access pat­terns.
Relationship: contrasting
Domain: Hardware
Sentence 1: Recall that the Min-CostSAT is a special case of 0-1 ILP with all coef.cients in the 2The use of MIS in computing lower bound is often credited to scherzo.
Sentence 2: the Unate Covering solver included in the fa­mous Espresso minimizer used it as early as in 1984. constraints to be 1.
Relationship: contrasting
Domain: Hardware
Sentence 1: As we discussed theoretically in Section 3.4 and also demonstrate with experiments in the next section, our technique is able to nearly eliminate numerical dispersion errors.
Sentence 2: because the inter­partition interface handling is based on a less accurate (2,6) FDTD scheme, the coupling is not perfect, which leads to erroneous re.ec­tions at the interface.
Relationship: contrasting
Domain: Hardware
Sentence 1: If fis added to the abstract model, two out of ieweL four new states in S)ihave a successor in Stiiim while, frand i.otL nfrhave no successors and are considered dead-end states.
Sentence 2: if nis added to the abstract model, three out of four m new states inS)ihave a successor in Stiii.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is arguably also the reason why the ILP-scheduled code ends up having less spills than GCS-scheduled code after register allocation (0.2% versus 0.8% as a percentage of all instructions).
Sentence 2: in contrast to the ILP scheduler GCS is code­size aware and curbs code motion that entails compensa­tion copies (including partial-ready code motion) if the ex­pected bene.t does not justify the estimated code size in­crease.
Relationship: contrasting
Domain: Hardware
Sentence 1: If a setup timing constraint of Ob is a tight , we must apply FDD clocking to speci.ed input-output register pair for Ob.
Sentence 2: a non-tight setup timing constraint is ensured by one or more steps mar­ r1 r2 r1 t C(b) C(b = a ' ) = a ' C(a ' ) (a) (b) Figure 3: Illustration of C1: Ensuring the hold timing con­straint by SRV-based register assignment.
Relationship: contrasting
Domain: Hardware
Sentence 1: Infact, the linear transformations we used were very similar to those discussed in [43].
Sentence 2: we found that non-unimodular transformations (such as scaling) did not bring additional bene.ts over unimodular ones in our bench­marks.To approximate the ideal tile size (blockingfactor), weex­perimented with different tile sizes and selected the one that per­formed the best.
Relationship: contrasting
Domain: Hardware
Sentence 1: On further analysis of the 21:40 -09:15 period, we .nd that there is substantial overlap between the events detected: there are 15 events in common.
Sentence 2: of the 7 events that were detected by ZCR but not by Volume (RMS), 5 were false positives where no event could be identi.ed when the source audio was listened to.
Relationship: contrasting
Domain: Hardware
Sentence 1: However, for the Cu and CNT technology, the compound metric increases at lower bandwidth density, and decreases at the higher values because of various competing factors: At low values, as bandwidth density increases, power dissipation reduces, but is compensated by an increase in the latency (Figure 5).
Sentence 2: at higher bandwidth density both the power and the latency rise with increase in the bandwidth density, lowering the compound metric (Figure 9).
Relationship: contrasting
Domain: Hardware
Sentence 1: The traditional method for visualizing 3D objects often makes use of orthogonal perspectives and complex controls that occur in CAD and 3D modeling packages such as Blender.
Sentence 2: the Volume Slicing Display makes use of our spatial intuitions; a virtual object floats in real space and the display s cuts through it can be easily repositioned by moving the position of the slicing screen as if it were intersection a real 3D object.
Relationship: contrasting
Domain: Hardware
Sentence 1: For larger designs with many diverse blocks, it is easier to .nd deadspace for TSV-island insertion.
Sentence 2: given a region of deadspace on a particular die, a TSV island also requires another region of dead­space on a neighboring die, with adequate alignment between the two regions.3 Figure 2(b) illustrates a feasible TSV-island place­ment thanks to proper deadspace alignment while Figure 2(c) illus­trates an infeasible TSV-island placement  blocks may need to be shifted to create suf.cient aligned deadspace.
Relationship: contrasting
Domain: Hardware
Sentence 1: In Table 3, using only Vth=0.14V gives an average power reduction of 9.3% versus Design Compiler with Vth=0.23V, as the lower Vth allows gates to be downsized, and possibly we are seeing some purely sizing benefits from our approach now that some timing slack is available to use it.
Sentence 2: using only Vth=0.08V does not on average reduce power, due to the higher leakage.
Relationship: contrasting
Domain: Hardware
Sentence 1: Most applications (i.e., canneal Figure 14b, ferret Figure 14e, and raytrace Figure 14f) show quasi-linear scalability character­istics, with more than 5 × speedup with 6 CPUs.
Sentence 2: other applications (i.e., dedup and facesim Figure 14c and d) present sub-linear scalability characteristics even with a relatively small number of CPUs.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4.1 IDEALS/RMR The concept of IDEALS/RMR is that a node with a high energy reserve acts for the good of the network by participating in routing all packets that come to it, and by generating its own packets from all locally detected events.
Sentence 2: a node with a near-depleted energy reserve acts selfishly, by only generating or forwarding important packets.
Relationship: contrasting
Domain: Hardware
Sentence 1: .N a given message, t « p aprime, e(·) a random error as de.ned above, the value ( ) a := m d div (pt + e(pt))mod t can be seen as a random variable uniformly distributed in .t .
Sentence 2: clearly, a onlyhas a chance to ful.ll the assumption cor­rectlyif 2l(pt) is a multiple of t. the assumption is justi.ed for other cases as well, because the distance to the uniform distribution is negligiblysmall as t « 2l(pt) .
Relationship: contrasting
Domain: Hardware
Sentence 1: The former determines an increase of the power consumption, whereas the latter leads to a non optimum width, from the noise standpoint.
Sentence 2: increasing the source inductance produces a reduction of the LNA transconductance (Gm), which, at resonance, is given by: Gm=1/(2.0· LS ) (2) In this design, a typical value for CGS is 0.5pF; on the other hand, the value of C can be minimized by either mounting the naked die directly on the board or using a BGA package.
Relationship: contrasting
Domain: Hardware
Sentence 1: Instead, the whole system of equations for the entire mesh has to be solved simultaneously, which requires much more computa­tional power.
Sentence 2: this formulation is unconditionnaly stable, which means it is possible to use larger time incre­ments .t and consequently fewer time steps to speedup the simulation, and it is in fact the formulation used by our and most other approaches.
Relationship: contrasting
Domain: Hardware
Sentence 1: Static timing analysis (STA) uses the worst-case corner variations in delay calculation, which means that it calculates the delay assuming that all of the process variations cause each gate to take the largest delay during set-up checking.
Sentence 2: since the random parts of the variations of each gate cannot be worst simultaneously on the same chip statistically, STA is usually optimistic by a large margin, which causes over-estimation in delay calculation, requires excessive delay margin in design phases, and makes the timing closure difficult.
Relationship: contrasting
Domain: Hardware
Sentence 1: On the other hand, LRU-Ordered does well by achieving a similar effect; it at­tempts to avoid going down to deep low-power states, even if an active chip needs to be sent to a (shallow) low-power state.
Sentence 2: lRU-Greedy and LRU-Smooth degrade performance more substantially; they can exhibit degradations as high as 76% and 67%, respectively.
Relationship: contrasting
Domain: Hardware
Sentence 1: On every write access to the partitioned RAM, the same de­coded address is used to access the DataFlitMem location where writeDataFlit is stored-so, we don t need a write decoder for DataFlitMem.
Sentence 2: on a read access to the partitioned RAM, the decoded address is different from the address to retrieve readDataFlit: so we need a separate read decoder for DataFlitMem These observations lead to the following equations representing the power consumption of an optimized FIFO: For data .its, (utilizing the entire width of the original SRAM).
Relationship: contrasting
Domain: Hardware
Sentence 1: Essentially, the replicas share one control .ow and perform the same operation instruction-by-instruction.
Sentence 2: the replicas can diverge in their data values in an ar­bitrary way and use different memory addresses as long as there exista one-to-one mapping between their addresses.We call this diversi.cation model as SIMDA(Single Instruction Multiple Data and Address).
Relationship: contrasting
Domain: Hardware
Sentence 1: 8.2 Multi-core Results When the working set of an application .ts into the cache, the application will not bene.t signi.cantly from compression even though its data might have high redundancy.
Sentence 2: when such an application is running concurrently with another cache-sensitive application in a multi-core system, storing its cache lines in com­pressed format will create additional cache space for storing the data of the cache-sensitive application, potentially leading to sig­ni.cant overall performance improvement.
Relationship: contrasting
Domain: Hardware
Sentence 1: VML Function Itanium Processor Pentium III Processor vdInv 4.3 11.5 vdSqrt 7.3 33.5 vdInvSqrt 6.2 31.8 vdExp 6.2 37.8 vdSin 9.3 49.9 vdTan 12.3 75.9 Table 5: Comparing VML performance (clocks/element) between the Itanium and Pentium III processors Multiple arithmetic units already help ensure good perfor­mance on these functions.
Sentence 2: the extended preci­sion and reduced rounding errors of the fused multiply-add units further enhance performance because full accuracy is much easier to maintain, reducing or eliminating costly steps needed on the other processors to maintain high accuracy over more rounding steps.
Relationship: contrasting
Domain: Hardware
Sentence 1: It proved possible to insert faults in memory space without affecting the running application and then use the trace information gathered as an effective mean to analyze program flow, before and after the actual fault activation.
Sentence 2: as all NEXUS compliant debuggers currently communicate with the host machine through Ethernet or USB connections, and as the fault campaigns must be run on the host machine, this imposes a bottleneck on the time required for an actual memory access.
Relationship: contrasting
Domain: Hardware
Sentence 1: plex overall, but su.ers from two additional sources of over­head necessary for correct execution: (1) result bus con­tention due to out-of-order completion and (2) constrained issue between regions.
Sentence 2: for all benchmarks we see that the additional performance loss over Switch is small: for SPEC INT, SPEC FP, PARSEC, and Parboil, the geomet­ric mean performance loss is 10.0%, 5.2%, 4.4%, and 1.5% over the baseline.
Relationship: contrasting
Domain: Hardware
Sentence 1: FPGA: XILINX VIRTEX-5 The Virtex-5 is typical of a contemporary high perfor­mance FPGA, containing a mixture of .ne-grained Lookup­Tables(LUTs) andFlip-Flops(FFs), andlarger specialised RAM andDSP(multiplier) units.
Sentence 2: itis stillpossi­bletouse manyof thesameRNG algorithmsthathavebeen developed in software.
Relationship: contrasting
Domain: Hardware
Sentence 1: INTRODUCTION High-level synthesis (HLS) software tools such as AutoESL and its successor Xilinx Vivado-HLS [2] are capable of taking an in­put C program and generating effective RTL with performance that can rival manual design [14].
Sentence 2: even for a sub-class of pro­grams with regular loop bounds and array accesses (namely, af.ne programs [18]), additional efforts are still required in complement to Vivado-HLS capabilities to get the best performance in par­ticular to exploit data reuse opportunities in the program, generate off-chip communications, and overlap communication and compu­tations [13, 24, 28].
Relationship: contrasting
Domain: Hardware
Sentence 1: Since Lf , the numerator of DR, is unknown for an instance of parameter variations, we alternatively minimize the denominator Lpf which is the number of edges in the potentially-failing segments.
Sentence 2: since Lpf + Ldnf = L holds, minimizing Lpf is equivalent to maximizing Ldnf which is the number of edges covered by the de.nitely non-failing segments.
Relationship: contrasting
Domain: Hardware
Sentence 1: Traditionally, designers have attempted to alleviate the memory bottleneck by exploring di.erent cache con.gura­tions, with limited use of more special purpose memory mod­ules such as stream bu.ers [9].
Sentence 2: while real-life ap­plications contain a large number of memory references to a diverse set of data structures, a signi.cant percentage of all memory accesses in the application are generated from a few instructions, which often exhibit well-known, predictable ac­cess patterns.
Relationship: contrasting
Domain: Hardware
Sentence 1: It is because the required computation time of a generic 0-1 ILP solver to .nd the min­imum solution tends to increase as the 0-1 ILP problem size increases.
Sentence 2: the problem size can be signi.cantly reduced by considering only the operations that require 1 CSA block in .nding the implementations of the constants, i.e., the operations whose one of the inputs is the .lter in­put or its shifted versions.
Relationship: contrasting
Domain: Hardware
Sentence 1: Traditionally, performance/power variations are handled by a combination of speed/power binning and design margining [2]: speed/power binning tests all fabricated chips, those of which with a slower speed or excessive power are either discarded or sold at a reduced price; design margining uses worst-case process cor­ners to guarantee the design requirement.
Sentence 2: these solutions are becoming insuf.cient as the variability increases along with 1This research was supported in part by NSF grants of CAREER 0643902, CNS 0720659 and CCF 0702617. technology scaling, and may not be a viable solution when the variability encountered in the new process technologies becomes very signi.cant.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since prior work showed that phase-based cache tuning significantly impacts energy consumption and execution time, and DTM techniques can significantly impact temperature, energy consumption, and execution time, we combine phase-based cache tuning and DFS for fine-grained and efficient temperature, energy, and execution time optimization.
Sentence 2: since optimizing one design objective may adversely impact the other design objectives, combining these techniques presents a multi-objective optimization problem.
Relationship: contrasting