sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: network, the proposed ONoC architecture utilizes path In [9], we have proposed Circular-first Routing (CR) as a direction to prevent interference scenarios.
Sentence 2: clockwise direction within a super node is taken for routing data streams to the destination nodes located at the same wavelength group, while counter-clockwise direction is chosen for routing data packets targeted to the other wavelength group.
Relationship: entailment
Domain: Hardware
Sentence 1: We can expand the state vector inTaylor Series with respect to the parameters,but not with respect to the frequency, leading to 8 where Hii = Lxii, making the parametric dependence clearly explicit.
Sentence 2: the parametric transfer function can be written as the contribution of the nominal transfer function plus the contribution of the non-parametric trans­fer function sensitivities w.r.t.
Relationship: entailment
Domain: Hardware
Sentence 1: RESULTS This sections reports and discusses a set of quantitative analysis of the proposed FSM-based power-gating control.
Sentence 2: the following results will be shown: Section 3.2 will show an in-depth analysis of the performance reliability trade-off for a particular reference application, con­sidering different FSM con.gurations and the attainable IPC versus NBTI-induced delay degradation;  Section 3.3 demonstrates that the bene.ts of a particular FSM con.guration have a strong application dependence, consid­ering a broad range of test cases from different benchmark suites;  Section 3.4 will present the impact that the wake-up latency has on the number of clock cycles the FSM stays in lower states;  Section 3.5 reports preliminary results on the digital design of the proposed FSM approach, considering standard-cell .ow at 45 nm technology.
Relationship: entailment
Domain: Hardware
Sentence 1: Now consider a delay failure on {p,q} caused by an extra physical delay on p. In the presence of a HT failure on path {d,g,k,m} (from FF0 to FF3), signal o is 0 after the first positive edge on CLK which, in turn, causes q to undergo a 1.0 transition, whether or not the same transition on {p,q} reaches q in time or not.
Sentence 2: if the delay on path {o,q} (from FF3 to FF4) is less than T-d, FF4 captures the correct value in the next clock cycle in spite of a delay failure existing on p. HT failure of {d,g,k,m} masks the setup-time failure on {p,q}.
Relationship: entailment
Domain: Hardware
Sentence 1: Our solver is able to utilize circuit topological information and signal correla­tions to enforce a decision ordering that is more ef.cient for solv­ing circuit-based SAT problem instances.
Sentence 2: for unsat­is.able circuit examples, our solver is able to achieve from 2x up to more than 75x speedup over a state-of-the-art SAT solver.
Relationship: entailment
Domain: Hardware
Sentence 1: The overall benchmarking approach for configurable computing systems consists of developing a benchmarking methodology, benchmark specifications, and public dissemination of the benchmarks.
Sentence 2: the approach for developing the benchmark suite includes performing the following tasks:  Requirements Summary review a broad range of applications and metrics to identify benchmarks that are relevant to configurable computing;  Methodology Development develop a rigorous methodology which can be applied across all benchmarks, including procedures, metrics, measurement, and reporting of information;  Benchmark Development -develop unbiased benchmark specifications that focus on what is to be implemented, not how;  Benchmark Evaluation -implement each benchmark on a target configurable computing platform to validate the specification;  Public Dissemination -address the public availability of the benchmarks.
Relationship: entailment
Domain: Hardware
Sentence 1: Co-Design of Body Doping and Workfunction The off current target at different body-doping can also be achieved by engineering the gate work-function (an option for metal gate process) which modifies the flat band voltage (see (2)).
Sentence 2: if lower body-doping is accompanied close to mid­ gap workfunction (both for NFET &#38; PFET), the nominal Vt and off current can be maintained.
Relationship: entailment
Domain: Hardware
Sentence 1: Analyzing data collected between September 2008 and May 2009, we .nd that although preferen­tial attachment captures the evolution of the network, its in.uence varies signi.cantly based on how long ago a user joined the ser­vice.
Sentence 2: preferential attachment does not appear to ap­ply to new entrants of the FriendFeed service.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION As an early adoption of 3D integration, 3D-stacked DRAM is a promising technology for overcoming the barriers in DRAM scal­ing, thereby offering an opportunity to break the memory wall with improved DRAM cell density (capacity) and wire routing re­sources (connectivity), as well as reduced wire length (latency and power) [1, 2, 3, 4, 5, 6].
Sentence 2: wide IO DRAM [1] has been standardized by JEDEC as a high bandwidth and low-power 3D DRAM for embedded SoC system.
Relationship: entailment
Domain: Hardware
Sentence 1: F k ,...,F k 0 n-1 are easily calculated by setting i=0 and simulating the LFSR symbolically [equations (1) are satisfied for every value of i].
Sentence 2: the LFSR is initialized with symbolic state (c0(t0), ..., cn-1(t0))=(a0, ..., an-1) and is clocked k times.
Relationship: entailment
Domain: Hardware
Sentence 1: Yield improvement has been modeled by using a random vari­able FR factor with a uniform distribution in (1, 10) to divide the original cell failure rate FR.
Sentence 2: for each cell, the new variant s failure rate will be decreased randomly from a value in (300ppb, 500ppb) to a value in (30ppb, 500ppb).
Relationship: entailment
Domain: Hardware
Sentence 1: UTD di.raction coe.cients can be computed for eachdi.racted path, or canbe interpolated froma smallsetofprecomputed values forfasterprocessing.
Sentence 2: the second common di.raction-calculation method us­es theBiot-Tolstoy-Medwin(BTM) solution,a time-domain formulation for di.ractionfrom a rigid orpressure-release wedge[7,8,19].theBTM-basedexpression de­rivedbySvenssonet al.in[9]hasbeenusedby anumberof authors (e.g., see [3,20,21]) becauseitisformulated asa line integral along the di.ractingedgeandthusiswellsuited forusewith .niteedges,and because theBTMsolutiongives an exact solutionfor di.ractionfromarigid(orpressure re­lease)wedge.Furtherdetailsof theBTMformulationin[9] areprovidedin Section3 asitis the basisfor ourapproxima­tiontechnique.
Relationship: entailment
Domain: Hardware
Sentence 1: The UCP [10] is, given a matrix M of m rows and n columns, for which Mi, j is either 0 or 1, is the problem of  .nding a minimum cardinality column subset C, such that for all C', .j.C'Mi, j = 1,.i .
Sentence 2: {1,···,n}.|C|=|C'| (1) the columns in the set C cover M in the sense that every row of M contains a 1-entry in at least one of the columns of C, and there is no smaller set C' which also covers M. The matrix M is called constraint matrix of UCP.
Relationship: entailment
Domain: Hardware
Sentence 1: An important issue of the design .ow is estimating the IPC and the block power dissipations required to generate the temperature distribution of the microarchitecture layout.
Sentence 2: the num­ber of pipelined latencies required by each bus of the microarchi­tecture is proportional to its length, and therefore for every .oor­plan, there is a corresponding bus-latency con.guration, and con­sequently an IPC and a power (and temperature) distribution.
Relationship: entailment
Domain: Hardware
Sentence 1: We also make a key observation that the performance overhead of Ascend can be largely elim­inated by taking advantage of the streaming computation model.
Sentence 2: if the working set of the currently-processed record .ts in the cache, Stream-Ascend can signi.cantly re­duce both the ORAM capacity requirement and the number of ORAM accesses.
Relationship: entailment
Domain: Hardware
Sentence 1: In such a case, we have demonstrated that the energy efficiency is optimized when VDD is lowered as much as possible to just meet the throughput requirements.
Sentence 2: due to the quadratic nature of dynamic energy and the fixed throughput requirement, using a higher VDD to quickly finish the computation and then turning off the supply by means of sleep transistors to reduce leakage consumes more energy overall than lowering VDD to the point where there is just enough time to finish the computation.
Relationship: entailment
Domain: Hardware
Sentence 1: Our speci.c contributions are as follows:  Foremost, our work is the .rst to recognize opportunities forinter-core TLB cooperation and propose mechanisms in re­sponse.
Sentence 2: by pushing TLB mapping information from theinitial miss core (leader) to the other cores, Leader-Followerprefetching can eliminate up to 57% of the TLB misses acrossthe surveyed workloads.
Relationship: entailment
Domain: Hardware
Sentence 1: There are several approaches, e.g., Snugglebug [3], Java PathFinder [20], and DART [9], that use precise symbolic or concolic analysis to search for a concrete execution path that ends at a given program point with a state that satis.es a given condition.
Sentence 2: these approaches under­ 2 Although it is not fully clear from their paper, we assume that they include arrayload and arraylength instructions within their get.eld category, and arraystore instructions within their put.eld category.
Relationship: entailment
Domain: Hardware
Sentence 1: Addi­tionally, if a witness is found, MaxBMC asks for the quality q of this witness.
Sentence 2: the witness with the highest quality for each transition step is identi.ed, and therefore, MaxBMC determines the Pareto-optimal qualities for the sequence lengths until a bound k. As in BMC, one can encode the structure of MaxBMC as CNF, including soft clauses: M axBM Ck = I0 .T0,1 .. .
Relationship: entailment
Domain: Hardware
Sentence 1: We focus our study on conflicts generated by information sharing, leading us to develop a methodology for assessing internal risk based on a representation of the information flow and of the value items exchanged, and on the identification of configurations that can lead to, or could be exploited by opportunistic behaviors'.
Sentence 2: we focus on partners behavior related to misrepresentation of reality, meaning that each actor can lie, providing fake inputs to the computation of the SC's working point.
Relationship: entailment
Domain: Hardware
Sentence 1: Then in W the 3rd dissection, the sliding step is W = 64 , and the error bound 43 1 from Theorem 1 is )2 1.556%.
Sentence 2: after 64 - ( 1 128 two dissections, we only need consider windows whose density is very close to the actual maximum density (the density difference is less than 1.556%).
Relationship: entailment
Domain: Hardware
Sentence 1: Never­theless, in-depth investigation reveals that many design and security issues have not been fully understood based on ex­ Hsien-Hsin S. Lee School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA 30332 leehs@gatech.edu isting literature.
Sentence 2: the role of integrity protection and its relationship with privacy protection in the context of secure processor design was not su.ciently addressed.
Relationship: entailment
Domain: Hardware
Sentence 1: However, due to .ner time granularity of enforce­ment of cache partitioning (smaller enforcement interval), we may have cache repartitioning happening multiple times before processor partitioning of the next iteration (as illus­trated in Figure 3).
Sentence 2: we may have di.erent cache partitions enforced for the same processor partition (during the same iteration), depending on theratiobetween enforce­ment interval for processor partitioning and the enforcement interval for cache partitioning.
Relationship: entailment
Domain: Hardware
Sentence 1: The 2001 System Drivers Chapter observed that rapid MPU frequency increases up to that time had been en­abled by reduction in the number of fanout-of-four (FO4) delays per clock period.
Sentence 2: microarchitecture (aggressive pipelin­ing, with fewer stages of logic per pipeline stage) had been used to increase frequency at a faster rate than the intrinsic growth of device switching speed.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION The internet-sector server marketisgrowingatafast pace,by 40 to 65% per year according to various market trend studies (in-cludingbyIDC).Thisfast increaseisduetovariousnovel internet services that are being offered, along with ubiquitous internet ac­cess possibilities through various devices including mobile devices such as smartphones and netbooks.
Sentence 2: smartphones en­able their users to be permanently in touch with email, the internet, social networking sites such asFacebook andTwitter, e-commerce, etc.
Relationship: entailment
Domain: Hardware
Sentence 1: Given C E VG1 = C E VG2, we use the mathematical induction to prove the functional equivalence of G1 and G2.
Sentence 2: we would like to show that G1(.n) = G2(.n) for i i i = 0 ~ n. 1) Base case: For i = 0: Since .n 0 contains only the all-0 vector, the weighted summation of G1 and G2 under .n 0 is zero.
Relationship: entailment
Domain: Hardware
Sentence 1: 1.0 Introduction In 1997, the Semiconductor Industry Association (SIA) identified a major design crisis approaching in its National Technology Road Map for Semiconductors [Sia97].
Sentence 2: they mentioned the drastic increase of clock frequency and the exponential increase of circuit complexity, and concluded that a novel asynchronous approach could be required to solve some of the industry s future problems.
Relationship: entailment
Domain: Hardware
Sentence 1: Figure 2 presents estimates of total interconnect area as 512 length-4 channel wires are gradually replaced with 8-to-1 bit-serial wires.2 Although area is needed for the bit-serial wiring and SER/DES circuits, area is saved as traditional wiring is removed.
Sentence 2: note the input connection block area shrinks signi.­cantly because semi-random switch patterns can be replaced with more orderly word-wide inputs [10].
Relationship: entailment
Domain: Hardware
Sentence 1: Therefore, we can con­clude that when the tagis atthe Xth way of a cache setin thebigger cache where X> (A/2),depending on the value of X, tail tohead searching can reduce the number of ways searchedinside a set ofthe smaller cache from one to (A/2).
Sentence 2: the tail to head searching can reduce searching up to 50% compared to the head to tail search.
Relationship: entailment
Domain: Hardware
Sentence 1: Some hardening techniques for matrix multiplication are presented and compared in [11].
Sentence 2: as cache corruption produces multiple errors on the same row or column of the output matrix, errors can be corrected in constant time by adding checksums in the input matrices extending the Algorithm Based Fault Tolerance (ABFT) TABLE III FFT CROSS SECTION AND FIT AT NYC  TABLE IV REAL AND IMAGINARY PART PERCENTAGE, CROSS SECTION, AND FIT Percentage Cross section FIT FFT Real 94.96% 3.50·10-6cm2 4.90·105 FFT Imaginary 96.17% 3.55·10-6cm2 4.97·105 TABLE V FFT SINGLE AND MULTIPLE ERRORS FFT Real FFT Imaginary Single Multiple Single Multiple Percentage 1.61% 98.39% 4.00% 96.00% FIT 7.89·103 4.82·105 19.80·103 4.67·105 technique proposed in [19], based on Freivalds results [20].
Relationship: entailment
Domain: Hardware
Sentence 1: Unexcitability Analysis of SEUs Affecting the Routing Structure of SRAM-based FPGAs Cinzia Bernardeschi Luca Cassano Andrea Domenici Department of Information Engineering University of Pisa, Italy cinzia.bernardeschi@ing.unipi.it Department of Information Engineering University of Pisa, Italy luca.cassano@ing.unipi.it Department of Information Engineering University of Pisa, Italy andrea.domenici@ing.unipi.it Luca Sterpone Dipartimento di Automatica ed Informatica Politecnico di Torino, Italy luca.sterpone@polito.it ABSTRACT Testing SEUs in the con.guration memory of SRAM-based FPGAs is very costly due to their large con.guration mem­ory, therefore it is necessary to optimize the generation of test patterns.
Sentence 2: in order to reduce the e.ort required of automatic test pattern generators, it is useful to identify early the unexcitable faults, i.e., those faults that cannot be excited by any combination of input signals.
Relationship: entailment
Domain: Hardware
Sentence 1: These four properties can be separately maintained in di.erent manners in a system.
Sentence 2: for example, transactional memo­ries (TMs) [22] maintain A, C, and I, separated from D, while a recent study on failure-atomic msync [36] focuses on A and D. a persistent memory system needs to en­sure atomicity, consistency, and durability.
Relationship: entailment
Domain: Hardware
Sentence 1: µ ...... y d assuming perfect contacts, given by the Landauer-Buttiker formula, is 4e2/h 2p (5) = 155 µS [11].
Sentence 2: the resistance of a carbon h nanotube of length L < .CNT with ideal coupling to the two metal LK = contacts at its ends is given by [34]: 2e2v F h (1) R = R = 6.45K.
Relationship: entailment
Domain: Hardware
Sentence 1: 3 illustrates the congestion detection circuit where a 3-bit shift register is adopted to store the threshold signal whenever a new flit enters or leaves the buffer (flit events: flit_tx or flit_rx).
Sentence 2: in each flit event, if the number of occupied cells of the buffer is larger (smaller) than a threshold value, the threshold signal is assigned to one (zero) and stored in the shift register.
Relationship: entailment
Domain: Hardware
Sentence 1: The increasing (or decreasing) rising time causes a shrinking (or widening) output pulse width, resulting in a failure at the end of the 10mm link.
Sentence 2: the output pulse widths obtained from process corner simulations of the single delay cell design are Wout,0 >Wout,1 >Wout,2 > ... > Wout,10 (1) (bit 1 transmission f ailure) or Wout,0 <Wout,1 <Wout,2 < ... < Wout,10.
Relationship: entailment
Domain: Hardware
Sentence 1: Switching off power to a cache line has important implications for the rest of the cache circuitry.
Sentence 2: the first access to a powered-off cache line should: (i) result in a miss (since data and tag might be corrupted without power) (ii) reset the counter and restore power to the cache line and (iii) delay an appropriate amount of time until the cache-line circuits stabilize after power is restored.
Relationship: entailment
Domain: Hardware
Sentence 1: An algorithm is terminating if, for any fair history H of the algorithm where no process crashes, each (partially or fully completed) call to a procedure in H in­curs a .nite number of steps.
Sentence 2: (in H each process that participates either terminates after completing a .nite number of procedure calls, or else it makes in.nitely many procedure calls.)
Relationship: entailment
Domain: Hardware
Sentence 1: In order to generate a test for a fault f, i.e.
Sentence 2: stuck-at-0 (s-a­0) or stuck-at-1 (s-a-1), the circuit CNF FC is augmented f by additional constraints Ffor fault detection and fault F propagation with respect to the speci.c fault f. the following CNF formulation results: f f FTest = FC · FF f The CNF Ftypically includes the complete output cone of F the fault site, the faulty gate itself, and D-chain constraints topropagate the fault to an observation point [15].
Relationship: entailment
Domain: Hardware
Sentence 1: Although originally developed for consumer vehicles, the CAN bus is now gaining widespread acceptance for use in many other land, sea, and air-based vehicle platforms.
Sentence 2: the CANaerospace upper-layer protocol, standardized by NASA, is of particular interest as it defines message types and encodings for many datum related to air-vehicle parameters and control as well as providing inherent support for N-redundancy.
Relationship: entailment
Domain: Hardware
Sentence 1: Co-executingjobs may con.ict with each other on various shared resources which may adversely affectoverallperformance.Or,re­versely, systemperformance maygreatlybene.tfrom co-executing jobs that put compatible demands on shared resources.
Sentence 2: the performance interactions and symbiosis between co­executingjobs on multithreadedprocessors canbepositive or neg­ative[28].
Relationship: entailment
Domain: Hardware
Sentence 1: Our results, collected using the Simics sim­ulation toolset [17], demonstrate that not just the different ap­plications require different percentages of idle processors to be used for computation duplication, but also even within the same application, the different loop nests work best (from the perspective of the energy-delay-fallibility product) with the different percentages of idle processors being used for dupli­cation.
Sentence 2: the amount of duplication should be tuned at a loop nest granularity.
Relationship: entailment
Domain: Hardware
Sentence 1: Hence, the total capacitance at the dynamic node for p-type domino is not as small as could be expected from a first-order analysis.
Sentence 2: the drive current degradation due to the lower mobility of the node voltages in the circuit become close to Vdd or ground, including the virtual ground (vgnd) or virtual supply (vsup), in the case of PMOS or NMOS gating, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: On the contrary, in [6, 7], we showed that di.erent kinds of EFSMs can be generated starting form the same HDL description, and each of them is composed of transitions with a more or less uniformly dis­tributed probability of being activated.
Sentence 2: in [6] we proposed a procedure that generate a new EFSM, start­ing from a reference EFSM (REFSM) that is exactly equiv­alent to the HDL description of design under veri.cation (DUV).
Relationship: entailment
Domain: Hardware
Sentence 1: In other words, The two .nal constraints (C8 and C9)relateall thevariables to each other.
Sentence 2: the constraint C8 determines the relationship between the overall used layers, yrs,and the layers used by each speci.c application, ukrs.The re­lationship is straightforward from the de.nition of the two variables.
Relationship: entailment
Domain: Hardware
Sentence 1: The configuration register may also be configured to shut down ways, resulting in a 4 Kbyte direct­mapped or 2-way set associative cache or a 2 Kbyte direct­mapped cache.
Sentence 2: 2 Kbyte 2-or 4-way set associative and 4 Kbyte 4-way set associative caches are not possible using the configurable cache hardware.
Relationship: entailment
Domain: Hardware
Sentence 1: Different evaluation functions in .tting with the implementation backend and the correspond­ing implementation technology can be incorporated into our so­lution framework to evaluate the implementation cost of the set partitions and RST topologies generated.
Sentence 2: we exper­imentedwithanimplementationcostmodel basedonthe power consumption parameters of a 70nm process technology where leakage power is a major source of energy consumption.
Relationship: entailment
Domain: Hardware
Sentence 1: To statistically encode such a sparse pattern as our prior knowledge, we exploit the fact that if the early-stage coefficient aE,m has a large (or small) magnitude, it is likely that the late-stage coefficient aL,m also has a large (or small) magnitude.
Sentence 2: we model each late-stage coefficient as a zero-mean Gaussian distribution: 2 aL m 1 2 4 6 8 10 12 pdf (a )= L,m ...... · exp - , .2 a2 Number of Samples per Configuration · p·.·aE m 2 · (15) , .
Relationship: entailment
Domain: Hardware
Sentence 1: Collapsing We define a collapsing condition as that when all states in to(s) are NOP and none of them directly appears in a reachability check.
Sentence 2: under such a condition, we collapse all the NOP states and merge them with s. .t.to(s) (with t being NOP), we remove the transitions s.f(x,i) t and t.TRUE q and add a new transition s.f(x,i) q.
Relationship: entailment