sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: The comparison and analysis for the luminescence spectrum of the four devices mentioned above are discussed followed, and the detailed luminescence mechanism of white PLED based on MEH-PPV and PVK is explained base on the results of experiment.
Sentence 2: red and blue luminance material is always dissolved into solution firstly and then formed emitting layer on the ITO glass by the method of spin coating or ink-jet printing, so the cognition of luminescence mechanism is very difficult.
Relationship: neutral
Domain: Hardware
Sentence 1: 3.3 Transaction based Error Characteri­zation The error simulations are executed for multiple bench­marks and the criticality of each signal is assessed based on the effects of a single-bit error on any signal over different types of transactions, namely, read and writes in our case.
Sentence 2: with the increasingly stringent power and area budget all such schemes are under reconsideration.
Relationship: neutral
Domain: Hardware
Sentence 1: Recon.guration is 0 8 0 5 only applied to the memory interfaces, and internal bus widths are 0 0 0 .xed.
Sentence 2: figure 8(c) il­  (a) No mal z d IPC  ( ) No mal z d  Po   Table 2: Characteristics of selected GPGPU benchmarks (the instruction count (IC) and the memory intensity (MI)).
Relationship: neutral
Domain: Hardware
Sentence 1: The importance of subbands are used to allocate quantization bits for MDCT coe.cients of each subband so that the important subbands should be coded .rst in the bitstream to gain the gradually  Figure 1: Block diagram of G.729.1 encoder.
Sentence 2: in [5] frequency regions are divided to more segments that each segment contains about only 2-3 scale-factor subbands.
Relationship: neutral
Domain: Hardware
Sentence 1: Master Core out-of-order superscalar at 2 GHz, 4-wide, 128-entry ROB, 96-entry LD/ST queue, Worker Cores up to 64, in-order at 2 GHz L1 Caches 32KB, 4-way, 64-byte block, 1 port, 1-cycle, LRU, split I/D L2 Caches private 256KB, 8-way, 64-byte block, 2-port, 8-cycles, NRU, 16 MSHRs, uni.ed, coherent, inclusive Coherence MESI directory per memory controller, 4 virtual networks, 10-cycles, non-blocking L2 Prefetcher PC-based stride, 64 streams, degree of 4 NoC 2D Mesh at 2 GHz, 2 cores per node, 16-byte control packets, 80-byte data packets, 16-byte links, 1-cycle link, 5-stage routers, 4 virtual networks, 4 VCs per virtual network DRAM 4 dual-channel memory controllers, 16GB DDR3 SDRAM, PC3-15400, 8 banks, FR-FCFS scheduling policy  EBP 32 commands, 8 outstanding requests ECM 8 epochs using 3 bits per L2 tag Table 1: Detailed architectural parameters for the simulated system.
Sentence 2: based on this value, the associated cache-lines are requested with the proper coherence permissions: Shared or Exclusive.
Relationship: neutral
Domain: Hardware
Sentence 1: The STB spreads accesses across banks, so each bank sees a statistically similar request stream, but sampled proportionally to bank partition size: 2/3 of the accesses are sent to the .rst partition, and 1/3 to the second.
Sentence 2: on a miss on the private cache levels, a per-core share­bank translation buffer (STB) .nds the bank the line maps to, as well as its bank partition.
Relationship: neutral
Domain: Hardware
Sentence 1: Results of the Incorporated 3D Physical Planning Flow For the experiments on 3D physical planning, we use an Alpha­like detailed microprocessor with the IVM verilog model [16], as well as several MCNC benchmarks.
Sentence 2: the temperature of each block can then be estimated as: ... ... T1 R11 R12 ... R1n P1 T2 R21 R22 ... R2n P2 ... ... .
Relationship: neutral
Domain: Hardware
Sentence 1: 1.5 xv  dv qv  1.5 1 0.5 0 Voltage qv xv  dv Each of these effects can individually cause circuit failures.
Sentence 2: as shown by the INV2 input (xv) and output (dv) voltages in Figure 3(a), even in the worst case when both aggressors switch simultaneously in the same direction, the output glitch of INV2 is not strong enough to cause a logic error in DFFV.
Relationship: neutral
Domain: Hardware
Sentence 1: (2) Some edges are almost always among the most criti­cal edges in the timing analysis graph.
Sentence 2: criticality History Guided FPGA Placement Algorithm for Timing Optimization Hao Li and Yue Zhuo Department of Computer Science and Engineering University of North Texas Denton, Texas, USA ABSTRACT We present an e.cient timing-driven placement algorithm for FPGAs.
Relationship: neutral
Domain: Hardware
Sentence 1: The transition times between si and sj are determined by the trajectory time .t computed by a transient (c) (c) step from pi to pj : (c) (c) T(R(si, sj)) = .t(pi ,pj ) (35) Each transition from a transient step has an atomic transition proposition of 0, marking it as dynamic transition created by a state space trajectory step: T(R(si, sj)) > 0 .
Sentence 2: the trajectory-directed partitioning algorithm is summarized in Algorithm 1.
Relationship: neutral
Domain: Hardware
Sentence 1: Once the PCM device receives an U NL INK command to unlink addrp for consecutive s bytes, the indirect bits and the link information of the corresponding virtual pages vpm (vpm + len) are reset to unlink the virtual pages vps (vps + len) linked to virtual pages vpm (vpm + len), so that data accesses to virtual pages vpm (vpm+len) in the main-memory space won t be redirected to the virtual pages vps (vps + len) in the storage space anymore.
Sentence 2: rethinking Database Algorithms for Phase Change Memory.
Relationship: neutral
Domain: Hardware
Sentence 1: VALIDATION IN A COMMERCIAL FPGA IMPLEMENTATION FLOW The Quartus University interface program (QUIP) kit is designed to enable uni­versity or other researchers to plug new CAD tools and ideas into the complete Altera s Quartus II CAD .ow from register transfer level (and even above) de­scriptions of circuits to programming .les for real FPGAs.
Sentence 2: the optimal placement solution in Figure 6(c) on this optimal clustering yields a longest path delay of 2.0, which cannot be improved by postplacement duplication.
Relationship: neutral
Domain: Hardware
Sentence 1: Noting that Ic =CV.,where C is the matrix of internode capacitances, we get V.=-C-1Im(V ) (8) For simplicity, we assume that all capacitors are to ground and have constant values.
Sentence 2: furthermore, fabrica­tion processes for SoC and AMS chips are typically developed to optimize performance and density of the digital circuits, as the dig­ital circuitry occupies the majority of the die area.
Relationship: neutral
Domain: Hardware
Sentence 1: Consider the case of a single potential HTLSIB where the initial chain length is n, and the chain length behind the potential HTLSIB is m. Assume the attacker checks the chain length by shifting in a distinctive d-bit pattern and observing when it exits the chain.
Sentence 2: c. Providing No Feedback: Hiding an Increase or Decrease in Chain Length So far, we have assumed an attacker will use the chain length as an indicator of whether a new area of the chain has been opened (or closed).
Relationship: neutral
Domain: Hardware
Sentence 1: The user with zero utility envies the other user s allocation.
Sentence 2: 0.6 0.4 24GB/s 12MB 0.6 0.4 x y =(4) 1 1 22 0.2 0.8 24GB/s 12MB 0.2 0.8 x y =(5) 2 2 22 In our example with two agents, Equations (4) (5) must be satis.ed.
Relationship: neutral
Domain: Hardware
Sentence 1: Dynamic quality control techniques for multimedia applica­tionshavebeen exploredin[19,20], which vary the amount of computation performed in each frame based on time and energy consumed, as well as thequality of the encodedframe.
Sentence 2: in the case of the checkerboard dataset, DES achieves lower (around 15%) energy bene.ts over the static conservative technique.
Relationship: neutral
Domain: Hardware
Sentence 1: Mid­dle/Right: multi-Vth synthesis .ow 3.1 Performance-optimized synthesis .ow Our .rst objective is to characterize critical path and area of the different adder implementations when synthesized for maximum performance and as a function of data parallelism.
Sentence 2: for a single-threshold technology library and power optimizations enabled in the synthesis tool, the DW selection strategy for power­optimal adder instances does not need to take the DIR into account.
Relationship: neutral
Domain: Hardware
Sentence 1: 709 714, May 2003. proposed as a strong solution to reduce the complexity and/or the energy dissipation of on-chip interconnect fabrics.
Sentence 2: tX schematics for the four bus schemes: P, S, ES, and SE P S SE  b1 b2  f Figure 7 compares the overall average activity factor for all schemes versus the sum of the input bitstream activity factors for m=4.
Relationship: neutral
Domain: Hardware
Sentence 1: Since ROB-DDs require a Boolean representation of the circuit and the size of a ROBDD grows, sometimes exponentially, with the number of Boolean variables.
Sentence 2: lEC uses .-automata as the uni.ed models for both the system design and the prop­erty, and checks whether the language of the system au- Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: neutral
Domain: Hardware
Sentence 1: 00: Original software without countermeasures  1x: Countermeasures protecting the data layer  2x: Combinations of data protection methods  3x: Countermeasures protecting the control .ow layer  4x: Combinations of control .ow protection methods  5x: Combinations of data and control .ow protection Following countermeasures were implemented and simulated:  Test 10: Instruction Duplication:  A calculation is carried out multiple times (here: twice) and the result is assigned to two variables.
Sentence 2: this software part was spared from fault simulations throughout this work, since in real security microcontrollers, the AES will be computed by speci.c hardware circuits protected by hardware counter­measures [19].
Relationship: neutral
Domain: Hardware
Sentence 1: 3.1 The basic ENC algorithm (ENC0) Whenever a thread needs to move from a non-native core to a destination core, ENC0 .rst sends the thread to its native core which has a dedicated resource for the thread.
Sentence 2: [9] Jason E. Miller, Harshad Kasture, George Kurian, Charles Gruenwald, Nathan Beckmann, Christopher Celio, Jonathan Eastep, and Anant Agarwal.
Relationship: neutral
Domain: Hardware
Sentence 1: CASE STUDY ON USING PCRAMSIM In this section, we conduct two case studies to demonstrate how to use the PCRAMsim tool to estimate and optimize the PCRAM memory design and the PCRAM cache design, respectively.
Sentence 2: in this paper we develop a PCRAM model called PCRAMsim to bridge the gap between the abundant research activity at the lower level and the lack of a high-level PCRAM model.
Relationship: neutral
Domain: Hardware
Sentence 1: Furthermore, as pointed out in [3], most DSP functions mainly concern certain quantitative performance criteria (e.g., signal to noise ratio (SNR)) and operations with such transient logic errors may not necessarily make the signal processing performance unacceptable.
Sentence 2: furthermore, we assume the desired SNR degradation overscaling to reduce the power consumption by about 13% when d has a uniform distribution between 0dB and 5dB, i.e., dmax=5dB.
Relationship: neutral
Domain: Hardware
Sentence 1: In addition, very difficult hardware bugs may be detected only when running the real software with real applications.
Sentence 2: 2) There is a number of modifications that are required for the FPGA netlist: customizing the testbench to Aptix platform, introducing clock generation and reset logic, building the clock distribution on the FPGA platform, changing the non-mappable structures and gated clocks, etc.
Relationship: neutral
Domain: Hardware
Sentence 1: The main hypothesis motivating previous work in wirelength estimation is that wirelength correlates well with post-route delay.
Sentence 2: b. Kahng and S. Reda, Intrinsic shortest path length: A new, accurate a priori wirelength estimator, in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, San Jose, CA, United States, 2005, pp.
Relationship: neutral
Domain: Hardware
Sentence 1: As the target wire wt = (u, v) is removed, its area flow af(wt) will be re-distributed to the fanout of u and it is desirable to remove a wire with smaller area flow.
Sentence 2: (3) Performing logic perturbation in routing stage is clearly more effective for delay improvements due to the more accurate timing information that can only be precisely known after routing.
Relationship: neutral
Domain: Hardware
Sentence 1: To find the Average Latency under different traffic pattern, test­benches connected to each router through local injection channels as a local Processing Element (PE) generates the number of packets somewhere between 10,000 and 100,000 and fills the destination of each packet according to the traffic pattern.
Sentence 2: in fact, R[3,3] and R[1,3] particularly in the depicted scenario due to failure in R[2,3] are supposed to received more flits compared to the non-faulty condition.
Relationship: neutral
Domain: Hardware
Sentence 1: [33] C. Weaver and T. M. Austin.
Sentence 2: memory and Register Protection In an MMM, the .rst key challenge is to prevent high-performance applications from corruptingthe state of reliable applications.In afault­free system this protection is achieved through a combi­nation of now-standard software mechanisms and policies (e.g., page-based memory protection) and hardware sup­port(e.g.,TLBpermission checks).Furtherprotection can be achieved using additional software mechanisms such as Overshadow[9].these existingmechanisms make the assumptionthathardwareitselfis reliable.
Relationship: neutral
Domain: Hardware
Sentence 1: 3.4 Deriving Module Interface Annotations The same procedure that was used to derive the scheduling relationship among rules (DERIVEREL) can be used to determine the scheduling relationship (interface annotation) of interface methods: DERIVEREL(g1, g2) returns the interface annotation for methods g1 and g2.
Sentence 2: hence, each action method of a module has two control signals: enable (en) and ready (rdy), while a read method has only a ready control signal (see Figure 2).
Relationship: neutral
Domain: Hardware
Sentence 1: The Read-out path would be turned on when Figure 4. the Write 0 operation completes and the floating bit-line would be pulled down.
Sentence 2: the row-based VGND control and the column-based data-aware Write Word-Line form a cross-point Write structure, thus eliminating Write Half-Select Disturb to facilitate bit-interleaving architecture.
Relationship: neutral
Domain: Hardware
Sentence 1: Since we only have one variable, even with a complicated physics-based model for a(vchip)and b(vchip), we can still e.ciently solve this problem in a numerical way.
Sentence 2: permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: neutral
Domain: Hardware
Sentence 1: Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full cita­tion on the .rst page.
Sentence 2: although the evaluation sequences were not used for training the model, they still come from the same database as the training data, and were hence recorded with the same actor, in the same settings, etc.
Relationship: neutral
Domain: Hardware
Sentence 1: ACKNOWLEDGEMENTS This work was funded in part by the NSF grant CNS 0958510 and Intel and supported by grants FA 99500910389 (AFOSR), FA 865011C7190 (DARPA), FA 87501020253 (DARPA), CCF/TC 1054844 (NSF) and a gift from Synopsys Inc.
Sentence 2: the design is also heavily pipelined, with roughly one .ip .op between each pair of com­plex logic gates for critical portions of the design.
Relationship: neutral
Domain: Hardware
Sentence 1: Receiver: TmoteInvent [29] was used as the listener node, due to its low-cost and low-power (100 times more power e.cient than the DSP on the transmitter) features that are expected from a WSN platform.
Sentence 2: the capability of these systems have been upgraded by using DSP/smart phones that typi­cally consume higher power and resources.
Relationship: neutral
Domain: Hardware
Sentence 1: Ina.ashcrowding ar­chitecture there is no padding: all the chip s tiles are small cores with a modicum of local memory.
Sentence 2: we lump all padding tiles into a single category, sim­ply assuming that a core tile serviced by i padding tiles boosts its performance by some enhancement factor f (i), and ignoring whether such a boost originates from fewer cache misses, fewer pipeline stalls, dedicated arithmetic cir­cuitry etc.
Relationship: neutral
Domain: Hardware
Sentence 1: This indicates that our method for guaranteeing per­formance is indeed effective, even when combined with algorithms such as OD+ and OS+ that are not designed to be performance­aware.
Sentence 2: for available slack values S in the interval (A · tM-1,8], we determine the value of Thk(S)to be the same as that at S = A· tM-1.
Relationship: neutral
Domain: Hardware
Sentence 1: While tolerating an unexpected timing error en­tails a large performance overhead in pipelined architectures [3], we observe that scheduling an instruction with a predictable timing error becomes logically equivalent to a variable latency operation.
Sentence 2: in libquantum, CDS is particularly effective as it can elimi­nate 86% of the timing violation penalty, compared to 64% in ABS.
Relationship: neutral
Domain: Hardware
Sentence 1: Nick Yu : The fabless business model will definitely not only survive, but will thrive, as the economic and technical factors that dictate the need to amortize the cost of technology development and fab ownership across multiple entities are all accentuated at each successive technology node.
Sentence 2: thus development methodologies on both, process and design end, need to accommodate changes to allow for global optimization of the end product, rather than just optimizing the process or the design.
Relationship: neutral
Domain: Hardware
Sentence 1: If such a scheme were to be implemented, then this would let DTM techniques (especially those with policies relying on frequent task migrations, e.g.
Sentence 2: eXPERIMENTS 6.1 Experimental Methodology The RTL simulation environment (our entire MPSoC was im­plemented in RTL using generated code from ASIPmeister [17] and hand modi.ed code) was ModelSim (HDL simulator) [18].
Relationship: neutral
Domain: Hardware
Sentence 1: Also, without considering the electrical .eld distribution, the noise is over-estimated because aggressors are seeing the whole TSV MOS capacitance.
Sentence 2: to alleviate the TSV-to-TSV coupling noise, we proposed a novel model and a method to protect the victim TSVs by grounded TABLE X NOISE REDUCTION RESULTS ON TWO DESIGN STYLES Placement style Irregular Regular Total noise on TSV net (V) 101.1 96.5 Noise reduction 27.3% 27.1% TSV-induced delay (ns) 0.81 0.93 TSV-induced power (µW) 12.75 12.86 TABLE XI FULL-CHIP NOISE REDUCTION WITH GUARD RING VS TSV SHIELDING Guard ring TSV shielding in [1] Protected TSV # 298 118 Initial TSV size (µm2) Protected TSV size (µm2) 49 68.89 to 121 49 361 Initial footprint 380µm× 380µm 402µm× 402µm Final footprint 380µm× 380µm 421µm× 421µm Noise reduction 27.3% 42.04% Area overhead (µm2) 11053 (7.65%) 42598 (26.4%) active region.
Relationship: neutral
Domain: Hardware
Sentence 1: Although other possible trade-off points could be considered, we empirically found that these four points yield good optimization results and provide a systematic approach for constructing all ver­sions of a cell.
Sentence 2: when the circuit is in standby mode, a larger amount of leakage reduction is desirable since this will translate directly to longer battery life (e.g., standby time for a cell phone).
Relationship: neutral
Domain: Hardware
Sentence 1: This expression for a complete loop is completely analogous to (2) for a single line.
Sentence 2: the inductance of this circuit is L1+2 =L11 +L22 +2L12: (2) If the partial inductance is a linear function of length, the inductance of the circuit is the sum of the inductance of its elements, i.e., Llinear =L11 +L22: (3) The difference between the nonlinear dependence [see (2)] and the linear dependence [see (3)] is the presence of the cross coupling term 2L12.
Relationship: neutral
Domain: Hardware
Sentence 1: It s quite clear from this .gure and the earlier energy comparisons that a larger cache is clearly bene.cial for the larger benchmarks (most of SPEC CPU2006 and Mediabench) and especially those with loop dominated codes provided that the loop iterations are suf.ciently large.
Sentence 2: we must carefully select the blocks to be written into the NVM array.
Relationship: neutral
Domain: Hardware
Sentence 1: As such we need to compute the moments of input admittance (impedance) of the transmission line to model the interconnect.
Sentence 2: g 1 + y C 2 R =1 +m1y +m2 y +····+mkyk +··· (9) 1 + y L where k-th moment is G 1 + y k C d R 1 + y L k dy mk = (10)k!
Relationship: neutral
Domain: Hardware
Sentence 1: The performance of our instruction schedul­ing algorithm combined with this faster hardware con.gu­ration is presented in Figure 4 as FAST.
Sentence 2: the performance improvement for simple scheduling (all operations executed on the recon.gurable hardware) and 20x faster recon.gurations is 27 % while our scheduling algorithm contributes to a performance improve­ment between 43 % and 94 % compared to SW.
Relationship: neutral
Domain: Hardware
Sentence 1: For instance, stronger error­correcting codes (ECCs) such as double-error correction / triple-error detection (DEC-TED) ECCs can be used, and bit interleaving, which ensures that physically adjacent bits are protected by different ECCs, can be used in conjunction with ECCs [24].
Sentence 2: for a hardware structure H considering M fault modes with GM fault groups in the structure, over a period of N cycles, the soft error rate of the structure is given by: M GM N By summing SERH over all structures, we can calculate the overall soft error rate of a chip from all single-and multi-bit transient faults.
Relationship: neutral
Domain: Hardware
Sentence 1: The number of spare banks depends on the bank failure rate.
Sentence 2: a row-sparing architecture would be not effective at tolerating 65K spare rows for a failed bank, because the sparing associated table SPEC-FP SPEC-INT PARSEC BIOBENCH GMEAN would become impractically large to build and search on of sparing: either a row or a bank.
Relationship: neutral
Domain: Hardware
Sentence 1: The in.uence of the in­dividual factors is expressed as main effects, while interaction ef­fects describe the in.uence of interactions.
Sentence 2: it is well known that the simulation of these benchmarks is very compute-intensive: for in­stance, the reported simulation time for the benchmark 177.mesa, when the reference input set used is about 3000 hours on a SPARC 333MHz machine.
Relationship: neutral
Domain: Hardware
Sentence 1: eg_r___8_ co_g_o_g_4_88___2de_kg_ co_g_o_g_8_88___98e_kg_ co_g_o_g_2d_88___d4e_kg_ 4ne 8ne2dne98ne4ne 8ne 2dne98ne4ne8ne2dne 98ne 284._88__o_ 0.884 0.888 0.833 0.833 0.803 0.808 0.804 0.809 0.029 0.00d 0.009 0.009 243._88kgi 0.904 0.898 0.289 0.083 0.249 0.220 0.0d9 0.044 0.039 0.098 0.093 0.089 28d._rr 0.848 0.243 0.2d3 0.299 0.292 0.298 0.204 0.208 0.032 0.098 0.092 0.048 294._g8c 0.289 0.004 0.234 0.238 0.049 0.009 0.009 0.004 0.8dd 0.009 0.009 0.009 044._8 0.809 0.29d 0.082 0.098 0.29d 0.049 0.09d 0.094 0.294 0.220 0.0d8 0.098 290. co0.404 0.9d3 0.884 0.228 0.29d 0.288 0.228 0.049 0.0d4 0.0d9 0.094 0.088             Table 2.
Sentence 2: printouts of this file are unaffected by this problem.
Relationship: neutral