sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: While a potential disadvantage of the aforementioned clocks is that every device may need to be contacted individually, potential advantages include additional energy reductions [18], and more fine-grained control of an NML ensemble (useful architecturally per [7]).
Sentence 2: any circuit will still be inherently pipelined [18], bit conflicts can still occur, and our insights are relevant to other clocking approaches too.
Relationship: contrasting
Domain: Hardware
Sentence 1: graph for LM, an edge ei,j between two tiles ti and tj denotes that the distance between the two tiles should be equal to or larger than a constant d(ei,j ).
Sentence 2: this de.nition is not suitable for DPT because DPT depends on the conditional spacing, i.e., the spacing between two patterns should be at least sd if these two patterns are on the same mask.
Relationship: contrasting
Domain: Hardware
Sentence 1: [9] discusses a network topology very similar to the one imple­mented in this paper; the authors conclude from their limited exper­iments that it is a feasible topology, which has trouble competing with mesh networks on smaller devices but scales better.
Sentence 2: the evaluation here is under the conditions of an MPSoC and not an embedded device, and the conclusions may also be different when application-speci.c information is taken into account.
Relationship: contrasting
Domain: Hardware
Sentence 1: Among the maximumperiodgenerators,wethenselectedfromthose withthebest equidistribution,whichisa measureoftheoret­icalquality[10],Thebestgeneratorfoundisactually maxi­mally equidistributed, which means it has the best possible quality for this type of generator, and provides equivalent quality togenerators such astheXorShift.
Sentence 2: alllin­ear generators have a known statistical .aw, due to their .xed linear complexity [11].
Relationship: contrasting
Domain: Hardware
Sentence 1: Several recent thermal-aware DVFS techniques are found effective in single-processor scenarios, where the cool tasks interleave the hot 2 tasks to keep the temperature .uctuating below its threshold [11], [12].
Sentence 2: in the multiprocessor scenarios, the notion of cool task calls for rede.nition in the presence of shortened thermal conducting paths under increasing chip density, as well as the parasitic thermal­runaway effect.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this case, the ISR will jump to the ExIntr_Hdlr() function which recovers task2 from the lock-wait table of lock#6 and marks task2 as ready in the ready table before the scheduler re-schedules it.
Sentence 2: if the received interrupt is for a short CS lock release, then the ISR will store back the initial value of Link Register of the processor so that the processor jumps to the last instruction just before sleeping, i.e., the short CS lock primitive execution.
Relationship: contrasting
Domain: Hardware
Sentence 1: Today, industry is advocating a suite of new and emerging tech­nologies energy-harvesting transducers [13], thin-.lm batteries [1], micropower integrated circuits [9], and nanopower microcontrollers [12] coupled with star network topologies, to address the pressing challenges of energy harvesting operation.
Sentence 2: we show how existing technologies  solar cells, simple capacitors, switching regulators, .eld-effect transistors, and low­power microcontrollers and radios can be combined in new ways, and coupled with simple protocols and good engineering, to achieve hassle-free, energy harvesting operation, without sacri.cing the ben­e.ts of interoperating with battery-powered meshes.
Relationship: contrasting
Domain: Hardware
Sentence 1: n-Modular Redundancy (nMR): Spatial or temporal redun­dant execution has long been a cornerstone for detecting soft errors, with hardware DMR (dual-modular redundancy) and TMR (triple­modular redundancy) being the solutions of choice for mission­critical systems.
Sentence 2: the cost of such techniques has relegated them to the high-budget server and mainframe domains (e.g., HP NonStop series [3] and IBM zSeries [2] machines).
Relationship: contrasting
Domain: Hardware
Sentence 1: Hence, the most viable method for estimating power consumption of 3D-DRAMs is to use system-level power models that use JEDEC-speci.ed current and voltage values from mem­ory datasheets, which are based on real hardware measurements.
Sentence 2: it should be kept in mind that the accuracy of the DRAM power model using these datasheet measures, de.nes the accuracy of the DRAM power and energy estimates.
Relationship: contrasting
Domain: Hardware
Sentence 1: For MPGdecoder, the performance degradation shown in Figure 6 is caused by a large number of read-only replica­tions because they should be read from the other on-chip cache whenever a read miss occurs if they are turned o. while the read-write replications do not cause the signi.cant performance degradation.
Sentence 2: by controlling the num­ber of TOS blocks, RALM reduces the energy consumption by 62.4% and 20.0% on average over BASELINE and DE-CAY, respectively.
Relationship: contrasting
Domain: Hardware
Sentence 1: Thisis because under fewer node numbers, the system requiresmore sound sources to make accurate estimation of inter­device distances.
Sentence 2: we do not observe signi.cant difference in the ultimate accuracy among the three cases.This is because as the number of sound sources increases,eventually the system will always have high probability ofaccurately estimating inter-devicedistances for everydevicepair.
Relationship: contrasting
Domain: Hardware
Sentence 1: In [8], it is observed that the circuit can be expanded to higher numbers of inputs by expanding the decode tree.
Sentence 2: it is important to note that expanding the tree be­yond a certain height reduces noise margins and makes the LUT circuit vulnerable to process variations, since it be­comes increasingly di.cult to detect the di.erence between high and low MTJ states due to the additional resistance introduced by the transistors in series.
Relationship: contrasting
Domain: Hardware
Sentence 1: Employing an EDC/ECC to larger data blocks reduces the total number of redundant bits concatenated to the memory; hence, per-line EDC/ECC imposes significantly lower area overhead in comparison to per-word EDC/ECC; lower area overhead leads to lower static power overhead and even lower dynamic power overhead.
Sentence 2: per-line EDC/ECC require a whole line access for every read or write operation to check or update the EDC/ECC of the line.
Relationship: contrasting
Domain: Hardware
Sentence 1: All the aforementioned researches achieve some notable results.
Sentence 2: the chip-package design has become increas­ingly challenging, more considerations must be accounted for: These approaches assume that bumps are arranged in .xed array locations with unique spacing, they then design the area-array ICs by planning the I/O placement with cost functions and constraints or connecting bumps and I/Os with RDL routing.
Relationship: contrasting
Domain: Hardware
Sentence 1: simulation #I simulation #2 It is obvious that the proposed .ow does not work for general circuits, as in general the solution of DAE equations depends on the initial condition, and the time segmentation essentially neglects this inter-segment dependence and thus may lead to incorrect re­sults.
Sentence 2: in practice, a lot of circuits of interest satis.es the so-called short-memory condition, i.e.
Relationship: contrasting
Domain: Hardware
Sentence 1: Ad­mittedly, HPWL is not the most widely used metric in FP-GAs.
Sentence 2: this is a good starting point for two rea­sons: First, most of the available academic ASIC placers are HPWL-driven, thus reporting on HPWL provides a fair and credible result; Second, it could be argued that routability or timing-driven placement can be derived from HPWL-driven placement by properly weighting the nets.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4, if we reduce power by switching G4 to a lower power higher delay con.guration, such as low-Vt to high-Vt with the slack mar­gin .Smax, no optimization may be further performed on G6 without violating the timing target.
Sentence 2: g3 and G5 can be optimized with the same slack margin for better Theoretically, the sum of log-normal random variables does not have a closed-form distribution.
Relationship: contrasting
Domain: Hardware
Sentence 1: Whereas, traditional gm-C filters, which can operate at higher bandwidths, suffer from limited linearity.
Sentence 2: current-mode active elements, like the second generation current conveyor (CCII) and the current feedback amplifier (CFA) exhibits attractive characteristics such as wide frequency operating range, low power, high linearity, high slew rate and simple circuitry [5].
Relationship: contrasting
Domain: Hardware
Sentence 1: Thetimespentinthebroadcastofthelocalsamplevectors andthecountersbecomessignifcantforsmalldatasets(i.e.
Sentence 2: 1Mkeys).thattimeisconstantindependentlyof thedatasetsizebecauseourparameterssands 0 arefxed and,qislimitedto512.Thattimecanbereducedvaryings, s 0andqwhenwehavetosortsmalldatasets.for themeasuresofthispaper,thosevalueshavebeenfxedas wesaid.TheCountingSplitCSEisconstantforallthedata setssortedanditisaroundthe20%ofthetotalexecution time.
Relationship: contrasting
Domain: Hardware
Sentence 1: On average, the proposed technique shows around 7% estimation error for 1K vectors compared to the HSPICE mea­surement.
Sentence 2: comparing the simulation speed, the proposed technique completed the estimation within a few seconds while the HSPICE took 3.4 hours on UltraSparc80® 450MHz dual proces­sors with a 4MB L2 cache.
Relationship: contrasting
Domain: Hardware
Sentence 1: One of the most popular models for congestion estimation in digital circuit designs is the probabilistic congestion model [7, 14], which e.ciently estimates routing congestion of a 2-pin net based on L-and Z-shaped pattern routes and has a good e.ciency and accuracy trade-o..
Sentence 2: we do not use the probabilistic congestion model because the size of the routing tiles in an analog circuit design is typically much smaller than that in a digital circuit design.
Relationship: contrasting
Domain: Hardware
Sentence 1: (instead of the same data cache as in [9]) at the time of the read (note that if we consider the replicas in the L2 cache, the proposed approach can achieve 100% loads with replica.
Sentence 2: in our experiments, we focus on investigating how many replicas can be found in the small replication cache at the time of read hits in L1 data cache).
Relationship: contrasting
Domain: Hardware
Sentence 1: Reducing Latencies of Pipelined Cache Accesses Through Set Prediction Aneesh Aggarwal Electrical and Computer Engineering Binghamton University Binghamton, NY 13902 aneesh@binghamton.edu Abstract With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high per­formance processors.
Sentence 2: with reducing feature sizes and in­creasing clock speeds, cache access latencies are increasing.
Relationship: contrasting
Domain: Hardware
Sentence 1: Energy-Efficient Cache Design Using Variable-Strength Error-Correcting Codes Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu Intel Corporation 2111 NE 25th Ave M/S JF2-04, Hillsboro, OR 97124, USA {alaa.r.alameldeen, ilya.wagner, zeshan.a.chishti, wei.a.wu, chris.wilkerson, shih-lien.l.lu}@intel.com ABSTRACT Voltage scaling is one of the most effective mechanisms to improve microprocessors energy efficiency.
Sentence 2: processors cannot operate reliably below a minimum voltage, Vccmin, since hardware structures may fail.
Relationship: contrasting
Domain: Hardware
Sentence 1: The deductive engine is a SATsolver.
Sentence 2: clearly, in this case, the structurehypothesis is re­strictive in that the procedure does not seek to .nd arbitrary forms ofinvariants.theveri.cation procedureis still sound,be­causeifa suitable inductiveinvariantisnot found, onemayfailto prove the property,butabuggy system will notbe deemed correct.
Relationship: contrasting
Domain: Hardware
Sentence 1: As the DRAM-cache frequency increases, the cost of the 24-cycle MissMap increases relative to the DRAM­cache latency, and therefore HMP provides a small but increasing relative performance bene.t as well.
Sentence 2: increasing the DRAM cache frequency reduces the relative additional bandwidth provided by the off-chip DRAM, thereby potentially decreasing the effectiveness of SBD.
Relationship: contrasting
Domain: Hardware
Sentence 1: In order to realize the negative o.set at p, a driver pin is found higher in the clock tree, so that if p is connected to it, the di.erence in Arrival Time (AT) will e.ectively realize the o.set.
Sentence 2: these driver pins, called from now on acceptors, should reside at the same scope of hyper-net as p to guarantee the same functionality as mentioned earlier.
Relationship: contrasting
Domain: Hardware
Sentence 1: Design and CAD Challenges Ruchir Puri IBM T J Watson Research Center Yorktown Heights, NY 10598 ruchir@us.ibm.com ABSTRACT With the impact of cost crunch in every industry including semi-conductor industry across the world, complexities of 22nm CMOS may appear to be way out in the distance future.
Sentence 2: more than the technology complexity, the new era of financial restraint will impose unprecedented productivity requirements on future design flows.
Relationship: contrasting
Domain: Hardware
Sentence 1: But this consistent miss rate improvment is realized at the cost of more energy consumption compared to RSC and RHC, which will be discussed later.
Sentence 2: since RSC dynamically powers off the cache ways -although this is done based on the cache pressure -the reduced cache capacity consistently impairs the cache performance (77% more cache misses), especially when the dynamic recon.guration scheme can not accurately capture the cache behavior.
Relationship: contrasting
Domain: Hardware
Sentence 1: The most simple EVX with all features disabled and a small VMSHR of 8 entries (limited-EVX) decou­ples memory and computation instructions and transfers multiple operands to the reservation stations in a single cycle.
Sentence 2: it pro­vides limited speedup over the scalar baseline for most of the kernels or even performance degradation due to VCU initialization, with the exception of ICCG, Ipred, Matrix and PiCell.
Relationship: contrasting
Domain: Hardware
Sentence 1: However, the continuous Vth degrada­ Joint modeling of interdependent degradation effects on logic networks and sleep transistors: Due to the increasing Vth of sleep transistors during active mode, the voltage level (denoted by VVdd as depicted in Figure 1) at which the logic network operates gradually decreases, therefore imposing additive performance loss.
Sentence 2: the decrease in VVdd can be offset, to a certain extent, by the smaller current required for normal opera­tion of the logic network due to its own degradation.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, at Pf =10-1 , the detection probability for t-sensing is still 92%; while in this case AD-sensing and KS­sensing perform better than t-sensing.
Sentence 2: as indicated in section 1, the exact noise distribution is often unknown in real situations and AD and KS based sensing work only if the exact noise distribution is known a-priori.
Relationship: contrasting
Domain: Hardware
Sentence 1: A few novel resistive NVM/CMOS circuits have been de­signed in the last few years, including non-volatile SRAM (n­vSRAM) [13], non-volatile Flip-Flop (nvFF) [14], non-volatile Full Adder (nvFA) [15] [17], non-volatile XOR/AND/OR gates [17] [19], etc.
Sentence 2: the reported non-volatile full adders in [15], [16] and the AND/OR gates in [18], [19] only use resistive memory as one of their operands.
Relationship: contrasting
Domain: Hardware
Sentence 1: 3 Motivation for Two-Step Partitioning Prior work on the identification of failing scan cells is based on random-selection partitioning, which is especially effective if the failing scan cells are uniformly distributed across a scan chain.
Sentence 2: in practice, faults in a circuit are likely to lead to clustered failing scan cells, thereby invalidating the uniform distribution assumption implicit in random-selection partitioning.
Relationship: contrasting
Domain: Hardware
Sentence 1: ORNoCC shares similar characteristics tto Snake when considering conservative values.
Sentence 2: bbecause ORNoC does not suffer from any waveguide crossinngs, a significant improvement is obtained when considering aaggressive values Lwc Co 43.26 25.875 14.225 28.975 15.8 Arch2: Snake and ORNoC arre crossbars.
Relationship: contrasting
Domain: Hardware
Sentence 1: The presented scheme is different from the prior code duplication related studies such as [1, 6, 8], as we focus on an embedded chip multiprocessor and try to minimize a different metric, which captures performance, energy, and re­liability.
Sentence 2: there is still a chance that a transient error can strike during execution of an unduplicated computation, which cannot be detected by our approach.
Relationship: contrasting
Domain: Hardware
Sentence 1: This technique resorts to probabilistic techniques to derive BER estimates analytically (without explicit circuit simulations) by starting with appropriate probabilistic models of all random noise and interference sources of the link, and by calculating intermediate probability distributions due to the various link components to the receiver output.
Sentence 2: the exact calculation of intermediate probabilitydistributions is not possible for arbitrary and realistic probabilistic noise models, and therefore inevitably these approaches entail many assumptions and approximations both in the noise models and the calculation of intermediate distributions.
Relationship: contrasting
Domain: Hardware
Sentence 1: Group IBM Research Los Angeles, CA Yorktown Heights, NY East Fishkill, NY Yorktown Heights, NY jinjun@ucla.edu {zolotov,natesan,chandu}@us.ibm.com ABSTRACT In the deterministic approach, a circuit is optimized for a single combination of process parameters.
Sentence 2: as Chips manufactured in 90 nm technology have shown large a result of manufacturing we receive chips corresponding parametric variations, and a worsening trend is predicted.
Relationship: contrasting
Domain: Hardware
Sentence 1: The high energy consumption of existing out­of-order implementations is the result of a long period of dedicated pursuit of performance at the expense of energy consumption: speculations are applied very aggressively and the circuitry for orchestrating out-of-order execution is not designed with energy e.ciency as a priority.
Sentence 2: the out-of-order model is not inherently more power-hungry.
Relationship: contrasting
Domain: Hardware
Sentence 1: When the ADAMS of the Out signal of sensing ¯0 ¯0 or ¯1 ¯1 is normally slower than state is ¯0 ¯1 ( 1 ), read disturbance could happen on both P-that of sensing ¯1 ¯0 , we may be able to differentiate these two cell and N-cell.
Sentence 2: the probability that read disturbance cases by carefully choosing the cutoff point.
Relationship: contrasting
Domain: Hardware
Sentence 1: dynamic voltage and frequency scaling (DVFS) is widely used to reduce dynamic power [4], while clock/power gating techniques [5] are commonly used to reduce leakage power in cores.
Sentence 2: implementing these techniques at a per-core granularity requires separate VDD and ground lines, as well as a prohibitively large number of VLCs (voltage level converters) and MCFIFO (multiple clock first­in-first-out) queue based frequency level converters [6][7], especially as the number of cores on a die increase.
Relationship: contrasting
Domain: Hardware
Sentence 1: A buffer can become live many times during the schedule, and is not necessarily live for a con­tiguous amount of time; this could happen, for example, if the buffer is in a nested loop with three or more actors.
Sentence 2: the pattern with which the buffer becomes live is periodic in the sense that it depends on the iteration counts of all loops that contain the actors constituting the edge of the buffer.
Relationship: contrasting
Domain: Hardware
Sentence 1: Finally, Figure 7shows the synthesized clock frequencyat dif­ferentdesignpoints.Hereweseea signi.canteffectfromthe more complex logic forgarbage collection:even thoughit consumes rel­atively little area, clock frequencyforgarbage collectionis notice­ably slower (15-39%) than Malloc across all design points.
Sentence 2: the difference between STW andRTGC is small with RTGC often faster.
Relationship: contrasting
Domain: Hardware
Sentence 1: On one hand, the speculation-control-sensitive workloads already have much fewer in-flight instructions than the baseline, and the reduced fetching capability does not significantly affect the overall performance.
Sentence 2: bwaves does not need a full-capability front-end to begin with because it has a mostly idle back-end due to the memory intensity as well as the infrequent misprediction-caused pipeline flushes.
Relationship: contrasting
Domain: Hardware
Sentence 1: Note that our frustum tracing technique is could be seen to be re­lated to adaptive super-sampling techniques in computer graphics such as [48, 17, 20].
Sentence 2: recent work in interactive ray tracing (for vi­sual rendering) has shown, that adaptive sampling  despite its natural advantages does not perform near as fast as simpler approaches that are based on ray packets and frustum techniques.
Relationship: contrasting
Domain: Hardware
Sentence 1: The clock reference supply volt­age is 1.8V in order to interface to the digital core.
Sentence 2: thesupply can be scaled easily to 900mV because start-up is based oncurrent, not voltage, and the current source for the reference hasbeen designed to be power supply independent over a broad range.A summary of these performance parameters is given in Table III.
Relationship: contrasting
Domain: Hardware
Sentence 1: Let us consider a single fault group of a fault mode with M bits.
Sentence 2: if all bits in this group are ACE, the SB-AVF and MB-AVF of this fault group in a single cycle are: M × 1 SB-AV F = = 100% 1 × M 1 MB-AV FM = = 100% = 1 × SB-AV F 1 if only one bit is ACE, then the single-and multi-bit AVFs of this group in a single cycle are: 1 × 1 100 SB-AV F = =% 1 × M M 1 MB-AV FM = = 100% = M × SB-AV F 1 Therefore, from .rst principles, we can see that the MB-AVF can vary between 1x and Mx SB-AVF, where M is the number of bits in the fault mode.
Relationship: contrasting
Domain: Hardware
Sentence 1: [21] model traf.c .ow as a 3-tuple consisting of a Hurst pa­rameter and parameters for hop distance and spatial injection distri­bution.
Sentence 2: these statistical models are not a formal/conservative representation of the underlying traf.c, and designing according to such models can be misleading [12].Formal Methods: The abstraction of a latency-insensitive sys­tem [5] has been explored as a veri.cation aid.
Relationship: contrasting
Domain: Hardware
Sentence 1: Approx­imately a 6.5x improvement in latency and a 51x improve­ment in throughput are possible for the largest problem con­sidered.
Sentence 2: notice that even for large problems there is a large portion of unutilized resources, which could be used to extract more parallelism in the interior-point method and achieve even greater speed-ups.
Relationship: contrasting
Domain: Hardware
Sentence 1: In addition, vertex 20 collects a precedent neighboring ESD connected com­ponent, ECC1, through visiting vertex 15 (lines 20 22).
Sentence 2: vertex 20 also visits the np-vertex, vertex 11, trying to expand ECC2 and to collect more p-vertices and more prece­dent neighboring ESD connected components.
Relationship: contrasting
Domain: Hardware
Sentence 1: Finally, proposals such as decay-based replace­ment [26] or PIPP [27] modify the replacement policy to provide some control over allocations.
Sentence 2: theylack strict control and guarantees over partition sizes and interference, preclude the use of a speci.c replacement policy within each partition, and are often co-designed to work with a speci.c allocation policy.
Relationship: contrasting