sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Modular exponentiation can be im­plemented using a square-and-multiply technique [27,28] which is presented in Algorithm 1, where n is the wordlength, e(i) denotes the bit i of E, Pi is the value of P at iteration i, and N is the mod­ulus value.
Sentence 2: modular exponentiation is reduced to a series of modular multiplication and square operations.
Relationship: entailment
Domain: Hardware
Sentence 1: First, the Gaussian distribution pdf(µL) is peaked at its mean value µL = µE, implying that the early-stage mean µE and the late-stage mean µL are likely to be similar.
Sentence 2: since the Gaussian distribution pdf(µL) exponentially decays with (µL -µE)2, it is unlikely to observe a late-stage mean µL that is completely different from the early-stage mean µE.
Relationship: entailment
Domain: Hardware
Sentence 1: Theorem 1 (moment matching property of algorithm 1): For the approximate parametric system ~~ ~~ ~ {G ,C ,G ,m,G ,C ,m,C ,B,L} , where G = -G U V T , 0 0 1 n 1 nn i 0 G G ppp ii ~ C = -G U V T , 1 = i = n , the reduced order model using the i 0 CC p i i projection matrix computed in algorithm 1 preserves the transfer function moments with respect to all parameters up to order k. As in Theorem 1, the projection V computed in Algorithm 1 corresponds to a nearby system that is based on the low­rank approximation of generalized sensitivity matrices.
Sentence 2: we compute an approximate projection matrix for the original parametric system and employ it for parametric model order reduction.
Relationship: entailment
Domain: Hardware
Sentence 1: While the former is used to show the case where a great number of physical pages have been previously written and thus garbage collection and erase operations are far more likely to be triggered by new requests, the latter is used to show the opposite situation.
Sentence 2: the former will allow us to examine the performance and endurance impact of garbage collection and erase operations that cause channels and chips to be in the busy state.
Relationship: entailment
Domain: Hardware
Sentence 1: A social networking workload consists of multiple services that run on multiple servers in a dis­tributedwayina data center, e.g.,Web servers, database servers, memcached servers,etc.The fundamentaldif.cultythataWeb2.0 workloadimposesisthatthe performanceofthe ensemblecanonly be measured by modeling and evaluating the ensemble, because of the complex interplay between the various servers and services.
Sentence 2: performance as perceived by the end-user, i.e., the response times observed by the end user, is a result of the perfor­mance of the individual servers as well as the overall interaction among the servers.
Relationship: entailment
Domain: Hardware
Sentence 1: .tpd,i, i=1 where tpd,i is the delay shift of the ith PMOS device in the gate.
Sentence 2: the delay shift of the NAND gate is determined by the delay shift of the PMOS device in the CP or PCP, while the delay shift of the NOR gate is the sum of delay shifts of all the PMOS devices in the gate.
Relationship: entailment
Domain: Hardware
Sentence 1: While state-based full predication (SFP) can remove wasteful power consumption onissuing/decoding instructions from conventional full predication,generating code for SFP is challenging for general CGRAs,especially when there are multiple conditionals to be handleddue to exploiting data level parallelism.
Sentence 2: in this paper, we presenta novel compiler framework addressing central issues such ashow to express the parallelism between multiple conditionals, andhow to allocate resources to them to maximize the parallelism.by separating the handling of control .ow and data .ow, our framework can be integrated with conventionalmapping algorithms for mapping data .ow.
Relationship: entailment
Domain: Hardware
Sentence 1: Although building block layout style may now be less practical for chip design because modern IC technologies use many metal layers for connections, and wires often can be routed over predesigned blocks, many of the techniques and ideas originally developed for building blocks find applications with other layout styles or technologies.
Sentence 2: the dynamic routing modification techniques have been further developed in the context of multichip modules (MCMs) [27][28][29].
Relationship: entailment
Domain: Hardware
Sentence 1: Therefore, .P = nP · rsource, where nP is the num­ber of source nodes associated with the proxy P. Since the processingtimeattheproxy(inthemillisecondlevelfor a Mica node,whichismainlyduetodecryption/reencryption) is signi.cantly smaller than Tproxy, we make the simplifying assumption that this process time can be ignored.
Sentence 2: the delay caused in the delivery of a real message is essentially the sum of the delays caused by the bu.er­ing at the source node where the event occurred and at the proxy that the messagepasses through onits way to theBS.
Relationship: entailment
Domain: Hardware
Sentence 1: EXPERIMENTAL RESULTS Example 1: We assume that {RTSV1 = 10O, CTSV1 = 400fF} and {RTSV2 = 1kO, CTSV2 = 800fF}.
Sentence 2: tSV1 is normal while TSV2 has a resistive open fault that makes the resistance rise by 100 times.
Relationship: entailment
Domain: Hardware
Sentence 1: [6], [7], [10] proposed a canonical delay model to address the node delay correlations through sharing global variations.
Sentence 2: they model each of the node delay as a summa­tion of three terms: ni = µi + aiRi +ßi,j Gj (1) j where ni(i =1, 2, ...) are random variables corresponding to the the ith node delay in the timing graph; µi is the expected value of ni; Ri, (named node variation), is a zero-mean, unity variance Gaussian random variable representing the localized statistical uncertainties of ni; Gj represents the jth global variation, and is also modeled as a zero-mean, unity variance Gaussian random variable; {Ri} and {Gj } are additionally assumed to be mutually independent; the weight parameters a i (named node sensitivity) and ßi,j (named global sensitivities) are deterministic constants, explicitly expressing the amount of dependence of ni on each of the corresponding independent random variables.
Relationship: entailment
Domain: Hardware
Sentence 1: For a page ta­ble cache to provide coverage it must simultaneously hold an L4, L3, and L2 entry, whereas a translation cache can provide coverage with only an L2 entry.
Sentence 2: the translation cache may be able store additional L2 entries in place of the L4 and L3 entries that are required to provide coverage in the page table cache.
Relationship: entailment
Domain: Hardware
Sentence 1: To keep the resistive losses per supply pin constant, the number of supply pins must increase as supply currents are increased either due to increased power usage by on-chip transistors, or due to lowering of the supply voltage.
Sentence 2: for a package with a total supply current of Isupply, delivered through Nsupply pins, each pin having resistance Rpin, it is desired that «2 Isupply d Rpin Nsupply = ksupply (a constant).
Relationship: entailment
Domain: Hardware
Sentence 1: Assistive Technology refers to "any item, piece of equipment, or product system, whether acquired commercially, modified, or customized, that is used to increase, maintain, or improve functional capabilities of individuals with disabilities,"3 while Adaptive Technology covers items that are specifically designed for persons with disabilities and would seldom be used by non­disabled persons.
Sentence 2: "Assistive Technology is any object or system that increases or maintains the capabilities of people with disabilities," while Adaptive Technology is "any object or system that is specifically designed for the purpose of increasing or maintaining the capabilities of people with disabilities.
Relationship: entailment
Domain: Hardware
Sentence 1: of (Lt,Tt)as follows: fLt,Tt = |J|·h(c,r) 2 Lt -Ls 2(Ts -Tt) = ·h( , )(48) (Lt + Ls)li li (Lt + Ls)li  4.3 Pruning Rules A straight-forward way to extend the conventional domi­nance relationship between two solutions in the presence of process variation is as follows: solution (L1, T1)is said to dominate solution (L2, T2)if condition P(L1 =L2)=1 and P(T1 =T2) = 1 are satis.ed.
Sentence 2: solution (L1, T1) always results in a larger required arrival time but with a less loading capacitance when compared to solution (L2, T2).
Relationship: entailment
Domain: Hardware
Sentence 1: For example, assuming that we can use the maximum amplitude of some subset of sensors to estimate the average maximum amplitude over all sensors for each stride, the maximum amplitude of sensors whose values tend to vary more across strides is more valuable.
Sentence 2: for metric m at sensor s, this is measured as spreadm(s), which in our case returns the entropy of m as measured at s. In arriving at the value of a metric m at a sensor s, it is reasonable to sample/predict the measurements of s at only those epochs when we would expect it to yield the value of m. to figure out the maximum amplitude at s, we would like to sample/predict s s measurement only at the epochs it is likely to achieve maximum amplitude.
Relationship: entailment
Domain: Hardware
Sentence 1: 8, our adaptive LDPC coded V-BLAST system shows good throughput performance while lowering the number of feedback traffic channels for NAK signals in time-varying channels.
Sentence 2: the number of the NAK signals for retransmission is greatly decreased at lower operating SNR ranges, which reduces the overhead of queue size at the transmitter and the receiver in each IR-HybridARQ scheme.
Relationship: entailment
Domain: Hardware
Sentence 1: Further, in the absence of dynamic CS technique the pipeline would have required 50% excess guard­band to prevent any delay fall-outs at 10yrs (compare dotted curve with the plot shown in asterisk in Figure 19).
Sentence 2: usage of dynamic cycle time stealing technique brings down the guard-band needed by 30% compared with the static guard-banding technique at the end of 10 years.
Relationship: entailment
Domain: Hardware
Sentence 1: For a given TAM width and wrapper design for a core, we assume that its testing time at the high data rate is f times less than its testing time at the low data rate.
Sentence 2: if it takes Tih(wi)seconds to test Core iat the high data rate with a TAM width wi, the time taken to test it at the low data rate is Tit(wi)seconds, where Tit(wi)=fxTih(wi).
Relationship: entailment
Domain: Hardware
Sentence 1: Rearrange the elements of S in ascending order, i.e., from smallest to largest and rename them s1,s2,···.For each interval [si,si+1], FX (-1)(u)+ F'(u)isasummationoftwo linear functions and the resulting function is a linear func­tion with respect to u.
Sentence 2: the minimum function value foreachintervalmustbedeterminedbyeitherstartingpoint or end point.
Relationship: entailment
Domain: Hardware
Sentence 1: This means that by setting up the 6T hit count threshold 2N times larger than that for 10T, we can detect with high accuracy whether 10T hits are above or below their expected value.
Sentence 2: the 10T hit counter saturates .rst if and only if more than 1 of to­ 2N +1  tal hits occur in the 10T ways.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition, it takes 3 clock cycles for the reader to know there are no more tags whose IDs start with '0' alive (refer to the 5th bit sent by the reader in Table 1).
Sentence 2: the number of clock cycles required is: Cycbinary= 2k(n -1) + 3 (9) Table 1: The inquiry process of Binary-tree protocol Reader sends Tags answer Identified tag (remaining tags reset) 0 * 0 1 001 0 1 1 1 011 0 1 0 0 0 100  Figure 2: Search on a binary tree.
Relationship: entailment
Domain: Hardware
Sentence 1: In our experiments we found that for four of our bench­marks, namely, bcel, jlex, proguard, and antlr, around 1% to 10% of the safe dereferences have maximum access-path length greater than 2.
Sentence 2: in jlex some of the safe dereferences discovered by our analysis required access­paths of length up to 6.
Relationship: entailment
Domain: Hardware
Sentence 1: It n 3 consists of (n/3) repetitions of a group of three consecutive columns of different heights.
Sentence 2: the columns with weights 23h, 23h+1, 23h+2 , h=0,1, ,(n/3)-1, have heights equal to H ii .H ii .H1 ii 1 1 , 1 3 and respectively (see for example the PPM H1 ii for n=6 in Figure 2(a) where =19).
Relationship: entailment
Domain: Hardware
Sentence 1: The y-axis in the plot spans all of the ACE fault injections in Figure 5 for the corresponding analysis methodology.
Sentence 2: for FI the y-axis spans the 9% of fault injections that were not masked in Figure 5 and for ACE, the y-axis spans the corresponding 31% of trials determined to be ACE by ACE analysis.
Relationship: entailment
Domain: Hardware
Sentence 1: D G1 = {A},G2 = {B, C},G3 = {D} Figure 10: Progress of algorithm for a simple exam­ple.
Sentence 2: at the termination of our algorithm, we will .nd the selected n=4 paths organized in T =3 buckets as G1 = {A},G2 = {B,C},and G3 = {D}.
Relationship: entailment
Domain: Hardware
Sentence 1: Based on Corollary 1, we can claim that for the following realizations, A1B* C* D* E* and A*B1C1D* E* ,where sub­script * means the corresponding path can be either sensiti­zable or unsensitizable, the selected four paths achieve the optimal post-ATPG PCM.
Sentence 2: among 25 =32 possible realizations, we achieve the optimal post-ATPG re­sults in at least 24 +23 - 22 = 20 realizations, or among 20/32=62.5% possible realizations.
Relationship: entailment
Domain: Hardware
Sentence 1: 5 Experimental results Effectiveness of the mutation analysis based on the proposed mutation model has been evaluated by verify­ing the design examples released with the OSCI TLM 2.0 library [5].
Sentence 2: six examples have been considered where different TLM communication protocols are implemented, i.e., bidirectional blocking untimed for pv example, byte enable single and byte enable block, unidi­rectional blocking untimed for example 3.3, and unidirectional unblocking timed for p2p pipe thread and bus 1m 3s.
Relationship: entailment
Domain: Hardware
Sentence 1: CONCLUSION Playing the Shotoku Taishi game using the proposed system revealed that participants enjoyed playing the game and that the awareness of participants regarding the phonological and syllabic characteristics of the Japanese language deepened.
Sentence 2: with regard to the latter, the participants prepared combinations of words that would be difficult for the system to clarify, considering that the system gradually clarified the persons that presented a problem and the vocalized words.
Relationship: entailment
Domain: Hardware
Sentence 1: As well, static power, which is predominantly due to sub-threshold leak­age for current technologies[13], is very process dependent and this makes it di.cult to ensure a fair comparison given the available information.
Sentence 2: we do not know the Table 5: Dynamic Power Consumption Ratio (FPGA/ASIC) Name Method Logic Logic Logic Logic, Only &#38; &#38; Memory DSP Memory &#38; DSP booth Sim 16 rs encoder Sim 7.2 cordic18 Const 6.3 cordic8 Const 6.0 des area Const 26 des perf .r restruct Const Const 9.3 9.0 mac1 Const 18 aes192 Sim 12 .r3 Const 12 7.4 di.eq di.eq2 molecular Const Const Const 15 16 15 12 12 15 rs decoder1 Const 13 16 rs decoder2 Const 11 11 atm Const 11 aes Sim 4.0 aes inv Sim 3.9 ethernet Const 15 serialproc .r24 Const Const 24 5.2 pipe5proc raytracer Const Const 12 12 Geomean 12 12 9.2 9.0  con.dence level of either worst-case leakage estimate.
Relationship: entailment
Domain: Hardware
Sentence 1: Towards Acceleration of Fault Simulation using Graphics Processing Units Kanupriya Gulati and Sunil P. Khatri Department of ECE, Texas A&#38;M University, College Station, TX 77843 kgulati@tamu.edu and sunilkhatri@tamu.edu ABSTRACT In this paper, we explore the implementation of fault simulation ona Graphics Processing Unit (GPU).
Sentence 2: we implement afault simulator that exploits thread level parallelism.
Relationship: entailment
Domain: Hardware
Sentence 1: In order to decide the required time interval for noise at a node to reach any DFF within its sampling window, we define the effective noise window TWeff N as such that only noise existing at node N inside TWeff N may be able to reach at least one DFF during the DFF s sampling window.
Sentence 2: if a noise originates or arrives at node N A larger TWeff N means a higher probability that a noise on node N can reach a DFF within the DFF s sampling window.
Relationship: entailment
Domain: Hardware
Sentence 1: The problem to noccalculate LB1 can be formulated as a graph problem.
Sentence 2: noc we construct a test incompatibility graph G =(V,E), in which each node vi denotes an embedded core and its weight equals LBi,noc, and we add an edge eij between two nodes vi and vj if these two cores cannot be tested simultaneously no matter which test I/O ports are utilized for them.
Relationship: entailment
Domain: Hardware
Sentence 1: However, in both [15, 21], the delayof the circuit is increased signi.cantly as CWSP elements are added be­fore every .ip-.op in the design.
Sentence 2: if an SET event results ina glitch of width 8 at the un-delayed input to the CWSP element, it willattain its correct value after time 8.
Relationship: entailment
Domain: Hardware
Sentence 1: The trend of a disk annual Ri j =1 failure rate as the disk utilization grows is different from that U = = i reported in the literature.
Sentence 2: our disk failure rate model BB disk disk , (2) built from real-world data of disk failures suggests that the probability that a disk fails under either very low or very high where Bdisk is the bandwidth of the disk system.
Relationship: entailment
Domain: Hardware
Sentence 1: Behind these di­verse breeds of placement algorithms, several benchmarks played a key role in stimulating state-of-the-art placement research.
Sentence 2: the appearance of the ISPD98 bench­mark suite [6] modeled real designs into partitioning bench­marks, which were later translated into placement bench- Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: entailment
Domain: Hardware
Sentence 1: Then, the DSE problem can be described as follows: Given a throughput (or initial interval) constraint for an actor, which implementation should be selected and how many replicas are needed so that the aggregated throughput of all the replicas is no less than the throughput constraint?
Sentence 2: for actor fm we want to get binary integers x1, x2,...,xSm indicating which implementation is selected, and integer um indicating number of replicas needed.
Relationship: entailment
Domain: Hardware
Sentence 1: THE HISTORY-BASED TAG-COMPARISON CACHE 2.1 Main Idea At and after the second reference to the same instruction in a cache-miss interval, performing tag checks is unneces­sary, as explained in Section 1.1.
Sentence 2: we can omit the tag check if: (i) the target instruction has been ref­erenced before, and (ii) no cache misses have occurred since the previous reference to the target instruction.
Relationship: entailment
Domain: Hardware
Sentence 1: The Neyman-Pearson lemma [14] says that the decision rule should be con­structed in order to have the maximum probability of detec­tion while not allowing the probability of false alarm to ex­ceed a certain value a.
Sentence 2: the Neyman-Pearson criterion is the solution to the following constrained opti­mization problem: max{Pr(Hits)}, such that Pr(FA) = a where a is an user-speci.ed upper bound of the probability of false alarm.
Relationship: entailment
Domain: Hardware
Sentence 1: Putting it all together, the overall energy cost of Kerberos key establishment is between 39.6 mJ and 47.6 mJ, while ECMQV key exchange requires an energy of between 79.0 mJ and 84.6 mJ (see Table 1).
Sentence 2: the energy consumption of ECMQV and Kerberos di.ers merely by a factor of between 1.78 (for high transmit power) and 1.99 (for low transmit power).
Relationship: entailment
Domain: Hardware
Sentence 1: Next, we estimate each component of the delay­power pro.le (DPP) {sl 2}Nh-1 by summing the energies of l=0 the 2D+ 1 Doppler coe.cients.
Sentence 2: the lth DPP element during the ith MCM symbolintervalisestimated as PD .
Relationship: entailment
Domain: Hardware
Sentence 1: The VPB steering scheme In consequence, to minimize the above mentioned communications increase, the second modification to the Baseline steering scheme should only apply to those cases in which there is a potential for improving the workload balance.
Sentence 2: we propose that the steering logic considers predicted source operands to be mapped in all clusters only when the workload imbalance is higher than a given threshold (that we set empirically to DCOUNT=16 and DCOUNT=8, for a 4-cluster and a 2-cluster configura­tions, respectively).
Relationship: entailment
Domain: Hardware
Sentence 1: Condition 1: Basic Fishbone A placement based on the basic Fishbone scheme is 100% Fishbone routable, if all the virtual output pins in the same column are assigned different  GOX and all the virtual input pins in the same row are assigned different GIY.
Sentence 2: no two vertical trunks in the same column are placed on the same X-coordinate (X-index), and no two horizontal branches in the same row are placed on the same Y-coordinate (Y­index).
Relationship: entailment
Domain: Hardware
Sentence 1: Much work has been devoted to the investigation of several aspects of the pseudorandom testing techniques, such as the impact of the finite length of the input pulse sequence, the duration of the single pulse, the ADC resolution, etc [1-3].
Sentence 2: aDC s with low resolution can be employed to sample the DUT response as the averaging effect intrinsically performed by the input-output cross­ correlation operation greatly reduces the effects of the quantization errors [2].
Relationship: entailment
Domain: Hardware
Sentence 1: of the NC-OFDM transceiver is better than that of the -1 10 MC-CDMA transceivers.
Sentence 2: as the percent­age of deactivated subcarriers increases, the BER per- BER BER  -2 -2 BER 10 -3 -3 10 -4 -4 formance of the MC-CDMA system worsens while the -2 10 0 2 4 6 8 10 12 14 16 18 20 SNR (dB) (a) AWGN Channel.
Relationship: entailment
Domain: Hardware
Sentence 1: In fact this intuitive idea can be formalized quite nicely with the following property: the output of a logical function should only be marked as tainted if and only if some set of tainted inputs actually had an opportunity to a.ect the output.
Sentence 2: if it is possible to a.ect a change in the output through any changes in any of the tainted inputs, the output should be marked as tainted.
Relationship: entailment
Domain: Hardware
Sentence 1: METHODOLOGY We now explain the method we use to explore voltage and fre­quency scaling as a static technique for design space exploration in terms of power versus performance trade-offs.
Sentence 2: 5.1 Voltage/Frequency Scaling we analyze the case where we reduce the voltage of the off-chip memory and off-chip buses from 3.3 Volts to 2 Volts (note that our original system consists of the MARS [12] proces­sor powered at 2.75 Volts with the memory buses and memory chip powered at 3.3 Volts).
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION Field Programmable Gate Arrays (FPGAs) are increasingly demanded by spacecraft electronic designers, because of their high flexibility in achieving multiple requirements such as high performance, no NRE (Non Refundable Engineering) cost and fast turnaround time.
Sentence 2: sRAM-based FPGAs are uniquely suited for remote missions, because they can be reprogrammed by the user as many times as necessary in a very short period.
Relationship: entailment