sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Again,thetechniquesweredevelopedspeci.callyfortheXil­inxXC6200architecture.Addresseswerecompressedusing runlengthencodingwhiledatawascompressedusingLZ compression(sliding-windowmethod[11]).Dedicatedon­chiphardwarewasrequiredforbothmethods.Asetofcon­.gurationbit-streams(2;88Kbits)wereusedto.ne-tune theparametersoftheproposedmethods.A16;bitsizewin-dowwasusedintheLZimplementation.Whilethiswindow sizeledtogoodresultsforthesebit-streams,itisimpractical forlargercon.gurationbit-streams.Moreover,a.ne-tuned schemeforlargercon.gurationbit-streamswouldleadto largersizewindows.Asstatedin[8],largersizewindows imposeafairlyhighhardwarepenaltywithrespecttothe bu.ersizeaswellasthesupportinghardware.
Sentence 2: in[6],wehavedemonstratedpreliminarycon.guration compressionresultsusingadictionary-basedapproach.How­ever,theapproachthatisproposedinthispaperissignif-icantlydi.erentthantheoneproposedin[6].In[6],the Con.guration LZW Bit-Stream Compact Representation DICTIONARY INDEX DICTIONARY Selectively delete substrings Heuristic Selectively delete nodes INDEX INDEX Figure2:Ourcon.gurationcompressiontechnique decompressedstringsaredeliveredinthereverseorder.In addition,theheuristicproposedin[6]onlydeletesallthe leafnodesfromallthesu.xtreeswithoutconsideringhow theindexsizeisa.ected.inthispaper,adi.er­entapproachisproposed.Ourgoalistodeletestringsand individualnodesinabottom-upapproachconsideringthe overallsavingsinmemory,thatis,boththedictionaryand theindexmemory.Asaresult,byapplyingourtechnique tothecon.gurationbit-streamsin[6],thememoryrequire­mentsforstoringthedictionaryandtheindexcanbefurther improvedby6;13%(seeSection5).
Relationship: neutral
Domain: Hardware
Sentence 1: In this section, we examine the asymptotic performance of PBcast andderive theoretical formulas for .nding optimal forwarding probability p. In PBcast, every node relays a packet that it receives for the .rst time with some probability p. Let us assume that at any time slot, in which the packet travels in the network, we color eachnode as blackor white withprobabilitypand1-p, respectively.
Sentence 2: 43rd Annual IEEE Symposium on Foundations of Computer Science, 2002.
Relationship: neutral
Domain: Hardware
Sentence 1: [9] H.Lang,J.Pfeifer,andJ.Maguire,Usingon-chip testpatterncompressionforfullscanSoCdesigns," Proc.ETW,2000,pp.47-52.
Sentence 2: wechooseasetofcolumnsrandomlyfromtheRM, andtreatthemsimilartodistinguishingcolumnsfor designingCmap.Todefnez,wekeeptheremaining pcolumnsofRM,andthentoeachrowY0(ti)ofthere­ducedRM,weaddthecounterstateb1b2:::bdlog2ke representingthetestti.Thetruthtableisthende­fnedasbefore.Thisapproachalsopreserveszero­aliasing.thesizeoftheinputsetofvariables defningzcanbeappropriatelychosentoftinavail­ p ablelogicsynthesistools,providingusoptionsfora fexibledesignbychoosingthesizeofp.Inthelimit­ingcase,nodistinguishinglinesmaybeused,i.e.,the second-stagecompactorisnotrequired.Allthemout­putsoftheCUTalongwiththecounterbitswillde­fnez,andsingle-outputcompactionwillbeachieved.
Relationship: neutral
Domain: Hardware
Sentence 1: Q-BART ThelogiofearlyversionsofQCAomponentssuhasthe logiunitorintermediatesignalgenerationlogiwassimply heked"by­hand"withtruthtables.Additionally,designs werereatedsimplybyusingsymbolstorepresent45of g0­degreeQCAells.Nofuntionalityouldbeattahedto them.Asdesignsgrewlarger,thislakofdesignautomation andtestingbeamemoreandmoreofaproblem.Tosolve thisproblem,anarhiteturalsimulator,Q­BART(Quan­tumBasedArhitetureRulesTool),wasdeveloped.
Sentence 2: 6.2.6 A Device Cell of a Majority Gate Interacting with a 90-Degree Cell Thisaseisidentialtothease6.2.1.Thedevieellwill simplygiveitsdatatotheg0­degreeoutputellofthema­joritygate.
Relationship: neutral
Domain: Hardware
Sentence 1: By jittering the interarrival times of the CBR UDP packets using a normal distribution (mean: 20ms, stddev: 1ms), we reduced the probability of the phenomenon occurring to the point where we did not observe it in any of our subsequent tests.
Sentence 2: the FC Inactive .ow reached the same cwnd value every congestion event and never triggered the heuristic.
Relationship: neutral
Domain: Hardware
Sentence 1: First identi.ed by E. F. Rent and published by Landman and Russo [8], Rent s Rule says that the number of wires that must cross into or out of a region of N components is reasonably modeled by: BW = cNp (1) where p is the Rent Exponent, which is typically in the range 0.5 0.7.
Sentence 2: assuming the data bits stay .xed, this also reduces the number of instructions, since an instruc­tion now applies to a group of W bits.
Relationship: neutral
Domain: Hardware
Sentence 1: In­stead of the traditional energy consumption structure ET > ER EL > EP, where ET , ER, EL and EP represent the energy consumption for transmitting, receiving, idle listening and processing, the energy consumption struc­ture is like ET » ER EL > EP.
Sentence 2: at the same time, any routing algorithm at the data link layer can be implemented according to application requirements.
Relationship: neutral
Domain: Hardware
Sentence 1: For example, suppose there is a 3-bit word variable with an initial interval [0, 7] and an initial bit-vector XXX, where X stands for unknown, if its interval is shrunk to [2, 3], then its bit-vector can be set as 01X correspondingly.
Sentence 2: this strat­egy is called the 1BUIP scheme, which requires one implication vertex of the current decision level on the cut.
Relationship: neutral
Domain: Hardware
Sentence 1: [17] Y. Sato, S. Hamada, T. Maeda, A. Takatori, and S. Ka jihara.
Sentence 2: when the delay sizes are small, delay defects can be hardly trig­gered in the test mode at a low frequency, and have to be tested at the normal operation speed with timing-aware ATPG methods.
Relationship: neutral
Domain: Hardware
Sentence 1: System-level designers only need to supply high-level NoC parameters to use our tool to explore the system­level impact of variation-induced timing violations.
Sentence 2: we perform the following hybrid modeling pro­cedure: we use STA to detect only the paths that are likely to fail, the worst-case input patterns that stress these paths, and then per­form circuit-level simulation only for these paths and these input patterns.
Relationship: neutral
Domain: Hardware
Sentence 1: Setup (long-path) constraints ensure that the sig­ * This work was partially supported by the National Science Founda­tion under Grant CCF-1320585 and a grant from Mentor Graphics.
Sentence 2: denote Ic and Oc as a set of pins in I and a set of pins O that are de.ned with a complex timing constraint c as de.ned above.
Relationship: neutral
Domain: Hardware
Sentence 1: wleak,while ytomain .Ho tdur­ to to yleak 1.5 1.8 1.6 1.4  Amplitude (V) 1.2 1 0.8 1 0 -0.5 0.9 100 200 300 400 500 600 Time (nsec) Vth (mV) Vth (mV) (a)WaveformsofHS-Dominogate (b)NormalizeddelayvsVth (c)Normalizeddynamicpowervs (Vdd=2.5V) Vth Figure4:BehaviorofHS-Domino Thecontention-freeoperationisclearlydemonstratedinFig­ure4(a)whereduringtheprechargephase(CLKgoesLOW), thekeeper'sinput(gate)remainsHIGH.
Sentence 2: figure7(b)comparestheMHS-Dominocircuitwiththe MTCMOSCD-Dominocircuitintermsofdynamicpower at500MHzCLK.AlthoughtheMHS-Dominocircuitin­troducesslightlyhigherloading,andanSSG,itactually hassignifcantlylowerpowerdissipationthantheconven­tionalMTCMOSversion.Thisisattributedtothefollow­ing:1.EliminationofthecontentionintheMHS-Domino gate,whichmeansthattherearenoshort-circuitcurrents duringswitching.2.N1 andP1 areminimumsizedde­vices,contributingtoaverysmallloadingefect.3.The sleepsignalgeneratorhardlyconsumesanydynamicpower becauseitsoutputisalways1"duringtheactivemode, and0"duringstandby.noswitchingoccursexcept duringtransitionfromonemodetotheother.Thesetran­sitionsarenotfrequentandtheirpowerdissipationpenalty becomeslesssignifcantifthesystemstaysmostofthetime intheidlestate(95%) Acomparisonbetweenthenormalizedleakagepowerofthe MTCMOSCD-DominoandMHS-Dominoisalsoshownin Figure7(c).MHS-Dominoconsumesslightlyhigherleak-agepowerthantheMTCMOSCD-Domino(controlledNM).
Relationship: neutral
Domain: Hardware
Sentence 1: The veri.cation was conducted using a Linux version of Cadence SMV in a Pentium IV 1.3 GHz workstation with 1 GB of main mem­ory.
Sentence 2: transfer Cancellation Due to the pipelined nature of the AMBA protocol, a master initiates transfer i +1before re­ceiving the response for transfer i. if transfer i resulted in a SPLIT or RETRY response from the slave, the master must cancel the transfer i +1.
Relationship: neutral
Domain: Hardware
Sentence 1: Design iterations are fast because there are so few corners.
Sentence 2: a general trajectory sampling method stores the linearized conductance and capacitance matrices, G and C, that are re­turned at each time point k by the Newton-Rhapson algorithm during transient simulation [1], [2]: G(k) C(k) = .i(v)|, = .q(v)|(2) vk vk After running projection-based MOR, the reduced matrices can be used as a low-order expansion point in a piecewise model [2].
Relationship: neutral
Domain: Hardware
Sentence 1: [9]M.B.CohenandC.J.Colbourn.Steinertriple systemsasmultipleerasureodesinlargediskarrays.
Sentence 2: inProeedingsofIPCCC2000(19thIEEE InternationalConfereneonPerformane,Computing andCommuniations),pages288.294.IEEE, February2000.
Relationship: neutral
Domain: Hardware
Sentence 1: Whiletransac­tional memory hasbeen extensively studiedforthegeneral­purpose computing domain, there have been relatively few works that consider adopting TM in the embedded domain (e.g.,[5,9,13]).
Sentence 2: the memory model of a MPSoC de.nes the responsibilities and challenges of the programmer with re­spect to management of data.
Relationship: neutral
Domain: Hardware
Sentence 1: To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.
Sentence 2: based upon the psychological implications of highness for social relations and nonverbal behavior [8], perceptions of power [16], and expressing authority [1], it is plausible that this vertical dimension would influence the psychological experience of thrown voice locations, too.
Relationship: neutral
Domain: Hardware
Sentence 1: For example, the upcoming Intel® Core 2 pro­cessor is reported to provide wider superscalar execution with larger buffers as compared to previous Intel® Pentium-M and Core 1 microarchitectures.
Sentence 2: store Queue Index Prediction example illustrating (a) a store updating the SPCT, (b) a misforwarded load using the SPCT to update the FSP, (c) a later instance of the same store updating the SAT, (d), a later instance of the load using the FSP and SAT to compute a SQ index, and (e) the load using the predicted index to directly access the predicted SQ entry.
Relationship: neutral
Domain: Hardware
Sentence 1: 2, assuming 8 buffer slots per input in all con.gurations: (a) 8 slots per input for a WH router; for VC­based routers: (b) 2 VCs per input with 4 slots/VC, and (c) 4 VCs per input with 2 slots/VC.
Sentence 2: results for homogeneous folded networks will be provided in our last set of experiments.
Relationship: neutral
Domain: Hardware
Sentence 1: Perez et al [37] experimentally compared twelve of the recent and/or well known prefetching schemes using the SPECcpu2000 benchmarks, and found that the Global History Buffer (GHB) with its PC/DC (program counter/ delta correla­tion) variant [25] scheme works the best among the twelve prefetchers.
Sentence 2: the results clearly demonstrate that the performance of the epoch-based correlation prefetcher is sensitive to available memory bandwidth.
Relationship: neutral
Domain: Hardware
Sentence 1: The optimized mapping through NSGA-II algorithm along with our approach is shown in Fig.8(b), where performance bottlenecks denoted by red boxes have restricted the latency proportion and saturated throughput to be about 184% and 12.2 GB/s respectively.
Sentence 2: 4 n ¦ni 1 PSAi, j ¦ ( i 1 p(i1, j,v,n1) p(i4, j,v,n4)p(i, j,v 1,n 1)) (20) 4 n n ,n 14 n ¦ni i 1 m m v-m where, p(i, j,v,m) Cv Fi, j (1-Fi, j ), i1, ,i4 zi, i1 i4 we derive the parameter blocki,j based on Eq.21.
Relationship: neutral
Domain: Hardware
Sentence 1: Dynamic Voltage and Frequency Scaling (DVFS) [14, 6] is a widely-used technique to scale a core s perfor­mance and power (e.g., Intel Turbo Boost [1]).
Sentence 2: we limit the number of single-thread workloads to 14 to ensure that the number of single­thread and multi-thread workloads is equal, so that the single-thread results do not dominate the overall average performance data.
Relationship: neutral
Domain: Hardware
Sentence 1: ClkIn2, t = T) is -t »-2t ÿVDD RC RX RC XR (8) V () t =-e 1-e + V , 12 RX +2R RX +2R DD / -t »-2t ÿVDD RRC RC XXR (9) V () t =-e 1+ e + V , 2 R +2RR +2R DD 2 XX / where V1(t) = VClkOut1(t) and V2(t) = VClkOut2(t).
Sentence 2: (a) (b) Figure 5: Current through RW1.
Relationship: neutral
Domain: Hardware
Sentence 1: Many existing CMPs use write­through L1 caches [26,4, 19] to avoid large coherence traf.c from their small L1 caches.
Sentence 2: on average across all commercial workloads, private caches have 10% RWS misses, while CMP-NuRAPID with ISC has only 2%; a reduction of 80%.
Relationship: neutral
Domain: Hardware
Sentence 1: In Proceedings of the USENIX Conference on File and Storage Technologies, pages 115 130, 2003.
Sentence 2: we can summarize the major contributions of this work as follows: We quantifytheimpactof conventionalcompiler-directed I/OprefetchingonsharedcachesatI/O nodes.Theexperimen­tal data collected using four high-performance applications that use disk-resident data sets reveals that, while conven­tionalI/O prefetchingbrings certain performance bene.ts,its effectiveness reduces signi.cantly as the number of clients is increased.
Relationship: neutral
Domain: Hardware
Sentence 1: Unfortunately, these bits and the logic to process them will be kept in the debugger process, necessitating control transi­tions all the way from the hardware layer to the user space software layer and back (as shown in the .rst half of Figure 1); also, we incur the costs of switching between the original process s virtual address space and that of the debugger where the counter is kept5 .
Sentence 2: 11http://recon.cx/2008/archive.html [11] P. A. Karger and D. R. Safford.
Relationship: neutral
Domain: Hardware
Sentence 1: Rather than optimizing the thermal pro.le of a single architecture instance, new synthesis methodologies and tools have to be developed taking into consideration the thermal features of the various architectural 978-3-9815370-0-0/DATE13/&#38;#169;2013 EDAA instances mapped onto the CGRP through recon.guration.
Sentence 2: [29] George L. Nemhauser and Laurence A. Wolsey.
Relationship: neutral
Domain: Hardware
Sentence 1: Categories and Subject Descriptors B.3.1 [Memory Structures]: Semiconductor Memories Static memory (SRAM); B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids General Terms Design, Performance, Reliability  Keywords SRAM, Write margin, Dynamic noise margin, Reliability, VCCmin, Static Noise Margin, Variation 1.
Sentence 2: the current noise circuit can be considered as a good approximation of the write circuit.
Relationship: neutral
Domain: Hardware
Sentence 1: 2.1 Global Routing In the 2D global routing problem, a placement solution is partitioned into a 2D array of global cells (g-cells), and then is modeled into a grid graph G(V, E), where V denotes a set of g-cells, E denotes a set of grid edges (g-edges), and two abutting g-cells are connected by a g-edge.
Sentence 2: s(Rx,y,w,h)= S(Rx2,y2,w2,h2) 2. foreach net n in S(Rx1,y1,w1,h1) 3. if n is not in S(Rx,y,w,h) 4. insert n into S(Rx,y,w,h) 5.
Relationship: neutral
Domain: Hardware
Sentence 1: Sev­eral techniques have tried to address this issue either by computing the discrepancy or disparity of sampling[8][7] or by changing the variance of the sampling distribution [10], to guide the direction of the growth to where it would en­counter more samples.
Sentence 2: in Algorithmic and [1] R. Alur, T. Henzinger, and P.-H. Ho.
Relationship: neutral
Domain: Hardware
Sentence 1: The model consists of seven attributes: the type, pipeline, and stage of one instruction; the type, pipeline, and stage of a second instruction; and the register interdependency that may exist between the two.
Sentence 2: as depicted in Figure 7, the processor consists of four exe­cution pipelines: branch (BPipe), simple arithmetic (RPipe), com­plex arithmetic (MPipe), and load/store (SPipe).
Relationship: neutral
Domain: Hardware
Sentence 1: Quantitatively, the predicted time with FPGA G/S model is 197.2 seconds if all G/S in FLASH larger than 16K are ported while porting the top 33 results in execution time of 198.7 seconds for accelerator system.
Sentence 2: 6 BACKGROUND The prevalence of Gather/Scatter operation in application can be seen in sorting algorithms, hash searches, and sparse-matrix vector multiplication[23] to name a few.
Relationship: neutral
Domain: Hardware
Sentence 1: ...., ......, etc) of transistors may change drastically.
Sentence 2: resistive network) can better approx­imate the original graph s power dissipation for arbitrary input excitations, the support-graph preconditioner will be more e.ective in approximating the dominant eigenvalues of the original system, thereby more signi.cantly reducing the number of iterations for .nding the solution.
Relationship: neutral
Domain: Hardware
Sentence 1: Restricting the predictor to learn correlations only with non-biased branches enables a modest length global history register to reach very deep into the program s execution history to .nd correlated branches and provide highly­accurate branch predictions with a modest storage budget.
Sentence 2: for incorporating such a predictor into a commercial processor, we advocate using probabilistic 3-bit counters [10] in the BST.
Relationship: neutral
Domain: Hardware
Sentence 1: Because in previous micrometer technologies, a failing cell expe­rienced all three kinds of failures (hold, read and write), it was not necessary to analyze separately the cell s stability for the read or write operations.
Sentence 2: the comparisons of the simulated read margin with (a) the calculated read mar­gin with Vdd = 800mV , (b) V1,2 and V3,4 with Vdd = 800mV , (c) the calculated read margin with Vdd = 600mV and (d) V1,2 and V3,4 with Vdd = 800mV .
Relationship: neutral
Domain: Hardware
Sentence 1: By replacing their simple passive backend electronics with BEI, it may prove possible to develop a machine capable of near-perfect brain tumor resection (surgical removal) since a study [11] concluded that tumor cells could be reliably detected with 95% accuracy and only a 12% false positive rate by their conductivity alone.
Sentence 2: in our case, the gain control was implemented in the low impedance internal path of the instrumentation ampli.er.
Relationship: neutral
Domain: Hardware
Sentence 1: TECHNOLOGICAL DETAILS The IC has been designed and fabricated using Maxim GST-2 semicustom double-poly self-aligned Silicon bipolar process, that features npn and pnp transistors, diodes, polysilicon and NiCr resistors, capacitors and three metal layers for interconnections.
Sentence 2: price-competitive solutions are required for systems Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: neutral
Domain: Hardware
Sentence 1: For SPLASH2, we use the default inputs, while for PARSEC, we use the simmedium input size.
Sentence 2: for a .xed number of BHQ[i] entries, as the block size increases, we lose less window (Figure 8(a)), the hit rate increases (Figure 8(b)) and the number of com­parisons decreases (Figure 8(c)) however, we saw in Figure 7(b) that false positives increase.
Relationship: neutral
Domain: Hardware
Sentence 1: INTRODUCTION Technology scaling results in interconnect delay increasingly dom­inate gate delay which means that a design that meets timing in a zero wireload timing environment (e.g., after logic synthesis) may not meet timing after performing physical synthesis.
Sentence 2: after placement and optimization, one can perform timing anal­ysis to identify not only the most critical paths, but all gates that lie on paths that do not meet their timing constraints.
Relationship: neutral
Domain: Hardware
Sentence 1: Addition network In fact, the number of speci.ed carries in column 2, 2 c=1, cannot be observed on the physical carry signals x C1,1 and C1,2 using BCP.
Sentence 2: fortu­nately, there always exists a functionally equivalent addition network and an order of the addends such that the number of n+1 carries identi.ed by Boolean propagation is c. In fact, x a simple chain of half adders like in Figure 6 ful.lls this requirement.
Relationship: neutral
Domain: Hardware
Sentence 1: Between 8 and 15 encryption threads, we are above the maximum number of threads that can truly run in parallel over the 8 cores.
Sentence 2: to overcome this in terms of network packets, we propose the use of multiple GPUs (our server authorizes the use of up to four GPU cards) and the grouping of packets together to have .les of higher size, almost 64KB or even 128KB.
Relationship: neutral
Domain: Hardware
Sentence 1: INTRODUCTION With the increasing presence of multimedia functions such as audio, video playback and speech synthesis in battery-powered devices and smart sensors, power management has become a top design consideration due to the limited energy budget and battery capacity.
Sentence 2: all the arithmetic computations in the region as well as all the memory accesses within the shaded sequence in Figure 2.4 can be skipped upon a RACB hit.
Relationship: neutral
Domain: Hardware
Sentence 1: The length of each internal scan chain, L, is 4 for the circuits S13207 and S15850, 9 for the circuits S35932 and S38417 and 8 for the circuit S38584.
Sentence 2: the best previous result for each circuit is shown in bold font, and an improvement percentage is listed in the last column based on the comparison to the best previ­ous result for each circuit.
Relationship: neutral
Domain: Hardware
Sentence 1: To reduce the sub-threshold leakage for efficient thermal design, Vt can be increased.
Sentence 2: by the same token, the heat transfer rates qbj out of each of the six boundaries of the domain may also be written as: 6 qbj = .bfjTf + b0 j q ( j =1,2,...,6) (8) f =1 where bfj's are the coefficients relating heat transfer rate at face j to temperature of face f and b0j is the relative heat transfer rate at face j to heat generation rate q in the cell.
Relationship: neutral
Domain: Hardware
Sentence 1: It should be notedd that the analyssis above was ddone using a linear electric field.
Sentence 2: comes Department of Electrical &#38; Computer Engineering Department of Materials Science &#38; Engineering University of Virginia, Charlottesville, VA 22908 {mk4kg, mrs8n, saw6b, jl5tk, rbc2w}@virginia.edu  ABSTRACT Recently, with the discovery of multiferroic materials, there has been a great interest in creating logic devices which exploit both magnetic and electric properties of these materials.
Relationship: neutral
Domain: Hardware
Sentence 1: The director, as a TV journalist, had expertise in assembling stories from content representing social events and was, therefore, also interested in processing own material in a manner similar to MyVideos.
Sentence 2: springer, 96 106 [16] Ursu, M. F., Kegel, I., Williams, D., Thomas, M., Mayer, H., Zsombori, V., Tuomola M. L., Larsson, H., and Wyver, J.
Relationship: neutral
Domain: Hardware
Sentence 1: UGAL matches the throughput of VAL on worst-case traf­.c but results in substantially higher latency because of the packets that are sacri.ced to .ll the minimal queues before congestion can be sensed.
Sentence 2: cONCLUSION Global adaptive routing is required to load-balance the global channels in some large-scale interconnection networks to achieve reasonable performance.
Relationship: neutral