sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: A Design Methodology for the Exploitation of High Level Communication Synthesis Francesco Bruschi, Politecnico di Milano, Italy Massimo Bombana, CEFRIEL, Italy Abstract In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions.
Sentence 2: the issues related to the synthesis of the communication between the system elements are considered.
Relationship: entailment
Domain: Hardware
Sentence 1: In contrast, dynamic effects threaten the safe transfer of data.
Sentence 2: transient noise can push data and timing edges apart andleadto incorrect sampling(excessiveskew),oritcanpushtwo consecutiveedges on the same wire suf.ciently close to cause inter­symbol interference.Wave pipelining needs additional timing mar­gin to tolerate this, hence must run slower as a connection length­ens.
Relationship: entailment
Domain: Hardware
Sentence 1: Depending on the compari­son between the VCO and o.-chip clocks, an optimal con­trol voltage (Vcont) is applied to VCO in order to match the two clocks (i.e., PLL locking).
Sentence 2: we can say that Vcont of PLL in locked condition actually re.ects any sources of variation in operating condition.
Relationship: entailment
Domain: Hardware
Sentence 1: Assuming equal current densities j on each of the two segments, this implies that there is an effective divergence, which can eventually lead to void nucleation and growth, equivalent to a current density of 2j on both wires.
Sentence 2: as compared to the case where the left-hand segment is missing and the right-hand segment has the same current density of j, the expected rate of atomic transfer is doubled at this node.
Relationship: entailment
Domain: Hardware
Sentence 1: 3) Ef.ciency: Now that the accuracy and the signi.cant computational savings of the proposed approach are estab­lished, we proceed to demonstrate its ef.ciency.
Sentence 2: a closer look at the plot of evolution of the .gure of merit (see Fig.2(b)) reveal the following interesting observations: · The rate of improvement of .gure of merit (slope of the evolution) with increasing number of simulations demon­strate the superiority of the proposed approach.
Relationship: entailment
Domain: Hardware
Sentence 1: Step 5: Add and schedule explicit prefetch instructions After all instructions have been scheduled and the algorithm has attached the appropriate hints to memory instructions, it may add explicit software prefetch instructions for some memory oper­ations.
Sentence 2: instructions that have a stride of 0, 1 or -1 ele­ments map their data ef.ciently to the buffers and the prefetch hints associated to them guarantee a high L0 hit rate (the same applies to strides of N or -N elements when loops are unrolled N times due to interleaved mapping, N being the number of clusters).
Relationship: entailment
Domain: Hardware
Sentence 1: In particular, we identify the three most signi.cant parameters for achieving ef.­ciency by exhaustively evaluating the Ck 15 possible combinations for k =1,..., 3.
Sentence 2: there are C115 = 15, C215 = 105,  C15 3 = 455 ways to select one, two, and three parameter(s) for adaptivity, respectively.For each k and each of the Ck 15 possible combinations foragiven k,we repeatthe optimizationof Section4 to identify the ef.ciency-maximizing combination.
Relationship: entailment
Domain: Hardware
Sentence 1: The write notices, however, reflect only the information re- garding the write operations.
Sentence 2: only the Acq(a) Acq(b> Acq(c) Acq(a) (a)An Example of the Inter-Process Dependency ®- (b) Dependency Tracking Figure 3: An Example of Dependency Tracking  vector clocks for release operations following any write operation are included in the write notices.
Relationship: entailment
Domain: Hardware
Sentence 1: In i (j) (j) fact, Gis a set of continuous space, and Ris a mapping i i from x *(t0 +.t)to m(t0 +.t)and x(t0 +.t).
Sentence 2: (0) Gis noted as the condition of no discrete jump in mi,and i (0) therefore Rdoes not change anything.
Relationship: entailment
Domain: Hardware
Sentence 1: We de.ne the ODC function ODCMi (x) of input x of a module Mi as the .rst term of equation 1.
Sentence 2: oDCM (x) represents the conditions under which input x to module Mi is not observable at the module output z.We can then rewrite equation 1 as: ODC(x)= ODCMi (x)+ ODC(z) (2) Given a module Mi with K inputs, {x1,x2, ..., xK },the ODC conditions of the inputs are computed by traversing the fanin cone of Mi backward.
Relationship: entailment
Domain: Hardware
Sentence 1: It is important to note that the LQ/SQ CAMs are much more complex than the CAMs used in the reser­vation stations (RS) for scheduling non-memory instruc­tions.
Sentence 2: the RS CAMs match on relatively small tags (plog2 Physical RF Sizel, typically 6-8 bits) whereas the LQ/SQ typically match on memory addresses (32-64 bits), although tricks such as staggered/partial tag matching and virtual-indexing/physical-tagging can be used to reduce the overhead.
Relationship: entailment
Domain: Hardware
Sentence 1: 1e-010 1e-012 1e-014 1e-016 1e-018 Nadh 1e-020 After the optimization, we perform the E-dominance analy­ sis to search accurately near the edge of the Pareto-optimal region.
Sentence 2: we use a condition of approximated domi­nance to perform a post-processing analysis in order to cal­culate an approximated Pareto front.
Relationship: entailment
Domain: Hardware
Sentence 1: The rationale behind this approach is to make sure that there are no discontinuities on the cache size that make the system schedulable.
Sentence 2: assuming that a given system using N cachelinesis schedulablebut non-schedulable when using N - 1 cache lines, it is necessary to ascertain whether the systemis non-schedulablefor any sizelowerthan N - 1.
Relationship: entailment
Domain: Hardware
Sentence 1: Our results demonstrate that the reliability improvement due to disk scrubbing depends on the scrubbing frequency and the workload of the system.
Sentence 2: for typi­cal scrubbing frequencies and workloads, the reliability im­provement due to disk scrubbing does not reach the level achieved by the IPC-based intra-disk redundancy scheme, which is insensitive to the workload.
Relationship: entailment
Domain: Hardware
Sentence 1: DeGroot de.nes an uncertainty function as any nonnegative measurable function U de.ned on the space P of distributions p over T.2 DeGroot then de.nes the information provided by an experiment by IDG[X, p;U]=U(p)-E[U(pX )].
Sentence 2: iDG[X, p;U] would be the difference be­tween the uncertainty prior to the experiment and the ex­pected uncertainty after the experiment.
Relationship: entailment
Domain: Hardware
Sentence 1: The clock periods under both the TSV1-in-ST configuration and the TSV2-in-ST configuration are larger than their reference clock period under the normal configuration implying that using an ST inverter as the output driver of a TSV does expand the clock period.
Sentence 2: the amount of expansion in the clock period is much larger in the TSV2-in-ST configuration than in the TSV1-in-ST configuration, since the TSV2 delay is much larger than TSV1 delay.
Relationship: entailment
Domain: Hardware
Sentence 1: BACKGROUND 2.1 Macro-Model Generation Given a system described by tabulated date H(sk ) .Cm×m , 1 = k = ns provided either from measurement or simulation, the task of macro-model generation is to .nda system G(s)= CT (sI - A)-1B + D (1) ,where A .Cn×n , B .Cn×m , C .Cm×n , D .Cm×m,such that the error ns E = |G(sk) - H(sk)|2 (2) 2 k=1 is minimized.
Sentence 2: in rational .tting or vector .tting, the matrix A is diagonal, i.e.
Relationship: entailment
Domain: Hardware
Sentence 1: We described a procedure for fault col­ b02 6 64 70 13 0.14 60.00 13 100.00 lapsing based on the level of similarity, and studied its b01 8 256 135 26 0.53 68.15 26 100.00 effectiveness experimentally.
Sentence 2: we identi.ed b06 12 4096 202 30 0.50 71.78 30 100.00 a minimum level of similarity that allows us to perform  b03 35 20000 452 38 0.45 75.88 38 100.00 b04 78 20000 1341 63 0.50 74.27 63 100.00 fault collapsing based on the level of similarity without b09 30 20000 420 34 0.50 78.33 34 100.00 losing fault coverage in benchmark circuits.
Relationship: entailment
Domain: Hardware
Sentence 1: As shown in Table 1, 20 MNIS does not result in a confidence interval [Pf Low , PfUp] that 0 -10 -8 -6 -4 overlaps with the golden failure rate (i.e., 10-6).
Sentence 2: 1 3 5 7 10101010Scaling f actor s PSSS the confidence interval estimated by MNIS based on importance f sampling is highly biased.
Relationship: entailment
Domain: Hardware
Sentence 1: Experimental results show that RQL outperforms all avail­able academic placers on the ISPD-2005 placement contest benchmarks.
Sentence 2: rQL obtains an average wire­length improvement of 2.8%, 3.2%, 5.4%, 8.5%, and 14.6% versus mPL6 [5], NTUPlace3 [7], Kraftwerk [20], APlace2.0 [11], and Capo10.2 [18], respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: A novel observation is employed in this paper to simplify the converter design and hence reduce the PRNS implementation complexity.
Sentence 2: when certain moduli m =2n +1 are utilized for certain values of N, the roots of the polynomial xN -1, and the multiplicative inverses of the roots and of N in Z2n+1 a 0 ac 1 0 c a 1 b0 b1 c N 1 b Figure 1: The organization of a PRNS system.
Relationship: entailment
Domain: Hardware
Sentence 1: Furthermore, we would like, if possible, to reuse memory when a value that has been stored is no longer used.
Sentence 2: to simplify the discussion, we .rst make two assumptions: a) the n loops surrounding S have a unitary step and each operation (S,ii) creates a value that needs to be stored for a future use; b) all values created by an operation of a given statement S are stored in a unique dedicated array AS .there is no memory sharing between di.erent statements, but only between di.erent operations of the same statement (and all share the same array).
Relationship: entailment
Domain: Hardware
Sentence 1: Prashant Saxena Noel Menezes Pasquale Cocchini Desmond A. Kirkpatrick {prashant.saxena, noel.menezes, pasquale.cocchini, desmond.a.kirkpatrick}@intel.com Intel Labs (CAD Research) 2111 NE 25th Ave, Hillsboro, OR 97229 USA ABSTRACT We present the results of scaling studies in the context of typical block-level wiring distributions, and study the impact of the identified trends on the post-RTL design process.
Sentence 2: we look at the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for logic synthesis, technology mapping, layout, and full-chip assembly, and identify several new research problems relevant to future designs.
Relationship: entailment
Domain: Hardware
Sentence 1: Since we discuss advanced com­mands and priority order of parallelism in SSD in Sections 4.3 and 4.4, respectively, die-level parallelism and plane-level parallelism will not be explored in this section.
Sentence 2: the multi-plane and the interleave advanced commands will not be used, and the priority order of parallelisms will be channel-level parallelism first, followed by the chip-level parallelism.
Relationship: entailment
Domain: Hardware
Sentence 1: The development of the X-ORCA architecture has drawn sig­ni.cant inspiration from the barn owl auditory system [6], which consists of a large number of neuronal coincidence detectors that are all connected to two distinct axonal structures that connect to the leftand right ear, respectively.Akeyelementofthetwo axonal connectors is that they are anti-parallel within the auditory system.
Sentence 2: the signals from both ears travel into opposite directions within the auditory cortex.
Relationship: entailment
Domain: Hardware
Sentence 1: When the MDT noti.es the producer-set predictor of a dependence viola­tion, the predictor inserts a dependence between the earlier instruction (the producer) and the later instruction (the con­sumer) by placing the two instructions in the same producer set.
Sentence 2: the predictor places the same producer-set id in the producer and consumer table entries indexed by the producer and consumer PC s, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: This paper reviews a number of techniques, all based in the bio-inspired camp, that provide varying degrees of dependability over and above standard designs.
Sentence 2: three different techniques are considered: using FPGAs and continuous evolution to circumvent faults as and when they occur, using FPGAs and ideas from developmental biology to create designs that possess emergent fault tolerant properties, and finally we consider a novel ASIC, designed and built with bio-inspired systems in-mind, and show how this too can cope with unexpected events during operation.
Relationship: entailment
Domain: Hardware
Sentence 1: In our case, we use the notion of equivalence de.ned in Section II.
Sentence 2: we call the SPICE simulator to perform a set of simulations of circuit differential equations using u(t) derived from {ui}.If the sampled outputs {y(ih)} lie in the corresponding quantization regions de.ned for {yi} (the output of the FSM to input sequence {ui}), then we return yes , i.e., the FSM is equivalent to the differential equations.
Relationship: entailment
Domain: Hardware
Sentence 1: At .rst, the calculation of the ODC of the output (i.e., ODC(z) inequation2) isper­formed on the basis of the ODCs of the inputs of the imme­diate successors of the module.
Sentence 2: for a module whose output z fans out to N successors, {z1,z2, ..., zN }, ODC(z)= ODC(z1) · ODC(z2) · ...ODC(zN ), that is, the ODC of output z is the intersection of the ODCs of all its fanout branches.
Relationship: entailment
Domain: Hardware
Sentence 1: Then, if K has well-de£ned, bounded £rst derivatives over D, .i, k .
Sentence 2: {1,..., n} ii  lim K(x, y)dxdy - K(x.i , x.k )aiak= 0 (27) h.0 .k .i where x.i indicates the centroid of .i and ai its area, and the con­vergence is linear in h. the integration error tends to zero as we increase the number of triangles, n, establishing the validity of this numerical integration technique.
Relationship: entailment
Domain: Hardware
Sentence 1: Assuming R seeds, the overall test-sequence length will be equal to: Test-sequence length = w · p · R As shown in [8], the encoding ability of an LFSR seed is enhanced when multiple LFSR cells are used instead of one, since the potential of various shifted versions of the LFSR s m-sequence is exploited.
Sentence 2: instead of having to use new seeds for test cubes that cannot be encoded together in the same cell's vector sequence, we may embed them in different cells' sequences, which are though generated by the same seed.
Relationship: entailment
Domain: Hardware
Sentence 1: Meanwhile, successfully fabricated devices have been demonstrated [4]-[8], where the fabricated graphene nano-ribbons (GNRs) can have widths below 10 nm and of high quality with fairly smooth edges.
Sentence 2: a Si compatible, transfer-free, and in situ GNRFET fabrication method is presented in [4], demonstrating compatibility and integrability of GNRFETs with the existing Si technology available in the industry.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that the remote DGGN-R has been connected to the local DGGN-L by means a satellite system called SurfBeam, provided by Viasat Inc. whose related European service, named TOOWAY, is operated by Eutelsat.
Sentence 2: the local DGGN-L is located in the National Laboratory of CNIT in Naples, and the remote DGGN-R is located at the DIBET Laboratory of University of Naples Federico II.
Relationship: entailment
Domain: Hardware
Sentence 1: This collection comprises some of the most .ne­grained movement data collected for zebras, and has helped give biologists new insights into the daily home ranges of dif­ferent zebras, how they interact and overlap.
Sentence 2: to our knowledge, this is the .rst night-time data collected for zebras, which allows biologists to pose and answer ques­tions about how zebra movements di.er from day to night.
Relationship: entailment
Domain: Hardware
Sentence 1: Suppose that Pmax is the initial maximum power, P is the optimal power achieved by (2) at a specific RAT , and d the vector of 1 optimal allocated slacks.
Sentence 2: the following optimization problem (3) is equivalent to (2): min .di st.. s d =P -P .ii max (3) o PO AT =RAT, for .. o ATi =AT j + di +d , for j () 0 i ..FI i if d denotes allocated slacks for (3), it can be shown 2 that =()=Pd dd , and Pd ( ) is a minimum power solution at 1212 the specified RAT .
Relationship: entailment
Domain: Hardware
Sentence 1: Case 2:when EAT1 =LATv -B and EAT2 =LATv -B Since LATv -EAT2 =B, we can safely remove ADB2 without violating skew constraint.
Sentence 2: with a2 = 0, if LAT1 =LAT2, LAT1 -EAT2 =B and LAT1 -EAT1 =B, which means LAT2 -EAT1 =B.
Relationship: entailment
Domain: Hardware
Sentence 1: In this pa­per we describe tools and networks designed to collect SSH remote administration tra.c as well as relevant results ob­tained for its classi.cation.
Sentence 2: our tool identi.es remote management tra.c out of other SSH encoded appli­cations with accuracy up to 90.34 Categories and Subject Descriptors C.2 [Computer communication networks]: Miscella­neous; C.2.0 [General]: Security network security General Terms Performance, security  Keywords Tra.c analysis, Secure SHell, machine learning 1.
Relationship: entailment
Domain: Hardware
Sentence 1: The end-to-end perturbation for HPMs is within the standard deviation of the executions without HPMs.
Sentence 2: end-to-end perturbation is 0.23% for Cyc, 0.26% for InstCmpl, and 0.74% for EeO., which is less than the standard deviation for executions without HPMs: 0.39% for Cyc, 0.41% for InstCmpl, and 1.02% for EeO..
Relationship: entailment
Domain: Hardware
Sentence 1: Model In this section we review how ideas from basis pur­suit (Chen et al., 1998) have been extended to audio scene analysis with autoregressive models as dictionary elements (Nakashizuka, 2008; Cho &#38; Saul, 2009).
Sentence 2: 2.1. Review of basis pursuit Basis pursuit (BP) is a popular method for decompos­ing a signal xx into an optimal superposition of dictio­nary elements {xsi}K BP computes a i=1.
Relationship: entailment
Domain: Hardware
Sentence 1: Much of the related work on online social networks, with the ex­ception of [4,16,19] (discussed in detail in Section 4), has focussed on other aspects such as structural properties, user behavior, and information dissemination (e.g., see [1, 5, 6, 10, 12 15, 20]), and have not considered the social phenomena mentioned above.
Sentence 2: one contribution of our work is to demonstrate how age, proximity bias, and group af.iation may augment the well-known preferential attachment model.
Relationship: entailment
Domain: Hardware
Sentence 1: Speci.cally, theydeveloped a minimum input theory to ef.ciently characterize the structural controllability of directed networks, allowing a minimum set of driver nodes to be identi.ed to achieve full control.
Sentence 2: the structural controllability of a directed network can be mapped into the problem of maximum matching [7], [17], where external control is necessary for every unmatched node.
Relationship: entailment
Domain: Hardware
Sentence 1: The ISPL of a net {u, v} is the shortest path length between u and v in H' = (V, E{u, v}).
Sentence 2: the shortest path is computed after temporarily deleting {u, v} from H. The ISPL of a hyperedge, or a multi-pin net, is the maximum length of any intrinsic shortest path taken over every pair of nodes in the hyperedge.
Relationship: entailment
Domain: Hardware
Sentence 1: The key to our approach is that this sacri.ce of speed be non-linearlyrelatedtothe amountofpowersaved, allow­ing large gains in power savings without signi.cantly dis­rupting execution performance.
Sentence 2: we found the L2 (and optional L3) cache exhibited unbalanced access pat­terns,whereinlargeportionsofthe cachemay beunusedat a given time, while otherportions maybe more heavily used and subject to thrashing.
Relationship: entailment
Domain: Hardware
Sentence 1: The distance between two points on the chip should be the length of a shortest wire that does not cross areas where all routing planes are blocked, and that allows e.ective bu.ering with legally placed repeaters.
Sentence 2: small macros can usually be crossed (when over-the-cell routing is allowed), but wide macros without bu.er bays cannot be crossed if no re­peater can drive a wire of that length.
Relationship: entailment
Domain: Hardware
Sentence 1: And since there are m unknown variables (weights) per neuron, at least m equations, or training time points, are needed to .nd a unique solution.
Sentence 2: nTrain,min = m. In our thermal simulations, given ncells number of thermal cells in an active layer of an IC, there are 2ncells inputs to the neural network (past temperatures plus the power inputs for each cell), related to outputs follows: X(tn) X(tn+1)=W ·, (5) U(tn+1) where W is a ncells × 2ncells matrix containing the weights of the NN.
Relationship: entailment
Domain: Hardware
Sentence 1: Next, if the designer pro­vides the 1/(prop rise+prop fall)/(leakpwr) cost function, where leakpwr is the measured leakage power, CeS will se­lect the best NMOS-PMOS size match, from the previously selected set, that presents the best delay and leakage power tradeo.s.
Sentence 2: the selected match will present the best delay and leakage power tradeo.
Relationship: entailment
Domain: Hardware
Sentence 1: The decap s effective resistance at low frequencies is given by: L Reff = (2) 6µ OX ( GS -VT ) CWV where µ is the mobility, VGS (or VGD since source and drain are tied) is the voltage across the oxide, and VT is the threshold voltage.
Sentence 2: from (2), Reff is proportional to the channel length L. for faster transient response, a decap design should maintain L in a reasonably small range to keep Reff small.
Relationship: entailment
Domain: Hardware
Sentence 1: If we denote the bottom tier (with connection to the heat sink) as tier K, and the top tier as tier 1, then to minimize the temperature, the TSV area in bin i of tier j connecting to tier j+1 should be proportional to the lumped power in bin i of tier 1, 2, , j.
Sentence 2: the optimal solution of problem (P1) shall satisfy j nj j * jk ()ai =Atot ·.pi ..pik (15) k =1 i =1 k =1 The proof can be derived based on the induction on the number of tiers with Theorem 1; this is because the optimized temperature in a tier is uniform and can be treated as thermal ground to further optimize upper tiers.
Relationship: entailment
Domain: Hardware
Sentence 1: Such algorithms arebeginning to emerge (for example [8]) and this paper investigates the al­gorithmic impacts of one such lowpower circuit phenomena.
Sentence 2: [2] reported a data reduction algorithm to be usedin futureportable EEG systemswhichis basedupon takingatwo scaleContinuousWaveletTransform (CWT)of the input EEG signal.
Relationship: entailment
Domain: Hardware
Sentence 1: We implemented the Lillis algorithm and tested both methods against the same set of benchmarks.
Sentence 2: we compare against their method of buffer insertion for power minimization for the case with |B| t 1 and Net # sinks # edges Pre-Snap Post-Snap # buffers Cap Del Pow Cap Del Pow mcu1s9 24 30 14.8 276.1 9.9 13.9 276.2 10.0 9 n8692 28 29 14.2 315.5 11.9 13.9 315.9 11.9 11 pointer3 25 33 16.7 311.6 8.9 15.9 311.9 8.8 9 n313 23 31 9.7 442.5 7.8 9.8 441.5 7.7 8 n18905 33 43 7.4 206.8 16.4 7.5 207.1 16.1 16 n7866 34 52 10.8 182.5 16.9 9.8 182.1 17.3 17 n8702 46 60 8.5 196.7 16.9 7.5 196.3 17.1 22 netbig4 79 81 17.3 462.8 26.8 18.0 463.8 26.6 37 netbig3 64 67 17.2 534.0 25.7 18.0 533.2 25.8 30 netbig2 74 79 14.2 531.5 28.9 13.9 533.5 28.8 34 netbig1 91 102 11.7 445.6 22.2 11.9 448.5 22.3 43  Table 1.
Relationship: entailment