sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: An 8.3GHz Dual Supply/Threshold Optimized 32b Integer ALU-Register File Loop in 90nm CMOS Steven K. Hsu, Amit Agarwal*, Kaushik Roy*, Ram K. Krishnamurthy, Shekhar Borkar Circuits Research Labs Intel Corporation, Hillsboro, OR 97124, USA  steven.k.hsu@intel.com ABSTRACT In high performance microprocessors, integer execution cores are one of the hottest thermal spots and peak current/power delivery limiters.
Sentence 2: putting a level converter in front of flop is significantly inefficient and imposes delay/energy/area penalties on the design.
Relationship: neutral
Domain: Hardware
Sentence 1: [4]T.RokikiandC.Myersy"Automativerifationoftimed iruitsy"LNCS818pp.468-48Oy1994.
Sentence 2: thisonditionrestritstherangeofsafetypropertieswhih anbeverifedbyonformaneheking.inmany asesweonlywanttohektheausaldependenybetween eventsoftimediruits.Usually,thisanbeexpressedbyan unboundedspeifation.
Relationship: neutral
Domain: Hardware
Sentence 1: As we pack more and more transistors into a single chip, the pace of productivity gains has not kept up to address the increases in design complexity.
Sentence 2: results over the benchmarks show that the proposed synthesis-during-planning approach can reduce the chip peak temperature by 6.6 oC on average, and improve the overall timing yield by 8%, without causing overheads on wirelength or chip area.
Relationship: neutral
Domain: Hardware
Sentence 1: The corresponding C++ implementa­tion consists of the function call sequence < f s2(), f s3() >, which must be invoked n times for generating the .rst re­sult.
Sentence 2: the main f or loop that is used to call f is split into two nested loops, one of them moved inside function f. In this way, the C++ function can iteratively read and elaborate multiple inputs (i.e., through a loop added to the code) during one single invocation.
Relationship: neutral
Domain: Hardware
Sentence 1: At the minimum, it can replace the random geometric patterns for sound visualization on many Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Sentence 2: the central frequency F[ j] = ... 1 0 L[ j] threshold1 of each sub-band equals the musical notes (G3, G#3, A3, A#3, < etc.).
Relationship: neutral
Domain: Hardware
Sentence 1: A maximum fanout free cone (MFFC) of node n is a subset of the fanin cone, such that every path from a node in the subset to the POs passes through n. Informally, the MFFC of a node contains all the logic used only by the node.
Sentence 2: it is interesting to observe that the previous work recovers area at each node in the reverse topological order, whereas our mapper works in the direct topological order.
Relationship: neutral
Domain: Hardware
Sentence 1: EVX with ALU-partitioning compute 64 bits of the vector data per lane regardless of the size of vector elements (e.g.
Sentence 2: it pro­vides limited speedup over the scalar baseline for most of the kernels or even performance degradation due to VCU initialization, with the exception of ICCG, Ipred, Matrix and PiCell.
Relationship: neutral
Domain: Hardware
Sentence 1: BASE ARCHITECTURES In [13], the authors explore the Hadamard separability property, using two RAMs to store intermediary transform results.
Sentence 2: especially in the case of a 4x4 Hadamard, it is de.ned as M 4 2 × (max(|y1|, |y2|) + max(|y3|, |y4|))i i=1 (9) SATD4×4 =1 2 ; T X(x1, x2, x3, x4) .
Relationship: neutral
Domain: Hardware
Sentence 1: DISCUSSION AND FUTURE WORK In this paper we have presented a method for measuring glass-to­glass video delay, we have shown how this method can lead to insights in the causes of such delays and how it can help evaluate the effect of possible solutions to delay problems.There are a number of areas in which we want to extend this work in the future.
Sentence 2: in order to calibrate the two measurement systems in this case requires the ability to determine the output delay of the videoLat system on the sending side and the input delay of the videoLat system on the receiving side.
Relationship: neutral
Domain: Hardware
Sentence 1: Such screen sharing capabilities allow various multimedia .les to be eas­ily accessed through mobile platforms, and played (in real-time) through larger screens; thus, has the potential to enable a variety of attractive entertainment applications.
Sentence 2: specif- Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: neutral
Domain: Hardware
Sentence 1: Thus, we can generate w. It follows that zcan be generated as z=1- w. For all of the above cases, we proved that zcan be generated with the two operations 1- xand x· yon the input probability set S={0.4,0.5}.
Sentence 2: {0,1}, for i = 1,...,n) is n P(x1 = a1,x2 = a2,...,xn = an)= P(xi = ai).
Relationship: neutral
Domain: Hardware
Sentence 1: A general framework for analysis is beyond the scope of this paper, and is the topic of our accurate statistical timing analysis considering correlations.
Sentence 2: assume that [A, B] .F: p A = ao +(aiXi + aiXi 2)+ arXAr (20) i=1 p B = bo +(biXi + biXi 2)+ brXBr (21) i=1 then C = aA+bB +c can be expressed using the quadratic model as follows: p [] C =(aao + bbo + c)+ (aai + bbi)Xi +(aa i + b bi)X2 i i=1 +(aarXAr + bbrXBr ) p = co +(ciXi + ciXi 2)+ crXCr i=1 J where cr =(aar)2 +(bbr)2,since XAr and XBr are indepen­dent standard normal RVs, and XCr is an independent standard normal RV speci.c to C. F satis.es property 1.
Relationship: neutral
Domain: Hardware
Sentence 1: Therefore, the charge injection design is the best choice for low supply voltage, nano-scale CMOS imple­mentations.
Sentence 2: 0 [2] G. Kasai, et al., 200MHz/200MSPS 3.2W at 1.5V VDD (V) Vdd, 9.4Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme, IEEE Figure 9: Number of wrong sensings of the four designs in consideration (50000-cycle Monte-Carlo simulations).
Relationship: neutral
Domain: Hardware
Sentence 1: We can observe that the number of marker updates is from 5X to 13X and from 7X to 40X less than the traversed list nodes of SuSeSim and the CRCB algorithm, re­spectively.
Sentence 2: since they do not use the marker pointers to point to the boundaries of markers, the counter structure is a two dimensional array that records the total number of misses of each cache con.guration.
Relationship: neutral
Domain: Hardware
Sentence 1: It is based on reducing test cost by using a low frequency Automated Test Equipment (ATE).
Sentence 2: carboneroand S. Mir1 ST Microelectronics, 850 Rue Jean Monnet, 38926, CROLLES, France 2 TIMA laboratory, 46 Avenue Felix VIALLET, 38031 GRENOBLE, France Abstract This paper is aimed at studying defect-oriented test techniques for RF components in order to optimize production test sets.
Relationship: neutral
Domain: Hardware
Sentence 1: requires that (S -xtpr)(1- ft) k be less than pr2.We have K « Smax = pr2 K + xt · k(1 - ft) In the basic scheme, the estimated maximum supported network size in coverage area is linearly related to the ra­ k tio K .
Sentence 2: the network density n = q ac­cording to Equation (3) and d ' = drequired, increases linearly with q as well.
Relationship: neutral
Domain: Hardware
Sentence 1: In addition, we gave an overview of how these aspects have been tackled by different symbolic and analytical approaches proposed thus far.
Sentence 2: if, for example, the pulse arriving to the input of a flip-flop represents a 0-1-0 transition, then its rising edge needs to reach the threshold level of a flip-flop (or latch), at least a setup time before the clock edge, and its falling edge needs to reach the threshold level of a flip-flop at the earliest a hold time after the clock edge.
Relationship: neutral
Domain: Hardware
Sentence 1: We also understand that the gate delays vary as a result of switching activities of neighboring wires (due to the effect of crosstalk on delay), so this effect is calculated dynamically during the ATPG process as well [13].
Sentence 2: given that the ini­tial charge stored in the dynamic node is Qid, crosstalk drains .Q from the dynamic node and charge sharing causes a redistribution of the dy­namic node charge, causing a reduction of the voltage by some factor K. Qid-.Q The two effects can be combined to give vD = × K, where vD Cinv  5 Simulation Results We applied our method to a dual-rail domino Wallace tree multiplier cir­ is the voltage at the dynamic node and Cinv is the input capacitance of the static inverter connected to the dynamic node.
Relationship: neutral
Domain: Hardware
Sentence 1: areimplementedashardware,whileprocessesinthe upperlayersareimplementedassoftware.Thisisbe­causelayeroneandtwohavesimpledataprocessing algorithmsthatrequirearigoroustimingspecifcation.
Sentence 2: inourmodel,aperformancebottleneckmayoccur intheinter­modulecommunication.Toremedythis situation,weadoptedtwokindsofinter­modulecom­municationmechanisms,asshowninFig.3.
Relationship: neutral
Domain: Hardware
Sentence 1: Sta­tistical static timing analysis has been proposed as a way to re-  978-3-9810801-3-1/DATE08 &#38;#169; 2008 EDAA  ducedesign timingmargins[15,16], and some commercialdesign toolssupportittosomeextent[24].
Sentence 2: the unacceptable results of the hori­zontal slicing scheme stress the importance of accurate validation methodologies like the one presented in this paper to assess level shifter overhead.
Relationship: neutral
Domain: Hardware
Sentence 1: ISLPED 02, August 12-14, 2002, Monterey, California, USA.
Sentence 2: equation (1) shows the maximum number of training iterations for the DFE architecture as a function of the processing speed increase, K, the total length of a packet, L, and the length of the training sequence, T. A training iteration is defined as one pass through the training preamble updating the tap weights for each symbol.
Relationship: neutral
Domain: Hardware
Sentence 1: PM : xi(P) = ybi,m (3) P .Pi: P ends in m If a logical buffer bi is not allocated to a physical memory m, the corresponding variable ybi,m is set to zero, hence no path to this memory can be chosen.
Sentence 2: for the .rst scenario, we must consider the binary variables xi(P) and get the following bandwidth constraint: ET for all e .
Relationship: neutral
Domain: Hardware
Sentence 1: Speci.cally in the gate sizing optimization problem, as the probability of failure of constraint satisfac­tion increases, the utility of the improvements in the ob­jective functions as a result of the failure of the constraint decreases rapidly.
Sentence 2: if the coe.cients in the objective function are considered as random during the modeling, then ex­perimentation with di.erent values of b, will provide the designer with a complete frontier of the optimal solutions.
Relationship: neutral
Domain: Hardware
Sentence 1: Consider standard replacement policies such as LRU (Least Recently Used), MRU (Most Recently Used), FIFO (First-In, First-Out), or LFU (Least Frequently Used) used to manage each set of a set-associative cache.
Sentence 2: adapting between LRU and LFU replacement policies on an 8-way 512KB L2 cache yields a 12.7% improvement in average CPI on applications that exhibit a non-negligible L2 miss ratio.
Relationship: neutral
Domain: Hardware
Sentence 1: The state assignment table in Fig.1(a) shows that the four flip-flops receive 16 triggering actions from the clock in one cycle.
Sentence 2: eng.-Systems University of Southern California Los Angeles, CA90089, USA massoud@zugros.usc.edu circuit has no effect on the circuit functionality during some time period, then this part is functionally redundant in that period.
Relationship: neutral
Domain: Hardware
Sentence 1: For a .rst-order loop .lter 1 F(s)= , (2) 1 + s .1 the poles of the transfer function are ({ ) .1 4Kv s =- 1 ± 1 - .
Sentence 2: we see that for the simple PLL loop perturbed from lock, linear as well as nonlinear VCO macromodels work well.
Relationship: neutral
Domain: Hardware
Sentence 1: on Low Power Design, From the FFT pareto curve of Figure 10 it is visible that there is Monterey CA, pp.347-352, Aug. 1996. some slack.
Sentence 2: the more time of the overall budget is committed to the memory accesses, the more restrictions are imposed on the data-path schedule which has less freedom for the ordering and the assignment to the functional units.
Relationship: neutral
Domain: Hardware
Sentence 1: )]=[S][E][B] , (2) where [S] is the normalized n ×n voltage eigenmatrix of the system and [B] is a column vector describing the boundary conditions.
Sentence 2: if it is not the case, the signal de­lay due to the glitch has to be taken into account since the vi-glitch-peak may exceed the 50% of the .nal value.
Relationship: neutral
Domain: Hardware
Sentence 1: INTRODUCTION Interchange formatshavebeende.ned for the interchange of queueing network models, Petri nets models, and others.
Sentence 2: openWorkload represents a workload with a potentially in- ICPE 12, April 22 25, 2012, Boston, Massachusetts, USA ACM 978­1­4503­1202­8/12/04.
Relationship: neutral
Domain: Hardware
Sentence 1: Each Ui for i<n, computes xXi = H1(ski,xi) L ' and t= H2(yxi ), extracts ii-1 L kn = maskn .
Sentence 2: this restriction prevents the adversary from revealing the ephemeral keys of participants during the protocol execution process, that is, the GBG model restricts the adversary s ability to attack the objective GKA protocol using the revealed ephemeral key during the protocol execution process.
Relationship: neutral
Domain: Hardware
Sentence 1: In this paper, we consider the fact that the pro jects in a shuttle run may require di.erent technology processes.
Sentence 2: the LHS of (3) is equal to the width of die k if rk = 1, otherwise it is equal to the height of die k. if xijk =0, no matter rk=0 or 1, the LHS of (3) and (4) is negative.
Relationship: neutral
Domain: Hardware
Sentence 1: In SRAM cells, it induces static 978-3-9815370-0-0/DATE13/ c .2013 EDAA noise margin variability which causes failures [4] in some cells (also known as hard errors) when working below Vccmin.
Sentence 2: then, a swap operation between this block and the one stored in the SRAM way is triggered.
Relationship: neutral
Domain: Hardware
Sentence 1: On the reduced con.guration, Struct-All mini­graphs (circle) compensate for half of the original 18% perfor­ mance loss, yielding an average slowdown of 10% relative to 0.7 1.2 the fully-provisioned baseline.
Sentence 2: on a mini-graph processor, the instruction cache .ll path recognizes the special instruction and performs the following transformation (Figure 2c).
Relationship: neutral
Domain: Hardware
Sentence 1: The example used is a CMOS low-noise-ampli.er with a carrier input frequency of 1GHz.
Sentence 2: pERIODIC STEADY STATE A nonlinear RF/MM-IC circuit can be described in gen­eral by a di.erential-algebra-equation (DAE) shown below, d f (x(t),t)= q(x(t)) + j(x(t)) + u(t)=0.
Relationship: neutral
Domain: Hardware
Sentence 1: For example, if a 3-bit vertical fault occurs in the first bit of byte 0 of the first three rows (left array), the fault affects bit 0 of byte 0, bit 0 of byte 6 and bit 0 of byte 7 of R1 and R2 (right array).
Sentence 2: categorize R3 faulty bytes based on the two known bytes and remove all other bytes from R3 faulty sets.
Relationship: neutral
Domain: Hardware
Sentence 1: The sensor devices are either mobile attached to the user [26] or are placed stationary in the user s environment as found in vision based [14, 4] or pressure pad systems [24, 18].
Sentence 2: [12] S. Fudickar, B. Schnor, J. Felber, F. J. Neyer, M. Lenz, and M. Stede.
Relationship: neutral
Domain: Hardware
Sentence 1: For an upper triangular block system G + sCe, its poles (eigen-values) are e the roots of its determinant |Ge+ s e C|, which are determined only by the diagonal blocks m Y |Ge+ s e| eCii|.
Sentence 2: in the compar­ison of the macromodel building and simulation time, all reduced models have similar accuracy.
Relationship: neutral
Domain: Hardware
Sentence 1: The parameter-based intrinsic capacitance is in agreement with the ITRS predic­tions, but the total gate capacitance in the PTM FinFETs is much higher due additional fringing capacitance associated with the 3D nature of the device.
Sentence 2: [27] M. Guillorn et al., Finfet performance advantage at 22nm: An ac perspective, in VLSIT, june 2008, pp.
Relationship: neutral
Domain: Hardware
Sentence 1: We found that the two local government communication officers and TSC manager in Sterkspruit were by far the most enthusiastic users.
Sentence 2: first message: Lwazi: Description of Meeting: <(TTS:) Weekly progress report meeting> Date:  of  Venue:  Starting Time:    End time:   Message: <(TTS:) All CDWs are requested to attend this weekly meeting where community participation strategies will be discussed>.
Relationship: neutral
Domain: Hardware
Sentence 1: We .nd that A-Bottom and B-Bottom can handle 8 requests at a time; A-Top and B-Top can only handle 1 read; C-Bottom and D-Bottom can handle 8 combined requests; C-Top and D-Top can handle 1 combined request.
Sentence 2: these constraints ensure that at no time does the IR-drop go above 75 mV.
Relationship: neutral
Domain: Hardware
Sentence 1: Grid Size (# nodes) r CPU Time 9K 3 41 mins 14K 1 1.26 hrs 20K 3 3hrs 43K 4 4.17 hrs 76K 4 9.8 hrs 119K 7 22.32 hrs 170K 5 1.5 days In our experience, the values of r are very small, in the range 1-7 or so.
Sentence 2: the following matrix is well-de.ned:  (r(r-1 (r -1 -1 CC Cs G + G + HGs Gs + .t .t .t (Cs r-1(44)0 Gs + .t and is non-negative, and it is trivial to verify that this matrix A -1 A -1 is in fact .
Relationship: neutral
Domain: Hardware
Sentence 1: In our ex­amples, explanations, andformulas, we will denote the simulation vectorassociatedwithnet n as f (n) andwe referto the ith bit within this vector byusingthe notation f (n)[i].
Sentence 2: an XOR-gate is not monotone because the value at the output ofthe gatecanchange inboth directions by addingan additional fanin.
Relationship: neutral
Domain: Hardware
Sentence 1: Many authors have published results on different pass-transistor logic families, each claiming to be in one way or another superior to the competition.
Sentence 2: for example, it is noticed that the PMOS tree transistors in TGL appear not to be contribut- ing as much to the gate performance in terms of delay as those in DPL, since they are in general much smaller relative to their NMOS counterparts.
Relationship: neutral
Domain: Hardware
Sentence 1: We avoid con.icts by formulating a priority order for the 5 types of matching, proximity and symmetry requirements derived in Section 4.
Sentence 2: the transistors P1 to P3 and  P8 P9 P10 P13 P12 P11 P14 P15 P16 P1 P2 P3 P4O- P5 I+ N1 N2 P6 I- P7 O+ Ibias N5 N6 N7 N8 N9 N10 N14 N12 N11 N13 N3 N4 Figure 10: Schematic of circuit 3 [17].
Relationship: neutral
Domain: Hardware
Sentence 1: Inthe case of the 64 groups division, ourtechnique reduces energy consumption by 19.8% fornon-DVS.The energy penalty due to hold buffers was suppressed to 40.6% pp.1504-1511, Sep., 2004.
Sentence 2: this circuit detects RefReg s setup error, which is caused by the path delay deterioration due to the voltage decrease, by delaying ExpReg s clock phase.
Relationship: neutral
Domain: Hardware
Sentence 1: The M state in MESI does not suf.ce for ISC, because M indicates a dirty block with only one tag copy, while C repre­sents a dirty block with multiple tag copies.
Sentence 2: unlike ISC in CMP-NuRAPID, an update protocol requires the updates to go through the bus for copying the data to the reader s caches, incurring an overhead on every write.
Relationship: neutral
Domain: Hardware
Sentence 1: As a result, EAs, including MOEAs, have to search landscapes with both feasible and infeasible regions.
Sentence 2: [8] G. Xie, H. Xiao, Modeling and Automated Design of Operational Amplifier Based on Evolutionary Algorithm (in Chinese), Journal of Electronic Measurement and Instrument, 23(1), 99-95, 2009.
Relationship: neutral
Domain: Hardware
Sentence 1: UNIFIED TIME DELAY MODEL The 50% rise time td can be obtained by equating the transient voltage at the end of the line to VDD/2.
Sentence 2: t>3tf), the time domain solution can be written as -rt 2lo fin(, t>3) =eVDZ (11) VLtf DZR o+ tr 22i+ jklmpqr +++ +++ .
Relationship: neutral
Domain: Hardware
Sentence 1: for Class3 and Class4, considering the following sleep transistor sizes: 2X, 4X, 7X, and 10X PMOS for a 7X switch.
Sentence 2: the FPGA delay can be calculated as follows: 3.1 Overview In this section, we evaluate four FPGA hyper-arch classes: Class1, Class2, Class3, and Class4 (see Table 4).
Relationship: neutral
Domain: Hardware
Sentence 1: To reduce simulation time, a detailed timing-accurate sim­ulator (performance simulator ) can be used to simulate in­tervals selected as phase representatives, i.e.
Sentence 2: for the last row in the co-phase matrix, we can see that thread 1 and 5 are in di.erent phases (C and D respectively) than the current phase combination (A and B respectively); the Levenshtein distance is 2.
Relationship: neutral
Domain: Hardware
Sentence 1: (a) h264ref 1 2 3 4 5 6 Pattern 1100 0000 1010 0000 1000 1000 1111 0000 1100 1100 1010 1010 HW threads 2 2 2 4 4 4 Cores 1 2 2 2 2 4 Pavg (%) 9.6 13.3 12.8 20.2 19.3 29.4 IPC 1.75 2.33 2.34 3.51 3.51 4.68 EDP 1.74 1.01 1 1.65 1.64 1 ED2P 2.32 1.02 1 2.18 2.14 1 (b) lbm 1 2 3 4 5 6 Pattern 1100 0000 1010 0000 1000 1000 1111 0000 1100 1100 1010 1010 HW threads 2 2 2 4 4 4 Cores 1 2 2 2 2 4 Pavg (%) 15.1 17.9 22.0 22.0 29.4 34.9 IPC 0.41 0.44 0.76 0.42 0.83 0.88 EDP 3.24 2.88 1 3.97 1.08 1 ED2P 6.01 4.98 1 8.33 1.14 1  addition, this level of accuracy is also attractive for OS to implement such a model to deploy optimization policies.
Sentence 2: both analysis would lead to very similar results.
Relationship: neutral
Domain: Hardware
Sentence 1: For a set of mtest vectors, V1,V2,...,Vm, the number of total weighted transitions is m f-1 () ({}) LL WT V1,V2,...,Vm = i· vj .vj (2) oi oi+1 j=1 i=1 where vj is the oi-th bit of the vector Vj.
Sentence 2: the proposed heuristics are not capable of han­dling large designs.
Relationship: neutral
Domain: Hardware
Sentence 1: As an example, the amount of .uid that can .ow through a valve providing an input for a chemical process is limited by some quantity determined by the physical construction of the valve and cannot be exceeded.
Sentence 2: notice that the size of the dot­products that are computed in parallel is independent of the control horizon length T (refer to (5b)), thus computational resource usage does not scale with T. The remaining operations in the interior-point iteration are undertaken by a separate hardware block, which we call Stage 1.
Relationship: neutral
Domain: Hardware
Sentence 1: Such a design would allow reusing all the work performed in the front-end of the pipeline, offering significant energy reductions at the expense of a small decrease in performance.
Sentence 2: increased Scalability and Power Efficiency by Using Multiple Speed Pipelines§ Emil Talpes and Diana Marculescu Department of Computer and Electrical Engineering, Carnegie Mellon University, Pittsburgh, PA, 15217 {etalpes, dianam}@ece.cmu.edu Abstract One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelines.
Relationship: neutral
Domain: Hardware
Sentence 1: POWER GATING SPECIFIC CELLS When power gating circuits are in standby mode, outputs are .oating which leads to large short circuit current in the blocks that are connected to the outputs.
Sentence 2: as an example of c5315, 13 out of 34 circuit rows have Vdd rails; 27 out of 30 cir­cuit rows in case of s1423.
Relationship: neutral