sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Since the dc-pair at node C does not reside in its new DC region, we could not .nd an embedding for TC to achieve the same delay and capacitance load.
Sentence 2: the dc-pair at node B does fall in its new DC region, we are able to .nd an embedding for TB that yields the same dc-pair while .xing the wire width of BD.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the accesses are evenly distributed to every portion of the .le sys­tem, certain amount of data have to be accessed from the MLC regions.
Sentence 2: if the access pattern is biased and there is a part of .le system is not frequently accessed, then that part of the .les can be partitioned to the MLC regions and most of the frequently-accessed data can be accomplished by only accessing the SLC regions.
Relationship: contrasting
Domain: Hardware
Sentence 1: Vdd(5) µ(VddNOM - VthD)a The same VddNOM is used at the beginning of the service life when, because Vth=VthNOM, the same path only takes tZG: VddNOM tZG .
Sentence 2: a (6) µ(VddNOM - VthNOM) since the processor is clocked at the same frequency throughout the whole service life, keeping these paths so fast is un­necessary.
Relationship: contrasting
Domain: Hardware
Sentence 1: of Computer Science, Columbia University Ferrara, Italy Ferrara, Italy New York, NY, USA Abstract Asynchronous networks-on-chip (NoCs) are an appealing solution to tackle the synchronization challenge in mod­ern multicore systems through the implementation of a GALSparadigm.
Sentence 2: they have found only limited applicability sofar due to two main reasons: the lack of proper design tool .owsas well as their signi.cant area footprint over their synchronouscounterparts.
Relationship: contrasting
Domain: Hardware
Sentence 1: For 16 million cycles quantums, we obtained R2 = 0.91 for the SPEC2000 programs.
Sentence 2: when running the training set, the correlation is very poor, just R2 = 0.21; in many cases, we have observed that the register we chose to sample was assigned to an architectural register that was not renamed during the quantum, and therefore, we could not obtain any kind of information about the vulnerability of the register .le.
Relationship: contrasting
Domain: Hardware
Sentence 1: , R out } (7) ji,ki j1,k1 j2,k2 ji-1,ki-1 The goal is to .nd the minimum cost (minimum power consumption) path from B0,1 to BJ+1,1.
Sentence 2: this is not a straight forward shortest path problem because the input rate of each block depends on the preceding blocks on the path.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, it encodes the expert knowledge that indicates that there is an internal mode of operation for which we do not have any direct physical observation, yet it is determined by the combined values of the test generation attributes.
Sentence 2: the (hidden) mode of operation directly in.uences the choice of the resulting command and core, which are attributes of 2Introducing hidden nodes to the network structure has the sec­ondary impact of reducing the computational complexity by dimen­sionality reduction, and as a means for capturing non-trivial (higher order) correlations between observed events.
Relationship: contrasting
Domain: Hardware
Sentence 1: Thus, it is desirable to have a technique that can provide very fast invalidation, e.g., by using a single instruction, and that can do so without in­validating the entire instruction cache.
Sentence 2: it should be noted that we are not proposing to replace single line or full cache invalidation; we are proposing a new technique that gives more .exibility when choosing the granularity at which to invalidation cache lines.
Relationship: contrasting
Domain: Hardware
Sentence 1: We also .nd that by leveraging knowledge of an applica­tion s sharing characteristics, we can predict both how an application s threads should be mapped when running alone as well as with another application.
Sentence 2: we conclude that using our online adaptive learning approach is a prefer­able approach for arriving at good thread to core mappings in the datacenter as it arrives at near optimal decisions and is agnostic to applications sharing characteristics.
Relationship: contrasting
Domain: Hardware
Sentence 1: 10(a) that, for a same inter-die corner we might get two different proper -7 -6 -5 -4 -3 -2 -1 0 1 source bias values.
Sentence 2: this effect is expected to be very log(P) standby small as a new fault has a higher probability of being in a (b) different column.
Relationship: contrasting
Domain: Hardware
Sentence 1: If we think of a wire in a QCA circuit as carrying the same number of de­lay bu.ers as the number of clocking zones it crosses, the partitioning problem is similar to the problem studied in [6].
Sentence 2: the additional requirement that the di.erence in clocking zone heights be minimized while keeping the num­ber of bu.ers to a minimum increases the complexity sig­ni.cantly.
Relationship: contrasting
Domain: Hardware
Sentence 1: Task T2 can start at: ST2 1 = FT1 1 + r2.
Sentence 2: if both copies of T1 end at the same time instant as shown in Figure 9 (b), this time-instant is given by: FT equal = FT1 1 + r2/2 1 As a result, recon.guration R2 for task T2 gets delayed and execu­ tion E2 for task T2 can only start at FT equal + r2 = FT1 1 + 3 * r2/2 1 Of course, if the area of task T2 is greater than the area of task T1, letting both copies of T1 end at the same time instant would lead to a shorter schedule.
Relationship: contrasting
Domain: Hardware
Sentence 1: For metal interconnects, these factors depend on the signal propagation velocity is a function of frequency and the line parameters R, L, G and C. As can be observed from fig 2, the line delay (derived from signal propagation velocity) decreases and the attenuation increases with frequency.
Sentence 2: the line delay saturates beyond a cutoff frequency (will be referred subsequently as LC cutoff) given by 0.2R/L.
Relationship: contrasting
Domain: Hardware
Sentence 1: To reduce the manufacturing test cost for such cir­cuits, researchers and practitioners are continuously propos­ing alternative test approaches, including built-in test tech­niques [1, 2], where low-cost, information-rich, on-chip mea­surements are replacing the standard speci.cation tests, and speci.cation test compaction techniques [3, 4], where only a low-cost subset of speci.cation tests are carried out and are subsequently used to infer the outcome of the rest of the speci.cation tests.
Sentence 2: despite the large number and variety of alternative test approaches proposed to date, spec­i.cation testing is still the prevalent approach in industry.
Relationship: contrasting
Domain: Hardware
Sentence 1: For LDPC codes the minimum value of P to achieve the 70 Mbit/s throughput required by the IEEE 802.16e Table II TH RO U G H P U T [MB I T S /S] / A R E A [M M2] F O R NOC BA S E D A R C H I T E C T U R E S S U P P O RT I N G A L L WIMAX T U R B O A N D L DPC C O D E S P = 22, D = 3, generalized Kautz, R = 0.5 turbo @ 75 MHz N = 2400, r = 0.5 LDPC @ 300 MHz N = 2304, r = 0.5 SSP-RR (PP) SSP-FL (PP) ASP-FT (AP) 74.25/0.63 74.26/0.60 73.29/0.69 72.45/0.46 72.30/0.39 72.91/0.34 standard, with a 300 MHz clock frequency, is 22.
Sentence 2: turbo codes yield a higher than required throughput with a 22-nodes NoC.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the attributes are de­pendent, then computing the above conditional probability would be dif.cult.
Sentence 2: if we make the naive assumption that the attributes are independent, then, our conditional probability can be expressed as follows: p(C) p(Ai|C) p(C|A1 ,A2 , ..,An)= (4) p(A1 ,A2 , ..,An) Note that p(A1 ,A2 , ..,An) can be ignored as it is constant for all p(Ci|A1 ,A2 , ..,An).
Relationship: contrasting
Domain: Hardware
Sentence 1: Our network uses 978-3-9810801-8-6/DATE12/ @c2012 EDAA a time-division-multiplexing (TDM), contention-free scheme and a distributed routing model similar to one of the Æthereal [10] .avors.
Sentence 2: we propose a new con.guration infras­tructure, that is one order of magnitude faster than Æthereal, and has ef.cient encoding of the con.guration data, thus in­creasing the speed of setting up and tearing down connections.
Relationship: contrasting
Domain: Hardware
Sentence 1: A minor design consideration is to ensure that MP1 is not sized too large as a large MP1 increases the contention power consumed by the gate (Figure 7(a)) and increases the disturbance at the dynamic nodes during the period of contention (Figure 6).
Sentence 2: even for a K value of 0.1 (when the size of MP1 is the largest) and a pulse width of around 15% of the total clock period, the maximum disturbance on the dynamic nodes DYN1 and DYN2 was only ~0.2 V, much below the switching point of the output inverter.
Relationship: contrasting
Domain: Hardware
Sentence 1: 7.4 Sharing between Heterogeneous Systems Because the device .le boundary is common to all An­droid systems, Rio s design readily supports sharing between heterogeneous systems, e.g., between a smartphone and a tablet.
Sentence 2: the implementation has to properly deal with the HAL library of a shared I/O device because it may be speci.c to the I/O device or to the SoC used in the server.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since the shadow memory doe s not keep the valid bits in the pro- cessor TLB, the cache must be flushed at invalidation of a shadow-to-physical mapping to make sure the accesses on the invalidated page be directed to the MTLB.
Sentence 2: in our design there is no need to flush the cache at the invalidation because the valid bits kept in the processor TLB can indicate the invalidity of the mapping.
Relationship: contrasting
Domain: Hardware
Sentence 1: The databases itself are processor independent and reused among all instruction sets.
Sentence 2: pipeline related decisions of the generator are guided by the timing of operations and by the user de.ned target fre­quency ftarget.Thegeneratortries toorganizethepipeline such, that the critical path does not exceed the timing con­straint f -1 unnecessarypipelining target.
Relationship: contrasting
Domain: Hardware
Sentence 1: Furthermore, due to the introducing of a large number of VRs for per-core DVFS, signi.cant amount of power will be dissipated by VRs To overcome the mismatch problem, some approaches to optimize existing components of a single VR have been presented [8], [9], [10], [11].
Sentence 2: these approaches still could not achieve high effectiveness under the low load current condition shown as Region I in Figure 2 (b).
Relationship: contrasting
Domain: Hardware
Sentence 1: When optimizing the placement of 4×4, 5×5, 6×6 regular mesh grids with uniform-width cells, our implementation of the branch-and-price solver is as e.cient as that in [6].
Sentence 2: with the branch-and-price model, the placement of cells with di.erent widths cannot be optimized as e.­ciently as the S Model, the RQ Model and the SCP Model.
Relationship: contrasting
Domain: Hardware
Sentence 1: In an ADB distribution operation, the delay value, vi, on the inserted ADB, ADBi, can be distributed into the buffers and ADBs in the next level by replacing the ADB, ADBi, with a buffer, Bi, introducing a dummy ADB, ADB0, to connect r flip-flops, FF1, and FFr, replacing the t buffers with t ADBs, ADBs+1,.. and ADBs+t, and adding its delay value, vi, into the delay values on the s original ADBs and the (t+1) introduced ADBs as illustrated in Figure 4(a).
Sentence 2: if a buffer only connects a set of ADBs in the next level, some connected ADBs can be further eliminated by using an ADB elimination operation under the minimized clock skew.
Relationship: contrasting
Domain: Hardware
Sentence 1: Yasuaki Kakehi Keio University 5322, Endo, Fujisawa-shi Kanagawa, 252-8520JAPAN +81-466-49-3638 ykakehi@sfc.keio.ac.jp tiple projectors and a screen that composed by view-control .lms and a Fresnel lens.
Sentence 2: there were some limita­tions due to system sizes and shapes since we adopted a rear projection approach.
Relationship: contrasting
Domain: Hardware
Sentence 1: SoC tTAM(serial) tTAM(co-opt) red(%) S 1 624066 620325 -0.6 d695 66779 49615 -25.7 p93791 1223481 967409 -20.9 5.
Sentence 2: we cannot get the optimal solution for all the cases.
Relationship: contrasting
Domain: Hardware
Sentence 1: At the other extreme, measurement of overall side channel signals created by transistor-and wire-granularity variation in activity might allow some low-level layout optimizations.
Sentence 2: such a metric 1) would be very dif.cult to measure on real systems  it would require one to somehow trigger activity on that speci.c transistor or wire while creating little or no activity on all other transistors and wires in the system under test, and 2) would only be useful to those with layout-level knowledge of the system s design, i.e.
Relationship: contrasting
Domain: Hardware
Sentence 1: Via-last TSVs which interfere with both device and metal layers should be aligned between neighboring device layers, and thus are more restricted.
Sentence 2: via-.rst TSVs interfere with device layer only, and thus can be inserted layer-by-layer independently; with the alignment consid­eration of via-.rst TSVs, however, interconnections between TSVs of neighboring layers can be minimized.
Relationship: contrasting
Domain: Hardware
Sentence 1: The adoption of CMPs and other multi-core systems is expected to increase the size of both L2 and L3 caches in the foreseeable future.
Sentence 2: diminutive feature sizes exac­erbate the impact of interconnect delay, making it a critical bottleneck in meeting the performance and power consump­tion budgets of a design [13, 1].
Relationship: contrasting
Domain: Hardware
Sentence 1: These scan resources add to the area of the chip aswell as to the leakage power in normal mode of operation.
Sentence 2: in [8], the authors proposed a method, where theyuse these scan resources as a shadow of the systemflip-flop the designusesfour latches (two for system flip-flop and two for scan flip-flop) to store the redundant copy of the data.
Relationship: contrasting
Domain: Hardware
Sentence 1: Additionally,their memory capacity may be as high as a few hundred Gigabytes1 , ac­tually becoming small versions of the expensive mainframes mentioned above.
Sentence 2: these x86-based machines are currently used asthebuildingblockforclusters, which areacheap and powerfulchoice forHPC.theseclustersdonotpro­vide aglobal shared-memory system.
Relationship: contrasting
Domain: Hardware
Sentence 1: 5.1 Architecture 1: Iterative Looping By only implementing a single round of the Serpent al-gorithm, a looping architecture with thirty-two iterations would seem to provide the greatest area-optimized solution.
Sentence 2: a significant drawback to this architecture is that the Serpent algorithm requires a different set of S-Box group- ings for each round.
Relationship: contrasting
Domain: Hardware
Sentence 1: 7.2.2 Multi-Core Results When the system has a single core, the memory bandwidth pres­sure may not be large enough to take full advantage of the band­width bene.ts of main memory compression.
Sentence 2: in a multi­core system where multiple applications are running concurrently, savings in bandwidth (reduced number of memory bus transfers) may signi.cantly increase the overall system performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: Specifically, averaging through different traffic patterns, 2D­HERT ONoC reduces data transmission delay by 18%, 4%, and 70% over OXbar, LR, and ETorus, respectively.
Sentence 2: it is worth noting that for hotspot traffic pattern, .­router reduces packet delay by 10% against the proposed architecture according to its arbitration­free architecture.
Relationship: contrasting
Domain: Hardware
Sentence 1: Many cache capacity allocation policies have been proposed, including Utilitarian policies [2] that maximize throughput [3], Communist policies [2] that improve fair­ness [1, 8], and Elitist policies [5] that guarantee QoS requirements for high-priority threads [6, 7].
Sentence 2: the ef.cacy of those allocation policies is largely determined by the underlying cache partitioning enforcement schemes.
Relationship: contrasting
Domain: Hardware
Sentence 1: To overcome this degradation, various assist circuitries for read and write operations have been proposed [1-3].
Sentence 2: a lot of new transistor structures such as Fin FET, Multi-gate FET, fully-depleted (FD) SOI and so on have been proposed, and according to ITRS, they are considered to be the promising candidates for future device that replace the conventional bulk CMOS technology.
Relationship: contrasting
Domain: Hardware
Sentence 1: To measure the improvement one must now consider the slacks of all cells that may be moved, and the objective becomes to im­prove the worst slack of the entire subcircuit.
Sentence 2: when one cannot improve the most critical path, the other paths may have avg -1112 -51 1061 -904 4 908 Table 2: The RUMBLE model accurately predicts the solution quality improvements in the reference timing model.
Relationship: contrasting
Domain: Hardware
Sentence 1: To avoid this redundancy, when m<M, itis assumed thatthe M - m lowest degree bits are always zero and that X = (xm-1,xm-2,...,x2,x1,x0,0,...,0) represents M-1 M-m+2 M-m+1 M-m x = xm-1a+ ...+ x2a+ x1a+ x0a.
Sentence 2: the m-bit vector (xm-1,...,x1,x0)does not nec­essarily represent x .
Relationship: contrasting
Domain: Hardware
Sentence 1: Compared to the unprotected case, our scheme provides a video quality improvement of 18dB (averaged over various fault injection cases and video sequences) at the cost of a 35% area overhead and 45% performance overhead due to the error-detection logic.
Sentence 2: partitioned sub-tables increase the potential for power-gating, thus bring a leakage energy saving of 58%.
Relationship: contrasting
Domain: Hardware
Sentence 1: Physically Unclonable Functions: Manufacturing Variability as an Unclonable Device Identi.er Ingrid Verbauwhede Roel Maes COSIC/ESAT and IBBT, K.U.Leuven COSIC/ESAT and IBBT, K.U.Leuven Kasteelpark Arenberg 10 Kasteelpark Arenberg 10 3001 Heverlee, Belgium 3001 Heverlee, Belgium ingrid.verbauwhede@esat.kuleuven.be roel.maes@esat.kuleuven.be ABSTRACT CMOS process variations are considered a burden to IC de­velopers since they introduce undesirable random variabil­ity between equally designed ICs.
Sentence 2: it was demon­strated that measuring this variability can also be pro.table as a physically unclonable method of silicon device identi­.cation.
Relationship: contrasting
Domain: Hardware
Sentence 1: Samplers count the input events statistically: an event t selected by a sampler operating at a rate r can be interpreted by software as r occurrences of tuple t compressed into one.
Sentence 2: clearly, such stream compression is lossy, because events skipped by the sampler may have been different than t. when the stream is biased towards tuple t (i.e., the stream is dominated by t), the sampler's accuracy may be sufficient for profiling purposes.
Relationship: contrasting
Domain: Hardware
Sentence 1: From the simulation results using MMP, the proposed bidirectional link shows at least 34% improve­ment in delay and at least 6× improvements in PDP at data rates of 500Mbps.
Sentence 2: if we compare mesured results of the proposed scheme with the simulations of the voltage­mode scheme using MMP, the proposed scheme o.ers 18% imprvement in delay and 3.73× improvements in PDP.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the recognizer is given an exhaustive set of these words , it would pick out the ones that best match the audio samples, and provide acoustic and/or confidence scores that we can then use to select target pronunciations.
Sentence 2: with a typical phoneme set of, say, 37 phonemes, trying to match a sequence of even only 5 phonemes creates a search space of 375 distinct sequences, making the task computationally impractical.
Relationship: contrasting
Domain: Hardware
Sentence 1: We can easily show that this model arises when considering the traffic pattern generated by the successfully transmitted packets (not collided) in a slotted Aloha multichannel system, under the simplifying assumption of global Poisson arrival traffic (the traffic corresponding to new and retransmitted packets).
Sentence 2: rather than focusing on the analysis of this scenario, we are interested here in describing the sensitiveness of the response time distribution to the truncation value of the geometric on and off periods.
Relationship: contrasting
Domain: Hardware
Sentence 1: When only edge count constraint is applied, the tasks are mapped as in Figure 5b), where the .lter task is still prone to the faults on an unreliable PE.
Sentence 2: a core-reliability-aware mapping schedules tasks as in Figure 5c), where further single bit-.ip fault injection on the .lter application does not hang the system due to the ECC protected program counter.
Relationship: contrasting
Domain: Hardware
Sentence 1: If one logic gate is active and the other is quiet, the coupling capacitance may cause the effective load capacitance of the active logic gate to be less than C1 + C~ or C2 + Cc when the active logic gate transitions from high-to-low and the quiet state is at logic low (ground).
Sentence 2: if the quiet state is high (Vdd), the effective load capacitance of the active logic gate can exceed C1 + Cc or Cz + C~.
Relationship: contrasting
Domain: Hardware
Sentence 1: Thekeyis generated from complexphysi­cal characteristicsof eachphysicalinstanceofanIC,andis thus extremely dif.cult to predict or extract.
Sentence 2: this approach is not completely suitable for trojan detection be­cause it does not prevent the insertion of trojan circuitry in the IC and causes unacceptable hardware overhead to obtain good levels of security.
Relationship: contrasting
Domain: Hardware
Sentence 1: The reason is that in [8], when merging two branches, without additional prop­erties on Q, C, W , the merging time is quadratic (in terms of the number of solutions) even if the number of the non­dominated solutions after merging is much less.
Sentence 2: a critical observation in layer as­signment is that it is possible to limit the number of non­dominated solutions during solution propagation to be lin­ear, by exploring some speci.c properties in layer assignment problem.
Relationship: contrasting
Domain: Hardware
Sentence 1: This ensures read SNM to be almost same as the hold SNM, improving read stability signi.cantly.
Sentence 2: the single-ended 8T,10T and 9T sub-threshold SRAMs su.er from small bitline swings due to the bitline leakage (junc­tion leakage) which can cause functional failures during the read access[14].
Relationship: contrasting
Domain: Hardware
Sentence 1: Some mod­ulo (2p - 1) adders and multipliers have been proposed[5, 6, 7].
Sentence 2: since these adders and multipliers are con­structed based on the ordinary binary arithmetic systems, the carry propagation will arise and the residue addition time is prop ortional to log(p) even for the improved adder architectures[8].
Relationship: contrasting
Domain: Hardware
Sentence 1: The objective of the cache-content selection problem in such scenarios is to improve the worst case system behavior according to some of real-time schedu­lability metrics as described in [16, 15, 12, 21, 4, 10].
Sentence 2: our objective of cache-content selection is to im­prove average case run-time of embedded applications which is completely di.erent objective, requiring a very di.erent strategy.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4.2 A GALS Simulation Framework Building a cycle-accurate simulator for a single-clock pipelined system is simple; in C, we only need to call vari- ous pipe-stage functions in the reverse order of their occur- rence in the pipeline.
Sentence 2: to simulate a multiple-clock I'cache 0pre0 I ,./"1 i!
Relationship: contrasting