sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Our results show that many factors in.uence the appropriate­ness of the delivery architecture including: the characteristics of the virtual environment, rate of movement, distribution and density of avatars.
Sentence 2: we note that peer-to-peer delivery has sig­ Figure 8: Effect of virtual world density on resource usage ­multicast performance with varying numbers of POPs lying network supports multicast (if the number of ISPs is large).
Relationship: entailment
Domain: Hardware
Sentence 1: As the .rst three conditions are already covered by event register 1, the value for event register 2 can be found to be 1101 to cover the re­maining condition ABCD = 1101.
Sentence 2: the trig­ger unit has to detect on the available trigger signals when Z = ABCD = 1011 OR ABCD == 1101 in order to capture the targeted trigger event Y = 1 in this example.
Relationship: entailment
Domain: Hardware
Sentence 1: The key to designing a microprocessor that can achieve both high scalar performance and high throughput performance is to dynamically vary the amount of energy expended to process each instruction according to the amount of parallelism available in the software.
Sentence 2: if there is little parallelism, a microprocessor should expend all available energy processing a few instructions; and if there is a lot of parallelism, the microprocessor should expend less energy in processing each instruction.
Relationship: entailment
Domain: Hardware
Sentence 1: There are also some FFs that serve as both backward FF and forward FF at the same time and we call it bidirectional FFs.
Sentence 2: for this type of FF, if we move them backward, it can help to eliminate the suspicious FF in its fan-in cone or change itself from suspicious to non-suspicious while if moving forward, it can be helpful to eliminate suspicious FF in its fan­out cone.
Relationship: entailment
Domain: Hardware
Sentence 1: We review previous approaches to this problem in the more gen­eral setting of linear dynamical systems (Lacy &#38; Bern­stein, 2002; Siddiqi et al., 2008), then describe a simple approach that works well in our setting.
Sentence 2: by appealing to Gershgorin circle theorem for eigen­value bounds (Golub &#38; Loan, 1996), we show that stability is guaranteed by imposing a simple £1-norm constraint on the model coe.cients.
Relationship: entailment
Domain: Hardware
Sentence 1: A highly compact and ef.cient design was obtained taking advan­tage of the architectural characteristics.1 1.. Introduction The ever-increasing demand for security, along with several crucial requirements like performance and tamper­resistance, has caused in the recent years an increasing de­ployment of hardware devices to support security services, such as con.dentiality, authentication, integrity and non­repudiation.
Sentence 2: asymmetric, or public-key, cryptography plays an important role in all modern security-aware appli­cations, since it has the fundamental property of enabling This work was supported in part by the Italian National Research Council (CNR), by Ministero dell Istruzione, dell Universit` a e della Ricerca (MIUR), and by Regione Campania, within the framework of following projects: SP1 Sicurezza dei documenti elettronici, Ges­tione in sicurezza dei .ussi documentali associati ad applicazioni di commercio elettronico, Centri Regionali di Competenza ICT, and Telemedicina.
Relationship: entailment
Domain: Hardware
Sentence 1: and the average batch size; accordingly, the traffic intensity remained also constant in all experiments.
Sentence 2: we fixed TABLE II SUMMARY OF PARAMETERS AND RESULTS IN THE SECOND SET OF EXPERIMENTS On-Off-Batch Iterations Mean Jitter Skewness HGeo[12, 8, 16]-Uniform[28, 40]-Constant[5] 4 13.222 7.340 0.158 Binomial[8, 0.625]-Constant[34]-Uniform[1, 9] 9 14.085 8.004 0.182 Uniform[4, 8]-Binomial[44, 0.75]-HGeo[20, 5, 20] 5 13.369 7.646 0.266 Constant[6]-Binomial[44, 0.75]-Binomial[10, 0.4] 4 13.161 7.356 0.167 response time distribution 0.06 0.05 0.04 0.03 0.02 0.01 0  5 10 15 20 25 30 Figure 9.
Relationship: entailment
Domain: Hardware
Sentence 1: Thus, we de.ne the weight of an active line l as Wl = the number of downstream sinks which allows us to directly minimize total sink delay impact over all nets in a given tile.3 4.2 Max-MinSlack-Fill-Constrained Objective A weakness of the MDFC PIL-Fill formulation is that we mini­mize the total delay impact independently in each tile.
Sentence 2: the impact due to .ll features on the signal delay of complete timing paths is not directly considered.
Relationship: entailment
Domain: Hardware
Sentence 1: These non­classical CMOS device structures include Double-Gate (DG) MOSFETs, the Pi-Gate (PG) MOSFETs, and the cylindrical Surrounding Gate (SRG) MOSFETs.
Sentence 2: sRG MOSFETs offer the best control of SCEs and sub-threshold characteristics [1-2].
Relationship: entailment
Domain: Hardware
Sentence 1: The automatically generated pronunciation result for Hebrew is especially noteworthy, in that the few recognition failures were all due to failure of our method to produce any pronunciations (this happens when no vocabulary choice provides reasonable match to the recording, as might happen if there is excessive noise during the recording or particularly unusual pronunciation).
Sentence 2: for those words for which our method did produce a pronunciation, subsequent recognition accuracy was 100%.
Relationship: entailment
Domain: Hardware
Sentence 1: As the benefits of VDD and Vth scaling have already been proved, in this paper we concentrate on quantitative pointers for using such know-how in deep sub-micron technologies.
Sentence 2: we want to find what the expected power savings are, what power-delay tradeoffs can be made, understand present static and dynamic power consumption trends, and investigate how far can process-dependent performance spread be tuned.
Relationship: entailment
Domain: Hardware
Sentence 1: On the basis of the observed de.ciency in provisioning cloud workloads, we propose a fractal model for prediction and optimization.
Sentence 2: we aim to provision the uti­lization of datacenter workloads to shift the distribution of utilization level to more energy e.cient values as much as Figure 2: CPU and memory usage of google work­loads in a Google s 12k-machine cell over about a month-long period [38] possible.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.3.3 Software-only Less Conservative Approach (SoLA) In this approach, we take the mechanism explained in Sec- tion 3.3.2 and try to be less conservative in the BRANCH cases.
Sentence 2: we want to eliminate iTLB lookups when a static analysis of the code by the compiler can re- veal that the branch target is within the same page as the branch instruction itself (this typically occurs when branch targets are given as immediate operands or as PC relative operands).
Relationship: entailment
Domain: Hardware
Sentence 1: In this context, the paper proposes a mutation model targeting the communication primitives of the new Sys­temC TLM 2.0 library [5].
Sentence 2: the paper analyzes the main primitives provided with such a library, and it presents the following innovative contributions (Figure 1): a way for formalizing the internal behavior of the TLM 2.0 communication primitives by using the extended .nite state machine (EFSM) model [6];  a set of mutations for such EFSMs based on an extension of the well-known transition fault model for FSMs [7];  identi.cation of relations between the proposed mutations and typical design errors.
Relationship: entailment
Domain: Hardware
Sentence 1: Two .ag bits (F1 F2 ) are also added to the tag entry of each cache block to guide pre­recovery operations.
Sentence 2: f1 F2 are set based on the status of the pre-recovery operation as: 1) F1 F2 = 01 for an on-going pre-recovery (counter=00001); 2) F1 F2 = 11 for a complete pre­recovery (counter=11000); and 3) F1 F2 = 00 for no or pending pre-recovery (counter=00000).
Relationship: entailment
Domain: Hardware
Sentence 1: If R write en is true, then, on the rising edge of Rclk, data is entered into the In.fo, into the location pointed at by R write pointer.
Sentence 2: r write en = (validprev) · (addrmatchprev · Full In f i f oprev) data is dropped if the packet is valid (.rst term above) and if the address matches, and the input FIFO is not full (second term).
Relationship: entailment
Domain: Hardware
Sentence 1: Th -Tc 1 Qc(I, Th, Tc)= NSITc - - I2Re(1) Rt 2 Th -Tc 1 Qh(I, Th, Tc)= NSITh - + I2Re(2) Rt 2 The power input to the TEC, PT E C , is equal to difference between Qh and Qc.
Sentence 2: pT E C (I, Tc, Th)= Qh -Qc = N(SI.T + I2Re), (3) where .T is equal to Th - Tc.
Relationship: entailment
Domain: Hardware
Sentence 1: Leaving i6 out of the tree will enable detection of such MBUs, which have a high probability of becoming visible to the system, at the cost of allowing single errors on i6 to propagate (with low probability) to the system level.
Sentence 2: careful AVF­driven selection of bits to include in the parity tree can be bene.cial both in terms of overhead and in terms of coverage.
Relationship: entailment
Domain: Hardware
Sentence 1: On the other hand, it is also promising to identify the logic primitives efficiently realized by controllable-polarity FETs in existing data structures.
Sentence 2: bDD Decomposition System based on MAJority decomposition (BDS-MAJ) [10] is a logic optimization system driven by binary decision diagrams that supports integrated MUX, XOR, AND, OR and MAJ logic decompositions.
Relationship: entailment
Domain: Hardware
Sentence 1: The main conclusion of this analysis is that not so many gates can be built in a single TRL unit in the case that the target fabric provides 6 transistors of each type (PMOS and NMOS) and 4 input variables, as originally indicated in [11].
Sentence 2: for these larger cells which are majority in this set, becomes necessary to spread the (transistor network of the) logic gates in two or three fabric units or to remap complex gates into arrangements of simpler (basic) ones.
Relationship: entailment
Domain: Hardware
Sentence 1: For a MH, both these factors are a function of its path loss and the level of interference from other MHs.
Sentence 2: we assume that the cost is C.(7/, Z, 7) = aP +/37 (5) where a and 13 are two design constants, P is the transmis- sion power needed to achieve the requested target SINR 7.
Relationship: entailment
Domain: Hardware
Sentence 1: This means that a computation can be performed along a wavefront starting with node (0, 0) (which depends on no other nodes) followed by computing (1, 0) and (0, 1) in parallel, then (2, 0), (1, 1) and (0, 2) also in parallel and so on.
Sentence 2: the lack of backwards data flow means that there is a huge amount of parallelism available in the computation.
Relationship: entailment
Domain: Hardware
Sentence 1: We propose an algorithm that will make use of the DFG to analyze the instruction dependency characteristics and rearrange the instructions in a manner which will place memory loads earlier while pushing instructions dependent onthese mem­ory loads later within the basic block.
Sentence 2: this algo­rithm must ful.ll the following constraints in order to maintain proper program execution and behav­ior: True datadependencies mustbe maintained  The order of store operations must be main­tained  The orderof loadoperations respectivetostore operationsmustbe maintained  it is important to note that the constraints listed above with regard to memory store ordering could be relaxed if the e.ective des­tination address was statically guaranteed not to con.ict withother memory load/store instructions.
Relationship: entailment
Domain: Hardware
Sentence 1: MTTF value (represented by the height of the bars) is the average normalized MTTF across all applica­tions, where the average MTTF at a perfor­mance of 1.0 and a cost of 1.0 is normalized to 1.0 Figures 7(a) and (b) show the highest average MTTF possible for each cost and performance constraint.
Sentence 2: for each point with cost=C and performance=P, we report the highest MTTF (averaged across all applications) among all the SD+GPD con.gurations with cost :C and perfor­mance ?P.
Relationship: entailment
Domain: Hardware
Sentence 1: Adaptive Data Protection in Distributed Systems Anna Cinzia SquicciariniCollege of Information Sciences and Technology Pennsylvania StateUniversityUniversity Park, PA, 16802 Giuseppe Petracca College of Information Sciences and Technology Pennsylvania State UniversityUniversity Park, PA,16802 Elisa Bertino Computer Science Department Purdue University West Lafayette, IN, 47906 ABSTRACT Security is an important barrier to wide adoption of dis­tributed systems for sensitive data storage and management.
Sentence 2: one unsolved problem is to ensure that cus­tomers data protection policies are honored, regardless of where the data is physically stored and how often it is ac­cessed, modi.ed, and duplicated.
Relationship: entailment
Domain: Hardware
Sentence 1: With this background, it is becoming more important to explore inorganic semiconductors such as silicon as well as new electronic functional materials with characteristics complementary to those of silicon.
Sentence 2: we have great expectations for organic molecular materials, which are mainly composed of carbon, and carbon nanomaterials such as graphene and carbon nanotubes for use as functional materials because abundant elements can be used for their synthesis.
Relationship: entailment
Domain: Hardware
Sentence 1: Here the median of UM .R3 , denoted by ¯u =( ¯ux, u¯y, u¯z)T is de.ned as a vector composed of the medians in each coordinate.
Sentence 2: u¯x is the me­ x xyz dian of {ui : ui =(ui ,ui ,ui )T ,i .M}.An alternative de.nition based on the average of displacements is possible h * i P wij dij (Xi -Xj ) * i T j.Ni Mc wij Xj + X * i = .X-Xj.
Relationship: entailment
Domain: Hardware
Sentence 1: We represent c2i and c1i as c2i =c2i ×2-l2i ×2l2i ' ' and c =c1i ×2-l1i ×2l1i , respectively.
Sentence 2: instead of the 1i ' original values of c2i and c1i, we store the values of c2i ×2-l2i , ' l2i, c1i ×2-l1i ,and l1i in the coef.cients table.
Relationship: entailment
Domain: Hardware
Sentence 1: We mention that even for high-dimensional subspaces the computation time for our metrics is not the limiting factor; the acquisition time still dominates the duration of the side-channel evaluation.
Sentence 2: leakage models with high-dimensional subspace reduced the required number TABLE I SU C C E S S R AT E F O R A L L L E A K AG E M O D E L S Subspace [dim] 2 9 37 93 163 # Traces for success rate=1 14971 7206 3137 2881 2250 by the German Federal Ministry of Education and Re­search (BMBF) in the project Resist through grant number 01IS10027A and CASED (www.cased.de).
Relationship: entailment
Domain: Hardware
Sentence 1: B. Computation of Approximate value For each [si,ei], f (x)is approximated by the corresponding quadratic function gi(x).
Sentence 2: the approximated value y of f (x)is computed as follows: y =gi(x)=c2ix2 +c1ix +c0i, (3) where the coef.cients c2i, c1i,and c0i are derived from the 2nd­order Chebyshev approximation polynomial [11].
Relationship: entailment
Domain: Hardware
Sentence 1: While the GCP can provide extra power, the existing power bud­gets still need to be enforced: (i) the DIMM and chip power budgets must be obeyed and (ii) the DIMM and chip power budgets are not changed by introducing the GCP.
Sentence 2: the power that the GCP provides to one chip is actually borrowed from other chips.
Relationship: entailment
Domain: Hardware
Sentence 1: [7] present a comprehensive survey of memory optimizations used in embedded systems.
Sentence 2: their discussion of memory packing and array-to-memory assignment [7, Section 3.3] is similar in principle to the LICCA problem formulation; one important difference is that they consider reordering parallel memory accesses through instruction scheduling; we do not have the leeway to perform this reordering as our concurrent memory accesses occur in the context of ISE invocations; in general, we cannot move an access to an array element from one ISE invocation to the next without altering the computation performed by the program.
Relationship: entailment
Domain: Hardware
Sentence 1: The second case is similar to the synchronous unilateral scheme in the following respect: In­stead of having a feedback signal r from machine M2 to M1 we have implicit timing constraints (enforced, e.g., through timer cir­cuits or counters) that enable state transitions in machine M1 only if M2 is guaranteed to have moved into the corresponding commu­nication states.
Sentence 2: the timing constraints enforce the reachability constraints of the four-cycle handshake abstraction.
Relationship: entailment
Domain: Hardware
Sentence 1: Figure 9 demonstrates the comparison results of the measurement, complete model and other simplified modeling strategies.
Sentence 2: for the last five bins, each represents one of the following simplifications: (1) Ignoring intentional decap; (2) Ignoring power-to-signal coupling capacitance;  (3) Ignoring top metal layer inductance; (4) Using an RLC series package model instead of S parameter based package model.
Relationship: entailment
Domain: Hardware
Sentence 1: Explore low-overhead techniques that can improve robustness and facilitate aggressive VS, thus improving energy efficiency under very high defect rates.
Sentence 2: we show how selective application of robust circuit techniques, such as 8T cells, only on some critical parts of the system (that are identified by our study) can reduce the overhead of conventional conservative robustness techniques that aim at restoring 100% reliable operation while ensuring minimum system throughput at high yield loss under high defect rates.
Relationship: entailment
Domain: Hardware
Sentence 1: First, prefetching will improve the average IPC of the main thread, but not that of the helper thread, leading to an upper bound on how far ahead a helper thread can run before the main thread will catch up to it.
Sentence 2: the main thread will catch up with the helper thread when slack(i, s, t) = 0 inEquation1 or, CPIm(s, t) · d(s, t) - o(s, t) d(t, i)max = (2) CPIh(t, i) - CPIm(t, i) Figure 4 portrays a graphical representation of this concept by plotting instructions executed versus time for a portion of a program s execution trace.
Relationship: entailment
Domain: Hardware
Sentence 1: The multi-threadedbase cycle countis settobethe same as the single-threadedbase cycle count,i.e.,we considerthe same unit of work done under multi-threaded and single-threaded execution.
Sentence 2: csmt Cst B,i = B,i.The multi-threaded miss event cycle counts are estimatedby multiplying the single-threaded miss event cycle counts with their respective ratios.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.1 Timing Information To implement a timing-accurate synchronization mecha­nism, we modi.ed the communication protocol between the ISS and the SystemC simulation kernel to exchange not only data, but also messages containing timing information.
Sentence 2: the SystemC simulation kernel, which drives the overall co-simulation, gets timing information from the ISS by means of GDB commands at each communication point (breakpoints in the SW code).
Relationship: entailment
Domain: Hardware
Sentence 1: 4.1.3 Net Weighting In order to get a more accurate delay estimation of ICG, we At each temperature in the SA process, the interconnect delays perform a list-scheduling on the bound CDFG.
Sentence 2: our are extracted from the current layout and back-annotated to the scheduling algorithm picks the ready operation node with the edges in the bound CDFG.
Relationship: entailment
Domain: Hardware
Sentence 1: Then, sinceonlyone memoryoperation canbeperformed at each time, the memory interface of the current function can formachain withallinterfacesofthefunctions which are directly called by the function itself in order to propagate the request until the correct addressed memory is found.
Sentence 2: the request can be propagated from inside to outside a function, up to the external memory, in case.
Relationship: entailment
Domain: Hardware
Sentence 1: In order to synthesise a circuit, Petrify requires an SG to have a complete state coding (CSC).
Sentence 2: no two reachable markings of the net may be encoded by the same Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: entailment
Domain: Hardware
Sentence 1: Total yield losses for relaxed and strict cases with horizontal power-down Losses with Scheme  # Chips  H-YAPD VACA Hybrid 191 51 131 25 Relaxed 752 224 516 146  Strict result, the number of chips that do not meet the delay constraint increases.
Sentence 2: for the base case of this cache architecture, we see that 18.1% of the chips are lost.
Relationship: entailment
Domain: Hardware
Sentence 1: Once the (list of) range(s) on the outermost dimension has been computed, the process is recursively applied on the next dimension (e.g., c1 in our example) [10].
Sentence 2: for each range of c0 obtained ' previously, we project out DR along the c1 dimension and repeat the process of possibly separating the projections into multiple contigu­ous regions.
Relationship: entailment
Domain: Hardware
Sentence 1: We assert that these classes of events are quite distinct, and this paper attempts to elucidate this principle by identifying the (mis)use of trapping in VMs for security bene.ts.
Sentence 2: our goal is to untangle security and virtualization by differentiating between the twin needs to trap both security-related events and emulation­related events (of which there may be overlap).
Relationship: entailment
Domain: Hardware
Sentence 1: Comparing the proposed method with HITEC, the fault ef.ciency by the proposed method is equal or higher than that by HITEC for all circuits except s5378, while the com­putational time of the proposed method is comparable to that of HITEC.
Sentence 2: for s1423 and s9234, the pro­posed method can provide test sequences with higher fault ef.ciency in smaller computational effort than HITEC.
Relationship: entailment
Domain: Hardware
Sentence 1: This de.nition illustrates both the physical meaning of K matrix and how it can be calculated.
Sentence 2: iteratively assign­ing the magnetic vector potential drop along conductor seg­ment i,(i=1;2;:::;n), to be 1, while the magnetic vector potential drops along all other conductor segments to be 0, we can obtain each column iof the Kmatrix through calculating the induced current in each conductor segments.
Relationship: entailment
Domain: Hardware
Sentence 1: When calculating the efficiency and input current of a candidate regulator cn for n (line 10 and 22 From Figure 4) iout(n) becomes a piecewise-linear function; so, instead of having a constant value for the efficiency and input current of node n, we need to model both of them as piecewise-linear functions.
Sentence 2: k1,k2 ,...,km k1 k2 km .
Relationship: entailment
Domain: Hardware
Sentence 1: library IEEE, DISCIPLINES;  use IEEE.math_real.all; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all;  use DISCIPLINES.electromagnetic_system.all; Following the library declaration, we have the entity declaration describing the interface of the model to the outside circuitry.
Sentence 2: it describes the analogue and digital ports as well as the parameters that are used in the behavioural description of the model and are influencing its electrical performance.
Relationship: entailment