sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: r(n) denotes a state at n-th clock tick.
Sentence 2: s1(r(n)) denotes f1 and S2(r(n)) = f2 at clock tick n. We further denote the following: p PROP (the set of all propositions), r(n)s p if S1(r(n))(p) = True; r(n)s .p if S1(r(n))(p) = False.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, [][ ] 1CL - is decoupled as * -1 -1 T ([S ] [ ]([ ] ) ) =C ].
Sentence 2: (16) n C S n diag [ m from (13) and (16), * -1 * -1 * -1 [C ] =Cm ] =[S ] [ ] [ S ]n .
Relationship: reasoning
Domain: Hardware
Sentence 1: Although these custom architectures are expected to achieve better latency and area utilization, their design process is more complex and faces several challenges, such as greater crosstalk and uncertainty in link delays due to irregular interconnect structures.
Sentence 2: a conservative enough custom design may actually offset the advantages of better performance [15]; especially for medium to large sized (in terms of total number of cores) NoC architectures.
Relationship: reasoning
Domain: Hardware
Sentence 1: Pr sksl) (2) (, s.M ki In the bipartition case where there are just two submachines, we have Pr(M1) = Pr(M1, M1) + Pr(M2, M1) (3) If a transition is within the same submachine Mi, the submachine label does not change.
Sentence 2: the inputs to the other submachine are kept disabled, causing no activity in that submachine.
Relationship: reasoning
Domain: Hardware
Sentence 1: All of these technologies show no gain, operate at cryogenic temperatures with poor signal to noise ratio, hence impractical to build electronic circuits which work and replace CMOS.
Sentence 2: 1.E-05 1.E-06 1.E-07 NMOS 1.E-08 CMOS 1.E-09 1.E-10 1.E-11  1930 1950 1970 1990 2010 Figure 2: Delay scaling Second CMOS is here to stay, even beyond nano-scale [5].
Relationship: reasoning
Domain: Hardware
Sentence 1: for coe.cients is set to 4, then the coef­.cient vector ci is modi.ed by replacing every coe.cient whose absolute value is less than 4 with 0.
Sentence 2: the new c1 becomes[01 000 000]T Now, multiplying the new coe.cient [c1]T with Hh(3) yields: [01000000]× Hh(3)=[1 - 11 - 11 - 11 - 1] We will extend the test set for PI1 with (1, -1, 1, -1, 1, -1, 1, -1).
Relationship: reasoning
Domain: Hardware
Sentence 1: Typical types of queries that can be ef.ciently answered by the Bayesian network model are derived from applying the Bayes rule to yield posterior probabilities for the values of a node (or set of nodes), X, given some evidence, E, i.e.
Sentence 2: assignment of speci.c val­ues to other nodes: p(E|X)* p(X)p(X|E)= p(E) a statistical inference can be made in the form of either select­ing the Maximal A Posteriori (MAP) probability, max p(X|E),or obtaining the Most Probable Explanation (MPE), argmax p(X|E).
Relationship: reasoning
Domain: Hardware
Sentence 1: Based on this, we can ex­press delay, area and power consumption of the proposed adder in terms of the parameters N and k. The proposed ACA adder has (N/k - 1) sub-adders, each of which is a 2k-bit adder.
Sentence 2: delay of the critical path can be expressed with Equation (2) and area can be estimated with Equation (3), where Cdelay and Carea are constants for delay and area, respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: The delayed ack signal pulls a trigger to the ring counter so that the content of the ring counter is rotated one bit.
Sentence 2: the token bit is rotated left each cycle, with 4 b1000 rotating to 4 b0001 in Figure 3(b), and the token is initialized to one at the reset phase (e.g., 4 b0001 for four-bit ring counter) so that there is only one 1 output by the ring counter.
Relationship: reasoning
Domain: Hardware
Sentence 1: A pulsed-latch is a latch synchronized by a pulse clock as shown in Figure 1(a) [3].1 Since the pulse is short, a pulsed-latch can be approximated as a fast, low-power, and small flip-flop taking advantages of both flip-flops and latches.
Sentence 2: migration from a flip-flop-based design to a pulsed-latch-based counterpart can effectively reduce the sequencing overhead.
Relationship: reasoning
Domain: Hardware
Sentence 1: The frequency domain waveform of the k-th modal ( ) Z0k .k(x-2U) wave, e -.kx +Gke , can be approximated RSi+Z0k by using a 3-pole approximation function, Qk (x, .).
Sentence 2: the i-th line wave can be approximately modeled as n Vi (x, .)
Relationship: reasoning
Domain: Hardware
Sentence 1: At the entire core level the scheduler consumes 3.9% area, 8.9% dynamic power, and 1.2% leakage power.
Sentence 2: the overheads at the entire core level are min­imal in our schemes (e.g., 0.24% area overhead, 0.13% dynamic power overhead, and 0.08% leakage power overhead in CDS).
Relationship: reasoning
Domain: Hardware
Sentence 1: 60% 50% 40% 30% 20% 10% 0% Figure 5: Subthreshold leakage power At low logic activity the active power is low and the leakage power dominates, reducing the effectiveness of NTV for energy efficiency.
Sentence 2: fine grain leakage power management, with sleep transistors or power gating techniques will be even more important.
Relationship: reasoning
Domain: Hardware
Sentence 1: 5.2 Custom Layout Design The exact evaluation of most parameters, such as PL and transistor area, can only be obtained after a layout design.
Sentence 2: we implement and compare three lay­out designs, sleep transistor free(ST-free) design, cluster­based sleep transistor design(CB-STD) and DSTN, for a 4­bit carry-lookahead(CLA) adder.
Relationship: reasoning
Domain: Hardware
Sentence 1: NEM relays exhibit zero leakage (experimentally verified) and their on-resistance values are predicted to be smaller than that of the NMOS pass transistors [Akarvardar 07, Nathanael 09, Timsit 04].
Sentence 2: routing switches made out of NEM relays present unique opportunities to reduce power and improve performance of FPGAs.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3.2 Statistical Delay Model The on-resistance of a gate i is inversely proportional to its size wi.
Sentence 2: using the Elmore delay model, the delay of gate i, di can be written as Cld,i di = ai + ßi (20) wi where ai is a .tting parameter, Cld,i is the capacitive load at the output of gate i.
Relationship: reasoning
Domain: Hardware
Sentence 1: Unfortunately, the vast majority of the reported models lack important details, such as values for various constants, measurement conditions, detailed explanation of parame­ters, etc.
Sentence 2: it becomes fairly challenging to employ the existing frameworks, in the context of microarchitecture, to perform meaningful aging e.ect calculations Various techniques have been proposed so as to mitigate the aging e.ect in processor core architectures.
Relationship: reasoning
Domain: Hardware
Sentence 1: ICCAD 2012, November 5-8, 2012, San Jose, California, USA Copyright &#38;#169; 2012 ACM 978-1-4503-1573-9/12/11... $15.00 the stacked chips as well as create package hot spots.
Sentence 2: thermal modeling approaches, which are able to simulate 3D system including stacked ICs, package and PCB efficiently, are required.
Relationship: reasoning
Domain: Hardware
Sentence 1: At tc, this magnet experiences .eld contribution only from a helper, and this .eld can at most be HmaxExtra (otherwise, the magnet will not switch).
Sentence 2: before switching, the magnet must see a clock .eld of at least HminExtra -HmaxExtra (line 4) such that the total .eld for metastability becomes HminExtra .
Relationship: reasoning
Domain: Hardware
Sentence 1: The conventional scheme proposed for estimating the IFO uses only partial information of combinations that pilots can provide, which stems from a rigorous assumption that the channel responses of pilots used for estimating the IFO change very rapidly.
Sentence 2: in this paper, we propose the novel IFO estimation schemes exploiting additional information of combinations that pilots can provide to improve the performance of the IFO estimation.
Relationship: reasoning
Domain: Hardware
Sentence 1: However,reportedresultsonthismetrisuggestedthatthe Hammingdistanedoesnotneessarilyorrelatewiththe atualdistaneinstatespae[16].Therefore,weenhane itbyweightingthebitsinthestatebytheirontrollabil­ity.Intuitively,thedifereneinahard­to­ontrolFFwill ontributemorethanaeasy­to­ontrolFFtotheoveralldis­taneofthetwostates.Therearetwoasestobedifered herewhenalulatingthediferene:  thebitinandidatestateis0andintargetstateis1;  thebitinandidatestateis1andintargetstateis0.
Sentence 2: inthefrstase,weneeda0to1transitionintheFFbitto justifytheFFvalueanda1to0transitionisneededinthe seondase.thedistaneistarget­state­related.
Relationship: reasoning
Domain: Hardware
Sentence 1: Moreover, since partial recon.guration only targets the module containing the faulty cell and leaves other aspects of the micro.uidic con.guration unchanged, a fast heuristic algorithm can be used to .nd a new location for this module.
Sentence 2: partial recon.guration is suitable for dynamic online recon.guration during .eld operation of the micro.uidic biochip.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, in our model, the total capac­ity used by ECC (in bits), CECC , is 416 bits/sector for drives whose areal densities are less than 1 Tb/in2, whereas those in the terabit range use 1440 bits/sector.
Sentence 2: derated Capacity Equation: From our above discussions on ZBR, Servo and ECC costs, we can calculate their to­tal space overhead (in bits/sector) as Ctzmin a = ntz( )(Cservo + CECC) 4096 the estimated capacity of the disk in terms of 512byte sectors is given by nzones-1 - a ntzCtzmin Cactual = nsurf ntz() (3) 4096 z=0 Validation: To verify the accuracy of this model, we calcu­lated the capacity estimated by our model for a set of server disks of different con.gurations, manufacturers, and fromdifferent years (obtained from [2]).
Relationship: reasoning
Domain: Hardware
Sentence 1: Performing MDP real-time with dynamically changing net­work conditions will increase the energy consumption and delay, due to the high computational and/or memory com­plexity.
Sentence 2: mDP is performed o.ine and the obtained optimal slot policy matrix P (b, e), for all possible bu.er bn and energy e n states, respectively, are stored in a table in­side each node.
Relationship: reasoning
Domain: Hardware
Sentence 1: Low-cost: many of the proposed schemes, especially context-based prefetchers, are expensive to implement, due to the amount of state information they require to perform e.ectively.
Sentence 2: they are not well suited to aggressive multi-core processors, the current industry trend, where area is at a premium and mul­tiple instantiations of the HW prefetchers may be re­quired to support prefetching into each core s L1 cache.
Relationship: reasoning
Domain: Hardware
Sentence 1: Figure 2 gives SPICE simulation results of leakage vs. delay of standard 6T SRAM cells using the same 90nm process and shows that delay increases and leakage decreases by raising Vth,Tox.
Sentence 2: in the right-hand side of Figure 1 cell latency increases (compare the two last rows) and one of the cells violates the target delay of 540ps.
Relationship: reasoning
Domain: Hardware
Sentence 1: T T dt Noise Height (v) Noise Height (v) Vdd Vdd (a) Regular DFF (b) SDT-DFF Figure 2 Noise Capture Zone (NCZ) of DFFs The third factor is the distribution of noise occurrences inside the circuit: noise caused by different mechanisms is likely to occur at certain regions.
Sentence 2: the endpoint DFFs of the paths on which noise are more likely to occur will potentially experience a higher rate of noise attack.
Relationship: reasoning
Domain: Hardware
Sentence 1: Both the dynamic and the leakage power consumption of a CMOS circuit depend upon the supply voltage, and they decrease at lease quadratically with decreasing supply voltages.
Sentence 2: in recent times, it is common to de­crease the supply voltage value in the non-critical parts of SoCs and multi-core processors, in order to reduce the power and en­ergy consumption.
Relationship: reasoning
Domain: Hardware
Sentence 1: C.Transformation-basedOptimizationMethods Sineitistotallyimpossibletogenerateanoptimal logiiruitbyonemethod(espeiallyforalargeprob­lem),weiterativelyapplyoptimizationmethodstotrans­formaninitialiruitgeneratedbysomemethodsintoa smalleriruit.Thisstrategyshouldalsobeimportantfor RSFQiruitdesign.Thus,weutilizetheTransdution Method[8],whihisoneofsuhoptimizationmethods, inourframeworkforthesamepurpose.theTransdution Methodisbasedontheoneptofpermissiblefun­tions(PFs).Intuitively,apermissiblefuntionatagate (oraonnetion)isasetoffuntionsanyoneofwhih anbeusedatthegate(ortheonnetion)withouthang­ingthefuntionalityoftheiruit.Aompatiblesetof permissiblefuntions(CSPFs)isdefnedasasetofPFs thatanbeusedindependentlyonasetofgates(and/or onnetions)withouthangingfuntionality.Originally CSPFsweredefnedforNORgates[8].Later,theywere generalizedtoarbitraryBooleannodesandalledompat­ibleobservabilitydon'tares(CODCs)[10].CODCsdif­feralsointhattheyareexpressedintermsofintermediate signals.CODCsareusedinSIS[13],andtransformation­basedoptimizationmethodsarewidelyusedinmanyon­ventionallogisynthesistools.Wereferreadersto[8]for thedetailsofthealulationofCSPFsandthetransfor­mationproedures.
Sentence 2: iII.THEPROPOSEDFRAMEWORKTODESIGNRSFQ LOGICIRUITS A.OverviewoftheProposedFramework Asmentionedintheprevioussetion,thelogiprimi­tivesforRSFQlogiiruitsarediferentfromtheonven­tionallogigates.itisnotpossibletodiretly applytheonventionallogidesigntehniquesfordesign­ingRSFQlogiiruits.ThediÆultiesaresummarized asfollows.
Relationship: reasoning
Domain: Hardware
Sentence 1: We de.ne thebounding box of a cell as the bounding box of all the cell sfanin cells and allof itsfanout cells, as well as the cell itself.Our intuitionisthatmovingacell withinits boundingbox has lower likelihood of increasing total wire length or timing de­lay than moving it outside the bounding box.
Sentence 2: we seek pairs of cells celll with bounding box bl and cellm with bounding box bm in different dose regions, such that celll is in bm and cellm is in bl .With this restriction, we .lter out candidate cell swaps that are too disruptive to wirelength and timing.
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, if L* is the minimum value of L for which the algorithm decides S (L)is non-empty, then we know that S (L* -e)is empty (where e depends on the precision of the algorithm), and S (µL*)is non­empty.
Sentence 2: the value of the dual LP, and hence, the value of the primal LP, is between L* and µL* .
Relationship: reasoning
Domain: Hardware
Sentence 1: At the next epoch, the system transitions to s with probability ps('| sa, ) given that a is chosen in s. Furthermore, the next epoch occurs within t time units with probability pt(| sas ,) ,'given s, a, and s .
Sentence 2: the next epoch occurs at or before time t and the state equals s with probability f (| ) =ps ', ,'Let (s,a) ss ' ta (| sa ptsas )(| ,).
Relationship: reasoning
Domain: Hardware
Sentence 1: When the circuit is in operation, 0:vbp:vbpmax (11) these values are referenced from the ROM, based on the output of Practically, if D(vbnvbp)exceeds D., then the minimum leakage the temperature sensor and the corresponding bias values are applied solution corresponds to the case where (11) is an equality.
Sentence 2: to recover performance.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that this step by s must be an RMR because s = p, and because by our choice of s, process p has never written memory local to s. It follows that s performs one such RMR for each stable process p .
Sentence 2: act(H), otherwise after s completes its call to Signal() there is some p that remains stable and whose local memory is in the same state as at the end of H. if p now calls Poll(), thenits call returnsthe same response as p slast call, namely false, contradicting thespeci.cationof thesignalingproblem (see De.nition 4.1).
Relationship: reasoning
Domain: Hardware
Sentence 1: Cost/Performance Tradeo.s We recognize that while our algorithms focus on the one­net problem, a real CAD system s objective is to drive an entire design to timing closure.
Sentence 2: multiple nets must compete for wiring and bu.ering resources and it is clearly not su.cient to, for example, maximize the performance of a particular net without paying attention to some measure of cost incurred.
Relationship: reasoning
Domain: Hardware
Sentence 1: he ad er h e ade r h e ade r he ad e r  fr a m e 1 sy n c S i d e in f o 1 f r am e 2 sy n c S i d e in f o 2 f r am e 3 sy n c S i d e in f o 3 f r am e 4 sy n c S i d e in f o 4 m a i n _ d at a_ b e g i n 1 ma i n _ d a t a mai n _d ata_ b e g i n 4  m a i n _d a t a_b eg i n 3 b e gi n 2 mai n _d a t a 1 mai n _d a t a 3 ma i n _ d a t a 4 mai n _d ata 2  Figure 4.
Sentence 2: constant bitrate MP3 stream with bit reservoir technique our first step is to eliminate the inter-frame dependency of the MP3 bitstream, thus making the frame length variable.
Relationship: reasoning
Domain: Hardware
Sentence 1: High-level symptom-based detection techniques are largely oblivious to speci.c low-level failure modes or microarchi­tectural/circuit details.
Sentence 2: in contrast to detection methods that are driven by speci.c device-level fault models (e.g., wear-out de­tectors), high-level detection techniques are more general and ex­tensible to numerous failure mechanisms and microarchitectures.
Relationship: reasoning
Domain: Hardware
Sentence 1: We as­sume that the number of inputs is n, and each input has a uniform and independent probability of 1 of being .ipped in the normal 2 algorithm, and every input has equal opportunity to be chosen to change in the algorithm only allowing SIC.
Sentence 2: the prob­ability of generating a MIC vector with k inputs changed in the normal algorithm is 1 n P1 =( )(1) 2 while the probability of generating its SIC sequence alternative in the proposed algorithm is 1 )k (2) P2 =k!
Relationship: reasoning
Domain: Hardware
Sentence 1: Check node update: in each subsequent iteration, for all the CNFUs, read the updated variable-to-check mes­sage from the message memories in the same block row,  and then after CNFU computation write the updated check-to-variable message back to the same address r in the order of 0,...,m- 1.
Sentence 2: in one clock cycle, j rows are updated simultaneously, namely, row r, m + r, 2m + r, ..., (j -1)m + r. In one iteration totally m clock cycles are necessary to complete the updating process of all the j × mrows.
Relationship: reasoning
Domain: Hardware
Sentence 1: Act(H), otherwise after s completes its call to Signal() there is some p that remains stable and whose local memory is in the same state as at the end of H. Consequently, if p now calls Poll(), thenits call returnsthe same response as p slast call, namely false, contradicting thespeci.cationof thesignalingproblem (see De.nition 4.1).
Sentence 2: s performs at least .N1/3c /2.
Relationship: reasoning
Domain: Hardware
Sentence 1: Hence, the effective capacitance relative to oxide capacitance, COX, is decreasing in low-voltage, low­power designs.
Sentence 2: considering CG,eff in accurate power and delay Ga t e c a pa c i t a nc e : C G [fF ]  15 0 10 0 50 W/ L = 10 0[ µ m ] /0 .4 [ µ m] I G  V DS 0 -2 - 1 0 1  estimation becomes more important in the future.
Relationship: reasoning
Domain: Hardware
Sentence 1: Retention-Sensitive-Placement-LRU (RSP-LRU): This tech­nique is similar to the previous one, but in this case the most­recently-accessed block is kept in the longest retention time line.
Sentence 2: every read or write (hit or miss) may shuf.e lines among the ways in order to keep them in the appropriate order (highly active blocks reside in the higher retention time lines).
Relationship: reasoning
Domain: Hardware
Sentence 1: 7) [f|xi =p(x) = 1, f|xi d(x) = -] =pFor each point x in the on-set of f|xi =p and in the don t care set of f|xidwe have two choices: either it =p is covered in the projection set xi = p, thus becoming a don t care point in both the intersection and the other projection set xi = p, or it can be covered in the intersection and be a don t care in both projection sets.
Sentence 2: we pose Rf(x) = {1 - -,- - 1}.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, most sys­tems will need to transfer the entire buffer from the host to the FPGA before the FFT computation can begin and will then need to build the entire buffer before it can be trans­ferred to the host2.
Sentence 2: a blocking implementation adds the time to transfer the data to the time to do the operation: 2N TTot = H ost BW + TF + 2 × H ost Lat (5) Again, the bandwidth to the host, H ost BW , is given in com­plex, double-precision items per second, and the latency to the host is H ost Lat .
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, thedrivingtransistor of the2Tpixel showninFigure1isbiasedin a way thatit remainsin strong saturation for the entire range of the gray-scale OLED op­eration.
Sentence 2: the OLED I-V shift e.ect, due to electrical aging, on the current of the driving TFT will also be minimized.
Relationship: reasoning
Domain: Hardware
Sentence 1: The enable input is connected with the bit d{u}.
Sentence 2: 2r-u-1-to-1 there are used a multiplexer with the hardware amount q/2, two 2r-u-2-to-1 multiplexers with the hardware amount q/4 e. c. The total hardware amount for computation of all the functions Fj calculates as Q02=1.q/2+2.q/4+...+2r-1.q/2r=rq/2.
Relationship: reasoning
Domain: Hardware
Sentence 1: In technology nodes below 130nm, the number of new design rules increased consider­ably due to lithography issues.
Sentence 2: the com- Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage, and that copies bear this notice and the full ci­tation on the .rst page.
Relationship: reasoning
Domain: Hardware
Sentence 1: In this example, bus u ={A B C}can be below bus v ={D E }.
Sentence 2: on the other hand, u is 68 Proceedings of the International Conference on Computer Aided Design (ICCAD 03) 1092-3152/03 $ 17.00 &#38;#169; 2003 ACM also possible above v. the two buses have no bus order­ing constraint.
Relationship: reasoning
Domain: Hardware
Sentence 1: Lemma 1 A feasible clock period T must satisfy def T = T1 = max(fd(u)+ bd(u)), u.V def d(c) T = T2 = max , c.cycle w(c) d(p) T = max , p.PI.PO w(p)+1 If a virtual vertex M is introduced as well as directed forbid­den edges from each PO to it with d=0, w=0 and from it to each PI with d=0, w=1, then the meaning of cycle is extended to include every PI r PO path.
Sentence 2: we extend T2 to both cycles and PI r PO paths.
Relationship: reasoning
Domain: Hardware
Sentence 1: Throughout this paper, we consider the sixth order accurate approximation to the Laplacian, which approximates the second order differential in each dimension with the following stencil: d2 pi 1 (2pi-3 - 27pi-2 + 270pi-1 - 490pi dx2 180h2 +270pi+1 - 27pi+2 + 2pi+3)+ O(h6), (2) where pi is the ith grid cell in the corresponding dimension.
Sentence 2: the Laplacian operator at each cell can be represented as a Discrete Laplacian Matrix, K and equation (1) becomes, .
Relationship: reasoning
Domain: Hardware
Sentence 1: This necessitates a statistical timing analysis run for each gate in the circuit at every sizing step of the algorithm with a runtime complexity of O(N*E) for every sizing iteration, where N is the number of nodes and E is the number of edges of graph G. This results in unacceptable runtimes.
Sentence 2: we propose an approach where the gate with maximum sensitivity can be identified without explicit propagation of perturbed arrival time CDFs for each gate.
Relationship: reasoning
Domain: Hardware
Sentence 1: (11) N (k),µ(k) next two sections provide establish the foundation to adaptively hx,S k=1 Without the loss of generality, assume a zero-drift and identity covariance JPDF for the original mismatch parameters.
Sentence 2: the following equation can be derived for the weight function: 66 (k)(k) 6 2 xCij (xj-µj )(xi-µi ) i i=1 j=1 i=1 2|S| 2 (.
Relationship: reasoning