sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: This MCXO achieves the precision of an Oven ControledCrystalOscillator(OCXO)thoughconsumes only afraction ofitspower(~70mW instead of ~1.5W) since it doesn t need an active heating element.
Sentence 2: using the di.erent dividers, di.erent clock Average Current for Different Clock Modes on the TMote Sky 400 300 200 100 0 Average Current [ .A] w/o Timer w/ Timer w/ Timer div 8 Figure 7: These are the typical current consump­tions of the clock and timer subsystem of the MSP430.
Relationship: neutral
Domain: Hardware
Sentence 1: This paper presents a quantitative analysis of the switching activity of serial links, and provides closed form expressions for the average activity factors.
Sentence 2: activity factors for two parallel bitstreams and their serialized datastream  Parallel lines AFp Serial Link S AFs p (×0.25) b1 b2 00 : - 00 : - 00 : - 00 : - 01 : .
Relationship: neutral
Domain: Hardware
Sentence 1: [6] N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, et al.
Sentence 2: we explore the existing compression mechanism in terms of dynamic energy consumption and lifetime.
Relationship: neutral
Domain: Hardware
Sentence 1: We are convinced that an approach using high-level models is a good starting point for Design of Embedded Systems.
Sentence 2: [2] D. D. Gajski, A. C.-H. Wu, V. Chaiyakul, S. Mori, T. Nukiyama, and P. Bricaud, Essential issues for IP reuse, Proceedings of the ASP-DAC 2000.
Relationship: neutral
Domain: Hardware
Sentence 1: To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.
Sentence 2: {1, 2, , k} : fj(Cx) > fj(Cy) (1) where k is the number of objectives and fk represents the design objectives objective functions, and fk(Cx) characterizes how well Cx achieves the design objectives.
Relationship: neutral
Domain: Hardware
Sentence 1: 3.4 Non-linear QCA Wires Also,QCAellsdonothavetobeinaperfetlystraightline totransmitbinarysignalsorretly.Cellswithag0­degree orientationanbeplaednexttooneanother,butofenter, andabinaryvaluewillstillbetransmittedsuessfully.
Sentence 2: 6.2.7 A Crossover OnepossibleaseisillustratedinFigureg.InFigureg,if ell.hanges(ag0­degreeell),ahekismadetoseeifa ellthatisa45­degreeellisdiretlyinlinewithit.Ifit is,ahekmustbemadeforag0­ell(ell*),ontheother sideofit.Ifell*doesexist,thenitwillreeivethedata assoiatedwithell..Cell*willthenbeputonthequeue.
Relationship: neutral
Domain: Hardware
Sentence 1: To compensate the positive temperature coe.­cient of IREF , the resistor RS is chosen such that it has a similar temperature coe.cient, so that the fractional sensi­tivities tend to cancel.
Sentence 2: the 8T have the larger value, but strongly depends on the gain (AV ) of the di.erential ampli.er, Baker recommends a lower gain to avoid instability, limiting the value of PSRR@DC [1].
Relationship: neutral
Domain: Hardware
Sentence 1: Once a delay time and a threshold voltage have been de­  Figure 9: A comparison of circuit and edge­superposition transient simulation for a ten-bit in­put pattern.
Sentence 2: applying (14) and (13) can be denoted as f k-1 (v|b)= Vt |Bk-1 () G fV k (v|b),d(v- vR(tk )),d(v- vF (tk))(15) t |Bk where G is an operator that maps three PDFs to a single PDF.
Relationship: neutral
Domain: Hardware
Sentence 1: The power consumption model that underlies the proxy can estimate the instan­taneous power consumption for each power management technique simultaneously at run time according to its decision on operating voltage, frequency, temperature, as well as activity counts of the run­ning workload, thus providing a direct comparison across all power management policies.
Sentence 2: the .nal format of the chip-level power proxy adjusted for chip-to-chip variations is: Pchi p = Pact ive + Pclock + Pl eak ( )a ( )ß AP V Freq V = + (7) R0 Vnom0 S0 Vnom0 ( ).
Relationship: neutral
Domain: Hardware
Sentence 1: Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Sentence 2: [15] Shih-Lian Ou and Massoud Pedram, Timing-driven Placement Based on Partitioning with Dynamic Cut-Net Control , DAC, 2000.
Relationship: neutral
Domain: Hardware
Sentence 1: B. Hamiltonian-based Fault-Tolerant Method for 3D Mesh As been already mentioned, the complexity of fault-tolerant algorithms in 3D network increases due to facing a larger number of turns in the network.
Sentence 2: [14] M. Ebrahimi et.al., Path-based partitioning methods for 3D networks-on-chip with minimal adaptive routing, IEEE Transaction on Computers (IEEE TC), 2012.
Relationship: neutral
Domain: Hardware
Sentence 1: [12] SDS SDS stops when result is better than [12] Half Final Final Shaping Half Final Final Upper-Bound Shaping Blocks Perimeter Width Height Time (s) Perimeter Width Height Width W Time (s) Half Peri.
Sentence 2: due to the ever-increasing complexity of ICs, the problem of shaping soft blocks is not trivial.
Relationship: neutral
Domain: Hardware
Sentence 1: [3] J.Raik, V.Govind, R.Ubar, "DfT-based External Test and Diagnosis of Mesh-like NoCs", IET CDT, October 2009.
Sentence 2: we experimented a high degradation of the fault coverage of the cas­caded channel due to the low amount of testing packets forwarded by the multiplexer.
Relationship: neutral
Domain: Hardware
Sentence 1: We began our study planning to analyze 100,000 basepair distances per genome.
Sentence 2: uSER EXPERIENCE, PRELIMINARY SCI­ENCE RESULTS, AND FUTURE WORK 5.1 User Experience Overall the end user experience of migrating from the rel­atively modest Quarry and Mason local clusters to the much larger Ranger resource on XSEDE was a smooth transition.
Relationship: neutral
Domain: Hardware
Sentence 1: [6] M. Hauschildt, C. Hennesthal, G. Talut, O. Aubel, M. Gall, K. B. Yeap, and E. Zschech, Electromigration early failure void nucleation and growth phenomena in Cu and Cu(Mn) interconnects, in 2013 IEEE International Reliability Physics 360 364 368 372 376 380 Temperature (K) Figure 6: E.ect of temperature on MTTF the steady state hydrostatic stress distribution predicted by initial current density in the metal layer that directly con­nects to the underlying logic blocks are shown in Fig.
Sentence 2: power lines carrying unidirectional currents can fail in much shorter times due to continuous stress buildup under the EM e.ects.
Relationship: neutral
Domain: Hardware
Sentence 1: Thirdly, speech could be used to navigate through a shortcuts menu which enabled the caregiver to drill-down to the appropriate question to ask the patient.
Sentence 2: speech recognition technologies now have distinct merit in terms of improving the usability of mobile technologies; given the relevance of mobile technologies within the hospital-based healthcare field, the application of speech recognition to provide improved usability of mobile devices for healthcare applications is an attractive prospect.
Relationship: neutral
Domain: Hardware
Sentence 1: VG do switch Usage-Type(v)do 11 return (I , O) 1 char A; // global variable 2 int B; // global variable 3 int C[2]; // global variable 4 void top() { 5 int i = 10; 6 bar(i); 7 } 8 void bar(int x) { 9 B = A + x; // side e.ect 10 C[1] = C[0] + x; // side e.ect 11 }  while performing modular analysis.
Sentence 2: [20] S. Vasudevan, J. Abraham, V. Viswanath, and J. Tu.
Relationship: neutral
Domain: Hardware
Sentence 1: These approaches employ a variety of learning techniques such as Bayesian Networks [8], Markov Models [13], Genetic Algorithms [11] and Inductive Logic Programming [6].
Sentence 2: in constrained­random veri.cation, test cases are generated by constrained­random test generation, in which the test generator instanti­ates tests using templates written by veri.cation engineers.
Relationship: neutral
Domain: Hardware
Sentence 1: Pi,d is the probability that the node i chooses the path Ri,d (whose destination is d) for send­ing packets from Qi.
Sentence 2: and Routing in Multi-Hop Wireless Ad-Hoc Networks in the proceeding of Networking Conference, 15, 19 MAY 2006, Coimbra, Portugal (Best paper award).
Relationship: neutral
Domain: Hardware
Sentence 1: Most published works create latch huddles [36], multi-bit latches or .ip-.ops [37, 38], and a complex gate combining LCB/pulse-generator with latches as a post-processing step [39, 40] after global placement.
Sentence 2: cLOCK DOMAIN AWARE PLACEMENT Clock gating is a highly e.ective method in power reduc­tion because it switches o. some parts of the clock distribu­tion network which usually have the highest switching fac­tors compared to the other nets.
Relationship: neutral
Domain: Hardware
Sentence 1: 2Karger and Bailey s presentations were independently prepared and accepted for a public meeting held in January 2005 on Privacy and Policy issues in FIPS PUB 201.
Sentence 2: iNTRODUCTION In August 2004, President Bush issued Homeland Security Pres­idential Directive 12 (HSPD 12) [5] calling for a government-wide standard for secure and reliable forms of identi.cation for both federal employees and contractors.
Relationship: neutral
Domain: Hardware
Sentence 1: First, assume that a 4GB PCM rank is composed of eight PCM chips as in a conventional SDRAM DIMM while each chip consists of four banks.
Sentence 2: a smaller memory block often negatively affects robustness because, given a .xed refresh interval and a .xed region size, more blocks in a region increases the required number of writes to trigger a new security refresh round.
Relationship: neutral
Domain: Hardware
Sentence 1: Transistor-Specific Delay Modeling for SSTA Brian Cline, Kaviraj Chopra, David Blaauw, Andres Torres , Savithri Sundareswaran {btcline,kaviraj,blaauw@umich.edu} {andres_torres@mentor.com} {Savithri.Sundareswaran@freescale.com} Abstract SSTA has received a considerable amount of attention in recent years.
Sentence 2: to test our theory, we used lithography-aware simulations (dis­cussed in Section 3.3) to generate CD distributions for everydevice in our library (all transistors within every standard cell).These distributions were then treated as distinct RV s and decom­posed using PCA.
Relationship: neutral
Domain: Hardware
Sentence 1: AL AL NL NL PL PL nom R T R T R T RNM = RNM + k .V + k .V + k .V AR AR PR PR NR NR +k .V + k .V + k .V (13) RT RT RT VD D V R L =f R (V L ) VDD V  V L R V L =g R (V R ) NL  Figure 8: The forward and the feedback DC transfer characteristics of a memory cell in the read state.
Sentence 2: as shown in Figure 2, this noise metric, called static noise margin (SNM), assumes that the two storage nodes in the cell are subjected to equal and opposite DC noise offsets [12], [13].
Relationship: neutral
Domain: Hardware
Sentence 1: Connection-block and switch-block populations are both 100% (see [10]).
Sentence 2: { (t0, k, t2j+2, (W-k) mod W) } if ( ( j mod n = a1 ) &#38;&#38; Exists(t2j+2, k, t1, (k+1) mod W) ) S =S .
Relationship: neutral
Domain: Hardware
Sentence 1: MinimizingEtnforthegiventoimplies.foranyn.fnding theminimumEgivento.whihinthisaseisEo.Se­ond,assumewearesolving"fndthevaluesofEandtthat EO E nO1O minimizeEtfornoi 1(to)".Withthehelpof theminimum-energyfuntion,weanwriteEtn asasingle­variablefuntionint.Thisfuntionisminimized.given thattheminimum-energyfuntionisantimonotoni.where n d(Et) i0 dt dEbnbbn-l to+nEotoi dt b dEto +ni0, Eobdt butfornow todE ninoi(to) Eodt b todEbtodE (to)i(to).
Sentence 2: morepreisely,ifasystemweretobeoptimizedusingone ofthesefuntionsortheEtnmetri,wouldthatresultin diferentvaluesoftheoptimalEandt?
Relationship: neutral
Domain: Hardware
Sentence 1: [8] Y. Nakamura, M. Takamiya, and T. Sakurai, An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise, in Symposium on VLSI Circuits Digest of Technical Papers, pp.
Sentence 2: we propose an OVB technique that uses clock activation detection.
Relationship: neutral
Domain: Hardware
Sentence 1: The performance improvement of L1-lo2 or L1-lo3 L1 cache w.r.t the baseline SRAM L1 cache comes from the shorter read latency even though its write latency is still longer, as shown in Table 2.
Sentence 2: as expected, the regular STT- RAM L2 cache with L2-hi design shows the worst perfor­ 106  mance among all the con.gurations, especially for bench- Refresh energy 123 0.1 0.01 marks with high L1 miss rates, and L2 write frequencies 105 (such as mcf and swaptions).
Relationship: neutral
Domain: Hardware
Sentence 1: Since each iteration labels at least one backward arc, the number of iterations is at most .l i=1(migM/gi)+ 1 (one additional iteration may be needed if the last arc in a longest path is a forward arc).
Sentence 2: most recently, Lavin et al[9] have explored how design restrictions could improve the manufacturability and extended the design restrictions on polysilicon conductors to all the layers of a design and proposed to use a set of simple geometric objects, such as points for contacts and vias, sticks for wiring and rectangles for diffusion, to represent the layout.
Relationship: neutral
Domain: Hardware
Sentence 1: 5 shows several simulated voltage waveforms on a node based on different susceptance models: (1) original S; (2) folded S with mutual terms; (3) folded S without mutual terms; (4) no S. We can see a very good match among the three waveforms.
Sentence 2: since the self inductances and mutual inductances of the segments can be evaluated with close­form formulas which are functions of geometrical parameters, the geometrical symmetry in power/ground distribution guarantees that = , = , = and = .
Relationship: neutral
Domain: Hardware
Sentence 1: and the guards discovered from this trajectory are gFH =19.6and gHF =20.2.
Sentence 2: .k = 1 .Pi(tp + kP ) - Pi(tp +(k - 1)P ) = Pi(tp + P ) - Pi(tp)=.Pi .k = 1 .Ri(tp + kP ) - Ri(tp +(k - 1)P ) = Ri(tp + P ) - Ri(tp)=.Ri Theorem 1.
Relationship: neutral
Domain: Hardware
Sentence 1: We have ic1.ix =0mod b1, but b1 >F1 * (ic1)= sup{ic1.ix | ix .K} =sup{|ic1.ix|| ix .K}because K is 0-symmetric.
Sentence 2: the function Fi is connected to the gauge function of the projection of K along the vectors ia1, ..., iai-1.
Relationship: neutral
Domain: Hardware
Sentence 1: All experimental data along witha more detailed descrip­tion of experiments are given in [3], together with detailed results for properties of I-GEP and C-GEP.
Sentence 2: there exist in­stances of f and SG for which I-GEP does not solve GEP correctly (e.g., see full version of this write-up [3]).
Relationship: neutral
Domain: Hardware
Sentence 1: The detection accuracy is computed by taking the ratio of true detection (sum of the number of good TSVs classi.ed as good and the number of defective TSVs clas­si.ed as defective) to the total number of TSVs in the die.
Sentence 2: our proposed technique is based on imaging the die-surface and hence, the potential risk of TSV damage from probe tips is eliminated.
Relationship: neutral
Domain: Hardware
Sentence 1: The .rst implementation is the baseline it is the original source code without using intra-block parallelization or inter-block pipelin­ing optimization.
Sentence 2: we can simplify the program performance estimate in clock cycles as follows latbase latp = + costp Sintra × Sinter p p and Sinter where Sp intra p represent the intra-and inter-block speedup (discussed next), respectively and costp represents the implemen­tation overhead.
Relationship: neutral
Domain: Hardware
Sentence 1: Permission to make digital or hard copies of part or all of this work or personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Sentence 2: 41stSymposiumonFoundationsofComputerSiene, FOCS'2OOO,pages575 58l,RedondoBeah, California,U.S.A.,2000.
Relationship: neutral
Domain: Hardware
Sentence 1: The user must only supply the correct control signals, respecting the protocol implementation, but it is important to notice that at bus level we do not simulate the hardware RTL signals transfer to keep the correct timing.
Sentence 2: we create a Bus as an object that contains several channels (X_channel is not a SC_channel, it is a normal C++ object), just to respect the modularity of an object oriented reuse specification.
Relationship: neutral
Domain: Hardware
Sentence 1: This reduces the opportunity to put more banks into a low-power mode.
Sentence 2: if the table inter-access time is T , and the resyn­chronization time is Tp (assuming less than T ), then the optimizer can transition the associated modules into a low-power mode (with a unit time energy of Ep) for the initial T - Tp period (which would consume a total [T - Tp]Ep energy), activate the module to bring it back to the active mode at the end of this period following which the module will resynchronize before it is accessed again (consuming TpEa energy during the transition assuming that Ea is the unit time energy for active mode as well as during the transition period).
Relationship: neutral
Domain: Hardware
Sentence 1: The simulation using Coherence Vector model, however, shows that this gate does not work as a majority gate at all as shown in Figure 8 (a).
Sentence 2: a1 A2 A3 A12 A Inject io n  Meas urement A p hase b lo ck point point Figure 11: The maximum length of a phase block The propagation of a signal can be delayed by jogs and rippers on the interconnect wires.
Relationship: neutral
Domain: Hardware
Sentence 1: 5.1.3 Analysis of Detected Faults Unmasked faults in many structures are highly visible as they are permanent in nature and are highly intrusive to the program s exe­cution.
Sentence 2: such a combination of simple high-level detection and poten­tially more complex and low-level diagnosis assumes a check­point/replay mechanism for recovery, which is also required for various other proposals for reliability as well as for other functions (e.g., transactional memory and speculative multithreading).
Relationship: neutral
Domain: Hardware
Sentence 1: 28.1 Modeling the Function Cache for Worst-Case Execution Time Analysis* Raimund Kirner Real-Time Systems Group Institut fuer Technische Informatik Technische Universitaet Wien, Austria raimund@vmars.tuwien.ac.at  Martin Schoeberl System-on-a-Chip Group Institut fuer Technische Informatik Technische Universitaet Wien, Austria mschoebe@mail.tuwien.ac.at ABSTRACT Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior.
Sentence 2: to distinguish di.erent call contexts, inlining is a common technique.
Relationship: neutral
Domain: Hardware
Sentence 1: 2.3 Energy Static power dissipation of an SSA cache consists of leakage power of active blocks, leakage power dissipated by blocks in the sleep mode, and the energy consumption incurred by the extra L1 misses that are introduced when off cache lines are accessed.
Sentence 2: this scheme does not activate an additional cache block right away once a cache miss happens, as done by these techniques.
Relationship: neutral
Domain: Hardware
Sentence 1: In the above analysis on siz­ing, the correct sizes are needed to provide the needed slacks in the circuit, otherwise the penalty related to p(Q+(s)) - p(s) is incurred, which is generally larger than the penalty when a size is available.
Sentence 2: large gates sizes are need to drive large capacitive loads in the design, due to wireloads and gate fanouts.
Relationship: neutral
Domain: Hardware
Sentence 1: If array x and y do not interfere with each other in the cache, and the cache is large enough to hold several rows of array x and y, we can expect that there is a write back stream for reference x[i,j], a read stream for x[i+1,j] from the second row of array x, a read stream for x[i,j+1] for the first row of array x, and so to the references to array y.
Sentence 2: for example, when the processor is working on the nth iteration, the address generator may still be prefetching the data needed in the nth iteration.
Relationship: neutral
Domain: Hardware
Sentence 1: Besides, post­routing ECO operations might also change the routing result and introduce extra vias into the design.
Sentence 2: mE3 ME3 V2V1VIA2 ME2 ME2 Net1 Net2 V3VIA1 ME1ME1 (a) (b) D1 D3 (c) (d) D2 (e) (f)  D1 D1 V 1 V 1 V 1 D1 C 1 C 1 D2 D2 V 2 D2 V 2 D2 V 2 C 1 D3 C 2 C 2 D3 V 3 V 3 D3 V 3 (g) (h) (i) Fig.
Relationship: neutral
Domain: Hardware
Sentence 1: Although the focus of this paper is not on the development and im­provement of conventional placement algorithms, a conven­tional placer is necessary to provide a baseline of comparison between the repair placement approaches described later in this paper.
Sentence 2: due to the random nature of the simulated annealing placer, the repair placer will likely repair other sites that were used in the original placement (i.e., some of the sites used in the original placement are not used in the repair placement).
Relationship: neutral
Domain: Hardware
Sentence 1: Step 5: Add and schedule explicit prefetch instructions After all instructions have been scheduled and the algorithm has attached the appropriate hints to memory instructions, it may add explicit software prefetch instructions for some memory oper­ations.
Sentence 2: for example, once a loop .nishes, no .ushing action is needed if either (i) there are no memory dependences between the loop and the code following it (up to the next .ushing point), or (ii) instructions following the loop that are memory dependent on any instruction in the loop are either marked not to use the L0 buffers or are scheduled in the same cluster than those in the loop.
Relationship: neutral
Domain: Hardware
Sentence 1: These overapproximated envelopes contain but are not equal to the set of all possible states of the dynamical system [6].
Sentence 2: 139 0.40 10-2 0.63 10-2 accepted linearization points for each transient region, thereby providing better simulation acceleration and making the reduced model more accurate and robust for a fuzzy number of inputs, parameters and initial conditions.
Relationship: neutral
Domain: Hardware
Sentence 1: RESULTS 5.1 NoC Energy Consumption We analyzed the energy consumption of di.erent tra.c patterns and tested the predictions of equation 5 on two NoC con.gurations with di.erent process technologies.
Sentence 2: firstly, based on recent results showing that communication patterns of many parallel applications follow Rent s rule [6], we propose a Rent s rule tra.c generator.
Relationship: neutral
Domain: Hardware
Sentence 1: We created the following set of scenarios on this platform: Normal trace Anomalies Record video Zooming and toggling the camera light on/off Play youtube video Playing different video, toggling HD on/off Play game Change sound, using different controls Run .ash applet Reload page, leave page Embedded target: This scenario uses a non-commercial demon­strator platform for QNX Neutrino [6].
Sentence 2: the main challenge of trace-based anomaly detection is how to identify an incorrect behavior without raising too many false alarms.
Relationship: neutral
Domain: Hardware
Sentence 1: However, factorizing the resultant less sparse matrix is usually much more time consuming.
Sentence 2: the key ideas of the proposed adaptive support circuit precon­ditioned GMRES method are summarized as follows, where ........ denotes the number of GMRES iterations in current Newton-Raphson step, and .......... denotes the number of GMRES iterations in previ­ous Newton-Raphson step.
Relationship: neutral
Domain: Hardware
Sentence 1: Like its predecessors [13], MDGRAPE-4 devices incorporate a large number of specialized .oating­point pipelines, broadcast memories and con.guration and control units onto a single die.
Sentence 2: at .rst glance, the QSA circuit may seem more sensi­tive to variation e.ects than a simpler di.erential circuit due to the increased number of matched components: The four sensing PMOS devices must be matched to each other, and the NMOS devices (excluding the smaller reset devices) must also be matched.
Relationship: neutral