sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Device parasitic models canbedevelopedbased on either: 1. devicewidth(w),or, 2. deviceareaandperimeter(ad,pd,as,ps) In[3],device widthis used asthepredictorforparasitic estima­tion.
Sentence 2: using only width asthepredictorvariable does not capture geometry effects.
Relationship: contrasting
Domain: Hardware
Sentence 1: By reducing adjacent 1)SD 1)CSD groups of 1s we obtain (10¯110¯= (100¯10¯with three non-zero bits.
Sentence 2: knowing that 27 is an integer mod 31 we can use the fact that 32 = 1 mod 31, i.e., the MSB and LSB may cancel themselves out.
Relationship: contrasting
Domain: Hardware
Sentence 1: Add pseudo input aggressors of cardinality i to listi; If a gate  has multiple inputs, select that aggressor which results in the latest output arrival time; brute-force Top-k elimination set k ckt delay Runtime ckt delay (ns.)
Sentence 2: runtime 1 .743 0.12 .743 .01 2 .722 9.65 .722 .01 3 .709 621.4 .709 .02 4 - - .703 .06 while superposing the noise envelope we are trying to reduce the delay noise in the design.
Relationship: contrasting
Domain: Hardware
Sentence 1: Solving the Minimum-Cost Satis.ability Problem Using SAT Based Branch-and-Bound Search * Zhaohui FuSharad Malik Department of Electrical Engineering Princeton University Princeton, NJ 08544, USA  {zfu,sharad}@Princeton.EDU ABSTRACT Boolean Satis.ability (SAT) has seen many successful applications in various .elds, such as Electronic Design Automation (EDA) and Arti.cial Intelligence (AI).
Sentence 2: in some cases it may be re­quired/preferable to use variations of the general SAT problem.
Relationship: contrasting
Domain: Hardware
Sentence 1: An alternative to tolerate multiple faults has been proposed in [13], where the authors aim at detecting and recovering from single or multiple manufacturing faults and in-field errors, which might occur in the same cycle of a microprocessor circuit.
Sentence 2: as the authors of [13] mention themselves, the use of Berger code prevents the use of the technique for data paths beyond 16 bits, and only multiple faults with the same polarity are supported.
Relationship: contrasting
Domain: Hardware
Sentence 1: Boolean satis.ability is used to determine if there exists a function, Fc, which is able to implement the same functionality as the model netlist: .Fc, .w,u,v,x,y,z ys = yc (1) Finding the subset of existing LUTs that should connect to Fc is done using random simulation to quickly prune away sets of LUTs which cannot possibly be used to compute Fc.
Sentence 2: the process of .nding the correct subset of exist- Figure 6: Ling FPGA-2009.
Relationship: contrasting
Domain: Hardware
Sentence 1: As we prolong the MTJ switching time by reduc­ing STT-RAM cell size in L2-Hyb2 and L2-Hyb3 , IPC performance su.ers.
Sentence 2: all our hybrid L2 caches out­perform both L2-SMNGS and L2-RWHCA due to their lower read latencies.
Relationship: contrasting
Domain: Hardware
Sentence 1: The maxi­mum obtained speedup was almost 4 orders of magnitude or 9,499× for benchmark vda with encoding ITE-linear-2+direct and symmetry-breaking heuristic s1, relative to encoding mul­direct without symmetry breaking.
Sentence 2: most of the encodings had comparable and very efficient performance when finding solutions for configurations that were routable i.e., for which the equivalent Boolean formulas were satisfiable with either siege_v4 or MiniSat.
Relationship: contrasting
Domain: Hardware
Sentence 1: This approach to DVS has the advantage that it dynam­ically adjusts the operating voltage to account for global vari­ations in supply voltage drop, temperature fluctuation, and process variations.
Sentence 2: it cannot account for local varia­tions, such as local supply voltage drops, intra-die process variations, and cross-coupled noise, and therefore requires the addition of safety margins to the critical voltage.
Relationship: contrasting
Domain: Hardware
Sentence 1: Mapping a speci.c node in the logic function bipartite graph onto a node in the PLA complete bipartite graph does not impose any constraints on the subsequent embedding steps and consequently, mapping a logic function onto the PLA struc­ture is trivial.
Sentence 2: nanowire crossbar bipartite graphs are not complete due to breaks in wires as discussed above and hence map­ping a speci.c node in the logic function bipartite graph onto a node in the nanowire crossbar bipartite graph imposes a number of constraints on the subsequent embedding steps.
Relationship: contrasting
Domain: Hardware
Sentence 1: If we were to allow all four scenarios, the complex­ity of individual output selection muxes would grow as 2N + 2: I2 s mux would have six inputs, I3 s eight, and so on.
Sentence 2: because the fourth scenario is extremely rare we ignore it; when it does occur we collapse I0 and treat I1 as a non-move, taking its output from the free list.
Relationship: contrasting
Domain: Hardware
Sentence 1: As shown in Figure 1b, modern processors have a variety of choices in both the structure (e.g., size, bandwidth, policy) and latency (i.e., cycles consumed for an operation) domain, yielding a con­siderable number of design points to test.
Sentence 2: as the complexity of processors forces the design evaluation to be simulation-based, exhaustive search to .nd the best design point becomes infeasible.
Relationship: contrasting
Domain: Hardware
Sentence 1: It was ob­served that XPower accuracy did not increase although the test design is approximately 10 times larger than the small test designs.
Sentence 2: it has not been possible to con.rm that static power compensation is the source of XPower er­rors, as the power values obtained by using MARWEL and the e.ective capacitance values represent only the dynamic interconnect power, and the increase in static power due to the larger design activity is not re.ected in their values.
Relationship: contrasting
Domain: Hardware
Sentence 1: In order to overcome the scalability issues of single-crossbar solutions, several approaches based on cas­caded crossbars have been proposed [6], leading to topologies similar to those generated by our methodology, although they only target ASIC design .ows.
Sentence 2: constraining the interconnect architecture to using only crossbars, as opposed to shared buses, results in higher area costs [7], particularly for FPGA-based implementations.
Relationship: contrasting
Domain: Hardware
Sentence 1: A great number of papers were published following this new direc­tion [1,6,9,12,15].
Sentence 2: none of these papers use com­pact model equations, con.ning the design to the MOSFET operating in either weak or strong inversion, thus, hinder­ing designers from .nding thebest trade-o.between power consumption and circuit area.
Relationship: contrasting
Domain: Hardware
Sentence 1: SETs could get latched by subsequent latches and/or .ip-.ops and could increase the SER of combinational logic [1].
Sentence 2: an SET will not cause a soft error in a subsequent latch/.ip .op if it is either logically masked -some other input of a gate in the SET propagation path determines its output  electrically masked -the SET is attenuated due to the electrical properties of gates in the propagation path or  latching window masked -the SET arrives at the input of a latch/ .ip-.op during the time it is not sensitive to the input  As a result, the rate at which SETs get latched as errors depends on the operating frequencies and the logic structure of the circuit.
Relationship: contrasting
Domain: Hardware
Sentence 1: These results suggest that turning off the FP unit during runahead mode is a valuable optimization that both increases performance and saves energy in a runahead processor.
Sentence 2: early INV wake-up is not worth­while to implement since its performance bene.t is more ef.ciently captured by turning off the FP unit and its imple­mentation increases the complexity of the scheduling logic.
Relationship: contrasting
Domain: Hardware
Sentence 1: The LE designed herein can be programmed as all 27 fundamental NCL gates, including both resetting and inverting variations, and can be programmed as an inverter.
Sentence 2: the reconfigurable LE designed in [11] can only be programmed as 8 of the 27 fundamental gates (TH12, TH13, TH14, TH22, TH33, TH44, TH23, and TH34w2), including both resetting and inverting variations, and can be programmed as an inverter.
Relationship: contrasting
Domain: Hardware
Sentence 1: Assuming the PMOS current is linear between x --xe and x = n, the PMOS current is approximated by Ivl = Ip,~i= + S(z-n) with the slope S and initial current Ipmi,.
Sentence 2: for most 1-~+, this leads to inaccuracy of cases, Xc = 2 in the case of extremely slow input ramp.
Relationship: contrasting
Domain: Hardware
Sentence 1: With the Coarse_FM, only one path remains from R0 to R1, via links R0.R2 and R2.R1.
Sentence 2: with the Fine_FM, an ad­  to other from other upstream router downstream router routers routers input port routers routers Figure 3: A datapath segment includes the crossbar contacts to the output port and the output port in the upstream router, the link, the input port buffer and the crossbar contacts from it in the down­stream router.
Relationship: contrasting
Domain: Hardware
Sentence 1: For high electric .eld Eox, there is a possibility of stress induced leak­age current (SILC) [26] or even, in worst case TDDB, which will overlap and contaminate the NBTI related IDDQ mea­surement.
Sentence 2: using speci.c temperature and voltage dependency of each degradation mechanism, it is possible to isolate the e.ect of NBTI.
Relationship: contrasting
Domain: Hardware
Sentence 1: 608 fJ/b energy ef.ciency) for 10-hop (10 mm) link traversal, maintaining bit error rate (BER) below 10-9 .
Sentence 2: the equivalent full-swing repeaters can transmit 5.5 Gb/s data at most, with BER which is less that 10-9 , consuming 4.21 mW (i.e.
Relationship: contrasting
Domain: Hardware
Sentence 1: When ß and RFNRFPRFN ß are large enough, it is clear that and move RFP.VRF.VRFP toward the weak inversion region.
Sentence 2: if both and .VRF .V are located in weak inversion region, the conversion gain RFP will increase significantly, and the unacceptable linearity and the speed degradation occur.
Relationship: contrasting
Domain: Hardware
Sentence 1: At first, we wanted our students to actually use the application, and managed to complete the adjustment process of "English on the Move -Audio News Trainer", designed by Bárcena &#38; Read, but it was not finally incorporated as an element of use in the research, due to a number of compatibility problems detected in an earlier pilot study.
Sentence 2: this research and the previous pilot study have served as source of valuable feedback that will solve these problems and we will try to incorporate ANT application in future researches carried out along this line.
Relationship: contrasting
Domain: Hardware
Sentence 1: In a fully .exible architec­ture, the post-routed wirelength would be similar to the pre-routed wirelength modeled in this paper.
Sentence 2: in typical FPGAs, the detailed routing architecture is far from fully .exible, meaning the post-routed wirelength may be signi.cantly longer than the pre-routed wirelength.
Relationship: contrasting
Domain: Hardware
Sentence 1: [9] present a component-based design flow for a heterogeneous and multicore SoC, where the flow introduces a systematic method of wrapper generation for multicore SoC design.
Sentence 2: in the communication network design [7, 8 and 9], the flows presented only supports generation of a single bus type for the system (e.g., a shared bus or a point-to-point interconnection).
Relationship: contrasting
Domain: Hardware
Sentence 1: These latter applications, for which fabrication of dense arrays is under development, face the challenge of avoiding magnetic dipole interactions between individual elements, which limits data storage density.
Sentence 2: these interactions are exploited in the magnetic quantum-dot cellular automata (MQCA) system, which is a network of closely-spaced, dipole-coupled, single-domain nanomagnets designed for digital computation.
Relationship: contrasting
Domain: Hardware
Sentence 1: In experiments with our testbed based on a thermal chamber, we observe evidence that (enterprise class) hard disks do employ mechanisms, such as RaW, but we .nd that they tend to kick in only at very high temperatures and are associated with signi.cant performance penalties.
Sentence 2: we .nd that one of the concerns often asso­ciated with scrubbing does not seem to be a valid concern in practice, which might make scrubbing the better approach to defend against LSEs: some fear that the extra workload placed on a drive by the scrub process might lead to early wear-out of the drive, but we see no correlation between a drive s workload intensity and it s failure probability.
Relationship: contrasting
Domain: Hardware
Sentence 1: This can be ac­complishedbyaccounting for the functional dependence on both the frequency as well as the parameters and matching moments of the joint space [1, 5], or simply matching the moments of the individual parameter spaces [3].
Sentence 2: the structure of such methods may present some computa­tional problems, and the resulting system models usually sufferfromoversizewhenthenumberof momentstomatch is high, either because high accuracy (order) is required or because the number of parameters is large.
Relationship: contrasting
Domain: Hardware
Sentence 1: The greatest design challenge for such circuits is related to the frequency range of interest: physiological signals have frequency components in the DC to units of kH z range [1].
Sentence 2: the slow electro-chemical processes that develop between the electrode-skin interface constitute a source of interfering signals in the sub-Hz frequency range [2], de­veloping o.set voltages in the electrodes which can have amplitudes of up to tenths of mV [3].
Relationship: contrasting
Domain: Hardware
Sentence 1: The impact of surface roughness on resistance in modern IC design and simulation thus is commonly handled by the analytical formula [4] -1 2 h 2 se =s1+ tan-11.4, (1) pd where se is the effective conductivity (EC), h is the RMS height of the roughness and d is the skin depth.
Sentence 2: since only h is incorporated in the formula, (1) fails to differentiate different patterns and settings of roughness as long as they share the same RMS height, rending it inaccurate and in.exible for most cases.
Relationship: contrasting
Domain: Hardware
Sentence 1: of Electrical Engineering National Cheng Kung University Tainan, Taiwan ihchen@ lpvlsi.ee.ncku.edu.tw, lihyih@mail.ncku.edu.tw, seya@ lpvlsi.ee.ncku.edu.tw Abstract-Performance estimation at system-level involves quantitative analysis to allow designers to evaluate alternative architectures before implementation.
Sentence 2: designers must spend a tremendous amount of time in system remodeling for performance estimation for each alternative solution in a huge design space.
Relationship: contrasting
Domain: Hardware
Sentence 1: Aread­modify­write 1.reads1oandf1o; 2.writesfo; 1 3.alulateso=fo81o8fo;and 4.writeso.
Sentence 2: thisrequirestwodiskreadsandtwodiskwrites.Evidently, whenwritingasingleblok,read­modify­writeappearsto haveasubstantialperformaneadvantage.when multipledisksaretobewritten,thisadvantageislesslear.
Relationship: contrasting
Domain: Hardware
Sentence 1: Practical Methods in Coverage-Oriented Verification of the Merom Microprocessor Alon Gluska Intel MG MATAM Haifa, Israel Alon.gluska@intel.com ABSTRACT Functional coverage is a well known means of measuring verification progress.
Sentence 2: approaches to coverage, such as Coverage Driven and Coverage Oriented approaches, are often difficult or impractical to implement.
Relationship: contrasting
Domain: Hardware
Sentence 1: In the interest of keeping the skew very close to zero, the algorithm guarantees that the number of regen­erating elements is equalized along any root-to-sink paths of the tree.
Sentence 2: in spite of the solid theoretical ba­sis of this solution, experimental results showed very small di.erences with the clock trees generated by the original approach by Igarashi et al., witnessing the goodness of the greedy approach of [13].
Relationship: contrasting
Domain: Hardware
Sentence 1: It is natural to choose xso that vq =(vbe,vbc)T becomes a point in the forward ac­tive operation region for all transistors.
Sentence 2: since vq is a vector consisting of branch voltages but x is a vector consisting of node voltages and branch currents of the independent voltage sources, we have to calculate the initial point x0 such that vq becomes a point in the forward active operation region.
Relationship: contrasting
Domain: Hardware
Sentence 1: These libraries of IP cores, either available in-house or commercialized on the market, are reused by embedding them into a single system chip, conceptually in the same way as integrated circuits were connected on PCBs.
Sentence 2: while system geometry shrinking and design reusing allow impressive gains, SoC testing faces new set of problems, among which we can identify: -testing cores with different functionnalities, coming from different companies, -accessing cores from the system primary inputs and outputs, -controlling whole SoC test process.
Relationship: contrasting
Domain: Hardware
Sentence 1: These trends are sustained by the numerous advantages the real-time SOC (system-on-chip)) approach offers : the use of an RTOS facilitates the management of aperiodic tasks and real time constraints;  dedicated HW modules can be implemented on the same chip to speed up critical applications tasks;  the chip capacity enables to implement complex applications with a large set of architectural alternatives;  the on-chip communication bandwidth makes HW / SW code- sign really attractive;  the processor core can be tailored reagrding the application in terms of co-processors and dedicated memory hierarchy.
Sentence 2: the associated design space is conjointly exploding and consequently requires methods and tools to guide the designer to- wards an (the) interesting solution.
Relationship: contrasting
Domain: Hardware
Sentence 1: Skew Management of NBTI Impacted Gated Clock Trees Ashutosh Chakraborty ECE Department The University of Texas at Austin Austin, TX 78703, USA ashutosh@cerc.utexas.edu ABSTRACT NBTI (Negative Bias Temperature Instability) has emerged as the dominant failure mechanism for PMOS in nanometer IC designs.
Sentence 2: its impact on one of the most im­portant components of modern IC design -the clock tree ­has not been researched enough.
Relationship: contrasting
Domain: Hardware
Sentence 1: The number of inequalities in (7) seems to be too large.
Sentence 2: as inequalities in (7) involve only binary variables, L they can be merged as follows: x - lxy - ly n + un) (1) Min HPWL =(u n n pcr1q1 + pcr2q2 1n.N subject to lx n xc + px u x n, .
Relationship: contrasting
Domain: Hardware
Sentence 1: Through architectural enhance­ments, supply voltage reductions and technology scaling, the power consumed per FPGAlogic element has been decreas­ing with each successive FPGAgeneration [5].
Sentence 2: these power reductions have been more than o.set by the increasing logic density of FPGAs, with the result being that the power consumed by the largest devices is now measured in watts.
Relationship: contrasting
Domain: Hardware
Sentence 1: The reason for this behavior is that at lower levels of memory traf.c, the lower hop-count of CMesh provides a faster network transit time compared to Mesh.
Sentence 2: as network load increases, CMesh becomes bandwidth limited (recall that CMesh has only half of the bisection bandwidth of Mesh and DB), and then queuing delays rather than the number of hops dominate the end-to-end message latency.
Relationship: contrasting
Domain: Hardware
Sentence 1: A couple of key observations can be made: 1. the tasks of interpreting, pro.ling, and translating are best o.oaded to a hardware co-processor in order to minimize overhead on the primary processor 2. the target of the translation must be capable of provid­ing accelerated computation for algorithms identi.ed in the hot-spot regions of the source binary  The idea of o.oading computation to a co-processor is com­monly employed.
Sentence 2: we propose that a recon.gurable target is provided in system.
Relationship: contrasting
Domain: Hardware
Sentence 1: This result illustrates the fact that increas­ing the number of vertical vias is, in fact, feasible in terms of area consumption by the wires themselves.
Sentence 2: as explained in Section 3.4, adding extra vertical bundles in the 3D crossbar is pro­hibitive in terms of arbitration complexity; the area, power and la­tency increases incurred by a highly-complex arbitration scheme negate any advantages provided by the increased number of inter­layer bundles.
Relationship: contrasting
Domain: Hardware
Sentence 1: Assuming two banks for an instant, the top bank is powered When entering sleep mode, the intermediate virtual supply settles 12 12 from Vdd to · Vdd, and the bottom bank is powered from ·  2 to exactly Vdd tual supply.
Sentence 2: this virtual supply settles to nearly when connecting the bulk nodes to the this same vir-Vdd to ground.
Relationship: contrasting
Domain: Hardware
Sentence 1: Although the techniques of [3] and [4] optimize the partitioning and ordering of the coefficients, the cost function of the algorithms is calculated for all the combinations over the coefficients, which is limited to a small group of coefficients, where the total number of permutations is calculated in a still reasonable time.
Sentence 2: for a higher number of coefficients these exhaustive algorithms are less attractive due to the time necessary to process the large number of combinations.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the set of coalesced t constraints of the two LBL s (denoted Lbland Lbl2) A11Bi>b14A11 (3) A2 2Bi>b24A22 has integer solutions, then the intersection is a new LBL:  Lblt Lbl2q{ qT11Bi+T11+f1s.t.
Sentence 2: constraints (3)} the real dif.culty is the decomposition of the differ­ences Lblt4dLblt Lbl2)and Lbl24dLblt Lbl2), and the reason is that the difference of two LBL s is not necessarily an LBL.
Relationship: contrasting
Domain: Hardware
Sentence 1: For each of n temperature-violating hot spots with temperature Ti > Ttarget, i =1, 2, ..., n, we perform sensitivity analysis for Ti with re­spect to the number of thermal vias at each thermal via location as in Section 3, and this can be performed fast due to the advantage of adjoint sensitivity analysis.
Sentence 2: to reduce the complexity of the LP prob­lem, we only record those non-trivial sensitivity values sv,ij = sth,in which sth is a constant threshold of sensitivity and in practice we take sth =0.01°C per via; the associated location j is then de.ned as a candidate thermal via location, and j =1, 2..., p,where p is the total number of candidate thermal via locations.
Relationship: contrasting
Domain: Hardware
Sentence 1: 3.4 CACH E C A PAC I T Y A D J US T M E N T By using way-shutdown technique to turn-off unused cache ways, the system static energy consumption can be re­duced [1, 8, 13].
Sentence 2: directly applying their approaches in multi-core system will lead to performance loss if the cache capacity of critical thread is too small to hold used data.
Relationship: contrasting
Domain: Hardware
Sentence 1: Achieving Out-of-Order Performance with Almost In-Order Complexity Francis Tseng Yale N. Patt Department of Electrical and Computer Engineering The University of Texas at Austin {tsengf,patt}@hps.utexas.edu  Abstract Thereis still muchperformance tobegainedbyout-of-order processors with wider issue widths.
Sentence 2: traditional methods of increasing issue width do not scale; that is, they drastically increase design complexity and power require­ments.
Relationship: contrasting