sadat2307/MSciNLI huggingface dataset:
Domain: Networks
Sentence 1: (1-qi+j )  (i, j -1) with transition rate jµ  ii) if i + j = M, the process only can move into the state (i, j-1) with transition rate (M -i)µ.
Sentence 2: the sub-matrices Ai(0 = i = M) in the case of random m-sensing are given by .
Relationship: reasoning
Domain: Networks
Sentence 1: - 3)-ad-aa-1 + N ia-2 That means both data transmission from x(l)and ACK transmis­sion from r(l)will be successful, i.e., ul(t)=1.
Sentence 2: (l)(l) Probul(t)=1lJ2= ProbJ1 n J3lJ2leading to the statement.
Relationship: reasoning
Domain: Networks
Sentence 1: In the example of Figure 1, the AES Engine gathers the results of the execution of jill and the tra.c trace that contains the execution of this attack.
Sentence 2: the experiment .le (jill.exp.xml)isstoredwiththe results (jill.res.txt and jill.res.pcap)and areportde­scribing the experiment execution (jill.aes.xml).
Relationship: reasoning
Domain: Networks
Sentence 1: S creates data packets to r1 and R1 creates packets to r2.So there is two packet copies on the link R1-R6.
Sentence 2: the cost (the number of packet copies in the network) of a REUNITE tree may be larger than that of a source tree constructed by a classic protocol as PIM-SM (Protocol Independent Multicast -Sparse Mode)[9], since 2In fact, this possibility also exists when the network has pure unicast routers or when the REUNITE router is over­loaded.
Relationship: reasoning
Domain: Networks
Sentence 1: Foreachend user i, the optimal utility is given as follows (()) Th n + L - 1 ui = 2(n + L - 1) ln 2 - L. 2s2 2n + L - 2 which corresponds the following user s throughput () Th(n + L - 1) n + L - 1 R = ln 2 .
Sentence 2: s2 2n + L - 2 (since function f (.
Relationship: reasoning
Domain: Networks
Sentence 1: For MPR mode, di.erent active reception areas are also disjoint but the active transmission areas can overlap and the transmitter nodes can respectively send information to their corresponding receivers within the communication range at the same time (see Figure 2(a)).
Sentence 2: if we sum up the active transmission areas to calculate Ataa, then Ataa is up­per bounded by T `nR2(n)´, which is the average number of nodes in a circle of one receiver [10, 7].
Relationship: reasoning
Domain: Networks
Sentence 1: We can see that 92% of the SSIDs in use have a length between 4 and 9 charac­ters, being very large sizes (>16) quite scarce and lacking any additional bene.ts.
Sentence 2: we consider that limiting the SSID to a smaller size would not represent any signi.cant limitation for most users, especially when targetting ad-hoc networks where the SSID must be de.ned every time a new network is created.
Relationship: reasoning
Domain: Networks
Sentence 1: (1 - FS (t)).The high-priority queue has strict priority and drains at rate 1.The low-priority queue uses the remaining bandwidth after servicing the high-priority traf.c.
Sentence 2: its drain rate is 1 - .BS (t) where t BS (t)=0 xfS (x)dx/E (S) is the fraction of the overall bytes that belong to .ows smaller than t.Note that in reality, the low­priority queue drains only when the high-priority queue is empty.
Relationship: reasoning
Domain: Networks
Sentence 1: In case we choose a set containing element j',then coverj' will increase by at least 1 and the contribution of element j' to the potential function will be 2(wj' +dj' -1) 2wj' -1 at most n=n .
Sentence 2: the expected contribution of element j' to the potential function after the iteration is at most -4dj' 2(wj' +dj' ) -4dj' 2wj' -1 n n+(1 -n )n 2w-2dj' -1 -4dj'-1 2w = n j' (n + n -n ) =n j' where to justify the last inequality, we prove that f(x)= x 2x-1 -1 -n x x-1 n + n =1 for every x =0.
Relationship: reasoning
Domain: Networks
Sentence 1: Speci.cally, we prove that for any .ln n+c constant c, the asymptotic probability of sn = ß0 pn ß0 -c ( 1 ß0 )-c - is at least 1 -- e and at most e 2 e .
Sentence 2: 1/ß0 -1/32 for anypositive sequence (.n : n = 1) with .n = o (ln n) and .n .8, it is asymptotically almost .ln n-.n .ln n+.n sure that ß0 = sn = ß0 .
Relationship: reasoning
Domain: Networks
Sentence 1: k k Returning to our analysis, then, note that Y can be de.ned as the sum of independent indicator random variables and that the expected value of Y is E(Z0)+ E(Z1)+ ···+ E(Zl-1).
Sentence 2: in the single-phase algo­rithm, E(Y)is lN/(l)+ ln/=(N+ ln)/.2c2c 2c we have the following fact: Lemma 3: Suppose N = l2c .
Relationship: reasoning
Domain: Networks
Sentence 1: Scanners typically target a particular vulnerable port over a range of IP addresses, and thus unsuccessful connection at­tempts to the same local host are considered less malicious, even if destined to di.erent ports.
Sentence 2: by default, LQS .ags a remote as a scanner only if it makes at least .ve failed connection attempts to the same local host but on di.erent destination ports.
Relationship: reasoning
Domain: Hardware
Sentence 1: (2) Wider Viewing Angle When wedesign a conventionalIPdis­play, we use a short focus and narrow viewing zone design to en­hancedepthresolutionof3Dimages.Stereoscopyisalsonecessary for a3Ddisplay.
Sentence 2: stereoscopyisnot necessaryforaBRDFdisplaybecause it is acceptable to see the same rays (same image) in both eyes.
Relationship: contrasting
Domain: Hardware
Sentence 1: It can then achieve good performance on constant as well as on general multipliers.
Sentence 2: it takes little advantage from the structural information in the Kei-Yong Khoo Cadence Design Systems, Inc. San José, California, USA khoo@cadence.com Multiplier in arithmetic expression quick synthesis by logic synthesis verification tool  Equivalence Checking Figure 1.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, the adpcmbenchmark has only two arrays for input and output, as well as several ar­rays to keep .lter coef.cient, in which case our tool does not really help.
Sentence 2: for the lpcbenchmark, where there are twelve arrays, each of which may have dif­ferent sizes and different logical purposes, we can compress the memory by merging arrays with non-overlapping life­times.
Relationship: contrasting
Domain: Hardware
Sentence 1: The relatively large range of .C .T combinations is due to the large range of metal densities for maximum density rule-based cases as thebu.er spacingis changed.
Sentence 2: the relativelycon­stant metal density in the design examples with minimum density rule-based .ll results in a smaller range of .C .T combinations Overall, the minimum and maximum density rule-based .ll methods produce designs with approximately the same performance in terms of .C .T .
Relationship: contrasting
Domain: Hardware
Sentence 1: µ of both 23-stage and 47-stage RO frequencies at 0.3V FBB is 3.6× faster than that at ZBB, and s/µ improves by around 1%.
Sentence 2: µ of both 23-stage and 47-stage RO frequencies at 0.3V RBB is smaller than that at ZBB by 70%, and s/µ deteriorates by 1%.
Relationship: contrasting
Domain: Hardware
Sentence 1: 9A-3 Usually, it is dif.cult to directly control the edge number in post-OPC mask on the design phase, and the following OPC process will introduce more wire fragments.
Sentence 2: due to the low printing requirement on the cut mask as illustrated in Section II, more fragment merging can be applied to provide a better correlation between the pre-OPC and post-OPC mask edge numbers.
Relationship: contrasting
Domain: Hardware
Sentence 1: INTRODUCTION Distributed shared memory(DSM) systems [5] provide a simple mean of programming for the networks of work- stations, which are gaining popularity due to their cost- effective high computing power.
Sentence 2: as the num- ber of workstations participating in a DSM system in- creases, the probability of failure also increases, which Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: contrasting
Domain: Hardware
Sentence 1: 8T SRAM can be a good candidate to enable 1) wide­range DVFS using the same supply level as that of logic blocks and 2) multi-ported memory operations.
Sentence 2: 8T SRAM s incapability to support column selection and multi-ported access at the same time can limit the types of applications for 8T bit-cells, especially in cache memories.
Relationship: contrasting
Domain: Hardware
Sentence 1: Benchmark Description Execution Errors Injected/ Cycles Consumed/Detected   auction ticket auction 467.4 75 / 27 / 25 calc calculator 338.5 71 / 14 / 14 .rstaid .rstaid info 618.5 423 / 127 / 126 jpeg jpeg viewer 1,052.9 1314 / 329 / 313 image photo album 1,157.1 430 / 302 / 271 manyballs bouncing balls 475.2 53 / 13 / 11 mvideo video player 2,732.6 63 / 44 / 40 pushpuzzle puzzle game 479.7 72 / 14 / 13 execution as usual.
Sentence 2: if its checksum indi­cates an error, we access the duplicate and check its checksum.
Relationship: contrasting
Domain: Hardware
Sentence 1: As a class, these stream-based prefetchers have been shown to be highly effective at eliminating the vast majority of frontend stalls stemming from instruction cache misses.
Sentence 2: due to the large instruction footprints and small, yet numerous differences in the control flow among the var­ious types of requests of a given workload, stream-based prefetchers require significant storage capacities for high miss cov­erage.
Relationship: contrasting
Domain: Hardware
Sentence 1: Post-silicon validation is not a new idea and in fact has been used for many years in many places.
Sentence 2: very little is published on post­silicon veri.cation methodologies (e.g., [13]), and most re­search in post-silicon validation has centered around on-line checking and debugging capabilities of the silicon platforms (e.g., [1, 8, 15]).
Relationship: contrasting
Domain: Hardware
Sentence 1: The implemented 8-words X 64-bits 8-port SRAM has 256-bit simultaneous data accessability by horizontal and vertical address con­.gurations and has 25.6 Gbits/s of high bandwidth.1 Embedded memory logic requires high bandwidth mem­ory to handle data parallelism of video signal processing.
Sentence 2: conventionally designed SRAM [1]-[2] does not provide multiple data at a time, which becomes a bottle­neck.
Relationship: contrasting
Domain: Hardware
Sentence 1: Here, r1 =1 means that exactly one wire can pass through the west boundary of the tile, and this wire must be of Type-1, -3, or -6.
Sentence 2: if this wire is of Type-1, then r3 , r5 , and r6 should also be at least one since they all contain Type-1 wires, instead of zero as in this r-vector.
Relationship: contrasting
Domain: Hardware
Sentence 1: As discussed in Section 1, our protocol provides a greater maximum possible savings for reads than for writes, so it is somewhat counter-intuitive that for all but one benchmark in Figure 5 the average write latency reduction is greater than that of the reads.
Sentence 2: this is readily explained by the fact that these benchmarks do not exhibit a great Write accesses, on the other hand, since they do not incur the penalty of accessing main memory, are less sensitive to the size of the trees than to the frequency with which they are torn down.
Relationship: contrasting
Domain: Hardware
Sentence 1: The local level one cache reuse can be improved by scheduling the iteration groups assigned to a core such that the tags of the contiguously sched­uled iteration groups have the least possible Hamming Distance between them.
Sentence 2: shared level cache reuse can be improved by scheduling iteration groups with minimum Ham­ming Distance on the cores sharing the cache such that those it­eration groups are executed simultaneously on the cores, thereby improving cache performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: On the one hand, eFalcon consists of multiple serial high-speed interfaces such as OBSAI, CPRI and SRIO to allow intra-board commu­nication but also board-to-board communication with data rates beyond 1 Gbit/s.
Sentence 2: the elaborate clock distribution concept of this platform allows an accu­rate synchronization of multiple platforms.
Relationship: contrasting
Domain: Hardware
Sentence 1: TWO LEVEL ANALYSIS Because the pro jection in TBS preserves the structure, the re­duced state matrices are sparse if the original ones are sparse.
Sentence 2: when pro jected by .at pro jection V in PRIMA and HiPRIME, the resulted G is m+1m+1 X X G = Vi T Gij Vj , (19) i=1 j=1 which loses the structure in general, and the reduced state ma­trices are dense.
Relationship: contrasting
Domain: Hardware
Sentence 1: We propose a new method to solve the SBW and the .ll insertion problem simultaneously, and we denote it as S BW F .
Sentence 2: current designers use a two-step approach which .rst solves the S BW problem, then applies either the de facto rule­based method or the more recently proposed model-based .ll insertion method [15] to determine the amount of .ll needed.
Relationship: contrasting
Domain: Hardware
Sentence 1: Thiswastes1 bitperentry,butalsowastes1.75K entries,sinceonly256(0.25K) entries are needed.The1bitwastedper .eldisa formof internal fragmentation and the 1.75K wasted .elds are a form of external fragmentation.
Sentence 2: to reduce external fragmentation, multiple .elds of the same size couldbe implemented withasingle BRAM set.since BRAMs are dual-ported, supporting more than two .elds would result in a loss of parallelism in terms of .eld access.
Relationship: contrasting
Domain: Hardware
Sentence 1: Re­cently, a solution was proposed for adapting an architectural checker for a complex microprocessor design to an acceleration platform [7] using this approach: low overhead embedded logic produces a compressed log of architectural events, which is later checked by an off-platform software checker.
Sentence 2: an architectural checker cannot provide the level of insight on design correctness, which a number of local checkers for microarchitectural blocks can.
Relationship: contrasting
Domain: Hardware
Sentence 1: In the paper, Tardis is claimed to have a data remanence duration of approximately three minutes using a 10µF capacitor.
Sentence 2: our experiments show that not only is SRAM remanence dependent on the external capacitance, but it is also a strong function of the peripheral circuitry, the microcontroller architecture, and the e.ective internal capacitance.
Relationship: contrasting
Domain: Hardware
Sentence 1: FR-FCFS is thread-unaware and slows down the high-priority cactusADM by 4.5X.
Sentence 2: nFQ takes into account thread weights by assigning each thread a share of the DRAM bandwidth that is proportional to the thread s weight [22].19 NFQ succeeds in prioritizing the higher­priority cactusADM, but fails to treat equal-priority threads equally because, as shown in previous sections, equalizing DRAM throughput of threads does not necessarily correlate with equalizing performance slowdowns.
Relationship: contrasting
Domain: Hardware
Sentence 1: Another approach is to adopt Latency Insensitive (LIS) [4] methodology, and a related approach, Globally Asynchronous Locally Synchronous (GALS) [5], uses handshake protocols for inter-module communication.
Sentence 2: both GALS and LIS methodologies have yet to find widespread use, partly due to the lack of adequate CAD support, and partly because they entail a massive change in design practice, which designers are reluctant to embrace.
Relationship: contrasting
Domain: Hardware
Sentence 1: ROSE is orthogonal to the existing fault tolerance techniques such as [3, 4, 5, 6, 7], but with advantages of negligible overhead on area, performance, and testing.
Sentence 2: rOSE can change the topology of the LUT-based logic network, and as we explain next, this can limit its applicabil­ity in the overall design .ow.
Relationship: contrasting
Domain: Hardware
Sentence 1: Conclusions The results we obtained demonstrate that the CAD algorithms are dispersed widely in the quality vs. runtimes tradeoff spectrum from a speedup of 8x to a 4.5x quality degradation.
Sentence 2: compared to the slowest combination of algorithms (Scatter and Original Pathfinder), the fastest combination (Annealer and Simple Router) produces only 1.2x degradation in the quality of the solution with 8x speedup in total runtime.
Relationship: contrasting
Domain: Hardware
Sentence 1: IdealSPD can match the main memory performance of Vantage on many mixes (albeit with twice the capac­ity) and R-NUCA s low latency on some mixes.
Sentence 2: idealSPD struggles to do both due to its shared/private  (a) Recon.guration interval (b) Jigsaw UMON con.guration Figure 12.
Relationship: contrasting
Domain: Hardware
Sentence 1: This .lter can also be used during CPPR, wherein if paths are being traced in a non-decreasing order of pre-CPPR path slacks, tracing is performed only as long as for each path traced, the pre-CPPR path slack is smaller than the pre-CPPR slack-limit threshold.
Sentence 2: a post-CPPR path slack that is smaller than a threshold post-CPPR path-slack-limit may indicate a design problem that forces a designer to perform design updates or optimization.
Relationship: contrasting
Domain: Hardware
Sentence 1: Electrical Simulation Experimental Results Fc (MHz) 4.5-5 4.2-4.9 Q 100 25 Output Swing (V) -0.9/+0.9 -0.45/+0.6 Current consumption (µA) 248 263  Our results show that this design approach achieves good performance results, showing good matching between simulation and experimental results.
Sentence 2: there is significant decreasing in the filter s quality factor performance in the experimental results.
Relationship: contrasting
Domain: Hardware
Sentence 1: With the impact of cost crunch in every industry including semi-conductor industry across the world, complexities of 22nm CMOS may appear to be way out in the distant future.
Sentence 2: more than the technology Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: contrasting
Domain: Hardware
Sentence 1: For single-.it packets, a starvation threshold of eightcyclesprovidesa marginal(1.5%) throughputincrease due to improving fairness, while for eight-.it packets it has no e.ect.
Sentence 2: setting a starvation threshold smaller than the packet length reduces performance gains because starvation control releases connections before packets can be fully transferred.
Relationship: contrasting
Domain: Hardware
Sentence 1: This cumulative number is 4313, 5897, 12931 and 33603 for the 1, 3, 5, and 10 breakpoint flows respectively, in contrast to 2858 for MorePlace and 2686 for the one-pass flow.
Sentence 2: unlike MorePlace that requires the addition and deletion of only 231 and 185 repeaters respectively in its final iteration, the one-pass flow layout is unrealizable because it still requires all 2686 repeaters to be added to its converged netlist.
Relationship: contrasting
Domain: Hardware
Sentence 1: Furthermore, existing fault-tolerant techniques typically use a single fault map and a centralized fault protection scheme which cannot be scaled for large CMP architectures: as a result each access needs to go through the fault map first, and no parallel cache accesses are allowed.
Sentence 2: these schemes miss the opportunity to leverage the scalable interconnection network (e.g., NoC fabric) to achieve fault-tolerance of the caches in these emerging multi/many-core architectures.
Relationship: contrasting
Domain: Hardware
Sentence 1: While the heterogenous implementation with 3 CLB columns and 1 resource column has an operating frequency of 88 MHz, the homogenous implementation with 4 CLB columns is able to operate at only 64 MHz (we con­sider the adjacent column pair of BRAM (embedded memory) and MULTX18 (embedded multiplier) as a single resource column for generating numerical data).
Sentence 2: these heterogenous resources are typically limited in number and present in speci.c locations.
Relationship: contrasting
Domain: Hardware
Sentence 1: A wide variety of schemes have so far been proposed for implementing stereoscopic displays on which 3D information can be displayed easily.
Sentence 2: no single-display scheme has yet been proposed that satisfies all the requirements of being able to recreate the dynamic parallax shifts that occur when users move around the object, while being able to display suitable stereoscopic images simultaneously to at least 3 users without any flicker or distortion.
Relationship: contrasting
Domain: Hardware
Sentence 1: Process technology solutions, e.g., Silicon-On-Insulator (SOI) [19, 24], to reduce soft errors by raising Qcritical by ex­tending the depletion region or increasing the capacitance while maintaining or reducing Qcollected have been proposed.
Sentence 2: technology engineering may require the expense of additional process complexity, yield loss, and substrate cost [1].
Relationship: contrasting
Domain: Hardware
Sentence 1: The leftover overhead in the case of using the heuristic algorithm in this set of experiments is about 10­30% because of the assumption in the heuristic algorithm that small types of physical memories are more suitable in the solutions which work on reducing the leftover simply because they are able to cover small uncovered parts with less implied leftover.
Sentence 2: this is dependent on the con.gurations of the small types (e.g., it can happen that the thinnest con.guration of the small type is wider than some con.gurations of the large type, which is the case in the set of experiments in Table 3).
Relationship: contrasting
Domain: Hardware
Sentence 1: The de.nition of hot predicate exhibits the two main char­acteristics of problematic regions of the code: .rst, the time spent and number of accesses are unusually high for a set of accesses, and second this problem occurs several times in the execution, further degrading performance.
Sentence 2: such hot predicate, even if detrimental for performances, may have no impact at all on the parallel scalability of the application considered.
Relationship: contrasting
Domain: Hardware
Sentence 1: The seamless compatibility to existing HDDs allows to use SATA and SAS SSDs not only as individual devices but also in RAID con.gurations without requiring any changes on the host side.
Sentence 2: since SSDs have di.erent per­formance and reliability characteristics and work internally in a di.erent way compared to HDDs, it is di.cult to pre­dict the behavior of SSDs in a RAID setup.
Relationship: contrasting
Domain: Hardware
Sentence 1: In the rule-based method,the .ll metalisregularly spacedbetween adjacent signal lines and causes increases in coupling capac­itance.
Sentence 2: the model-based .ll generation method­ologydoesnotplacethe .ll metalinaregularpattern,which has the tendency to reduce the capacitance increase as has been observed with rule-based .ll generation methodologies thatproducestaggered .llpatterns[9].
Relationship: contrasting
Domain: Hardware
Sentence 1: We .rst develop a sequential algorithm to combine the AoA estimates produced by the receivers to es­timate the node location under LOS propagation that has linear complexity in the number of measurements and is ap­proximately maximum likelihood.
Sentence 2: nLOS multi­pathsoften resultsinAoA estimatesthatare far fromthe true node bearing and act as outliers in the localization.
Relationship: contrasting
Domain: Hardware
Sentence 1: Finally, the pl2sp() function from Parquet-4 that we use to obtain the .nal overlap-free .oorplan has a time complexity of O(n ),where n is the total number of modules.
Sentence 2: in practice, we .nd that the runtime associated with this function call is negligibly small compared with that of solving the optimization problems (2) and (12).
Relationship: contrasting