sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: C. Fault Sensitivity Analysis Although FFS algorithm introduces a signi.cant speedup, for the already mentioned DOT setups the performance is not always suf.cient.
Sentence 2: for most frequently used and time-consuming transient simulations we exploit two additional characteristics of the fault simulation: 1) the main objective of the DOT method is to establish the detection status of a defect and not to determine the actual output values of the faulty circuit, 2) the output value is often measured at a few time points and therefore it is suf.cient to compute the output value only for these time points while many time points have to be computed in a standard transient analysis.
Relationship: reasoning
Domain: Hardware
Sentence 1: The tolerance of the self-compensated devices is set at 4nm since the 3s for the gate CD space(um) control is 4nm in 130nm technology [8].
Sentence 2: if linewidths are 4nm 0.18 larger than nominal at 0.4um defocus, we assume those patterns are 150 0.2 0.22 dense ; similarly, if linewidths are 4nm smaller than nominal, we 0.24 0.26 140 classify the patterns as iso .
Relationship: reasoning
Domain: Hardware
Sentence 1: (Proof) The number of different vectors speci.ed with q- 1 variables is at most 2q-1 <k.
Sentence 2: at least q variables are necessary to represent an index generation function with weight k. D Conjecture 3.1 shows that most functions with weight k can be represented with n=2plog2(k+1)l-3 variables as shown in Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: DDL DECOMPOSITION For an arbitrary 2-D layout pattern m(x,y), the Fourier transform M(u,v) of the spatial layout represents the coherent field distribution in the (u,v) Fraunhofer diffraction plane.
Sentence 2: the electrical field of the diffraction pattern for mask pattern m(x,y) in the (u,v) plane can be written as: .j2.
Relationship: reasoning
Domain: Hardware
Sentence 1: What is (nx--1)( nx 2) ( n -- i 1)( n m i j 4) y =j -- + --- important is to use the same routing model in the placement and (xi 1)( x --i 2) ( ni 1)( n + --- m i j 4) y =m in the final routing stage.
Sentence 2: the behavior of routing -- -- .
Relationship: reasoning
Domain: Hardware
Sentence 1: Assume that the DPCCH and DPDCH have the same channel characteristics during transmission, and we perform the channel estimation via the use of the pilot symbols at the DPCCH [2].
Sentence 2: dPDCH output signals for x1 and x2 of the P ­fingers STBC-RAKE receiver x d ,1 , x d,2 are given by x d .Pc p d p +=yyyy*,2,,2,,1,*,1,,1.Pc p d p (10) p=1 p=1 P P * * x d ,2 = .
Relationship: reasoning
Domain: Hardware
Sentence 1: When the configuration memory bits are considered the metric of a circuit s module j is computed as the number of critical CBs identified by the STAR discovery tool (CBCRITICAL) divided by the total number of configuration memory bit controlling the considered circuit s module (CBMODULES).
Sentence 2: we defined the Static Sensitivity as SensitivityStatic(j) = CBCRITICAL(j) / CBMODULES(j).
Relationship: reasoning
Domain: Hardware
Sentence 1: By substituting 00 for bits b1 b0, we obtain the value 96.
Sentence 2: the disjoint values {3, 11, dXEX 131, 139 }in map to the continuous values {96, 97, dXE X 98, 99 }in m. As shown in Figure 7, exhaustive enu­meration of values v1, v2, v3,and v4 reduces to the inte­gral between limits l1 and l2.
Relationship: reasoning
Domain: Hardware
Sentence 1: An OR gate combines the signal Xi with the output of the latch FBIi to generate the input of the latch FBIi.
Sentence 2: if at any cycle of the test session a 1 is generated on Xi (detection of an error on the bit position di), this value is memorized in the FBIi latch for the rest of the time, indicating a fault in the bit position di.
Relationship: reasoning
Domain: Hardware
Sentence 1: )2 .. )2 (r sin f - µ -(fr cos µIA1 1 2s2 AI Q r A .- 1 - p(r, f) = exp duction, there exists a demand for an e.cient method of 2psAI s 2s2 Q Q AA 1 (11)main focus of the work.
Sentence 2: the pdf of f can be computed by integrating (11) over r  3.
Relationship: reasoning
Domain: Hardware
Sentence 1: Using the obtained place­ment pattern and spacing, the switch allocation then evenly distributes the MTCMOS switches over the entire IC ex­cept its hard macros, where no MTCMOS switches can be inserted.
Sentence 2: iC s .oorplan should be .nalized before distributing MTCMOS switches, but the placement of the gated low-Vt cells is not done yet.
Relationship: reasoning
Domain: Hardware
Sentence 1: The hardware resources of an FPGA are uniformly distributed across the die, as such that a computing tile is replicated many times to generate an array of tiles.
Sentence 2: due to the device uniformity, the Xilinx carry-lookahead signals are emulated serially, along dedicated chains, as shown in Figure 1. y(2) x(2) y(1) x(1) y(0) x(0) Figure 1: Carry-lookahead network on Xilinx The Stratix family from Altera provides architectural support for carry-select addition [2].
Relationship: reasoning
Domain: Hardware
Sentence 1: However, when comparing the clock latency resulting from Flows (3) and (4), we found that even though the number of clock sinks resulting from Flow (3) is fewer than that resulting from Flow (4), the clock latency resulting from Flow (4) is still better than that resulting from Flow (3).
Sentence 2: it is essential to consider clock tree topology for clock latency reduction when applying MBFFs.
Relationship: reasoning
Domain: Hardware
Sentence 1: A retention .ip-.op usually preserves its state in an extra latch, which is fully biased during standby mode since it is not power-gated, and this extra latch induces continuous gate leakage, which is the main contributor to total leakage current, and this situation rapidly deteriorates as the Primary outputs CMOS technology scales [12].
Sentence 2: reducing the size of retention storage is an impor­tant issue in designing power-gated circuits.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thethirdcomponentisthepageplacementandremap­pinglogic.Theplacementinthesubcachesisbasedona page.So,allcachelinesfromaparticularpageareremapped toaspecifcsubcache.Inotherwords,thereisadirect mappingbetweenapageandasubcache.Whenasubcache showshighercachemissesthanaspecifedthresholdina giventimeinterval,apagemappedontothesubcacheisdy­namicallyremappedtothesubcachewiththeleastcache misses.Toperformthisdynamicremapping,eachsubcache hasitsownmisscounter.Thereisalsooneglobalmiss counterusedtodecidewhenthepageremappingshouldbe done.Thisisexplainedindetailinthefollowingsubsections.
Sentence 2: 4.2 Page Placement Weusepagesizesof4KBor8KB.Aconventionalcacheis partitionedinto4KBor8KBsubcachessuchthatthepage andthesubcachehavethesamesize.Forexample,ifwe assumean32KBinstructioncacheanda4KBpage,there areeightinstructionsubcaches.Whenapagefaultoccurs, thepageismappedontoasubcacheusingamappingsimilar todirectmappedcachesandthesubcacheidforthepageis storedintheextendedTLB(Figure3).Thissubcacheidis usedtoidentifycorrectsubcachecontainingrequesteddata thereafter.Sothesubcacheholdingtherequesteddatacan beperfectlyidentifed.Theupperbitsofthepageofsetare usedtoindexsubcachesandthelowerbitsareusedasthe ofsetwithinacacheline.Thetagsinthesubcachesareac­tuallypagenumbers(assubcacheandpageareofthesame size).Thetaginformationischeckedtoinvalidateallcache linesbelongingtoapagewhenthatpageisdynamically remappedintoanothersubcache.Notethatwithoutthe dynamicremappingthesubcachearchitectureandconven­tionalcachehavethesamemappingfunction.Thischanges whenpagesareremappedtoothersubcaches.Inorderto refectthechangesintheextendedTLB,theconventional pagetablemustalsobeextendedtoincludesubcacheid feld.SowheneveraTLBentryisreplaced,thesubcache idmustbestoredbacktothepagetable.WhentheTLB entryisbroughtinagainfromthepagetabletotheTLB, thesubcacheidinformationismaintained.the subcachecontainingrequesteddatacanbesafelyidentifed.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then, for tasks that can be dropped, we distinguish between two cases:  If task w starts later than maxF inishv (minStartw > maxF inishv ), this task is certainly dropped and never executed as the transition to the critical state has al­ready been completed.
Sentence 2: it does not appear in the schedule, and it is modeled with [0, 0] bound (lines 20­21 ).
Relationship: reasoning
Domain: Hardware
Sentence 1: Power and delay comparison of SBM-L, MLP-fast, SBM-H and SBM-I previously, if provided with a library with more cell sizes, we expect MLP-fast to perform no worse, if not better than MLP-fast with power-of-two cell sizes.
Sentence 2: when provided with a library having all­integer cell sizes, MLP-fast is also capable of obtaining designs with around 30% less power than SBM.
Relationship: reasoning
Domain: Hardware
Sentence 1: Introduction In shared memory multiprocessors utilizing invalidation­based coherence protocols, cache misses caused by inter­processor communication are a dominant source of proces­sor stall cycles for many applications.
Sentence 2: modern processors spend a signi.cant fraction of their time sitting idle, waiting for a memory reference that could not be ser­viced by its local cache hierarchy and instead must be trans­mitted by a more distant source.
Relationship: reasoning
Domain: Hardware
Sentence 1: 1 Introduction A key component of the emerging System-on-Chip (SoC) architectures is the on-chip interconnect, which is ex­pected to play a crucial role in dictating the performance, energy, and fault-tolerance of the overall system with tech­nology scaling [2, 6, 12].
Sentence 2: design and analysis of scal­able on-chip interconnects, also known as Network-on-Chip *This research was supported in part by NSF grants, EIA-0202007, CCF-0429631, CNS-0509251, CAREER 0093085, and a grant from DARPA/MARCO GSRC.
Relationship: reasoning
Domain: Hardware
Sentence 1: For each region Rx,y,w,h, lines 7-10 build its outgoing net set by a DP technique, in which Rx,y+h-1,w-1,1, Rx+w-1,y+h-1,1,1, and Rx,y,w,h-1 are the sub-regions of Rx,y,w,h and their outgoing sets are already obtained in the previous iterations of the nested loops in lines 5-14.
Sentence 2: based on Property 1, line 8 can merge S(Rx,y+h-1,w-1,1) and S(Rx+w-1,y+h-1,1,1) to build S(Rx,y+h-1,w,1), and then S(Rx,y+h-1,w,1) and S(Rx,y,w,h-1) also can be merged to build S(Rx,y,w,h) at line 10.
Relationship: reasoning
Domain: Hardware
Sentence 1: Node v is connected to the sets E1 and E1 of external hyper­edges eligible for boosting, where |E2|>|E1|, and to the sets of internal hyperedges sets I1 and I2.Node uis connected to only the internal hyperedges sets N1 and N2,where |N1| = |I1| and |N2| = |I2|.
Sentence 2: the gain of moving node vfrom partition 1 to partition 2 is dv = |I2|-|I1|+ |E2|-|E1|, while the gain of mov­ing node uis du = |N2|- |N1|.
Relationship: reasoning
Domain: Hardware
Sentence 1: Because our goal is to remove the correlation responsibil­ity from a human analyst, we evaluate our correlators with respect to how they perform compared to a human expert.
Sentence 2: to perform this evaluation, one of the authors manu­ally labeled each metric with yes, maybe, or no, depending on whether or not the pattern in the metric visually corre­lates with the pattern in the target metric.
Relationship: reasoning
Domain: Hardware
Sentence 1: 2.1 Metrics Onemetriofanerasure­resilientodeispartiularlyim­portant:Theupdatepenaltyisthenumberofhekdisks whoseontentmustbehangedwhenanupdateismadein theontentofagiveninformationdisk.Ifmhekdisksare involvedinawrite,thentheparallelismofthediskarray isreduedbyafatorofm+1.Soupdatepenaltiesmust bekeptassmallaspossible.Theupdatepenaltiesofan erasure­resilientodewithparity­hekmatrixH=[CII] aretheolumnsumsofC.Sineupdatesofdataareusually muhmorefrequentthanthereonstrutionofdatadueto erasures,theupdatepenaltiesaretypiallyofmostonern.
Sentence 2: ifanerasure­resilientodeisabletotolerateallk­erasures, theneveryupdatemustafettheontentofatleastk+1 disks(oneinformationdiskandkhekdisks).the updatepenaltiesofak­ERCareatleastk.(Amoregen­eralresultisprovedin[20].
Relationship: reasoning
Domain: Hardware
Sentence 1: Beside a constant value k (for the control logic), it needs 1log2Nl .ip-.ops for a scan shift position counter and 1log2N/W l .ip-.ops for the word position register for a module with N .ip-.ops connected to a W -bit wide bus.
Sentence 2: the .ip-.op overhead is: HSC N F F k + Z + 1log2Nl + 1log2 l + W (3) W The additional amount of look-up tables HLU T is in the worst case given by the logic for the scan chain interface plus an additional LUT for the scan multiplexer in front of each .ip-.op of the module.
Relationship: reasoning
Domain: Hardware
Sentence 1: Due to the access patterns of the B matrix, the data must be transfered down in its entirety before the computation can begin5.
Sentence 2: the time is: 4N2 TTot = H ost BW + TMM + 2 × H ost Lat (10) The H ost BW term in Equation 10 is given in double­precision .oating-point items per cycle in this case.
Relationship: reasoning
Domain: Hardware
Sentence 1: Resolution enhancement techniques (RETs) and other patterning solutions such as immersion and double-patterning lithography (DPL), off-axis illumination (OAI), sub-resolution assist features (SRAFs), and phase-shift mask (PSM) re­quire additional layout-restrictive DRs [5 11].
Sentence 2: early assessment of design restrictions imposed by technological choices is absolutely essential.
Relationship: reasoning
Domain: Hardware
Sentence 1: Consider the input transition in a particular clock cycle.Under this condition, if the input does not make a transition inthe next clock cycle (cycle E and F in Fig.
Sentence 2: 5), then the fallingedge of the pulse from the cycle E will reach the far-end of theline before the end of cycle F. This means that the far-end ofthe line would be at logic high at the end of cycle E and atlogic zero at the end of the cycle F. the output of thelatch will be toggled at cycle F but not at cycle G, correctlycapturing the input transitions.
Relationship: reasoning
Domain: Hardware
Sentence 1: Allowing temporary violation of x-net constraints may later result in an increase in i-nets within acceptable limits.
Sentence 2: the cabs which violate only x-nets are kept in a separate list, called as x-net reduce(c) 1: while (x net(c) > x net limit) 2: for (each neighbor n of c) 3: if (c is available for n) 4: pkey[n] = # nets in n not link to c; 5: skey[n] = # nets in n link to c; 6: if (no n is available) 7: return FALSE; 8: add n with max skey[n] with min skey[n]; 9: return TRUE; Figure 6: Pseudo code for x-net reduction algo­rithm.
Relationship: reasoning
Domain: Hardware
Sentence 1: In this way, the original data dependency in each iteration (or intra-iteration data dependency) has been transformed into successive iterations (or replaced by an inter-iteration data dependency).
Sentence 2: with the disappearance of intra­iteration data dependency, all the computations in one it­eration can be performed in parallel and, as shown later, the corresponding KES block can achieve the critical path of only Tmult + Tadd.
Relationship: reasoning
Domain: Hardware
Sentence 1: From Figure 5, when the TSV path is exploited a significantly larger current can be supplied to the transistors without exceeding the allowed voltage ripple.
Sentence 2: for the circuit shown in Figure 4b the limit of the voltage drop is reached where ILmax = 3.3 mA, while for the circuit that includes the TSV path the maximum current that can be sustained is ILmax = 9.4 mA; a considerable 2.8× increase.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then, the sum of the leakage terms Ii in grid k is given by: sub t 0 X Yi +ß0·dLk ß1·dT oxi e · ai ·e (13) i=1 The second part of the expression above is a sum of independent lognormal variables, which is a special case of sum of correlated lognormal variables, and this can be computed in linear time using Wilkinson s method.
Sentence 2: for gates of the same type with the same input state in the same grid, only a linear time complex­ity is needed and the sum of leakage of these gates is .nally ap­proximated by a lognormal variable that can be superposed in the original expression.
Relationship: reasoning
Domain: Hardware
Sentence 1: As a small misprediction in (a(d),t(d)) might change the dominance relationship among design points, we also predict points that are likely to be Pareto-optimal even though they are not given their predicted values (a(d),t(d)).
Sentence 2: q2 is composed of points that are not in Q1 (since those are already predicted to be Pareto-optimal), and that are not dominated when points in Q1 take values at the bottom-right corners (worst outcomes) in the con.­  Figure 4.
Relationship: reasoning
Domain: Hardware
Sentence 1: 0.63 0.100 0.20 0.17 4 0.23 0.63 0.200 0.20 0.18 3 0.23 rc In a typical microprocessor design, around 10% 20% on­ 0.48 0.100 0.20 0.17 4 0.25 chip global interconnects are inductively coupled and they 0.48 0.200 0.20 0.18 3 0.25 0.12 0.200 0.20 0.19 3 0.18 are usually critical wires.
Sentence 2: we choose one netlist 0.86 0.100 0.89 0.49 7 0.36 0.86 0.200 0.89 0.71 5 0.39 which has inverters driving two 1mm-long capacitively cou­ 0.63 0.100 0.89 0.48 6 0.32 0.63 0.200 0.89 0.68 5 0.36 rlc pled lines, and the other which has inverters driving two 0.48 0.100 0.89 0.49 5 0.29 5mm-long lines with both capacitive and inductive coupling.
Relationship: reasoning
Domain: Hardware
Sentence 1: Considering k outputs of a primitive, the threshold magnitude error rate (tme) is de.ned simply as the ratio of the number of deviations by more than d from the correct value to the total number of outputs.
Sentence 2: the Table 2: Energy-probability relationship of a pcmos inverter designed in tsmc 0.25µm technology with a noise magnitude (rms)value of 0.4V .
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, the improvement (or deterioration) of the design space depends mostly on the change in DSM between points B and C as a function of a particular design variable.
Sentence 2: we de.ne the design-space sensitivity to the     3 3 3 2 2 2 1 1 1 0 0 0 RP [k: ] RP [k: ] (a) VDD =1.0V and .
Relationship: reasoning
Domain: Hardware
Sentence 1: Our goal is to show the usefulness of the proposed max operation in an SSTA framework.
Sentence 2: to emulate the actual use of these results in true statistical max algorithm, we generated a test suite consist­ing of skewed arrival time distributions by running 50,000 Monte Carlo(MC) simulations on a toy circuit that that mimics the behav­ior of a real circuit.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus the order of notes on the spiral is: C, G, D, A, E, B, F#, C#, G#, D#, A#, F. It is noted that if the music interval between two notes is more possible to be harmonic interval, the distance between these two notes is smaller on the helix.
Sentence 2: the distance between notes with interval m can be utilized as the weighting of r(m).
Relationship: reasoning
Domain: Hardware
Sentence 1: The .rst key idea is to understand that intervals, like .oating point representations, inevitably accrue more errors as they push through deep chains of calculation.
Sentence 2: we replace the interval­valued modi.ed-nodal analysis (MNA) formulation and LU de­composition of [12] with interval-valued versions of the standard path-tracing algorithms [15] which signi.cantly reduces both the number of operations for (orthonormalized) moment generation, and the overall estimation error.
Relationship: reasoning
Domain: Hardware
Sentence 1: In this case, it is not straightforward for a designer to .gure out how to design a workable memory array with the minimum energy consumption and area overheads.
Sentence 2: the following sections V B1 V B2 V B3 V Bn RV Vwm V wm V wm-1Vwm-1 Vw1 V w1 RVVB1 VB2 VB3 VBn  Figure 1: The circuit model of the cross-point array.
Relationship: reasoning
Domain: Hardware
Sentence 1: For a constraint of the form a + b+ c + d = 1 where a, b, c and d are variables in the range [0, 1], we know that only one of them is to be rounded up to one, while the remaining variables should be zero.
Sentence 2: we consider vari­ables in groups, and de.ne an ordering for rounding those variables as explained in the following sections.
Relationship: reasoning
Domain: Hardware
Sentence 1: Substituting .V=0 into (1) and (2),  and optimal Vs are equal to 2I V 4V 2pfC I pssp p = (3) Vs,optimal = (4) p p 4pfC p Expression (4) indicates that the optimal voltage for maximum power harvesting depends on the vibration magnitude Ip and frequency f, which vary with the deployment environment and time.
Sentence 2: the maximum power point is also changing with the vibration status.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then, for the picked unit capacitors (i.e., there exists k+l unit capacitors), we can pair them according to the following cases:  Case 1. k and l are both odd: we pick one unit capacitor from k unit capacitors and from l unit capacitors, respectively, and consider the two selected unit capacitors as a pair.
Sentence 2: the remaining unit capacitors can form (k-1)/2 and (l-1)/2 pairs.
Relationship: reasoning
Domain: Hardware
Sentence 1: This scheme can be generalized by assuming that the origi­nal sleep transistor in n equally-sized parallel sub-sleep tran­sistors (as it is usually done), and add m redundant sleep transistors.
Sentence 2: since at each period only n over n + m paral­lel sub-sleep transistor must be activated, to guarantee the proper current capability), the new 0 probability P ' (Vg=0) becomes: ' m P(Vg=0) = P(Vg=0) ·1 - (4) n + m This approach is equivalent to over-sizing the sleep tran­sistor, in particular, to a size of: m W ' ·1 + (5) sleep = Wsleep n in terms of overhead it has the same disadvan­tages of the .rst solution.
Relationship: reasoning
Domain: Hardware
Sentence 1: For the logic gates discussed above, we only need the values of d(v,b) and tb(e), and not d(w,b ) and tb(e) simultaneously, where b denotes the complement of b.
Sentence 2: we need correlations between d(vi,b) (1=i=k), but not correlation between d(v,b) and d(v, b ) .
Relationship: reasoning
Domain: Hardware
Sentence 1: The differences are that the LSQ is accessed by both the IXU and the OXU and the processes of the LSQ are partially omitted as follows: 1) Omitting Order Violation Detection: When a store 01 n-1  iFU n-1 muxResult Wires iFU 1 mux iFU 0 mux    mux oFU 0 mux oFU m-1   instruction is executed in the IXU, there is no succes­sor load instruction that has already been executed.
Sentence 2: in this case, an order violation never occurs, and the search in the LSQ can be omitted.
Relationship: reasoning
Domain: Hardware
Sentence 1: Figure 3: A Revised Mux Based Scan C-Element  4.2 Test for Timing Constraints Delay faults in the data path of handshake circuits may increase the computation time, which not only may reduce the performance of the data path, but, more importantly, may also violate the bun­dled data constraint and cause the circuit to malfunction.
Sentence 2: these delay faults are more critical to test for.
Relationship: reasoning
Domain: Hardware
Sentence 1: The be eliminated from the critical path for the i-TLB, if the inter-cycle compaction scheme can be advantageous over design can perform the comparison against the MRU latch the intra-cycle compaction when the reuse address transla-as soon as the PC is updated before the subsequent fetch tion hit rate is higher.
Sentence 2: most of the benchmarks show cycle.
Relationship: reasoning
Domain: Hardware
Sentence 1: Another major problem of LLCs in 3D microprocessors is that LLCs are typically constructed by using several different dies, which means LLCs are most vulnerable to W2W variation; LLCs are composed of several layers in 3D microprocessors due to their large capacity(over 1MB).
Sentence 2: employing preventive techniques is necessaryfor LLCs to prevent severe yield losses.
Relationship: reasoning