sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Let F be the (2M +1) ×(2M +1) matrix with m-th row (F)m =[ v1 ,cos( 2pm ), ···,cos( 2pmM ), 2 2M+1 2M+1 sin( 2pm ), ···,sin( 2pmM )], ß(t)=[ß0(t),... ,ß2M (t)]T 2M+1 2M+1 2L and T(t)=[T(0,t),... ,T(2M2M+1 ,t)]T , which is the spa­tial vector of temperature samples.
Sentence 2: then, since F-1 = 2 FT 2M+1 , the BS can .nd ß(t)from T(t) and viceversa by: T(t)= Fß(t) .. ß(t)= 2 FT T(t) (7) 2M +1 to provide a set of reconstructed processes {ßTm(t)}2M m=0 T is equivalent to providing a reconstruction T(x,t).
Relationship: reasoning
Domain: Hardware
Sentence 1: BW: 25.6GB/s)close-and open-row FR-FCFS policy [41]64-entry transaction and command queues 11-11-11-28 tCAS-tRCD-tRP-tRAS 39-12-6-6 tRC-tWR-tWTR-tRTP 5-24 tRRD-tFAW dirty LLC eviction within the region.
Sentence 2: to minimize premature writebacks, BuMP employs the dirty region table (DRT) to keep track of cache-resident high-density modified regions that are evicted from the density table.
Relationship: reasoning
Domain: Hardware
Sentence 1: The purpose of the busy counters is to keep track of the remain­ing clock cycles for each (simulated) link to be idle.
Sentence 2: whenever a request arrives at the transmitter side, we choose a busy counter with the smallest value (representing the link that is the .rst to be available in future) for each con.gura­tion and increment each of them by the cumulative number of cycles to transmit the request packet over the link.2 As time goes on, all busy counters are decremented by one for each cycle until it reaches zero.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that finding the MICs of clusters is fast because it does not involve any matrix calculation, and there exist efficient heuristics [2][3][4] for this purpose.
Sentence 2: we assume the maximum instantaneous currents {MIC(Iclus1), MIC(Iclus2), MIC(Iclus3), MIC(Iclus4)} for all clusters are known in advance.
Relationship: reasoning
Domain: Hardware
Sentence 1: The value of Vfbb at which performance peaks depends to a .rst order on the ratio Ion/Ijunc smaller the ratio, smaller the maximum Vfbb that the device can tolerate before the increase in Ijunc starts dominating the increase in Ion.
Sentence 2: it is important to verify whether a sub-0.5V system has its performance peak in the Vfbb = Vdd regime.
Relationship: reasoning
Domain: Hardware
Sentence 1: A volume IE­based method is capable of handling arbitrary nonuniform materials with great ease, however, the resulting linear sys­tem of equations is not only dense but also large involving volume unknowns in the entire 3-D circuit.
Sentence 2: when the problem of interest involves complicated materials, the FEM method has been a popular method for choice because of its great capability in handling both irregular geometries and inhomogeneous materials.
Relationship: reasoning
Domain: Hardware
Sentence 1: A MHA consists of a set of Miss Status Hold­ing Registers (MSHR, also known as TBE) and the num­ber ofMSHRsdeterminesthe amountof outstandingmisses a cache can experience before it blocks.
Sentence 2: the more MSHRs a cache has the more a processor can go ahead be­fore stalling.
Relationship: reasoning
Domain: Hardware
Sentence 1: Let us assume that the delays of all tran­sitions are the same and that t2 is not enabled.
Sentence 2: from marking m(a)= 1, m(b)= 0, two transitions of the corresponding Markov chain are possible: Guard {a}is selected, transition t1 is enabled and .red lead­ing to a new marking m ' (a)= 0, m ' (b)= -1 with a negatively marked place b.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then the remaining time-points t1 to tn-1 are calculated such that they divide the range [0,tn] uniformly.
Sentence 2: the formula for tk is given by tk = (k / n) · tn (23) i+2 i+2 11 0 2a (t - t ) + i + 2 for k=0 to n. Sometimes, using a ratio approach given by i +1 i+1 11 0 b (t - t ) i + 1 .
Relationship: reasoning
Domain: Hardware
Sentence 1: If ez(Rj,Ri) is a critical Z-edge, then we have TCj-TCi = TPDi,j(max)-P. However, if pi,j > Di,j-di,j, we should have TPDi,j(max)=TPDi,j(min).
Sentence 2: ez(Rj,Ri) is not a critical Z-edge.
Relationship: reasoning
Domain: Hardware
Sentence 1: We measure and analyze this extra work in terms of energy (see Figure 7 in Section 5.2), and based on our studies, RaT consumes on average 57% more power for 2-thread workloads and 43% for 4-thread workloads than the basic ICOUNT fetch policy.
Sentence 2: raT requires more energy to increase the performance of the SMT proces­sor.
Relationship: reasoning
Domain: Hardware
Sentence 1: The restrictions on Proto for BioProto are implemented solely in the emitter: any Proto primitive that the BioProto emitter en­counters that does not have a :grn-motif annotation produces a compilation error, as does any literal that is not a Boolean.
Sentence 2: we simply declare and/or annotate only those primitives that are cur­rently supported; future expansions of BioProto to larger subsets of Proto can thus be handled simply by declaring/annotating the missing primitives or by adding the missing types to the language.
Relationship: reasoning
Domain: Hardware
Sentence 1: An invariant holds if all states of all paths of length k starting from the initial states satisfy the invariant, and there is no simple path of length k + 1 starting at an initial state or leading to a failure state, and not going through any other initial or failure states.
Sentence 2: the invariant is strengthened by eliminating those states that have some bad states among their successors at distance k or less.
Relationship: reasoning
Domain: Hardware
Sentence 1: requires 5478 bit-areas (one bit-area is the area required to implement one single-port SRAM bit) while the area required to implement a 2048-bit single-port array requires only 3229 bit-areas.
Sentence 2: the ratio of logic blocks packed per chip area for in both cases we conclude that dual-port arrays are a single port array is 0.0148, while the same ratio for a dual- not as efficient as single-port arrays when used to implement port array is 0.0117.
Relationship: reasoning
Domain: Hardware
Sentence 1: Second, we add a reset capability to the valid bit so the Power-Off signal can clear it.
Sentence 2: the first access to a power-off cache line always results in a miss regardless 244 ~ori~ Sl 2K cycle decay interval []64Kc 0 8Kc 1Kc] 0.15 ...................................................................................................................................................................................................  ~0.O9 i I = o.o6 -- ,co I 40 N i 20 i 0  &#38; Figure 5.
Relationship: reasoning
Domain: Hardware
Sentence 1: Conversely, if an ac­cess misses in ATD-LRU but hits in ATD-LIN, LIN is doing better than LRU.
Sentence 2: sCTR is incremented by a value equal to the costq of the miss incurred by ATD-LRU.6 Unless stated other­wise, we use a 6-bit SCTR counter in our experiments.
Relationship: reasoning
Domain: Hardware
Sentence 1: Essentially, the Vt-modulation capability by RBB weakens as short-channel effects become worse or body effect diminishes due to lower channel doping.
Sentence 2: rBB becomes less effective with technology scaling and as leakage currents are pushed higher by shorter L or lower Vt. Total Power (Watts) 100 10 3.1 Dual-Vt and Body Bias Dual-Vt designs can reduce leakage power during active operation, burn-in and standby.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3) Reservoir to PD separation: Fluids loaded in the reservoirs may contain .uorescent labels and thus they may in.uence the accuracy of a PD [15].
Sentence 2: the separation between a reservoir and a PD should be no less than a threshold LRP.A typical value of LRP is .ve times the length of electrodes on the DMFB [18].
Relationship: reasoning
Domain: Hardware
Sentence 1: Unlike forced circuits, which operate at .xed frequencies deter­mined by the inputs, frequencies of oscillators are internally ( au­tonomously ) determined and may change dynamically during op­eration.
Sentence 2: a major issue in oscillator envelope following is how to .nd the dynamically changing frequency accurately, such that envelopes vary smoothly and can be tracked ef.ciently.
Relationship: reasoning
Domain: Hardware
Sentence 1: Hence, the first derivative of the sine function in the first quadrant is scaled from the range [0, 1] to [0, p/2] [0, 1.57].
Sentence 2: we select segment slopes in the following set: {1.5, 1.25, 1.125, 1, .875, .75, .625, .5, .375, .25, .125, 0}.
Relationship: reasoning
Domain: Hardware
Sentence 1: A pseudo complementary implementation of MVL based on CNTFETs has been proposed; it replaces the resistors used in [2] with p­type CNTFETs (with their gates connected to ground) and utilizes threshold voltage operation by adjusting the chirality and the number of CNTs in each CNTFET.
Sentence 2: this approach (referred to as pseudo complementary) exploits the similarities in threshold voltage control in the p-and n-types while ensuring a correct MVL design for both ternary and quaternary logic gates.
Relationship: reasoning
Domain: Hardware
Sentence 1: As the number of cores on a chip increases, the pressure on the DRAM system will also increase and both the performance and fairness provided by the DRAM system will become critical deter­minants of the performance of future CMP platforms.
Sentence 2: to enable viable, scalable, and predictable CMP systems, fair and high­performance memory access scheduling techniques that control and minimize inter-thread interference are necessary [28, 22, 25].
Relationship: reasoning
Domain: Hardware
Sentence 1: After A/D conversion, the signal undergoes the selection in the correlator and the sub­sequent stages.
Sentence 2: in addition to the RF chip and DSP correlator, the following components are required: a band pass .lter for 1.575GHz,  50O matching networks for the LNA and the mixer on the RF chip,  IF band pass .lters at 175MHz plus a PLL .lter.
Relationship: reasoning
Domain: Hardware
Sentence 1: The time series of predicted location can be used to reserve/release resources in advance for the user s applications in di.erent cells.
Sentence 2: a measure of the quality of prediction can be de.ned as the fraction of wrong predictions over all predictions, i.e., the times that the cell phone is estimated to be in the wrong cell (leading to wasted resources in that cell, and missing resources in the cell where the cell phone actually is located).
Relationship: reasoning
Domain: Hardware
Sentence 1: We assume a 3D IC structure where all the channels are connected to a single coolant reservoir [3].
Sentence 2: for N modulated channels, the pressure drop across each channel (.Pi, i = 1, 2, ..., N ) can be written as a function of the chan­nel width function (based on the Darcy-Weisbach equation) and should satisfy the constraints: d (HC + wC i (z))2 .Pi =8µV.dz = .Pmax, (9) 0 (HC · wC i (z))3 .Pi = .Pj , .i, j = 1, 2, ..., N, (10) where µ is the .uid dynamic viscosity and .Pmax is the maximum allowable pressure drop in the system.
Relationship: reasoning
Domain: Hardware
Sentence 1: As an optimal trade-off be­tween accuracy and run-time, we chose the point (QUALITYintra = 100, QUALITYinter =50) because it yielded an accuracy within 0.009% of the 3s point with the highest discretization, with a run­time of 0.4 seconds.
Sentence 2: the work presented in this paper uses QUALITYintra = 100, QUALITYinter =50.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then: Square: Since z =x2, it is straightforward that .z, j =E[x2 j]=.x,(2 j) Power: In general, for a positive integer power n, the output is de.ned as z =xn.
Sentence 2: the moments at the output can be calculated as: .z, j =E[xnj]=.x,(n· j) Multiplication: The raw moments at the output of the multiplier can be calculated using the input moments and the correlation be­tween the inputs.
Relationship: reasoning
Domain: Hardware
Sentence 1: (9) i=0 Since when Si = 1, Y equals Zi, we have P (Y =1|Si = 1) = P (Zi = 1) = bni .
Sentence 2: (10) from Equations (4), (8), (9), and (10), we have n X bn pY = i Bin(t)= Bn(t), (11) i=0 which means that the circuit in Figure 3 with speci.c ran­dom variables as inputs implements the given Bernstein poly­nomial with coe.cients in the unit interval.
Relationship: reasoning
Domain: Hardware
Sentence 1: NOT (c),CNOT (c,b) C2NOT (b', c', a) .
Sentence 2: nOT (b), NOT (c),C2NOT (b,c, a) the final circuit is {NOT(c), NOT(c), CNOT(c,b), NOT(b), NOT(c), C2NOT(b,c,a)}.
Relationship: reasoning
Domain: Hardware
Sentence 1: 4.1 SPM Access Handling In a hybrid cache system, a memory access will be directed to the L1 cache and SPM according to its memory addresses.
Sentence 2: _ Figure 10: (a) An SPM Code Sample of riciandenoise (b) Detec­tion of Prefetching Loads Figure 11: Co-Simulation Support for HC-Sim  4.2 Prefetching Support and Prefetching Loads Prefetching is a common technique to improve the performance of SPM.
Relationship: reasoning
Domain: Hardware
Sentence 1: Selective logic gate upsizing, when combined with CNT process improvements, is effective in overcoming variations [Zhang 11a].
Sentence 2: in addition to performing gradient descent from our initial design point (with no upsizing and no processing parameter improvement), we also employ a gate upsizing algorithm: a parameterized fraction (..%) of the logic gates with the largest loads (in the nominal case) are upsized.
Relationship: reasoning
Domain: Hardware
Sentence 1: Obviously, this depth-.rst traversal is complicated in the pres­ence of loops (not present in Figure 5c) where circular dependen­cies can exist and the traversal could loop inde.nitely never reach­ing a leaf node.
Sentence 2: whenever Shoestring encounters a loop it forces the depth-.rst traversal to backtrack when the dis­tance between the instruction currently being processed and the instruction at the bottom of the loop exceeds Slat.
Relationship: reasoning
Domain: Hardware
Sentence 1: Memory [words of (n+k) bits]  Reconfiguration Logic  MUXes n Figure 6: Selecting a block of FBI latches during normal operation In figure 4, we note that during the normal operation, the outputs of the reconfiguration functions are constant, since the inputs of these functions are fixed at constant values during the repair phase.
Sentence 2: there is no delay added to the memory operation due to the computation of the output values of these functions.
Relationship: reasoning
Domain: Hardware
Sentence 1: When the load circuit is in stand-by (i.e., CLB= 1 and CL= 0 ), all the nRSm and pRSm switches are turned on, and both the pSW and nSW are turned off.
Sentence 2: the U-SVL and L-SVL circuits respectively generate a slightly lower supply voltage VD (=VDD-vn<VDD) and a relatively higher ground-level voltage VS (=vp>0V), where vn and vp are the total voltage drops of all nRSm and all pRSm, respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: a 24(1- Y ) a The expression of VDDmin in (37), (40), and (41) indicates that 1) VDDmin is a function of the square-root of logarithm of the number of inverters (N), 2) the slope is proportional to s pn , which is the standard deviation of the within-die VTH difference variation defined in (20), 3) the balance of the strength of PMOS and NMOS transistors, which is expressed as the parameter b in (40) hence the influences of those transistors are relatively small.
Sentence 2: the closed-form model can be applied to NAND and and (41), affects the intercept.
Relationship: reasoning
Domain: Hardware
Sentence 1: While some may appear to be Gaussian, in reality, their variation cannot vary from - to + as a Gaussian dis­tribution does.
Sentence 2: we propose a di.erent quadratic model to rep­resent all timing quantities in a timing graph as follows: X D = d0 + (aiXi + biXi 2) + arXr + brXr 2 , (4) where Xi represents global sources of variation, and Xr rep­resents purely independent random variation.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, as we discussed in Section II-A, sudden interruptions of the write/erase operations will result in the data corruption in a MLC NAND flash.
Sentence 2: we propose the following control scheme to guarantee the data integrity: during the normal operations of NFSS, the data of a P1 page is retained in the DRAM until the programming to its P2 page in the NAND flash array is completed.
Relationship: reasoning
Domain: Hardware
Sentence 1: In this work, the constants of a TMCM operation are represented in an m × n matrix C, where m and n are the number of outputs and time slots (the number of constants in an array), respectively.
Sentence 2: this work was supported by national funds through FCT, Fundac¸ao para a Ci encia e a Tecnologia, under project PEst-OE/EEI/LA0021/2013.
Relationship: reasoning
Domain: Hardware
Sentence 1: (i) Also, the constant term of the hyperplane, ß0 , was changed, by (i) increasing its value to .0 = P. Notice that the original value (i) ß0 =P because this is not the peak plane.
Sentence 2: it is impossible for the raised plane to under-estimate the delay at a corner C t which has Y1 = 0.
Relationship: reasoning
Domain: Hardware
Sentence 1: The plaintext P is typically gen­erated from a shorter string (in our case ID) by padding it with random bits until it is the size of n. The RAM e.cient variant of the Rabin scheme does away with the modular reduction step, replacing it with an addi­tion of a random multiple of the divisor.
Sentence 2: instead of M = (mod n) the tag transmits M =+ r · n. This P 2 P 2 replacement was shown in [15, 19] and more recently in [20] to have no detrimental e.ect on security, as long as the size of r is properly chosen ([15] suggests a value of |n| + 80).
Relationship: reasoning
Domain: Hardware
Sentence 1: ENERGY EFFICIENT CACHE ARCHI-TECTURES Thestudyofcacheenergyconsumptionisrelativelynew andtheoptimizationtechniquescanbebroadlyclassifed ascircuitandarchitectural.Themaincircuitoptimiza­tionsincludeactivatingonlyaportionofthecellsonthe bit(DBL)andwordlines,reducingthebitlineswingsus­ingpulsedwordlines(PWL)andisolatedsenseamplifers (IBL),andchargerecyclingintheI/Obufer[12].Theap­plicationoftheseoptimizationsisindependentofthecode sequencesthemselves.Manyarchitecturaltechniqueshave beenproposedasoptimizationsforthememorysystem[25; 13;16].Manyofthesetechniquesintroduceanewlevelof memoryhierarchybetweenthecacheandtheprocessordat­apath.Forinstance,theworkbyKinet.al.
Sentence 2: [16]proposed accessingasmallfltercachebeforeaccessingthefrstlevel cache.Theideaistoreducetheenergyconsumptionby avoidingaccesstoalargercache.Whilesuchatechnique canhaveanegativeimpactonperformance,itcanresultin signifcantenergysavings.Theblock-bufering(BB)mech­anism[13]usesasimilarideabyaccessingthelastaccessed, buferedcachelinebeforeaccessingthecache.Unlikecir­cuitoptimizations,theefectivenessofthesearchitectural techniquesisinfuencedbytheapplicationcharacteristics andthecompileroptimizationsused.Forinstance,software techniquescanbeusedtoimprovethelocalityinacache linebygroupingsuccessivelyaccesseddata.Then,acache buferingschemecanexploitthisimprovedlocality.increasingspatiallocalitywithinacachelinethroughsoft­waretechniquescansavemoreenergy.Adetailedstudy ofsuchinteractionsbetweensoftwareoptimizationsandthe efectivenessofenergy-efcientcachearchitectureswillbe usefultobothcompilerwritersandhardwaredesigners.
Relationship: reasoning
Domain: Hardware
Sentence 1: For example, using an experiment similar to the one used for XOR, the LUT implementation of NAND3 was 67% slower and consumed 25% more energy.
Sentence 2: while most FPGAs are based on homogeneous CLBs comprised of iden­tical LUTs, our VPGA CLB should be heterogeneous and include a combination of LUTs and simple logic functions.
Relationship: reasoning
Domain: Hardware
Sentence 1: 4.3 Statistical Static Timing Analysis AftertheVEXprocessor was synthesized withPhysicalCom­piler and static timing analysisperformed withPrimeTime, coarse placement as well as timing information were available through the def and the sdf .les respectively.
Sentence 2: we could apply theprocess variation modeldirectly tothegatedelays of the synthesized netlist.
Relationship: reasoning
Domain: Hardware
Sentence 1: Any guidance mechanism needs to know the design state, so the guided simu­lator must make additional function calls and memory accesses on each simulation cycle.
Sentence 2: what s worse is that making the simulation state visible at each cycle can disable some compiler optimizations, imposing a substantial slowdown.1 abstraction-guided 1Thanks to Valeria Bertacco for explaining this source of overhead.
Relationship: reasoning
Domain: Hardware
Sentence 1: E. Note that for the as­signed voltage V * less than Vth, trapped charge problem ei will not be incurred.
Sentence 2: vdi can be expressed as following: V * - max(Vth, Vprei ), if V * = Vth ei ei Vdi =0, if V * < Vth ei The global e.ect of trapped charge can be reduced by minimizing Vdmax , which is the maximum of Vdi (see Eq.
Relationship: reasoning
Domain: Hardware
Sentence 1: 4.5 Further Optimization with More SNDRs Recall that our proposed methodology focuses on transparency to existing CTS .ows, i.e., we perform the wire sizing after routing, potentially just before design closure and signoff.
Sentence 2: we limit our selection of SNDRs to constant track cost, so as not to harm the original design with noise coupling or with routing ECOs.
Relationship: reasoning
Domain: Hardware
Sentence 1: It can be easily deduced that a group (j1G ,j2G ,j3G)E JGwill be executed in node (j1G ,j2G)during the time step t(jG)=j1Gj2Gj3G .
Sentence 2: the linear time schedul­ing vector for this example is IG=(1,1,1).
Relationship: reasoning
Domain: Hardware
Sentence 1: Fromthesedataweseethateachmodelhasitsown strengthandweaknesses.
Sentence 2: (1)Zarkesh-Ha'smodelcannot provideEpredictionandittakesp(Rentexponent)asanre­quiredparameter.thePrefmodelprovidesthemost reasonablefanoutdistributionprediction.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, the distance of the conditional Pi+1)­ distributions between the two neighboring states is E(xm E(YPi+1+.m E(xm Pi), which is equal to Pi+1)-E(YPi+.m Pi).
Sentence 2: since program interference is mainly determined by the threshold Pi+1) voltage changes on the direct-neighbor aggressor cells, E(.m and E(.m Pi) are close as the neighbors are programmed to the same value m. E(xm Pi+1)-E(xm Pi) is similar to E(YPi+1)­E(YPi), which is equal to the distance of the neighboring distributions before neighbor cells are programmed and is independent of the exact values programmed to the direct­neighbor aggressor cells.
Relationship: reasoning
Domain: Hardware
Sentence 1: During each interval [ta(c m , ), ta(c m , ) + t], t > 0, exactly id id t cells arrive at the PPS and destined for the same output­port j (i.e., there are no stalls between the cells comprising tra.c T ).
Sentence 2: lemma 3.8 implies that for each cell c such that ta(c) > ta(c m , ), R(ALG, d, c) .
Relationship: reasoning
Domain: Hardware
Sentence 1: -VS2 = ftF (if2) (5) So, one can conclude that if the resulting M1 current ID1, that was chosen to keep M1 operating with if1 = 3, is also used to control the drain current of M2 (through the M5-M6 current mirror), M2 also operates under a constant inversion level, making F (if2) constant.
Sentence 2: if a voltage propor­tional to ft is attached to the source terminal of M2, with the right proportionality factor F (if2) adjusted (using the current mirror aspect relation K1), the equality of (5) can be satis.ed.
Relationship: reasoning
Domain: Hardware
Sentence 1: Given a reversible function f, the complexity measure C(f) is equal to the sum of the individual Hamming distances between input assignments and output assignments for all rows of the truth table of f. After considering different variants of complexity measures based on decision diagrams, we have chosen the following one: Definition 5 The complexity measure D(f) of an n*n reversible function f is equal to D(f) = s(f) - n, where s(f) denotes the number of non-terminal nodes in the reduced ordered SBDD of f with complemented edges.
Sentence 2: d(identity function) = 0.
Relationship: reasoning