sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: After updating the array for all samples, the action for each state is the one that minimizes the metric.
Sentence 2: after up­dating the Acc table for all samples, the action for each state, ST[CPIkij ][L2PIkij][MPIkij][i][j], is the frequency combina­tion (x,y) that produce the minimum Acc[CPIkij][L2PIkij][MPIkij][i][j][x][y].
Relationship: entailment
Domain: Hardware
Sentence 1: The basic implementation is to prefetch data P iterations earlier than its actual access to hide the load latency, where P is the estimated prefetch latency from lower-level memory in terms of loop iteration [15].
Sentence 2: in order to hide the memory access latency, the prefetching instruction of the memory reference set at iteration i + P + 1 will be issued at iteration i and will replace iteration i s data access set.
Relationship: entailment
Domain: Hardware
Sentence 1: In the current-limited regime, complementary LC-VCOs o.er higher gm for a given bias current and lower switching transis­tor noise than NMOS only VCOs [8].
Sentence 2: to obtain the same phase noise performance, the complemen­tary LC-VCO consumes less power than NMOS/PMOS-only topologies.
Relationship: entailment
Domain: Hardware
Sentence 1: Practical Aspects of Reliability Analysis for IC Designs T. Pompl 1 C. Schlünder 1 M. Hommel 1 H. Nielen 1 J. Schneider 2 +49 89 234 41029 + 49 89 234 52934 +49 89 234 40491 +49 89 234 50632 +49 89 234 23974 thomas .pompl christian.schluender martina.hommel heiko.nielen jens.schneider @infineon.c om @infineon.c om @infineon.c om @infineon.c om @infineon.c om 1 Infineon Technologies, Otto-Hahn-Ring 6, 81730 Munich, Germany 2 Infineon Technologies, Am Campeon 1, 81726 Munich, Germany ABSTRACT Voltage analysis is a major part of design-in reliability as voltage is the driver for electric degradation in dielectrics and MOS devices.
Sentence 2: voltage has the largest influence on gate oxide reliability.
Relationship: entailment
Domain: Hardware
Sentence 1: Besides, because m, p, and q are relative to the dimension of the crossbar n, we assume m = km × n, p = kp × n, and q = kq × n. Then, we can rewrite (1) as 22 2 Area = (2 + k )( k + k )Pn + (2 + k )Pn .
Sentence 2: (2) m p qnw mnw Area = O(n2).
Relationship: entailment
Domain: Hardware
Sentence 1: Recent proposals include lightweight block ciphers HIGHT [16], PRESENT [5], CLEFIA [20], LED [14], PRINCE [6], and SIMON/SPECK [4], lightweight stream ciphers Grain [15], Trivium [8], and MICKEY [3], as well as a lightweight hybrid cipher Hummingbird [10] and its security en­hanced version Hummingbird-2 [11].
Sentence 2: lightweight symmetric ciphers have also attracted a lot of attention from indus­try, as demonstrated by the adoption of CLEFIA and PRESENT in the ISO/IEC Standard 29192-2.
Relationship: entailment
Domain: Hardware
Sentence 1: (fk)is the cor­responding fault rate and si is the slack allocated to Tk (part of which is reserved for recovery).
Sentence 2: whenever the available slack is larger than the task s WCET, by scheduling a recovery task, one can preserve the reliability of a real-time task while 1In fact, such a slow-down may result in a reliability degradation of at least two orders of magnitude [27].
Relationship: entailment
Domain: Hardware
Sentence 1: The algorithm Tree-6-L(2, 1, 1)-coloring, instead of comput- ing the grid vertex to which each tree vertex is mapped, directly maps each grid edge to a shift on the color pattern sequence, thus obtaining the color of a tree vertex as the sum of the shifts along the tree path.
Sentence 2: cross-ing a vertical edge upwards corresponds to one left cyclic shift on the pattern sequence, crossing a vertical edge down- wards corresponds to one right cyclic shift, and crossing on a horizontal edge corresponds to a cyclic shift of three po- sitions.
Relationship: entailment
Domain: Hardware
Sentence 1: As discussed above, we need to update slack at the inputs of a node, v', only when the changed node, vc, is present along a proper subset of the inputs.
Sentence 2: while this notion works for an acyclic graph, it must be modi.ed for a strongly connected graph, since thereisapath betweeneverytwonodesinthegraph.Inthiscase, we use knowledge of tokens to determine when a timing change '' arrives a v. for each input edge, (u, v) .
Relationship: entailment
Domain: Hardware
Sentence 1: Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr Institute for Integrated Systems Aachen, Germany ADLs is to capture the architectural information required for the tool generation in a consistent and unambiguous way.
Sentence 2: the C compiler and the instruction-set simulator (possibly on differ­ ent abstraction levels) require the speci.cation of the instructions semantics, however, from very different points of view.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that this level of information can allow us to perform detailed optimizations which could not be possible underthe coarse grainimplementation.Forexample, bykeepingharmful prefetch andcachemissinformation ata client pair granularity, we can throttle I/O prefetches from a clientonlyif suchprefetcheswilldiscardthedataofa certain other client or set of clients, and let the remaining prefetches it issues go through.
Sentence 2: it can be possible to tunethebehaviorof eachclient asfar asI/Oprefetchingis concerned with respect to the behavior of every other client individually.
Relationship: entailment
Domain: Hardware
Sentence 1: This paper presents the exploration of different con.gurations of a double gate fully depleted SOI based FinFETs for ef.cient design of current mirror designs.
Sentence 2: com­parison among the important Figures-of-Merit (FoMs) current mir­ror designs including mismatch, variability, output resistance (r0), compliance voltage (VCV ) is presented for: (1) shorted-gate (SG), (2) independent-gate (IG), and (3) low-power (LP) con.gurations.
Relationship: entailment
Domain: Hardware
Sentence 1: Signals produced by a relatively slowly-varying linear filtering process are most suitable for LPC, especially, if the filter is excited by infrequent, brief pulses.
Sentence 2: [2] a signal s spectral magnitude, as opposed to phase, is widely used (e.g., in human perception, it is more important to model the magnitude of speech spectra accurately than their phase).
Relationship: entailment
Domain: Hardware
Sentence 1: 4.1 Delay noise from skew window It has been shown in [15] that regardless of the aggressor transi­tion, the worst-case delay noise occurs when the victim input transi­tion occurs at the latest point in its timing window.
Sentence 2: adding the worst-case delay noise to the late victim input arrival time will result in the maximum slowdown (increase in the victim output timing window).
Relationship: entailment
Domain: Hardware
Sentence 1: Because of the blockages and the boundary restriction in the micro.uidic array, it is hard to directly apply the three rules to the ILP formulations in the cell set C. For example, if a droplet di stalls at the location (0,0) within time t - 1 to t in Figure 2 (a), due to the boundary restriction of micro.uidic array, the exact number of must-be-deactivated cells is 3 instead of 8.
Sentence 2: we may need extra constraints and variables to de­termine the exact number in EC-Rule II, which signi.cantly in­creases the complexities of the ILP formulations.
Relationship: entailment
Domain: Hardware
Sentence 1: As­sociated with each core, there is a locality &#38; utility monitor that dynamically pro.les both NRU and BNRU hit curves from the core s SLLC reference sequence.
Sentence 2: the NRU and the BNRU hit curves are captured by an LRU pro.ler and a BNRU pro.ler respectively, both of which are based on auxiliary tag directories (ATD) and the set sam­pling technique [10].
Relationship: entailment
Domain: Hardware
Sentence 1: [5], the bounds derived in Theorem 1 can be used to determine the maximal delay of events and the necessary memory to store packets waiting to be processed.
Sentence 2: the following two equations give bounds on both quantities: delayc = sup inf{t= 0: au c (u)= ßl c(u +t)} (7) u=0 {} backlogc = sup{au c (u)- ßl c(u)} (8) u=0 the delay can be bounded by the maximal horizon­tal distance between the curves au and ßl , whereas the backlog is bounded by the maximal vertical distance between them.
Relationship: entailment
Domain: Hardware
Sentence 1: We should try to keep the congestion with newly generated directives similar to that without any directives.
Sentence 2: the congestion constraint to the LDA problem can be gLDA = ßgorg , where gLDA and gorg are calculated by a congestion metric of the routing solution with and without assigned directives, respectively, and ß is a user-de.ned parameter.
Relationship: entailment
Domain: Hardware
Sentence 1: This paper elaborates on this challenge and summarizes our ideas and contributions towards a solution, as presented in a hot-topic special session at DATE-2012.
Sentence 2: we present several key approaches and tools: the StarPU runtime system, based on performance-aware dynamic scheduling and selection of task variants to auto­matically run on the most suitable type of execution unit in the context of heterogeneous systems, combined with the SkePU skeleton programming library as front-end to provide abstraction and more parallelism (Section II);  the Of.oad-C++ language, an extension of C++ for high­level portable programming of accelerator-based systems, and its compiler to OpenCL (Section III);  the PEPPHER component model and methodology to achieve performance portability for applications based on annotated software components that expose their im­plementation variants, performance-relevant metadata and tunable parameters in an extended composition interface (Section IV).
Relationship: entailment
Domain: Hardware
Sentence 1: For example, assuming reports of 10 32-bit resource features per second, a large provider like Amazon (say 100K instances) would have at least an overhead 10 * 32 * 100K 32 Mbps of outbound traf.c to send these reports (ignoring metadata and cryptography).
Sentence 2: to reduce this bandwidth cost, we envision an aggregation step that processes the log entries before generating R. given the attested reports across multiple time epochs, a trusted aggregator generates a sta­tistical summary of the resource consumption vector across time.
Relationship: entailment
Domain: Hardware
Sentence 1: x[14] X[7] X[15] x[n+3N/4] j W 3n N Instead of the row-wise parallelization in pipelined FFTs, it is also possible to parallelize along a column of the SFG as shown in Figure 2(a).
Sentence 2: n/r butter.ies are instantiated to compute one stage (i.e.
Relationship: entailment
Domain: Hardware
Sentence 1: Analytical models from Section 2 are employed in this part.
Sentence 2: the number of PMOS transistors computed from the synthesis in Stage#1 is used to represent the circuit as a bare collection of (PMOS) transistors; this matrix representation is initialized with default threshold voltage values according to the reference technology node and according to process variation pa­rameters (see Section 5 for more details on this).
Relationship: entailment
Domain: Hardware
Sentence 1: [17] have provided evidence suggesting that it is possible to tune the recti.ca­tion or current-voltage asymmetry either by changing the end group of the molecular device or by changing the ac­tual metal contact [7].
Sentence 2: the asymmetry ob­served in the molecular current-voltage characteristics may be caused by the di.erences in the metal-molecule coupling at the two contacts.
Relationship: entailment
Domain: Hardware
Sentence 1: There are two critical cycles that determine the cycle time twchb (the time be­tween the generation of two successive tokens) of the pipeline [3].
Sentence 2: 3teval + tprech + 2tCD , if teval = tprech twchb = 2teval + 2tprech + 2tCD , if teval < tprech where teval is the evaluation time, tprech is the precharge time through the PMOS pull-up network, and tCD is the output completion detection time.
Relationship: entailment
Domain: Hardware
Sentence 1: Overall, STT-MRAM is regarded as the most promising and capable eNVM for providing a unified eNVM solution for emerging mobile products.
Sentence 2: when a mobile system has a low duty cycle, the values of embedded STT-MRAM can be maximized by replacing eFlash, OTP, retention flip-flop, and SRAM simultaneously, delivering the eNVM-only memory configuration.
Relationship: entailment
Domain: Hardware
Sentence 1: If the path constraint con.icts with an antecedent A ' of the property being checked, the corresponding path program will also be at con.ict with antecedent A ' .
Sentence 2: a ' is always false on the path program, which implies that the property will be true on this path program since our property is in the form of G(A ' * X =tB ' ).
Relationship: entailment
Domain: Hardware
Sentence 1: ; obtain addressing result by solving MCMF network; for each net in addressing result do route the net; if failure route then reroute or drop this addressing result; else update pin assignment; end end escape route for all nets; return pin assignment result and routing solution; end The main idea in our addressing and routing algorithm is we discussed in Section 4.1.
Sentence 2: we construct Gvcc 357 problems corresponding to a pin-electrode merging.
Relationship: entailment
Domain: Hardware
Sentence 1: Based on these de.nitions, and once the algorithm iden­ti.es the number of CPs as well as the number of FPs, the process is very simple: for each switch the algorithm checks if the number of connected ports minus the number of failed ports is more than one (line 15).
Sentence 2: the al­gorithm checks if the switch has more than one alive out­put port.
Relationship: entailment
Domain: Hardware
Sentence 1: We invoke additional semantic web lookup services such as dbpedia and freebase, or foursquare and geonames in order to enrich the descriptions of the 1 http://linkedevents.org/ontology/  Table 1: Number of event/agent/location and photo/user descriptions in the dataset published in [14] In this paper, we consider a subset of this events dataset that corresponds to the intersection of Last.fm, Flickr and YouTube.
Sentence 2: we consider the set of last.fm events for which there is at least one photo and one video shared respectively on Flickr and YouTube that has been tagged with the lastfm:event=xxx machine tag.
Relationship: entailment
Domain: Hardware
Sentence 1: We have to ensure that the node uses no more than energy ED during the next day.
Sentence 2: we have to take into account a worst case situation where all energy used to drive t1 and t2 has to traverse the battery with conversion e.ciency .. We can write N22-1 N22-1 e1 ·L2 · r1(t + i)+ e2 ·L2 · r2(t + i)= .
Relationship: entailment
Domain: Hardware
Sentence 1: 1.3 Paper Goals and Organization The remainder of this paper focuses on the architectural design choices to enable the SD-MUXes, the supporting CAD toolflow, and the experimental evaluation thereof.
Sentence 2: it is of great importance to ensure than the introduction of SD-MUXes does not significantly impair the performance of industrial-scale circuits that do not use the dynamic multiplexing functionality; fortunately, no adverse affects were observed in our experiments.
Relationship: entailment
Domain: Hardware
Sentence 1: Each storage block should have dimensions in such a way that Assuming that P denotes the total number of processor its size, SIZEm (given as input), will .t into the allocated cores, M the total number of storage blocks, (CX ,CY ,CZ ) space.
Sentence 2: sIZEm =width × height: the dimensions of the chip, (PX ,PY ) the dimensions of the processor core, our approach uses 0-1 variables to specify the CX CY coordinates of each storage block and processor core.
Relationship: entailment
Domain: Hardware
Sentence 1: Below, we sketch an illustrative proof for both stability and zero tracking error in one example scenario.
Sentence 2: we consider the case where the power efficiency (EC) and the power capping (SM) controllers are nested as shown in Figure 2, and prove the following two results: (i) The EC controller can make the CPU utilization track a specified utilization target by dynamically tuning the clock frequency, in spite of slow changes in the workload demand; (ii) The SM controller can make the server power consumption track a given local power cap, possibly set by the upper layer controllers such as the EM or the GM, by dynamically tuning the utilization target fed into the EC controller.
Relationship: entailment
Domain: Hardware
Sentence 1: We now show that the escape routing problem transformed into a SAT problem of the form can be F =FGFEFP FS =1 (2) where G, E, P , and S are the sets of all grid nodes, edges, pin nodes, and slot nodes, respectively.
Sentence 2: we are looking for a variable assignment to simultaneously satisfy the 2) Construct FE: For each edge e, either the edge variable is equal to 0, or the two nodes connected by e are equal.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION Information Technology (IT) industries have greatly advanced over the past few years.
Sentence 2: as the Internet is being rapidly and widely distributed, user created contents (UCCs), which users actively participate in making and sharing multimedia Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: entailment
Domain: Hardware
Sentence 1: di Automatica e Informatica Politecnico di Torino Torino, ITALY 10129  ABSTRACT The e.ects of temperature on delay depend on several pa­rameters, such as cell size, load, supply voltage, and thresh­old voltage.
Sentence 2: variations in Vth can yield a tem­perature inversion e.ect causing a decreases of cell delay as temperature increases.
Relationship: entailment
Domain: Hardware
Sentence 1: The second is maintaining a consistent or­der of realizing any two circuits that share routers relative to each other in all the shared routers.
Sentence 2: for any two circuits, C1 and C2, that share a sub-path, p, either C1 is realized before C2 in all the ports on p, or C2 is realized before C1 (see Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: Trunk Decomposition Based Global Routing Optimization Devang Jariwala Dept of Computer Science Uni of Illinois at Chicago djariwal@cs.uic.edu ABSTRACT We present global routing optimization methods which are not based on rip-up and re-route framework.
Sentence 2: the routing optimization is based on trunk decomposition [13] of the global routing.
Relationship: entailment
Domain: Hardware
Sentence 1: HMOR, a fusion of circuit decomposition theorems and mo- ment matching algorithms, can be easily embedded into in- terconnect synthesis algorithms to perform hierarchical tim- ing and multi-attacker noise analysis with great efficiency and accuracy.
Sentence 2: we present its application to re- , peater insertion for multiple-attacker noise analysis for both capacitive and inductive coupling.
Relationship: entailment
Domain: Hardware
Sentence 1: However, this does not mean that all components of a given application will work well un­der the disk layouts determined by our pro.le-driven approach.
Sentence 2: while it is expected that the layouts found by our ap­proach will operate well for most of the loop nests of the applica­tion, it is still possible that these layouts perform poorly for a couple of nests.
Relationship: entailment
Domain: Hardware
Sentence 1: Recall from Section  2.2 that the key reason for the nearest-sharer choice is to achieve observational equivalence between the cache s coherence interface and the internal interface.
Sentence 2: because a cache interface would not make a read request for a block already present in shared, the internal interface should not make a read request for a block already present in its sub-tree and rather should require that the nearest sharer in its sub-tree provide the block.
Relationship: entailment
Domain: Hardware
Sentence 1: We show how the TTD can be used to implement tamper-evident storage where clients are guaranteed to immediately detect illegitimate modi.­cations to their data (including replay attacks and forking attacks) whenever they wish to perform a critical operation that relies on the freshness and validity of the data.
Sentence 2: we introduce and analyze a log-based scheme in which the TTD is used to securely implement a large number of virtual monotonic counters,which can then be used to time-stamp data and provide tamper-evident storage.
Relationship: entailment
Domain: Hardware
Sentence 1: In this code, Thread1 executes a tlbsync instruction that is effectively a fence for the MRF.
Sentence 2: the tlbsync guarantees that the tlbie instruction executed by Thread1 has been observed by other cores.1 Similar to the above programming example, a runtime hardware error or design bug could cause a TLB invalidation to be dropped or delayed, resulting in TLB inco­herence.
Relationship: entailment
Domain: Hardware
Sentence 1: Moreover, the adoption of Field Pro­grammable Gate Arrays (FPGAs) as the .nal implementa­tion platform rather than a rapid prototype target, further motivates the exploration of new techniques with respect to classical ones, tailored for Application Speci.c Integrated Circuit (ASIC) implementations, to focus on the peculiar aspects of the platform and of the faults that may corrupt the system behavior and computations.
Sentence 2: fPGAs exhibit a (re)programmable feature that is usually exploited at design time to con.gure the de­vice to perform the required functionality; such a con.gura­bility characteristic introduces both bene.ts and drawbacks since it derives from the presence of memory elements that can be programmed to provide the desired functions, but that are also a.ected by the considered faults.
Relationship: entailment
Domain: Hardware
Sentence 1: The objective of this paper is to propose a design, abbre­viated as FlashRec, that improves not only the logging over­heads but also the recovery performance for DBMSs over MLC (and SLC) .ash memory, where the low reliability and the partial-programming constraints of the MLC .ash mem­ory must be considered.
Sentence 2: a logging mechanism with start, update and end log blocks are proposed to sup­port e.cient transaction recovery in joint considerations of both wear-leveling and garbage collection over .ash memory.
Relationship: entailment
Domain: Hardware
Sentence 1: Since memory capacity scalesfaster than bandwidth, this delay is likely to increase in future smart­phones.
Sentence 2: while it is possible to accelerate the process by writing out only selected portions of the memory state, the challenges in doing so are similarto thosefacedby Flikker.the program­mer must identify critical data in the application and be prepared to restore the application based only on the critical data.
Relationship: entailment
Domain: Hardware
Sentence 1: However, an additional enhancement (lines 8a and 9) makes it possible to utilize the concrete constraints to enlarge viol(X) further.
Sentence 2: a small number of MUSes from the unsatisfiable formula conc X .viol X are extracted and used to select subsets of viol(X) each of which is sufficient to keep the formula unsatisfiable.
Relationship: entailment
Domain: Hardware
Sentence 1: To simplify the following discussion, we omit the initial duration d and amplitude a from the notations of MEI and MMI in Equations (2) and (3), but keep in mind that they actually exist.
Sentence 2: after adding wire w into the circuit, no matter how small MEI(s) is, a complete glitch with initial duration and amplitude is propagated from gate s to gate t once a high-energy particle strikes gate s. the resulting increase in error impact of gate s due to glitches propagated along the new connection w does not depend on MEI(s).
Relationship: entailment