sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: An IPC graph has to be: 1) a strongly-connected HSDF graph, i.e., for any two actors there exists a directed cycle (not necessarily a processor or a bus cycle) that contains both actors; 2) a first-in-first-out (FIFO) HSDF graph, i.e., in the self-timed execution, the completion events of actor firings occur in the same order as the corresponding starting events.
Sentence 2: tokens cannot overtake each other in an actor ([3 ­ §2.5.2]).
Relationship: entailment
Domain: Hardware
Sentence 1: Y. Charlie Hu, Alan Cox and Willy Zwaenepoel Department of Computer Science Rice University Houston, Texas 77005 {ychu, alc, willy}@cs.rice.edu Abstract We demonstrate that data reordering can substantially improve the performance of .ne-grained irregular shared­memory benchmarks, on both hardware and software shared-memory systems.
Sentence 2: we evaluate two dis­tinct data reordering techniques that seek to co-locate in memory objects that are in close proximity in the physical system modeled by the computation.
Relationship: entailment
Domain: Hardware
Sentence 1: However, network traces typically only give the absolute time when packets are sent, so the core may send pro­cessed data to the consumer prior to it even receiving the data from its producer!
Sentence 2: the network-trace approach fails to re­alistically evaluate application performance, because the timing of packet generation, which depends on on-chip network conditions, is assumed before the actual simulation of the network.
Relationship: entailment
Domain: Hardware
Sentence 1: ULE ways are reused at HP mode in spite of their ine.ciency at high Vcc because they reduce the number of slow and energy­hungry memory accesses [14].
Sentence 2: we use an 8KB 6T+10T hybrid cache as the baseline [13] with 8 ways and 32B/line, where 6 ways are implemented with di.erential 6T cells and 2 ways with 10T cells [11], although our proposal is not limited to this con.guration.
Relationship: entailment
Domain: Hardware
Sentence 1: Formally, we can de.ne a data transformation for an ar­ray Ausing a pair (MA,mlA).
Sentence 2: this pair (referred to as data transformation henceforth) performs the following two map­pings: X,!MAX xl,!x+l MAlmA the original reference matrix Xis trans­formed to MAXand the original constant vector xlis trans­formed to MAxl+mlA.
Relationship: entailment
Domain: Hardware
Sentence 1: A linear, time-varying system is a dynamical system for which the superposition principle holds but the time-invariant property may not.
Sentence 2: if y1(t) and y2(t) are the responses of the system to the input stimuli x1(t) and x2(t), respectively, then the response to a linearly combined input a·x1(t)+b·x2(t) is equal to the linearly combined output a·y1(t)+b·y2(t) where a and b are real numbers.
Relationship: entailment
Domain: Hardware
Sentence 1: Sets of circuit don t care conditions are classi.ed as con­trollability (or satis.ability) (CDC) and observability (ODC) don t care conditions.
Sentence 2: we address sets of don t care (DCs) conditions de.ned as follows: Observability DCs: These are lines where value assignments do not in.uence the outcome of the current SAT solver goal.
Relationship: entailment
Domain: Hardware
Sentence 1: Considering Figure6and assuming U(z)and Y(z)are the z-domain representations of u(k)and y(k)respectively, the value of u(k)at time k = k0 is the coef.cient of z -k0 in U(z).
Sentence 2: the values of u(k)for different ks are encoded as the coef.cients of z terms in U(z).
Relationship: entailment
Domain: Hardware
Sentence 1: Instead, the aging rate of the FF/PO data arrival time has to be considered as well.
Sentence 2: assuming the same aging rate for the FF/PO data arrival time in the optimized circuit, only di/dDfraction i of the available slack can be used for constraint optimization and the rest is assumed to be used due to the extension of the post-aging delay change.
Relationship: entailment
Domain: Hardware
Sentence 1: The cost of streaming through L words of data, for a given architecture containing W words per cache line, is calculated as Cf irst + (I(L/W )l - 1) * Cstream .
Sentence 2: we as­sume that after paying Cf irst to bring in the .rst cache line from main memory, the remaining data accesses cost Cstream due to enabled stream prefetching.
Relationship: entailment
Domain: Hardware
Sentence 1: Sincemanysmalldeviceshavenosecondarystorageand relyonmemorytoretaindata,therearepowercostsfor memoryeveninotherwiseidlesystems.Theamountof memoryavailableinmobiledevicesisexpandingwitheach newmodeltosupportmoredemandingapplications(e.g., multimedia)whilethedemandforlongerbatterylifealso continuestogrowsignifcantly.
Sentence 2: hardwarecomponents,suchasmemorychips,arebe­comingavailablethatoferpowermanagementfeatures.weconsiderpower-awareDRAMcthat hipssup­portseveraldiferentpowermodes:active,standby,nap andpowerdowninorderofdecreasingpowerconsumption butincreasingaccesstime.Ourgoalinthisworkistode­terminehowtoexploittheseemerginghardwarefeaturesfor themostefectivemainmemorypowermanagement.
Relationship: entailment
Domain: Hardware
Sentence 1: In terms of aggregate service, a super-round is equivalent to a round in the original algorithm or DRR.
Sentence 2: if sf (M) is the service of f during the m th super-round and crf (M) f s credit at the end of it, then sf (M) = wf + crf (M - 1) - crf (M).
Relationship: entailment
Domain: Hardware
Sentence 1: During the last years, many research activities have been attempting to de.ne .exible hardware architectures, that are suitable to perform the fundamental public-key cryptographic operations independent of the parameter val­ues (e.g., the value of the modulus used for modular arith­metic), the operand length, and even the speci.c class of mathematical operations to compute.
Sentence 2: a few proposals have been recently made [14, 15, 6, 13] to pro­vide uni.ed hardware architectures for executing both inte­ger modular arithmetic and GF (2M ) operations, thus cov­ering all the underlying arithmetics supporting RSA cryp­tography and EC cryptography.
Relationship: entailment
Domain: Hardware
Sentence 1: The task of detecting such faults is complicated due to the con­tinued increases in size and complexity of multi-core processors.
Sentence 2: multi-core processor architectures continue to evolve as they incorporate increasing number of cores and sockets, multi­ple layers of memory (for example, L1-L3), and complex proces­sor interconnects such as memory bus, hypertransport and others.
Relationship: entailment
Domain: Hardware
Sentence 1: HS3d approximates Flotherm with an R2 value of 0.87, while both Flotherm and HS3d show only a weak relationship to power dissipation (R2 < 0.17) and power density (R2 < 0.65).
Sentence 2: the units (IntMap, FPQ, LdStQ) which di.er the most from the Flotherm model are characterized as being downstream of the air.ow moving past the hottest part of the chip, the integer queue.
Relationship: entailment
Domain: Hardware
Sentence 1: This paper characterizes the sources of overhead in high-perfor- mance DRAM systems and investigates the most effective ways to reduce a system's exposure to performance loss.
Sentence 2: we look at mechanisms to increase a system's support for concurrent transactions, mechanisms to reduce request latency, and mecha- nisms to reduce the "system overhead"--the portion of the primary memory system's overhead that is not due to DRAM latency but rather to things like turnaround time, request queueing, inefficien-cies due to read~write request interleaving, etc.
Relationship: entailment
Domain: Hardware
Sentence 1: While the impact on a QoS-sensitive workload is dependent on the particular QoS metric, we ran SPECWeb4 [2], an industry standard web benchmark testing web server loads such as banking and eCommerce applications.
Sentence 2: this workload is signif­ 4we used the SpecWeb2005 eCommerce workload also found in SPECWeb2009 [3].
Relationship: entailment
Domain: Hardware
Sentence 1: The Control Unit manages the test execution; by receiving and decoding commands from the control signals, this module is able to manage the test execution and the upload of the results.
Sentence 2: it covers three tasks: x it receives from the data signals the number of patterns to be applied x it drives the test_enable signal that starts and stops the test execution and provides the information about the end of the test x it selects the result to be uploaded.
Relationship: entailment
Domain: Hardware
Sentence 1: In the case that the LUT is used for the smaller functions, each function can use m+1 distinct inputs, but must share (k-1)-(m+1) = k-m-2 inputs.
Sentence 2: for the 6,2 LUT used as two 5-LUTs, three inputs are distinct for each of the two 5-LUTs, and two inputs must be shared.
Relationship: entailment
Domain: Hardware
Sentence 1: For the signal on the middle line of three coupled lines, it is observed that with the increase of mutual inductance, the ratio (the gap) between the maximum and minimum delays decreases as shown in Figure 8.
Sentence 2: higher inductance leads to lower delay uncertainty and narrower switching windows, which is a positive effect of inductance, as narrower switching windows gives significant degrees of freedom in physical design to limit noise and control glitches.
Relationship: entailment
Domain: Hardware
Sentence 1: Equality of the simpli.ed programs is a suf.cient but not in general necessary condition for equality of the original programs, so the simpli.ca­tion process that is at the heart of fractal symbolic analysis should be applied sparingly.
Sentence 2: had our base symbolic analyzer been able to analyze only straight-line code, we would have con­cluded conservatively that the loop distribution of Figure 3(a,b) is not legal.
Relationship: entailment
Domain: Hardware
Sentence 1: With a buffer-aware interconnect timing model, new polynomial­time optimal algorithms are proposed for timing-driven cloning, including both .nding optimal sink partitions (identifying the fan­outs) for the original and the duplicated gates, as well as physi­cal locations for both gates.
Sentence 2: we present an O(m)­time optimal algorithm to minimize the worst slack if the original gate is movable, and an O(m log m) algorithm if the original gate is .xed, where m is the number of fan-outs.
Relationship: entailment
Domain: Hardware
Sentence 1: [1, Lv]: svi(v)=svi-1(v)+1  Let svbeg(v)=sv0(v)and svend (v)=svLv(v)  We create one or more scheduling variables for an operation node depending on its pipeline latency.1 The value of a schedul­ing variable essentially captures the relative temporal position (in terms of control state) of an operation node (or one pipeline stage of an operation node) in the .nal schedule.
Sentence 2: for instance, sbeg(v)=K indicates that, in the STG, the longest simple path (without consid­ering the loop-back transitions) from the initial state to the starting state of v has a length of K. when the input is a pure DFG, the scheduling variables directly correspond to the absolute node schedules in terms of control steps.
Relationship: entailment
Domain: Hardware
Sentence 1: Based on the previous observations, we also define DRVDS1 and DRVDS0 as the voltage levels applied to VDD_CC, in DS mode, such that the lower bound of SNMDS1 and SNMDS0, respectively, considering all core-cells in the array, is zero.
Sentence 2: dRVDS1 and DRVDS0 are the lower bounds of core-cell array supply voltage that still ensure retention of logic 1 and logic 0 , respectively, in all core-cells, when the SRAM is in DS mode.
Relationship: entailment
Domain: Hardware
Sentence 1: A path is called a dt -critical path if its delay is greater than the timing requirement minus dt.
Sentence 2: dt delay increment on a dt-critical path will cause the path s delay to exceed the  p F1 y q s t r dt-dominator: {g, h, i} dt-side input: w1 (l -> i), w2 (n -> h), w3 (j -> e), w4 (r -> f), w5 (p -> o), w6 (q -> d) Figure 3: The original circuit.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we propose a novel CAD solution to the path isolation problem, where the goal is to .lter the bins of can­didate paths and determine, by leveraging PSTA models, the true path that corresponds to the measured delay in every bin.
Sentence 2: we will use PSTA information about candidate paths to determine the most likely combination of true speed­paths P * = {P1,t1 ,...,Pn,tn },where Pi,ti .
Relationship: entailment
Domain: Hardware
Sentence 1: In this context, we study reversible circuits which are a subset of quantum circuits that map conventional 0-1 bit-strings into other such bit-strings.
Sentence 2: the largest module in Shor s number­factoring algorithm [13] modular exponentiation is implemented as a reversible circuit [7] (acting on entangled quantum states), exceeds all other modules asymptotically in size, and thus requires most attention of CAD tools.
Relationship: entailment
Domain: Hardware
Sentence 1: For a given target t, a set of mutually independent spawn points are selected among all blocks in the procedure with reaching probability to t greater than a threshold3,bycom­puting a heuristic value indicating their e.ectiveness as spawn points for the target.
Sentence 2: the merit of a given spawn-point s is computed as the product of the follow­ing factors: The .rst factor is the posteriori probability that the spawn precedes the target.
Relationship: entailment
Domain: Hardware
Sentence 1: As an example, the comparator could be designed in order to give to its output: i) (1, 0) or (0, 1), as Pass indication; ii) (0, 0) or (1, 1), as Fail indication and in the case of faults affecting itself.
Sentence 2: this latter condition should be guaranteed for all faults likely to affect the comparators of next generation microprocessors, that is all possible internal SAs, SOPs and BFs [22, 23].
Relationship: entailment
Domain: Hardware
Sentence 1: 5.3 Baselines 5.3.1 Conventional LPM The .rst baseline that we choose to compare with is the con­ventional LPM (CLPM ) that is currently prevalent in micro­controllers.
Sentence 2: the LPM4 mode of the MSP430G2­452 is chosen as CLPM , as it is the least power consuming data retention mode available.
Relationship: entailment
Domain: Hardware
Sentence 1: ACKNOWLEDGMENTS We acknowledge our colleagues in Motorola s DigitalDNA laboratories and in the Architectures and Systems Platforms group, who implement design tools and lithography process strategies and partner with us so that our algorithmic processes and their design standard lithographic and thin film processes work in concert.
Sentence 2: we wish to acknowledge the significant experience and learning that Clyde Browning, Bernie Roman, Kevin Lucas, Ed Travis, Tareq Bustami, and Alfred Reich have brought to us.
Relationship: entailment
Domain: Hardware
Sentence 1: Effect of Adaptivity: We observe that the expected traf.c for adaptive versions of the routing schemes have very similar distribution to the static version with similar or lesser corre­sponding values for the data points of interest.
Sentence 2: for RDC and RDG, the AI routing scheme reduces the maximum traf.c by 50% in comparison to its static counterpart, SI.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.1 Periodic Routing The .rst tool written to prototype the MDGRAPE-4 NoC was a fairly standard detail router that is unremarkable ex­cept for the fact that it supports a notion of periodic bound­ary.
Sentence 2: it allows the user to de.ne pairs of lines which limit the routing area, but which allows wires to pass through one line and emerge wrapped around from the other.
Relationship: entailment
Domain: Hardware
Sentence 1: The algorithm it- eratively builds and tests all regression models of the form: P = co + ciQ1 + c2Q2 + + cwQw ... where Qi denotes the i-th term (of order C) of the form: Qi -~ VlV2...~)G and vj is a candidate independent variable.
Sentence 2: the algorithm iterates on all regression models of up to T product terms of up to C variables each.
Relationship: entailment
Domain: Hardware
Sentence 1: Tracking Spatial Utilization: Spatial utilization is mea­sured by tracking the utilization of 64-byte sub-blocks allocated in sets that the block size predictor samples.
Sentence 2: it allocates a utilization bit vector (8 bits for a 512 byte block, one for each 64B sub-block) for each sampled way and sets a bit to true whenever the corresponding sub­block is accessed by the CPU.
Relationship: entailment
Domain: Hardware
Sentence 1: peak_current; By applying the 0-1 ILP solver, we have the results that S1,1 = 1, S1,2 = 0, S3,1 = 1, S3,2 = 0, S4,2 = 0, S4,3 = 1, S6,2 = 0 and S6,3 = 1.
Sentence 2: the peak current is 2*c under the multi-domain clock skew schedule in which TC1 = d1, TC2 = d2, TC3 = d1, TC4 = d3, TC5 = d2 and TC6 = d3.
Relationship: entailment
Domain: Hardware
Sentence 1: Results of Tables 1 and 2 show that less than 2% of channel-level co-directional nets are longer than 0.3 of FPGA dimension and less than 0.07% of the groups has contains more than 8 wire segment.
Sentence 2: in channel-level multiplexing, there are not considerably suitable groups for multiplexing.
Relationship: entailment
Domain: Hardware
Sentence 1: First, they are task-centric and/or code-centric whereas Flikker is data­centric.
Sentence 2: the techniques require programmers to identify regions of code where errors are allowed (code perfora­tion infers such regions automatically [16]), while Flikker requires programmers to identify data items where errors are allowed, i.e., non-critical data.
Relationship: entailment
Domain: Hardware
Sentence 1: With respect to this temporal relation­ship, multimedia applications are characterized by soft rather than hard real-time constraints and then they may tolerate a small percentage of missed deadlines.
Sentence 2: the behavior of multimedia applications is not necessarily characterized by a sin­gle hard real-time constraint, as is the case for safety critical appli­cations, but by a probability (or distribution of probabilities) which captures some variability in the performance metrics.
Relationship: entailment
Domain: Hardware
Sentence 1: Such characteriza­tion process is unavoidably expensive and accuracy of the resulting statistical variation models is strongly in.uenced by the limitation in test structures, test time and measure­ment accuracy as well as sources of variation that are di.­cult to monitor.
Sentence 2: characterizing within-die pro­cess variations and spatial correlations requires a signi.cant number of measurements and presents special challenges [8].
Relationship: entailment
Domain: Hardware
Sentence 1: This is a critical problem as both power and performance behavior of a design are signi.cantly in.uenced by the data communication (data access) distances between the processor cores and storage blocks.
Sentence 2: if a computation block (e.g., a processor core) frequently ac­cesses data from certain storage blocks, these storage blocks should be placed into positions close (in vertical or horizon­tal sense) to that processor core.
Relationship: entailment
Domain: Hardware
Sentence 1: The results demonstrate that for these cells propagated noise does not have such a relevant impact as for single-stage cells.
Sentence 2: for complex and multiple-stage cells, the error percent of linear superposition (obtained by modeling the cell with a linear resistor) with respect to ELDO simulations was always less than a few percents for all possible worst-case combinations of propagating glitches and switching aggressors.
Relationship: entailment
Domain: Hardware
Sentence 1: If we de.ne an RV ri as being a discrete 774 Proceedings of the International Conference on Computer Aided Design (ICCAD 03) 1092-3152/03 $ 17.00 &#38;#169; 2003 ACM Knowing that (s2 -s 2 )/Var( s2 ) is standard normal, this Vi Vi Vi condition reduces to: (v )(v ) (s2 -s 2 ) n (s2 -s 2 ) n 2,i Vi 1,i Vi F -F =a.
Sentence 2: (35) Ssi Ssi if s2 <s12 ,i,then a 1 -a con.dence level that node i is Vi safe is attained i. n satis.es (35).
Relationship: entailment
Domain: Hardware
Sentence 1: In this work, we chose to replicate data only at the time of write since read-only data are already available (in its unmodi.ed form) from the next level in the memory hierarchy.
Sentence 2: it is more important to provide higher reliability for cache lines that are dirty (since in a write back dL1 these are not .ushed to L2), while in the case an error occurs for a clean line, one could always go deeper in the memory hierarchy to bring the line [9].
Relationship: entailment
Domain: Hardware
Sentence 1: The concept of reliable blocks, i.e., management units, are proposed to not only enhance the reliability but also increase the block utilization and defer the erase time (so as to improve the read/write response time).
Sentence 2: we aim at the alleviation of program disturb inside each block (referred to as intra-block program disturb)to have more reliable blocks for better reliability and even performance.
Relationship: entailment
Domain: Hardware
Sentence 1: However, for convenience, we will continue to use them as parameters when proving the lower bound.
Sentence 2: we choose the following values for the parameters (for simplicity assume that these values are all integers): k = l = n~log S n and e=d=~ 1 (lo-~n) k Recall that M = 2 cl°g'~, so due to Claim 4.2, the prob- ability that f outputs 0 on a negative test input is at least: 1-,~"c log n e-~ = 2½n½1og] he- ½,~ log] ,-,= -k'1 for large enough n, it is more than any constant probability (we take 3 as our constant).
Relationship: entailment
Domain: Hardware
Sentence 1: (i, j)e(Y-[x,y])((dPxy -dP = CCy *(ty ij) *CCi *ctij)+ ij ((i, j)=[x,y])((dPxy -dPx ij ) *CCi *ctij ) -Eqn (B) ij dij depends only on whether vertices vi and v j are in the same partition, or in different partitions.
Sentence 2: dPij xy = dP ij if (i, j)= [x,y].
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we adopt the Impor­tance Sampling (IS) based information theory inspired Minimum Cross Entropy method, to propose a general technique to quickly evaluate the failure probability of SRAM cells.
Sentence 2: we .rst mathematically formulate the failure of SRAM cells such that the concept of Cross Entropy Distance can be leveraged, and the distance between the ideal distribution for IS and the practical distribution for IS (which is used for generating samples), is well-de.ned.
Relationship: entailment
Domain: Hardware
Sentence 1: Supposethatthe trajectoryof agivenMT takesitthrough an overlay at a point where the overlay has width w. Assuming that the overlay consists of a single tracking area, then the distance that the MT will travel before deregistering will be of the form kvT, for k an integer.
Sentence 2: deregistration will occur at the smallest value of k such that kvT > w, namely k = .w/vT.
Relationship: entailment
Domain: Hardware
Sentence 1: EXPERIMENTAL RESULTS This section describes a comprehensive characterization of the clock load of the ASIC-like control logic designs in the POWER4 core.
Sentence 2: this section presents the total wire load, total device load, Clock Uplift Factor, and the portion of the wire load on each of the four available metal wiring layers for individual ASIC-like control logic designs, the six functional units, and the core itself.
Relationship: entailment
Domain: Hardware
Sentence 1: When Ds[4]=0 and Dt[4]=0, let Addr[8]=0, Addr[7:4]= Ds[4:0], Addr[3:0]=Dt[4:0], there are 256 entries in this address range, and the yellow partition will be stored in it;  When Ds[4]=0 and Dt[4]=1, let Addr[8:6]=3 b100, Addr[5:4] = Dt[1:0], Addr[3:0]=Ds[4:0], there are 64 entries in this address range, and the pink partition will be stored in this area;  When Ds[4]=1 and Dt[4]=0, we can swap Ds and Dt, so the second pink partition will be stored in the same address range.
Sentence 2: because the two pink partitions are symmetric, we only store one of them to the RAM block.
Relationship: entailment