sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: resultoftheoptimalellanddeapplaementforhip2is showninFig.8.Weobservethatthisplaementisonsis­tentwiththehotspotsofthehip,i.e.,largerdeapsare alloatedlosertothetwosidesofthehip.Afteroptimiza­tion,thevoltagedroopintheVddplaneisintherangeof 00.196Vandthatofthegroundplaneisintherangeof 00.191V.Theoptimizationproesshasjudiiouslybal­anedthepowergridvoltagedrooponthewholehip.
Sentence 2: thenoiseredutiontrendwithrespettotheellou­panyratioriforhip2isshowngraphiallyinFig.9.This experimentisperformedbyremovingsomeellsfromeah rowofthehiptoahievethedesiredoupanyratio.For eahase,around10perentofthetotalgridnodesarebe­yondthenoisemargin.Ahipwithloweroupanyratios providesmoreemptyspaefordeouplingapaitorsand onsequentlyiseasiertooptimize.inFig.9,the noiseredutionismoreeÆientforaseswithlowerou­panyratiosthanforthosewithhigherones.
Relationship: reasoning
Domain: Hardware
Sentence 1: These branches are insensitive to the previously mentioned 100% 100% 98% 96% 96%  Branch Prediction Hit Rate 94% 92% 90% 94% 92% 90% 88% 88% 86% 86%  Connecting Data Transfering Clossing Connecting Data Transfering Clossing Flow Live (N-th Pkt) Flow Live (N-th Pkt) (a) Branch Prediction -Tra.c without (b) Branch Prediction -Tra.c with aggregation level high aggregation level Figure 5: Branch prediction study through packet .ow life tra.c properties (see Section 4).
Sentence 2: they are easy to predict, since the prediction is similar among packets.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since dynamic compensation is 1 1 0.8 0.6 0.4 0.2 0 employed, high leakage, low-Vtp, PMOS access devices are not needed for standby stability.
Sentence 2: neighboring cell write upset can be alleviated by employing high-Vtp PMOS and low-Vtn NMOS devices (Figure 11b,c).
Relationship: reasoning
Domain: Hardware
Sentence 1: Table 1: Notations used in the derivation u Width of the placement area v Length of the placement area L Distance (tiles) between two placement area W Capacity of channels (long wire) S Total number of interconnections to be routed .l Length of the l-th interconnection Xi,j Length of the i-th interconnection at channel j Yj Number of interconnections at channel j R Average length of all interconnections N Total number of channels available D Distance between the placement and the long wire channel has available long wires.
Sentence 2: it is important for the stochastic model to be able to capture the fringing e.ect.
Relationship: reasoning
Domain: Hardware
Sentence 1: For the device parameters of 0.25µm CMOS process, the energyconsumption of an SERC is about 7.3 times and that of carry generator is about 2.1 times compared to that of a buffer at the optimal condition of Vdd=2.4V and f=651kHz.
Sentence 2: we broke the logic reversibility with an SERC if we could reduce more than 8 buffers.
Relationship: reasoning
Domain: Hardware
Sentence 1: We show that nanowire crossbars do not scale well in implementing logic and it is more important to have fast­er nanowire FETs with high channel resistance and low capacitance than fabricating larger arrays of crossbars.
Sentence 2: we propose a Crossbar Cell design based on small nanowire crossbars that can be fabricated with exist­ing nanoimprinting and lithography methods.
Relationship: reasoning
Domain: Hardware
Sentence 1: 1 2A d12 A (a) 1 A1 d13 3 (b) 2 A2 d23 A3 where A is the nominal arrival time.
Sentence 2: the arrival time at the output node of a path has a simple representation that faithfully captures the sensitivity of the path to the parameters, given by the bi terms in (4).
Relationship: reasoning
Domain: Hardware
Sentence 1: However, scheme II is only slightly behind scheme I for the same delay constraint, but from a process standpoint, scheme I is more costly than scheme II.
Sentence 2: it is the preferred scheme, as it is Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 05) 1530-1591/05 $ 20.00 IEEE not only economically feasible but also achieves close to optimal leakage.
Relationship: reasoning
Domain: Hardware
Sentence 1: Clearly, we turn off the TG after the charge sharing is complete.
Sentence 2: we can calculate the dynamic energy consumption of the TG for one complete active-sleep cycle as follows: 1 22 4 × (2C V = 4C V (12) Etg-total =× 2 tg ) DD tg DD to calculate the actual energy saving ratio (ESR), we need to subtract the correction ratio Etg-total/Etotal from the ideal ESR in (9).
Relationship: reasoning
Domain: Hardware
Sentence 1: As discussed in Appendix D, if a PDC has i elements, its possible moving o.set can be determined in O(i log n) time after O(n log n)­time preprocessing.
Sentence 2: the re.nement takes O(n 2 log2 n) time in the worst case and O(n log2 n) time for practical ap­plications.
Relationship: reasoning
Domain: Hardware
Sentence 1: 5C-4 Network Flow-based Simultaneous Retiming and Slack Budgeting for Low Power Design Bei Yu*, Sheqin Dong*, Yuchun Ma*, Tao Lin*,YuWang*,Song Chen and Satoshi Goto *TNList, Department of Computer Science &#38; Technology, Tsinghua University, Beijing, China Graduate School of IPS, Waseda University,Kitakyushu,Japan Abstract Low power design has become one of the most signi.cant requirements when CMOS technology entered the nanometer era.
Sentence 2: timing budget is often performed to slow down as many components as possible so that timing slacks can be applied to reduce the power consumption while maintaining the performance of the whole design.
Relationship: reasoning
Domain: Hardware
Sentence 1: Under the power consumption constraint, it is desirable to achieve gain with input and output impedance match, while maintaining the minimum noise and distortion level, also minimizing the silicon area.
Sentence 2: when formulating the GP problem, we minimize area subject to the following constraints:  Noise match (F = Fmax )  Input impedance match (S11 = Smax )  Gain requirement (G = Gmin)  Output impedance match (S22 = Smax )  Nonlinear distortion requirement (I = Imin)  11 22 Power constraint (P = Pmax ) Where F is the noise .gure, S11 is the input re.ection coe.­cient, Gis the gain, S22 is the output re.ection coe.cient, I is the third-order intercept point (IIP3) and P is the power consumption.
Relationship: reasoning
Domain: Hardware
Sentence 1: Let Eidenote the set of nets at level i.For i a net eijEEi , eijcan be represented as a set of the modules {mkleijhas a i pin connecting to mk}.
Sentence 2: the estimated wirelengh wjiof a net ejiEEiis de.ned by ; ;;;; j#(((xp+wp/2) (x+w /2))2  ;p ; ; j m1 m 3 m2 0 <_ x1 0 <_x2 x1+w1<_ x3 x2+w2<_ x3 mc +w<_ x3 3x t (a) v 0 <_ y t 2 <_ y 0 v1 3 A2 v1 y2+ <_y w2 1 vs v t A v3 y+ 1<_y 1 w1 tv3 v2 y+ A1<_ y v2 1w1 t vs Ghc Gv c (c) (b) Figure 5: (a) A cluster module mwith the cluster scheme {{ml, m2}, m3}.
Relationship: reasoning
Domain: Hardware
Sentence 1: Following the layout rule specified by the library, metal layer 4 requires a minimum width of 0.1 um and a spacing of 0.1 um.
Sentence 2: the total width of the reg­ister columns is 262.4 um and 380.8 um, which is less than the square-root of the area of a 4-entry integer and a 2-entry FP CRIB, which are 105732 um2 and 192600 um2.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then, fon )with0 <l = n de.nes ll the ON-set (don t care set)for thel-th output of f. We now include in the QBF formulation that the speci­.cation is meet if the l-th output of f for a given minterm is don t care.
Sentence 2: we rewrite the QBF formula from aboveasa conjunctionof n one-output functions, where the don tcare outputs always evaluate to true, i.e.
Relationship: reasoning
Domain: Hardware
Sentence 1: Leakage current characteristics of previously published sleep switch dual-Vt domino logic circuit 30 The Igate produced by a low-Vt NMOS transistor is 47 u and techniques in the literature are discussed in Sections B and C. u higher than the Igate produced by a low-Vt PMOS transistor at 110 ºC and 25 ºC, respectively, as listed in Table I gb V DD cg I bg I su b  are not critical for the performance of a domino logic circuit.
Sentence 2: i dg I  those transistors that are active during the 0 gs V DD 0 0  (a) (b) precharge phase have a high-Vt [10].
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, the reliability of the organism is given by the fact that, at any moment, at least Nc-Sc columns are operational: Nc Nc i i Nc -i ROrg ()t = .
Sentence 2: ci RColumn (1 - RColumn ) (20) iNc -Sc = Since a column is fully operational if all Mc component cells are functional, the reliability function for a column results as: c R ()t = RM ( ) t (21) Column Cell the final expression for the reliability function of an organism (or of any given cellular structure) is given by equation (22): N c cc cc N iM M N -i ROrg ()t = .
Relationship: reasoning
Domain: Hardware
Sentence 1: However, due to the very nature of the aging inducing phenomena we believe that a more appropriate, but also more complex approach should be a full probabilistic model: the age could be regarded not only as a function of the instantaneous value at time t of a degradation parameter X, for example, but also of its history (from t=0 to the time moment t at which we want to compute the age): A= A(t, x1,x2, ..., xn), where x1,x2, ..., xn are stochastic processes which enter in the expression of A by their particular realizations.
Sentence 2: a is also a stochastic process whose char­acteristics (e.g., probabilities, moments) have to be obtained from the properties of x1,x2, ..., xn.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, unfortunately, at the high voltage level, the delay of the smallest clock buffer CKBX1 is 0.05 ns, which is only slightly larger than that of clock buffer CKBX4.
Sentence 2: even if we use the smallest clock buffer CKB1 to implement the buffer chains, the total number of clock buffers in these two PMABs still achieves 410 (i.e., 181+182+47 = 410), which still will result in tremendous overhead on power consumption.1 Table 1: Clock latencies in circuit ex (before PMABs are inserted).
Relationship: reasoning
Domain: Hardware
Sentence 1: Routability-Driven Placement for Hierarchical Mixed-Size Circuit Designs * Meng-Kai Hsu1, Yi-Fang Chen1, Chau-Chin Huang1, Tung-Chieh Chen3, and Yao-Wen Chang1,2 1Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan 2Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan 3Synopsys Inc., Hsinchu, Taiwan {kaie, yifang, wlkb83}@eda.ee.ntu.edu.tw, donnie.chen@synopsys.com, ywchang@cc.ee.ntu.edu.tw ABSTRACT A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements.
Sentence 2: it is desirable to develop an e.ective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time.
Relationship: reasoning
Domain: Hardware
Sentence 1: Table 5: Fault-tolerant placement results Total sensitivity Crit_Delay(s) Arch T-VPlace F-T-VPlace T-VPlace F-T-VPlace 4x4 672.45 535.44 (-20%) 4.34E-08 4.24E-08 4x10 633.47 441.02 (-30%) 3.81E-08 3.86E-08 6x4 466.15 336.94 (-28%) 3.62E-08 3.68E-08 6x10 431.02 272.74 (-37%) 3.39E-08 3.32E-08 Table 6: Simultaneous power and fault tolerance optimization in placement (compared with T-VPlace) P-T-VPlace F-T-VPlace Arch Power MTTF Power MTTF Reduction Increase Reduction Increase 4x4 18% 13% 18% 26% 4x10 28% 27% 26% 44% 6x4 25% 14% 20% 38% 6x10 31% 46% 32% 58% 4.2 Morphing P-T-VPlace for Fault Tolerance To reduce the fault rate of the circuit, we have to place the highly­sensitive nets which connects between the clusters as close as possi­ble to minimize the total sensitivity along the global interconnect.2 Essentially, this is the same intuition behind the power-aware place­ment.
Sentence 2: our fault-tolerant placement, namely F-T-VPlace, takes the same cost function as P-T-VPlace and replaces the switch­ingactivityterm, f (i), with the sensitivity of a net.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that a register is allocated when vi D is executed on vi R until DR R  vj is executed on vj at all resources representing same PE as vi represents.
Sentence 2: the weight of arcs from all uk representing those resources to vi R must be increased by R. At T (vj D), a register is to be released at vj R until a new data is produced by vi D at the next iteration of the loop.
Relationship: reasoning
Domain: Hardware
Sentence 1: The message length distribution function must be a descending function, so that ()is positive.
Sentence 2: blocking time of a G Y message at hop i of flow F is the average of waiting time in equivalent queue with weight (): G Y BF* ()=.8 G( )×Wi F*(+ p, s) (8) is YY Y =0 where WF * (Y +P, s) is the LST of the mean waiting time in i equivalent queue with size Y +P messages.
Relationship: reasoning
Domain: Hardware
Sentence 1: We note  -8 x 10 1.8 1.6 1.4 1.2 1 0.8 0.6 Quality --> (b)Scaling vsQuality Figure1: Scalable-e.ortprocessorforSVMs[16], andquality vs energy trade-o.s of the scaling mechanisms the fact that even among resilient applications, the degree of resilience varies greatly depending on the application and data.
Sentence 2: as shown in this paper, statically setting thescaling mechanismsisinadequate.
Relationship: reasoning
Domain: Hardware
Sentence 1: These instructions are used to load/store the data in memory, to manipulate the program counter (PC) to make sure the computation to be carried out in a correct sequence.
Sentence 2: we can divide the total number of instruction per iteration into two parts, shown in Instriterat Equation (7), Instriterat = Instrsppt + Instroperat (7) where Instroperat is the number of instructions that carry out the calculation directly, and Instrsppt is the number of support instructions.
Relationship: reasoning
Domain: Hardware
Sentence 1: Similarly, all of the outgoing arcs of v must enters some vertex w where R(v) is left-adjacent to R(w) (we can view R(v0) as an empty region right-adjacent to the right-most region).
Sentence 2: if v is in the path, no other vertices vwhere R(v) = R(v.) can be in the path, for otherwise there will be a path from v to the predecessor of v., but the arcs are only from a region left adjacent to another region.
Relationship: reasoning
Domain: Hardware
Sentence 1: For a network load of 0.9, at N = 4, the improve­ment in throughput as compared to N = 2, is 27% where as at N = 8 as compared to N = 4, the improvement in throughput is almost 47%.
Sentence 2: allocating more links is advantageous for complement tra.c as all nodes use the same link for communication.
Relationship: reasoning
Domain: Hardware
Sentence 1: Sensi­tivity analysis is based on the assumption that the statistical circuit response to variations in process parameters (f ) is approximately by a linear superposition of input sensitivities, n with f = s + P i=1 [sV ti · .Vti + sßi · .ßi/ßi].
Sentence 2: if the variation parameters follow a Normal distribution (inherent assumption in SA), the output will also follow a Normal distribution with mean and variance given by: j µ s P n (15) s2 i=1 (sV tisV ti)2 +(sßisßi)2  Figure 3: Histogram showing the distribution of DFFQ Clock to Q Delay comparing the response computed using MC against S-DoE.
Relationship: reasoning
Domain: Hardware
Sentence 1: Maximum sensitiv­ity is achieved when the input vector V has high probability H(V)=0.67 when falling transitions fail .rst, or H(V)=0.33 when rising transitions fail .rst.
Sentence 2: the output TP of the failed path in terms of V is given by the probability of the two sequences occurring: TPfall failed =2 × P(V =1) × P(V =0) × P(V =0) =2 × P(V =1) × (1 - P(V =1))2 =2H(V)(1 - H(V))2 (7) In the same way, when the rising transitions fail, a transition is only detected when V is 0 .
Relationship: reasoning
Domain: Hardware
Sentence 1: Inthefrstase,weneeda0to1transitionintheFFbitto justifytheFFvalueanda1to0transitionisneededinthe seondase.Therefore,thedistaneistarget­state­related.
Sentence 2: wedefnethestatedistaneweightaordingtothetarget state'svalue: Defnition3.DistaneweightforithFFinthestateisS F=(1- F)*n. where FistheontrollabilityofF.Ifthetarget statevalueinthisbitis0,thenitisthe0ontrollabilityof thisFF.Iftargetstatevalueinthisbitis1,thenitisthe1 ontrollability.nisthetotalnumberofFFs.The0and 1ontrollabilityusedherearetheprobabilistibasedmea­surementinsteadofSCOAPsothattheirvaluearealways between0.0and1.0.Inpratie,weusethefrequenyof eahFFswithingto0and1duringsimulationasits0and 1ontrollability.theeasiertheFFistoontrol 0or1,theloseitsorrespondingswithingfrequenyvalue isto1.0,andfromdefnition3,thesmalltheweightforthis FF.nserveshereastheupperboundfortheweight.The worseaseisthataFFisneverswithedto0/1,thenitsor­responding Fis0,thenitsweightisthemaxweight n.BasedontheweightdefnedforeahFF,theover­allweightedHammingdistanebetweenstateAandtarget stateBisomputedusingthefollowingformula: n .
Relationship: reasoning
Domain: Hardware
Sentence 1: TableIshowstherelationshipbetweenthegrain sizeandtheimplementedcircuitsperformanceincase ofPROTEUS­Lite.Thecircuitsthathavecoarse­grain hardmacrocanworkfasterthantheothersandthus satisfyourrequirements.
Sentence 2: figure8illustrateshowwecanusethevirtualparts withthesoftware.Eachvirtualpartcommunicates throughtheMPUinterfacecircuitwiththesoftware runningontheMPUcard.Allinterfaceregistersin theMPUinterfacecircuitsaremappedontoMPU­accessiblememoryaddresses.Thedevicedrivergen­eratorgeneratesaheaderfle(Clanguage),which includesinterfaceregisteraddressdefnitionsasstatic valuesforeachvirtualpart.Duringprogramdevelop­ment,aprogrammercanusenicknames,defnedinthe headerfle,insteadoftherawaddresses.Thebasead­dressofeachcircuitintheheaderfleusestheaddress mapofeachmodule,whichpreventsaddressconges­tion.thedesignercanbefreedfromtheaddress managementwork.
Relationship: reasoning
Domain: Hardware
Sentence 1: When T S is high however, M4 and M5 are both off, which leads to the connection between the gates of M8 and M9 being sev­ered; M6 and M7 are both turned on pulling the gates of M8 and M9 to GN D and VDD, respectively.
Sentence 2: in this mode both M8 and M9 are off, leaving the output tri-stated.
Relationship: reasoning
Domain: Hardware
Sentence 1: Additionally, our main ideas and our performance guaran­teeing methods are also useful for other performance-related tradeo.s, such as performance-reliability tradeo.. For ex­ample, the selective reliability management scheme [16] in­duces performance slowdowns while replicating instructions to detect hardware errors.
Sentence 2: our method dynami­cally tracking slowdowns and guaranteeing performance can de.nitely bene.t such schemes to achieve a balance between performance and target functionalities.
Relationship: reasoning
Domain: Hardware
Sentence 1: (31) shows how to compute E[IT Ii], the other term can be com­puted similarly.
Sentence 2: 2M hX ` X ´i E[IT Ii] = E Io,j Io,i exp - (ßjk + ßik).k j.N k=1 2M« X Xß2 ik + 2ßjk ßik jk + ß2 = Io,j Io,i exp(31) 2 j.N k=1 the gradient of the second moment can be computed only in O(nM) time.
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, the main challenge now is to capture the information (starting and ending addresses) of n runs of 1s in just k intervals where n » k. Merging adjacent intervals due to the upper bound on k, will capture some non-updated cache lines into the intervals, which leads to overheads.
Sentence 2: the intervals with the smallest runs of non-updated cache lines between them should be merged.
Relationship: reasoning
Domain: Hardware
Sentence 1: Consequently, compressing EEG The average uncertainty after determining the E class labels signals, up to a ratio of approximately 10, increases DK L (X||X ) is given by the conditional entropy: minimally (i.e., by 0.20 bits) and rapidly beyond this.
Sentence 2: d the information content of the compressed-domain features I P(C) I S (X|C)= -P(xk|C) logP(xk|C), (12) is maintained up to a large compression ratio.
Relationship: reasoning
Domain: Hardware
Sentence 1: Directly after a secure erase, which ensures that every block of a SSD is empty, the random write performance was 19,816 IOPS, af­ter the drive has been .lled with data sequentially, it was 1,338 IOPS, and after the capacity of the drive has been written using random writes, performance of random writes was 587 IOPS.
Sentence 2: in normal operation, it will vary be­tween 587 and 1,338 IOPS.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, it is known to this community that CLR might not be a good metric (to approximate the e.ects of process variation) since a circuit will not operate at di.erent voltages at the same time.
Sentence 2: we shall focus on the optimization of clock skew and just treat the CLR optimization as a side e.ect of the skew minimization, same as the work [16].
Relationship: reasoning
Domain: Hardware
Sentence 1: Further, as smart devices fall in the realm of embedded computing the processors must be designed with a short turn around time.
Sentence 2: chip designers have adopted a heterogeneous System-on-Chip architecture for these processors where each sub-system (application, graph­ics/media, communication, peripheral) is designed with an Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: reasoning
Domain: Hardware
Sentence 1: Another rea­son not to increase the number of die in the stack beyond a certain point is to avoid potential thermal problems.
Sentence 2: for this FPGA makeup a 3D stack of four die would achieve silicon area savings of 26% (from 0.71 cm2 to 0.52 cm2) compared to the planar de­sign, together with an improved performance of 61% (from 11.8ns to 4.6ns) as measured by the average interconnection delay.
Relationship: reasoning
Domain: Hardware
Sentence 1: Similarly, the best individuals obtained from Lo­cal competition of individuals in a subset of the population form the Local Pareto Front and are termed Locally Supe­rior solutions.
Sentence 2: in a GA, the cross-over operation has a better chance of producing more Globally Superior solu­tions when operating on two Globally Superior solutions, than when operating on two Globally Inferior solutions or a Globally Superior solution with a Globally Inferior solu­tion.
Relationship: reasoning
Domain: Hardware
Sentence 1: Ef.cient MemoryManagement of a Hierarchical and a Hybrid Main Memoryfor MN-MATE* Platform Kyu Ho Park, Sung Kyu Park, Hyunchul Seok, Woomin Hwang, Dong-Jae Shin, Jong Hun Choi, and Ki-Woong Park Computer Engineering Research Laboratory, KAIST kpark@ee.kaist.ac.kr, {skpark, hcseok, wmhwang, djshin, jhchoi, woongbak}@core.kaist.ac.kr ABSTRACT The advent of manycore in computing architecture causes se­vere energy consumption and memory wall problem.
Sentence 2: emerging technologies such as on-chip memory and non­volatile memory (NVRAM) have led to a paradigm shift in computing architecture era.
Relationship: reasoning
Domain: Hardware
Sentence 1: In hmmer, the out-of-order microarchitecture is able extract sub­stantial instruction level parallelism due to the low percent­age of dependent instructions (Figure 8).
Sentence 2: even with the lower recurrence of BDIs, time borrowing suffers substantial performance loss in hmmer, as an instruction replay has large overhead in hmmer than in lower IPC mcf or xalancbmk.
Relationship: reasoning
Domain: Hardware
Sentence 1: Being Xr and Gr the sets of prioritized documents in the system output and gold standard respectively, the correct relationships in the system output are priority relationships between relevant documents in Xr and irrelevant documents in ¬Xr.
Sentence 2: r corresponds with: R(X) = AvgdP (rg(d, d ' )|rx(d, d ' )) = P (Gr|Xr)P (Xr)P (¬Gr|¬Xr) + P (¬Gr|¬Xr)P (¬Xr)P (Gr|Xr) = P (¬Gr|¬Xr)P (Gr|Xr)(P (Xr) + P (¬Xr)) = P (¬Gr|¬Xr)P (Gr|Xr) This corresponds with the product of precisions over pos­itive and negative sets in the output.
Relationship: reasoning