sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: 2.2 Memristor-based Memory Attractive properties of the memristor such as non-volatility, high distinguishability, low-power, scalability and fast ac­cessing speed make it a promising candidate for the next­generation high-density and high performance memory tech­nology [8][10].
Sentence 2: memristor-based memory struc­ture has been studied recently [8].
Relationship: reasoning
Domain: Hardware
Sentence 1: Second, the instructions executed per second depend on the operating frequency (as seen in Eq(7)) and therefore the utilization of a core changes with the frequency.
Sentence 2: the power consumption of a processing core as a function of operating frequency, P(F), can be written as: peak peak P(F)= P · fd(F)· uI(F) + P · fs(F) (8) dyn sta The equation above consists of three components: (1) Ppeak and dyn Ppeak sta are the peak dynamic and static power consumption of each core from the design speci.cations; (2) fd(F)and fs(F)encapsu­late the impact of voltage and frequency scaling on the peak dy­namic and static power consumption, assuming the the processor utilization remains constant; (3) uI(F) encapsulates the change in processor utilization as a result of frequency scaling.
Relationship: reasoning
Domain: Hardware
Sentence 1: By assuming the gate delay follows Gaussian Distribution,the delay distribution of a path also follows Gaus­sian Distribution, which can be represented as (µ,s), where µ is the mean value of the path delay and s is the standard deviation of the path delay.
Sentence 2: the probability for the delay of path i to exceed clock period T is: T - µi Di = 1 - F( ) .
Relationship: reasoning
Domain: Hardware
Sentence 1: Hence, in order to improve RaT e.ciency, we would like to stop execut­ing the runahead thread when it .nishes generating useful prefetch requests, that is, there is no more MLP to be ex­ploited.
Sentence 2: we want to determine the useful lifetime of a runahead thread to expose as much MLP as possible with the minimum number of speculative instructions.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3) SROA Generation: The tapping point set Sopt generated from tapping point set generation may not be quali.ed to form an SROA due to a potential lack of integrity.
Sentence 2: the object of SROA Generation is to substitute a portion of the rings in the tapping point set Sopt with the other rings in S in order to satisfy the SROA construction rules with a minimum total distance increase.
Relationship: reasoning
Domain: Hardware
Sentence 1: The gate leakages are inherently unique at each IC post-fabrication due to PV.
Sentence 2: for the input .j , the total measured leakage (Imeas(.j )) can be written as: leak K Imeas k ..j leak (.j )+ E(.j )= Ileak(qjk) (1) k=1 where E(.j ) is the measurement error for the input .j , qjk is the input at the gate Gk after applying .j to the primary inputs, and Ileakk (qjk) is the leakage of gate Gk with qjk as its inputs.
Relationship: reasoning
Domain: Hardware
Sentence 1: Because of the reg­ularity of FPGAs, the input slew rate for the same type of circuit elements is very close.
Sentence 2: the chip short circuit power can be further simpli.ed as: X Psc = f · SW · SCi(Sli) (14) i.T where Sli is the input slew rate of type i circuit element, which is computed as the output slew rate of the element driving type i element.
Relationship: reasoning
Domain: Hardware
Sentence 1: We de.ne the literal set L as L ={li} ={x¯1,x1,x¯2,x2,...,x¯n,xn,},i=1,2,...,2n Accordingly, the cofactor set F is de.ned as F ={fi} ={fx¯1 ,fx1 ,fx¯2 ,fx2 ,...,fx¯n ,fxn ,},i=1,2,...,2n Shannon Expansion can be implemented by simply using aMUX with xi as the select bit and the positive and negativecofactors connected to the positive and negative MUX inputs,respectively.
Sentence 2: the three-input PLE shown in Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: For values of 8pi with high probability, fs(x, p) can be inferred from (11), in which cks = log dks , qi = log pi, ui = 8pi/pi, and yj = log xj .
Sentence 2: fs(x, p) 1 can be reformulated as a log-sum-exp constraint where Opi  np np lse As 0 + uj As j y, bs 0 + uj bsj 0 (12) j=1 j=1 with appropriate Aj s and bj s, j = 0, 1, .
Relationship: reasoning
Domain: Hardware
Sentence 1: {p2, p3} Duplicated states perform the same operations as the orig­inal states, so concatenation to conditional blocks does not modify the functionality.
Sentence 2: a functionally equiv­alent FSMD (referred to as recomposed FSMD) can be ob­tained from the original FSMD by performing concatena­tion to each conditional block that are undergoes specula­tive code motion during HLS.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since each basis has its distinct structure matrices J0,the related potential coe.cient matrix P0 = J0T HJ0 has di.er­ent densities.
Sentence 2: it s desirable that one can choose a since the charge on panel 4 is the sum of charges on panels 6 and 7, upper level panels now only need to gather the charge on panel 4 and do not need the charge on panel 6.
Relationship: reasoning
Domain: Hardware
Sentence 1: Although ourrankingisrootedinthefundamentalphysics of the situation, early implementations of time-sync proto­cols in sensor networks elevated the signi.cance of the sec­ond source well above the third.
Sentence 2: much of the early work on time synchronization, speci.cally for sensor networks, focused on the design of protocols and regression mechanisms to cope with the noisy time stamps that their implementations achieved.
Relationship: reasoning
Domain: Hardware
Sentence 1: Constant current driving When using the current source as a constant drive, the domain wall velocity can be obtained by dV (t) - (r - r ) · v = (8) H L I · dt Here, the current I is constant, and hence, the domain wall velocity v is fixed.
Sentence 2: the voltage cross the memristor decreases linearly, providing a nice linearity curve for temperature detection.
Relationship: reasoning
Domain: Hardware
Sentence 1: The notation Si is used to denote the projection onto i-th element in a tuple.
Sentence 2: s1(s) = f1 and S2(s) = f2 for a state s. i Definition: Run (r) A run r RUNS is defined as r: N o STATES, a mapping that associates a sequence of clock ticks represented as integers with a sequence of states.
Relationship: reasoning
Domain: Hardware
Sentence 1: The second condition of the if statement (E ' (t)=E ' (t +p))is always true when p is a multiple of the LCM of all delays of the original circuit (M).
Sentence 2: p is a multiple of the oscillation period if E(t)=E(t+ p)where p> 0, t = t0, and (p%M =0).
Relationship: reasoning
Domain: Hardware
Sentence 1: However, as de­scribedin the followingsubsections, we alsoconsider observabil­ity don t cares (ODCs).As a consequence,the simulation values in the fanout ofthe target net might change aftera replacement.
Sentence 2: after each restructuring operation,wemark the simula­tion vectors in the transitive fanout ofatarget netas tainted .
Relationship: reasoning
Domain: Hardware
Sentence 1: The CAUTION++ architecture should allow putting in place correctly the identi.ed RRM techniques, hopefully despite the occurrence of faults.
Sentence 2: the design of the CAUTION++ architecture necessitates validation and ver­i.cation activities to be performed as soon as possible from the very early phases of the design process, in order to justi­.ably trust the identi.ed solutions and to make appropriate choices among several possible alternatives.
Relationship: reasoning
Domain: Hardware
Sentence 1: Each operator is either a .rst order operator or a composition using higher order op­erators.
Sentence 2: in the following, vectors are written as x =(xi)0=i<n = (x0,...,xn), and operators An are functions on these vectors of length n. y = Anx indicates that an operator An is applied to an input vector x, generating an output vector y.
Relationship: reasoning
Domain: Hardware
Sentence 1: The analysis above showsthatDishighlysensitivetothe change in .H.
Sentence 2: in other words, minimizing .H isagood surrogateformin­imizing D. our routingobjectiveisto minimize the .H after routing.nishes.Wedothisbytryingtoleave .H unchanged, or minimizingtheincreaseinits value, when routing each net, and bytryingto reduce.H when ripping up a netintheEPDpostpro­cessing stage.
Relationship: reasoning
Domain: Hardware
Sentence 1: To avoid a rapid growth in the number of vertices in the projection polygon, COHO performs a simpli.cation step where the projection polygon is replaces by an enclosing poly­gon of smaller degree.
Sentence 2: every vertex but one in a cluster will be discarded by the simpli.cation process, but the projection algorithm expended a signi.cant amount of compu­tation time to determine these vertices.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since the iterations are incremental, instances having incorrect VTH selection are not swapped back to a higher VTH once another upstream or downstream instance is found that proves to be a better VTH selection.
Sentence 2: taking prorated weights at the beginning of the selection process not only reduces the leakage power of the entire design but also reduces the number of iterations that would be required to achieve timing closure.
Relationship: reasoning
Domain: Hardware
Sentence 1: The two different values will suit different needs of gates G2 and G3: Gate G2 can choose value 1 to optimize NBTI degradation, and gate G3 can also choose value 0 for better leakage reduction.
Sentence 2: our proposed technique has higher flexibility with regard to connecting the fan-out gates before or after the transmission gate to achieve better leakage reduction.
Relationship: reasoning
Domain: Hardware
Sentence 1: Nevertheless, it is based on macroblock level pipeline and can not seamlessly fit into our design, since 4x4 level pipeline requires calculation of each 4x4 block in double-z order instead of directly computing a 16x16 block as a whole.
Sentence 2: we propose a two-level seed scheme to pre-calculate a main seed and store seven calculated pixels of certain locations as second-level seeds.
Relationship: reasoning
Domain: Hardware
Sentence 1: In other words, the change of gm, gmbs, and gds from Reg#i to Reg#j is fixed.
Sentence 2: in the case that a small amount of MOSFETs change operating regions, we could update the L and U matrices directly with the rank-one update technique [12][13], rather than updating the MNA matrix and performing costly LU factorization again.
Relationship: reasoning
Domain: Hardware
Sentence 1: In short, manual ab­straction can be computationally expensive, time-consuming and of varying .delity.
Sentence 2: it is very desirable to be able to abstract macromod­els directly and automatically from full SPICE-level circuits with- Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: reasoning
Domain: Hardware
Sentence 1: (3) When considering only conduction losses, VOU T needs to be as close to VOU T,N L as possible for a given VIN for a converter to be ef.cient.
Sentence 2: as discussed above, it is not possible for VOU T to equal VOU T ,N L. when considering both conduction loss and parasitic switching loss [9], it should be as optimally close to VOU T ,N L as possible.
Relationship: reasoning
Domain: Hardware
Sentence 1: If the delay at Tnom of these paths is below the con­straint Dnom, thenitwill also be metat Twc (since they are all-HVT, and their delay will decrease with  increasing temperatures); If not, revert to the original path by restoring the SVT cells as in the initial circuit; The resulting circuit will never have a timing violation at Twc (and, of course, neither at Tnom by construction).
Sentence 2: the circuit is temperature-insensitive.
Relationship: reasoning
Domain: Hardware
Sentence 1: CLEVER: Cross-Layer Error Veri.cation, Evaluation and Reporting Rafael Kioji Vivas Maeda School of Electrical Engineering Federal University of Minas Gerais, MG, Brazil rafaelkioji@gmail.com ABSTRACT The continuously progressing technology scaling is not only the source for increasing performance and complexity of em­bedded systems, but also the reason for rising reliability con­cerns of the underlying hardware.
Sentence 2: numerous techniques emerged in recent years to mitigate wide range of error causes.
Relationship: reasoning
Domain: Hardware
Sentence 1: ).m 2 - ..m.m-1; k = m; (5) where .k is the change of the binary voltage of the kth line: i .k = v f - v and Cl isthetotal capacitancebetween alineand the ground, RT is the total resistance of the driver and the line.
Sentence 2: the delay of the kth line can only take the values 0, 1, 1+ .,1+2.,1+3.,and 1+4., that we categorize them in to six delay classes, D00, D0,D1, D2,D3,and D4.
Relationship: reasoning
Domain: Hardware
Sentence 1: Depending on the comparison outcome, (1) the Most Signi.cant Bit (MSB) of data is retrieved, and (2) the circuit .xes next resistance reference to extract the Least Signi.cant Bit (LSB).
Sentence 2: mLC read latency is real­ized in a sequence of one sense followed by two comparisons which is longer than a SLC read comprising of one sense and one comparison.
Relationship: reasoning
Domain: Hardware
Sentence 1: If variable a is assigned to register R2, the smallest feasible clock period becomes 12 and the total possible clock arrival time width becomes 26 (since Wb, Wg, W1, W2, and W3 become 10, 8, 0, 0, and 8, respectively); if variable a is assigned to register R3, the smallest feasible clock period becomes 12 and the total possible clock arrival time width becomes 2 (since Wb, Wg, W1, W2, and W3 become 2, 0, 0, 0, and 0, respectively).
Sentence 2: variable a is assigned to register R2.
Relationship: reasoning
Domain: Hardware
Sentence 1: To reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, reprogrammed outside of the ORGA package us­ing a holographic memory writer, and implemented onto the ORGA package with high precision beyond the capabilities of manual as­sembly [14],[15].
Sentence 2: to remove that daunting problem, this paper presents a nine-context programmable ORGA and its writer.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, as a word of caution, large scale control system de­signs are often not to resilient by design and may become prey to such stealth attacks if suf.cient resilience is not built by design in the .rst place.
Sentence 2: our ideas become all the more relevant for op­erational security until there is a principled way of designing fully attack resilient control structures and algorithms (which by itself is a very challenging research endeavor and may not offer a cost effective design solution).
Relationship: reasoning
Domain: Hardware
Sentence 1: The delays of other peripheral circuitries, including decoder, sense amplifier and data bus, are insensitive to the data address in RAM.
Sentence 2: sAVS may not be applicable to fetch, register read, D-cache and writeback stages since the delays of those RAM-based stages (30 FO4 for Fetch (I-Cache) and D-Cache, 24 FO4 for register read and writeback) are close to the clock period (36 FO4).
Relationship: reasoning
Domain: Hardware
Sentence 1: Post-hoc tests (Bonferroni correction) revealed that the AV incongruent condition was signi.cantly different from each in­dividual congruent condition at the p < 0.001 level.
Sentence 2: these IA VO (deg) (mm) 0 0.5 0.75 1 0 100 100 96.9 93.8 6 93.8 87.5 93.8 90.6 12 93.8 100 100 90.6 18 100 100 93.8 100 24 87.5 96.9 96.9 96.9 Table 4: Percentage of expected-fusion responses to incongruent stimuli /ga/ba/.
Relationship: reasoning
Domain: Hardware
Sentence 1: The .L columns show that after cell replacement, the average number of extra metal layer needed for Style-B-circuits can be reduced from 1.25 to 0.42; for the initial Style-C-circuits from 1.08 to 0.25.
Sentence 2: applying only Style-B or Style-C cells on critical paths could significantly improve the metal layer availability without worsening the circuit timing.
Relationship: reasoning
Domain: Hardware
Sentence 1: Unfortunately, many embedded memories cannot achieve low VDDmin because of read or write failure.
Sentence 2: memories have become one of the bottlenecks to reducing the VDDmin of 2D-1 1 2 3 WL 1 Selected Cell 1 Write Operation Write half-selected disturb Cell Sigma 0 PUL PURPUL PUR Q0Q0 Normal_25C 1QB1QBPGL PGLPGR PGR PDL PDR PDL PDR -1 Normal_85C -2 Normal_125C BL BLB BL BLB 1 011 -3 0 50 100 150 200 250 300 350 400 Read Operation  Read half-selectedSelected Cell disturb Cell Standby Current (uA) WL 11 Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: Unlike test points, the structure of the logic impli­cation hardware may allow for the detection of errors without any a priori knowledge of the patterns applied and without having to de­termine what the internal circuit values should be for a given input combination or sequence.
Sentence 2: these same logic implications can also be used in functional testing without requiring gate-level simu­lation of the functional test sequence or storage of expected internal values.
Relationship: reasoning
Domain: Hardware
Sentence 1: Their very slow ramp times increase energy consumption considerably, as a consequence of the large cross-over currents drained in the sequential cells.
Sentence 2: in order to improve e.ciency compared to conventional clocking, latch circuits have to re­strict the cross-over current dissipation overhead below the Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies arenot made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: reasoning
Domain: Hardware
Sentence 1: (j)) e v are respectively de.ned as follows: .e(i)=2de(i)/ce(i) - 1, (1) .v(j)=2dv(j)/cv(j) - 1, (2) where ce(i) is the capacity of ei, cv(j) is the capacity of vj , de(i) is the demand of ei, which is the number of segments that have routed on ei,and dv(j) is the demand of vj , which is the number of line ends that have lain on vj .
Sentence 2: the routing cost of a global routing path is the summation of the vertex costs and the edge costs in the path.
Relationship: reasoning
Domain: Hardware
Sentence 1: Decoder 8×256 7×128 6×64 5×32 4×16 Composition 3D-3R 3D-3R 2D-3R 3D-2R 2D-2R Time (ns) 0.58 0.46 0.38 0.34 0.30 BC decoder PD NPD PD NPD PD NPD PD NPD PD NPD 6×32 5×32 6×16 4×16 6×8 3×8 6×4 2×4 6×2 1×2 Composition CAM 3D-2R CAM 2D-2R CAM NAND3 CAM NAND2 CAM INV Time(ns) 0.49 0.56 0.31 0.43 0.22 0.36 0.17 0.32 0.13 0.28  Baseline Tag Dec No Mem cell Tag Mem 20bit x 512 Data Dec No Mem cell Data Mem 256bitx512 Total size 141312 B-Cache 64×6x8 CAM 17bitx512 32×6x16 CAM 256bitx512 147456 we can see that all of the decoders have time slack left.
Sentence 2: the B-Cache would not have any time access overhead compared with a conventional direct-mapped cache.
Relationship: reasoning
Domain: Hardware
Sentence 1: 2 (20) 2 **** We have proposed the hybrid inter-sector CoMP transmis­ rB1H2 -rB2H1rB1H1 +rH2 B2 |H1|2+|H2|2  s1 - s2 - + = |H1|2+|H2|2  sion B to e.ectively reduce the decoding complexity at cell­edge user.
Sentence 2: through numerical and simulation studies, it was the ML detection of scheme B can be reduced to symbol-wise decoding (single-symbol decoding) and the de­tector only has to calculate 2M.
Relationship: reasoning
Domain: Hardware
Sentence 1: Hence, only one of the shifts, ..1, ..2,or .., is greater than zero.
Sentence 2: any A-operation that realizes an addition can be in the form of .. +2..2 .. or (.. + ..)2-.., where in the former, only one of the left shifts and the right shift are zero and in the latter, both of the left shifts are zero.
Relationship: reasoning
Domain: Hardware
Sentence 1: INTRODUCTION Underpresentassumptionsonthecomputingenvironments, processorsareexpensiveandmemoryisrelativelycheap.
Sentence 2: animportantproblemistoutilizeprocessorsef­fciently.Forgeneral-purposeapplications,theutilizationof processorsinparallelcomputersisnotasefcientasthatin single-processorcomputers,sothatthelatterachievebetter performanceperdollar.Infuturecomputingenvironments, however,therolesareexpectedtobereversed,sothatthe majorityofchipareaisusedformemory.the optimizationproblemmaythenbecometheefciencyinuti­lizingtherelativelyexpensivememory.Recentresearchon processorsinmemory(PIM),computinginRAM,andsmart memoryparadigms[9,14,18]showsthatmultipleprocessors perchip,integratedwithmemorybanks,canincreasethe memory-processorbandwidthconsiderably,leadingtoim­provedmemoryutilization.Also,withtherapidadvancesin  Dept.
Relationship: reasoning
Domain: Hardware
Sentence 1: As can be seen, independently from the application, the key differentiator used to identify the worst benchmarks from the reliability viewpoint is the analysis of which ones make in­tensive use of a reduced number of registers, namely, FFT and bitcount.
Sentence 2: they are the benchmarks that experience the most severe MTTF reduction (i.e., 35% in 10 years following the normalized pattern of Figure 4) due to the hotspots found in the highly-accessed registers.
Relationship: reasoning
Domain: Hardware
Sentence 1: For most of the test cases, the number of single vias that have at least one feasible redundant via each is about 54%~75% of the number of the edges of EI .
Sentence 2: using the double-cut constraints instead of the con.ict constraints corresponding to the edges of EI , the number of constraints of our 0-1 ILP (= #A-Vias) can be reduced signi.cantly.
Relationship: reasoning
Domain: Hardware
Sentence 1: The victim driver holding resistance is supposed to be constant, but this assumption introduces a highly inaccurate approximation, since not only this resistance is not constant, but also it becomes negative during noise propagation.
Sentence 2: it is quite possible that the noise at the victim driver input induces a negligible propagated noise glitch at the output, while at the same time it may significantly increase the holding resistance, thus resulting in a much larger total noise when injected noise is present (the driver weakening effect).
Relationship: reasoning
Domain: Hardware
Sentence 1: Another Figure 2: Item Composition Schemes used for Protocol Speci.­ cation in SystemCSV disadvantage that is common to all formalisms for communication protocol speci.cation presented so far is that in order to synthe­size a transaction producer/consumer pair, the protocol must be de­scribed from two different views: the transaction producer view and the transaction consumer view.
Sentence 2: for the same proto­col two different speci.cations have to be developed which results in a decrease in design ef.ciency and increases veri.cation effort.
Relationship: reasoning
Domain: Hardware
Sentence 1: In addition to monitoring the data associated with events, an event-accurate checker also needs to perform bookkeeping of the internal contents of the microarchitectural block, and thus an embedded logic implementation would be grossly inef.cient.
Sentence 2: for functionality checking, the data associated with events should be recorded and transferred off-platform for post­simulation analysis in software, where the validity of the recorded sequence of events is checked.
Relationship: reasoning
Domain: Hardware
Sentence 1: But a GP proces­sor has the .exibility to execute any future standard changes or extension, which might not be implementable in an RPE, due to its more application speci.c design -for example coarse-grained architectures which implement only a speci.c operational set inside each ALU which .ts the dedicated ap­plication area.
Sentence 2: in order to provide a better life-cycle, additional GP processor cores can be included into the de­sign.
Relationship: reasoning