sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: At every step to increase a clique size, when a nodes is selected, the sum of the weights of outgoing arcs from the selected node to all nodes in clique is checked to be less than NR.
Sentence 2: step 2: Assign weights to arcs of compatibility graph: The weight of an arc (directed edge) denotes the number of registers required from the time the source node (a mapping) is executed to the time the destination node is executed.
Relationship: neutral
Domain: Hardware
Sentence 1: Max-flow Output Assignment Formulation Our technique for evaluated the MSD metric without SAT is as follows: We perform a binary search on potential MSD values to determine the minimum MSD.
Sentence 2: 5.1 Cardinality Constraints we can safely preassign a second node to either the same One way to assert cardinality constraints in our SAT instances is via a partition as the first or another arbitrary partition.
Relationship: neutral
Domain: Hardware
Sentence 1: Categories and Subject Descriptors: B.m [Hardware, Miscellaneous]; B.7.m Integrated Circuits, Miscellaneous General Terms: Design Keywords: FPGA, Nanotechnology Copyright is held by the author/owner(s).
Sentence 2: the panel seeks to answer the following questions: 1) Do atomically-engineered materials and fabrication techniques offer new capabilities that are sufficiently compelling to encourage the necessary investment and learning?
Relationship: neutral
Domain: Hardware
Sentence 1: However, due to conflicts in the cache, capacity limitations and low visibility into the actions on the lower level caches, these properties cannot be held using the typical LRU policy in the last­level cache.
Sentence 2: to statically separate the set into two subsets of different sizes, we logically map the first X lines to priority level 2 and the next N-X lines to priority level 1.
Relationship: neutral
Domain: Hardware
Sentence 1: To optimize the power-bandwidth product of the amplifier, while still profiting from the averaging property, the minimum possible interpolation factor of 2 is chosen at the output of each gain stage.
Sentence 2: [8] Xicheng Jiang, Zhengyu Wang, M. Frank Chang, A 2GS/s 6b ADC in 0.18µm CMOS , IEEE International Solid-State Circuits Conference, Vol.
Relationship: neutral
Domain: Hardware
Sentence 1: on Computers, 30(5): 305-312, May 1981.
Sentence 2: to ensure the probability after ad­justment is still between 0 and 1, we use the following equation to calculate Proute: Wroute 1 (8) Proute = Pedge + ( N - ) × k R .Wroute (Ri ) NR i=1 where NR is the total number of edges in G and Ri is the route represented by the edge i in G. k is an adjustment coefficient cho­sen to amplify the differences between the probabilities of routes with different weights and is selected such that all values for each Proute are between 0 and 1.
Relationship: neutral
Domain: Hardware
Sentence 1: Suppose that, among many functional paths, paths p1, p2, and p3 stand out as three critical reliability paths at di.erent time points, e.g., path p1 has the largest delay from time 0 up to time t1, path p2 has the largest delay during [t1, t2], and path p3 becomes the most critical after time t2.
Sentence 2: we design RCRPs in a way that, by measuring RCRPs delay using on-chip structures such as [10, 11, 17], estimation on the largest delay can always closely track that of the critical reliability paths.
Relationship: neutral
Domain: Hardware
Sentence 1: To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.
Sentence 2: reconfiguration at the cellular level [13] the added flexibility could not be protected by employing the same self-repairing mechanism used in case of the logic mode; a strategy based on redundant coding was chosen in order to ensure the integrity of storage data [10].
Relationship: neutral
Domain: Hardware
Sentence 1: A processor using per-core DVFS can deliver considerably higher performance/power efficiency than a processor using chip-wide DVFS when it exhibits small core­to-core (C2C) voltage variations (Section 2).
Sentence 2: in active state, a PCPG device incurs a slight voltage drop across it (i.e., between the supply voltage and the actual voltage applied to the core).
Relationship: neutral
Domain: Hardware
Sentence 1: -ae, is the clock skew between s. and e. Assume s,e sthat for a timing run at another corner cj, s. was also found to be the startpoint of the path causing the worst-case slack at e. As a result, the slack for e at corner cj is written as: j jjj s= k.+ d.- t(7) hold s,e s,e hold In this case, the change in hold slack .ij ,where sj = si + hold hold .ij , can be written as follows: j - kij - di ij .ij = k..+ d..+ t- t(8) s,e s,e s,e s,e hold hold Knowing the exact value of .ij would require performing an STA run at cj .
Sentence 2: table 1 shows our test circuits and their respective sizes.
Relationship: neutral
Domain: Hardware
Sentence 1: For the applications with large work­load variability, the operating voltage and frequency can be further controlled dynamically around these static values.
Sentence 2: the VFI partitioning problem is formu­lated as follows: Given An NoC architecture;  The scheduling of the driver application across the network;  Maximum number of allowed VFIs;   Figure 3 Different voltage-frequency island partitionings and corresponding static voltage assignments for a 2×2 network.
Relationship: neutral
Domain: Hardware
Sentence 1: In this paper, we adopt the standard definition of arrival time and transition time that is commonly used in STA and ATPG tools, meaning that the arrival time of a signal transition is set to the time instance at which signal waveform crosses the 0.5Vdd voltage level whereas the transition time of a signal transition is defined as the slope of a line connecting two specific points on the noisy input: the points are when the signal waveform crosses the 0.1Vdd and 0.9Vdd voltage levels.
Sentence 2: p2 shows that in order to significantly reduce the slowdown from its worst-case level, the input skew will have to be changed by a rather large amount.
Relationship: neutral
Domain: Hardware
Sentence 1: A.1 Fixed-Symbol-Length Schemes As discussed in the previous section, there could be X-bits left after merging the compatible codewords by Alternate Fill [17], which can be .lled without affecting the entropy of the entire test vector.
Sentence 2: iEEE Transactions on Computer-Aided Design, 22(6):783 796, June 2003.
Relationship: neutral
Domain: Hardware
Sentence 1: In our approach, not only the energy harvester model but also the optimisa­tion algorithm is implemented in a single VHDL-AMS test­bench.
Sentence 2: the energy harvester has a large storing capacitor of 0.22F and even for one chromosome, simulating the voltage across it with time step of 0.1ms for 100 seconds takes almost 10 min­utes.
Relationship: neutral
Domain: Hardware
Sentence 1: (19) h By substituting F(Zk) with (17), one can obtain VT CV VT CV Zk-1 ( + VT GV )Zk = - V T f(xj ) h h (20) + VT GV zj - V T Bu.
Sentence 2: it can conveniently provide predicted boundary of multiple trajectories under uncertain interval parameters by one-time computation, in contrast to simulate different trajectories one by one.
Relationship: neutral
Domain: Hardware
Sentence 1: Complete and practical methods have been proposed to check multi-cycle paths [12].
Sentence 2: an Efficient Algorithm to Verify Generalized False Paths Olivier Coudert OC Consulting Auf der Höh 16a 83607 Holzkirchen, Germany Skype: ocoudert Twitter: @ocoudert olivier_coudert@ocoudert.com ABSTRACT Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures.
Relationship: neutral
Domain: Hardware
Sentence 1: While timing can vary by unacceptably large amounts, a second important factor is the leakage power (which is becoming a major fraction of the total power): its exponential dependence on process parameters can lead to large swings in the power dissipation from die to die after manufacturing.
Sentence 2: finally, hybridization of CNT and Cu interconnects will be discussed as a very attractive alter­native for deep nanometer scale VLSI technologies.
Relationship: neutral
Domain: Hardware
Sentence 1: In this work, results are presented for multiple dominance margin values, where for setup analysis the largest dominance margin allowed is 30ps, and in the case of hold analysis it is 10ps.
Sentence 2: although crosstalk analysis can have a signi.cant e.ect on datapath delays, this is not very likely to happen for a partial corner without also happening for the anchor corner.
Relationship: neutral
Domain: Hardware
Sentence 1: The .rst ldr and the subsequent str instructions in Figure 2 illustrate two accesses of this type, where the stack offset value of -44 from the frame pointer (fp) .ts in the 12-bit immediate .eld of the load/store instructions in ARM.
Sentence 2: it is important to emphasize that this approach is our speculation we have not found this approach being suggested in the literature, which is not surprising considering its drawbacks listed above.
Relationship: neutral
Domain: Hardware
Sentence 1: (6) to show how the con.ict miss probability falls as a function of the sparsity factor, c for a particular number of hash functions, k. 3.5 dMHC Area Model In order to achieve near-associativity, dMHC could require high values of the k and c parameters.
Sentence 2: active messages: a mechanism for integrated communication and computation.
Relationship: neutral
Domain: Hardware
Sentence 1: 2 There are 5 voltage-frequency pairs available to be selected, i.e., (0.8V, 10MHz), (0.9V, 20MHz), (1.0V, 30MHz), (1.1V, 40MHz), (1.2V, 50MHz).
Sentence 2: we have: i=1 N le mem out .fo =(A.fo + A.fo i,j j a) · z· S(9) N-1 j=i 3) Power constraints: The total power consumption of the system can be calculated by Equation (10), which consists of the power of all PEs and asynchronous FIFOs.
Relationship: neutral
Domain: Hardware
Sentence 1: However the optimal working point computed for the entire chain can in some cases lead to a reduced profit for some of the actors, who can be tempted to adopt a dysfunctional behavior, carrying out the attacks described in Section 2.
Sentence 2: as confirmed by the experimental results, lowering the probability of an attack could not produce an effective modification of the risk profile of an actor (and vice versa).
Relationship: neutral
Domain: Hardware
Sentence 1: [39] A. Svizhenko and M. P. Anantram, Effect of Scattering and Contacts on Current and Electrostatics in Carbon Nanotubes, Physical Review B, Vol.
Sentence 2: the high resistance associated with an isolated CNT (greater than 6.45 K.) [11] necessitates the use of a bundle (rope) of CNTs conducting current in parallel to form an interconnection [4, 15].
Relationship: neutral
Domain: Hardware
Sentence 1: Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization Paul Zuber *, Armin Windschiegl§,Ra ´ul Medina Beltr ´an de Ot ´alora , Walter Stechele , et Andreas Herkersdorf Lehrstuhl f ¨ur Integrierte Systeme, TU M ¨unchen, *Email: Paul.Zuber@tum.de §IBM Deutschland Entwicklung, B ¨oblingen Abstract This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance.
Sentence 2: we can exploit the remaining space after routing, especially grid-based routing, such that highly active wire segments become more isolated than segments with low switching activities.
Relationship: neutral
Domain: Hardware
Sentence 1: First and foremost, the number of memory references re­quired for a page walk is effectively independent of all architec­tural parameters except for the MMU and the L2 cache organiza­tion.
Sentence 2: with the page table cache, the three top entries hit in the private page table cache, and only one entry (the L1 entry) requires a memory access, which may or may not hit in the L2 data cache.
Relationship: neutral
Domain: Hardware
Sentence 1: In current FPGA tools, the user must select the exact target device of the tool before synthesizing any design.
Sentence 2: [2] H. Hamann, A. Weger, J. Lacey, Z. Hu, and P. Bose, Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements, IEEE Journal of Solid-State Circuits, vol.
Relationship: neutral
Domain: Hardware
Sentence 1: Micro-scale ET effects involve length/time scale of 10nm-10Pm/0.1ns-10Ps, while macro-scale issues involve much larger length/time scales.
Sentence 2: in order to comprehend the impact of cooling on thermal gradients and hot­spots, a self-consistent electrothermal methodology for estimating substrate temperature profile has been developed (Fig.
Relationship: neutral
Domain: Hardware
Sentence 1: Great Lake Symposium on VLSI, 2006.
Sentence 2: for example, the output signal ar­rival time t0 of an interconnect is given by the summation of the input signal arrival time t1 and the delay d of the in­terconnect.1 t0 = t1 + d cdf(t0 = t)= pdf(t1 = t1)pdf(d = t2)dt1dt2 t1+t2=t .
Relationship: neutral
Domain: Hardware
Sentence 1: of MOBICOM 2002, Atlanta, GA, USA, September 2002.
Sentence 2: we can observe that for LH =3the LE is compara­ble for all values of M. as the value of LH increases, the LE decreases more rapidly for higher number of antenna sectors, due to the fact that the overlapping region becomes smaller when the antenna sectors become narrower.
Relationship: neutral
Domain: Hardware
Sentence 1: Here, there are two things we would like to point out.
Sentence 2: therefore, the linear program is formed by combining Equa­tion (1)-(3) and Equation (5)-(7) and the following objective: L Minimize xi (8) i.P the setup constraints limit the delays that can be inserted, it is likely that the allowed inserted delays cannot satisfy the hold-time constraints which makes that the above linear program not feasible.
Relationship: neutral
Domain: Hardware
Sentence 1: This method is used extensively on package level analysis.
Sentence 2: what to do with the other discrete die shadow pins was an open question and we tried two cases: (I) attach all the die capacitance under the 2mm X 2mm die model or (II) distribute it evenly in the 9x9 die shadow, with 2x2 of the sections placed under the attached die model, and the rest directly attached to the package/die interface pins (see Figure 6).
Relationship: neutral
Domain: Hardware
Sentence 1: We recommend that you print the file for best legibility.
Sentence 2: eIPC 5 4 3 2 1 0 thepreviousscalarregion.Thesameoverlappingsituation happenswiththeinitialscalarinstructionsofthescalarre­gionthatfollowseachvectorregion.Wehavemeasuredthis overlapforeachprogramanditneverexceeds4%ofthe totaloperationsexecuted.
Relationship: neutral
Domain: Hardware
Sentence 1: If we examine the coverage model closely, we see that it consists of two parts: (1) a basic event that speci.es that a command is sent and few cycles later a response is sent back; (2) pa­rameters that are attached to the basic event, such as the type of command and the type of response.
Sentence 2: since LTL expressions refer to the in.nite future, they cannot always be evaluated during simulation that takes a .nite time.
Relationship: neutral
Domain: Hardware
Sentence 1: [11] de­scribed a high-level interconnect power model for wires of a single core chip.
Sentence 2: compared to inter-tile wires,  8 AF = 1% AF = 0.1% 10 100 100 0 5 10 15 20 10 relative power 6 10 90 90 80 80 4 70 10 70 number of wires relative power 60 60 2 50 50 10 40 40 30 0 30 10 20 20 0 1 2 3 4 5 101010101010 wire length (gate pitch) 10 10 00 Figure 3: Wire distribution of our base chip.
Relationship: neutral
Domain: Hardware
Sentence 1: After excitation by a photon, an electron in the valence band of the nanocrystal is transferred to the conduction band, while the hole in the valence band may transfer to the hole-conducting MEH-PPV and the electron can either remain in the nanocrystal or move through the nanocrystal network by hopping or tunneling.
Sentence 2: large-area, solution-processed photovoltaic devices fabricated from materials other than crystalline silicon are of keen interest to the energy community.
Relationship: neutral
Domain: Hardware
Sentence 1: For example, the delay of the PMOS increases and that of the NMOS decreases under the effects of STI stress, therefore the total delay appears only a little variation.
Sentence 2: then the mobility under the influence of STI stress can be obtained as follows: 3/2 3/2 3/2 f f(m )/ (mm )    (9) STI 0 eff hh hl where f0 is the original mobility without considering the effects of the STI stress.
Relationship: neutral
Domain: Hardware
Sentence 1: Using NAND Flash Memory for Executing Large Volume Real-Time Programs in Automotive Embedded Systems  Kwangyoon Cho School of Computer Science and Engineering Seoul National University Seoul, Korea ez1@snu.ac.kr Kyoung-Soo We School of Computer Science and Engineering Seoul National University Seoul, Korea we123456@snu.ac.kr Chang-Gun Lee School of Computer Science and Engineering Seoul National University Seoul, Korea cglee@snu.ac.kr Kanghee Kim School of Electronic Engineering Soongsil University Seoul, Korea khkim@ssu.ac.kr ABSTRACT For advanced features of next generation vehicles, the real­time programs in automotive embedded systems are dra­matically increasing.
Sentence 2: optimally combining pinning/LRU really helps reducing the WCET for the given RAM size.
Relationship: neutral
Domain: Hardware
Sentence 1: Off-path Leakage Power Aware Routing for SRAM-based FPGAs Keheng Huang1,2,YuHu1, and Xiaowei Li1 Bo Liu3,4, Hongjin Liu3,4, Jian Gong3,4 1.State Key Laboratory of Computer Architecture, 3.Beijing Institute of Control Engineering, Institute of Computing Technology, Chinese Academy of Sciences 4.Science and Technology on Space Intelligent 2.Graduate University of Chinese Academy of Sciences {huangkeheng, huyu, lxw}@ict.ac.cn Abstract As the feature size and threshold voltage reduce, leakage power dissipation becomes an important concern in SRAM-based FPGAs.
Sentence 2: we conducted experiments on twenty MCNC benchmark circuits to estimate the logic state probability of each wire by .... .. tool [14], and collected the probability skew for each circuit.
Relationship: neutral
Domain: Hardware
Sentence 1: The probabil­ity that a route l of wire k will insert a bu.er at grid (x, y), b insert(x, y, l, k) should be calculated in order to estimate the amount of bu.er usage b usage(x, y).
Sentence 2: in order to compute the congestion infor- Assume that both the upper and the lower The routes bound of the buffer insertion constraint are 2 for wire k : Buffer location The number of feasible routes for wire k passing The probability of wire k through each grid passing through each grid The probability of a route with successful buffer insertions a: 1.0 b: 0.5 c: 0.5 d: 0.5 e: 0.5 f : 1.0 4/4 2/4 1/4 2/4 2/4 2/4 1/4 2/4 4/4 Probability of successful buffer insertion Figure 2: Our Congestion Model mation using this model, we need estimates of b usage(x, y) and b success(x, y) ateachgrid(x, y).
Relationship: neutral
Domain: Hardware
Sentence 1: (page_alloc_req &#38;&#38; page_alloc_rsp &#38;&#38; page_alloc_pgnum==magic_page) ) ); /* * If in LCNT1 state and there is a dealloc of the magic page, * then we should see a freeing of the magic page */  assert_page_free_valid: assert property( @(posedge Clk) disable iff (!Rst_)( (trkState==LCNT1 &#38;&#38; page_dealloc_req &#38;&#38; page_dealloc_rsp &#38;&#38; page_dealloc_pgnum==magic_page) |-> (page_free_req &#38;&#38; page_free_pgnum==magic_page ) ); /* * If in !
Sentence 2: during the first 8 byte data chunk within a packet, in_sop will be asserted, and during the last 8 byte chunk, in_eop will be asserted.
Relationship: neutral
Domain: Hardware
Sentence 1: Although,inDDR3DRAM,arow corresponds to8KB across arank,we assumeaminimumin­DRAMcopygranularity(Section4.3.2)of4KB sameasthepage sizeusedbytheoperatingsystem(DebianLinux)inourevalua­tions.
Sentence 2: inthefollowingsection, wedescribethesecondmodeofRowClone thePipelinedSerial Mode(PSM).Althoughnotasfastorenergy-efficientasFPM,PSM addressesthesetwolimitationsofFPM.
Relationship: neutral
Domain: Hardware
Sentence 1: k-SMT The k-th moment Steiner minimum tree (k-SMT), de.ned [18] in [18], is shown to be be a trade-off between SMT and MRSA because 0-SMT is SMT and 8-SMT is MRSA.
Sentence 2: (3) We design an incremental detailed routing sub.ow to validate the bene.t of timing-driven Steiner topologies, using commercial tools, libraries and design examples.
Relationship: neutral
Domain: Hardware
Sentence 1: A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories C.Zambelli * , M.Indaco , M.Fabiano , S.Di Carlo , P.Prinetto , P.Olivo * and D.Bertozzi * * University of Ferrara, Engineering Department, 44122, Ferrara -ITALY Politecnico di Torino, Department of Computer and Control Engineering, Torino -ITALY Abstract In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to im­prove the uncorrected/miscorrected bit error rate (UBER) and to provide a more .exible usage model where the performance-reliability trade-off point can be adjusted at runtime.
Sentence 2: [14] P. Cappelletti, C. Golla, P. Olivo and E. Zanoni, Flash Memories , Kluwer, 1999.
Relationship: neutral
Domain: Hardware
Sentence 1: In many processors, caches occupy about 50% of the chip area [1].
Sentence 2: p V P-3V C0 0.255 0.0217 0.190 C1 0.312 0.0235 0.242 C2 0.287 0.0224 0.220 C3 0.318 0.0187 0.262 C4 0.269 0.0175 0.217 C5 0.293 0.0165 0.244 C6 0.245 0.0143 0.202 C7 0.276 0.0268 0.196 C. Hybrid Cell Assignment To design a hybrid-cell SRAM, we need to find out the slowest read and write delay starting with all low-Vt SRAM cells (C0 case.)
Relationship: neutral
Domain: Hardware
Sentence 1: Some of these challenges such as dealing with computational complexity can be partially addressed by advances in computational engines such as Binary Decision Dia­grams (BDDs) [9], Boolean satis.ability (SAT) [29], and satis.a­bility modulo theories (SMT) solvers [5].
Sentence 2: journal of Computer and System Sciences, 50:20 31, 1995.
Relationship: neutral
Domain: Hardware
Sentence 1: 1e-010 1e-012 1e-014 1e-016 1e-018 Nadh 1e-020 After the optimization, we perform the E-dominance analy­ sis to search accurately near the edge of the Pareto-optimal region.
Sentence 2: the second solu­tion provides NADH = 6.07 · 10-6 nmol/mg and ATP = -3734.6 nmol/mg (consumption), over-pro ducing the fol­lowing metabolites: H+ mtx , ISOCmtx , SUCmtx and ATPims , whereas CITmtx , MALims and AMPims , PYRims , GLUims,cyt and aKGims are totally consumed.
Relationship: neutral
Domain: Hardware
Sentence 1: .f(·) .F, f(·) can be maximized and minimized e.ciently  and assume that all timing quantities are represented using delay models that are in F. For example, timing quantity A is modeled as follows: A = fA (X1, ···,Xp)= fA(X) .F (2) where X =[X1, ···,Xp] represent process/environmental param­eters.
Sentence 2: in fact, if [A, B] .F1,then C = aA + bB + c also .F1.
Relationship: neutral
Domain: Hardware
Sentence 1: Below we report these seeds alto­gether with the corresponding outcomes produced by the set of equations after assigning (column-wise) all seed values to the proper variables: s1 = 1 0 0 1 1 0 0 0 0 0 s2 = 0 0 1 0 1 1 0 0 0 0 s3 = 1 1 0 0 0 0 1 0 0 0 s4 = 1 0 1 1 1 0 0 1 0 0 s5 = 1 1 0 0 1 0 0 0 1 0 s6 = 1 1 1 1 0 0 0 0 0 1 x1 x2 x5 x9 x10 = 0 1 0 0 0 1 x1 x3 x4 x6 x8 = 00 1 0 1 1 x2 x6 x7 x10 = 0 1 0 0 1 0 x3 x4 x6 x8 x9 = 10 0 1 1 0 x1 x3 x5 x7 x8 = 000000 As can be seen, the right hand side of the last equation remains constant, i.e., it is independent of all free variables.
Sentence 2: let the number of seed variables injected into this sys­tem require four 64-bit computer words to represent them.
Relationship: neutral