sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: If no class mispredicts occur, the amount of work done and energy consumed will be roughly equal to that if preloading is not used.
Sentence 2: the work discussed in this paper is based on energy meas- urements of the Itsy Pocket Computer [4], a state-of-the-art pocket computer developed by Compaq Computer Corpor- ation's Palo Alto Research Labs.
Relationship: neutral
Domain: Hardware
Sentence 1: Our butter.y­based topology is designed for east-west traf.c, and it may not be as well suited to a system with a four-sided memory layout.
Sentence 2: [45] K. Saban, Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Ef.ciency, Xilinx, White Paper, 2011, wP380 (v1.1).
Relationship: neutral
Domain: Hardware
Sentence 1: The designer may also provide application-specific information as optional inputs including input logic probabilities, DFF functional weighting are the average evaluation time for each node: speedup factors factors and overall softness weighting factors.
Sentence 2: aSSA shows constant analyzing time for circuits of similar complexity (ADDER, Xt1 and Xt2) while exhibits performance improve as the circuit size increases (DEC).
Relationship: neutral
Domain: Hardware
Sentence 1: The selection of links and of the number of redundant copies to be sent on the links is stochastically done at runtime by the net­work routers.
Sentence 2: the link connecting core Px,y to core Px,y+1 is denoted by Lx,y,N or by Lx,y+1,S, where the .rst two indexes denote one end of the link, while the third index shows the direction of the link.
Relationship: neutral
Domain: Hardware
Sentence 1: For instance, if we compare the PO layer for STD c432 layout and c499 layout (Figures 4a and 4b), we obtain Fourier graphs that look almost the same.
Sentence 2: on one hand PO and OD de.ne the transistor active areas, and the polysilicon gate critical dimension variation has a tremendous impact on the timing and energy consumption of circuits.
Relationship: neutral
Domain: Hardware
Sentence 1: The symbolic to physical address converter is deter­mined by the particular data layout method used.
Sentence 2: in order to demonstrate the simplifying effect of the power of two as­sumption, Equation 1 is rearranged to Equation 5. frc(x,y)=W(y - y mod n)+xn +y mod n (5) x n If it can be assumed that the number of memory columns is a power of two, Equation 5 can be signi.cantly simpli.ed.
Relationship: neutral
Domain: Hardware
Sentence 1: For example, the Mica2 can run at 3.3V/45mA; the iMote at 2.5V/60mA; and the Eco node at 3.3V/20mA.
Sentence 2: everlast [9] addresses the inrush­current problem by using a feed-forward regulator instead, but it does not inhibit booting.
Relationship: neutral
Domain: Hardware
Sentence 1: We are interested to synthesize the MEDL of the TTP con­trollers (and as a direct consequence, also the MHTTs) so that the process set is schedulable on an as cheap (slow) as possible processor set.
Sentence 2: in order to guide the optimization process, we need a cost function that captures the degree of schedulabil­ity for a certain MEDL implementation.
Relationship: neutral
Domain: Hardware
Sentence 1: Synthesisof reactive(1) designs.In 7th International Conference onVeri.cation, Model Checking, and Abstract Interpretation (VMCAI), volume 3855 of Lecture Notes in Computer Science, pages 364 380.
Sentence 2: in practice, this reach­ability problem can be solved for many kinds of continuous dynamical systems (including the intra-mode dynamics for the example shown in Fig.
Relationship: neutral
Domain: Hardware
Sentence 1: ij ctij)+ (i, j)eY (dPxy ij *CCi *ctij ) where [x,y] denotes either (x,y) or (y,x).
Sentence 2: 0 From the de.nition of the execution time change metric, it would appear that when a vertex is moved to a different partition, the met­ric values for all its ancestors would need to be updated.
Relationship: neutral
Domain: Hardware
Sentence 1: However, intuitively, one one may expect a greater .eld margin (difference between would expect a logic 1 state to be preferred since Magnet D should experience stronger F-coupling from Magnets B and H0 H1 A .nal observation demonstrates that another factor needs to be A and ) by placing the functional layers close, our C combined.
Sentence 2: the collective coupling .eld, Bout, from the inputs can be expressed by Eq.
Relationship: neutral
Domain: Hardware
Sentence 1: Furthermore, the metastability resolution time (tMSR(0), tMSR(1), tMSR(2))is improved by roughly a multiple of i over the original (tMSR(orig))when employing wagging synchronization.
Sentence 2: 2.2 Variable Control Circuit Parameters The properties of the system are defined by the connectivity of the control graph.
Relationship: neutral
Domain: Hardware
Sentence 1: [11] survey several heuristic approaches for VRP and MDVRP.
Sentence 2: in non-congestion-aware mode the distance between two scan FFs is the Manhattan distance, whereas in congestion­aware mode the distance is calculated as Dist ance(fi, f j)=xCon ·|xi -xj|+yCon ·|yi -y j| (3) where xCon and yCon are congestion coef.cients in the horizontal and vertical directions, calculated as the average ratio of used tracks to the total number of tracks for all grid cells in the bounding box {(xi, yi), (x j, y j)}.
Relationship: neutral
Domain: Hardware
Sentence 1: Figure1IllustrationofWidthofaComputation Clearly,W(0)=I,W(N)=O,and1:W(i): I+i:I+V:3N,foranyi.Indeed,I:2N,sine(by Defnition1)eahnodeofIprovidesanoperandtoatleast onenodeinVandeahnodeinVhasatmosttwooperands.
Sentence 2: pROOF.WebeginbyshowingthatBound(1)anbe rewrittenas T:(a(6)+6da(3N))N d..3N) +E,=l6Na(2B,.l)NB,.
Relationship: neutral
Domain: Hardware
Sentence 1: Ensuring O(1) Searches For key searches, instead of searching the segments directly, we maintain on-chip predictive filters that can be quickly queried to determine which segment, if any, holds the key.
Sentence 2: table 2: Expected number of false positives in segmented hash No of segments, N Bits per bucket, mb/n Naïve Bloom Filter Selective Filter Insertion Algorithm 1 × Pr.
Relationship: neutral
Domain: Hardware
Sentence 1: This paper is organized as follows: Section 2 describes the theoretical basis for our design approach; in Section 3 we give results from synthesis on a real technology library; in Section 4 we discuss an extension that covers the case of general vectorial Boolean functions; Section 5 concludes the paper.
Sentence 2: the permutation block is substituted with a new com­ponent whose purpose is to implement the actual Boolean function and which has 2N inputs (the decoded lines from the decoder) and 2M outputs (the lines to be fed into the encoder).
Relationship: neutral
Domain: Hardware
Sentence 1: Aregiongraphisanadjaenygraphbasedonthe regionsofthefoorplan1 .Eahregionisavertexinthis graph.Twovertiesarejoinedbyanedgeifandonly iftheorrespondingregionsshareaommonsegment ontheirboundaries.TheoutputofanyoftheBFSal­gorithmsanberepresentedintheregiongraphRGas follows:eahregionvertexontainsalistofthemodules thatwerealloatedareainthatregionbytheBFSal­gorithmalongwiththeareathatwasalloatedtoeah.
Sentence 2: inputID .1 .2 .3 .4 .5 .6 .7 .8 .9 .10 BeforeCenterAdjustment 3(3) 3(1) 3(2) 3(2) 3(1) 3(4) 3(3) 3(2) 3(2) 3(4) AfterCenterAdjustment 3(1) 3(2) 3(3) 3(1) 3(4) 3(1) 2( ) 3(2) 3(2) 3(5) Table5:Maximumnumberofmodulesthatareassignedtoaregionand,inparentheses,thenumberofregionswitha maximum-moduleassignment.TheseareshownbeforeandafterenteradjustmentforIBFS.Observethattheentryfor 17afteradjustmentis2(*).Thisindiatesthattherewerenoregionssharedby3ormoremodules.The*indiatesthat thenumberofregionswithtwomodulesisnotofinterest.
Relationship: neutral
Domain: Hardware
Sentence 1: We state the construction of a rank reduced linear re­gression model formally as follows.
Sentence 2: assume we have computed all the m signal arrival times of partition i by the second order SSTA, then one of these signal arrival times (say ATk)is given by: TT TT ¯ ATk = Mk + ßk G + GAkG + ck Xi + Xi BkXi, (11) global local Xloc i .
Relationship: neutral
Domain: Hardware
Sentence 1: [8] T. F. Chan, J. Cong, T. Kong, J. R. Shinner, Multilevel optimization for large-scale circuit placement., Proc.
Sentence 2: in each of these solves, the hybrid × 22cells outside the sub-region are propagated to the nearest boundary subregion, cells are considered movable, model is used to gain the speedup without sacrifice of performance.
Relationship: neutral
Domain: Hardware
Sentence 1: Experimental Setup In thissectionwedescribeourevaluationmethodology.Allourre­sultsareobtained with thebaselinecon.gurationsystemdescribed below.
Sentence 2: due to a much smaller fraction of aggregate L2 cache capacity being available to individual processors, there can be a signi.cant increase in intra­processor misses (all cache misses in a private cache are intra­processormisses),comparedtoasharedL2 cacheof amuchlarger (aggregate)capacity.
Relationship: neutral
Domain: Hardware
Sentence 1: Even if performance were not an issue, this approach is not feasible in the SR, as the code for the XorShift and Combine Tausworthe genera­tor does not .t in the 128-word instruction memory.
Sentence 2: tail coverage out to ±8s is also required for a good qualitygenerator[25],sotheabsolute minimum .xed-point output format is 19 bits with 15 fractional bits.
Relationship: neutral
Domain: Hardware
Sentence 1: Since there is no clock at all there is no need to perform a clock tree synthesis and the associated timing closure.
Sentence 2: lS LS LS LS LS LS LS LS Quasi-Delay-Insensitive (QDI) asynchronous logic, like HERMES-A using dual rail, ANOC using 1-of-4 IN North OUT North DI code for lower power, or CHAIN using more OUT Res complex 2-of-7 DI code for code density and additional power reduction, to provide robust NoC routers and links insensitive to timing variations ; Mixed design (internal router using bundle data logic while long NoC links are implemented using QDI logic), like in ASPIN [11], to benefit of both IN Res LS LS LS OUT LS West LS LS LS IN LS West Activity Control Voltage Control counts Vhig h/V lo w Switch data in&#38;out OUT South IN South LS IN LS East LS LS LS OUT LS East LS LS LS LS LS LS LS LS LS LS advantages : smaller logic in the routers, robustness on the long NoC links, but requiring additional conversion Figure 13.
Relationship: neutral
Domain: Hardware
Sentence 1: The technique in (1) is based on the prior results in [5] (which is optimal for continuously variable voltages, but not for discrete ones) and [3] (which is optimal for a single task, but not for multiple tasks), whereas the technique in (2) is based on an e.cient linear programming formulation.
Sentence 2: the target area is in the VLSI hardwired (i.e., static) data path scheduling, and not in the software-controlled (i.e., dy­namic) CPU speed scheduling by voltages.
Relationship: neutral
Domain: Hardware
Sentence 1: (mW) WLAN wait 2 40 5 [8] WLAN sync 4 40 76 [9] LTE sync 22 80 - LTE sense 20 40 - DVB-T sense 7 40 -  6.
Sentence 2: most of the existing solutions and prototypes do not focus on the practical design constraints that have to be considered when using those techniques in low-power and low-cost handheld devices.
Relationship: neutral
Domain: Hardware
Sentence 1: By experimenting with susceptance matrices associated with small-scale power/ground distribution 0.02 0.01 6 REFERENCES [1] Semiconductor Industry Association, The International Tech­nology Roadmap for Semiconductors: Design, 1999 Edition [2] H. Chen and D. Ling, Power Supply Noise Analysis Methodol­ogy for Deep-Submicron VLSI Chip Design, in Proc.
Sentence 2: it is worth noting that all the entries in SDG and SDGT are negative, and because of the shielding effect of susceptance ele­ ments, the diagonal entries in SDG and STDG which model the sus­ ceptive couplings between physically close symmetrical Vdd and Gnd segments have much bigger magnitudes than the other off­diagonal elements in S. Fig.
Relationship: neutral
Domain: Hardware
Sentence 1: At the beginning of a new simula­tion cycle, SystemC kernel checks the content of the mes­sage to be possibly exchanged with the driver.
Sentence 2: table 1 shows the performance of the two proposed co-simulation schemes, compared to the case of a co-simulation scheme based on the instantiation of wrap­pers in SystemC [14], (called GDB-Wrapper).
Relationship: neutral
Domain: Hardware
Sentence 1: 2 to arrive at the following parameter model: Zgridi = Cgridi · T (3) [XT T [ST RT ]T where Zgridi = gridi Ygridi]T , T = , Cgridi = Agridi 0 .
Sentence 2: none of these have included junction tunneling leakage, and a statistical full-chip leakage analysis method, which can handel the case where the underlying process pa­rameters are correlated non-Gaussian distributions, is still in need.
Relationship: neutral
Domain: Hardware
Sentence 1: This behaviour implies that the NIC s interrupts interfere with some form of batching optimization applied by the storage controller, leading to a reduced I/O throughput level.
Sentence 2: by having to actually consume step LOCAL BASE16 copy 0.157 (0.270) 0.163 (0.160) uncompress 43.932 (3.560) 45.337 (3.370) scan 81.524 (0.640) 83.784 (2.210) compress 496.400 (1.160) 501.013 (2.640)  Table 4: Filesystem test results for trace-.le (a single large .le, that is processed in a sequential scan).
Relationship: neutral
Domain: Hardware
Sentence 1: The load capacitance consists of the wire capacitances C(G) and the gate capacitances of G s wfanout gates U: CL(G) = Cw(G) + .
Sentence 2: the accuracy of this piecewise linear approximation is therefore completely determined by the subranges of x -y, i.e., by the choice of m and n. the constraint on cell size ranges where such approximation is applicable is eliminated, enabling optimization over the full range of gate sizes.
Relationship: neutral
Domain: Hardware
Sentence 1: The pads, 2, 3, 6, 7 and 9, are connected onto the channels between all the adjacent bump balls by assigning two partial global wires.
Sentence 2: if the number of the net, ni, is located inside the range between the bump balls, nj and nr, nr and ns, or nk and ns, the partial global wire from the channel of the net, ni, to the channel between the bump balls, nj and nr, nr and ns, or nk and ns, will be assigned.
Relationship: neutral
Domain: Hardware
Sentence 1: Thereasonforthisbehavioristhatthecellinducesonlyasmall perturbationinthevoltagelevelofthebitline.
Sentence 2: we evaluate thebenefitsofRowClone using 1) a casestudyofthefork systemcall,animportantoperationused by modern operating systems, 2)sixcopy/initialization inten­sive benchmarks: bootup,compile,forkbench,memcached [2], mysql [3],andshell(Section 7.3describes thesebenchmarks), and3)awidevarietyofmulti-core workloads comprising thecopy/initialization intensive applicationsrunning alongside memory-intensive applicationsfrom theSPEC CPU2006 bench­marksuite [51].
Relationship: neutral
Domain: Hardware
Sentence 1: This representation is widely used in multiplierless implementations, because it reduces the number of non-zero digits by 33%, on average compared with the binary representation [5].
Sentence 2: this constraint expresses that the operations in the path must not be included in the solution altogether, by guaranteeing that the solution to be found by the 0-1 ILP solver has the minimum delay and allowing the possible sharing of partial terms that are inputs of the operations in the path with other partial terms.
Relationship: neutral
Domain: Hardware
Sentence 1: Therefore, only the last element will be kept in the cache af­ter prefetching, while the previous N - 1 data transfers are useless with additional energy overhead.
Sentence 2: iMPACT OF REUSE PATTERN ON SPM PREFETCH EFFICIENCY 2.1 SPM Prefetching Without Reuse With explicit control on data movement, we need to identify the prefetched and evicted data sets, which is essential for an SPM prefetching scheme.
Relationship: neutral
Domain: Hardware
Sentence 1: If the input range is not an important concern, for example, when Vref is 1 V and the supply voltage is 2.5 V or even higher, then the operating point of the input of comparator can be well defined without forcing the transistors into triode region.
Sentence 2: the CAV-based 6-bit flash ADC is divided into four parts: complementary reference voltage generation block, average-value unit, comparator string, and the encoder.
Relationship: neutral
Domain: Hardware
Sentence 1: These routing algorithms eliminate deadlocks without ad­dingVC,byprohibiting some global turns as shown in Figu­re1(, , ).
Sentence 2: hARDWARE IMPLEMENTATION In a 2D-Mesh, a given router R can be in 9 di.erent si­tuations: If none of the 8 neighboring routers is faulty, R is con.gured as NORMAL, implementing the classical X-First routing function.
Relationship: neutral
Domain: Hardware
Sentence 1: Whereas the LSQ requires associative and age-prioritized searches for each access, we propose that an address-indexed store-forwarding cache (SFC) perform store-to-load forwarding and that an address-indexed mem­ory disambiguation table (MDT) perform memory disam­biguation.
Sentence 2: memory disambigua­tion requires at most two sequence number comparisons for each issued load or store.
Relationship: neutral
Domain: Hardware
Sentence 1: Sparse LU) and reduces the associated L2 misses by up to 75%, however, in the rest of the benchmarks it cannot iden­tify the memory access patterns accurately and the reduc­tion in L2 misses falls below 30%.
Sentence 2: this form of software-directed prefetching can overcome some of the challenging issues with hardware-only prefetchers such as timeliness, accuracy, and access pattern prediction.
Relationship: neutral
Domain: Hardware
Sentence 1: We used ASLAN to automatically synthesize approximate ver­ sions of ten sequential benchmarks, resulting in energy reductions of 1.20X-2.44X for tight quality constraints, and 1.32X-4.42X for moderate quality constraints.
Sentence 2: by using general purpose veri.cation techniques, we are able to address the problem in a broader and more general context.
Relationship: neutral
Domain: Hardware
Sentence 1: We enco de a maximum of 4 of these, with those that are unused being ignored.
Sentence 2: research suggests that hardly any morpholog­ical features are created de novo from new genes [2, 19], instead di.erent morphological features between species are the result of the same genes (usually one of the four Hox clusters) being employed in di.erent contexts.
Relationship: neutral
Domain: Hardware
Sentence 1: 4.2 Comparisons between Reliability and Performance Based Current Density Limits Figure 6 shows the comparison of javg-performance with the values of javg­reliability for isolated and realistic multilevel structures in a 0.1-µm technology.
Sentence 2: by doing so and assuming balanced loads at the two ends p and q of the trunk and using (22), the optimum length l* for ensuring zero clock skew can be obtained by solving the following equation: .l * *  (24) () lA =0 ßTxdx +- 0 where A is a constant and can be written as follows: 2 LL 1 Lc0 (25) LC +ß(0 +CL ) () -0 ßxT x dx ) A = ( + L Lc Txdx c () .. Lc +C 2 0 L 00 Given circuit parameters L, CL, c0, ß, and T(x), we can easily compute the constant A and solve (24) to obtain the optimum position for the clock signal connection to the net segment.
Relationship: neutral
Domain: Hardware
Sentence 1: Rather than generating a set of geometric constraints with parasitic bounds as in [5], the intrinsic relationship between performance and parasitics is regarded as a mixed-integer nonlinear function of layout geometries restricted within the maximum allowed performance deviation.
Sentence 2: 60.0 100 90.0 10.0 - PB-RC 63.9 105.1 90.5 16.7 3084 PS-RC 64.0 105.0 90.4 16.7 2920 PM-RC 64.3 106.4 90.5 16.7 2815 Folded- cascode opamp Spec.
Relationship: neutral
Domain: Hardware
Sentence 1: Kluwer Academic Publishers, 1995.
Sentence 2: if one considers a t0 < t, such that v(t) is insensitive to v(t0), then one may assume that v(t0) = 0 without a.ecting the voltages at time t. As a matter of fact, we can assume that at all time t'= t0,wehave v(t')= 0.
Relationship: neutral
Domain: Hardware
Sentence 1: While long­er gate lengths linearly worsen area and capacitance, improved short-channel effects reduce variability to enable more aggressive voltage scaling, which quadratically improves power consump­tion.
Sentence 2: varia­bility and soft error reliability have often been heralded as key concerns for logic and memory at low voltages, but recent tech­niques have been developed to both mitigate root causes at the device level and augment operating margins at the circuit level.
Relationship: neutral
Domain: Hardware
Sentence 1: Empirical Determination of Channel Characteristics for DSRC Vehicle-to-vehicle Communication Vikas Taliwal, Daniel Jiang, Heiko Mangold, Chi Chen Raja Sengupta DaimlerChrysler Research and Technology North America, Inc. University of California at Berkeley 1510 Page Mill Road Palo Alto, CA 94306 650 845 2561 taliwal@rtna.daimlerchrysler.com ABSTRACT Dedicated Short Range Communication (DSRC) wireless band, allocated by the FCC for vehicular communication, constitutes the basis for one of the first vehicular ad-hoc networks/systems that is likely to be deployed.
Sentence 2: general Terms Measurement, Performance Keywords Dedicated Short Range Communication, Nakagami fading channels, parameter estimation, spatial channel correlation, vehicle-to-vehicle communication.
Relationship: neutral
Domain: Hardware
Sentence 1: A Universal Approach to Data Center Network Design Bruce Maggs Department of Computer Science, Duke University Durham, North Carolina, USA Abstract This talk proposes an approach to the design of large-scale general-purpose data center networks based on the notions of volume and area universality introduced by Leiserson in the 1980's in the context of VLSI design.
Sentence 2: for all other uses, contact the owner/author(s).
Relationship: neutral
Domain: Hardware
Sentence 1: Variants v3 and v4 can realize the G.721 encoder, while variants v1 and v4 can realize the Pegwit encoder.
Sentence 2: the idea is to implement several ASIC designs in such a way that they share the datapath, memory structure, and several bottom layers of intercon­nect, while each design has only a few unique metal layers.
Relationship: neutral
Domain: Hardware
Sentence 1: These archi­tecture description languages (ADL) automate the generation of code generators and instruction set simulators.
Sentence 2: 3 Operation State Machine Model Microprocessor speci.cations commonly partition their de­scriptions into two fundamental layers: the operation layer includ­ing the semantics and the timing of the operations, and the hard­ware layer including various hardware units.
Relationship: neutral
Domain: Hardware
Sentence 1: SEU) can occur in an unknown lo­cation (bit) of a codeword, therefore they can be effectively considered as random errors.
Sentence 2: the following three cases are considered: 1) comparison of simplex and duplex RS(18,16) with no scrubbing and variable SEU rate; 2) analysis of duplex RS(18,16) for different Tsc periods and under the worst case scenario of the SEU rate; 3) comparison of simplex and duplex RS(18,16), and sim­plex RS(18,16) under different rates for permanent faults.
Relationship: neutral
Domain: Hardware
Sentence 1: However, with the IC technolo­gies advancing, when the driver impedance does not dom­inate the metal resistance ofinterconnect any more, these models begin to su.er inaccuracy problem.
Sentence 2: standard Deviation Figure 5 demonstrates seven waveforms obtained from HSPICE simulations on the modeling and actual circuit of a0.18µm technology inverter.
Relationship: neutral
Domain: Hardware
Sentence 1: The majority of these were attempts to reach a vul­nerable service (e.g., phpMyAdmin).
Sentence 2: this compiled version of the Web Handler is slightly larger (1,570 LUTs, 665 FFs) compared to the orig­inal manual implementation (1,026 LUTs and 586 FFs), but both achieve nearly the same performance when creating re­sponse packets (the compiled version needs two additional cycles).
Relationship: neutral