sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: The algorithm achieves the CRLB for small angular estimation errors (for N = 6 receivers), but the performance deteri­orates for large spreads in AoA.
Sentence 2: the sequential algorithm, whichis aninstance of a stochastic approximation algorithm lutionusingbothAoAand range modalitiesissimilartothat with AoA alone with moderate increases in N. with very good range measurements, very large increases in N are necessary to achieve competing resolution.
Relationship: contrasting
Domain: Hardware
Sentence 1: Ann Gordon-Ross University of FloridaGainesville-FL, USA ann@ece.u..edu Frank Vahid University of California, Riverside Riverside-CA, USA vahid@cs.ucr.edu Memory subsystem parameters such as total size, line size, and associativity can be tuned to an application s temporal and spatial locality to determine the best cache con.guration to meet optimiza­tion goals [3].
Sentence 2: the effectiveness of such tuning is de­pendent on the ability to determine the best cache con.guration to complement an application s memory addressing behavior.
Relationship: contrasting
Domain: Hardware
Sentence 1: 1.1RelatedWork Thefllunitanddecodedinstructioncachewerehard­wareassistsproposedbyPattet.al.aspartofthe HPSdesignphilosophy[13,14].Theydescribethe fllunit,whichcompactsinstructionsgeneratedfrom aserialinstructionstreamintoadecodedinstruction cache.TheuseofthesehardwareassistsonanHPS versionoftheDECVAXprocessorwasseentoresult insignifcantperformanceimprovements[14,15].The ideaofafllunitwasrevisitedbyFranklinandSmoth-ermanin1994,todynamicallygroupRISCinstruc-tionsintoaVLIWlikeinstructions,andshowedup totwotimesimprovementsoverasingleissueproces­sor[12].Inalaterpaper,SmothermanandFranklin showedthatcollectingdecodedX86instructionsus­ingafllunitandstoringtheminadecodedinstruc­tioncachecanimprovethedecoderateascompared toaP6-likedecodingstructure[16].Theyalsopre­sentedaregisterallocationandrenamingschemeus­ingthefllunitapproachtoalleviatetheexcessive bandwidthplacedontheP6registerrenaminghard­ware.ThepicoJava-IIdoesnotrequireadditionalre­namingstageorexcessiveportstotheStackCache registerfle,asitalreadyhasmultipleportstofacili­tateinstructionfoldingoptimizations.
Sentence 2: 295 Fillunitbasedoptimizationsfortracecaches[17] andtracecachebasedpreprocessing[18]improves performancebytransforminginstructionswithina traceline.tracecacheshavebeenproposed formachineswhichcanexecuteupto8or16in­structionsinparallelandhencestoremultiplebasic blocksinatracecacheline.Inmarkedcontrast,we storeonlyonebasicblockofbytecodesintheDB­Cache,aswearelimitedbythehardwareresources whichwecanaddinanembeddedenvironment.We performinstructionfoldingwithinaDB-Cacheline, insteadofacrossbasicblockstoreducecomplexity.
Relationship: contrasting
Domain: Hardware
Sentence 1: Let V1 be the initial value of V(t) and V2 be the maximum voltage the rising edge of Table 3 Dynamic Power of a 4-LUT under different input vector pairs 2.4.2.3 Transition Density and Glitch Analysis A recent work on FPGA power modeling [Poon02] uses Boolean difference to calculate the transition density.
Sentence 2: it is difficult for Boolean difference to precisely capture the spatial and temporal signal correlations among circuit nodes [Chou96].
Relationship: contrasting
Domain: Hardware
Sentence 1: Adiferentapproachtostatisticalperformancemodel­ingwasusedin[NS94].Aperformancemodelwascon­structedbasedontheinteractionsbetweenmachineand programparallelism.Thisworkextendedanearliermodel presentedin[Jou89].Withthesemodels,benchmarksare analyzedandperformanceisestimateddirectlybyappli­cationofaformularelatingprogramandmachineparal­lelism.Thissameresearchgroupcontinuedtheirstatis­ticalmodelingworkin[NS97].AsetofMarkovmodels wereconstructedtorepresentmachinebehaviorwhileex­ecutingaspecifcbenchmark.Thesemodelswherethen linkedtogetherandperformanceestimated.Thisapproach ismoreabstractthanthedirectsymbolicexecutionmethod presentedhere,andtheauthorsfocusonmoreidealma­chinemodels.However,extremelyaccurateperformance estimatesareachieved.
Sentence 2: insomerespectsthegoalsofourapproacharesimi­lartothegoalsofthecreatorsofthesyntheticWhetstone [CWW76]andDhrystone[Wei94]benchmarks.weattempttoprovideanautomatedapproachtogenerat­ingasyntheticbenchmark.Furthermorethisautomated approachisbaseduponanalysisofrealprogramsandis demonstrablymorerepresentativeofactualmachineper­formance.
Relationship: contrasting
Domain: Hardware
Sentence 1: In general, a preferred-direction implementation of the X Architecture is likely to increase the number of vias and can be worse for delay despite the reduction in wire length.
Sentence 2: the M2 path from (0,0) to (0,10) to (10,20), with a wrong-way diagonal jog, includes no vias and is also 19.5% shorter than the Manhattan connection (Figure 4d).
Relationship: contrasting
Domain: Hardware
Sentence 1: We see that, as the number of BHQ[i] entries increases, the lost detection window decreases (Figure 8(a)) and the hit rate increases (Figure 8(b)).
Sentence 2: we have to do more timestamp compar­isons until a hit or BHQ[i] exhaustion (Figure 8(c)), and the BHQ takes more area.
Relationship: contrasting
Domain: Hardware
Sentence 1: Due to the wider tracks in this set of routes, the contribution to the total delay due to inductive effect among signal nets alone increased to an additional 5.5% of the RC delay for both processes.
Sentence 2: the contribution of in­ductive effect under the non-ideal power supply to the total owo delay still maintained 7% and 8% for the 0.18 and the owo 0.13 processes, respectively, in addition to the delays due to the inductive effect among signal nets alone.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the optimal alignment taiopt = t, asisillustrated in Figure 5(b), we compute the noise on node l at the optimal align­ ment, constrained by the switching window of [taie,tail]of k. If taiopt > t and the switching window of k has not yet ended at time t,there is again ambiguity about whether the optimal alignment can occur and we schedule a check point for a future point in time to determine if the optimal alignment is possible.
Sentence 2: contrary to the early event time computation, the check point is scheduled at the noisy victim late event time t , computed with the aggressor aligned at vntime t at node k (line 14,15).
Relationship: contrasting
Domain: Hardware
Sentence 1: From readings in Tables 2, 3, 4 and 5 we conclude that the internal oscillator modes consume less power regardless of whether the radio is ON or not..
Sentence 2: for the external oscillator, when operating at less than the oscillator frequency (0.9 3MHz) some frequency limiting circuitry functions consuming more power as compared to the high frequency range (3 8MHz) as indicated in Tables 4 and 5.
Relationship: contrasting
Domain: Hardware
Sentence 1: For power-constrained applications, such as medical instruments, wireless sensor networks, and implantable devices, subthreshold SRAMs and logics are popular utilized to minimize power consumption.
Sentence 2: with the progress of process technology scaling down, designing reliable subthreshold circuits have to face many challenges, including process-induced device variation, serious threshold voltage variation due to dopant fluctuation, and decreasing Ion-Ioff-ratio.
Relationship: contrasting
Domain: Hardware
Sentence 1: The probability that a randomly selected node is an attacker is (1 -g)fn, and we have: E(Tu)= TRR + 1 (E(Tsense )+ E(Tdetect)+ E(TRR)) × ( -1) (3) (1 -(1 -g)fn)h Time to find a good path in Reputation System(minutes) the node a long time to .nd a good path.
Sentence 2: when pis close to 0 or the route length is small, Tu approaches 0, which means that the node can .nd a good path quickly.
Relationship: contrasting
Domain: Hardware
Sentence 1: This means that ti progresses in its execution until it reaches pnext without being preempted, i.e., from a progression of prog(k), ti reaches a progression of pnext by being executed only for (pnext - prog(k)) time units, and with an unchanged cumulative preemption delay of total delay(k).
Sentence 2: in the execution scenario built by Algorithm 1, (k+1) ti s execution reaches a progression of prog= pnext by being executed for Qi time units, and with a cumulative preemp­tion delay of total delay(k+1) = total delay(k) + delay= max total delay(k).
Relationship: contrasting
Domain: Hardware
Sentence 1: We show that the data packing technique requires 38 wires for a 32-bit bus and achieves a speedup of more than 2.3× and 1.5× over the unencoded bus in the address and data buses, respectively.
Sentence 2: the data permuta­tion technique requires 34 wires for a 32-bit bus and achieves a speedup of more than 1.6× and 1.4× over the unencoded bus in the address and data buses, respectively.
Relationship: contrasting
Domain: Hardware
Sentence 1: The capacitance of the direct wires is close to zero, which leads to the small value for the coe.cient kmod 3 .
Sentence 2: in the case of the interconnections between a module and theI/Opins, many lines aregoing around the module, leading to a higher number of double and hex lines, Error [%] Error [%] which results in a higher value for the coe.cient k3 io .
Relationship: contrasting
Domain: Hardware
Sentence 1: Various sophisticated fiber-optic interferometric sensors have already been well researched, involved that the intrinsic Fabry-Perot (IFP) sensor, the extrinsic Fabry-Perot (EFP) sensor and the in-line fiber etalon (ILFE) sensor [1-4]in particular, which present a high resolution, a resistance of electromagnetic interference, and be easily inserted into or attached to different engineering structures.
Sentence 2: each type has its own disadvantages, especially interfered by thermal and bent effect, be difficult to fabricate in large-scale and a weak multiplex ability to realize a distributed system.
Relationship: contrasting
Domain: Hardware
Sentence 1: Under conditions of our experiments and considering limits of the proposed models, we can conclude that (1) the implementations of evolvable systems which are based on the idea of VRC are not so sensitive to faults in the con.guration memory as it could be assumed if one considers their higher implementa­tion cost (however, they are more sensitive to faults than a VRC-less solution), (2) it is possible to improve fault toler­ance of digital circuits by means of their evolutionary de­sign directly in the VRC and (3) redundant components (LUTs) help to protect the circuit from faults in the con­.guration bitstream.
Sentence 2: these experimental results obtained from simulations must be con.rmed by real imple­mentations of VRCs in FPGAs and in real environments.
Relationship: contrasting
Domain: Hardware
Sentence 1: complexity of dual edge-triggered storage elements, their delay is typically larger than that of single edge-triggered structures.
Sentence 2: the delay of the proposed flip-flop is comparable to the fastest high-performance single-edge triggered designs: 33% worse than SDFF and 20% worse than HLFF (39% and 25% including the duty cycle penalty) as shown in Fig.
Relationship: contrasting
Domain: Hardware
Sentence 1: P 63 9 P clock=12 clock=12 S=10,E=2  S=0,E=1 1 CC CC 1 2 Probability Probability 1 23 21 clock=14 P 9 9 P clock=14 1 23 21 S=0,E=1 S=2,E=1  101112 13 14 CC 1 1 CC 8 9 10 11 12 Time Time P 9 9 P Unit A Unit B clock=15 clock=15 S=slack S=1,E=1 S=3,E=1 E=event CC 1 1 CC Figure 5: An example of clock selection.
Sentence 2: randomly choosing the clock cycle time without .rst identifying possible candidate clocks leads to exhaustive search­ing, which is highly undesirable.
Relationship: contrasting
Domain: Hardware
Sentence 1: For instance, if there is a rect­angular region on the screen that displays Thomas Jefferson in some readable font, a human might expect that pressing that por­tion of the screen would select Jefferson, causing Jefferson s name to be highlighted and eventually causing a vote to be recorded for Jefferson if no other selection is subsequently made in this con­test.
Sentence 2: because it involves semantic interpretation of the contents of a particular screen image by a human it is not clear how to specify this expected behavior in a precise, mathematical fashion.
Relationship: contrasting
Domain: Hardware
Sentence 1: )= pear strange and is infact not done in [6].
Sentence 2: it im- H0+ .1H11 + .21H12 + .2H21+ (7) +.2 plies that BA = LAT when B= LT, which, as we shall see has 2H22 + .1.2Hxt  Figure 1.
Relationship: contrasting
Domain: Hardware
Sentence 1: Because of tightly allotted design time and expensive mask cost, pre-fabrication tim­ing veri.cation considering both manufacturing and environmental variability will become a key technology for successful chip design.
Sentence 2: recent chip design with lowered supply voltage yet increasing power dissipation enforces us to endure delay vari­ation due to supply voltage .uctuation [5, 6].
Relationship: contrasting
Domain: Hardware
Sentence 1: Direct comparisons would be dif.cult to make, even if we had access to their source code, because advanced data structures use more memory and require signi.cant up-front set-up, along with maintenance.
Sentence 2: a single-threaded version of LIRE takes only <15% of runtime in our entire place-and-route .ow, despite frequent (>10) invocations by the placer (Table 1).
Relationship: contrasting
Domain: Hardware
Sentence 1: This scaling leads to a similar scaling for refresh BASE SD HE HER BASE SD HE HER BASE SD HE HER BASE SD HE HER BASE SD HE HER  BASE SD HE HER BASE    SD HE HER ECC will consume 34% of the power consumed by SECDED.
Sentence 2: the increase in Hi-ECC s dynamic power pushes its total power to 58% of SECDED s total power.
Relationship: contrasting
Domain: Hardware
Sentence 1: Reported ex­perimental results on a network similar to the one we used in our propagation experiments state that dissemi­nating 11kB takes 10,000 transmissions: disseminating the 19kB of the native implementation would take ap­proximately 18,000 transmissions.
Sentence 2: from the data in Table 3, a RegionsVM program takes fewer than .ve hundred transmissions, less than 3% of the cost, while providing safety.
Relationship: contrasting
Domain: Hardware
Sentence 1: Under a u-RT demultiplexing al­gorithm, a switch with speedup S = 2 and input-bu.ers larger than u, can employ a centralized algorithm (e.g., [3]).
Sentence 2: a fully-distributed demultiplexing algorithm in­troduces relative queuing delay and relative delay jitter of at ) ( r N R S time-slots, for any bu.er size under leaky­bucket .ows with no bursts.
Relationship: contrasting
Domain: Hardware
Sentence 1: Energy Recovery Clocked Dynamic Logic Matthew Cooke, Hamid Mahmoodi, Qikai Chen, and Kaushik Roy School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA { cookem, mahmoodi, qikaichen, kaushik}@purdue.edu Abstract Energy recovery clocking results in significant energy savings in clock distribution networks as compared to conventional square­wave clocking.
Sentence 2: since energy recovery clocks are sinusoidal in nature, standard dynamic logic styles do not work efficiently when used with energy recovery clocks.
Relationship: contrasting
Domain: Hardware
Sentence 1: By evaluating (19) directly for M = 2 and covariance matrix in (26), we have the asymptotic sum-rate as [ ] 1 (1 - d2) Rsum = log + 0.51.
Sentence 2: (27) 2 d1d2 the outer sum-rate distortion for two Gaussian source has been previously found as, [7], [ ] 1 (1 - d2) Ro sum = log .
Relationship: contrasting
Domain: Hardware
Sentence 1: (Noteinpartiularthatwiththefxeddelay parameter=010,aper-fowbandwidthalloationthat isequaltothemeanrateofthefowsissuÆienttosupport theend-to-enddelaybound219ofthedelayservielass.)
Sentence 2: theaveragereservedbandwidtheventuallydropsonsider­ablybelowthoseofthePer-fowBB/VTRSandIntServ/GS shemes.Asaresult,undertheAggrBB/VTRSsheme thereissuÆientresidualbandwidthlefttoadmitoneortwo morefowsintothenetwork.UnderthePer-fowBB/VTRS sheme,aVT-EDFshedulerstartswithalloatingthemin­imumpossibledelayparametertoafow,therebyproduing theminimumbandwidthalloation(i.e.,themeanrateof thefow).asmorefowsareadmitted,thefea­sibledelayparameterthatanbealloatedtoanewfow beomeslarger,resultinginhigherreservedrate.Asare­sult,theaveragereservedbandwidthperfowinreases.It isinterestingtonotethatalthoughthePer-fowBB/VTRS andIntServ/GSadmitthesamenumberoffows(i.e.,27), thePer-fowBB/VTRSshemehasaslightlysmallerav­eragereservedrateper-fow.Henethereismoreresidual bandwidthleftunderthePer-fowBB/VTRSshemethan thatundertheIntServ/GSsheme,albeitthisresidualband­widthisnotenoughtoadmitanotherfow.Thisslightgain intheresidualbandwidthisduetotheabilityofthePer­fowBB/VTRSshemetoperformpath-wideoptimization whendeterminingtheminimumfeasiblerate-delayparam­eterpairforafow.Inontrast,intheIntServ/GSsheme, thereservedrateofafowisdeterminedusingtheWFQ referenemodel,whihthenlimitstherangethatthede­layparameteranbeassignedtothefowinanRC-EDF sheduler.
Relationship: contrasting
Domain: Hardware
Sentence 1: (A) In contrast, if the SA's offset is 3.5s from the mean, then almost half of all possibilities for IREADm:1 fail the yield criterion.
Sentence 2: because it is less likely that the value for VOS is at least 3.5s, the probability that a die has a failed column like this increases only to 7.5%.
Relationship: contrasting
Domain: Hardware
Sentence 1: In particular, the bandwidth between two 3D­stacked chips is a function of the chips common surface area, whereas the bandwidth between 2.5D-stacked chips is bounded by their perimeters.
Sentence 2: 3D stacking incurs additional area overhead for TSVs, often requiring large keep-out regions [2], [42], where a 2.5D-stacked chip is .ipped face down so that the top-layer metal directly interfaces with the µbumps.
Relationship: contrasting
Domain: Hardware
Sentence 1: 2.2 FaultyBitsinCacheMemories Parity and SECDED1 [4] can detect and/or correct hard errors in cache memories.
Sentence 2: permanent faulty bits cannot be repaired, and thus, there are two options when a hard error is detected: either the hardware is recon.g­ured/disabled to prevent further errors, or error correction mechanisms such as SECDED are in place to recover origi­nal data continuously from faulty data storage.
Relationship: contrasting
Domain: Hardware
Sentence 1: Based on Table 1, incre­mental arrival-time (required-arrival-time) calculations may not seem to be the most attractive application of the concept given that N in this case is typically less than 10 (50).
Sentence 2: incremental chip slack calculation involves a min operation over tens-of-thousands of Gaussian test-slacks, wherein only a small subset of test-slacks are updated dur­ing each incremental timing optimization step.
Relationship: contrasting
Domain: Hardware
Sentence 1: INTRODUCTION Ready-to-use IP designs of complex functionalities greatly re­duce the time and effort of hardware development.
Sentence 2: iP designs in the form of static library modules have the limitation Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: contrasting
Domain: Hardware
Sentence 1: Fig­ure 3(b) shows the optimal-timing CSA-tree structure, which we call circuit1, produced by the algorithm in [14] under a restriction on the CSA timing model.
Sentence 2: figure 3(c) shows the optimal-timing FA-tree structure, which we call circuit2, produced by the algorithm in [12] under the general FA timing model.
Relationship: contrasting
Domain: Hardware
Sentence 1: Parameter Descriptions N Number of segments T0 Nominal refresh period Ti Refresh period of Segment i V = Refresh period vector Table 2: TRM parameters Independent refresh operation from each segment requires per-segment row and column access circuitry.
Sentence 2: this hardware overhead is minimal since most DDIs have already Figure 6: Transpose unit (* denotes either R, G, or B) adopted multi-bank frame bu.ers to reduce the internal op­erating frequency by accessing multiple banks simultane­ously.
Relationship: contrasting
Domain: Hardware
Sentence 1: The Receiver Architecturally, the receiver is simpler than the transmitter since it only contains a clock and a decoder.
Sentence 2: both of their de.nitions are more complex: rx s clock is more complex because we capture the effects of drift, jitter, and so forth here, so the timeout updates nondeterministically (again using the System.Random library); rx s decoder is more complex because here we model whether rx captures the signal depending on the relationship between tx s and rx s timeouts.
Relationship: contrasting
Domain: Hardware
Sentence 1: The capacitance of a thin nanowire ribbon will be much lower than that of the copper wire, perhaps as little as 30% as much, depending on the aspect ratio of the copper.
Sentence 2: for such thin conductors the resistance of nanotubes will be higher than that of traditional thick copper, but short interconnects (up to 100 gate pitches or so) are not dominated by wire R, but by driver R, and gate and interconnect C. Therefore re­placing short copper wires by a thin layer of nanotubes could provide both lower power dissipation and increased perfor­mance[20].
Relationship: contrasting
Domain: Hardware
Sentence 1: These non-MTCMOS IPs are directly powered by VDD and GND, and therefore, vigilant (always awake) even in the sleep mode.
Sentence 2: since the output nodes of all MTCMOS gates get floating as the VGND gets floating in the sleep mode, the floating inputs to the vigilant IPs can cause very large short-circuit current that flows from VDD to GND directly as shown in Figure 6.
Relationship: contrasting
Domain: Hardware
Sentence 1: Also, the algorithm of [1] extends the exact CSE algorithm of [9] to handle the constants un­der the general number representation increasing the search space and .nds more promising solutions than those of the exact CSE algorithm.
Sentence 2: the graph-based algorithms are not restricted to a particular number repre­sentation and synthesize the constants iteratively by build­ingagraph.
Relationship: contrasting
Domain: Hardware
Sentence 1: Most STA tools model the noisy input waveform at in_u with an equivalent linear waveform, * eff, with a single reference point (input arrival time) and a constant slope (an effective input slew.)
Sentence 2: different waveforms with identical arrival time and slew when applied at in_u can result in very different propagation delays through 4INVx.
Relationship: contrasting
Domain: Hardware
Sentence 1: In an ideal situation where L2 cache slices are larger than program working sets, the OS can allocate new pages to requester cores; each L2 cache slice then simulates a pri­vate cache, ensuring fast data access.
Sentence 2: if a local cache slice is too small for the program s working set and its performance suffers due to this, subsequent page allocations may be directed to cache slices in other cores to increase the effective cache size.
Relationship: contrasting
Domain: Hardware
Sentence 1: Since there are many differ­ent sensing applications that require small, passive transduc­ers and relatively simple amplifying circuitry, this does not severely limit the usefulness of the system within the chosen design space.
Sentence 2: some active sensors like air quality sensors and gas detectors which have substantially greater current drives for heaters or pulsed infrared lamps cannot be powered by AudioDAQ.
Relationship: contrasting
Domain: Hardware
Sentence 1: This stems from the fact that the proposed schemes employ more combinations of pilots than those of the con­ventional scheme (i.e., more combinations of pilots leads to the better IFO detection probability performance in AWGN channel).
Sentence 2: in the multipath fading chan­nel, the performance of the two proposed schemes is reversed above the SNR value of -10 dB and the performance of the proposed scheme I and conventional scheme becomes reverse in the SNR range, more than -4 dB, respectively as shown in Fig.
Relationship: contrasting