sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: A specialized set of synthesis techniques, formally known as datapath merging [1] [3], have been proposed in order to map datapath con.gurations onto the shared resources of a CGRP in an optimized manner.
Sentence 2: while the operation binding consists of the resource sharing deci­sions among the operations of a single DFG, the datapath merging refers to the resource sharing decisions among the functional units of multiple datapaths (see Figure 1), where each datapath is generated after performing the operation binding on its corresponding DFG.
Relationship: entailment
Domain: Hardware
Sentence 1: (i) ERR0 =1, : .Pi+1 Gi i+1 ERR1 =0k-1:0 k-1:0 =1, .Pk-1:0Pki -1:0 =0,which implies that a long carry chain generates at a bit position and prop­agates to the MSB position.
Sentence 2: if ERR0 =1,ERR1 adder width window size Perr(ERR0 =1, ERR1 =1) 64 14 < 0.01% 128 15 < 0.01% 256 16 < 0.01% 512 17 < 0.01%  = Table 1: Error rates in VLCSA-2 for signed Gaussian inputs, 0, we know that a long carry chain occurs and does not incur errors.
Relationship: entailment
Domain: Hardware
Sentence 1: We used a modified version of CACTI 3.0 [10] and assumed 0.13µm technology.
Sentence 2: we modified CACTI so that it can estimate the energy, access time, and area of memory Memory LossReduction PerfLoss 8-r/8-w ports RF - 27% w/ 16 DWQ 85% 4% w/ 16 OPB 15% 22% w/ 16 DWQ and 16 OPB 96% 1% structures such as a register file, the DWQ, and the OPRQ, which do not require tag memory in cache memories.
Relationship: entailment
Domain: Hardware
Sentence 1: The study examines scanning prevalence, rates, types, and address clustering, offering a unique global perspective.
Sentence 2: in this paper we also examine the phenomenon of scanning, but from a perspective global in time rather than space.the data upon which we base our study begins in 1994 during which the measured site experienced virtually no scanning activity through 2006, long past the point at which scanning became a ubiq­uitous phenomenon [10].
Relationship: entailment
Domain: Hardware
Sentence 1: Even if executed on the same GPU, FFT and MxM have different throughput and execution time, which may indeed turn into different radiation-induced error rates.
Sentence 2: the FFT elaborates 8 times more data than MxM (64x512x512 complex elements in the FFT versus 2048x2048 real elements in the MxM), but instantiate less threads (512x512 for each of the 6 iterations in the FFT versus 2048x2048 in the MxM).
Relationship: entailment
Domain: Hardware
Sentence 1: Accurate assessment of the testability of a given part of a design is important not only because it avoids problems in the production testing phase, but also because it makes sure that the design is being properly tested from a functional point of view.
Sentence 2: the existence of dark spots in the design, i.e., blocks or constructs that are not being properly exercised is to be avoided in an agile development process.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.2 Optimization Problem We seek a solution that will systematically satisfy the objective that the sum of the buffer sizes required does not exceed the avail­able on-chip resources (e.g., the number of BRAMs).
Sentence 2: we want to .nd the loops l for all arrays a such that: BS(a, l) < maxBuffSize a.Arrays(P) .
Relationship: entailment
Domain: Hardware
Sentence 1: However, in order to take moments on a linear network, we still must model transis­tors as linear resistors.
Sentence 2: our devices are modeled with only two .xed resistances: when a device is on, we assume a .xed .nite 2When using (unmodi.ed) Nodal Analysis, the matrix is symmet­ric, diagonally dominant, and has positive diagonal elements.
Relationship: entailment
Domain: Hardware
Sentence 1: Hence, the steady-state temperatures of the 3D IC must be written as a function of this distance in the analytical formulation, with the channel widths as an input parameter.
Sentence 2: if the distance from the inlet is measured along the coordinate axis z, then we need to .nd an equation of the form: d T(z) = F(z, wC(z), T(z)), (1) dz where T(z) is the steady-state temperatures vector on the IC and wC(z) is a vector of width functions of different  Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: Under this approximation, we can set the constant ks as follows: Hg Wg × Ws + × Hs Ch Cv ks = , (4) Area(s) where Hg (Wg) is the height (width) of the congestion bin, Hs (Ws) is the height (width) of the netbox, Ch (Cv)isthe total horizontal (vertical) capacity of the congestion bin.
Sentence 2: ch (Cv) represents the number of wires in all metal layers that can pass the congestion bin horizontally Hg Wg (vertically).
Relationship: entailment
Domain: Hardware
Sentence 1: 2) .f W .W min dd min = =0 , = =0 , .W .W .V .V dd dd 22 22 () .V .g ( ) V .f W .W min dd min = =0 , = =0 22 22 .W .W .V .V dd dd Note that the first two conditions in Equation 2 tend to push optimization toward larger gate sizes and lower Vdd.
Sentence 2: a reduction in Vdd causes an increase in W, which causes further reduction in Vdd.
Relationship: entailment
Domain: Hardware
Sentence 1: This paper presents single-sensor methods for device pose classi.cation and walking speed estimation that generalize well to standard mobile phones and tablets.
Sentence 2: the paper makes the following contributions: We give device pose classi.cation and walking speed es­timation methods that are predictive for new users, and do not assume known sensor orientation or placement;  Our approach, based on regularized kernel methods, can   be ef.ciently implemented online; and Through a leave-one-participant-out generalization exper­iment with 14 participants, we show that online pose esti­mation accuracy was 94%, and online speed estimator had an error of less than 12-15% compared to truth.
Relationship: entailment
Domain: Hardware
Sentence 1: It be­comes obvious that the design methodology and simulation performance have a signi.cant impact on the ef.ciency of the exploration process, hence, on the quality of the archi­tecture implementation and the design time.
Sentence 2: the ability to vary the abstraction level of the underlying ar­chitecture model, that means, the re.nement from an initial functional speci.cation to an RT-level implementation, is of extreme importance to avoid expensive turn-around times.
Relationship: entailment
Domain: Hardware
Sentence 1: The path loss and interference usually vary with time and, as a result, there is a considerable variation in the error rates observed in message packets transmitted over the wireless channel.
Sentence 2: sINR for MH i in a given transmission is ~' = cz, + N, (1) where G is called the channel processing gain, Pi is the trans- mit power of MH i, 7/i is the path loss between MH i and the BS, 27i is the amount of interference for MH i, and Ni is the intensity of the noise in MH i's wireless channel.
Relationship: entailment
Domain: Hardware
Sentence 1: 2.2 Timing Models and Test Point Insertion The delay of a single logic gate can be expressed as d = gh + p, where g and h are logical e.ort and electrical e.ort, respectively; and p is parasitic delay.
Sentence 2: we use the delay model in [15] that connects the gate delay to its sizing and operating voltages: · L2 ktp · kf it Vdd Delay = · (1+s)Vdd-Vth 2 · n · µ · f2 2·n·ft t (ln(e + 1))2 (1) .i · Wi + Wi+1 · Wi where L is e.ective channel length, Vth is threshold voltage, W is gate width, Vdd is supply voltage, n is substreshold slope, µ is mobility, Cox is oxide capacitance, D is clock pe­riod, ft is thermal voltage ft = kT /q, s is drain induced barrier lowering (DIBL) factor, subscripts i and i + 1 rep­resent the driver and load gates, respectively, .
Relationship: entailment
Domain: Hardware
Sentence 1: (Cnt_0_0 # Cnt_0_1 #= Cnt_0_0 + 2, (Cnt_0_0 #>= 8) #==> Cnt_0_1 #= Cnt_0_0, For incomplete case statements, the expressiveness of GNU Prolog provides a solution.
Sentence 2: the selected inputs are combined as a new integer variable; and another new Boolean variable is introduced to encode the fact that the default entry is taken.
Relationship: entailment
Domain: Hardware
Sentence 1: They can then moved within the data-path if and only if there are enough registers associated to the serialization feed-back loop at that time.
Sentence 2: since .p i=ksi denotes the delay­line depth associated with these registers, the num­ber of registers that can be used for pipelining is then min(.p i=ksi,.i) (see .gure 3.e for the skewing and 3.f for the register factorization).
Relationship: entailment
Domain: Hardware
Sentence 1: (VPC -Vk)ik (VPC ,Vk,t)+ ; k=1Rk replace its constraints by circuit equations: V.k = fk and V¯.k = f¯ k, for k =1,2,...,n, (3) ik(VPC ,Vk,t) (Vk-V¯k) Vk-V¯k) where fk = - and f¯ k = ; set time T to ¯ Ck CkRk RkCk the .nal charging time; set f(·) to zero; the trajectory vector u(t) to be optimized becomes the power clock voltage VPC (t).
Sentence 2: one is to shape the power clock waveform, to minimize the total energy dissipation during charging each capacitor from a speci.ed initial voltage to a speci.ed .nal voltage within a time period T .
Relationship: entailment
Domain: Hardware
Sentence 1: As shown in the table, our design methodology C can improve the die area by 15.9% and the maximum IR drop by 41.8% with compa­rable wirelength and average delay, compared to the design methodology B.
Sentence 2: as shown in Table 2, our methodology required only one iteration to get the reported results while Methodologies A and B needed several itera­tions.
Relationship: entailment
Domain: Hardware
Sentence 1: We assume that step 2 is performed using a backward stable algorithm for example Gaussian elimination with partial pivoting, the GMRES iterative method, Backward stability implies that there exists Hk such that (1) (A + H )d = r where , Hk =f(n)es A k k k where f(n) is a reasonably small function of n .
Sentence 2: equation (1) states that the computed solution dk is an exact solution for an approximated problem.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.2 Timely Access of Main Memory Predictor Tables The second key insight observed from the epoch model is that it is possible to hide the latency of accessing a slow pre­dictor under a prior off-chip miss.
Sentence 2: if the pre­diction is needed in the current epoch, the predictor access can be timely as long as the access is made in an earlier epoch.
Relationship: entailment
Domain: Hardware
Sentence 1: The typical contract consists of a precondition (obligation) and a postcondition (bene.t) and it is interpreted as a partial correctness guarantee: If the input to the operation ful.lls the precondition and if the operation terminates, then the output is guaranteed to meet the postcondition.
Sentence 2: a contract provides a (partial) speci.cation of an operation that an implementation of the operation must ful.ll.
Relationship: entailment
Domain: Hardware
Sentence 1: We showed that, in the case of internal faults, some DFT structures may become useless, with detrimental effects on test effectiveness and product quality.
Sentence 2: as an example, we have shown that, for a recently proposed scheme (employed for the Motorola high performance microprocessor e500 core [17]), this may be the case for the 48% of all possible stuck-ats, for the 46% of all possible stuck-opens and for the 10% of all possible resistive bridgings.
Relationship: entailment
Domain: Hardware
Sentence 1: Categories and Subject Descriptors B.5.2 [Design Aids]: Automatic synthesis; F.1.2 [Modes of Com­putation]: Process Management Parallelism and concurrency General Terms Design, Algorithms, Languages  Keywords High Level Synthesis, Iterative stencil loops, Symbolic Execution, Performance and Area Estimation 1.
Sentence 2: iNTRODUCTION A large number of interesting algorithms for scienti.c computa­tion and multidimensional signals processing, come in the form of iterative applications of a given transformation t. starting from a signal f (a frame), the overall transformation T is de.ned as the repeated application of t: f1 = t( f ), f2 = t( f1), ..., fn = t( fn-1) = T ( f ) Typically, the desired T ( f ) is a .xed point of the single step trans­formation t : t(T ( f )) = T ( f ).
Relationship: entailment
Domain: Hardware
Sentence 1: 2.2 Synthetic Error Injection Lacking a design with real errors, as is often the case in veri.cation research, it is necessary to inject design errors to evaluate the capabilities of a proposed veri.cation approach.
Sentence 2: automatic diagnosis and diagnostic test pat­tern generation tools require designs with errors for exper­imental evaluation of their e.ectiveness.
Relationship: entailment
Domain: Hardware
Sentence 1: In general, if a datapath component and its associated signals can be implemented by a set of conven­tional FPGA tiles arranged in a H × H square with W tracks per channel, the same circuit can also be implemented by a single FPGA tile with bus-based connections.
Sentence 2: the granular­ity of the tile, M , should be equal to H2 ; and the logic capacity of the multi-bit logic block should be H2 times of the logic capacity of a conventional FPGA logic block.
Relationship: entailment
Domain: Hardware
Sentence 1: We utilize the Rent s rule based circuit fanout distribution 0 [12][13] to validate their claim of allocating the segments of mostly length 4.
Sentence 2: we observe that for the best area­delay trade-off, FPGA arrays need to have segments of length 4 as given in equation (19): Circuits FO m Ours Xilinx-like FO Net FO () .
Relationship: entailment
Domain: Hardware
Sentence 1: On the side of random access memory (RAM), nano-magnetic storage devices (MRAM) are very promising candidates to replace the traditional CMOS-based memory solutions.
Sentence 2: spin Transfer Torque (STT) memory is gaining signi.cant attention as it is non-volatile, scalable, has low read access times and its endurance can reach to that of SRAM [3, 7, 16].
Relationship: entailment
Domain: Hardware
Sentence 1: The existence of the lowest necessary threshold voltage VT (VTmin) of MOSFETs in each block, and the ever-larger VT variation (.VT) that occurs with device scaling are mainly responsible for the issues.
Sentence 2: for the SRAM block, which needs quite a high VTmin (e.g., 0.5-0.7 V) to ensure the data retention current, Vmin is high and becomes higher due to the ever-larger .VT [2].
Relationship: entailment
Domain: Hardware
Sentence 1: Comparing the best models returned for different values of C we observe that most of the terms of a lower-order best model do appear as sub-terms in higher-order best models.
Sentence 2: the best model in 8(4, 4) is a third- order model, namely, the best model in `5(4, 3): B(4, 4) = B(4, 3).
Relationship: entailment
Domain: Hardware
Sentence 1: A General Method to Evaluate RF BISTTechniques Based on Non-parametric Density Estimation Haralampos-G. Stratigopoulos, JeanneTongbong and Salvador Mir TIMA Laboratory/CNRS 46Av.F´elixViallet, 38031 Grenoble, France Abstract We present a general method to evaluate RF Built-In Self-Test (BIST) techniques during the design stage.
Sentence 2: the adaptive kernel estimator is used to construct an estimate of the joint probability density function of the performances of the RF device under test and the actual BIST measurements.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that (where applicable) such a compiler-based strategy has an important advantage over pure OS-based and hardware-based techniques.
Sentence 2: the compiler-based strategy (unlike pure OS or pure hardware-based strategies) does not rely on history of data access patterns; that is, the compiler can predict (quite accurately for the array-intensive codes) future data access patterns (and also, future idle times), and select the most appropriate mode to switch to when idleness is predicted.
Relationship: entailment
Domain: Hardware
Sentence 1: The tighter delay constraint values are chosen such that the differences are exactly equal to the delay overheads exhibited by the flipflop variants in Table 1.
Sentence 2: given a circuit with the operating delay point set at (D-62)ps, the inclusion of the F100 flipflops at the out­puts will introduce a fixed amount of delay overhead (of exactly +62ps) resulting in the modified circuit operating at the initial delay value D. In a similar fashion, we introduce the F130 flipflop for the circuit synthesized to operate at (D-92)ps and so on for the five delay points depicted in the plot.
Relationship: entailment
Domain: Hardware
Sentence 1: Because ubiquitous computing requires a ver­tical system integration spanning all levels from application software down to low-level hardware issues we provide some complementary approaches here covering some fundamental implementation approaches.
Sentence 2: these are: recon.gurable architectures for .exible adaption to communication standards  recon.gurable solutions for e.cient wireless baseband implementations  dynamic power management  recon.gurable processors  design of .exible systems based on Network-on-Chip (NoC) platforms  software-based hardware deployment and remote re­con.guration  This paper is structured as follows: First we decribe how speci.c system features which are important for ubiquitous systems can be addressed on block-level by applying recon­.gurable techniques.
Relationship: entailment
Domain: Hardware
Sentence 1: We illustrate the application of novel HW-SW thermal and reliability analy­sis frameworks to enhance the resilience to aging of processing cores of MPSoCs at the microarchitectural level.
Sentence 2: we provide for illustration purposes the consequences of differ­ent compiler optimizations and registers assignment techniques in the shared register .le architecture of a Leon 3 processor [15] while executing an extended set of real-life benchmarks.
Relationship: entailment
Domain: Hardware
Sentence 1: Thus our results on total counts also contradict Mathur and Cook s results: we believe the reason for this is thatPME assume perfecttrace alignment whichdonothold ingeneral(seeFigure3in Section2.1.3).Ifthis assumption does not hold, then the corrections that PME computes may introduce error instead of reducing error.
Sentence 2: we believe, and our results support our belief, thatTAM is a more consistent performer than PME.
Relationship: entailment
Domain: Hardware
Sentence 1: These characterizations are based on two forbidden sub­structures (again, see [14] for details).
Sentence 2: this means that the following con.gurations have to be avoided: 1. induced chordless cycles of length 4 in E EE; 2. so-called 2-chordless odd cycles in the set E EEof edges excluded from E EE(see [11, 14] for details); 3. infeasible stable sets in E EE.
Relationship: entailment
Domain: Hardware
Sentence 1: To compute the arrival time in a block-based SSTA frame­work, two atomic operations, max and sum, are needed.
Sentence 2: given D1 and D2 D1 = d01 + A1X + XT B1X + r1R1, T D2 = d02 + A2X + XB2X + r2R2, (14) we want to compute T Dm =max(D1,D2)= dm0 + AmX + XBmX + rmRm, T Ds = D1 + D2 = ds0 + AsX + XBsX + rsRs.
Relationship: entailment
Domain: Hardware
Sentence 1: While EMR of a router only drops its associated wavelength, RMRs are labeled with their respective resonant wavelength modes.
Sentence 2: rMRs of router (i,j,l) labeled with .1,a , .1,ß , .l , .d1 , .d2 , .2,a , and .2,ß drop wavelength channels associated to the destination groups D1,a , D1,ß , Dl , Dd1 , Dd2 , D2,a , and D2,ß , respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: Given the two different mapping schemes offered by L0 buffers, the compiler will choose between two different unrolling factors for each loop: N (where N is the number of clusters, in this work, 4), and no unrolling.
Sentence 2: the algorithm will choose the unrolling fac­tor (1 or N) that minimizes compute time, which can be computed statically by the compiler.
Relationship: entailment
Domain: Hardware
Sentence 1: Additional set of constraints for domino gate output x includes all the possible constraints of type g1 *g2*...*gn *x, where {g1,g2,...,gn} is the minimum set of non clock inputs turning off the pull-down network of that node.
Sentence 2: applying 0 to {g1,g2,...,gn} and 1 to the other gate inputs in evaluation phase pro­duces 1 at output x.
Relationship: entailment
Domain: Hardware
Sentence 1: When any of the two following criteria is satisfied, the location of this sub-band and this frame is considered an onset: Sub-band loudness is above a pre-determined threshold L[ j] = threshold1 follows the musical note structure.
Sentence 2: the central frequency F[ j] = ... 1 0 L[ j] threshold1 of each sub-band equals the musical notes (G3, G#3, A3, A#3, < etc.).
Relationship: entailment
Domain: Hardware
Sentence 1: (¬x2 .y2)  INF((x1,x2),(y1,y2)):=(x1 .y1,x2 .y2)  SUP((x1,x2),(y1,y2)):=(x1 .y1,x2 .y2)  Of course, the above de.nition has been made with some care.
Sentence 2: it turns out that the above operations on .
Relationship: entailment
Domain: Hardware
Sentence 1: These attacks allow the adversary to either reduce the size of the computationally hard problem underlying the cipher security, or provide additional information to solve it ef.­ciently.
Sentence 2: concerning the case of symmetric block ciphers, Biham and Shamir introduced the Differential Fault Analysis (DFA) technique [5], providing a way to break the security provided by the DES cipher.
Relationship: entailment
Domain: Hardware
Sentence 1: We assume an adversary who can eavesdrop and mod­ify all FPGA-external communication lines, eavesdrop and modify all FPGA-external memories, arbitrarily recon.gure the FPGA, but cannot eavesdrop or modify FPGA-internal states.
Sentence 2: we exclude invasive attacks such as glitch attacks, microprobing attacks or attacks using laser or Focused Ion Beam (FIB) to gain or modify FPGA internals.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION Aggressive silicon geometry scaling opens the door to new market segments, encompassing a vast array of emerging ap­plications such as environment sensors to monitor wind, sea level, temperature, tsunamis, biomedical and healthcare sen­sors to monitor the body, etc.
Sentence 2: technology evo­lution enables the design of battery-powered ultra-low-cost (e.g., below 1 USD) computing devices to achieve the main requirements for this new market segment: (i) ultra-low en­ergy consumption in order to extend battery lifetime, (ii) very simple system design for increased yield and reduced cost and (iii) strong functional and timing guarantees for running crit­ical applications on top.
Relationship: entailment
Domain: Hardware
Sentence 1: The common notation of a qubit denotes one of these states as |0> and the other as |1>.A quantum system with a collection of n qubits is called a quantum register of size n. Unlike a classical bit, the state of a qubit can take not only two pure states |0> and |1>, but also any linear combinations of these pure states, also called superposition, resulting in exponentially larger state space.
Sentence 2: the state of a qubit .
Relationship: entailment
Domain: Hardware
Sentence 1: k: root if [o~] = 0 node(c~) = node(ig,... ,ik+l)[ik] otherwise We can then define the set .A(p) of substates leading to node p (or "above" p) as .A(p) = {c~ : node(s) = p}.
Sentence 2: a(one) = S. We illustrate the use of decision diagrams for storing a state space with a few simple examples.
Relationship: entailment
Domain: Hardware
Sentence 1: In reality, slew constraint is much more prevalent than timing constraint: it is reported in [2] that only a fraction (roughly 5-10%) of nets need to be re-bu.ered for delay op­timization; for the remaining fraction (roughly 90-95%), the slew based bu.er insertion was su.cient to meet the net s timing constraint.
Sentence 2: it is su.cient to bu.er all nets to .x slew violations without worrying about delay.
Relationship: entailment