sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: As depicted in these figures, in general, 2D­HERT is the most efficient optical architecture under various traffic patterns, while ETorus leads to the worst power and delay metrics compared to the optical architectures.
Sentence 2: averaging through different traffic patterns, 2D­HERT ONoC reduces data transmission delay by 18%, 4%, and 70% over OXbar, LR, and ETorus, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: (9) In (5)-(9), the DCT coefficients {G(u, v); u = 1,2,...,P, v = 1,2,...,Q} are the problem unknowns.
Sentence 2: we need to determine {G(u, v); u = 1,2,...,P, v = 1,2,...,Q} based on the measurement data {g(xm, ym); m = 1,2,...,M}.
Relationship: entailment
Domain: Hardware
Sentence 1: Rn and z .Rq, which in conjunction are the design variables for each of S applications, or scenarios.The variable xmust be chosen before the particular scenario s is known; the vari­able z, however, is chosen after the value of the scenario random variable is known.
Sentence 2: z is a function of the scenario random variable s. To describe our choice for z, we list the values we would choose under the di.erent scenarios; i.e., we list the vectors z1,...,zS .
Relationship: entailment
Domain: Hardware
Sentence 1: Our aim, with the SMARTdriver, is to delay the response for the best-case without a.ecting the worst-case, so that the variation in delay becomes as small as possible.
Sentence 2: the concept is to make the re­sponse slower with minimum e.ective capacitance, as the cycle delay has to be set to the worst-case delay anyway.
Relationship: entailment
Domain: Hardware
Sentence 1: With the help of this simulator, we can infer (Table 1) end-to-end delays for both real-time and best-e.ort tra.c, as well as compute network statistics such as packet loss, network throughput and lifetime, via per-node energy con­sumption estimation.
Sentence 2: this simulation model gets user-de.ned attributes (network topology and nodes parameters) through an XML .le, which we automatically generate through an ad-hoc MATLAB script, which takes as inputs the outputs of the Network Deployment Simulator (i.e., nodes positions and parent-child relations, Section 3) and the windows o.set de.ned by the TDCS scheduling tool (Section 4.1).
Relationship: entailment
Domain: Hardware
Sentence 1: Any higher noise amplitude will result in there snm remaining a single equilibrium state, making the SRAM cell unable to store either 0 or 1 .
Sentence 2: if the remaining equilibrium state represents a 1 , the charging/discharging process on the two capacitors will pull any initial state, even if it is a 0 , to the only equilibrium state 1 .
Relationship: entailment
Domain: Hardware
Sentence 1: Waiting for 50 cycles before deciding whether or not to exit runahead mode re­duces the probability of prematurely incorrect predictions).
Sentence 2: if too many of the loads executed during runahead mode are INV, this is used as an indication that the current runahead period will not generate useful prefetches, therefore the processor is better off exiting runahead mode.
Relationship: entailment
Domain: Hardware
Sentence 1: These testcases come from hard Combinational Equiva­lence Checking (CEC) problems of HDL speci.cations against their gate level implementation.
Sentence 2: from the generic results of Cases Berkmin 0 1 2 4 k Vliw001 165 227 462 230 354 429 Vliw002 117 47 186 160 177 351 Vliw003 213 15 202 168 472 339 Vliw005 96 61 132 213 217 316 Vliw006 150 126 168 303 260 420 Vliw008 103 11 87 102 168 256 Vliw011 68 40 67 160 64 323 Total 912 527 1304 1336 1712 2434 *Aborted after 1 hours.
Relationship: entailment
Domain: Hardware
Sentence 1: 2.2 Other combinations of static and dynamic analyzers 2.2.1 Reverse engineering The combination of static and dynamic information ex­traction is used in other domains.
Sentence 2: several reverse engineering techniques use a comparable approach: in [9], the dynamic analysis is used to re.ne the result of the static analysis and eliminate false positive in design pattern recognition, and in [14], the static and dynamic information are combined to generate UML diagrams.
Relationship: entailment
Domain: Hardware
Sentence 1: Finally, to achieve extreme performance gains from mem­computing, we also implement the idea of having a speci.c memcomputing cache as suggested in [6].
Sentence 2: this cache is used exclusively to accommodate LUTs for in­memory computation, and this is achieved by inheriting the Cache class and assembling it to the system through the .exible python-enabled con.guration scripts in gem5.
Relationship: entailment
Domain: Hardware
Sentence 1: To achieve these goals, the cost function for each grid node used in a routing path is augmented by a penalty function for each routing directive.
Sentence 2: the PathCost formula (see VPR [3]) is modified in the following manner to account for the effects introduced by bias factors: PathCost (n) = PathCost (m) + num _ factors PresCost (n) · HistCost (n) ·.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.W.1.2 Transforming into a MLGP Prob/em In this section, we show that, for a given wire order as obtained by the algorithm in section 4.2, the formulation in section 3 can be transformed into a MLGP problem.
Sentence 2: it can be shown that the constraints (a)-(g) can all be expressed in the form of: f (Wi gsi; ) h( Pi gdi gAyie/d gAtiming )(I6) where f (Wi,si;) represents a posynomial function of Wi and si; g and h (PigdigAyie/dgAtiming) represents an affine function of Pi, di, Ayie/d and Atiming.
Relationship: entailment
Domain: Hardware
Sentence 1: It is easy to see that the time complexity of the algorithm is on the average linear with respect to the product of these two figures.
Sentence 2: it is faster than quadratic considering that the number of unique references N is much smaller than the number of total references N.  Benchmark Time (sec) Benchmark Time (sec) adpcm 2.9 adpcm 27 bcnt 0.11 bcnt 0.13 blit 6.8 blit 2.0 compress 290 compress 30 crc 0.80 crc 5.1 des 19 des 31 engine 28 engine 56 fir 0.67 fir 2.3 g3fax 1200 g3fax 390 pocsag 3.2 pocsag 8.2 qurt 0.090 qurt 0.20 ucbqsort 23 ucbqsort 31 Table 8: Algorithm run Table 9: Algorithm run time: data traces.
Relationship: entailment
Domain: Hardware
Sentence 1: For both memory and logic chips, the result has been exponential increases in speed and functional density versus time combined with exponential decreases in power dissipation and cost per function versus time.
Sentence 2: the number of logic transistors and memory bits per chip have been quadrupling every three to four years, while the speed of microprocessors, for example, has been more than doubling every three years, increasing from about 2 MHz for the Intel® 8080 in the mid-1970 s to well over 1 GHz for current leading-edge chips.
Relationship: entailment
Domain: Hardware
Sentence 1: ME T S: Metric for Electro-Thermal Sensitivity Contrasting electrical and electro-thermal simulations can evaluate the particular contribution of self-heating for a particular device at a speci.ed temperature.
Sentence 2: at a par­ticular temperature in Figure 4(a), the difference between Ia and Iet is the degradation in current due to self-heating.
Relationship: entailment
Domain: Hardware
Sentence 1: If the resulting OM is greater than 1, then it is clamped to 1.
Sentence 2: theorectically, it can be shown that [16] if a signal f has an observability measure less than 1, then the input vector v under consideration is not in the B oolean difference [1] of the output z i with respect to f. a fault effect at f cannot be sensitized to z i under input vector v. As a result, it is safe to conclude that f is a false single defect candidate because it is not solely responsible for the failing output under consideration.
Relationship: entailment
Domain: Hardware
Sentence 1: Assume the the maximum variation on switching delays of the crosspoints is 200%.
Sentence 2: if the expected switching delay of the crosspoints is T ,then for a crosspoint it can be a value between T and 3T .There­fore, in the worst case, the delays of both crosspoints n1 and s1 are 3T , while delays of n2 and s2 are T .
Relationship: entailment
Domain: Hardware
Sentence 1: Translation Caching: Skip, Don t Walk (the Page Table) Thomas W. Barr, Alan L. Cox, Scott Rixner Rice University Houston, TX {twb, alc, rixner}@rice.edu  ABSTRACT This paper explores the design space of MMU caches that accel­erate virtual-to-physical address translation in processor architec­tures, such as x86-64, that use a radix tree page table.
Sentence 2: these caches accelerate the page table walk that occurs after a miss in the Translation Lookaside Buffer.
Relationship: entailment
Domain: Hardware
Sentence 1: As the number of test structures is increased, more information can be derived about variations on the die, and its delay PDF can be predicted with greater con.dence: the standard deviation of the PDF from SSTA is always an upper bound on the standard deviation of this new delay PDF, as shown in Figure 1(d).
Sentence 2: by using more or fewer test structures, the approach is scalable in terms of statistical con.dence.
Relationship: entailment
Domain: Hardware
Sentence 1: We want to identify branches whose outcomes infer a value range of the same variable and the range (of the store) subsumes the range of the load.
Sentence 2: to put it in a simple form, our goal is to discover the follow relationship: branch bs s directionÎstore st s range; store st s range subsumes load ld s range; load ld s rangeÎ branch bl s direction; such a relationship indicates that from branch instruction bs s direction we can know bl s direction exactly.
Relationship: entailment
Domain: Hardware
Sentence 1: A Universal Approach to Data Center Network Design Bruce Maggs Department of Computer Science, Duke University Durham, North Carolina, USA Abstract This talk proposes an approach to the design of large-scale general-purpose data center networks based on the notions of volume and area universality introduced by Leiserson in the 1980's in the context of VLSI design.
Sentence 2: we suggest that the principle goal of the network designer should be to build a single network that is provably competitive, for any application, with any network that can be built for the same amount of money.
Relationship: entailment
Domain: Hardware
Sentence 1: Although many core architectures po­tentially provide increased performance, they also suffer from in­creased IC power densities and thermal issues are a serious concern in latest designs with deep submicron process technologies [5, 8].
Sentence 2: it is key to design many core designs that prevent hot spots and large on-chip temperature gradients, as both condi­tions severely affect system s characteristics.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.5 Maintaining the A-pipe success rate Since an instruction gets only a single chance at pre­execution in the A-pipe, a deferred instruction and all its data.ow successors (until an update arrives from the B-pipe) will fully expose any stalls associated with the consumption of their results.
Sentence 2: the two­pass scheme provides one second chance to expose ILP; for these instructions, that chance has been lost.
Relationship: entailment
Domain: Hardware
Sentence 1: For instance, given four load instructions load a[i], load a[i+1], load a[i+2], load a[i+3] scheduled in consecutive clusters and marked as interleaved mapping, only one of them is marked to prefetch the next L1 block to the buffers (POSITIVE prefetch in case variable i is increased at the end of the loop).
Sentence 2: only the .rst instruction in the .nal schedule is marked.
Relationship: entailment
Domain: Hardware
Sentence 1: Properties of the Veri.cation Algorithm We will now investigate the properties of the veri.cation algorithm.
Sentence 2: we prove that the algorithm is sound, that it is com­plete (under the assumption that the auxiliary procedure Interpo­late returns the right assertions), and that its time and space com­plexity is polynomial in the data complexity of the input program and speci.cation (again, under the assumption about Interpolate).
Relationship: entailment
Domain: Hardware
Sentence 1: The results indicate that the Wi-Fi logger may reduce the battery s lifetime by 9% at least, 14% in average, and 27% at most, since 60% of people use their 5 Day 1Day 7 Used Storage (Mbytes) 4 Day 14 3 2 1 smartphone for 14 to 41 hours with a single battery charge [31].
Sentence 2: a user can use the smartphone with the proposed system for 12.4 to 31.8 hours depending on individual usage patterns.
Relationship: entailment
Domain: Hardware
Sentence 1: Such high design and performance overheads are apparently unaffordable in embedded and on-chip ap­plications.
Sentence 2: the error rate of an MLC cell must be signi.cantly reduced (i.e., down to ~ 10-6 )so that the error rate of a 64B cache line can be improved to ~ 1.5× 10-8 .
Relationship: entailment
Domain: Hardware
Sentence 1: Compared with C/DC, S/DC significantly reduces the redundant prefetches through the three filtering mechanisms while issuing comparable new prefetches.
Sentence 2: s/DC_conf0 only avoids generating redundant prefetches when handling stride patterns, and S/DC_conf1 can further eliminate most of the redundant prefetches generated when handling other DC patterns.
Relationship: entailment
Domain: Hardware
Sentence 1: The nominal RSNM of case (C) (90mV at Vdd = 0.4V) is comparable to the value of the 10T bulk subthreshold SRAM (~ 90 mV at Vdd = 0.4V) [8].
Sentence 2: the 6T UTB SOI SRAM cell with back-gating technique can provide sufficient margin for subthreshold operation comparable to the 10T bulk subthreshold SRAM cell.
Relationship: entailment
Domain: Hardware
Sentence 1: Since the applications are network­bounded, we would like to increase as much as possible the rate of remote memory operations issued, and injected on the network.
Sentence 2: we would like to match the injection rate sustained by the nodes and the network bandwidth, to avoid, or at least minimize, the undesirable stalls for the core pipeline(s) caused by remote memory ac­cesses.
Relationship: entailment
Domain: Hardware
Sentence 1: By individually controlling the body bias voltage of all the elemental circuits in the FPGA tile, fabricated FPGA drastically reduces the static current by 92.6% in the maximum case and by 91.4% on average, while the FPGA tile area is increased by well-separation margins and programmable body bias circuits.
Sentence 2: well-separation margins occupy 41% of the tile area.
Relationship: entailment
Domain: Hardware
Sentence 1: hn Lemma 1: If the intersection of two mutually exclusive nodes hown and is non-empty under a condition Y, then the nodes in the nhnn intersection are implicants of node Y.
Sentence 2: if (&#38;&#38;Y) FgnFgneFgg lSand (how&#38;&#38;Y) lS, then YlS, where lSis the set of common implications.
Relationship: entailment
Domain: Hardware
Sentence 1: Our simula­tions account for all performance and energy overheads incurred by our schemes.
Sentence 2: the energy numbers we present in­clude the energy spent in maintaining the idleness predictors (in the hardware-directed scheme) and the energy spent in maintain­ing the table-to-bank mappings (in the query-directed scheme), and in fetching and executing the bank turn-on/off instructions (in the query-directed scheme).
Relationship: entailment
Domain: Hardware
Sentence 1: On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis Saurabh N. Adya Igor L. Markov Paul G. Villarrubia University of Michigan University of Michigan IBM, Corporation EECS Department EECS Department 11501 Burnet Road Ann Arbor, MI 48109-2122 Ann Arbor, MI 48109-2122 Austin, TX 78758 sadya@eecs.umich.edu imarkov@eecs.umich.edu pgvillar@us.ibm.com ABSTRACT In the context of physical synthesis, large-scale standard-cell place­ment algorithms must facilitate incremental changes to layout, both local and global.
Sentence 2: .exible gate sizing, net buffering and detail placement require a certain amount of unused space in every region of the die.
Relationship: entailment
Domain: Hardware
Sentence 1: Since picture-by-picture peak signal-to-noise-ratio (PSNR) cannot accurately reflect the impact of different frame rates on human vision system, we propose to utilize the mean opinion score (MOS) metric instead of PSNR metric for better VQ evaluation.
Sentence 2: given the extraction parameter {t,q}, the empirical model for SVC in [9] can be adopted to quantitatively measure the VQ of the reconstructed video as (, ) Qq() uTCF t (1) VQt q () the MOS for picture quality Q(q) is written as 1 () 92.8 u(1 ) Qq (2) 0.34( Gq() s) 1 e where G(q) is the average peak signal-to-noise ratio (PSNR) at quality level q.
Relationship: entailment
Domain: Hardware
Sentence 1: However, recent studies show that NoCs can draw a substantial percentage of a chip s power, by up to 10%~36% [8, 9, 28].
Sentence 2: the static power of routers has become a significant contributor of power consumption, consisting of more than 35% and 43% of the total NoC power at 45nm and 32nm processes, respectively (more details in Section 2).
Relationship: entailment
Domain: Hardware
Sentence 1: In addition, the probability that the distance of an active user to the BS is between r and r+ dr is proportional to the actual load generated by these users, namely: d.(r) (1 - B) .
Sentence 2: c(r) the density of active users is inversely propor­tional to their peak rate C(r) as in the absence of admission control (refer to §3.1).
Relationship: entailment
Domain: Hardware
Sentence 1: Based on this method an input with the real value of 0 = p = 1isconverted to 0 by the probability of (1 - p) and converted to 1 by the prob­ability of p. Using constraints of form I and II in the relaxed mode improves the LP solver runtime signi.cantly, however, due to this random conversion from real to binary, the op­timality of the solution is greatly reduced.
Sentence 2: the solutions obtained by RLP are extremely sub-optimal.
Relationship: entailment
Domain: Hardware
Sentence 1: ABB research showed that adjusting the body voltage is an effective method for 3.1 Thermally-Dependent Delay Modeling Delay constraints are imposed by setting the delay at each regis­ter input and at each primary output (PO) node to be less than Tclk , the clock period.
Sentence 2: the delay at the output of gate k, dkO , is obtained by adding dk, the delay of gate k, to the maximum delay at gate k s inputs while considering all gates j in the fanin of k. + max ) dkO = dk (djO (1) jEF I(k) Logical effort provides a simpli.ed means of modeling gate delays.
Relationship: entailment
Domain: Hardware
Sentence 1: The search process is driven by a cost function, shown below, that includes both physical and logical distance information: ACTFi = ODC(xj) DIST(i, j)= af(D(i, j)) + ßg(L(i, j)) j=1 In fact, module Mi is idle for all the conditions such that none of its inputs is observable to the environment.
Sentence 2: when ACTFi = 1, the clock signal feeding module Mi can be disabled, as no useful computation is going to be performed by the logic in Mi.
Relationship: entailment
Domain: Hardware
Sentence 1: While stream processors are well-suited to implementing algo­rithms that are data.ow in character, a key challenge is the ef.cient implementation of control constructs.
Sentence 2: the presence of conditionals ( if-then-else constructs) and loops ( for and while constructs) in algorithms typically creates performance bottlenecks that limit the throughput of the resulting stream processor even if the remainder of the algorithm is ef.ciently pipelined.
Relationship: entailment
Domain: Hardware
Sentence 1: As shown in this figure, optically routing destination­checking and acknowledgement packets through the network consumes approximately 80% and 86% of the total power dissipated for optical data transmission in the case of low and high offered loads, respectively.
Sentence 2: power consumption of 2.5E+6 220 2.0E+6 180 1.5E+6 140 1.0E+6 100 5.0E+5 60 0.0E+0 20 0.0 0.2 the control architecture dominates total power consumption.
Relationship: entailment
Domain: Hardware
Sentence 1: Transaction recovery is essential to database management systems (DBMSs) to ensure the atomicity and durability of transactions, and a number of excellent designs were pro­posed.
Sentence 2: aRIES [17] is one of the state-of-the-art approaches, beside shadow paging, and is widely adopted by conventional DBMSs such as MySQL, DB2, BigTable and HBase [9, 18].
Relationship: entailment
Domain: Hardware
Sentence 1: Constant correction [1] and variable correction [2] schemes are proposed for approximate AND-array multiplier­ s. However, since Booth multipliers are much more e.cient than AND-array multipliers, approximate Booth multipliers have been intensively investigated [3]-[8].
Sentence 2: s­tatistical linear regression analysis [3], estimation threshold calculation [4] and self-compensation approach [5] have been utilized to compensate the truncation error.
Relationship: entailment
Domain: Hardware
Sentence 1: To guarantee the timing correctness of the circuit after repair without necessarily changing our problem formulation completely, we translate the timing constraint for each to-be-repaired fault as length constraints in the .ow graph.
Sentence 2: each wire/mux in the TSV grid is associated with a length weight, and given a length constraint for each signal, the length of repair channel (the distance between the signal with the faulty TSV and its reconnected TSV) cannot violate the length constraint.
Relationship: entailment
Domain: Hardware
Sentence 1: In this context, some previous works [20][21] have coped with the analysis of benefits and drawbacks of following such an approach in the design process.
Sentence 2: this work presents an innovative extension of the approach discussed in [21] introducing the exploitation of polymorphism in the design of the ATM UTOPIA Cells Handler [3]: benefits and drawbacks of such an approach are discussed in the following.
Relationship: entailment
Domain: Hardware
Sentence 1: Here we plot two curves based on the test criteria: the solid curve uses both intra- and inter-ADC test specification for screening the ADC array, and the dotted curve uses a test criteria based on intra-ADC specifications only.
Sentence 2: for the dotted curve, we indirectly enforce the inter-ADC performance with testing it by tightening the variance requirement on individual ADCs (by a factor of 4).
Relationship: entailment
Domain: Hardware
Sentence 1: This means that although the algorithm for discretization is applied on each instance in the design, the solution cell from the library is found but is not instantiated in the design.
Sentence 2: by applying discretization, the size and shape of the phys­ical cell which matches the given load are provided to the placer, but the timing analysis is not updated to re.ect this choice.
Relationship: entailment
Domain: Hardware
Sentence 1: The Speedy DDR controller alone provides a baseline power consumption that includes major draws due to IOBs (2.322 W), PLLs (0.227 W), and leakage (0.601 W).
Sentence 2: the IOB power consumption is very high due to the large number of DDR pins and the use of digitally controlled impedance (DCI) [3]: the 105 pins of the DDR2 interface account for 2.284 W. The variable portion of the power cost is dominantly attributable to clock distribution and BRAMs.
Relationship: entailment
Domain: Hardware
Sentence 1: Regarding the memory management of embedded devices, there are two critical issues: (i) designing the most suitable on-chip memory con.guration and (ii) restructuring the appli­cation code to make better use of the available on-chip memory space.
Sentence 2: exploiting small, fast, and power-ef.cient on-chip memories is critical from both performance and power angles.
Relationship: entailment