sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: For a general circuit, the procedure described for the example cir­cuit of Figure 2 is repeated for each constraint.
Sentence 2: by addition of at most two additional variables for each constraint j, robustness 2In our case, the equality in (14) also holds because there are some points in the ellipsoid set which have (P1/2f1,u)= dP1/2f1d· dud.
Relationship: reasoning
Domain: Hardware
Sentence 1: The pull-out voltage (Vpo) is the VGS needed for the beam to reach equilibrium at a position out of contact with the drain electrode and is smaller than Vpi.
Sentence 2: oFF state spring   For NEM relays operational at CMOS-compatible voltages, the (a) NEM relay-based circuit designs should ensure that the NEM relay mechanical delay does not become the time-limiting factor in circuit operation [11].
Relationship: reasoning
Domain: Hardware
Sentence 1: Moreover, for ultra-scaled technology nodes (interconnect width < 20 nm), the RC product is no longer simply determined by the output resis­tance of the switch and capacitance of the interconnect, since the resistance of the metallic interconnects increases signi.­cantly due to dimensional scaling and size e.ects.
Sentence 2: it is of great interest to explore alternative materials for the use of future nanoscale interconnects for the CMOS technol­ogy.
Relationship: reasoning
Domain: Hardware
Sentence 1: Projection of threshold variation NRG parameters sVth (mV) Wc (nm) sL (nm) 65nm 45nm 32nm 22nm 20 0 19.9 23.8 28.1 45.8 1 21.6 27.8 39.0 71.2 2 26.3 39.2 69.4 50 0 19.9 23.8 28.1 45.8 1 23.8 33.3 51.7 98.6 2 33.3 55.2 105.2 the channel significant reduces [1].
Sentence 2: it becomes more challenging to precisely control the position of dopants and as a consequence RDF will be more significant.
Relationship: reasoning
Domain: Hardware
Sentence 1: Every time such an adjustment is done the incremental computation of the arrival times and leakage will be incorrect, since the estimated arrival times of the node fanins and their leakage is based on an un-modi.ed Vth assignment in their subtrees.
Sentence 2: every time such a re-assignment is done while merging solutions, the delay and leakage has to be computed again by doing a timing analysis for the node s subtree and adding the leakage of every gate in the node subtree.
Relationship: reasoning
Domain: Hardware
Sentence 1: It has been shown in [2, Theorem 2.1] that one can obtain the sum of them in one shot by computing the exponential of a slightly larger (n + p) × (n + p) matrix, where n is the dimension of A and p is the order of the c-functions (p = 2 in (3)).
Sentence 2: (3) can be rewritten into .
Relationship: reasoning
Domain: Hardware
Sentence 1: From a critical path [9, 22] perspective, reducing the latency for a single dynamic miss is bene.cial until a sec­ondary critical path that does not include the miss is formed.
Sentence 2: for a single instance of a problem load, the latency-reduction to execution-time reduction function is the identity (i.e., one cycle for one cycle) from zero to the point where the instruction loses criticality, and .at afterwards.
Relationship: reasoning
Domain: Hardware
Sentence 1: THE MINIMIZATION ALGORITHM IntheprevioussetionwehaveshownthateahBoolean funtionfisk­autosymmetri,fork?0.Ifk?1,fwill besimplyalledautosymmetri.Forminimizationpurposes wehaveaninreasingadvantageforinreasingk?1,as minimizingak­autosymmetrifuntionwithnvariablesand epointsreduestominimizingadiferentfuntionwithn-k variablesande/2k points.Evenfork=1wehavetoover onlyonehalfoftheoriginalpoints.
Sentence 2: fortunately,foragivenfuntionf,fndingtheassoiated linearspaeLfandomputingtheautosymmetrydegreek isaneasytask,beausetherequiredalgorithmispolynomial inthenumbernofvariablesandinthenumberofpointsof f.ByDefnition2,afuntionfislosedunderaifforany uEfthereexistsvEfsuhthatv=ufa.forall uEf,thereexistsavetorvEfsuhthatweanexpress aasa=ufv.Inotherwords,amustbesearhedwithin thevetorsoftheset{ufvIu,vEf}.Morepreisely: THEOREM5.LetfbeaBooleanfuntion.ThenLf = uEf(uff).
Relationship: reasoning
Domain: Hardware
Sentence 1: The main problem of a non truthful mechanism is that a bidder is pushed to ask for an incentive for building a photovoltaic plant, even if she would have installed the plant even without a regional contribution.
Sentence 2: together with the plan, we have to de.ne a proper set of policy instruments, the budget allocated to each of them and a corresponding truthful mechanism to distribute the money.
Relationship: reasoning
Domain: Hardware
Sentence 1: Inverter: The delay, power, and noise margins for simultaneous defects and variations in the GNRFET inverter are dominated by variations in GNR width and exacerbated by charge impurities.
Sentence 2: in the worst case when all GNRs in the array are affected, delay increases by over 2X, static power increases by over 7X, dy­namic power increases by over 2X, and the noise margin reduces to zero.
Relationship: reasoning
Domain: Hardware
Sentence 1: The address on lat­est pa is queued upon assertion of mrq war chk a2 and after the check is performed, the same PA is issued on mwq pa out with the assertion of dispatch write1 st. Interestingly, this is a real FIFO structure in the design, which IODINE was able to infer automatically; however, the designer knew that the actual depth of the FIFO as designed was 9, not 8.
Sentence 2: this invariant pointed to a functional coverage de.ciency: the test suite never exercised the FIFO full con­dition.
Relationship: reasoning
Domain: Hardware
Sentence 1: In other words, for each combination of faults we have obtained the minimum number of lamb switches to be disabled in order to make the irregular topology com­patible with the LBDR routing mechanism.
Sentence 2: dIF1-LS and DIF2-LSP show the average di.erence between the min­imum number of lamb switches and the lamb switch algo­rithm without and with rescue, respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: As shown in Figure 2, it ispossiblefor multiplefan-outbranches to hold a steady value during test and block the observation of many toggling gates.
Sentence 2: so, the fault list may give a rough estimate for some patterns butotherpatternsmayhavea signi.cantnumberof transitions that simply cannot be propagated to an observation point due to such masking.a simulation-based approach must be used.
Relationship: reasoning
Domain: Hardware
Sentence 1: More­over, in a current recommended rules, since it is di.cult for poly and active layout to re.ect all proximity rules and pro­cess variation rules, the limited information of the system­atic variability are just considered.
Sentence 2: there are three issues with the current layout optimization approach for standard cells: The design rules are applied to all devices and all lay­ers without any criticality (or sensitivity to variations) information.
Relationship: reasoning
Domain: Hardware
Sentence 1: ¬obs(v, k) = 1 Sketch of Proof: It is easy to show that the original circuit is equiv­alent to the circuit after merging v onto u by arguing that for every input assignment either f (u) = f (v) or obs(v, k) = 0, that is, either their functions are identical or no path from v to any vertex within k levels is sensitizable.
Sentence 2: no differences can propagate to any circuit output.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that Miller s heuristic uses swap gates in addition to Toffoli gates, and is hence able to do better than the optimal method (which only uses Toffoli gates) for small gate counts.
Sentence 2: if our and the optimal methodologies are extended to handle swap gates in addition to Toffoli gates, their average gate counts would be even better than Miller s heuristic.
Relationship: reasoning
Domain: Hardware
Sentence 1: Even though this cell s Karnaugh map has an equal number of 0s and 1s, the cell s output is less likely to switch for any given input switch because the 0s and 1s are grouped together and not interspersed (as in the Karnaugh map of the XOR gate).
Sentence 2: by using a di.erent number of booster and represser layers of gates, we can control the switching and hence the computational complexity of simulation.
Relationship: reasoning
Domain: Hardware
Sentence 1: According to the reschedule, as depicted in Figure 5(b), the weights of edges (x1, x2), (x3, x4) and (x6, x7) are decremented by 1, and the weights of (x1,x4), (x3, x7) and (x2, x6) are incremented by 1.
Sentence 2: we can easily .nd that the number of edge weights to update by a resched­ule of an operation is bounded by a constant (=6), independently of the size of access graph.
Relationship: reasoning
Domain: Hardware
Sentence 1: Figure 10 describes the model which reflects the arrival of an I/O intensive VM.
Sentence 2: o N (NT 1) O U (6) 1 P NP (NT 1) according to formula (6), the average length of virtual disk queue of each VM Ls1 and the average response time of each I/O request Ws1 can be calculated as formula (7) and formula (8).
Relationship: reasoning
Domain: Hardware
Sentence 1: A shoe sole­embedded DE generator will experience maximum stretch when the plantar pressure at its location is the highest, with the instant of maximum pressure depending on the location over the sole.
Sentence 2: we propose an array of 99 shoe sole­embedded DE micro-generators to harvest the mechanical en­ergy from foot-strikes, wherein DE charge timing is individ­ually controlled and will vary with location.
Relationship: reasoning
Domain: Hardware
Sentence 1: DesignhierarhyDandRentexponentsofhierarhialel­ementsinDgiveaguidaneforthemultilevellustering proedure.
Sentence 2: clusteringisdefnedasamergingproessontheexist­ingvertiestoformsmallernumberofbiggerverties.In multilevelpartitioningshemespublished,pairwisemerging hasbeenwidelyused[7,8,2].Wehaveperformedextensive experimentswithvariouslusteringmethods,andFC(First Choie)oarseningproposedin[8]turnedouttobethemost efetive.weareusingaonnetivityostandmerg­ingpoliysimilartoFCinhMetis.Eventhoughweare usingthesameideaastheoneinhMetistoformbiggerver­  Vi uv H1 and H2 are saturated!
Relationship: reasoning
Domain: Hardware
Sentence 1: As a backbone router, we consider a Cisco CRS 1 series router with eight line cards at 40 Gbps with peak power consumption of 4,834 W. Under the CCN premise, eight line cards at 40 Gbps each would generate an overall Interest packet rate of about 1 Gpck/s, while the overall access rate to the packet store would be of 0.026 Gpck/s.
Sentence 2: we need to deploy a packet store per line card and to use 10-GByte DRAM memory (Fig.
Relationship: reasoning
Domain: Hardware
Sentence 1: As is well known, the placement of guard bands in be­tween circuits to be isolated among each other and/or guard rings surrounding substrate-noise sensitive devices must be a baseline measure to achieve isolation against substrate coupling, since this approach does not neces­sitate changes of a circuit design.
Sentence 2: how large isolation can be achieved by a guard band/guard ring in a given technology should be evaluated at the initial stage of any SoC developments.
Relationship: reasoning
Domain: Hardware
Sentence 1: Let .P denote the rate at which messages arrive at the proxy P. Recall that our design makes source nodes gener­ate tra.c with exponentially distributed inter-arrival times with a rate rsource that is identical across all the source nodes.
Sentence 2: .P = nP · rsource, where nP is the num­ber of source nodes associated with the proxy P. Since the processingtimeattheproxy(inthemillisecondlevelfor a Mica node,whichismainlyduetodecryption/reencryption) is signi.cantly smaller than Tproxy, we make the simplifying assumption that this process time can be ignored.
Relationship: reasoning
Domain: Hardware
Sentence 1: As a result, the execution time does not vary across program invocations 2 as long as (i) objects are always placed in the same memory location and (ii) the same input data set is used, under which a single path in the program is exercised.
Sentence 2: forcing randomised timing behaviour on conven­tional caches, requires the assistance from a specialised com­piler and runtime system that randomises the location of objects in memory, and so the cache layout, before execution begins.
Relationship: reasoning
Domain: Hardware
Sentence 1: 1.2 Driver Application Although the goal of the our research is to investigate sys­tem architecture and design methodology concepts for elec­tronic textiles, successful systems research of this nature re­quires that one not only develop these concepts, but also val­idate them in context of real technology constraints and ap­plication requirements.
Sentence 2: we use pervasive patient monitoring and sensor-driven personalized trans-dermal drug  Figure 1: System Architecture of the Medical Jacket delivery as our driver application.
Relationship: reasoning
Domain: Hardware
Sentence 1: Weisolatedthefoldinglogicfromthedecodestage andpresentthetiminganalysisofthemodifedde­codestage(D')inTable1.Isolatingthefoldinglogic fromthecriticalpathbringsdownthemaximumde­ 2ThepicoJava-IIusesspecialtwobyteopcodesforimplementa­tionspecifcextensionstotheJVMinstructionset[4]  shift value to I-buffer Figure4:Logicalongthecriticalpathofthedecode stage.Thisfgureshowsthelogicthatcontributestothecritical path,inthedecodestage(additionallogicoccurringinparallelis notshown).
Sentence 2: layfrom12.74nsto8.68ns,thusallowingtodrivethe clockatafasterratethanitwouldhavebeenpossi­blewithfoldinglogicinthecriticalpath.Wepropose tomovetheinstructionfoldinglogicfromthedecode stagetothefllunit.Thefllunitisoutsidethecritical pathofthepipeline,anddoesnotafecttheclockasit cantakemultiplecyclestooperatewithoutafecting theperformance.Afterthefoldinglogicisremoved fromthecriticalpathofprocessorandaddedtothe fllunit,theregistercacheunit(RCU)becomesthe longeststageinthepipeline(havingadelayof9.33 ns).bymovingthefoldinglogictothefll unitwecanincreasetheclockrateofpicoJava-IIby approximately25%,whichisasignifcantimprove­ment.Increaseinclockfrequencywillhoweverresult inincreaseinprocessorpower.Embeddedapplica­tionswithpowerastheprimarydesignconstraint maywanttomakeuseofonlytheotherproposed microarchitecturalenhancements.
Relationship: reasoning
Domain: Hardware
Sentence 1: Now, Problem 1 can be restated as: Problem 2: Given a base processor, an application, and an area budget AB, .nd a set of custom instructions {Insi} such that CSi × ECi is maximized while AREA = AB.
Sentence 2: i After Phase I, a number of custom instructions {Insi} be­ comes available, where typically Ai +SA > AB.we i need to select a subset of the custom instruction nodes.
Relationship: reasoning
Domain: Hardware
Sentence 1: This is why, for some of our investigations that require the management of ATA commands (e.g., TRIM, SMART) and the control of the AHCI, we needed an in-house driver.
Sentence 2: we also developed an AHCI miniport driver, as a part of WDM (win­dows driver model, which can generate TRIM commands by .lling target addresses for the deleted contents with di.erent access patterns (random/sequential), handle SMART com­mands to check the PE cycles of the SSDs, and manually control speci.c power modes to examine background tasks.
Relationship: reasoning
Domain: Hardware
Sentence 1: This method has an inherently exponen­tial run-time with circuit size.
Sentence 2: in the pursuit of reducing the run-time, advocators of full-chip analysis have to use primitive delay models, assume that gate delay PDFs are given [3,4], neglect parameter correlations [2,3,8] and draw on inaccurate approxima­tions [7].
Relationship: reasoning
Domain: Hardware
Sentence 1: The violation of A2 in this case has been the result of the failure of the SS service to send an event invoking the Depart operation in CRS following the event Happens(ic:UI:RelKey(op3,veh2),28, R(28,28)) and the subsequent departure of veh2 from the relevant car park.
Sentence 2: cRS did not invoke the operation Available to mark veh2 as unavailable in IS and, subsequently, when the operation FindAvailable was invoked in IS to find an available vehicle at loc2, it reported veh2 as an available vehicle (see literals L11-L13 in Figure 6)5 .
Relationship: reasoning
Domain: Hardware
Sentence 1: After SPM allocation, instructions and/or data that are not stored into the SPM are accessed through the tradi­tional memory hierarchy, which can exploit the temporal and spa­tial locality at runtime to improve the average-case performance.
Sentence 2: compared to a pure cache-based architecture, the HSC can potentially combine the advantages of both caches and SPMs to achieve better performance, energy ef.ciency, and/or time pre­dictability.
Relationship: reasoning
Domain: Hardware
Sentence 1: In channel modulo 2n +1, computations are slightly more complicated as shifts and adds in the manner of 2n - 1 channel can only be performed on lower n bits of xk, while the special case of xk =2n needs to be dealt with separately.
Sentence 2: in the 2n +1 channel the fundamentals 1 and 2 have to be calculated as follows: {±2ixk,±2jxk} when xk <2n 1.
Relationship: reasoning
Domain: Hardware
Sentence 1: There­fore, fT ×f increments in each iteration till k×k.
Sentence 2: figure 1: Basic Block Diagram for OMP Recon­struction Algorithm Table 1: PSNR and Sparsity Analysis numbers for variety of Image Sizes with OMP Reconstruction Al­gorithm Image Sizes Sparsity k PSNR (dB) 256×256 8 27.22 256×256 32 34.70 256×256 48 34.89 384×384 8 21.24 384×384 32 22.88 384×384 48 22.91 512×512 8 21.19 512×512 32 25.65 512×512 48 25.71 768×768 32 22.55 768×768 90 22.95 complexity of Least Square algorithm is dependent on the size of sparsity.
Relationship: reasoning
Domain: Hardware
Sentence 1: An in-depth analysis of the effect of SDM on the NoC latency and throughput in [8] shows that splitting the links into two sub-links increases the throughput considerably (as the path diversity of SDM reduces the head of line blocking) with some negative effect on the average message latency (as the number of flits of a packet is increased).
Sentence 2: sDM is a suitable bandwidth multiplexing scheme for our NoC, since in addition to throughput, by selectively employing the sub-networks, we can also improve the power and latency of the NoC.
Relationship: reasoning
Domain: Hardware
Sentence 1: We .nd that A-Bottom and B-Bottom can handle 8 requests at a time; A-Top and B-Top can only handle 1 read; C-Bottom and D-Bottom can handle 8 combined requests; C-Top and D-Top can handle 1 combined request.
Sentence 2: data placement in banks has a signi.cant impact on request parallelism.
Relationship: reasoning
Domain: Hardware
Sentence 1: Nevertheless, even the t-dimension search space may be too big for many practical systems and this approach still needs to per­form the simulations on the entire DSP systems in order to obtain (j1) (j2) (jt) the function fe(d, A,A, ··· ,A).
Sentence 2: 1 2 t we propose to further approximate the above approach in order to further reduce the complexity.
Relationship: reasoning
Domain: Hardware
Sentence 1: In Figure 10, each line in the graph keeps the duty-cycle con­stant,i.e.,thefraction of the time each coreis experiencing afault.
Sentence 2: 100µs faults with a duty cycle of 1% are occuring, on aver­age, every 10ms, and 1sec faults are occurring, on average every 100sec.
Relationship: reasoning
Domain: Hardware
Sentence 1: 1 A = MIN (1) QT In the basic structure, the total conductance value, will be given by the equation (2) and the gain value of the open loop, is described by the equation (3), which analyzes the circuit, considering all the system components.
Sentence 2: g = G + G (2) TL g 1 m MIN A == (3) MINQ G · Q T TT the minimum transconductance final value to attend the condition, will be given by the equation (4), where it is certified that the load interferes directly in the oscillation condition, making that the active element is about require answering its application needs.
Relationship: reasoning
Domain: Hardware
Sentence 1: Typically, main contributors of this uncertainty include missing technology characterization data (e.g., fail­ure models and parameter variations), non-formalized environmental stress conditions and functional loads, inconsistent design data .ows, as well as limited robustness awareness of EDA tools.
Sentence 2: the robustness of components must be consid­ered as a design target in order to bene.t from modern automotive semiconductor technologies.
Relationship: reasoning
Domain: Hardware
Sentence 1: Hence, rall = So · min ri,j .ri,j > 0 (3) N ri,j is the rate of each PE, which is in.uenced by partition (yi,j), parallelization (xi), VFI assignment (cfi,j) and block latency (Ti,j).
Sentence 2: we have: ri,j = xj · yi,j · cfi,j /Ti,j (4) where cfi,j selects a pair of voltage and frequency values from {(Vk,CFk)}, i.e., K cfi,j = cj,k · CFk (5) k=1 1 This is a multiple objective optimization using lexicographic method.
Relationship: reasoning
Domain: Hardware
Sentence 1: 9, it can be seen that the probability that the MUX input wt is selected as its output is Pt, because this probability is the same as the probability that the current state of the FSM is St.
Sentence 2: we can obtain PY as PY = P (Y = 1) M N -1 = P (Y = 1 | wt is selected) · P (wt is selected) t=0 M N -1 M N -1 = P (wt = 1) · P (wt is selected) = Pwt · Pt.
Relationship: reasoning
Domain: Hardware
Sentence 1: Even thought (Lt,Tt) depend on their downstream ran­dom variations in a complicated way, the way we compute (Lt,Tt) is via the recursive equations according to either (1) and (2), or (3) and (4), or (5) and (6).
Sentence 2: we develop an e.cient algorithm to compute the j.p.d.f.
Relationship: reasoning
Domain: Hardware
Sentence 1: INTRODUCTION 1.1 Motivation and Previous Work Interconnects, unliketransistors,donotperform anylogicalfunc­tion and merely transfer information from one location to another.
Sentence 2: delays and power dissipation due to interconnects are Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not madeordistributedforpro.t or commercial advantage and that copies bearthisnoticeand thefull citation onthe .rstpage.Tocopy otherwise,to republish, topost on servers or to redistribute tolists, requiresprior speci.c permissionand/or afee.
Relationship: reasoning
Domain: Hardware
Sentence 1: CONTACT LAYOUT OPTIMIZATION From Figure 3, even though the sensitivity of contact vari­ation could be di.erent from input process condition, this tells us that the optimal position of NMOS and PMOS con­tact holes might be di.erent for the best printability and device performance in standard cell.
Sentence 2: we should .nd the optimal S/D contact layout in design time by taking the process variability due to lithography and the performance dependency due to stress relaxation into consideration.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, the DFT meth­ods in [9] and [10] assumed that a controller and a datapath are isolated each other and signal lines in between them are directly controllable and observable from the outside of circuits.
Sentence 2: extra multiplexers are added to the signal lines in between a con­troller and a datapath, and an extra test controller is also embedded to provide the test plans for the datapath.
Relationship: reasoning
Domain: Hardware
Sentence 1: In comparison with the discrete-register based architecture, DRFM o.ers a higher degree of opportunity of reducing the cost of global (inter­island) connections by con.ning as many the computations to the inside of the islands as possible.
Sentence 2: for DRFM architecture, two important problems to be solved e.ectively in high-level synthesis are: (problem 1) schedul­ing and resource binding for minimizing inter-island connec­tions, and (problem 2) data transfer (i.e., communication) scheduling through the inter-island connections for minimiz­ing the access con.icts among the data transfers.
Relationship: reasoning
Domain: Hardware
Sentence 1: The z-direction (perpendicular to Si substrate) effective thermal conductivity of combined ith ILD layer and wire layer (Keff,i,z) can be derived from its unit area thermal resistance: R =(t + t ) K .
Sentence 2: (14) , i wire, i i ILD eff ,,iz t + tt + t iILD,, iILD , i wire , i wire .
Relationship: reasoning