sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: A Parallel VLSI Architecture for Markov Chain Monte Carlo based MIMO Detection Uwe Deidersen, Dominik Auras, Gerd Ascheid Institute for Communication Technologies and Embedded Systems RWTH Aachen University, 52056 Aachen, Germany {deidersen,auras,ascheid}@ice.rwth-aachen.de ABSTRACT Multiple-input multiple-output (MIMO) wireless transmis­sion together with iterative decoding at the receiver is a key technique to achieve high spectral e.ciency.
Sentence 2: par­ticularly the required soft-input soft-output (SISO) MIMO detector entails a very high complexity, which motivates the investigation of suboptimal detectors with reduced complex­ity.
Relationship: contrasting
Domain: Hardware
Sentence 1: Therefore, the efficiency of these techniques is dependent on the application program characteristics and the architecture, such as how frequent the locking attempts occur in the application (i.e., how many CSes exist in the program) or whether there are lots of processors making use of locks.
Sentence 2: there are some queue based software solutions like array based queuing locks [7], MCS locks [9] and LH and M locks [10].
Relationship: contrasting
Domain: Hardware
Sentence 1: Figure 7: The impedance characteristics: (a) the nominal impedance values, and (b) variation in the impedance observed by the core due to variation in the VR parameters (impedance response of the off-chip VRs are overlapped on top of each other due to negligible effect of variation TABLE V Comparison of the nominal value and variability of the output parameters and impact on the core performance for off­chip VR and IVR under variation Mean Value VDROOP (mV) TS,LOAD (nS) OVREF (mV) TS,SET (nS) FCORE (MHz) Off-Chip VR 171.3 3056.2 231.2 4347.7 49.2 IVR 96.4 584.3 46.1 181.8 103.7 3s/µ (%) VDROOP TS,LOAD OVREF TS,SET FCORE Off-Chip VR 0.78 14.07 26.01 29.55 2.46 IVR 16.17 29.13 135.21 30.57 9.24 We observe that at the higher power corner the ESRL is the most dominant source of variation in the total power (2.07% variability).
Sentence 2: it is important to note that variability in the total power is much smaller than the variation in the power loss.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4.1 Quantitative Performance Benchmarking 4.1.1 Effect of Host Operating Systems VMware VM s on Red Hat Linux 7.1 host machine performed better than on Windows host in terms of installation time, which would save as much as 40 to 50% of time (Table 5 and Figure 3).
Sentence 2: there was no significant difference on CPU performance between Linux and Windows hosts using VMware, although Linux performed slightly better than Windows (Figure 4).
Relationship: contrasting
Domain: Hardware
Sentence 1: [4], noting that the off-diagonal entries of L-1 diminish much faster than those in L, proposed the sparsi.ca­tion of L-1 by retaining only signi.cant terms; the resulting L -1 can reduce the number of coupling terms and speed up simulation.
Sentence 2: l-1 needs to be computed .rst, which is prohibitively expensive.
Relationship: contrasting
Domain: Hardware
Sentence 1: A major problem of the high-level WCET analysis is that the maximal number of computation steps of a statement (like a loop) may heav­ily depend on the input data, but some of the approaches do simply compute the WCET bounds for the substatements and add these afterwards.
Sentence 2: simply adding the max­imal bounds for all substatements clearly yields highly pes­simistic bounds.
Relationship: contrasting
Domain: Hardware
Sentence 1: In 2006, the first MRAM based on Field Induced Magnetic Switching (FIMS) was commercialized [10] and it addresses particularly some specific niche markets such as space, security and aeronautics thanks to its radiation hardness.
Sentence 2: the first MRAM is greatly limited by its FIMS approach, which requires two high currents (~10mA) [5] and this leads to low memory density and high switching power.
Relationship: contrasting
Domain: Hardware
Sentence 1: The 2T-1R dual source-line technique was shown to be very e.ective in mitigating the stress condition for the tunneling barrier of the MTJ while the reduction in write power was not signi.cant for RC bit-cells, if it is designed to incur no bit-cell area overhead.
Sentence 2: 31% of write power reduction was achieved for SC bit-cells.
Relationship: contrasting
Domain: Hardware
Sentence 1: The precision required varies for different applications: those involving measurement of time of .ight or time difference of arrivals often require precisions on the order of microseconds [33], while for long-term recording of event times and for many system mechanisms, millisec­ond or second resolution is suf.cient.
Sentence 2: despite these variations, some form of time synchronization is one of the most common and critical requirements in embedded sens­ing.
Relationship: contrasting
Domain: Hardware
Sentence 1: The latter seemed at .rst exciting as it could be the start­ing point for long-lasting partnerships with state-of-the-art operating system research for parallel hardware, such as Bar­rel.sh [18], Helios [17] or fos [23, 24].
Sentence 2: there is an immense practical obstacle to this latter strategy: not only must we port the new operating system to our plat­form; the corresponding application-level implementation work, required to make the C library and application pro­grams compatible with the new system, must be compounded with the portability requirement that the code should also run on commodity hardware.
Relationship: contrasting
Domain: Hardware
Sentence 1: To this end, we point out that e.cient implementations of negotia­tion-based routing and A*-search require a priority queue, which academic researchers and graduate students may not be willing or able to implement e.ciently.
Sentence 2: a highly optimized, reusable, heap-based implementation is now avail­able with all C++ compilers as a part of the Standard Tem­plate Library (STL).
Relationship: contrasting
Domain: Hardware
Sentence 1: On one hand, simple approximations of nodal energy usage derived from estimates of node duty cycle and communication rates [4] do not capture the low­ level system power pro.le.
Sentence 2: simulators that extrapolate system macrobenchmarks the large-scale, long-term, and system-wide behavior of a sensor network from models based on microbenchmarks of a single node cannot assure the accuracy of their generalizations [14].
Relationship: contrasting
Domain: Hardware
Sentence 1: For the non-adaptive encoder, increase in yield comes at signif­icant PSNR penalty because the encoder has to ensure a low enough complex con.guration (for all die) that satis.es the required yield and hence a staircase PSNR waveform is observed.
Sentence 2: adaptation allows for a graceful degra­dation in PSNR when improving yield, as operating con.g­urations can change on a die-by-die basis.
Relationship: contrasting
Domain: Hardware
Sentence 1: Here, the variation is de.ned as the following equation, and it corresponds to circuit controllability.
Sentence 2: max( f#1, ..., f#6) - min( f#1, ..., f#6) variation = × 100 f#1 f#n is oscillation frequency of line #n. when the body-bias voltage becomes larger than 0.5V, the measured oscillation frequency varies depending on the body-biasing position.
Relationship: contrasting
Domain: Hardware
Sentence 1: Owing to these strong points, OFDM has been adopted for wireless local area networks (WLANs) such as IEEE 802.11a (IEEE 802.11g) [1][2], high performance LAN type 2 (HIPERLAN/2) [3].
Sentence 2: oFDM systems are extremely sensitive to timing and frequency synchronization [4].
Relationship: contrasting
Domain: Hardware
Sentence 1: following expression: nstalled i tSLA < (tDM A + texe) * npage , (3) i=0 where nstalled is the number of stalled I/O requests target­i ing the same FIMM and nis the number of pages asso­ page ciated with the ith stalled request.
Sentence 2: withthe queue-examination strategy, Triple-A counts the numberof stalled requests for each FIMM when the queue has nomore room for accepting incoming I/O requests.
Relationship: contrasting
Domain: Hardware
Sentence 1: ibm01 dragon 0.58 0.86 0 1803 TOOP 0.63 0.90 0 547 3.3x 10% ibm07 dragon 3.55 4.55 0 5002 T OOP 3.96 4.79 0 1998 2.5x 12% ibm09 dragon 3.21 3.77 0 8736 TOOP 3.54 4.05 0 3415 2.6x 7% ibm11 dragon 4.77 5.50 0 9953 T OOP 5.25 6.33 0 4380 2.3x 10%  3.2 Interconnection-Aware Blocking Scheme The pre-fixed blocking scheme can effectively reduce th e size of the solution space for each cluster placement problem.
Sentence 2: it blindly posts artificial regulations on clusters to restrict where they can be moved.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, although measured power is similar for gcc s regions around 88s, 110s, 140s, 210s and 230s, the similarity matrix reveals that the 88s, 210s and 230s regions are much more similar than the other two re­gions, which are also shown to be mutually dissimilar.
Sentence 2: other applications we have studied, such as gzip, show more regular patterns with several similar phases.
Relationship: contrasting
Domain: Hardware
Sentence 1: 1(b), we could decompose the given layout into two masks, and if DPT con.icts occur, we could perform LM on these two masks separately according to the DPT design rules.
Sentence 2: this sce­nario might over-enlarge the layout area and induce redundant stitches, resulting in a poor-quality solution, as the resulting layout illustrated in Fig.
Relationship: contrasting
Domain: Hardware
Sentence 1: Moreover, a Moe­bius circuit has error detection and error gate search features as well.
Sentence 2: though CLK tree synthesis which is inevitable for a DCVSL and CMOS circuits are not required in a Moebius circuit, the transistor count and energy per operation in the Moebius are respectively about 12 times and 10 times larger than Non-pipeline  = = = = = = = = = = Figure 6: Simulation comparison with Moebius and static CMOS static CMOS.
Relationship: contrasting
Domain: Hardware
Sentence 1: The sequence pair is A1 B1 B2 ) C1 C2 A2 , B1 A1 C1 B2 A2 C2 From this sequence pair, we can conclude that bus u should be below v, v should be below w,and w should be below u.
Sentence 2: this is impossible in a BDF solution.
Relationship: contrasting
Domain: Hardware
Sentence 1: = 0.750. response time distribution 0.04 0.035 0.03 0.025 0.02 5 10 15 20 25 30 response time distribution 0.06 0.05 0.04 0.03 0.02 0.01 5 10 15 20 25 30  response time distribution 0.04 0.03 0.02 0.01 5 10 15 20 25 30 Note that, in general, results are sensitive to the complete distributions of the input random variables.
Sentence 2: this is especially noticeable for the response time distribution itself, but not for the first moments, as we can see from Table II.
Relationship: contrasting
Domain: Hardware
Sentence 1: Because the S-Boxes and the Linear Transformation form the bulk of the round function, it is fair to estimate the decryption imple- mentation as requiring more space within the FPGA than the amount available for Architectures 2, 3, and 4.
Sentence 2: an interesting alternative which explores the specific capa- bilities of FPGAs is to reconfigure the target device with a decryption architecture on-the-fly.
Relationship: contrasting
Domain: Hardware
Sentence 1: This test involves sequential read/write I/O, espe­cially for the scan step.
Sentence 2: by having to actually consume step LOCAL BASE16 copy 0.157 (0.270) 0.163 (0.160) uncompress 43.932 (3.560) 45.337 (3.370) scan 81.524 (0.640) 83.784 (2.210) compress 496.400 (1.160) 501.013 (2.640)  Table 4: Filesystem test results for trace-.le (a single large .le, that is processed in a sequential scan).
Relationship: contrasting
Domain: Hardware
Sentence 1: Recent approaches using a gate-array style fabric and top metal-level configuration will also help provide an intermediate point on the NRE-flexibility continuum.
Sentence 2: neither of these solutions address the design NRE and time-to-market needs for today s SoC s which can have over 100 million transistors enough to theoretically place the logic of over one thousand 32bit RISC processors on a single die.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is also a reason why the latest NVIDIA Fermi architecture (e.g., GTX 480 GPUs) provides larger shared memory and an L1 cache.
Sentence 2: as shown in Section 7, the high number of SPs in an SM in GTX480 (and even higher number of SPs in GTX680) makes TLP more important to hide instruction execution latencies.
Relationship: contrasting
Domain: Hardware
Sentence 1: If coherent detection is utilized at the receiver, the residual frequency shift can af­fect the detection process unless it is compensated through dedicated Doppler tracking [6].
Sentence 2: if di.erential de­tection is used, the residual frequency shift does not a.ect the detection process because it is similar between adjacent subcarriers, thus satisfying the assumption that the chan­nel response does not vary drastically between consecutive subcarriers.
Relationship: contrasting
Domain: Hardware
Sentence 1: A variety of techniques exist to deal with such faults, from special radiation-hardened circuit designs (e.g., [6]) to localized error detection and correction (e.g., [1]) to architectural redundancy (e.g., [26], [23], [20], [2], [16], [18]).
Sentence 2: all of these approaches introduce a significant penalty in performance, power, die size, and design time.
Relationship: contrasting
Domain: Hardware
Sentence 1: We show that when thermal stress is severe, an aggressive DTM response based on voltage scal­ing is likely best, because this obtains approximately cubic reductions in power density relative to the reduction in fre­quency.
Sentence 2: when thermal stress is mild and only a mild DTM response is needed, we show that an archi­tectural response that exploits instruction-level parallelism (ILP) has less overhead than DVS possibly even no over­head if ILP is suf.cient.
Relationship: contrasting
Domain: Hardware
Sentence 1: For the multi-scenario bu.er insertion problem in multi­core processor designs, a naive approach is to run Ginneken-Lillis algorithm separately on each instance and then pick one of them, which is most critical (e.g., among the best solutions of all instances in max-slack problem, a critical so­lution is the one with the smallest slack) and apply it to all instances.
Sentence 2: the algorithm run on one instance may prune a partial solution which is preferred in another instance.
Relationship: contrasting
Domain: Hardware
Sentence 1: In the first category, circuitry is added to mask selected unload val­ues so that X s do not reach the MISR [7], [11], [12], [13].
Sentence 2: if the number of X s is too large or the distribution is unfavorable, masking may have a high area overhead or it may not be selective enough; therefore, non-X values would also be masked out, resulting in a potential loss of coverage or increased number of patterns.
Relationship: contrasting
Domain: Hardware
Sentence 1: When the present accumulation factor is set to 1.1 for TDVPR, the routability result of TDVPR is improved with TDVPR routing 4 additional instances than SpiralRoute-MCF.
Sentence 2: with the exception of des/5 the additional instances do not meet the timing target, and there are 19 problem instances when only SpiralRoute-MCF routed a so­lution meeting the timing target.
Relationship: contrasting
Domain: Hardware
Sentence 1: Note that only the LSB of the b-bit digits Xn and Yn can be equal to one in order to satisfy 0 = X, Y < 2 * M. For digit Tn the two LSBs can be equal to one, while the rest of the bits are zero, because T< 4 * M is always ensured.
Sentence 2: in the implementations that are discussed in Sect.
Relationship: contrasting
Domain: Hardware
Sentence 1: Note that even if b is executed relatively frequently, but such exe­cutions of b are dispersed in the trace T rather than clustered, then self-concomitance s(b,T ) will still be low.
Sentence 2: if for certain input a particular loop is frequently executed, then the trace self-concomitance s(a,T ) of each basic block a from this loop will be large.
Relationship: contrasting
Domain: Hardware
Sentence 1: Whenever a con.ict occurs during the search, the con.ict is analyzed to .nd the responsible decisions and a con.ict clause is subsequently added to the CNF formula, followed by a backtrack in the search.
Sentence 2: because the ad­ditional XOR clauses added to the CNF formula are only used for comparing the given pair, all con.ict clauses added to the CNF formula are valid only for that particular node comparison process and should be removed, along with the XOR clauses, before proceeding to the next candidate pair.
Relationship: contrasting
Domain: Hardware
Sentence 1: A Reuse-Aware Prefetching Scheme for Scratchpad Memory Jason Cong, Hui Huang, Chunyue Liu and Yi Zou Computer Science Department University of California, Los Angeles Los Angeles, CA 90095, USA {cong, huihuang, liucy, zouyi}@cs.ucla.edu ABSTRACT Scratchpad memory (SPM) has been utilized as prefetch buffer in embedded systems and parallel architectures to hide memory ac­cess latency.
Sentence 2: the impact of reuse pattern on SPM prefetch­ing has not been fully investigated.
Relationship: contrasting
Domain: Hardware
Sentence 1: For instance, tOP for a read and a write command is given by tRD and tWR, respectively, which correspond to the period of data transfer during the respective read and write operations.
Sentence 2: tOP equates to tRAS, tRP and tRFC for ACT, PRE and REF, commands respectively, which are JEDEC-speci.ed minimum timing constraints to be satis.ed for these operations to .nish [20].
Relationship: contrasting
Domain: Hardware
Sentence 1: Deadlock-free routing is crucial because it guarantees correct functionality under worst-case scenarios.
Sentence 2: some routes calculated from the CDG are non­minimal which increases the average hop count and hurts  Name dodec mesh-dim mesh-romm torus/ring-dim d3 d8 d4 d5 Routing example adaptive deadlock-free routing dimensional order routing 50 ROMM [16] dimensional order routing 45 torus/ring-adp minimal adaptive routing [17] Table III: Topologies &#38; routing algorithms for comparison network performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the input is high (tied to VDD), NEMS1 is OFF since the beam and both gatesare at the same voltage level (there is no electrostatic force to bend the beam).
Sentence 2: the beam of NEMS2 is tied to GND and the input isconnected to VDD, which creates sufficient electrostatic attraction to deflect the beam and turn the device ON, thus connecting OUT to GND.
Relationship: contrasting
Domain: Hardware
Sentence 1: While the timing closure problem has been extensively studied in academia [5][6][7], and several commercial flows have been proposed by the EDA industry, of equal importance is the impact of wiring on de­fining the block or chip size, in particular for logic synthesis, which traditionally has attempted to minimize cell area in order to mini­mize the size of a block or IC, without considering the interconnect area.
Sentence 2: since the DSM wirelength trends do not scale with feature sizes, cell area minimization can no longer guarantee over­all block or die area minimization.
Relationship: contrasting
Domain: Hardware
Sentence 1: The tool uses carefully crafted and tuned cost functions to achieve high-quality timing and placement solutions in reasonable time; these make it the current champion among academic tools for placement of MCNC and other public-domain benchmark circuits.
Sentence 2: published versions of VPR do not handle carry-chains or multiple delay constraints, and apply primarily to non-hierarchical, island­style architectures.
Relationship: contrasting
Domain: Hardware
Sentence 1: Note that once the writeEnable signal is activated by the FIFO con­troller, the write wordline corresponding to the current .it can get activated only after propagation delay through the write counter and the delay through the decoder (illustrated by Wordline Enable Path in Figure 4.3).
Sentence 2: writeDataFlit propagates only on metal wire and would always gate the wordline correctly.
Relationship: contrasting
Domain: Hardware
Sentence 1: The automaton describ­ing the AHB read transfers is smaller, as most transi­tions are contingent on the behaviour of the slave which is less varied than that of the master as it has fewer sig­nals.
Sentence 2: aMBA Peripheral Bus(APB) shown in Fig­ure 4 is extremely small with only three states as it has only two control signals and had no pipelined operation.
Relationship: contrasting
Domain: Hardware
Sentence 1: We conclude that it is quite challenging to predict up-front when sharing will provide an area bene.t, as it depends on the speci.c technology mapping and packing decisions made by Quartus, which appear to depend on the speci.c pattern implemented.
Sentence 2: we observe two general trends: 1) Sharing is more likely to be bene.cial for composite oper­ators that consume signi.cant area, particularly when the MUXes that facilitate sharing can be rolled into the same LUTs as those implementing portions of the operator func­tionality.
Relationship: contrasting
Domain: Hardware
Sentence 1: This is in direct contrast to super-threshold design where, without regard for performance, it is always possible to reduce energy requirements by lowering voltage.
Sentence 2: subthreshold voltage levels exist where reducing volt- Phenomena Sample Rate (Hz) Atmospheric temperature 0.017 -1 Barometric pressure 0.017 -1 Body temperature 0.1 -1 Natural seismic vibration 0.2 -100 Blood pressure 50 -100 Engine temperature/pressure 100 -150 ECG (electro-cardiogram) 100 -250 Figure 1 illustrates the performance of these benchmarks on a variety of commercial microcontrollers (the .gure is from [13]).
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, the veri.cation of transmissivity and re.ectivity is a very time consuming task in case of the cascade of microresonators with a very large value of N (for example, N = 20 [14]).
Sentence 2: this can be veri.ed in a very short time using the infrastructure developed in this research because all the results are veri.ed under the universal quanti.cation of system parameters.
Relationship: contrasting
Domain: Hardware
Sentence 1: Increasing the size of this window would unfairly in.ate the coverage provided by Shoestring since accommodating large checkpointing intervals requires substantial hardware/software overhead.
Sentence 2: if large checkpointing in­tervals eventually .nd their way into mainstream processors, the heuristics used by Shoestring can be easily tuned to exploit this additional support and provide even greater coverage.
Relationship: contrasting
Domain: Hardware
Sentence 1: The families of recurrences presented in this section en­sure that we meet some of our requirements: performance (bymaking sure that the criticalpathisFF-LUT-FF), max­imummemorybandwidthutilisation, andlogice.ciency(as each active bit uses exactly one LUT).
Sentence 2: they only provide necessary conditions for maximum period, quality, andpolynomialdensity,theydon t guaranteeit.
Relationship: contrasting
Domain: Hardware
Sentence 1: small number of misses eliminated per pre-execution in ms t and In summary, the experimental results in this section demon- raytrace explains why they are more affected by the thread- strate that the additional hardware support for our pre-execution spawn latency.
Sentence 2: the other four applications (except scheme can be very minimal: Register copying can be done in compress) eliminate an average of at least 20 misses and can software and a scratchpad may not be necessary.
Relationship: contrasting
Domain: Hardware
Sentence 1: We pick simulation windows using the methodology described in Section 3.2, but we extend their duration to 1 billion instruc­tions.
Sentence 2: comparisons against off-line learning (e.g., Sec­tion 4.4.1) use the smaller simulation windows of 100 million in­structions due to the complexity of simulating OFF-LINE.
Relationship: contrasting