sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: The advantage of this gate 978-3-9815370-2-4/DATE14/ c @2014 EDAA Kae Nemoto2 Ilia Polian1 2National Institute of Informatics 2-1-2 Hitotsubashi, Chiyoda-ku Tokyo, Japan {devitt|nemoto}@nii.ac.jp set is that it can be seamlessly integrated into very advanced QECC schemes, allowing for scalable, large-scale information processing [7], [9].
Sentence 2: as quantum teleportation is inher­ently probabilistic the direction of qubit rotations is random.
Relationship: contrasting
Domain: Hardware
Sentence 1: We express the function Db(x, y)as Db(x, y)=Px(b, v)Py(b, v), (5) v.V where Px and Py are the overlap functions of bin b and block v along the x and y directions.
Sentence 2: the overlap functions Px and Py are neither smooth nor di.erentiable.
Relationship: contrasting
Domain: Hardware
Sentence 1: When the slice count increases from 16 to 32 the percentage of the throughput attributable to reads is reduced because the increased demand from the clients write requests pushes the compaction load lower.
Sentence 2: the Huawei Gen3 exploits channel parallelism for individual 8 MB-patch accesses so it can achieve much higher throughout when the slice count is small, but its throughput does not increase with increasing slice count.
Relationship: contrasting
Domain: Hardware
Sentence 1: In that work, there is a very small variation in the transient width between four technology nodes (250, 180, 130 and 100 nm) for low energy particles.
Sentence 2: for particles with high LET, for instance 70 MeV-cm2/mg, the widths of transients between the 250 nm (948 ps) and 100 nm technologies (694 ps) decreases 27%, while between the 180 and 130 nm technology nodes, the transient width for this level of energy increases from 772 ps to 900 ps, i.e., 17%.
Relationship: contrasting
Domain: Hardware
Sentence 1: Applications of communica­tion frameworks for HTH activation and HTH-based covert channels [13], or for capturing the information leakage [17] caused by HTH have also been described.
Sentence 2: these works are di.erent from ours in the sense that all of them assumes that the circuit is Trojan infected at the point of its deployment, while in the proposed work the Trojan is inserted run-time through Ethernet communication inter­face.
Relationship: contrasting
Domain: Hardware
Sentence 1: It is further divided into .xed-sized physical pages (e.g., 4KB pages) and each physical page is composed of a .xed number of physi­cal lines, where the size of a physical line is the same as the cache line size (e.g., 64B) of the adopted CPU; this is because a cache line is the basic unit of CPU to access memory.
Sentence 2: the linear logical (address) space of PCM is partitioned into the main-memory space and the storage space.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this case, we have a simple bound n on the critical pulse width: T ()I =CV dd /I (19) crit n n This expression states that when the noise amplitude is sufficiently high, the SRAM cell will undergo a state-flip once the total charge deposited by the transient noise is equal to the charge stored on the node, CVdd .
Sentence 2: if the noise amplitude is comparable to those of the driving currents, the critical pulse width given by (18) is greater than that given by (19), as confirmed by the experiments in the next section.
Relationship: contrasting
Domain: Hardware
Sentence 1: 3.2.2 Method 2: Estimation of local routes based on pin density Based on our experiments, Method 1 is reasonably fast and very effective in modeling congestion due to local routes.
Sentence 2: calcu­lating Steiner trees for all the pins of each net in every g-cell can be­come a productivity bottleneck when congestion analysis is invoked hundreds of times (for example, during physical synthesis).
Relationship: contrasting
Domain: Hardware
Sentence 1: Figure 4: Architectural view of our SET Tolerant Design DFF modi.ed  Figure 5: Gate Level View of our SET Tolerant Design There was a 66mV reduction in the noise margin of an inverter in the pro­tection logic due to our modi.ed sizing approach.
Sentence 2: since thisskewed sizing is only used in the secondary path, and all the nodes inthe protection circuitry are SET immune based on the discussion of Sec­tion 3.2, this is not a problem.
Relationship: contrasting
Domain: Hardware
Sentence 1: COMPRESSION TECHNIQUES: APPLI-CABILITY &#38; IMPLEMENTATION COST Datacompressionhasbeenextensivelystudiedinthepast.
Sentence 2: numerouscompressionalgorithmshavebeenproposedto reducethesizeofdatatobestoredortransmittedovera network.Thee.ectivenessofacompressiontechniqueis characterizedbytheachievedcompressionratio,thatis,the ratioofthesizeofthecompresseddatatothesizeoftheorig­inaldata.dependingontheapplication,metrics suchasprocessingrate,implementationcost,andadaptabil­itymaybecomecriticalperformanceissues.Inthissection, wewilldiscusscompressiontechniquesandtherequirements tobemetforcompressingFPGAcon.gurationsinFPGA­basedembeddedsystems.
Relationship: contrasting
Domain: Hardware
Sentence 1: Structural relationships are related to the standard no­tion of type polymorphism in languages with more advanced type systems than C; commonly (but not exclusively) .elds in a structural relationship would have related polymorphic types in statically typed functional or object-oriented lan­guages.
Sentence 2: solving our problem requires more than identifying polymorphic .elds, as we must also understand the actual contents of those .elds, which means .nding and correlating the .eld assignments.
Relationship: contrasting
Domain: Hardware
Sentence 1: It is observed that the total leakage current of a 16KB memory cell array is exponentially dependent on Tox and Vth.
Sentence 2: hence, we approximate the total leakage power as follows: a 1* Vth a 2 * T o x P to ta l (V th , To x ) = A0 + A1 * e + A 2 * e the delay of the array is shown to be linear with Tox and  word address decoders, with address and data buffers consuming the least amount of leakage.
Relationship: contrasting
Domain: Hardware
Sentence 1: We .nd that, if a benchmark is not very bursty, then the STT­RAM-4TSB-SS scheme, in spite of using only 4 TSBs for send­ing requests from the core to cache layer, on an average improves performance.
Sentence 2: if an application is bursty, STT-RAM-4TSB-SS scheme is not able to manage the requests to busy and idle banks well enough due to the lack of congestion estimation among parent and child nodes in this scheme.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the vi-glitch-peak is less than the 50% of the .nal value, the 50% delay of the signal can be determined with the RC-like main lobe by using (15).
Sentence 2: if it is not the case, the signal de­lay due to the glitch has to be taken into account since the vi-glitch-peak may exceed the 50% of the .nal value.
Relationship: contrasting
Domain: Hardware
Sentence 1: Only two equality constraints -(n+1) 0 p+1 0 (i.e., .s = .s and .s = .s for n incremented, and -n 1 p+2 1 .s = .s and .s = .s for p incremented) need to be added per time-frame expansion.
Sentence 2: if we were to append a new time-frame at the end of the array, we would have to add (n+p +2) looping constraints related to the new time-frame added.
Relationship: contrasting
Domain: Hardware
Sentence 1: In one method, the workload chunk size al­lotted to each thread is .xed.
Sentence 2: this may not be      Work Power Processor Mapping Code Partitioning Partitioning 32 CMOS cores Homogeneous: CMOS  Equal Equal CMOS-Base      32 TFET cores Homogeneous: TFET Equal Equal TFET-Base Homogeneous: CMOS or TFET Equal Equal Hetero-Manual-Best 8 CMOS and 24 TFET cores  Heterogeneous: CMOS and TFET Dynamic Dynamic Hetero-Auto   Table 2: Evaluated multicore con.gurations.
Relationship: contrasting
Domain: Hardware
Sentence 1: The replication or migration of shared data blocks at arbitrary locations on chip require the use of directory- or broadcast-based mechanisms for lookup and coher­ence enforcement, as each block is likely to have different place­ment requirements.
Sentence 2: to date, there have been only few promising directions to provide fast lookup [31], while the area and latency overheads of directory-based schemes (Section 2.2) dis­courage their use, and broadcast-based mechanisms do not scale due to the bandwidth and power overheads of probing multiple cache slices per access.
Relationship: contrasting
Domain: Hardware
Sentence 1: This technique, called power gating (PG), is a coarse-grained application of multi-threshold CMOS (MTCMOS) and widely used for reducing sub-threshold leakage current [8].
Sentence 2: in a header-based PG design, the PMOS sleep transistors suffer continuous NBTI stress during active mode (sleep = 0 ) and age very rapidly.
Relationship: contrasting
Domain: Hardware
Sentence 1: For instance, consider the impact the size of subroutine foo() has on spawn-target pair selection.
Sentence 2: if foo(),together with blocks b, d, e,and x .t inside the instruction cache, then initiating a prefetch of block x starting at block a is e.ective, because the loop will likely iterate several times before the main thread branches from b to access x.if foo() together with of its callees (if any) require more instruction storage than the cache capacity, then there is no point in spawning a prefetch thread to target x from any block.
Relationship: contrasting
Domain: Hardware
Sentence 1: This means, that it is not possible to obtain the elapsed time e, which is required by the RecDEVS transition functions dext(s, x, e) and dcon(s, x, e) as stated in Equation 2.
Sentence 2: there is a wide range of appli­cations where the elapsed time is either not required, or it is only used to preserve the timeout of the originating state.
Relationship: contrasting
Domain: Hardware
Sentence 1: A whole class of applications anddesigns 20 that can make use of sub-threshold operation have been shown  in the literature [14]-[16]-[23].
Sentence 2: due to very low per­ formance, low functional yield and very high performance/energy variabilityduetoparametric variation[8], sub-thresholdlogic ap­ plications in commercial products have been limited.
Relationship: contrasting
Domain: Hardware
Sentence 1: Intemporalpartitioning,eahsignalgeneratedinastage mustbebufereduntilthestageitislastneeded.Wedefne theommuniationostatastageasthenumberofsignals thatneedtobebuferedattheendofthatstage.Anex­ampleisshowninFig.2.Theoutputofnodeahastobe buferedattheendofstage2andshouldremainbufered untilstage4.Itisknownthatthestorageneededforbufer­ingupsignalsreatesaonsiderableoverhead[2].Henean objetiveintemporalpartitioningistominimizetheom­muniationost.
Sentence 2: inspatialpartitioning,itisknownthatlogirepliation anbeperformedtoreduethenumberofinteronnetions betweenomponents[7,8,6,14].repliatinglogi temporallyhasneverbeensuggestedorinvestigatedbefore.
Relationship: contrasting
Domain: Hardware
Sentence 1: An intuitive approach is to use multiple processors to evaluate simultaneously happened events in parallel.
Sentence 2: it has been proved that such parallelism is not sufficient to maintain a decent speed-up due to the following 2 reasons: 1) generally only a small percentage (e.g., ~1%) of all circuit elements have active events, and 2) not all elements with active events can be handled simultaneously because the logic dependency actually implies a partial ordering in which the events have to be processed.
Relationship: contrasting
Domain: Hardware
Sentence 1: This way, PC al­locator requests which may later have to be invalidated do nottake resourcesawayfrompacketswhich arede.nitelyel­igible for chaining.
Sentence 2: sub-optimal chaining decisions are still possible because only some of the lower-priority re­questsmay actuallybecome eligible,but otherlower-priority requests may have been granted instead.
Relationship: contrasting
Domain: Hardware
Sentence 1: Compared to SMS and VWQ (results not shown), BuMP improves performance by 3% and 9%, on average, due to higher read coverage.
Sentence 2: full-region hurts performance by 67% (up to 4x for Data Serving), due to oversaturation of memory bandwidth, highlighting the importance of avoiding bulk transfer operations upon accesses to low-density regions.
Relationship: contrasting
Domain: Hardware
Sentence 1: Any block in L encounters at most one miss (the cold miss) every time when the program executes inside L. Proof: Since the miss distance of the underlying cache is X, after the cold miss of a block d, at least X other different blocks are needed for the next miss on d to happen.
Sentence 2: this is impossible when the program executes inside the loop L since it does not contain enough blocks.
Relationship: contrasting
Domain: Hardware
Sentence 1: concentration allows the two rows of wire bandwidth to be combined thus, resulting in a reduction of bandwidth per channel by only a factor of 2.
Sentence 2: the generalized hy­percube (Figure 12(c)) topology would increase the number of channels in the bisection of the network by a factor of 16, which would adversely impact the serialization latency and the overall latency of the network.
Relationship: contrasting
Domain: Hardware
Sentence 1: During normal operation, any time that REQ (request) is raised, the register REG for a given stage is loaded into the 7b down counter.
Sentence 2: tABLE I. SUMAMRY OF DTW BLOCKS AND ISPD12 BENCHMARKS  Property  Circuit DTW Blocks ISPD 2012 Benchmarks  DTW4 DTW6 DTW12 USB PCI DMA VGA Levels 10 28 192 10 3 2 6 Synchronous Cell Count 457 1145 5382 360 1606 13649 74885 Post-layout Area Overhead (%) 63 53 58 106 21 4.4 13 Throughput Delay Overhead (%) 9.8 7.7 7.8 12.6 17.4 6.7 2.5   further dynamic resiliency optimization is applied, as shown by the last part of Fig.
Relationship: contrasting
Domain: Hardware
Sentence 1: The importance of CT converters is due to the inherent anti-aliasing .ltering, low-power and/or high bandwidth operation.
Sentence 2: cT converters are sensitive Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: contrasting
Domain: Hardware
Sentence 1: A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems Qingan Li* , Yanxiang He * , Yong Chen * , Chun Jason Xue , Nan Jiang * , and Chao Xu * * School of Computer Science, Wuhan University, China Department of Computer Science, City University of Hong Kong, Hong Kong ww345ww@gmail.com, {yxhe,cyong}@whu.edu.cn, jasonxue@cityu.edu.hk, {nanjiang,xuch}@whu.edu.cn Abstract Phase Change Memory (PCM) is a promising DRAM replacement in embedded systems due to its attractive characteristics such as extremely low leakage power, high storage density and good scalability.
Sentence 2: pCM s low endurance constrains its practical applications.
Relationship: contrasting
Domain: Hardware
Sentence 1: = 362,880 VIA characters and 362,880×9×9 ~ 3.0×107 grids of stencil area, which exceeds the 3.6×106 limit.
Sentence 2: if we adopt2-stepswitchingwith6!=720flexibilityinthesecondVIAlayer,therequiredflexibilityforthefirstVIAlayeris9!/6!=540,resulting in the total VIA character number of 720+540 = 1260.
Relationship: contrasting
Domain: Hardware
Sentence 1: Encounter True-Time Delay Test Tool TM[6] is one such available commercial ATPG tool that uses actual design timing in­formation for ATPG.
Sentence 2: most of the widely used commer­cial ATPG tools are still timing unaware and generate test patterns based on the ease of .nding an affected path, instead of a least slack path.
Relationship: contrasting
Domain: Hardware
Sentence 1: MULTI-CHANNEL SSD SCALABILITY During last two decades, the improvements in .ash mem­ory technology have led to di.erent e.ects on storage de­vices: bit density increases, but other important features including performance, lifetime, and energy are drastically reduced.
Sentence 2: the SSD vendors strive to provide higher capacity products while keeping their perfor­mance at a reasonable level [20, 49].
Relationship: contrasting
Domain: Hardware
Sentence 1: ThisproblemhasSmaxvalueof99.2%,andthusisalmost fullyutilizedatthebloklevel.However,relaxingallpos­siblernetsisnexttoimpossible4 .Instead,werandomly relaxedrnetsandrepeatedthisfor500times.Figure13 showsaplotofthenumberofnetsrelaxed,r,againstthe numberofunroutednets.Thegraphshowstheminimum, averageandmaximumnumberofunroutednetsinthesam­ple.Figure14showstheprobabilitythattherelaxedprob­lemisroutedinhalfthetime.Althoughnotshownhere,the averageroutingtimeforasuessfulroutehasdereasedto aboutonequartertoonethirdoftheoriginalroutingtime, withmanyasesdroppingtoonlyafewseonds.
Sentence 2: theexperimentsshowthattopologyrelaxationimproves routability.Infat,themorenetsthatarerelaxed,the highertheprobabilitythattheiruitisroutedinhalfthe presentroutingtimeasshowninFigure14.we notethatitisimprudenttorelaxeverynet,sinethedelayof thepathsonwhihtherelaxednetliesinreases.Thus,the 4p15has55netsthatanberelaxed.thereare C(55Vr)diferentwaystohoosernetstorelax.Evenif eahinstanetookoneseondtosolve,testingallthe255 probleminstaneswillrequire1.1millionyearstoomplete!
Relationship: contrasting
Domain: Hardware
Sentence 1: The time reported for via minimization is not the time taken by the entire bi­nary search, but rather the time for the .nal SAT solve with the via bound equal to the minimum possible.
Sentence 2: it can be shown that with a few processors searching in parallel for the minimum number of vias possible, the expected total runtime is a small factor larger than the average SAT solve time Tavg (for example, with k = 3 processors the expected runtime is less than 4Tavg ).
Relationship: contrasting
Domain: Hardware
Sentence 1: Decoupling for Power Gating: Sources of Power Noise and Design Strategies Tong XuPeng LiBoyuan Yan Department of ECE Department of ECE Department of ECE Texas A&#38;M University Texas A&#38;M University Texas A&#38;M University College Station, Texas 77843 College Station, Texas 77843 College Station, Texas 77843 xutong85@tamu.edu pli@tamu.edu byan@tamu.edu ABSTRACT Power gating is essential for controlling leakage power dis­sipation of modern chip designs.
Sentence 2: power gating introduces unique power delivery integrity issues and trade­o.s between switching and rush current (wake-up) supply noises.
Relationship: contrasting
Domain: Hardware
Sentence 1: For instance, if a window happens to enclose a point common to all boxes associated with a node, we know that each box in the set will overlap the window.
Sentence 2: if the global bounding box of the entire set happens to be disjoint adaptive quadtree skipping underpopulated levels WW (a) no oblong children yet (b) oblong children of N dark nodes require inspection light nodes are contained by W white nodes are disjoint of W Figure 2: Oblong nodes are bene.cial of the window, none of the boxes will overlap it.
Relationship: contrasting
Domain: Hardware
Sentence 1: DBAR considers the congestion value of the nodes along the X and Y directions that reside in the minimal path to the destination node.
Sentence 2: if the congestion conditions of both nodes 11 and 14 are zero or one, the congestion status of nodes 7, and 3 in the Y direction are compared with the value of zero in the X direction, thereby the packet is probably sent to the node 14.
Relationship: contrasting
Domain: Hardware
Sentence 1: These long equalized links can be used as point-to-point wires between pairs of cores, but as there is insu.cient on-die wiring to support dedicated links between all pairs of cores, equalized links map more readily to indirect, multi-stage NoC topologies with long global links.
Sentence 2: as we mentioned earlier, such topologies do not leverage application locality, turning all traf.c into cross-die global traversals, which leads to high NoC latency and energy overheads.
Relationship: contrasting
Domain: Hardware
Sentence 1: Other components, such as, the VCMs and their motor drivers, head suspensions, pivot bearings, and head preampli.ers are expected to constitute only a small part of the overallcost of anintra-diskparalleldrive.
Sentence 2: the overarchingquestionis whetherthisincreasedcost(and its correspondinghigher sellingprice)wouldbe worth the investment for the eventual customer of the product.
Relationship: contrasting
Domain: Hardware
Sentence 1: As for short defects, it is well-known that supply current tests like IDDQ test are very effective and useful, since short defects are modeled as bridging faults in logic circuits and bridging faults are very difficult to be detected by measuring logic values of the primary output terminals.
Sentence 2: it is very difficult to detect open defects by measuring supply current of ICs.
Relationship: contrasting
Domain: Hardware
Sentence 1: The cool spot experiences higher von Mises stress, since the temperature difference from the stress free temperature, 275.C in our case, is larger in the cool spot than in the hot spot.
Sentence 2: since the maximum temperature difference across the die is only 20.C, the impact of an operating tempera­ture on the TSV reliability across the die is not signi.cant.
Relationship: contrasting
Domain: Hardware
Sentence 1: This additional interactive training could be performed using any sheet music, but we prefer to use mu­sical scales and exercises as they are traditionally a funda­mental step in instrumental practice; as a musician, it feels natural to hear (and correct) mistakes in timbre by practic­ing scales.
Sentence 2: there are also solid technical reasons to practice scales before attempting more complicated music: it allows us to pinpoint and .x problems in isolation.
Relationship: contrasting
Domain: Hardware
Sentence 1: Prediction in the MDCT domain as suggested in [9] is also computationally expensive.
Sentence 2: if we perform the error concealment operation directly in the Huffman coded domain, which we define as the compressed domain, we need only a small fraction of memory (~418 bytes in our example) to store an MP3 frame in comparison with the much larger amount (18432 bytes) for a single frame in the MDCT domain approach.
Relationship: contrasting
Domain: Hardware
Sentence 1: Weights wx attached to nodes of the CCG represent a function s WCET for a particular con­text, and edge weights w(x,y) computed by aiT represent how many times y is called by x in a context.
Sentence 2: the WC-path required for cache contents selec­tion can not be computed using the CCG, because informa­tion about the control .ow within functions is hidden in the CCG.
Relationship: contrasting
Domain: Hardware
Sentence 1: While LID will have a cost in area and frequency com­pared to a perfectly pipelined non-LI system, as design sizes continue to grow and CAD run time for each design itera­tion increases, the design costs of such systems become large enough to make LID attractive at the system level to inter­connect large modules.
Sentence 2: to fully exploit the promise and bene.ts of LID it must be integrated into CAD .ows and exploited by CAD tools to improve designer productiv­ity and design quality.
Relationship: contrasting
Domain: Hardware
Sentence 1: 978-3-9815370-2-4/DATE14/&#38;#169;2014 EDAA Certain parts of the standard SRAMs are alreaady optimized to avoid full swing operation limiting the bennefit of voltage reduction in such cases.
Sentence 2: other portionns of the memory still feature full-swing dynamic and static operaation that benefits from power reduction with supply voltage.
Relationship: contrasting
Domain: Hardware
Sentence 1: On-chip SRAM peripherals multiple sleep mode normalized leakage power savings 4.1 Reducing Leakage In On-Chip SRAM Peripherals To maximize the leakage reduction in each of the on-chip SRAM memories peripherals one solution would be to always put them into ultra low power mode.
Sentence 2: this requires wakeup of their peripheral circuits before accessing them adding 3 cycles to their access latency and significantly reducing performance.
Relationship: contrasting