sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: In the university where the authors of this paper work, the approach is a combination of general description and low­level programming, while in other universities the approach may focus more on performance, or other details depending on the textbook taken for the computer I/O subsystem topic.
Sentence 2: this paper is not related to how the computer I/O subsystem topic is taught, but how it is acquired by the students.
Relationship: contrasting
Domain: Hardware
Sentence 1: When compared to H-4x1A{1,2,3}D buses, an electrical bus with support for an equal number of snoop requests per bus cycle (four) exhibits comparable power consumption and ac­tive device area, but a 50% increase in metal area overhead.
Sentence 2: an electrical baseline with support for half as many snoop requests per bus cycle adds up to similar area and power characteristics as the opto-electrical counterparts.
Relationship: contrasting
Domain: Hardware
Sentence 1: Listing 1: The most useful combinations of adders and other logic in 1 LUT / bit always @* begin // Adder/subtracter if (x 2) result addsub = x0 - x1 ; else result addsub = x0 + x1; // 2-to -1 multiplexer and adder if (x3) result addmux = x0 + x1; else result addmux = x0 + x2 ; end Listing 2: Examples of other useful combinations of adders and other logic in 1 LUT / bit always @* begin // Using MULT AND to disable // the carry-chain if (x0) result multand = x1 + x2; else result multand = x1 | x2 ; // Adder combined with bit -wise or // of 3 inputs .
Sentence 2: result or = x0 + (x1 | x2 | x3 ); end in some situations a designer may be better o. using another structure allowed by equation 4.
Relationship: contrasting
Domain: Hardware
Sentence 1: As shown in Table 1, all the PiCode images with dimen­ sion 29 × 29 modules can be decoded at a BER below 1.25% using ZXing s algorithm, and at ~0% BER (i.e., 0 error out of the 500 samples) with the proposed algorithm.
Sentence 2: for high capacity PiCode with 45 × 45 mod­ules, the BERs of ZXing s approach are near 50%.
Relationship: contrasting
Domain: Hardware
Sentence 1: When |e|=Dij , then skew (vi 2 {Dij rc·Dij r·Dij ·CTi t (sr,sl)=t(vi,sr)-t(vj,sl)+(+ ) skew 2 Wu rc·D2 Dij ij r·Dij ·CTi t (sr,sl)=t(vi,svj,sl)+( 2 + Wl ) skew r)-t( Suppose that the skew permissible range for sr and sl is [LPRrl,UPRrl] and let M0 =[t0 (sr,sl)+ skew skewDij Dij Dij t 0 sr,sl)]/2, M =[t (sr,sl)+t (sr,sl)]/2, and skew(skew skewskewMPR =[LPRrl +UPRrl]/2.
Sentence 2: mPR is the center of the permissible range, M0 Dij )is the center of the skew skew (Mskewrange when z =0(z = Dij ).
Relationship: entailment
Domain: Hardware
Sentence 1: (3) s is always executed irrespective of the evaluation of c. (4) s belongs to the same basic block as a statement s ' from (1) or(2)and consequentlyexecutionof s ' ensures theexecution of s.  Statementcoverageofabranch conditionis de.nedinawaythat it closely approximates the statement coverage of a test that causes the conditiontoevaluateto true.Ourcoverage analysis ensuresthat the coverage reported by our technique is an under-approximation or a conservative estimate of the test coverage reported by a simu­lator.
Sentence 2: if a statement is reported as covered by our technique, it must be reported as covered by the simulator as well, while the converse may or may not be true.
Relationship: entailment
Domain: Hardware
Sentence 1: De.nition 3 [Coverage Hole in RTL Spec: ] A coverage hole in the RTL speci.cation is a property RH over APn, such that (RARH):A, and there exists no property, Rc, over APnsuch that Rcis weaker than RH H H c and (RARH):A.
Sentence 2: this is the weakest property that suf.ces to close the coverage hole.
Relationship: entailment
Domain: Hardware
Sentence 1: (2) To capture such potentials in a practical setting, we also per­form a scheduler design space exploration to quantify the impact of different design decisions.
Sentence 2: by selectively applying task grouping and ordering, we show that proper grouping alone brings up to 2.23x speedup over a random schedule, using a good ordering gives up to 1.17x additional speedup, and applying group­ing and ordering across multiple cache levels gives up to 1.52x speedup over a single-level schedule.
Relationship: entailment
Domain: Hardware
Sentence 1: 2Available for download at http://perform.wpi.edu/ downloads/#cubic Evaluation of our ns-3 CUBIC veri.es the implementation, and comparisons with Linux measurements provide valida­tion.
Sentence 2: the ns-3 implementation produces a CUBIC-like cwnd growth pattern which is critical for mod­ern TCP implementations to e.ectivley utilize available net­work capacities.
Relationship: entailment
Domain: Hardware
Sentence 1: Therefore, say the transmission data has 8bit(here we denote the data as TxD), data transmission can be started at 4×TxD away from the top of the code (the spreading code for data transmission), and go back to the top of the code when the shift position reaches the end.
Sentence 2: all the 1024 chips are sent by starting somewhere in the code of 1024 chips and coming back to the start point.
Relationship: entailment
Domain: Hardware
Sentence 1: Column SMBu.s (red .%) shows the percentage of buffers saved compared with the unconditional scheme [6] used in industry for several years that must use the tightest target cycle time t0 for the whole circuit.
Sentence 2: the number of slack matching buffers is reduced by as much as 73% with an average of 33% and medan of 31%.
Relationship: entailment
Domain: Hardware
Sentence 1: For non-Gaussian CNT diameter distributions, (4.2) can be used to find a similar guideline for cm.
Sentence 2: the value (or range) of cm must be chosen such that the tail probability of [1 Fmd(cm)] is on the order of 1/104 = 10-4, assuming 104 is the targeted Ion /Ioff ratio.
Relationship: entailment
Domain: Hardware
Sentence 1: Indeed, in order to obtain full bene.t of the afore­mentioned energy-e.cient techniques, it is crucial to have agood characterization of servers in the datacenter, as a function of the utilization of the server s components.
Sentence 2: it is necessary to know and understand the energy and power consumption of servers and how this changes under the di.erent con.gurations.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.4 Met ast abilit y Avoidance A fundamental challenge in counter.ow pipelining is to handle metastability, which can result when a pipeline stage receives a data token and an anti-token nearly simultaneously.
Sentence 2: if the data token arrives .rst, the stage is supposed to process it; if the anti­token arrives .rst, the data token must be destroyed; however, if both arrive close together, the stage s control may become metastable.
Relationship: entailment
Domain: Hardware
Sentence 1: 2.1 Heat Source and Thermal Properties The heat source g(x, t) is allowed to both produce (addi­tive source) and withdraw (sink) heat2, and we model it by a continuous space-time Gaussian stochastic process, which is periodic and bandlimited over space, and which is ban­dlimited over time.
Sentence 2: g(x, t)is given by: M M g0(t) g(x, t)= v + (gm(t)cos(.mx)+ gm+M (t)sin(.mx)) 2 m=1 (1) where M + 1 is the number of harmonics (spatial bandwidth of 2M +1), .m = mp , m =0 (thus the fundamental spatial L period is 2L, which is equal to the length of the ring), and {gm(t)}2M is a set of 2M + 1 continuous-time real wide­ m=0 sense stationary (WSS) Gaussian stochastic processes with zero mean and which are assumed to be independent, that is, the cross-correlation Rgm1 gm2 (.
Relationship: entailment
Domain: Hardware
Sentence 1: Instead of de­veloping new face detection algorithms speci.cally for .sh­eye images, we properly pre-process the .sheye image and leverage existing face detection tools.
Sentence 2: we per­form an o.ine camera calibration process to obtain the cam­era model, with which we can e.ectively rectify a .sheye im­age into a planar one to .x the radial distortion.
Relationship: entailment
Domain: Hardware
Sentence 1: Using Speculative Computation and Parallelizing techniques to improve Scheduling of Control based Designs Roberto Cordone Fabrizio Ferrandi# Gianluca Palermo# Marco D. Santambrogio# Donatella Sciuto# Universit`a Statale di Milano -DTI #Politecnico di Milano -DEI via Bramante, 65 pza Leonardo da Vinci, 32 26013, Crema, ITALY 20133, MILANO, ITALY Tel: +39-0373-898-054 Tel: +39-02-2399-3479 Fax: +39-0373-898-010 Fax: +39-02-2399-3411 e-mail: cordone@dti.unimi.it e-mail: {ferrandi gpalermo santambr sciuto}@elet.polimi.it November 18, 2005 ABSTRACT Recent research results have seen the application of parallelizing techniques to high-level synthesis.
Sentence 2: the effect of spec­ulative code transformations on mixed control-data .ow designs has demonstrated effective results on schedule lengths.
Relationship: entailment
Domain: Hardware
Sentence 1: We make the observation that intelligent thread management can be used to provide this additional control.
Sentence 2: we use a previously developed performance technique to prevent L2 cache misses from one or more threads from hoarding machine resources and 108 108 108 # of Occurrences # of Occurrences # of Occurrences # of Occurrences # of Occurrences # of Occurrences 106 104 102 106 104 102 106 104 102 100 100 100 then periodically releasing a subset, a scenario that results in bursts of Power (Watts) Power (Watts) Power (Watts) activity at resonance.
Relationship: entailment
Domain: Hardware
Sentence 1: Moreover, to prevent polling activity from injecting interfering traf.c on the interconnect, we distribute noti.cation and release .ags so that each pro­cessor does busy waiting on a private, local memory cell.
Sentence 2: we leverage the multi-banking feature of on­cluster TCDMs to make sure that each slave directs its polling transactions to a different memory bank.
Relationship: entailment
Domain: Hardware
Sentence 1: C. Putting All Together: Set-Associative Caches The ETP of a memory operation accessing to a S · W set-associative cache with random placement and replacement policies is the combination of the ETPs of both policies.
Sentence 2: the random placement will allocate memory objects into the S sets with a probability of 1/S while the random replacement policy will evict a way to allocate a new fetched cache line with a probability of 1/W .
Relationship: entailment
Domain: Hardware
Sentence 1: The processor traverses the q subtrees in the order determined by ~r~[i] (lines 48-51), but it tra-verses within a subtree only if the corresponding bit in the progress tree is not set (line 44).
Sentence 2: each pro- cessor PID traverses its progress tree in a post-order fashion using the q-ary digits of its PID and the permutations in qJ to establish the order of the subtree traversals, except that when the messages from other processors are received, the progress tree of processor PID is potentially pruned based on the progress of other processors.
Relationship: entailment
Domain: Hardware
Sentence 1: 4.1 Hardware Design We propose a basic hardware module called the intensity evaluation cell to compute ri,ml , .i,ml,m * and .i,ml,m * for a data point oi and a dimension m ' following the hyper­recursive intensity evaluation strategy discussed in the pre­vious section.
Sentence 2: an intensity evaluation cell does not provide the intensity value directly, but it collects statistical information from data so that the intensity value can easily be computed.
Relationship: entailment
Domain: Hardware
Sentence 1: Adaptive Thermal Management for Portable System Batteries by Forced Convection Cooling E:QingDropboxWork_In_Progressfan.png Qing Xie, Siyu Yue, and Massoud Pedram  Department of Electrical Engineering University of Southern California Los Angeles, California, United States, 90089 {xqing, siyuyue, pedram}@usc.edu Donghwa Shin, and Naehyuck Chang Department of EECS/CSE Soule National University Soule, Korea, 151-747 {dhshin, naehyuck}@elpl.snu.ac.kr  Abstract Cycle life of a battery largely varies according to the battery operating conditions, especially the battery temperature.
Sentence 2: batteries age much faster at high temperature.
Relationship: entailment
Domain: Hardware
Sentence 1: The available number of cluster pins is bounded by the cluster size and the maximum avail­able pins in each cluster in the architecture.
Sentence 2: if j is the num­ber of pins which can be used, then k +1 j 3n + 2 , since the == minimum number of pins is k+1 (k is the LE size) and the maxi­mum number of pins is 2n+2+n = (3n+2).
Relationship: entailment
Domain: Hardware
Sentence 1: Since a higher vthprocess ao  has a higher a, as shown in Table 1, a higher vthprocess gets less ao switching power saving from pipelining.
Sentence 2: the optimal logic depth N.is given by: 1b1a1b1b1 N. (+-) (9) 4bo aobobo The equation indicates that the capacitance ratio of a timing ele­ ment and an FO4 inverter bis positively correlated to N..bo larger timing element parasitics lead to less deep pipelining.
Relationship: entailment
Domain: Hardware
Sentence 1: This transformation does not change the equivalence of the entire circuit to the identity.
Sentence 2: if g1 ·g2 ····· -1 gk-1 ·gk = I (Identity), then g ·g1 ·g2 ·····gk-1 ·gk ·g1 = 1 -1 -1 g ·I ·g1 = g1 ·g1 = I.
Relationship: entailment
Domain: Hardware
Sentence 1: One of the main reasons which limits interlayer liquid cooling technology is the lack of Electronic Design Automation (EDA) tools that can provide IC designers with e.cient simulation of thermal behavior of ICs cooled using microchannel heat sinks.
Sentence 2: this situation becomes a major bottleneck for the development of thermal-aware design and run-time approaches for liquid cooled 3D ICs.
Relationship: entailment
Domain: Hardware
Sentence 1: The HEES system with the proposed algorithm can achieve higher overall cycle efficiency than that of the homogeneous EES system because of the near-optimal choice of CTI voltage, charging/discharging currents and high cycle efficiency of the supercapacitor bank.
Sentence 2: the HEES system needs less input energy to support the same load demand and thereby further reduce the SoC swing and average SoC level of the battery array.
Relationship: entailment
Domain: Hardware
Sentence 1: As a compromise, in this work, we use CNT to complement with, instead of replace, existing metal wires to implement word­lines/bit-lines in digital memories.
Sentence 2: we propose a simple hybrid word-line/bit-line structure, where a metal wire and a CNT bundle form a parallel word-line/bit-line and the metal wire and CNT bundle have good contact at the two ends.
Relationship: entailment
Domain: Hardware
Sentence 1: This observation allows .le allocations to be organised so as to achieve product-forms, facilitating simple quantitative analysis.
Sentence 2: since the number of free input probabilities is n(n- 1) - n(n- 2) = n, which is the number of inputs that do not fork, one strategy is to choose the non-forking input probabilities in any way desired, for example propor­tional to the rates of the corresponding disk drives.
Relationship: entailment
Domain: Hardware
Sentence 1: TFETs enable 10X speed improvement at ultra-low voltages (e.g., 250 mV or lower), compared to MOSFETs.
Sentence 2: operation in the MHz range is allowed even for voltages in the order of 200-250 mV, which makes TFETs very well suited for applications where energy is crucial and low performance is tolerable (e.g., biomedical and implantable systems, sensor nodes).
Relationship: entailment
Domain: Hardware
Sentence 1: ( z a/E2si )2 n0 = (20) 3.3 Error Bound In order to choose a meaningful error bound Efor use in (20), recall that our intent is to approximate the variance of every node voltage as follows: s2 Sr¯i (21) Vi Let d be a small positive number, 0 <d<1.
Sentence 2: it makes sense to aim to achieve a user-de.ned error bound on sde.ned relative Vi to the supply voltage, Vdd, as follows:  sVi -Sr¯i =dVdd (22) we want to .nd E(to be used in (20)) as a function of din order for the following to be true:  |r¯i -µi|<E =.
Relationship: entailment
Domain: Hardware
Sentence 1: Because the Iinv function is monotonic, its inverses are also func­tions.
Sentence 2: we de.ne ininv(Vout,Iout)to be the input voltage to the inverter such that if the output voltage is Vout, then the output current will be Iout.In other words: Iinv(ininv(Vout,Iout),Vout)= Iout (3) We now assume that all forward inverters have the same transfer function and that all cross-coupling inverters have the same transfer function.
Relationship: entailment
Domain: Hardware
Sentence 1: Measurements of the MICA2 in dif­ferent power states [5], and the impact of the Shake n Wake board upon the amount of time spent in each power state, in­dicate that for the ACM structural integrity monitoring ap­plication, the combined long-term average power consump­tion of the MICA2 processor radio board, the MDA300 data acquisition board, the Shake n Wake board, and the sen­sors will be reduced from 29.8 mW to 121.8 .W by using the Shake n Wake implementation of lucid dreaming, i.e., bat­tery life will be increased from 10.91 days to seven years.
Sentence 2: battery life will be limited only by the shelf life of the batteries.
Relationship: entailment
Domain: Hardware
Sentence 1: Percentage of Total L3 Cache Leakage Power 80% 70% 60% 50% 40% 30% 20% 10% Workload Figure 8: Cache leakage energy of way prioritiza­ variation can have signi.cant in.uence on the cache leakage pro.le.
Sentence 2: equal areas of the cache may have leakage factors that di.er by more than an order of magni­tude.
Relationship: entailment
Domain: Hardware
Sentence 1: 16.73%11.31%12.05%15.48% Table1:Results:BusActivity.
Sentence 2: 3.2SwitchingActivityResults Wehaveselectedanumberofrealisticsoftwareapplications (i.e.,thosedistributedtogetherwiththePtolemyframework[7] andtypicalforimplementationinembeddedsystems),andwe haveusedthemtobenchmarkthecapabilitiesofthespatially­adaptivebusinterface,whenappliedinthecontextofanARM­basedsystemcontaining,besidestheARM7TDMIcore,amem­ory,threeAHBmastersrequestingrandommemoryaccesses andtwoAHBslavesmodelingacommunicationdevice.Table1 collectsthedataoftheexperiments.ColumnSp.Adapt.re­portstheaveragepercentageofachievedtransitionsavings.address(A),data-read(DR)anddata-write(DW) busesareconsidered.Thetableincludesalso,incolumnsAdapt., BIandBI2,similarresultsforadaptivecode,bus-invertcode andbi-partitionedbus-invertcode,respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: T -1 MC · S · (log P - A ·T) g g = 0(37) can be substantially different.
Sentence 2: the accuracy of = 2 · A {logPg,q MC; q = 1, 2, , Q} associated with different scaling factors {sq; q = 1, 2, , Q} can be different, because the scaled failure rates {Pg,q; q = 1, 2, , Q} strongly depend on the scaling factors.
Relationship: entailment
Domain: Hardware
Sentence 1: Therefore, as far as the inequality (3) is satisfied, low power consumption can be achieved by substituting single-rail static circuits for dual-rail dynamic circuits, yet performance enhancement by the overlapped partial remainder computation is still maintained.
Sentence 2: except for the three most-significant-digit part of the partial remainder to determine the quotient digit, the rest of the RSD adders can be implemented with single-rail static circuits, which results in power reduction.
Relationship: entailment
Domain: Hardware
Sentence 1: Thermals and Performance Benefits of Stacking Stacking memory with the CPU has the benefit of providing a high bandwidth path to a large last level cache which reduces the off-die bandwidth requirements significantly as well as provide CPU performance benefits and lower overall power.
Sentence 2: 666 simulations of the addition of 32-64 MB cache to the CPU result in a 3x reduction in off-die memory BW while simultaneously providing a 15% performance and 15% reduction in power[5].
Relationship: entailment
Domain: Hardware
Sentence 1: The reason is that symbi­oticjob schedulingisless effective and oflessinterestfor multi­threaded workloads.
Sentence 2: threads in a multi-threaded workload that communicate frequently are preferably co-scheduled on a multi­threadedprocessorin orderto reduce synchronization and commu­nication overhead.the realbene.t of symbioticjob scheduling isinco-scheduling unrelatedjobs.Inaddition,sequen­tial programs will continue to be an important class of workloads which motivatesfurther research towards more effective symbiotic jobscheduling.
Relationship: entailment
Domain: Hardware
Sentence 1: We see that the coef.cient corresponding to Capi is much larger than that for Slewi in both gate delay and slew formulas in most of cases.
Sentence 2: the delay and slew are more sensitive to the S j = c · (bi + ai+1 · vi) + r · (KD ·Cpin j + KS · ai+1 ·Cpin j+1) (13) In above formula, the value of the unit resistance r is in order of magnitude smaller than that of the unit capacitance c, and the dominant term in formula (13) is c · (bi + ai+1 · vi).
Relationship: entailment
Domain: Hardware
Sentence 1: Figure 9(a) plots the wastage in the .xed-512B block size organization and that incurred in the Bi-Modal Cache for 8-core workloads.
Sentence 2: the workloads E8,E12,E14 and E15 that suffered signi.cant wastage in the .xed block size con.guration have considerably bene.ted.
Relationship: entailment
Domain: Hardware
Sentence 1: Benchmark Circuit Information Circuit #Nets # Gates Total # couplings %Nets with coupling Average # of couplings per net c432 218 181 445 81.65 4 c499 582 540 1100 82.47 4 c880 431 370 245 32.01 3 c1355 626 584 1072 90.57 3 c1908 506 472 682 90.11 2 c2670 1118 884 1749 78.35 3 c3540 1069 1018 3529 94.76 6 c5315 1876 1697 3920 62.95 6 c6288 2450 2417 11210 93.06 10 c7552 2449 2241 10940 91.42 9 alu64 1935 1803 9085 93.17 10 We note that delay model Property 3 applies not only to a single aggressor but also to multiple aggressors.
Sentence 2: the noisy arrival time tvn due to multiple optimally aligned noise pulses is later than all aggressor driver input arrival times tai,i that induced the noise pulse.
Relationship: entailment
Domain: Hardware
Sentence 1: However, the exact degree depends on the workload locality pat­tern.
Sentence 2: for hj and smvm, which exhibit high L1 shar­ing degree (see Table 4), random schedules poor task grouping generate many cache-to-cache transfers; and as the transfer latency increases, give recursive schedules signi.cant performance advan­tage (compared to 32-core executions, 1.83x and 1.65x additional locality bene.ts with 1024 cores, respectively).
Relationship: entailment
Domain: Hardware
Sentence 1: In fact, we need to enforce that ex­actly c of those select-signals are set to 1 (ensuring a pri­mary input/.ip .op set to a Boolean value), while all re­maining ones are set to 0 (leading to a primary input/.ip .op with an observability don t care).
Sentence 2: for all k primary input/.ip .op signals sig0, sig1, .
Relationship: entailment
Domain: Hardware
Sentence 1: The combination of growing LLC capacity, shrinking SRAMcelldimensions, andincreasingfabrication variability that reduces error margins is leading to a higher soft error rate (SER) [19, 27, 29].
Sentence 2: recent trends show that multi-bit burst errors in the array are becoming signif­icant, partially because many memory cells can fall under thefootprint of a single energeticparticle strike[19,21,26].
Relationship: entailment
Domain: Hardware
Sentence 1: Each processor and link is characterized with a set of discrete supply voltage values and the corresponding operating frequency.
Sentence 2: given a target application described by a communication dependence and computation graph (CDCG), a set of heterogeneous processor cores, a tile-based NoC architecture and the hard deadline of the application, we propose an energy efficient NoC synthesis algorithm which solves the following problems simultaneously: i) tile mapping to determine the corresponding tile that each processor should be mapped onto; ii) routing path allocation to obtain the legal routing path for each communication transaction; iii) physical voltage island creation and voltage assignment for each voltage island and communication link.
Relationship: entailment