sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: The sum of a set of Gaussians is, itself, a Gaussian.
Sentence 2: tpath(d)= tu0 + tu1 + ... + tud-1 (9) v = d × µtu ; spath(d)= d × stu (10) µtpath(d) spath(d)1 stu = v (11) µtpath(d) dµtu as a percentage of the nominal delay, the variation decreases by a factor of the square root of the path length, d. This means, slow circuits will see small variation, while circuits that are highly pipelined with few LUTs and inter­connect segments between .ops will see a larger variation as a percentage of nominal path delay.
Relationship: entailment
Domain: Hardware
Sentence 1: Categories and Subject Descriptors B.3.3 [Memory Structures]: performance analysis and design aids; Keywords nanoelectronics, resistive switches, hybrid circuit, electrochemical metallization, monte carlo simulation, variability, irreproducibility, scaling 1.INTRODUCTION In recent years resistive switches (RS) have gained considerable attention as these devices provide non-volatile and multilevel storage capabilities.
Sentence 2: these devices are commonly seen as an area-efficient successor to well-established storage devices since their comparatively simple setup may help to overcome the technological as well as economical limits anticipated for scaling CMOS beyond the 10nm node [1].
Relationship: entailment
Domain: Hardware
Sentence 1: An important requirement that needs to be imposed here is that at no step of the merging process should the dimension of a partition be increased.
Sentence 2: when merging two partitions, the resulting partition must have the dimension of (1) P2 merges P1 VPNs 00101001 xxxx0000 00101010 P2 xxxx0001 3-bit partition 00101011 ...... P1 00101100 xxxx1100 P1 xxxx1101 00101101 10010000 10010001 (2) P1, P2, and P3 merged 10010010 10010011 4-bit partition P2 1-bit partition P3  Figure 5: VPN partition merging the larger partition from the initial pair of partitions.
Relationship: entailment
Domain: Hardware
Sentence 1: 8 bits '0 Sub-array 1in~,,,o in l~uts Sub ..... y2 '1' 6 bits :', 7 2 ilii| ~ ....... Sub-array 1 Sub-array 2 oi "2 Sub-army 1 I Address 1 I Address2 dual port 512x8 ; Data 1 Data 2 Data 1 Data 2 Sub-array 2 i I° Sub-array 1 Sub-array 2 Outputs Outputs a) Horizontal Partitioning Figure 2: Partitioning  3 Algorithm Description: Area Minimization Algorithm In this section, we consider strict area minimization.
Sentence 2: the goal is to pack as much logic into the available arrays as possible (since the more logic that is implemented in the arrays, the less that must be implemented using the logic re- sources of the FPGA), without regard for the speed of the final circuit.
Relationship: entailment
Domain: Hardware
Sentence 1: Maximal Parallelism A layout has maximal parallelism if the addresses of data in any interval {t, t +1,...,t + n - 1} of n consec­utive addresses are mapped to n di.erent disks.
Sentence 2: for every starting point t with 0 = t = bm - n and every i and i ' with 0 = i<i ' .
Relationship: entailment
Domain: Hardware
Sentence 1: Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces Carlotta Guiducci1, Alexandre Schmid2, Frank K. Gürkaynak2, and Yusuf Leblebici2 1DEIS University of Bologna, Italy 2Microelectronic Systems Laboratory (LSM), EPFL Lausanne, 1015 Switzerland Abstract The prospective use of upcoming nanometer CMOS technology nodes (65nm, 45nm, and beyond) in bio­electronic interfaces is raising a number of important issues concerning circuit architectures and design.
Sentence 2: the advantages of scaling and higher density integration must be balanced against the requirements of low noise design, uniform power density and surface temperature distribution, better component matching, and immunity to parameter variations.
Relationship: entailment
Domain: Hardware
Sentence 1: present a probing technology that could be used for probing TSVs with .ner pitch [11], the possibility of implementing RF-based wireless techniques to test chips at both die and wafer levels has also been ex­plored [6, 8].
Sentence 2: laser direct testing techniques, currently used to detect defects in PCBs, could be used for contact-less testing of 3D ICs [6].
Relationship: entailment
Domain: Hardware
Sentence 1: At-speed scan testing may suffer from test-induced yield loss [2­6] due to two factors: (1) excessive IR-drop (supply voltage drop at cells [2] due to current flowing through a RLC network) caused by the high switching activity of test data, test operation, and test clocking, and (2) the at-speed nature of using a short cycle for capturing a test response.
Sentence 2: iR-drop increases path delay, which then results in timing violations by the short capture cycle.
Relationship: entailment
Domain: Hardware
Sentence 1: Also, assuming that the channel responses of a CP and an adjacent scattered pilot (SP) nearest to it in an OFDM sym­ bol are the same and the channel responses of CPs located on the same indices in the two consecutive OFDM symbols are the same, the conventional scheme in [2] uses combina­ tions only of a CP and an SP nearest to it and of two CPs.
Sentence 2: only some parts of all combinations among CPs and SPs are used for the carrier frequency o.set estima­ tion.
Relationship: entailment
Domain: Hardware
Sentence 1: This is because v5 is in the transitive fanout cone of v3 , replacing v3 with v5 will result in a cyclic combinational circuit.
Sentence 2: furthermore, Condition 1 can be modi.ed by reversing the value of ns to .nd another kind of substitute node that replaces a target node with an additional inv.if ns =0 and ns = 1 are MAs for the stuck-at 0 and stuck-at 1 fault tests on nt , respectively, nt can be replaced by ns with an additional inv.
Relationship: entailment
Domain: Hardware
Sentence 1: As the rate of permanent faults depends on the reliability of the memory chips, then it can be estab­lished using for example the models of [6], [1].
Sentence 2: the following three cases are considered: 1) comparison of simplex and duplex RS(18,16) with no scrubbing and variable SEU rate; 2) analysis of duplex RS(18,16) for different Tsc periods and under the worst case scenario of the SEU rate; 3) comparison of simplex and duplex RS(18,16), and sim­plex RS(18,16) under different rates for permanent faults.
Relationship: entailment
Domain: Hardware
Sentence 1: If the access latency of the issue queue is two cycles (in the case of MC scheme), some of the produced results may not be compared with the operand tags.
Sentence 2: if the issue queue is accessed in ev­ery odd cycles (because of two cycle latency), all the re­sults produced in even cycles cannot be compared with the operand tags of instructions present in the issue queue.
Relationship: entailment
Domain: Hardware
Sentence 1: For example, one application is to evaluate the upper bound on the potential loss of coverage during path selec­tion, which is the PCM of the (T - 1)th bucket.
Sentence 2: no matter how many more paths are to be added, the improvement on coverage from our path selection will not be more than the PCM of the (T - 1)th bucket.
Relationship: entailment
Domain: Hardware
Sentence 1: preconditioned conjugate gradient method [3] [4] [25], multi­grid techniques [13] [18] [27], divide-and-conquer methodol­ogy [24] [19], random walks [16], locality [6], relaxation it­erative method [26], and Poisson solver optimized for GPU platforms [17] have emerged.
Sentence 2: [20] and [7] have been proposed for TAU 2011 Power Grid Simulation Con­test [14].
Relationship: entailment
Domain: Hardware
Sentence 1: 2.5 Network initialization To guarantee correct formation of the routing table after deployment, the distances between the sampling nodes and the control node should be obtained; it should be used to initialize the network.
Sentence 2: the network initialization consists of the following procedure: (1) The control node (which is the one initializing the network) sends a ranging request frame to the other nodes one by one (which are the target terminal of ranging) to ask for a distance measurement.
Relationship: entailment
Domain: Hardware
Sentence 1: 5.1 Static Approximate Adder Comparison We examine the static behavior of the proposed GDA adder in this subsection.
Sentence 2: we implement the di.erent con.g­uration modes of GDA adder and ACA adder3 as dedicated 32-bit static approximate adders and two approximate adders (Lu s adder [1] and V LC SA-1 [13]) for comparison.
Relationship: entailment
Domain: Hardware
Sentence 1: Hence, the formal verification of a processor with a 5-entry instruction queue takes 215 seconds the sum of the formal verification times for the Execution Engine and the Fetch Engine with a 5-entry instruction queue.
Sentence 2: the pre­sented method results in 2 orders of magnitude speedup for the processor with a 5-entry instruction queue, compared to its monolithic formal verification (see Table 1).
Relationship: entailment
Domain: Hardware
Sentence 1: For this problem, we consider the gate capacitance and the diffusion capacitance as functions of the inverter size.
Sentence 2: cg0=ßW0, Cd0 = aW0, Cgx=ßWx, and Cdx = aWx in Figure 4 here a and ß are gate and diffusion capacitance of unit size.
Relationship: entailment
Domain: Hardware
Sentence 1: On theGPU we statically allocate memoryfor3 sets of 8Klearnedclauses, oflength <10literals,=10literals and<25lit­erals, and =25literals and <50literals.
Sentence 2: in all ourbenchmarks, the .nal decision of reporting the instance to be satis.able or unsatis­.able was madeby theMiniSAT(CPU)portion ofMESP.forthese structuralbenchmarks, theSurveySAT routine was never able exit early by determining a satisfying assignment using walksat.
Relationship: entailment
Domain: Hardware
Sentence 1: Recall this means that each pipeline stage is represented by a transition and each channel is associated with one forward and one backward place.
Sentence 2: constraint (i) and (ii) together implement constraints for forward and backward places modi.ed to capture the impact of sc buffers added to each channel c. constraint (i) is based on constraint (i) in Figure 6. f(m) = 0 guarantees that for each channel c = (vi, vj) with no initial token, the arrival time of node vj is at least as large as the arrival time of node vi plus the forward latency of the channel (lc) plus the forward latency of the sc slack matching buffer that will be added to the channel.
Relationship: entailment
Domain: Hardware
Sentence 1: As a result, if we transmit per­muted data of two consecutive data items which have the same upper half, we get no transitions on the alternate wires in the bus and hence these alternate wires can act as shield wires to prevent opposite transitions.
Sentence 2: if d1 : n 2 ' 1 and the state of the system is 0, data is not transmitted actual data items with the same upper half, we transmit the ' and d2 : two an ···a with d1[16 : 9].
Relationship: entailment
Domain: Hardware
Sentence 1: Note that current ICLUS = {Iclusi} = {Iclus1, Iclus2, Iclus3, Iclus4} discharging from clusters depends on the input vectors.
Sentence 2: for an input vector, we can obtain ICLUS; and then with ICLUS, we can find IST = {ISTi} = {IST1, IST2, IST3, IST4} = F*ICLUS.
Relationship: entailment
Domain: Hardware
Sentence 1: The coarse grid matrices are then cheap to compute and generally as sparse as the original .ne grid matrix.
Sentence 2: as we have denoted the conduc­tance matrix G as .ne grid matrix Af which is symmetric and positive de.nite, the coarse grid matrix is computed from the Galerkin formula Ac = RAf P = Af P which P T implies that Ac is cheap to construct using .. (Ac)= akl (2) ij k.Gi l.Gj the entries in the coarse grid matrix are obtained by summing the entries in Af that connect the di.erent aggregates.
Relationship: entailment
Domain: Hardware
Sentence 1: Currently, all the assays are programmed by hand and it is very complex to program droplet operations for more than two assays performed in parallel on-chip.
Sentence 2: the end user should not be burdened with any programming tasks and the operation of the biochips should ideally be completely transparent, wherein the user only has to specify the assay protocol and input the liquid samples.
Relationship: entailment
Domain: Hardware
Sentence 1: (14) t |Bkt |Bk 2  3.4 Inductive Algorithm A more abstract representation of (14) and (13) helps to simplify subsequent use and also clari.es some of the de­pendencies.
Sentence 2: applying (14) and (13) can be denoted as f k-1 (v|b)= Vt |Bk-1 () G fV k (v|b),d(v- vR(tk )),d(v- vF (tk))(15) t |Bk where G is an operator that maps three PDFs to a single PDF.
Relationship: entailment
Domain: Hardware
Sentence 1: BACKGROUND In this section, we will explain how MRF inference maps to an energy minimization method for the stereo matching problem.
Sentence 2: we describe the preprocessing part of this method, Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: entailment
Domain: Hardware
Sentence 1: As a .nal remark, we note that, due to performance reasons, some nonlinear lookup tables are stored in such a fashion that the out­put bits of the functions they represent are represented as a permuted and sparse sequence.
Sentence 2: this takes place in optimized imple­mentations of ciphers such as the DES, where the actual lookup table action is merged together with a bitwise permutation.
Relationship: entailment
Domain: Hardware
Sentence 1: A 50 MHz clock specifies a clock tick of 20 ns period -which means that we cannot wait out the (minimum) active time of 50 ns exactly.
Sentence 2: the fidelity of a state­machine wait , will depend on the clock rate: @50 MHz, 3 ticks will wait out 60 ns; @100 MHz, 5 ticks will wait out 50 ns.
Relationship: entailment
Domain: Hardware
Sentence 1: To quickly determine the range of a distribution so that we can decide if the Monte-Carlo sampling should stop ear­lier, a 3-sigma bound measurement is used.
Sentence 2: after the .rst k samples, we test to see whether the 3rd standard deviation above the mean is smaller than the value of the reference line (likewise, we test to see whether the 3rd stan­dard deviation below the mean is larger than the value of the reference line).
Relationship: entailment
Domain: Hardware
Sentence 1: Fortunately this case is easy to identify and .x: we simply unroll (or strip-mine) the loop body such that each epoch gets a block of iterations that perform all of the sequen­tial stores to a given cache line.
Sentence 2: we use block­cyclic rather than cyclic (aka round-robin ) scheduling, which is a common technique for avoiding the analogous problem of false sharing in traditional shared-memory multiprocessors.
Relationship: entailment
Domain: Hardware
Sentence 1: The total rate of this transition is given by A~[p[ik],p[jk]], which is the sum over all nodes p' such that p'[ik] = p[ik] and p'[jk] = P[jk] of the probability of being in state (p', ik) given that we are in node p[ik], multiplied by the rate of the transition from ik to jk at level k. This transition will continue to affect later levels until all the arcs corresponding to the transition are self-arcs.
Sentence 2: if p[ik] = P[jk], then the corresponding arcs at the next level will all be self- arcs, and e will not affect any other levels.
Relationship: entailment
Domain: Hardware
Sentence 1: MEASUREMENT METHODOLOGY The .rst goal of the measurement methodology is to ob­tain the capacitance values for the global wires used for  Figure 1: Measurement setup routing, as this information contains proprietary technol­ogy details and it is unavailable to us.
Sentence 2: xilinx Virtex-II Pro devices are the target technology considered inthiswork.
Relationship: entailment
Domain: Hardware
Sentence 1: For a positive edge­triggered D-type flip-flop, the pin C1 is connected to the clock and the pin C2 is connected to the complement of the clock; on the other hand, for a negative-edge-triggered D-type flip-flop, the pin C2 is connected to the clock and the pin C1 is connected to the complement of the clock.
Sentence 2: both the positive­edge-triggered D-type flip-flop and the negative-edge-triggered D­type flip-flop are implemented in the same circuit structure except for the opposite clocking schemes.
Relationship: entailment
Domain: Hardware
Sentence 1: Mod­ern designs are often pipelined to be shallow, resulting in a small D. As we will see the best values of Ct are around 8, so a typical operating regime will have Ct = D. In practice, when Ct = D, it should be possible to keep C F 2.
Sentence 2: we need at least Ct leaf routes to handle the leaf inter­connect serialization, which is also enough to handle node serialization when Ct = S. Since Ct = D, we will have depths that need more than one context for routing, Cti .
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION While the progress in electronics thus far has relied on the scaling of transistors and an increasingly complex maze of interconnecting wires, future advances in circuitry will require mating CMOS technology with new types of fabrication technologies, device principles, and circuit architectures.
Sentence 2: power dissipation limits and the interconnect bottleneck at high integration levels, coupled with the inherently low drive capability of small devices, will mandate the use of relatively simple, ultrasmall devices laid out in highly regular arrays and interconnected predominantly locally all done with nanometer-scale precision.
Relationship: entailment
Domain: Hardware
Sentence 1: Determining Cases of Scenarios to Improve Coverage in Simulation-based Veri.cation Shuo Yang1 Robert Wille1,2 Rolf Drechsler1,2 1Institute of Computer Science, University of Bremen, 28359 Bremen, Germany 2Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany {shuo,rwille,drechsler}@uni-bremen.de ABSTRACT Functional veri.cation of complex designs is still dominated by simulation-based approaches.
Sentence 2: coverage­driven Veri.cation (CDV) is well acknowledged and applied in industry.
Relationship: entailment
Domain: Hardware
Sentence 1: In order to add noise to our simulations we considered the meth­ods described in [10] and [19].
Sentence 2: we generated additive white Gaussian noise (AWGN) with 0 mean and 10mV standard deviation (a reasonable value for a 22nm technology node), RTS noise with values of the amplitude equal to 50mV , and we con­sidered theFast Slow corner library that represents theworst-case scenario.
Relationship: entailment
Domain: Hardware
Sentence 1: The nondeterministic behavior is provoked by the usage of the dedicated carry lines in FPGAs over a given threshold of 89%.
Sentence 2: our experiments suggest that in order to obtain a good entropy source inside a Xilinx FPGA, it is sufficient to use the carry chain over 89% and to place the rest of the logic blocks in the same region (around the carry line).
Relationship: entailment
Domain: Hardware
Sentence 1: Since the fabric constraint has been employed in the map­ping process, we can realize that the consecutive mapping of different bits, e.g., 01 (1 after 0) or 10 (0 after 1), creates the pitfall of invalid path creation during expansion.
Sentence 2: if we expand, using short edge in this work, at the second level of the mapping of 01 (1 after 0) or 10 (0 after 1), an invalid path will occur.
Relationship: entailment
Domain: Hardware
Sentence 1: Therefore, in order to obtain the maximum number of localized arrays, we need to eliminate these two kinds of con.icts.
Sentence 2: we need to determine a proper direction for each edge in this array1 loop1 array1 loop1 array1  loop1 array2 loop2 array2 loop2 array2 loop2 array3 loop3 array3 loop3 array3 loop3 array4 loop4 array4 loop4 array4 loop4 (a) (b) (c) array1 loop1 array2 loop2 array3 loop3 loop3 Figure 6: Global Optimization.
Relationship: entailment
Domain: Hardware
Sentence 1: flag = false repeat if RLL(X) # tagp go to L flag = RSC(X, [p, seqp]) until flag L: if (flag) Implementing read, write It is straightforward to extend our algorithm in Figure 2 to implement read and write operations in addition to LL, SC and VL operations.
Sentence 2: the implementa- tion of Write(p, &#38;#169;, v) is the same as the implementation of SO(p, (9, v) with the following changes: replace the CAS on Line 8 with write(X, [p, seqp]) and remove Lines 12 and 13.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition to error counts, the BG systems also record infor­mation on the mechanisms that were used to correct errors, which we can use as additional clues regarding the nature of errors.
Sentence 2: both BG/P and BG/L provide separate log messages that allow us to distinguish multi-bit errors, and BG/P also records in­formation on chipkill errors (i.e.
Relationship: entailment
Domain: Hardware
Sentence 1: Some interesting observations have been established dur­ing the error simulation phase: The model checker can increase the length of the test sequences generated starting from one witness.
Sentence 2: it can produce a witness W of length L and other witnesses, for the same rule, which include W , but are longer than L. This extra e.ort in the generation of further witnesses is useless since, such longer test se­quences never increased, in our experiments, the error coverage.
Relationship: entailment
Domain: Hardware
Sentence 1: 3) Formal veri.cation of quality: In ASLAN, we utilize formal veri.cation methods to guarantee that the safety and liveness properties described above are preserved during syn­thesis.
Sentence 2: we employ time frame expansion, a technique widely used in sequential circuit analysis and veri.­cation, on the SQCC to verify the validity of the approximate circuit.
Relationship: entailment
Domain: Hardware
Sentence 1: Let y be a circuit node, val be a functional requirement, and t be a temporal requirement.
Sentence 2: the Boolean function TCF(y=val, t+) characterizes the set of input vectors that, when evaluated, can cause node y=val to be stable later than time t. given an input vector x, the Boolean function TCF(y=val, t+) is equal to 1 if and only if node y=val is stable later than time t when input vector x is applied.
Relationship: entailment
Domain: Hardware
Sentence 1: G (x, z, x', z') - j.µ(s+ j.e )G (x, z, x' z') = 0, i > 0, z = 0 (2) i iii the point (0, z ), while the second one represents the effect of an opposing current (negative sign) lying at the point (0, -z -2/.).
Sentence 2: solving (1) and (2), using continuity at the interface the effect of the substrate is represented, in this boundaries between different regions, results in an integral approximation, by a single image of the source line current.
Relationship: entailment
Domain: Hardware
Sentence 1: Different from the motion of doping front in the solid­state memristor, the domain-wall movement in the spintronic memristor happens only when the applied current density (J) is above the critical current density (Jcr) [12][13][14][15][16] [17][18].
Sentence 2: gv = 0 when J < Jcr in Eq.
Relationship: entailment
Domain: Hardware
Sentence 1: To simplify our validation approach, we only consider samples where the output levels are greater than 0.9 Vdd or less than 0.1 Vdd since any output values greater or less than those values can be thought of as being in steady-state.
Sentence 2: comparisons are made only when the output voltage from the noise-free inverter is at Vdd or GND.
Relationship: entailment
Domain: Hardware
Sentence 1: Prefetches to open banks are given priority, prefetched data are brought into the LRU position of the L2 sets, and prefetched commands are given low priority in the memory controller.
Sentence 2: the SRP priori­tizer receives feedback from the memory system and is­sues prefetch commands only if the channels are idle and there is no pending request from the L2 cache.
Relationship: entailment