sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Therefore, for the dual load approach, the data returned by both the .rst load and the second load must be compared with their replicas to ensure the data integrity.
Sentence 2: generally, multiple cache ports can be implemented in four ways: either by conventional and costly ideal mul­tiporting, by time division multiplexing, by inter­leaving the cache through multiple independently­addressed banks, or by replicating multiple single­port copies of the cache [2].
Relationship: neutral
Domain: Hardware
Sentence 1: In the audio domain, Huygens principle is applied by stating that a pri­mary source wave front can be created by secondary audio sources(plane of speakers) that emit secondary wavefronts, the superposition of which creates the original one.
Sentence 2: iNTRODUCTION Today, there are many multichannel audio technologies providing the so-called immersive or 3D-audio, which re­quires various speakers setups, consisting of up to hundreds of speakers.
Relationship: neutral
Domain: Hardware
Sentence 1: Let y = ax where x and y are the register values a0 a3 a0 a1 a0 + a3 a1 ×aa ×a aa a2 a1 a2 a3a2 a3 (a) exam-(b) block diagrams ple of an a-multiplier Figure 1: The circuit for the a-multiplier for GF(24) generated by g(z)= z 4 + z+1 and the block diagrams used for a multiplier of X =(xm-1,...,x1,x0,0,...,0) and Y =(ym-1,...,y1,y0,0,...,0) respectively.
Sentence 2: the universal MSR multiplier produces the product a b of the register values a and b.
Relationship: neutral
Domain: Hardware
Sentence 1: We discuss the use of the generated results in determining the performance of communication links, and discuss system design implications.
Sentence 2: u(z)t)and (1) are normalized in such a way that iU(z)t)i2 ac(z)=ar (z)j ai (z)Ac(z)=Ar (z)j Ai (z)(8)  and form the real-valued long column vectors is the instantaneous optical power.
Relationship: neutral
Domain: Hardware
Sentence 1: TABLE II Slice Areas of the Interconnection Components  Block Size (slices) BRAM % XC2V6000 Router (8bits) 189 0 0,56 NI 121 1 0,36 A router can forward five packets per clock cycle at 150MHz.
Sentence 2: the input controller receives data from the router and sends it to the shared memory to an address defined by the port number of the packet.
Relationship: neutral
Domain: Hardware
Sentence 1: (y =0)/ {(1,x :=a), (1,y :=b), (1,c :=0)} y =0/{} st/{} ject the program (this is typical for compilers of synchronous languages).
Sentence 2: neither (., 0, 1, .e, .e, ¬e) nor (., ., T, n, U, ¬e) is a Boolean algebra.
Relationship: neutral
Domain: Hardware
Sentence 1: HminExtra : The minimum required additional x-directed .eld to keep a given magnet metastable for all input combinations and for any t < tM .
Sentence 2: (a) AF-line moves information; (b) an AF-line has a new input, and an external clocking .eld is used to facilitate re-evaluation of the line; (c) as -30 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 Hx (mT) the .eld is removed, devices relax along their easy axes; (d) Energy landscape of a representative magnet when subjected to different .eld combinations.
Relationship: neutral
Domain: Hardware
Sentence 1: The consequent burdening on the speed of the simulation framework is therefore mitigated.
Sentence 2: available: http://www.eetimes.com/document.asp?doc id=1274512 [18] P. Rosenfeld, E. Cooper-Balis, and B. Jacob, Dramsim2: A cycle accurate memory system simulator, Computer Architecture Letters, vol.
Relationship: neutral
Domain: Hardware
Sentence 1: Power consumption was reduced by 67% at the OTA level compared to the original design (folded topology).
Sentence 2: the more constraints we add, the smaller the interesting con.guration space K. if a constraint is tight, i.e., it either de.nes lower dimensional manifolds for example when the constraint is an equality, or the measure of the manifold is small, the more likely it is to introduce some bias in the sampling mechanism because of the di.culty in selecting points in these manifolds.
Relationship: neutral
Domain: Hardware
Sentence 1: The recent emergence of microcontroller-based platforms like Arduino [2] allow electronic instrument de­signers a relatively easy way to both integrate off-the-shelf sensors, and read and generate signals like MIDI -and the availability (and reliability) of tools like these, is a likely motivation for many researchers and builders to focus their primary efforts on control.
Sentence 2: iNTRODUCTION The work of electronic music instrument developers is closely related to the general development and availability of technology.
Relationship: neutral
Domain: Hardware
Sentence 1: To determine the hazard behavior of a circuit s output, the function is invoked with the primary output gate as its argument.
Sentence 2: in this case, v s evaluation cannot help re.ne the Kung value of w. More precisely, an HF-constraint passed to a gate v,HF(v),is a set of Kung values that v can accept at its input to make the circuit s primary output hazard-free (see Example 3 of Section 3).
Relationship: neutral
Domain: Hardware
Sentence 1: Decoded Filter Cache(DFC)[19] bu.ers the instructions that have small decode widths and high execution frequen­cies.
Sentence 2: [2] Raminder S. Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Kenichi Nitta, Avadhani Shridhar, Koichi Seki, and Katsuro Sasaki.
Relationship: neutral
Domain: Hardware
Sentence 1: As seen from the .gure, for f1, f2 = 2kHz, the value of stable virtual sti.ness increases initially upto 350 Nm/rad compared to the value at B = 0.
Sentence 2: since the focus of present work was higher sampling-rate applications, experiments were conducted at sampling-rates T1 > 1kHz.
Relationship: neutral
Domain: Hardware
Sentence 1: PSD of demodulated output signal for different 3 cut-off frequencies corresponding to a first order filter.
Sentence 2: for instance, according to Figure 3 which illustrates a general form block diagram of a first-order time-mode IIR filter two weighted delayed additions are needed in order to realize the following transfer function: b0+b1z-1 fout = (1) fin 1+a1z-1 In following section, the basic building block used in this work is described.
Relationship: neutral
Domain: Hardware
Sentence 1: Since the length of time when the latch is transpar­ ent thereby capturing input data is very short, its behav­ ior is very similar to an edge-triggered .ip-.op.
Sentence 2: we then performed the Monte Carlo simulation 5000 times to see the quantitative e.ect of within-die process variations on skew; a standard deviation was 15 ps, which is 20% of a target skew, with the minimum and the maximum skew of 24 ps and 126 ps, respectively.
Relationship: neutral
Domain: Hardware
Sentence 1: [3] M. Orshansky and K. Keutzer, A general probabilistic framework for worst case timing analysis, in Proc.
Sentence 2: proof: Without loss of generality, we assume an input skew dis­tribution s = s0+ s1 ·x1+ s2 ·x2 (2) having a mean s0 and sensitivities s1 and s2 with respect two independent standard normal random variables x1 and x2 .
Relationship: neutral
Domain: Hardware
Sentence 1: The head .it also contains source and destination node identi.ers, and the physical memory address of the cache block.
Sentence 2: [30] N. Muralimanohar, R. Balasubramonian, and N. Jouppi, Optimizing nuca organizations and wiring alternatives for large caches with cacti 6.0, in Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, (Washington, DC, USA), IEEE Computer Society, 2007.
Relationship: neutral
Domain: Hardware
Sentence 1: Since the area of a w-bit LCH data path is O(w 2), the area of the divide-and-concatenate architecture shown in Figure 3 is about half of that of a w-bit LCH hash data path shown in Figure 1.
Sentence 2: while the parallel data paths technique using four w-bit LCH data paths incurs 400% area overhead, the equivalent divide-and-concatenate LCH data path using six­teen w/4-bit LCH data paths can reduce the dynamic power consumption to 1/16 without incurring any area overhead.
Relationship: neutral
Domain: Hardware
Sentence 1: To simplify our validation approach, we only consider samples where the output levels are greater than 0.9 Vdd or less than 0.1 Vdd since any output values greater or less than those values can be thought of as being in steady-state.
Sentence 2: furthermore, relaxed safety margins allow more room for designers to aggressively scale down power consumption by lowering the supply voltage or increase circuit performance by clocking at higher operating frequency.
Relationship: neutral
Domain: Hardware
Sentence 1: Also, if it is considered that the smaller loops (3), (6), (7), (10), (11) and (12) are part of larger loops that pass through state S1, then the state S1 is present in all branches, so it can be also be considered a good candidate for a check-point state in FSM B.
Sentence 2: as FPGAs are becoming larger, the time to load an entire bitstream in high density devices (more than 11Mbits of customization cells) are reaching the hundreds of milliseconds.
Relationship: neutral
Domain: Hardware
Sentence 1: Summary of test applications Benchmarks Description gzip compressing a given input file fgrep searching for a given pattern in the files residing in a directory math floating-point calculations bf (blowfish) a symmetric block cipher with a variable length key from 32 to 448 bits crc 32-bit cyclic redundancy check on a file djpeg decoding a jpeg image file qsort sorting a large array of strings in ascending order  Figure 6 represents the measured performance degradation with target performance loss ranging from 5% to 20% at steps of 5%.
Sentence 2: in practice, the error introduced in this way is quite small considering that the memory access time is about two orders of magnitude greater than the instruction execution time.
Relationship: neutral
Domain: Hardware
Sentence 1: It considers data and network secu­rity, leaving physical security out of scope.
Sentence 2: the idea is to do for medical devices what USB and Bluetooth did for personal computing: de­vices conforming to the ICE standard, either natively or us­ing an after-market adapter, would be able to inter operate with other ICE-compliant devices, regardless of manufac­turer.
Relationship: neutral
Domain: Hardware
Sentence 1: While static routing schemes [18][19] use fixed paths and offer no fault resiliency, dynamic (or adaptive) routing schemes [20]-[38] can alter the path between a source and its destination over time as traffic conditions and the fault distribution changes.
Sentence 2: two different core complexities were considered for our analysis: 6×6 (36 cores) and 9×9 (81 cores).
Relationship: neutral
Domain: Hardware
Sentence 1: Next Place Transition: Figure 2 shows the transitions made by groups with sizes 2 and 3, between the top-4 locations visited by the entire student population during the month of July, 2014.
Sentence 2: 2 GruMon System Design GruMon enables similarities between individuals to be computed in near real-time by tapping on space/time in­formation as well as mobile sensor-generated data which detects motion-related activities such as walking, turning, standing still, and .oor level changes, to uncover groups.
Relationship: neutral
Domain: Hardware
Sentence 1: Also, at each iteration of SA process, if a floorplan generated by B*-tree is illegal, this floorplan will be discarded and SA continues on the next iteration.
Sentence 2: if the power value of a certain grid varies from its nominal value due to leakage variations, this variability will propagate to each grid due to spatial correlations, which in turn will contribute to the thermal behavior of the whole system.
Relationship: neutral
Domain: Hardware
Sentence 1: XT4- Jaguar) processors rather than Xeon s. We then use the models to predict the performance of FLASH and HYCOM on this system to answers the question What if all Gather/Scatter operation that would perform faster on the FPGAs were ported and run on them how that would affect overall application runtime?
Sentence 2: even though we eliminated 107 blocks from porting to G/S hardware, we did not lose anything from the 1 ... measured -predicted ... benefits of the accelerators.
Relationship: neutral
Domain: Hardware
Sentence 1: PRELIMINARIES A sequential circuit can be modeled as a circuit graph G(V,E), where V is the set of vertices and E is the set of directed edges.
Sentence 2: in fact, the clock skew schedule (0,-2,-1,0,2) works with clock period Popt = 4 tu if p3,4 is between 1 tu and 5 tu and p1,3 is between 1 tu and 3 tu.
Relationship: neutral
Domain: Hardware
Sentence 1: 3, is easily integrated with mixed-signal smart pixels for image processing in analog domain before digitization [14]-[18].
Sentence 2: since these are pro­duced simultaneously during thefabrication process, thegain can be precisely implemented,except for channel-length modulation ef­fects, which are the dominant cause of non-linear distortions in the circuit.theRCCM ampli.er sgain,showninFig.4,isgivenbythe equation IO W2/L2 1+ .VDS2 = .
Relationship: neutral
Domain: Hardware
Sentence 1: [4] Batchu, R., Skjellum, A., Cui, Z., Beddhu, M., Neelamegam, J., Dandass, Y., and Apte, M. Mpi/ft: Architecture and taxonomies for fault-tolerant, message-passing middleware for performance-portable parallel computing.
Sentence 2: finally, each MPI process sends its communication channel information to the Central Manager, which aggregates the information and returns the aggregated information to all MPI processes.
Relationship: neutral
Domain: Hardware
Sentence 1: Summarizing from the above models, we notice that the foundations of these models are all built on a .rst-order RC circuit and the inherent one-pole characteristic ofthis cir­cuit makes it unable to fully .t with the non-linear output ofa gate, particularly in the nowadays deep submicron tech­nology.
Sentence 2: moreover, based on the second characteristic, the gate model can be in­corporated into the process ofinterconnect delay evaluation seamlessly.
Relationship: neutral
Domain: Hardware
Sentence 1: DCVS XOR Gate Two-Port Network Model of the N tree VDD I1 I4 V1 V4  Matrix Equation  Q Q G12+G15 -G12 0 -G12 0 0 -G15 0 X2 (a) (b) G12+G24+G23+G26 -G23 -G23 -G24 0 -G26 G23+G30+G35 0 -G35 0 (c) I1 -G24 0 -G26 V2 I2 0 -G35 V3 I3 0 -G15 0 V1 0 = I4 G45+G24 0 V4 -G45 -G45 I5 G45+G15+G35+G56 -G56 V5 -G56 G56+G26+G60 I6 0 V6 Figure 5: Example of an arbitrary mesh network requiring matrix solving techniques.
Sentence 2: any exclusivity conditions still apply to each vector in­dividually.
Relationship: neutral
Domain: Hardware
Sentence 1: Since proportional to the MIC flowing through the sleep transistor, By definition, MIC(Ci) is equal to the largest MIC(Ci,Tj) for all j. IMPR_MIC(STi) helps to predict the IR drop more accurately than We present this relationship in EQ(4).
Sentence 2: because of the current discharge balance phenomenon for DSTN shown in Figure 4, the exact MIC(STi) cannot be calculated easily.
Relationship: neutral
Domain: Hardware
Sentence 1: Multiadaptive Bionic Wavelet Transform: Application to ECG Denoising and Baseline Wandering Reduction.
Sentence 2: introducing the diagonal matrix S(k1,k2) .Rn×n de.ned as S(k1,k2)= diag {s1,··· ,sn} (3) with  1 ,k1 =i=k2 si = , 0 , otherwise the quadratic variation of x(k1,k2) can be computed as [x(k1,k2)] = DS(k1,k2)x 2 .
Relationship: neutral
Domain: Hardware
Sentence 1: Brief Announcement: A Framework for Semantic Reasoning about Byzantine Quorum Systems Evelyn Pierce Lorenzo Alvisi D(~partement de Syst~.mes de Communication Department of Computer Sciences Ecole Polytechnique Federale de Lausanne University of Texas at Austin 1015 Lausanne, Switzerland Austin, TX USA evelyn.pierce@epfl.ch Iorenzo@cs.utexas.edu ABSTRACT We have defined a class of shared variables called TS-var~ables that includes those implemented by the various Byzantine quorum system constructions of Malkhi and Reiter, and de- veloped a number of definitions and theorems enabling us to reason about these variables abstractly.
Sentence 2: aPPLICATION TO MASKING QUORUM SYSTEMS Variables implemented by masking quorum systems, as orig- inally proposed in [3], are easily seen to be TS-variables.
Relationship: neutral
Domain: Hardware
Sentence 1: When, the row is no longer needed (or often when a different row is requested), the contents of the row buffer are written back into the original row of bit-cells and then a new row may be accessed.
Sentence 2: by bounding (and tracking) a lim­ited number of pages in write-back mode, we could greatly amplify the effectiveness of both HMP and SBD techniques.
Relationship: neutral
Domain: Hardware
Sentence 1: An idle rank can enter low power modes to save power, but it hasto return to standby mode to serve memory access, thus exiting low power mode introduces performance penalty.
Sentence 2: bank partitioning [15, 16, 26] partitions the internal memory banks among cores to isolate memory access streams of different applications and eliminate the inter-thread interference; it solves the interference as its root and improves DRAMperformance significantly.
Relationship: neutral
Domain: Hardware
Sentence 1: The latency of the carry from the full adder and the sum of the FX1 cell is one and two clock phases, respectively.
Sentence 2: (11) ' -v " r Similarly, the Boolean logic function of c for the various cells are as follows: cFX0 =abde cFX1 =ab +(a +b)de cFX2 =ab(de +f)+def .
Relationship: neutral
Domain: Hardware
Sentence 1: The system can be operated by issuing instructions to the microcontroller through the PCI.
Sentence 2: if the Free Frame list is insuf.cient for the logic that the new algorithm s function is to realize, or is empty, some functions from the FPGA have to be erased so as to accommodate the logic necessary for the functions of the new algorithm whose execution has been requested by the host PC.
Relationship: neutral
Domain: Hardware
Sentence 1: As a result, conventional cache management approaches that treat all memory accesses equally are bound to result in inefficient space utilization and poor performance even for applications with good locality properties.
Sentence 2: innovations in multithreading (SMT [31], HT [15], etc) and system-on-a-chip (SoC) or single-chip multiprocessors (CMP) are changing the nature of platform architecture and execution behavior.
Relationship: neutral
Domain: Hardware
Sentence 1: The development of embedded system techniques [1], [2] and their integration with novel signal processing methods [3], [4] has raised the possibility to devise structurally more refined, non­invasive EEG measurement systems and brain computer Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Sentence 2: figure 2 ­Block diagram of the evolvable structure PowerPC2 generates the new partial bit­streams (saved to the shared RAM) to reconfigure the hidden layer by varying the number of neurons in it.
Relationship: neutral
Domain: Hardware
Sentence 1: We compute two lists of heading deviations Ha and Hb with an entry for each t of the sampling fre­quency in the time interval [t0 - T,...,t0] where t0 is the current time and T is a window threshold.
Sentence 2: the recognition results from only acceleration signals have not been too promis­ing when considering cross device and person performance.
Relationship: neutral
Domain: Hardware
Sentence 1: Although the techniques behind Magnet were devised for topic-based pub/sub, they may be generalized to content­ 1Strictly speaking, the probability of creating a link from node u to node v is inversely proportional to the integral of the probability density function of peer identi.er distri­bution between the identi.ers of u and v in the identi.er space.
Sentence 2: in the worst case sce­nario when subscriptions are completely uncorrelated or un­known or both, the message dissemination costs are no worse than those of name-independent DHT systems.
Relationship: neutral
Domain: Hardware
Sentence 1: In the 10nm technology node used, the Metal-2 pitch was assumed to be M2pitch = 48nm, which corresponds to a 75% scaling from the 16nm node [14].
Sentence 2: du, Q. Ma, H. Song, J. Shiely, G. Luk-Pat, A. Miloslavsky, and M. D. Wong, Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography, in Proceedings of the 50th Annual Design Automation Conference.
Relationship: neutral
Domain: Hardware
Sentence 1: Figure 4 compares a subset of the results from Figure 3 with miss counts from alternative cache configurations, including the IIC.
Sentence 2: the victim cache 111 30000 40000 50000 60000 70000 Misses PCDB lru 128 lru 256 lru 512 opt 128 opt 256 opt 512 150000 200000 250000 300000 Misses DR AW 200000 250000 300000 350000 400000 Misses SPECWEB 0 10000 20000 4 8 16 32 64 128 256 FA Ass ociativity 0 50000 100000 4 8 16 32 64 128 256 F A As s ociativity 0 50000 100000 150000 4 8 16 32 64 128 256 FA Associativity TPCC TPCC_LONG OLTP1W 600000 160000 2.5E+07 500000 120000 140000 2.0E+07  400000   200000 300000 Misses 60000 80000 100000 Misses 1.0E+07 1.5E+07 Misses 40000 100000 20000 5.0E+06  0 0 4 8 16 32 64 128 256 FA 0.0E+00 4 8 16 32 64 128 256 FA As s ociativity Associativity Associativity  Figure 3.
Relationship: neutral
Domain: Hardware
Sentence 1: This basis dependency turns out to be important also for universal .eld multiplication.
Sentence 2: the inputs to the multiplier are A=(AM-1,AM-2,...,A1,A0) and B =(BM-1,BM-2,...,B1,B0) whose register values are M-1 M-2 10 a = AM-1a+ AM-2a+ ...+ A1a+ A0aand = BM-1aM-1 + BM-2aM-2 b + ...+ B1a1 + B0a0 respectively.
Relationship: neutral
Domain: Hardware
Sentence 1: Modeling Covariance with Kernel Functions Consider the covariance function speci.ed in Equation 3.
Sentence 2: d. Modeling Radial Variation A key contribution of this work is the extension of Gaus­sian process modeling over Cartesian coordinates to a joint Cartesian-radius space, capturing our intuition that wafer variance is often radial.
Relationship: neutral
Domain: Hardware
Sentence 1: 120100  90 100 80 % Energy Consumed in Datapath Components % Energy Consumed in Pipeline Stages 70 60 50 40 30 20 80 60 40 20 10 0 tomcatv btrix mxm vpenta adi dtdtz bmcm psmoo eflux amhmtm (b) Figure2:Energydistribution(%)of(a)themajorenergyconsumingdatapathcomponentsand(b)the pipelinestages.ThememorypipelinestageenergyconsumptiondoesnotincludethatoftheICacheand DCache.
Sentence 2: eNERGY DISTRIBUTION Withtheemergenceofenergyconsumptionasacriticalcon­straintinsystemdesign,itisessentialtoidentifytheenergy hotspotsofthesystemearlyinthedesigncycle.Therehas beensignifcantworkonestimatingandoptimizingthesys­tempower[7].manyhavefocusedonestimat­ing/optimizingonlyspecifccomponentsofthesystemand mostdonotcapturetheintegratedimpactofcircuit,archi­tecturalandsoftwareoptimizations.Further,mostexist­inghigh-levelRTLenergyestimationtechniquesprovidea coarsegrainofmeasurementresultingin20-40%errorrela­tivetothatofatransistorlevelestimator[2].Bycontrast, SimplePowerprovidesanintegrated,cycle-accurateenergy estimationmechanismthatcapturestheenergyconsumed  97 Program Source #ofArrays InputSize(KB) InstructionCount DcacheMissRates tomcatv Specfp95 9 119 4,868,048 0.182 nasa7/btrix Specfp92 29 4,312 44,430,039 0.167 nasa7/mxm Specfp92 3 120 47,168,707 0.112 nasa7/vpenta Specfp92 9 114 2,274,945 0.143 adi Livermore 6 241 6,062,860 0.098 dtdtz(aps) PerfectClub 17 1,605 42,119,337 0.135 bmcm(wss) PerfectClub 11 126 89,539,244 0.105 psmoo(tfs) PerfectClub 1 204 16,955,980 0.077 eflux(tfs) PerfectClub 5 297 12,856,306 0.114 amhmtm(wss) PerfectClub 10 125 89,145,635 0.039 Table1:Programsusedintheexperiments.Dcachemissratesarefor1Kdirectmappedcacheswith32byte linesizes.Instructioncountisdynamicinstructioncount.
Relationship: neutral