sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: In contrast to systems that are based on charge transport, spin dynamics opens the possibility for non­volatile low dissipation memory devices, since charges do not need to be in motion for information transport.
Sentence 2: for the recent, and not yet completed, benchmarking exercise, a set of criteria has been defined which can be adapted but must include gain, signal/noise ratio, non-linearity, speed, power consumption, architecture and integratability, efficiency, tolerances and manufacturability as well as the timeline of each potential technology.
Relationship: neutral
Domain: Hardware
Sentence 1: The channel encoder uses a convolutional code with 64 states, non-systematic, non-recursive, and using the Maxlog MAP (BCJR) algorithm to encode b into c .
Sentence 2: the variation between SQRD and MMSE-SQRD is due to the division of the vector multiplications and subtractions performed in two steps, to reduce the increase in hardware.
Relationship: neutral
Domain: Hardware
Sentence 1: This is due to the diffusion height of the minimum-sized cell being signi.cantly less than the row height of the standard cell.
Sentence 2: vmin varies across different cell types {INV, NAND2, NAND3, NAND4, NOR2, NOR3, NOR4} and strength {X0, X1, X2, X3}.
Relationship: neutral
Domain: Hardware
Sentence 1: Using layered communication architecture and standardized IIPs can fulfill these requirements.
Sentence 2: for a total wire width of 15 µm, using copper wires with technology dependent constant ß=1.65 , minimum wire width w = 0.1 µm, minimum distance between two adjacent wires s = 0.1 µm, distance between the signal wires and ground plane h = 0.2 µm, wire thickness t = 0.21 µm (giving an aspect ratio of 2.1), the optimal number of wires is 19 if ideal drivers are assumed and no repeaters are used.
Relationship: neutral
Domain: Hardware
Sentence 1: The key points are 1) a context-based mode prediction method to reduce the number of candidate modes 2) a sub-sampling based acceleration technique for integer Hadamard transformation 3) a reconfigurable intra-predictor circuit that generate predicted blocks with every mode selected by 1) in a sequential manner.
Sentence 2: 3.3 3-stage Job Interleaving Scheme The 66% theoretical computation reduction guaranteed by the proposed algorithm certainly comes at some cost in terms of processing time and hardware resource.
Relationship: neutral
Domain: Hardware
Sentence 1: Higher bias currents result in faster operating speeds at the expense of increased power consumption.
Sentence 2: the output delay of the MCML gate is determined by Cload · Vswing .p = (1)Ibias The logic function is realized by a network consisting of multiple levels of nMOS transistors, which is determined by the binary decision diagram (BDD) corresponding to the Boolean function being realized.
Relationship: neutral
Domain: Hardware
Sentence 1: In the implementation of the 8­bank CIM, the line remains in its initial location as long as it is not evicted from the cache.
Sentence 2: traditionally, uniprocessor microarchitectures partitioned the cache based on content (e.g., Instructions Cache versus Data Cache in the Harvard architecture) and hierarchically (e.g., cache levels: L1, L2, etc.).
Relationship: neutral
Domain: Hardware
Sentence 1: The trace self-concomitance s(b, T ) of a basic block b is a measure of how clustered consecutive executions of the block b are, and is de.ned as: s(b,T )= .
Sentence 2: loop analysis has several drawbacks: (i) the structure and relationship of loops can be very complex; (ii) this structure can sig­ni.cantly vary for different inputs; (iii) the precise structure of loops is irrelevant for the placement of instructions in the SPM because only relative (temporal) proximity of executions matters, rather than the precise order of these instructions (as provided by the loop analy­sis) [12, 13, 14, 15].
Relationship: neutral
Domain: Hardware
Sentence 1: 3(b), the three functions 1DLEDMEM, READDMEM 8 >>< currentR DR implementation register and W R1T EDMEM need to be de.ned, capturing for given writeR S. E stage will write address and data, if the respective transaction is issued on the R destR S.IR write destination data memory interface.
Sentence 2: [18] R. Hosabettu, G. Gopalakrishnan, and M. Srivas.
Relationship: neutral
Domain: Hardware
Sentence 1: If a mesh tile is completely covered by the real TSV shape, Rz and Rx/y are directly obtained referring to the XY-mesh and Z-mesh size.
Sentence 2: figure 2(c) is a plot showing the magnitude of current density distribution in the XY planes, when Z=30.0um, 29.0um, 1.0um, and 0.0um.
Relationship: neutral
Domain: Hardware
Sentence 1: Copyright 2012 ACM 978-1-4503-0781-9/12/01 ...$10.00.
Sentence 2: formally, let xi be the local feature vector associated with the ith window cell of the activity signal x,and let Pj denote the jth primitive (cluster) out of m prim­itives (clusters) in the vocabulary.
Relationship: neutral
Domain: Hardware
Sentence 1: Sections 6 and 7 show experimental results.
Sentence 2: in general, the number of terminals connected by m pin nets can be calculated recursively to give: p 1 p 1 Tm= km 1) m) (14) () (( net in an FPGA array of N clusters, the total number of m pin nets is given by:p 1 p 1 ((m 1) m) Net m ---------------------------(15) () kN ------------------------­ m Note that this does not account for the number of I/O nets on the periphery of the chip.
Relationship: neutral
Domain: Hardware
Sentence 1: Because the XOR constraints necessary for evenly sensitizing a design are small with respect to the size of the design, our SAT en­gine experiences little performance degradation, compared to techniques where large XOR constraints are added to a SAT instance.
Sentence 2: to stimulate a design uniformly, we generate small ran­dom XOR constraints that involve inadequately stimulated signals and derive stimuli with a SAT solver.
Relationship: neutral
Domain: Hardware
Sentence 1: The rationale in this case is to add a number of new tests in the set such that they still detect the targeted transition faults but through paths that have not been sensitized by the original test set.
Sentence 2: columns 2, 7, and 12 show the size of the original test set (equal to the number of test functions generated) for subcircuits Cd, Cd-1, and Cd-2, respectively.
Relationship: neutral
Domain: Hardware
Sentence 1: The reduced parasitics for interconnects can further significantly simplify the circuit and power distribution network design for high perform­ance applications.
Sentence 2: memory Integration Technology The main potential benefits of 3-D integration include reduced overall footprint, and reduction of overall wiring length for a given system configuration, with the associ­ated improvements in propagation delay and energy per 1b: Wafer-level 978-3-9810801-3-1/DATE08 &#38;#169; 2008 EDAA  1126 interconnect switching transfer, as much as 54% and 51% respectively by one estimate [4].
Relationship: neutral
Domain: Hardware
Sentence 1: These challenges include: Increased resolution -While 1080p is a common na­tive resolution for many displays, this particular spa­tial format is popular because it matches current high­de.nition video standards.
Sentence 2: in this case, the input vector would instead have a 1 in the third value, and the coe.cient matrices would be updated with a w, tx, and ty values to choose and translate the window.
Relationship: neutral
Domain: Hardware
Sentence 1: This panel brings together specialists from industry and ESL tool houses to discuss whether current ESL tools available are usable and meeting the requirements of the industry.
Sentence 2: kalekos, CoWare, USA Pierre Paulin, ST Microelectronics, Canada Mike Meredith, Forte Design Systems, USA Masami Aihara, Toshiba, Japan Shawn McCloud, Mentor Graphics, USA Krisztian Flautner, ARM, UK Categories &#38; Subject Descriptors: B5.1, B5.2, B6.3, B7.2, C.0, J.6 General Terms Design Keywords Electronic System Level (ESL) design, behavioral and system synthesis, electronic design automation Copyright is held by the author/owner(s).
Relationship: neutral
Domain: Hardware
Sentence 1: Moreover the timing analysis results show that this architecture has a worst-case processing rate of 465 VGA frames per second, far exceeding the throughput necessary to decode VGA resolution videos in real time.
Sentence 2: the architecture presented in [8] proposes the use of a 4-tap diagonal FIR filter for interpolation luminance instead of the 2-D 6-taps filters generating losses in quality in the decoded video.
Relationship: neutral
Domain: Hardware
Sentence 1: 0.1 0.1 0.1 0.1 0.1 0.1 0.01 0.1 1 20  >40 40 Vdd =1 V, Vripple = 100 mV, tr = 100 ps, tf = 300 ps, tch = 400 ps Note that Cr as determined by (10) increases rapidly dec with the e.ective radius based on the target impedance, becoming in.nite at dmax .
Sentence 2: v f = V f (5) C load = 0.9 Vdd.
Relationship: neutral
Domain: Hardware
Sentence 1: CONCLUSIONS In this paper, we developed elastic RESET (ER) to con­struct non-2n-state MLC cells.
Sentence 2: if we  (a) mcf (b) libquantum (c) astar (d) xalancbmk (e) milc (f) bzip2 (g) lbm (h) wrf (i) gcc-200i (j) gcc-type Figure 12: Compression ratio of the whole execution (X-axis is normalized execution percentage).
Relationship: neutral
Domain: Hardware
Sentence 1: Processor 8-core, 4GHz, Intel atom-like cores private, 32KB/32KB, 4-way, LRU, I/D-L1 128B line size, write-back private, 2MB, 4-way, LRU L2 128B line size, write-back DRAM private, 32MB, 8-way, LRU Cache 128B line size, write-back 32GB, 128B line size, 32 banks, 4 ranks, PCM 8/32-entry read/write queues Main Read .rst, write burst when full Memory 4000-cycle write, 500-cycle read SET: 4000 cycles [15], 90µW/bit, 13.5pJ/bit [11] RESET: 500 cycles [15], 480µW/bit, 19.2pJ/bit [11] Table 3: Baseline Con.guration The simulated workloads are summarized in Table 4.
Sentence 2: since WoM-SET performs one proactive-SET operation for ev­ery other write to the same line, there are two types of writes: i) WoM-SET-1 represents the write using the 1st-write code.
Relationship: neutral
Domain: Hardware
Sentence 1: The correction ratio can be calculated as: E 4C V 2 4C tg -total tg DD tg = 2 = (13) E (C + C )V C + C total G P DD G P This correction ratio is proportional to the size of the TG, since Ctg itself is proportional to the size of the TG.
Sentence 2: figure 4 shows an example of the balanced (i.e., CG=CP) charge recycling operation when transitioning from sleep to active mode for an inverter chain in 70nm CMOS technology generated in HSPICE.
Relationship: neutral
Domain: Hardware
Sentence 1: For large designs, OBDD representation for the entire transition relation usually cannot be constructed.
Sentence 2: 2 Proceedings of the Design,Automation and Test in Europe Conference and Exhibition (DATE 03) 1530-1591/03 $17.00 &#38;#169; 2003 IEEE when the ATPG continued backtracking to .nd the fourth, .fth and the sixth solutions (the three lying under d the right branch of node 10, Soln#4, Soln#5 and Soln#6 ), we observed an interesting phenomenon: the same partial assign­ fFTnTFnFnment for decision nodes 1101}is repeated.
Relationship: neutral
Domain: Hardware
Sentence 1: [Tha1-99, Tha2-99] in that these performance gains are achieved through user-de.ned hints and implementation-de.ned directives, to communicate the anticipated application I/O pat­tern(s) to the underlying .le system which has the capability to exploit this additional knowledge.
Sentence 2: figure 1: GPFS block allocation used by MPI-IO/GPFS in data shipping mode (using the default stripe size) I/O agents are multi-threaded and are also responsible for combining data access re­quests issued by all participating tasks in collective data access operations.
Relationship: neutral
Domain: Hardware
Sentence 1: Restricted K bounds 6 Conclusions The wiring congestion is a very important design factor which directly impacts the time-to-market of complex System-on-Chip designs, and must be considered both globally in logic synthesis, and locally in physical design.
Sentence 2: gLSVLSI 03, April 28-29, 2003, Washington, DC, USA.
Relationship: neutral
Domain: Hardware
Sentence 1: In that latter work, the control algorithm used the cost of a set of cache references as an indirect indicator of the processor performance.
Sentence 2: unique to the Accounting Cache is that although a cache con.guration is selected during a time interval it is possi­ble to measure the hit/miss rate of any other con.guration, and consequently it is possible to evaluate the cost of a set of cache references for all con.guration even although only one of the con.gurations have been used during an inter­val.
Relationship: neutral
Domain: Hardware
Sentence 1: The 200-cycle interval is shown here to illustrate the potential high-frequency di/dt e.ects from a .ne-grained perspective.
Sentence 2: the com­bined weight of the sliding window, 1 = 3.7 The queue con­troller will therefore permit both module gating events to occur, since the threshold constraint is not violated in this case.
Relationship: neutral
Domain: Hardware
Sentence 1: The key idea to guarantee privacy is obfuscated program execution in hardware; to evaluate an arbitrary in­struction, Ascend gives o. the signature of having evalu­ated any possible instruction.
Sentence 2: second, the user sends its encrypted private inputs encryptK (xuser), a pub­lic running time T and a public number of bytes to in­clude in the .nal result S. At the same time, the server
Relationship: neutral
Domain: Hardware
Sentence 1: Unlike tradi­tional packaging in which the die is attached to the substrate face up and the connection is made by using wire, the sol­der bumped die in .ip-chip BGA is .ipped over and placed face down, with the conductive bumps connecting directly to the matching metal pads on the laminate substrate [13].
Sentence 2: the design of such a system would make it nearly impossible to detect the transmitter through visual inspec­tion or by netlist extraction.
Relationship: neutral
Domain: Hardware
Sentence 1: Abstract In this paper, we present a radiation-hardened digital design approach.This approach is based on the use of Code Word State Preserving (CWSP)elements at each .ip-.op of the design, and leaving the rest of the designunaltered.
Sentence 2: in Section 3.1, we discuss,by way of introduction, the design of the CWSP element, and explainhow it is utilized in [21, 15].
Relationship: neutral
Domain: Hardware
Sentence 1: However, increasing n from 2 to 32 results in less than 10% reduction in latency.
Sentence 2: we use a 3The simulation setup is described in Section 3.2 oblivious adaptive 40 35 oblivious adaptive  40 35 3030   Latency (cycles) Latency (cycles) Latency (cycles) Latency (cycles) 25 20 15 10 25 20 15 10 5 5 0 Figure 3: Block diagram of a 1K node high-radix 0 folded-Clos network with radix-64 routers.
Relationship: neutral
Domain: Hardware
Sentence 1: Cycle-accurate and circuit simulation results of a wide-issue superscalar processor indicate that: (1) in future CMOS technologies (e.g., 70nm and beyond), cache architectures that exploit bitline isolation can eliminate up to 90% of the bitline discharge, (2) on­demand precharging (i.e., decoding the address and subsequently precharging the accessed subarrays) is not viable in level-one caches because precharging increases the cache access latency, and (3) our proposal for gated precharging to exploit subarray reference locality and precharging only the recently accessed sub­arrays eliminates nearly all of bitline discharge in nanoscale CMOS caches with only a 1% of performance degradation.
Sentence 2: the energy overhead in switching the precharge devices is expected to dramatically decrease compared to the static pull-up s bitline discharge for future CMOS technologies.
Relationship: neutral
Domain: Hardware
Sentence 1: However, in our case, the RF energy conversion is a transient process in which the output power capacitor C2 is charged by the rectified RF energy.
Sentence 2: it has been proved in rectenna design that the RF front end low pass filter following the input antenna serves as a buffer for better impedance matching between the rectifier circuit and antenna and blocks the flow of harmonic energy from the rectifier back to antenna [4]; both effects are crucial for the best efficiency.
Relationship: neutral
Domain: Hardware
Sentence 1: There are UPDATE operations to component i occurring in three consecu­tive phases.
Sentence 2: at the next step, some processes may also write t +1mod 4 to T [i].no process reading t +1 mod 4 from T [i]will write to T [i]during this phase, since the parity of t +1 mod 4 matches the parity of the phase.
Relationship: neutral
Domain: Hardware
Sentence 1: Abstract Reverse scaled LC transmission lines are an effective alternative to on-chip global interconnects which severely limit the chip performance in nano-CMOS technologies.
Sentence 2: we define ratios ar1 and ar2 as ar1 w / hd (5) ar2 t / hd (6) We compute w, hd and t for a given cross sectional area (A) of the interconnect as follows, (7) w A u ar1 / ar2  Fig 3.
Relationship: neutral
Domain: Hardware
Sentence 1: Furthermore are area and clock frequency measures shown which were obtained through further logic synthesis of the controller models for a XILINX Virtex V100CS144-4 using Syn­opsys FPGA II compiler.
Sentence 2: in the next step a trans-  s == p1 s == p2 G1 G1 G2  e e .. 12  (a) FA graph with labeled e edges (b) condensed FA graph without e edges Figure 6: Transformation of FA graph with e transitions into a condensed FA without e transitions formation is applied to the two automaton graphs which gener­ates equivalent graphs without e-transitions.
Relationship: neutral
Domain: Hardware
Sentence 1: The general max S problem with arbitrary path delays cp determined by AATs and RATs can be reduced to the case of identical cp by adding a super-source and a super-sink connected respectively by constant­ delay edges to all timing sources and sinks.
Sentence 2: e2p de F =max=max(1) pp cp cp Here de denotes the signal delay along edge e of the timing graph and can also be written as de =dij(xi;yi;xj;yj),making F a function of vertex locations via convex delay models for individual edges.10 Common edge delay models can be based on linear or quadratic (squared) edge wirelength, or on Elmore delay (see Section 2.3).
Relationship: neutral
Domain: Hardware
Sentence 1: [2] Yao, X. and Higuchi, T., Promises and challenges of evolvable hardware, IEEE Transactions on Systems Man and Cybernetics Part C-Applications and Reviews, 1999, 29(1):87-97.
Sentence 2: for example, an evolved individual with 4 inputs and 3 outputs, the fitness value of each output of parents is 14/16, 9/16, 15/16 and 9/16, 12/16, 11/16.
Relationship: neutral
Domain: Hardware
Sentence 1: [5] G. Iapichino, C. Bonnet, O. del Rio Herrero, C. Baudoin, I. Buret, A Mobile Ad-hoc Satellite and Wireless Mesh Networking Approach for Public Safety Communications , 10th International Workshop on Signal Processing for Space Communications, 2008.
Sentence 2: finally, Windows Media Encoder has been installed on the laptop-A to send test video by means the emulated link connecting the aerial vehicle with the Mobile Ground Station .
Relationship: neutral
Domain: Hardware
Sentence 1: These more frequent interrup­tions with multiplexing will perturb the program more than the less frequent interruptions ofDTW(Sum): in the worst case these interruptions will perturb the very behavior that the performance analyst needs to understand.
Sentence 2: this evaluation is de.cient because performance analysts often wish to investigate the relationship between the time-varying behavior of metrics; this section explores whether or not multiplexing enables reasoning across metrics.
Relationship: neutral
Domain: Hardware
Sentence 1: Both architectures presented by [7] and [8] support variable block size.
Sentence 2: y1 =(A + F)+ 44[(C + D)-(B + E)]+ 4(C + D)-(B + E) (5) The second step of the processing unit calculates the half-pixel luminance value applying equation (2) to y1 if the control unit indicates the interpolation of V or H Type half-pixels, or equation (3) if it indicates the interpolation of D Type.
Relationship: neutral
Domain: Hardware
Sentence 1: While the original Tomasulo architecture only scheduled instructions via the issue queue read from instruction mem­ory, enabling faulty instructions to re-execute will require a mechanism toreintroduceacompletedinstructionbackinto the execution engine.
Sentence 2: given this, the correct and reli­able operation of these microprocessors will become a more prominent objective in order to satisfy consumer experience levels.
Relationship: neutral
Domain: Hardware
Sentence 1: Table3:PerformaneComparisonforPratialExamples AppliationSpeedupahieved Examplesbyoursuggestion I.33 IIRFilterI.27 V.Conlusions Inthispaper,animpreiseomputationisnewlypro­posedasafastdataomputingtehniqueandwehave presentedanewomputationarhiteturesupportingthe impreiseomputation.Comparedtoonventionalarhi­teture,thesuggestedarhiteturehasfuntionalunits havingfasterproessingtimeduetotheimpreiseom­putation.Furthermore,tomaximallyexploitthevari­ousproessingtimeoffuntionalunits,anasynhronous iruitdesignisinorporatedintothearhiteture.To showthepotentialperformanebeneftsofourarhite­ture,simulationresultsarealsopresented.Animpreise omputationandtheproposedarhitetureareexpeted tobeusedefetivelyinthedataintensiveproessingofa miroproessor,adigitalsignalproessororamultimedia proessor.
Sentence 2: vI.Aknowledgements ThisworkhasbeensupportedinpartbytheKorea SieneandEngineeringFoundationundergrant20006­302­01­2andbytheKAIST/K­JISTIT­21Initiativein BK21ofMinistryofEduation.
Relationship: neutral
Domain: Hardware
Sentence 1: Fundamentals, E82-A(11):2499 2504, 1999.
Sentence 2: {SI,SO} starting with SI and ending with SO and set of covered tests C .T Phase 1: Run the multi-fragment greedy algorithm (Figure 2) to get scan chain fragments P0,...,PD+1 and set of covered tests C. Phase 2: Construct a complete graph G' with vertex set {SI,SO}.
Relationship: neutral
Domain: Hardware
Sentence 1: proposed an an­alytical model in [5] to predict whether interconnections can be successfully routed through when given an FPGA archi­tecture.
Sentence 2: when the long wires at channel 1, 2 and 3 are all routed, although these channels are the shortest paths for the interconnec­tion, the interconnection will traverse to channel 4, which Figure 3: (a) An abstract view of both direct and fringed interconnections in a link after the place­ment and routing steps.
Relationship: neutral
Domain: Hardware
Sentence 1: We show that our approach is able to achieve the same level of accuracy with at least two orders of magnitude reduc­tion in computation time and an order of magnitude less memory re­quirements.
Sentence 2: for example, if the input mesh is complex with 5,000 vertices, the number of modes mixed is bounded by 1000 instead of the earlier 3N = 15, 000 which isa substantial performancegain.
Relationship: neutral
Domain: Hardware
Sentence 1: For instance, in H.264/AVC, there are only nine 4x4 intra candidates [25].
Sentence 2: finally, considering Transpose-2T architecture, the en­ergy results were close for all syntheses, with a maximum varia­tion of 7.9% reduction, when comparing maximum frequency TE method with the target throughput FHT method.
Relationship: neutral
Domain: Hardware
Sentence 1: D The algorithm is e.cient not only from a theoretical point of view but also in practice: A run on 3.6 millions circuits and 9 regions take less than 90 seconds (on an IBM P650 with 1.45 GHz).
Sentence 2: finally, Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: neutral