sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Thus, C and D cannot be con.icting and it is impossible to construct two con.ict edges that intersect each other at the points other than the endpoints of the con.ict edges.
Sentence 2: lemma 1 is t (6) D Figure 3: Embedding of Planar CG With Lemma 1, we can prove the following theorem: Theorem 1.
Relationship: reasoning
Domain: Hardware
Sentence 1: Because of the property of exponential wire shape, Wsource is always the largest width and Wsink is the smallest one.
Sentence 2: we have the relationship Wmin = Wsink = Wsource = Wmax (18) In reality, we can setup the width constraints, discretize the allowable range of the wire width, and assign to Wsource and Wsink di.erent values to get di.erent wire shaping solu­tions.
Relationship: reasoning
Domain: Hardware
Sentence 1: This unidi­rectional signal is caused by QCA s clocking scheme, where an electric .eld E created by underlying CMOS wire is prop­agating uni-directionally within each logic block.
Sentence 2: we assume the placement, the input to our QCA routing prob­lem, is done based on a K-Layered Bipartite Graph (KLBG).
Relationship: reasoning
Domain: Hardware
Sentence 1: A task Ti can never exploit the -WTi, (D-WRTi), STi dynamic slack which is obtained from its subsequent tasks (i.e., Outputs: the tasks Ti+1 through Tn).
Sentence 2: those tasks that come later -.i and di in a schedule have more chance to gain larger dynamic slacks as compared to the tasks that come earlier in the schedule.
Relationship: reasoning
Domain: Hardware
Sentence 1: In fact, the size of a site is really the size of the layout area, divided by the number of cells, thus it is the average size of a cell and the interconnect that may be associated with it.
Sentence 2: all that is captured by the notion of a RG site is the idea that the leakage due to one cell would on average be spread out or allocated to the layout area of a single site.
Relationship: reasoning
Domain: Hardware
Sentence 1: Now, from condition (I) in the PSLP-FV problem formulation of equation (12), a minimum decrease in the setup time of the i th soft-edge FF-set t (w ,v) si, i which meets the long-path constraint in the i th stage of the linear pipeline, will produce the minimum increase in the power dissipation of the i th soft-edge FF-set P (w ,v) .
Sentence 2: the FF i, i optimal solution is achieved by utilizing the smallest possible transparency window sizes which prevent setup time violation.
Relationship: reasoning
Domain: Hardware
Sentence 1: CLUSTERED VOLTAGE SCALING Inthissetionwewilldesribethedetailsofthelustered voltagesalingoriginallypresentedUsamiandHorowitz([1]): Itsbasiideawasthatofpreservingalusteredstrutureas ameanstobothahievesimpliityofalgorithmandgood qualityofresults.Asinallvoltagesalingalgorithms,this proposaltriestoreduevoltagesupplylevelforthosegates thatarenotritialfortheiruitperformane(i.e.gates thathaveasuÆientlyhighslak),withoutmodifyingsizes ofgatesandiruittopology.Themethodwasoriginally proposedforadual­voltagesenariothatseemstobethe mostviablefromtehnologialpointofviewasdisussed intheprevioussetion.Inthefollowing,wewillindiate withVandVrespetively,thehighandlowvolt­agelevels.Thealgorithmtriestooptimizepoweronsump­tionwithoutworseningperformanefgures,andtherefore ompareswiththeaseofallellssuppliedwithV.
Sentence 2: thisaseprovidesthemostperformingsolution,duetothe monotonialbehavioroftheurvesdelayversussupplyvolt­age.Thealgorithm'soreisastrategytosuessivelysup­plyellswithVwhilemaintainingthemaximumperfor­mane.Themainproblemofamultiplevoltageshemein anetlistonsistsinthepossibilityofonnetinggateswith the"wrong"relationshipsofvoltagelevels.Asamatterof fat,whileaonnetionbetweenaellsuppliedbyV toaellsuppliedbyVdoesnotintroduepartiular problems,theoppositeisnotaeptable.Thisisduetothe fatthatalogial'1'orrespondstoaneletriallevelof V,thatmightbetoosmalltodriveorretlythefol­lowinggate.Theonsequeneofthisonnetionisthusa signifantdegradationofnoisemargins,and,possibly,the introdutionofanon­valideletriallevel(thegatedown­streammaynotinterpretitasa'1'),aswellassomestati dissipationintheseondgate(seeFigure1).Sinethis typeofonnetionsannotbeeliminatedinadual­voltage sheme,theuseoflevelshiftersismandatorytoompensate theunevenessofvoltagelevels[3,4].Levelshifterstakeas inputslow­voltageswingsignalsandreturnfull­swingsig­nalsasoutputs.Anexampleofatypiallevelshifteris showninFigure1.Eveniftheintrodutionoflevelshifters solvesalltheeletrialproblemsoflow­to­highvoltageon­netionstheydonotomeforfree:Theyintrodueanew soureofpowerdissipation,takemoresilionarea,andan addtothedelayoftheiruit.theyshouldbe addedassparinglyaspossible.
Relationship: reasoning
Domain: Hardware
Sentence 1: We cannot use the previous Handlers originally devel­oped for [15], since the new features introduced with the NetFPGA port cause changes in the Handler-internal struc­ture.
Sentence 2: we created a special Malacoda description for the Web (HTTP) Handler of [15] and stripped from the com­piled VHDL code the functionality speci.cally required for the NetFPGA version of NetStage, thus leaving a version comparable to the original one (which targeted the BEE3 platform).
Relationship: reasoning
Domain: Hardware
Sentence 1: Replacing such loads with a single effective capacitance is very dif.cult.
Sentence 2: the conventional timing library for­mat which stores the data for a cell in 2-D lookup tables (LUT) with indices as input transition time (Sin) and effective load capacitance (Ceff ) and outputs as output transition time (Sout) and gate delay is no longer suf.cient to model a driver.
Relationship: reasoning
Domain: Hardware
Sentence 1: The dual problem (D) is strictly related to the primal la­grangian problem (LP): if a dual feasible solution m is used as a lagrangian multiplier vector, the corresponding opti­mum zu LP (m)equals the value w(m)of the dual solution.
Sentence 2: h c Acm =c (m)?0 =pLP (m)=0 = hcc =zLP (m)=me =em =wD (m) any good dual solution is a good lagrangian mul­tiplier vector.
Relationship: reasoning
Domain: Hardware
Sentence 1: V. VIA CONFIGUREABLE LOGIC BRICK Circuits fabricated using CNFETs have lithographic related variations in addition to the imperfections specific to the CNT technology.
Sentence 2: for designs specific to ASIC implementations we are proposing via-configurable regular Figure 7. sample brick to implement 3-input function[11] TABLE V. FUNCTIONAL YIELD OF BRICKS IMPLEMENTED WITH PARALLEL TUBE, TRANSISTOR STACKING AND HYBRID CONFIGURATIONS FOR DIFFERENT PERCENTAGE OF METLLIC TUBES Brick Configuration Pm =0% Pm =4% Pm =7% Pm =10% Parallel Tube 100.0 99.6 77.5 21.6 Transistor Stacking 100 100.0 97.7 80.5 Hybrid 100 99.6 87.5 53.5 logic blocks approach [11].
Relationship: reasoning
Domain: Hardware
Sentence 1: To minimize the total powerconsumption of the MTCMOS inverter chain, the delayconstraint in (11) must be modified as, f r Delay = max{d , d }= T 20 The objective function of (11) also needs to be modified to model the gate-tunneling current of the sleep transistors in the activemode.
Sentence 2: (15) should be modified as, .
Relationship: reasoning
Domain: Hardware
Sentence 1: Second, Distance-based Cross-Core prefetching may be usedfor multiprogramming with no additional hardware.
Sentence 2: since each DTentry has a context ID, prefetching is based on patterns seen in thesame application (though it might be based on multiple threads).in a scenario where multiple single-threaded workloadsrun, prefetching would only be initiated based on patterns seenwithin cores, as in uniprocessor Distance-based prefetching.
Relationship: reasoning
Domain: Hardware
Sentence 1: Due to the constraints of consumer system integration(formfac­tor, packaging, power, heat), each application or class of applica­tionstill callsforaspeci.ccircuitinorderto .tintotheperfor­mance/powerbudget.Inthat context,being ableto rapidly explore thedesign spacetakingintoaccountthespeci.citiesoftheapplica­tionis a necessity.
Sentence 2: theMPSoCdesign approaches aim .rstly at clearly separating computationfrom communication, us­inginterfaces that are standardized, allowing toquickly exchange one IP by an other and to add or retrieve a processor.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, in minimum cost timing bu.ering, a bu.er insertion may result in many non­dominated (C, W, Q) tuples with the same C value, where Q denotes the require arrival time (RAT).
Sentence 2: in slew bu.ering, at each bu.er position along a single branch,at most |B| new solutions can be generated through bu.er insertion since C, S are the same after inserting each bu.er.
Relationship: reasoning
Domain: Hardware
Sentence 1: That enables the issue of a single request to the memory controller queue; processing of multi-line requests that are directed to the same DRAM page together as a single request in the queue; and, in the end, close the page after completing all of the prefetches.
Sentence 2: multi-line requests: a) improve bandwidth use, b) simplify our priority scheme by executing back-to-back page-related requests, and c) improve our controller e.ciency for closing the DRAM pages.
Relationship: reasoning
Domain: Hardware
Sentence 1: are adjustable through 12 control bits from the shift regis­ters.
Sentence 2: a total of 8 digitized signals pass through four 8x1 multiplexers and the resulting four signals act as con­trolling signals at three 16x1 multiplexers, the outputs of which feed a dependent current source (DCS) for a voltage to current conversion.
Relationship: reasoning
Domain: Hardware
Sentence 1: Sp' } = {1,3,4} corresponds to a recovery sequence {xi}0=i=6 = {0101100}.
Sentence 2: the read-optimal and balanced recovery scheme is symbols d0,1, d2,1 , d5,1 are recovered by row parity, and symbols d1,1 , d3,1, d4,1 are recovered by diagonal parity.
Relationship: reasoning
Domain: Hardware
Sentence 1: In the case of a load/store instruction utilizing the CPSI and CDMI blocks for low-power address transfers, the request to the memory subsystem can be sent at the beginning of the .rst stage, while the data is effectively returned at the end of the subsequent pipeline stage.
Sentence 2: the transactions to the data memory are effectively pipelined and the address calculation logic in the CDMI adds no delay to the memory access time.
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that tr is a function of the input transition time (tin) and the output load.
Sentence 2: the iterative effective capacitance equation for matching any .% point of the gate output transition time can be written as: Exp G t ,, r ,c =c +k .c where c .= c rc eff () (r n p f ) n Exp ()f ª y ln(1 -.)
Relationship: reasoning
Domain: Hardware
Sentence 1: It is obvious that if scheduling and FU allo­cation can be solved exactly for a MSV, the number of cycles with non-maximal FMSVs will be always fewer than or equal to the result with maximal FMSVs that cover the non-maximal FMSVs.
Sentence 2: only maximal FMSVs should be consid­ered under an area constraint.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, if pin pi+1 s y-coordinate is outside of the Steiner range of si, we have to backtrack FST s Fk, k = i - 1 to 2,in Fi from back to front until the distance between pi+1 and tk in x-dimension is larger than that between pi+1 and pi in y-dimension.
Sentence 2: it takes O(m 2) in worse case.
Relationship: reasoning
Domain: Hardware
Sentence 1: In contrast, using a single precision .oating-point notation, high resolution operations are achieved whereas the dynamic range allows the algorithms to operate with both the largest and smallest possible values during the polynomial interpo­lation (40953 and 4E-4, respectively).
Sentence 2: we justify the use of the single precision .oating-point arithmetic (32 bits) instead of the .xed-point notation.
Relationship: reasoning
Domain: Hardware
Sentence 1: If we only con­sider O(n) pairs of vertices, we will have only O(n) Steiner point candidates, which is more ef.cient for the Steiner point selection.
Sentence 2: the bottleneck has become how to choose O(n) pairs of vertices to generate desirable Steiner point candidates, which is our OAVG construction in Section 3.3.1.
Relationship: reasoning
Domain: Hardware
Sentence 1: The heuristic can be easily altered to determine a high leakage vector by suitably changing the input constraints for the constituent cells.
Sentence 2: our heuristic can be Random Heuristic Ckt Minimum Leakage (mA) Minimum Leakage (mA) Diff % Runtime Savings (X) c17 0.000927 0.000927 0.00 2420.00 c432 0.053687 0.054487 -1.49 247.67 c499 0.148894 0.14869 0.14 1098.22 c880 0.085622 0.08504 0.68 134.52 c1355 0.119469 0.118096 1.15 161.04 c1908 0.182616 0.178759 2.11 63.15 c2670 0.290749 0.290168 0.20 22.55 c5315 0.597011 0.608196 -1.87 24.48 c6288 0.589224 0.571751 2.97 458.81 c7552 0.836394 0.830377 0.72 34.03 i4 0.043078 0.038726 10.10 52.36 i5 0.073675 0.068402 7.16 69.83 i6 0.109648 0.114423 -4.35 320.41 i7 0.148743 0.149879 -0.76 129.22 i8 0.580241 0.597182 -2.92 48.84 i10 0.718149 0.721337 -0.44 35.24 my_add 0.064005 0.064766 -1.19 1318.00 c8 0.066114 0.067407 -1.96 378.40 cc 0.018429 0.018809 -2.06 2182.00 cht 0.053588 0.053577 0.02 724.22 clip 0.129456 0.134287 -3.73 1012.00 cm138a 0.004540 0.004563 -0.51 5100.00 Table 6: Results for a set of ISCAS and MCNC benchmark circuits compared with random search across 10000 vectors.
Relationship: reasoning
Domain: Hardware
Sentence 1: The propagation or masking of an error by a module depends on many variables, both static, e.g., the logic function implemented by the module, and dynamic, e.g., the current value of the other inputs of the module or the state of internal registers.
Sentence 2: several different signatures are possible for a single fault, especially when complex circuit topologies and functions are considered, since dynamic factors may change which comparators are triggered.
Relationship: reasoning
Domain: Hardware
Sentence 1: Complexsystemshavetobeoptimizedforperformanceand poweraswell.Thisespeciallyholdsforthefastgrowing marketofmobilecomputing/communicationdeviceslikecell phones,personaldigitalassistantsetc.
Sentence 2: thisisthemotivationfortheworkpresentedhere:to explorewhethercodecompressioncanbebenefcialforper­formanceandpowerinadditiontoareasavings.wedesignedanarchitecturethatwecallapost-cachear­chitecture(decompressionunitlocatedbetweenCPUand cache).Also,ourdecompressionunitisabletodecompress on{the-fywithoutsystemperformancepenalties(sincethis 1Pleasenotethatthisdoesnotholdforsoftwarecreatingself{ modifyingcode.
Relationship: reasoning
Domain: Hardware
Sentence 1: As an example, increasing .Toh from 100ps to 200ps only results in 9% increase in the Robustness Function, whereas increasing .Toh from 200ps to 300ps causes a 42% improvement.
Sentence 2: identifying the most economical scheme requires careful investigation of the Circuits , Research Report, http://esdat.ucsd.edu/~chong/nia.pdf.
Relationship: reasoning
Domain: Hardware
Sentence 1: 2(i)(i) (C- µ) jt Nelit; It should be emphasized that, the relative supply noise j.I sensitivities with respect to the decap candidates within the 9: t=t+1; same block would be similar even the absolute deacap sen­ sitivity values may have changed signi.cantly (after apply­ing the block level decap budgeting step using CE method).
Sentence 2: the SCE decap algorithm only requires one time adjoint sensitivity analysis throughout the decap optimiza­tion procedure.
Relationship: reasoning
Domain: Hardware
Sentence 1: This step ensures that the test will be executed as often as the application allows and can help the designer in the design space exploration.
Sentence 2: the proposed method generates a solution composed of the self-test program (set of selected self­test routines), the minimum test period that does not disturb the application, and data and program memory sizes required for the whole system (meeting the initial constraints defined by the target platform).
Relationship: reasoning
Domain: Hardware
Sentence 1: Note that, after .nalizing the learning phase, the runtime selection of a cache con.guration does not require previous tuning of all available microarchitectures before the selection of one with the highest performance, as proposed in other adaptive methodologies [2, 19].
Sentence 2: our on-line control method requires lower overhead for the determina­tion of the stable state of the microarchitecture than prior reported studies.
Relationship: reasoning
Domain: Hardware
Sentence 1: LZWInsoftware-basedapplications,onlytheindexis consideredinthecalculationofthecompressionratio.Inad­dition,statisticalencodingschemesareutilizedforfurther compressingtheindex.Asaresult,intypicalLZWappli­cations,superiorcompressionratios(i.e.,10;20%)have beenachievedbyusingcommerciallyavailablesoftwarepro­grams(e.g.,compress.gzip).However,suchcommercial programsarenotapplicabletoourcompressionproblem.
Sentence 2: asdiscussedearlier,inthecontextofembeddedenviron­ments,boththedictionaryandtheindexareconsideredin thecalculationofthecompressionratio.Thesizeofthe deriveddictionarieswascomparabletothesizeoftheorig­inalbit-streams.negativecompressionoccurred, Table1:Compressionratiosforthecon.gurationbit-streams Implementation Bit-stream size (bits) Compression ratio LZW Compact Heuristic Lower Bound MARS RC6 Rijndael Serpent Two.sh FFT-256 FFT-1024 4 x FIR-256 FIR-1024 3608000 2546080 3608000 2546080 6127712 1751810 1751840 1751840 1751840 179 % 119 % 198 % 165 % 186 % 140 % 159 % 180 % 177 % 96 % 69 % 104 % 95 % 103 % 85 % 89 % 97 % 96 % 82 % 59 % 89 % 79 % 86 % 68 % 72 % 80 % 79 % 73 % 48 % 81 % 67 % 76 % 56 % 64 % 73 % 71 % Table2:DictionaryandIndexmemoryrequirements.
Relationship: reasoning
Domain: Hardware
Sentence 1: inimize:Pp+Pa (16) Intermsofdecisionvariables,theaboveiswrittenas: inimize:Pp 1 + Yi,v,I,(I+Li,v-1)*P(iVvVIIM)(17) N Iv iEF ,v ThePpisusedasaconstraintlater.
Sentence 2: (b)Uniqueness Constraints :Theseconstraintscon.rmthatev­eryoperationoiisscheduledinappropriatecontrolstepswithinthemobilityrange(Si,Ei)withaparticularsupplyvoltage.Itmaybeoperatedatmorethanoneclockcycledependingonthesupplyvoltage.Theseconstraintsarerepresentedas,Vi,1:i:o, Si+Ei+1-Li,v Yi,v,I,(I+Li,v-1)=1(18)vI=Si Whentheoperatorsareoperatingathighestvoltage,theyaresched­uledinoneuniquecontrolstep,whereas,whentheyaretobeop­eratedatlowervoltagestheyneedmorethanoneclockcycleforcompletion.forlowervoltagethemobilityisrestricted.
Relationship: reasoning
Domain: Hardware
Sentence 1: Although the average distance from invalida­tion to subsequent load coherence miss is much longer in SPECweb99 than in TPC-H, the ECDC protocol is able to retain cache lines for a longer period of time than in TPC-H (approximately 50,000 cycles as opposed to 5,000 cycles).
Sentence 2: a signi.cant fraction of false sharing misses are avoided.
Relationship: reasoning
Domain: Hardware
Sentence 1: 2.5 MGUARD Overview Our solution to these challenges is to move all the new compo­nents off the critical paths of AMB, in contrast to Vigilare [31] that snoops the bus and is bounded with the bus speed.
Sentence 2: our solution is as close to the physical memory as one can possibly get by integrating programmable detection modules directly with the DRAM DIMM devices.
Relationship: reasoning
Domain: Hardware
Sentence 1: For instance, IBM targets 114 SDC FIT, 4,566 system-kill DUE FIT and 11,415 processor­kill DUE FIT for Power4 processors [2].
Sentence 2: to minimize the reliability cost, designers should develop or choose the most cost-effective mechanisms to meet the pre-de.ned reliability goal in terms of SDC FIT and DUE FIT.
Relationship: reasoning
Domain: Hardware
Sentence 1: Using clock buffer CKBX4 in TSMC 65 nm cell library for illustration, its delay at the high voltage level and at the ULV level is about 0.04 ns and 2.38 ns, respectively.
Sentence 2: for the same register, the clock skew of its clock arrival time between the high voltage level and the ULV level may be over 10 ns.
Relationship: reasoning
Domain: Hardware
Sentence 1: The FSD parameter to the BDW collector controls the rate of GC by stating the ideal free-space that a given GC should  em3d raytrace 1 1 2 db 1 1 1 jack 2 2 1 bisort 0 0 0 tsp 0 0 0 power 0 0 0 compress 0 0 0 mpegaudio 0 0 0 GeoMean GC-intensive 3.2 2.0 2.4 Overall 2.1 1.4 1.7  Table 7: Live hardware parameters Processor PowerPC 970 (Apple G5), 1.8GHz, 8-way issue, 200 max­imum instructions in .ight Caches 64KB direct-mapped instruction L1, 32KB 2-way associa­tive data L1, 512KB 8-way uni.ed L2, 8 L1 and 8 L2 MSHRs Memory 512MB Prefetch Prefetch into L1 using dcbt instruction obtain after each collection cycle as a fraction of total heap size.
Sentence 2: fSD 3 (the BDW default) states that GC should free up a third of the heap at each GC, expanding the heap as necessary only  db 0.7 10 10 0 -1 33 tions).
Relationship: reasoning
Domain: Hardware
Sentence 1: The scheduler checks the resources avail­able (FUs are the only resource considered in this discus­sion) to .nd the earliest available cycle for the operation to execute and schedules it at that time.
Sentence 2: using the exam­ple from Figure 2(a), assume operations are numbered with their priority, so operation 1 would be the .rst one sched­uled.
Relationship: reasoning
Domain: Hardware
Sentence 1: These y 0.6 0.4 0.2 0 -0.2 -0.4 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Figure 5: Tunnel diode phase portrait algorithm have no knowledge of the system s state space; hence the guidance and growth of the RRTs is only locally optimal.
Sentence 2: they are not very e.cient at generating traces toward the goal regions.
Relationship: reasoning
Domain: Hardware
Sentence 1: Gathering a set of particular performances pi into a vector gives us an idea of the total performance of the system.
Sentence 2: x Performance model P Figure 2: Electronic system S parametrized by X with excita­tion E and response Y leading to a performance P seen from a designer s point of view, the key relation­ship is: P = F(X) (3) The mathematical modeling of this relationship is called perfor­mance modeling.
Relationship: reasoning
Domain: Hardware
Sentence 1: To account for global di.erences inkeybetween the MIDI reference and the recorded stanzas, we revert to the ob­servation by Goto [6] that the twelve cyclic shifts of a 12-dimensional chroma vector naturally correspond to the twelvepossible transpositions.
Sentence 2: it su.ces to de­termine the cyclic shift index .
Relationship: reasoning
Domain: Hardware
Sentence 1: Because the de­sign space of the possible topologies is so large, choosing the bestone is a dif.cult problem that cannot be solved only by experience.In fact, the problem is even harder given the heterogeneity of cores,and the traf.c patterns among them.
Sentence 2: the development of automatic tools to design NoC isa key enabler for the success of the NoC design paradigm.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, combining balanced mapping and fine-grain turn­off creates an unexpected inefficiency in port usage because nei­ther technique achieves utilization symmetry within a copy.
Sentence 2: we advocate a counter-intuitive strategy of prior­ity mapping, which maps all high-priority ALUs to one copy and all low-priority ALUs to another copy (e.g., priority 1 and 2 to one copy, and priority 3 and 4 to another), to be used with fine­grain turnoff.
Relationship: reasoning
Domain: Hardware
Sentence 1: (x,y,z),AjDw If one region (x, y, z) is highly correlated to action Aj, it will then have relatively small within class distance (x,y,z),Aj (x,y,z),Aj Dw and large between class distance Db , which gives large .sher score F(x,y,z),Aj .
Sentence 2: .sher score can be an indicator of correlation between an action and regions.
Relationship: reasoning
Domain: Hardware
Sentence 1: In addition, the low-slew+high-skew method [2] achieves lower energy than unbuffered H-tree at the cost of low Fmax.
Sentence 2: we conclude that a simultaneous management of variation-aware slew and skew proves to be an ef.cient way to obtain a low-energy and robust clock network targeting at a high Fmax in ULV circuits.
Relationship: reasoning