sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: H0 It should be noted, however, that the loop transformation deter­mined based on NT;1 H0may not be able to generate the op­timal transformation in absolute sense; it is just expected to give us an improved version.
Sentence 2: as an example, let us consider the following program fragment which consists of two separate nests: for (i1 0ji2 nji1++) for (i2 0ji2 nji2++) f...U[i1][i2]... g for (i3 1ji3 nji3++) for (i4 0ji4 n;1ji4++) f...U[i3;1][i4+1]... g Considering the original access patterns of these nests, we have: 10 10 Hand N: 01 01 the second nest should be transformed using a loop transformation Tsuch that: 10T;1 ;10 010;1 should be satis.ed.
Relationship: reasoning
Domain: Hardware
Sentence 1: A probing front-end module (PFE) consists of a source fol­lower (SF) and a latch comparator (LC), where probe wiring from a target signal of interest is input to SF and its DC­level-shifted output voltage Vsf is compared with reference voltage Vref by LC, immediately within PFE when sam­pling clock Tck is given.
Sentence 2: output of PFE, Dout, is a single bit binary digital stream.
Relationship: reasoning
Domain: Hardware
Sentence 1: Droplet arrival order Adjustment D1 D2 W 1 2 3 D2 is made to arrive after W verses the site tra­ 1 3 2 Maintain this order 3 1 2 Maintain this order 3 2 1 W is made to arrive after D2 verses the site tra­ 2 1 3 D1 is made to arrive after W verses the site tra­ 2 3 1 W is made to arrive after D1 verses the site tra­ which further increases the droplet-routing time.
Sentence 2: there is a need to synchronize wash-droplet routing with func­tional droplet-routing steps, in order to reduce the time needed for droplet routing, and at the same time completely avoid cross-contamination.
Relationship: reasoning
Domain: Hardware
Sentence 1: (k+1) To ensure inequality (4), we note that d(k+1):d (k+1)/wby ij ij de.nition of d (k+1)and d (k+1):d (k)by de.nition of a successful iter­(k+1) ation.
Sentence 2: our goal will be reached once we have d (k)/wij = hi d(k)(k) maxp 03eij tp 0 /cp 0 which can be accomplished by re-weighting: ij / [] (k+1)d (k)/d(k)(k) w =(max t/cp 0 (5) ij ij )p 0 p 03eij The max-terms in this formula are called criticalities and can be computed using static timing analysis, which is especially ef.cient when the main global objective is slack maximization.
Relationship: reasoning
Domain: Hardware
Sentence 1: Block structure before writing test stimulus bit to the first cell whose column SIOaddress is smallest among the row of cells that will flip their m states.
Sentence 2: in the case of testing stuck-at faults, the number of cycles to test a LRAS-designed circuit is the sum CEm  CEBm Tm1 Tm2 of writing cycles and capture cycles: Pg T =sp 1 LRAS ¦¦(l +) p=1 l =1 where P denotes the number of test patterns, g is the number Qim of blocks, slp is the number of scan cells that flip their Dim states to load the pth test stimulus into the lth block.
Relationship: reasoning
Domain: Hardware
Sentence 1: As the crystallization rate is a function of temperature, given the variability of PCM cells within an array, reliable crystallization requires a programming pulse of hundreds of nanoseconds [11].
Sentence 2: the SET latency of a PCM cell is longer than both the RESET latency and the read latency, usually 5 10× the read la­tency [5, 6].
Relationship: reasoning
Domain: Hardware
Sentence 1: Although the last application show a con.icting e.ect of vector caching with loop-unrolling, the high cache hit rate is obtained by disabling loop-unrolling, and the highly-e.cient computing comparable to that on the 4B/FLOP bandwidth system is obtained.
Sentence 2: the vector cache is able to recover the lack of the memory bandwidth in these scienti.c ap­plications.
Relationship: reasoning
Domain: Hardware
Sentence 1: The .ne-grained rank-level 3D DRAM (Figure 2 (c)) involves re-architecting the DRAM dies and introducing an additional logic die.
Sentence 2: this design incurs much greater NRE cost for both the DRAM dies and the logic dies than does the coarse-grained design, not to mention the fabrication cost of the extra TSVs.
Relationship: reasoning
Domain: Hardware
Sentence 1: Calculating Internal Data Rate (IDR): The maximum IDR would be experienced by tracks in the outermost zone (zone 0) of the disk drive, since there are more bits stored there while the angular velocity is the same across the tracks.
Sentence 2: we can express the maximum IDR (in MB/sec) of the disk as: rpm ntz0 × 512 IDR =()( ) (4) 60 1024 × 1024 where ntz0 is the number of sectors/track in zone 0, and rpmis the angular velocity expressed as rotations-per-minute.
Relationship: reasoning
Domain: Hardware
Sentence 1: Ef.­ciency overhead for sequential execution, presented in paren­theses in the last column, is between 1.03 and 1.59 (which averages 1.22) for all of the studied applications.
Sentence 2: in­ 5Artiaga has experienced similar problems with the original fork-exec ver­sions of Volrend and Cholesky [1].
Relationship: reasoning
Domain: Hardware
Sentence 1: For example, there are 35 power domains in a single router in [25] to implement this method of power-gating in addition to the complex coordination needed among different components, which incurs significant energy and area overhead with considerable design effort.
Sentence 2: a much more effective way of removing the dependence between the node and router is needed, so as to combat the BET limitation from the source by reducing the number of wakeups while maintaining the ability to transport packets in the NoC.
Relationship: reasoning
Domain: Hardware
Sentence 1: With 15 An LFSR cannot be all0s, so an n-bit LFSR actuallygoesthrough 2n - 1 values, with eachbitsetto1for 2n-1 ofthevalues.
Sentence 2: thelikelihoodforanybittobe1 is 2(n-1) .With n=16,theprobabilityis0.5000076, whichisclose enoughto 12 for (2n)-1 most practical purposes.
Relationship: reasoning
Domain: Hardware
Sentence 1: Figure 5 illustrates how this pinning mechanism can play the role of a coa­lescing phase by preventing the reconstruction phase of Leung and George s algorithm from inserting move in­structions: in Figure 5(b), x1 and x2 were pinned to x to eliminate these move instructions; however, this pin­ning creates an interference, which results in a repair move x = x along with a move x = x on the replace­ment of the f instruction; in Figure 5(c), to avoid the interference, only x2 was pinned to x, resulting in only one move instruction.
Sentence 2: we will only look for a variable pinning that does not introduce any new interference.
Relationship: reasoning
Domain: Hardware
Sentence 1: (4) vi,vj .evi,vj .e net e Since W (x, y) is not smooth and non-convex, it is hard to minimize it directly.
Sentence 2: several smooth wirelength ap­proximation functions are proposed, such as quadratic wire­length [12, 19], Lp-norm wirelength [6,18], and log-sum-exp wirelength [5,17,23].
Relationship: reasoning
Domain: Hardware
Sentence 1: Fortunately, transistor sizing can be used to equalize the delay of this path with the delay of the other critical path (Mn1-Mn2-Mn3, Mp6 or Mn1-Mn2-Mn4, Mp6).
Sentence 2: this delay penalty is not significant compared to the power saving that can be achieved, as it will be shown later.
Relationship: reasoning
Domain: Hardware
Sentence 1: The substrate of an SOI chip is the 5-th terminal of an SOI tran­sistor, affecting its behavior through capacitive coupling.
Sentence 2: unlike traditional MOSFET, the electrical model of an SOI transis­tor has 5 terminals (Figure 1 (b)) thus increasing the number of independent variables and correspondingly the number of dimen­sions of a table model.
Relationship: reasoning
Domain: Hardware
Sentence 1: As reported in [16], a 64-bit PowerPC in SOI technology has a maximum operating frequency, fMAX, that is approximately 1.24 times the fMAX in bulk CMOS technology.
Sentence 2: we scale the power dissipation in SOI technology by a factor of 1/1.24 while estimating the power dissipation of the 64-bit ALU circuit operating at the same frequency as in bulk CMOS technology.
Relationship: reasoning
Domain: Hardware
Sentence 1: The xtime-2 is de.ned by left shift by 1 bit, and bit-wise XOR with 0x1B if the most signi.cant bit is 1; The xtime-3 is de.ned as xtime-2 result XOR with its original value.
Sentence 2: there are only two de-facto atomic operations: 1) bit-wise XOR, executed by proposed DW-XOR, and 2) xtime-2.
Relationship: reasoning
Domain: Hardware
Sentence 1: For instance, whereas a full adder is just a set of gates in a gate level description, it is a mod­ule in a Verilog RTL description.
Sentence 2: the basic building blocks for gate level descriptions are the logic gates; and the basic blocks for RTL descriptions are half and full adders, decoders, encoders, multiplexers, and demultiplexers.
Relationship: reasoning
Domain: Hardware
Sentence 1: The data shows that regions A-Top, and D-Top can only safely handle a single read at a time.
Sentence 2: with a worst-case pattern, just two reads can lead to a voltage under 1.425 V. regardless of what else is happening on the 3D-stack, the memory controller must enforce that these regions never service more than 1 read at a time.
Relationship: reasoning
Domain: Hardware
Sentence 1: Theenergyconsumedindatacachesaloneafterapplying thecompileroptimizationswithnoblockbuferingorsub­bankingwasalsostudied.Wefndthatthetilingandloop transformations,generally,increasethecacheenergycon­sumptionduetotheadditionalmemoryreferencesintro­ducedbyscalarreplacement.Thisefectisprettydominant inthetilingoptimizationthatresultsina186%increase inenergyfor4Kdatacachesonanaverage.However,this efectisovershadowedbythedrasticreductioninthenum­berofmoreenergyconsumingof-chipaccessestothemain memory.Wealsoobservethattheunrollingoptimizationis suitableforreducingboththecacheenergyandtheoverall energyinthemxmcode.
Sentence 2: 3.3 Combined Optimizations Itwasfoundthatwhenacombinationofdiferentsoftware andhardwareoptimizationsisapplied,tilingperformsthe bestamongthethreeindividualcompileroptimizationsap­pliedintermsofmemorysystemenergyacrossdiferent4K cacheconfgurationsSince,wementionedearlierthattiling increasesthecacheenergyconsumption.sub-bankingand blockbuferingareofparticularimportancehere.Forthe tiledcode,movingfromabasedatacacheconfgurationto onewitheightblockbufersandfoursub-banksreducesthe overallmemorysystemenergybyaround10%.itis importanttouseacombinationofhardwareandsoftware optimizationsindesigninganenergy-efcientsystem.
Relationship: reasoning
Domain: Hardware
Sentence 1: Although normally only part of the cache, e.g., 7/8, may be used as scratchpad memory in Intel XScale processors [21], Simics supports only TABLE I L1&#38;L2CACHE CHARACTERISTICS Name L1 Instruction Cache L1 Data Cache L2 Cache Default Cache Size (KB) 16 8 512 Line Number 256 128 8192 Line Size (B) 64 64 64 Writing Method Write-through Write-through Write-back Mapping Mechanism 8-way 4-way 8-way Replacement Mechanism LRU LRU LRU Cycles on read-hit 1 2 7 Cycles on write-hit 1 2 7 cache sizes that are powers of two.
Sentence 2: we use the whole cache as scratchpad memory for the convenience of simulation.
Relationship: reasoning
Domain: Hardware
Sentence 1: The reason for this is not only that the last term of equation 1 is close to unity, but also that with a large value of Vds, VT would be lowered due to drain induced barrier lowering2 (DIBL) [3, 1].
Sentence 2: leakage reduction techniques should ensure that the supply voltage is not applied across a single device, as far as possible.
Relationship: reasoning
Domain: Hardware
Sentence 1: As stated before, after the initial warmup time, each DWT pair transforms two pixels in each cycle.
Sentence 2: the throughput of the parallel design can be cal­culated as shown in Equation : P arallelT hroughput = n * SpeedOfDW T P rocessor (5) Since the throughput depends on both the width of the design and the speed of DWT processors, it is possible to change their values and still maintain the same throughput.
Relationship: reasoning
Domain: Hardware
Sentence 1: Finally, the expression can be simpli.ed using the scalar product inequality (a·b =|a||b|) for the in.nity norm.
Sentence 2: minki=1(di.i/s2 i ) d = k × minki=1((si/di)di.i/s2 i ) minki=1(di.i/s2 i ) d = k × minki=1(si/di) × mink ) i=1(di.i/s2 i 11 d = = max ki=1(di/si) (5) k × minki=1(di/si) k  1 1  1  1 0.8 0.8 0.8 0.8 0.6 0.6 0.6 0.6 0.4 0.4 0.4 0.4  (iii) sparc_ifu_dec (iv) sparc_lsu_ctl (b) (iii) sparc_ifu_dec (iv) sparc_lsu_ctl (a)  Top ranked gates from DCG Number of low VT swaps Figure 3: With independent process variations (a) Critical weights of top ranked gates obtained from DCG and (b) Comparison of yield improvement obtained using using low-VT swapping based on DCG and conventional metric for gate criticality MC.
Relationship: reasoning
Domain: Hardware
Sentence 1: Figure 4 shows both the hardware architecture with four MPC750s and SoCLC and the software architecture with an RTOS extension developed to support SoCLC mechanism at the kernel level.
Sentence 2: using the ExIntr_Hdlr() RTOS API to search, the highest-priority waiting task is selected from the lock-wait table and then the task is inserted into the ready list of the kernel.
Relationship: reasoning
Domain: Hardware
Sentence 1: Obviously, any matching Emat ch of bipartite graph Gbp corre­sponds to a feasible binding of T to M, and the total weight of Emat ch equals the cost of the attempted binding, or the number of newly introduced inter-island connections.
Sentence 2: the up­dated binding solution produced by the minimum-weighted bipar­tite matching is optimal among all the possible bindings of T to M, as in the following conclusion.
Relationship: reasoning
Domain: Hardware
Sentence 1: In an MLC cell, however, raising the amplitude of programming current during a soft transition (e.g., switching the resistance state of the small MTJ only) may also increase the probability of overwriting the cell, e.g., accidently .ipping the resistance state of the large MTJ.
Sentence 2: the write operation of MLC cells generally has a higher write error rate than that of SLC cells.
Relationship: reasoning
Domain: Hardware
Sentence 1: (Many methods, e.g ., least-square .tting, can be used to .nd good linear approximations for e -yj within the interval [log Lj , log Uj ].)
Sentence 2: we can reformulate each constraint fs(x, p) 1 in (9) as a log-sum-exp constraint (like (12)) to obtain a robust GP of the form (3) with the ellipsoidal uncertainty: T -1 np +nx }, U = {d = (u, u ) | d. d 1, d E R(16) where 1 satisfying Fx2 (1) = s, and .
Relationship: reasoning
Domain: Hardware
Sentence 1: This is very inefficient, since it will consume way too much power for most of the standards and operation modes, and for a broad range of specifications this solution is simply technically infeasible.
Sentence 2: a software-defined reconfigurable transceiver with flexible or reconfigurable building blocks, where the performance and hence the power consumption can be scaled under digital control to the needs of the standard and operating mode, is much more desirable.
Relationship: reasoning
Domain: Hardware
Sentence 1: When serially transmitting a set of symbols, minimizing the transition count can be achieved by using codes with minimal intra-word transition count.
Sentence 2: similarly to what is proposed in [3], the LIWT encoding works by map­ping symbols (that is, pixel di.erences) in decreasing order of occurrence probability to codewords sorted in increasing order of intra-word transitions.
Relationship: reasoning
Domain: Hardware
Sentence 1: This process is nothing but the dual of the tech­nique used for Heuristic 1, thanks to the relation (proved in Theorem 2) Fi(iai)Fn* +i-1(icn+1-i) = 1.
Sentence 2: we could use the same proof, reasoning with the dual basis of (ici)1=i=n.
Relationship: reasoning
Domain: Hardware
Sentence 1: Different from the previous work, we are interested in the propos­ing of a non-volatile translation layer (also referred to as PCM translation layer) for PCM jointly as the main memory and stor­age with proper device commands, so as to realize the concept of one memory .
Sentence 2: it could be used to reduce the physical space required by the hardware components in space-limited com­puting systems (e.g., smartphone and ultrabook) and to improve the system s storage performance with enhanced energy ef.ciency.
Relationship: reasoning
Domain: Hardware
Sentence 1: Therefore, the switch arbiter instructs the FIFO virtual channel buffers to shift one position in stage 1, and the .its latched in the pipeline buffers are sent to the crossbar in stage 2.
Sentence 2: a soft error in the SA could give rise to several packet-loss problems: (a) A soft error in the control signals might prevent the .its from traversing the crossbar in stage 2.
Relationship: reasoning
Domain: Hardware
Sentence 1: This is analogous to the observations for a single SSD and the two parity-less RAID con.gurations, and, again, makes such setups more suitable for demand­ing scenarios requiring more predicable and higher mini­mum performance.
Sentence 2: the results indicate that higher over-provisioning positively a.ects random write per­formance of parity-based SSD RAIDs as well.
Relationship: reasoning
Domain: Hardware
Sentence 1: For the rest of the input combinations, the signal paths are CL(Carry Logic) + IMUX21.
Sentence 2: the signal paths of all logical Table 2: Conventional vs. proposed 3:2 compressors with a p/n ratio of 1.5 (65nm CMOS, tau = 3.511ps) Conventional Proposed Change Cin(Input A) 22.5 20 -11.1% Cin(Input B) 22.5 20 -11.1% Cin(Input C) 17.5 15 -14.3% CT otal 72.5 77.5 +6.9% GSum 9.26 4.75 -48.7% PSum 16.89 13.16 -22.1% GCarry 2.78 2.78 SAME PCarry 8.15 8.15 SAME high and all logical low input combinations are not sitting on the signal path of other input combinations.
Relationship: reasoning
Domain: Hardware
Sentence 1: The minimization of the objective function min [code change(E0,z) -code change(E1,z)] avoids any vector z as a solution if there is another vector z ' such that a signal with initial value 0 (1) is not balanced in code change(E0,z)(code change(E1,z)) but is balanced in code change(E0,z ' )(code change(E1,z ' )).
Sentence 2: this function reduces the number of unbalanced signals and, thus, less choices are possible when the model is feasible and a new unbalanced signal must be added to S ' .
Relationship: reasoning
Domain: Hardware
Sentence 1: 1 BUS 2, j.i .. +.. ( i , Mj ) ()}/ ( 1) xfer M prob j xfer BUS i.BUS 2 j=BUS 1 prob(BUS2) is calculated similarly.
Sentence 2: the switching activities of bus1 and bus2 (assumingtemporal independence of data values on the bus) are: ( 1) prob BUS ( - ( xfer BUS ( sw BUS =2 1)[1 prob BUS 1)] 1) ( 2) prob BUS ( - ( xfer BUS ( sw BUS =2 2)[1 prob BUS 2)] 2) the average energy consumption per clockcycle of the split bus architecture is calculated as: 2 E =0.5(CBUS1sw(BUS1) +CBUS 2 sw(BUS 2))Vdd n +.Edriver,Mi +Edriver,BUF1 +Edriver,BUF 2 i=1 where Edriver,x can be calculated by the equations in Section 2.
Relationship: reasoning
Domain: Hardware
Sentence 1: nominal buffer is 5.1% and the nominal tunable buffer itself consumes 21% more power than a repeater.
Sentence 2: this scheme incurs a sizeable penalty in terms of power but since it is dynamic it can be applied selectively so that for the most portion of interconnect-length and a vast majority of its lifetime we operate using nominal dimensions and stay within an acceptable power-budget.
Relationship: reasoning
Domain: Hardware
Sentence 1: When a later instruction refers to a previously renamed destination register (with its logical binding), it must be able to traverse the renaming and obtains the value stored inside the corresponding physical register or just the tag of the physical register if the value has not yet been produced.
Sentence 2: the register rename logic is used to translate logical register designators into physical register designators and is accomplished by accessing a mapping table with the logical register designator as the index.
Relationship: reasoning
Domain: Hardware
Sentence 1: Even when there may appear to be space for buffers in the alleys between large blocks, these regions are often densely packed or may needed later to .x critical paths.
Sentence 2: within physical synthesis, a buffer insertion scheme needs to be aware of the poros­ity of the existing layout to be able to decide when to insert buffers in dense regions to achieve critical performance improvement and when to utilize the sparser regions of the chip.
Relationship: reasoning
Domain: Hardware
Sentence 1: 3.2 Multiple TSVs between Adjacent Layers When multiple TSVs between adjacent layers are allowed (i.e., B> 1), we cannot determine TSV locations for x and y coordinates separately.
Sentence 2: we represent the TSVs vv locations by {(xkb,ykb):1 = k = L - 1, 1 = b = B} where vv (xkb,ykb) denotes the location of the bth TSV between lay­ers Mk and Mk+1.
Relationship: reasoning
Domain: Hardware
Sentence 1: Frame Width (W) 1,920 Frame Height (H) 1,080 Number of IN ASIPs 1 Number of H.264 ASIPs 36 Number of OUT ASIPs 1 TABLE I AN EXAMPLE OF A CONFIGURATION FILE.
Sentence 2: the allocation of slices and bit stream our H.264 encoder is scalable across scaling does not require any modi.cations to software more scalable.
Relationship: reasoning
Domain: Hardware
Sentence 1: In our implementation, each functional unit is pipelined, and the initiation interval of each functional unit is one.
Sentence 2: a lower bound of II considering the ith type of functional unit is given as follows: II = Inst i si (5)  5.2 Resource Model The resources required by every allocated functional unit instance and the multiplexers are used to estimate the total resource usage.
Relationship: reasoning
Domain: Hardware
Sentence 1: For example, when F P = 0.01, if we vary F N from 0.01 to 0.1, NMI remains almost the same, because in a realistic IDS operation environment, the base rate is very low (close to zero), indicating that the uncertainty of X is close to zero.
Sentence 2: the entropy of X (nearly zero) is far less than the en­tropy of Y because the IDS can produce many false positives, as shown in the right part of Figure 2.
Relationship: reasoning
Domain: Hardware
Sentence 1: Comp ared to the multi-functional, p in-constrained DM FB, the field-p rogrammab le p in-constrained DMFB required 1.44x more p ins for a comp arably sized array (12x18 vs. 15x15).
Sentence 2: field­p rogrammab le do es come at a p rice in terms of p in-count and, sometimes, assay execution time, comp ared to state-of-the-art assay -sp ecific and mu lti-functional p in-constrained DM FBs; however, the flexibility p rovided is unmatched by p rior DM FBs and offers a significant advancement in terms of p rogrammability .
Relationship: reasoning
Domain: Hardware
Sentence 1: Since t(vi,sr), t(vi,sr), t(vj ,sl), and t(vj ,sl)are constants (see explanation later), without loss of generality, we may assume that t(vi,sr)= ß1, t(vi,sr)=ß2, t(vj ,sl)=ß3, and t(vj,sl)=ß4.
Sentence 2: r·CTi r·CTj {z 0 t(sr,sl)a =(rc·Dij + +)·z+t skewskew,a Wu Wl zr·CTi r·CTj 0 tskew(sr,sl)a =(rc·Dij + +)·z+tskew,a Wl Wu and 2 rc·DrDij ·CTj {0 t=(ß1 -ß4)-( ij +) skew,a 2 2 Wl (8) 0 rc·DrDij ·CTj tskew,a =(ß2 -ß3)-( 2 ij + Wu ) Case (b).
Relationship: reasoning
Domain: Hardware
Sentence 1: EVALUATION  4.1 DVFS Algorithms for Efficiency Comparison The key objective of this section is to evaluate the effectiveness of the LDO VRs derived from PCPG devices.
Sentence 2: we can use various per-core DVFS algorithms optimized for high­performance multi-core processors including the algorithms exploiting C2C frequency and power variations along with thread migrations (TMs) [2].
Relationship: reasoning