sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: As shown in this table, the uniform sampling with 5 points (U5) and the non-uniform sampling with 3 points (NU3) scenarios lead to 26.7% and 25.4% timing margin reduction (167% and 155% lifetime improvement), respectively.
Sentence 2: for this purpose, we start from a netlist mapped into the original aging-unaware library.
Relationship: neutral
Domain: Hardware
Sentence 1: 1.2 V o Voltage(V) 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 2.0 2.1 2.2 2.3 2.4 2.5 Time(ns) Fig.
Sentence 2: the exact value of VN depends on the previous state of the inputs (we ignore the effect of leakage currents here).
Relationship: neutral
Domain: Hardware
Sentence 1: (0, 1) and 0 = g(0),g(1) = 1,  then g(t) can be converted into a Bernstein polynomial of degree m with coe.cients 0 = bmi = 1(i =0, 1,...,m).
Sentence 2: for each speci.c value of n, we also properly designed the adder tree shown in Figure 4.
Relationship: neutral
Domain: Hardware
Sentence 1: theproprietarynatureofmanyommerialalgorithmiim­plementationsoftenpreventthereleaseofprodut­quality odesintothepublidomain;and(2)historially,signal proessingsystemsombinedaMAC­entriDSPorewith aontrollerorhostproessor,meaningthatkernelompu­tationandontrolodeweresplitarosstwoproessors,so tunedindustryimplementationsofunifedontrolandker­nelodewererare.
Sentence 2: theoriginalresultsunder­representtheodesizepenalty ofhyperblokoptimizationbyanaverageof41.3%,whihis asignifantmisestimation.
Relationship: neutral
Domain: Hardware
Sentence 1: TRANSISTOR PLACEMENT Because of the single-row di.usion style of our regular fabric, the transistor placement problem simpli.es to the problem of .nding a good ordering of the PMOS and NMOS transistors within their respective rows.
Sentence 2: the transistor placements produced by our al­gorithm are therefore optimal with respect to brick width (and hence area, since brick height is assumed .xed), and strongly Pareto optimal with respect to channel density and estimated wirelength.
Relationship: neutral
Domain: Hardware
Sentence 1: Trying to specify pipelining via regular expressions or any other cycle-by-cycle style requires the user to entangle all the possible parallel behaviors by hand, result­ing in a dif.cult, error-prone speci.cation process and an unread­able speci.cation.
Sentence 2: by intro­ducing two novel extensions  storage variables and a pipelining operator we have created a speci.cation style that does work very well for interface monitors.
Relationship: neutral
Domain: Hardware
Sentence 1: Therefore SDRAM rows adjacent in the physical address space stride across dif- ferent banks.
Sentence 2: .,..._,i,lil i ; /I, _IIMIIM[ ~ ~1 ,I .I..... ,Idll -~,~| II .MUllUlII ~1 II .,dlIIMMII[ [ ,HI II .,dlIMIIlUlI!
Relationship: neutral
Domain: Hardware
Sentence 1: Two major problems have to be faced: the first is that TLM includes a range of abstraction levels and the second is that a mapping between TLM assertions and RTL assertions should be provided and formally proven.
Sentence 2: by using formal methods the verification activity may concentrate just on the expected behavior of the Design Under Test (DUT), because the formal analysis itself takes care of the DUT implementation details.
Relationship: neutral
Domain: Hardware
Sentence 1: Short Latency probability X {A[16:14] B[16:14]} {A[17:14] B[17:14]} {A[17:13] B[17:13]} {A[18:13] B[18:13]} P (L) 0.1250 0.0625 0.0312 0.0156  * C o n ven t i o na l Figure 3.
Sentence 2: figure 5 shows the general architecture of an adder (with single critical path) in the purview of our elastic clocking scheme.
Relationship: neutral
Domain: Hardware
Sentence 1: Depending on the purpose and the physical category, the requirements can be very different in terms of bandwidth, resolution and size.
Sentence 2: larger crystals with a frequency variation < 0.1% permit a Power Consumption 1mW Temperature Sensor  Microphone Static LCD-Digit 1µW Switch 1bps 1kbps 1Mbps Bandwidth Bandwidth and energy demand of several  Figure 2. reduction of space for the energy supply because the intervals for Sensor LED components during a 100% duty cycle, based on [6] the synchronization of the system rates can be increased.
Relationship: neutral
Domain: Hardware
Sentence 1: [4] D. Boggs, A. Baktha, J. Hawkins, D. Marr, J. Miller, P. Roussel, R. Singhal, B.
Sentence 2: separating the two goals allows a much more relaxed implementation (hence the name) which not only mitigates the escalating micro­processor design complexity, but can lead to opportunities a more sophisticated and proactive approach can not provide.
Relationship: neutral
Domain: Hardware
Sentence 1: (5) If there is no CNOTt1 before [t1,{c1}], ixt1 )remains i0)just before the gate [t1,{c1}].
Sentence 2: after applying [t1,{c1}], the state of ixt1 )and that of ixc1 )must be the same, which means that we can change t1 to c1 in the index set of the latter gate s control bits.
Relationship: reasoning
Domain: Hardware
Sentence 1: As veri.ed in prior works [8 13], it is helpful to reduce the logic value differences between v1 and its response vector v2 by .lling the X-bits in v1 intelligently; while in LoS scheme, v1 is turned into v2 by a shift clock.
Sentence 2: adjacent .ll [7] originally proposed for shift power reduction can be adopted to reduce the capture power of LoS scheme.
Relationship: reasoning
Domain: Hardware
Sentence 1: Moreover, it becomes more complicated when the char­acter of asymmetric read/write access is considered.
Sentence 2: for the popular one-transistor-one-MTJ (Magnetic Tunnel­ing Junction) based STT-RAM cell, various design parame­ters, such as MTJ shape, MgO thickness, access transistor s gate length/width, etc., can be a.ected by process variation­ s. the characteristics of STT-RAM cells in an STT-RAM cache can be quite di.erent from each other.
Relationship: reasoning
Domain: Hardware
Sentence 1: The cost ci is the power overhead from the conversion and is expressed as: ci = P (SiZ ) - P (SiXY ) (7) where P (SiZ ) and P (SiXY ) are the power of a Z-cut (i.e., using one TSV) or an XY-cut (i.e., using multiple TSVs) for Si.
Sentence 2: our goal is to choose low-cost nodes for TSV count reduction.
Relationship: reasoning
Domain: Hardware
Sentence 1: Moreover, the weight of each vertex indicates the perturbation of the corresponding feasible double via.
Sentence 2: the DVI/WB problem is modeled as that of .nding a minimum-weight maximum independent set (mWMIS) on the enhanced con­.ict graph, i.e., among all maximum independent sets, .nd­ing the one with the smallest total weight.
Relationship: reasoning
Domain: Hardware
Sentence 1: For FA-DFR/BER scheme, our preliminary ex­periments show that the difference in PSNR between consecutive frames make the 2nd , 3rd,and 4th frame in the descending or­der of the importance on average.
Sentence 2: fA-DFR/BER with 2nd frame is studied to improve the video quality most and indicates that we select BER rather than DFR whenever a soft error occurs in encoding the 2nd frame.
Relationship: reasoning
Domain: Hardware
Sentence 1: After separately deriving each sub-PSF, the sub-PSFs might be overlapped with each other on the merging have g(x, y) G(x , y ) gc(x , y ) (a) (b) Figure 4: Illustration of deriving a sub-PSF from the original boundaries.
Sentence 2: as we merge the sub-PSFs, the merging bound- PSF.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then, at time tj+1,the n-th sensor reads the real temper-2.5 ature value T(xn,tj+1) and quantizes the prediction error E(xn,tj+1)= T(xn,tj+1) - T.(xn,tj+1), getting the quan­ tized output ET(xn,tj+1), with an scalar quantizer Q.Next, all the sensors send their quantized prediction errors to the BS, which obtains a reconstruction for each temperature T value T(tj+1) by adding these quantized prediction errors to the previously predicted values, that is, TT(xn,tj+1)= T.(xn,tj+1)+ ET(xn,tj+1), n =0,... ,2M (18) Then, the BS starts performing the prediction operation again and the whole process is repeated.
Sentence 2: the sys­tem is very similar to that of a closed-loop DPCM where the encoders are the sensors and the decoder is the BS, and importantly, the prediction operation makes use of the heat equation and the conductivity properties of the heat con­ductor ring.
Relationship: reasoning
Domain: Hardware
Sentence 1: It can also be used in improving simulation performance during the system correctness and performance analysis phase of a project.
Sentence 2: if parallel re­source structures are present in the resource mapped system (e.g., Figures 6 and 7) then straightforward parallel simula­tion techniques can be used to reduce simulation times Consider, for example, Figure 7 where there are both se­rial and parallel structures and two types of resources: FP-GAs and GPPs (assume that all GPPs are identical).
Relationship: reasoning
Domain: Hardware
Sentence 1: The performance measure for this nonlin­earity is usually expressed by the third-order input intercept point (I I P3) per DC power consumption (I I P3/DC ), since the third-order intercept point (I P3) is usually proportional to DC power consumption.
Sentence 2: it is a great challenge to increase I P3/DC for extremely low-power systems such as ZigBee.
Relationship: reasoning
Domain: Hardware
Sentence 1: The equationfordynamicpower dissipation canbegiven as(10).
Sentence 2: l k)sk V 2 Pd(i)= tpi Ci(¯dd/(2tc) (10) k=foi theleakagepower of agateisdirectlyproportional to its size, and the dynamic power is proportional to the sum of the sizes of its fan-out gates.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, we have dk + dk latch +(dk nor) = dsetup, xor as the setup-time constraint for the latch at pipeline stage k.More­over, the hold-time constraint of a latch speci.es the minimum time interval that input data of the latch must remain unchanged after the latch is closed for input data to be accepted correctly [12][13].
Sentence 2: we have (k-1) (k-1) (k-1) (k-1) k k dxor + dnor + d+ d= (dxor + dnor)+ dhold, latch bundle as the hold-time constraint for the latch at pipeline stage k.If delays of gates with the same type are the same, the hold-time constraint can be rewritten as (k-1) (k-1) d+ d= dhold.
Relationship: reasoning
Domain: Hardware
Sentence 1: Recently, leakage power also affects the yield inpower-constrained designs [2]-[5] due to limited total power budget,which is imposed by limited power-supply and cooling-solutioncapacity.
Sentence 2: many leaky dies, satisfying Fmax constraints sufficiently, may be discarded because they exceed power (andthermal) constraint; this becomes worse as technology scaling increases the spread of leakage power (e.g.
Relationship: reasoning
Domain: Hardware
Sentence 1: It can be seen from the road tra.c statistics in [27] that the number of cars on a motorway is almost 5 times larger than the number of cars using built-up roads with a max­imum speed limit of 60 km/h.
Sentence 2: the average density of cars on the motorway shall have the greatest impact on the distribution of a WSN for vehicular.
Relationship: reasoning
Domain: Hardware
Sentence 1: This is because a powered-off block cannot perform the assumed functions temporarily, and waking up the block takes an additional wakeup delay, thus potentially stalling system progress.
Sentence 2: effective use of power-gating should achieve two objectives in a balanced way: (1) Maximize net energy savings, which means to maximize the idleness of unneeded functional blocks in order to increase the cumulative energy savings while reducing the associated energy overhead as much as possible; (2) Minimize performance penalty, which means to partially or completely reduce/hide the wakeup latency of needed functional blocks, so that execution can continue with minimal delay.
Relationship: reasoning
Domain: Hardware
Sentence 1: fi d(X)  Table 2.1: Truth table of an incompletely speci.ed function.
Sentence 2: x1 x2 x3 x4 f1 f2 x1 x2 x3 x4 f1 f2 0 0 0 0 d 1 1 0 0 0 0 1 0 0 0 1 d 1 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 1 0 1 1 1 0 0 1 0 0 d d 1 1 0 0 1 d 0 1 0 1 d d 1 1 0 1 1 d 0 1 1 0 1 0 1 1 1 0 d 0 0 1 1 1 1 1 1 1 1 1 d 1 we have the following: DE FINIT ION 2.3.
Relationship: reasoning
Domain: Hardware
Sentence 1: a separate constraint has to be built for each truth table line of the function f to be synthesized.
Sentence 2: the instances grow ex­ponentially with respect to the number of input variables of the function f. In this paper, we present an approach for reversible logic synthesis which leadstoa polynomial size encodingby tak­ing advantage of Quanti.ed Boolean Formula (QBF) sat­is.ability a generalization of Boolean satis.ability.
Relationship: reasoning
Domain: Hardware
Sentence 1: If we denote the seed vector as S, the output slice vector as 0and the XOR network matrix as X, then the relationship between an output slice and its seed can be expressed as: [0]=[X][S] Suppose the required output slice contains four speci.ed bits, such as 0=(0b010i03040506070809)=(x1xx0x1xx0).
Sentence 2: o0 = S3 O0 0001 O1 = S2 S3 O1 0011 O2 = S1 S2 S3 O2 0111 O3 = S0 S1 S2 S3 O3 1111 S0 O4 = S0 O4 1110 S1 S1 S2 = O5 1101 S2O5 = S0 S1 S3 S3 S2 O6 1010 O =S 60 O7 = S1 S3 O7 0101 O8 1011O8 = S0 S2 S3 O9 0101O9 = S1 S2 Figure 3: Matrix representation of an XOR network example with only (01040609) speci.ed to (1010), the seed can be determined by utilizing the four rows in matrix Xcorrespond­ing to 01006and 09.
Relationship: reasoning
Domain: Hardware
Sentence 1: Itisalsotruethatourmethodanbeappliedforlarger iruitstowhihBDD-basedmethodsarenotfeasible.In onlusion,ourmethodisomplementaritytotheexisting BDD-basedmethods.
Sentence 2: theobviousadvantagesofthemethod[9]overour methodisthefollowing.Ourmethodannotfndthe speialusageofCBsasmentionedinSe.III-E.Onthe otherhand,themethod[9]sometimesextratsthespe­ialusageofCBsfromtheirBDDrepresentationsine themethodonstrutsiruitsdiretlyfromRSFQlogi primitives.Aswementioned,byignoringthisspeialus­ageofCBs,weansuessfullyutilizetheonventional logitehniquesinourframework.Notealsothatthe optimizationphaseinourframeworkanhandlethisspe­ialCBsbytreatingthemasORgateswithsomespeial onditions.itiseasytomodifyourTransdution Methodsothatitanbeappliedtotheiruitobtained bythemethod[9].Suhmodifationsandfurtherom­parisonwiththeBDD-basedmethodsshouldbedoneas ourfuturework.
Relationship: reasoning
Domain: Hardware
Sentence 1: The biggest advantage of the Transduction Method is to be easier to import con­straints on physical design into logic design.
Sentence 2: while the physical design like placement and routing is getting more important for high-performance FPGA circuit design, transformation-based logicoptimizations, such as the Trans­duction Method as well as ATPG (Automatic Test Pattern Generation)-based ones [5] [6] [8] [9] [10] [11] [12], are also getting more signi.cant, since such optimization methods can transform logic circuits so .exibly that the circuits sat­isfy the speci.cations, such as the speed and area.
Relationship: reasoning
Domain: Hardware
Sentence 1: First, Imai and Asano proved that n axis-aligned rectan­gles (e.g., bounding boxes) have a single non-empty n-way inter­section iff each pair of these rectangles overlap.
Sentence 2: rather than check all subsets of overlapping bounding boxes, we may search  Figure 4: Flow of net clustering and TSV-island insertion.
Relationship: reasoning
Domain: Hardware
Sentence 1: A fixed pipeline can not efficiently orchestrate the prediction process as it needs to guarantee a fixed throughput total active clock cycles under the worst condition.
Sentence 2: a fine granularity, self­ 10e1 10 12 3 4 56 7 8 9 10 9 Testing Video sequences 8 7 6 5 testvideoseque4 nces 3 2 adaptive pipeline shown in Figure 5, is proposed which is self 9 2 1 1 8 No.ofgatedcl7ocks 6 5 4 3 1. container 2. mother daughter 3. news  4. akiyo   5. foreman adjustable under input combinations.
Relationship: reasoning
Domain: Hardware
Sentence 1: This configurability partially enables/disables the error detection on the less significant N bits of the fraction determined through the error_significance_threshold clause.
Sentence 2: the FP pipeline is able to detect and correct any timing error if it is reconfigured for the accurate mode; on the other hand, in the approximate mode the FP pipeline ignores any timing error on the less significant N bits of the fraction.
Relationship: reasoning
Domain: Hardware
Sentence 1: Furthermore, FPGA clock rates have remained stable for sometime, with 250-300Mhz being a maximum clock rate on high-end commodity FPGA products for greater than 5 years.
Sentence 2: when wanting to manipulate high speed net­work streams such as those at and beyond 10Gbps, FPGA­based designs must capitalise on the increased gate-count: the designs must become larger and inevitably more com­plex.
Relationship: reasoning
Domain: Hardware
Sentence 1: physical CBRAM crossbar implementation with a 130nm CMOS process, where the sheet resistance is 0.06O/D and the minimum width of interconnect metal is 0.2µum (for M2 and M3).
Sentence 2: in the following simulations, Rmesh is estimated to 0.12O and Raccess to 5O (corresponding to a metal line of 0.2µm×16µm).
Relationship: reasoning
Domain: Hardware
Sentence 1: In order to obtain the desired wave with target sink nearest to source during each iteration, ViaBuf only marks each wave with its target sink, while modi.ed RMP marks each wave with the reachable sinks of solutions.
Sentence 2: solutions in a wave might have di.erent reachable sinks in ViaBuf al­gorithm, but all these solutions are intended to build a tree for this target sink.
Relationship: reasoning
Domain: Hardware
Sentence 1: Theorem2.Inarecursivebi-partitioningapproachon anidealcircuit,themaximumroutingdemandoverallthe 2H 1;a tileboundariesCmaxC11;a,whereC1isthenetcutof thefrstbi-partitioninganda=Ci+1/Ciistheratiobetween netcutsoftwoconsecutivepartitioningoperations.
Sentence 2: proof:Infgure1(b),thecircuitispartitionedintotwo partswithanetcutC1.ThismeansthatthereareC1nets crossingfromlefttoright,orviceversa.Letuslookata tileboundarylocatedattherighthalf.Intheworstcase, alltheseC1netspassthisspecifcboundary.Hencethefrst bi-partitioningcontributesC1totheroutingdemandofthis boundary.Similarly,theithbi-partitioningcontributesCi totheroutingdemand.foranyboundary,theupper boundofthemaximumroutingdemandis 2H 2H;1 XX1;a2H i Ci =C1 a=C1 .
Relationship: reasoning
Domain: Hardware
Sentence 1: Finally, the tra.c characterization and consequently the quality of ser­vice require special attention due to the new requirements that arise with the implementation of IoT, whose main char­acteristic involves heterogeneous technologies.
Sentence 2: this research proposes to address these open issues, summarized below, and of fundamental importance for the IoT [1] [3]: Mobility in heterogeneous scenarios;  Standardization taking into consideration the various involved technologies;  Tra.c characterization;  Quality of Service -QoS taking into account the new requirements arising from the heterogeneity of involved nodes.
Relationship: reasoning
Domain: Hardware
Sentence 1: Two points ((a1, (a1k1 + y1)%B) and (a2, (a2k2 + y2)%B)) are in the same group as long as con.guration in which every pair of faults are not in the same group.
Sentence 2: at the time when a data block ac­ cumulates f faults at most C f 2 + 1 re-partitions have been performed.
Relationship: reasoning
Domain: Hardware
Sentence 1: Denoting by x(k1,k2)=[xk1 ··· xk2 ]T,with 1 = k1 <k2 = n, a generic subvector2 of x, it will come in handy later to express the quadratic variation of x(k1,k2)interms of x.
Sentence 2: introducing the diagonal matrix S(k1,k2) .Rn×n de.ned as S(k1,k2)= diag {s1,··· ,sn} (3) with  1 ,k1 =i=k2 si = , 0 , otherwise the quadratic variation of x(k1,k2) can be computed as [x(k1,k2)] = DS(k1,k2)x 2 .
Relationship: reasoning
Domain: Hardware
Sentence 1: The logic high-level VH corresponds to a positive input voltage whereas the logic low-level VL corresponds to a negative input voltage.
Sentence 2: each couple of memristors {Mij+, Mij-}, with conductance Gij+ and Gij­associated to a differential input {Xi+, Xi-} constitutes a signed­synaptic weight Wij = K (Gij+ - Gij-) from input i with state Xi to output j with state Xj.
Relationship: reasoning
Domain: Hardware
Sentence 1: Provided that M1, M2, M3 and M12 work in the ohmic region, upon ideal transistors matching, the whole set of equations developed for the divider still holds.
Sentence 2: assuming a floating load CL at the transconductor´s outputs (see Figure 3 a)), the differential current IL through this load can be expressed as: 1 Iz + + I = (Vin -Vin -) = Gm (Vin -Vin -).
Relationship: reasoning
Domain: Hardware
Sentence 1: As observed in the table, the function Table II: Synthesis results: Con.guration functions function Area [µm2] total power [µW/GHz] Optical network I 1 052 686 Optical network II 366 663 Electrical network 363 725 used in the "Optical Network I" is the largest one; it requires 1052µm2, which is 3 times the area of the other functions.
Sentence 2: the overhead reported in table I represents the worst case of the three examples.
Relationship: reasoning
Domain: Hardware
Sentence 1: = .Lu(ni)= Lu(nj ), ki kj where the function L(ni)and Lu(ni) denote the respective length and unit length of the capacitor net ni (i.e., Lu(ni)= L(ni)/ki).
Sentence 2: if the unit lengths of all capacitor nets are the same, the length ratio exactly matches the desired capacitance ratio.
Relationship: reasoning
Domain: Hardware
Sentence 1: Another advantage of our model, is to avoid deadlocks, be­cause, as shown in Figures 4 and 5, the codes .nally gen­erated for computation tasks and server tasks (here from the code of Figure 3) are completely symmetrical, and re­tain the control .ow of the initial code.
Sentence 2: even if the execution conditions of communications are not known at compile time, they are the same on the server tasks and on the computation tasks during the execution, and the runtime ensures that there is always one, and solely one, consumer access per produced page of a communication bu.er.
Relationship: reasoning
Domain: Hardware
Sentence 1: 18: } 19: } 20: } 21: } Fig.5 Algorithm of DFT Strategy 2 of ATPG patterns of blocks except Bfs must not exceed TP(Bfs) so that TP(Bfs) is nearly equal to the number of ATPG patterns of an LSI from Assumption 1.
Sentence 2: this algorithm takes notice that the numbers of ATPG patterns of partial scan design blocks must not exceed TP(Bfs) (from 15th line to the 18th line of Fig.5).
Relationship: reasoning
Domain: Hardware
Sentence 1: Also, increases in associativity cannot choose which sets to merge, while the SBC can be implemented using either a static policy, which also preestablishes which sets can be as­sociated, or a dynamic one that allows to associate a set with any other one.
Sentence 2: as we will see in the evaluation, the SBC achieves better performance than equivalent increases in associativity while not bringing their inconveniences.
Relationship: reasoning
Domain: Hardware
Sentence 1: The partition, {Tk(i, cs, nsk)}, represents how the next state of each latch, nsk, depends on the values of inputs, i, and the current state, cs, of all latches: 1 We do not distinguish between sets, relations, and their characteristic functions.
Sentence 2: it is possible to think of [(cs), Img(ns), and T(i, cs,ns) as completely specified Boolean functions represented using e.g.
Relationship: reasoning
Domain: Hardware
Sentence 1: However test sequences conversion is infeasible in same cases, because of the presence of faults which are detectable on the SEFSM, but undetectable on the REFSM [7].
Sentence 2: we propose a procedure to generate a new kind of EFSM, which is exactly equivalent to the REFSM, but it preserves the traversing characteristics of the SEFSM (see Section 4).
Relationship: reasoning