sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Because most requests in the request buffer be­come marked with a small BatchDuration, the scheme prioritizes memory-intensive threads with high row-buffer hit rates.
Sentence 2: a small BatchDuration effectively eliminates request batching and degenerates to a row-hit-.rst, rank-.rst, oldest-.rst prioritization pol­icy, which (similar to FR-FCFS) penalizes less-intensive threads with low row-buffer locality, as shown in Figure 12(middle) and (right).
Relationship: reasoning
Domain: Hardware
Sentence 1: In addition, since deg(p(x)) = z, the terms with the lowest z powers of x in a(x) do not contribute to the quotient of a(x)/p(x).
Sentence 2: the computation of r can be simpli.ed as: r = Q(' n-k)×(n-k)a ' , (6) where a ' =[an-k+z-1,an-k+z-2, ··· ,az]T is a vector formed by the coe.cients of the terms with the highest n -k pow­ers of x in a(x).
Relationship: reasoning
Domain: Hardware
Sentence 1: We observed that unfor­tunately all the SSDs tested provide insu.cient information to understand SSD internal characteristics; in particular, all the data are normalized or provided as percentage based on their lifespan expectations, and some SSDs do not even re­port their PE cycles on reads.
Sentence 2: we present the reliability evaluation results of a speci.c version of SSD-A, which is used in Apple MacBook Air; unlike other SSDs we tested, SSD-A provides absolute maximum/average PE cycles on both reads and writes.
Relationship: reasoning
Domain: Hardware
Sentence 1: (a) HEMT Structure under optical illumination (b) Small Signal Equivalent Circuit of HEMT under illuminated Condition HEMT to be used as photo-detector utilizes modulation doping to increase the free electron carrier concentration without increasing the scattering rate.
Sentence 2: it is also modulation doped field effect transistor (MODFET).If a wide band gap material such as AlGaAs n-type material forms a hetero junction with a narrow gap, intrinsic material, such as GaAs, then electrons will move from wide band gap material to the narrow band gap material to equilibrate the Fermi level.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, relating to class capacity of X and Y, the covariance in different cases can not be directly compared, therefore they need to be marked, which is shown in Formula 4 (4) This indicator can be called decisive coefficient , ranging from 0 to 1, and its values reflect the degree of the correlation between two sequences, but it can not reflect the correlation direction of the sequences.
Sentence 2: through Formula 5, this indicator can grow into the one that not only can indicate the degree of correlation but also reflect the direction.
Relationship: reasoning
Domain: Hardware
Sentence 1: Secondly, since domain C has a tighter voltage droop constraint (50mV), a large number of LDOs are put here to reduce the maximum voltage droop so that the stringent requirement (4) can be satis.ed.
Sentence 2: the input voltage and overall power e.ciency of the circuit is mostly determined by the LDOs in domain C. Since the Vdd level in C is low and the LDOs in this domain have large input-to­output voltage di.erence, the power e.ciency driven optimization tries to lower Vin in order to raise up the e.ciency.
Relationship: reasoning
Domain: Hardware
Sentence 1: More­over, it does not distribute the documents homogeneously in all classes.
Sentence 2: the resulting taxonomy annota­ Directories Arch Biol Buss Cook Lang Neur News Heal Taxonomy Max tree depth 5 11 5 7 8 5 4 6 Total nodes 125 1610 213 674 515 210 29 259 Total Documents 1163 9202 7180 16124 4125 2446 517 8683 Vocabulary Label words 210 1671 238 595 501 230 36 312 Vocabulary size 729 2140 682 869 883 644 561 702 Average words/docs 10.80 8.61 8.88 7.86 8.91 9.63 10.34 8.23 Documents Labels in Docs (%) 94 100 99 100 100 88 98 99 Contextual Labels in Docs (%) 72 73 85 89 90 70 89 77 Local Labels in Docs (%) 45 60 62 75 64 51 70 58 Arch = science>social sciences>archeology Biol = science>biology Buss = business>business and services Cook = home>cooking Lang = science>social sciences>language and linguistics Neur = health>conditions and diseases>neurological disorders News = news>media Heal = shopping>health Table 1: Some taxonomies statistics.
Relationship: reasoning
Domain: Hardware
Sentence 1: On the other hand, the SER of combinational logic within the processor increases quite rapidly as the feature size is reduced [6] and as voltage is decreased [4].
Sentence 2: given that memory arrays can a.ordably be hardened using parity, Hamming codes, or ECC since the cost of the coding logic is amortized over thearray, focusing onhardeningthecombinationallogicand state throughout thedatapathwillbecome theprimary chal­lenge.
Relationship: reasoning
Domain: Hardware
Sentence 1: It is .rst dXEX applied to the left half of to get a modi.edm-bit dXEX value pNow, the CRS operation is again performed dXEX dXEX on pto get the transformed value m. This makes all the bits in a given crosstalk pattern adjacent to each other dXEX and located in the MSB region of .
Sentence 2: dis­ dXEXm persed values in the originalmap to continuous val­ dmXEX ues in .
Relationship: reasoning
Domain: Hardware
Sentence 1: To see this, suppose that the gain of the ampli.er is A,the input voltage is Vin and the initial voltage of the ampli.er output is Vs,weget A· Vin = -(Vs -Vin).
Sentence 2: (4) the voltage at the input node can be written as Vin = -Vs/(1 + A).
Relationship: reasoning
Domain: Hardware
Sentence 1: The formulation of the .rst con­straint in equation 7, actually captures whether there is a higher probability of glitch occuring at the gates in the tran­sitive fan-in of the gate i or if there is a higher probability of glitch occuring on the gate i itself.
Sentence 2: simultaneously bounding the slack variables along with maximizing Xk * Sk forces selective minimization or maximization of gate sizes of the gates depending on the higher probability of the oc­curence of a glitch, either on transitive fan-in of the gate or on the gate itself.
Relationship: reasoning
Domain: Hardware
Sentence 1: 2 shows that the bit error rate based on the rapid convergence schedule with 6 iter­ations outperforms that based on the standard and over­lapped schedule with 10 iterations.
Sentence 2: the decoder based on the rapid convergence schedule achieves 3.33 times and 1.66 times faster compared to that based on the stan­dard and overlapped schedule respectively.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, the contention 1-Pcon va probability, Pcon idle can be estimated as NV n ' « X j-1 ' Ppeh (1 -Pready busy) Pcon idle = Ph(j) 1- j NV j=2 « ' o Ppeh (1 -Pready busy) +Ph' (j-1) .
Sentence 2: (9) NV we have Pcon va as a combination of Pready busy and Pcon idle, which are recursively correlated.
Relationship: reasoning
Domain: Hardware
Sentence 1: Thus, employing preventive techniques is necessaryfor LLCs to prevent severe yield losses.
Sentence 2: 2.2 Narrow-width Values The narrow-width value contains meaningful data values in the LSB side and the remaining bit portion in the MSB side is filledwith all 0 s. only storing the meaningful portion of data values is enough and the remaining part of the data values can befilled by using zero-extension logics.
Relationship: reasoning
Domain: Hardware
Sentence 1: Furthermore, the closed formula ne­glects some integrality properties that the topology naturally has.
Sentence 2: instead of using Theorem 2 it is possible to calculate a slightly better bound using Hu.man coding [19]: If we set ss = RATs -ATr -cwire dist(Pl(r),Pl(s)) for all s .S, order these values s=s=···=s s1 s2 sn and iteratively replace the largest two sand sby sn-1 sn -cnode +min{ssn-1 ,ssn }= -cnode + s sn-1 until only one value s * is left, then the maximum possible slack with respect to our delay model is at most s * .This bound is never worse than the closed formula of Theorem 2.
Relationship: reasoning
Domain: Hardware
Sentence 1: An AND gate with inputs x and y with independent proba­bilities 0.4 and 0.5, respectively, will have an output z with probability 0.2 since for an AND gate, P(z =1)=P(x=1,y =1) (2) =P(x=1)P(y =1).
Sentence 2: using only combinational logic, we can get the additional set of probabilities {0.2,0.6}.
Relationship: reasoning
Domain: Hardware
Sentence 1: [2] that these cross-layer protocols perform pairwise cross-layer de­sign within limited scope, referring to cross-layer design only between two layers, and do not consider all of the OSI lay­ers involved in the communication of WSNs such as the transport, routing, medium access control, and physical lay­ers.
Sentence 2: they propose a single uni.ed cross-layer proto­col which combines these layers in order to provide e.cient and reliable communication for WSNs.
Relationship: reasoning
Domain: Hardware
Sentence 1: In contrast, for the Lean-OoO core, PIF fails to improve PD, and for the Lean-IO core, PIF actu­ally diminishes PD, providing less-than-linear performance density benefit that cannot compensate for its area overhead.
Sentence 2: we conclude that lean-core processors benefit from instruction prefetching nearly as much as fat-core designs, but mandate area­efficient mechanisms to minimize the overhead.
Relationship: reasoning
Domain: Hardware
Sentence 1: 6) includes a main block that computes correctly most of the time but makes inter­mittent VOS or process variation induced errors.
Sentence 2: ya[n]= yo[n]+ 1[n], (2) where ya[n] is the main block output, yo[n] is the error-free output, and 1[n] is the signal representing timing errors due to VOS or process variations.
Relationship: reasoning
Domain: Hardware
Sentence 1: It can be seen that the number of MOSFETS switching their PWNL regions can be more than 200 during one low-rank update, and it is more expensive to compute LU factors by low-rank update than by full LU factorization.
Sentence 2: in practice, whether to use low-rank update or full LU factorization should be determined based on the pre-set ratio of the number of switching nonlinear devices over that of total nonlinear devices.
Relationship: reasoning
Domain: Hardware
Sentence 1: This model generates correct output waveforms in the presence of i) arbitrarily shaped and timed input waveforms, ii) multiple-inputs glitching, iii) arbitrary loads, and iv) external noise coupling.
Sentence 2: this model is suitable for computing glitch delays for noise window calculations [3], for computing the effect of coupling on noise propagation in the presence of device non-linearities or for arbitrary loads, and even for generating data for building the mathematical model, as was proposed in [8] for creating timing models.
Relationship: reasoning
Domain: Hardware
Sentence 1: Although the technology scaling treadmill has continued, doubling transistors Active Leakage PowerTotal Power (mW) (mW) 103 101 1 102 10-1 101 10-21 every generation, reduction in supply voltage scaling does not reduce energy per operation to utilize all the transistors.
Sentence 2: supply Voltage (V) the next challenge we face is of energy efficiency not 65nm CMOS, 50°C 450 101 just low power but to continue to deliver logic throughput with Energy-Efficiency(GOPS/Watt) much less energy consumption.
Relationship: reasoning
Domain: Hardware
Sentence 1: 70 Proceedings of the International Conference on Computer Aided Design (ICCAD 03) 1092-3152/03 $ 17.00 &#38;#169; 2003 ACM Feasible Bus Checking Orientation According to Theorem 1, if the blocks of a bus violate block ordering in the given sequence pair, the bus cannot be assigned.
Sentence 2: the .rst step is to identify these buses and remove them from the bus set.
Relationship: reasoning
Domain: Hardware
Sentence 1: Since, P/G TSVs are an integral part of the 3D PDN, they should be optimally planned, to realize a reliable power supply design in 3D-ICs.
Sentence 2: it is necessary to consider the TSV placement [1], [10] as well as the TSV sizes [11] when minimizing the IR-drop of 3D-ICs.
Relationship: reasoning
Domain: Hardware
Sentence 1: 5 shows that our Memristor ACU is immune to certain magnitude of noise and the immunity varies v with the category of the function: For example, sin(x) and x -1 are more sensitive to the noise while exp(-x2) and xcan tolerate the noise with larger magnitude.
Sentence 2: during the application of the Memristor ACUs, the noise condition must be well controlled below the corresponding level for speci.c functions.
Relationship: reasoning
Domain: Hardware
Sentence 1: D. Mitigation Techniques for Emerging NVM Memory The bene.ts of using these emerging memory technologies in computer system design can only be achieved with miti­gation techniques that can help address the inherited disad­vantages that related to the write operations: (1) Because of the non-volatility feature, it usually takes much longer and more energy for write operations compared to read operations; (2) Some emerging memory technologies such as PCRAM has the wear-out problem (lifetime reliability), which is one of the major concerns of using it as working memory rather than storage class memory.
Sentence 2: introducing these emerging memory technologies into current memory hierarchy design gives rise to new opportunities but also presents new challenges that need to be addressed.
Relationship: reasoning
Domain: Hardware
Sentence 1: Latency of 2D and 3D multi-channel con.gurations for UR traf.c.
Sentence 2: .at switch, as seen from the frequency numbers in Table V. the throughput of CLRG is slightly lower than the 3D L2L LRG, but compared to a 2D switch, they have 15% better throughput.
Relationship: reasoning
Domain: Hardware
Sentence 1: By addressing case (1) and (2), we create the set of interval windows shown in Table 1.
Sentence 2: to prove (1), note that k(i,o,x,m) = k(i,o,x,m -1) + IM[, where M is the set of all nodes such that TASAP = m. the expan- sion of interval [x to m -1] to [x to ra] is a trivial process that can only improve the quality of the bound (because now we have the chance to consider more nodes that can be scheduled before m, i.e., k( i, o, x, m) = k( i, o, x, ra -1) + IMI).
Relationship: reasoning
Domain: Hardware
Sentence 1: For a discrete-time system (4), the control action becomes aggres­sive (i.e., more reactive or responsive) with the system poles closer to zero which results in a shorter settling time ts.On the other hand, the maximum input signal requirement Umax becomes higher when the system poles are placed closer to zero (i.e., with an aggressive controller).
Sentence 2: the control design mainly hinges on meeting the two con.icting requirements C1 and C2.
Relationship: reasoning
Domain: Hardware
Sentence 1: It can be shown that the voltage at any node i in the electrical network is equal to the expected gain the walker will receive if he starts from the corresponding node in the random walk.
Sentence 2: the node voltage can be estimated by running N walks from node i as N , (2) Vi = 1/ N · .Dk k =1 where Dk is the gain of the kth walk.
Relationship: reasoning
Domain: Hardware
Sentence 1: It can be observed that the SEU tolerance has been built into the logic function being realized.
Sentence 2: after reducing the truth table using Karnaugh Maps, the OR function can be represented in our approach as OR = E ( A + B) + P E Repeating the similar steps for standard 2 input AND, XOR, as well as Full Adder circuits yields the following expressions:   AND= E (A B)+P E XOR= E (AB + AB)+P E FullAdder_Sum= E (A.B.C)+P E  FullAdder_Carry= E (AB+BC+ AC)+P E Based on these expressions, the generalized expression for any logic function F therefore becomes, Fhardened = E (F ) + P E from the above expressions it is clear that the proposed technique uses the error signal from the decoupled ground line as a control signal to allow only correct transitions by the circuit being hardened.
Relationship: reasoning
Domain: Hardware
Sentence 1: 8 Pareto-optimal Front of jitter, gain and current of VCO (a) 3-D (b) projection on gain vs. current (c) projection on gain vs. current plus contour lines of jitter (d) projection on jitter vs. current pluscontours of gain (e) projection on jitter vs. gain plus contours of current Asmentioned in Sec.3.2, we can assume that the optimal solution will be on the Pareto front.
Sentence 2: we calculate explicit analytical models for the Pareto fronts of the behavioral­level parameters and thus reduce the design space.
Relationship: reasoning
Domain: Hardware
Sentence 1: EVALUATION We.rstpresenttheendurancepotentialofdynamicallyreplicatedmemorybycomparingPCMcapacityandlifetimeunderSECDEDECCandDRM.Wethenquantifytheperformanceoverheadofdynamicreplicationwithlazyandeagerreplicationpoliciesat   hasenoughvalidpagepairstohandleincomingfailures.Sincethememorycontrollercannothandleerrorswhenthereadytableentriesareexhausted,wemustensurethatthecapacityofthereadytableislargeenoughtomakesuchaneventextremelyunlikely.
Sentence 2: toboundtheprobabilityofthiseventoccurring,weconsiderintervalsofn secondsinourexperimentsabove.Thereadytableholds128entries,sowewouldliketoshowthatthememorycontrollerisunlikelytousemorethan64entriesinanintervalandthattheoperatingsystemislikelytore.llatleast64entriesinaninterval.duringeachinterval,theoperatingsystemwillbecapabletore.llingtheentriesusedbythememorycontrollerinthepreviousinterval,whilehavingenoughcapacitytotoleratethememorycontroller susageinthecurrentinterval.
Relationship: reasoning
Domain: Hardware
Sentence 1: When technology scales down into 45nm and 32nm technol­ogy, each SKITTER sensor tends to have increasing number of stages, thereby larger area overhead.
Sentence 2: stage count and transistor count for TSUNAMI PSN sensor and SKIT-TER sensor are estimated at di.erent technology nodes as shown in Columns 2 through 5 of Table 4.
Relationship: reasoning
Domain: Hardware
Sentence 1: Another factor, linked to the low volume of this sector, was the low interest from ASIC s vendors for this market, and finding an ASIC was becoming challenging.
Sentence 2: infrastructure products designed in late 90 s are essentially based on ASSP s and glue FPGA s. These IC s are currently fulfilling all the needs, in terms of capacity and speed, of these products leaving no room for ASIC s.  After the major downturn of the overall telecom industry, infrastructure equipment is now facing two challenges.
Relationship: reasoning
Domain: Hardware
Sentence 1: We then showed that the same problem can­not be solved in the DSM model with the same parameters, even if we weaken these parameters in all of the following ways simultaneously: (1) we allow only one signaler instead of many, (2) we settle for O(1) RMRs complexity in the amortized sense rather thanin the worst case,(3) we allow unbounded space,(4) we weaken theprogress conditionfrom wait-freetoterminating,and(5) weallow useofCompare­And-Swap or Load-Linked/Store-Conditional in addition to reads and writes.
Sentence 2: we separatetheCC andDSM mod­els in terms of their power for solving the signaling problem e.ciently with respect to amortized RMR complexity.
Relationship: reasoning
Domain: Hardware
Sentence 1: The heat due to viscous dissipation in­creases from 0.91 W in 2002 to 1.13 W in 2003.
Sentence 2: in the sec­ond region, due to the higher rotational speed growth (and its relationship in the cubic power), the viscous dissipationgrows from 2 W in 2004 to over 35.55 W in 2009, caus­ing a signi.cant rise in temperature, well beyond the ther­mal envelope of 45.22 C. all other things remain­ing constant, it is clear that future single platter disk drives would not be able to provide the desired IDRs at the 2.6 platter size.
Relationship: reasoning
Domain: Hardware
Sentence 1: 8 >>>>>>>>>>>>>< >>>>>>>>>>>>>: init(y0)=1 init(y1)=0 init(y2)=0 next(y0)=(,0 .,1).¬y0 next(y1)=(,0 .,1).¬y1 next(y2)=0 init(,0)=1 init(,1)=0 next(,0)=0 next(,1)=,0 .,1 Figure 10: Final acyclic equation system for program Q1 The main purpose of our method is to transform an equa­tion system with cyclic dependencies into an equivalent acyc­lic one.
Sentence 2: it can be used for the translation of Quartz or Esterel programs with delayed actions to acyclic equation systems.
Relationship: reasoning
Domain: Hardware
Sentence 1: Furthermore,ontinuedaggressivesalingdownofVLSI featuresizehasinreasedtherequirementforoxideplanarity inanSTIproess,beauseoneofthemostdiÆultphoto­lithographystep.gatepatterning,isimmediatelyafterSTI.
Sentence 2: oxideplanarity,defnedasthediferenesofoxidethikness attrenhedgesfordiferentlayoutloations,dependson CMPuniformityinSTI.Forthe193nmgenerationstepper with0.75numerialaperture,thedepthoffous(DOF)is about4000AAfternormalrandomproessvariation A.on­sumes2000AAandavariationbudgetof1000A alloatedfor deposition,bake,lean,eth,andstripotherthanexpo­sureinanormalphotostep,DOFisonlyabout1000A.AInaddition,thephotostepinSTI,althoughmuheasier thangatepatterning,hashundredsofangstromsofvaria­tion[4].toensuremanufaturabilityofadesign, totaltopographyvariationfromtheCMPstepinSTImust beontrolledtobewithinonlyafewhundredangstroms.
Relationship: reasoning
Domain: Hardware
Sentence 1: The transistors P1, P2, P3, P8, P9, and P10 form a bank of four transistor current mirrors.
Sentence 2: the transistors P1 to P3 and  P8 P9 P10 P13 P12 P11 P14 P15 P16 P1 P2 P3 P4O- P5 I+ N1 N2 P6 I- P7 O+ Ibias N5 N6 N7 N8 N9 N10 N14 N12 N11 N13 N3 N4 Figure 10: Schematic of circuit 3 [17].
Relationship: reasoning
Domain: Hardware
Sentence 1: According to De.nition 3, the power-network resource re­quirement of the .oorplan in Figure 1(a) is greater than that in Figure 1(b) since both bounding boxes of VDDH and VDDL blocks in the .oorplan of Figure 1(a) are larger than those of Figure 1(b).
Sentence 2: the .oorplan in Figure 1(b) is more desirable.
Relationship: reasoning
Domain: Hardware
Sentence 1: First, if two tran­sistors that are adjacent in the ordering have a di.usion net in common, then the net may be shared in di.usion between the two transistors, resulting in a brick width reduction of one poly pitch (see Figure 2).
Sentence 2: a good ordering will minimize brick width by allowing for as much di.usion shar­ing between adjacent transistors as possible.
Relationship: reasoning
Domain: Hardware
Sentence 1: In Mapping B, where FPGAs are utilized, the time asso­ciated with FPGA simulation constitutes the major simula­tion performance bottleneck and parallelizing this simula­tion component yields almost a linear reduction in simula­tion time.
Sentence 2: with two processors the speedup is almost 2, and with four processors the speedup is nearly 4.
Relationship: reasoning
Domain: Hardware
Sentence 1: Moreover, many of the experimental stud­ies present in the literature ignore the fact that most of the contemporary communication systems employ very complex and sophisticated transmission and multi access techniques such as the use of di.erent modulation schemes and bursty communications.
Sentence 2: in this study, a comprehensive and .exible experimental setup with various practical sce­narios is established in order to evaluate the performance of energy detection method for spectrum sensing.
Relationship: reasoning
Domain: Hardware
Sentence 1: To compare this method with the uniform coding,we encoded the ASCII characters with the codes from ..(7, 1), ..(7, 2) and ..(7, 3) and report the corresponding average costs in the following: Encoding Data-aware ..(7, 1) ..(7, 2) ..(7, 3) Avg cost 1.24 1.42 1.37 1.34 We see that the ASCII data-aware coding,on average, reduces the energy cost to 92% of the best cost achieved from ..(7, 3).
Sentence 2: for overwriting each ASCII character, there will be an 8% reduction in the energy cost compared to the results of the uniform encoding.
Relationship: reasoning
Domain: Hardware
Sentence 1: In the meanwhile, participants should investigate the powerful CNF encoder for converting the CircuitSAT problem into CNF format [16].
Sentence 2: the final program should have two modes: in setting exploration phase, the program should optimize and generate the SAT solver setting and encoder setting based on the small set of samples, and in the solving phase, the program becomes a CNF encoder that converts a CircuitSAT problem into CNF, based on the optimized setting.
Relationship: reasoning