sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Since the null space of E is normally .ltered out in Krylov subspace constructions [4], the resulting ROM is normally  1C-1 nonsingular which misses the Mi (i =0, 1, ···) term in the original model.
Sentence 2: the polynomial term P (s) cannot be preserved by existing Krylov-subspace projec­tions.
Relationship: reasoning
Domain: Hardware
Sentence 1: From this figure, we can easily see that, at a fixed CPU clock frequency, CPIavg is linearly related to MPIavg as follows: CPI =b f()·MPI +c (6) avg avg where b(f) is frequency-dependent slope.
Sentence 2: notice that intercept c is equal to the average on-chip CPI, CPIavg onchip and is independent of frequency f. Eq.
Relationship: reasoning
Domain: Hardware
Sentence 1: In addition, for applications with self-modifying code (e.g., runtime code generation), parity-protected instruction caches will have problems to correct the transient errors even if they are detected.
Sentence 2: in order to protect the instruction cache ap­propriately to meet the reliability requirement without over-compromising other design constraints, such as performance and energy consumption, the .rst step is to understand and measure cache vulnerability to transient errors accurately and quantitatively.
Relationship: reasoning
Domain: Hardware
Sentence 1: Each time a job Ji tries to access a gcs, this can be currently locked by a lower priority remote job of a task tj .lpr(i).
Sentence 2: the blocking time due to lpr tasks which share the same GR with Ji is given by the longest gcs of tasks in the set .i,j: G (.GR Bi2(wi(q))= q · ni · max j ) (7).tj..i,j Each job Ji can also be blocked by hpr jobs that request the same GR as Ji (i.e.
Relationship: reasoning
Domain: Hardware
Sentence 1: But, what is important to note here is that, while a small degradation in the fair speedup metric (e.g., below 1) is tolerable (although not preferred as we would like to maximize the fair speedup metric), we cannot tolerate any degradation above a certain threshold (QoSTh).
Sentence 2: we can use the QoS metric to .lter the partitions that do not meet the QoS require­ment and be rest assured that we are not eliminating any potential candidates for optimization with respect to the fair speedup metric.
Relationship: reasoning
Domain: Hardware
Sentence 1: -5 x 10 -1.603 -1.025  When we use the perturbation 4×10-3sin(2p1.01f0t), which can­not lock the oscillator as shown above, the PPV-HB does not converge.
Sentence 2: our PPV-HB can be exploited as a useful approach to help predict injection locking: the oscillator is injection locked if PPV-HB converges.
Relationship: reasoning
Domain: Hardware
Sentence 1: As to other levels, the wire length of control signals is the sum of the wire lengths of upper level clock edge all ways up to the root.
Sentence 2: the power consumed by clock edge i at level n can be expressed as: Pclk(i) =kclk AiLclk(n) = Wclk(n) Ai (7) where kclk is a constant, Wclk (n) = kclk Lclk (n) , and Ai is the number of active periods of the node connected to clock edge i.
Relationship: reasoning
Domain: Hardware
Sentence 1: 5.3 Timing Analysis As described in the preceding section, we e.ectively use the carry chains that are present in the Stratix-III FPGA to mimic the logic chains we have proposed for the purposes of placement and routing; however, the critical path delays that are obtained from Quartus-II are based on the delays of the full adders on the carry chains, rather than the mul­tiplexers that we introduced in the logic chain.
Sentence 2: the delay of each adder in the carry chain should be replaced with the delay of the multiplexer instead.
Relationship: reasoning
Domain: Hardware
Sentence 1: The main reason behind this high degree of par­allelism is that, in RRAM, 4x many planes and 2x many dies compose a single page (as compared to conventional NAND .ash), and the size of incoming I/O requests for most workloads tested are large enough to span all macro­level resources.
Sentence 2: rRAM-128 successfully com­pensates for the potential performance loss caused by the slab-based memory access strategy.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, because M5 conducts current I5 and raises up VQbar, M1,2 s read-VTC has higher VQbar values than the hold-VTC at the neighborhood of VQ = 800mV .
Sentence 2: the cell s stable state in the read operation is at the inter­section of the two VTCs, (800mV , 143mV ).
Relationship: reasoning
Domain: Hardware
Sentence 1: During the prop­agation, if an item from an arrival time is smaller than the time of the enabling clock edge in that local time zone, the constraint created from propagating this item further is dominated by the constraint created from the arrival time propagation starting from the enabling clock edge.
Sentence 2: we can remove such an item from the arrival time without a.ecting the timing con­straint represented by (30).
Relationship: reasoning
Domain: Hardware
Sentence 1: NODE ENERGY MODEL The relationship between power and energy is characterized as: ENODE=PNODE × tMODE (3) where ENODE is the energy consumed by the node PNODE is the power consumed by the node (from (2)) tMODE is the time spent by the node in a given mode As observed from Figure 6 and Figure 7, VSHUNT does not remain constant over the entire interval.
Sentence 2: the average value of VSHUNT has been considered in the calculation to provide a much stable result.
Relationship: reasoning
Domain: Hardware
Sentence 1: Latency constraints are often necessary in our pipeline syn­thesis .ow, because the loop exit condition needs to be com­puted within the .rst I I steps of the pipeline, in order to de­termine whether the next iteration should start when specula­tive execution is not performed.
Sentence 2: we implement swing modulo scheduling on top of the SDC system: every edge in the SDC constraint graph is regarded as a data dependence.
Relationship: reasoning
Domain: Hardware
Sentence 1: Nevertheless, the representative of an in-out module needs to be placed on the right or the top boundary.
Sentence 2: if the in-out module is a self-symmetry module, we have the boundary constraint for the corresponding node in an ASF-B*-tree as follows: Being the root node in a left-skewed branch or in a right-skewed branch: the representative would be placed   (a) (b) (c) (d) in the bottom-left corner and no module could be placed at either its top side or its right side.
Relationship: reasoning
Domain: Hardware
Sentence 1: It can be seen from Table 4 that the differences between the smallest and the largest accidental detection indices are signi.cant.
Sentence 2: the accidental detection  Table 5: Test generation Table 6: Relative run times tests circuit orig dynm 0dynm incr0  irs208 42 33 34 41 irs298 43 36 37 43 irs344 28 26 25 31 irs382 42 45 35 47 irs400 37 37 35 44 irs420 70 62 60 71 irs510 65 67 66 74 irs526 75 74 64 86 irs641 74 66 59 77 irs820 149 130 125 179 irs953 110 106 99 120 irs1196 179 162 153 209 irs5378 254 240 224 ­irs13207 411 397 342 ­ average    112.8 105.8 97.0 ­ index is expected to make a difference in the test set size and in the steepness of the fault coverage curve if used as a fault ordering heuristic.
Relationship: reasoning
Domain: Hardware
Sentence 1: The gel is a glycoprotein based substance with the same resistivity as seawater [5].
Sentence 2: the ampullae can detect electric .elds in the water through the Voltage di.erential at the skin pore versus the base of the electrore­ceptor cells that is, the di.erence in neurological activity between the terminal axons at the pore and those in the interior vesicles of the ampulla [6] as shown in .gure 2.
Relationship: reasoning
Domain: Hardware
Sentence 1: In addition, the DC power of the PA is more than 90% of the whole transmitter power with a com­plex modulation scheme like OFDM in 802.11p, since it requires back-off due to its high PAPR signals and the power ef.ciency is dramatically reduced as output power decreases from the satura­tion point.
Sentence 2: power management of the PA is crucial to .t the 802.11p front-end within a smartphone s stringent power budget.
Relationship: reasoning
Domain: Hardware
Sentence 1: Figure7(b)comparestheMHS-Dominocircuitwiththe MTCMOSCD-Dominocircuitintermsofdynamicpower at500MHzCLK.AlthoughtheMHS-Dominocircuitin­troducesslightlyhigherloading,andanSSG,itactually hassignifcantlylowerpowerdissipationthantheconven­tionalMTCMOSversion.Thisisattributedtothefollow­ing:1.EliminationofthecontentionintheMHS-Domino gate,whichmeansthattherearenoshort-circuitcurrents duringswitching.2.N1 andP1 areminimumsizedde­vices,contributingtoaverysmallloadingefect.3.The sleepsignalgeneratorhardlyconsumesanydynamicpower becauseitsoutputisalways1"duringtheactivemode, and0"duringstandby.Thus,noswitchingoccursexcept duringtransitionfromonemodetotheother.Thesetran­sitionsarenotfrequentandtheirpowerdissipationpenalty becomeslesssignifcantifthesystemstaysmostofthetime intheidlestate(95%) Acomparisonbetweenthenormalizedleakagepowerofthe MTCMOSCD-DominoandMHS-Dominoisalsoshownin Figure7(c).MHS-Dominoconsumesslightlyhigherleak-agepowerthantheMTCMOSCD-Domino(controlledNM).
Sentence 2: forlowVthvalues,theMHS-Dominoconsumeslessleakage powercomparedtotheconventionalMTCMOSversionat controlledNM.Thediferenceinleakagepowerbetweenthe twocasesisnegligiblesincetheleakagecurrentisinthe orderofpico-amperes.MHS-Dominoeliminates thecontention,enhancestheperformance,reducesdynamic powerdissipationandexhibitsverylowleakagecurrentdur­ingstandbywithminimalareaoverhead.
Relationship: reasoning
Domain: Hardware
Sentence 1: TheStaggerdatadistributionleadstoadiferentbehaviour ofPCS-Radixsort.Thecomputationofthebucketdistri­ butionCSEislargerthanthatfortherestofdistributions.
Sentence 2: conversely,thealltoallkeycommunicationislowerthan thatforotherdatadistributions.Allthisisduetothelarge localdataskewinthisdistribution.withthe Staggerdatadistribution,PCS-Radixsortreducessignif­icantlytheamountofdatacommunicatedbyreassigning bucketstoprocessors.
Relationship: reasoning
Domain: Hardware
Sentence 1: i) Tox: Oxide thickness ii) Nhalo: Halo peak doping concentration iii) lc: Characteristic lateral decay length of Gaussian halo Considering a three-dimensional space composed by the Tox, Nhalo, and lc, the yield optimization problem can be represented as follow: Maximize Yield = Px {C(x)=1} x=(Tox,Nhalo,lc) (1) Subject to : Variation in x elements where C, denotes a binary random variable de.ned based on desired bounds on ION and total leakage, and Px {C(x)=1}represents the probability that a device with parameters (x) satis.es constraints in presence of variation.
Sentence 2: c is formulated by (2).
Relationship: reasoning
Domain: Hardware
Sentence 1: 2.2 Crossing line effects and their simulation Thewaytoonsiderrossinglinesefetdependsontheir loalisationwithrespettoaT-line.Wedistinguishbetween twoases:(a)uniformrossinglinesdistribution,e.g.power  Figure2:Cross-setionsofsupportedgeometriesfor on-hipT-lineimplementation:mirostrip-like(a-d) ando-planar(e-f)strutures.
Sentence 2: grid,and(b)loalinreaseintherossinglinesdensity,whih anhappenduetopreseneofabus.Inontrasttothease ofjoints,splits,andbends,whoseefetonaT-linebehav­iorisusuallynegligible,aninterfereneausedbyabusmay haveasignifantontribution,foritswidthmayreahsev­eralhundredsofmirons(Consider,forexample,a64-bitbus with2flinesseparatedbylf,whosewidthreahesl9Of ).thesetionsofatransmissionlinewhihrun beneathorabovewiderossingbusanbeadequatelytreated.
Relationship: reasoning
Domain: Hardware
Sentence 1: Empirical analysis we performed with smaller thresh­olds, such as 0.1 and 0.2, showed that, due to the low level of redundancy in House A and House B, most of the sen­sor failures are classi.ed as severe.
Sentence 2: we chose a threshold that allowed us to have a more diverse failure pro­.le for all houses.
Relationship: reasoning
Domain: Hardware
Sentence 1: [Tclk + thold - T2 - D, Tclk - tsetup - T2] As seen in Figure 3, D occurs only if A occurs, that is, only if the amplitude of the glitch at the output F is larger than the switching threshold VS,latch, the duration will be different from zero, and then: D .
Sentence 2: a (7) and thus: A n D = D (8) the probability that a glitch originating at gate G is latched at the output F can be written as: P(A n D n T) = P(T n D) = P(t1 .
Relationship: reasoning
Domain: Hardware
Sentence 1: Theimportanceofstatepersistencecanbeseenfromthefollowing.Supposethatastates hasapersistentstatevariableyi .Consideringthecircuitinstates undertheall-xprimaryinputvector,weknowthatYi isspeci.ed.TheinputconeofYi canbepartitionedintoalogicblockGi whoselinesassumespeci.edvalues,andalogicblockHi whoselinesassumeunspeci.edvalues.Theunspeci.edvaluesinHi maybeduetotheall-xpri­maryinputvector,orbecauses ispartially-speci.ed.FaultsaffectingthelinesinHi cannotbepropagatedtoYi ,sinceYi assumesaspeci.edvalueindependentofthevaluesofthelinesinHi .Inaddition,therearefaultsinGi thatcannotbeactivatedsincetheiractivationrequirestheoppositevaluetothatassignedtothefaultsiteunders .Finally,Yi mayalsobeinsensitivetovaluesoflinesinGi .Forexample,ifYi istheoutputofanANDgatewithoneinputequalto0andtheotherinputequalto1,Yi isinsen­sitivetotheinputequalto1,andpossiblytosomeofthelogicdrivingit.
Sentence 2: withahigherpersistencep(s ),thereisalargernumberofstatevariablesthatassumespeci.edvaluesunders ,andalargernumberoffaultsthatcannotbeactivatedorpropagatedtocertainnext-statevariables.Thus,astates withahigherpersistencep(s )allowsfewerfaultstobedetected.duringtestgeneration,stateswithlowerpersistencearepreferable.
Relationship: reasoning
Domain: Hardware
Sentence 1: Then, the transfer function can be expressed by poles and residues.
Sentence 2: k1 k2 H(s)=+ (2) s + p1 s + p2 the relationship between the two poles and the four parameters ofthe RC circuit can be obtained from the com­parison ofequation (1) and (2) as the following two equa­tions 111 p1 + p2 =++ R1C1 R2C1 R2C2 (3) 1 p1 · p2 = R1C1R2C2 In addition, the relationship ofthe two residues and the two poles can be rewritten as p1 · p2k1 = p2 - p1 (4) p1 · p2k2 = p1 - p2 Supposing that, in time domain, the input voltage Vi(t) ofthis circuit is a unit step signal, the output response Vo(t) in term ofthe two poles and residues can be expressed as follows.
Relationship: reasoning
Domain: Hardware
Sentence 1: ( t d )0.0944 + Ccou pl = e 1.44 ( s d + 2.059s w )1.144 + + 0.7428( w + 1.592s w )0.1612) · +(1.158( w + 1.874s ) d )1.179 · ( (1) d + 0.9801s (() ) 2 · µ · x 2x L = ln + 0.5 + 0.2235(w +t) (2) p w +t Since the values refer to a top-level metal wire, the distance (d) to the ground plane in Eq.
Sentence 2: 1 is assumed to be large compared to the spacing s. the capacitance to ground will be neg­ligible compared to the coupling capacitance.
Relationship: reasoning
Domain: Hardware
Sentence 1: Resultsfortheextendedexperimentareplottedassolidlines inFigure2forM3andM4.Whiletheadditionofvirtualvias mimicsthebehavioroftherouterforhighernumbersof layers,theactualnumberofsuchhigherlayersisunknown.
Sentence 2: themodelofSai-Halaszcanbecheckedonlyagainst theoriginalcongestedresult(withoutvirtualvias).This comparisondoesnotshowaclosematchinFigure2.The ChenmodelfollowsexperimentdatawellforM3,butnotfor anyotherlayer.Figure2showsthat(i)nomodel accuratelypredictstheutilizationfactoronalllayers,even thoughwetunedtheroutingefciencytofttheexperiments and(ii)nomodelcorrectlypredictstherelationshipbetween viaimpactandthenumberofvias.Section4investigates thereasonsforthis.
Relationship: reasoning
Domain: Hardware
Sentence 1: Should a faulty input configuration subsequently occur (e.g., (a1 b1; a2 b2; ...; an bn) = (1 0; 1 1; ... ; 1 1)), because of the SOP, the internal node o1 maintains its previously charged high logic value (rather than being discharged through the conductive T1 and T2 transistors), so that a low logic value is maintained at the output and testout nodes, providing a Pass output indication, despite the faulty input configuration.
Sentence 2: a Pass, rather than a Fail, is generated because of the comparator internal SOP, with dramatic effect on microprocessor quality and test effectiveness.
Relationship: reasoning
Domain: Hardware
Sentence 1: Now we define the probability of detection pd as the probability of correct detection of a primary signal existence which can be calculated using ....= ....+..Q...-2.... ..(....2+....2)2..... .. (....2+....2)..        (8) Equation (9) is another form of (8) introducing the Signal-to-Noise Ratio (SNR), ., which is equivalent to (....2....2/) ....= ....+..Q...-2...... (..+1)....22....... (..+1)....2..         (9) According to the best of our knowledge, all the extensive work done in energy detection assumes a fixed value of pfa and accordingly calculate the other parameters, never the less, here we aim at minimizing pfa and maximizing pd at the same time which are two contradictory processes according to (6) and (9) with respect to the value of ts.
Sentence 2: an optimization solution is needed to evaluate the optimum value of ts.
Relationship: reasoning
Domain: Hardware
Sentence 1: Because of the principle of locality, it is fair to assume that the useful prefetched cache lines, in general, would be accessed within a short period of time after they are brought into the cache.
Sentence 2: it makes sense to put the prefetched cache line into SD leakage control mode if it is not accessed within this short decay period (anticipating that it will not be accessed at all).
Relationship: reasoning
Domain: Hardware
Sentence 1: Here, also the cost function is also designed to optimize for both performance and leakage waste, which is presented as follows: a a G = * LK + (1 - ) * ES T (3) 10 10 where, LK and EST represent leakage power and earliest start time for a placement; a is the leakage-schedule length trade-off coef.cients, which can be used to provide a balance between the two optimization goals.
Sentence 2: the cost function not only facil­itates to reduce the leakage dissipation but also provides designer the ability to manage the trade-off between performance (schedule length) and leakage saving.
Relationship: reasoning
Domain: Hardware
Sentence 1: C(P) = Z Ati (P), where Ati (P) is defined as, Ati (P) = ( ti (P) -Ti ) * PENALTY / Ti , if ti _>Ti ( Ti -ti (P)) * CREDIT / Ti , if ti <Ti The penalty factor is chosen to be much larger than the credit factor, so that violations are penalised greatly.
Sentence 2: in a given generation, high fitness strings are those whose corresponding placements have less violations.
Relationship: reasoning
Domain: Hardware
Sentence 1: When a marked request is fully serviced, the DRAM controller decrements TotalMarkedRequests.When TotalMarkedRequests reaches zero, the controller starts a new batch by 1) marking the oldest Marking-Cap requests per bank from each thread, 2) computing the new Max-Total ranking of threads us­ing the ReqsInBankP erT hread and ReqsP erT hread registers.
Sentence 2: the additional logic required by PAR-BS consists of logic that 1) marks requests (marking logic), 2) determines thread ranking (rank­ing logic), and 3) computes request priorities based on marked-status and thread rank (prioritization logic).
Relationship: reasoning
Domain: Hardware
Sentence 1: However, FPGAs circuit speed lag behind that of ASICs due to the fact that programmable switches used in FPGAs have higher resistance and capacitance and hence result in signi.cant delays.
Sentence 2: to make bet­ter use of FPGAs, timing optimization for FPGAs deserves more research e.orts in order to reduce the circuit speed gap between ASIC and FPGA.
Relationship: reasoning
Domain: Hardware
Sentence 1: In (15), .j1 = k(j,i) sk(j) D2DD2D j2(1 = j1,j2 = N), .m is independent from .m sk(j1) sk(j2).
Sentence 2: .m D2D is also described by a Gaussian dis­ sk tribution, 2 f.mD2D = N (0,smD2D ), (17) sk sk N 22 smD2D = smD2D , (18) sk sk(j) j=1 n s(j) nk(j) s mD2D = sdD2D - sdD2D .
Relationship: reasoning
Domain: Hardware
Sentence 1: We denote constraint Vclus2.Increasing Vclus2 can e.ectively reduce the total sleep transistor area while Vclus1 is no longer related  V 2 to the total area when Vclus1 >+ Vclus2RiIclus1.In clus2 practical designs, Ri is relatively very small compared with Rst.
Sentence 2: increasing Vclus1 becomes useless in re­ducing the total sleep transistor area when Vclus1 is slightly larger than Vclus2,because Vst1 is always slightly larger than Vst2 when the total sleep transistor area achieves the mini­mum.
Relationship: reasoning
Domain: Hardware
Sentence 1: If single faults f1 and f2 in S are identi.ed as equivalent by local fault collapsing, then multiple faults f m c1 and fcm 2 in C(S) corresponding to f1 and f2, respectively, are also equivalent.
Sentence 2: according to Theorem 1, the number of faults targeted by our test generation procedure can be reduced by local fault collapsing for S. the reduction of the target faults can reduce additive logics for modeling a mul­tiple fault as a single fault in MS-TEM.
Relationship: reasoning
Domain: Hardware
Sentence 1: On the other hand, the performance o.ered by the system should be at least close to that o.ered when using a conven­tional cachememory.
Sentence 2: inordertoimprovethe resulting performance, the instructions to be loaded and locked into cache memory must be chosen very carefully since this se­lection directly a.ects the execution and response times of the system tasks.
Relationship: reasoning
Domain: Hardware
Sentence 1: The cancellers in [8, 9] are aimed not at the power system shown in Figure 1(b), but at the power system shown in Figure 1(a); therefore, from the beginning, they are inadequate for reducing the output voltage droop of an off-chip-capacitor-free on-die LDO regulator.
Sentence 2: the power system shown in Figure 1(b) requires techniques other than voltage droop detection to reduce the voltage droop.
Relationship: reasoning
Domain: Hardware
Sentence 1: This leads to (CD /CS)dVT = VTmin, and thus CD /CS = VTmin/dVTmax = 40 when VTmin = 0.2 V and dVTmax = 5 mV.
Sentence 2: the FD-SOI enables successful sensing even with an extremely small CS (e.g., one­eighth that of the usual designs) for a fixed CD, enabling the use 4 3  t ( V T0 + .
Relationship: reasoning
Domain: Hardware
Sentence 1: If So>S+,-N (3) o we can substitute (2) with: S o+,?P2NMmodS>S+,-N(4) oo Recall that (VVBmodN.
Sentence 2: therefore: = (<N (5) Inequality (3) is satis.ed if O>,-N, which is true iff: N>, N>(-dN Od+l)N>( since N>(by inequality (5), inequality (3) must be true.
Relationship: reasoning
Domain: Hardware
Sentence 1: The most power efficient full 200 210 260 310 360 410 460 Delay (ps) adder for higher speeds is the XOR2-based, and the most power effi­ cient full adder for long delays is the mirror type.
Sentence 2: the cell li- Figure 3.5: Comparison among different full-adders in a 16 col­ brary must include the SUM-GEN cell since the mirror full adder has  umn 16:2 compressor.
Relationship: reasoning
Domain: Hardware
Sentence 1: It should be noticed that, provided that M1 operates in the saturation regime and that M2 operates in the linear regime, there are no constraints concerning the inversion level of operation of any transistor.
Sentence 2: the fundamentals of the integrator operation do not need to be justified by means of the asymptotical behavior of the device, neither deep in weak inversion nor in very strong inversion.
Relationship: reasoning
Domain: Hardware
Sentence 1: However, 1If we use a pull-down NMOS transistor instead of M3 and ex­change M1 and M2, we have an output-holding circuit, which is used for power gating circuits with footer switches since both M1 and M2 are off, this change does not propagate to the output, while the output is hold high by the pull-up PMOS de­vice M3.
Sentence 2: the output is hold high even when the logic gates are power-gated.
Relationship: reasoning
Domain: Hardware
Sentence 1: In fact, such a dependence exists in our pro­gram; for example, both B2(j) and B1(j+1) read and write to A(m+1,jB+B..N).
Sentence 2: a compiler that relies on depen­dence analysis cannot block LU with pivoting using the transforma­tion strategy of Carr and Lehoucq.
Relationship: reasoning