sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: LOW-OVERHEAD STATE RETENTION FFS In this section, we propose two sequential circuit schemes which assure no state loss during the stand-by mode while attaining high performance and low power consumption both in the active and in the sleep mode.
Sentence 2: our solu­tions are still based on the insertion of a retaining-balloon circuit but lower signi.cantly the dynamic/static power dis­sipation as well as the delay overhead associated to the state­retaining logic.
Relationship: entailment
Domain: Hardware
Sentence 1: Thus we have that lw(T ) = 2t (T ) - 1.
Sentence 2: by Lemmas 4, 6 and 7, we have the following theorem: Theorem 5. t (T ) = lw(T ) = 2t (T ) - 1 for a tree T .lw(T )= t (T ) if T is binary.
Relationship: entailment
Domain: Hardware
Sentence 1: 5.1 Single fbump/ADC/TSV Defect When there is a single fbump/ADC/TSV defect, the bilinear denoise algorithm can recover the missing pixel data as long as its left and right neighbors are not missing.
Sentence 2: to recover the pixel data on column x, both columns x 2 and x + 2 must be correct.
Relationship: entailment
Domain: Hardware
Sentence 1: Hence, we propose to apply small modi.cations to the software and protocols executing on sensor nodes to expose some information about the internal node state to the sniffer net­work to enable better identi.cation of possible failure causes.
Sentence 2: we propose a mechanism called passive distributed assertions (PDA), which allows a developer to assert certain prop­erties of the distributed system state such as there should be at least one cluster head among the neighbors of each node.
Relationship: entailment
Domain: Hardware
Sentence 1: Since the current tends to .ow via the path with the lowest imped­ance, it will return from a close-by path when the frequency is high, thus making the forward coupling inductance as well as the effective loop inductance minimized.
Sentence 2: for well designed circuits, the on-chip interconnect structure is often of a form that can be analyzed via 2D models.
Relationship: entailment
Domain: Hardware
Sentence 1: If node i transmits to node j then the transmission will be successful only if (i) rij = r(n) and (ii) rkj >r(n) for every other node k .i, j that transmits simultaneously with node = i.
Sentence 2: node i can successfully transmit a packet to node j only if i is a neighbor of j and no other neighbor of j is transmit­ting concurrently with i.
Relationship: entailment
Domain: Hardware
Sentence 1: HWS cache configurations with the same size and set­associativity (above 2, since 2 ways of different size can never have a total capacity equal to a power of 2) as the conventional cache behave better.
Sentence 2: if the conventional cache has ways of size S, a 3-way HWS cache configuration with 2·S|S/2|S/2 way sizes performs better than the conventional cache with S|S|S way sizes.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.2 Process Variation Sensor The variation sensor used in this work is based on DIBL (Drain Induced Barrier Lowering) effect, where it is observed that for a short channel device, threshold voltage is modulated by drain voltage [6].
Sentence 2: high drain voltage can lower the source-channel barrier so that channel is formed at lower gate voltages (lower threshold voltage).
Relationship: entailment
Domain: Hardware
Sentence 1: Note that if approximations are involved in de.n­ing the models and the maps, this is not necessarily true, i.e., abstraction maps may be non conservative.
Sentence 2: a feasible performance vector at level l +1 may not correspond to a feasible one at level l. The top-down phase then proceeds formulating a top-level design problem as an optimization problem with a cost func­tion C(ytop) and a set of constraints de.ned in the Ytop space, gtop(ytop) = 0 that identi.es a feasible set in Ytop.
Relationship: entailment
Domain: Hardware
Sentence 1: So, on an ALU ar­ray of 7 columns * 6 rows, all the loops except MPEG kernel will be mapped with a single con.guration, so that the loops can be ex­ecuted with the maximum possible throughput (1 iteration/cycle).
Sentence 2: there was no unnecessary con.guration change due to the routing failure in the combining phase.
Relationship: entailment
Domain: Hardware
Sentence 1: In general, our method predicts walking speed better than Weinberg s method, having comparable prediction error on curves or fast-walk interval, while performing better (with statistical signi.cance) when the participant is holding de­vice on ear, or walking on stairs.
Sentence 2: weinberg s method tended to overestimate walking speed on stairs, be­cause walking up/down stairs has higher acceleration range compared to walking on a .at surface, while the actual strides were con.ned to the step length of the stairs.
Relationship: entailment
Domain: Hardware
Sentence 1: In the early days of recording and distribution of analogue media [Chiarglione 2003], the owners of intellectual assets had a greater advantage in controlling their revenue streams because of the way in which media was delivered to and the consumed by the end user.
Sentence 2: the media was limited to the device or medium that contained it and/or the device required to consume it and it could not be duplicated by the end user.
Relationship: entailment
Domain: Hardware
Sentence 1: A more .ne-grained context recognition using additional multimodal sensors could support a speci.c optimization of the HI in this situation.
Sentence 2: additional cues like the user s activ­ity may support the estimation of the user s current hearing wish for the following two cases: (1) if the hearing wish and activity change, but the acoustic context stays the same, and (2) if the hearing wish and user activity stay the same, but the acoustic context changes.
Relationship: entailment
Domain: Hardware
Sentence 1: The pseudorandom sequence based tuning algorithm For a Linear Time Invariant (LTI) circuit, the tuning parameters are directly related to its impulse response h(t) and the tuning process can be accomplished through the evaluation of a suitable approximation of h(t).
Sentence 2: it has been shown [8] that the main circuit specifications can be related to a limited number of samples of h(t).
Relationship: entailment
Domain: Hardware
Sentence 1: HTGs have been de.ned as intermediate parallel program representations that encapsulate minimal data and control de­pendences, and can be used to extract and exploit functional and task-level parallelism.
Sentence 2: the hierarchical task graph, as de.ned in [8], is a directed graph HTG whose ver­tices can be: simple, representing a task with no subtasks, compound, representing a task that consists of other tasks in an HTG (e.g., higher level structures such as subroutines or loops), loop, representing a task that is a loop whose iteration body is an HTG.
Relationship: entailment
Domain: Hardware
Sentence 1: It assumes that once the transmit rate of any packet pair, Px and Px+1, within the packet train is the same as the available bandwidth, the remaining packet pairs after packet Px, which have a higher transmission rate, will be further separated by cross traffic.
Sentence 2: the dispersion of the rest of the packet pairs at the receiver will be larger than the spacing at the sender side.
Relationship: entailment
Domain: Hardware
Sentence 1: These properties all involve checking that a vari­able v depends only on some speci.ed set W = {w1,...,wn} of variables, and nothing else.
Sentence 2: we must verify that v can be expressed as a deterministic function of the other vari­ables: v = f(w1,...,wn), for some function f , or in shorthand, v = f(W ).
Relationship: entailment
Domain: Hardware
Sentence 1: Impact of Independent Failure Mechanisms The key fact ignored by existing MTTF models is that different failure mechanisms impact on different compo­nents of a system; for example, TDDB and NBTI affect transistors, while EM affects interconnects and TC impacts on the packaging.
Sentence 2: the effects of failure mechanisms impacting on different components are inde­pendent from the spatial perspective and thus should not be additive, even though the magnitude itself of every single MTTF is positively correlated with each other due to the joint dependence on temperature and other technol­ogy-dependent parameters.
Relationship: entailment
Domain: Hardware
Sentence 1: Given the ability to support error-awareness through less expen­sive error detection codes based schemes, our strategy is to use the information on SER (soft error rate) to 1. bypass potential failures by triggering error recovery mecha­nisms which reinitialize the erroneous data cache, and 2. reinforce application data using error-resilient encoding mech­anisms by translating the SER into the input metric of the encoding algorithm (being considered as the network packet loss rate).
Sentence 2: awareness of micro-level errors (i.e., bit errors) is translated into policies that have macro-level impacts in terms of execution failure, performance, energy consumption, and QoS.
Relationship: entailment
Domain: Hardware
Sentence 1: For tests that compare the data arrival against the clock arrival in the same clock cycle (e.g., data must be stable after the clock signal arrives at the capturing .ip-.op in this case), the total pessimism incurred is the di.erence between the early and late arrival times at the last meeting point between the data path and clock path.
Sentence 2: the signal propagation to this common point is identical for both clock and data, and thus does not warrant any early-late split.
Relationship: entailment
Domain: Hardware
Sentence 1: Stopping at this ob­vious design point, however, leaves signi.cant performance oppor­tunities uncovered.
Sentence 2: we study the use of 3D-stacked DRAM to implement a large last-level cache (LLC), and we show how to exploit the physical organization of DRAMs to further en­hance the performance of multi-core systems.
Relationship: entailment
Domain: Hardware
Sentence 1: In order to improve the cache behavior of accesses through this reference, we need to select a data transformation ma­ ~ trix Mxsuch that the last column of MxRxI+Mxr~xshould con­tain the index of the innermost loop with a small coef.cient and this loop index should not appear in any other column.
Sentence 2: the following constraint should be satis.ed: u0 u u ::: u 0 1 B u u u ::: u 0 C MxRx = B B u u u ::: u 0 C C; (1) @ :::u :::u :::u :::::: :::u ::: c A main() p main() p (a) (b) p p p p  p* p**p (c) (d) Figure 2: (a) Bottom-up phase.
Relationship: entailment
Domain: Hardware
Sentence 1: Threads with equal weights should still be slowed down equally.
Sentence 2: to support this notion of thread weights and to pri­oritize threads with larger weights, STFM scales the slowdown value computed for the thread by the thread s non-negative weight such that the weighted slowdown is S =1+(S - 1) * Weight.threads with higher weights are interpreted to be slowed down more and thus they are prioritized by STFM.
Relationship: entailment
Domain: Hardware
Sentence 1: Low Power and High Performance Design Challenges in Future Technologies (Invited Paper) Vivek De and Shekhar Borkar Intel Corporation Microprocessor Research Labs H isboro, OR 97124 ABSTRACT We discuss key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance.
Sentence 2: we focus on short-channel effects, device parameter variations, excessive subthreshold and gate oxide leakage, as the main obstacles dictated by fundamental device physics.
Relationship: entailment
Domain: Hardware
Sentence 1: The above approaches offer very limited throughput bene.t, since they are mainly targeted to improving a loop s latency.
Sentence 2: the optimizations introduced by these approaches focus on shaving off some delays from each loop iteration, and offer modest concur­rency increases: the tail-end of an iteration for a given data item is allowed to overlap somewhat with the start of that same item s next iteration, or the tail-end of an item s last iteration overlaps some­what the start of the next item s .rst iteration.
Relationship: entailment
Domain: Hardware
Sentence 1: In contrast to those approaches,the range of the required predictions in our case is very narrow.Since in this work, we opt to divide each cache frame of faultycaches in two equal divisions (each division is marked by aseparate faulty flag), coarse grain spatial footprint predictionscan be issued.
Sentence 2: the proposed coarse grain spatialfootprint predictor (CG-SFP) is designed to predict if thewhole cache block or only the left/right portion of a block willbe requested by the core (three decisions in total).
Relationship: entailment
Domain: Hardware
Sentence 1: Furthermore, current consumption is expected to increase further, due to the increasing complexity of the designs and reduc­tion in supply voltage, making it more difficult to meet stringent supply integrity constraints.
Sentence 2: the LdI/dt drop is expected Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.
Relationship: entailment
Domain: Hardware
Sentence 1: These approaches incur significant area overhead and higher leakage during both the high-voltage and low-voltage modes.
Sentence 2: the work in [27] shows that a 10T cell would achieve a comparable operating voltage to our VS-ECC but with a much larger area overhead (100% overhead for the 10T cell vs. less than 4% overhead for VS-ECC).
Relationship: entailment
Domain: Hardware
Sentence 1: Design and Implementation of a Multi-stream CableCARD with a High-Speed DVB-Common Descrambler Joonyoung Jung Broadcasting System Dept., ETRI 161 Gajeong-dong, Yuseong-gu Daejeon, KOREA +82-42-860-1626 jungjy@etri.re.kr  Ohyung Kwon Broadcasting System Dept., ETRI 161 Gajeong-dong, Yuseong-gu Daejeon, KOREA +82-42-860-5810  ohkwon@etri.re.kr ABSTRACT As the digital cable TV broadcasting technique is developed, various applications on a digital cable receiver have been required.
Sentence 2: openCableTM specifications for digital cable TV broadcasting have presented a cable receiver with multi-tuner for serving a Digital Video Recorder (DVR) application, a Picture-In-Picture (PIP) application, a Picture-Out-Picture (POP) application and etc.
Relationship: entailment
Domain: Hardware
Sentence 1: (normally de.ned by .BLmin c 0.1Vdd) So if the access time is longer than the prescribed maximum allowed value Tmax, then an access time failure is said to have happened.
Sentence 2: if at time t = Tmax, the voltage difference between node BL and BLB is still smaller than .BLmin, the access failure is happened.
Relationship: entailment
Domain: Hardware
Sentence 1: Based on these results, [7] and [8] explored four heterogeneous logic block architec­tures with a combination of LUTs, MUXes, and logic gates, and showed that such architectures offer signi.cant perfor­mance and density bene.ts over conventional homogeneous LUT-based PLBs.
Sentence 2: [8] explored heterogeneous logic blocks for the VPGA fabric and showed that a hetero­geneous PLB with a combination of 3-LUTs and three input Nand gates with programmable inversion (ND3WI gates), offers the best performance and density for both logic and datapath applications.
Relationship: entailment
Domain: Hardware
Sentence 1: In this work we are using the polyhedral model to consider data access patterns for communication between sets of loop nests, and to optimize this communication ordering in order to perform .ne-grained commu­nication and enable parallelization within a loop nest and pipelining between loop nests through loop transformation.
Sentence 2: in this work we consider programs that consist of a sequence of data­dependent blocks, where each block is a loop nest containing mul- Cd1 Cd2 ... Cdm Cd0 where S .
Relationship: entailment
Domain: Hardware
Sentence 1: (7) t |B0 t |B0 22 If N is properly selected, N will be large enough so that the current bit and the Nth previous bit have no intersymbol interference, then the rise and fall edge responses must have stabilized over N bit periods.
Sentence 2: the rise and fall edge responses must have the property that vR(t)= vhigh and vF (t)= vlow for all t> (D + NT ).
Relationship: entailment
Domain: Hardware
Sentence 1: Unfortunately, though theoretically possible, electri­cal simulation of complex systems may become impractical.
Sentence 2: for S.Ms, the extraction of their performance involves the analysis of a very large number of samples at the modulator output, which means a very long transient analysis: days or weeks of CPU time can be required to estimate the signal-to-noise ratio from the extracted layout of a typical S.M [3],[4].
Relationship: entailment
Domain: Hardware
Sentence 1: h c Acm =c (m)?0 =pLP (m)=0 = hcc =zLP (m)=me =em =wD (m) Thus, any good dual solution is a good lagrangian mul­tiplier vector.
Sentence 2: any optimal dual solution is an optimal lagrangian multiplier, since zu )=wD (mu), LP (mu and it is a well-known consequence of the duality theo­rem [19] that wu=zPu.
Relationship: entailment
Domain: Hardware
Sentence 1: This work addresses an important problem of minimizing the power consumption of circuit while controlling the NBTI induced delay increase to meet the circuit timing con­straint by simultaneously utilizing the effects of voltage scaling and body biasing on both NBTI and power consumption.
Sentence 2: we solve the problem of .nding a set of supply and body biasing volt­age values to apply circuit clusters on standard cell based design to minimize the total power consumption while satisfying the con­straint of circuit life time, considering the NBTI induced delay factor in circuit timing computation.
Relationship: entailment
Domain: Hardware
Sentence 1: The ratio that CountingNum is divided by the T otalCountingNum summed up by each grid is regarded as a weight, and it is multiplied by the total sample size.
Sentence 2: if the value is not an integer, we will round o.. CountingNum F = × T otalSampleSize TotalCountingNum F : Sampling frequency of each grid T otalCountingNum : sum up all CountingNum T otalSampleSize : the number of wanted sampling   Grid number Polygons in this grid Figure 4: The example for density table for critical area extraction.
Relationship: entailment
Domain: Hardware
Sentence 1: However, optimization for yield is interested in im­proving only those chips that violate timing constraints with­out wasting resources speeding up chips that are already su.ciently fast.
Sentence 2: if an edge or path is only critical in asubset of theprocess spaceand thereare no failing chips in that region, then there is no point improv­ing that edge or path.
Relationship: entailment
Domain: Hardware
Sentence 1: FPGA architectures, however, have been enhanced since this work, and it is not clear whether these older techniques still suffice.
Sentence 2: the LUT size has been increased from 4 to 6 inputs, and both Altera (Stratix-II/III) and Xilinx (Virtex-5) have developed methods to use LUTs in conjunction with the fast carry­chains to perform ternary addition; the advantage of ternary addition was outlined in [16].
Relationship: entailment
Domain: Hardware
Sentence 1: 3) ISCAS 85 Layout Generation: We will focus on com­binational logic circuits like the ISCAS 85 benchmarks [12] to illustrate our regularity metric.
Sentence 2: we have developed the complete set of benchmarks layouts in the 65 nm technology node using a commercial standard cell library (STD) and the Robust standard cell approach (Robust).
Relationship: entailment
Domain: Hardware
Sentence 1: Generally, a well-tuned cache hierarchy and organization would eliminate the time overhead of fetching instruction and data words from the main memory, which in most cases resides off-chip and requires power costly communication over the system bus that crosses chip boundaries.
Sentence 2: in embedded, mobile, and handheld systems, optimizing of the processor cache hierarchy has received a lot of attention from the research community [7][8][9].
Relationship: entailment
Domain: Hardware
Sentence 1: For example, on a recent Xilinx Virtex 6 device with 36Kbit Block RAMs (BRAMs), a 512-entry CAM with a 40-bit key requires 64 BRAMs to perform the match, despite the fact that 512, 64-bit entries can be stored in a single BRAM.
Sentence 2: the overhead for implementing the match portion for the fully associative memory on this FPGA is 64× the stored mem­ory capacity.
Relationship: entailment
Domain: Hardware
Sentence 1: It is a single task learning (STL) mode which neglects the potential rich information sources hidden in other related tasks.
Sentence 2: when studying the relationship be­tween x1,x2 , ..., xt and xt+1, they only consider this current task, without taking into account other related tasks, such as studying the relationship between x1,x2 , ..., xt and xt+2.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION Micro.uidic biochips have now come of age, with appli­cations to biomolecular recognition for high-throughput DNA sequencing, immunoassays, and point-of-care clinical diagnostics [1], [2].
Sentence 2: digital micro.uidic biochips, which use electrowetting-on-dielectric to manipulate discrete droplets (or packets of biochemical payload ) of picoliter volumes under clock control, are especially promising [2], [3].
Relationship: entailment
Domain: Hardware
Sentence 1: 2.3 Averaging 2.3.1 Baseline Subtraction In cognitive pupillometry, the physical quantity of interest is the change in pupil diameter relative to its diameter shortly before the mental activity being studied [Beatty and Lucero-Wagoner 2000].
Sentence 2: what matters is dilation (or con­striction), not absolute pupil size.
Relationship: entailment
Domain: Hardware
Sentence 1: A simple calcu­lation (see Table 1) shows that the gain factor dramatically grows with the skew.
Sentence 2: the gain factor is a con­ w .ASR Gain factor 2 1-w (1-w/2) w< 1 (1-w/2)2 m 1-w w =1 4m/ ln m 41 ln m 2 w-12-w (1-w/2)w-1 1  2 m (w/2-1)2 w-1 Table 1: Asymptotic dependence on m of the gain factor and ESS under Square-root allocation for truncated m-items Zipf distribution with power w. stant fraction for w< 1, logarithmic in m for w =1, and (fractional) polynomial in m for w> 1; for w> 2the ESS under Square-root is constant and the gain factor is thus linear in m. Figure 2 plots the gain factor as a function of the number of items for representative values of the power parameter w. We next consider two natural query distribution ob­tained from Web proxy logs (the Boeing logs described in [1]).
Relationship: entailment
Domain: Hardware
Sentence 1: Under a rather broad set of conditions, the resulting distribution ofx should tend towards a normal distribu­tion (even when the e are not iid, under the assumption that no sin­ i gle variation source dominates [13]).
Sentence 2: hence, much of the mass of the distribution lies within a range smaller than that indicated by the radius of the interval, which is the size of the largest deterministic excursion from the nominal, easily computed as N Rx= () .1 (13) xi the chance ofx taking a value far from its nominal value is extremely small.
Relationship: entailment
Domain: Hardware
Sentence 1: Since load balance changes after each re-meshing step, the overall load balance reported is is computed by averaging over steps.
Sentence 2: predicted load balance s at a particular step is computed as: .P n(p)/P p=1 s = (1) n(p)max where n(p) is the number of cells on processor p and P is the total number of processors, and n(p)max is the maximum number of cells on all processors.
Relationship: entailment
Domain: Hardware
Sentence 1: It also reduces phys­ical design efforts in which detailed placement and routing will be performed on-the-.y.
Sentence 2: only global placement and routinghavetobecompletedatthedesigntimeanddetailedcon.g­urationofindividualcrossbars(forlogicmappingorsignalrouting) willbedetermined atthe con.guration timeby BISM.The follow­ing BISM schemes are proposed depending on the defect density level.
Relationship: entailment