sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: In order to simplify the model, we found that the delay dependence on each voltage is near-linear in the (narrow) range of valid voltages.
Sentence 2: to be more accu­rate, we have used a quadratic polynomial to represent the dependence of delay on each voltage, and made allowance for cross-product terms, by using a template expression for delay as follows: .
Relationship: contrasting
Domain: Hardware
Sentence 1: On the other hand, in the full Illinois MESI protocol, a block can be preferen­tially retrieved from another cache rather than from mem­ory.
Sentence 2: when multiple caches share a copy, a vot­ing mechanism is required to decide which cache will sup­ply the data, and this voting mechanism can bene.t from the use of low latency wires.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this case, we can .rst set either T or D to an identity matrix, and then use Eq (4), Eq (7) and Eq (8) to determine the other one to localize the target array.
Sentence 2: in cases where there are multiple loop nests in the whole program and multiple arrays accessed by these loop nests, to localize the maximum number of arrays (this means we can re­duce the inter-thread con.icts for the maximum number of arrays), which one of these two matrices should be determined .rst for an array becomes crucial.
Relationship: contrasting
Domain: Hardware
Sentence 1: On the one hand, the pseudo-input part (PSI) of the excitation pattern (the inter­nal scan chain part) is generated through functional justi­.cation, i.e., load the pseudo-output (PSO) of the second vector.
Sentence 2: the PI part is provided using the functional inputs by setting the provider cores in the pro­ducer DELTEST mode.
Relationship: contrasting
Domain: Hardware
Sentence 1: Post-Routing Redundant Via Insertion and Line End Extension with Via Density Consideration * Kuang-Yao Lee Ting-Chi Wang Kai-Yuan Chao Department of Computer Science National Tsing Hua University Hsinchu, Taiwan Department of Computer Science National Tsing Hua University Hsinchu, Taiwan Intel Corporation Hillsboro, OR 97124 kaiyuan.chao@intel.com d924347@oz.nthu.edu.tw tcwang@cs.nthu.edu.tw Abstract - Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure.
Sentence 2: if the amount of inserted redundant vias is not well controlled, it could violate via density rules and adversely worsen the yield and reliability of the design.
Relationship: contrasting
Domain: Hardware
Sentence 1: To reduce log sizes, software-only replay systems commonly include disk state within checkpoints and allow replaying software to recreate disk state without logging it explicitly in the same way replaying software recreates memory state [6].
Sentence 2: experiments showed that the hardware-level Interleaving log accounts for the majority of data within our replay logs, thus obviating the need to introduce the complexities of including disk state within our checkpoints.
Relationship: contrasting
Domain: Hardware
Sentence 1: Floorplan Driven Leakage Power Aware IP-Based SoC Design Space Exploration * Aseem Gupta , Nikil Dutt , Fadi Kurdahi Center for Embedded Computer Systems University of California, Irvine Irvine, CA 92697 USA {aseemg,dutt,kurdahi}@uci.edu ABSTRACT Multi-million gate System-on-Chip (SoC) designs increas­ingly rely on Intellectual Property (IP) blocks.
Sentence 2: due to technology scaling the leakage power consumption of the IP blocks has risen thus leading to possible thermal runaway.
Relationship: contrasting
Domain: Hardware
Sentence 1: 3.3 Exploiting the Critical Path QB-SyncFollow, QB-Sharing and QB-SyncSharing The most basic quantum building policy, QB-Count, pro­duces quanta based on counting instructions and breaking a quantum when a deterministic, target number of instructions is reached.
Sentence 2: instruction-count based quantum build­ing does not capture the fact that threads do not have the same rate of progress.
Relationship: contrasting
Domain: Hardware
Sentence 1: Most existing studies assume that a void occurs when the atomic concentration drops down to a speci.c percentage.
Sentence 2: there is no clear answer on how low the concentration threshold should be to declare a void.1 Therefore, we describe a continuous resistivity increase when atomic concentration decreases, but vary the in.nite resistivity values from 32.0 to 300.0 (see Func 32.0 to Func 300.0 in Figure 9(a)).
Relationship: contrasting
Domain: Hardware
Sentence 1: DDF is the most expressive model (in fact, it is Touring-equivalent), but it is very hard to analyze and to prove properties on its ex- ecution (even testing for termination is undecidable in general DDFs).
Sentence 2: sDF cannot fully express control- dominated behavior (e.g., conditional execution), but it can be analyzed very eifl~clently.
Relationship: contrasting
Domain: Hardware
Sentence 1: ForFPGAappliations,afewpartitioningmethodsuti­lizingdesignhierarhyhavebeenreportedreently[10,3,4].
Sentence 2: theymainlyfousonproblemsizeredutionusingdesign­basedlustering.Thehierarhialelementsareseletively preservediftheyarefeasiblebothsizeandpinount aresmallerthanthelimitofeahFPGAdevie.Fornon­feasiblehierarhialelements,someoperationsareapplied tointelligentlybreakuptheelements.Underthesizeand pinountonstraints,usuallytheirgoalistofndasetof thegoodfeasibleblokswhihmaximizesdevieutilization, i.e.,minimizesthenumberofFPGA'sused.their frameworksarenotdiretlyappliabletogeneralpartition­ingproblems,andtheymaypreservethehierarhialele­mentswithlooselyonnetedinternalellsunlesstheexter­nalpinountexeedstheupperbound.Moreover,theyare noteasytobetransformedintothemultilevelsheme.
Relationship: contrasting
Domain: Hardware
Sentence 1: As can be seen in Figure 11, the static code size between thedi.erent machines are all relatively close(for example MM is 83 instructions instead of the 73 from in the orig­inal GLIFT machine) with only a few glaring exceptions (AES is 2X bigger and BSort is 5X bigger).
Sentence 2: even though AES is 2X bigger, it is approximately 68X faster using Leases instead of the original GLIFT ISA.
Relationship: contrasting
Domain: Hardware
Sentence 1: Thus, the proposed strategy is better than both the conventional sequences in terms of memory accesses.
Sentence 2: it has an additional compute overhead with respect to row sequence, as the Type 0 0 operation count comparison goes as: #Type 0 0...... < #Type 0 0...... < #Type 0 0...... (from Equation 2 and Ta­ble I) with reverse ordering for Type X Y.
Relationship: contrasting
Domain: Hardware
Sentence 1: To compute the correlation functions for all possible values of n( KnK) results in a com­ == plexity O(K2).
Sentence 2: we later show that we can restrict n to val­ues less than the response time of the power grid without loss in accuracy, which is significantly smaller than K for large vector sequences and hence, the complexity is linear with K. In the next subsection, we describe the computation of mean and standard deviation of voltage supply fluctuations, using the statisti­cal parameters of block currents as derived in this section.
Relationship: contrasting
Domain: Hardware
Sentence 1: The proposed solution builds on the workof [9] and [20], which demonstrate that transition-signalingsingle-rail bundled data can be ef.ciently employed in basicrouting and arbitration functions.
Sentence 2: [9] and [20] targetonly simple tree-based switch architectures, while this workaddresses the intricacy of a full 5-ported switch design.
Relationship: contrasting
Domain: Hardware
Sentence 1: Sig­ni.cant accuracy improvement has been achieved in statis­tical timing analysis, e.g., by including into consideration correlations between process and system runtime variations [2, 3], multiple-gate-input switching [1], crosstalk coupling [7, 8], etc.
Sentence 2: a fundamental problem remains in achieving accurate VLSI statistical timing analysis, which is addressed in this paper.
Relationship: contrasting
Domain: Hardware
Sentence 1: When a wires must be increased by more than 100% of their normal width, block is turned on from its idle mode, it draws large current from which means their current densities exceed 2x of the maximum power supply, and thus causes its neighboring blocks to allowed.
Sentence 2: since power noise is not always present, a 2x maximum current density improvement can still be considered EM-safe for these wires.
Relationship: contrasting
Domain: Hardware
Sentence 1: Williams Implementation Group Synopsys, Inc. Broomfield, CO 80020 Tel : 650-584-4867 Fax : 617-600-9697 e-mail: tww@synopsys.com  Figure 1.
Sentence 2: relative improvement in laptop computing technology as more and more transistors are packed closer and closer together, the ability to supply power to, and dissipate heat from, these circuits is becoming harder to accomplish in a reliable, efficient, and cost-effective fashion.
Relationship: contrasting
Domain: Hardware
Sentence 1: But it must be mentioned that this performance is available for up to 16 M keys or (64 MB key storage) where we require three times of streaming the problem through the FPGA, what is then slightly slower.
Sentence 2: by adding a second memory port to the system and using partial run-time re­con.guration, the FPGA will outperform the GPU in speed.
Relationship: contrasting
Domain: Hardware
Sentence 1: Camposano s path-based scheduling [18] and Wakabayashi s condition vector-based scheduling [19] were two noticeable works in the early 1990s.
Sentence 2: camposano s work enumerates all execution paths, which could be exponential in number, while Wakabayashi s work involves a lot of complication in scheduling due to the simultaneous consideration of conditional and unconditional resource sharing by operations.
Relationship: contrasting
Domain: Hardware
Sentence 1: If the metadata is stored alongside data in the same pages, then 29 blocks (and their metadata) could be stored per page (as in [4]).
Sentence 2: a channel typically has 8 16 banks, and thus the interleaved scheme will have only 232 464 metadata entries in open row-buffers per channel8.if the metadata was stored separately, we can store 512 metadata entries per page increasing the likelihood of getting more row-buffer hits.
Relationship: contrasting
Domain: Hardware
Sentence 1: In addition, as discussed in [1], ATE generates continuous test data, and CUTs expect the same traf.c shape with zero­jitter requirement.
Sentence 2: if using NoC-TAM scheme, shared channels, shared routers, and load .uctuation (i.e., test data are condensed into bursty format during transmission) render traf­.c jitter an inevitable phenomenon.
Relationship: contrasting
Domain: Hardware
Sentence 1: Moreover, although the metrics proposed in previous approaches have been applied during the matching phase, none of them ex­tends these metrics to guide the covering, which actually selects the mapping solution, and thus, these techniques ignore the search space available during the covering.
Sentence 2: we utilize the gen­erated congestion maps during the covering process to compute the total track over.ow due to different mapping choices, and to se­lect the one that minimizes this track over.ow while satisfying the delay constraints.
Relationship: contrasting
Domain: Hardware
Sentence 1: The variant FRW scheme increases the variance of MC procedure, and thus slows down its convergence.
Sentence 2: the efficiency benefit of the variant FRW overwhelms its drawback, as demonstrated in Section V. C. Concurrent Extraction of Multiple Nets For the actual application of FRW, instead of the single-net capacitance extraction (with a single master conductor), we often need to extract the capacitances of multiple nets in a same design.
Relationship: contrasting
Domain: Hardware
Sentence 1: In the case of a spring­mass MEMS accelerometer, the measured quantity isthe capacitance, or the difference of the two capacitances, and analytical relation between capacitance and internal device parameters can be used to convert this information to acceleration, which is the actual measurement goal.
Sentence 2: the accuracyof this information depends on two factors: (a)measurement accuracy of the capacitance difference, and (b) knowledge on the parameters of the internalMEMS structure.
Relationship: contrasting
Domain: Hardware
Sentence 1: Given this utility function, if M = {1, 2, 3, 4} and the receiver rates Rk, k=(1,2,3,4) are {4, 3, 2, 1 }, then the best thing to do is to not prune any receivers and operate at group rate RM=I.
Sentence 2: if the receiver rates are {2, 2, 2, 1 }, then the best thing to do is to prune the fourth member and operate at group rate R[1,2,31=2.
Relationship: contrasting
Domain: Hardware
Sentence 1: The performance loss seen by the incomplete bypass results led the authors to explore multi-banked and hierar- chical register file organizations.
Sentence 2: in our simula- tions, the performance loss that motivated their work does not exist; the Alpha microarchitecture is limited by other overheads, and has sufficiently aggressive scheduling to overcome the effects of one-cycle bubbles between depen- dent instructions.
Relationship: contrasting
Domain: Hardware
Sentence 1: RESULTS AND DISCUSSION The simulated leakage currents in the VT-control method and DG con.guration are compared in Fig.3.As observed in the plots, the leakage current is considerably reduced both for NMOS and PMOS transistors in comparison with the DG con.guration.A controlling range of about three orders of magnitude is achievable in the leakage current, indicating the potential capability of the VT-control method in mini­mizing the standby power.
Sentence 2: the total dynamic power resulting from charge-transfer to the top and bottom gates of the transistors is plotted versus VCN and VCP and compared with the DG con.guration in Fig.4.The values for VT-control method are higher than DG but of the same order.from the previous plot, it can be predicted that the increase in the dynamic power consumption may be well compensated by the dramatically reduced leakage current, especially as the circuit activity is decreased.
Relationship: contrasting
Domain: Hardware
Sentence 1: 5.3 Multi-Level Optimization Inthe resultspresentedthusfar,wehave observedthatincreasing theeffectiveness ofNBTI mitigationtechniques atonly thecircuit or microarchitecturelevel toimprovetheguardband entailspenal­ties in terms of area, power, delay, and application performance.
Sentence 2: lightweight optimizations at each level could provide a net increase in guardband reduction with less overhead.
Relationship: contrasting
Domain: Hardware
Sentence 1: These frameworks exploit the heterogeneity in the sensitivity of di.erent programs to varying core frequen­cies to optimize their cumulative throughput and energy, while guaranteeing a minimum level of performance for each pro­gram.
Sentence 2: in the context for multithreaded programs, these schemes o.er limited bene.ts as all threads are often homogeneous and the interdependency between them needs to be considered.
Relationship: contrasting
Domain: Hardware
Sentence 1: 4.2 Inter-Region Level The circuitry described in the previous subsection ensures that a single region can be turned on without violating the current constraint of the power grid.
Sentence 2: in practice there might be excess current caused by other activity, such as unrelated signals passing through the region (for switch boxes that are not powered down), or from transient signal changes while turning on a region.
Relationship: contrasting
Domain: Hardware
Sentence 1: Also, the sensors used to meter electricity are actively and constantly powered, meaning they re­quire expensive AC-DC power supplies and draw their own power even when the load they are metering is off.
Sentence 2: we propose a system that is easy to deploy, offers .ne grained and automated wireless data collection, and uses in­expensive energy-harvesting sensors which draw zero power when the measured loads are turned off.
Relationship: contrasting
Domain: Hardware
Sentence 1: On the other hand, physical segments are consid­ered young physical segments when their remaining write counts are larger than 10N' and called old physical segments when their ' remaining write counts are no more than 10N' ,where N<N and 10N' is regarded as the retiring threshold Tr to separate young  ciently .nd out all the young physical segments in the storage space with the next-.t algorithm.
Sentence 2: when a virtual segment in the storage space needs a new free physical segment, the space manager is invoked by the storage manager to return an comparatively old free physi­cal segment.
Relationship: contrasting
Domain: Hardware
Sentence 1: Design of Mixed Gates for Leakage Reduction Frank Sill Jiaxi You Dirk Timmermann College of CSEE College of CSEE College of CSEE University of Rostock University of Rostock University of Rostock Germany Germany Germany frank.sill@uni-rostock.de jiaxi.you@uni-rostock.de dirk.timmermann@uni-rostock.de ABSTRACT Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs.
Sentence 2: design tech­niques for the reduction of leakage power should not decrease design performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs Sudarshan Bahukudumbi and Krishnendu Chakrabarty Richard Kacprowicz Department of Electrical and Computer Engineering Intel Corporation Duke University, Durham, NC 27708 Email: {spb, krish}@ee.duke.edu Abstract Wafer-level test during burn-in (WLTBI) has re­cently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing.
Sentence 2: the testing of multiple cores of a system-on-chip (SoC) in parallel during WLTBI leads to constantly-varying device power during the duration of the test.
Relationship: contrasting
Domain: Hardware
Sentence 1: Ef.cient SMT-based ATPG for Interconnect Open Defects Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker University of Freiburg, Georges-Köhler-Allee 51, 79110 Freiburg, Germany Abstract Interconnect opens are known to be one of the pre­dominant defects in nanoscale technologies.
Sentence 2: automatic testpattern generation for open faults is challenging, because of theirrather unstable behaviour and the numerous electric parameterswhich need to be considered.
Relationship: contrasting
Domain: Hardware
Sentence 1: Bugs with error detection latencies longer than a few thousand clock 978-3-9815370-0-0/DATE13/&#38;#169;2013 EDAA cycles are highly challenging because it is extremely difficult to trace too far back in history for bug localization.
Sentence 2: bugs in complex SoCs can result in very long error detection latencies of several millions to billions of clock cycles [Hong 10, Lin 12, Reick 12].
Relationship: contrasting
Domain: Hardware
Sentence 1: For the 8-bit butterfly datapath, the data and input gating to the unused hardware leads to a 66% energy dissipation reduction over a non-scalable design.
Sentence 2: for 16-bit computations, the energy dissipation of the scalable designs increases over the non-scalable design, due to the energy overhead from the energy-scalability enabling logic.
Relationship: contrasting
Domain: Hardware
Sentence 1: Hence, the topmost transistor works in saturation region only (Vds > Pv[Vgs -Vth]a/2, see section 2.1) when all input voltages Vin of the stack start to change.
Sentence 2: the other transistors in the sub-stack (see figure 3) work in linear region (Vds < Pv[Vgs -Vth]a/2, see section 2.1) [15].
Relationship: contrasting
Domain: Hardware
Sentence 1: The failure regions of fully-salicided NMOS after 125-V MM ESD stress are only located within a few gate regions, which is due to current crowding within the weak salicided surface channel.
Sentence 2: the failure regions of NMOS with dummy-gate structure after 325-V MM ESD stress are uniformly located among all the contact regions of drain side.
Relationship: contrasting
Domain: Hardware
Sentence 1: The ultimate idea is to directly utilize the high-frequencycarrier signal for the localization purpose.
Sentence 2: since the available FPGAs cannot directly process 2.5 GHz signals, the experimental setup is using an f = 5MHz low-frequency (localization) signal, which is modulated onto a fc = 2.484 GHz carrier (channel 14 of the 802.11b standard).
Relationship: contrasting
Domain: Hardware
Sentence 1: 2.3 Support-Circuit Preconditioning Approach An on-the-.y support-circuit preconditioning (SCP) tech­nique has been recently proposed in [5].SCP starts from sparsifying the linear circuit networks to generate ultra-sparsi.er support graphs, and subsequently combines these support graphs with other nonlinear devices to build the support­circuit preconditioner.This technique is very e.ective for parasitic-dominated circuit designs within which the linear circuit elements or parasitics dominate (the number of linear   gd g2 d d h g h Cds g3 gds h Cgdd g2 s g5 g1 Ultra-Spparsifier gmm g Active Devices Active Devices g2 g 3 g hh g C d Cds mgsh gV s g5 g1 Support-Circuitit Preconditioner SSupportt GGraphh S t Ci Figure 2: Support circuit generation.
Sentence 2: circuit elements is much greater than the number of nonlin­ear devices), since the support-circuit preconditioning ma­trix can be signi.cantly sparsi.ed, and thus more e.cient to factorize.when nonlinear devices dominate in a design, the e.ectiveness of the prior support-circuit precon­ditioner can be drastically weakened: as a result, factorizing the support-circuit preconditioner matrix can be as expen­sive as factorizing the original system matrix.
Relationship: contrasting
Domain: Hardware
Sentence 1: The number of ALMs used by XOR memories grows very slowly as memory depth increases, since for the XOR design ALMs are used only to implement the XOR operations and forwarding logic, both of which grow linearly with memory width and only logarithmically with memory depth.
Sentence 2: the number of ALMs used by LVT memoriesgrows with memorydepth since(i) they are used to construct the LVT itself, which grows signi.cantly for deep and/or many-ported memories, and(ii) theyimplementforwarding logic, which grows with the number of BRAMs used.
Relationship: contrasting
Domain: Hardware
Sentence 1: It is clear that the HTFET is a superior device compared to Si NMOS in its sub-threshold region, showing both higher IOn as well as higher IOn/IOf f ratio.
Sentence 2: it is also important to consider the Id-Vd characteristics of the HTFET, since the saturation voltage (Vd-sat)plays an important role in the noise-margin characteristics of digital circuits.
Relationship: contrasting
Domain: Hardware
Sentence 1: Intypicalcases, conventional level shifter is able to achieve less than 5 fanout-of-four in­verter(FO4)delays atVDDL, whichis su.cientlyfastfor most subthreshold applications.
Sentence 2: considering 3s processvariation,Wnneedstobeup-sizedatleasttwotimes larger than the nominal case to maintain functionality.
Relationship: contrasting
Domain: Hardware
Sentence 1: Whengoing from a HC-SD to a HC-SD-SA(2)con.guration, the CDF curvesfor these two workloads shift upby a large amount, indicating a signi.cant improvement in performance.
Sentence 2: the HC-SD and (1/2)R curves for these two workloads in Figure 4 show a smaller performance improvement.
Relationship: contrasting
Domain: Hardware
Sentence 1: The change in gate oxide current resulting from OBD is modeled by the power-law expression in Equation 1: p .Igate =K(Vgd) (1) The change in gate-to-drain (gate-to-source) current is repre­sented as a function of a linear scaling factor K, the gate-to-drain (gate-to-source) voltage Vgd (Vgs), and a power-law exponent, p. Both .tting parameters K and p vary depending on the amount of degradation experienced by the transistor in question.
Sentence 2: for much of the empirical data collected in [26], choosing a p =5.0, while still allowing K to track degree of degradation, resulted in a good .t throughout the majority of the progressive breakdown region.
Relationship: contrasting