sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Extended Abstract:Design of a Small Acoustic Modem for Dense and Low-Cost Oceanographic Monitoring Kun Zeng,  Yue-hai Zhou,  Fei-yun WU,  Feng TONG Key Laboratory of Underwater Acoustic communication and Marine Information Technology of the MOE, Xiamen University, Xiamen, China zengkun635@sina.com ruddy100@sina.com wfyfly@126.com ftong@xmu.edu.cn 1.
Sentence 2: in the demodulation process the judgment condition for pulse width is designed to be smaller than 3ms to accommodate the pulse width variations caused by underwater acoustic channel.
Relationship: neutral
Domain: Hardware
Sentence 1: The results combining a low-pass .lter with thresh­olding the EEG maps produce a cleaner binary masks which contain a better estimation for the object location (Figure 8).
Sentence 2: the kernel takes standard deviation s as a parameter de.ning the spatial extension of the .lter: 1 x 2 + y 2 G(x, y) = v exp - (4) 2s2 2ps2 The Gaussian .ltering and posterior binarization of the resulting EEG map requires de.ning the two parameters a and s. As in the previous section, these were selected via minimizing error the training dataset.
Relationship: neutral
Domain: Hardware
Sentence 1: AnexampleisshowninFigure3.Toconstructt1,westart fromthemoduleatthelowerleftcornerandtravelupward (leftsubtree)andtotheright(rightsubtree).Whenever thelowerleftcornerofanothermodulexisreached,anode labeledxisinsertedintothetreeandtheprocesswillbe repeatedstartingfrommodulexuntilallthemodulesin thefoorplanarevisited.Thetreet2canbebuiltsimilarly bystartingfromthemoduleattheupperrightcornerand traveldownward(rightsubtree)andtotheleft(leftsub­tree).Thepaper[8]hasshownthatthepairoftreesbuiltin thiswaymustbetwinbinarytoeachother,andthereisa one-to-onemappingbetweenmosaicfoorplanstructureand twinbinarytrees.Weobservedthattheinordertraversal ofthetwobinarytreesconstructedfromamosaicfoorplan mustbethesame.LetuslookattheexampleinFigure3.
Sentence 2: tIGHT BOUND ON NUMBER OF IRRE-DUCIBLE EMPTY ROOMS Inordertodescribenon-slicingstructurebyamosaic foorplanrepresentation,somepreviouswork[9]includedummy blocksofzeroareainthesetofmodules.Themethodde­scribedinsection2.3isveryefcientbutitisapplicable totheTBSrepresentationonly.Ingeneral,weonlyneed tohaven;1extradummyblocksinordertorepresentall non-slicingstructuresbyamosaicfoorplanrepresentation.
Relationship: neutral
Domain: Hardware
Sentence 1: To estimate DIMM power we inserted current sensors in power supply lines of each DIMM and aggregated the data using data ac­quisition system.
Sentence 2: such in­crease in memory size and speed have led to a signi.cant * This work has been funded by NSF Project GreenLight grant 0821155, NSFSHFgrant 0916127, MuSyC, UC Micro grant 08-039, Sun Microsystems, and Cisco.
Relationship: neutral
Domain: Hardware
Sentence 1: CONCLUSIONS This paper has proposed a simple and useful method to approximate the capacitance ratios by rational numbers to improve capacitance matching, a critical issue in the design of switched-capacitor .lters.
Sentence 2: , n. (12) CC the development presented above shows that, given an integer D, the problem of .nding the suitable approximation for the ratio Ci/C is solved if it is possible to .nd an integer Ni that satis.es the constraint (10).
Relationship: neutral
Domain: Hardware
Sentence 1: Fuses 10k GE -128 GE2 4k GE 20k GE 10k GE 32 GE Includes LR-PUF control External Flash/EEPROM 256-bit 2T MTP NVM Repetition and Golay 128 bits key length 64 2T OTP anti-fuses Total 44.2k GE Naturally, the total resource cost of the memory-based LR-PUF is higher than the cost of storing a key in NVM or using a regular PUF (which can both be done with a sub­set of the components from the list above).
Sentence 2: recon.gurable physical unclonable functions -enabling technology for tamper-resistant storage.
Relationship: neutral
Domain: Hardware
Sentence 1: CONCLUSIONS We introduced a method for clock gating synthesis that constructs the gating condition out the disjunction of signals and their complements that are already present in the existing logic.
Sentence 2: if the combinational transitive fan-out of any h does not include any (i) primary outputs, (ii) clock gate inputs, or (iii) register inputs not gated by g(x), this connection can be replaced with a constant.
Relationship: neutral
Domain: Hardware
Sentence 1: LD1 lifespan LD2 lifespan RD 1 RD 2 LD 1 LD 2 RD 3 RD 4 LD1 lifespan LD2 lifespan LD f4 Figure 5: Variable lifespans and register load line fault effects A control line effect that causes an extra load is potentially dis­ ruptive if the load occurs within a lifespan of R; in Figure 5(b), LnDpfo2, LnDpf 3, and L Dpfs4fall into this category.
Sentence 2: the example has a total of 37 SFR faults.
Relationship: neutral
Domain: Hardware
Sentence 1: Going from single-bit upset (SBU) to multi­bit upset (MBU) fault injections, we do not observe significant changes in overall fault rates except MBU produces more de­tectable faults than SBU in GPR injection experiments.
Sentence 2: when predicting resiliency of a given function, the algorithmic masking in that function should also be tak­en into account.
Relationship: neutral
Domain: Hardware
Sentence 1: Based on the physical proximity of the high voltage (critical) cells in the placement, the algorithm ef.ciently explores the solution space of all possible island bound­aries and .nds the voltage islands (also called the voltage island partitioning) for the best tradeoff between the total power and the number of islands.
Sentence 2: in current industry low power design, people only focus on the maximum power reduction on the cells.
Relationship: neutral
Domain: Hardware
Sentence 1: We are also investigating possible software countermeasures that use random bits to alter the param­eters.
Sentence 2: clearly, a onlyhas a chance to ful.ll the assumption cor­rectlyif 2l(pt) is a multiple of t. the assumption is justi.ed for other cases as well, because the distance to the uniform distribution is negligiblysmall as t « 2l(pt) .
Relationship: neutral
Domain: Hardware
Sentence 1: (3) Note that the data arrival times at R2 are given by the propagation constraints [9]: () d1 + D12a a2 = min Pm - Tmin , (4) Pm - Tmin, d1 + D12b () D1 + D12a A2 = max PM - Tmin .
Sentence 2: the proposed delay insertion algorithm is applicable on such circuit structures.
Relationship: neutral
Domain: Hardware
Sentence 1: On average an improvement with a factor of over 100 is observed, both for large as for small hypercubes.
Sentence 2: x Performance model P Figure 2: Electronic system S parametrized by X with excita­tion E and response Y leading to a performance P seen from a designer s point of view, the key relation­ship is: P = F(X) (3) The mathematical modeling of this relationship is called perfor­mance modeling.
Relationship: neutral
Domain: Hardware
Sentence 1: Handling Con.icts: Clearly, the above design works well in the expected usage scenario -when the latency within the memory is consistent and predictable, and where bank con.ictsand timing constraint violations are uncommonbe­cause of the large number of banks.
Sentence 2: with lower tra.c, there are fewer possibilities of the con.icts that raise access latency in the packet-based system.
Relationship: neutral
Domain: Hardware
Sentence 1: In [3, 4], Cantin et al propose a technique for snoop traffic filtering that uses a structure called a Region Coherence Array (RCA) within each node to keep track of the sharing status of regions.
Sentence 2: the main contributions of this paper are as follows: We propose a snoop traffic filtering technique that makes use of coarse-grained sharing information on the basis of regions within a page, pro-actively collecting the sharing information of all regions within a page during snoop activities on any line within that page.
Relationship: neutral
Domain: Hardware
Sentence 1: Cycles 49,440 Operation Accuracy 32 bit The execution cycle was estimated by performing a 2,048­point IMDCT using Mentor ModelSim based on the follow­ing conditions:  If the IMDCT module makes bus-request signal avail­able, an arbiter allocates the bus to the IMDCT mod­ule immediately.
Sentence 2: to generate the pro.le summary of the decoding pro­cess, each sample was decoded using Tremor by ARMulator (an emulator of ARM processors) with zero memory wait.
Relationship: neutral
Domain: Hardware
Sentence 1: 7.3 SBC Behavior While comparisons in miss rate, average access time or IPC allow to assess the e.ectiveness of the SBC with re­spect to other designs, measurements on its internal behav­ior allow to understand better how it achieves these results.
Sentence 2: this ensures that all the invalid entries have the largest saturation values in the DSS.
Relationship: neutral
Domain: Hardware
Sentence 1: One SIM card, many systems: Despite many e.orts [1], users are still tied to a single SIM card for phone calls or SMS, mainly because the SIM card is associated with a unique number.
Sentence 2: pre-copying the data for driver copy_from_user requests requires the client stub module to determine in advance the addresses and sizes of the process memory data bu.ers needed by the driver.
Relationship: neutral
Domain: Hardware
Sentence 1: Looking into the future, we note that in regular algorithms, the dependence graph is data oblivious (the butter.y graph of FFT is an example) and so inexactness can be exposed and managed by the compiler.
Sentence 2: doing this in a principled way that optimizes power and energy savings while staying within the constraints of inexactness tolerance of the application is a chal­lenging problem.
Relationship: neutral
Domain: Hardware
Sentence 1: Assuming that there are enough resources to si­multaneously execute 3 copies of task T1 or 2 copies of task T2,(b) and (c) show some possible task graph con.gurations after such a transformation.
Sentence 2: the database consisted of information correspond­ing to images of various sizes-since each task is completely pipelined, the recon.guration delay and number of columns occupied by the task is independent of the image size, but, the execution time is directly proportional to the image size.
Relationship: neutral
Domain: Hardware
Sentence 1: The core theorem is easily expressible in the CLU logic, as the successor function can be used to directly de.ne the rank functions.
Sentence 2: the use of WEB-re.nement for proving the correctness of pipelined machines was introduced in [10], where a num­ber of simple three stage pipelined machines were veri.ed using the ACL2 theorem proving system [7, 8].
Relationship: neutral
Domain: Hardware
Sentence 1: The power consumption measurement was done while transmitting at the full 1 W power output, so this would be the total wattage if using an omnidirectional an­tenna.
Sentence 2: 3.1 RF evaluation We connected an Agilent 9344C spectrum analyzer to the output of the Doodle Labs card through a 50 dB attenua­tor and the result is shown in Figure 1.
Relationship: neutral
Domain: Hardware
Sentence 1: Recently developed 3D data struc­tures have improved this mapping and thus allow the use of e.cient optimization approaches.
Sentence 2: during 3D interconnect prediction the number of layers that has to be taken into account is larger, design objectives are di.erent compared to previous technologies, and additional constraints must be considered: Table 2: Most common 3D data structures applied to 3D .oorplanning problems with regard to their publication date, worst-case complexity of the operations, size of the solution space and main characteristics (n = number of modules, n.g.
Relationship: neutral
Domain: Hardware
Sentence 1: [10] Lewin, D.: Consistent hashing and random trees: Algorithms for caching in distributed networks.
Sentence 2: s2ic As we mentioned in the previous paragraphs, in both ap­proaches, based on location records and collections, we are storing several copies / replicas in DHT, each of the copies / replicas identi.ed by the DHT key computed from one of the names and placed using this DHT key onto a corresponding DHT node (the successor of the DHT key in Chord).
Relationship: neutral
Domain: Hardware
Sentence 1: To perform this task, we used Vapor to abstract the Verilog description of the checker.
Sentence 2: [14] Dong Wang, Pei-Hsin Ho, Jiang Long, James Kukula, Yunshan Zhu, Tony Ma, Robert Damiano, Formal property verification by abstraction refinement with for­mal, simulation and hybrid engines , In Proceedings of the DAC, pages 25-40, 2001.
Relationship: neutral
Domain: Hardware
Sentence 1: RELATED WORK Numerous methods exist to measure and disaggregate electri­cal loads in residential and commercial buildings including non­intrusive load monitoring, plug-load monitoring, and hybrid ap­proaches.
Sentence 2: we have shown that the energy emit­ ted from many electrical loads is roughly proportional to the energy consumed by that load, and that by harvesting this side-channel en­ergy, it is possible to intermittently power sensors whose activation interval (and in turn packet transmission period) approximately en­codes the underlying energy use.
Relationship: neutral
Domain: Hardware
Sentence 1: But this is di.cult: On the one hand, a typical sensor node relies on a microcontroller that o.ers 64K of ROM, 4K of RAM, and 2K of EEPROM storage [2].
Sentence 2: in summary, our evaluation results con.rm that compressed MoteML .les are signi.cantly smaller than both simple Sen­sorML and compressed SensorML encodings.
Relationship: neutral
Domain: Hardware
Sentence 1: They addressed reliability by employing fault toler­ant techniques based on error detection [7], failure prediction Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Sentence 2: the computational runtime of the mapping algo­rithm will increase because equation 6 must be evaluated many times inside the branch-and-bound algorithm.
Relationship: neutral
Domain: Hardware
Sentence 1: Therefore, when directly applying the criterion (24) to the entire data set, a large number of possible c values corresponding to extremely fine-grain clusters are irrelevant and may lead to an inaccurate result due to highly imbalanced left and right sequences.
Sentence 2: based on the aforementioned observation, we propose to add a post-processing step to the traditional L-method to accurately determine the number of clusters.
Relationship: neutral
Domain: Hardware
Sentence 1: A 1 Cycle-Per-Byte XML Parsing Accelerator Zefu Dai, Nick Ni, Jianwen Zhu Department of Electrical and Computer Engineering University of Toronto Toronto, ON, Canada, M5S 3G4 {zdai|yni|jzhu}@eecg.toronto.edu  ABSTRACT Extensible Markup Language (XML) is playing an increasing important role in web services and database systems.
Sentence 2: 4.2.4 High-bandwidth On-chip Data Structure To perform schema validation, many rules have to be checked against an XML construct under parsing.
Relationship: neutral
Domain: Hardware
Sentence 1: Real circuitshave unknown optimal solutionquality, and thusdo not shed muchlight on heuristic suboptimality.
Sentence 2: parameter description T timingpath delay upper bound N number of primary inputs/outputs K (maximum)data path depth f id(i) fanin distribution (#cells withi = 1, ..., I fanins) fod(j) fanoutdistribution(#cells with j =1,..., O fanouts) To generate the circuit properly, the input parameters must sat­isfy three constraints.
Relationship: neutral
Domain: Hardware
Sentence 1: The main important parameters such as overall system e.ciency [2], total number of slots [2] and identi.cation time of the ISO/IEC 18000-6C standard, also known as the Class 1 Generation 2 (C1G2) standard, were compared.
Sentence 2: this research proposes to address these open issues, summarized below, and of fundamental importance for the IoT [1] [3]: Mobility in heterogeneous scenarios;  Standardization taking into consideration the various involved technologies;  Tra.c characterization;  Quality of Service -QoS taking into account the new requirements arising from the heterogeneity of involved nodes.
Relationship: neutral
Domain: Hardware
Sentence 1: Although the high frequency response is highly localized, the mid­low frequency currents (1-2 GHz) dissipate outward from the source to affect several gates.
Sentence 2: in addition, we assumed that total active and passive decoupling capacitance was a low value of 10pF for that area and attached it to the lower metal as 5,512 individual capacitors.
Relationship: neutral
Domain: Hardware
Sentence 1: However, as PCM is non-volatile, FTL mapping table can be kept into PCM-based main memory permanently without considering power failure.
Sentence 2: since the lifetime of PCM is mainly determined by the maximum number of bit .ips in each PCM cell, no matter how smaller the block-level mapping table is, it is important to reduce the maximum number of bit .ips in each PCM cell to enhance the reliability of the entire system.
Relationship: neutral
Domain: Hardware
Sentence 1: Also, we must include the constraint that links current, size and inversion level on any transistor, ID 1 W =1 (12) 2 nf2 µCox L if T and equation (8), the posynomial equality constraint that links (gm/ID)and if , which we will substitute by the in­equality constraint (9) to form the relaxed GP.
Sentence 2: if we solve the relaxed geometric program with only constraint (9) in it, it is reasonable to assume that the optimization problem will always .nd its solution with the largest (gm/ID) ratio posible, since those Figure 3: Common-source ampli.er circuit.
Relationship: neutral
Domain: Hardware
Sentence 1: Whole chip failures are tolerated by chipkill mem­ory and RAID-M [9, 12], and partial failures are tolerated with schemes that map out faulty locations [7, 16, 22].
Sentence 2: first, we want to show that our reliable microprocessor can quickly and correctly detect and diagnose hard faults, even in the presence of transient faults.
Relationship: neutral
Domain: Hardware
Sentence 1: 3 can also be inferred that the natural frequency of the loop s oscillations should the phase/gain margins drop to 0 is expected to be between 2.4 MHz (0db gain crossover frequency) and 3.5 MHz (180 degrees phase lag).
Sentence 2: node Stability Peak Natural Frequency, Hz Loop at 3.3 MHz Output 28.884067 3.16E+06 net052 28.884063 3.16E+06 net136 28.884748 3.16E+06 net138 27.522194 3.16E+06 net99 27.086771 3.31E+06 Loop at 36.3 MHz net066 0.948229 3.63E+07 Loop at 47.9 MHz net81 5.334409 4.79E+07 net17 0.504486 4.68E+07 net056 4.608340 4.79E+07 Loop at 51.3 MHz net013 5.063032 4.90E+07 net57 4.485003 5.01E+07 net16 0.252345 5.01E+07 net75 5.072788 4.90E+07 net019 0.232893 5.13E+07 the suggested method of using the stability plot to analyze circuit s stability without breaking the main feedback loop proved also very useful in identifying local feedback loops which may require compensation as well.
Relationship: neutral
Domain: Hardware
Sentence 1: The global constraints obtained can be used to simplify the problem instance and prune the search space of the SAT solver.
Sentence 2: computation of in­direct implications involves extensive use of contra-positive * supported in part by NSF Grant 0196470, 0305881, 0417340, and SRC Grant 2005-TJ-1359.001 Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.
Relationship: neutral
Domain: Hardware
Sentence 1: Hence, we use the Versatile Place and Route (VPR) tool (FPGA placement and routing tool) [Betz 97] to place and route 20 largest MCNC benchmark circuits [Yang 91] and 3 relatively large (>10k LUTs) circuits from QUIP benchmark design set [Altera QUIP, Pistorius 07].
Sentence 2: 4.1 is the total capacitance Vs GND of a NEM relay.
Relationship: neutral
Domain: Hardware
Sentence 1: For example, in Figure 9, the inputs of the gate 5 depends on A, B, C and D. Some of these vertices may also share subpaths when reaching the inputs of gate 5.
Sentence 2: 1.0 (Value is less than equal to Time t) Time t 0.0 Figure 2 Arrival times are modeled as Cumulative Probability Density Functions (CDFs).
Relationship: neutral
Domain: Hardware
Sentence 1: The inability of industrial timing veri.cation tools to iden­tify false paths was slightly mitigated by allowing the de­signer to tag known false paths, to be ignored during timing veri.cation.
Sentence 2: the value of this variable will be computed by adding the arrival time value at the input pin to the proper delay value, chosen according to the logic value variables of the input and output pins.
Relationship: neutral
Domain: Hardware
Sentence 1: .. =[.. ..×..1 1 , ..1 ..×..2 ,...,.. ..×....-1 ..-1 , ....-1 ..×.... ], (8) This lemma indicates that if the number of inputs is iden­tical to the number of outputs (i.e., .. = ..),which is the 684 Note that every diagonal block entry in (11) and (12) is a .... ×.... square matrix,thus .. and .... are both (..1 + ..2 + ... + ....) ×(..1 + ..2 + ... + ....) square matrices.
Sentence 2: they both satisfy the condition that .... = .... for ..<.. but more data are utilized for the latter.
Relationship: neutral
Domain: Hardware
Sentence 1: Leakage currents of two-input NAND gate Input Leakage (pA) Leakage (pA) for high-Vt For low-Vt 1 As to synthesis, the work uses the Stelling s technique in [8] which produces timing-optimal arithmetic FA/HA-tree structure without considering interconnect delay.
Sentence 2: this does not mean that our power reduction approach heavily relies on the timing-driven synthesis and placement.
Relationship: neutral
Domain: Hardware
Sentence 1: Of course, this method is exponential in its run time complexity with circuit size and is not useful as a practical solution.
Sentence 2: consider the set of k predecessor nodes np,i of node n, with fanin subgraphs GS,i, and the intersection graph GI ={NI,EI} consisting of the union of edges and nodes shared by two or more subgraphs, excluding the source node ns.
Relationship: neutral
Domain: Hardware
Sentence 1: This example shows that for two consecutive coarse­grained intervals of different phases, the prediction results tend to be inaccurate if the .ne-grained phase behavior in one coarse­grained phase is predicated based on the execution history in the previous one.
Sentence 2: for the .ne-grained phase analysis, such as LV or Mkov, we also use the same partition method.
Relationship: neutral
Domain: Hardware
Sentence 1: ACM Multimedia Workshop Marina Del Rey CA USA Copyright ACM 2000 1-58113-311-I/00/11 ...$5.00 Broadband Environment for Personalized TV Experience (IBEX)"[5] aiming at an actual service operation, succeeding our previous service-oriented demonstration for TV-Anytime Forum[6] at NAB2000.
Sentence 2: 3.2.2 Metadata Description Metadata description is instance of metadata conformable to metadata schemas.
Relationship: neutral
Domain: Hardware
Sentence 1: This paper shows that eliminating some of the [10] H. S. Wang, L. S. Peh, and S. Malik, Power-driven Design bu.ers in the router and using adaptive link bu.ers saves an of Router Microarchitectures in On-chip Networks, in appreciable amount of power and area, without signi.cant Proceedings of the 36th Annual ACM/IEEE International Symposium on Microarchitecture, Washington DC, USA, degradation in the throughput or latency.
Sentence 2: we can overcome the credit turn-around time without having to sacri.ce throughput in iDEAL.
Relationship: neutral
Domain: Hardware
Sentence 1: A VLIW architecture description template constituting a large variety of instructions is the starting point of semi­retargeting.
Sentence 2: the facts are as follows: (1) Micro-pro.ler tends to over-estimate the cost of instructions since its opti­mizations are not as strong as those of MIPS-GCC, as canbe observed in Figure 6.(a).
Relationship: neutral