sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Our study shows that both the XHPWL model and the XStWL model can reduce the X wirelength.
Sentence 2: our results reveal the e.ective­ness of the X architecture on wirelength reduction during placement and thus the importance of the study on the X­placement algorithms, which is di.erent from the results given in the previous work that the X-architecture place­ment might not improve the X-routing wirelength over the Manhattan-architecture placement.
Relationship: entailment
Domain: Hardware
Sentence 1: SECTION A: In default mode, RQL obtains the best HPWL results on all eight circuits of the ISPD-2005  benchmark suite.
Sentence 2: rQL obtains an average wirelength improvement of 2.8%, 8.5%, 14.6%, 3.2% and 5.4% versus mPL6, APlace2.0, Capo10.2, NTUPlace3 and Kraftwerk respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: PROPOSED SOLUTION FOR RELIABLE MODULAR TESTING 4.1 Jitter-Aware Test Wrapper Design Different from mitigating traf.c jitter by using buffers, the basic idea behind the proposed test wrapper design is to halt the scan pro­cess by gating the scan clock signal when necessary.
Sentence 2: when compared with the previous designs, for scan tested cores, besides the normal SHIFT and CAPTURE states, we introduce two extra states: HALTIN state for the case that the test vector .its come late to the wrapper due to retransmission on input path, and HALTOUT state for the case that new test response .its cannot be transmit­ted because the test traf.c is blocked on the output access path (as shown in Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: Second, it explores a wide swath of the area-performance design space of this data.ow architecture.
Sentence 2: we describe the microarchitecture for two key parts of the WaveScalar processor: its most area­intensive components, including those that implement its dis­tributed data.ow capabilities, and the interconnection net­works that localize data communication, contributing heavily to performance.
Relationship: entailment
Domain: Hardware
Sentence 1: Let ib be the vector such that S =diag(ib)and M = Q-11.Then Mix mod ib =0 i. there exists iu .Zn such that Mix = Siu i. there exists iv .Zn (iv = Q-21iu) such that ix = Aiv.
Sentence 2: there is a direct correspondence between sublattices .
Relationship: entailment
Domain: Hardware
Sentence 1: The solution is evaluated by means of a .tness function that builds the con.guration described in the chromosome starting from the speci.cations of the application and the architecture given in input, and performs a simulation of its execution, on the basis of the models presented in Section III, to evaluate the considered metrics.
Sentence 2: the application is scheduled with a list-based scheduling algorithm to compute the various metrics, i.e., execution period, energy consumption, lifetime and performability.
Relationship: entailment
Domain: Hardware
Sentence 1: While these states can be used to implement majority and multi-valued logic [4, 5], it was suggested that this approach could also provide more radical departures that evolve spatial correlations through the nonlinear dynamics of interactions between elements similar to cellular automata [3].
Sentence 2: arrays of locally connected elements [6] have been shown to exhibit such behavior as simple image processing functions [7], the storage of sequences of patterns and the simulation of certain wave dynamics [8].
Relationship: entailment
Domain: Hardware
Sentence 1: Although it is widely believed that understanding tra.c demands is necessary for achieving good utilization of the network [21, 2, 9, 15], this belief was never carefully quan­ti.ed: How well can a routing designed with no knowledge (or only ball-park knowledge) of the TM perform?
Sentence 2: how precise an estimate of tra.c demands is needed in order to guarantee good utilization?
Relationship: entailment
Domain: Hardware
Sentence 1: The reduced num­ber of ports, however, constrains the potential parallelism of memory operations, thereby limiting the overall accelera­tor performance.
Sentence 2: hLS tools allow the binding of a data structure, such an array, to a generic memory in­stance but introduce tight constraints on the use of these memories: e.g., for most tools the total number of process interfaces that can access a data structure cannot exceed the Listing 1: Synthesizable SystemC code of two simple number of ports of the corresponding memory instance.
Relationship: entailment
Domain: Hardware
Sentence 1: , plug it in (2) and use where n=0 Binomial Expansion, we have (6).
Sentence 2: zZ ' ' '' '' T(f , g ; f , g ) can be expanded as ' ' ' In(f , g) = Tn(f + f, g ' + g; f , g ) ' ' *'''' 8 × F(f + f , g + g)F (f , g )df dg .
Relationship: entailment
Domain: Hardware
Sentence 1: In order to create training data for forming a test-termination prediction model, an IC that has failed N test patterns is used to produce N diagnostic results.
Sentence 2: test patterns that include the first one (either passing or failing) through the first failing pattern are used to produce the first diagnostic result, test patterns that include the first through the second failing pattern are used to produce the second diagnostic result, and so on until N diagnostic results are created using all N failing test patterns.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.2.1.1 Non-monotone Clustering Constraints and Optimal Mapping Depths The fundamental difficulty of k/m-macrocell based FPGA mapping is that the constraint on the number of inputs and the number of product terms of a k/m-macrocell are not monotone clustering constraints.
Sentence 2: a cone C~ is k-infeasible (or, m- unpackable) does not guarantee that all its super-cones (i.e.
Relationship: entailment
Domain: Hardware
Sentence 1: In summary, we observe that value prediction produc­es significant performance improvements for a cluster or­ganization, which are higher than those observed for a cen­tralized one, especially when adequate steering techniques are implemented.
Sentence 2: we have found that for a 4­cluster configuration the IPCR4 ratio increases on average by 18%, from 0.65 to 0.77, and for a 2-cluster configuration IPCR2 increases by 5%, from 0.85 to 0.89.
Relationship: entailment
Domain: Hardware
Sentence 1: (8) suggests that by introducing the TSS scheme into a DRM system, the long-term delay shift of a critical path is proportional to the Vth degradation measured from the asso­ciated aging sensor.
Sentence 2: the Vth sensor measure­ment indicates the NBTI-induced degradation of the entire Table 1: TSS Based Delay Shift Estimation for IS­CAS85&#38;89 Circuits Name Estimation Error by TSS Scheme relative to time 0 delay (%) .t = 1000 clk .t = 2500 clk .t = 5000 clk .t = 10000 clk Cst.
Relationship: entailment
Domain: Hardware
Sentence 1: prefetches exceeds the threshold value (which is 35% in our experiments)in epoch e,thedatablocks broughtbythatclient tothememory cache arepinnedintheshared cache duringthe entire epoch e+1.Inthis case,whenaprefetchtriestokick out a data block of this processor, another victim (from another client) is selected, again based on the LRU policy.
Sentence 2: thevictimistheblockthat has not been broughtinto thecachebythat client andhasthelowestLRU valueamong all suchblocks.As before,the countervalues areresetto0 at thebeginningof each epoch.Notealsothattheblocksbrought into the shared cache in epoch e+2 (bytheclientwhoseblocks are pinned in epoch e+1) are not pinned.
Relationship: entailment
Domain: Hardware
Sentence 1: (2) Unstable TSV-bu.ers (e.g., Figure 3(b)): A TSV-bu.er is called in an unstable state if it causes additional normal bu.er insertion due to the delay imbalance by the intrinsic delay of the TSV-bu.er.
Sentence 2: at least one normal bu.er is needed to make an initially unstable TSV-bu.er be stable.
Relationship: entailment
Domain: Hardware
Sentence 1: 5(b) reports the breakdown of the channel total storage that is required to obtain maxi­mum bandwidth in a non-saturated NoC as function of the number K of channel repeaters.
Sentence 2: the sequence of points on the x-axis corresponds to 20 di.erent design sce­narios for K that varies from 1 to 10.
Relationship: entailment
Domain: Hardware
Sentence 1: At a closer analysis, all the existing cryptographic primitives have proofs of security based on two assumptions: (1) read­proof hardware; that is, hardware that prevents an enemy from reading anything about the information stored within it; and (2) tamper-proof hardware; that is, hardware that prevents an enemy from changing anything in the information stored within it.
Sentence 2: existing cryptographic schemes consist of an algorithm which the adversary knows, but cannot change (i.e., stored in tamper-proof hardware), and a secret key, which the adversary does not know and cannot change (i.e., stored in hardware which is both read-proof and tamper-proof) [17].
Relationship: entailment
Domain: Hardware
Sentence 1: The number of .oorplans that are tried remains the samein the second option,but thermal signature is used, which has less correlation with actual temperature now.
Sentence 2: there is a possibility that a .oor­plan may be regarded to have low maximum temperature while it is opposite in reality, which explains the result in Figure 7(c) and in turn (a) and (b).
Relationship: entailment
Domain: Hardware
Sentence 1: This can be further extended if there are multiple non-volatile areas to be used in conjunct with power gating, which should be feasible in similar ways that the current implementations of quick power gating [4, 5].
Sentence 2: when we are performing power-off operations, we can choose which of non-volatile areas to be used for saving the states of the programs running on the processor.
Relationship: entailment
Domain: Hardware
Sentence 1: In comparison, the dynamic approach adaptively 5000 5200 5400 5600 5800 6000 5000 5200 5400 5600 5800 6000 Request Number Request Number adjusts the TUC value; if there are too many blocks selected (a) Financial Trace (b) PC Trace Figure 4: Idle Time distribution between 2 consec­utive .ash-access requests The long idle time between .ash-access requests can be exploited to mitigate the computation overhead in the block eviction process.
Sentence 2: we propose to partition the WBC into two regions: a Work Region (WR) and an Evic­tion Region (ER).
Relationship: entailment
Domain: Hardware
Sentence 1: Note that if v0 corresponds to main in a C program, T P equals the complete program execution 0 time when partitioning P speci.es whether vertices are mapped to HW or SW. For a partitioning P,the execution time change metric .P i ,for a vertex vi, is de.ned as the change in execution time when the vertex vi is moved to a different partition.
Sentence 2: .P denotes the change i in T P when vertex vi is mapped to a different partition.
Relationship: entailment
Domain: Hardware
Sentence 1: As for BFs, by means of HSPICE simulations, we have found that the 10% of all possible BFs can result in the generation of a Pass, rather than a Fail, at the BIST structure output, each for values of connecting resistance (Rbrid) lower than a maximal value (Rmax), whose value depends on the considered BF.
Sentence 2: we found that, for these BFs, Rmax = 4k.. As an example, Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: Lastly, we conclude that dividing a bank into only 32 groups provides close bene.ts as compared to dividing it into 512 groups.
Sentence 2: additionally,we notethatfor all the examinedprograms, CE always provides a robust performance versus S. noneof theprograms, running underanygroupgranularity, shows performance degradation against S. Fig.
Relationship: entailment
Domain: Hardware
Sentence 1: Technology scaling enables the integration of numerous transistors and complex functionality in a single chip, enabling the realization of such miniature WBSN systems, but as we move beyond the 65nm node, new nano-scale electronic devices exhibit a significant growth of reliability issues.
Sentence 2: as transistors are getting smaller it becomes more difficult to fabricate them, which causes spatial and temporal variations in their characteristics that lead to unpredictable behavior.
Relationship: entailment
Domain: Hardware
Sentence 1: (26) 0 Wehave explicitly used the notation xzxc,T0 (t), as a reminder that the solu­tion xz(t)ofthe adjoint system,depends onthe output vectorxc andthetime point T0 .
Sentence 2: note that the adjoint solution xzxc,T0 satis.es(see section§S4 ofthe supplementary materialfordetails): xzxc,T0 (T0 )= xc, and (27) xzxc,T0 (t)= x0 .t>T0 .
Relationship: entailment
Domain: Hardware
Sentence 1: With the optimal routing, the total cost to go from node s to t becomes m Vt * (s0)= min Csi-1,si (8) .si.P m s0,sm j=1 where i =0,1,...,m and vsm = vt.
Sentence 2: each router m is able to look ahead for all possible paths Ps0 ,sm to the destination and choose the one with minimal delay.
Relationship: entailment
Domain: Hardware
Sentence 1: Note that, in order to be able to impersonate a victim at, say, approximately 20:00 of every Monday in a two-year period, the adversary must fabricate about 104 AS_REQ * messages as described above and, for each such message, obtain a signature from the card.
Sentence 2: a few minutes of access to a victim s card are su.cient for the adversary to be able to impersonate the victim, on a regular basis, for years.
Relationship: entailment
Domain: Hardware
Sentence 1: INTRODUCTION AND MOTIVATION Among the negative side e.ects of technology scaling, the reliability of CMOS devices has become of primary concern.
Sentence 2: due to an increasing electric .eld across an ex­tremely thin oxide, the generation of interface traps under negative bias temperature instability (NBTI) in pMOS tran­sistors has become the most critical reliability issues that determine the lifetime of CMOS devices [1, 2].
Relationship: entailment
Domain: Hardware
Sentence 1: They identi.ed regions of 2 meters to 5 meters within which move­ment could be reliably detected [43].
Sentence 2: they have been able to localise an ob ject with an accuracy of 1 meters by creating hexagonal cell-clusters over which measurements are scheduled according to a TDMA scheme which was fur­ther improved by Wilson et al.
Relationship: entailment
Domain: Hardware
Sentence 1: white@mit.edu ABSTRACT An ef.cient approach to full-wave impedance extraction is devel­oped that accounts for substrate effects through the use of two-layer media Green s functions in a mixed-potential-integral-equation (MPIE) solver.
Sentence 2: the choice of implementation for the layered media Green s functions motivates the development of ac­celerated techniques for both volume and surface integrations in the solver.
Relationship: entailment
Domain: Hardware
Sentence 1: The proposed approaches exploit the knowl­edge on prefetched lines by employing a different decay in­terval (time frame after which the cache line is turned off) for prefetched lines.
Sentence 2: in the proposed strategies, the prefetched lines and the normal lines (i.e., the lines brought into the cache through execution of load operations) use differ­ent thresholds.
Relationship: entailment
Domain: Hardware
Sentence 1: By showing students high performance computing in the context of how it is used, namely on big problems running on big machines, they are allowed to have an authentic computing experience.
Sentence 2: the issue of performance analysis becomes very important, as students quickly find that there is the trivial interpretation of how they expect problems to scale, there is the theoretically understandable eventuality of Amdahl s law, and there is the actual reality in which the algorithm used to solve the problem, the approach used to parallelize the code, the configuration of each node, and the interconnect between the nodes can all interact in nonlinear and unpredictable ways.
Relationship: entailment
Domain: Hardware
Sentence 1: The rest of the symbols are assumed for local wire width variations, linearized by .rst-order Taylor series expansion, and are only shared by a cluster of RLC elements that are close enough to one another.
Sentence 2: for the case of, say, 6 uncertainty terms, we partition each net-list into 6 groups, and assign the same uncertainty term to every element in one group.
Relationship: entailment
Domain: Hardware
Sentence 1: A number of tools have been developed to enable veri.ca­tion engineers to have more control over the generation of ran­dom tests.
Sentence 2: some of these techniques involve the use of program templates that de.ne the structure of the desired test, along with primitives to control the randomization of the related data, such as opcodes, register operands, and memory addresses [3].
Relationship: entailment
Domain: Hardware
Sentence 1: Consider a set of objects O1,O2,...,On and a set of cor­responding access probabilities p1,p2,...,pn.
Sentence 2: the reference string can be denoted as r1,r2,...,rt,...,rN , where rt is the object referenced at time t. Under IRM: Pr[rt =Oi]=pi , 1= i= n, t > 0 the probability of rt being Oi is pi.
Relationship: entailment
Domain: Hardware
Sentence 1: This extremely exible architecture had few critical paths (power and clock wires) and highly re­dundant network connectivity through the fat-tree [19]; this allowed the compiler to map out the defects in the system, and simply route around bad LUTs and interconnects when compiling.
Sentence 2: the conscious design decision to out-wire Rent s Rule (Teramac used Rent s Rule exponents of 2/3 to 1, as opposed to 1/2 to 2/3) allowed the system to function normally despite defects in 10% of logic cells and 10% of interchip interconnects.
Relationship: entailment
Domain: Hardware
Sentence 1: In nanometer scale technologies where leakage dominates the power consumption, an increase in the power It can be seen from (18) that parameters such as the supply voltage, operating frequency, junction-to-ambient thermal resistsance, and ambient temperature can cause thermal runaway when their values increase above certain critical values.
Sentence 2: such parameters can alsobeused tocontrol andprevent thermal runaway.
Relationship: entailment
Domain: Hardware
Sentence 1: We have extended a modern RTL, Chisel [1], and found inspiration from the software world [11], to take a new approach: instead of abstracting away fundamental features of the architecture as in High Level Synthesis abstract only those details which a designer is uncertain of.
Sentence 2: designers construct their circuits in RTL as usual but leave holes, or explicit indeterminacies, in their designs.
Relationship: entailment
Domain: Hardware
Sentence 1: Their analysis, in turn, is based on Sharir and Pnueli s tabulation based approach to inter-procedural analysis [18], with an important modi.cation: when a call­site is encountered, the analysis proceeds to analyze the callee (together with all its transitive callees) to completion before proceeding with the analysis of the caller.
Sentence 2: a depth-.rst propagation strategy is followed, rather than a chaotic strategy or a breadth-.rst strategy (we dis­cuss later the advantages offered by this strategy).
Relationship: entailment
Domain: Hardware
Sentence 1: CONCLUSION In this paper, we presented a novel approach for solving the con­sistency problem that arises as soon as an architecture description language (ADL) serves multiple purposes.
Sentence 2: the auto­matic generation of C compiler and instruction-set simulator from a single model description either leads to a loss in modeling .ex­ibility, or introduces a huge potential for inconsistencies.
Relationship: entailment
Domain: Hardware
Sentence 1: Although several architectural DMR proposals suggest thatDMR can easilybe turned on and off(e.g.,[19,32]), a key observation of this paper is that dynamically switch­ing between DMR and non-DMR within a single system is not as straightforward as it might appear.
Sentence 2: we observe that 1) care must be taken to preserve the integrity of reliable applications memory and register state, and 2) thedesireto executeadditionalindependentsoftwarethreads for aperformance application complicatesthe schedulingof softwarethreadstocores.Aspart of thesolutiontothe .rst problem, we propose to maintain a small amount of redun­dancy for non-DMR applications by re-validating permis­sion for any stores that miss in the L1 cache.
Relationship: entailment
Domain: Hardware
Sentence 1: The semi-lattice has well-de.ned top and bottom elements, which correspond to the least constrained and most con­strained protocol variants of a particular logic family, respectively.
Sentence 2: our approach provides, for the .rst time, precise, well­de.ned upper and lower bounds on the design space of concurrent protocols for asynchronous pipelines using dynamic logic, as well as the complete set of legal, intermediate protocols, which together form the complete design space.
Relationship: entailment
Domain: Hardware
Sentence 1: In these two figures, the features extracted from high frequency components, corresponding to the big x-axis coordinates, have small p-values, in comparison with the features extracted from low frequency components, corresponding to the small x-axis coordinates.
Sentence 2: the spectrum features extracted from high frequency components are more statistically significant than the features extracted from the low frequency components, which confirms our analysis and inference presented in section 2.
Relationship: entailment
Domain: Hardware
Sentence 1: While existing technology mapping and placement algorithms could be directly incorporated into our JIT compiler, we are working on developing such algorithms designed for our SCLF.
Sentence 2: we are developing a placement algorithm designed in conjunction with both our configurable logic fabric and ROCR hoping to be able to exploit this information to choose a placement such that ROCR can perform routing more efficiently and create designs with shorter critical paths using fewer routing resources.
Relationship: entailment
Domain: Hardware
Sentence 1: We hope that the empirical study and analysis of retention error mitigation techniques, driven by experimental measurements from real DRAM chips, presented in this paper can enable new, effective, and ef.cient mechanisms in the future that will lead to more reli­able design and operation of future DRAM systems.
Sentence 2: we believe the development of ef.cient online retention time pro.l­ing techniques for DRAM is a promising area of immediate future work that can bene.t from our characterizations and analyses.
Relationship: entailment
Domain: Hardware
Sentence 1: In this paper, we improve over the work of [2], by proposing an encoding solution which exploits inter-pixel correlation in a di.erent way.
Sentence 2: we speci.cally target the en­coding function to the serial nature of the transmission; the basic idea of the method is to minimize intra-word transi­tions by clustering the 1 s in the encoded values towards one end of the word.
Relationship: entailment
Domain: Hardware
Sentence 1: An ELM experiment investigating the e.ects of race of information sources found that white American subjects were systematically processing messages in a low-involvement situation when the source of the information was black.
Sentence 2: where the ELM would predict that white par­ticipants would not pay attention to the content of the mes­sage in forming an opinion, they were doing so if and only if the source was black [27].
Relationship: entailment
Domain: Hardware
Sentence 1: 4.2 Body Bias Generator for Back Body Bias The measured average current of the low power body bias generator was about 5.4uA (unstable state ;1-5) and 1.5uA (stable; 6) at 27°C and VDD1=1.0V.
Sentence 2: it is effective when the  leakage current of the whole semiconductor integrated circuit is larger than the conventional minimum value.
Relationship: entailment