sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: 1.1 Working Set Identi.cation It is well known that a program doesn t use its entire memory space all the time but in fact uses subsets of its memory space at di.erent periods of time.
Sentence 2: a pro­gram s runtime can be divided into several phases such that the set of pages touched by the program in each phase (the working set) is more or less constant.
Relationship: entailment
Domain: Hardware
Sentence 1: The last phase (backend) has concerned with the logic synthesis where the whole set of VHDL files have been synthesized to generate (by means of Mentor Graphics Leonardo [6] and Xilinx Design Manager/EDK [5]) the bitstream for the target platform: the Xilinx Virtex-II Pro FPGA family [5].
Sentence 2: it has been used the Memec Design Virtex-II Pro Development Kit [19].
Relationship: entailment
Domain: Hardware
Sentence 1: We discretize the pass-band of the filter and represent it by K discrete frequency values {hk; k = 1,2, ,K}.
Sentence 2: instead of solving the unknowns {µn; n = 1,2, ,N} as continuous variables, we constrain the solution space to a set of discrete values defined by {hk; k = 1,2, ,K}.
Relationship: entailment
Domain: Hardware
Sentence 1: These hard blocks have .xed locationsand must communicateoverafairlylong distance.
Sentence 2: second, high-bandwidth, bit-serial wires can save area in low­cost devices like Cyclone and Spartan which have a restricted amountof interconnectavailable.itiseasyto generate large designs using EDK and SOPCBuilder; these tools generate complex systems interconnected by a word-oriented crossbar-like fabric.
Relationship: entailment
Domain: Hardware
Sentence 1: I. INT RODUC T ION The multi-gate MOSFETs are considered to be among the best candidates to extend the CMOS technology into the 14 nm node [1].
Sentence 2: gate-All Around (GAA) devices, closely followed by FinFETs, can be scaled to the shortest channel length possible for a given gate oxide thickness [2].
Relationship: entailment
Domain: Hardware
Sentence 1: Failure boundaries µ1, µ2, and µ3 represent values for the duty cycle of the clock signal under investigation and they are ordered such that µ1 < µ2 < µ3, thereby making µ3 the most aggressive failure boundary to reach among the three.
Sentence 2: µ1, µ2, and µ3 are chosen to be 13.7%, 24.9%, and 34.4% over the nominal output, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: One appeal of this approach is that application tuning has the potential to completely remove a resource wall, by eliminating communication, while changing the ef­.ciency of the protocol only has the e.ect of moving the resource wall a little further out.
Sentence 2: from an overall application performance perspective, it is far better to change the algorithm to remove communication (if pos­sible) then it is to create hardware mechanism to make the communication more e.cient.
Relationship: entailment
Domain: Hardware
Sentence 1: SOC MEMORY ALLOCATION Based on the memory controller described in Section 3, we developed a methodology to optimize the memory orga­nization of the entire accelerator.
Sentence 2: after the designer has selected an implementation for each process, it is possible to determine the number of parallel memory inter­faces that each data structure requires to ensure a su.cient amount of memory bandwidth to the processes.
Relationship: entailment
Domain: Hardware
Sentence 1: Since the Data memory is accessed at about 50-60ns (at the average case), and the major part of the queue handling is done in parallel with the data access, we claim that our system introduces minimum latency.
Sentence 2: in terms of latency, you get the queue handling almost for free , since the DMM s latency is about the same as the one of a typical (support only read and write) DRAM subsystem.
Relationship: entailment
Domain: Hardware
Sentence 1: Introduction The components offuturemulticoreprocessors willbecomeless re­liable as technology scales,becauseindividualdevices areincreas­inglysusceptible to a variety ofhardwarefaults[6,8,10,12,34,36].
Sentence 2: technology experts warn about an increase in in­termittent faults faults which occur frequently and irregularly for a period of time, commonly due to process variation or in­progress wear-out, combined with voltage and temperature .uctu­ations[6,8,12,13].These arein addition to transient faults(or soft errors), typically caused by particle strikes, and permanent faults, which occur repeatedly after adevice sustainsirreversibledamage.
Relationship: entailment
Domain: Hardware
Sentence 1: Speci.cally, concentrating on a set of array-intensive appli­cations that make frequent use of the disk system, this paper makes the following two contributions: We present an approach which, given a data-intensive ap­plication code, determines automatically the parts of the ap­plication code that can be executed on the smart disk system.
Sentence 2: this approach, which is based on integer linear programming (ILP), partitions the application code between the host system and the smart disk system.
Relationship: entailment
Domain: Hardware
Sentence 1: Perhaps surprisingly, we show that this limitation of testing can be eliminated if testing is combined with a limited amount of formal veri.cation and if the machine is designed appropriately.
Sentence 2: we show that for an election with N contests in which each contest involves selecting one out of k candidates, we can verify correctness with just O(kN)tests, instead of the O(kN )tests exhaustive testing would require.
Relationship: entailment
Domain: Hardware
Sentence 1: Therefore, the WG-16 transformation WGT-16(Xd)can be computed using four multipliers in total, where two multipli­ ers are utilized for generating Y , one for computing Y 211 +1 -1 and one for calculating Y 211 .
Sentence 2: thanks to the nice property for computing the trace of the product of any two elements with tower .eld representations in F(((22 )2 )2 )2 , ( ) Y 211 +1 Y 26 .16 Y 211 -1 the two multiplications and YY 211 (211 -1) inside the trace function have been replaced by bitwise AND and XOR operations, which reduces both hardware and time complexities signi.cantly.
Relationship: entailment
Domain: Hardware
Sentence 1: When we increase the slack S1for Sink1 to 2 in Figure 3 (b), b0has tostay VddH restricted by S0 = 1.
Sentence 2: b0 is restricted by both S0and S1, and VddL can only be assigned to b0 when S0 =3 .S1 =2.
Relationship: entailment
Domain: Hardware
Sentence 1: The W1:W2 ratios are (a) 2:1 (b) 8:1 (c) 1:8 and (d) 1:1.  depending on the choice of the termination criteria and adaptive resampling methods.
Sentence 2: false split reporting rate was high with the K-means and two-nearest-neighbor algorithm due to the shape of the final cluster not being a loop.
Relationship: entailment
Domain: Hardware
Sentence 1: 6 Design exploration The application described in Section 2 presents interesting implementation trade-offs that must be accurately investigated especially as regards its coexistence on the same hardware plat­form with other important engine control functionalities.
Sentence 2: real time aspects (due to .ltering functions) of the knock detection functionality require early assessments of over­all computational loads in order to carefully de.ne the hard­ware partition of the platform so to minimize cost without com­promising performance.
Relationship: entailment
Domain: Hardware
Sentence 1: CO., LTD {sp7.hong, sungjoo.yoo, hoonsang.jin, kmchoi, jkong, sookwan.eo}@samsung.com ABSTRACT We propose a new intra-task dynamic voltage scaling (DVS) method to capture an important fact of software runtime distribution and integrate it into DVS effectively.
Sentence 2: the proposed method finds performance levels, for a given software runtime distribution, i.e.
Relationship: entailment
Domain: Hardware
Sentence 1: While this may not be desirable from the perspective of minimiz­ing the average power, it may also not be possible, in the case where we cannot arbitrarily adjust the adaptive volt­age.
Sentence 2: if the upper range of the adjustable volt­age is .nite, denoted by U, then the expected yield becomes lim(vtol .U-)Pr(.Vadaptive = vtol)p .
Relationship: entailment
Domain: Hardware
Sentence 1: This way performance loss for any cache sample concentrates close to the average and hence, performance becomes highly pre­dictable.
Sentence 2: the highest standard deviation for each one of the .ve schemes is 3.1% for the Pellston-like scheme, 3.0% for wdis,3.6% for bit .x, and 1.9% and 0.6% for the cache subblock disabling scheme without and with predictability enhancements respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: HALF-PIXEL MOTION ESTIMATION REFINEMENT A characteristic that contributes to the high compression rates achieved by the H.264/AVC Motion Estimation is the possibility to generate fractional motion vectors (FMV) with half-pixel or quarter-pixel accuracy [2].
Sentence 2: a movement that happens from a frame to another in a video running at 30  frames/sec is not restricted to integer pixel positions only.
Relationship: entailment
Domain: Hardware
Sentence 1: However, (1) the simple Rent s Rule spatial bisection we took to get p did not consider dividing wires and PEs by evaluation time, (2) we can get a pair of nodes at a PE that are the same depth from the input, and (3) there are designs where signi.cantly more than half the nodes are at depth 2.
Sentence 2: in the general case, the con.guration memories may need to change at more than two di.erent times.
Relationship: entailment
Domain: Hardware
Sentence 1: logically write data of pages p (p + len) back to their correspond­ing linked LBAs.
Sentence 2: when the device driver plans to issue the command U NL INK (p, len) to unlink the mapping between pages l (l + len) and their corresponding len LBAs, it actually derives the starting memory address addrp for page p; then the device driver requests the memory controller to issue a real U NL INK command to request the PCM device to unlink the memory from address addrp for consecutive s bytes that equal to the size of len pages, so that accesses to addresses addrp (addrp +s) are not redirected to other addresses anymore.
Relationship: entailment
Domain: Hardware
Sentence 1: Our implementation exploits the under­lying LLVM constructs and information from the synthesis to e.ciently determine relevant post dominance informa­tion.
Sentence 2: lLVM has a special select instruction of the form y = select cond x1 x2; the synthesis tool typ­ically targets the condition variable of select instructions for operation gating.2 Function Find-Gating-Info crawls over the data .ow graph of CCDFG G, .rst identifying each select instruction; for each y it then .nds all variables that are post-dominated by y recursively.
Relationship: entailment
Domain: Hardware
Sentence 1: The covering regions C Ri j form the collection of sub­sets S.  If the bu.er size bj denotes the weight of a subset C Ri j , then the ob jective is to pick minimum weighted sum of subsets such that each node has at least one subset covering it.
Sentence 2: the mesh bu.ering problem is identical to the set cover problem with I .
Relationship: entailment
Domain: Hardware
Sentence 1: The circuits used for experiments were synthesized from large Burst-mode asynchronous controller speci­.cations [8] using the Minimalist and the SIS toolsets.
Sentence 2: for single-output implementations, state minimization (min-states in Minimalist) and state assignments (assign-states -s -O -P in Minimalist) were performed by asynchronous tools while two­level (espresso -Dso) and multilevel synthesis (script-rugged in SIS) as well as technology mapping (map in SIS) were performed using non-hazard-free synchronous tools.
Relationship: entailment
Domain: Hardware
Sentence 1: As shown in Figure 14,Triple-A successfully reduces both kinds of contentions bydistributing the extra load of the hot clusters through datamigration and physical data-layout mapping, as the numberof clusters increases.
Sentence 2: the link contention timeis almost completely eliminated while the storage contentiontime is steadily reduced as the number of clusters increases.This is because the storage contention time is bounded by (a) Without Triple-A (b) With Triple-A Figure 15: Breakdown of the average execution time of read micro-benchmark on a nonautonomic all-f ash array (a) and Triple-A (b) under varying network sizes.
Relationship: entailment
Domain: Hardware
Sentence 1: In general, 2D-HERT outperforms various optical architectures due to its simple all-optical data network and high-speed low­power control plane.
Sentence 2: averaging through different traffic patterns, proposed architecture achieves average per­packet power reduction of 53%, 45%, and 95% over optical crossbar, .-router, and electrical Torus, respectively.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.2 Bounding the Distribution of Circuit Delay We now show how we can derive a bound on the cdf of the longest path delay propagating through the probabilistic timing graph that has the properties defined in the previous section.
Sentence 2: we derive an upper and a lower bounds on Ft( ) = P(max{D1...DN } = t) where Di is the delay of the ith path.
Relationship: entailment
Domain: Hardware
Sentence 1: We found that the drag times for auction, calc, .rstaid, image, jpeg, manyballs, mvideo, and pushpuzzle are 53%, 45%, 59%, 53%, 82%, 54%, 88%, and 48%, respectively.
Sentence 2: the objects in our embedded applications spend a large percentage of their lifetimes in the heap beyond their last-use.
Relationship: entailment
Domain: Hardware
Sentence 1: By retaining the topics from Google News and not just the articles, we are able to incor­porate current trending topics as well as de.ne a separate set of long-term topics we wish to track.
Sentence 2: there are 2,000 popular long-term news topics, such as the Syrian Revolution and North Korea, that we always search for regardless of if they make the front page of Google News.
Relationship: entailment
Domain: Hardware
Sentence 1: Thus, for any 0 = z = Dij , the skew is within the bound Bz =[tskew z (sr,sl),tskewz (sr,sl)].
Sentence 2: if |evi |=0, the 0 minimum and the maximum skew are given as tskew (sr,sl)=K and t 0 sr,sl)=K.
Relationship: entailment
Domain: Hardware
Sentence 1: http://dx.doi.org/10.1145/2668332.2668377 Chih-Hang Wang Department of Computer Science National Tsing Hua University superwch7805@gmail.com Po-Yu Chen Department of Computer Science National Tsing Hua University chenpy@mx.nthu.edu.tw built on different platforms.
Sentence 2: web services pro­vide network functions through web standards and protocols (e.g., HTTP, XML and SOAP).
Relationship: entailment
Domain: Hardware
Sentence 1: The C Block in Figure 4 imposes routing constraints that must be satisfied in order to deliver input signals I0 and I1 in the correct order to the SD-MUX inputs.
Sentence 2: i0 and I1 must be routed on routing segments w6 and w7; the order is irrelevant, i.e., either I0 can be routed on w6 and I1 on w7, or vice-versa; similarly, I0 and I1 must be routed on w4 and w5 as well.
Relationship: entailment
Domain: Hardware
Sentence 1: 3.4 Veri.cation procedure Although to describe the feasible set one just needs to solve prob­lem 5 for different values of ., the question of an ef.cient veri.ca­tion procedure still holds.
Sentence 2: we wish to .nd out how many instances need to be veri.ed to guarantee that a new instance will in fact meet the required speci.cations.
Relationship: entailment
Domain: Hardware
Sentence 1: Once d is found from (4), the updated response x~ can be easily calculated from (5): x~ = x + d. In most practical cases, a power grid network is often updated with local changes and, hence, the problem unknown d in (4) is sparse.
Sentence 2: the incremental change of the power grid voltage is almost zero at many internal nodes, as will be demonstrated by the numerical examples in Section 5.
Relationship: entailment
Domain: Hardware
Sentence 1: * Denote by Wu,i the upper bound after iteration i and * ** W the lower bound after iteration i. W = W and l,i u,0 u W * = W * .
Sentence 2: instead of querying the oracle with .,wequery l,0 l it with (a series of di.erent) .. which forms a geometric sequence converging to ..set .
Relationship: entailment
Domain: Hardware
Sentence 1: ACKNOWLEDGMENTS The authors would like to thank Udeepta Bordoloi, Michael Chu, and Patricia Harell from AMD Stream Computing Group, Santa Clara, for their support and detailed technical discussions leading into implementing these algorithms, as well as for providing the GPU hardware used in this study.
Sentence 2: discussions with Dr. Bordoloi was a basis to much of the analysis of our results.
Relationship: entailment
Domain: Hardware
Sentence 1: 5 is known to have a hysteresis property, meaning that a stronger-than-normal input voltage is needed in order to flip the output state (which has a larger inertia).
Sentence 2: we need a much higher voltage to change the output of a ST inverter from 1 to 0 , and much lower voltage to change the output from 0 to 1 .
Relationship: entailment
Domain: Hardware
Sentence 1: Previ­ous work has shown that coscheduling to the maximum supported level on modest (up to 8 way) SMT is in general best, [33] and [23] showed that cases of negative symbiosis are rare and actually required (to exhibit it in that study) crippling the base SMT con.g- FRACi = (19 - pi) / (19 - pj ) uration to arti.cially create bottlenecks on system resources.
Sentence 2: j=1 There are two related factors in a schedule that can boost utiliza-jobs get scheduled for a fraction of available cycles tion.
Relationship: entailment
Domain: Hardware
Sentence 1: Another advantage of the LHPN model over our previ­ously published HPN models is that the systems can be mod­eled more compactly which results in smaller state spaces.
Sentence 2: the HPN diode models presented in [18] re­quire over 2000 zones to represent the state space while the LHPN models require 132 zones or less.
Relationship: entailment
Domain: Hardware
Sentence 1: The ratio of phrase-aligned snippet Ours Random Boundary Alignment 75% 15% We also tested the computational complexity of our algorithm, with Pentium IV 1.8G running Windows XP, the snippet extraction process can be completed in less than 5% of the time-length of the music.
Sentence 2: for a music clip of 4-minute long, the processing time is about 10 seconds.
Relationship: entailment
Domain: Hardware
Sentence 1: In other words, awareness of micro-level errors (i.e., bit errors) is translated into policies that have macro-level impacts in terms of execution failure, performance, energy consumption, and QoS.
Sentence 2: we explore a Drop and Forward Recovery (DFR) mechanism (shown in Figure 3(c)) that drops a current encoding frame and moves forward to the next frame once an error is de­tected in a mobile video encoding system.
Relationship: entailment
Domain: Hardware
Sentence 1: As can be observed from Table 3(a), when resolution is poor (= 4), a rule with high GAVR and low yield loss confounds the EM formulation of [4].
Sentence 2: the formulation of [4] only identifies the rule most responsible for yield loss when its corresponding .k is extremely high (i.e., out of 18 table entries, 17 are .k=1.00 and the reaming case is .k=0.90).
Relationship: entailment
Domain: Hardware
Sentence 1: Since each SRAM cell has cross­coupled inverters, each inverter is used to charge the gate of the PFET device of the other by storing the proper value to the cell before transitioning to recovery mode.
Sentence 2: a 1 needs to be written for recovery of the left PFET devices of the cells (CL) while a 0 needs to be written for recovery of the right PFET devices of the cells (CR).
Relationship: entailment
Domain: Hardware
Sentence 1: 4.3 Auditory Scene Categorization To better evaluate the performance of the auditory scene categoriza­tion with co-clustering algorithm, we first do some minor correc­tions in the key element spotting based on the available ground truth information.
Sentence 2: we delete the noise from the key element list of A2, and add the pure gunshot to the list of A4.
Relationship: entailment
Domain: Hardware
Sentence 1: A larger but more aggressive multipumped design can also ex­ploit banking to reduce the number of cycles required to perform reads: each bank can perform two unique reads, and all banks can operate in parallel; when reads are completed, one pair of writes can be performed across all banks each cycle until all writes are performed.
Sentence 2: the block RAMs are read like a banked memory and are written like a replicated memory.
Relationship: entailment
Domain: Hardware
Sentence 1: The origin of this near can­cellation and doubling stems from the observation that, after some algebra, the L contribution for these modes may be written as L y z ( d 0 e x ' f x y z dx dy dz (25) whereas the P contribution becomes: P w2 t n f 0 y z dy dz (26) y z both with the same integrand function f x y z .
Sentence 2: the P matrix elements, divided by w2, are the collapsed version of the L ones, up to a sign according to whether the element corre­spond to two modes traveling in the same or opposite sense along the z axis.
Relationship: entailment
Domain: Hardware
Sentence 1: coef(C) mod coef(N) = 0, where upper_bound(N), lower_bound(N) are bounds of the loop of iterator N; coef(N) is the coefficient of iterator N in index expression; mod is the modulo operation.
Sentence 2: all moving iterators should have coefficients that evenly divide each other and for any two iterators the greatest coefficient should not be less than the value on which the loop with iterator with lesser coefficient can change the value of the index expression.
Relationship: entailment
Domain: Hardware
Sentence 1: gorithms and the selection of the components and architecture fault model.
Sentence 2: the designers focus on the control al­ *This research was supported in part by the Marco/Gigascale Systems Re- Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 04) 1530-1591/04 $20.00 &#38;#169; 2004 IEEE Figure 1.
Relationship: entailment
Domain: Hardware
Sentence 1: In addition, in the ULV regimes, the small (10-20mV) VT difference out of layout modifications can become sufficient to control driving strength due to the exponential impact of VT on transistor drain current.
Sentence 2: the proposed method can benefit driving a large tors, exhibits similar delay-energy performance when LVT tran­ sistors works at Vdd=0.35-0.38V.
Relationship: entailment
Domain: Hardware
Sentence 1: However, additional measures are re­quired when the MTCMOS methodology is applied in the design of sequential logic circuits.
Sentence 2: storage el­ements such as latches and .ip-.ops present state-retention problems during the stand-by mode since the .oating vir­tual ground disconnects the storage nodes from the power supply leading to the corruption of the stored data.
Relationship: entailment
Domain: Hardware
Sentence 1: The timing diagram of the above step 3) can be drawn as Figure2.
Sentence 2: update-DR is active on the dotted line, and Cature-DR is active on the bold line, thus 2.5 TCKs is required from Update-DR to Capture-DR. it can be seen that it takes 2.5 TCKs from the application of interconnect test patterns through output BSCs to the observation of test responses on input BSCs.
Relationship: entailment
Domain: Hardware
Sentence 1: Comparing the solutions produced by the various multi-resource partitioning algorithms we can see that there is a considerable amount of variability on the quality of the .nal solutions.
Sentence 2: in the absence of V -cycle re.nement, the quality of the solutions pro­duced by MP are signi.cantly worse than those produced by ei­ther MC or MPMC.
Relationship: entailment
Domain: Hardware
Sentence 1: 4 Prototype Performance Aside from the delay circuit s ability to span the required delay range, we also require that it be able to pass the high data-rate signals (up to 6.4Gbps) with minimal distortion.
Sentence 2: since the delay circuit contains 7 active components, it might be susceptible to jitter (and other noise effects) which accumulate as the signal passes through all the 7 stages.
Relationship: entailment