sadat2307/MSciNLI huggingface dataset:
Domain: Hardware
Sentence 1: Mok and Chen introduced this idea in [1, 4] and showed promising results for MPEG-streams where the average load for a sequence of I-, P-and B-frames is much smaller than in a stream that consists only of large I-frames, which is assumed by a context-blind worst-case response time analysis [1].
Sentence 2: the periodic sequence of types of activating events was supposed to be completely known.
Relationship: contrasting
Domain: Hardware
Sentence 1: A lot of papers have been published to deal with repeater insertion in a more complicated environment such as: simultaneous area and power optimization [4], delay and bandwidth constraints [5], throughput­centric optimization [6], and throughput-per-energy-area optimization [7].
Sentence 2: all of these papers essentially employed the same conventional global interconnect design methodology, and completely ignored the inductance effects, treating the interconnect as an RC delay line.
Relationship: contrasting
Domain: Hardware
Sentence 1: In the ideal case, if the CPU requests are distributed evenly across the run time, it will take 40,000 cycles to pro­duce 16 requests, which is within the worse-case capability of the 16-deep debt queue.
Sentence 2: the results show that the bandwidth requirement of the CPU trace varies signi.­cantly over time; as such, the optimal debt queue depth also varies with time.
Relationship: contrasting
Domain: Hardware
Sentence 1: MODELING &#38; ANALYSIS OF CNT INTERCONNECTS The first reported work comparing CNT interconnects to copper [7] highlighted the imminent thermal/reliability problems of minimum dimension Cu interconnects, vias and contacts and examined the advantages as well as the process technology requirements for CNT bundle based vias.
Sentence 2: several studies comparing only the performance of CNT interconnects to that of Cu have been contradictory.
Relationship: contrasting
Domain: Hardware
Sentence 1: O0 and hence an accurate support function representation is maintained.
Sentence 2: in the linear subsystem of DI-PLL, the formula form of the support function representation is di.cult to use since the reachable state space computation contains the intersection operation between the linear and nonlinear reachable state space and vectors in Ot can only be mapped to Ot-.t.
Relationship: contrasting
Domain: Hardware
Sentence 1: In these proposed memory systems, data is distributed by hard­  Figure 1: NAND .ash Figure 2: MRAM ware between NVM and CM to achieve a balanced read/write performance.
Sentence 2: these approaches are typically de­signed for speci.c memory levels (e.g., cache and main mem­ory) and do not e.ectively leverage applications data access characteristics.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this case, the signal vld_1 is already available in the RTL.
Sentence 2: it is possible that there is no RTL signal corresponding to the signal driving the input of register vld_2: always@(posedge clock) begin case (select): 4 b0000 : vld_2 <= in1; 4 b0001 : vld_2 <= in2; .... end One option for the tool is to duplicate the logic driving the input of register vld_2 but that is clearly sub-optimal from a power savings stand-point.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, under such a construction, if we use a hierarchy of two levels of the muldirect encoding for a total number of colors K, such that the number of Boolean variables used for the first-level muldirect encoding is n, then the number of Boolean variables used for the second-level muldirect encoding will be .K/n.. More recently, Kwon and Klieber [22] have proposed a SAT encoding for CSPs that, based on our terminology, can be classified as direct-i+direct for a 2-level version, where i is the number of Boolean variables used in the top encoding, and could include more than two levels, but with the direct encod­ing used at each level.
Sentence 2: our method for hierarchical composition of encodings is completely general, and allows for any simple encoding to be used at any level of a hierarchi­cal encoding.
Relationship: contrasting
Domain: Hardware
Sentence 1: In this paper we use Multicore Association Communi­cations API (MCAPI) for the logical communication, and show how it simpli.es FPGA designs and even porting ap­plications between on-chip FPGA processors and .xed IP­blocks.
Sentence 2: raising the abstraction introduces also per­formance overheads that we consider as well in a case study.
Relationship: contrasting
Domain: Hardware
Sentence 1: Although routing rules are in­cluded to reduce the likelihood of equivalent faults, faults F10 and F11 both have critical area and have the response 11111111.
Sentence 2: since F11 has nearly 25 times as much critical area as fault F10, the response 11111111 can most Also, a strategy to reduce the likelihood of equivalent faults is described.
Relationship: contrasting
Domain: Hardware
Sentence 1: of Computer Science and Engineering Seoul National University University of California, San Diego Seoul, Korea 9500 Gilman Dr., La Jolla, CA 92093 {chunmok, jihong}@davinci.snu.ac.kr dhkim@ucsd.edu ABSTRACT In shared bus-based multiprocessor system-on-a-chips (MP-SoCs), snoop-based schemes are widely used to maintain cache coherency.
Sentence 2: many of broadcasts are useless because remote caches seldom have the matching blocks and their tag lookups do not supply data.
Relationship: contrasting
Domain: Hardware
Sentence 1: In reality, it is impossible to fully simulate a perfect AWGN source since it would require infinite bandwidth.
Sentence 2: if some finite noise bandwidth is assumed and the duration of calculation time step for both circuit simulators is less than the half of maximum switching period of the PWL noise voltage sources, each data point can be regarded as a set of discrete data points sampled from a continuous AWGN function at each time step for complete recovery by Nyquist rate.
Relationship: contrasting
Domain: Hardware
Sentence 1: As shown in Figure 14, when m is doubled, throughputs increase by roughly a factor of 1.2 for non-pipelined designs and by roughly a factor of 2 for pipelined designs.
Sentence 2: despite having smaller area and critical path delays, smaller fields make it more probable that the set of coefficients corresponding to the set of received encoded messages are linearly dependent, preventing recovery of the original messages [23].
Relationship: contrasting
Domain: Hardware
Sentence 1: For the transaction on inp for instance, a C++ source code fragment is: execute_vc() { if (data present on port I) then { read data value; do processing;  } // else do nothing return; } In this fragment, the code related to port_O and port_P has been left out.
Sentence 2: the code implements the specification of the inp interface in Figure 6.
Relationship: contrasting
Domain: Hardware
Sentence 1: In functional veri.cation of such a system, we used a processor bus functional model (BFM) to combine native software execution with a cycle-accurate interconnect simu­lator and an HDL simulator.
Sentence 2: we found that signif­icant extensions need to be made to the conventional BFM methodology in order to capture various data-race cases in simulation, which eventually happen in modern multi­processor systems.
Relationship: contrasting
Domain: Hardware
Sentence 1: Joint Sizing and Adaptive Independent Gate Control for FinFET Circuits Operating in Multiple Voltage Regimes Using the Logical Effort Method Xue Lin, Yanzhi Wang, and Massoud Pedram University of Southern California Los Angeles, CA, 90089, US {xuelin, yanzhiwa, pedram}@usc.edu ABSTRACT voltagescalability.
Sentence 2: another important operation to minimize the energy-... point of FinFET circuits, the optimal FinFET has been proposed as an alternative for bulk CMOS in current and future technology nodes due to more effective channel delay product, typically lies in near-threshold regime.
Relationship: contrasting
Domain: Hardware
Sentence 1: In the worst-case, when one four GNRs in both the p-type and n-type GNRFETs are N=9 GNRs, the delay increases by 6 77%.
Sentence 2: there is a 12 30% decrease in the delay of an inverter when one four GNRs in both the p-type and n-type GNRFETs are N=18 GNRs.
Relationship: contrasting
Domain: Hardware
Sentence 1: China chuzhufei@mail.nbu.edu.cn, {xiayinshui, wanglunyao}@nbu.edu.cn ABSTRACT To implement multi-voltage technique in SoC designs, level shifters (LSs) are essential modules which translate signals among dif­ferent voltage domains.
Sentence 2: inserting LSs requires non­negligible area and timing overhead.
Relationship: contrasting
Domain: Hardware
Sentence 1: Finally, to satisfy the requirement that the integral (sum) of the co-occurrence distribution is equal to one, the co-occurrence matrix p(S, E) is nor­malized across the whole matrix, that is: p(s ,e ) = occr / m n occr (15) i j ij ..i=1 j=1 ij 3.2.2 BIC-based Cluster Number Estimation In the above co-clustering algorithm, the row cluster number k and the column cluster number l are assumed to be known.
Sentence 2: in an unsupervised approach, it's not possible to specify the cluster numbers beforehand.
Relationship: contrasting
Domain: Hardware
Sentence 1: The failure rate for a given system can be modelled as a function of the failure rates of its individual subsystems, suggestions being present in the MIL-HDBC-217 document, which is publicly available [44].
Sentence 2: this document has been strongly criticized for its failure rate estimations based on the Arrhenius model, which relates the failure rate to the operating temperature: E .=Ke KBT (1) - where K is a constant, KB is Boltzmann s constant, T is the absolute temperature and E is the activation energy for the process [18].
Relationship: contrasting
Domain: Hardware
Sentence 1: Even though the measure cannot be used for an absolute evaluation of a system s throughput (as heuristic cost depends on the net numbers and their detailed topology structure), the .gure shows that relative correlations are well mapped, so that the cost can be used inside an optimization engine.
Sentence 2: wirelength and throughput are very loosely correlated, if at all (see result section for numerical examples).
Relationship: contrasting
Domain: Hardware
Sentence 1: In our simu­lations, the design corner can be setup as the follows: Based on the impacts of the major sources of device variations, the worst corner happens when L, Vth and t show positive deviations from their nominal values and W shows a negative deviation from its nominal value.
Sentence 2: the worst corner of A is dif.cult to determined: a large MTJ surface raises the magnitude of MTJ switching threshold current while causes the reduction of MTJ resistance, which can improve the NMOS transistor driving ability, and vice versa.
Relationship: contrasting
Domain: Hardware
Sentence 1: Coordinated, Distributed, Formal Energy Management of Chip Multiprocessors Philo Juang Qiang Wu pjuang@princeton.edu jqwu@cs.princeton.edu Li-Shiuan Peh Margaret Martonosi Douglas W. Clark peh@ee.princeton.edu mrm@ee.princeton.edu doug@cs.princeton.edu Departments of Electrical Engineering and Computer Science Princeton University Princeton, NJ  ABSTRACT Designers are moving toward chip-multiprocessors (CMPs) to lever­age application parallelism for higher performance while keeping design complexity under control.
Sentence 2: to date, no power man­agement techniques have been proposed for coordinated power con­trol of multiple processor cores.
Relationship: contrasting
Domain: Hardware
Sentence 1: The DME, and many other algo­rithms, require that the CDN s abstract topology to be generated initially by another algorithm, such as Mean and Median Method (MMM), Geometric Matching Algorithm (GMA) or Balanced Bipartition (BB) [2].
Sentence 2: the topology governs the pairing between nodes, impacts the location of the Steiner nodes, and as a result, influences the total wire length.
Relationship: contrasting
Domain: Hardware
Sentence 1: With the algorithm described in [19], unca­pacitated Minimum Cost Flow Problems can be solved in time O(|V (G)|(log |V (G)|)(|E(G)| + |V (G)| log(|V (G)|))) = O((n 2 k + nk2 + (n + k)2 log(n + k)) log(n + k)) which is O(n 2 log2 n) if k is .xed.
Sentence 2: for VLSI instances with several millions of circuits, the algorithm is much too slow, since its running time grows more than quadratically with n. There are other algorithms that exploit the special structure of the Transportation Problem.
Relationship: contrasting
Domain: Hardware
Sentence 1: This interleaving results in a row-con.ict for each access and there­fore signi.cantly increases the latency experienced by each thread.
Sentence 2: with a Marking-Cap of 5, PAR-BS would service A s 5 15For example, STFM delays requests from threads that are estimated to be slowed down much less than others.
Relationship: contrasting
Domain: Hardware
Sentence 1: Furthermore, most of these existing techniques either provide a unidirectional design space [1, 17] leading to accumulative error or have a narrow and restrictive design space [16, 20].
Sentence 2: the inexact logic minimization techniques provided a richer design space, but overlooked the inherent compensa­tion ability that could be gleaned from these logic trans­formations and relied on absolute or worst case statistical measures as the guiding principles that more often than not lead to pessimistic under-designed inexact systems.
Relationship: contrasting
Domain: Hardware
Sentence 1: Of course, this is not an exact indication of where dyfl instructions could be removed by static analyses e.g., an instruction may be redundant in one runbut notin another,oritmaybe that code motion can changea polarized dyfl instruction into a non-polarized one, or vice-versa.
Sentence 2: a high fraction of polarized instructions would intuitively suggest that further static analyses might be straightforward.
Relationship: contrasting
Domain: Hardware
Sentence 1: Figure 1: Schematic structure of a GRLS system Using frequency dividers is a common industry practice for generating clock frequencies due to the simplicity of the problem of clock division.
Sentence 2: we innovate over ex­isting approaches by building our local Clock Generation Units (CGUs) as clock division blocks supporting multiple input clocks to give more .exibility in the choice of the lo­cal frequencies and ultimately achieve higher energy savings through DDVFS.
Relationship: contrasting
Domain: Hardware
Sentence 1: 1, s, s3,..., we should use exponential functions with base s. Adding the constraints that p(G) s are integers, we are able to obtain the exact solution using the MLP model.
Sentence 2: if there is no such relation between cell sizes, we can solve the MLP model with the p(G) s being real variables, and use the smallest available cell size that is larger than the calculated value as the cell size assignment.
Relationship: contrasting
Domain: Hardware
Sentence 1: As we have previously shown, DVFS has a useful property: B1T = B1E1/0.95 B1E2 = B1T · 0.85 Note that above BIPS predictions do not account for transi­tion overheads.
Sentence 2: at design time, the cost of switching among modes is well known as well as the BIPS and Power Matrix scalings.
Relationship: contrasting
Domain: Hardware
Sentence 1: Extensive validation experiments were performed for several combinations of network topology, routing algorithm, buffer size, mean message length, and flit size.
Sentence 2: for the sake of specific illustration and brevity, we provide results for the following cases only: Average Message Latency (Cycle)  400 100 0 0 0.005 0.01 0.015 0.02 0.025 Traffic Generation Rate (Message/Node/Cycle) Traffic Generation Rate (Message/Node/Cycle)  Figure 3.
Relationship: contrasting
Domain: Hardware
Sentence 1: of Cores 50K 100K 200K 400K 100 200 400 600 0.4 0.5 0.6 0.7 4 8 16 WS 0.8% 3.0% 3.6% 5.1% 4.2% 3.0% 1.3% -2.5% 2.5% 3.0% 2.1% 1.3% 3.0% 3.9% 3.5% PE 21.3% 33.5% 18.5% 10.5% 25.7% 33.5% 35.4% 19.5% 30.3% 33.5% 30.7% 31.8% 33.5% 32.4% 35.8% rank [6] to improve DRAM performance and save power.Sub-rank compensates for the reduced bank level parallelismcaused by bank partitioning; it also reduces the number of devices involved in a single memory access, thereby reducing DRAM power consumption.
Sentence 2: sub-rank reduces memory peak bandwidth and increases data transferring time, its improvement of performance is slight and sometimes it even hurts system performance.
Relationship: contrasting
Domain: Hardware
Sentence 1: A few recent proposals have explored bypass algorithms for LLCs.3 One proposal [6] remembers the tag of a by­passed block (if the incoming block is bypassed) or the vic­timized block (if the incoming block is not bypassed) to observe the next use to the bypassed/allocated block and the saved/victimized block, and accordingly learns whether bypassing is a good decision.
Sentence 2: this proposal ran­domly selects incoming blocks for bypassing based on a by­pass probability, which is adjusted dynamically based on the e.ectiveness of bypassing.
Relationship: contrasting
Domain: Hardware
Sentence 1: To address variability, these efforts so far have focused 1 0.9 on statistical analysis [14] and techniques to address systematic variation through measure, model, mitigate approach (DFM) [15].
Sentence 2: 0.8 in order to address variability directly, new system and circuit techniques must be devised that can sense variability and 0.7 dynamically critical circuit parameters to adapt the behavior of the circuit.
Relationship: contrasting
Domain: Hardware
Sentence 1: Therefore, we expect that the proposed charge recycling technique, which simply changes V0 from VDD to VDD/2, does not change the positive peak value of the GB.
Sentence 2: as seen from (17), the leakage power consumption has increased by a factor of (1+1/2n) compared to the conventional power gating the negative peak value of the GB, and the GB settling time bothmethod.
Relationship: contrasting
Domain: Hardware
Sentence 1: L. 2.3 ChainMap Duplication The exclusivity constraint of chains is de.ned as the re­quirement that a chain net be a single-source, single-sink relationship between adjacent LEs.
Sentence 2: when the network is viewed as a set of LUTs, as in SIS internal representation, it means that a node t can have at most two chain outputs u and v. there are constraints on which LUTs can be part of the same LE, assuming that an architecture allows a full K-LUT function on the chain.
Relationship: contrasting
Domain: Hardware
Sentence 1: Over a traditional physi­cal register .le mechanism, we need only: (i) the ability to update the register rename map when the result of an in­struction is one of these selected values, (ii) additional state bits to the instruction window entries to keep track of the selected values, and (iii) suitable modi.cations of the con­trol logic.
Sentence 2: in addition to the normal broadcast for instruction wakeup, a re-broadcast is still necessary when a physical register is remapped.
Relationship: contrasting
Domain: Hardware
Sentence 1: The conclusion in [3] indicates that for ReRAM with a large SET current (> 500µA), strong CFs exist in the cell and thus only HRS retention failure is observed in these cells because the ruptured CFs are more like to be reconstructed.
Sentence 2: for ReRAM with a small SET current (< 100µA) [19], only LRS retention failure is ob­served, because weakly formed CFs are more likely to be ruptured due to the random degeneration of oxygen vacan­cies in the CFs.
Relationship: contrasting
Domain: Hardware
Sentence 1: For example, integer adder, which occupies most of the circuit area of an integer FU, comprises 4k - 6k transistors [10], [22].
Sentence 2: an FP multiplier and an FP adder, which require fast transistors as integer FUs, comprise over 200 k transistors[22], which is several tens times of that in integer adders.
Relationship: contrasting
Domain: Hardware
Sentence 1: For this purpose, a drop threshold is selected so that if aX,i or ßX,j is smaller than this threshold, it is deemed to have small value and will be placed into a drop candidate pool to be pruned from the variation vector representation.
Sentence 2: dropping aX,i or ßX,j with small magnitude is the same as applying truncation to the variation vector.
Relationship: contrasting
Domain: Hardware
Sentence 1: Cost Analysis Under the same redundancy ratio, the proposed repair scheme has higher hardware cost when compared to other TSV repair solutions, i.e., our redundancy scheme requires three 1-to-3 muxes for each TSV, while signal-shifting and signal-switching have one 1-to-3 mux for each signal TSV.
Sentence 2: the extra cost is justi.ed by the corresponding signi.cant TSV yield improvement.
Relationship: contrasting
Domain: Hardware
Sentence 1: b) Updating TInterference due to interference in DRAM bank: Because thread C has issued a request, other threads with requests to the same bank have to wait for R to be serviced and therefore expe­rience an increased stall-time.
Sentence 2: increasing TInterference of these threads by the service latency of R is too simplistic as it ignores memory-level parallelism [8, 2] of threads.
Relationship: contrasting
Domain: Hardware
Sentence 1: The most direct method is by the addition of extra tran­sistors inside the memory element such that the input stage is slowed in order to filter fast transient pulses.
Sentence 2: such a scheme is infeasible since, in addition to the large overheads incurred in power and delay, it increases the effective device area susceptible to direct particle strikes thereby making the flipflops more vulnerable to SETs.
Relationship: contrasting
Domain: Hardware
Sentence 1: Traditionally, the time-domain DTS s should perform two-point calibration to have their accuracy approaching to that of the voltage-domain ATS s. For reducing calibration time and cost, a dual-DLL based DTS [8] was recently proposed to adopt one-point calibration that can still removes the effects of process variations.
Sentence 2: this design has some shortcomings.
Relationship: contrasting
Domain: Hardware
Sentence 1: When a set of .oorplanning instances falls within the operating range of PATOMA, resulting solutions are slightly better than Capo s and are found several times faster.
Sentence 2: pATOMA seems to trade robustness for runtime and in some cases generates solutions with remarkably long wires for example, Figure 4 shows PATOMA solutions for the IBM-HB+10 benchmark and the cal040 design, which have 1.4x and 9.7x worse HPWL, respectively, compared to the best seen solutions.
Relationship: contrasting
Domain: Hardware
Sentence 1: In [15] the BDD-based over-approximation is used to guide the SAT solver with the in­formation obtained by the over-approximation, whereas in [7] and [22] the reachable state space is over-approximated by a computed invariant.
Sentence 2: in contrast to these methods we iteratively strengthen a computed invariant by using an over-approximated set of counterexamples.
Relationship: contrasting
Domain: Hardware
Sentence 1: 3.3 The Manufacturing Barrier: Integrating TFET and FinFET Technologies TFET technology is at an exploratory stage and it is too premature to analyze it from the yield and cost perspec­tives.
Sentence 2: from an integration perspective, TFET and FinFETdevicescanbefabricatedonasinglechipina mono­lithic fashion using a silicon substrate.
Relationship: contrasting
Domain: Hardware
Sentence 1: However, for smaller L2 cache sizes, the SINIC network buffers over.owintomain memory.Theoverheadofthe resulting DRAM­to-cache buffer copies causes signi.cant bandwidth degradation (a 40% reduction down to 6 Gbps with a 1 MB cache).
Sentence 2: without the zero-copyoptimization,V-SINIC provides similar performance characteristics, though at a slightly reduced performance level due to additional overheads in the device driver.3 the zero­copyoptimization eliminates thebuffer copyentirely, making per­formance insensitive to the cache size, and allowing the system to saturate the network in every con.guration.
Relationship: contrasting