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psub Sx,Sy,Dz | 111110********** 10100001xxyyzzzz | Sx - Sy -> Dz | Subtracts the contents of the Sy operand from the Sx operand and stores the result in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are updated. | void psub (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_minus_dc_bit.c"
} |
dct pdmsb Sy,Dz | 111110********** 1011111000yyzzzz | If DC = 1: Sy data MSB position -> MSW of Dz, clear LSW of Dz Else: nop | Conditionally finds the first position to change in the lineup of Sy operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated. | void pdmsb_sy_dct (void) {
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
psts MACL,Dz | 111110********** 110111010000zzzz | MACL -> Dz | Stores the contents of the MACL register in the Dz operand. The DC, N, Z, V, and GT bits of the DSR register are not updated. | void psts_macl (void) { DSP_REG[ex2_dz_no] = MACL; if (ex2_dz_no == 0) { A0G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A0G |= MASKFFFFFF00; } else if (ex2_dz_no == 1) { A1G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A1G |= MASKFFFFFF00; } } |
dct psts MACH,Dz | 111110********** 110011100000zzzz | If DC = 1: MACH -> Dz Else: nop | Conditionally stores the contents of the MACH register in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits of the DSR register are not updated. | void psts_mach_dct (void) { if (DC == 1) { DSP_REG[ex2_dz_no] = MACH; if (ex2_dz_no == 0) { A0G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A0G |= MASKFFFFFF00; } else if (ex2_dz_no == 1) { A1G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A1G |= MASKFFFFFF00; } } } |
dct psts MACL,Dz | 111110********** 110111100000zzzz | If DC = 1: MACL -> Dz Else: nop | Conditionally stores the contents of the MACL register in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits of the DSR register are not updated. | void psts_macl_dct (void) { if (DC == 1) { DSP_REG[ex2_dz_no] = MACL; if (ex2_dz_no == 0) { A0G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A0G |= MASKFFFFFF00; } else if (ex2_dz_no == 1) { A1G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A1G |= MASKFFFFFF00; } } } |
dcf psts MACH,Dz | 111110********** 110011110000zzzz | If DC = 0: MACH -> Dz Else: nop | Conditionally stores the contents of the MACH register in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits of the DSR register are not updated. | void psts_mach_dcf (void) { if (DC == 0) { DSP_REG[ex2_dz_no] = MACH; if (ex2_dz_no == 0) { A0G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A0G |= MASKFFFFFF00; } else if (ex2_dz_no == 1) { A1G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A1G |= MASKFFFFFF00; } } } |
dcf psts MACL,Dz | 111110********** 110111110000zzzz | If DC = 0: MACL -> Dz Else: nop | Conditionally stores the contents of the MACL register in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits of the DSR register are not updated. | void psts_macl_dcf (void) { if (DC == 0) { DSP_REG[ex2_dz_no] = MACL; if (ex2_dz_no == 0) { A0G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A0G |= MASKFFFFFF00; } else if (ex2_dz_no == 1) { A1G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A1G |= MASKFFFFFF00; } } } |
rotcl Rn | 0100nnnn00100100 | T << Rn << T | Rotates the contents of general register Rn one bit to the left through the T bit, and stores the result in Rn. The bit rotated out of the operand is transferred to the T bit. | void ROTCL (int n) {
long temp;
if ((R[n] & 0x80000000) == 0)
temp = 0;
else
temp = 1;
R[n] <<= 1;
if (T == 1)
R[n] |= 0x00000001;
else
R[n] &= 0xFFFFFFFE;
if (temp == 1)
T = 1;
else
T = 0;
PC += 2;
} |
rotcr Rn | 0100nnnn00100101 | T >> Rn >> T | Rotates the contents of general register Rn one bit to the right through the T bit, and stores the result in Rn. The bit rotated out of the operand is transferred to the T bit. | void ROTCR (int n) {
long temp;
if ((R[n] & 0x00000001) == 0)
temp = 0;
else
temp = 1;
R[n] >>= 1;
if (T == 1)
R[n] |= 0x80000000;
else
R[n] &= 0x7FFFFFFF;
if (temp == 1)
T = 1;
else
T = 0;
PC += 2;
} |
rotl Rn | 0100nnnn00000100 | T << Rn << MSB | Rotates the contents of general register Rn one bit to the left, and stores the result in Rn. The bit rotated out of the operand is transferred to the T bit. | void ROTL (int n) {
if ((R[n] & 0x80000000) == 0)
T = 0;
else
T = 1;
R[n] <<= 1;
if (T == 1)
R[n] |= 0x00000001;
else
R[n] &= 0xFFFFFFFE;
PC += 2;
} |
rotr Rn | 0100nnnn00000101 | LSB >> Rn >> T | Rotates the contents of general register Rn one bit to the right, and stores the result in Rn. The bit rotated out of the operand is transferred to the T bit. | void ROTR (int n) {
if ((R[n] & 0x00000001) == 0)
T = 0;
else
T = 1;
R[n] >>= 1;
if (T == 1)
R[n] |= 0x80000000;
else
R[n] &= 0x7FFFFFFF;
PC += 2;
} |
shad Rm,Rn | 0100nnnnmmmm1100 | If Rm >= 0: Rn << Rm -> Rn
If Rm < 0: Rn >> |Rm| -> [MSB -> Rn] | Arithmetically shifts the contents of general register Rn. General register Rm specifies the shift direction and the number of bits to be shifted. | void SHAD (int m, int n) {
int sgn = R[m] & 0x80000000;
if (sgn == 0)
R[n] <<= (R[m] & 0x1F);
else if ((R[m] & 0x1F) == 0)
{
if ((R[n] & 0x80000000) == 0)
R[n] = 0;
else
R[n] = 0xFFFFFFFF;
}
else
R[n] = (long)R[n] >> ((~R[m] & 0x1F) + 1);
PC += 2;
} |
shal Rn | 0100nnnn00100000 | T << Rn << 0 | Arithmetically shifts the contents of general register Rn one bit to the left and stores the result in Rn. The bit shifted out of the operand is transferred to the T bit. | void SHAL (int n) {
if ((R[n] & 0x80000000) == 0)
T = 0;
else
T = 1;
R[n] <<= 1;
PC += 2;
} |
shar Rn | 0100nnnn00100001 | MSB >> Rn >> T | Arithmetically shifts the contents of general register Rn one bit to the right and stores the result in Rn. The bit shifted out of the operand is transferred to the T bit. | void SHAR (int n) {
long temp;
if ((R[n] & 0x00000001) == 0)
T = 0;
else
T = 1;
if ((R[n] & 0x80000000) == 0)
temp = 0;
else
temp = 1;
R[n] >>= 1;
if (temp == 1)
R[n] |= 0x80000000;
else
R[n] &= 0x7FFFFFFF;
PC += 2;
} |
dcf pdmsb Sx,Dz | 111110********** 10011111xx00zzzz | If DC = 0: Sx data MSB position -> MSW of Dz, clear LSW of Dz Else: nop | Conditionally finds the first position to change in the lineup of Sx operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pdmsb_sx_dcf (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
pshl #imm,Dz | 111110********** 00010iiiiiiizzzz | If imm >= 0: Dz << imm -> Dz, clear LSW of Dz
If imm < 0: Dz >> imm, clear LSW of Dz | Logically shifts the top word contents of the Dz operand, stores the result in
the top word of the Dz operand, and clears the bottom word of the Dz operand
with zeros. When Dz is a register that has guard bits, the guard bits
are also zeroed. The amount of the shift is specified by the immediate value.
When the shift amount is positive, it shifts left. When the shift amount is
negative, it shifts right.
The DC bit of the DSR register is updated according to the specifications for
the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pshl_imm (void)
{
unsigned short tmp_imm;
DSP_ALU_SRC1 = DSP_REG[ex2_dz_no];
switch (ex2_dz_no)
{
case 0x0:
DSP_ALU_SRC1G = A0G;
break;
case 0x1:
DSP_ALU_SRC1G = A1G;
break;
default:
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
}
tmp_imm = ((EX2_LW >> 4) & MASK0000003F); // bit[9:4]
if ((tmp_imm & MASK0020) == 0)
{
// Left Shift 0 <= cnt < 16
char cnt = tmp_imm & MASK001F;
if (cnt > 16)
{
printf ("\nPSHL Dz,#Imm,Dz Error! #Imm=%6X exceed range.\n", tmp_imm);
exit ();
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW << cnt--;
carry_bit = ((DSP_ALU_SRC1_HW << cnt) & MASK8000) == 0x8000;
}
else
{
// Right Shift 0 < cnt <= 16
char cnt = (~tmp_imm & MASK001F) + 1;
if (cnt > 16)
{
printf ("\nPSHL Dz,#Imm,Dz Error! #Imm=%6X exceed range.\n", tmp_imm);
exit ();
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW >> cnt--;
carry_bit = ((DSP_ALU_SRC1_HW >> cnt) & MASK0001) == 0x1;
}
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no == 1)
A1G = 0x0;
negative_bit = DSP_ALU_DST_MSB;
zero_bit = DSP_ALU_DST_HW == 0;
overflow_bit = 0x0;
#include "shift_dc_bit.c"
} |
shld Rm,Rn | 0100nnnnmmmm1101 | If Rm >= 0: Rn << Rm -> Rn
If Rm < 0: Rn >> |Rm| -> [0 -> Rn] | Logically shifts the contents of general register Rn. General register Rm specifies the shift direction and the number of bits to be shifted. Rn register contents are shifted to the left if the Rm register value is positive, and to the right if negative. In a shift to the right, 0s are added at the upper end. The number of bits to be shifted is specified by the lower 5 bits (bits 4 to 0) of the Rm register. If the value is negative (MSB = 1), the Rm register is represented as a two's complement. The left shift range is 0 to 31, and the right shift range, 1 to 32. | void SHLD (int m, int n) {
int sgn = R[m] & 0x80000000;
if (sgn == 0)
R[n] <<= (R[m] & 0x1F);
else if ((R[m] & 0x1F) == 0)
R[n] = 0;
else
R[n] = (unsigned)R[n] >> ((~R[m] & 0x1F) + 1);
PC += 2;
} |
sts A0,Rn | 0000nnnn01111010 | A0 -> Rn | Stores DSP register A0 in the destination. | void STSA0 (int n) {
R[n] = A0;
PC += 2;
} |
sts.l A0,@-Rn | 0100nnnn01100010 | Rn-4 -> Rn, A0 -> (Rn) | Stores DSP register A0 in the destination. | void STSMA0 (int n) {
R[n] -= 4;
Write_32 (R[n], A0);
PC += 2;
} |
sts X0,Rn | 0000nnnn10001010 | X0 -> Rn | Stores DSP register X0 in the destination. | void STSX0 (int n) {
R[n] = X0;
PC += 2;
} |
sts.l X0,@-Rn | 0100nnnn10000010 | Rn-4 -> Rn, X0 -> (Rn) | Stores DSP register X0 in the destination. | void STSMX0 (int n) {
R[n] -= 4;
Write_32 (R[n], X0);
PC += 2;
} |
sts X1,Rn | 0000nnnn10011010 | X1 -> Rn | Stores DSP register X1 in the destination. | void STSX1 (int n) {
R[n] = X1;
PC += 2;
} |
sts.l X1,@-Rn | 0100nnnn10010010 | Rn-4 -> Rn, X1 -> (Rn) | Stores DSP register X1 in the destination. | void STSMX1 (int n) {
R[n] -= 4;
Write_32 (R[n], X1);
PC += 2;
} |
sts Y0,Rn | 0000nnnn10101010 | Y0 -> Rn | Stores DSP register Y0 in the destination. | void STSY0 (int n) {
R[n] = Y0;
PC += 2;
} |
stc SPC,Rn | 0000nnnn01000010 | SPC -> Rn | Stores control register SPC in the destination. | void STCSPC (int n) { R[n] = SPC; PC += 2; } |
stc.l SPC,@-Rn | 0100nnnn01000011 | Rn-4 -> Rn, SPC -> (Rn) | Stores control register SPC in the destination. | void STCMSPC (int n) { R[n] -= 4; Write_32 (R[n], SPC); PC += 2; } |
stc DBR,Rn | 0000nnnn11111010 | DBR -> Rn | Stores control register DBR in the destination. | void STCDBR (int n) { R[n] = DBR; PC += 2; } |
stc.l DBR,@-Rn | 0100nnnn11110010 | Rn-4 -> Rn, DBR -> (Rn) | Stores control register DBR in the destination. | void STCMDBR (int n) { R[n] -= 4; Write_32 (R[n], DBR); PC += 2; } |
stc Rm_BANK,Rn | 0000nnnn1mmm0010 | Rm_BANK -> Rn (m = 0-7) | Stores a banked general register in the destination. Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0. | void STCRm_BANK (int n) { R[n] = Rm_BANK; PC += 2; } |
stc.l Rm_BANK,@-Rn | 0100nnnn1mmm0011 | Rn-4 -> Rn, Rm_BANK -> (Rn) (m = 0-7) | Stores a banked general register in the destination. Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0. | void STCMRm_BANK (int n) { R[n] -= 4; Write_32 (R[n], Rm_BANK); PC += 2; } |
sts MACH,Rn | 0000nnnn00001010 | MACH -> Rn | Stores system register MACH in the destination. | void STSMACH (int n) { R[n] = MACH; #if SH1 if ((R[n] & 0x00000200) == 0) R[n] &= 0x000003FF; else R[n] |= 0xFFFFFC00; #endif PC += 2; } |
pneg Sy,Dz | 111110********** 1110100100yyzzzz | 0 - Sy -> Dz | Reverses the sign. Subtracts the Sy operand from 0 and stores the result in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pneg_sy (void) {
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_minus_dc_bit.c"
} |
movml.l @R15+,Rn | 0100nnnn11110101 | (R15) -> R0, R15+4 -> R15 (R15) -> R1, R15+4 -> R15 ... (R15) -> Rn | Transfers a source operand to a destination. This instruction performs transfer between a number of general registers (R0 to Rn/Rm) not exceeding the specified register number and memory with the contents of R15 as its address. If R15 is specified, PR is transferred instead of R15. That is, when nnnn(mmmm) = 1111 is specified, R0 to R14 and PR are the general registers subject to transfer. | void MOVLPML (int n) { for (int i = 0; i <= n; i++) { if (i == 15) PR = Read_32 (R[15]); else R[i] = Read_32 (R[15]); R[15] += 4; } PC += 2; } |
movmu.l Rm,@-R15 | 0100mmmm11110000 | R15-4 -> R15, PR -> (R15) R15-4 -> R15, R14 -> (R15) ... R15-4 -> R15, Rm -> (R15) | Transfers a source operand to a destination. This instruction performs transfer between a number of general registers (Rn/Rm to R14, PR) not lower than the specified register number and memory with the contents of R15 as its address. If R15 is specified, PR is transferred instead of R15. | void MOVLMMU (int m) { Write_32 (R[15] - 4, PR); R[15] -= 4; for (int i = 14; i >= m; i--) { Write_32 (R[15] - 4, R[i]); R[15] -= 4; } PC += 2; } |
movmu.l @R15+,Rn | 0100nnnn11110100 | (R15) -> Rn, R15+4 -> R15 (R15) -> Rn+1, R15+4 -> R15 ... (R15) -> R14, R15+4 -> R15 (R15) -> PR | Transfers a source operand to a destination. This instruction performs transfer between a number of general registers (Rn/Rm to R14, PR) not lower than the specified register number and memory with the contents of R15 as its address. If R15 is specified, PR is transferred instead of R15. | void MOVLPMU (int n) { for (int i = n; i <= 14; i++) { R[i] = Read_32 (R[15]); R[15] += 4; } PR = Read_32 (R[15]); R[15] += 4; PC += 2; } |
movrt Rn | 0000nnnn00111001 | ~T -> Rn | Reverses the T bit and then stores the resulting value in general register Rn. The value of Rn is 0 when T = 1 and 1 when T = 0. | void MOVRT (int n) { if (T == 1) R[n] = 0x00000000; else R[n] = 0x00000001; PC += 2; } |
movt Rn | 0000nnnn00101001 | T -> Rn | Stores the T bit in general register Rn. The value of Rn is 1 when T = 1 and 0 when T = 0. | void MOVT (int n) { if (T == 1) R[n] = 0x00000001; else R[n] = 0x00000000; PC += 2; } |
nott | 0000000001101000 | ~T -> T | Inverts the T bit, then stores the resulting value in the T bit. | void NOTT (void) { if (T == 1) T = 0; else T = 1; PC += 2; } |
swap.b Rm,Rn | 0110nnnnmmmm1000 | Rm -> swap lower 2 bytes -> Rn | Swaps the upper and lower parts of the contents of general register Rm and stores the result in Rn. The 8 bits from bit 15 to bit 8 of Rm are swapped with the 8 bits from bit 7 to bit 0. The upper 16 bits of Rm are transferred directly to the upper 16 bits of Rn. | void SWAPB (int m, int n) { unsigned long temp0, temp1; temp0 = R[m] & 0xFFFF0000; temp1 = (R[m] & 0x000000FF) << 8; R[n] = (R[m] & 0x0000FF00) >> 8; R[n] = R[n] | temp1 | temp0; PC += 2; } |
dct pdec Sx,Dz | 111110********** 10001010xx00zzzz | If DC = 1: MSW of Sx - 1 -> MSW of DZ, clear LSW of Dz
Else: nop | Conditionally subtracts 1 from the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated. | void pdec_sx_dct (void) {
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
movx.w @Ax+Ix,Dx | 111100A*D*0*11** | (Ax) -> MSW of Dx, 0 -> LSW of Dx, Ax+Ix -> Ax | Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for X memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros. | MSW of Dx = (Ax); LSW of Dx = 0; Ax = Ax + Ix |
movx.w Da,@Ax | 111100A*D*1*01** | MSW of Da -> (Ax) | Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for X memory. The source word data is the top word of the register. | (Ax) = MSW of Da |
movx.w Da,@Ax+ | 111100A*D*1*10** | MSW of Da -> (Ax), Ax+2 -> Ax | Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for X memory. The source word data is the top word of the register. | (Ax) = MSW of Da; Ax = Ax + 2 |
movx.w Da,@Ax+Ix | 111100A*D*1*11** | MSW of Da -> (Ax), Ax+Ix -> Ax | Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for X memory. The source word data is the top word of the register. | (Ax) = MSW of Da; Ax = Ax + Ix |
nopy | 111100*0*0*0**00 | No Operation | No access operation for Y memory. | No operation performed. |
dcf pdmsb Sy,Dz | 111110********** 1011111100yyzzzz | If DC = 0: Sy data MSB position -> MSW of Dz, clear LSW of Dz Else: nop | Conditionally finds the first position to change in the lineup of Sy operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pdmsb_sy_dcf (void) {
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
pcmp Sx,Sy | 111110********** 10000100xxyy0000 | Sx - Sy | Subtracts the contents of the Sy operand from the Sx operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pcmp (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_minus_dc_bit.c"
} |
plds Dz,MACL | 111110********** 111111010000zzzz | Dz -> MACL | Stores the Dz operand in the MACL register. The DC, N, Z, V, and GT bits of the DSR register are not updated. | void plds_macl (void) { MACL = DSP_REG[ex2_dz_no]; } |
mov.w R0,@(disp,GBR) | 11000001dddddddd | R0 -> (disp*2 + GBR) | Transfers the source operand to the destination. The 8-bit displacement is multiplied by two after zero-extension, enabling a range up to +510 bytes to be specified. | void MOVWSG (int d) { unsigned int disp = (0x000000FF & d); Write_16 (GBR + (disp << 1), R[0]); PC += 2; } |
mov.l R0,@(disp,GBR) | 11000010dddddddd | R0 -> (disp*4 + GBR) | Transfers the source operand to the destination. The 8-bit displacement is multiplied by four after zero-extension, enabling a range up to +1020 bytes to be specified. | void MOVLSG (int d) { unsigned int disp = (0x000000FF & (long)d); Write_32 (GBR + (disp << 2), R[0]); PC += 2; } |
movco.l R0,@Rn | 0000nnnn01110011 | LDST -> T If (T == 1): R0 -> Rn 0 -> LDST | MOVCO is used in combination with MOVLI to realize an atomic read-modify-write operation in a single processor. This instruction copies the value of the LDST flag to the T bit. When the T bit is set to 1, the value of R0 is stored at the address in Rm. If the T bit is cleared to 0, the value is not stored at the address in Rm. Finally, the LDST flag is cleared to 0. Since the LDST flag is cleared by an instruction or exception, storage by the MOVCO instruction only proceeds when no interrupt or exception has occurred between the execution of the MOVLI and MOVCO instructions. | void MOVCO (int n) { T = LDST; if (T == 1) Write_32 (R[n], R[0]); LDST = 0; PC += 2 } |
movli.l @Rm,R0 | 0000mmmm01100011 | 1 -> LDST (Rm) -> R0 When interrupt/exception occured: 0 -> LDST | MOVLI is used in combination with MOVCO to realize an atomic read-modify-write operation in a single processor. This instruction sets the LDST flag to 1 and reads the four bytes of data indicated by Rm into R0. If, however, an interrupt or exception occurs, LDST is cleared to 0. Storage by the MOVCO instruction only proceeds when the instruction is executed after the LDST bit has been set by the MOVLI instruction and not cleared by an interrupt or other exception. When LDST has been cleared to 0, the MOVCO instruction clears the T bit and does not proceed with storage. | void MOVLINK (int m) { LDST = 1; R[0] = Read_32 (R[m]); PC += 2 } |
movua.l @Rm,R0 | 0100mmmm10101001 | (Rm) -> R0 Load non-boundary alignment data | Loads the longword of data from the effective address indicated by the contents of Rm in memory to R0. The address is not restricted to longword boundaries address (4n). This instruction allows loading from non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3). Data address error exceptions do not occur when access is to non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3). | void MOVUAL (int m) { Read_Unaligned_32 (R0, R[m]); PC += 2; } |
movua.l @Rm+,R0 | 0100mmmm11101001 | (Rm) -> R0, Rm + 4 -> Rm Load non-boundary alignment data | Loads the longword of data from the effective address indicated by the contents of Rm in memory to R0. The address is not restricted to longword boundaries address (4n). This instruction allows loading from non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3). Data address error exceptions do not occur when access is to non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3). | void MOVUALP (int m) { Read_Unaligned_32 (R0,R[m]); if (m != 0) R[m] += 4; PC += 2; } |
movml.l Rm,@-R15 | 0100mmmm11110001 | R15-4 -> R15, Rm -> (R15) R15-4 -> R15, Rm-1 -> (R15) ... ... R15 - 4 -> R15, R0 -> (R15) Note: When Rm = R15, read Rm as PR | Transfers a source operand to a destination. This instruction performs transfer between a number of general registers (R0 to Rn/Rm) not exceeding the specified register number and memory with the contents of R15 as its address. If R15 is specified, PR is transferred instead of R15. That is, when nnnn(mmmm) = 1111 is specified, R0 to R14 and PR are the general registers subject to transfer. | void MOVLMML (int m) { for (int i = m; i >= 0; i--) { if (i == 15) Write_32 (R[15] - 4, PR); else Write_32 (R[15] - 4, R[i]); R[15] -= 4; } PC += 2; } |
movs.l @-As,Ds | 111101AADDDD0010 | As-4 -> As, (As) -> Ds | Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits. | null |
movs.l @As,Ds | 111101AADDDD0110 | (As) -> Ds | Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits. | null |
movs.l @As+,Ds | 111101AADDDD1010 | (As) -> Ds, As+4 -> As | Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits. | null |
movs.l @As+Is,Ds | 111101AADDDD1110 | (As) -> Ds, As+Is -> As | Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits. | null |
movs.l Ds,@-As | 111101AADDDD0011 | As-4 -> As, Ds -> (As) | Transfers the source operand data to the destination. The transferred data is a longword.
Note: When one of the guard bit registers A0G and A1G is the source operand it is sign extended and stored as a word. | null |
movs.l Ds,@As | 111101AADDDD0111 | Ds -> (As) | Transfers the source operand data to the destination. The transferred data is a longword.
Note: When one of the guard bit registers A0G and A1G is the source operand it is sign extended and stored as a word. | null |
movs.l Ds,@As+ | 111101AADDDD1011 | Ds -> (As), As+4 -> As | Transfers the source operand data to the destination. The transferred data is a longword.
Note: When one of the guard bit registers A0G and A1G is the source operand it is sign extended and stored as a word. | null |
fcmp/eq FRm,FRn | 1111nnnnmmmm0100 | If FRn = FRm: 1 -> T Else: 0 -> T | Arithmetically compares the two single-precision floating-point numbers in FRn and FRm, and stores 1 in the T bit if they are equal, or 0 otherwise. | void FCMP_EQ (int m, int n) { PC += 2; clear_cause (); if (fcmp_chk_single (m, n) == INVALID) fcmp_invalid (); else if (fcmp_chk_single (m, n) == EQ) T = 1; else T = 0; } |
fcmp/gt FRm,FRn | 1111nnnnmmmm0101 | If FRn > FRm: 1 -> T Else: 0 -> T | Arithmetically compares the two single-precision floating-point numbers in FRn and FRm, and stores 1 in the T bit if FRn > FRm, or 0 otherwise. | void FCMP_GT (int m, int n) { PC += 2; clear_cause (); if (fcmp_chk_single (m, n) == INVALID || fcmp_chk_single (m, n) == UO) fcmp_invalid (); else if (fcmp_chk_single (m, n) == GT) T = 1; else T = 0; } |
float FPUL,FRn | 1111nnnn00101101 | (float)FPUL -> FRn | Taking the contents of FPUL as a 32-bit integer, converts this integer to a single-precision floating-point number and stores the result in FRn. | void FLOAT_single (int n) { union { double d; int l[2]; } tmp; PC += 2; clear_cause (); FR[n] = FPUL; // convert from integer to float tmp.d = FPUL; if (tmp.l[1] & 0x1FFFFFFF) inexact(); } |
ftrc FRm,FPUL | 1111mmmm00111101 | (long)FRm -> FPUL | Converts the single-precision floating-point number in FRm to a 32-bit integer, and stores the result in FPUL. | void FTRC_single (int m) { PC += 2; clear_cause (); switch (ftrc_single_type_of (m)) { case NORM: FPUL = FR[m]; // Convert float to integer break; case PINF: ftrc_invalid (0, &FPUL); break; case NINF: ftrc_invalid (1, &FPUL); break; } } |
fipr FVm,FVn | 1111nnmm11101101 | inner_product (FVm, FVn) -> FR[n+3] | Calculates the inner products of the 4-dimensional single-precision floating-point vector indicated by FVn and FVm, and stores the results in FR[n + 3]. | void FIPR (int m, int n) { if (FPSCR_PR == 0) { PC += 2; clear_cause (); fipr (m,n); } else undefined_operation (); } |
fmov.s FRm,@Rn | 1111nnnnmmmm1010 | FRm -> (Rn) | Transfers FRm contents to memory at address indicated by Rn. | void FMOV_STORE (int m, int n) {
Write_32 (R[n], FR[m]);
PC += 2;
} |
fmov.s @Rm+,FRn | 1111nnnnmmmm1001 | (Rm) -> FRn, Rm+4 -> Rm | Transfers contents of memory at address indicated by Rm to FRn, and adds 4 to Rm. | void FMOV_RESTORE (int m, int n) {
FR[n] = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
fmov.s FRm,@-Rn | 1111nnnnmmmm1011 | Rn-4 -> Rn, FRm -> (Rn) | Subtracts 4 from Rn, and transfers FRm contents to memory at address indicated by resulting Rn value. | void FMOV_SAVE (int m, int n) {
Write_32 (R[n] - 4, FR[m]);
R[n] -= 4;
PC += 2;
} |
fmov.s @(R0,Rm),FRn | 1111nnnnmmmm0110 | (R0 + Rm) -> FRn | Transfers contents of memory at address indicated by (R0 + Rm) to FRn. | void FMOV_INDEX_LOAD (int m, int n) {
FR[n] = Read_32 (R[0] + R[m]);
PC += 2;
} |
fmov.s FRm,@(R0,Rn) | 1111nnnnmmmm0111 | FRm -> (R0 + Rn) | Transfers FRm contents to memory at address indicated by (R0 + Rn). | void FMOV_INDEX_STORE (int m, int n) {
Write_32 (R[0] + R[n], FR[m]);
PC += 2;
} |
fmov.s @(disp12,Rm),FRn | 0011nnnnmmmm0001 0111dddddddddddd | (disp*4 + Rm) -> FRn | Transfers memory contents at the address indicated by (disp + Rn) to FRn. | void FMOV_INDEX_DISP12_LOAD (int m, int n, int d) {
long disp = (0x00000FFF & (long)d);
FR[n] = Read_32 (R[m] + (disp << 2));
PC += 4;
} |
fmov.s FRm,@(disp12,Rn) | 0011nnnnmmmm0001 0011dddddddddddd | FRm -> (disp*4 + Rn) | Transfers FRm contents to memory at the address indicated by (disp + Rn). | void FMOV_INDEX_DISP12_STORE (int m, int n, int d) {
long disp = (0x00000FFF & (long)d);
Write_32 (R[n] + (disp << 2), FR[m]);
PC += 4;
} |
prnd Sx,Dz | 111110********** 10011000xx00zzzz | Sx + 0x00008000 -> Dz, clear LSW of Dz | Does rounding. Adds the immediate data 0x00008000 to the contents of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of Dz with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void prnd_sx (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST = (DSP_ALU_SRC1 + DSP_ALU_SRC2) & MASKFFFF0000;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_plus_dc_bit.c"
} |
fdiv FRm,FRn | 1111nnnnmmmm0011 | FRn / FRm -> FRn | Arithmetically divides the single-precision floating-point number in FRn by the single-precision floating-point number in FRm, and stores the result in FRn. | void FDIV (int m, int n) {
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case PINF:
case NINF:
inf (n, sign_of (m) ^ sign_of (n));
break;
case PZERO:
case NZERO:
zero (n, sign_of (m) ^ sign_of (n));
break;
case DENORM:
set_E ();
break;
default:
normal_fdiv_single (m, n);
break;
}
break;
case PZERO:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
case PINF:
case NINF:
break;
default:
dz (n, sign_of (m) ^ sign_of (n));
break;
}
break;
case NZERO:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
case PINF:
inf (n, 1);
break;
case NINF:
inf (n, 0);
break;
default:
dz (FR[n], sign_of (m) ^ sign_of (n));
break;
}
break;
case DENORM:
set_E ();
break;
case PINF:
case NINF:
switch (data_type_of (n))
{
case DENORM:
set_E ();
break;
case PINF:
case NINF:
invalid (n);
break;
default:
zero (n, sign_of (m) ^ sign_of (n));
break;
}
break;
}
}
void normal_fdiv_single (int m, int n) {
union
{
float f;
int l;
} dstf, tmpf;
union
{
double d;
int l[2];
} tmpd;
tmpf.f = FR[n]; // save destination value
dstf.f /= FR[m]; // round toward nearest or even
tmpd.d = dstf.f; // convert single to double
tmpd.d *= FR[m];
if (tmpf.f != tmpd.d)
set_I ();
if (tmpf.f < tmpd.d && FPSCR_RM == 1)
dstf.l -= 1; // round toward zero
check_single_exception (&FR[n], dstf.f);
} |
padd Sx,Sy,Du
pmuls Se,Sf,Dg | 111110********** 0111eeffxxyygguu | Sx + Sy -> Du
MSW of Se * MSW of Sf -> Dg | Adds the contents of the Sx and Sy operands and stores the result in the Du operand. The contents of the top word of the Se and Sf operands are multiplied as signed and the result stored in the Dg operand. These two processes are executed simultaneously in parallel. | void padd_pmuls (void)
{
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
switch (EX2_DU)
{
case 0x0:
X0 = DSP_ALU_DST;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
break;
case 0x1:
Y0 = DSP_ALU_DST;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
break;
case 0x2:
A0 = DSP_ALU_DST;
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
break;
case 0x3:
A1 = DSP_ALU_DST;
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
break;
}
#include "fixed_pt_plus_dc_bit.c"
} |
pinc Sy,Dz | 111110********** 1011100100yyzzzz | MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz | Adds 1 to the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pinc_sy (void) {
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
#include "integer_unconditional_update.c"
#include "integer_plus_dc_bit.c"
} |
pneg Sx,Dz | 111110********** 11001001xx00zzzz | 0 - Sx -> Dz | Reverses the sign. Subtracts the Sx operand from 0 and stores the result in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pneg_sx (void) {
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC2 = X0;
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
break;
case 0x1:
DSP_ALU_SRC2 = X1;
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
break;
case 0x2:
DSP_ALU_SRC2 = A0;
DSP_ALU_SRC2G = A0G;
break;
case 0x3:
DSP_ALU_SRC2 = A1;
DSP_ALU_SRC2G = A1G;
break;
}
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_minus_dc_bit.c"
} |
pdmsb Sy,Dz | 111110********** 1011110100yyzzzz | Sy data MSB position -> MSW of Dz, clear LSW of Dz | Finds the first position to change in the lineup of Sy operand bits and stores the bit position in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pdmsb_sy (void) {
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
overflow_bit = 0;
#include "integer_unconditional_update.c"
#include "integer_plus_dc_bit.c"
} |
lds Rm,MACL | 0100mmmm00011010 | Rm -> MACL | Stores the source operand into the system register MACL. | void LDSMACL (int m) {
MACL = R[m];
PC += 2;
} |
lds.l @Rm+,MACL | 0100mmmm00010110 | (Rm) -> MACL, Rm+4 -> Rm | Stores the source operand into the system register MACL. | void LDSMMACL (int m) {
MACL = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
lds Rm,PR | 0100mmmm00101010 | Rm -> PR | Stores the source operand into the system register PR. | void LDSPR (int m) {
PR = R[m];
PC += 2;
} |
lds.l @Rm+,PR | 0100mmmm00100110 | (Rm) -> PR, Rm+4 -> Rm | Stores the source operand into the system register PR. | void LDSMPR (int m) {
PR = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
lds Rm,DSR | 0100mmmm01101010 | Rm -> DSR | Stores the source operand into the DSP register DSR. | void LDSDSR (int m) {
DSR = R[m] & 0x0000000F;
PC += 2;
} |
lds.l @Rm+,DSR | 0100mmmm01100110 | (Rm) -> DSR, Rm+4 -> Rm | Stores the source operand into the DSP register DSR. | void LDSMDSR (int m) {
DSR = Read_32 (R[m]) & 0x0000000F;
R[m] += 4;
PC += 2;
} |
lds Rm,A0 | 0100mmmm01110110 | Rm -> A0 | Stores the source operand into the DSP register A0. The MSB of the data is copied into A0G. | void LDSA0 (int m) {
A0 = R[m];
if ((A0 & 0x80000000) == 0)
A0G = 0x00;
else
A0G = 0xFF;
PC+=2;
} |
fdiv DRm,DRn | 1111nnn0mmm00011 | DRn / DRm -> DRn | Arithmetically divides the double-precision floating-point number in DRn by the double-precision floating-point number in DRm, and stores the result in DRn. | void FDIV (int m, int n) {
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case PINF:
case NINF:
inf (n, sign_of (m) ^ sign_of (n));
break;
case PZERO:
case NZERO:
zero (n, sign_of (m) ^ sign_of (n));
break;
case DENORM:
set_E ();
break;
default:
normal_fdiv_double (m, n);
break;
}
break;
case PZERO:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
case PINF:
case NINF:
break;
default:
dz (n, sign_of (m) ^ sign_of (n));
break;
}
break;
case NZERO:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
case PINF:
inf (n, 1);
break;
case NINF:
inf (n, 0);
break;
default:
dz (FR[n], sign_of (m) ^ sign_of (n));
break;
}
break;
case DENORM:
set_E ();
break;
case PINF:
case NINF:
switch (data_type_of (n))
{
case DENORM:
set_E ();
break;
case PINF:
case NINF:
invalid (n);
break;
default:
zero (n, sign_of (m) ^ sign_of (n));
break;
}
break;
}
}
void normal_fdiv_double (int m, int n) {
union
{
double d;
int l[2];
} dstd, tmpd;
union
{
int double x;
int l[4];
} tmpx;
tmpd.d = DR[n >> 1]; // save destination value
dstd.d /= DR[m >> 1]; // round toward nearest or even
tmpx.x = dstd.d; // convert double to int double
tmpx.x *= DR[m >> 1];
if (tmpd.d != tmpx.x)
set_I ();
if (tmpd.d < tmpx.x && FPSCR_RM == 1)
{
dstd.l[1] -= 1; // round toward zero
if (dstd.l[1] == 0xFFFFFFFF)
dstd.l[0] -= 1;
}
check_double_exception (&DR[n >> 1], dstd.d);
} |
dcf pclr Dz | 111110********** 100011110000zzzz | If DC = 0: 0x00000000 -> Dz
Else: nop | Conditionally clears the Dz operand. The instruction is executed when the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pclr_dcf (void)
{
if (DC == 0)
DSP_REG[ex2_dz_no] = 0x0;
} |
psha Sx,Sy,Dz | 111110********** 10010001xxyyzzzz | If Sy >= 0: Sx << Sy -> Dz
If Sy < 0: Sx >> Sy -> Dz | Arithmetically shifts the contents of the Sx or Dz operand and stores the result in the Dz operand. The amount of the shift is specified by the Sy operand. When the shift amount is positive, it shifts left. When the shift amount is negative, it shifts right. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void psha (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0 & MASK007F0000;
break;
case 0x1:
DSP_ALU_SRC2 = Y1 & MASK007F0000;
break;
case 0x2:
DSP_ALU_SRC2 = M0 & MASK007F0000;
break;
case 0x3:
DSP_ALU_SRC2 = M1 & MASK007F0000;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
if ((DSP_ALU_SRC2_HW & MASK0040) == 0)
{
// Left Shift 0 <= cnt <= 32
char cnt = DSP_ALU_SRC2_HW & MASK003F;
if (cnt > 32)
{
printf ("\nPSHA Sz,Sy,Dz Error! Shift %2X exceed range.\n", cnt);
exit ();
}
DSP_ALU_DST = DSP_ALU_SRC1 << cnt;
DSP_ALU_DSTG = ((DSP_ALU_SRC1G << cnt)
| (DSP_ALU_SRC1 >> (32 - cnt))) & MASK000000FF;
carry_bit = ((DSP_ALU_DSTG & MASK00000001) == 0x1);
}
else
{
// Right Shift 0 < cnt <= 32
char cnt = (~DSP_ALU_SRC2_HW & MASK003F) + 1;
if (cnt > 32)
{
printf ("\nPSHA Sz,Sy,Dz Error! shift -%2X exceed range.\n", cnt);
exit ();
}
if ((cnt > 8) && DSP_ALU_SRC1G_BIT7)
{
// MSB copy
DSP_ALU_DST = (DSP_ALU_SRC1 >> 8) | (DSP_ALU_SRC1G << (32 - 8));
DSP_ALU_DST = (long)DSP_ALU_DST >> (cnt - 8);
}
else
DSP_ALU_DST = (DSP_ALU_SRC1 >> cnt) | (DSP_ALU_SRC1G << (32 - cnt));
DSP_ALU_DSTG_LSB8 = (char)DSP_ALU_SRC1G_LSB8 >> cnt--;
carry_bit = ((DSP_ALU_SRC1 >> cnt) & MASK00000001) == 0x1;
}
overflow_bit = ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "shift_dc_bit.c"
} |
ftrc DRm,FPUL | 1111mmm000111101 | (long)DRm -> FPUL | Converts the double-precision floating-point number in DRm to a 32-bit integer, and stores the result in FPUL. | void FTRC_double (int m) {
PC += 2;
clear_cause ();
switch (ftrc_double_type_of (m))
{
case NORM:
FPUL = DR[m >> 1]; // Convert double to integer
break;
case PINF:
ftrc_invalid (0, &FPUL);
break;
case NINF:
ftrc_invalid (1, &FPUL);
break;
}
}
int ftrc_double_type_of (int m) {
if (sign_of (m) == 0)
{
if (FR_HEX[m] > 0x7FF00000
|| (FR_HEX[m] == 0x7FF00000 && FR_HEX[m+1] != 0x00000000))
return NINF; // NaN
else if (DR_HEX[m >> 1] >= POS_INT_DOUBLE_RANGE)
return PINF; // out of range, +INF
else
return NORM; // +0, +NORM
}
else
{
if ((DR_HEX[m >> 1] & 0x7FFFFFFFFFFFFFFF) >= NEG_INT_DOUBLE_RANGE)
return NINF; // out of range, +INF, NaN
else
return NORM; // -0, -NORM
}
}
void ftrc_invalid (int sign, int* result) {
set_V ();
if ((FPSCR & ENABLE_V) == 0)
{
if (sign == 0)
*result = 0x7FFFFFFF;
else
*result = 0x80000000;
}
else
fpu_exception_trap ();
} |
dct pdmsb Sx,Dz | 111110********** 10011110xx00zzzz | If DC = 1: Sx data MSB position -> MSW of Dz, clear LSW of Dz
Else: nop | Conditionally finds the first position to change in the lineup of Sx operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated. | void pdmsb_sx_dct (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
pdec Sx,Dz | 111110********** 10001001xx00zzzz | MSW of Sx - 1 -> MSW of Dz, clear LSW of Dz | Subtracts 1 from the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pdec_sx (void) {
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
#include "integer_unconditional_update.c"
#include "integer_minus_dc_bit.c"
} |
dcf pneg Sx,Dz | 111110********** 11001011xx00zzzz | If DC = 0: 0 - Sx -> Dz Else: nop | Conditionally reverses the sign. The instruction is executed if the DC bit is set to 0. Subtracts the Sx operand from 0 and stores the result in the Dz operand. The DC, N, Z, V, and GT bits are not updated. | void pneg_sx_dcf (void) {
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC2 = X0;
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
break;
case 0x1:
DSP_ALU_SRC2 = X1;
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
break;
case 0x2:
DSP_ALU_SRC2 = A0;
DSP_ALU_SRC2G = A0G;
break;
case 0x3:
DSP_ALU_SRC2 = A1;
DSP_ALU_SRC2G = A1G;
break;
}
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 0)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
dcf pdec Sx,Dz | 111110********** 10001011xx00zzzz | If DC = 0: MSW of Sx - 1 -> MSW of DZ, clear LSW of Dz Else: nop | Conditionally subtracts 1 from the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pdec_sx_dcf (void) {
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
movs.w Ds,@-As | 111101AADDDD0001 | As-2 -> As, MSW of Ds -> (As) | Transfers the source operand data to the destination. The transferred data is a word, the top word of the register is stored as the word data. | null |
movs.w Ds,@As | 111101AADDDD0101 | MSW of Ds -> (As) | Transfers the source operand data to the destination. The transferred data is a word, the top word of the register is stored as the word data. | null |
movs.w Ds,@As+ | 111101AADDDD1001 | MSW of Ds -> (As), As+2 -> As | Transfers the source operand data to the destination. The transferred data is a word, the top word of the register is stored as the word data. | null |
movs.w Ds,@As+Is | 111101AADDDD1101 | MSW of DS -> (As), As+Is -> As | Transfers the source operand data to the destination. The transferred data is a word, the top word of the register is stored as the word data. | null |
movs.l @-As,Ds | 111101AADDDD0010 | As-4 -> As, (As) -> Ds | Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits. | null |