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fmov.d XDm,@Rn | 1111nnnnmmm11010 | XDm -> (Rn) | Transfers contents of memory at address indicated by (R0 + Rm) to XDn. | void FMOV_STORE_XD (int m, int n) {
Write_64 (R[n], XD[m >> 1]);
PC += 2;
} |
fmov.d @Rm+,DRn | 1111nnn0mmmm1001 | (Rm) -> DRn, Rm + 8 -> Rm | Transfers contents of memory at address indicated by Rm to DRn, and adds 8 to Rm. | void FMOV_RESTORE_DR (int m, int n) {
DR[n >> 1] = Read_64 (R[m]);
R[m] += 8;
PC += 2;
} |
fmov.d @Rm+,XDn | 1111nnn1mmmm1001 | (Rm) -> XDn, Rm+8 -> Rm | Transfers contents of memory at address indicated by Rm to XDn, and adds 8 to Rm. | void FMOV_RESTORE_XD (int m, int n) {
XD[n >> 1] = Read_64 (R[m]);
R[m] += 8;
PC += 2;
} |
fmov.d DRm,@-Rn | 1111nnnnmmm01011 | Rn-8 -> Rn, DRm -> (Rn) | Subtracts 8 from Rn, and transfers DRm contents to memory at address indicated by resulting Rn value. | void FMOV_SAVE_DR (int m, int n) {
Write_64 (R[n] - 8, DR[m >> 1]);
R[n] -= 8;
PC += 2;
} |
fmov.d XDm,@-Rn | 1111nnnnmmm11011 | Rn-8 -> Rn, (Rn) -> XDm | Subtracts 8 from Rn, and transfers XDm contents to memory at address indicated by resulting Rn value. | void FMOV_SAVE_XD (int m, int n) {
Write_64 (R[n] - 8, XD[m >> 1]);
R[n] -= 8;
PC += 2;
} |
fmov.d @(R0,Rm),DRn | 1111nnn0mmmm0110 | (R0 + Rm) -> DRn | Transfers contents of memory at address indicated by (R0 + Rm) to DRn. | void FMOV_INDEX_LOAD_DR (int m, int n) {
DR[n >> 1] = Read_64 (R[0] + R[m]);
PC += 2;
} |
fmov.d @(R0,Rm),XDn | 1111nnn1mmmm0110 | (R0 + Rm) -> XDn | Transfers contents of memory at address indicated by (R0 + Rm) to XDn. | void FMOV_INDEX_LOAD_XD (int m, int n) {
XD[n >> 1] = Read_64 (R[0] + R[m]);
PC += 2;
} |
lds Rm,FPUL | 0100mmmm01011010 | Rm -> FPUL | Loads the source operand into FPU system register FPUL. | void LDSFPUL (int m) {
FPUL = R[m];
PC += 2;
} |
sts FPUL,Rn | 0000nnnn01011010 | FPUL -> Rn | Stores FPU system register FPUL in the destination. | void STSFPUL (int n) {
R[n] = FPUL;
PC += 2;
} |
lds.l @Rm+,FPUL | 0100mmmm01010110 | (Rm) -> FPUL, Rm+4 -> Rm | null | void LDSMFPUL (int m) {
FPUL = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
sts.l FPUL,@-Rn | 0100nnnn01010010 | Rn-4 -> Rn, FPUL -> (Rn) | Stores FPU system register FPUL in the destination. | void STSMFPUL (int n) {
R[n] -= 4;
Write_32 (R[n], FPUL);
PC += 2;
} |
frchg | 1111101111111101 | If FPSCR.PR = 0: ~FPSCR.FR -> FPSCR.FR
Else: Undefined Operation | Inverts the FR bit in floating-point register FPSCR. | void FRCHG (void) {
if (FPSCR_PR == 0)
{
FPSCR ^= 0x00200000; // toggle bit 21
PC += 2;
}
else
undefined_operation ();
} |
dcf pcopy Sy,Dz | 111110********** 1111101100yyzzzz | If DC = 0: Sy -> Dz Else: nop | Conditionally stores the Sy operand in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pcopy_sy_dcf (void) {
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 0)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
mov.b @Rm,Rn | 0110nnnnmmmm0000 | (Rm) -> sign extension -> Rn | Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register. | void MOVBL (int m, int n) {
R[n] = Read_8 (R[m]);
if ((R[n] & 0x80) == 0)
R[n] &= 0x000000FF;
else
R[n] |= 0xFFFFFF00;
PC += 2;
} |
mov.w @Rm,Rn | 0110nnnnmmmm0001 | (Rm) -> sign extension -> Rn | Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register. | void MOVWL (int m, int n) {
R[n] = Read_16 (R[m]);
if ((R[n] & 0x8000) == 0)
R[n] &= 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
PC += 2;
} |
mov.l @Rm,Rn | 0110nnnnmmmm0010 | (Rm) -> Rn | Transfers the source operand to the destination. | void MOVLL (int m, int n) {
R[n] = Read_32 (R[m]);
PC += 2;
} |
mov.b Rm,@Rn | 0010nnnnmmmm0000 | Rm -> (Rn) | Transfers the source operand to the destination. | void MOVBS (int m, int n) {
Write_8 (R[n], R[m]);
PC += 2;
} |
mov.w Rm,@Rn | 0010nnnnmmmm0001 | Rm -> (Rn) | Transfers the source operand to the destination. | void MOVWS (int m, int n) {
Write_16 (R[n], R[m]);
PC += 2;
} |
mov.l Rm,@Rn | 0010nnnnmmmm0010 | Rm -> (Rn) | Transfers the source operand to the destination. | void MOVLS (int m, int n) {
Write_32 (R[n], R[m]);
PC += 2;
} |
mov.b @Rm+,Rn | 0110nnnnmmmm0100 | (Rm) -> sign extension -> Rn, Rm+1 -> Rm | Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register. | void MOVBP (int m, int n) {
R[n] = Read_8 (R[m]);
if ((R[n] & 0x80) == 0)
R[n] &= 0x000000FF;
else
R[n] |= 0xFFFFFF00;
if (n != m)
R[m] += 1;
PC += 2;
} |
ldc.l @Rm+,VBR | 0100mmmm00100111 | (Rm) -> VBR, Rm+4 -> Rm | Stores a source operand in control register VBR. | void LDCMVBR (int m) {
VBR = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
ldc Rm,MOD | 0100mmmm01011110 | Rm -> MOD | Stores a source operand in control register MOD. | void LDCMOD (int m) {
MOD = R[m];
PC += 2;
} |
ldc.l @Rm+,MOD | 0100mmmm01010111 | (Rm) -> MOD, Rm+4 -> Rm | Stores a source operand in control register MOD. | void LDCMMOD (int m) {
MOD = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
ldc Rm,RE | 0100mmmm01111110 | Rm -> RE | Stores a source operand in control register RE. | void LDCRE (int m) {
RE = R[m];
PC += 2;
} |
ldc.l @Rm+,RE | 0100mmmm01110111 | (Rm) -> RE, Rm+4 -> Rm | Stores a source operand in control register RE. | void LDCMRE (int m) {
RE = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
ldc Rm,RS | 0100mmmm01101110 | Rm -> RS | Stores a source operand in control register RS. | void LDCRS (int m) {
RS = R[m];
PC += 2;
} |
ldc.l @Rm+,RS | 0100mmmm01100111 | (Rm) -> RS, Rm+4 -> Rm | Stores a source operand in control register RS. | void LDCMRS (int m) {
RS = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
dct psub Sx,Sy,Dz | 111110********** 10100010xxyyzzzz | If DC = 1: Sx - Sy -> Dz Else: nop | Conditionally subtracts the contents of the Sy operand from the Sx operand and stores the result in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated. | void psub_dct (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 1)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
fcnvsd FPUL,DRn | 1111nnn010101101 | float_to_double (FPUL) -> DRn | Converts the single-precision floating-point number in FPUL to a double-precision floating-point number, and stores the result in DRn. | void FCNVSD (int n) {
if (FPSCR_PR != 1)
undefined_operation ();
else
{
switch (fpul_type ())
{
case PZERO:
case NZERO:
case PINF:
case NINF:
case NORM:
DR[n >> 1] = FPUL; // convert float to double
break;
case DENORM:
set_E ();
break;
case qNaN:
qnan (n);
break;
case sNaN:
invalid (n);
break;
}
}
} |
dct pdec Sy,Dz | 111110********** 1010101000yyzzzz | If DC = 1: MSW of Sy - 1 -> MSW of DZ, clear LSW of Dz Else: nop | Conditionally subtracts 1 from the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated. | void pdec_sy_dct (void) {
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
bld #imm3,Rn | 10000111nnnn1iii | imm of Rn -> T | Stores a specified bit of the LSB 8 bits of a general register Rn in the T bit. The bit number is specified by 3-bit immediate data. | void BLD (int i, int n) {
long imm, assignbit;
imm = (0x00000007 & (long)i);
assignbit = (0x00000001 << imm) & R[n];
if (assignbit == 0)
T = 0;
else
T = 1;
PC += 2;
} |
bldnot.b #imm3,@(disp12,Rn) | 0011nnnn0iii1001 1011dddddddddddd | ~(imm of (disp+Rn)) -> T | Inverts a specified bit of memory at the address indicated by (disp + Rn), and stores the resulting value in the T bit. The bit number is specified by 3-bit immediate data. Data is read from memory as a byte unit. | void BLDNOTM (int d, int i, int n) {
long disp = (0x00000FFF & (long)d);
long imm = (0x00000007 & (long)i);
long temp = Read_8 (R[n] + disp);
long assignbit = (0x00000001 << imm) & temp;
if (assignbit == 0)
T = 1;
else
T = 0;
PC += 4;
} |
pclr Dz | 111110********** 100011010000zzzz | 0x00000000 -> Dz | Clears the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The Z bit of the DSR register is set to 1. The N, V, and GT bits are cleared to 0. | void pclr (void) {
DSP_REG[ex2_dz_no] = 0x0;
if (ex2_dz_no == 0)
A0G = 0x0;
else if (ex2_dz_no == 1)
A1G = 0x0;
carry_bit = 0;
negative_bit = 0;
zero_bit = 1;
overflow_bit = 0;
#include "fixed_pt_plus_dc_bit.c"
} |
sts.l Y0,@-Rn | 0100nnnn10100010 | Rn-4 -> Rn, Y0 -> (Rn) | Stores DSP register Y0 in the destination. | void STSMY0 (int n) {
R[n] -= 4;
Write_32 (R[n], Y0);
PC += 2;
} |
sts Y1,Rn | 0000nnnn10111010 | Y1 -> Rn | Stores DSP register Y1 in the destination. | void STSY1 (int n) {
R[n] = Y1;
PC += 2;
} |
sts.l Y1,@-Rn | 0100nnnn10110010 | Rn-4 -> Rn, Y1 -> (Rn) | Stores DSP register Y1 in the destination. | void STSMY1 (int n) {
R[n] -= 4;
Write_32 (R[n], Y1);
PC += 2;
} |
synco | 0000000010101011 | Prevents the next instruction from being issued until instructions issued before this instruction has been completed. | This instruction is used to synchronize data operations. When this instruction is executed, the subsequent bus accesses are not executed until the execution of all preceding bus accesses has been completed. | void SYNCO (void) {
synchronize_data_operaiton ();
PC += 2;
} |
trapa #imm | 11000011iiiiiiii | SH1*,SH2*: PC/SR -> stack area, (imm*4 + VBR) -> PC
SH3*,SH4*: PC/SR -> SPC/SSR, imm*4 -> TRA, 0x160 -> EXPEVT, VBR + 0x0100 -> PC | Starts trap exception handling. | void TRAPA (int i) {
int imm = (0x000000FF & i);
#if SH1 || SH2 || SH2A
R[15] -= 4;
Write_32 (R[15], SR);
R[15] -= 4;
Write_32 (R[15], PC + 2);
PC = Read_32 (VBR + (imm << 2));
#elif SH3 || SH4 || SH4A
TRA = imm << 2;
SSR = SR;
SPC = PC + 2;
SGR = R15;
SR.MD = 1;
SR.BL = 1;
SR.RB = 1;
EXPEVT = 0x00000160;
PC = VBR + 0x00000100;
#endif
} |
fmov FRm,FRn | 1111nnnnmmmm1100 | FRm -> FRn | Transfers FRm contents to FRn. | void FMOV (int m, int n) {
FR[n] = FR[m];
PC += 2;
} |
fmov.s @Rm,FRn | 1111nnnnmmmm1000 | (Rm) -> FRn | Transfers contents of memory at address indicated by Rm to FRn. | void FMOV_LOAD (int m, int n) {
FR[n] = Read_32 (R[m]);
PC += 2;
} |
mov.w R0,@(disp,Rn) | 10000001nnnndddd | R0 -> (disp*2 + Rn) | Transfers the source operand to the destination. The 4-bit displacement is multiplied by two after zero-extension, enabling a range up to +30 bytes to be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead. | void MOVWS4 (int d, int n) {
long disp = (0x0000000F & (long)d);
Write_16 (R[n] + (disp << 1), R[0]);
PC += 2;
} |
mov.w Rm,@(disp12,Rn) | 0011nnnnmmmm0001 0001dddddddddddd | Rm -> (disp*2 + Rn) | Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack. | void MOVWS12 (int d, int m, int n) {
long disp = (0x00000FFF & (long)d);
Write_16 (R[n] + (disp << 1), R[m]);
PC += 4;
} |
mov.l Rm,@(disp,Rn) | 0001nnnnmmmmdddd | Rm -> (disp*4 + Rn) | Transfers the source operand to the destination. The 4-bit displacement is multiplied by four after zero-extension, enabling a range up to +60 bytes to be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead. | void MOVLS4 (int m, int d, int n) {
long disp = (0x0000000F & (long)d);
Write_32 (R[n] + (disp << 2), R[m]);
PC += 2;
} |
mov.l Rm,@(disp12,Rn) | 0011nnnnmmmm0001 0010dddddddddddd | Rm -> (disp*4 + Rn) | Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack. | void MOVLS12 (int d, int m, int n) {
long disp = (0x00000FFF & (long)d);
Write_32 (R[n] + (disp << 2), R[m]);
PC += 4;
} |
mov.b @(R0,Rm),Rn | 0000nnnnmmmm1100 | (R0 + Rm) -> sign extension -> Rn | Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register. | void MOVBL0 (int m, int n) {
R[n] = Read_8 (R[m] + R[0]);
if ((R[n] & 0x80) == 0)
R[n] &= 0x000000FF;
else R[n] |= 0xFFFFFF00;
PC += 2;
} |
mov.w @(R0,Rm),Rn | 0000nnnnmmmm1101 | (R0 + Rm) -> sign extension -> Rn | Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register. | void MOVWL0 (int m, int n) {
R[n] = Read_16 (R[m] + R[0]);
if ((R[n] & 0x8000) == 0)
R[n] &= 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
PC += 2;
} |
mov.l @(R0,Rm),Rn | 0000nnnnmmmm1110 | (R0 + Rm) -> Rn | Transfers the source operand to the destination. | void MOVLL0 (int m, int n) {
R[n] = Read_32 (R[m] + R[0]);
PC += 2;
} |
movs.l Ds,@As+Is | 111101AADDDD1111 | Ds -> (As), As+Is -> As | Transfers the source operand data to the destination. The transferred data is a longword. | null |
pabs Sx,Dz | 111110********** 10001000xx00zzzz | If Sx >= 0: Sx -> Dz
If Sx < 0: 0 - Sx -> Dz | Finds absolute values. When the Sx operand is positive, the contents of the operand are transferred to the Dz operand. If the value is negative, the value of the Sx operand is subtracted from 0 and stored in the Dz operand. | null |
pabs Sy,Dz | 111110********** 1010100000yyzzzz | If Sy >= 0: Sy -> Dz
If Sy < 0: 0 - Sy -> Dz | Finds absolute values. When the Sy operand is positive, the contents of the operand are transferred to the Dz operand. If the value is negative, the value of the Sy operand is subtracted from 0 and stored in the Dz operand. | null |
padd Sx,Sy,Dz | 111110********** 10110001xxyyzzzz | Sx + Sy -> Dz | Adds the contents of the Sx and Sy operands and stores the result in the Dz operand. | null |
dct padd Sx,Sy,Dz | 111110********** 10110010xxyyzzzz | If DC = 1: Sx + Sy -> Dz
Else: nop | Conditionally adds the contents of the Sx and Sy operands and stores the result in the Dz operand. The instruction is executed if the DC bit is set to 1. Otherwise, no operation is performed. | null |
dcf padd Sx,Sy,Dz | 111110********** 10110011xxyyzzzz | If DC = 0: Sx + Sy -> Dz
Else: nop | Conditionally adds the contents of the Sx and Sy operands and stores the result in the Dz operand. The instruction is executed if the DC bit is set to 0. Otherwise, no operation is performed. | null |
padd Sx,Sy,Du
pmuls Se,Sf,Dg | 111110********** 0111eeffxxyygguu | Sx + Sy -> Du
MSW of Se * MSW of Sf -> Dg | Adds the contents of the Sx and Sy operands and stores the result in the Du operand. The contents of the top word of the Se and Sf operands are multiplied as signed and the result stored in the Dg operand. These two processes are executed simultaneously in parallel. | null |
paddc Sx,Sy,Dz | 111110********** 10110000xxyyzzzz | Sx + Sy + DC -> Dz | Adds the contents of the Sx and Sy operands to the DC bit and stores the result in the Dz operand. The DC bit of the DSR register is updated as the carry flag. The N, Z, V, and GT bits of the DSR register are also updated. | void paddc (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2 + DSPDCBIT;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_dc_always_carry.c"
} |
fcmp/gt DRm,DRn | 1111nnn0mmm00101 | If DRn > DRm: 1 -> T Else: 0 -> T | Arithmetically compares the two double-precision floating-point numbers in DRn and DRm, and stores 1 in the T bit if DRn > DRm, or 0 otherwise. | void FCMP_GT (int m, int n) {
PC += 2;
clear_cause ();
if (fcmp_chk_double (m, n) == INVALID || fcmp_chk_double (m, n) == UO)
fcmp_invalid ();
else if (fcmp_chk_double (m, n) == GT)
T = 1;
else
T = 0;
}
int fcmp_chk_double (int m, int n) {
// see description of FCMP/EQ instruction.
}
void fcmp_invalid (void) {
// see description of FCMP/EQ instruction.
} |
mov.b Rm,@(R0,Rn) | 0000nnnnmmmm0100 | Rm -> (R0 + Rn) | Transfers the source operand to the destination. | void MOVBS0 (int m, int n) {
Write_8 (R[n] + R[0], R[m]);
PC += 2;
} |
mov.w Rm,@(R0,Rn) | 0000nnnnmmmm0101 | Rm -> (R0 + Rn) | Transfers the source operand to the destination. | void MOVWS0 (int m, int n) {
Write_16 (R[n] + R[0], R[m]);
PC += 2;
} |
mov.l Rm,@(R0,Rn) | 0000nnnnmmmm0110 | Rm -> (R0 + Rn) | Transfers the source operand to the destination. | void MOVLS0 (int m, int n) {
Write_32 (R[n] + R[0], R[m]);
PC += 2;
} |
mov.b @(disp,GBR),R0 | 11000100dddddddd | (disp + GBR) -> sign extension -> R0 | Transfers the source operand to the destination. The 8-bit displacement is only zero-extended, so a range up to +255 bytes can be specified. The loaded data is sign-extended to 32 bit before being stored in the destination register. | void MOVBLG (int d) {
unsigned int disp = (0x000000FF & d);
R[0] = Read_8 (GBR + disp);
if ((R[0] & 0x80) == 0)
R[0] &= 0x000000FF;
else
R[0] |= 0xFFFFFF00;
PC += 2;
} |
mov.w @(disp,GBR),R0 | 11000101dddddddd | (disp*2 + GBR) -> sign extension -> R0 | Transfers the source operand to the destination. The 8-bit displacement is multiplied by two after zero-extension, enabling a range up to +510 bytes to be specified. The loaded data is sign-extended to 32 bit before being stored in the destination register. | void MOVWLG (int d) {
unsigned int disp = (0x000000FF & d);
R[0] = Read_16 (GBR + (disp << 1));
if ((R[0] & 0x8000) == 0)
R[0] &= 0x0000FFFF;
else
R[0] |= 0xFFFF0000;
PC += 2;
} |
mov.l @(disp,GBR),R0 | 11000110dddddddd | (disp*4 + GBR) -> R0 | Transfers the source operand to the destination. The 8-bit displacement is multiplied by four after zero-extension, enabling a range up to +1020 bytes to be specified. | void MOVLLG (int d) {
unsigned int disp = (0x000000FF & d);
R[0] = Read_32 (GBR + (disp << 2));
PC += 2;
} |
mov.b R0,@(disp,GBR) | 11000000dddddddd | R0 -> (disp + GBR) | Transfers the source operand to the destination. The 8-bit displacement is only zero-extended, so a range up to +255 bytes can be specified. | void MOVBSG (int d) {
unsigned int disp = (0x000000FF & d);
Write_8 (GBR + disp, R[0]);
PC += 2;
} |
pinc Sx,Dz | 111110********** 10011001xx00zzzz | MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz | Adds 1 to the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pinc_sx (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
#include "integer_unconditional_update.c"
#include "integer_plus_dc_bit.c"
} |
mov.w @Rm+,Rn | 0110nnnnmmmm0101 | (Rm) -> sign extension -> Rn, Rm+2 -> Rm | Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register. | void MOVWP (int m, int n) { R[n] = Read_16 (R[m]); if ((R[n] & 0x8000) == 0) R[n] &= 0x0000FFFF; else R[n] |= 0xFFFF0000; if (n != m) R[m] += 2; PC += 2; } |
mov.l @Rm+,Rn | 0110nnnnmmmm0110 | (Rm) -> Rn, Rm+4 -> Rm | Transfers the source operand to the destination. | void MOVLP (int m, int n) { R[n] = Read_32 (R[m]); if (n != m) R[m] += 4; PC += 2; } |
mov.b Rm,@-Rn | 0010nnnnmmmm0100 | Rn-1 -> Rn, Rm -> (Rn) | Transfers the source operand to the destination. | void MOVBM (int m, int n) { Write_8 (R[n] - 1, R[m]); R[n] -= 1; PC += 2; } |
mov.w Rm,@-Rn | 0010nnnnmmmm0101 | Rn-2 -> Rn, Rm -> (Rn) | Transfers the source operand to the destination. | void MOVWM (int m, int n) { Write_16 (R[n] - 2, R[m]); R[n] -= 2; PC += 2; } |
mov.l Rm,@-Rn | 0010nnnnmmmm0110 | Rn-4 -> Rn, Rm -> (Rn) | Transfers the source operand to the destination. | void MOVLM (int m, int n) { Write_32 (R[n] - 4, R[m]); R[n] -= 4; PC += 2; } |
mov.b @-Rm,R0 | 0100mmmm11001011 | Rm-1 -> Rm, (Rm) -> sign extension -> R0 | Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register. | void MOVRSBM (int m) { R[m] -= 1; R[0] = Read_16 (R[m]); if ((R[0] & 0x80) == 0) R[0] &= 0x000000FF; else R[0] |= 0xFFFFFF00; PC+=2; } |
mov.w @-Rm,R0 | 0100mmmm11011011 | Rm-2 -> Rm, (Rm) -> sign extension -> R0 | Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register. | void MOVRSWM (int m) { R[m]-= 2; R[0] = Read_16 (R[m]); if ((R[0] & 0x8000) == 0) R[0] &= 0x0000FFFF; else R[0] |= 0xFFFF0000; PC += 2; } |
dct pinc Sy,Dz | 111110********** 1011101000yyzzzz | If DC = 1: MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz Else: nop | Conditionally adds 1 to the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated. | void pinc_sy_dct (void) {
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
fsts FPUL,FRn | 1111nnnn00001101 | FPUL -> FRn | Transfers the contents of system register FPUL to floating-point register FRn. | void FSTS (int n) {
FR[n] = FPUL;
PC += 2;
} |
fabs FRn | 1111nnnn01011101 | FRn & 0x7FFFFFFF -> FRn | Clears the most significant bit of the contents of floating-point register FRn to 0, and stores the result in FRn. | void FABS (int n) {
FR[n] = FR[n] & 0x7FFFFFFFF;
PC += 2;
} |
fneg FRn | 1111nnnn01001101 | FRn ^ 0x80000000 -> FRn | Inverts the most significant bit (sign bit) of the contents of floating-point register FRn, and stores the result in FRn. | void FNEG (int n) {
FR[n] = -FR[n];
PC += 2;
} |
fcnvds DRm,FPUL | 1111mmm010111101 | double_to_float (DRm) -> FPUL | Converts the double-precision floating-point number in DRm to a single-precision floating-point number, and stores the result in FPUL. | void FCNVDS (int m) {
if (FPSCR_PR != 1)
undefined_operation ();
else
{
PC += 2;
clear_cause ();
switch (data_type_of (m))
{
case NORM:
case PZERO:
case NZERO:
normal_fcnvds (m, &FPUL);
break;
case DENORM:
set_E ();
case PINF:
FPUL = 0x7F800000;
break;
case NINF:
FPUL = 0xFF800000;
break;
case qNaN:
FPUL = 0x7FBFFFFF;
break;
case sNaN:
set_V ();
if ((FPSCR & ENABLE_V) == 0)
FPUL = 0x7FBFFFFF;
else
fpu_exception_trap ();
break;
}
}
} |
dct pcopy Sx,Dz | 111110********** 11011010xx00zzzz | If DC = 1: Sx -> Dz Else: nop | Conditionally stores the Sx operand in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated. | void pcopy_sx_dct (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_SRC2 = 0;
DSP_ALU_SRC2G = 0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 1)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
swap.w Rm,Rn | 0110nnnnmmmm1001 | Rm -> swap upper/lower words -> Rn | Swaps the upper and lower parts of the contents of general register Rm and stores the result in Rn. The 16 bits from bit 31 to bit 16 of Rm are swapped with the 16 bits from bit 15 to bit 0. | void SWAPW (int m, int n) {
unsigned long temp;
temp = (R[m] >> 16) & 0x0000FFFF;
R[n] = R[m] << 16;
R[n] |= temp;
PC += 2;
} |
xtrct Rm,Rn | 0010nnnnmmmm1101 | Rm:Rn middle 32 bits -> Rn | Extracts the middle 32 bits from the 64-bit contents of linked general registers Rm and Rn, and stores the result in Rn. | void XTRCT (int m, int n) {
unsigned long high = (R[m] << 16) & 0xFFFF0000;
unsigned long low = (R[n] >> 16) & 0x0000FFFF;
R[n] = high | low;
PC += 2;
} |
psub Sx,Sy,Du
pmuls Se,Sf,Dg | 111110********** 0110eeffxxyygguu | Sx - Sy -> Du
MSW of Se * MSW of Sf -> Dg | Subtracts the contents of the Sy operand from the Sx operand and stores the result in the Du operand. The contents of the top word of the Se and Sf operands are multiplied as signed and the result stored in the Dg operand. These two processes are executed simultaneously in parallel.
The DC bit of the DSR register is updated according to the results of the ALU operation and the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated according to the results of the ALU operation. | void psub_pmuls (void)
{
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
switch (EX2_DU)
{
case 0x0:
X0 = DSP_ALU_DST;
negative_bit = DSP_ALU_DST_MSB;
zero_bit = (DSP_ALU_DST == 0);
break;
case 0x1:
Y0 = DSP_ALU_DST;
negative_bit = DSP_ALU_DST_MSB;
zero_bit = (DSP_ALU_DST == 0);
break;
case 0x2:
A0 = DSP_ALU_DST;
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
break;
case 0x3:
A1 = DSP_ALU_DST;
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
break;
}
#include "fixed_pt_minus_dc_bit.c"
} |
cmp/str Rm,Rn | 0010nnnnmmmm1100 | If Rn and Rm have an equal byte: 1 -> T Else: 0 -> T | Compares general registers Rn and Rm, and sets the T bit if any of the 4 bytes in Rn are equal to the corresponding byte in Rm. The contents of Rn and Rm are not changed. | void CMPSTR (int m, int n) { unsigned long temp; long HH, HL, LH, LL; temp = R[n] ^ R[m]; HH = (temp & 0xFF000000) >> 24; HL = (temp & 0x00FF0000) >> 16; LH = (temp & 0x0000FF00) >> 8; LL = temp & 0x000000FF; HH = HH && HL && LH && LL; if (HH == 0) T = 1; else T = 0; PC += 2; } |
clips.b Rn | 0100nnnn10010001 | If Rn > 0x0000007F: 0x0000007F -> Rn, 1 -> CS If Rn < 0xFFFFFF80: 0xFFFFFF80 -> Rn, 1 -> CS | Determines saturation. Signed data is used with this instruction. The saturation upper-limit value is stored in general register Rn if the contents of Rn exceed the saturation upper-limit value, or the saturation lower-limit value is stored in Rn if the contents of Rn are less than the saturation lower-limit value, and the CS bit is set to 1. The saturation upper-limit value is 0x0000007F (127). The saturation lower-limit value is 0xFFFFFF80 (-128). | void CLIPSB (int n) { if (R[n] > 0x0000007F) { R[n] = 0x0000007F; CS = 1; } else if (R[n] < 0xFFFFFF80) { R[n] = 0xFFFFFF80; CS = 1; } PC += 2; } |
clips.w Rn | 0100nnnn10010101 | If Rn > 0x00007FFF: 0x00007FFF -> Rn, 1 -> CS If Rn < 0xFFFF8000: 0xFFFF8000 -> Rn, 1 -> CS | Determines saturation. Signed data is used with this instruction. The saturation upper-limit value is stored in general register Rn if the contents of Rn exceed the saturation upper-limit value, or the saturation lower-limit value is stored in Rn if the contents of Rn are less than the saturation lower-limit value, and the CS bit is set to 1. The saturation upper-limit value is 0x00007FFF (32767). The saturation lower-limit value is 0xFFFF8000 (-32768). | void CLIPSW (int n) { if (R[n] > 0x00007FFF) { R[n] = 0x00007FFF; CS = 1; } else if (R[n] < 0xFFFF8000) { R[n] = 0xFFFF8000; CS = 1; } PC += 2; } |
clipu.b Rn | 0100nnnn10000001 | If Rn > 0x000000FF: 0x000000FF -> Rn, 1 -> CS | Determines saturation. Unsigned data is used with this instruction. If the contents of general register Rn exceed the saturation value, the saturation value is stored in Rn and the CS bit is set to 1. The saturation value is 0x000000FF (255). | void CLIPUB (int n) { if (R[n] > 0x000000FF) { R[n] = 0x000000FF; CS = 1; } PC += 2; } |
clipu.w Rn | 0100nnnn10000101 | If Rn > 0x0000FFFF: 0x0000FFFF -> Rn, 1 -> CS | Determines saturation. Unsigned data is used with this instruction. If the contents of general register Rn exceed the saturation value, the saturation value is stored in Rn and the CS bit is set to 1. The saturation value is 0x0000FFFF (65535). | void CLIPUW (int n) { if (R[n] > 0x0000FFFF) { R[n] = 0x0000FFFF; CS = 1; } PC += 2; } |
div0s Rm,Rn | 0010nnnnmmmm0111 | MSB of Rn -> Q, MSB of Rm -> M, M ^ Q -> T | Performs initial settings for signed division. This instruction is followed by a DIV1 instruction that executes 1-digit division, for example, and repeated division steps are executed to find the quotient. See the description of the DIV1 instruction for details. | void DIV0S (int m, int n) { if ((R[n] & 0x80000000) == 0) Q = 0; else Q = 1; if ((R[m] & 0x80000000) == 0) M = 0; else M = 1; T = ! (M == Q); PC += 2; } |
div0u | 0000000000011001 | 0 -> M, 0 -> Q, 0 -> T | Performs initial settings for unsigned division. This instruction is followed by a DIV1 instruction that executes 1-digit division, for example, and repeated division steps are executed to find the quotient. See the description of the DIV1 instruction for details. | void DIV0U (void) { M = Q = T = 0; PC += 2; } |
plds Dz,MACH | 111110********** 111011010000zzzz | Dz -> MACH | Stores the Dz operand in the MACH register. The DC, N, Z, V, and GT bits of the DSR register are not updated. | void plds_mach (void) { MACH = DSP_REG[ex2_dz_no]; } |
dcf pinc Sy,Dz | 111110********** 1011101100yyzzzz | If DC = 0: MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz Else: nop | Conditionally adds 1 to the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pinc_sy_dcf (void) {
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
dct padd Sx,Sy,Dz | 111110********** 10110010xxyyzzzz | If DC = 1: Sx + Sy -> Dz Else: nop | Conditionally adds the contents of the Sx and Sy operands and stores the result in the Dz operand. The instruction is executed of the DC bit is set to 1. Otherwise no operation is performed. The DC, N, Z, V, and GT bits are not updated. | void padd_dct (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1: DSP_ALU_SRC2 = Y1;
break;
case 0x2: DSP_ALU_SRC2 = M0;
break;
case 0x3: DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 1)
{
DSP_REG [ex2_dz_no] = DSP_ALU_DST;
if(ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7) A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no==1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
movy.w Da,@Ay+Iy | 111100*A*D*1**11 | MSW of Da -> (Ay), Ay+Iy -> Ay | Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for Y memory. The source word data is the top word of the register. | * of the instruction code is MOVX instruction designation area. MSW = High-order word of operand. |
movs.w @-As,Ds | 111101AADDDD0000 | As-2 -> As, (As) -> MSW of Ds, 0 -> LSW of Ds | Transfers the source operand data to the destination. The transferred data is a word, the word data is loaded to the top word of the register and the bottom word is cleared with zeros. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits. | null |
movs.w @As,Ds | 111101AADDDD0100 | (As) -> MSW of Ds, 0 -> LSW of Ds | Transfers the source operand data to the destination. The transferred data is a word, the word data is loaded to the top word of the register and the bottom word is cleared with zeros. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits. | null |
movs.w @As+,Ds | 111101AADDDD1000 | (As) -> MSW of Ds, 0 -> LSW of Ds, As+2 -> As | Transfers the source operand data to the destination. The transferred data is a word, the word data is loaded to the top word of the register and the bottom word is cleared with zeros. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits. | null |
movs.w @As+Ix,Ds | 111101AADDDD1100 | (As) -> MSW of Ds, 0 -> LSW of DS, As+Ix -> As | Transfers the source operand data to the destination. The transferred data is a word, the word data is loaded to the top word of the register and the bottom word is cleared with zeros. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits. | null |
dct pinc Sy,Dz | 111110********** 1011101000yyzzzz | If DC = 1: MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz Else: nop | Conditionally adds 1 to the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated. | void pinc_sy_dct (void) {
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
dcf pinc Sy,Dz | 111110********** 1011101100yyzzzz | If DC = 0: MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz Else: nop | Conditionally adds 1 to the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pinc_sy_dcf (void) {
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
mov.w @(disp,Rm),R0 | 10000101mmmmdddd | (disp*2 + Rm) -> sign extension -> R0 | Transfers the source operand to the destination. The 4-bit displacement is multiplied by two after zero-extension, enabling a range up to +30 bytes to be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead. The loaded data is sign-extended to 32 bit before being stored in the destination register. | void MOVWL4 (int m, int d) {
long disp = (0x0000000F & (long)d);
R[0] = Read_16 (R[m] + (disp << 1));
if ((R[0] & 0x8000) == 0)
R[0] &= 0x0000FFFF;
else
R[0] |= 0xFFFF0000;
PC += 2;
} |
mov.w @(disp12,Rm),Rn | 0011nnnnmmmm0001 0101dddddddddddd | (disp*2 + Rm) -> sign extension -> Rn | Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack. The loaded data is sign-extended to 32 bit before being stored in the destination register. | void MOVWL12 (int d, int m, int n) {
long disp = (0x00000FFF & (long)d);
R[n] = Read_16 (R[m] + (disp << 1));
if ((R[n] & 0x8000) == 0)
R[n] &= 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
PC += 4;
} |
dct pneg Sy,Dz | 111110********** 1110101000yyzzzz | If DC = 1: 0 - Sy -> Dz Else: nop | Conditionally reverses the sign. The instruction is executed if the DC bit is set to 1. Subtracts the Sy operand from 0 and stores the result in the Dz operand. The DC, N, Z, V, and GT bits are not updated. | void pneg_sy_dct (void) {
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 1)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |