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fdiv FRm,FRn | 1111nnnnmmmm0011 | FRn / FRm -> FRn | Arithmetically divides the single-precision floating-point number in FRn by the single-precision floating-point number in FRm, and stores the result in FRn. | void FDIV (int m, int n) {
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case PINF:
case NINF:
inf (n, sign_of (m) ^ sign_of (n));
break;
case PZERO:
case NZERO:
zero (n, sign_of (m) ^ sign_of (n));
break;
case DENORM:
set_E ();
break;
default:
normal_fdiv_single (m, n);
break;
}
break;
case PZERO:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
case PINF:
case NINF:
break;
default:
dz (n, sign_of (m) ^ sign_of (n));
break;
}
break;
case NZERO:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
case PINF:
inf (n, 1);
break;
case NINF:
inf (n, 0);
break;
default:
dz (FR[n], sign_of (m) ^ sign_of (n));
break;
}
break;
case DENORM:
set_E ();
break;
case PINF:
case NINF:
switch (data_type_of (n))
{
case DENORM:
set_E ();
break;
case PINF:
case NINF:
invalid (n);
break;
default:
zero (n, sign_of (m) ^ sign_of (n));
break;
}
break;
}
}
void normal_fdiv_single (int m, int n) {
union
{
float f;
int l;
} dstf, tmpf;
union
{
double d;
int l[2];
} tmpd;
tmpf.f = FR[n]; // save destination value
dstf.f /= FR[m]; // round toward nearest or even
tmpd.d = dstf.f; // convert single to double
tmpd.d *= FR[m];
if (tmpf.f != tmpd.d)
set_I ();
if (tmpf.f < tmpd.d && FPSCR_RM == 1)
dstf.l -= 1; // round toward zero
check_single_exception (&FR[n], dstf.f);
} |
rts | 0000000000001011 | PR -> PC
Delayed branch | Returns from a subroutine procedure by restoring the PC from PR. Processing continues from the address indicated by the restored PC value. This instruction can be used to return from a subroutine procedure called by a BSR or JSR instruction to the source of the call. | void RTS (void)
{
unsigned int temp;
temp = PC;
PC = PR;
Delay_Slot (temp + 2);
} |
rts/n | 0000000001101011 | PR -> PC | Performs a return from a subroutine procedure. That is, the PC is restored from PR, and processing is resumed from the address indicated by the PC. This instruction enables a return to be made from a subroutine procedure called by a BSR or JSR instruction to the origin of the call. | void RTSN (void)
{
PC = PR;
} |
rtv/n Rm | 0000mmmm01111011 | Rm -> R0, PR -> PC | Performs a return from a subroutine procedure after a transfer from specified general register Rm to R0. That is, after the Rm value is stored in R0, the PC is restored from PR, and processing is resumed from the address indicated by the PC. This instruction enables a return to be made from a subroutine procedure called by a BSR or JSR instruction to the origin of the call. | void RTVN (int m)
{
R[0] = R[m];
PC = PR;
} |
clrmac | 0000000000101000 | 0 -> MACH, 0 -> MACL | Clears the MACH and MACL registers. | void CLRMAC (void)
{
MACH = 0;
MACL = 0;
PC += 2;
} |
clrs | 0000000001001000 | 0 -> S | Clears the S bit to 0. | void CLRS (void)
{
S = 0;
PC += 2;
} |
clrt | 0000000000001000 | 0 -> T | Clears the T bit. | void CLRT (void)
{
T = 0;
PC += 2;
} |
icbi @Rn | 0000nnnn11100011 | Invalidate instruction cache block indicated by logical address | Accesses the instruction cache at the effective address indicated by the contents of Rn. When the cache is hit, the corresponding cache block is invalidated (the V bit is cleared to 0). At this time, write-back is not performed. No operation is performed in the case of a cache miss or access to a non-cache area. | void ICBI (int n)
{
invalidate_instruction_cache_block (R[n]);
PC += 2;
} |
movs.l @As,Ds | 111101AADDDD0110 | (As) -> Ds | Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits. | null |
movs.l @As+,Ds | 111101AADDDD1010 | (As) -> Ds, As+4 -> As | Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits. | null |
movs.l @As+Is,Ds | 111101AADDDD1110 | (As) -> Ds, As+Is -> As | Transfers the source operand data to the destination. The transferred data is a longword. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits. | null |
movs.l Ds,@-As | 111101AADDDD0011 | As-4 -> As, Ds -> (As) | Transfers the source operand data to the destination. The transferred data is a longword. | null |
movs.l Ds,@As | 111101AADDDD0111 | Ds -> (As) | Transfers the source operand data to the destination. The transferred data is a longword. | null |
fadd DRm,DRn | 1111nnn0mmm00000 | DRn + DRm -> DRn | Arithmetically adds the two double-precision floating-point numbers in DRn and DRm, and stores the result in DRn. | void FADD (int m, int n) {
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
set_E ();
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case NORM:
normal_faddsub (m, n, ADD);
break;
case PZERO:
case NZERO:
register_copy (m, n);
break;
default:
break;
}
break;
case PZERO:
switch (data_type_of (n))
{
case NZERO:
zero (n, 0);
break;
default:
break;
}
break;
case NZERO:
break;
case PINF:
switch (data_type_of (n))
{
case NINF:
invalid (n);
break;
default:
inf (n, 0);
break;
}
break;
case NINF:
switch (data_type_of (n))
{
case PINF:
invalid (n);
break;
default:
inf (n, 1);
break;
}
break;
}
} |
fsqrt DRn | 1111nnn001101101 | sqrt (DRn) -> DRn | Finds the arithmetical square root of the double-precision floating-point number in DRn, and stores the result in DRn. When FPSCR.enable.I is set, an FPU exception trap is generated regardless of whether or not an exception has occurred. When an exception occurs, correct exception information is reflected in FPSCR.cause and FPSCR.flag and DRn is not updated. Appropriate processing should therefore be performed by software. | void FSQRT (int n) {
PC += 2;
clear_cause ();
switch (data_type_of (n)) {
case NORM:
if (sign_of (n) == 0)
normal_fsqrt_double (n);
else
invalid (n);
break;
case DENORM:
if (sign_of (n) == 0)
set_E ();
else
invalid (n);
break;
case PZERO:
case NZERO:
case PINF:
break;
case NINF:
invalid (n);
break;
case qNAN:
qnan (n);
break;
case sNAN:
invalid (n);
break;
}
}
void normal_fsqrt_double (int n) {
union {
double d;
int l[2];
} dstd, tmpd;
union {
int double x;
int l[4];
} tmpx;
tmpd.d = DR[n >> 1]; // save destination value
dstd.d = sqrt (DR[n >> 1]); // round toward nearest or even
tmpx.x = dstd.d; // convert double to int double
tmpx.x *= dstd.d;
if (tmpd.d != tmpx.x)
set_I ();
if (tmpd.d < tmpx.x && FPSCR_RM == 1)
{
dstd.l[1] -= 1; // round toward zero
if (dstd.l[1] == 0xFFFFFFFF)
dstd.l[0] -= 1;
}
if (FPSCR & ENABLE_I)
fpu_exception_trap();
else
DR[n >> 1] = dstd.d;
} |
fsqrt FRn | 1111nnnn01101101 | sqrt (FRn) -> FRn | Finds the arithmetical square root of the single-precision floating-point number in FRn, and stores the result in FRn. When FPSCR.enable.I is set, an FPU exception trap is generated regardless of whether or not an exception has occurred. When an exception occurs, correct exception information is reflected in FPSCR.cause and FPSCR.flag and FRn is not updated. Appropriate processing should therefore be performed by software. | void FSQRT (int n) {
PC += 2;
clear_cause ();
switch (data_type_of (n)) {
case NORM:
if (sign_of (n) == 0)
normal_fsqrt_single (n);
else
invalid (n);
break;
case DENORM:
if (sign_of (n) == 0)
set_E ();
else
invalid (n);
break;
case PZERO:
case NZERO:
case PINF:
break;
case NINF:
invalid (n);
break;
case qNAN:
qnan (n);
break;
case sNAN:
invalid (n);
break;
}
}
void normal_fsqrt_single (int n) {
union {
float f;
int l;
} dstf, tmpf;
union {
double d;
int l[2];
} tmpd;
tmpf.f = FR[n]; // save destination value
dstf.f = sqrt (FR[n]); // round toward nearest or even
tmpd.d = dstf.f; // convert single to double
tmpd.d *= dstf.f;
if (tmpf.f != tmpd.d)
set_I ();
if (tmpf.f < tmpd.d && FPSCR_RM == 1)
dstf.l -= 1; // round toward zero
if (FPSCR & ENABLE_I)
fpu_exception_trap ();
else
FR[n] = dstf.f;
} |
pcopy Sy,Dz | 111110********** 1111100100yyzzzz | Sy -> Dz | Stores the Sy operand in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits are also updated. | void pcopy_sy (void) {
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_plus_dc_bit.c"
} |
dcf pdmsb Sy,Dz | 111110********** 1011111100yyzzzz | If DC = 0: Sy data MSB position -> MSW of Dz, clear LSW of Dz Else: nop | Conditionally finds the first position to change in the lineup of Sy operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pdmsb_sy_dcf (void) {
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
lds.l @Rm+,A0 | 0100mmmm01110110 | (Rm) -> A0, Rm+4 -> Rm | Stores the source operand into the DSP register A0. The MSB of the data is copied into A0G. | void LDSMA0 (int m) {
A0 = Read_32 (R[m]);
if ((A0 & 0x80000000) == 0)
A0G = 0x00;
else
A0G = 0xFF;
R[m] += 4;
PC += 2;
} |
lds Rm,X0 | 0100mmmm10001010 | Rm -> X0 | Stores the source operand into the DSP register X0. | void LDSX0 (int m) {
X0 = R[m];
PC += 2;
} |
lds.l @Rm+,X0 | 0100nnnn10000110 | (Rm) -> X0, Rm+4 -> Rm | Stores the source operand into the DSP register X0. | void LDSMX0 (int m) {
X0 = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
lds Rm,X1 | 0100mmmm10011010 | Rm -> X1 | Stores the source operand into the DSP register X1. | void LDSX1 (int m) {
X1 = R[m];
PC += 2;
} |
lds.l @Rm+,X1 | 0100nnnn10010110 | (Rm) -> X1, Rm+4 -> Rm | Stores the source operand into the DSP register X1. | void LDSMX1 (int m) {
X1 = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
lds Rm,Y0 | 0100mmmm10101010 | Rm -> Y0 | Stores the source operand into the DSP register Y0. | void LDSY0 (int m) {
Y0 = R[m];
PC += 2;
} |
lds.l @Rm+,Y0 | 0100nnnn10100110 | (Rm) -> Y0, Rm+4 -> Rm | Stores the source operand into the DSP register Y0. | void LDSMY0 (int m) {
Y0 = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
float FPUL,DRn | 1111nnn000101101 | (double)FPUL -> DRn | Taking the contents of FPUL as a 32-bit integer, converts this integer to a double-precision floating-point number and stores the result in DRn. | void FLOAT_double (int n) {
union
{
double d;
int l[2];
} tmp;
PC += 2;
clear_cause ();
DR[n >> 1] = FPUL; // convert from integer to double
}
|
dcf pdec Sy,Dz | 111110********** 1010101100yyzzzz | If DC = 0: MSW of Sy - 1 -> MSW of DZ, clear LSW of Dz Else: nop | Conditionally subtracts 1 from the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pdec_sy_dcf (void) {
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
dcf pdec Sx,Dz | 111110********** 10001011xx00zzzz | If DC = 0: MSW of Sx - 1 -> MSW of DZ, clear LSW of Dz
Else: nop | Conditionally subtracts 1 from the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pdec_sx_dcf (void)
{
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
stc.l RE,@-Rn | 0100nnnn01110011 | Rn-4 -> Rn, RE -> (Rn) | Stores control register RE in the destination. | void STCMRE (int n) {
R[n] -= 4;
Write_32 (R[n], RE);
PC += 2;
} |
stc RS,Rn | 0000nnnn01100010 | RS -> Rn | Stores control register RS in the destination. | void STCRS (int n) {
R[n] = RS;
PC += 2;
} |
stc.l RS,@-Rn | 0100nnnn01100011 | Rn-4 -> Rn, RS -> (Rn) | Stores control register RS in the destination. | void STCMRS (int n) {
R[n] -= 4;
Write_32 (R[n], RS);
PC += 2;
} |
stc SGR,Rn | 0000nnnn00111010 | SGR -> Rn | Stores control register SGR in the destination. | void STCSGR (int n) {
R[n] = SGR;
PC += 2;
} |
stc.l SGR,@-Rn | 0100nnnn00110010 | Rn-4 -> Rn, SGR -> (Rn) | Stores control register SGR in the destination. | void STCMSGR (int n) {
R[n] -= 4;
Write_32 (R[n], SGR);
PC += 2;
} |
stc SSR,Rn | 0000nnnn00110010 | SSR -> Rn | Stores control register SSR in the destination. | void STCSSR (int n) {
R[n] = SSR;
PC += 2;
} |
stc.l SSR,@-Rn | 0100nnnn00110011 | Rn-4 -> Rn, SSR -> (Rn) | Stores control register SSR in the destination. | void STCMSSR (int n) {
R[n] -= 4;
Write_32 (R[n], SSR);
PC += 2;
} |
dct pdec Sy,Dz | 111110********** 1010101000yyzzzz | If DC = 1: MSW of Sy - 1 -> MSW of DZ, clear LSW of Dz Else: nop | Conditionally subtracts 1 from the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated. | void pdec_sy_dct (void) {
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
fcmp/eq DRm,DRn | 1111nnn0mmm00100 | If DRn = DRm: 1 -> T Else: 0 -> T | Arithmetically compares the two double-precision floating-point numbers in DRn and DRm, and stores 1 in the T bit if they are equal, or 0 otherwise. | void FCMP_EQ (int m, int n) { PC += 2; clear_cause (); if (fcmp_chk_double (m, n) == INVALID) fcmp_invalid (); else if (fcmp_chk_double (m, n) == EQ) T = 1; else T = 0; } |
fcmp/gt DRm,DRn | 1111nnn0mmm00101 | If DRn > DRm: 1 -> T Else: 0 -> T | Arithmetically compares the two double-precision floating-point numbers in DRn and DRm, and stores 1 in the T bit if DRn > DRm, or 0 otherwise. | void FCMP_GT (int m, int n) { PC += 2; clear_cause (); if (fcmp_chk_double (m, n) == INVALID || fcmp_chk_double (m, n) == UO) fcmp_invalid (); else if (fcmp_chk_double (m, n) == GT) T = 1; else T = 0; } |
float FPUL,DRn | 1111nnn000101101 | (double)FPUL -> DRn | Taking the contents of FPUL as a 32-bit integer, converts this integer to a double-precision floating-point number and stores the result in DRn. | void FLOAT_double (int n) { union { double d; int l[2]; } tmp; PC += 2; clear_cause (); DR[n >> 1] = FPUL; } |
ftrc DRm,FPUL | 1111mmm000111101 | (long)DRm -> FPUL | Converts the double-precision floating-point number in DRm to a 32-bit integer, and stores the result in FPUL. | void FTRC_double (int m) { PC += 2; clear_cause (); switch (ftrc_double_type_of (m)) { case NORM: FPUL = DR[m >> 1]; break; case PINF: ftrc_invalid (0, &FPUL); break; case NINF: ftrc_invalid (1, &FPUL); break; } } |
fcnvds DRm,FPUL | 1111mmm010111101 | double_to_float (DRm) -> FPUL | Converts the double-precision floating-point number in DRm to a single-precision floating-point number, and stores the result in FPUL. | void FCNVDS (int m) { if (FPSCR_PR != 1) undefined_operation (); else { PC += 2; clear_cause (); switch (data_type_of (m)) { case NORM: case PZERO: case NZERO: normal_fcnvds (m, &FPUL); break; case DENORM: set_E (); case PINF: FPUL = 0x7F800000; break; case NINF: FPUL = 0xFF800000; break; case qNaN: FPUL = 0x7FBFFFFF; break; case sNaN: set_V (); if ((FPSCR & ENABLE_V) == 0) FPUL = 0x7FBFFFFF; else fpu_exception_trap (); break; } } } |
paddc Sx,Sy,Dz | 111110********** 10110000xxyyzzzz | Sx + Sy + DC -> Dz | Adds the contents of the Sx and Sy operands to the DC bit and stores the result in the Dz operand. The DC bit of the DSR register is updated as the carry flag. The N, Z, V, and GT bits of the DSR register are also updated. | void paddc (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2 + DSPDCBIT;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_dc_always_carry.c"
} |
dcf pshl Sx,Sy,Dz | 111110********** 10000011xxyyzzzz | If DC = 0 & Sy >= 0: Sx << Sy -> Dz, clear LSW of Dz
If DC = 0 & Sy < 0: Sx >> Sy -> Dz, clear LSW of Dz
If DC = 1: nop | Conditionally logically shifts the top word contents of the Sx operand, stores
the result in the top word of the Dz operand, and clears the bottom word of the
Dz operand with zeros. When Dz is a register that has guard bits, the guard bits
are also zeroed. The amount of the shift is specified by the Sy operand. When
the shift amount is positive, it shifts left. When the shift amount is negative,
it shifts right.
The instruction is executed if the DC bit is set to 0.
The DC, N, Z, V, and GT bits are not updated. | void pshl_dcf (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0 & MASK003F0000;
break;
case 0x1:
DSP_ALU_SRC2 = Y1 & MASK003F0000;
break;
case 0x2:
DSP_ALU_SRC2 = M0 & MASK003F0000;
break;
case 0x3:
DSP_ALU_SRC2 = M1 & MASK003F0000;
break;
}
if ((DSP_ALU_SRC2_HW & MASK0020) == 0)
{
// Left Shift 0 <= cnt <= 16
char cnt = DSP_ALU_SRC2_HW & MASK001F;
if (cnt > 16)
{
printf ("\nPSHL Sx,Sy,Dz Error! Shift %2X exceed range.\n", cnt);
exit ();
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW << cnt--;
carry_bit = ((DSP_ALU_SRC1_HW << cnt) & MASK8000) == 0x8000;
}
else
{
// Right Shift 0 < cnt <= 16
char cnt = (~DSP_ALU_SRC2_HW & MASK000F) + 1;
if (cnt > 16)
{
printf ("\nPSHL Sx,Sy,Dz Error! Shift -%2X exceed range.\n", cnt);
exit ();
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW >> cnt--;
carry_bit = ((DSP_ALU_SRC1_HW >> cnt) & MASK0001) == 0x1;
}
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no == 1)
A1G = 0x0;
}
} |
dcf pinc Sx,Dz | 111110********** 10011011xx00zzzz | If DC = 0: MSW of Sx + 1 -> MSW of Dz, clear LSW of Dz Else: nop | Conditionally adds 1 to the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pinc_sx_dcf (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
pdmsb Sx,Dz | 111110********** 10011101xx00zzzz | Sx data MSB position -> MSW of Dz, clear LSW of Dz | Finds the first position to change in the lineup of Sx operand bits and stores the bit position in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pdmsb_sx (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
overflow_bit = 0;
#include "integer_unconditional_update.c"
#include "integer_plus_dc_bit.c"
} |
dct pinc Sx,Dz | 111110********** 10011010xx00zzzz | If DC = 1: MSW of Sx + 1 -> MSW of Dz, clear LSW of Dz
Else: nop | Conditionally adds 1 to the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated. | void pinc_sx_dct (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
sts.l MACH,@-Rn | 0100nnnn00000010 | Rn-4 -> Rn, MACH -> (Rn) | Stores system register MACH in the destination. | void STSMMACH (int n) {
R[n] -= 4;
#if SH1
if ((MACH & 0x00000200) == 0)
Write_32 (R[n], MACH & 0x000003FF);
else
Write_32 (R[n], MACH | 0xFFFFFC00)
#else
Write_32 (R[n], MACH);
#endif
PC += 2;
} |
sts MACL,Rn | 0000nnnn00011010 | MACL -> Rn | Stores system register MACL in the destination. | void STSMACL (int n) {
R[n] = MACL;
PC += 2;
} |
sts.l MACL,@-Rn | 0100nnnn00010010 | Rn-4 -> Rn, MACL -> (Rn) | Stores system register MACL in the destination. | void STSMMACL (int n) {
R[n] -= 4;
Write_32 (R[n], MACL);
PC += 2;
} |
sts PR,Rn | 0000nnnn00101010 | PR -> Rn | Stores system register PR in the destination. | void STSPR (int n) {
R[n] = PR;
PC += 2;
} |
sts.l PR,@-Rn | 0100nnnn00100010 | Rn-4 -> Rn, PR -> (Rn) | Stores system register PR in the destination. | void STSMPR (int n) {
R[n] -= 4;
Write_32 (R[n], PR);
PC += 2;
} |
sts DSR,Rn | 0000nnnn01101010 | DSR -> Rn | Stores DSP register DSR in the destination. | void STSDSR (int n) {
R[n] = DSR;
PC += 2;
} |
sts.l DSR,@-Rn | 0100nnnn01100010 | Rn-4 -> Rn, DSR -> (Rn) | Stores DSP register DSR in the destination. | void STSMDSR (int n) {
R[n] -= 4;
Write_32 (R[n], DSR);
PC += 2;
} |
dcf pdmsb Sx,Dz | 111110********** 10011111xx00zzzz | If DC = 0: Sx data MSB position -> MSW of Dz, clear LSW of Dz Else: nop | Conditionally finds the first position to change in the lineup of Sx operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pdmsb_sx_dcf (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
ftrv XMTRX,FVn | 1111nn0111111101 | transform_vector (XMTRX, FVn) -> FVn | Takes the contents of floating-point registers XF0 to XF15 indicated by XMTRX as a 4-row × 4-column matrix, takes the contents of floating-point registers FR[n] to FR[n + 3] indicated by FVn as a 4-dimensional vector, multiplies the array by the vector, and stores the results in FV[n]. | void FTRV (int n) {
if (FPSCR_PR != 0)
undefined_operation ();
else
{
float saved_vec[4];
float result_vec[4];
int saved_fpscr;
int dst;
PC += 2;
clear_cause ();
saved_fpscr = FPSCR;
FPSCR &= ~ENABLE_VOUI; // mask VOUI enable
dst = 12 - n; // select other vector than FVn
for (int i = 0; i < 4; i++)
saved_vec[i] = FR[dst+i];
for (int i = 0; i < 4; i++)
{
for (int j = 0; j < 4; j++)
FR[dst+j] = XF[i+4j];
fipr (n, dst);
saved_fpscr |= FPSCR & (CAUSE | FLAG);
result_vec[i] = FR[dst+3];
}
for (int i = 0; i < 4; i++)
FR[dst+i] = saved_vec[i];
FPSCR = saved_fpscr;
if (FPSCR & ENABLE_VOUI)
fpu_exception_trap();
else
for (int i = 0; i < 4; i++)
FR[n+i] = result_vec[i];
}
} |
fsrra FRn | 1111nnnn01111101 | 1.0 / sqrt (FRn) -> FRn | Takes the approximate inverse of the arithmetic square root (absolute error is within ±2^-21) of the single-precision floating-point in FRn and writes the result to FRn. Since the this instruction operates by approximation, an imprecision exception is required when the input is a normalized value. In other cases, the instruction does not require an imprecision exception. | void FSRRA (int n) {
if (FPSCR_PR != 0)
undefined_operation ();
else
{
PC += 2;
clear_cause();
switch (data_type_of (n))
{
case NORM:
if (sign_of (n) == 0)
{
set_I ();
FR[n] = 1 / sqrt (FR[n]);
}
else
invalid (n);
break;
case DENORM:
if (sign_of (n) == 0)
fpu_error ();
else
invalid (n);
break;
case PZERO:
case NZERO:
dz (n, sign_of (n));
break;
case PINF:
FR[n] = 0;
break;
case NINF:
invalid (n);
break;
case qNAN:
qnan (n);
break;
case sNAN:
invalid (n);
break;
}
}
} |
fsca FPUL,DRn | 1111nnn011111101 | sin (FPUL) -> FRn
cos (FPUL) -> FR[n+1] | Calculates the sine and cosine approximations of FPUL (absolute error is within ±2^-21) as single-precision floating point values, and places the values of the sine and cosine in FRn and FR[n + 1], respectively. Since this instruction is an approximate operation instruction, an imprecision exception is always required (even if the input is a 0, the result is imprecise). | void FSCA (int n) {
if (FPSCR_PR != 0)
undefined_operation ();
else
{
float angle;
long offset = 0x00010000;
long fraction = 0x0000FFFF;
set_I ();
fraction &= FPUL; // extract sub-rotation (fraction) part
angle = fraction; // convert to float
angle = 2 * M_PI * angle / offset; // convert to radian
FR[n] = sin (angle);
FR[n+1] = cos (angle);
PC += 2;
}
} |
fabs DRn | 1111nnn001011101 | DRn & 0x7FFFFFFFFFFFFFFF -> DRn | Clears the most significant bit of the contents of floating-point register DRn to 0, and stores the result in DRn. | void FABS (int n) {
FR[n] = FR[n] & 0x7FFFFFFFF;
PC += 2;
} |
fneg DRn | 1111nnn001001101 | DRn ^ 0x8000000000000000 -> DRn | Inverts the most significant bit (sign bit) of the contents of floating-point register DRn, and stores the result in DRn. | void FNEG (int n) {
FR[n] = -FR[n];
PC += 2;
} |
dct plds Dz,MACH | 111110********** 111011100000zzzz | If DC = 1: Dz -> MACH Else: nop | Conditionally stores the Dz operand in the MACH register. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits of the DSR register are not updated. | void plds_mach_dct (void) { if (DC == 1) MACH = DSP_REG[ex2_dz_no]; } |
dct plds Dz,MACL | 111110********** 111111100000zzzz | If DC = 1: Dz -> MACL Else: nop | Conditionally stores the Dz operand in the MACL register. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits of the DSR register are not updated. | void plds_macl_dct (void) { if (DC == 1) MACL = DSP_REG[ex2_dz_no]; } |
dcf plds Dz,MACH | 111110********** 111011110000zzzz | If DC = 0: Dz -> MACH Else: nop | Conditionally stores the Dz operand in the MACH register. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits of the DSR register are not updated. | void plds_mach_dcf (void) { if (DC == 0) MACH = DSP_REG[ex2_dz_no]; } |
dcf plds Dz,MACL | 111110********** 111111110000zzzz | If DC = 0: Dz -> MACL Else: nop | Conditionally stores the Dz operand in the MACL register. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits of the DSR register are not updated. | void plds_macl_dcf (void) { if (DC == 0) MACL = DSP_REG[ex2_dz_no]; } |
psts MACH,Dz | 111110********** 110011010000zzzz | MACH -> Dz | Stores the contents of the MACH register in the Dz operand. The DC, N, Z, V, and GT bits of the DSR register are not updated. | void psts_mach (void) { DSP_REG[ex2_dz_no] = MACH; if (ex2_dz_no == 0) { A0G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A0G |= MASKFFFFFF00; } else if (ex2_dz_no == 1) { A1G = DSP_ALU_DSTG & MASK000000FF; if (DSP_ALU_DSTG_BIT7) A1G |= MASKFFFFFF00; } } |
sts FPUL,Rn | 0000nnnn01011010 | FPUL -> Rn | Stores FPU system register FPUL in the destination. | void STSFPUL (int n) { R[n] = FPUL; PC += 2; } |
lds.l @Rm+,FPUL | 0100mmmm01010110 | (Rm) -> FPUL, Rm+4 -> Rm | null | void LDSMFPUL (int m) { FPUL = Read_32 (R[m]); R[m] += 4; PC += 2; } |
sts.l FPUL,@-Rn | 0100nnnn01010010 | Rn-4 -> Rn, FPUL -> (Rn) | Stores FPU system register FPUL in the destination. | void STSMFPUL (int n) { R[n] -= 4; Write_32 (R[n], FPUL); PC += 2; } |
frchg | 1111101111111101 | If FPSCR.PR = 0: ~FPSCR.FR -> FPSCR.FR Else: Undefined Operation | Inverts the FR bit in floating-point register FPSCR. When the FR bit in FPSCR is changed, FR0 to FR15 in FPR0_BANK0 to FPR15_BANK0 and FPR0_BANK1 to FPR15_BANK1 become XR0 to XR15, and XR0 to XR15 become FR0 to FR15. When FPSCR.FR = 0, FPR0_BANK0 to FPR15_BANK0 correspond to FR0 to FR15, and FPR0_BANK1 to FPR15_BANK1 correspond to XR0 to XR15. When FPSCR.FR = 1, FPR0_BANK1 to FPR15_BANK1 correspond to FR0 to FR15, and FPR0_BANK0 to FPR15_BANK0 correspond to XR0 to XR15. | void FRCHG (void) { if (FPSCR_PR == 0) { FPSCR ^= 0x00200000; // toggle bit 21 PC += 2; } else undefined_operation (); } |
fschg | 1111001111111101 | If FPSCR.PR = 0: ~FPSCR.SZ -> FPSCR.SZ Else: Undefined Operation | Inverts the SZ bit of the floating-point status register FPSCR. Changing the value of the SZ bit in FPSCR switches the amount of data for transfer by the FMOV instruction between one single-precision data and a pair of single-precision data. When FPSCR.SZ = 0, an FMOV instruction transfers a single-precision number. When FPSCR.SZ = 1, the FMOV instruction transfers a pair of single-precision numbers. | void FSCHG (void) { if (FPSCR_PR == 0) { FPSCR ^= 0x00100000; // toggle bit 20 PC += 2; } else undefined_operation (); } |
fpchg | 1111011111111101 | ~FPSCR.PR -> FPSCR.PR | Inverts the PR bit of the floating-point status register FPSCR. The value of this bit selects single-precision or double-precision operation. | void FPCHG (void) { FPSCR ^= 0x00080000; // toggle bit 19 PC += 2; } |
nopx | 1111000*0*0*00** | No operation | No access operation for X memory. | null |
stc GBR,Rn | 0000nnnn00010010 | GBR -> Rn | Stores control register GBR in the destination. | STCGBR (int n) { R[n] = GBR; PC += 2; } |
stc.l GBR,@-Rn | 0100nnnn00010011 | Rn-4 -> Rn, GBR -> (Rn) | Stores control register GBR in the destination. | void STCMGBR (int n) { R[n] -= 4; Write_32 (R[n], GBR); PC += 2; } |
stc VBR,Rn | 0000nnnn00100010 | VBR -> Rn | Stores control register VBR in the destination. | void STCVBR (int n) { R[n] = VBR; PC += 2; } |
stc.l VBR,@-Rn | 0100nnnn00100011 | Rn-4 -> Rn, VBR -> (Rn) | Stores control register VBR in the destination. | void STCMVBR (int n) { R[n] -= 4; Write_32 (R[n], VBR); PC += 2; } |
stc MOD,Rn | 0000nnnn01010010 | MOD -> Rn | Stores control register MOD in the destination. | void STCMOD (int n) { R[n] = MOD; PC += 2; } |
stc.l MOD,@-Rn | 0100nnnn01010011 | Rn-4 -> Rn, MOD -> (Rn) | Stores control register MOD in the destination. | void STCMMOD (int n) { R[n] -= 4; Write_32 (R[n], MOD); PC += 2; } |
stc RE,Rn | 0000nnnn01110010 | RE -> Rn | Stores control register RE in the destination. | void STCRE (int n) { R[n] = RE; PC += 2; } |