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dct pinc Sx,Dz | 111110********** 10011010xx00zzzz | If DC = 1: MSW of Sx + 1 -> MSW of Dz, clear LSW of Dz Else: nop | Conditionally adds 1 to the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated. | void pinc_sx_dct (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
dcf pcopy Sx,Dz | 111110********** 11011011xx00zzzz | If DC = 0: Sx -> Dz Else: nop | Conditionally stores the Sx operand in the Dz operand. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pcopy_sx_dcf (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_SRC2 = 0;
DSP_ALU_SRC2G = 0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 0)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
ldbank @Rm,R0 | 0100mmmm11100101 | (Specified register bank entry) -> R0 | The register bank entry indicated by the contents of general register Rm is transferred to general register R0. The register bank number and register stored in the bank are specified by general register Rm. | void LDBANK (int m) {
R[0] = Read_Bank_32 (R[m]);
PC += 2;
} |
ldc Rm,SR | 0100mmmm00001110 | Rm -> SR | Stores the source operand in the control register SR. | void LDCSR (int m) {
#if SH1 || SH2 || SH2 || SH3
SR = R[m] & 0x0FFF0FFF;
#elif SH2A
SR = R[m] & 0x000063F3;
#elif SH4 || SH4A
SR = R[m] & 0x700083F3;
#endif
PC += 2;
} |
ldc.l @Rm+,SR | 0100mmmm00000111 | (Rm) -> SR, Rm+4 -> Rm | Stores the source operand in the control register SR. | void LDCMSR (int m) {
#if SH1 || SH2 || SH2 || SH3
SR = Read_32 (R[m]) & 0x0FFF0FFF;
#elif SH2A
SR = Read_32 (R[m]) & 0x000063F3;
#elif SH4 || SH4A
SR = Read_32 (R[m]) & 0x700083F3;
#endif
R[m] += 4;
PC += 2;
} |
ldc Rm,TBR | 0100mmmm01001010 | Rm -> TBR | Stores a source operand in control register TBR. | void LDCTBR (int m) {
TBR = R[m];
PC += 2;
} |
ldc Rm,GBR | 0100mmmm00011110 | Rm -> GBR | Stores a source operand in control register GBR. | void LDCGBR (int m) {
GBR = R[m];
PC += 2;
} |
ldc.l @Rm+,GBR | 0100mmmm00010111 | (Rm) -> GBR, Rm+4 -> Rm | Stores a source operand in control register GBR. | void LDCMGBR (int m) {
GBR = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
ldc Rm,VBR | 0100mmmm00101110 | Rm -> VBR | Stores a source operand in control register VBR. | void LDCVBR (int m) {
VBR = R[m];
PC += 2;
} |
fmul FRm,FRn | 1111nnnnmmmm0010 | FRn * FRm -> FRn | Arithmetically multiplies the two single-precision floating-point numbers in FRn and FRm, and stores the result in FRn. | void FMUL (int m, int n) {
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
set_E ();
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
zero (n, sign_of (m) ^ sign_of (n));
break;
case PINF:
case NINF:
inf (n, sign_of (m) ^ sign_of (n));
break;
default:
normal_fmul (m, n);
break;
}
break;
case PZERO:
case NZERO:
switch (data_type_of (n))
{
case PINF:
case NINF:
invalid (n);
break;
default:
zero (n,sign_of (m) ^ sign_of (n));
break;
}
break;
case PINF:
case NINF:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
default:
inf (n, sign_of (m) ^ sign_of (n));
break
}
break;
}
} |
movx.w @Ax,Dx | 111100A*D*0*01** | (Ax) -> MSW of Dx, 0 -> LSW of Dx | Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for X memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros. | MOVX.W @R4,X0 ! Before execution: R4 = 0x08010000, @R4 = 0x5555, X0 = 0x12345678
! After execution: R4 = 0x08010000, X0 = 0x55550000 |
movx.w @Ax+,Dx | 111100A*D*0*10** | (Ax) -> MSW of Dx, 0 -> LSW of Dx, Ax+2 -> Ax | Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for X memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros. | MOVX.W @R4+,X0 ! Before execution: R4 = 0x08010000, @R4 = 0x5555, X0 = 0x12345678
! After execution: R4 = 0x08010002, X0 = 0x55550000 |
movx.w @Ax+Ix,Dx | 111100A*D*0*11** | (Ax) -> MSW of Dx, 0 -> LSW of Dx, Ax+Ix -> Ax | Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for X memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros. | null |
movx.w Da,@Ax | 111100A*D*1*01** | MSW of Da -> (Ax) | Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for X memory. The source word data is the top word of the register. | null |
movx.w Da,@Ax+ | 111100A*D*1*10** | MSW of Da -> (Ax), Ax+2 -> Ax | Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for X memory. The source word data is the top word of the register. | null |
movx.w Da,@Ax+Ix | 111100A*D*1*11** | MSW of Da -> (Ax), Ax+Ix -> Ax | Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for X memory. The source word data is the top word of the register. | null |
nopy | 111100*0*0*0**00 | No Operation | No access operation for Y memory. | null |
ldc.l @Rm+,DBR | 0100mmmm11110110 | (Rm) -> DBR, Rm+4 -> Rm | Stores a source operand in control register DBR. | void LDCMDBR (int m) {
DBR = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
ldc Rm,Rn_BANK | 0100mmmm1nnn1110 | Rm -> Rn_BANK (n = 0-7) | Stores a source operand in banked general register. Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0. | void LDCRn_BANK (int m) {
Rn_BANK = R[m];
PC += 2;
} |
ldc.l @Rm+,Rn_BANK | 0100mmmm1nnn0111 | (Rm) -> Rn_BANK, Rm+4 -> Rm | Stores a source operand in banked general register. Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0. | void LDCMRn_BANK (int m) {
Rn_BANK = Read_32 (R[m]);
R[m] += 4;
PC += 2;
} |
ldre @(disp,PC) | 10001110dddddddd | disp*2 + PC -> RE | Stores the effective address of the source operand in the repeat end register RE. The effective address is an address specified by PC + displacement. The PC is the address four bytes after this instruction. The 8-bit displacement is sign-extended and doubled. Consequently, the relative interval from the branch destination is -256 to +254 bytes. | void LDRE (int d) {
long disp;
if ((d & 0x80) == 0)
disp = (0x000000FF & (long)d);
else
disp = (0xFFFFFF00 | (long)d);
RE = PC + (disp << 1);
PC += 2;
} |
ldrs @(disp,PC) | 10001100dddddddd | disp*2 + PC -> RS | Stores the effective address of the source operand in the repeat start register RS. The effective address is an address specified by PC + displacement. The PC is the address four bytes after this instruction. The 8-bit displacement is sign-extended and doubled. Consequently, the relative interval from the branch destination is -256 to +254 bytes. | void LDRS (int d) {
long disp;
if ((d & 0x80) == 0)
disp = (0x000000FF & (long)d);
else
disp = (0xFFFFFF00 | (long)d);
RS = PC + (disp << 1);
PC += 2;
} |
lds Rm,MACH | 0100mmmm00001010 | Rm -> MACH | Stores the source operand into the system register MACH. | void LDSMACH (int m) {
MACH = R[m];
#if SH1
if ((MACH & 0x00000200) == 0)
MACH &= 0x000003FF;
else
MACH |= 0xFFFFFC00;
#endif
PC += 2;
} |
lds.l @Rm+,MACH | 0100mmmm00000110 | (Rm) -> MACH, Rm+4 -> Rm | Stores the source operand into the system register MACH. | void LDSMMACH (int m) {
MACH = Read_32 (R[m]);
#if SH1
if ((MACH & 0x00000200) == 0)
MACH &= 0x000003FF;
else
MACH |= 0xFFFFFC00;
#endif
R[m] += 4;
PC += 2;
} |
movy.w @Ay,Dy | 111100*A*D*0**01 | (Ay) -> MSW of Dy, 0 -> LSW of Dy | Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for Y memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros. | null |
movy.w @Ay+,Dy | 111100*A*D*0**10 | (Ay) -> MSW of Dy, 0 -> LSW of Dy, Ay+2 -> Ay | Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for Y memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros. | null |
movy.w @Ay+Iy,Dy | 111100*A*D*0**11 | (Ay) -> MSW of Dy, 0 -> LSW of Dy, Ay+Iy -> Ay | Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for Y memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros. | null |
movy.w Da,@Ay | 111100*A*D*1**01 | MSW of Da -> (Ay) | Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for Y memory. The source word data is the top word of the register. | null |
movy.w Da,@Ay+ | 111100*A*D*1**10 | MSW of Da -> (Ay), Ay+2 -> Ay | Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for Y memory. The source word data is the top word of the register. | null |
pinc Sy,Dz | 111110********** 1011100100yyzzzz | MSW of Sy + 1 -> MSW of Dz, clear LSW of Dz | Adds 1 to the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pinc_sy (void) {
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
#include "integer_unconditional_update.c"
#include "integer_plus_dc_bit.c"
} |
pdec Sx,Dz | 111110********** 10001001xx00zzzz | MSW of Sx - 1 -> MSW of Dz, clear LSW of Dz | Subtracts 1 from the top word of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pdec_sx (void) {
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
#include "integer_unconditional_update.c"
#include "integer_minus_dc_bit.c"
} |
movy.w @Ay,Dy | 111100*A*D*0**01 | (Ay) -> MSW of Dy, 0 -> LSW of Dy | Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for Y memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros. | null |
movy.w @Ay+,Dy | 111100*A*D*0**10 | (Ay) -> MSW of Dy, 0 -> LSW of Dy, Ay+2 -> Ay | Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for Y memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros. | null |
movy.w @Ay+Iy,Dy | 111100*A*D*0**11 | (Ay) -> MSW of Dy, 0 -> LSW of Dy, Ay+Iy -> Ay | Transfers the memory source operand data to the destination register operand. The transferred data can only be word length for Y memory. The word data is loaded to the top word of the register and the bottom word is cleared with zeros. | null |
movy.w Da,@Ay | 111100*A*D*1**01 | MSW of Da -> (Ay) | Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for Y memory. The source word data is the top word of the register. | null |
movy.w Da,@Ay+ | 111100*A*D*1**10 | MSW of Da -> (Ay), Ay+2 -> Ay | Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for Y memory. The source word data is the top word of the register. | null |
movy.w Da,@Ay+Iy | 111100*A*D*1**11 | MSW of Da -> (Ay), Ay+Iy -> Ay | Transfers the register source operand data to the destination memory operand. The transferred data can only be word length for Y memory. The source word data is the top word of the register. | null |
movs.w @-As,Ds | 111101AADDDD0000 | As-2 -> As, (As) -> MSW of Ds, 0 -> LSW of Ds | Transfers the source operand data to the destination. The transferred data is a word, the word data is loaded to the top word of the register and the bottom word is cleared with zeros. When the destination operand is a register with guard bits, the sign is extended and stored in the guard bits. | null |
exts.w Rm,Rn | 0110nnnnmmmm1111 | Rm sign-extended from word -> Rn | Sign-extends the contents of general register Rm and stores the result in Rn. The value of Rm bit 15 is transferred to Rn bits 16 to 31. | void EXTSW (int m, int n) {
R[n] = R[m];
if ((R[m] & 0x00008000) == 0)
R[n] & = 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
PC += 2;
} |
extu.b Rm,Rn | 0110nnnnmmmm1100 | Rm zero-extended from byte -> Rn | Zero-extends the contents of general register Rm and stores the result in Rn. 0 is transferred to Rn bits 8 to 31. | void EXTUB (int m, int n) {
R[n] = R[m];
R[n] &= 0x000000FF;
PC += 2;
} |
extu.w Rm,Rn | 0110nnnnmmmm1101 | Rm zero-extended from word -> Rn | Zero-extends the contents of general register Rm and stores the result in Rn. 0 is transferred to Rn bits 16 to 31. | void EXTUW (int m, int n) {
R[n] = R[m];
R[n] &= 0x0000FFFF;
PC += 2;
} |
mac.l @Rm+,@Rn+ | 0000nnnnmmmm1111 | Signed, (Rn) * (Rm) + MAC -> MAC 32 * 32 + 64 -> 64 bits | Performs signed multiplication of the 32-bit operands whose addresses are the contents of general registers Rm and Rn, adds the 64-bit result to the MAC register contents, and stores the result in the MAC register. Operands Rm and Rn are each incremented by 4 each time they are read. When the S bit is cleared to 0, the 64-bit result is stored in the coupled MACH and MACL registers. When bit S is set to 1, addition to the MAC register is a saturation operation of 48 bits starting from the LSB. For the saturation operation, only the lower 48 bits of the MACL register are enabled and the result is limited to a range of 0xFFFF800000000000 (minimum) and 0x00007FFFFFFFFFFF (maximum). | void MACL (int m, int n) {
unsigned long RnL, RnH, RmL, RmH, Res0, Res1, Res2;
unsigned long temp0, temp1, temp2, temp3;
long tempm, tempn, fnLmL;
tempn = Read_32 (R[n]);
R[n] += 4;
tempm = Read_32 (R[m]);
R[m] += 4;
if ((long)(tempn ^ tempm) < 0)
fnLmL = -1;
else
fnLmL = 0;
if (tempn < 0)
tempn = 0 - tempn;
if (tempm < 0)
tempm = 0 - tempm;
temp1 = (unsigned long)tempn;
temp2 = (unsigned long)tempm;
RnL = temp1 & 0x0000FFFF;
RnH = (temp1 >> 16) & 0x0000FFFF;
RmL = temp2 & 0x0000FFFF;
RmH = (temp2 >> 16) & 0x0000FFFF;
temp0 = RmL * RnL;
temp1 = RmH * RnL;
temp2 = RmL * RnH;
temp3 = RmH * RnH;
Res2 = 0;
Res1 = temp1 + temp2;
if (Res1 < temp1)
Res2 += 0x00010000;
temp1 = (Res1 << 16) & 0xFFFF0000;
Res0 = temp0 + temp1;
if (Res0 < temp0)
Res2++;
Res2 = Res2 + ((Res1 >> 16) & 0x0000FFFF) + temp3;
if(fnLmL < 0)
{
Res2 = ~Res2;
if (Res0 == 0)
Res2++;
else
Res0 = (~Res0) + 1;
}
if (S == 1)
{
Res0 = MACL + Res0;
if (MACL > Res0)
Res2++;
Res2 += MACH & 0x0000FFFF;
if (((long)Res2 < 0) && (Res2 < 0xFFFF8000))
{
Res2 = 0xFFFF8000;
Res0 = 0x00000000;
}
if (((long)Res2 > 0) && (Res2 > 0x00007FFF))
{
Res2 = 0x00007FFF;
Res0 = 0xFFFFFFFF;
}
MACH = (Res2 & 0x0000FFFF) | (MACH & 0xFFFF0000);
MACL = Res0;
}
else
{
Res0 = MACL + Res0;
if (MACL > Res0)
Res2 ++;
Res2 += MACH;
MACH = Res2;
MACL = Res0;
}
PC += 2;
} |
fcmp/eq DRm,DRn | 1111nnn0mmm00100 | If DRn = DRm: 1 -> T
Else: 0 -> T | Arithmetically compares the two double-precision floating-point numbers in DRn and DRm, and stores 1 in the T bit if they are equal, or 0 otherwise. | void FCMP_EQ (int m, int n)
{
PC += 2;
clear_cause ();
if (fcmp_chk_double (m, n) == INVALID)
fcmp_invalid ();
else if (fcmp_chk_double (m, n) == EQ)
T = 1;
else
T = 0;
}
int fcmp_chk_double (int m, int n)
{
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
return INVALID;
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
return UO;
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case PINF:
return GT;
case NINF:
return LT;
default:
break;
}
break;
case PZERO:
case NZERO:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
return EQ;
default:
break;
}
break;
case PINF:
switch (data_type_of (n))
{
case PINF:
return EQ;
default:
return LT;
}
case NINF:
switch (data_type_of (n))
{
case NINF:
return EQ;
default:
return GT;
}
}
if (DR[n >> 1] == DR[m >> 1])
return EQ;
else if (DR[n >> 1] > DR[m >> 1])
return GT;
else
return LT;
}
void fcmp_invalid (void)
{
set_V ();
if ((FPSCR & ENABLE_V) == 0)
T = 0;
else
fpu_exception_trap ();
} |
pdec Sy,Dz | 111110********** 1010100100yyzzzz | MSW of Sy - 1 -> MSW of Dz, clear LSW of Dz | Subtracts 1 from the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pdec_sy (void) {
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
#include "integer_unconditional_update.c"
#include "integer_minus_dc_bit.c"
} |
shlr8 Rn | 0100nnnn00011001 | Rn >> 8 -> [0 -> Rn] | Logically shifts the contents of general register Rn 8 bits to the right, and stores the result in Rn. The bits shifted out of the operand are discarded. | void SHLR8 (int n) {
R[n] >>= 8;
R[n] &= 0x00FFFFFF;
PC += 2;
} |
shlr16 Rn | 0100nnnn00101001 | Rn >> 16 -> [0 -> Rn] | Logically shifts the contents of general register Rn 16 bits to the right and stores the result in Rn. The bits shifted out of the operand are discarded. | void SHLR16 (int n) {
R[n] >>= 16;
R[n] &= 0x0000FFFF;
PC += 2;
} |
bf label | 10001011dddddddd | If T = 0: disp*2 + PC + 4 -> PC
Else: nop | This is a conditional branch instruction that references the T bit. The branch is taken if T = 0, and not taken if T = 1. The branch destination is address (PC + 4 + displacement * 2). The PC source value is the BF instruction address. As the 8-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -256 to +254 bytes from the BF instruction. | void BF (int d) {
int disp;
if ((d & 0x80) == 0)
disp = (0x000000FF & d);
else
disp = (0xFFFFFF00 | d);
if (T == 0)
PC = PC + 4 + (disp << 1);
else
PC += 2;
} |
bf/s label | 10001111dddddddd | If T = 0: disp*2 + PC + 4 -> PC
Else: nop
(Delayed branch) | This is a delayed conditional branch instruction that references the T bit. If T = 1, the next instruction is executed and the branch is not taken. If T = 0, the branch is taken after execution of the next instruction. | void BFS (int d) {
int disp;
unsigned int temp;
temp = PC;
if ((d & 0x80) == 0)
disp = (0x000000FF & d);
else
disp = (0xFFFFFF00 | d);
if (T == 0)
PC = PC + 4 + (disp << 1);
else
PC += 4;
Delay_Slot (temp + 2);
} |
bt label | 10001001dddddddd | If T = 1: disp*2 + PC + 4 -> PC
Else: nop | This is a conditional branch instruction that references the T bit. The branch is taken if T = 1, and not taken if T = 0. The branch destination is address (PC + 4 + displacement * 2). The PC source value is the BT instruction address. As the 8-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -256 to +254 bytes from the BT instruction. | void BT (int d) {
int disp;
if ((d & 0x80) == 0)
disp = (0x000000FF & d);
else
disp = (0xFFFFFF00 | d);
if (T == 1)
PC = PC + 4 + (disp << 1);
else
PC += 2;
} |
bt/s label | 10001101dddddddd | If T = 1: disp*2 + PC + 4 -> PC
Else: nop
(Delayed branch) | This is a conditional branch instruction that references the T bit. The branch is taken if T = 1, and not taken if T = 0. The PC source value is the BT/S instruction address. As the 8-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -256 to +254 bytes from the BT/S instruction. | void BTS (int d) {
int disp;
unsigned temp;
temp = PC;
if ((d & 0x80) == 0)
disp = (0x000000FF & d);
else
disp = (0xFFFFFF00 | d);
if (T == 1)
PC = PC + 4 + (disp << 1);
else
PC += 4;
Delay_Slot (temp + 2);
} |
bra label | 1010dddddddddddd | disp*2 + PC + 4 -> PC
(Delayed branch) | This is an unconditional branch instruction. The branch destination is address (PC + 4 + displacement * 2). The PC source value is the BRA instruction address. As the 12-bit displacement is multiplied by two after sign-extension, the branch destination can be located in the range from -4096 to +4094 bytes from the BRA instruction. If the branch destination cannot be reached, this branch can be performed with a JMP instruction. | void BRA (int d) {
int disp;
unsigned int temp;
temp = PC;
if ((d & 0x800) == 0)
disp = (0x00000FFF & d);
else
disp = (0xFFFFF000 | d);
PC = PC + 4 + (disp << 1);
Delay_Slot(temp + 2);
} |
movs.l Ds,@As+ | 111101AADDDD1011 | Ds -> (As), As+4 -> As | Transfers the source operand data to the destination. The transferred data is a longword. | null |
movs.l Ds,@As+Is | 111101AADDDD1111 | Ds -> (As), As+Is -> As | Transfers the source operand data to the destination. The transferred data is a longword. | null |
pabs Sx,Dz | 111110********** 10001000xx00zzzz | If Sx >= 0: Sx -> Dz
If Sx < 0: 0 - Sx -> Dz | Finds absolute values. When the Sx operand is positive, the contents of the operand are transferred to the Dz operand. If the value is negative, the value of the Sx operand is subtracted from 0 and stored in the Dz operand. | null |
pabs Sy,Dz | 111110********** 1010100000yyzzzz | If Sy >= 0: Sy -> Dz
If Sy < 0: 0 - Sy -> Dz | Finds absolute values. When the Sy operand is positive, the contents of the operand are transferred to the Dz operand. If the value is negative, the value of the Sy operand is subtracted from 0 and stored in the Dz operand. | null |
padd Sx,Sy,Dz | 111110********** 10110001xxyyzzzz | Sx + Sy -> Dz | Adds the contents of the Sx and Sy operands and stores the result in the Dz operand. | null |
dcf pdec Sy,Dz | 111110********** 1010101100yyzzzz | If DC = 0: MSW of Sy - 1 -> MSW of DZ, clear LSW of Dz Else: nop | Conditionally subtracts 1 from the top word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. The instruction is executed if the DC bit is set to 0. The DC, N, Z, V, and GT bits are not updated. | void pdec_sy_dcf (void) {
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
fmov DRm,DRn | 1111nnn0mmm01100 | DRm -> DRn | Transfers DRm contents to DRn. | void FMOV_DR (int m, int n) {
DR[n >> 1] = DR[m >> 1];
PC += 2;
} |
fmov DRm,XDn | 1111nnn1mmm01100 | DRm -> XDn | Transfers DRm contents to XDn. | void FMOV_DRXD (int m, int n) {
XD[n >> 1] = DR[m >> 1];
PC += 2;
} |
fmov XDm,DRn | 1111nnn0mmm11100 | XDm -> DRn | Transfers XDm contents to DRn. | void FMOV_XDDR (int m, int n) {
DR[n >> 1] = XD[m >> 1];
PC += 2;
} |
fmov XDm,XDn | 1111nnn1mmm11100 | XDm -> XDn | Transfers XDm contents to XDn. | void FMOV_XDXD (int m, int n) {
XD[n >> 1] = XD[m >> 1];
PC += 2;
} |
fmov.d @Rm,DRn | 1111nnn0mmmm1000 | (Rm) -> DRn | Transfers contents of memory at address indicated by Rm to DRn. | void FMOV_LOAD_DR (int m, int n) {
DR[n >> 1] = Read_64 (R[m]);
PC += 2;
} |
fmov.d @Rm,XDn | 1111nnn1mmmm1000 | (Rm) -> XDn | Transfers contents of memory at address indicated by Rm to XDn. | void FMOV_LOAD_XD (int m, int n) {
XD[n >> 1] = Read_64 (R[m]);
PC += 2;
} |
fmov.d DRm,@Rn | 1111nnnnmmm01010 | DRm -> (Rn) | Transfers DRm contents to memory at address indicated by Rn. | void FMOV_STORE_DR (int m, int n) {
Write_64 (R[n], DR[m >> 1]);
PC += 2;
} |
pclr Dz | 111110********** 100011010000zzzz | 0x00000000 -> Dz | Clears the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The Z bit of the DSR register is set to 1. The N, V, and GT bits are cleared to 0. | void pclr (void) {
DSP_REG[ex2_dz_no] = 0x0;
if (ex2_dz_no == 0)
A0G = 0x0;
else if (ex2_dz_no == 1)
A1G = 0x0;
carry_bit = 0;
negative_bit = 0;
zero_bit = 1;
overflow_bit = 0;
#include "fixed_pt_plus_dc_bit.c"
} |
prnd Sx,Dz | 111110********** 10011000xx00zzzz | Sx + 0x00008000 -> Dz, clear LSW of Dz | Does rounding. Adds the immediate data 0x00008000 to the contents of the Sx operand, stores the result in the upper word of the Dz operand, and clears the bottom word of Dz with zeros. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void prnd_sx (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST = (DSP_ALU_SRC1 + DSP_ALU_SRC2) & MASKFFFF0000;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_plus_dc_bit.c"
} |
fsub FRm,FRn | 1111nnnnmmmm0001 | FRn - FRm -> FRn | Arithmetically subtracts the single-precision floating-point number in FRm from the single-precision floating-point number in FRn, and stores the result in FRn. | void FSUB (int m, int n) {
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
set_E ();
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case NORM:
normal_faddsub (m, n, SUB);
break;
case PZERO:
case NZERO:
register_copy (m, n);
FR[n] = -FR[n];
break;
default:
break;
}
break;
case PZERO:
break;
case NZERO:
switch (data_type_of (n))
{
case NZERO:
zero (n, 0);
break;
default:
break;
}
break;
case PINF:
switch (data_type_of (n))
{
case PINF:
invalid (n);
break;
default:
inf (n, 1);
break;
}
break;
case NINF:
switch (data_type_of (n))
{
case NINF:
invalid (n);
break;
default:
inf (n, 0);
break;
}
break;
}
} |
dct pdmsb Sy,Dz | 111110********** 1011111000yyzzzz | If DC = 1: Sy data MSB position -> MSW of Dz, clear LSW of Dz Else: nop | Conditionally finds the first position to change in the lineup of Sy operand bits and stores the bit position in the Dz operand. The instruction is executed if the DC bit is set to 1. The DC, N, Z, V, and GT bits are not updated. | void pdmsb_sy_dct (void) {
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
} |
dct pclr Dz | 111110********** 100011100000zzzz | If DC = 1: 0x00000000 -> Dz
Else: nop | Conditionally clears the Dz operand. The instruction is executed when the DC
bit is set to 1. The DC, N, Z, V, and GT bits are not updated. | void pclr_dct (void)
{
if (DC == 1)
DSP_REG[ex2_dz_no] = 0x0;
} |
fmov.d DRm,@(R0,Rn) | 1111nnnnmmm00111 | DRm -> (R0 + Rn) | Transfers DRm contents to memory at address indicated by (R0 + Rn). | void FMOV_INDEX_STORE_DR (int m, int n)
{
Write_64 (R[0] + R[n], DR[m >> 1]);
PC += 2;
} |
fmov.d XDm,@(R0,Rn) | 1111nnnnmmm10111 | XDm -> (R0 + Rn) | Transfers XDm contents to memory at address indicated by (R0 + Rn). | void FMOV_INDEX_STORE_XD (int m, int n)
{
Write_64 (R[0] + R[n], XD[m >> 1]);
PC += 2;
} |
fmov.d @(disp12,Rm),DRn | 0011nnn0mmmm0001 0111dddddddddddd | (disp*8 + Rm) -> DRn | Transfers memory contents at the address indicated by (disp + Rn) to DRn. | void FMOV_INDEX_DISP12_LOAD_DR (int m, int n, int d)
{
long disp = (0x00000FFF & (long)d);
DR[n >> 1] = Read_64 (R[m] + (disp << 3));
PC += 4;
} |
fmov.d DRm,@(disp12,Rn) | 0011nnnnmmm00001 0011dddddddddddd | DRm -> (disp*8 + Rn) | Transfers DRm contents to memory at the address indicated by (disp + Rn). | void FMOV_INDEX_DISP12_STORE_DR (int m, int n, int d)
{
long disp = (0x00000FFF & (long)d);
Write_64 (R[n] + (disp << 3), DR[m >> 1]);
PC += 4;
} |
fldi0 FRn | 1111nnnn10001101 | 0x00000000 -> FRn | When FPSCR.PR = 0, this instruction loads floating-point 0.0 (0x00000000) into FRn. If FPSCR.PR = 1, the instruction is handled as an illegal instruction. | void FLDI0 (int n)
{
FR[n] = 0x00000000;
PC += 2;
} |
fldi1 FRn | 1111nnnn10011101 | 0x3F800000 -> FRn | When FPSCR.PR = 0, this instruction loads floating-point 1.0 (0x3F800000) into FRn. If FPCSR.PR = 1, the instruction is handled as an illegal instruction. | void FLDI1 (int n)
{
FR[n] = 0x3F800000;
PC += 2;
} |
flds FRm,FPUL | 1111mmmm00011101 | FRm -> FPUL | Transfers the contents of floating-point register FRm into system register FPUL. | void FLDS (int m)
{
FPUL = FR[m];
PC += 2;
} |
sets | 0000000001011000 | 1 -> S | Sets the S bit to 1. | void SETS (void)
{
S = 1;
PC += 2;
} |
sett | 0000000000011000 | 1 -> T | Sets the T bit to 1. | void SETT (void)
{
T = 1;
PC += 2;
} |
sleep | 0000000000011011 | Sleep or standby | Places the CPU in the power-down state. | void SLEEP (void)
{
Sleep_standby();
} |
stbank R0,@Rn | 0100nnnn11100001 | R0 -> (specified register bank entry) | R0 is transferred to the register bank entry indicated by the contents of general register Rn. | void STBANK (int n)
{
Write_Bank_32 (R[n], R[0])
PC += 2;
} |
stc SR,Rn | 0000nnnn00000010 | SR -> Rn | Stores control register SR in the destination. | void STCSR (int n)
{
R[n] = SR;
PC += 2;
} |
stc.l SR,@-Rn | 0100nnnn00000011 | Rn-4 -> Rn, SR -> (Rn) | Stores control register SR in the destination. | void STCMSR (int n)
{
R[n] -= 4;
Write_32 (R[n], SR);
PC += 2;
} |
stc TBR,Rn | 0000nnnn01001010 | TBR -> Rn | Stores control register TBR in the destination. | void STCTBR (int n)
{
R[n] = TBR;
PC += 2;
} |
cmp/eq Rm,Rn | 0011nnnnmmmm0000 | If Rn = Rm: 1 -> T Else: 0 -> T | Compares general registers Rn and Rm, and sets the T bit if they are equal. The contents of Rn and Rm are not changed. | void CMPEQ (int m, int n) { if (R[n] == R[m]) T = 1; else T = 0; PC += 2; } |
cmp/hs Rm,Rn | 0011nnnnmmmm0010 | If Rn >= Rm (unsigned): 1 -> T Else: 0 -> T | Compares general registers Rn and Rm, and sets the T bit if Rn is greater or equal Rm. The values for the comparison are interpreted as unsigned integer values. The contents of Rn and Rm are not changed. | void CMPHI (int m, int n) { if ((unsigned long)R[n] >= (unsigned long)R[m]) T = 1; else T = 0; PC += 2; } |
cmp/ge Rm,Rn | 0011nnnnmmmm0011 | If Rn >= Rm (signed): 1 -> T Else: 0 -> T | Compares general registers Rn and Rm, and sets the T bit if Rn is greater or equal Rm. The values for the comparison are interpreted as signed integer values. The contents of Rn and Rm are not changed. | void CMPGE (int m, int n) { if ((long)R[n] >= (long)R[m]) T = 1; else T = 0; PC += 2; } |
cmp/hi Rm,Rn | 0011nnnnmmmm0110 | If Rn > Rm (unsigned): 1 -> T Else: 0 -> T | Compares general registers Rn and Rm, and sets the T bit if Rn is greater Rm. The values for the comparison are interpreted as unsigned integer values. The contents of Rn and Rm are not changed. | void CMPHI (int m, int n) { if ((unsigned long)R[n] > (unsigned long)R[m]) T = 1; else T = 0; PC += 2; } |
cmp/gt Rm,Rn | 0011nnnnmmmm0111 | If Rn > Rm (signed): 1 -> T Else: 0 -> T | Compares general registers Rn and Rm, and sets the T bit if Rn is greater Rm. The values for the comparison are interpreted as signed integer values. The contents of Rn and Rm are not changed. | void CMPGT (int m, int n) { if ((long)R[n] > (long)R[m]) T = 1; else T = 0; PC += 2; } |
cmp/pl Rn | 0100nnnn00010101 | If Rn > 0 (signed): 1 -> T Else: 0 -> T | Compares general register Rn and sets the T bit if Rn is greater 0. The value in Rn for the comparison is interpreted as signed integer. The contents of Rn are not changed. | void CMPPL (int n) { if ((long)R[n] > 0) T = 1; else T = 0; PC += 2; } |
cmp/pz Rn | 0100nnnn00010001 | If Rn >= 0 (signed): 1 -> T Else: 0 -> T | Compares general register Rn and sets the T bit if Rn is greater or equal 0. The value in Rn for the comparison is interpreted as signed integer. The contents of Rn are not changed. | void CMPPZ (int n) { if ((long)R[n] >= 0) T = 1; else T = 0; PC += 2; } |
ocbwb @Rn | 0000nnnn10110011 | Write back operand cache block | Accesses data using the contents indicated by effective address Rn. If the cache is hit and there is unwritten information (U bit = 1), the corresponding cache block is written back to external memory and that block is cleaned (the U bit is cleared to 0). In other cases (i.e. in the case of a cache miss or an access to a non-cache area, or if the block is already clean), no operation is performed. | void OCBWB (int n) {
if (is_dirty_block (R[n]))
write_back (R[n]);
PC += 2;
} |
pref @Rn | 0000nnnn10000011 | (Rn) -> operand cache | SH4 and SH4A: Reads a 32-byte data block starting at a 32-byte boundary into the operand cache. The lower 5 bits of the address specified by Rn are masked to zero. This instruction is also used to trigger a Store Queue write-back operation if the specified address points to the Store Queue area. For more information refer to Store Queues in the manual. SH3 and SH2A: Reads a 16-byte data block into the cache. The address specified by Rn should be on 32-bit boundary. No address related error is detected in this instruction. In case of an error, the instruction operates as NOP. Note: On products with no cache, this instruction is handled as a NOP instruction. | void PREF (int n) {
prefetch_operand_cache_block (R[n]);
PC += 2;
} |
prefi @Rn | 0000nnnn11010011 | Reads 32-byte instruction block into instruction cache | Reads a 32-byte block of data starting at a 32-byte boundary within the instruction cache. The lower 5 bits of the address specified by Rn are masked by zeroes. This instruction does not generate data address error and MMU exceptions. In the event of an error, the PREFI instruction is treated as an NOP (no operation) instruction. When the address to be prefetched is missing from UTLB or is protected, the PREFI instruction is treated as an NOP instruction and a TLB exception does not occur. Note: This instruction can be used before the SLEEP command is issued to prefetch instructions for execution on return from the SLEEP state. | void PREFI (int n) {
prefetch_instruction_cache_block (R[n]);
PC += 2;
} |
resbank | 0000000001011011 | Bank -> R0 to R14, GBR, MACH, MACL, PR | Restores the last register saved to a register bank. Note: The issue cycle count is 19 when a bank overflow has occured and the registers are restored from the stack. | void RESBANK (void) {
int m; // Number of register bank to which a save was last performed.
if (BO == 0)
{
PR = Register_Bank[m].PR_BANK;
GBR = Register_Bank[m].GBR_BANK;
MACL = Register_Bank[m].MACL_BANK;
MACH = Register_Bank[m].MACH_BANK;
for (int i = 0; i <= 14; i++)
R[i] = Register_Bank[m].R_BANK[i];
}
else
{
for (int i = 0; i <= 14; i++)
{
R[i] = Read_32 (R[15]);
R[15] += 4;
}
PR = Read_32 (R[15]);
R[15] += 4;
GBR = Read_32 (R[15]);
R[15] += 4;
MACH = Read_32 (R[15]);
R[15] += 4;
MACL = Read_32 (R[15]);
R[15] += 4;
}
PC += 2;
} |
pcopy Sx,Dz | 111110********** 11011001xx00zzzz | Sx -> Dz | Stores the Sx operand in the Dz operand. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits are also updated. | void pcopy_sx (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_SRC2 = 0;
DSP_ALU_SRC2G = 0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_plus_dc_bit.c"
} |
pand Sx,Sy,Dz | 111110********** 10010101xxyyzzzz | Sx & Sy -> Dz, clear LSW of Dz | Does an AND of the upper word of the Sx operand and the upper word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. When Dz is a register that has guard bits, the guard bits are also zeroed. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pand (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW & DSP_ALU_SRC2_HW;
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no == 1)
A1G = 0x0;
carry_bit = 0x0;
negative_bit = DSP_ALU_DST_MSB;
zero_bit = (DSP_ALU_DST_HW == 0);
overflow_bit = 0x0;
#include "logical_dc_bit.c"
} |
pand Sx,Sy,Dz | 111110********** 10010101xxyyzzzz | Sx & Sy -> Dz, clear LSW of Dz | Does an AND of the upper word of the Sx operand and the upper word of the Sy operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the Dz operand with zeros. When Dz is a register that has guard bits, the guard bits are also zeroed. The DC bit of the DSR register is updated according to the specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. | void pand (void) {
switch (EX2_SX) {
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY) {
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW & DSP_ALU_SRC2_HW;
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no == 1)
A1G = 0x0;
carry_bit = 0x0;
negative_bit = DSP_ALU_DST_MSB;
zero_bit = (DSP_ALU_DST_HW == 0);
overflow_bit = 0x0;
#include "logical_dc_bit.c"
} |
fschg | 1111001111111101 | If FPSCR.PR = 0: ~FPSCR.SZ -> FPSCR.SZ
Else: Undefined Operation | Inverts the SZ bit of the floating-point status register FPSCR. Changing the value of the SZ bit in FPSCR switches the amount of data for transfer by the FMOV instruction between one single-precision data and a pair of single-precision data. When FPSCR.SZ = 0, an FMOV instruction transfers a single-precision number. When FPSCR.SZ = 1, the FMOV instruction transfers a pair of single-precision numbers. | void FSCHG (void)
{
if (FPSCR_PR == 0)
{
FPSCR ^= 0x00100000; // toggle bit 20
PC += 2;
}
else
undefined_operation ();
} |
fpchg | 1111011111111101 | ~FPSCR.PR -> FPSCR.PR | Inverts the PR bit of the floating-point status register FPSCR. The value of this bit selects single-precision or double-precision operation. | void FPCHG (void)
{
FPSCR ^= 0x00080000; // toggle bit 19
PC += 2;
} |
fmul DRm,DRn | 1111nnn0mmm00010 | DRn * DRm -> DRn | Arithmetically multiplies the two double-precision floating-point numbers in DRn and DRm, and stores the result in FRn. | void FMUL (int m, int n) {
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
set_E ();
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
zero (n, sign_of (m) ^ sign_of (n));
break;
case PINF:
case NINF:
inf (n, sign_of (m) ^ sign_of (n));
break;
default:
normal_fmul (m, n);
break;
}
break;
case PZERO:
case NZERO:
switch (data_type_of (n))
{
case PINF:
case NINF:
invalid (n);
break;
default:
zero (n,sign_of (m) ^ sign_of (n));
break;
}
break;
case PINF:
case NINF:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
default:
inf (n, sign_of (m) ^ sign_of (n));
break
}
break;
}
} |