Talk:Instruction cycle

message: is this even accurate? User_talk:212.219.142.161
Not clear at point 3 ("indirect address" is vague) User_talk:87.5.218.102
:True, shouldn't that be direct address, anyway? Olivia Guest 14:18, 23 December 2006 (UTC)
replies: text: Actually, I've found other articles with the correct cycles. I'll clean this page up later. falsedef 23:21, 18 January 2007 (UTC)

text: Indeed, there is also a lot of vandalism going on, maybe someone can clean this up and perhaps lock the page? User:Anonymous 11:45, 07 March 2010 (UTC)
thread_title:  Accuracy 

message: Why does it start at 2?? What happened to the all important 1? Anyone?
Antonyh3 (talk) 01:58, 9 November 2010 (UTC)
thread_title:  Instruction cycle 

message: The Zilog Z80 article mentions "T-cycles".
The Intel 8008 article mentions "T-states".
Are they really the same thing?
Should this instruction cycle explain what those states are?
--DavidCary (talk) 03:51, 19 August 2011 (UTC)
replies: text: According to their articles, a Z80 t-cycle is one clock cycle and a 8008 t-state is two clock cycles.  So no, they're different.  They are specific to those machines, and don't belong here. -R. S. Shaw (talk) 06:24, 21 August 2011 (UTC)
thread_title:  T-cycle 

message: I am not a regular wikipedia author and am busy writing at the moment (sorry that I am not just editing the article directly). For my research I tracked down what I believe to be source material for fetch-decode-execute paradigm. It would be nice if someone could include a citation for it: 
J. Holland. A universal computer capable of executing an arbitrary number of sub-programs simultaneously. In Papers presented at the December 1-3, 1959, eastern joint IRE-AIEE-ACM computer conference, IRE-AIEE-ACM ’59 (Eastern), pages 108–113, New York, NY, USA, 1959. ACM.  — Preceding unsigned comment added by Infinitesteps (talk • contribs) 20:12, 11 November 2012 (UTC)
thread_title:  Original Source 

message: I don't know how to call in an expert from the Wikipedia project Computer Science, but do you think this is a good idea?  Halp.  — Preceding unsigned comment added by 66.205.158.7 (talk) 19:50, 17 February 2013 (UTC)
thread_title:  Experts 

message: To my mind, this case should be covered in the article, since it is a special yet very common operation to be performed. Thanks! --2001:638:501:4246:6257:18FF:FEF1:52BB (talk) 19:31, 15 February 2016 (UTC)
thread_title:  What happens with PC on JUMP instruction? 

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thread_title:  External links modified 

message: the article doesn't even mention or distinguish microcode? needs serious help. 2604:2000:EED4:A00:0:0:0:2 (talk) 05:33, 1 December 2016 (UTC)
thread_title:  Microcode? 

message: In the diagram, the 5th step is "MAR contents to CIR", should this be MDR instead, since the MAR just holds a memory address whilst CIR holds actual instructions?
123.243.171.231 (talk) 04:32, 15 October 2017 (UTC)
thread_title:  Flowchart accuracy 

message: In the fetch cycle,
*The CPU copies the contents of the PC to MAR prepared for instruction loading.
*The memory loads the instruction specified in MAR to MBR/MDR.
*The CPU copies the instruction from MBR to IR for instruction decoding.
*The CPU increments the PC to point to the next instruction.
In the execute cycle,
*To fetch data from memory, CPU generates the address to the MAR and data transfers to the MBR.
*IR sends out the appropriate control signals to cause data to be moved from one register to another or an operation to be performed by the ALU taking data from registers.
*To write data back to memory, CPU copies the result of the ALU to the MBR. CPU then generates the address and copies to MAR.
*The data bus loads the data from MBR to the memory location specified by MAR.
Twnhotel (talk) 06:54, 6 June 2018 (UTC)
thread_title:  CPU performing steps when each instruction has at most one data fetch and one data write back