Talk:Cache coherence

message: Text on this page is word for word identical this: http://www.numascale.com/directory-based.html - which of course may be copied from Wikipedia (but no acknowledgement is given). Either way I suspect this page could be rewritten. 81.178.193.87 (talk) 19:12, 17 November 2012 (UTC)
thread_title: Copyright/licensing issue

message: This article should not be merged with cache. Cache coherency is a distinct topic. Dennis 20:01, 18 Dec 2004 (UTC)
thread_title: Merge

message: Whoever wrote this needs to go back and make a couple of changes:
1.  Cache consistency != cache coherency
Coherency has to do with what values can be returned from a read, consistency has to do with the propagation of writes and when written values can/will be returned by a read.  Read Hennessey and Patteron's book Ch6 to get an overview.
2.  It might be nice to give some different examples of different CC protocols.  The three major families of protocols are broadcast snoop, directory based, and hybrid (the only hybrid I know of is the IBM X3, see http://www.realworldtech.com/includes/templates/articles.cfm?ArticleID=RWT042405213553&mode=print for a description of the hybrid broadcast, directory protocol.
David Kanter
* Does anyone agree that the sentence "Cache coherence is intended to manage such conflicts and maintain consistency between cache and memory" should be changed to "... maintain coherence between cache and memory"? I think this sentence is "incoherent" with the coherence definition. Edans.sandes 18:27, 28 April 2007 (UTC)
thread_title: Consistency vs coherency

message: I think the article should be generalized to apply to any kind of cache, and make a clear distinction when it's speaking about the CPU cache and when not. I have also added the 
 tag for caching failure, as it is an artifact of cache incoherency. -- intgr 11:37, 6 December 2006 (UTC)
thread_title: Generalization

message: This article doesn't talk about strategies like:
* Not strictly guaranteeing coherency, for performance or simplicity. For example, a cache might have the policy "you'll get a consistent version from me, but it might not be the latest one".
* Checking to see if a resource has changed, before serving the cached copy or refreshing.  (Used for web caches, for example.)
-- Beland 23:02, 15 May 2007 (UTC)
replies: text: Well, I guess there is a link to consistency model, but this is not very well explained, and it is a core concept. -- Beland 23:05, 15 May 2007 (UTC)

text: I strongly agree. At a minimum - memory cache of disk storage (as in SAN file systems). Page should not refer specifically to processors and memory. Lets stay at a general level of: 
#reader,
#writer, 
#cache (...unshared), 
#data store (...shared). 
--Kubanczyk 18:41, 7 September 2007 (UTC)
thread_title:  Expansion request 

message: Dumb question.  Since the text of the article consistently uses the spelling "cache coherence", why is the article "Cache coherency"?  --Jorend 00:43, 26 October 2007 (UTC)
replies: text: The 2nd question is stupid, dictionaries exist, see . The problem is that the article uses both words (coherence and coherency are different words, not different spellings, since they also have different pronunciations); but coherence is the most common spelling, also in this technical meaning. Going to fix this. --Blaisorblade (talk) 10:07, 28 December 2008 (UTC)
replies: text:  To explain why I'm doing the rename directly: I'm working on these articles while studying the topic, and coherency (which is a word born after consistency and similar words, I guess) is never used, except in the title of "Effects of cache coherency in multiprocessors" by M. Dubois and F.A. Briggs (note the first author is French). The same authors, in "Memory access buffering in multiprocessors", switch to the other spelling. Also dictionaries consistently suggest coherence. So, I'm switching everything I find. --Blaisorblade (talk) 10:18, 28 December 2008 (UTC)
thread_title:  Article title 

message: How do directory-based cache coherence protocols work? --Abdull (talk) 15:39, 9 August 2008 (UTC)
thread_title:  Directory-based cache coherence protocols 

message: The Coherence protocol article is almost empty, all the existing information fits here in existing subsections, and cache coherence seems to me impossible to discuss without discussing coherence protocols. What do you think? --Blaisorblade (talk) 09:57, 28 December 2008 (UTC)
thread_title:  Merge from [[Coherence protocol]] 

message: AMD uses MOESI in opteron, Intel - MESI in pentium & Core. What protocols are used by other vendors? Such information can be added into article.
—Preceding unsigned comment added by A5b (talk • contribs) 
:You are encouraged to add such information to the article. :)
:Don't forget to add references for verifiability. If you're not sure how to do that, just use http://your.link.here/.... -- intgr [talk] 17:13, 9 October 2009 (UTC)
thread_title:  practically used protocols 

message: Minor note: shouldn't the "Illinois" and "MESI" items in the protocol list be replaced by one item "MESI (Illinois) protocol"? They refer to the same thing, and it is not clear why have two entries in the list.  —Preceding unsigned comment added by Alexeicolin (talk • contribs) 13:50, 25 March 2010 (UTC)
thread_title:  Protocol list: multiple items for same protocol 

message: Insertion of "and" is incorrect in "Different processors may see an operand and assume different sequences of values.", although more than one editor (lately ) has introduced it. I am surprised this should be contentious as the sentence jarred with me on first reading it. It seemed so simple at the time.
Both forms are grammatically correct (nearly) but they differ in meaning: the subject of the verb "assume" is changed. The version without "and" is correct because:
* It is (each copy of) the cached the operand that assumes a different sequence of values, and the several processors that see it. "Assume" is used here in the sense of "adopt" or "take on". The processor is not assuming anything: it is seeing this happen.
* There is no "and" in the source cited (Neupane), which is in turn quite likely quoting from Grammatikakis, et. al..
Better than either is "Different processors may each see an operand assume a different sequence of values." The singular is to be preferred because each processor sees one particular sequence.
--Prof Tournesol (talk) 06:25, 19 December 2015 (UTC)
thread_title:  Wording of "Overview" bullet 3 

message: The article says: "The cache coherence problem exists only in systems with private local caches." I claim this isn't true. Assume a CPU with 4 cores and 2 levels of cache. One L1 cache (L1.0) is shared between CPU0 and CPU1, another one (L1.1) is shared between CPU2 and CPU3. L2 is shared between all 4 cores. Therefore, there aren't any private local caches and according to the statement I'm challenging, there can't be a cache coherence problem. But suppose a thread running on CPU0 reads a variable and a different one running on CPU2 accesses the same one pretty much at the same time. Both L1.0 and L1.1 contain a cache line holding that variable. If now both processes modify the variable, we have a cache coherence problem.  — Preceding unsigned comment added by McGucket (talk • contribs) 22:25, 13 December 2016 (UTC)
thread_title:  Existence of the Cache Coherence Problem 

message: i find that this article should speak also about software coherency and mention that directory based and snoop protocols are hardware based cache coherency protocols  — Preceding unsigned comment added by 2001:660:6302:21:6495:BC40:E65D:45DD (talk) 11:18, 15 September 2017 (UTC)
thread_title:  software / hardware coherence 

message: Hello fellow Wikipedians,
I have just modified one external link on Cache coherence. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
*Added archive https://web.archive.org/web/20140811023120/http://sc.tamu.edu/systems/eos/nehalem.pdf to http://sc.tamu.edu/systems/eos/nehalem.pdf
When you have finished reviewing my changes, you may follow the instructions on the template below to fix any issues with the URLs.
Cheers.—InternetArchiveBot (Report bug) 22:28, 6 December 2017 (UTC)
thread_title:  External links modified 

message: I am confused by "In a read made by a processor P to a location X". As a native English speaker it seems that this should read "In a read made by a processor P from a location X".
Is there some technical reason for using "to" for both reads and writes?
Thanks,
-kb
(I'm trying to understand "false sharing" and getting really clear on cache coherency seems a necessary prerequisite. Using a clearer preposition here would help. I'm happy to make the change, but want to make sure I'm not breaking something else I don't appreciate.) Kentborg (talk) 17:13, 27 July 2023 (UTC)
replies: text: @Kentborg 109.74.43.253 (talk) 00:25, 17 August 2023 (UTC)
thread_title:  Preposition Pickiness (from vs to) 

message: === Coherence-Free Cache ===
It might be possible to create an exclusive cache. This would make possible a coherence-free processor.
FrankYang43338 (talk) 16:21, 23 March 2024 (UTC)
thread_title:  Coherence mechanisms 

message: It might be possible to create an exclusive cache. This would make possible a coherence-free processor.
FrankYang43338 (talk) 16:21, 23 March 2024 (UTC)
thread_title:  Coherence-Free Cache