Talk:Flash memory

message: Can someone explain why erasure can only take place one sector at a time, instead of one word at a time?
:I *think* that the erase circuitry is quite complex and to duplicate it for every cell would be prohibitively expensive in terms of chip area used.
::All the cells in a block ("sector" if you prefer) share the same source (source as in source, gate, and drain of a transistor). Erasure happens by creating a large electric field between the source and gate of the transistors, causing electrons to tunnel off the floating gate to the source.
::To erase an individual cell (one bit for SLC, usually two bits for MLC), that cell would have to have its own source connection. That would double the number of bitlines. Each would have to be routed (during layout, a phase of the design process), which would take additional design time, increase the area of the chip and/or require additional metal layers. All of those add cost.
::The second answer to your question is that because it involves tuneling, erasure is a slow process, taking seconds to complete. It's simply not acceptable to pay such a huge time cost to change the state of a single bit. When that huge time cost is amortized over the large number of bits in a block, it becomes a more acceptable trade-off. (By way of analogy, a two-core CPU performs a single task no faster than a single-core CPU, but since it can perform two tasks in parallel, it's effectively twice as fast at performing two tasks. The erase operation is effectively faster because it happens in parallel to so many bits.) Fhaigia (talk) 05:51, 16 August 2008 (UTC)
replies: text: yes word at a time EEPROMS do exist and do get used where only a small amount of storage is needed and simplicity is desired just as static ram is used for main system ram by many microcontrollers  for similicity. However i'm pretty sure it would be prohibitively expensive to use them for general disk like storage which was what i originally meant to say. Plugwash 13:08, 22 July 2005 (UTC)

text: File systems on FLASH devices is beyond the scope of this article. Going into a description of how the wear levelling is done specifically for a FAT FS would not be appropriate here, but instead, a link to another article or webpage that explains it would be of benefit. HumphreyW (talk) 10:39, 31 August 2009 (UTC)
replies: text: Wear levelling should be independent of the actual use. I doubt that wear levelling mechanisms implemented in actual products are based on any knowledge about FAT. Yet, in my opinion it is not stated clear enough that FAT is considered an example of "abusive and/or poorly designed hardware/software" in the context of Flash memory (the "for example..." sentence at the end of the "Block erasure" section should be more explanatory, and maybe the whole paragraph should be restructured because actually the next section is the one on "Memory wear"); actually it was never a well designed file system (the wear problem of FAT also occurs on floppy disks and was more or less regularly observed at the time floppies were widely used). --132.195.106.57 (talk) 12:56, 3 May 2010 (UTC)
replies: text: I agree. That "for example" at the end of wear leveling makes very little sense and is confusing to read.68.1.39.77 (talk) 02:00, 12 August 2010 (UTC)
replies: text: As well as I remember, from years ago, FAT system tend to write to successive blocks, at least until system restart, when looking for unused blocks to write.  That would naturally be somewhat of a wear leveling.  But it could be that the chips internally wear level, independent of the external block access pattern.  This should be explained better in the article. Gah4 (talk) 07:46, 1 September 2018 (UTC)
thread_title:  Why erasure in units of sectors? 

message: This article could do with some words about Read Disturb on NAND flash memories. It's a relatively recent field of research but there is citeable work by, amongst others, NASA, Aleph1(YAFFS), Micron and a couple of patents that claim to reduce the problem.  —Preceding unsigned comment added by 83.104.81.210 (talk) 13:45, 13 January 2009 (UTC)
replies: text: I just came to this page to make the same comment. I wanted to link the article write amplification to this page where I hoped to find Read Disturb covered. If I get a chance I will add what I can find. If someone else does feel free to let me know on my talk page so I can link from write amplification. § Music Sorter § (talk) 04:32, 19 June 2010 (UTC)
thread_title:  Read Disturb 

message: Apologies if I missed it, but it seems that the article needs to explain the origin of "flash" in this context. It seems to me that it stems from slang usage in such a term as "in a flash", meaning in effect instantaneously. Being an old hand in electronics (I'm 74), I can well remember the quartz-windowed UV EPROMs that took tens of minutes to erase. Extremely-fast erasing could have given rise to the term "flash". Regards, Nikevich (talk) 14:54, 9 September 2010 (UTC)
replies: text: From the article: "According to Toshiba, the name "flash" was suggested by Dr. Masuoka's colleague, Mr. Shoji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera." HumphreyW (talk) 15:20, 9 September 2010 (UTC)
thread_title: Origin of "Flash"?

message: The smallest sectors typically found in an "SPI flash" is 4 kB, but they can be as large as 64 kB. Since the "SPI Flash" lacks an internal SRAM buffer, the complete page must be read out and modified before written back, making it slow to manage.
This seems inaccurate to me. Recently saw a Numonyx chip (M25P128) which has 256KB sectors (64 sectors x 1024 pages x 256 bytes).
Also, if any bits are to be changed from 0 to 1, the complete sector has to be erased, while writes to previously erased space can be as small as 1 byte.
195.91.155.90 (talk) 07:46, 10 September 2010 (UTC)
thread_title: SPI flash update size

message: I couldn't see the data retention lifetime given in the article.  In good conditions, how long will flash accurately retain the data if put into storage?  (eg: LTO tape rates at something like 30 years, what's the equivalent?)  ‒ Jaymax✍ 11:01, 7 October 2010 (UTC)
thread_title:  Retention 

message: The first part of the article which describes the physics is good BUT IT LACKS INFORMATION ABOUT WHAT HAPPENS WHEN THE FLASH MEMORY WEARS OUT.  Do the insulators get perforated?  Do the cells tend to wear-out stuck-at 0, or stuck-at 1 ??  Are there any measures (cooling, lowering the programming voltage or speed) that can be used to extend flash memory life?
About 70% of the article consists of random observations about how flash memory CHIPS work.  It might be good to split this up into articles about the different kind of chips, with brief overviews, because this part of the article has low info-content and is unwieldy. SystemBuilder (talk) 20:04, 15 December 2010 (UTC)
thread_title:  Wearout & Article Balance ?? 

message: These days one often finds NOR flash operating at ~1.8 V for read/program/erase. This situation is not explained in this article. Isn't much higher voltage required for tunnel or hot carrier injection?61.216.233.12 (talk) 16:54, 19 February 2011 (UTC)
replies: text: Yes, a much higher voltage is used internally. How can we make the flash memory#Internal charge pumps section's explanation better? --DavidCary (talk) 21:04, 8 January 2014 (UTC)
thread_title: Single voltage for program/erase/read 

message: The original flash devices did not have a state machine and relied on the CPU to push cycles to the chip with uS timings.  If the write/erase routines got interrupted, etc. this could corrupt of damage the flash memory (circa 1993).  Eventually, the NOR flash manufacturers put a state machine on flash and created the JEDEC standard.  I think some information on this would add to the history section.  — Preceding unsigned comment added by 64.229.136.29 (talk) 02:30, 1 September 2011 (UTC)
thread_title:  Flash state machines 

message: This article has been found to be edited by students of the Wikipedia:India Education Program project as part of their (still ongoing) course-work. Unfortunately, many of the edits in this program so far have been identified as plain copy-jobs from books and online resources and therefore had to be reverted. See the India Education Program talk page for details. In order to maintain the WP standards and policies, let's all have a careful eye on this and other related articles to ensure that no material violating copyrights remains in here. --Matthiaspaul (talk) 12:58, 31 October 2011 (UTC)
thread_title:  Look out for possible copyright violations in this article 

message: Surely flash has a static life rating for archival storage, but there is no mention here.
132.3.33.68 (talk) 21:04, 1 November 2011 (UTC)
replies: text: Most likely, one should check the data sheet from the manufacturer.  The fundamental limit is the time constant of amorphous silicon dioxide, that is the resistivity times the permittivity, which form an RC circuit to the floating gate. The read and write process involve dielectric breakdown, which eventually damages the structure, and likely decreases its time constant.  Gah4 (talk) 07:57, 1 September 2018 (UTC)
thread_title: static life?

message: the article needs a bit of work to ensure that everythng that is particular to only one technology is so identified.
For example does the entire Block Erasure section apply to "specifically NOR flash"? I think not but the way it is written is ambiguous.
132.3.33.68 (talk) 21:04, 1 November 2011 (UTC)
thread_title: NAND/NOR clarificaiton

message: This phrase appears in the first paragraph as if the reader would know what a high density NAND type is.  I don't.  That's too obscure a phrase to appear in the first paragraph.  The first paragraph should be at a more elementary level.  — Preceding unsigned comment added by Skysong263 (talk • contribs) 20:59, 2 November 2011 (UTC)
thread_title:  "The high density NAND type." 

message: If you would read this article alone, you would think that all there is in a flash memory is the actual memory cells.  This is not so.  There is also control circuitry.  The control circuitry is not adequately discussed here.  — Preceding unsigned comment added by Skysong263 (talk • contribs) 21:11, 8 November 2011 (UTC)
replies: text: Some of the control operations are address decoding and such, which are well known and likely explained well other places. Others are likely proprietary to each designer, and, while they might be nice to know, aren't really important here. Gah4 (talk) 08:00, 1 September 2018 (UTC)
thread_title:  more needed about architecture 

message: 1. In the right column, memory should follow the sequence Historical, Early stage, In development which I believe more chronologically appropriate.
2. There should be consistency in the way Flash memory is presented in the article. At first the article talks about NAND and NOR, then it talks about NOR and NAND. I believe one sequence should be used throughout the article, possibly NOR, then NAND for chronological reasons.
3. "Dr. Masuoka presented the invention at the IEEE 1984 International Electron Devices Meeting (IEDM) held in San Francisco, California."
Since NAND Flash memory was presented in 1987, I assume that Masuoka presented NOR Flash memory in 1984. However, this is not stated in the article and the information should probably be added.
4. The last paragraph in the history section is all in the present tense. I believe it should be in the past tense since NAND was presented in 1987.
5. I think it would be nice to have a section dedicated to the comparison of NOR and NAND. The two types could be compared in two columns to give a quick idea of the two variants.
6. Flash is a proper name and it should be capitalized.
7. "For example, nearly all consumer devices ship formatted with MS-FAT file system, which pre-dates flash memory, having been designed for DOS, and disk media."
I don't see the relevance of MS-FAT within the paragraph.
8. When was wear leveling introduced for regular production?
ICE77 (talk) 06:29, 16 December 2011 (UTC)
thread_title:  Comments and questions 

message: I am not yet able to find an answer to this question regarding wear leveling:
For the NAND flash memory (flash drive) to be transparent to the OS, it needs to have a controller on the chip and store a wear level mapping (LBA to PBA) on the device. The question is, where is such mapping table stored?
If the mapping table is also stored on the flash memory, it needs to be updated every time a write command is received. Therefore, the blocks that store the mapping table will wear out first, while other data blocks are not worn out yet.  — Preceding unsigned comment added by 131.107.0.81 (talk) 22:28, 30 December 2011 (UTC)
replies: text: The storage format can vary from manufacturer to manufacturer (and typically isn't public knowledge), and I've never worked on such a device or filesystem.  With that qualification: The translation map doesn't have to be in a fixed place, the controller just needs some way of finding it (starting by consulting a fixed place or places).  One can reduce the number of erase operations needed by using the fact that changing '1' bits to '0' doesn't require an erase operation, so that there doesn't have to be an erase operation (within the metadata) every time the map changes.  For example, one can use journalling techniques, where updates are implemented as appending a change record (since appending doesn't require an erase per append), and only occasionally consolidating this list of changes into a more convenient form (to reduce the number of change records to be read). Pjrm (talk) 23:43, 6 October 2012 (UTC)
replies: text:  That's how JFFS2 works, for example, which is a log-structured filesystem designed to run directly on top of flash memory devices.  JFFS2 just keeps appending all of the filesystem changes, with periodic garbage collection to reclaim unused space, so there's no fixed place where the filesystem's metadata is stored it's scattered around together with the stored data.  As part of the garbage collection, JFFS2 tries to "redirect" future writes to less frequently used blocks; anyway, JFFS2 doesn't employ some highly complex wear-leveling algorithms which are required to scale the whole thing to gigabytes of flash, but a similar approach is most probably used by the current commercial SSDs.  In other words, commercial SSDs almost for sure wear-level the actual wear-leveling metadata. — Dsimic (talk | contribs) 04:25, 4 March 2014 (UTC)
replies: text: I don't know the specifics, and much might be proprietary. Note, though, that much of the design of the memory cells is to maximize storage density.  Remapping logic is much smaller, and so could be built with larger, and longer life, cells.  That is just a guess, though. Gah4 (talk) 08:03, 1 September 2018 (UTC)
thread_title:  Wouldn't wear leveling mapping blocks wear out first? 

message: Quartz (SiO2, silicon dioxide) can be darkened by radiation. Also, quartz has an ability to "heal" itself. There's a trick used by dishonest mineral vendors: If you bombard an ordinary quartz crystal with x-rays, the stone turns dark and can be sold as a fake "smoky quartz" at a higher price. The customer doesn't realize he's been scammed until a few months later, when the crystal starts to fade back to its original color. 
Obviously the x-rays are damaging the crystal bonds. In a semiconductor device, damaged bonds result in quantum traps which may allow charges (data) to escape, long after the x-ray source is turned off. And if the analogy from smoky quartz holds true, much (or all?) of that lattice damage is temporary. This should give us a few questions: 
# Is x-ray damage an issue for flash drives? 
# Is x-ray damage cumulative? Or does it completely heal? In other words, does it permanently reduce the storage life? 
# Neglecting lattice damage, x-rays have the same erasing effect as UV light (see EPROM#Details). How large is that effect? How many x-rays (medical, dental, or airport) will erase a flash memory? 
# Should travelers (esp. frequent flyers) avoid letting airport security x-ray their flash drives? 
# Is data lifetime shorter at high elevations, where there's less atmosphere to shield out solar radiation? 
# Non-radiation damage: If I take a flash drive and give it a million write cycles -- and then wait a year -- does the accumulated damage heal itself? 
# Do silicon nitride and other gate insulators fare differently? 
-- LessThanTwo (talk) 00:08, 1 June 2012 (UTC)
replies: text: Interesting questions, LessThanTwo. I started a new section flash memory#X-ray effects. Perhaps someday that section will grow big enough to answer all your questions. Currently it only partially addresses the "x-rays ... erase a flash memory" question. --DavidCary (talk) 06:00, 24 December 2013 (UTC)
replies: text: I suspect that the dose needed for color change is fairly high, much higher than airport X-rays, and I suspect even much more than dental X-rays.  Note also that the write cycle wear is also due to traps induced by the write and erase currents through the dielectric.  There is a note about a proposed, but as written not yet implemented, chip with a heater to help repair write and erase damage.  The article also mentions use of X-rays for verification of ball-bonding on PC boards, and the possible data loss. Data loss should be at much lower doses than trap damage. Note that the material of interest is amorphous (non-crystalline) SiO2, not the crystalline form for rock collectors. Gah4 (talk) 08:11, 1 September 2018 (UTC)
thread_title:  Radiation Effects 

message: This article is the most factually incorrect one I have ever seen on Wikipedia. Literally one or two errors or misrepresentations per paragraph. Bravo.  — Preceding unsigned comment added by 64.79.114.83 (talk) 18:10, 20 June 2012 (UTC)
replies: text: And yet your world-renowned expertise in this issue is such that you are unable to provide a single example of what you think is wrong.  Without that this is nothing more than trolling. Crispmuncher (talk) 20:19, 20 June 2012 (UTC)

text: I have fair amount of experience of flash memory technologies and I do not find this article or its talks/discussions that misleading as 64.79.114.83 thinks. It describes very well the basics and also some details about the fundamentals of flash memory.  — Preceding unsigned comment added by 83.249.37.47 (talk) 08:26, 30 July 2012 (UTC)
replies: text: Much of the design of actual chips is proprietary. I suspect that the article is mostly right for the generic case, but likely a little of compared to production devices.  Otherwise, if you find errors, fix them. Gah4 (talk) 08:13, 1 September 2018 (UTC)
thread_title:  Congratulations 

message: The diagram states that NOR erases to logical 0, but the text states Erase is binary '1'
PRogramming NOR sets to logical 1 (in diagram) but text states Programming sets binary '0'
Which is correct?  Is Logical 0 = binary '1' and Logical 1 = binary '0'?  — Preceding unsigned comment added by 216.52.146.25 (talk) 22:04, 9 September 2013 (UTC)
replies: text: Early EPROMs erased to a logic '0', but later, and as far as I know current, to logic '1'.  There used to be some processors with an X'00' NOP instruction, which made it slightly more convenient to erase to zero.  Seems to me that consistency is more important than the actual value, though.  The chips could include appropriate inverters where needed. Gah4 (talk) 08:16, 1 September 2018 (UTC)
thread_title:  NOR program/erase  logical vs. binary? 

message: Bit-level addressing suits bit-serial applications (such as hard disk emulation)
I don't have absolute knowledge, but I am pretty sure hard disk emulation does not need bit-level addressing. Given that the memory is the slow component, you would be much better off reading bits in parallel and then serializing them in the output stage.  --Buchs (talk) 18:26, 29 August 2014 (UTC)
thread_title:  Hard Disk Emulation not a good example of bit-level addressing need 

message: Though I have some good basic technical knowledge, and though I read it multiple times, I just can't follow this sentence due to it's extremely weird phrasing: Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistor below the size where they can be made reliably, to the size where further reductions would increase the number of faults faster than it would increase the total storage available. ("Eh?? Again please, Mr. Sulu?!") Seriously, any objections to change the sentence a little (or split it up into 2 of them) to bring the actual facts to light a little better? One basic issue in that sentence is the triple usage of "size", to begin with. -andy 2.242.118.118 (talk) 14:43, 19 February 2015 (UTC)
replies: text: As with hard disk drives, there are bad blocks due to imperfect manufacturing. Bad blocks can be mapped out at device testing time.  You can, then, adjust the size optimizing the good blocks after bad block mapping. Gah4 (talk) 08:19, 1 September 2018 (UTC)
thread_title:  Confusing sentence? 

message: Can someone explain what is meant by "100 k cycles" and what physical property of the memory has that value? Dondervogel 2 (talk) 22:16, 1 April 2015 (UTC)
replies: text: The value is the average or guaranteed number of erases per cell (100 k = 100,000). As explained in the article an erase occurs when all bits in a cell are changed to 1. Actually this is necessary even if only one bit in the cell should be changed to 1, because only a whole cell can be changed to 1 (erased). If only some of the bits really should change to 1, the flash controller must perform the Read-erase-modify-write operation. 100 k is actually a quite high value, most SSDs have a lower limit. --MrBurns (talk) 01:40, 2 April 2015 (UTC)
replies: text:  So could "SLC NAND flash is typically rated at about 100 k cycles" instead be written "SLC NAND flash is rated at 100,000 erases per cell"? Dondervogel 2 (talk) 06:14, 2 April 2015 (UTC)
replies: text: I actually fouind out, that a cell is just one bit, what I meant before is called a block, so probably it would be correct in this way:  "SLC NAND flash is rated at 100,000 erases per block". --MrBurns (talk) 06:29, 3 April 2015 (UTC)
thread_title:  "typically rated at about 100 k cycles" 

message: An erased (SLC) flash cell represents a binary one, but is there a reason why this state - which as far as I can see is a physical state neither one thing nor another - should equate to a binary one and not zero? As far as humans are concerned anything in an empty or erased state would probably be more associated with zero than one. When an empty flash page is read we are presented with zeroes, not ones (because a default page of zeroes is sent instead of the actual empty page). It all seems the wrong way round, but I don't know why it was originally done this way. Kletzmer (talk) 11:03, 23 September 2015 (UTC)
replies: text: As I noted above: Early EPROMs erased to a logic '0', but later, and as far as I know current, to logic '1'. There used to be some processors with an X'00' NOP instruction, which made it slightly more convenient to erase to zero. Seems to me that consistency is more important than the actual value, though. The chips could include appropriate inverters where needed.   External write logic needs to know which way it works.  While either would work, once the decision is made, it should be kept constant. Gah4 (talk) 08:22, 1 September 2018 (UTC)
thread_title:  Why is an erased cell one and not zero? 

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thread_title:  External links modified 

message: The article says: In NOR flash, cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate. In NAND flash, cells are connected in series, resembling a CMOS NAND gate.  Note that with the symmetry of CMOS logic, both NOR and NAND gates have both series and parallel connected transistors.  PMOS and NMOS, on the other hand, have only one type for each.  Should the example be NMOS?  Gah4 (talk) 08:25, 1 September 2018 (UTC)
thread_title:  cmos logic gates 

message: has added a tag to the Memory wear section, "Modern flash memory is significantly more durable, but this section appears to rely on data from 2008". It is true that the refs are from around 2008. In a quick search I have not been able to find any newer reliable sources. I don't beleive the assertion that, "Modern flash memory is significantly more durable." The datasheets I've looked at show raw durability as low as 3000 erase cycles. My understanding is that manufacturers have been working to increase capacity, not durability. Durability is addressed by wear leveling and wear leveling works better as capacity increases. ~Kvng (talk) 16:06, 27 January 2019 (UTC)
thread_title:  Memory wear