Talk:Intel QuickPath Interconnect

message: Historically people would use "Hertz" when refering to clocks or even data transfers.  If you consider the DDR Memory bus, it transfers data on both edges of the beat clock.  The current Front Side Bus is "quad pumped" which transfers on the rising edge, middle, falling edge, and middle of the beat clock.  
In case of the front side bus you would say "the beat clock is running at 200MHz and the data is tranferred at 800MT/s."  (MT/s = Megatransfer per second.)  Since more is happening than just "bit transitions" it is more accurate to say "transfer."  Data is transferring from one device to another.
I don't have a citation, just experience.
--Cmiyc 18:01, 14 February 2007 (UTC)
thread_title: Gigatransfer

message: Some sources say that CSI stands for "Common System Interconnect" rather than "Interface".
85.216.19.4 16:41, 30 May 2006 (UTC)
thread_title: Correct Name?

message: Should this article be renamed to QuickPath?  The name has shown up quite a bit recently.  Imperator3733 22:02, 28 July 2007 (UTC)
replies: text: Do you have any links?  I have never heard of this name before, and the only things I could quickly find on Google were an unsourced article on some random website and an old item on the Inquirer.  Neither is at all reliable.  — Aluvus t/c 22:36, 28 July 2007 (UTC)
replies: text: I think it would be better to wait for some more official sources that confirm the new name. -- Bovineone 07:03, 29 July 2007 (UTC)
replies: text: I guess we could wait a bit to rename it Imperator3733 16:30, 3 August 2007 (UTC)
replies: text: Once this name change is confirmed and sourced, this should most certainly be changed to the new name. CSI appears to be an ambiguous acronym, as it would likely be confused with the common notation for  CSI (TV show).  Freedomlinux 20:54, 3 August 2007 (UTC)
replies: text: What about this article from  DailyTech? (second to last paragraph).  Imperator3733 18:41, 12 August 2007 (UTC)
thread_title:  QuickPath 

message: "Intel first delivered it in November 2008..."
I'm not sure this is quite possible given it is still October of 2008.  —Preceding unsigned comment added by Teebird04 (talk • contribs) 18:22, 19 October 2008 (UTC)
replies: text: Well that was me using my schizophrenic crystal ball. Intel has already delivered the X58 to motherboard manufacturers, and the motherboards are already available for sale, with a nice QuickPath connecting the X58 to the Socket B (AKA LGA1366). So, QuickPath is "delivered." However, they are worthless without the Core i7 to plug into the socket. Intel says the Core i7 will be available in November 2008.Go figure. -Arch dude (talk) 22:01, 19 October 2008 (UTC)
thread_title:  Nostradamus 

message: It would be interesting to see a comparison to HyperTransport here. Just looking at the data here and on the HyperTransport article, I don't see why anyone would use QuickPath over HyperTransport. My best guesses are that Intel had already started work on QPI before HTX3, licensing issues, or NIH syndrome... --Aij (talk) 00:07, 22 January 2009 (UTC)
replies: text:  intel's qpi is much more restricted, this is probably due to intel wanting profit from qpi license schemes to produce chips Markthemac (talk) 00:32, 27 April 2009 (UTC)
thread_title:  Comparison to HyperTransport 

message: "Performance numbers for QuickPath are reported to be 4.8 to 6.4 Gigatransfers per second (GT/s) per direction. Therefore the bandwidth amounts to 12.0 to 16.0 GB/s per direction, or 24.0 to 32.0 GB/s per link.[7]"
The calculated bandwidth is as follows:
6.4 (GTransfer/s) * 20 (bits) * 0.8 (accounts for 8b/10b encoding) / 8 (bits/bytes) * 2 (directions) = 25.6 GB/s (per link)
Something is wrong with that author's math.
edit: That author's doesn't account for 20 bit to 16 bit conversion, which explains the difference in calculations.  —Preceding unsigned comment added by 24.72.40.3 (talk) 01:50, 8 February 2009 (UTC)
thread_title:  Calculated bandwidth error 

message: the article completely miss-charactarizes QPI, and I am partly to blame. QPI is a four-layer protocol. L1 passes 80-bit phits, L2 uses the 80-bits to convey 72-bit units (8-bit header, 64-bit payload) with an 8-bit CRC, L3 is a routing layer, and L4 is a message layer. I will try to fix this mess some tiem in the next three days. -Arch dude (talk) 23:58, 16 April 2009 (UTC)
replies: text: I finally fixed the clock rate-related part of the problem, but we still need to add the protocol layer description. -Arch dude (talk) 12:55, 12 June 2009 (UTC)

text: I have now described the layers. It's not perfect, but it's no longer a mess. -Arch dude (talk) 17:37, 18 July 2009 (UTC)

text: according to the Intel paper listed as a reference, QPI is a 5-layer interconnect, which is what the article says. If you have better references to Intel docs, please update the article. If you do not wish to update the article, feel free to just put the info here and someone else can update the article. Please identify any problems in detail. A general charge of "misinformation" is difficult to fix. It is also insulting to the contributors, who are trying their best to provide correct information. If you can do better, then please do so: Don't just complain. -Arch dude (talk) 00:08, 17 February 2012 (UTC)
thread_title:  This article 
is
 
was
 is still  a mess 

message: The article claims that Intel Corp. acquired the Alpha Development Group from DEC. They could have only done so when DEC sold Digital Semiconductor to them in 1997. However, if I am not mistaken, the Alpha-related staff were not transferred as part of that sale. When Compaq announced they would stop Alpha development, they also said that most of the Alpha designers would go to Intel Corp. Some were retained for the Alpha 21364 and 21364A projects, some until after Compaq had merged with HP. Did Intel Corp. really get the ADG from DEC? Or from Compaq? Or neither? Rilak (talk) 08:08, 29 September 2009 (UTC)
thread_title:  Alpha Development Group 

message: <quote>
As of 9th September 2009, Intel altered their implementation on mainstream versions of the Core i5/i7 chips (notably the i5 750, i7 860 and 870) to exclude a QPI, replacing it with a PCIe interface alongside the new Intel P55 chipset, presumably as a pre-cursor to on-die GPUs and Larrabee (GPU).
<unquote>
Wrong! QPI is still used on-die (intercore and cores-to-memory interface).  —Preceding unsigned comment added by Stasdm (talk • contribs) 19:01, 24 November 2009 (UTC)
thread_title:  Core i5 

message: The article is a bit sloppy (no offense to anyone), but then Wikipedia is a process not a destination. I took the liberty of reorganizing some of the text, put some of the "bottom line" info up top (BLUF), and started an Implementation section to capture some of the "techotica" (which needs to be organized by someone closer to the technical knowledge), a couple of minor grammatical fixes here and there, etc. I didn't dig much deeper than the top half. Hopefully I helped more than harmed. 208.252.197.131 (talk) 19:28, 5 March 2011 (UTC)
replies: text: Thanks! That was a definite improvement. I've made some additional changes to de-emphasize info that was of topical interest when QPI was first released. Articles related to new computer hardware are prone to this problem and need to be cleaned up after about two years. -Arch dude (talk) 23:16, 5 March 2011 (UTC)
thread_title:  Work in Progress 

message: This article is very technical, which isn't a bad thing, but there isn't much here for the layperson. I was hoping to discern why the Core i5 (with it's DMI) is better than the Core 2 Duo (FSB), and why the i7 (QPI) is better still. May I suggest a paragraph or two about why the newer processors are superior, and how exactly they differ in fuctionality. nagualdesign (talk) 23:20, 26 December 2011 (UTC)
replies: text: ..Perhaps something from the first reference, An Introduction to the Intel QuickPath Interconnect, like Table 1 on page 10 along with an explanation. nagualdesign (talk) 23:54, 26 December 2011 (UTC)
replies: text: Perhaps Wikipedia should provide thsi information somewhere, but this article is not the place. The place for this informatin might be "comparison of bus architectures" or comparison of Intel system architectures." However, I may be hard to create such articles without doing original research, which is not allowed here at Wikipedia. -Arch dude (talk) 02:54, 27 December 2011 (UTC)
thread_title:  Suggestion 

message: An image of QuickPath-design would be really helpful to differentiate this technology with the obsolete but well-known northbridge/southbridge-design. --Daan5000 (talk) 13:24, 29 December 2014 (UTC)
replies: text: Hello!  Went ahead and ...  Surely not the best one possible, but still better than nothing. :) — Dsimic (talk | contribs) 13:50, 29 December 2014 (UTC)
thread_title:  Image 

message: The Ring Bus inside Sandy Bridge processors are based on QPI technology, or an enhanced version. The link, connecting Agents, is outside that ring bus, but almost another internal QPI bus. Emphasising the cache coherency would lead ambiguity. For the internal Ring Bus, one could compare a system with more processors linked with QPI bus, there one ring or more complex graph could be seen. In the Ring Bus, we could compare each stop to a local memory region of a XEON processor on a QPI bus, data request might travel through many cache slices (processors), and eventually transfer back, then a full ring would appear. QPI, itself, is not a Ring Bus, but a point-to-point, routing-based bus, similar with Hyper Transport Bus. So the Ring Bus might simplify the routing mechanism as a ring bus, for it's an internal bus, without considering too much on external world interconnection. The snooping bus within that Ring eases the System Agent to keep cache coherency. One could compare this with the back side bus within Pentium II physical package. — Preceding unsigned comment added by 119.53.112.120 (talk) 08:17, 11 September 2015 (UTC)
replies: text: Sorry for my delayed response.  Regarding  and your explanation, current wording in the article is based on the page 10 in associated reference.  I'd really love to see that expanded further, but the documentation describing the CPU internals seems to be rather scarce; any chances, please, for providing reliable sources to back your explanation? — Dsimic (talk | contribs) 04:57, 10 October 2015 (UTC)
thread_title:  Ambiguous