Talk:Adder (electronics)

message: I made some argument about this. But I didn't do the job for my own because I'm not a native speaker of English. I want to see someone does that job.  —Preceding unsigned comment added by Routitz (talk • contribs) 17:48, 5 April 2010 (UTC)
thread_title: ripple carry adder

message: Would anyone object to putting overflow detection circuits for adder circuits in this article? The articles about overflow didn't seem quite the place to put information like this. Lordhatrus (talk) 16:32, 6 June 2008 (UTC)
thread_title: Overflow Detection for Adders

message: We should probably also link to Carry-skip and Carry-select adders too, since they lie between ripple adders and full lookahead adders.Symmetry 14:47, 18 January 2007 (UTC)
replies: text: The article carry-skip adder now exists, it used to be called carry-bypass adder (see the talk page for details).  I've edited this article, and renamed the instance of carry-bypass adder to carry-skip (although still mentioning the alternative nomenclature).  I didn't make any other changes, but want to point out that in the More complex adders section, there are duplicate links for the carry-skip and carry-select adders (they're mentioned in-line with the text, and on the line following which mentions "other adder designs". Bcastell (talk) 13:33, 10 December 2012 (UTC)
thread_title: Carry-Skip and Carry-Select

message: two questions:  what is the difference between a carry-lookahead and a carry-propagate, which I have also heard of?  Are they the same thing?  Also, is the carrry select adder the same as the carry save adder?  these can be confusing because they share the same acronym.
jUst wondering.  Thanks for good work.
:A carry-save adder is actually an architecture for adding more than 2 binary numbers together, like in a multiplier.  I'm not certain, but I think a carry-propagate adder might be as well.
Ckape 03:03, 3 Jan 2005 (UTC)
thread_title: carry-lookahead vs carry-propagate

message: full adder has three inputs inp1,inp2 and carry.
The one u have stated is a half adder .
In my Logic Design book, it says a full adder has two inputs - not three like this article says. Is this article wrong on that? Fresheneesz 07:28, 13 March 2006 (UTC)
thread_title: Full adder

message: Is the picture for the full adder really ok? For C_out it implements 
C_out = (A and B) or (C_in and (A xor B)),
which is not equivalent to the stated expression  
C_out = (A and B) or (C_in and (A or B)).
The latter puts a 1 for C_in in the last row of the truth table, whereas the former puts a 0 there.
Note also that the note under the truth table does not concern this problem; A and B can both be 1 simultaneously. 
—Preceding unsigned comment added by 129.16.80.10 (talk) 10:40, 18 January 2008 (UTC)
thread_title:  Full adder picture OK? 

message: The full adder picture has no arrows or lines in it at all when I look at it in the article. On the description page, I still see no lines. When I click the actual image URL I see the lines. What gives? Is it a browser error? (happens for me in Safari or Firefox 3 in MacOS X) Staecker (talk) 22:01, 10 December 2008 (UTC)
thread_title:  Full adder picture again 

message: From the article revision History: 
:The layout of  ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder.
:The gate delay can easily be calculated by inspection of the full adder circuit.
:Each full adder requires three levels of logic.  In a 32-bit [ripple carry] adder, there 32 full adders,so the critical path (worst case) delay is 32*3=96 gate delays.
I guess this part should be checked. The critical path doesn't occur in that path. Although that is the worst case in this situation, serially connected adders doesn't suffer from that path, because A OR B can be evaluated as soon as the signals come. The critical path occurs through the  C_o  to  C_i  root, which is the very signal that cannot be evaluated unless the previous stage is finished. The critical path delay of stage i is  2*i + 1, where i > 0. And the first adder is stage 0 in this case.
My reference is "Contemporary Logic Design" which is written by Randy H. Katz.
written by User:Routitz moved to discussion by MichaelFrey (talk) 17:42, 7 April 2010 (UTC)
thread_title:  Comments in the Article 

message: i have no idea what the official name is, but it is possible to make an effective adder by putting half adders into a pyramid.  —Preceding unsigned comment added by 178.109.166.32 (talk) 18:07, 12 January 2011 (UTC)
thread_title:  pyramid of half adders 

message: The formula for carry  and the picture  are not same. There is an OR between (x.y) and the other part not XOR. Marmzok (talk) 08:24, 24 June 2011 (UTC)
replies: text: In this circuit, the net logic is identical with the lower-right gate being OR or XOR, since the two inputs can never both be high.  Both are correct, independently of how the logic formula is written. Dicklyon (talk) 05:46, 23 October 2021 (UTC)
thread_title:  a mistake 

message: Ok, this is turning into a mess so I brought this to the attention of the talk page so I don't jump in and make things worse without first verifying I understand what's going on here. If I understand correctly:
# At 5:59am we have a vandalizer. 
# At 6:10am we have the same vandalizer striking again.
# At 7:25am we have a prompt reverter which undid the 6:10 edit but not to the 5:59 edit.
# Then on Sept 23rd at 10:15pm someone noticed this then attempted to undo the 5:59 edit but only accomplished what appears to be a partial revert.
What do you feel would be the best coarse of action here? --Thelazyleo (talk) 09:09, 24 September 2012 (UTC)
replies: text: If you see something wrong and you can fix it, Be Bold and fix it. Wikipedia didn't used to debate every comma and non-breaking space...--Wtshymanski (talk) 17:58, 24 September 2012 (UTC)
thread_title:  Vandalism and Partial Reverts starting Sept 22nd turning into a mess 

message: The two methods for calculating Cout are the same. Both list the method as C_{out} = (A \cdot B) + (C_{in} \cdot (A \oplus B))
The text of the artical sates Using only two types of gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per chip. In this light, Cout can be implemented as and it then lists the same methods above C_{out} = (A \cdot B) + (C_{in} \cdot (A \oplus B)). The second method contains 3 types of logic gates: AND, OR, and XOR.
 This change caused some sort of parser error and then the math code was changed again.  This is the point where the two methods to calculate Cout became the same.
Maxximillian (talk) 21:57, 7 March 2013 (UTC)
thread_title:  The alternate form for the Carry Out seems to be the same form as the original Carry Out 

message: "Full adder" certainly deserves its own page, possibly removing some information in this article.
--Trex4321 (talk) 07:55, 6 September 2021 (UTC)
replies: text: Oppose. It's a couple of paragraphs here - it could be tightened up without all the textbook-style lecturing. Better one  article that briefly and accurately surveys the topic than a forest of highly-similar articles to explain every variant and flavor. Just how much effort do we expect the reader to expend in picking out the minute shards of explanation from the deep shag carpet of Wikipedia to re-assemble the souvenir ashtray of knowledge? --Wtshymanski (talk) 20:21, 7 September 2021 (UTC)

text: Oppose. I also oppose this! Because it would totally gut the article, leaving not that much remaining. Also it is somewhat contrary to my suggestion to just rename this article (see section above). If people wish to write much more on the topic of full adders then just add more sections, its okay if the article grows  · · · Omnissiahs hierophant (talk) 01:28, 8 September 2021 (UTC)

text: Oppose – the current coverage with half adders and full adders and ways of building on them seems about right. Dicklyon (talk) 05:23, 23 October 2021 (UTC)
thread_title:  Split out "Full Adder" 

message: The adder blocks shouldn't be called a "full adder" when it doesn't output a carry on its own, but rather has P and G outputs. Instead, the adder with P and G as outputs is completed as a full adder with the carry-lookahead block. The label on the adder blocks should be changed to make it less confusing. 2601:703:280:9C80:C993:D992:C34E:4AE0 (talk) 02:22, 25 January 2023 (UTC)
thread_title:  Block diagram for carry-lookahead adder seems incorrect