Talk:VIA C3

message: I'm very skeptical about "quantum" in the description of the random number generators. It sounds like a marketing buzzword to me.  I found some more detail on the implementation of the RNG on VIA's site, and it's clear to me that they're confused: they list four sources of randomness, one of which does have a quantum source (the first one), two of which have a thermal source (the next two), and one (the last one) which, I believe, can be either quantum or thermal, depending on the parameters.  The last one is the one they actually use.  I had edited out the "quantum" from the article text, but I reverted it because I'm not 100% positive that the source was not, in fact, quantum.
Does anyone know what the oscillators used to control the frequency in a CPU are?  Is it a quartz oscillator?  If so, I found this paper on frequency calibration which says that the primary limits to accuracy of typical quartz oscillators are thermal, not the fundamental quantum limits.  --Dylan Thurston 05:29, 10 April 2006 (UTC)
replies: text: Update: As indicated in the article text, I found information on the VIA site written by someone who knows what they're talking about and edited accordingly. --Dylan Thurston 06:30, 10 April 2006 (UTC)

text: Yes, the random number system is thermal. Quantum is a marketing term. You get this all the time with VIA. Their product names do not tie up to hardware like with AMD, Intel, NVIDIA, ATI, etc. That makes writing up their tech all the harder, since you have to get past the marketing. Timharwoodx 20:10, 11 June 2006 (UTC)
thread_title:  "quantum" random number generators 

message: Well, the C7 seems to be based upon the Celeron-M socket, in pin and electrical terms. I don't understand how VIA lost the rights to socket 370, but retained rights to Celeron-M. And if they are so confused about their bus rights, why not license the EV7 like AMD did? I've even seen an article that suggests VIA may get sued for using the Celeron-M socket. And why do VIA call the Celeron-M socket V4? Are they trying to hide their infringement of Intel IP? Its so hard to get good answers to some of these issues, because VIA are more interested in selling to China than America.  Timharwoodx 20:17, 11 June 2006 (UTC)
replies: text: I agree the marketing behind the NX bit is horrible.  While it makes certain methods of exploit much more difficult, and therefore some set of exploits impossible, it is a good thing, but I think can be better represented here.  Instead of saying "NX flag to reduce buffer overflows and guard against viral attacks", it would be better to say something like: "NX flag, which can make some types of software vulnerabilities more difficult to exploit, and therefore may help protect against some computer viruses."  Or something like that.  -- TDM 23:13, 13 September 2006 (UTC)
thread_title: C7 bus

message: Has Via claimed NX can protect against viruses? I know AMD has called it "Enhanced Virus Protection" on their chips.  This is a bit of a misnomer, and Microsoft, who call it "Data Execution Protection" have the most accurate name.  The article mentions NX guarding against viruses, but this isn't really accurate - most viruses work via legitimate means that NX won't prevent.  NX certainly can protect against buffer/stack overflows, though.
:I agree the marketing behind the NX bit is horrible.  While it makes certain methods of exploit much more difficult, and therefore some set of exploits impossible, it is a good thing, but I think can be better represented here.  Instead of saying "NX flag to reduce buffer overflows and guard against viral attacks", it would be better to say something like: "NX flag, which can make some types of software vulnerabilities more difficult to exploit, and therefore may help protect against some computer viruses."  Or something like that.  -- TDM 23:13, 13 September 2006 (UTC)
thread_title:  No-Execute Bit 

message: As there are several people who agree on my point of view, I recently do some splitting and merging and cleaned up WinChip, VIA C3, VIA C7 and Centaur Technology. So I hope, that now everybody will work together in improving these articles as there are some informations left which need to be added... --Stickedy 03:39, 23 April 2007 (UTC)
thread_title:  Split 

message: I added VIA C7 and Antaur information to the "Roadmap Changes" section.  --KJRehberg (talk) 04:16, 23 February 2008 (UTC)
thread_title:  Roadmap changes 

message: Well, I've decided to scrub the talk page, because I've done a complete re-write of the main page, and its just confusing to have comments that refer to something that no longer exists. I think the new page sets out the core generations relatively clearly. Why VIA chose to name things they way the did - don't know. I think the key point that emerges from the core table, is that the C5X (Nehemiah) was the key core revision, and the C5P (Nehemiah) is what emerged as the C3. The C7 is a core shrink to 90nm SOI, a new socket, with some tweaks to the encryption engine. Its NOT a new core, as such. More like the Palomino / Thunderbird etc revisions AMD made to the Athlon, so I don't see C7 deserves a new page. Presumably the C5X is the next generation P4 clone they expected to hit 3 GHz on one of the old roadmaps, 16 stage pipe, etc. But they figured out by trial and error marketing, that there was more money in the embedded market, than fighting a loosing battle for performance leadership. The embedded deals have been reported on theinquirer.net as now generasting major revenue / profits for VIA. Small, cheap, low power, seems to be a winning formula over raw performance, for many industrial clients. Timharwoodx 19:21, 30 December 2005 (UTC)
replies: text: http://www.livejournal.com/users/libv/4494.html
Quite funny. I should probably update the main page sometime to reflect the bus mess. Timharwoodx 21:06, 12 January 2006 (UTC)
replies: text: Sectionalized this useful but not top-of-page-worthy random section. --KJRehberg (talk) 04:19, 23 February 2008 (UTC)
thread_title:  Talk page cleanup 

message: 128KiB L1 cache was not unique or distinct to C3. K7 had this way beforehand.  —Preceding unsigned comment added by 67.241.177.124 (talk) 04:39, 25 May 2008 (UTC)
thread_title:  Cache 

message: The Nehemia Cores section states: 
Additionally, it implemented support for the cmov instruction, making it a 686-class processor.
 This is technically untrue, as CMOV is an optional i686 instruction.  Previous cores (Samuel 2, Ezra) were 686 cores, but did not implement the optional CMOV instruction.
--65.121.28.16 (talk) 01:29, 3 June 2008 (UTC)
thread_title:  CMOV versus 686 status 

message: The following lines have been removed due to being original research and phrased in an extremely unencyclopedic manner:
EDIT: Got a Nehemiah board with the Padlock feature that is recognized as "C3", it doesnt support "long NOP" and its not a i686 cpu. see: http://lkml.org/lkml/2008/7/22/263
You need "Generic x86 instructions" in the kernel.
69.109.221.32 (talk) 02:47, 12 September 2009 (UTC)
thread_title:  Some chattiness removed 

message: https://www.tomshardware.co.uk/x86-hidden-god-mode,news-58952.html
"Some x86 CPUs [reported against VIA C3 Nehemiah] have hidden backdoors that let you seize root by sending a command to an undocumented RISC core that manages the main CPU, security researcher Christopher Domas told the Black Hat conference here Thursday (Aug. 9 [2018])"
Sawatts (talk) 09:03, 10 August 2018 (UTC)
thread_title:  "God Mode" exploit reported