Talk:List of Intel CPU microarchitectures

message: Someone proposed merging this article and Intel Tick-Tock. I just wanted to state my agreement for such and plans to carry such out in the future if there are is not a consensus against such a move. I believe the Tick-Tock is descriptive of Intel's committed cadence across a number of their more recent CPU microarchitectural and fabrication technology developments and as such makes sense to incorporate it as one or more section(s) within this article (an argument could be made to incorporate this into a list of their fabrication technologies as well but since there is no such article and it so far only applies to their CPU microarchitectures I believe this is currently the most appropriate place). It could further be generalized in to a general roadmap table including parts that have not been part of their tick-tock cadence. 50.53.15.59 (talk) 15:08, 23 July 2013 (UTC)
replies: text: Merged as new section 68.165.77.79 (talk) 04:28, 23 September 2015 (UTC)
thread_title:  [[Intel Tick-Tock]] merge proposal 

message: See http://en.wikipedia.org/w/index.php?title=List_of_Intel_CPU_microarchitectures&diff=570526280&oldid=570517480
if it's a tock, please revert. "2-way coarse-grained multithreading per core (not simultaneous)" seems to be quite different. Can it still be the same microarchitecture? When is it a new one, if there are tweaks? Always? See also Pendium M and Enhanched Pentium M (take out indent?). Not only a shrink. But minor enhanchments? New instructions(? SSE3 and SSE2) can hardly be minor enhanchments as they imply "new"/enhanched microarchitecture? Maybe th "tock" always includes something more that a shrink? comp.arch (talk) 13:02, 28 August 2013 (UTC)
thread_title:  Indentation = shrink ("tock")? 

message: SO I have an Arrandale cpu in my laptop. By the Wiki article, its desktop counterpart is the Clarkdale. However, its nopwhere to be found on the list. Why is this?207.81.0.235 (talk) 13:24, 20 January 2015 (UTC)
replies: text: Clarkdale (microprocessor) and Arrandale (microprocessor) are not microarchitectures, but microarchitectures variants. Visite fortuitement prolongée (talk) 20:16, 4 April 2015 (UTC)
thread_title:  Clarkdale/Arrandale? 

message: Is it time to rename the Tick, Tock and semi-Tock to Process, Architecture and Optimisation? Seems to be the new roadmap Intel has adopted.
http://www.anandtech.com/show/10183/intels-tick-tock-seemingly-dead-becomes-process-architecture-optimization
Cambookpro (talk) 22:32, 14 April 2016 (UTC)
thread_title:  Move from Tick/Tock to Process/Architecture/Optimisation 

message: Even in all Wiki articles about Intel's CPU, there are many references to generational chronology. 8th generation this, 6th generation that... But I can't find any article relating code names to generations, nor exposing such generational chronology by itself. IMHO this article should include it. Simply by adding the column... Thanks.
--24.200.214.47 (talk) 22:19, 26 February 2017 (UTC)
thread_title:  Generational chronology road map ? 

message: Hello fellow Wikipedians,
I have just modified one external link on List of Intel CPU microarchitectures. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
*Added archive https://web.archive.org/web/20131114063059/http://pc.watch.impress.co.jp/video/pcw/docs/569/575/p2.pdf to http://pc.watch.impress.co.jp/video/pcw/docs/569/575/p2.pdf
When you have finished reviewing my changes, you may follow the instructions on the template below to fix any issues with the URLs.
Cheers.—InternetArchiveBot (Report bug) 18:03, 25 December 2017 (UTC)
thread_title:  External links modified 

message: Not sure how reliable this is, also needs translation: https://tweakers.net/nieuws/151984/roadmap-toont-dat-intel-in-2021-nog-desktop-cpus-op-14nm-maakt.html --Pizzahut2 (talk) 10:31, 25 April 2019 (UTC)
thread_title:  Roadmap desktop 2021 / mobile 2020 

message: I guess Intel was using "XXX Lake" names for their microarchitectures starting with Skylake, but Intel now seem to refer to the microarchitecture as "Sunny Cove" and seem to refer to the mobile Sunny Cove processors as having the code name "Ice Lake".
So are the "XXX Lake" names being used for something other than CPU microarchitectures now, e.g. for chips with both CPU and GPU, as Anandtech seems to be suggesting here ("Sunny Cove, built on 10nm, will come to market in 2019 and offer increased single-threaded performance, new instructions, and ‘improved scalability’. Intel went into more detail about the Sunny Cove microarchitecture, which is in the next part of this article. To avoid doubt, Sunny Cove will have AVX-512. We believe that these cores, when paired with Gen11 graphics, will be called Ice Lake.")? Guy Harris (talk) 18:36, 10 May 2019 (UTC)
thread_title:  Is the next CPU microarchitecture name "Sunny Cove" or "Ice Lake"? 

message: The table starts with microarchitectures, putting microprocessors into parentheses. Then starting with Penryn, it's suddenly continued with microprocessors instead of microarchitectures. Pizzahut2 (talk) 20:52, 18 December 2019 (UTC)
thread_title:  x86 microarchitectures table 

message: Is "Palm Cove" a real microarchitecture?  The only significant info I could find on it is at WikiChip.  Other sources such as Anandtech suggest that it is mostly Skylake microarchitecture with a few additions like AVX-512 and some instructions.  Is there any reliable source for Palm Cove? --Vossanova o< 20:05, 4 May 2020 (UTC)
thread_title:  Palm Cove? 

message: On May 21st I moved Alder Lake from "Pentium 4 / Core lines" to "Hybrid" since it's a hybrid, but this got reverted May 28th with the reason "it's not the same hybrid as Lakefield, Lakefield Refresh and Ryefield". Recent roadmap: https://heise.cloudimg.io/width/1920//_www-heise-de_/imgs/18/2/9/5/0/5/2/0/Roadmap-318a5c78606a6aa6.jpg --Pizzahut2 (talk) 13:54, 21 August 2020 (UTC)
replies: text: Alder Lake is definitely a hybrid, maybe they didn't know that back in May though. A more recent source can be found here, which includes that same roadmap image. It's a bit deceptive to put it in that table below Tiger Lake, because that suggests it's a direct successor to the non-hybrid Tiger Lake, which isn't necessarily true.  I don't think Intel has discussed what, if any, processor would be only Golden Cove.  So, two options. 1) take it back out, and take Lakefield off the table too, or 2) leave it, and add Alder Lake next to Gracemont as well (that might just make things more confusing without context). --Vossanova o< 20:32, 21 August 2020 (UTC)

text: Reading the new article a bit more, Intel considers Alder Lake more of a "performance hybrid" than Lakefield, so it's possible Alder Lake could be a successor to Tiger Lake, just with some extra Gracemont cores (leaked slides suggest up to 8 GC + 8 GM cores). So I'm leaning toward leaving it like it is for now. --Vossanova o< 20:39, 21 August 2020 (UTC)
thread_title:  Which section for Alder Lake? 

message: Here is an article of the future fabrication process at Intel Accelerates Process and Packaging Innovations.  Rjluna2 (talk) 17:24, 28 July 2021 (UTC)
thread_title:  Intel Accelerates Process and Packaging Innovations 

message: The article now says about P6 that is was "First x86 processor to support SIMD instruction with XMM register implemented,"
I think this is incorrect. The first was Pentium MMX, which added MMX but was otherwise based on P5. See MMX_(instruction_set).
The first P6 processor, Pentium Pro, did not include MMX. Page Pentium_Pro notes "However, its lack of MMX implementation reduces performance in multimedia applications that made use of those instructions."
ErkkiRuohtula (talk) 17:07, 1 December 2021 (UTC)
thread_title:  MMX 

message: https://www.intel.com/content/www/us/en/newsroom/news/bold-multiyear-xeon-roadmap-accelerate-data-center-leadership-growth.html
https://www.intel.com/content/dam/www/public/us/en/newsroom/posts/inv-day-processor-roadmap-16x9.jpg
https://twitter.com/IanCutress/status/1494448351730937857
https://pbs.twimg.com/media/FL1Y2HFXsAMguSM?format=jpg&name=4096x4096
The leaks were dead accurate, yet small minded people here(they know who they are) removed the codenames because of stupid crystalball rule. 
Have fun re-adding all those codenames to the article and tables now. And yes, smarter editors like me feel very vindicated that losers at life admins and mods defending that dumb rule are proven wrong again and again. — Preceding unsigned comment added by 42.190.161.224 (talk) 07:36, 18 February 2022 (UTC)
replies: text: Of course they couldn't be added, those were only rumors. If they were wrong, then we would have been writing false information. We, as editors, need to follow specific rules. P.S: please sign your messages by using four tildes. Itsquietuptown ✉️📜 13:29, 18 February 2022 (UTC)

text: Have a read through WP:CIVIL, please do not attack other editors if you want your voice genuinely heard and talked about. AP 499D25 (talk) 11:46, 17 February 2023 (UTC)
thread_title:  Intel Roadmap confirms Raptor Lake, Arrow Lake, Lunar Lake, Emerald Rapids 

message: IMO should be a subitem of Golden Cove. Not really a new arch at all. Also similar if not exactly the same as Sandy Bridge -> Ivy Bridge and SkyLake derivatives. Artem S. Tashkinov (talk) 14:51, 25 October 2022 (UTC)
thread_title:  Raptor Cove/Lake