Talk:Superscalar processor

message: I'm having problems with the statement that the Cray was the first superscalar system. I'm currently studying the paper by Tomasulo written in 1965, which describes a modified IBM 360 system that was developed to be superscalar. The paper introduces the concepts of reservation stations and the common data bus, so the fact that it has not been mentioned makes me wonder what's going on in the history section. It's probably likely that the Cray was developed in parallel. Also, this modified IBM was likely only ever used for research purposes-but that sure as hell doesn't mean it wasn't the first superscalar computer. The paper is dated September 16th, 1965, and is called "An efficient algorithm for exploiting multiple arithmetic units". In this paper he make no reference to any currently existing superscalar systems, which led me to question the position of his research in the superscalar development timeline. If anyone wants to clear up this mess, be my guest; I have to finish this review in a few hours and sleep.  —Preceding unsigned comment added by 82.10.136.208 (talk) 01:57, 27 October 2008 (UTC)
thread_title:  Who was first? 

message: This definition of the term "superscalar" is too loose. Implementing "a form of parallelism" fails to distinguish it from even pipelined architectures, let alone VLIW architectures. Also, lack of a good definition appears to have lead to the arguments over the Intel i860. Hennessy and Patterson (Computer Architecture - A Quantitative Approach, 2nd Ed., 1996) indicate that to be superscalar, a machine needs to issue more than one instruction per cycle (which is obviously not the same as executing more than one per cycle). This would then classify machines that have multiple functional units capable of operating in parallel, but only issue one instruction per cycle as scalar (e.g. Sun's microSPARC-II). VLIW architectures are also effectively multiple-issue, but the number of instructions issued is fixed (and determined by the compiler), but in a superscalar machine, the number can vary and are typically determined dynamically. Having said this, modern compilers schedule for superscalar machines based on knowledge of the capabilities of the dependency-checking mechanisms of the target processors, so it would be more correct to say that a combination of static and dynamic scheduling is used.
84.92.139.115 17:17, 26 December 2005 (UTC)
thread_title: Definition of "superscalar"

message: Tried to improve initial description, esp. regarding superscalar vs pipelining. While virtually all superscalar CPUs are pipelined, it's important to differentiate the two in order to clarify what superscalar actually is. Joema (talk) 14:13, 5 December 2007 (UTC)
replies: text: I don't really understand why the difference between a functional unit and a processor core should be explained here, since there is little potential for confusion. Rilak (talk) 14:42, 5 December 2007 (UTC)
replies: text: That was my thought, but someone requested clarification, thus my effort:  Joema (talk) 02:49, 6 December 2007 (UTC)
replies: text: The requested clarification only said that superscalar and pipelining should be explained more clearly... How did processor cores come into this? I think that the statement in question should be changed to this: "A superscalar processor executes more than one instruction per a clock cycle by simultaneously issuing multiple instructions to multiple execution units." Rilak (talk) 07:32, 6 December 2007 (UTC)
replies: text: He mentioned processor cores in his question. Saying "issuing multiple instructions to multiple execution units" could imply multiple cores, unless clarified. We need to describe superscalar in a way that's unambiguous and distinct from pipelining and multi-core CPUs. Ideally it should be worded such that a technically literate, but non-professional casual reader can understand it: Wikipedia:Make technical articles accessible. If you can re-word in a way that accomplishes all these, feel free to make the changes. Joema (talk) 13:23, 6 December 2007 (UTC)
replies: text: There are two entirely different concepts being discussed -- processor cores, and the individual execution units within each core.  And that's something that any technically literate user should understand -- that a core contains multiple components each of which perform different functions.  For example, adders, shifters/rotaters, multipliers, etc.  Within that single core it is possible, provided the bus width and other supporting logic is available, to issue two instructions, one to an adder and another to a shifter, provided there are no dependencies between the two operations.  For example, the statement "a = (b + c) * (d / 2)" can be dispatched so that "b + c" are calculated by the adder and "d / 2" by the shifter.  The hypothetical multiplier can't produce the product since it is dependent on the results of the first two instructions (which are being executed simultaneously in different execution units).  BUT, if a "e * 3" term were added, and the input bus made wide enough (and the logic needed to handle the new dependency calculation complexity added) to fetch all three instructions with one go, it could be assigned to the multiplier unit and all three terms computed in parallel.Tall Girl (talk) 03:08, 5 June 2011 (UTC)
thread_title:  Initial description