Talk:Phase-locked loop

message: "might have an internal 2.4 GHz core clock which is phase aligned to a bus clock running at 100 MHz"
:Isn't the 100 MHz phase-aligned to the 2.4 GHz?  Hmmm...  I guess not. - Omegatron 17:13, Mar 2, 2005 (UTC)
::Never heard of the term phase aligned. What does it mean?--Light current 01:10, 28 March 2006 (UTC)
thread_title: Untitled

message: The article is getting a little disorganized again and I've just pruned some apparent redundancies and added a section break. --Wtshymanski 15:03, 4 November 2005 (UTC)
thread_title: Time for a rewrite

message: This is listed on the "PPL" disambiguation page, but "PLL" redirects here and is given in the article as the acronym.  Is it also referred to as PPL sometimes, or is it just there by mistake? -Elmer Clark 07:23, 6 February 2006 (UTC)
replies: text: **** I've never seen it called this.  May be a common fat-finger error.  Only the Phase Lock vs. Locked usage. -- Steve -- 00:44, 10 September 2007 (UTC)
thread_title:  PPL? 

message: The mechanical analogy refers to a frequency locked loop- not a PLL and is therefore incorrect. This section needs rewriting explaining the phase locking operation.
--Light current 21:07, 18 February 2006 (UTC)
replies: text: **** Thus my comments on analogies in general.  I like the marching band suggestion. -- Steve -- 00:44, 10 September 2007 (UTC)

text: I think the guitar tuning is a fine example.  However, there should definitely be wording added to clarify how it is inaccurate.  It would have confused me if I did not check the Talk page and find the discussions here.  71.245.36.73 (talk) 20:41, 19 January 2008 (UTC)
thread_title:  Mechanical analogy 

message: :::  First describe its purpose, then *general* types, then examples of those types.  Remove "An important part".  _ALL_ PLL parts are important.  The rest is ok, except the phase does not always have to go to zero.  Type 1 loops have a constant, non zero error.
::: On types of PDs:
::: There are two major types:
::: 1- Analog.  Describe the multiplying process, sum/diff freqs, 90 degree settling point, dual requirements of the low pass filter and the resulting capture/lock range concepts. Examples, 4-Quad analog mult and double balanced diode mixer.
::: 2- Digital. There are two subtypes.  
:::: A- The XOR, analogous to the analog types (unavoidable pun). This type is NOT fundamentally different from the above analog types and may be better placed there. It depends on how you wish to clasify them - by functionality or simply circuit type - I think here is ok.  Explain that square wave inputs, or nearly so, are required and all other analog concepts apply.
:::: B- The phase/freq (zero phase error) type. Most complex, edge triggered, Up/ Down outputs are difference between input edges, charge pump, lock detect output possible.  The 4044 and its decendants.
-- Steve -- 00:44, 10 September 2007 (UTC)
thread_title:  **** PD section 

message: Phase-lock loops can be implemented in analog or digital form.
:: ****  Software as well. -- Steve -- 00:44, 10 September 2007 (UTC)
thread_title:  STRUCTURE AND FUNCTION: 

message: I have never seen a PLL used for a UART.  Every time I run into a UART, it only divides down a reference clock to get its data clock; there is no phase-lock, VCO, or phase detector.  This is why you see such interesting oscillator frequencies as 1.8432 MHz for sale (1.8432 MHz / 32 = 57.6 kbps, for example).  The closest thing to a phase lock is the state machine for detecting the falling edge of the start bit, and it discards its "phase lock" information almost immediately (an error in the clock or data rate can cause the stop bit to be misinterpreted as the last data bit, or missed entirely).  If anyone has an example, please give it, but I'd hardly think it was a common application.
That said, they're used all over the place in high-speed (Mbps/Gbps) serial links.  But that's generally two applications: multiplying up a reference clock to the bit rate on the transmit side, and recovering the clock from the data on the received side. --97.99.113.227 16:34, 5 August 2007 (UTC)
thread_title:  DIGITAL PLL 

message: This should go before digital and be (as it tried to be) the general overview in more detail.  This does not describe a basic PLL.  
1- The U/D PD and charge pump are an advanced type.  For a type 0 loop, the PD only is needed and the phase error is NOT brought to zero, but only to some fixed difference.  As in the mixer or Exclusive OR PD & filter.   The charge pump makes it a type 1 which does get the phase error to zero.
2- While the loop compensator does almost always have a ‘low pass’ characteristic and is frequently called as such, its primary purpose is to make the loop stable and defines its dynamic performance (lock time, lock range, pull-in range, damping, etc). It should also be noted that classical control theory methods can be used to determine loop dynamics provided the transfer functions of the individual blocks are well known.
3- The “bias generator” and “output converter” (whatever that is) are irrelevant in a basic description.
4- Again, the divide by N is also irrelevant for basics.
5- The “smooting” effect of the low pass filter is secondary to its primary purpose of determining loop dynamics.  It is a "loop compensator".  When spurious caused by VCO control line ‘ripple’ is a factor, then the low pass characteristics between the PD and VCO become important and often there is a trade-off between the loop dynamics and spurious.  When more attenuation of spurious is needed, this can start to affect loop dynamics and more filtering usually requires slowing the loop.
: **** P.S. The analog and XOR PD types have what can be considered to be excessive output ripple so that the low pass characteristics of the filter frequently greatly over-shadow the loop compensation considerations.  In the complex types of PD, the loop compensating characteristics (lock time and settling characteristics) are a larger consideration and the low-pass (high frequency attenuating) characteristics become secondary, but not unimportant or trivial. -- Steve -- 00:44, 10 September 2007 (UTC)
thread_title:  ANALOG PLL 

message: This section should only describe the effect each type of feedback circuit has:
None :     Fout = Fin.
Divide by N :   Fout = N x Fin.
Multiplier : Fout = Fin / N
Programmable /N :   Multiple Fout’s
Mixer :   Fout = Fmix +/- Fin.
Distribution amp :   Phase at all distributor outputs in phase lock.
: There's also a modification to the divide-by-N feedback system that allows Fout = Fin x (N + M/A).  The divide-by-N circuit is replaced with a divide-by-N-or-N+1 circuit, and another counter is used to switch in the N+1 setting for M of every A cycles.  This is commonly used in radio circuits for IF generation, as it allows channels narrower than the reference oscillator, and since the reference oscillator can run faster, the loop can be made more stable. However, it can have more jitter than high-speed digital communications circuits may desire. --97.99.113.227 16:44, 5 August 2007 (UTC)
replies: text:   **** I stopped short of this.  this can refer to the Farichild "Pulse Swollowing" or "dual Modulus" technique, or the modern more agressive and quite proprietary and complex fractional N methods (that address the issues you mention).  -- Steve -- 00:44, 10 September 2007 (UTC)
thread_title:  FEEDBACK PATH: 

message: Why Antenna ?
Though my major was control theory, I didn’t review the math.  Too long ago (:-).
: It's probably not appropriate anyway because it is too complex to cover adequately here.  -- Steve -- 00:44, 10 September 2007 (UTC)
thread_title:  SEE ALSO: 

message: A mechanical clock's escapement accomplishes a form of phase locking. The pendulum is the frequency reference, while the toothed wheel driven by a spring or running water is like the VCO which operates off a battery.
= = Perhaps, but you are correct with "a form of phase locking".  While true, an analogy should be something quite common that is easily thought of by a reader.  I think a better analogy is the common cruise control on an automobile.  While more like a frequency lock loop (without knowledge if the internal circuitry it could be either), it is familiar to many people and quite similar in function ie. Frequency and speed being easily compared.
= =   RE: Intro
:: While it may not be immediately obvious, the fact that the frequency is also "controlled" is a secondary effect resulting from the relationship between phase and frequency.   Therefore, it is truely phase which is measured and the frequency actually just follows.  There is such a thing as an FLL (Frequency lock loop) where the frequency *is* measured/compared and the phase is not so tightly affected due to the relationship. 
71.201.106.220 14:35, 17 July 2007 (UTC)
replies: text:  I disagree that an escapement is a valid analogy.  A Shortt master/slave clock would be, however, but that's not something many people know.  One way to see that an escapement isn't a valid analogy is to see what happens if the input (the pendulum swings) stops for a moment.  Answer: so does the output (the turning of the gear train).  But with a PLL the output continues over gaps in the input, which is what makes clock recovery possible. Paul Koning 20:34, 18 July 2007 (UTC)
replies: text:  I was not comfortble with the clock.  I was thinking the escapement wheel was locked to the pendulum with the number of teeth being like a divide by N, but thought it was a stretch. On the other hand, the fact that the PLL dVCO oesn't Actually "stop" is only the result that the specific implememtation lf a VCO doesn't allow it to go to zero freq.  If it could, it would follow the reference frequency down to zero, in some of the types. (only an irrelevant nit, though)-- Steve -- 00:44, 10 September 2007 (UTC)
thread_title:  PHASE LOCKING & MECHANICAL CLOCKS 

message: With all these good comments and so much to fix, unless someone DOES something, it'll not happen.  I propose that you (whomever) just Pick either a section or the overall outline and change it.  Then we can work on those changes.  I'll take the first move and re-do the intro, per my above, and wait for the flack. Regards, -- Steve -- 00:44, 10 September 2007 (UTC)
replies: text: Numbered lists should indicate priority. I would strongly recommend avoiding numbered lists in the lead paragraph of the article. I agree that the block diagram has a few elements that are not explained in the description of operation.  Perhaps you can explain Type 0, Type 1, loops and the significance of the types. References are always good. --Wtshymanski 16:05, 17 September 2007 (UTC)
replies: text:  Would an unnumbered list be appropriate?  Explanation of feedback system 'type' belongs in Control Theory, which I see it is not.  -- Steve -- 03:33, 23 September 2007 (UTC)
thread_title:  Proposal 

message: * Clock synthesizers for microprocessors are almost always analog PLLs.  The whole point is to multiply the frequency to well above the crystal frequency.  To do that with a DPLL, you'd need an extremely high frequency clock source to run the DPLL, and that would defeat the purpose.
* As someone else observed above, UARTs don't use PLLs, as they are asynchronous.  PLLs are used for clock recovery in many synchronous data communication systems, but those aren't UARTs.
* The claim that "The phase detector may be a simple comparator" is so unclear as to be useless.  What kind of comparator?  A magnitude comparator?  What is it comparing? 
* The claim that "much of a digital PLL may be implemented using even a very small" PAL is wrong or at least misleading, and basically irrelevant.  A very small PAL is something like a 16V8, 20V8, or 22V10, and you can't get a substantial part of any practical DPLL into one.  Even if your counters only have four-bit resolution, That uses 8 of the 10 available macrocells in the 22V10, which doesn't leave enough for the control logic.  A more modern CPLD with 32 or more macrocells may be suitable, but technically that isn't a "small PAL".
Given that the DPLL section is riddled with errors and the information that isn't outright incorrect is misleading, the section needs to be either completely rewritten or eliminated.
--Brouhaha (talk) 22:17, 29 December 2007 (UTC)
thread_title: DPLL section nearly completely wrong

message: From the article:
Hence the VCO output takes the form
:x_r(t) = A_r \cos\left( \int_0^t \omega_r(\tau)\, d\tau \right)
              = A_r \cos(\omega_f t + \varphi(t) )
Where does the integral come from? --Abdull (talk) 15:27, 22 June 2008 (UTC)
replies: text: Phase is the integral of frequency...  Oli Filth(talk) 15:33, 22 June 2008 (UTC)
thread_title:  Integral 

message: A while since I've been here.
I added this to the basic design.  I have designed such feedback sections:
It should also be noted that the feedback is not limited to a frequency divider.  This element can be other elements such as a frequency multiplier, or a mixer.  The multiplier will make the VCO output a sub-multiple (rather than a multiple) of the reference frequency.  A mixer can translate the VFO frequency by a fixed offset.   It may also be a combination of these.  An example being a divider following a mixer; this allows the divider to operate at a much lower frequency than the VCO without a loss in loop gain. 
Regards, Steve
 -- Steve --  (talk) 01:18, 21 September 2009 (UTC)
thread_title:  Basic Design addition 

message: I again diffidently suggest that if one has to write "There is confusion about X", that one does not understand X sufficiently to contribute to an encyclopedia article. People come to (professinal) encyclopedias expecting to come away less confused. Of course, as long as you are verifiably confused.... --Wtshymanski (talk) 19:29, 18 May 2010 (UTC)
thread_title: Confusion

message: Here is some input from a user who just browsed by : What is a phase-lock loop ?
I am posing the question with an assumption that many already know the answer . I profess also a tilted perspective, because the phase-lock may not be interesting for anyone not already familiar with 'the basics', and I am not familiar with 'the basics' . From the start (story untold), I thought this might be an algorithm . I am not quite convinced it is not an algorithm, but as an algorithm can be considered basically a method, it is perhaps more significant (...) to formulate what it does . This will be the approach seen taken in the current article . A phase-locked loop or phase lock loop (PLL) is a control system that tries to generate an output signal whose phase is related to the phase of the input "reference" signal. So ok, it says system, not method . Now consider a very base parallel example : A dam . There is the river, providing the input and output . The river is a natural occurence, and it does not need to be explained in terms of functionality - unless if you are a hyper-structuralist and know how to read French . Then there is a dam . The dam is man-made, and it has a function . It is kind of a control system that will generate an output, and the output could also strive to reflect the temporally observable fluctuations defining the input flow . This is not a very terse parallel, because the output of the dam has at least two conceptually diverging manifestations . One is electrical current, the other is water-current . Now, enter the phase-lock . I sincerely hope this is man-made (cf. tunnel). The significant flow, is perhaps not necessarily man-made, but at the least it is typically man-made . The output of a phase-lock is un-ambiguous, i.e. not similar at all to a dam . But like the dam, coincidentally, it 'observes', or relates to some input . In that way, it is not an algorithm, definitely a method, and optimistically a system . The implied 'algorithm' would be to consider a flow, and a break of the flow . And in fact there is also conceptually diverging outputs from the phase-lock, i.e. it is not un-ambiguous at all : )In 'Frequency Synthesis' phase-lock provide a controlled version of the input . )In 'Clock generation', although input and output is identically uninteresting, the aspect of the flow as kinetic impulse, with the famous binary characteristics of being there, or not being there, is all that matters . 
A phase-lock can manipulate a typically artificial input stream, such as a radio-signal . A phase-lock can also provide timing . The primary aspect of the phase-lock is the manipulative behaviour . It is contextual whether the flow is interesting for its temporal characteristic (the binary kinetics) or whether it is the modularities of the flow that is considered valuable . A phase-lock can be described in abstract as a method with dual output aspects, implementing a determining algorithm to pertain to a singular input . 
... Sechinsic (talk) 08:21, 15 July 2010 (UTC)
thread_title:  A small essay, but very relevant 

message: Mark A. Wickert, Phase-Locked Loops with Applications, ECE 5675/4675 Lecture Notes, Spring 2008, pages 1-14 to 1-20, cites Roland E. Best, Phase Locked-Loops: Theory, Design, and Applications, fourth edition, Mc-Graw Hill, 1999, for classification of PLLs.
*Analog or Linear PLL (LPLL). Phase detector is an analog multiplier. Loop filter is active or passive.
*Digital PLL (DPLL). An analog PLL with a digital phase detector (such as XOR, edge-trigger JK, phase frequency detector). May have digital divider in the loop.
*All digital PLL (ADPLL). ADLL is digital in two senses: all digital components and discrete time signals. Closely related to SPLL. VCO uses digitally control oscillator (NCO). Example is 74ls297.
*Software PLL (SPLL). Discrete time implementation of either LPLL or DPLL.
Glrx (talk) 18:55, 2 December 2010 (UTC)
replies: text: Starting with Glrx's contribution here, I have replaced classification content with what Best has to say about it. There were some changes; Wickert or Glrx appears to have taken some liberties. --Kvng (talk) 15:04, 3 December 2010 (UTC)
thread_title: PLL Classification

message: PP (talk) 15:10, 7 February 2010
: The figure is misleading at best.  A PLL cannot operate as diagrammed.  For one thing, even if there was no filtering performed (or we want to leave out the filter for clarity) there must be a phase detector for the thing to function.  I don't have time at this moment to fix the figure, but will try to get to it soon.  For now I just modified the figure caption -- sorry.  If you want to subsume all of this into the figure element that is represented as an adder, it really ought not to be shown as an adder, and some mention should be made in the caption that it is a phase detector+filter.
::I agree it is misleading. I think putting a warning in the caption is too mild a response. I have temporarily removed the figure until it can be fixed or a replacement found. --Kvng (talk) 14:44, 10 February 2011 (UTC)
thread_title:  Figure needs work, I think 

message: May I just say again that the "auto race" is the worst analogy I have ever seen? I doubt anyone in the history of teaching about phase-locked loops has compared a PLL to a race. Isn't the point of an analogy to explain some feature of a physical system by comparing it with a simpler, more familiar, system? --Wtshymanski (talk) 13:51, 17 October 2011 (UTC)
thread_title: Loathesome analogy

message: Can I pose a question here?
As an electronicist with 35+ years experience working with PLLs (and a mathematically retarded brain), I've never really understood the underlying principle of the PLL, despite successfully repairing and manufacturing PLL-specific circuits. And now I still don't!
In all this time, repairing other people's designs and designing and building my own circuits using PLLs, I have never, ever, cared about or used the phase detection feature of a PLL explicitly, and none of the circuits I've ever seen do either. I'm not saying that phase-dependent circuits don't exist, just that in practical (consumerist) terms, they aren't relevant to how PLLs are used in the real world.
What PLLs are used for, in the real world, is generation (synthesis) of frequencies. The frequencies (sub- or super-multiples of the reference frequency) may be phase-locked, but that's totally irrelevant in most modern PLL designs that barmaids or spotty teenagers may be browsing these pages to better understand.
What I'd like to see is a description of how the PLL itself works (which is kind of mentioned, but using abstruse mathematical symbology), and what it's used to do.
Notwithstanding specialists' declarations, there are more PLLs used in computer systems (CPUs, MPUs, SoCs, etc)to generate phase-irrelevant clock signals than have ever been built for use in radio, astronomy, communications, and so on, for all time. And when they are used in non-computer paradigms, they are nearly always used to generate a locked frequency, not a locked phase. The phase locking seems to be a handy side-effect of generating a stable frequency. I'm sure purists will scream, but then that's what I'm here for :)
So : can someone, please, present a useable analogy for what the PLL circuit or module (software or hardware) is generally/typically used for?
The guitar analogy works for everyone except the purists. The point of the analogy is clear - the feedback is used to reduce the beat frequencies to zero (or close to). And when the beat frequency is zero (as determined by ears or an oscilloscope), the phase is, by definition, zero too. That's close enough for most readers of this page, believe me.
If EE majors are reading this article and are getting confused, then they should be paying more attention in class. This isn't a university education site, it's for dumbarses like me who would like to see the experts able to describe both the function and the use of the particular technological idea. Currently, that's not happening, and that makes this one of the most disappointingly useless wikipedia pages I've come across, and the talk page is just as frustrating when viewed from the perspective of a "typical" user! We have arguments about technical accuracies of analogies that most people would find not only perfectly helpful, but are actually only "wrong" when viewed from a hyper-technical perspective. I don't give a rat's patootie if frequency is mistaken for phase in an analogy - it's an ANALOGY. From the Greek, ana (like) logos (thought). Think of them as gedankenexperiments. They don't have to be perfect, they have to be useful. Race cars and pace cars may be more accurate than a guitar tuning, but who doesn't know what an out-of-tune guitar sounds like?
Please, put a clear description, and a workable, practicable analogy at the top of the page, and talk about poles and filters and linearities below. If I can't understand what a PLL is used for, then your 12-year-old barmaid sure as heck can't.
And who the hell put in the garbage about ECL's supremacy as PLL circuits? Perhaps that person could explain why no-one uses ECL any more, and why CMOS and TTL PLL circuits changed the world? Talk about pet theories. That's the sort of crap we find in the pseudo-scientific articles. I'm not saying it's not true (though I can't actually buy ECL to test the theory proposed), but I am saying it's pointless, irrelevant, and definitely someone's personal point of view.
Cephas Borg (talk) 02:01, 25 May 2012 (UTC)
replies: text: The operation of a phase-locked loop will only be clear if one abandons the frequency viewpoint and looks at phase. For modern clock distribution networks in synchronous systems, the issue is not matching the frequency of all the clock copies but rather making sure that the clock transitions are synched up. All the clocks need to be in phase. Glrx (talk) 19:19, 30 May 2012 (UTC)
replies: text:    Stopping by after quite some time, I see this article is languishing.  I disagree with Glrx. This can be true for clock synchronization applications, but this is not true in general, especially for frequency synthesizers and other analog applications.  As a designer of synthesizers and an instructor, the designer must keep both domains in mind; in fact, switching back and forth moving to various parts of the loop.  Ignoring one domain is disingenuous of the complete subject.  We find (at least I have, from experience teaching) that the subject of phase is a rather esoteric one.  Oh yes, electronics students “know what it is”, but working with it as a primary variable is a new and unfamiliar experience and this is an important transition that must be guided carefully. 
I agree completely with Cephas Borg; it couldn't be a clearer indictment from someone who came to learn.  I think this article is still out of control.  Wtshymanski appears to have a quite good instructional view. For someone looking for a fundamental understanding at an encyclopedia level, the article does little but obfuscate and confuse. 
While commenters are obviously well meaning and have 100% correct comments, bombarding a beginner immediately with every conceivable advanced detail of the most sophisticated considerations of the system, or, just as bad, only focusing on one of the applications, does not bring the reader along to a better general understanding --  that practice is quite pedantic.  You must start with the fundamentals and build on them in a logical manner; introducing advanced considerations only once the proper foundation has been laid.   Perhaps teaching this material for years gives one a better understanding of a good progression of concepts.    
Also, there is nothing wrong with proceeding in parallel with history and adding the newer applications and their respective special considerations once the fundamentals are covered.   
Applications that require the shifting of focus can be mentioned early, but brought in with more detail in another section that specifically calls out the different application.  Arguing whether there are more computers with clock distribution loops or radios and TVs with synthesizers is pointless. 
A complete rewrite is quite an undertaking.   I have notes I made over several years of watching this article and will attempt to fold them in periodically.
I edited the intro paragraphs to give smoother development of the fundamentals, yet provide for the inclusion of the various types/uses of PLLs.  I moved the term definition of "reference" out of the first sentence to a more suitable place.  Definitions of specific terminology aren't necessary in an intro and could be left out till later, but seemed ok for now.
I removed the hyper-detail of the "time derivative" as it is unnecessary to grasp the frequency lock characteristic and worked hard to add reference to clock sync as one of the primary uses.
 -- Steve --  (talk) 04:47, 12 July 2013 (UTC)
thread_title:  I'm more confused than before I found this page! 

message: Sorry for the multi-edit and possible poor formatting of this entry - I'm rusty at Wiki.  I awoke after posting and I realized that calling the VCO output the "desired signal" is not always the case (demodulation).  The intro focus should be what the PLL *is* not what it *does*.    Because there are several different uses/configurations, details of what the PLL *does* is best left for later.  The phase locking aspect is the *is*.
I also believe that a reader coming in cold may need to be reminded that these are periodic "signals" as opposed to otherwise.
I also decided that defining a name (reference) for the input should be done later in the article (see my previous inside the above section).
 -- Steve --  (talk) 14:04, 12 July 2013 (UTC)
thread_title:  Introduction Revisited 

message: Using x_r and x_c as notation for signal waveforms is not a good idea. It is common to denote state of dynamical system as x(t), phase as \theta. Maybe f(\theta) is also not the best choice, but definitely better than mixing state of filter and signal waveform.
195.19.251.8 (talk) 09:14, 10 February 2015 (UTC)
thread_title:  Modelling section 

message: This article is quite inaccurate in many places.  E.g., the first sentence reads "A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. "  This is wrong.  Better would be something like "A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal with a frequency that is locked to the frequency of an input signal, using phase differences between the two to lock them to each other".  — Preceding unsigned comment added by 129.241.50.248 (talk) 21:23, 21 February 2017 (UTC)
replies: text: I believe this was discussed long ago.  While a PLL typically does by default also set the frequerncies at the phase detector equal, having equal frequencies as the end result is not always the requirement. The phase is the variable that is "locked" and frequency is a secondary effect.  The phase can be the most important design requirement and it is the primary feature of the circuit type.  There are also ways to have phase detection at harmonically related frequencies. The VCO frequency can be below, above, offset, or a combination of those from some reference frequency.   If you see other potential improvements, please add them here, Regards,  -- Steve --  (talk) 23:51, 23 February 2017 (UTC)
thread_title:  Inaccuracies 

message: When reading the section "Linearized phase domain model" I noticed that the Laplace variable s in the formula \frac{\theta_o}{\theta_i} = \frac{K_p K_v F(s)} {s + K_p K_v F(s)} must be unitless when pluging in the variables' units as described in the section. Having a unitless Lapace variable is surprising for electrical engineers where s is usually of dimension radians/second.
When pluging in the given units into the forula for the natural frequency \omega_n = \sqrt{\frac{K_p K_v}{\tau_1}} we see that the natural frequency is of unit Hertz. I suggest therefore to replace the notation \omega_n by f_n or to add a comment that explains the unusual notation.
 — Preceding unsigned comment added by Fvultier (talk • contribs) 12:00, 11 May 2017 (UTC)
thread_title:  Units in Linearized phase domain model 

message: Following 
, we consider a discrete time model of the CP-PLL.
Let t_0 = 0.
Denote by t_0^{\rm middle} the first instant of time such that the PFD output becomes zero.
If i(0)=0, then t_0^{\rm middle}=0.
Then we wait until the first trailing edge of the VCO or Ref,
and denote the corresponding moment of time by t_1.
Continuing in a similar way, one obtains
increasing sequences \{t_k\} and \{t_k^{\rm middle}\} for k=0,1,2....
Let t_k < t_k^{\rm middle}.
Then for t \in [t_k,t_k^{\rm middle}) the \text{sign}(i(t)) is a non-zero constant (\pm1).
Denote by \tau_k the PFD pulse width (length of the time interval,
where the PFD output is a non-zero constant),
multiplied by the sign of the PFD output 
:
\begin{align}
  & \tau_k = (t_k^{\rm middle} - t_k)\text{sign}(i(t)),
  & t \in [t_k,t_k^{\rm middle}), \\
  &  \tau_k = 0 & t_k=t_k^{\rm middle}.
\end{align}
If the VCO trailing edge hits before the Ref trailing edge,
then \tau_k < 0 and in the opposite case we have \tau_k > 0.
Thus, \tau_k shows how one signal lags behind another.
Zero output of PFD i(t) \equiv 0 on the interval (t_k^{\rm middle},t_{k+1})
implies a constant filter output.
Denote this constant by v_k. We have
:
\begin{align}
  & v_F(t) \equiv v_k, \quad t \in [t_k^{\rm middle},t_{k+1}).
\end{align}
Following 
,
the number of parameters can be reduced
to just two (\alpha and \beta):
:
  \begin{align}
    p_k = \frac{\tau_k}{T_{\rm ref}},
      u_k=T_{\rm ref}
      (
        \omega_{\rm vco}^{\text{free}} + K_{\rm vco}v_k
      ) - 1,\\
    \alpha = K_{\rm vco}I_pT_{\rm ref}R,
     \beta = \frac{K_{\rm vco}I_pT_{\rm ref}^2}{2C}.
  \end{align}
Here p_k is a normalized phase shift and u_k+1 is a ratio of the VCO frequency \omega_{\rm vco}^{\text{free}} + K_{\rm vco}v_k to the reference frequency \frac{1}{T_{\rm ref}}.
Final system of equations describing CP-PLL without overload is the following 
:
  \begin{align}
    u_{k+1} =   u_k +2\beta p_{k+1},\\
    p_{k+1}=
    \begin{cases}
      \frac{-(u_k + \alpha + 1) + \sqrt{(u_k + \alpha + 1)^2 - 4\beta c_k}}{2\beta},
      \\
      \qquad\qquad \text{ for }  p_k \geq 0, \quad c_k \leq 0,
      \\
      \frac{1}{ u_k + 1} -1 + ( p_k \text{ mod }1),
      \\
      \qquad\qquad \text{ for }  p_k \geq 0, \quad c_k > 0,
      \\
      l_k-1,
      \quad \text{ for } p_k < 0, \quad l_k \leq 1,
      \\
      \frac{-(u_k + \alpha + 1) + \sqrt{(u_k + \alpha + 1)^2 - 4\beta d_k}}{2\beta},
      \\
      \qquad\qquad \text{ for } p_k < 0, \quad l_k > 1,
    \end{cases}\\
  \end{align}
where
:
\begin{align}
      c_k = (1 - ( p_k \text{ mod }1))( u_k +1) - 1,
\\
    S_{l_k} = -( u_k - \alpha + 1 ) p_k + \beta p_k^2,
\\
    l_k = \frac{1 - (S_{l_k} \text{ mod }1)}{ u_k + 1},
    d_k = (S_{l_k} \text{ mod }1) +  u_k.
\end{align}
One of the advantages of described discrete time model
is that it has the only one steady state at (u_k=0,p_k=0).
For practical purposes, only locally (asymptotically) stable steady state, in which the loop returns after small perturbations of its state,
is of interest.
Here the VCO overload conditions have the following form
:
  \begin{align}
    p_k>0,
    u_k<2\beta p_k-1,\\
    p_k<0,
    u_k<\alpha-1.
  \end{align}
If these conditions are satisfied,
then the additional cases of the loop dynamics
have to be taken into account 
.
--Marat Yuldashev 20:33, 29 May 2020 (UTC)
thread_title: Discrete time model of Charge-Pump PLL

message: To explain the classical math model of APLL I may suggest to consider the block diagram of two-phase locked loops. For this model, the derivation of the mathematical model is straightforward (see Phase-locked_loop#Phase_domain_model_of_APLL).
Also I suggest to add APLL schemes in the signal space and in the signal’s phase space.
The models of APLL in the signal space and in the signal’s phase space are distinguished by a term with a double frequency. For the two-phase phase locked loops both models are equivalent (since the phase detector output does not contain the term with a double frequency).
nk (talk) 08:40, 28 May 2020 (UTC)
thread_title:  Mathematical models of APLL and Two-phase PLL

message: I won't criticise the rest because I like that the Big Maths is deferred, and the history and mechanical observation that leads into how a PLL comes to exist is good, better than I expected to find. The only general change I'd expect is to move the chunk describing the main elemental blocks of a PLL to appear right below the early identification of those blocks. The raw mechanics must always come before any finer analysis.
The big omission is the almost absent discussion of how the lock state is indicated. I assume that some degree of phase noise will always exist, so it's not an absolute state, but how much is 'good enough'? At what point is it is correct to indicate lock, and how is it done?
I ask because to reduce capture time it is often required that the oscillator be limited to a range close to the input range, so to avoid confusion of what is good and bad, it is necessary to gate the output off if it's bad! It's a simple concept to understand WHY, but there is next to no discussion of HOW. I know how to do it with a 4046 and a NAND gate, but I do not know how to explain it! :) What's the minimum need, to understand how it is agreed and indicated as 'locked'? More exactly, how do we communicate this to the devices that need to know?
81.187.19.110 (talk) 09:37, 29 May 2022 (UTC)
thread_title:  A fundamental omission: How to indicate phase lock.