Talk:Xenos (graphics chip)

message: Suggest moving to Xenos (GPU). No assertion of usage prominence over other uses for "Xenos". Would favour Xenos (Greek) under first precendences.--ZayZayEM (talk) 05:55, 10 December 2007 (UTC)
replies: text: It would make sense to me, as the concept is the source of the other names. Other possibilities though would be to point this to the disambiguous page. --Falcorian (talk) 17:49, 10 December 2007 (UTC)
replies: text: Should it be Xenos (GPU), Xenos GPU or Xenos (graphical processing unit)--ZayZayEM (talk) 02:09, 11 December 2007 (UTC)

text: I am third his.  am doing something about it.  Naming it in similar way Hollywood chip was named Hollywood (graphics_chip)Oldag07 (talk) 18:13, 9 December 2008 (UTC)
thread_title:  Move 

message: In this article, they seem to have come to a "1.5 billion vertices per second" figure from somewhere. I would assume they thought that since a typical polygon is a triangle with three sides, 1.5 billion vertices, would form 500 million polygons.
So it seems they worked backwards from the "500 million" figures released by Microsoft, and just assumed 1.5 billion vertices from there.
It's my understanding, that typical gpu listings for this figure,  calculate vertex shader processing, by assuming it takes 4 clock cycles to complete the simplest vertex positional transform (matrix * vector). 
So for every vertex shader you have, = 1/4 the clock frequency. That's true of all gpus from what I can tell. And since all polygons in a mesh could (theoretically) be sharing a vertex with it's neighbor in strips and fans, the theoretical maximum polygon count is sometimes "considered" 1 to 1 with vertex rate.
The problem here, is that (being unified) all of Xenos's alus could potentially be processing geometry at once, such would be the case in the z-only pre-pass. But it wouldn't make much sense to list that as a per second figure of 6 billion. And technically, 1 block of alus devoted to vertex work, would be 2 billion vertices per second. But again, even that wouldn't make sense, for a list of reasons.
So, Microsoft listed the "set-up" limit in their specifications. That would be the maximum you could actually draw on screen, after back-face and occlusion culling, etc.. And with a reasonable number of vertex shader instructions (outside of simple transform), you would avoid reaching that limit.
I'm not sure how it should technically be listed, but isn't the 1.5 billion figure ad-lib? It's derived from the "500 million" set-up limit, and quoted as if it's the same measure as you see in other gpus. (which is a listing of transform rate, not set-up rate)
And it lists 16, because that's the number of alus in a single simd block of shaders. You could just as easily devote more than 1 simd blocks of shader alus to vertex work if you found use for it. Or less.
Anyone agree / disagree? Thanks. I won't modify it personally, but I doubt it'd be written up like that officially.
Swapnil 404 (talk) 06:49, 15 September 2009 (UTC)
thread_title:  So, how was the vertex rate figured? 

message: One of the lead engineers who was working on the Xenos (His name escapse me at the moment) stated that the xenos is capable of 96 billion shader ops per second, thats twice the ammount stated by Microsoft, Im assuming that the piplines now do 2 vector4 ops and 2 scalar ops, so 4 ops per pipline and 48*4*500,000,000=96,000,000,000 shader ops per second, I dont know if this is true, or what I said just then made any sense, im just wondering if anyone can confirm or disprove this but if its right can you please post this on the article (If im right I think it may effect everything and definetly make the flop count per pipline 20).  —Preceding unsigned comment added by Gears, Gears, Gears (talk • contribs) 02:49, 29 January 2008 (UTC)
replies: text: Yeah, I remember when he said that. Feldstein I think it was. But I don't think he was implying shader ops. Perhaps shader flops. 4 flop madds per cycle, per shader. Rather than just listing vector and scaler. It could be, that you can issue a vector, scaler, vertex fetch, and texture load, all with-in one instruction cycle. That would be 4. And it would contrast Nvidia, because they hadn't decoupled their texturing ops from shader ops, etc.. And one stalls the other.Swapnil 404 (talk) 02:00, 23 February 2008 (UTC)
replies: text: I remember seeing 64 unified shaders way back before the official releases, was that a downgrade or just speculation?  —Preceding unsigned comment added by 201.81.199.213 (talk) 18:02, 30 April 2008 (UTC)
thread_title:  Double shader preformance for the Xenos? 

message: Evidently someone has changed it incorrectly to that specification.  Although the actual change to the hardware may be coming soon enough: http://www.tgdaily.com/content/view/37376/135/
I'll just leave it as is unless someone else wants to change it for the time left that it is being produced in the 90nm process.
--J5689 (talk) 01:16, 7 July 2008 (UTC)
thread_title:  The Xenos does not use the 65nm process yet 

message: Stupid question:  How much memory does it have?
24.222.205.103 (talk) 16:32, 11 September 2008 (UTC)
thread_title:  Memory 

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thread_title: Image copyright problem with Image:R500gpu.jpg

message: No move Parsecboy (talk) 14:42, 15 December 2008 (UTC)
thread_title:  Requested move 

message: I notice the "maximum" Z-rate when msaa is enabled is wrong. It's listed as 16 gigasamples per second, where it's actually 32. (64 per clock)
http://www.beyond3d.com/content/articles/4/4
"8 pixels writes per cycle, as well as having the capability to double the Z rate when there are no colour operations. However, as the ROP's have been targeted to provide 4x Multi-Sampling FSAA at no penalty this equates to a total capability of 32 colour samples or 64 Z and stencil operations per cycle."
Which would be 32 z samples per second. 
Some people might see it as being kinda misleading being part of the "free" aa expansion in edram, as opposed to raw z fill-rate, but the article already cites the raw z-fill as 8 rops * 2xZ = 16 gigasamples per clock * .500mhz = 8 gigasamples per second.
As long as it specifies 4xmsaa (which it does), it should be fine.
Also outlined by AMD/ATI on page 3 from here: 
http://www.ati.amd.com/developer/eg05-xenos-doggett-final.pdf
Swapnil 404 (talk) 05:05, 15 September 2009 (UTC)
thread_title:  Z-rate with aa enabled. 

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thread_title:  External links modified 

message: The claim that the chip is based off of an R500 series chip is uncited and dubious. There are a number of sources which indicate that the chip is actually more similar in architecture to the R600/HD 2000 series - albeit an early version that does not yet support the full DirectX 10 API - instead supporting an extended version of DirectX 9c. Consider: it supports hardware tessellation (as does the HD2000 series). The claim that it is based off of any specific consumer GPU is in particular dubious as it is clearly a custom part with custom dedicated fixed function units (again, the tessellation unit, but also the memory architecture is also massively different). http://rastergrid.com/blog/2010/09/history-of-hardware-tessellation/
See here, which claims that the GPU is based off of the TeraScale architecture (the codename for the architecture starting with the R600/HD2000 series of GPUs): https://www.techpowerup.com/gpu-specs/ati-xenos-xenon.g424
This article also claims that the Xenos uses a unified shader architecture, which again was not present until the R600 series in mainstream desktop computers: https://www.anandtech.com/show/1719/7
The R500 series still used fixed function pixel and vertex shaders. This is a very significant departure in architectural designs and clearly puts the Xenos chip taxonomically far closer to the R6xx series than the R5xx line even though it predates it. In fact the 5-wide vector unit as a part of a unified architecture which is  described in the article again is a distinctive feature of the R600/TeraScale unified shader architecture. This sounds quite similar to the 5D 'MADD' function of the R580's vertex processors as written here: https://m.hexus.net/tech/reviews/graphics/4477-ati-radeon-x1900-xt-xtx/?page=2 
But the R580's fragment processors do not function like that, showing another distinction between the two parts and architectures.
The introduction of the unified shader architecture represents a very important part in graphics architecture history, having occurred in equivalent generations for both ATi and nVidia graphics processors in the R600 and G80 series of GPUs respectively as DirectX 10 was coming around on PCs and eventually enabling GPGPU programming. As such, labeling this as though it is based off of an architecture using split pixel/vertex shaders as in the R500 series is quite misleading.
— Preceding unsigned comment added by 86.181.181.243 (talk • contribs) 22:02, 29 June 2020 (UTC)
replies: text: According to the documents presented during the patent dispute between LG and ATI, most importantly the R400 document library folder history, the sequencer specification version 2.11, and the sq_alu emulator code, it's clear that the Xenos is based on the original R400 architecture that was way ahead of its time and never appeared in PC graphics cards. The R400 series on the PC actually had an upgraded R300, and the R500 created later was their solution for Direct3D 9.0c features on the PC. The ALU instruction set in the internal emulator, the layout of shader inputs and exports (both the graphics pipeline ones and the passthrough shader exports aka the "memexport" functionality of the Xenos) in the specification, are identical to the ones used in the Xenia Xbox 360 emulator as well as the registers of the Adreno 200 (AMD Z430) based on the Xenos, while the R300, the R500 and the R600 have a large number of major differences, even including the names of the core parts of the pipeline stages (both the R400 documents and the Adreno headers call the shader unit SQ (Sequencer), the ROP unit RB (Render Backend), for example, while in R5xx Acceleration the former is called US, the latter is ZB and CB; on the R6xx the RB is also called DB and CB). The R600 (TeraScale) is way newer than the Xenos (and the R500), supporting Direct3D 10, co-issuing 5 separate instructions for scalars rather than one 4-component vector and one scalar instruction, having an integer ALU. I've corrected the information in the article based on these findings. — Triang3l (talk) 16:49, 10 December 2021 (UTC)
thread_title:  Claims of R5xx/x1900/x1800 'base' chip dubious/uncited