Talk:Instructions per second

message: I found a possible reference for the still unreferenced entries in the timeline table. It is from a book from Kai Qian,David den Haring,Li Cao named Embedded Software Development with C. It can be found under google books: http://books.google.com/books?id=aB1EgF0jB-MC&pg=PA8&lpg=PA8&dq=AMD+Athlon+%223,561+MIPS%22+-wiki&source=bl&ots=pG_B87T73t&sig=P4YYT12GS7tH9quVl9jiGUo5084&hl=de&ei=MQQbTYLmIYvwsgb91OH5DA&sa=X&oi=book_result&ct=result&resnum=1&ved=0CBUQ6AEwAA#v=onepage&q=AMD%20Athlon%20%223%2C561%20MIPS%22%20-wiki&f=false  —Preceding unsigned comment added by 80.238.172.215 (talk) 09:58, 29 December 2010 (UTC)
thread_title:  Reference for the Timeline Table 

message: Hello.  I'm sorry that I don't know how to edit Wikipaedia correctly, but the most of the M- prefixes for the recent processors are incorrect.  They should all be GIPS, not MIPS.  This can easily be confirmed by visiting the link cited in this table.  I would appreciate it if somebody more savvy than I am could correct this.  Thank you.  — Preceding unsigned comment added by 96.255.78.233 (talk) 01:47, 25 November 2011 (UTC)
thread_title:  Errata in Timeline

message: * Aren't timelines usually in chronological order? Shogun 01:07, 21 March 2006 (UTC)
replies: text: yep, they are. I corrected the table. jidan 15:56, 15 May 2006 (UTC)
thread_title:  Timeline 

message: Guys -- The data you posted about the Cell processor is just plain incorrect.  Please update the page.  For the record:
Cell runs at 3.2 GHz.
Cell has one dual-threaded fully 64-bit Power Architecture core.  This core, not including its AltiVec vector processor, does 6400 MIPS... although these are 64-bit instructions so the comparison to 32-bit processors is really not too valid.  (Should we claim that it's 12800 "32-bit MIP equivalents"?)
In ADDITION to the above, the Cell has 8 single-threaded 128-bit processor cores.  That adds 25600 MIPS or 102400 32-bit MIP equivalents... for a total of 38400 (115200).
FLOPS have nothing to do with the above.  In FLOPS, the Cell does over 200 single-precision GFLOPS and in the high teens in double precision.  As of today (30 Mar 2007), information on the next-generation processor has been released... although I am not at liberty to disclose its performance until someone cites it.
The figure you cited was not a peak value (as cited for other processors).  Instead, you took the performance on a given benchmark (Linpack) in FLOPS... which are not comparable to MIPS.
The Cell Team at IBM
:No, you can not multiply the MIPS value by 2 using the excuse that processor has some 64 bit instructions. One 64 bit instruction is still just one instruction. And, let's face it, 64 bit instructions are rarely used in real world applications. After all, 64 bit data is quite rare. Most common data is 8 bit (character data, 8 bit/channel RGB data etc.). In addition, most applications use only 32 bit instruction set in order to be compatible with older processors, so 64 bit processor is no faster than 32 bit one. But even if the program is compiled to use 64 bit insturctions, it will only be around 2% to 5% faster than the 32 bit version.
:Indeed, FLOPS measurement should not be mixed with MIPS. MIPS is only about integer performance. No matter how powerful FPU is included with the CPU, it does not have effect on the MIPS value of the CPU.
:There is no such thing as "peak value" in MIPS measurement. MIPS is the average number of instructions executed by the processor when running a real world application. (Well, the term "peak MIPS" is sometimes used to say that it is the speed of the CPU when the application fully fits in L1 cache so that the memory access is not slowing down the operation. Which is the case with Dhrystone benchmark, for example.)
:-- PauliKL (talk) 22:09, 24 February 2008 (UTC)
replies: text: Yes, but MIPS started in the days when processors did about the same amount per instruction. Before hardware multiply, when you had an MQ register and did shift and add, or shift and subtract, and each instruction operated on one processor word. As hardware changed, and the amount of processing that an instruction, or even a clock cycle, could do change, MIPS became less and less useful. That is why some call it Meaningless Indicator of Processor Speed. Gah4 (talk) 22:08, 23 April 2015 (UTC)
thread_title:  Cell Data is blatantly incorrect 

message: If a microprocessor can execute a singular instruction million times per second (MHz), then why can't it execute a million unique instructions within the same timeframe (MIPS)? What is the game-changing constraint here? This article does not explain this rather bizarre behaviour.Anwar (talk) 10:44, 15 May 2008 (UTC)
replies: text: Huh? What do you mean? MHz is unit of frequency, not unit of instructions per second. In context of processors, MHz is usually used to measure the clock frequency. Traditional CISC processor may require multiple clock cycles to execute one instruction, so they deliver less than 1 MIPS/MHz. RISC processors typically execute every instruction in one clock cycle. In that case, they would execute about as many instructions per second as the MHz value would indicate. Number of instructions executed per second is not same as MIPS, but with 32-bit processors, it is quite close. However, there are processors that can execute multiple instructions in parallel (superscalar). Further, there are processors with multiple cores. These deliver more than 1 MIPS/MHz. --PauliKL (talk) 19:10, 15 May 2008 (UTC)
thread_title:  MIPS = MHz? 

message: Could someone add the Mips of the IBM 704 (1954) and the IBM 7030 (1961) to this table? I'm too dumb to do so. tnx in advance. See also new proposed timeline above. Aleichem (talk) 20:37, 8 June 2008 (UTC)
thread_title:  IBM 704 & IBM 7030 

message: Why were the IBM Mainframe cpus removed? The newest z196 Mainframe have 24 cpus and gives 50.000 MIPS. This means each 196 give 2.000 MIPS each. Please add it. 
The z10 Mainframe with 64 cpus, gives 28.000 MIPS, this means each z10 cpu gives 450 MIPS. Please add that.  — Preceding unsigned comment added by 217.73.15.6 (talk) 11:06, 23 January 2012 (UTC)
thread_title:  IBM Mainframe cpus removed? 

message: I've made some corrections to the DIPS/cycle/core calculations for Intel Core i7 processors, they were half what they should have been because the math was done with the number of logical cores, not physical cores. Please remember to only count the number of PHYSICAL cores in CPUs with HyperThreading. Alereon (talk) 07:45, 11 October 2011 (UTC)
thread_title:  Corrections to DIPS/cycle/core 

message: N270 is single core right?  The Atom entry lists 2.4 and 1.2 as if it is dual core.  I think both values should be 2.4 but would like a second opinion before editing.  thanks.  — Preceding unsigned comment added by 194.46.201.216 (talk) 11:50, 12 October 2012 (UTC)
thread_title:  Atom N270 

message: Intel 8080 MIPS numbers are incorrect and not plausible.  The Intel 8080 and 8085 instructions ran in from 4 to 17 clock cycles each.  There were a few 4 cycle, quite a few each of 5, 7, 10, 11, 13, 16, and 17.  I wrote alot of 8080 code and optimized at the clock-cycle level.  I used a rule of thumb of 10 cycles per instruction and found it a very good generalization.  This would be 0.2MIPS, or 0.1 IPS/Cycle-per-second.  Certainly anything claiming to be authoritative has to be in this ball park.  The table lists 0.33 MIPS, or 6 instructions per clock cycle on average.  This program would be primarily a long string of carefully selected arithmetic instructions with no memory accesses, branding, or stack operations - very unrealistic.  What an average MIPS rate is in the absence of a standard benchmark is debatable, but in no case could one claim an 8080 to be above 0.5 MIPs.  The paragraph just above the table states that a 2MHz 8080 executes 0.64 MIPS.  With the shortest instruction being 4 clock cycles, this is not possible.  Can the originator of the current numbers give any reference or anecdote on which they are based?  
Until someone comes up with an authoritative reference of some sort I would use my numbers of 0.2 MIPS at 2MHz, 0.1 IPS/Cycles per second.  At the very least, the 0.64 should be made consistent with the 0.33, and I would argue that the 0.33 is unrealistic.  If nobody is happy with my number, put a range of 0.2-0.33 depending on instruction mix.  I do not know how to edit and don't want to mess it up.
The new proposed table lists the Altair 8800.  This seems redundant since the 8080 is already listed, but more important it lists it as 10 KIPS.  Per my numbers above, this is 10x too slow.  Even given the possibility of slow memory and wait states, there is no way it could possibly be this slow.  This I believe should be 100KIPS, but not knowing how many wait states it ran to memory over the S100 bus, I cannot give an accurate number.  
The proposed table also lists the 8085 and gives number that are inconsistent with the listed 8080 numbers.  Except for the level of integration, both processors are identical, and execute all instructions in exactly the same number of clock cycles under all conditions.  The mainline 8085 ran at 3MHz vs. the 8080's 2MHz, do the MIPS should be 1.5X listing 3MHz instead of 2, and the IPS/ClockCyclePerSecond should be the same.  If you cranked up the power supply voltage they would run at 10MHz or so :-)   ...   But not for long :-( ...
— Preceding unsigned comment added by Rnsc5j (talk • contribs) 23:00, 25 January 2013 (UTC)
thread_title:  8080 Timing 

message: Last few rows of the summary table were incorrectly added (wrong number of columns etc.), so they should to be fixed.  It would be great if someone could handle that.  Thank you. -- Dsimic (talk) 15:55, 7 October 2013 (UTC)
thread_title:  Summary table needs to be fixed 

message: There is a move discussion in progress on Talk:Kilometres per hour which affects this page. Please participate on that page and not in this talk page section. Thank you.  —RMCD bot 01:00, 10 December 2013 (UTC)
replies: text: I don't see that MIPS got much discussion there, but it doesn't seem appropriate, anyway.  MIPS is not the plural of MIP, though I have seen MIP used as the singular. (VAX is a 1 MIP machine.) Reminds me of my old favorite, LASE and LASING are the verb forms of the acronym LASER. Gah4 (talk) 22:38, 11 November 2015 (UTC)
thread_title: Move discussion in progress

message: In the 1950's and 1960's, computers weren't all that different. Scientific processors commonly had a 36 bit word, and instructions operated on that word size. You could probably make a fair comparison between a DEC PDP-10 and an IBM 7090 based on instruction execution rate. Even so, it is a rough indicator, but sometimes that isn't so bad.  But as processors diverged, it became less useful. Comparing a 6502 with its 8 bit accumulator and an IBM 370/158 with 32 bit registers, based just on instruction execution rate is meaningless.  When comparing members of a family, such as different models of VAX, or different models of IBM S/370, MIPS also tends to work. VAX MIPS, based on a certain VAX processor being 1 MIPS (even when it probably wasn't) and a reasonable set of benchmark programs also might be useful, though it removes the whole meaning behind the acronym. Might as well just compare in relative speed to a specific VAX processor, and not call them VAX MIPS. Gah4 (talk) 12:03, 28 October 2014 (UTC)
replies: text: There doesn't seem to be much interest in figuring out what to do with this. In the 1970's, people did use benchmarks to give MIPS values to machines for comparison purposes, but those benchmarks have to be reasonable for the machines of interest. Also, up through the early 1970's, it was usual to publish instruction timings for processors. But when processors started doing instruction overlap, those timings were meaningless, and they stopped being published. There are probably tables in Datamation that one could search for. About that time, it was realized that the benchmarks being used really weren't useful for comparing real problems. As the minicomputer market grew, new benchmarks were used for them, but not for comparing them to bigger mainframes and supercomputers. The VAX 11/780 was advertised as a 1MIPS machine, and others compared theirs to VAX. As the 8 bit microcomputer market grew, there were benchmarks, but not, as well as I know, measured in MIPS. Given that, this article should have tables based on actual tables from the 1950s to 1970s, one for mainframes, one for minicomputers. As the benchmarks used wouldn't run on the 4004, or many other small computers, those should not be in the table. Also, machines that do instruction overlap should not be, as the benchmarks don't apply. Newer benchmarks were created, but the times don't trace back to MIPS.  Find actual tables, and don't make up numbers! Gah4 (talk) 04:55, 23 October 2015 (UTC)
thread_title:  Meaningless Indicator of Processor Speed 

message: There seems to be disagreement on what MIPS means, but the numbers in the chart seem to be meaningless.  Some suggest that the numbers should be based on a benchmark, and then scaled, but that isn't where the chart numbers come from. Trying to compare an 8080 and 370/158 based on instruction counts is meaningless. Before IBM System/360, machines for commercial use processed characters or decimal digits, and could be reasonably compared by instruction counts. Scientific machines, often with 36 bit words, could also be compared. Comparisons between the two are meaningless. Comparisons against 8 or 16 bit processors against 32 bit processors, on instruction counts, is meaningless. If based on a benchmark, for one, you have to specify the benchmark, and it has to run on all processors being compared. I don't know that there are any references that explain this, though. Gah4 (talk) 05:26, 21 July 2015 (UTC)
thread_title:  Meaningless Indicator of Processor Speed 

message: Is there any interest in fixing this?  As is noted a few times in the discussion, MIPS really isn't millions of instructions per second, but a speed calculated from a benchmark.  Even more, different benchmarks will give different, not really comparable, values.  Seems to me that the only fix is a separate table for each benchmark. That would allow for comparison between machines tested with that benchmark. Most obvious, given the Wikipedia rules, is tables based on published values for each benchmark.  I believe that SPEC doesn't allow one to do their own tests. Some could probably be run on newer, or on existing older machines. Many of the posted numbers have no relation to any benchmark, some are based on instruction timing for a single instruction.  Some are completely unrealistic. I have asked previously, with no hint of any interest. Gah4 (talk) 07:41, 6 May 2016 (UTC)
thread_title:  Changes 

message: These are 8-bit microcontrollers from the MCS-48 family introduced in 1976.  They are not six times faster than the VAX 11/780.  The idea they do 6 MIPS is absurd and false.  They're clocked at 6Mhz, which is not the same thing.  The "source" for this claim is just an advertisement that cites clock rate.  107.141.160.161 (talk) 16:53, 9 August 2016 (UTC)
thread_title:  Intel 8035/8039/8048 entry is wrong 

message: The table seems to indicate that the Dhrystone benchmark was run on machines from the Univac I through the newest Intel multicore processor.  Is this really true? Gah4 (talk) 09:13, 13 August 2016 (UTC)
replies: text: Absolutely not. The first version of the Dhrystone was released in 1984 (IIRC). Many of the machines listed predate 1984, and were decommissioned by the time Dhrystone was released, so it's impossible to have run Dhrystone on them (and hobbyists running Dhrystone on a poorly written simulator of questionable accuracy isn't credible). I also suspect the MIPS ratings for those early machines may have been raw MIPS ratings, so they're not comparable to Dhrystone. Additionally, some of the early computers, microcomputers, and microcontrollers are so lacking in capability, it would have been impossible to run Dhrystone on them in the first place. The table isn't useful because it confuses what IPS is. Is it raw IPS? Or relative IPS? How can raw IPS be made comparable to relative MIPS? How can relative IPS, made by half a dozen different benchmarks or implementations of the same benchmark be comparable? The table ignores all of these questions and is merely a collection of arbitrary MIPS ratings. L9G45AT0 (talk) 08:10, 14 August 2016 (UTC)
replies: text: Probably Dhrystone was released for some of the CPUs that where already out at that time, but probably not for anything older than the Intel 8080. For the 8080: it probably wasn't much in use anymore in 1984, but many silblings of it where, e.g. the Zilog Z80 which was backwards compatible to the Intel 8080 and sold much longer for Desktops as the 8080 (the 8080 was produced until 1990 according to Wikipedia, but at that time probably only for embedded systems). --MrBurns (talk) 14:40, 6 February 2019 (UTC)
thread_title:  Dhrystone 

message: The MIPS ratings for systems with multiple processors appear to be either measured by running multiple instances of a benchmark on each processor/core, or by multiplying the MIPS rating of one processor/core by the number of processors/cores in the system. Other entries appear to add together the MIPS ratings of several processors. Only the first method, running multiple instances of a benchmark on each processor/core is valid; and when this is done, it needs to stated that what is measured is throughput. Given that other entries in the table are not about throughput, having some entries listing throughput and others not, is wrong, confusing, and useless. Should the throughput ratings be removed? L9G45AT0 (talk) 08:31, 14 August 2016 (UTC)
thread_title:  Multiprocessor MIPS 

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message: MOPS (Million Operations Per Second) refers to this article, however, the acronym is not mentioned here. According to bores.com one instruction in a certain processor can do several operations: "two arithmetic operations (an add and a multiply), three memory accesses (two reads and a write), one floating point register update, three address pointer increments". Google also find the meaning "Mega Operations Per Second" for MOPS.
Since IPS, KIPS and GIPS are mentioned in this article, I further wonder whether there are also OPS, KOPS and GOPS? The book "Programming Multicore and Many-core Computing Systems" by Sabri Pllana, Fatos Xhafa, 2017, mentions KOPS (Kilo Operations Per Second). GOPS (Giga Operations Per Second) is found, e.g., in "Handbook of Multimedia Computing" by Borko Furht, 1999. OPS (Operations Per Second) without quantifier prefix seems to be less common. I have found it at least in "Advanced algorithms and architectures for signal processing III" - a proceedings from 1988.
Once all acronyms are explained here, the pages OPS, KOPS and GOPS might get a link to this article, too.--2001:638:A0A:1192:ED2E:FABF:906C:61B7 (talk) 08:50, 14 February 2019 (UTC)
replies: text: Well, it is worse than that.  MIPS, despite the meaning of the acronym, is generally considered a benchmark index.  That is, one compares the speed of a processor on a specific benchmark program (or set of programs) and scales the MIPS value accordingly.  That is also reasonably often done for FLOPS, (MegaFLOPS, GigaFLOPS, etc.).  In the floating point case, since many algorithms have about the same ratio of add/subtract:multiply:divide, it works pretty well.  MIPS not quite a well, but sometimes close enough.  It is less obvious how to count memory access operation, or index register updates that are part of an instruction.  I would think the OPS values would also be benchmark values, but I don't remember seeing them used. Gah4 (talk) 20:16, 14 February 2019 (UTC)
thread_title:  Operations per Second / Instructions per Second 

message: : I've re added the Gibson Mix weights as a collapsed table. This was a widely use metric in the early years of scientific computing and is referenced from several other articles. In collapsed form it doesn't add significant clutter.--agr (talk) 18:32, 21 March 2021 (UTC)
replies: text: Collapsed is better than not, but I still think it's unnecessary detail in this article. I'm all for documenting the history of computing (and you can see my contributions to multiple articles on that), but this seems like trivial arcana relevant to very few readers. --Macrakis (talk) 18:56, 21 March 2021 (UTC)
replies: text: Our articles on the IBM 700/7000 series and IBM System/360, which cover three generations of computing, use the Gibson Mix to describe the floating point performance of some 18 machines. Knowing how it was computed allows one to better understand how those numbers compare to more modern measurements. The Timeline of instructions per second section contains plenty of entries that might be considered "trivial arcana relevant to very few readers." Indeed much of the articles on computer history contain material that could be categorized so. Yet on the whole, Wikipedia is an excellent resource on computer history largely because we do include so much.--agr (talk) 20:57, 21 March 2021 (UTC)
replies: text: I'm not saying that it's unimportant historically, just that it doesn't seem to make sense here: "unnecessary detail in this article". Probably the best solution is to have a separate article on the Gibson Mix as a benchmarking tool. After all, Whetstone, which is still used, isn't documented in detail in this article. Heck, even in its own article, there isn't enough detail given to reproduce it. --Macrakis (talk) 23:43, 21 March 2021 (UTC)
replies: text: A separate article is not an unreasonable suggestion, however the notability bar is higher for a separate article. The references I've found so far are brief. Instruction mix might be a better topic, incorporating Gibson and some others. Right now there seem to be a surfeit of overlapping articles, including Instructions per cycle and Cycles per instruction, and I do not want to add unnecessarily. I'll look into it further.--agr (talk) 15:58, 22 March 2021 (UTC)
thread_title:  The Gibson Mix 

message: If i only want to see the development of x86 CPUs and their MIPS computation power, then this is at the moment not possible, because the table is not sortable by CPU architecture. The table could be improved by separating the CPU model from the architecture and putting the architecture in its own columns. 84.158.123.253 (talk) 18:36, 18 September 2023 (UTC)
thread_title:  Please make the table sort-able by CPU architecture