Talk:Consistency model

message: I notice that the external link to lecture notes suggest that they are copyright Ian Welch 2004. However, the slides bear a striking resemblance to Andrew Tanenbaum's slides that accompany Chapter 6 of his Distributed Systems book. I'm not sure of the policy regarding this. Any thoughts? Tim Watson 18:18, 24 January 2006 (UTC)
thread_title: Welch and Tanenbaum sources

message: What are these "rules" that a programmer must follow to maintain consistency?  —Preceding unsigned comment added by 128.138.64.20 (talk) 05:45, 27 February 2008 (UTC)
thread_title: Programmer's rules

message: The article says "To hold the contract, compilers may reorder some memory instructions". It is widely known that the reverse is true: the compiler may reorder instructions to optimize the code, but in some cases to ensure consistency this must be prevented (by usage of locking constructs or optimization barriers). I'm not sure if the author meant something else, or if this is plain confusion. --Blaisorblade (talk) 05:31, 26 December 2008 (UTC)
replies: text: I was confused by that as well. I don't think consistency is an issue in those languages, because it is assumed that there is only one copy of data that gets stored in memory. If I understand the term "consistent" correctly, the issue applies only when there are multiple copies of the same data. BTW, if that's a correct statement, some version of it should appear in this article. Danielx (talk) 09:04, 18 October 2009 (UTC)
thread_title:  Confusion 

message: Instead of defining it, the first paragraph begs the question.  Please add a definition of the concept to the first sentence.  —Preceding unsigned comment added by 128.61.119.63 (talk) 19:49, 29 April 2011 (UTC)
replies: text: What question are you talking about? ToddBradley (talk) 15:59, 31 January 2013 (UTC)
thread_title:  Begs the question 

message: The one-sentence paragraph "Verifying sequential consistency is undecidable in general, even for finite-state cache-coherence protocols" really reads like a non-sequitur here. This section is an introduction and overview of consistency models, and here is suddenly a sentence containing one specific fact about "sequential consistency" without context. I'm not an expert in this field, but it seems like this fact (that verifying it is "undecidable in general") should be in the separate article about sequential consistency. ToddBradley (talk) 15:59, 31 January 2013 (UTC)
thread_title:  Non-sequitur 

message: Some academics (e.g., ) divide consistency models into data-centric, how what consistency rules are enforced when looking at the distributed system globally, and client-centric, how the consistency rules look from a single client's perspective. Would it make sense to have such a division in this article too? --Cristiklein (talk) 10:45, 7 January 2014 (UTC)
thread_title:  Data-centric vs. client-centric 

message: While stating that processor consistency defined by Goodman is not comparable to the one implemented in DASH, the explanation texts are almost identical for both (except for 2 words). Please compare:
:: All processors need to be consistent in the order in which they see writes done by one processor and in the way they see writes by different processors to the same location (coherence is maintained). However, they do not need to be consistent when the writes are by different processors to different locations.
and:
:: All processors need to be consistent in the order in which they see writes by one processor and in the way they see writes by different processors to the same location. However, they do not need to be consistent when the writes are by different processors to different locations.  — Preceding unsigned comment added by 131.188.6.45 (talk) 16:07, 12 November 2018 (UTC)
thread_title:  Inconsistent definition of Processor Consistency 

message: The following text doesn't make sense: 
:: In Example A, the result is possible only in IBM 370 because read(A) is not issued until the write(A) in that processor is completed. On the other hand, this result is possible in TSO and PC because they allow the reads of the flags before the writes of the flags in a single processor. 
If the result is possible only in IBM 370 how is then possible in TSO and PC as well?  — Preceding unsigned comment added by 141.30.226.34 (talk) 21:20, 23 June 2019 (UTC)
thread_title:  Commentary on relaxed write to read Example A is contradictory