Talk:Multi-channel memory architecture

message: I started the article, as it was requested.  I'm not extremely familiar with the intracite architecture, so more detail would be good.  DoomBringer 00:44, 12 Jun 2005 (UTC)
replies: text: Hello.  Updated to the best of my ability; added the graphic.  Will add a fuller of explanation of Intel vs. AMD later.  --Bobcat 20:54, 11 July 2005 (UTC)
replies: text: Good work.  The graphic could use some work, maybe to show dual vs single: basically, a wider pipe to memory in the dual channel scenario.  I like it though.  DoomBringer 03:10, 12 July 2005 (UTC)
replies: text: No offense, but I think the graphic is misleading.  It represents peripherals (AGP, IDE, and USB) to be as fast as the CPU, which is very wrong.  In fact, they are even slower than the memory controller.  It would be more correct to represent this as an inverted pyramid.  I question the applicability of the term "bottleneck", actually, as a bottleneck is a slow point between two fast points. -- Bilbo1507 02:09, 20 January 2007 (UTC)
thread_title:  Start

message: Some real life data (benchmarks etc.) would be interesting to see. -- 213.253.102.145 16:57, 12 April 2006 (UTC)
replies: text: Oh we're not supposed to just make stuff up and use the power of positive thinking to make it so??  :P  Ya, someone should look into this. -- Bilbo1507 02:28, 20 January 2007 (UTC)
thread_title:  Practical data 

message: As per the entry, "Each memory module in each slot should be identical to the one in its matching slot."  Why is that?  What if they aren't identical? --mriker 03:49, 11 May 2006 (UTC)
replies: text: Internal structure, speed rating  and capacity should match, no need to have identical pairs although there are usually less problems with two identical sticks. --Denniss 16:11, 11 May 2006 (UTC)
replies: text: You should identify that the reason they need to match is because they will be run in sync, and most BIOSes will run them both at the speed of DIMM 0, rather than the fastest compatible speed 
None of this article is particularly true on consumer boards any more, where the RAM sold is often fairly terrible in real speed but contains XMP information saying it should run much faster.  RAM training at boot determines what speed the mess of memory as a whole will actually run at.  I've had the speed go up and CL go down on older memory (i.e. it got faster) after the second bank was populated with faster memory.  It was now running at above its rated XMP speed and below its baseline CL.  Presumably there was a flaw in the motherboard's termination or voltage control logic  somewhere and populating the second bank of quad channel "fixed" it.  I think on old boards with memory controllers on the northbridge the 2nd bank could be running at a different speed than the first.   Usually ECC RDIMMs are matched because the motherboards they're used in don't contain the ability to upclock them past their base speed;  server boards are meant to be stable, not get 2fps more out of something (and their memory bandwidth is already high enough that it isn't the limiting factor, anyway).  If full system memory wasn't purchased at the time the server was built it'll usually be replaced with more identical memory because it's what was on the vendor qualified hardware list, not because other memory wouldn't work.  --A Shortfall Of Gravitas (talk) 12:21, 20 June 2023 (UTC)
thread_title:  Matching pairs of memory 

message: I think its worthwhile to mention that technologies like XDR and FB-DIMM were created with the idea that the high pincount of DDR was a bad thing and those technologies instead seek to have wide internal busses which serialize data into thin external busses by having more on-chip circuitry. Possibly there should be mention of the 480 pins that dual channel DDR-II requires? Unfortunately my wordcraft skills aren't particularily high today.  --222.155.100.80 23:36, 23 June 2006 (UTC)
thread_title:  Criticism 

message: Do dual channel motherboards accept memory which doesn't support dual channel? i.e. is it backward compatible? Would be handy to know...
:There is no memory supporting only single-channel or only dual-channel. All memory sticks may work in dual-channel if you have a pair of two. Best is is identical modules or at least two similar ones (speed grade, memory density). --Denniss 09:55, 1 February 2007 (UTC)
replies: text: Some retail boxed ram, especialy ones from Kingston, sometimes have a "Not Dual-Channel Compatible" warning label on them. I remember occasionally seeing this when I worked for <popular electronics store>. Keep in mind that these usually still work but, as mentioned in this Wiki article, some motherboards may have issues with them. My P4 board with an SIS chipset had no problem dual channel-ing them.66.177.213.82 21:32, 20 August 2007 (UTC)
thread_title:  Question 

message: So, perhaps it should be added by someone who knows the answer.  I'd like to know if RAM, in a dual-channel configuration, continues to run at the same clock speed or not.  For example, PC-3200 RAM runs at 200 MHz.  Would it continue to run at 200 MHz in a dual-channel configuration?  It seems like I've read before that the speed drops in half (100 MHz in this example). Modul8r 22:50, 29 May 2007 (UTC)
replies: text: Why should the speed be cut in half ? In Dual-channel both PC-3200 sticks are still operating at 200 MHz as long as they are compatible to each other and the memory controller likes them, too. --Denniss 11:38, 30 May 2007 (UTC)

text: Your memory would only down-clock if you mixed it with a slower chip. For example, if you put in a PC-2100 chip in there, all your ram would run at 133 MHz.66.177.213.82 21:34, 20 August 2007 (UTC)
thread_title:  I came here for clock speed information and couldn't find it 

message: This article is littered with misabbreviations. I once corrected them, however they were reverted, and the guilty party insisted that "GiB" was the correct abbreviation for gigabytes. Was there some inverse revolution where letters were ADDED to abbreviations, or does this other user not know what he's talking about? Seedsoflight 20:16, 7 September 2007 (UTC)
replies: text: See Binary prefix --Denniss 13:47, 9 September 2007 (UTC)
thread_title:  MB or MiB? 

message: If you only use one stick of DDR2, is the speed effectively halved because it can't use dual channel? 91.84.211.193 10:24, 17 September 2007 (UTC)
replies: text: The maximum memory transfer rate is halved. Usually system performance does not decrease at the same rate but it depends on the board/CPU how much it decreases (a P4 is severely affected but a Core/Athlon64 not that hard). --Denniss  —Preceding signed but undated comment was added at 15:22, 17 September 2007 (UTC)
thread_title:  Dual Channel with one stick 

message: The sole source for this article is currently a whitepaper from two technology companies that stand to benefit from promoting new memory technology. The whitepaper provides an elementary explanation of how dual-channel architecture works, but fails to discuss the question of what kinds of application environments succeed or fail to take advantage of this feature. The wide disparity of benchmark results (as little as about 3% improvement to as much as about 80% improvement, based on the approximate but not clearly stated raw numbers of directly comparable components, and ignoring the sometimes misleading use of chart numbering) makes clear that the identification of these specific environments is vital to understanding whether dual-channel is of any use to a consumer for their particular needs. (That's why I came to this article in the first place.) Can't we find some more objective and more thorough sources for this 4-year-old technology? ~ Jeff Q (talk) 03:45, 20 September 2007 (UTC)
thread_title:  Inadequate information and sourcing 

message: In order to achieve this, two or more DDR/DDR2 SDRAM memory modules must be installed into matching banks
I don't know if this is universal or not, but the sentence above is misleading. Colored banks can (always?) belong to the same channel -- to get dual-channel working correctly, paired modules should be installed to opposite banks, not matching banks. Thus, in a 3-bank configuration where 2 banks are blue and one is black, dual channel setup would require 1 module in a blue slot and 1 module in the black. Ham Pastrami 06:11, 26 October 2007 (UTC)
thread_title:  Modules should be in non-matching banks 

message: If the motherboard has two pairs of differently coloured DIMM sockets (the colours indicate which bank they belong to, bank 0 or bank 1), then one can place a matched pair of memory modules in bank 0, but a different-capacity pair of modules in bank 1, as long as they are of the same speed. Using this scheme, a pair of 1 GiB memory modules in bank 0 and a pair of matched 512 MiB modules in bank 1 would be acceptable for dual-channel operation.[1]
This is highly misleading. First of all, the word "bank" is being used ambiguously to mean a pair of corresponding DIMMs from each channel, which is not technically correct since the term "bank" refers to a single side of a module (paired up for DIMMs). The whitepaper itself refers to these as "DIMM 0" and "DIMM 1" of each channel (A and B). In practice, these would normally be labeled as bank 0/1, 2/3, 4/5, and 6/7 or simply as DIMM-0 through DIMM-3. The rest of the paragraph is also needlessly ambiguous -- what it's trying to say is that you can mix modules of different size in a channel, as long as the configuration is mirrored in the other channel. Which is somewhat redundant with stating the need for matching pairs of DIMMs. I'll try to clean it up later if no one gets around to it. Ham Pastrami 18:15, 26 October 2007 (UTC)
thread_title:  Misuse of "bank" 

message: I'm confused about how the word "bank" is used and it is particularly confusing since the SDRAM chips on the DIMMs themselves each contain 8 banks of DRAM, addressed by the BA[2:0] ("bank address") pins.
My understanding: each memory location is uniquely addressed by (i) channel number, (ii) rank number, (iii) bank address, (iv) row-address and (v) column-address:
* "Channel 0" refers to all memory connected to controller data bits 63:0.
* "Channel 1" refers to all memory connected to controller data bits 127:64.
* "Rank 0" refers to all memory connected to controller chip select CS0_N.
* "Rank 1" refers to all memory connected to controller chip select CS1_N.
* "Bank 7" refers to memory addressed when BA[2:0]=111.
The SDRAMs' address and control pins are shared between channel 0 and channel 1.
A diagram would help here.  —Preceding unsigned comment added by 62.254.223.97 (talk) 16:45, 5 January 2011 (UTC)
thread_title:  Further ambiguity of the term "bank" 

message: I've removed this line from actual results: 
But still there where numerous reports of users who've felt a performance boost from dual-channel. Some users reported a boost circa 70% in comparison to single-channel.
Aside from the terrible grammar and misspelled words, I felt that the lack of evidence and weasel words necessitated the removal until someone can write it up better and provide actual evidence Kakomu (talk) 17:45, 28 April 2008 (UTC)
thread_title:  Actual results 

message: Can anyone explain the difference between these 2? They all increase memory bandwidth. I understand that interleaving helps accessing contiguous memory locations due to locality by overlapping CAS. Dual channel seems to imply no interleaving, but parallel access to both memory modules. This would explain why it generally doesn't improve performance. It wouldn't speed up contiguous accesses up to the virtual memory page size.  —Preceding unsigned comment added by 128.61.49.181 (talk) 10:15, 24 June 2008 (UTC)
replies: text: Memory interleaving is a technical term that means the memory controller stores one block of data in the first module, then the next block in the next module, and so on, until it gets back to the first module. It only makes sense to do if you can access multiple modules in parallel, which usually implies multiple memory buses, although older asynchronous DRAM systems could take advantage of limited interleaving on the same bus by sending commands to the next module before reading results back from the previous one. Dual-channel OTOH is a marketing buzzword which means the system can read from two modules faster than from a single one. Note the use of the word "channel" rather than an actual meaningful word. For example, dual-channel would describe a 2-way interleaved system as well as an early dual CPU Opteron which had two completely separate memory buses. Aij (talk) 00:04, 29 February 2012 (UTC)
replies: text: CPUs have one set of data lines to each channel if you check the pinouts.  The only reason to have this configuration at all, since it eats up die space, is to take advantage of multiple sticks of memory to increase speed, and the easiest way to do that is hardware level striping across them.  In the case of multi-chip processors with memory controllers built in which are fairly new (the Q6600 was an MCM but still had a Northbridge) there is usually a memory controller per-CCD and various striping configurations are possible, although going from 8-way striping on a TR Pro for example to 4x2-way striping doesn't affect overall memory bandwidth as negatively as dropping from 8 to 2 banks does in real world comparisons vs. Ryzens since each CCD is able to fetch from its local memory simultaneously, and the whole mess is really dependent on workload, NUMA-awareness of programs if more than one NUMA node per processor is being used, etc.  Additional banks OTOH usually just add to the capacity and on most systems past dual bank 4-channel broadwell force a drop in overall memory speed to the next lower JEDEC level if the second bank is populated (which might not actually affect bandwidth, since CL usually becomes faster along with clock becoming slower and the two are heavily related). A Shortfall Of Gravitas (talk) 12:41, 20 June 2023 (UTC)
thread_title:  Difference between Interleaving, Dual Channel 

message: A discussion has been started at WP:MOSNUM concerning the continued deprecation of IEC prefixes.  Please comment at the MOSNUM talk page. Thunderbird2 (talk) 19:13, 5 July 2008 (UTC)
thread_title:  Should MOSNUM continue to deprecate IEC prefixes? 

message: Now that everyone is installing 4 slots of memories, is there any quad channel mobo out?  Lightblade (talk) 04:16, 15 August 2008 (UTC)
thread_title:  Quad channel? 

message: i can't believe you people take tom's hardware's garbage as a
source for performance examples.
I put it simple, I run everest 5.5 in DDR2-1066 single channel and I
get 5970MB/sec read, I put it in dual channel (G.skill 2x2GB PI Edition) and I get 7870MB
there's a difference
please take a look somewhere serious like xbitlabs or do your own measures with 
your own computers.
hope it changes before i change the article removing tom's hardware's garbage 
from a serious website like Wikipedia  —Preceding unsigned comment added by 190.31.175.252 (talk) 11:52, 5 August 2010 (UTC)
replies: text: You're measuring the transfer rate using a benchmarking tool designed specifically to maximize transfer rate, i.e. the same assumption that manufacturers use in order to inflate the appearance of performance gain. A real-world application (i.e. software that is not a benchmarking tool) generally cannot be optimized in such a way because they are more constrained by the CPU, I/O, or any number of other bottlenecks. You miss the entire point of the Tom's article, which was to verify real-world performance benefits against the advertising claims and theory, which although true, are meaningless. In other words, your gain of ~50% memory bandwidth results in a gain of only +5% frames per second when running an actual game. That is the point of the Tom's article. Nobody disputed the benchmark scores themselves. Ham Pastrami (talk) 05:59, 12 October 2010 (UTC)
thread_title:  about the measures in performance gain with dual channel 

message: I propose that Triple-channel architecture be merged into Dual-channel architecture and that the article be renamed "Multi-channel architecture" or similar. It seems that having seperate articles is redundant, as the two concepts are very similar. 98.103.186.3 (talk) 18:15, 18 January 2011 (UTC)
replies: text: Agree. Please just do this, as it is highly logical so needs no mass discussion. Use "Multi-channel architecture" and do sections for "Dual-channel architecture", "Triple-channel architecture", and "Quad-channel architecture". But PLEASE make sure you sort all the current link-to's to link to the new appropriate section on the new page, eg. "Multi-channel architecture#Dual-channel architecture". --Jimthing (talk) 17:33, 31 August 2011 (UTC)

text: Agree. The technology behind this is similar, and most of the content will overlap in each article. GL1zdA (talk) 15:06, 20 September 2011 (UTC)

text: Okay. Since there haven't been any No's so far and since this seems like a good thing to do, I am going to go ahead and do it. Arjun G. Menon (talk · mail) 07:01, 1 October 2011 (UTC)
thread_title:  Merger proposal 

message: The article is need of improvement. Any experts on the subject are welcome to add info to this article. For others, the German Wikipedia article on Dual Channel memory could be used for reference for improving this article. Arjun G. Menon (talk · mail) 08:06, 1 October 2011 (UTC)
thread_title:  Article needs to be improved 

message: What happened with quad-channel memory?  — Preceding unsigned comment added by 80.187.151.86 (talk) 10:59, 6 January 2012 (UTC)
thread_title:  X79 and quad-channel? 

message: What is the Bottleneck diagram supposed to tell me? That my USB port is faster than my memory? That peripheral data has to go through memory before it goes to a CPU? I don't think it's the right way of visualizing the Bottleneck principle. It does not visualize how fast memory is in comparison to mos peripherals. Please help me out but isn't the bottleneck in numbercrunching usally CPU->RAM->CPU.  — Preceding unsigned comment added by 92.205.102.196 (talk) 10:54, 3 July 2012 (UTC)
replies: text: Commented out so not visible.  It would be useful to have an updated version with the salient bottleneck issue. A possible separate pair of images showing single channel/dual channel would also help. Widefox; talk 14:14, 25 October 2012 (UTC)
thread_title:  Bottleneck What the Hell 

message: This section mentions that unganged multi-channel memory could be used to speed up multi-threading, but since a multi-threading program shares a common virtual address space, how would a multi-threading application allocate memory so that the physical pages of memory ended up on separate unganged busses of memory? For a multi-processing application (separate virtual address space for each process), it could be possible for the operating system to allocate paged memory from separate busses for 2 to 4 processes (for double to quad channel memory), but I don't know if there are any operating systems that do this. Rcgldr (talk) 03:03, 23 May 2013 (UTC)
replies: text: In unganged mode, a core is assigned to use only one of the memory buses. A thread will only run on one core, so it doesn't have to worry about multiple buses. 65.87.26.124 (talk) 01:08, 9 January 2014 (UTC)
replies: text:  It could be envisioned in the same way RAID 0 works, when compared to JBOD.  With RAID 0 (ganged mode), it's up to the additional logic layer to provide better (ideally even) usage of all available hardware units (HDDs, memory banks); with JBOD (unganged mode) it's relied on the statictical usage patterns to ensure even usage of all available hardware units.  I'll try to find a reference, and add this into the article. — Dsimic (talk) 01:20, 9 January 2014 (UTC)
thread_title:  ganged versus unganged 

message: I have edited the list of quad-channel supporting CPUs to include more 2nd and 3rd gen. chips and 4th gen. Haswell chips. I pulled everything from ARK and went through checking for supporting families. Everything should be updated until the E7 series is launched this fall. The AMD list could use updating too. --Jsd45 (talk) 23:47, 30 September 2014 (UTC)
thread_title:  Quad-Channel Haswell-E  

message: I think there should be something in the article about the first dual channel chipsets. If I remember correctly, the first Dual Channel chipset was the Intel 850 (11/2000) and the first DDR-SDRAM Dual Channel chipset was the nVidia nForce (06/2001). --MrBurns (talk) 14:09, 25 November 2014 (UTC)
replies: text: Hello!  That sounds like a good suggestion; any chances, please, for providing a few references for that? — Dsimic (talk | contribs) 19:08, 27 November 2014 (UTC)
thread_title:  Dual Channel History 

message: Please validate these information. I have not the technical knowledge to do it myself.
http://www.mersenneforum.org/showthread.php?t=20575
93.88.103.166 (talk) 18:30, 14 April 2017 (UTC)
thread_title:  Found some benchmarks