Talk:CMOS

message: Here's a link i'll bookmark here about CMOS imaging.
*PDF Format - Why CMOS Image Sensors are Poised to Surpass CCDs
I'm no wikipedian (yet...) but it might be a good idea to create a CMOS(image_sensor) thingie? /Erik
:yeah, you can be linked here hoping to find information about the image sensor, and you find a completely unrelated article, if nobody else does it i'll give it a try when i have some time. -- Joolz 16:29, 6 Mar 2005 (UTC)
replies: text: Um, this article isn't completely unrelated.  A CMOS image sensor is a sensor that uses the P/N junction available in a standard CMOS process as the photodetector.  Thus the image sensor can be fabbed on a normal CMOS production line, which means they get to take advantage of either (a) older 0.25um lines which have been completely amortized at this point, and so produce fairly cheap silicon or (b) newer, tighter lines which get smaller pixels on the sensor.Iain McClatchie 08:26, 7 Mar 2005 (UTC)
thread_title: Image sensor

message: I added some info on the recent problems with static power consumption. I wonder if is is too much or too little. There is, of course a lot to be said on the subject. For instance, it is not only sub-threshold leakage, but also effects like gate tunneling and several others. The current way of handling this is to use MTCMOS, Multiple Threshold CMOS. This makes it possible to have transistors with different threshold voltages on the same chip. So we can have both high speed, high leakage gates and low speed, low leakage on the same chip. This has been used all the way back to 0.18 micrometre cell libraries.
I have heard reports of some designs that had a static power consumption of up to 50% of total power. 
What do you guys think? How much shuld we write about this?
:Where has your text gone? The basics should be explained. There's a badly rated article on this, see my merger proposal from multithreshold-CMOS.  —Preceding unsigned comment added by 153.96.104.2 (talk) 11:08, 17 August 2009 (UTC)
thread_title: Static power consumption

message: Where are the Missing HYPENS
CMOS stands for Complementary METAL-OXIDE-SEMICONDUCTOR.
This is NOT the same as Complementary Metal Oxide Semiconductor. 
The Construction method is A base layer of N-type or
P-type Semiconductor material (usually SILICON).
An insulating layer of Silicon Dioxide is then deposited on
the semiconductor layer.
A layer of a metal usually Aluminum or tungsten is then deposited on the metal layer .
Regions of both P-Type and N-type semiconductor is then made on the the surface.
This creates the necessary complementary transistor junctions needed for
the basic GATE package.
The use of the three layers of METAL,OXIDE,SEMICONDUCTOR is the derivation
of the ACRONYM MOS    NOT a mythical not existent Metal Oxide Based Semiconductor material.
— Preceding unsigned comment added by 203.87.74.39 (talk) 23:20, 23 July 2004 (UTC)
replies: text: Now starts WW3. EEng 18:23, 26 April 2019 (UTC)
replies: text: Apparently not. It's been more than 24 hours since I made that comment and edited the article to use "Complementary metal-oxide semiconductor", and there is no sign of trouble so far. —BarrelProof (talk) 22:04, 27 April 2019 (UTC)
replies: text: Your version would suggest that there's a metal oxide involved, and that the relationship of the semiconductor to the metal and the oxide is not symmetric. That's just wrong. It's about a stack of materials: metal–oxide–semiconductor. The oxide is usually silicon dioxide, and the metal is often not a metal, but that's what it refers to and that's why dashes are used in sources that want to help the reader parse the meaning.  Dicklyon (talk) 22:08, 27 April 2019 (UTC)
replies: text: It's good to see that someone is paying attention. Your explanation is much more clear than that of the IP in 2004. —BarrelProof (talk) 22:51, 27 April 2019 (UTC)
replies: text: I'll drink to that. Dicklyon (talk) 02:18, 28 April 2019 (UTC)
thread_title: Hyphens?

message: Is CMOS a special case of MIS (metal insulator semiconductor)?
--Abdull 17:48, 18 Jun 2005 (UTC)
replies: text: CMOS is a design methodology (complimentary gate networks), not really a type of gate manufacture technology.  CMOS uses MOSFET gates. -- uberpenguin 20:50, 2005 Jun 18 (UTC)
I find it confusing when the same word means 2 very different things.
In this case, we have:
* the "static logic" CMOS design methodology logic family that involves complementary gate networks, both  active pull-up and  active pull-down, such that no matter whether the clock or any other input is high or low, the output pin is either pulled-up or pulled-down, but not both. Such a design technique is a kind of  static logic, since it holds its state properly when the clock is stopped, and also uses almost no power when the clock is stopped. Such designs could theoretically be implemented with several fabrication technologies such as discrete nFET and pFET transistors, BiCMOS, silicon on insulator, etc., although most implementations use the CMOS chip fabrication technology. Many modern CPUs do not use this CMOS design methodology -- instead they use dynamic logic (digital logic).
* the CMOS chip fabrication technology, which puts both nFETs and pFETs on the same chip. Practically all transistors produced in the world today are produced using this fabrication technology, including all modern CPUs. This fabrication technology can be used to produce both digital static logic ("CMOS design methodology") and digital dynamic logic chips, as well as analog chips (in particular, CMOS sensor) and mixed-signal chips.
What can we do to reduce the confusion?
Is there 2 other terms (other than "CMOS") that would be more appropriate for these 2 things?
--68.0.124.33 (talk) 04:02, 23 August 2008 (UTC)
thread_title:  MIS 

message: Is there a better article for all the how-to tips on configuring PCs? It doesn't feel to me as if they belong here; I wouldn't put a set of instructions for my CMOS wristwatch here.   Where to put the how-to information? --Wtshymanski 17:18, 20 Jun 2005 (UTC)
replies: text: The BIOS CMOS deserves a separate article of its own, linked from both CMOS and BIOS. The howto roadmap (it would have to be more detailed to warrant calling it tips) could then fit in better. --Shaddack 21:02, 20 Jun 2005 (UTC)
replies: text: Done. Iain McClatchie 07:53, 26 Jun 2005 (UTC)
replies: text:  Now at CMOS RAM, aka Nonvolatile BIOS memory. --68.0.124.33 (talk) 16:31, 22 August 2008 (UTC)
thread_title: How-to tips should be moved

message: These are notes for myself or anyone else who feels like contributing.  It seems like a lot of artwork, I guess because hardware design, especially process and layout, is quite visual.
* Better explanation of the difference between a CMOS circuit and a CMOS process
* Cross section of a PMOS gate, and another cross section of an NMOS gate, in a double-well process (substrate and a simple NWELL implant).
* Same diagram, pointing out the unwanted PNP transistors and the resulting SCR.  Description of latchup (forward bias the source/drain diode to well/diffusion, turn on the PNP, turn on the SCR, kablooey).  Description of how latchup is prevented.
Diagrams of various major process options:
* Cross section of PMOS and NMOS gates, triple well process
* Cross section of PMOS and NMOS gates in a SOI process.
For each of those process options, a series of pictures showing how they get built up would be nice.  This is a lot of artwork, but I think it's the best way to convey the information.
I'd also like to see a representation of the scale of modern chips.  Perhaps artwork of a transistor (100 nm indicated), then an inverter (1 um indicated), that inverter amidst rows of standard cells (10 um indicated), rows of standard cells in a block (100 um indicated), and a micrograph of a chip or full chip layout (1 mm indicated) with a block labelled.  Each pic could have a scale and highlight the component in the previous pic.
And, um, if anyone is going to comment that this material has to be structured, broken into many pages, yes, of course, but first it must be written and drawn, which is a lot harder.
Iain McClatchie 21:30, 30 October 2005 (UTC)
replies: text: Latchup already has its own article. --Shaddack 05:24, 21 January 2006 (UTC)
thread_title:  Stuff I'd like to see here 

message: Hi,, Can you please explain if their is a chip call "CMOS RAM"?
Or where we can find CMOS chip? is with in ROM chip?
pat..
:See CMOS RAM. It used to be a SRAM with a back-up battery, but today's it's mostly a serial EEPROM. --Shaddack 05:20, 21 January 2006 (UTC)
thread_title:  About CMOS 

message: So how do CMOS sensors compare to CCDs? I remember reading somewhere that although the CCDs are harder to manufacter, they are better for image quality; but then, I've also read that CMOS sensors are better in that way. And how do 3CCDs compare to a single CMOS? —The preceding unsigned comment was added by 24.23.6.222 (talk • contribs) .
:A CMOS sensor uses a CMOS inverter per pixel as a preamplifier. This reduces the space available for the photodiode, and in turn the sensitivity and dynamic range.--Arnero 14:55, 28 January 2006 (UTC)
replies: text: but presumablly it also means they can be fabricated in a standard cmos fab and i believe there is a LOT of spare capacity in older (Larger feature) CMOS fabs that people are looking to find other uses for. Plugwash 17:51, 28 January 2006 (UTC)
replies: text: So what is the difference then? A CCD only needs nMOSFETs and under-utilizes a CMOS-Fab. But presumablly it needs higher quality silicon, to not loose any electrons in the very long chain to the first amplifier.--Arnero 13:34, 29 January 2006 (UTC)
thread_title:  CMOS vs CCD 

message: In addition to high-k dielectics, another approach to gate leakage reduction is to use a silicon superlattice to enhance drive current whilst siultaneously reducing leakage. This has advantages that it can be incorporated into the production process without costly re-tooling and also superadded onto other techniques such as silicon-on-insulator (SOI), giving additive benefits. See "Addressing Gate leakage with Rerengineered Silicon" (www.reed-electronics.com/semiconductor/article/CA6418540?pubdate=3%2F1%2F2007Lesterruss 10:55, 25 March 2007 (UTC)
thread_title: gate leakage reduction with a silicon superlattice

message: Who invented CMOS technology? --Abdull 22:00, 30 November 2007 (UTC)
replies: text: According to this page, Frank Wanlass of Fairchild Semi in 1963. Others say Wanlass and Sah. Dicklyon 05:58, 1 December 2007 (UTC)
thread_title:  CMOS' invention 

message: I think that the layout is bad. There are no connection to the polysilicon gates, and the desing won't work. See  for a good nand layout.  —Preceding unsigned comment added by 200.126.158.167 (talk) 06:53, 18 September 2008 (UTC)
replies: text: It seems alright to me.  The picture you linked to doesn't have anything more that resembles a connection to the polysilicon gate.  I think the overlapping of the polysilicon onto the NMOS and PMOS is clear enough.Liuyuan Chen 21:01, 19 September 2008 (UTC)
replies: text: The one he linked does show contacts to metal lines that come in from the edge of the cell.  It would be nice to see that on the layout we have, but some cells like this one are designed so that you can lay down contacts later.  The fact that they're missing doesn't make it wrong. Dicklyon (talk) 02:12, 20 September 2008 (UTC)
thread_title:  NAND Layout 

message: do they use enhancement or depletion mode mosfets?  or both? - Omegatron 02:19, July 11, 2005 (UTC)
:CMOS always uses all enhancement-mode MOSFETs (in other words, a zero gate-to-source voltage turns the transistor off).
:(Should we specifically mention that in this article, or delegate it to the MOSFET article?)
:Depletion-mode MOSFETs are on (conducting) when the gate-to-source voltage is zero.
:It's physically possible to wire up some depletion-mode MOSFETs in a typical CMOS configuration. Such a hypothetical depletion-mode gate, by itself, might seem to "work" if you applied an input voltage far enough *above* the VCC rail to turn off the pFETs, or far enough *below* the GND rail to turn off the nFETs.
:But an input voltage anywhere between the power rails (such as the output voltage from a similar gate) would turn on all the transistors in the gate, both depletion-mode pFETs and depletion-mode nFETs, shorting the power rails together.
:As far as I know, the only depletion-mode mosfets ever used in digital logic were in the long-obsolete HMOS logic family.
:For more information on enhancement mode vs. depletion mode, see MOSFET#Depletion-mode MOSFETs and Field effect transistor#FET operation.
--68.0.124.33 (talk) 22:11, 22 August 2008 (UTC)
replies: text:  I'll mention it briefly in Technical details. - Rod57 (talk) 08:33, 4 January 2016 (UTC)
thread_title:  Enhancement or depletion? 

message: I have a little problem w/the lack of explanation for the NAND layout. If you look at the polies, below them is diffusion. This makes them depletion-type MOSFETs. Now I realize that by convention when a CMOS layout is drawn a single monolithic diffusion is drawn for both the drain and the source, making channel under the gate by default, and that it's up to the reader to intuitively know that below the poly is really substrate or well. Unfortunately, I didn't know that last week, and had to find my prof before I could understand. I think this should be explained in the article. AngusCA (talk) 05:42, 15 February 2010 (UTC)
replies: text: You could be bold and put something in yourself if you understand it, and think it will improve the article. Jwoodger (talk) 05:50, 15 February 2010 (UTC)
replies: text: With the kind of trash-talk I've taken for making a perfectly reasonable but infeasible suggestion on a talk page, calling attention to a point of confusion about something I only learned last week is the boldest I get. AngusCA (talk) 04:20, 16 February 2010 (UTC)
thread_title:  Depletion CMOS? 

message: In the image Cmos_impurity_profile.PNG, which shows a cross-section of a chip with a CMOS inverter, aren't the Source and Drain mis-identified in the PMOS transistor? Thank you 69.27.178.6 (talk) 18:15, 6 February 2009 (UTC)
replies: text: Most likely, that transistor would be hooked up the other way around, based on the proximity of the transistors to each other and to the power rails.  But as drawn, there's nothing to actually determine which would be source and which drain.  It would be better to leave off the S and D, or maybe label them each as S/D.  Or draw some connections to make an inverter.  Dicklyon (talk) 15:20, 14 October 2009 (UTC)
thread_title:  Source/Drain mis-identification? 

message: That badly rated page nicely explains some details of state-of-the-art measures to bring down static power consumption of CMOS circuits. It should be merged into the section on static power on this page.
Additionally, the section on static power here needs a brush up as well. -- Joerg Schreiter
: Perhaps the multi-threshold article should be changed to a power-saving page, and other techniques of power saving could be added, including a link to this CMOS page? Brews ohare (talk) 14:22, 14 October 2009 (UTC)
thread_title:  Merger proposal :  [[Multi-threshold CMOS]] 

message: Baker is an excellent source for the entire subject of this page. It is cited in connection with its discussion of the original patent, but has a lto more to say (about 1000 pages). Brews ohare (talk) 14:20, 14 October 2009 (UTC)
replies: text: Yes, Jake did a good book; but it's not the source used to write the article.  And I notice that he or someone spammed his book and web site over a bunch of pages already, including this one:  .  There's no point adding "further reading" junk like that, nor citing a ref in irrelevant places, esp. in the lead paragraph.  Dicklyon (talk) 15:10, 14 October 2009 (UTC)
replies: text: It is not pertinent whether Jake's book was used to write the article; it is a pivotal work in this area and should be cited. The reference to the patent number is fine, but it is not linked, and the link to Jake's book provides not only the historical figures from that paper, but a full intro to the CMOS technology. Eliminating this source as an in-line reference with a link is a backward step. Brews ohare (talk) 15:40, 14 October 2009 (UTC)
thread_title:  Baker reference 

message: I'm not sure, but it seems that first paragraph of article contains sentences it should not contain. It references how wide is CMOS in use. It does not define CMOS by itself.
Article contains repetitive topics, also. User:Vanished user 8ij3r8jwefi 13:59, 28 November 2009 (UTC)
thread_title:  First paragraph and topic repetition 

message: A sentence in the "Temperature range" section reads "There were theoretical indications as early as August 2008 that silicon CMOS will work down to 40 kelvin, or -243 °C.[2]"
Isn't 40 kelvin -233 °C, not -243 °C? Conversely, wouldn't -243 °C be 30 kelvin?
If anyone has read the cited paper (Edwards C, "Temperature control", Engineering & Technology Magazine 26 July - 8 August 2008, IET), please correct one or the other to make them consistent.
Based on the paragraph alone, 40 kelvin is probably correct and -243 °C is probably erroneous. . .  —Preceding unsigned comment added by Needlesslystilted (talk • contribs) 00:44, 11 January 2010 (UTC)
thread_title:  Temperature range error? 

message: This statement from the "Inversion" section is completely nonsensical:
"CMOS circuits are constructed so that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor."
The original author is trying to make the point that, with pFETs in a static CMOS digital circuit, the drain/source terminals are either connected to a positive voltage (greater than the threshold voltage, VT), or be tied to a node which includes the gate of another MOSFET.
This article is hectic and not well-written. The entire article requires a complete overhaul. For example, the "NAND gate in physical layout" section shows a cross section of the silicon stack itself, but there is no gate. There's just two, disjoined transistors. The diagram of the NAND gate's top-level layout doesn't include the layer for a p-well or n-well. Further, I believe that the article should be split in to two: CMOS-as-a-process-technology, and CMOS-as-a-circuit-technology.
I know that Wikipedia has a tag to indicate that an article requires a re-write, but I can find no policy on when a re-write is justified or allowed. I'd really like to fix this article, but I realize that it will require a lot more than some strategically-placed bandages. Can anyone tell me where I should be directing my efforts in requesting an article re-write?  —Preceding unsigned comment added by Cinnanom (talk • contribs) 14:48, 28 August 2010 (UTC)
thread_title:  Article Rewrite Required 

message: I don't think this is a very nice article on CMOS. At a minimum, there should be a reference to the 5400 family and a schematic of a NOR so it can be visually compared to a NAND. The inverter's image is repeated twice in the article. This article does not show good substance. Here are some additional comments.
1. The sentence "There are small reverse leakage currents which is formed due to formation of reverse biased between diffusion regions and wells." needs fixing.
2. The sentence "In modern process diode leakage is very small compared to sub threshold and tunnelling currents, so these may be neglected during power calculations." needs corrections.
3. "1.d. Contention current in ratioed circuit" is an incomplete section and it needs expanding.
4. I made several corrections in the "Power: switching and leakage". For some reason, lots of words were capitalized. There were also plenty of misspellings so I assume the section is relatively new.
ICE77 (talk) 01:08, 22 February 2011 (UTC)
replies: text: WP:SOFIXIT.  Dicklyon (talk) 03:40, 22 February 2011 (UTC)
thread_title:  Corrections and comments 

message: The most of data signals usually have very low activity factors (0-0.2), except maybe for domino logic (which is used rarely today). I fixed "0.5" used in the article by 0.1 and added link to the paper in which there is a distribution of % of signals vs. their activity factor. In general, I think the "activity factor" is not explained well in the article, in my opinion it should be added as an independent article in Wikipedia (working on it...)
Mkostya (talk) 18:23, 18 August 2012 (UTC)
thread_title:  Dynamic power consumption 

message: Some people correctly point out that pass transistor logic and dynamic logic (digital electronics) don't seem to match the description at CMOS#Duality.
So when they see circuits in those and other logic family#On-chip design styles, they ask "why is this ... considered a CMOS circuit?" (Talk:XOR gate#Why is that CMOS?)
My understanding is that there is a very specific logic family F that does match the description at CMOS#Duality.
My understanding is that there is a more general category C of circuits constructed from both nFET and pFET transistors that includes many logic families, including F, pass transistor logic, and dynamic logic.
The ambiguity arises because most people talking about F call it "CMOS", and most people talking about C call that "CMOS".
There are many other cases where people use the same word to refer to some general category C in one sentence, and the same word to refer to some specific case F in another sentence -- genericized trademark, metonymy, etc.
Is there some more specific terms we could at least mention in this article, one term that unambiguously refers to F and a different term that unambiguously refers to C?
--DavidCary (talk) 01:57, 16 October 2015 (UTC)
replies: text: Cinnanom (above: Rewrite required) suggests CMOS as a logic, and CMOS as a technology - is that the same distinction you are making ? - Rod57 (talk) 13:38, 28 May 2018 (UTC)
thread_title:  unambiguous terms, two uses of CMOS

message: "high Vth transistors are used when switching speed is very important, while low Vth transistors are used in speed sensitive paths" doesn't read properly for me. Missing the word "less", perhaps?
Sorry if I'm using the wrong approach to flag the issue -- I'm NOT an experienced contributer!
Cabbageears (talk) 01:37, 17 October 2015 (UTC)
replies: text: Someone has fixed with "not" for high vth. - Rod57 (talk) 14:35, 28 May 2018 (UTC)
thread_title:  high Vth vs low Vth wording 

message: The denser VLSI processors 14 nm, 10 nm, Intel's 22 nm etc seem to all use FinFET to achieve the high densities (and low power). Could mention here. Maybe need a clearer separation of CMOS logic from CMOS technology processes ? - Rod57 (talk) 10:23, 23 June 2017 (UTC)
thread_title:  Should we mention FinFET here 

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thread_title:  External links modified 

message: Per ongoing discussion at Wikipedia:Village_pump_(proposals)#RfC:_Delete_IABot_talk_page_posts? and Template_talk:Sourcecheck#Can_we_change_the_standard_message_to_says_its_OK_to_delete_the_entire_talk_page_section I'd like to delete the above External links modified section. Any objections ? - Rod57 (talk) 18:57, 30 May 2018 (UTC)
thread_title: Proposed talk page edit

message: Under Technical details is it ok to say that other materials can be used apart from silicon. eg  Germanium  for research. Does GaN enhancement mode transistors  mean GaN could be used for CMOS? If not, what else is needed ? - Rod57 (talk) 13:32, 28 May 2018 (UTC)
replies: text: OK, HRL claims CMOS using GaN (and AlGaN) (just 2 transistors on one chip!) : HRL Laboratories claims first gallium nitride CMOS transistor fabrication. Feb 2016 "gate widths of the PMOS and NMOS transistors were 500μm and 50μm, respectively." "With 5V pulses with steps of 10ns rise/fall times, the output swung between 0V and ~5V with 90ns fall and 670ns rise. "Slower rise time is due to higher on-resistance of the PMOS. Although the performance is yet to be improved, the functional inverter IC proves the feasibility of the GaN CMOS technology."" - Rod57 (talk) 18:41, 30 May 2018 (UTC)
thread_title:  What can be used instead of silicon