Talk:Simultaneous multithreading

message: Montecito uses SMT: http://www.doc.ic.ac.uk/~phjk/AdvancedCompArchitecture/PastPapers/2003-2004-MEng3Test.pdf you can read at 1.b: "In a proposed simultaneous multi-threading (SMT, also known as hyperthreaded) Itanium 2 design, a single CPU core is extended with two program counters, and two register sets, so that it can execute two different threads at the same time. Referring to Figure 1 (page 46), identify which parts of the design would have to be changed, and explain briefly what would have to be done." --134.155.99.41 07:53, 24 November 2006 (UTC)
thread_title: Montecito

message: As The Register points out
http://www.reghardware.co.uk/2008/04/03/idf_inside_silverthorne/page2.html
Intel is launching a new type of CPU that uses HyperThreading in place of out-of-order execution so some mention should be made about this.
Hcobb (talk) 18:01, 22 April 2008 (UTC)
thread_title: Diamondville isn't out of order

message: I haven't the references for this but as far as I know the ICL Series 39 machines had a 'B-pipe' which was exclusively for system use. It did the initial handling of interrupts, scheduled task switches, and did virtual to real address translations for the I/O. Individual micro instructions were taken from the B-pipe when there was a gap in the main pipe - or when necessary for example after an interrupt it happened the other way round. Dmcq (talk) 10:05, 28 September 2008 (UTC)
thread_title:  Another early example 

message: I've seen SMT presented in a few different courses and textbooks, and what they usually do is view it from the superscalar utilization angle, define two kinds of waste - "horizontal" and "vertical", and then show how SMT reduces both kinds of waste. IMHO, this presentation is easier to understand. (This is also the method that Tullsen, Eggers and Levy adopt in their seminal paper introducing SMT) 
I'd like to re-organize the article in that fashion. Are there any thoughts/comments/concerns on this?
--Pramod 06:34, 3 January 2009 (UTC)
thread_title:  Article needs reorganization? 

message: Does this really have anything to do with multithreading?
"Programs written before multiprocessor and multicore designs were prevalent commonly did not optimize cache access because on a single CPU system there is only a single cache which is always coherent with itself. On a multiprocessor system each CPU or core will typically have its own cache, which is interlinked with the cache of other CPU/cores in the system to maintain cache coherency. If thread A accesses a memory location [00] and thread B then accesses memory location [01] it can cause an intercache transaction particularly where the cache line fill exceeds 2 bytes, as is the case for all modern processors."
If you have a single core implementation with multithreading then you have "a single cache which is always coherent with itself" and the description of thrashing between multiple caches is moot.  And if you have a multiprocessor implementation even without multithreading then you have this problem.  As such, it seems more like it belongs in a multiprocessor and/or coherency article.
75.25.154.173 (talk) 23:47, 4 June 2010 (UTC)
thread_title:  Cache Thrashing Description? 

message: The MIPS 34K and 1004K soft CPUs implement a type of barrel-processing MT. These CPUs are single-issue (not superscalar) so they do not implement SMT. Dyl (talk) 03:08, 12 October 2010 (UTC)
thread_title:  MIPS multithreading not SMT 

message: A disambiguation page should be created for the abbreviation SMT. I'd appreciate if anyone more experienced than me could do that.  — Preceding unsigned comment added by Guissoares (talk • contribs) 20:42, 15 March 2011 (UTC)
thread_title:  Disambiguation 

message: How about adding:
SPARC64 VI (2 cores with 2-way VMT+CMP), SPARC64 VII (4 cores with 2-way SMT), SPARC64 VII+ (4 cores with 2-way SMT). Newer designs by Fuijtsu for HPC applications doesn thave SMT: SPARC64 VIIIfx (8 cores without SMT, but with HPC extensions), SPARC64 IXfx (16 cores without SMT)
Intel Larrabe GPU (4 or 8-way SMT)
All GPUs since introduction of programmable shaders have SMT built-in (with as high as 512 threads per core).  — Preceding unsigned comment added by 91.213.255.7 (talk) 16:15, 7 December 2011 (UTC)
thread_title:  Other implementations 

message: This term is used in this article without clearly explaining what it means. (What is being optimized here? Cost, power, size, time?) Hcobb (talk) 01:18, 20 January 2013 (UTC)
thread_title:  efficiency solution 

message: Hey everyone. What type of cleanup this article requires? InfocenterM (talk) 13:50, 29 July 2013 (UTC)
thread_title:  Cleanup 

message: Hello fellow Wikipedians,
I have just added archive links to  on Simultaneous multithreading. Please take a moment to review my edit. If necessary, add  after the link to keep me from modifying it. Alternatively, you can add  to keep me off the page altogether. I made the following changes:
*Added archive http://web.archive.org/web/20060411091555/http://www.princeton.edu:80/~jdonald/research/hyperthreading/ to http://www.princeton.edu/~jdonald/research/hyperthreading/
*Added archive http://web.archive.org/web/20031004003818/http://www.cs.washington.edu:80/research/smt to http://www.cs.washington.edu/research/smt/
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thread_title:  External links modified