Talk:Cyrix 6x86

message: "It has six performance levels: PR 90+, PR 120+, PR 133+, PR 150+, PR 166+ and PR 200+"
i'm sure i always saw theese advertised without the R and they were claimed to be pentium equvilence (e.g. p200+ was supposed to mean better than a 200mhz pentium iirc). Plugwash 02:22, 29 May 2006 (UTC)
thread_title:  PR 

message: The article says:
"Unfortunately for the competition, Intel wanted to build a more powerful, more workstation-friendly CPU with the Pentium. They built by far their fastest FPU yet; a formidable pipelined unit, the first in an x86 CPU, that could also execute many important FPU instructions very quickly (low latency). Pipelining brought with it the ability to execute more than one instruction per clock cycle, giving it a decisive advantage over chips without a pipelined FPU. The poor FPU performance of the 6x86 can be mostly attributed to major FPU instructions taking at least 4 clocks, putting throughput at one quarter of the Intel P6's peak FPU execution rate. The FPU was not pipelined, and it also was no help that most programmers hand-tailored their code with optimizations designed for the Pentium's FPU. So, while the Pentium was speeding along executing various floating point instructions at a rate of more than one per clock cycle, the 6x86 was executing at a mere fraction of this rate. It was not much faster than a 486 FPU at the same clock speed."
I don't know much about the Pentium FPU, but I know that pipelining does not allow more than one instruction to be executed per clcok cycle -  it allows several instructions to be executed simulataneously, but only one will be completed each cycle. I very much doubt the Pentium FPU could ever complete more than one instruction per clock cycle. Also, Pipelining was not a novel technique at this time - it was a major component of the RISC architectures of the mid-80s and the principle was understood in the 70s (see the MIPS architecture subject for refs).
At the end of the day though, I don't know what all this stuff about the pentium FPU architecture is doing here anyway. Wouldn't it be enough to say that the Pentium FPU was a lot faster, and programmers took advantage of this in a way Cyrix had not predicted? 194.30.171.59 10:59, 22 June 2006 (UTC)
thread_title:  Pipelining 

message: "It has been speculated by experts that 6x86 was designed to perform well specifically on business-oriented benchmarks of the time, most notably Ziff-Davis' Winstone benchmark."
What experts are they talking about? It seems as if a baseless claim was thrown in the article and they attempt to give it credibility by saying that "experts" said it. I had a Cyrix 6x86-PR166+, and it performed nicely. I think a more accurate statement would be that the 6x86 was designed to perform well specifically on business-oriented applications. TwinTurboZ 16:08, 24 March 2007 (UTC)
thread_title:  This part should be removed 

message: "The 6x86 combines aspects of both RISC and CISC. It has a superscalar, superpipelined core, and performs register renaming, speculative execution, out-of-order execution, and data dependency removal.". 
As far as I know the 6x86 is a CISC processor. It incorporates techniques to improve IPC but these techniques are neither typically CISC nor RISC. They can alos be incorporated into other types of instruction sets, VLIW for example. JVLebbink 07:40, 11 October 2007 (UTC)
thread_title:  Named Techniques are not Risc(y) 

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