Talk:XScale

message: Very first paragraph mentions v5TE instruction set architecture but there is no x-ref on Wiki.  Would be nice to elaborate.  --Todd 20:32, 12 July 2006 (UTC)
replies: text: I was under the impression that it was designed as a joint venture.
Furthermore, I also thought that the XScale was quite a re-design, compared to the SA-1110. For example, unmodified StrongArm code runs about as fast on a 400Mhz XScale as the 206MHz SA-1110. (That's what they claim about the Sharp Zaurus SL-5500 vs 5600.) The XScale is, however, designed to be able to run at a much higher clock frequency. They have been hinting at new versions approaching 1GHz, consuming around 1W since 2000, but I haven't seen any hard evidence for this yet. - Popup 15:53, 2004 Feb 4 (UTC)
I thought it was Digitals version of Arms core modified to closely suit their process technology
Though ARM consulted on the design, the actual design work was done solely by Digital/DEC. SA-1 core was a grounds-up design within Digital, while SA-2 core is a grounds-up design within Intel. Dyl 14:24, 1 April 2006 (UTC)
thread_title:  Miscellany 

message: There are some differences in the XScale MMX implementation compared to IA86 MMX worth mentioning, most notably that the destination register need not be one of the source registers, ie:
 
 // XScale:
 mm0 = mm1 + mm2;
 
 // IA86:
 mm0 = mm1;
 mm0 += mm2;
MX44 12:37, 21 July 2006 (UTC)
thread_title:  Wireless MMX 

message: From http://www.intel.com/pressroom/archive/releases/20060627corp.htm it looks like the "sale of XScale business to Marvell" covers only the communications and application processor business (i.e. PXA). There's no mention of the IXP business going the same way. The way this is described in the article (and in the ARM architecture article) would suggest it is.
Clarification needed. Ptoboley 12:57, 21 September 2006 (UTC)
thread_title:  Sale of XScale business to Marvell 

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