Talk:Program counter

message: I have been reading a bit in my course book about computer hardware and found the following information:
8086/8088 processors have a 16 bit data bus and a 20 bit address bus, so two registers are needed to contain an address: a segment register and an offset register. The memory address can be obtained by bit-shifting the segment register by four bits to the left and performing a summation with the offset register.
The memory a program used is seperated into segments. The segment containing the code is called the code segment, and it's segment register is named CS. It's offset register is named IP or instruction pointer.
This information should be added in a page on instruction pointer and a disambiguation page should be made.
--Bernard François 11:39, 6 March 2006 (UTC)
replies: text: No, no, please don't.  We don't need a content fork.  PC and IP are truly two different terms for the same fundamental concept.  If you understand this you should LOL at the joke in the above section.  This is a related discussion so I'm making it a subtopic under the above.  Wbm1058 (talk) 20:25, 21 October 2011 (UTC)
thread_title: instruction pointer disambiguation

message: This is horribly unencyclopaedic in its tone, somewhere in-between OR and a POV diatribe.  I'm tempted to get rid of it, because it's not particularly informative.  Any thoughts?  Oli Filth(talk|contribs) 01:08, 25 April 2012 (UTC)
replies: text: I thought my version was a vast improvement in terms of this exact problem.  In particular, it went from exploring the state-of-mind of the programmer, to merely discussing the implications of the sequential-execution model.  I do not see why you reverted to the previous version to attach .  Spike-from-NH (talk) 01:43, 25 April 2012 (UTC)
replies: text: Oh, that was completely unintentional, I have no idea how that occurred.  Reverted now.  Oli Filth(talk|contribs) 13:17, 25 April 2012 (UTC)

text: Whew!  Thank you for the clarification. Spike-from-NH (talk) 17:39, 25 April 2012 (UTC)
thread_title:  POV section: "All-pervasive nature of the program counter" 

message: , :
A recent edit added the claim that "In some architectures, the PC points to the current instruction plus a processor-dependent constant."; that edit was reverted.
The claim was presumably derived from the "Saving from r15" section of this part of the ARM Developer Suite Assembler Guide, which said:
:In general, avoid saving from r15 if possible.
:If you do save from r15, the value saved is the address of the current instruction, plus an implementation-defined constant. The constant is always the same for a particular processor.
In manuals describing an instruction set, the PC/IP is probably mostly used in a description of the behavior of the idealized processor that all implementations of the instruction set provide.  For example, it would be used in descriptions of instructions, e.g.:
:JMP [EA] - Jump unconditionally
: PC <- [EA]
:JSR [R], [EA] - Jump to Subroutine
: [R] <- PC
: PC <- [EA]
In some instruction sets, including the one whose instructions are described there, when an instruction is executed, the PC/IP points to the instruction following the one being executed, so that 1) the address of that instruction is saved as the return address and 2) when the instruction finishes, the next instruction is fetched from the PC/IP, meaning that the jump instructions cause the next instruction to be fetched from the effective address of the jump instruction.  The current x86 manuals seem to show the IP/EIP/RIP working that way, as, with RIP-relative addressing, "An effective address is formed by adding displacement to the 64-bit RIP of the next instruction.", and in the description of the CALL instruction, one step is "Push(IP);", "Push(EIP);", or "Push(RIP);", pushing the address of the next instruction onto the stack.
For others, such as MIPS32, it points to the instruction being executed, so that, to quote the MIPS32 manual:
:The address of the instruction that occurs during the next instruction time is determined by assigning a value to PC during an instruction time. If no value is assigned to PC during an instruction time by any pseudocode statement, it is automatically incremented by either 2 (in the case of a 16-bit MIPS16e instruction) or 4 before the next instruction time. A taken branch assigns the target address to the PC during the instruction time of the instruction in the branch delay slot.
and, in the description of the Jump and Link instruction, the first step of the sequence of steps is
: GPR[31] <- PC + 8
(+8 = +4+4, with the first +4 skipping over the JAL instruction and the second +4 skipping over the instruction in the delay slot).
The instruction set might make it visible as a general-purpose register; A32 (32-bit ARM), for example makes it visible as r15.  What the ARMv7 A-profile manual says is:
:PC, the program counter
:* When executing an ARM instruction, PC reads as the address of the current instruction plus 8.
:* When executing a Thumb instruction, PC reads as the address of the current instruction plus 4.
:* Writing an address to PC causes a branch to that address.  
So, for 32-bit ARM (the 32-bit instruction set containing ARM instructions), the PC points to the instruction following the next instruction, as instructions are all 4 bytes long.  I'm not sure what the case is for Thumb/Thumb-2, as there are both 16-bit and 32-bit instructions.  The Branch and Link instruction sets the link register (r14) to PC - 4, backing it up to point to the instruction following the BL instruction.
So, at the instruction set architecture level, while an instruction is being executed, the PC/IP might point to the instruction being executed, to the instruction following the instruction being executed, or somewhere else following the instruction being executed.
At the microarchitecture level, there might not be a set of N transistors that make up "the program counter register" or "the instruction pointer register"; each instruction being executed might, for example, have, associated with it, a PC/IP value appropriate to that instruction, following the rules of the instruction set architecture, and the instruction fetch hardware might have its own register holding the PC/IP value, which it copies into the stuff it hands to the execution hardware.
So the page should perhaps distinguish between "PC/IP as a concept in the description of the instruction set architecture" and its implementation in various microarchitectures.  The "Hardware implementation" should discuss only the latter of the two - and not make any claims without reliable sources. That might reduce the contents of that section substantially if the references can't be found, and expand the contents substantially if they can be found. :-)  The rest of the article should probably focus on the instruction set architecture PC/IP, and just indicate that it might, during the execution of an instruction, point to the instruction being executed, the next instruction that would be executed if the instruction doesn't cause a transfer of control (or even if it does cause a transfer of control if there's a branch delay slot), or some arbitrary instruction set architecture-defined or implementation-defined place past the instruction being executed.  — Preceding unsigned comment added by Guy Harris (talk • contribs) 
:Thanks; I did not grasp this from the cited page.  I've restored a version of the new sentence but moved it (and the other sentence with an exception to the rule) out of the Intro and into Notes.  On a further reorganization of the article, I have no opinion.  Spike-from-NH (talk) 13:22, 21 October 2019 (UTC)
replies: text: I agree; most people reading the article will be thinking of PC in the context of an instruction set. Mildsunrise (talk) 11:30, 22 October 2019 (UTC)
thread_title:  PC/IP pointing past the current instruction 

message: The Symbol section mostly described symbols used in expressions evaluated by the assembler at assembly time to refer to the address of the current instruction, i.e. the value the program counter would have when the fetch of the instruction in question begins.  That strikes me as more relevant to assembly language than to this page. One term used for the address of the current instruction is the "location counter"; see, for example, page 3 of the PDP-7 assembler manual, page 3-8 of the PAL III Symbolic Assembler Programming Manual for the PDP-8, page 3-13 of the PDP-11 MACRO-11 Language Reference Manual, page 3-18 of the VAX-11 MACRO Language Reference Manual, and pages 18-19 of the IBM Operating System/360 Assembler Language manual.  It's called the "location assignment counter" for the 1130; see pages 7-8 of the IBM 1130 Assembler Language manual.
The bit about DEC describes, instead, a symbol used to refer to the program counter as an operand fetched (or stored into) by an instruction at run time, for those instruction sets that support this such as the PDP-11 and VAX instruction sets.  DEC generally uses  as the symbol for the address of the instruction; see, for example, page 10 of the PDP-7 assembler manual, page 3-8 of the PAL III manual, page 3-13 of the MACRO-11 manual, and page 3-18 of the VAX MACRO manual.  The use of  is more relevant to assembly language, juast as for other symbols; the use of  in operands may be relevant to this page, with a discussion of those instruction sets where the PC can be used in operand specifiers.
IBM tended to use "*" as the symbol.  See, for example, pages 4-5 of the IBM 7090/7094 Programming Systems FORTRAN II Assembly Program (FAP) manual (where they don't seem to have a phrase such as "location counter", although, according to page 25, the pseudo-operation to set the counter is ), pages 18-19 of the OS/360 assembler manual, and pages 9-10 of the 1130 assembler manual.
As for , that's a convention used by programmers in various IBM assembler languages to indicate to human readers of the code a value that would be set at run time; see, for example, page 5 of the IBM FAP manual.  The two s in the expression refer to the "location counter" value; it may just be that it's a visually-notable pre-defined symbol such that subtracting it from itself 1) produces a result of 0 to use as a placeholder and 2) looks visually distinct - it may not be significant that what you're subtracting from itself is the location counter.  That's a convention possibly worthy of note, but more relevant either to the assembly language page or to the pages about the computers where that convention was used. Guy Harris (talk) 23:30, 8 September 2023 (UTC)
thread_title:  I removed the Symbol section as not being very relevant here