Talk:Intel Core 2

message: In the past, I have gone through and edited the unit of measure used to quantify the speed of each CPU's front side bus from "MT/s" (megatransfers per second) to "MHz."  Usually my edits would be reverted within the hour, back to "MT/s."  I haven't bothered to change anything here this time, but I have to ask:  Why are we using that unit of measure, and moreover, why are we using it incorrectly?
The Wikipedia page for Megatransfer states, quote: "The units usually refer to the "effective" number of transfers, or transfers perceived from "outside" of a system or component, as opposed to the internal speed or rate of the clock of the system. One example is a computer bus running at double data rate where data is transferred on both the rising and falling edge of the clock signal. If its internal clock runs at 100 MHz, then the effective rate is 200 MT/s, because there are 100 million rising edges per second and 100 million falling edges per second of a clock signal running at 100 MHz."
Well, the Core 2 line of processors uses an AGTL+ "quad-pumped" Front side bus, which performs four transfers per clock cycle.  This would mean that a Core 2 Duo T7400 (2.16 GHz core clockspeed, 667 MHz front side bus clockspeed) would NOT (as this article indicates) possess a front side bus capable of 667 MT/s, but rather would possess a front side bus capable of 2668 MT/s (4 * 667).
Apart from being wholly incorrect, the use of MT/s for measuring the speed of the front side bus of the Core 2 processors is simply wrong.  Intel's own materials clearly show processor specifications listed in MHz, not MT/s.  Why do we insist on MT/s?
A Pickle (talk) 04:26, 29 June 2009 (UTC)
replies: text: First a T7200 667 mhz fsb IS a quadpumped 166mhz FSB, The northbridge and the cpu are at 667mhz but transfer in between is at 166mhz.--Transisto (talk) 06:22, 29 June 2009 (UTC)

text: The actual clock driving the bus in your T7400 example is 166 MHz.  This is then quad-pumped to 667 MT/s (or as quoted by Intel, 667 MHz).  Intel (and AMD) chose to continue describing bus speeds in MHz because it was familiar to customers, even though with the advent of double-pumping it was no longer precisely accurate (and, as your example shows, can be very confusing even to people familiar with the topic).  Wikipedia articles on this topic use the unambiguous but less familiar "MT/s" units.  Whatever the relative merits of either approach, the way the units are used in this and other Wikipedia articles is technically correct. — Aluvus t/c 00:31, 1 July 2009 (UTC)
thread_title:  Front side bus quantities:  MHz or MT/s? 

message: I added the information about the L2 and M0 stepping Merom-2M die and the Core 2 Duo ULV CPUs to the "Merom" section. I also updated the main summary to include the lowest speed of the ULV CPU (1.06 GHz, U7500) as well as adding the micro-FCBGA interface for the C2D LV, ULV, and some T5000 series CPUs and updated the core names to include the 2 MB dies' core names. Pgk1 03:29, 25 September 2007 (UTC)
thread_title:  Updated summary for Merom-2M/Allendale die and the Core 2 Duo ULV CPUs 

message: According to this (http://www.tomshardware.com/2007/10/29/intel_penryn_4ghz_with_air_cooling/page4.html) SSE4 is supported in VirtualDub already. Update time for "SSE4 is not yet supported in any app"! Just a little reminder! 76.227.11.127 16:00, 12 November 2007 (UTC)
thread_title:  SSE4 

message: I was hoping to find the answer in this article, but no luck.  Seems to me that the processors would be constantly "butting heads" trying to access memory at the same time (thus forcing one of the processors to wait & stop execution).  How does Intel get around this problem?  -  Theaveng (talk) 20:17, 21 November 2007 (UTC)
replies: text: See SMP "Access to RAM is serialized" or "Non-Uniform_Memory_Access". The "butting heads" problem has to be handled in software (typically the OS) but it is only really a problem for writing. Accessing the same memory does not really mean, they are accessing the same memory ranges at the same time but rather they share the same memory in contrast to having dedicated memory each. The advantage is that you do not have to transfer between the processors which would require more bandwidth and be slower than synchronisation via semaphores or similar mechanisms. --217.87.87.117 (talk) 19:50, 22 November 2007 (UTC)
thread_title:  How can 2 (or 4) processors share the same memory? 

message: Where are the core 2 xeon clovertown cpu specs?  —Preceding unsigned comment added by Spydercanopus (talk • contribs) 02:31, 23 November 2007 (UTC)
replies: text: That is because Clovertown is a Xeon and is therefore discussed in the Intel Xeon article instead.Coldpower27 (talk) 20:14, 24 November 2007 (UTC)
thread_title:  Clovertown missing 

message: With the advance of the 45nm fabrication process, and the resultant decrease in heat emission by the CPU's transistors, can 8-core 45nm Core 2 CPUs become a reality? If Intel decides to release some Core 2 Octo CPUs, will they be compatible with the current chipsets (Intel Bearlake chipsets)? Will they require special voltage regulators that may not be present on current LGA775 motherboards?
Or will 8-core CPUs be realized only on the post Core 2 architecture (Nehalem, if I'm correct here)?  —Preceding unsigned comment added by Hellcat fighter (talk • contribs) 16:14, 8 December 2007 (UTC)
thread_title:  Core 2 Octo 

message: The article states that "The currently available Core 2 Duo E4300 only uses an Allendale core, released on January 21, 2007."
Yet, I appear to have a piece of hardware on my hands that defies this statement.  —Preceding unsigned comment added by 67.55.8.197 (talk) 22:21, 8 January 2008 (UTC)
replies: text: All L2 Stepping cores are indeed Allendale SKU's, CPU-Z sometimes doesn't read accurately. L2 or M0 Steppings are Allendale while B2, G0 steppings are Conroe. That is more accurate and CPU-Z won't screw that up.Coldpower27 (talk) 16:18, 19 January 2008 (UTC)
thread_title:  Possible inaccuracy about Conroe and Allendale cores 

message: What is the processor announced by Intel at MacWorld today that was 4MB, 1.6 or 1.8GHz Core 2 and shrunk 60%? Nja247 (talk • contribs) 21:43, 15 January 2008 (UTC)
replies: text: A rather special Merom. — Aluvus t/c 00:46, 16 January 2008 (UTC)

text: It is a Merom core with a TDP of 20W so between Low voltage and Standard voltage, which uses the pacakaging technology designed for the SFF Montevina platform due to come out in the middle of this year. Originally it was to be used only with Penryn's, but for Apple Intel designed something special.  —Preceding unsigned comment added by Coldpower27 (talk • contribs) 16:20, 19 January 2008 (UTC)
thread_title: MacWorld

message: There is a lot of great tech jargon to talk shop with in this article, but what is the improvement in speed for each chip in real terms?  A chart and a link at the end of it to one or more test comparison sites would be appreciated by many readers. (And, if not for this article, can anyone direct me to a site that gives some kind of statistical comparison?)
 
I am going to buy a new high-end laptop for graphic design. The current processor options are: T9500 (2.6 GHz), T9300 (2.5 GHz) T8300 (2.4 GHz), T8100 (2.1 GHz), X7900 (2.8 GHz), T7800 (2.6 GHz), T7700 (2.4 GHz), or a T7500 (2.2 GHz). - - (Today is 10 fevr. 2008) - - These chip options come on the Sony AR line, LG W1 Line, and Dell Precision line, supposedly their best laptops. - - Is an X7900 faster than a T9500?
This article needs someway for me and other readers to evaluate the bang-for-buck factor in these chips. What is the real incremental speed improvement in each one anyway?  Charvex (talk) 08:28, 10 February 2008 (UTC)
thread_title:  Real World Comparisons 

message: The article claims that:  Merom (מרום) is the Hebrew word for a higher plane of existence or a level of heaven, BaMerom (במרום) means "in the heavens". The name was chosen by the Intel team in Haifa, Israel, who designed this processor.
Are you positive?  Any reference on that?  Because there is also a biblical lake Merom which was situtated in what is today Hula Valley, and my gumption tells me that it's thence the processor code name is derived from.  Thanks, Maikel (talk) 17:08, 12 March 2008 (UTC)
thread_title: Merom etymology

message: Yorkfield has been released, At least in the US, and in OEM form.
http://www.tankguys.com/product_info.php?products_id=1817
Not sure about elsewhere.
Thus, this article should be updated soon to reflect this.
67.224.19.160 (talk) 20:29, 26 March 2008 (UTC)
replies: text: I've updated it with the most recent information so far. --GuitarFreak (talk) 13:59, 9 April 2008 (UTC)
thread_title:  Yorkfield released 

message: Note. For interested authors, debate and a vote is ongoing on Talk:MOSNUM regarding a proposal that would deprecate the use of computer terms like “kibibyte” (symbol “KiB”), “mebibyte” (symbol “MiB”), and kibibit (symbol “Kib”). It would no longer be permissible to use terminology like a “a SODIMM card with a capacity of two gibibytes (2 GiB) first became available…” and instead, the terminology currently used by manufacturers of computer equipment and general-circulation computer magazines (“two gigabytes, or 2 GB”) would be used. Voting on the proposal is ongoing here.  Greg L (my talk) 21:16, 27 March 2008 (UTC)
thread_title: MiB and KiB v.s. MB and KB

message: I'm just wondering why this article isn't named Core 2 Duo, since this is the name Intel uses on their product website and general marketing.
82.74.182.58 (talk) 19:09, 15 June 2008 (UTC)
replies: text: Because it also covers the Core 2 Solo, Core 2 Quad, and Core 2 Extreme. — Aluvus t/c 19:33, 15 June 2008 (UTC)
thread_title:  Core 2 Duo 

message: Analagous to the Pentium D branded CPUs, the Kentsfields comprise two separate silicon dies (each equivalent to a single Core 2 duo) on one MCM[27]. This results in lower costs but lesser share of the bandwidth from each of the CPUs to the northbridge than if the dies were each to sit in separate sockets as is the case for example with the AMD Quad FX platform[28].
This seems wrong... According to the article quoted, the bandwidth share is 50% either way. With AMD example, this is 1 HyperTransport channel per CPU where the total for both CPUs is 2 HyperTransport channels, whereas for intel it is 1/2 of FSB per core, with a total for both is 1 FSB. So how exactly is this an advantage to justify the "but"?--194.249.198.32 (talk) 14:05, 24 June 2008 (UTC)
replies: text: Some Intel chipsets intended for multiprocessor Xeon setups now have a dual front side bus, which is perhaps what this passage is trying to get across.  Multicore desktop chips do not get this speed boost.  It's difficult to figure out what exactly this text is supposed to be saying.  — Aluvus t/c 01:32, 25 June 2008 (UTC)
thread_title:  Bandwidth share 

message: I found this section awfully confusing, as it indicates that a single-channel DDR-266 will be matched to a 1066 MT/s FSB. That's ludicrous -- that memory will only deliver 50% of the bandwidth that the FSB needs. Similarly it indicates that a dual-channel DDR3-1066 is matched to 533 MT/s FSB; that's a serious overkill, as the memory will be used at 25% capacity. A better approach is to separate the table by FSB bandwidth and memory type:
533 MT/s FSB --> dual-channel DDR-266 or single-channel DDR2-533
667 MT/s FSB --> dual-channel DDR-333 or single-channel DDR2-667
800 MT/s FSB --> dual-channel DDR-400 or single-channel DDR2-800
1066 MT/s FSB --> dual-channel DDR2-533 or single-channel DDR2-1066 or single-channel DDR3-1066
1333 MT/s FSB --> dual-channel DDR2-667 or single-channel DDR3-1333
1600 MT/s FSB --> dual-channel DDR2-800 or dual-channel DDR3-800 or single-channel DDR3-1600
Keep in mind, just because the FSB clock matches the memory clock, it doesn't mean that they are "matched". You need to take into account the bandwidth. It doesn't help having the poor sod thinking that he needs anything more than very inexpensive dual-channel DDR2-533 for his E6300. Just my 2 cents -- thanks.
12:35, 31 August 2008 (UTC)
replies: text: One thing that I have come across recently (to my cost) is that a lot of motherboards seemingly cannot deal with DDR2-533MHz memory any more. I have an MSI G31M3-F (Intel G31 chipset) bought just this week, to run a Core 2 E7300, and an Asus P5K-E (Intel P35 chipset) bought at the beginning of 2008 to run a Core 2 Quad Q6600 and neither will accept DDR2-533MHz (the latter does gamely try to force the memory to run faster, which worked in one example). Both of these chips should want 533MHz memory in order to be matched up properly, but both refuse to, forcing me to run less well-matched DDR2-667MHz. Did Intel find a magic way around this matching issue, or is this an oversight on their part? --GetThePapersGetThePapers (talk) 23:10, 9 November 2008 (UTC)
thread_title:  Matched Memory section 

message: I have a laptop with a Celeron 530 M. According to the article on the Celeron series that should be the Merom core, yet CPU-Z says it's a Conroe L.  —Preceding unsigned comment added by Bizzybody (talk • contribs) 07:54, 4 December 2008 (UTC)
thread_title: Conroe L or Merom?

message: I believe the Q8000 series was a reduced version of the Yorkfield (Q9000). According to this article it was made to compete on price with the Phenom X3.  Ham Pastrami (talk) 10:15, 2 February 2009 (UTC)
thread_title:  Q8000 not in article 

message: or does only the xeon line support that? Plugwash (talk) 21:21, 9 February 2009 (UTC)
thread_title:  does the core 2 line support multi socket boards 

message: core 2 deo 2.80 processor working and betterments next modal core 2 deo...... kbalakr@gmail.com  —Preceding unsigned comment added by 122.252.252.124 (talk) 12:39, 10 March 2009 (UTC)
thread_title:  core 2 duo prossesor perfomence 

message: Remember. I and my brother own the two Wolfdales (E8400).  — Preceding unsigned comment added by 23.117.16.45 (talk) 17:39, 19 July 2015 (UTC)
thread_title:  Duo 

message: It's been around and all over that this CPU isn't core.  I don't know why?  There are A LOT of core CPUs.  — Preceding unsigned comment added by 23.117.16.45 (talk) 02:05, 8 September 2015 (UTC)
thread_title:  Conversation 

message: I find there is no such thing.  I own the Core 2 Duo E8400.  It's just a basic Core! like i3 i5 i7 solo duo quad EP (Extreme Processor) etc...  Look up my emblem and you can see.  Then look up the other emblems and see what you think about the Corei3 now.  — Preceding unsigned comment added by 2602:301:7751:160:1D1C:5C29:ED0:86C0 (talk) 02:38, 5 September 2016 (UTC)
thread_title:  Stop the Press 

message: I think this logo should feature in this wiki page, but don't know how to include it here.
New Logo - http://orig15.deviantart.net/8994/f/2014/045/5/9/_original_logo__v_3__intel_inside_core_2_vpro_by_18cjoj-d72e916.png 
Old Logo - https://i349.photobucket.com/albums/q377/StockersPics/Core2VProInside.jpg -- Alexey Topol (talk) 02:24, 1 January 2017 (UTC)
thread_title:  "Core 2 vpro"-Logo 

message: I could ask you if you had any doubt whereas the most modern of living style could contain enough information that comes with a "SEQUAL." This is what you are referring to correct? Labels have that says "CORPORATE." There is this one company in Salt Lake City, Utah, but it is closed now and run down. If for any particular reason the implant here serves as a listening device, maybe such handheld devices might work out for you. Face to face calling exists these days and not a single person seemed to have noticed it's emergence. For that matter I would hope the container for the laughing that ensues about how we came across combing a video card and a CPU came about. I would hope you had a better chance, at that may you, while you scurry about looking for these 'computers.' Did you ever notice that CPU-Z shells out an aquiline equation for not just only the multi, but also Sigel `core` usage that derives a similar outcome for less expensive companies, such as Predon Corporation that does it's security net on bot Core & Dual Core.  — Preceding unsigned comment added by 65.186.58.156 (talk) 07:51, 6 August 2020 (UTC)
thread_title:  Fatal Sales 

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thread_title:  External links modified