Talk:Duron

message: I removed several of the recently added Infos .
#The last Duron is called Applebred and not Appalbred (I have two, one A- and one B-model, every CPU-ID program tells me Applebred).
#Appaloosa was cancelled
#Both Slot-A and Socket-A Athlons/Durons had Exclusive L2-Cache, Core was not very different
#P3-Celeron was available with 100 MHz FSB, too. I'm not sure with inclusive L2-Cache though
#Lots of stuff about Caches do not belong to this article, use CPU cache for this kind of stuff
--Denniss 23:47, 9 January 2006 (UTC)
replies: text: Your should check your "facts", the Appaloosa was planned but cancelled, the Applebred is just a variant of the T-Bred with partially disabled L2-Cache and nothing more. It seems sandpile.org has some problem with inclusive and exclusive L2-Cache, see P4 with exclusive L2-Cache but inclusive L3 ?!? A quote from one "Google source": Wir Moderatoren haben vorgestern mit Jan Gütter gesprochen, er hat die Bezeichnung "Applebred" bestätigt, das reicht mir und ist für mich eine offizielle Aussage (short translation: Moderators have asked Jan Gütter (of AMD) and he confirmed Applebred, that's enough for me and is as good s an official statement) from here --Denniss 01:41, 10 January 2006 (UTC)

text: Applebred are both available as T-Bred A and T-Bred B, I have a 1600er A and a 1400er B (as Athlon XP now). I have not much Info about Appaloosa but it's possible it was planned as a CPU with physically only 64 KB L2 available analog to Spitfire and Morgan. --Denniss 05:44, 10 January 2006 (UTC)
thread_title:  Changed made by [[User:Swaaye]] 

message: Hi,
I think there is a small "bug" in the article. I have access to a Duron which does not have SSE, but the article lists them all with SSE. Here is the /proc/cpuinfo output from Linux, if it helps:
 20:52 athlon:~ # cat /proc/cpuinfo 
 processor       : 0
 vendor_id       : AuthenticAMD
 cpu family      : 6
 model           : 4
 model name      : AMD Athlon(tm) processor
 stepping        : 2
 cpu MHz         : 900.037
 cache size      : 256 KB
 fdiv_bug        : no
 hlt_bug         : no
 f00f_bug        : no
 coma_bug        : no
 fpu             : yes
 fpu_exception   : yes
 cpuid level     : 1
 wp              : yes
 flags           : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat
                   pse36 mmx fxsr syscall mmxext 3dnowext 3dnow
 bogomips        : 1802.69
(The SSE flag would normally appear after "fxsr" on an SSE-capable CPU.)
:Spitfire has only a partial SSE implementation. It has the integer portion of SSE, but AMD calls it Extended 3DNow (which has other stuff too). So they can't say it's fully SSE compliant. --Swaaye 20:16, 4 June 2006 (UTC)
thread_title:  No SSE 

message: Applebreds were released (according to this page, I'm assuming it's correct) on August 21 2003, which translates to mid week 34 2003. The first die-locked chips (not necessarily Applebreds) began appearing in week 34, though it was rare to get a die-locked week 34-38 CPU. Week 39 was when die-locking became nearly universal, giving a period of about 4 weeks. The main thing is that the week number on the chips is not when the chip is bought - typical channel times back then were in the order of 2-4 weeks. On the other hand, the August 21 date probably isn't a "widely available for sale" date, which will cut a week or two off the other end. Hence where I get the ~4 week number. I'll see if I can dig up something more accurate, but given the rate of change in the tech world it may be hard to get. Until then, the ~4 week number (IMO) is a good start.
150.203.19.142 06:50, 8 February 2007 (UTC)
thread_title:  Die-locking 

message: I recently took apart an old computer of mine to find that it had an AMD Duron processor in it. The date on the processor said 1999. The motherboard supported cpu clock speeds of 100mhz to 133mhz, so it's safe to assume the processor was limited to run within this range. The article claims the Duron processor was created in 2000, but I have one that is marked with the date 1999.
24.115.3.224 19:22, 1 March 2007 (UTC)
replies: text: Look a the image of the Duron we have here, it is also listed with copyright 1999. But this date usually means the design is of 1999 but not the CPU itself. The time stamp looks like it specifies week 32, 2000, as date of creation for this core. Also the article does not claim it was created in 2000 but it was officially published at this date.--Denniss 22:29, 1 March 2007 (UTC)
thread_title:  Possible inaccuracies? 

message: Article: "The Duron was discontinued in 2004..."
Infobox: "Produced: 	From mid 2000 to 2006"
Which is right? 86.132.138.84 19:39, 13 November 2007 (UTC)
replies: text: probably development was discont. in 2004 but it remained available until 2006  —Preceding unsigned comment added by 65.31.222.144 (talk) 22:10, 19 January 2009 (UTC)
thread_title:  Inconsistency in dates? 

message: When the Duron was first introduced, both the Duron and the Athlon ran fixed multipliers based on a 100MHz FSB (200DDR FSB) and were designed to do so, if only because there were no motherboards for them that supported a 133MHz FSB. For example, the VIA KT-133 chipset motherboards ran the CPU (Athlon and Duron) at 100MHz FSB (200DDR FSB) and could feed the SDR memory bus at its slower, asynchronous 133MHz (hence the KT133 designation) at a very high throughput for the time. AMD's own Socket A motherboard chipset at this time didn't even support async 133MHz SDR Memory let alone a 133MHz FSB.
Later motherboards with chipsets such as the VIA KT-133A, were introduced to support the "new" Athlons running at 1GHz+ with a 133MHz FSB. However, even then, there were "Thunderbird" Athlons sold at 1GHz - 1.4GHz produced for the older boards that ran at 100MHz FSB.
It wasn't really until the Athlon XP and the Morgan based Durons, that AMD would make a clear marketed deliniation between the FSB speed of the processors.  — Preceding unsigned comment added by 24.10.146.29 (talk) 05:02, 6 March 2013 (UTC)
thread_title:  Initial Duron vs First Socket A Athlon 

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thread_title:  External links modified