Talk:Intel Core (microarchitecture)

message: This article should be put into Conroe to conform to the standard of articles on microprocessor architectures in Wikipedia.  Intel processor microarchitectures are referred to by their code names in Wikipedia, not by their generation number. For example, Intel P7 directs the viewer to Netburst, and Intel P5 does not exist, the P5 architecture is described under Pentium.  Intel P6 is also very similar in that only links to the names of processors of that generation are listed with architectual improvements described at each processor instead of the features of the artcitecture described directly at Intel P6.
This article seems slightly more detailed than Conroe, so the improvements made to this article should be integrated into Conroe.  This is the reason I suggested the article for merging instead of deletion.
:I respectfully disagree. Conroe is not the name of the eight generation architecture, only the code name of the first desktop chip to use the new architecture. Unfortunately, Conroe does not represent all the chips of the new architecture, and a broader article to represent them all is needed. There will be other chips to succeed Merom, Conroe, and Woodcrest that will use the new architecture. Conroe actually reminds me of Willamette, the first ever NetBurst chip in 2000, and that chip did not even merit its own article. On the other hand, Intel P8 represents the whole architecture, at least until a finalized brand name is released. But until then, the architecture is Intel P8. The two can not be merged. Would you like to just keep the two articles distinct? --Noypi380 05:55, 25 August 2005 (UTC)
thread_title: "Intel P8" should redirect to [[Conroe]]

message: It was discussed instead in Talk:Conroe that Conroe should redirect to Intel P8. Any objections? --Noypi380 14:32, 27 August 2005 (UTC)
thread_title: [[Conroe]] redirected to P8 instead

message: Intel officially calls it the Next Generation Microarchitecture. Dan100 (Talk) 10:49, 13 December 2005 (UTC)
replies: text: Thing is, at this point, there's virtually no information about Conroe that's not covered by NGMA. There simply aren't enough details on Conroe, at this moment, to warrant a separate article. I propose that we re-create the Conroe article only when both a final name and details on the available models are released. Jgp 03:56, 17 December 2005 (UTC)

text: I agree with Jgp. All information about Conroe are covered by NGMA. When more information will be available, we could create some new articles about each processor (Merom, Conroe, Woodcrest) whose links will be available in the NGMA article. Just like NetBurst article which has the links of all NetBurst processors. kostas213 19:13, 26 January 2006 (UTC)
thread_title:  No such thing as "P8" 

message: I don't think that Merom's FSB is 1066 MHz, but it is 667 MHz, just like the FSB of Core Duo (Yonah) processor. It is known that Merom will make use of the same chipset (945) as Core Duo. So the FSB will be 667 MHz, as I think. It is also should be mentioned that Merom - Conroe - Woodcrest are 4-issue cores.
:You're right. I have, however, heard that a second wave of Meroms will launch in early 2007, supporting an 800 MHz FSB. I've corrected the FSB data, and I've also switched MHz over to MT/s, due to conflicts on other pages regarding what constitutes FSB speed. Jgp 22:50, 25 January 2006 (UTC)
thread_title:  FSB for Merom is 1066 MHz? 

message: I have added that the new cores will be 4-issue. I think that this fact is one of the most important characteristics of the new architecture. I have also mentioned that previous architectures (P6, P6-Banias, NetBurst) made use of 3-issue cores. --kostas213 19:02, 26 January 2006 (UTC)
thread_title:  NGMA cores are 4-issue wide. 

message: Can someone explain to me why much of this article does not violate WP:NOT#Wikipedia is not a crystal ball?  It says "Wikipedia is not a collection of unverifiable speculation. All articles about anticipated events must be verifiable ...".  I mean, the processor line is interesting, of course, but why not wait until it actually comes out instead of speculating? -- Gnetwerker 07:40, 20 March 2006 (UTC)
thread_title: Wikipedia is not a Crystal Ball

message: I am aware of the Mac Pros containing quad-core 3GHz processors, but aren't they just overclocked Clovertowns? --Masud 20:44, 4 April 2007 (UTC)
replies: text: I have found the answer: according to Intel's Bill Kircos these are really 3GHz. --Masud 11:47, 6 April 2007 (UTC)
thread_title:  Are there genuine 3GHz Clovertown parts? 

message: Aren't the cloverotwn's and kentsfield quad core yet in the server section in the table they are all listed as having 2 cores. Could someone clear this up?   203.214.6.247 08:54, 22 April 2007 (UTC)
replies: text: Oops, you're quite right. When I did the overhaul and created the tables, I forgot to do that. I've done it now, thanks for the reminder. --Masud 15:32, 22 April 2007 (UTC)
thread_title:  Quad Core? 

message: Did intel change to the Allendale core on the Xeon 3040s/3050s recently?  Since release they've been Conroes with half of their L2 cache disabled, basically e6300 and e6400 chips.  The article states that they are Allendale core, I did not change it because quite frankly I don't know. The hardcore icon the sandman 22:11, 25 May 2007 (UTC)
thread_title:  Xeon 3040/3050 allendale? 

message: Since "Microarchitecture" isn't part of the official name, why rename the article to Intel Core microarchitecture instead of Intel Core (microarchitecture). The latter is more conventional. jgp TC 00:25, 13 September 2006 (UTC)
replies: text: Sounds reasonable.  I was just addressing WP:NC's capitalization guideline but the expert editors here can ponder that avenue as well.  I'd consider whether people ever refer to the microarchitecture as simply "Intel Core".  It appears that term would always refer to something else but I could be wrong.  —Wknight94 (talk) 00:51, 13 September 2006 (UTC)
thread_title: Page move

message: To bring this article in line with Nehalem (CPU architecture) and Gesher (CPU architecture), should this article be renamed to Intel Core (CPU architecture)? --Masud 21:38, 22 April 2007 (UTC)
replies: text: I'm not sure that would be consistent because NetBurst has nothing in brackets and neither does Intel P6 and we can't get rid of the microarchitecture part either because that would cause confusion with Intel Core.--Sat84 11:53, 23 April 2007 (UTC)
replies: text: Hmmm... but don't we normally have things in brackets when we distinguish between two things that are named the same thing? For example Fight Club (film) and Fight Club (video game)? In this case, we have the processor and the architecture, both called the same thing: Intel Core and so we need the distinguishing. Similarly, there will be a processor called Nehalem but the term is also used to describe the architecture. --Masud 12:46, 23 April 2007 (UTC)
replies: text:  Seems reasonable but then we would have to change Intel Core to Intel Core (CPU) to be consistent or would we leave that alone?--Sat84 13:12, 24 April 2007 (UTC)
replies: text:  I should think the rename of that article is in order too. --Masud 15:54, 24 April 2007 (UTC)

text:  And irritatingly enough, the Intel Core (CPU) isn't even of the Intel Core (CPU architecture)! --Masud 16:00, 24 April 2007 (UTC)

text:  Changing it would make sense & I'd support it. Cooldude7273 01:01, 25 April 2007 (UTC)
thread_title:  Rename article? 

message: In case you didn't know, Intel has their ARK (Automated Relational Knowledgebase) in beta. It lists all of their processors and all their details. See http://arstechnica.com/news.ars/post/20071107-intels-new-ark-is-lifeboat-for-journalists-chip-junkies.html for more details.
Masud 06:16, 9 November 2007 (UTC)
replies: text: Sweet!  That sounds very interesting.  -- Imperator3733 18:49, 9 November 2007 (UTC)
thread_title:  Intel ARK 

message: I've started a discussion on the processor roadmap graphics over at Talk:Nehalem (microarchitecture)#Processor roadmaps.  Please take a look and make a comment if you have any thoughts.  Thank you.  -- Imperator3733 (talk) 15:06, 11 June 2008 (UTC)
thread_title:  Processor roadmaps 

message: The processor table seems useful, but what I'd rather like to see is a table that shows the relation between all the steppings and how they are used.
List of 65nm Intel Core steppings:
        	        	      	     	        	         	Mobile (Merom)	Mobile (Merom)	Mobile (Merom)   	Desktop (Conroe)	Desktop (Conroe)	Desktop (Conroe) 	Desktop (Conroe)	Desktop (Kentsfield)	Desktop (Kentsfield)	Server (Woodcrest, Tigerton, Clovertown)
Stepping	Released	Area  	CPUID	L2 Cache	Max Clock	Celeron       	Pentium       	Core 2           	Celeron         	Pentium         	Core 2           	Xeon            	Core 2              	Xeon                	Xeon
B2      	Jul 2006	143mm²	06F6 	4MB     	2.93GHz  	M5xx          	              	T5000 T7000 L7000	                	                	E6000 X6000      	3000            	                    	                    	5100
B3      	Nov 2006	143mm²	06F7 	4MB     	3.00GHz  	              	              	                 	                	                	                 	                	Q6000 QX6000        	3200                	5300
L2      	Jan 2007	111mm²	06F2 	2MB     	2.13GHz  	              	              	T5000 U7000      	                	E2000           	E4000 E6000      	3000            	                    	                    	
E1      	May 2007	143mm²	06FA 	4MB     	2.80GHz  	M5xx          	              	T7000 L7000 X7000	                	                	                 	                	                    	                    	
G0      	Apr 2007	143mm²	06FB 	4MB     	3.00GHz  	              	              	T7000 L7000 X7000	                	                	E4000 E6000 Q6000	3000            	Q6000 QX6000        	3200                	5100 5300 7200 7300
M0      	Jul 2007	111mm²	06FD 	2MB     	2.40GHz  	5xx T1000     	T2000         	T5000 T7000 U7000	E1000           	E2000           	E4000            	                	                    	                    	
A1      	Jun 2007	81mm² 	10661	1MB     	2.20GHz  	M5xx          	              	U2000            	220 4x0         	                	                 	                	                    	                    	
List of 45nm Intel Core steppings:
        	        	     	     	        	         	Mobile (Penryn)	Mobile (Penryn)                	Desktop (Wolfdale)	Desktop (Wolfdale)	Desktop (Wolfdale)	Desktop (Yorkfield)      	Desktop (Yorkfield)	Server (Harpertown)	Server (Dunnington)
Stepping	Released	Area 	CPUID	L2 Cache	Max Clock	Celeron        	Core 2                         	Pentium           	Core 2            	Xeon              	Core 2                   	Xeon               	Xeon               	Xeon
C0      	Nov2007 	107mm	10676	6MB     	3.00GHz  	               	T9000 P9000 SP9000 SL9000 X9000	                  	E8000             	3100              	QX9000                   	                   	5200 5400          	
M0      	Mar2008 	82mm 	10676	3MB     	2.40GHz  	7xx            	SU3000 P7000 P8000 T8000 SU9000	E5000             	E7000             	                  	                         	                   	                   	
C1      	Mar2008 	107mm	10677	6MB     	3.20GHz  	               	                               	                  	                  	                  	Q9000 QX9000             	3300               	                   	
M1      	Mar2008 	82mm 	10677	3MB     	2.50GHz  	               	                               	                  	                  	                  	Q8000 Q9000              	3300               	                   	
E0      	Aug2008 	107mm	1067A	6MB     	3.33GHz  	               	T9000 P9000 Q9000 QX9000       	                  	E8000             	3100              	Q9000 Q9000S QX9000      	3300               	5200 5400          	
R0      	Aug2008 	82mm 	1067A	3MB     	2.93GHz  	7xx            	T6000 P8000 SU9000             	E5000             	E7000             	                  	Q8000 Q8000S Q9000 Q9000S	3300               	                   	
A1      	Sep2008 	??   	106D1	3MB     	2.67GHz  	               	                               	                  	                  	                  	                         	                   	                   	7400
:I think that looks pretty cool. Part of the issue though is explaining what this means to the average reader of the article. While most readers would be familiar with processor model names, and things like no. of cores etc., we might need an explanatory paragraph preceding these tables.
:I don't think it clutters the article, as I find the information thus presented to be quite interesting. However, others may disagree. Any further opinions?
:--Masudr (talk) 15:27, 28 January 2009 (UTC)
thread_title:  List of steppings? 

message: The article says: "Core's execution unit is 4 issues wide, compared to the 3-issue cores of P6, P-M (Banias, Dothan, and Yonah), and NetBurst microarchitectures."
This sentence does not make any sense. There is no "execution unit". There are multiple execution units, a combination of ALUs, AGUs and FPUs (and perhaps some special purpose units on the side). These execution units are fed with instructions dispatched from something such as a reserve station. The "four-issue" refers to the number of micro-ops (or whatever they are called these days) that are sent to the reserve station. The reserve station itself can dispatch more instructions to the execution units than the number of instructions sent to it.
The sentence should say something along the lines of: The Core microarchitecture is a four-way superscalar design, compared to the three-way superscalar P6.
Before someone rushes to update the article, my comments are based on the P6 microarchitecture. The Core microarchitecture may be completely different, I don't know, but the sentence needs to be fixed. Rilak (talk) 12:09, 13 March 2009 (UTC)
thread_title:  Superscalar 

message: The intro does mention Pentium so I am assuming the instruction set is x86 based, but is it so? This should be mentioned/explained in the intro (unlike most other technical details in this article, this is important for the "regular" users trying to find proper compiler options when transfering codes between different machines!) Thanks.  —Preceding unsigned comment added by 128.97.82.220 (talk) 02:03, 3 December 2009 (UTC)
thread_title:  Is it x86, after all? 

message: Some mention of what these things can go into would be extremely helpful!  For example - can I pull out my Socket 604 chip, and substitute in any other socket 604; and if not - is there some way to figure out from what I'm currently using, what other ones will work?
203.45.103.88 (talk) 05:23, 28 March 2010 (UTC)
replies: text: This issue is normally addressed in the articles on individual products and sockets.  It can be a surprisingly complex issue, and cuts across microarchitectures anyway (Netburst and Core products are both available on LGA 775, for example).  — Aluvus t/c 20:27, 28 March 2010 (UTC)
thread_title:  Interoperability 

message: List of Intel Core 2 microprocessors says that the Core 2 Quad Q9550S has a 2×6MB L2 cache, while this page says it's a (implied single) 12MB L2.  That's a significant difference -- the pair of cores that share an LS will communicate faster than the ones using separate L2 caches. The processor table suggested above has less duplication of information and thus reduces the chances of inconsistency.  Guy Macon  20:32, 21 April 2010 (UTC)
thread_title:  Inconsistency between Wikipedia pages 

message: According to http://en.wikipedia.org/wiki/Sandy_Bridge were Sandy Bridge mainstream
processors launched earlier this year, so 'Sandy Bridge' in the technology
roadmap figure (IntelProcessorRoadmap.svg) should be black, not blue
(as it is not a future technology any more).  — Preceding unsigned comment added by Andre.holzner (talk • contribs) 11:46, 21 February 2011 (UTC)
thread_title:  IntelProcessorRoadmap.svg needs small update 

message: This link should be added as a reference/external link and the information can be used to update and refresh the data in the article:
Intel Processor Identification with CPUID  — Preceding unsigned comment added by Husmousa (talk • contribs) 21:45, 4 December 2011 (UTC)
thread_title:  A comprehensive authoritative summary of recent Intel microarchitecture 

message: The last sentence and source in the intro (ie. "The Core microarchitecture was designed by Israel's Intel Israel (IDC) team...") are not coherent. The article states that Intel Israel were responsible for the Core 2 Duo, but nothing about earlier iterations etc.
It should be changed to reflect the source, or better sources found for the claim.60.242.39.220 (talk) 13:57, 15 April 2012 (UTC)
thread_title: Israel's role in Core design

message: Two places on the page describe Dunnington as model 30, and two give a CPUID value as 0x106DX but D=13 so 0x106DX would be model 29 not model 30.  Which is it?  — Preceding unsigned comment added by 94.245.127.15 (talk) 12:30, 28 May 2012 (UTC)
thread_title:  Is Dunnington model correct 

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