Talk:List of HDL simulators

message: Focus is primarily Verilog/SystemVerilog and VHDL simulators. 
Missing is SystemC and many other HDL language simulators.
Do any other "languages" actually belong here? Such as Mast or analog mixed signal variants of 
the simulators that actually appear in this list?
RickEversole (talk) 16:41, 19 February 2020 (UTC)
thread_title:  Current list is incomplete 

message: Does this really need to be its own article? This seems to
duplicate some effort in the Verilog page. If it does
make sense to make this a page of its own, perhaps the Verilog
article should be coordinated with this by adding a link here.
Steveicarus 03:06, 18 May 2007 (UTC)
thread_title:  Does this really need to be its own article? 

message: It turns out that the author of this article, ngsayjoe, is affiliated
with the zeemz tool listed here, so I guess that it is not accident that
it is the "most user friendly and affordable" tool on the list. This
person has also appeared comp.lang.verilog performing similar stealth
marketing.
My independence may also be suspect because I'm the author of Icarus Verilog,
which is also on this list. I'll remove the "most popular" for that entry
because whether it is true or not (I have opinions that I'll keep to
myself) it doesn't belong there without references.
Steveicarus 14:40, 18 May 2007 (UTC)
thread_title:  Full disclosure 

message: Having worked on the GUI used by Synopsys, I can understand how they were able to integrate SystemVerilog quite quickly.  The VCS GUI was developed independently of the simulator, (by Simulation Technologies, later Summit Design )and was designed to be able to work with different simulators and different HD Languages (concurrently, no less). With SystemVerilog being just another simulator using just another language, developing the software wrapper to integrate 
the simulator into the VCS GUI wouldn't have been a monumental task. --64.238.49.65 (talk) 13:43, 25 March 2008 (UTC)
thread_title:  SystemVerilog & VCS 

message: The Icarus source/exe aren t spyware free. So I think it shouldn t be shown here...  —Preceding unsigned comment added by 91.3.78.137 (talk) 21:18, 29 September 2008 (UTC)
thread_title:  ICarus not save 

message: How about
http://www.axiom-da.com/mpsim.html
66.127.55.23 (talk) 05:05, 7 January 2011 (UTC)
thread_title:  Axiom? 

message: This article should be renamed to "List of Verilog and VHDL" simulators. The two overlap, most simulators support both. I'm not sure how to rename an article in Wikipedia.  —Preceding unsigned comment added by 174.116.190.217 (talk) 20:57, 16 January 2011 (UTC)
thread_title:  Generalize this to VHDL/Verilog simulators 

message: The Tachyon Design seems to be open source, is it fair to include it in the second list?  — Preceding unsigned comment added by 24.59.190.49 (talk) 21:27, 9 October 2015 (UTC)
thread_title:  Wrong list 

message: The list of commercial simulators does not mention SystemVision from Mentor Graphics, Simplorer from Ansys, or Saber from Synopsys. It does mention Mentor's Modelsim, which is integrated into SystemVision. SystemVision and Simplorer support VHDL-AMS. Saber supports VHDL-AMS and the proprietary MAST modeling language. These are all simulators I have used.  — Preceding unsigned comment added by 68.191.34.123 (talk) 13:48, 27 March 2017 (UTC)
thread_title:  Incomplete list 

message: Even though these days it is mostly seen in verification SystemC is an ISO Standard HDL and synthesizable language. I know at least Cadence Stratus and Mentor Graphics Catapolt can systhesize it. There may be other companies that offer SystemC synthesizors but that is not really an issue here. I mention it mostly to prove it is an honest to golly HDL which should be listed here. There is even an Accelera Standard document which defines the "SystemC Synthesizable Subset."
You would have to ask Cadence and Mentor about their customers but unofficial word from a Cadence AFE I know suggests it is popular for developing ASICs needing complex math. It seems to also be a player in the "High Level Synthesis" world. C/C++ is already popular for complex algorith development, both for speed reasons and because more people know it. If the algorith is developed and tested in SystemC as C++ and then synthesized directly from the resulting SystemC  that skips the notoriously high risk process of reimplementing it in a different HDL. There is no translate/reimplement step to add bugs. 
Note: The Accellera version from the Accellera web page should be listed in the free simulator section and most commercial Verilog and VHDL simulators will also simulate SystemC for verification purposes. The commercial simulators I know about (big 3) that simulate SystemC are all based on the Accellera simulator code base as was the intent. My knowledge is limited though. I only know about Accellera and the 'big 3' SystemC simulators. But if no one else takes a stab at it I might give it a shot. SystemcC simulation is already mentioned in the 'description' column for two of the big-3. I would mostly 1) add an Accellera entry to the free list and 2) add SystemC 2.3.3 (current version) to the language column in the commercial list for the companies that I know about because everyone supports that version. I don't know about support for earlier versions so i wouldn't be able to add that. I might add a mention and link to the synthesizable subset document.
Zencuke (talk) 00:52, 7 March 2019 (UTC)
thread_title:  SystemC is missing from the "language" column 

message: The free section has 2 tables broken out by language but the commercial sections lumps them all together into one table. I can see arguements for either format but it should be consistant.
Zencuke (talk) 00:52, 7 March 2019 (UTC)
thread_title:  Why the inconsistancy between the free and commercial tables?