Talk:Classic RISC pipeline

message: Very good write-up.  Let me add another wrinkel.  MIPS' conditional branches cannot be decided until the EX stage.  One consequence of this is that the stages above the delay slot must be flushed upon branch.  However the delay slot may have been stalled if it depends on a unfinished load, so care must be taken to not flush the wrong instruction.  A pain in the neck to get right, not to mention the cycle-time impact on all the control logic.  And if you want the unconditional branches to issue from the decode stage (for a lower branch penalty), then the control gets even more complicated -- Tommy Thorn, 2006-03-25
:Branches in EX?  Nope.  In both early MIPS and early SPARC pipelines, the conditional branches were decided in the decode stage.  That means the conditional branch recurrence was two cycles: instruction fetch, register read, branch decision, and instruction address mux.  No bubbles are added to the pipeline.  The R4000 pipeline added two bubbles for each taken branch.
:In the Classic pipe, the delay slot cannot be stalled on a load hit.  The load is in Access, the branch is in Execute, and the data from the load bypasses into Decode, to be used in the next Execute cycle.
:Computing the branch condition in the decode stage definitely cuts into the time available for the instruction cache.  The early machines had 40+ inverter-3 delays per clock cycle, which is what made this decision feasible.
:Later, when we did superscalar machines, the delay slots which had seemed so clean before were a nuisance.  I remember Mitch Alsup giving a presentation in 1990 on the Motorola 88000 ISA.  He knew then that delay slots were a good short-term but bad long-term idea. Iain McClatchie 07:21, 31 March 2006 (UTC)
thread_title:  Other problems with delay slots 

message: This article calls the fourth pipeline step access, while the DLX article (DLX being an example of classic RISC pipeline implementation) calls the fourth step MEM - Memory access unit. Are both the same? --Abdull (talk) 14:27, 23 May 2008 (UTC)
thread_title:  MEM vs. Access 

message: I was reading this article to refresh my memory on data forwarding and am either confused or think there is a mistake in the pipeline diagram using bypass.  The code being executed is not in the correct order in the pipeline  (first instruction should be in the right most position)  Does this make sense?  — Preceding unsigned comment added by 63.124.79.253 (talk) 13:14, 25 August 2011 (UTC)
thread_title:  Pipeline Diagram Incorrect? 

message: In the article it is saying that the early risc machines had not microcode. How about the modern risc architectures? Do they translate their instructions in their internal 'microoperations' like x86 does and is it done in the decode stage? What these mops are? If they are some another instructions encoded in the bits sequencies, and emitted in some buffer, then they also must be decoded. Right? It would be very nice if one writes about how is now, because articles tell only how it was in the very past. For example the article on arm arch. mention the same without-microcode initial design and says nothing how it is now. And what the hell that microcode is? Especially for risc? In the x86 mops are "risc-like", so what the translation in risc? Risc into risc? How that microcode is represented internally? Just another encoded bit seqencies, or something else? And then, what exactly decoding is: dispatching/routing/switching to the appropriate execution units the information about what to do and what with,
OR this is translation of the stream of the one level machine instructions into the stream of another set internal machine instructions?
Sorry for my noobiness and horrible english.
77.52.154.144 (talk) 19:33, 26 June 2013 (UTC)
thread_title:  Decode in RISC 

message: It would be helpful if there was some discussion on whether "classic" is used to to denote outdated and how this article fits into a modern architectures and understanding of pipelining.  — Preceding unsigned comment added by Indolering (talk • contribs) 23:04, 15 March 2021 (UTC)
thread_title:  Classic == Outdated?