Talk:CAS latency

message: AFAIK, CAS does not have to be an integer. For instance, a memory chip can have CAS latency 2.5. -thealsir
: Only the first generation DDR supported non-integer CAS latency, and there, only half-integer values were possible.  In practice, the only values used were 2, 2.5, and 3.  Later generations omitted the option, since their higher clock speeds gave the same timing resolution.  71.41.210.146 (talk) 09:33, 9 February 2009 (UTC)
thread_title: Integers?

message: Could somone expand this page to include some info on CAS2 (CAS3, etc.?) Thanks! Ewlyahoocom 20:33, 10 April 2006 (UTC)
replies: text: Do you mean CAS 2 as in the latency speed?  I use Dram that is rated at CAS 2.5, for example.  Zedmaster375 2 July 2008  —Preceding comment was added at 21:50, 2 July 2008 (UTC)
thread_title: CAS2?

message: * I have serious objections with the paragraph: <quote>"For example, consider a 133 MHz CL3 device (7.5 ns per cycle, 3 cycles request latency) versus a 100 MHz CL2 device (10.0 ns per cycle, 2 cycles request latency). The first bit would be available after 22.5 ns (7.5 ns * 3) on the CL3 device and after 20.0 ns (10.0 ns * 2) on the CL2 device, demonstrating the benefit of a lower CAS latency. However when reading a burst of even 4 bits, the higher clock speed wins: 45.0 ns (7.5 * 3 latency + 7.5 * 3 bits after the first) versus 50.0 ns (10.0 * 2 latency + 10.0 * 3 bits after the first)."</quote>   The math is just plain wrong considering that DRAM is never accessible by individual bits.  The smallest unit of download from or upload to DRAM is 1 byte (8 bits).  Multiplying 7.5ns or 10.0ns for each bit is ridiculous. 208.48.228.132 00:04, 22 July 2006 (UTC)
replies: text:  They clearly describe what happens on every individual data pin. How many pins there are and therefore how many bytes are trasferred in parallle is somewhat offtopic for this article.
Yes, I agree. Multiplying the cycle time for each bit is ridiculous. It's not even 8 bits, but 64 bits. Data buses are 64-bit wide. So once the CAS latency is incurred for the first 64-bits, every consecutive 64 bits will be transferred every I/O bus cycle (or twice in case of DDR). Also, it'll be good to mention what the unit of request from the CPU is -- L2/L3 cache line size? So the DRAM transfers say about 256 bytes in burst. It's going to be 7.5*3 + 7.5*31ns; however, if the load is on the aligned boundary, the load latency is going to be 7.5*3 + L2 miss time + L1 miss time + memory controller/bus arbitration cycles.  —Preceding unsigned comment added by 71.66.255.86 (talk) 18:29, 3 August 2008 (UTC)
thread_title: Errata

message: The article clearly says "burst", that is several bits sequentially accessed on each bit lane, or several words of full bus width.  Bus width is 8 or 16 bits, and there are (at least were) also 4 and 32 bit wide DRAM chips, but I can't remember if they were in the JEDEC spec.  So a burst of 4 on an 8-bit wide device would read 32 bits.
: "Burst" in DRAM parlance means fetching more than one time after receiving address information. Early memory technologies required address information for every read. Burst is an optimization which relies on the fact that reads are often sequential.  — Preceding unsigned comment added by 2A00:CA8:A14:6A01:4685:FF:FE33:1E8B (talk) 03:32, 8 January 2019 (UTC)
thread_title: About Bursts

message: The OP is taking the point of view from a single bit. In practice many bits (8/byte) are returned in parallel, but the timings are the same for each.
121.44.212.138 13:55, 3 April 2007 (UTC)
thread_title: Reply

message: I'm not an engineer but I if remember correctly from college, this analogy may help (pls correct errors).
Suppose you are a teacher taking a class on a field trip.  A magic vehicle that will take your class is used by all the schools in the district. There is only a one way road that connects all the schools and the bus drives around from one school to the next all day waiting for students to pick up.  When it get the order it will drive down the road passing the other schools until it get to yours.  If it happens to be at your school when the call comes it can pick your students up right away but if it just left your school it will take time to drive all the way around to get back to your school.  The complete circle is like the CAS.
You may ask, "Why not just stay at the first school and wait?"  The answer is that if you are the last school it will always take the full time to get to you.  By circling, the vehicle will usually be closer than that.  In fact, it will be an average of half the distance to any school at any given time.  (There are other technical reasons why it is done this way too.)
Other things to consider are the Memory Bus Speed and Memory Bus Width (size).  The Memory Bus Speed is like the road speed limit and the Memory Bus Width is like the number of seats on the vehicle.
Now back to the trip.  The vehicle arrives at your school.  It has 10 seats and you have 50 students.  10 get in and are magically transported to their destination.  The (now empty) vehicle has continued to move on to the next school.  The rest of your class must wait for the vehicle to return.
Now, if the vehicle had more seats (Wider Memory Bus) or it could travel faster (Memory Bus Speed) or the route was shorter(CAS) your students could get to their destination quicker.
It is important to remember that the CAS is not really a distance on a road. It is the number of ticks on the system clock. The analogy is only useful to help you visualize why the CAS is not the only determining factor of memory speed. —The preceding unsigned comment was added by 157.130.64.90 (talk) 18:02, 6 April 2007 (UTC)
thread_title:  Analogy 

message: Should Trcd, Trp etc... be capitalised as tRCD, tRP, as per the SDRAM latency article? 82.195.186.33 13:10, 23 August 2007 (UTC)
thread_title:  Timing Symbols 

message: The poster who posted the errata is simply wrong.  The original poster is correct.  For example, with DDR the chip is actually read 64 bits at a time, not 8 bits as some others have suggested.
When the original poster said the 1st bit would be available in 22.5 ns, he meant (and it's obvious) that the 1st 1 bit (deep) x 64 bits wide would be available.  When he said 4 bits he meant that the 1st 4 bits (deep) x 64 bits wide would be available.
I have taken the liberty of adding some additional explanation to article and removing the misleading section tag.  I am an infrequent editor and I do not know if removing the tag requires consensus or not, but if it does then I'm sure that someone can add it back.
 —Preceding unsigned comment added by 72.147.48.164 (talk) 05:01, 11 September 2007 (UTC)
thread_title:  Errata is wrong 

message: Thus CAS Latency (CL) is the time (in number of clock cycles) that elapses between the
In which clock cycles? CPUs or RAMs?--89.212.75.6 18:36, 2 November 2007 (UTC)
thread_title:  Timing units? 

message: There are no sources for most info. So its pure opinion. 82.43.183.13 (talk)
I wouldn't call it opinion, more 'general knowledge'. But some sources would be good! -ilovemrdoe 05:30, 30 December 2007 (UTC)
thread_title:  Sources? 

message: According to the original article, i suppose that even though CAS5 is the minimum on DDR3 RAM, the clock speed boost will at some point offset the speed difference on even the smallest amount of data?
As in maybe DDR2-800 is faster at 4-4-4-12 but DDR3 may be faster in ALL situations at 5-5-5-15? Talrinys (talk) 11:58, 26 January 2008 (UTC)
thread_title:  RAM speed increase versus CAS latency 

message: Am I being stupid, or does the simple advice "the lower the CAS the better" given directly contradict the table, in that the lower the CAS number in the table, the longer the total time is?—Preceding unsigned comment added by 86.4.175.44 (talk) 22:49, 4 June 2008 (UTC)
replies: text: No, it's just inobvious. The CAS is the number of cycles needed to access the memory. As the speed (time for each cycle) is going up faster than the CL, the total time is going down. Compare the last two entries of the first table: the MHz of the second is double that of the previous one (conveniently for our math), meaning each cycle takes half as much time. As the 800 MHz memory is using 5 cycles, less than double the 3 needed for the 400 MHz memory, it needs slightly less time than the 400 MHz memory. --Rindis (talk) 19:49, 24 June 2008 (UTC)

text: My question is why is it better?  That seems rather err, subjective.  For example there is a slow food movement, how do I know some people don't prefer to wait longer for their computers to compute?  Maybe "The lower the CAS, the faster the memory?"  PS: the Slow Computing people are already working on their official website, but they are still waiting for their systems to load Dreamweaver...  Zedmaster375 2 July 2008  —Preceding comment was added at 21:56, 2 July 2008 (UTC)
thread_title:  Contradictions? 

message: The examples given work with the assumption that 1 bit is being put on the bus every cycle. Data buses are 64-bit wide. So the memory doesn't transfer one bit for every I/O bus clock cycle -- it transfers eight bits.  —Preceding unsigned comment added by 71.66.255.86 (talk) 18:23, 3 August 2008 (UTC)
thread_title:  Misleading? 

message: "In the table below, data rates are given in million of transfers per second (MT/s), while clock rates are given in MHz, cycles per second."  
The foregoing sententence references the table and "clock rates". However, the table uses "Command rate" as a header.  This is the first occurence of the term "command" in the article.  Perhaps a parenthetical or description  associating "command rate" with "clock rate" would clarify the use of "Command rate" in the table. Or, perhaps just changing the header to "Clock cycle rate" would suffice?  Andage01 (talk) 15:50, 3 June 2009 (UTC)
thread_title:  Clock Cycles/Command Rate 

message: Quite a fully-featured article but it seems to skip the basics for people who just want to know what it is and how to make sense of a CAS rating.  — Preceding unsigned comment added by 86.148.36.186 (talk) 10:44, 7 September 2011 (UTC)
thread_title:  Doesn't seem to state what, if anything, CAS stands for (which might help to explain it) or what it's actually measured in. 

message: The examples goes so:
:As an example, a typical 1 GiB SDRAM memory module might contain eight separate one-gibibit DRAM chips, each offering 128 MiB of storage space.  Each chip is divided internally into eight banks of 227=128 Mibits, each of which comprises a separate DRAM array.  Each array contains 214=16384 rows of 213=8192 bits each.  One byte of memory (from each chip; 64 bits total from the whole DIMM) is accessed by supplying a 3-bit bank number, a 14-bit row address, and a 10-bit column address.
Well, shouldn't it read 
: , and a 13-bit column address.
Also, (I think) there is a terminological incoherency in usage of the words "module", "chip", and "bank" between the 1st section (the above example) and the 2nd section. Namely, the 2nd section (Effect on memory access speed) starts its 2nd paragraph with
:Because memory modules have multiple internal banks, ...
Either (A) the "memory modules" should be "memory chips" or (B) the "banks" should be "chips". Which is it, (A) or (B) (or none)?  — Preceding unsigned comment added by 92.37.27.220 (talk) 13:50, 22 June 2012 (UTC)
replies: text: (A), each chip has multiple internal banks.  (Which means that modules built of chips technically do too, but I agree it's confusing.)  The text could also be clearer that "bank" and "array" are synonymous.  As for the number of bits, the text is correct.  Each column is 8192 bits.  Since each chip outputs one 8-bit byte, it needs 10 column address bits to specify one of 8192/8 = 1024 possible bytes. 92.119.17.10 (talk) 13:15, 13 October 2020 (UTC)
thread_title:  Example of "a typical 1 GiB SDRAM": shouldn't there be a 13-bit (not 10-bit) column address? 

message: can anyone pls update that table for dd3 speeds : 1866, 2133, 2400, 2666 and finaly 2800 ?
88.102.84.189 (talk) 14:50, 4 August 2013 (UTC)
thread_title:  more freqvencies :) 

message: Can anyone fix the table for DD2-1066, because i add DD2-533 & DDR2-400 to the table and in the row of DD2-1066 the CAS latency moves and i can't fix it. 186.60.194.94 (talk) 01:07, 10 June 2015 (UTC)
thread_title:  fix memory timing table. 

message: GDDR5 timings, this PDF on page 133:
http://www.hynix.com/datasheet/pdf/graphics/H5GQ1H24AFR(Rev1.0).pdf
* CAS = 10.6ns
* tRCD = 12ns
* tRP = 12ns
* tRAS = 28 ns
* tRC = 40ns
No much more compared to DDR3 like 10% also can someone explain BURST modes?, because GDDR always use BURST8 and DDR can use 0,4,8.
In DDR, how things change with burst?  how many times can a controller change the burst modes?
————————The link " http://www.hynix.com/datasheet/pdf/graphics/H5GQ1H24AFR(Rev1.0).pdf" appears to be broken, is the original source still available? GearsWorker (talk) 09:29, 2 July 2018 (UTC)
thread_title:  GDDR5