Talk:Protection ring

message: Is this a reference to NIST Special Publications (SPs)?   — Preceding unsigned comment added by 96.252.66.105 (talk) 15:56, 18 June 2012 (UTC)
replies: text: "SPS" is not in the article any more, so there's no need to define it now. Guy Harris (talk) 21:55, 13 November 2015 (UTC)
thread_title: define SPS

message: this term is mentioned quite a few times on this page and on the page for microkernels. I have no idea what it means, and it's definition is not clear. The only thing clear is that it is the alternative to privileged/kernel model.  —Preceding unsigned comment added by 209.77.137.57 (talk) 00:28, 14 August 2008 (UTC)
thread_title: define user mode

message: This article would benefit from a clearer explanation about what a protection ring is and does. It assumes the reader knows what "one of two or more hierarchical levels or layers of privilege" means and why "rings were among the more revolutionary and visible concepts ..." The whole lead seems to step around defining what a ring is in simple terms, why it is significant, and how it is used. A very concise paragraph addressing some of the basics would be a great improvement to the lead section. JonHarder 13:57, 25 July 2006 (UTC)
thread_title: Confusing or unclear

message: Why is elegance linked in the "Interoperation between CPU and OS levels of abstraction" section?  —Preceding unsigned comment added by 207.96.162.77 (talk) 18:36, 17 December 2007 (UTC)
replies: text:  Because it has a different definition for different people. And in this context, it should be made clear which one is meant. … Of course linking to a generic page and expecting the reader to find which one was means, isn’t exactly solving that. ;) — 89.1.58.198 (talk) 09:23, 23 May 2023 (UTC)
thread_title: Why

message: What is a kernel mode driver ?. --Mac (talk) 10:35, 25 April 2008 (UTC)
thread_title:  Kernel mode driver 

message: I'd like to request more in-depth discussion on hypervisors like those running IBM mainframes, perhaps historical perspective with the (again) IBM romp vm layer that ran AIX as a guest, or any of the alternative and/or comparable approaches (sun? hp?) that predate amd's and intel's johnny-come-lately implementation of this idea. 84.82.170.167 (talk) 23:18, 9 February 2009 (UTC)
thread_title:  Hypervisor 

message: For quite some time now x86 processors have implemented a System Management Interrupt. This is a non-maskable interrupt similar to the NMI that causes a transition back to the BIOS (actually whatever lives at 0xA0000 behind the legacy video ram). The OS has no control over this interrupt and is not notified that the interrupt occurred in any way. It is intended to be used by motherboard manufacturers to transparently deal with special features of their boards. See  for more info about why this is important. DaBraunBird (talk) 16:59, 8 December 2009 (UTC)
replies: text: SMM mode sometimes reffered as "Ring -2" `a5b (talk) 14:46, 10 January 2012 (UTC)
thread_title:  System Management Interrupt - Ring {{math|{{radical|-1}}}} 

message: The statement that micro-kernels are "sacrificing performance" is too strong, and contradicted by the performance of modern micro-kernels, such as L4.  — Preceding unsigned comment added by 121.127.198.152 (talk) 00:36, 8 August 2014 (UTC)
thread_title:  Microkernel performance 

message: overlapping scope - x86 can/should be a section in main article given current article Widefox; talk 18:33, 13 June 2017 (UTC)
thread_title:  Proposed merge with [[Privilege level]] 

message: Given that Intel recently announced potential removal of ring 2 and 3, and this quote in the article:
The attractiveness of fine-grained protection remained, even after it was seen that rings of protection did not provide the answer...
What are the replacements modern systems will have? … All I can think of is RBAC-like systems, like RSBAC (French afaik) and SELinux (NSA, USA), etc. But that doesn’t have hardware support. But maybe it isn’t necessary…
It would be good if the replacements, whatever they are, would be shortly mentioned in the article, and linked to a (new?) article about them.
— 89.1.58.198 (talk) 09:28, 23 May 2023 (UTC)
replies: text: Well, there are capability-based systems, but I don't know of anybody selling them these days. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 16:15, 1 December 2023 (UTC)
replies: text: I don't know of any products from it yet, but the CHERI project from SRI International and the University of Cambridge has added capability support to MIPS, Arm, RISC-V and, err, umm, an instruction set that's not generally considered "R", namely x86.  Arm has shipped a prototype CHERI-equipped SoC and demonstrator board.  (I think somebody from Cambridge gave a talk, atn one point, using a notebook computer with a CHERI-equipped MIPS processor running a CHERI-supporting FreeBSD as the presentation machine.) Guy Harris (talk) 20:01, 1 December 2023 (UTC)
thread_title:  Post-”rings of protection” solutions? 

message: Perhaps it's time to split Call gate (Intel) into a generic article and an Intel-specific article, and possibly add an article specific to Multics? Are there any wikipedians with a Multics background? -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 16:08, 30 November 2023 (UTC)
replies: text: I’m a dabbler, but not more than that. Peter Flass (talk) 18:53, 30 November 2023 (UTC)
thread_title:  Link to [[Call gate]]s