Talk:X86 instruction listings

message: No Secure enclave processing instructions listed.  — Preceding unsigned comment added by 100.6.80.179 (talk) 01:04, 8 October 2018 (UTC)
thread_title:  SGX Instructions Missing 

message: wich instructions are integer, wich are floating point, wich are "other"? (similar distinction as in SSE/2/3 lists) Alinor 14:03, 25 February 2006 (UTC)
thread_title:  MMX, 3DNow! 

message: Some processors are not mentioned in the "instructions added with" lists:
*80187 [ Note: THe 80187 is the FPU for the i80c186, because the i80188 is 8 bit ][ Intel 187 ]
*80487 [actualy a i80486DX integrated FPU]
</blockquote>"The i487 SX was not really a Co Processor. It was a normal i80486 DX processor when installed to disable the onboard SX Processor and take over main operation of the CPU and add an FPU. The i487 has one pin more than a normal 486 cpu, so you need a special socket to install this chip."</endblockquote>[ i80487sx ]207.53.252.58 (talk) 20:27, 17 July 2023 (UTC)
thread_title:  missing instructions 

message: Was CPUID introduced in the 486? This article says that it was, but I think it might have been introduced with the Pentium and not earlier. - Richardcavell 04:17, 3 January 2007 (UTC)
replies: text: To quote Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide, Part 1, page 17-6 (the 600th page of the PDF document in question), "The CPUID instruction is available in all Pentium and P6 family processors and in later models of the Intel486 processors. The ability to set and clear the ID flag (bit 21) in the EFLAGS register indicates the availability of the CPUID instruction.", so it was introduced in later 486 models - some had it, some didn't. Guy Harris 09:39, 3 January 2007 (UTC)
thread_title:  CPUID 

message: I'm going to be converting the lists of instructions that aren't in table form (e.g. 486 instructions and up) and converting it into tables as a way to spend my summer. If you want to help with this or have any questions / comments, post them on my usertalk. Thanks! Andreyvul (talk) 07:23, 31 July 2008 (UTC)
thread_title:  Overhauling the article...anybody want to help? 

message: The instructions bswap,cmpxchg,invd,invlpg,wbinvd,xadd
Do they exist on the AMD K5 and AMD K6?  
What about on the Cyrix 686?
And the Pentium instructions: cmpxchg8b, rdmsr, rdtsc, wrmsr ...
Do they exist on the AMD K5 and AMD K6?
What about on the Cyrix 686?
Mark Hobley  —Preceding undated comment was added at 20:36, 8 February 2009 (UTC)
thread_title:  Clarification of supported instructions 

message: When you compile a program for a windows 32 bit system, which assembly language and which machine language is used? In other words, which of the instruction sets is it that is used in .exe-files? I can't find it in the article, maybe it could be put there? --Kri (talk) 23:49, 26 February 2009 (UTC)
replies: text: It depends which compiler you're using, and what options you passed to it. JulesH (talk) 11:01, 7 March 2009 (UTC)
replies: text: I'm not talking about any specialized exe-programs that works for your processor only, but about the general .exe files that work on all windows 32 bit computers (for example VLC in exe format is supposet to work on all windows computers). So I wonder, which set of machine language instructions does Windows require of the processor to support? Also, is this required set of instructions the same for Linux, since it is run on PC:s as well? --Kri (talk) 19:25, 7 March 2009 (UTC)

text: Is there really no one who knows the answer to that question? Ok, which is the most commonly used x86 instruction set then? --Kri (talk) 16:52, 17 March 2009 (UTC)
replies: text: First, a modern compiler compiles directly to machine code. Second, there actually are no "general .exe files"; it really depends on the compiler you are using. For example, Microsoft C++ compiler options allow you to enable SSE or SSE2 instructions to be generated. MazeGen (talk) 19:07, 13 May 2009 (UTC)

text: Yes it's true that compilers can choose to emit whatever code they want. But the questioner(s) asked about the common-or-garden win32 exe that might be found on a 32-bit Windows box. The answer is (a) 386 instruction set at a minimum, but (b) it is rather more likey nowadays that if you were to dig into more recently built exes you would find that the compiler was told to assume that a Pentium Pro (the first of the 686 family if you like) or higher be present, and indeed you might well find that (c) SSEv.xx instructions will be present in some apps where the authors know that they are not going to be deployed on very old machines because the authors do not support ancient operating systems. So either 386 or 686 is the answer. For PCs running 64-bit Windows (ie AMD64 aka x64), then you will find two different types of windows exes: the native 64-bit ones written in the x64 instruction set and running in the new x64 "long mode", and you may also find some 32-bit app exes which will run too just as in 32-bit windows.83.105.29.227 (talk) 12:49, 1 June 2009 (UTC)
replies: text: Common practice is to code a bunch of critical functions in SIMD (SSE 1/2/3/4 etc.), include them all in the exe, and use runtime CPUID checking to see the machine's capabilities. Then, using dynamic binding (e.g. function pointers), the most optimised available version is used. Therefore this "general exe" will run in scalar mode on a 386, but use the latest SSE X functions on a Core i7, for example. I'm not too sure about auto-vectorisation; I suspect different codepaths would all be included, and again dynamic binding used. It would be quite irresponsible for compiler makers to break output for older CPUs. C xong (talk) 04:49, 16 March 2010 (UTC)
thread_title:  Which instruction set is used in 32 bit windows programs today? 

message: This was broken out into a section for instructions added in the Pentium II.  This is incorrect.  The Pentium Pro instruction reference  lists it as available since the Pentium.  I don't have a reference to the original Pentium manuals, but I see no reason to believe that it was not listed in those; certainly when I was working on NASM the instruction was well known, and I'm pretty certain it wasn't on our list as undocumented. 
Even if it wasn't officially documented at the time, it has since been officially documented as available on the Pentium, so it belongs in the section for Pentium.  I have moved it back.  JulesH (talk) 22:35, 28 March 2009 (UTC)
thread_title:  RDTSC 

message: The 386 table lists LODSW as new. That should be deleted surely? As not "new" - was in the 8086? Check thatI'm not going mad, and feel free to correct the table, or I'll do it.83.105.29.227 (talk) 12:51, 1 June 2009 (UTC)
replies: text: Removed. C xong (talk) 04:51, 16 March 2010 (UTC)
thread_title:  Check my brain pls - LODSW and 386 

message: OR is linked to http://en.wikipedia.org/wiki/Logical_NOR instead of http://en.wikipedia.org/wiki/Logical_OR.
As i'm pretty new to assembly, i won't change it but would like to have it checked by someone who knows what he's doing.
:Changed. Be bold! C xong (talk) 04:56, 16 March 2010 (UTC)
thread_title:  Wrong link in instruction table 

message: * I think that MOV {DS|ES|SS},r/m are very documented instructions and perhaps the most popular way to load segment registers. (The other popular way is PUSH <something> / POP {DS|ES|SS}. The MOV CS,r/m is indeed undocumented. Although, the 8086 datasheet contains generic 'register/memory to segment register' opcode, and doesn't show MOV CS,r/m as an exception. Moreover I verified MOV CS,r/m instruction on various versions ('78, '78 '81 and '79 '83) of Intel 8088, on Intel and Harris 80C88, AMD 8088, and NEC V20 and V20HL, and it works on all of them, causing a far jump.
* AAD (and probably AAM) instruction with argument doesn't work properly on NEC V20, V30 and probably other NEC CPUs. They always assume that argument is 0Ah.
* I don't think that AAD implementation was buggy on first Intel CPUs (as Original 8086/8088 instructions sections mentions). It simply was not documented to accept any argument other than 0Ah  —Preceding unsigned comment added by 71.111.52.89 (talk) 20:39, 22 January 2011 (UTC)
replies: text: Hello, i hope my question back can answered after so long time. I have a question for "MOV CS,r/m"..."and it works on all of them, causing a far jump", if you only modify the CS and not the IP-Register, that kind of "far jump" is done by an "MOV CS,r/m"-Instruction? Do you realy have tested it on old physical CPUs?I can remember on original Documentation (from Intel and others) about the 386 and there are the "MOV SR,r/m" (0x8E ...) and "MOV r/m,SR" (0x8C ...) described as normal OpCodes with all 6 possible Segment-Registers for both Directions (only the valid usecase for "MOV CS,r/m" was not described).Greatings, Erik --2003:ED:F7FF:17D1:E03F:66BD:87C5:5946 (talk) 22:58, 21 October 2022 (UTC)
replies: text: The far jump that occurs is that the segment is changed but the offset remains the same.  So e.g. if you load CS with 1234 with the address following the move begin dead:beef, you jump to 1234:beef.  On the 80186 and later, loading CS through anything but an explicit jump instruction is instead forbidden. --FUZxxl (talk) 14:43, 23 October 2022 (UTC)
thread_title:  Undocumented Instructions 

message: For instance what is /r? WvvvvL01 69 /r /is4 say what? This stuff is not so easy to find out, and isn't generally covered in ASM manuals.
PS: Not asking for help, just saying it's too opaque as is. --67.54.192.52 (talk) 05:42, 3 February 2011 (UTC)
thread_title:  An opcode notation legend would be helpful 

message: The presented information about the ENTER instruction (that it is equivalent to PUSH BP / MOV BP, SP / SUB SP, n) is correct only if the second operand (the nesting level) is zero. If it's non-sero, the behaviour of ENTER is more complex. See for example the Am186™ and Am188™ Family Instruction Set Manual (p. 4-53) for a description of this instruction.
Лъчезар☭共产主义万岁★ 15:17, 4 April 2011 (UTC)
thread_title:  The ENTER instruction is more complex than presented 

message: The sections 1.2 ("Added in specific processors") and 2.2 ("Added in specific processors") state that the instructions listed in its sub-sections have been added with some processor, but they miss to describe what the basis for the addition was. Not in all cases is the addition relative to the previous section / processor. In most cases, it is not the base 8086/8087 instruction set, either.
These sections should be updated to explicitly state relative to which other section or processor the instructions listed in the current section were added.
Gandalf44 (talk) 15:38, 11 May 2011 (UTC)
thread_title:  "Added" relative to what ? 

message: Section 1.2 ("Added in specific processors") describes SSEx as processors and lists certain instructions that were added. Section 3 ("SIMD instructions") describes SSEx as a set of instructions (which is correct). There are multiple issues with this approach:
* It is confusing to describe SSEx as both a processor and as a set of instructions. It is really only a set of instructions, there are no processors or microarchitectures with these names, however there are processors that support these sets of instructions (and sometimes there are flavors of the same processor type that support these differently, e.g. I believe that Pentium 4 has a flavor that supports just SSE2 and one that supports SSE3 in addition).
* The set of instructions in both descriptions is sometimes similar, and sometimes quite different (e.g. 1.2.9 "Added with SSE" and 3.6.2 "SSE SIMD Integer Instructions" list very different instructions, while the instructions in 1.2.15 "Added with SSE4a" are a subset of those in 3.10.2 "SSE4a"). This is very confusing, even after one gets beyond the previous issue by interpreting that as processors.
I suggest that section 1.2 really only mentions instructions added by processors (or microarchitectures, as a means to refer to all the processors implementing that microarchitecture), and that specific named instruction sets are only described in section 3. If processor types need to be qualified because there are different flavors supporting different instruction sets, than such a qualification simply needs to be added.
Gandalf44 (talk) 15:56, 11 May 2011 (UTC)
thread_title:  SSEx processor vs. SSEx instruction set 

message: The instruction list shown in the table in section 3.6.2 ("SSE SIMD Integer Instructions") lists NOP with opcode 0F 1F. This is different from the NOP in the 8086 base instruction set (opcode 90). It would be helpful to explain why a different NOP was needed (if anyone knows ... - or at least to point out that this is a different opcode that shares the same mnemonic).
Gandalf44 (talk) 16:52, 11 May 2011 (UTC)
thread_title:  NOP in SSE instructions 

message: I believe it would be useful to add AT&T mnemonics to help finding instructions such as movl/addl/etc, both to help search engine results and also when doing textual searches inside the page.
However, this could complicate a bit things, since for instance many such instructions (e.g. mov) are defined for 8086 on Intel syntax, but might have to be added under a different family for the "extended" version.  — Preceding unsigned comment added by Dhekir (talk • contribs) 07:25, 20 July 2015 (UTC)
thread_title:  AT&T syntax/mnemonics 

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thread_title:  External links modified 

message: the page lacks 8A ** ** ** instruction, which is from 8086 or older and compatiblity is kept till today.
I tried today to disassemble some program and it seems my disassembler also don't know it.
here is some info, I don't fully understand: http://ref.x86asm.net/coder32.html#x8A  — Preceding unsigned comment added by 89.74.199.35 (talk) 02:12, 9 August 2016 (UTC)
thread_title:  Compatibility instructions 

message: Is there a similar page for ARM listings?
If not, then one could create by automating from the ARM documentation itself. Anyone up for it?  — Preceding unsigned comment added by Temp00guy (talk • contribs) 01:51, 29 April 2017 (UTC)
replies: text: LOL, it's not as easy as you might think, because "ARM" has many different instruction sets / architectures / cores.  For useability, most end users don't give a crap about architectures or instruction sets, instead they care what is in a specific core, and unfortunately cores may be a SUBSET of an architecture and support one or more instructions sets (or sub-instruction sets).  In past years, I took a stab at doing all "ARM Cortex-M#Instruction sets" cores and it was very difficult to do.  A very high percentage of the top of the ARM Cortex-M was created by me.  • Sbmeirow • Talk • 09:45, 29 April 2017 (UTC)

text: No one should try to attack this issue without planning the article and table layout first.  It's better for multiple people to hash it out concepts and issues first.  We either need to do it right or NOT do it at all.  • Sbmeirow • Talk • 09:45, 29 April 2017 (UTC)

text: ARM has released machine readable architecture specification for their v8-A processor.  Perhaps we can start from there? Temp00guy (talk) 00:18, 5 May 2017 (UTC)
thread_title:  ARM instruction listings 

message: thumb|https://hsto.org/webt/ph/4k/70/ph4k700mdvxwacaepm4uzqoq188.png
from https://habr.com/ru/post/503486/  — Preceding unsigned comment added by Arkeke (talk • contribs) 06:31, 24 November 2020 (UTC)
thread_title:  Add graph 

message: I would like an operands column in the table under integer instruction listings. I don't think the notes column would suffice. This text might not be sufficient, in that case, ask and I shall provide info. This may be unnecessary, in that case ignore this.  — Preceding unsigned comment added by BigGayDinosaur (talk • contribs) 04:56, 4 January 2021 (UTC)
thread_title:  Operands