Talk:Serial Peripheral Interface

message: "A serial peripheral bus is the most flexible choice [...]"
"[...] making it an excellent choice for some data transmission systems."
"SPI looks at first like a non-standard. However, [...]"
"The interface is also easy to implement for bench test equipment [...]"
This article is well written, but does anyone else get the feeling that this article was written by the SPI Promotional Society?
--Dan McCarty 14:52, 21 June 2006 (UTC)
thread_title:  Early comments 

message: Is SPI used as an interconnect across boards, or is it an onboard bus only? —Preceding unsigned comment added by 63.231.83.177 (talk • contribs) 
there is no reason it can't be used across boards, the standard doesn't define any standard connectors though and as the article says its a very loose standard. As with any bus of this nature achievable distances will depend heavily on clock speed and characteristics of the interconnecting lines. Plugwash 23:36, 7 October 2006 (UTC)
thread_title: across boards or single board

message: The parallel port voltage level on the most recent PCs is less than 5V.  This can make it difficult to use it for direct SPI control, so some sort of interface IC is usually needed. DFH 12:03, 3 November 2006 (UTC)
thread_title:  Parallel port voltage 

message: Upper Canada Technologies was the company that supplied the "IOport" driver to enable WinNT machines to directly control the parallel port.  Their web address was http://www.uct.on.ca/ but this is no longer a valid URL. DFH 12:11, 3 November 2006 (UTC)
thread_title:  Upper Canada Technologies 

message: The page needs more details IMO; sorry I have time to gripe about it now, but not enough to fix it much (I'm researching on whether disabling the frame select/chip select is mandatory between frames when SCPH=0, and my boss is checking every no and then...).  Even the external links don't have much detail. 202.33.138.40 05:13, 29 November 2006 (UTC)
thread_title:  Need more details 

message: A diagram depicting this would be a useful addition to the article. DFH 19:08, 21 December 2006 (UTC)
replies: text: I'll put it on my list to do.  Can you name any specific devices that do daisy chaining?  Cburnett 19:26, 21 December 2006 (UTC)
replies: text: Freescale (Intelligent High Current Self-Protected Hi-Side Switch) MC33982 and MC33984 both support daisy chain. DFH 20:54, 22 December 2006 (UTC)

text: Done. Cburnett 20:58, 21 December 2006 (UTC)
replies: text: Thanks, but I noticed there is a line missing from slave 3 back to the master. DFH 20:48, 22 December 2006 (UTC)
replies: text: Fixed. Cburnett 00:16, 26 December 2006 (UTC)
replies: text: Thank you. 57.66.65.38 13:35, 4 January 2007 (UTC)
thread_title:  Daisy chain connection of several SPI slaves 

message: We don't need a separate Wikipedia article about Queued Serial Periperal Interface (QSPI).  An additional section in this article would suffice. Any volunteers?  I am therefore removing the QSPI redlink from the See also section. DFH 19:37, 21 December 2006 (UTC)
replies: text: I created the respective redirects: QSPI, Queued Serial Peripheral Interface Bus, Serial Peripheral Interface. Cburnett 20:11, 21 December 2006 (UTC)
replies: text: Do you have any documentation on it?  I can't seem to find any good docs in my quick google search. Cburnett 03:21, 22 December 2006 (UTC)
replies: text: I too did a quick Google search yesterday, yet didn't stumble upon a proper spec.  There are probably some Motorola or Freescale products which embody it. I will search again soon.  DFH 20:46, 22 December 2006 (UTC)
replies: text:  , ,  are examples of QSPI. DFH 22:18, 22 December 2006 (UTC)
replies: text:  This section now cites a useful reference. DFH 20:23, 5 January 2007 (UTC)
thread_title:  QSPI 

message: Bus is not a proper noun, nor is it part of the acronym.  Should the title be changed to Serial Peripheral Interface bus (by means of a page move)? DFH 21:16, 22 December 2006 (UTC)
replies: text: I'd say drop the "bus" altogether. If not that, then lowercase "bus". Cburnett 21:26, 22 December 2006 (UTC)
replies: text: It seems the article began (or was duplicated) as Serial Peripheral Interface, which is now a redirect to here, but has some edit history. These circumstances make a move back more difficult.  It may be simpler just to make "bus" lowercase. DFH 22:01, 22 December 2006 (UTC)
thread_title:  Why is bus capitalized in the article's title ? 

message: I am about to replace the particular example "For example, the LPC2104/2105/2106 (a ARM7TDMI 60 MHz microcontroller)" by a reference to the SPI Block Guide. DFH 16:35, 4 January 2007 (UTC)
replies: text: Glad to see a more generic reference! Cburnett 20:14, 4 January 2007 (UTC)
thread_title:  Clock phase and polarity 

message: The bars over SS are missing.(There should be bars over SS to indicate the Active Low nature) —The preceding unsigned comment was added by 203.91.193.50 (talk) 10:03, 6 March 2007 (UTC)
replies: text: I agree, maybe these should be here.  Especially since the broad nature of the article uses the notion that SS is always asserted when the line is pulled low (and idle high).  Now granted, EVERY chip that I have used makes this the state of operation, but is this a given for all parts or is this just a convention that most choose to follow?  And generally, this is defined by the slave parts, since most parts that implement master mode don't allow use of the SS line as a assertion out line.--Ronb 16:32, 7 April 2007 (UTC)
replies: text:  Done. Cburnett 16:41, 7 April 2007 (UTC)

text: My two cents: use the 'nCS' convention (or if you must, 'nSS') rather than trying for fancy typography.
I just updated the article to point out that chipselects are not always active low. -- 69.226.212.132 06:09, 2 June 2007 (UTC)
thread_title:  Missing Bar over SS 

message: IMO there's no point in having a separate page on MicroWire.  Maybe someone with an account can merge that one into this page.  Ideally there should be a bit more info there, too. --69.226.212.132 06:12, 2 June 2007 (UTC)
thread_title:  MicroWire 

message: Someone with a bit of time to create art might consider the classic picture showing how the master and slave side shift registers hook up to each other.  SPI controller documentation for most SOC chips will have such a picture.  When updating the description of data transfer, I added verbiage to say what happens ... but that's very amenable to a picture (pick some oddball word size, maybe 11 bits).  That level of presentation -- words, not bits -- has been mostly missing; which is too bad since it's the level that most developers think at. --69.226.212.132 06:20, 2 June 2007 (UTC)
replies: text: I have added an image.  Comments and suggestions?  Cburnett 01:55, 25 June 2007 (UTC)
replies: text: Artwork ... thanks!  My first reaction was that showing the memory is a bit confusing; it's just sitting there.  I'd suggest just focussing on the shifty bits; getting beyond that starts to get into structures that won't exist in all controllers (like tx/rx buffer registers, possibly backed by FIFOs or with DMA, etc).  A picture I happened to have readily at hand is Fig 17-2 in Atmel's ATmega168 spec ... no memory drawn, but it does show the master with clock generator and managing chipselect.  On closer examination, the bit numbering is also a bit confusing.  Normally bit 0 is the LSB and would be shown on the right ... here it's shown on the left!  But in deference to those heretical systsems where bit 0 is the MSB (and thus is shown on the left), it might be better to just label "MSB" and "LSB".  I hope you prefer "copious feedback" to "grunt, yeah". ;)  69.226.213.6 15:54, 28 June 2007 (UTC)
replies: text: I was thinking and planning a short series of images: a copy from memory to the buffer; then the transfer; then storing back to memory.  I was waiting for feedback before investing that much work.  Hindsight says I should have mentioned this above. :)  I always welcome constructive feedback!  Cburnett 16:32, 28 June 2007 (UTC)
thread_title:  Shift register picture desirable 

message: It would be useful if somebody could explain where generally the SPI devices are to be found.
83.208.14.127 00:56, 25 June 2007 (UTC)
replies: text: Guess I'm not sure what you mean.  You can find it on many, many microcontrollers (PIC, Atmel, Philips, etc.) and many, many devices (Maxim for one).  Cburnett 01:35, 25 June 2007 (UTC)

text: I'm not sure either.  Most distributors have on-line catalogs nowadays, and you can probably just enter SPI as a search key.  I've done that with DigiKey(.com) with success.  Chip vendors don't tend to sort by interconnect though; if you want a Zigbee chip, you'd just have to *know* that they almost universally talk SPI.  (Except for modules that embed a SPI chip and a microcontroller, offering a "high level" interface with a UART or something to the micro.)  69.226.213.6 15:31, 28 June 2007 (UTC)

text: Yes; I'm no PXA fan, myself.  The key is:  don't limit yourself to SPI-specific controllers.  ISTR that pxa270 doesn't have dedicated SPI; it has a multipurpose SSP controller which can be used in SPI mode (among other modes including I2S).  Lots of controllers have similar multipurpose serial ports ... OMAP1 has McBSP, which can be used in SPI mode, so an OMAP5912 supports a whole bunch of SPI:  3 McBSP ports, one MicroWire, one SPI ... two MMC slots with SPI support, and ISTR a few other controllers too.  Atmel AT91rm9200 has one SPI and three SSC; AT91sam9261 has two spi and three SSC, as does the AVR32 AT32AP7000.  And yes, bitbanging SPI is really easy, depending on the data rates you need and how much CPU bandwidth you have free.  69.226.247.176 19:15, 14 August 2007 (UTC)
replies: text: Another option may be to use some basic logic chips (or a PAL) to gate the SPI outputs so that only one chip at a time sees SPI activity even though the controller has only one SPI interface. Plugwash 00:18, 15 August 2007 (UTC)
thread_title:  so where can one find it? 

message: There seems to be a problem with the first picture for the SPI interface. The MOSI of the Master should go to the MISO of the slave and the MOSI of the slave to the MISO of the master.  —Preceding unsigned comment added by Mihaigalos (talk • contribs) 22:02, 6 October 2007 (UTC)
replies: text: MOSI means "master out, slave in".  So the MOSI pins get connected together and MISO pins get connected together.  Thus, you don't have to rewire if you switch the master around.  Cburnett 04:32, 7 October 2007 (UTC)
thread_title:  Picture of Bus interface problem 

message: Well-deserved B-class article.  Correct me if I'm wrong: I marked the importance as low.  -download | sign! 22:18, 7 April 2009 (UTC)
thread_title:  Assessment 

message: There was a link on the article for a commercial hardware implementation of SPI, that was not interesting as a reference and in my opinion configured advertising. I suppressed it.
RCelistrinoTeixeira (talk) 11:46, 4 July 2009 (UTC)
thread_title:  Commercial link 

message: What is GSPI?  —Preceding unsigned comment added by 71.131.2.31 (talk) 06:53, 22 October 2010 (UTC)
thread_title:  What is GSPI? 

message: Is anyone interested in renaming this article to "SPI bus"?  Recently, the "Controller area network" article was renamed to the "CAN bus", see http://en.wikipedia.org/wiki/Talk:CAN_bus#Requested_move_2  This isn't a formal request, but instead meant to be a discusion.  • Sbmeirow • Talk •  15:37, 14 January 2012 (UTC)
replies: text: It looks like that was done because they could not agree whether it should be Controller Area Network and Controller area network. It is best to avoid acronyms in titles (see WP:ACRONYMTITLE). ~KvnG 15:44, 14 January 2014 (UTC)
thread_title:  Rename article? 

message: Isn't In-circuit serial programming (as described in the article) just an application of the SPI bus?
Sylvain Leroux (talk) 13:40, 27 March 2012 (UTC)
thread_title:  Merge with  In-circuit serial programming   

message: isn't this:
  SPIDELAY(SPISPEED - (SPISPEED/2));
the same as this?
  SPIDELAY(SPISPEED/2);
if not, can someone comment the code to say why!  — Preceding unsigned comment added by 87.194.212.27 (talk) 14:29, 16 July 2012 (UTC)
thread_title:  The Code Sample 

message: "Most slave devices have tri-state outputs so their MISO signal becomes high impedance (disconnected) when the device is not selected. Devices without tri-state outputs can't share SPI bus segments with other devices; only one such slave could talk to the master, and only its chip select could be activated."
: First off, can't is a strong word here -- a slave device without a tri-state MISO (output) pin can just have it's MISO pushed through a tri-stateable buffer, and have the buffer's /E pin tied to the slave device's /E pin. Not to mention, if you weren't interested in the data from MISO on that particular slave device, you could just leave MISO disconnected (i.e., no additional hardware solution, let's you write to multiple devices that do not have tri-state MISOs, and still read from the devices that matter.)  Alternately, if you did need to be able to read from that slave device, and you don't have a tri-state buffer, you could use a separate IO pin for that particular slave device, etc...
: Second off, any /E (chip select) pin of any device could still be enabled, and data could still be sent to any device on the bus via the MOSI pin (regardless of what was going down on the MISO pins).
BrainSlugs83 (talk) 09:25, 19 September 2012 (UTC)
thread_title:  Incorrect Information 

message: When did SPI come out? Has the popularity of it been increasing in the last few years? Perhaps this article could use a history section up top. —Voidxor (talk) 08:06, 3 February 2009 (UTC)
replies: text: Agree.  This article needs a history section. • Sbmeirow • Talk • 13:31, 26 March 2013 (UTC)
replies: text: Motorola's MC68HC11 Reference Manual is from 1989. In a 1986 patent, however, Motorola names a completely different invention "Serial Peripheral Interface (SPI)". Thus, it is safe to say that the SPI was developed in the late eighties. --Rainald62 (talk) 15:05, 15 August 2016 (UTC)
thread_title: History

message: I find it interesting that a particular user does not believe that "SPI" could be pronounced like "SPY" and is asking for references.  Anyone who has worked in the industry since the SPI bus has been implemented (30+ years now?) has probably heard it called S-P-I (spelled out) or alternatively, like the word "SPY" (long I sound in English, but not like "SPEE", which has a short I sound). 
I work at a major semiconductor company and we use the pronunciation "SPY" all the time for SPI (along with "S-P-I".)  It is akin to saying a "Dual Inline Package" (DIP) is a "dip", pronounced the same way as in what you use with potato chips...however, I've rarely heard anyone say a "D-I-P" package.
If you need some sort of internet reference, here is one:  http://electronics.stackexchange.com/questions/57902/how-do-you-pronounce-the-following-set-of-words,  you'll see people use both "S-P-I" and "SPY" being used as pronunciations.  — Preceding unsigned comment added by 137.71.23.54 (talk) 18:23, 3 May 2013 (UTC)
replies: text: Hi, the particularly interested user questioning the pronunciation "spy" is me. ;-) In all those decades I never heard it being pronounced "spy", that's why I asked for a source. Thanks for providing one. To be honest, I do not count this forum post as a reliable reference, but I will leave it at that. If you find better sources, please provide them. Thanks. --Matthiaspaul (talk) 22:27, 3 May 2013 (UTC)
thread_title:  Pronunciation of SPI 

message: Why was the code simulation section deleted?  It should be considered "pseudo-code" of how SPI works, which is sometimes more helpful than textual descriptions.  • Sbmeirow • Talk • 23:09, 29 January 2015 (UTC)
thread_title:  Why was Code Section deleted? 

message: I'm considering adding some timing diagrams to this article to illustrate typical timing arcs, but since there is no standard, I fear that it would be too definite to be factual.  Would it be?
I'm considering the following arcs for the timing diagram.  What problems are there with these?  The way to read is:  [first in time] -> [second in time] [timing type].  I've made these arcs relative because of SPI variations.  For example, instead of writing "ss falling edge" I've written "ss enable" because enable can be either high or low.
For slave:
 [ss enable]          -> [sclk receive edge] [setup]
 [sclk receive edge]  -> [ss disable]        [hold]
 [mosi]               -> [sclk receive edge] [setup]
 [sclk receive edge]  -> [mosi]              [hold]
 [ss enable]          -> [miso]              [delay]
 [sclk transmit edge] -> [miso]              [delay]
For master:
 [ss enable]          -> [sclk receive edge] [delay]
 [receive edge]       -> [ss disable]        [delay]
 [miso]               -> [sclk receive edge] [setup]
 [sclk receive edge]  -> [miso]              [hold]
 [ss enable]          -> [mosi]              [delay]
 [sclk transmit edge] -> [mosi]              [delay]
Beeflo (talk) 15:12, 11 February 2015 (UTC)
thread_title:  How about a timing diagram? 

message: pdf document link 'SPI Block Guide V03.06' do not provide said document.  — Preceding unsigned comment added by 80.50.149.118 (talk) 10:28, 26 March 2016 (UTC)
replies: text: The entire internet suffers from link rot.  • Sbmeirow • Talk • 20:42, 26 March 2016 (UTC)
thread_title:  Reference broken 

message: I was reading Microsoft technical titled *HID over I2C*, which said:
    Today, the HID I²C driver targets SoC systems that support Simple Peripheral Bus (SPB) and GPIO. In the future, Microsoft may support this driver on non-SoC systems.
Of course I've heard of SPI, and I'm familiar with it, but this seems to reference something different (not sure) called **Simple Peripheral Bus**.    When I used that as a Wikipedia search, it got referred to the SPI page.   
Is this an indication that the Simple Peripheral Bus (SPB) is the same as Serial_Peripheral_Interface, or are the different?
If different, should we remove "bus" from the title of this article?  I usually see it referred to as SPI rather than SPIB.
Also if not, an article regarding Simple Peripheral Bus (SPB) seems appropriate.   Does anyone have any additional information?
--Burt Harris (talk) 20:26, 20 May 2018 (UTC)
thread_title:  SPI vs SPB? 

message: Anyone ever encounter these? It appears they are particular to ExpressIf ICs and correspond to SIO2 and SIO3 signals of QSPI, but I am not sure. I am curious what the HD and WP mean, but can't find anything anywhere! It would be nice to have those names included here, along with any other industry names for those lines.
--38.88.217.186 (talk) 22:54, 19 June 2019 (UTC)
thread_title:  SPIHD and SPIWP ??? 

message: This final section was surely added by an Intel marketing person: https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Intel_Enhanced_Serial_Peripheral_Interface_Bus. The whole page provides a good balance of vendor-specific implementation and the core general knowledge of SPI. However, getting to the bottom of the page the reader is met with a small wall of text that is really just pro-Intel and the details don't help the general knowledge of SPI at all. This section should likely be housed elsewhere (and probably already is), with a link to that source and some choice SPI-specific details included here.
--73.59.110.102 (talk) 05:49, 6 August 2020 (UTC)
replies: text: I agree.  The eSPI standard is sufficiently different to SPI to merit a new page with just a link from SPI. For example "1-bit, 2-bit, or 4-bit communications at speeds from 20 to 66 MHz", SPI is just a way to clock bits around, anything with this degree of formality is a totally  different thing needs a new page. Mtpaley (talk) 18:43, 6 August 2020 (UTC)
thread_title:  Intel Enhanced Serial Peripheral Interface Bus 

message: Much of this article reads more like a technical reference or guide than an encyclopedic article, and really could use a rewrite with these guidelines in mind. The code example in particular really doesn't belong. Lots of it could be very useful on Wikibooks, Wikisource, and Wikiversity though! Jonathan FarnhamJ 22:08, 2 March 2021 (UTC)
thread_title:  Reads like a technical guide 

message: I don't understand why this section has been added.  The article is about the SPI standard not types of flash storage.  The linked article seems to be implying that using SPI on flash is somehow new but it has been commonly used for decades and it is irrelevent for this article if it is NAND/NOR or something exotic. It even says that their product offers 10 year retention and so can be used for boot code, I don't know about you but knowing that the computer in my car/tv/whatever only has a 10 year life seems like a strange advert.
Why should this be kept? Mtpaley (talk) 10:15, 30 August 2021 (UTC)
thread_title:  SPI NAND 

message: In the Data transmission section, the second of these sentences is not always correct:
"On the clock edge, both master and slave shift out a bit and output it on the transmission line to the counterpart. On the next clock edge, at each receiver the bit is sampled from the transmission line and set as a new least-significant bit of the shift register.".
The last sentence seems to contradict these two in the Clock phase and polarity section:
"SPI master and slave devices may well sample data at different points in that half cycle.  This adds more flexibility to the communication channel between the master and slave.".
Confusion around this, including references to this article, has recently caused a few dozen engineer*hours at my day job.  As a first attempt at explaining the complexity, would it be OK to change the sentences in the Data transmission section to remove some of the the specific detail:
"In each clock cycle, one bit is shifted from the sender to the receiver on each data line."
And change the sentences in the Clock phase and polarity section to:
"Some SPI devices sample data at different points in the clock cycle.  For example, a SPI controller could sample incoming data immediately before it generates the same clock edge that will cause the peripheral device to output the next data.  This technique is commonly used when accessing SPI memory chips, to provide the peripheral with almost a full clock cycle to output data rather than only a half cycle."
--Ianr44 (talk) 09:55, 2 September 2021 (UTC)
thread_title:  Capture timing