Talk:Return-to-zero

message: I believe there are either two conventions for Return to Zero encoding or what is currently listed on the wiki page is not the correct implementation of RZ encoding.
In return-to-zero (RZ) encoding, a binary 1 is represented by a full power voltage in the first half of the bit time and zero voltage in the second half of the bit time. A binary 0 is represented by a zero voltage during the entire bit time. CMOS Circuits for Passive Wireless Microsystems By Fei Yuan (page 52)
http://books.google.com/books?id=rflX220f7R0C&lpg=PA53&ots=Va7kPmv20Z&dq=rz%20encoding&pg=PA53#v=onepage&q=rz%20encoding&f=false
In my understanding, RZ Encoding has two states, the zero voltage state and the "full power" (V+) voltage state.  
The encoding scheme that is currently described on the Wiki page has three voltage states, the zero voltage (middle state), the significant condition and the other(?) significant condition.
Gimpyestrada (talk) 19:08, 11 October 2011 (UTC)
thread_title:  Incorrect or Multiple Meanings of RZ Encoding 

message: The oldest data standards that RZ and NRZ come from considered how to encode marks, not the time between marks called spaces. They don’t contemplate bit clocks quite the same way as later standards. RZ simply means return to zero between marks. It’s what later authors call a binary data stream. it’s so simple it invites invented definitions.
This bowlderized RZ definition comes courtesy of post internet contributors. It’s an imaginative mashup of biphase aka Manchester encoding, the old +/- 15v RS-232 standard or the differential RS422/RS485 standards, and an old IBM bipolar line printer interface standard that solved a DC offset problem.
Manchester encoding is an inefficient use of channel capacity but encoding a 1 as 01 and a 0 as 10 puts a lot of edges in the data stream. There’s always a mid-bit edge The only challenge is bit boundary sync. A receiver finding an infinite sequence of encoded 0’s or 1’s in progress can’t determine which one. 
the imagined trinary FSK encoding is someone’s personal fantasy. It’s possible to view some of the adjacent channel interference reducing shaped modulations as n-ary, n odd FSK modulations.  it leads to a very low cost receiver that has a high bit error rate, but you can look at it that way.
The described three level signal encoding is not commonly used, and it never has been. The RS standards defined the band around 0v as an illegal or indeterminate state, as a practical matter a receiver had its hysteresis loop centered on 0v and the line receiver’s output was the last legal line state. As a practical matter everything since has done likewise albeit with clever uses of illegal both-high and both-low states for some of the differential serial busses.  
The only tri-level line standard I can recall was IBM’s AMI, Alternate Mark Inversion. It was used for  IBM main-frame to line printer interfaces in the 60’s because it can be DC blocked to avoid large neutral/ground shifts found in the data centers of the era. It reverses the polarity of alternate 1’s. I can’t recall if it was RLL or biphase to guarantee transitions. 
PolychromePlatypus (talk) 17:52, 16 March 2023 (UTC)
thread_title:  This RZ description is not the preferred form.