Talk:Pentium F00F bug

message: This entry would be greatly improved by a list of affected models like the list in the Pentium FDIV bug entry.
Alas, I haven't been able to find a reliable source listing which models are affected.  Some anonymous Usenet posts claim that AMD K5 and K6 processors are not affected but Cyrix (which ones?) are.
And yes, the title should be changed from F00f to F00F. Upper case representations of hexadecimal numbers are quite common; my perception is that F00F is more common than f00f. Guy Macon (talk) 19:28, 18 March 2007 (UTC)
thread_title:  Add list of affected models? 

message: IMHO there should be some information about the workaround in this article.  —Preceding unsigned comment added by 62.181.193.162 (talk) 08:38, 18 September 2007 (UTC)
replies: text: I don't think there are any workarounds other than using softfloat libraries (implementing the affected arithmetic operations with integer arithmetic). -- intgr [talk] 09:21, 18 September 2007 (UTC)
replies: text: I think you're confusing this (Pentium F00F bug) with the Pentium FDIV bug, there are workarounds for this one, eg  - taviso 03:17, 19 September 2007 (UTC)
replies: text: You're right, I was confusing it with the FDIV bug. :) -- intgr [talk] 07:27, 19 September 2007 (UTC)
thread_title:  Workaround 

message: I wanted to clean up the pronunciation, but can't tell if it's pronounced with the oo of foot or the oo of food. kwami (talk) 11:02, 15 December 2007 (UTC)
replies: text: It is not pronounced  · · · Omnissiahs hierophant (talk) 11:28, 18 August 2021 (UTC)
thread_title:  help with pronunciation 

message: Or does this sound like the automonapoea (SP?) "FOOF!"? Maiq the liar (talk) 18:02, 18 January 2008 (UTC)
thread_title:  Is it just me... 

message: The article states 'No Intel processors since the introduction of the Pentium Pro have been affected by the bug' - but the  Intel Quark SoC X1000 (intreduced with the galileo platform) is based on a intel 486/pentium hybrid, which states: 
 cat /proc/cpuinfo
 processor       : 0 
 vendor_id       : GenuineIntel
 cpu family      : 5
 model           : 9
 model name      : 05/09
 stepping        : 0
 cpu MHz         : 399.076
 cache size      : 0 KB
 fdiv_bug        : no
 hlt_bug         : no
 f00f_bug        : yes
So, we have more affected cpu's  — Preceding unsigned comment added by 46.228.92.142 (talk) 11:48, 29 August 2014 (UTC)
replies: text: Thanks, but to add this to the article we would need a reliable source supporting this claim. -- intgr [talk] 14:39, 29 August 2014 (UTC)
replies: text: German wiki cites heise: http://www.heise.de/developer/artikel/Intels-Einplatinen-Computer-Galileo-unter-der-Lupe-2252539.html and confirms it under Intel Quark page  — Preceding unsigned comment added by 85.221.130.92 (talk) 17:48, 29 August 2014 (UTC)
replies: text:  Heise cites Wikipedia which cites Heise? Not reputable. Reverted article. Has anyone actually *tested* this? Linux is detecting Quark as Pentium and then assuming Quark has the bug. See See also https://twitter.com/marcan42/status/526559512853889024.     — Preceding unsigned comment added by 60.242.88.97 (talk) 08:05, 27 October 2014 (UTC)
replies: text: I think Heise was linking to Wikipedia for an explanation about what the f00f bug is, not "citing Wikipedia" for the presence of the bug on Quark. The mention of Quark was added after the Heise article was published: . But you're probably right that there's not enough evidence that they tested it, so let's keep it out of the article. -- intgr [talk] 09:34, 27 October 2014 (UTC)
thread_title:  New CPU affected 

message: I have 2 minor & 1 major issue with the article, for which i'd like to receive some comments before attempting any corrections (which might be mistaken, afterall):
First minor issue is where it says that the relevant registers are R0 and R2 in more modern processors. Even in 64-bit architectures there are no such named registers. General purpose registers having numbers in their names are R8 thru R15 only. AFAIK, the text should state RAX and RDX, respectively, unless things have really been renamed this way in very recent hardware, for which reason i withhold editing for now.
Second minor issue is that, since the relevant instruction is cmpxchg8b, which operates on single bytes, the affected register should be AL, not AX, nor EAX, nor RAX (all of which are wider than one byte). I tried confirming this by disassembling the opcodes, but the only disassembler i have available now (objdump) just renders "(bad)", which is only natural, since this is an illegal instruction afterall.
Then the major issue is where it says in the article (unsourced, as far as i can tell) that there were workarounds for this problem issued for operating systems back then. I can't see how this could be, since it is a purely hardware issue which does not depend on privileges or particular CPU configurations; ie, it is unpreventable (unless you stop running native code altogether and emulate everything, which is obviously unfeasible). If there really were workarounds (even partial ones) that could be deployed in software, this would be of immense interest. Anyone has any clue either way?  — Preceding unsigned comment added by 79.168.78.24 (talk) 03:27, 11 April 2018 (UTC)
replies: text: OK. I really need to go through sources more thoroughly in advance. Turns out the Dr.Dobbs reference in the text contained the official workarounds from Intel, plus two others of his own devising, all of which are very interesting as they elucidate the deepest quirks of microprocessors in action. I'll try to summarise them for the article. My second minor issue above was in fact my mistake, i don't know where i got the idea that the cmpxchg8b instruction operated on single bytes, so, nevermind. As for the first minor issue, i'm going for the correction.  — Preceding unsigned comment added by 79.168.78.24 (talk) 03:54, 11 April 2018 (UTC)
thread_title:  Three Remarks