Talk:Synchronous dynamic random-access memory

message: ===Untitled===
This was originally redirecting to Dynamic random access memory (where the SDRAM is from), but that only has a link to SDR SDRAM, which discusses SDRAM and that SDR SDRAM is considered "normal" SDRAM. That is why I thought the redirect should change. Matejhowell 13:55, 20 January 2006 (UTC)
replies: text: was moved to Parallel ATA on 6 April 2009. – wbm1058 (talk) 18:40, 12 August 2020 (UTC)
thread_title:  Redirect where? 

message: This was originally redirecting to Dynamic random access memory (where the SDRAM is from), but that only has a link to SDR SDRAM, which discusses SDRAM and that SDR SDRAM is considered "normal" SDRAM. That is why I thought the redirect should change. Matejhowell 13:55, 20 January 2006 (UTC)
thread_title: Untitled

message: I've moved the contents of SDR SDRAM to this page and will shortly move DDR SDRAM here as well.  There are not nearly enough major differences (they amount merely to timing issues) between the two common forms of SDRAM to merit separate articles.  What's more "SDR SDRAM" is an ugly backronym and is bad practice to use anyway (just as the article on ATA isn't named "PATA"). -- uberpenguin @ 2006-04-29 03:27Z
:  was moved to Parallel ATA on 6 April 2009. – wbm1058 (talk) 18:40, 12 August 2020 (UTC)
thread_title:  Move/redirect 

message: Is ddr the same or different from sdram?
The last sentence could be clearer.
68.16.132.212 21:24, 2 November 2006 (UTC)
replies: text: Same thing; clocked on two edges instead of one. -- mattb @ 2006-11-02T23:25Z
I've read this article several times now, and being a fairly educated person of average intelligence, I'm still just guessing that the frequency of SDRAM means the number of SDRAM cycles per system clock cycle. For example, if the frequency is "100 MHz" this means that the SDRAM has 100 MHz per system clock cycle, but I don't really know if this is correct. The point is that this article does not explain explicitly to my understanding one of the most basic defining characteristis of the subject, unless it is buried somewhere in the article and I missed it. I thought sure I would see it in the the "timing" topic, but, alas, not really. Could someone please address the distinguishing feature of this stuff?  — Preceding unsigned comment added by Stalkedinpink (talk • contribs) 16:49, 15 March 2011 (UTC)
thread_title:  ddr and sdram 

message: The 1st paragraph indicates that asynchronous operated "as quickly as possible" because it doesn't have to wait for a clock signal.  I could be wrong here (it's been 15 years since then when I jumped to the solar PV industry), but when I was a DRAM integration/yield engineer for Micron while we were migrating from asynchronous to synchronous I understood the asynchronous problem differently.
As I understood it, since asynchronous transistors were not tied to a clock then as data traveled between the data-pins and the cell (as it travels through the periphery) each periphery transistor's latching was controlled by the transistor in front of it, introducing nested propagation delays.
Am I wrong?  Wasn't synchronous intended to reduce propagation delays caused by this nested-transistor-operation in the periphery?  If so then it seems this first paragraph should be changed from:
Traditionally, dynamic random access memory (DRAM) has an asynchronous interface which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus.
	
to:
Traditionally, dynamic random access memory (DRAM) has an asynchronous interface which means that data propagated through nested gates (transistors) to get the memory cell as quickly as the gates could propagate the data. SDRAM has a synchronous interface, meaning that these gates are synchronized with computer's system bus clock signal, allowing timing optimization to reduce those propagation delays.
Davea0511 (talk) 18:04, 5 September 2009 (UTC)
replies: text: The argument "we had to add some waiting to speed up the interface that operates as quickly as possible" is opposite to commons sense and destroys it. Yet, it is crazy funny therefore and better fits the happy decadence postmodern reality that freedom and market manipulators create around us. You are too late. Sorry. --Javalenok (talk) 15:53, 24 June 2011 (UTC)
thread_title:  1st paragraph: asynchronous operated "as quickly as possible"?  What about propagating delays? 

message: Is it necessary to explain what pipelining is in this article? Enum (talk) 23:39, 14 March 2010 (UTC)
replies: text: It should at least be removed from the summary. It seems to come out of nowhere.  -Zoon van Zaal (talk) 00:27, 8 April 2013 (UTC)
thread_title:  Pipelining 

message: I propose that DDR4 SDRAM be merged into this article. It doesn't have much worth keeping, but looks like it has some newer info about clockspeeds and production process. We did this two years ago with an AfD, but now the article's back and the same arguments apply. I don't think we need a separate DDR4 article until the spec hits 1.0 or someone writes a really awesome article about finalized features or something. Alereon (talk) 01:01, 25 November 2010 (UTC)
replies: text: Okay, I went ahead and merged the only recent source and redirected DDR4 here. Alereon (talk) 15:14, 3 January 2011 (UTC)
thread_title:  Merger Proposal for DDR4 

message: Since the above merger (which I agreed with), DDR4 has developed to the point that it can clearly sustain its own article. While JEDEC hasn't finalized the specification, there is more to say than comfortably fits into this umbrella article and enough to make a satisfactory article in its own right.
See DDR4 SDRAM.
Important - this article is out of date on DDR4. As best I can see, the new article is accurate so far, so this article's mention of DDR4 should be reviewed and brought into line with it. FT2 (Talk | email) 00:47, 26 April 2011 (UTC)
thread_title:  Unmerger of DDR4 

message: In the paragraph under the SDR-SDRAM header it says;
"Typical SDR SDRAM clock rates are 66, 100, and 133 MHz (periods of 15, 10, and 7.5 ns). Clock rates up to 150 MHz were available for performance enthusiasts."
This is somewhat misleading. Yes, memory modules for the PC were released in 150MHz variants. But! In late 2000/2001 GeForceMX videocards contained much faster SDR-SDRAM memory; 3.3ns which corresponds to 300MHz. Double that of the chips on modules for regular use.
See this post on a forum for more info; http://www.falconfly.de/cgi-bin/yabb2/YaBB.pl?num=1156155727
NitroX infinity (talk) 09:44, 6 September 2011 (UTC)
thread_title:  Somewhat misleading part 

message: Article currently states: "Performance up to DDR3-2200 (PC3 17600 modules) are available for a price." However, the e-tailer Newegg has a listing for DDR3-2800 http://www.newegg.com/Product/Product.aspx?Item=9SIA0ST09M2930 and also offers: 
    DDR3 2200 (PC3 17600) (1)
    DDR3 2400 (PC3 19200) (22)
    DDR3 2600 (PC3 20800) (4)
    DDR3 2666 (PC3 21300) (4)
    DDR3 2800 (PC3 22400) (1)
In addition, some motherboards (unsure of source) claim to support up to DDR3-3000.
50.75.41.93 (talk) 16:39, 10 June 2012 (UTC)
thread_title:  Modification required for DDR3 Max MT/s Availability 

message: I think this article is outdated, just one look at the ddr types section and you will understand that.  — Preceding unsigned comment added by 41.46.94.48 (talk) 10:24, 8 January 2014 (UTC)
thread_title:  This article hasn't been updated in a long time 

message: I believe that the procedures to read and write along with other technical details belong in a technical manual or datasheet and not in Wikipedia. It would be more useful to cite the main differences with standard SDRAM, the purported advantages over the latter, and the reasons why is it a failed successor. Agent Fog (talk) 21:19, 19 September 2014 (UTC)
thread_title:  Too technical section: Virtual Channel Memory (VCM) SDRAM 

message: One can read in this paragraph that " (one per row, 4096 in the example we have been using) ", I don't understand where that number comes from. I think it actually should be 2048, because we have 8192 rows and 4 banks, so if my understanding is good, 4 rows can be refreshed simultaneously during each auto-refresh cycle, ergo 8192/4=2048 commands are needed (adding this simple calculation improves readability in my opinion). As a side note, can someone confirm that the auto-refresh cycle duration is tRRC? 78.193.132.125 (talk) 21:39, 4 February 2015 (UTC)
thread_title:  About auto-refresh 

message: To be frank, I had to learn this the hard way. I bought a mainboard on the flea market some time ago, which was dirt hell but cheap as hell as well ;) I managed to get the board cleaned and it would do perfectly as a file server in Linux. Now I tried to find my old DDR-SDRAM and ... epic fail. "My" board requires 3.3v SDRAM that has one additional notch (not mentioned in the article!!) and thus won't accept any 2.5v DDR-SDRAM. Tried it multiple times (not violently mind you!), back and forth until I discovered that one notch on my SDRAM while the slot requires RAM with two notches. -andy 2.242.214.197 (talk) 15:11, 14 March 2015 (UTC)
replies: text: Have you checked the DIMM article?  It clearly describes two notches on 168-pin SDRAM memory modules. — Dsimic (talk | contribs) 07:19, 25 March 2015 (UTC)
thread_title:  SDR SDRAM (3.3v) has one additional notch! 

message: The lede as of 2015-12-25 () states: "Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus." It is fundamentally wrong to portray SDRAM as being synchronous to a "system bus". There is no intrinsic reason why SDRAM has to be synchronous to the system bus, or for SDRAM to be used in an application where there is a system bus. SDRAM is simply DRAM with a synchronous interface (though this article is slanted towards SDRAM as a standard from JEDEC, which also defines an internal DRAM organization, rather than as a type of DRAM).
Any reputable reference or textbook can support this claim, one which I have ready access to (Memory Systems: Cache, Memory, Disk by Bruce Jacob et al.) states on p. 332: "The primary difference between SDRAMs and earlier asynchronous DRAMs is the presence in the system of a clock signal against which all actions (command and data transmissions) are timed. Whereas asynchronous DRAMs use the RAS and CAS signals as strobes—that is, the strobes directly cause the DRAM to sample addresses and/or data off the bus—SDRAMs instead use the clock as a strobe, and the RAS and CAS signals are simple commands that are themselves sampled off the bus in time with the clock strobe." This is more or less how every university textbook or professional reference concerned with digital electronics or computer organization would describe SDRAM.
The current lead sentence is also PC-centric, even though SDRAM technology was not developed specifically for PCs, even if they are widely used by them. For instance, an embedded system with a high-end embedded microprocessor may not have a system bus, containing all required peripherals on-chip, and directly interfacing to one 32-bit SDRAM IC via a memory bus to its on-chip memory controller. Another example would be an FPGA system where the user has interfaced an SDRAM IC to the programmable general-purpose I/O pins, and data movement between the FPGA and SDRAM is entirely controlled by the user-implemented application-specific custom logic in the FPGA. These are just two examples of where, contrary to the current revision, where SDRAM could be used in a system lacking a system bus, and in a system which does not resemble a programmable general-purpose computer.
The new lead section should accurately define the subject: "Synchronous dynamic random-access memory (SDRAM) is any dynamic random-access memory (DRAM) where the operation of its interface is coordinated by an external clock signal."
The reason why the proposed lead states that it is the operation of the interface is coordinated by an external clock signal is that SDRAMs have an asynchronous core. The pre-charge and sense amplification phases, for instance, are asynchronous, and IIRC, not pipelined. It is the mere latching of commands, addresses, and data (and transmission of data in the case of reads) that is synchronous. The mention that the coordination of the operation of the external interface by an external clock is to distinguish it from the internally generated clock signals that are present in the cores of asynchronous DRAMs, which are still present in modern SDRAMs.
The lead section should also defer discussion of interleaving and pipelining until later. Strictly, interleaving and pipelining as described by the lead section is specific to the JEDEC standards on SDRAM. Synchronous DRAMs in the past have not included these features, thus the propery of synchronous operation is completely sperate of JEDEC's SDRAM organization. The final sentence in the current revision, "SDRAM is widely used in computers; after the original SDRAM, further generations of double data rate RAM have entered the mass market DDR (also known as DDR1), DDR2, DDR3 and DDR4, with the latest generation (DDR4) released in second half of 2014.", is also PC-centric in that it ignores the wide use of SDRAM in any digital electronic system where the capacity and performance of SDRAMs are required. This could be improved by simply replacing the mention of computres with digital electronics, but it would have to cite a reliable source, and I don't have one readily available.
Are there any comments regarding the lead section? AZ1199 (talk) 11:24, 2 January 2016 (UTC)
thread_title:  Inaccurate lead section 

message: what year did pc66 ram or any kind of sdr ram hit the market?  — Preceding unsigned comment added by 73.211.117.192 (talk) 22:54, 15 December 2017 (UTC)
thread_title:  When did pc66 ram hit the market 

message: :Feel free to state your position on the renaming proposal by beginning a new line in this section with *Support or *Oppose, then sign your comment with ~~~~. Since polling is not a substitute for discussion, please explain your reasons, taking into account Wikipedia's policy on article titles.
*Support first, oppose others Agree with Dekimasu. This shouldn't be done grouped, especially since you aren't proposing what to do with the occupied targets like DDR.  To avoid an inconsistent result for the DDR/GDDR pages, better to leave them in place. -- Netoholic @  21:49, 14 February 2019 (UTC)
replies: text:   ~ Arkhandar (message me) 20:57, 15 February 2019 (UTC)
replies: text: @ ... but I am.Djm-leighpark (talk) 21:17, 15 February 2019 (UTC)
replies: text:  I'll give you a cookie for that if you want to ~ Arkhandar (message me) 21:20, 15 February 2019 (UTC)
thread_title: Survey

message: Yes, it makes sense to split the material specific to the original "SDRAM" generation, as opposed to information common to the entire family of standards, to , and then merge PC66, PC100, and PC133 into the newly split . – wbm1058 (talk) 20:42, 27 January 2020 (UTC)
replies: text:  that looks fine to me too. I had a look at doing this myself, but had trouble separating the SDR-SDRAM from the SDRAM material; I wonder if you, or someone closer to this field than me, might given it a go. Klbrain (talk) 20:33, 11 August 2020 (UTC)
thread_title:  Proposed merge & split 

message: Hi All - Wondering: The several sections in the article, e.g. DDR2, DDR3, DDR4, etc; Why do none of these sections make mention of connectors' numbers of pins? e.g. various DDR(X) SDRAM form-factors might be 184 pins, 240 pin (1.5V or 1.8V, two different ones at 240 pins), and/or 288pins.. Info needs to be added, updated? Thanks! -From Peter {a.k.a. Vid2vid (talk | contribs)} 04:36, 25 June 2020 (UTC)
thread_title:  DDR(X) SDRAM, Connectors' numbers of Pins?? 

message: WP:COMPUNITS is not a licence to introduce ambiguity in any article. I have restored an earlier, stable version of the article so we can discuss the disputed edits since 20 April. Relevant statements include:
* Do not assume that the binary or decimal meaning of prefixes will be obvious to everyone. 
* Disambiguation should be shown in bytes or bits, with clear indication of whether in binary or decimal base. There is no preference in the way to indicate the number of bytes and bits, but the notation style should be consistent within an article. 
* The IEC prefixes kibi- (symbol Ki), mebi- (Mi), gibi- (Gi), etc., are generally not to be used
The bottom line is that disambiguation is needed. The only question is how. It's hard to satisfy all three requirements, suggesting WP:IAR as the only practical guideline, and disambiguation using the most practical method to hand. What do others think? Dondervogel 2 (talk) 16:46, 24 April 2021 (UTC)
replies: text: Agree – seconding that in full. Ambiguous units don't help anyone and explanations for readers unfamiliar with binary IEC prefixes are available on the linked page. --Zac67 (talk) 09:57, 25 April 2021 (UTC)

text: You keep trying to have these whack-a-mole discussions on far-off pages away from WT:MOSNUM. The correct location for this discussion is WT:MOSNUM. Stop starting forest fires and start the discussion where it makes sense. You're not going to change the wording of WP:COMPUNITS here. —Locke Cole • t • c 16:48, 25 April 2021 (UTC)
thread_title:  Disputed edits 

message: Hello, I was wonder why GDDR was under the 'Failed Successor.' It doesn't seems like it has failed as it became the standard RAM for all graphics cards for the last decades beside the brief attempt of HBM in consumer cards in the mid 2010s 61.68.245.48 (talk) 23:13, 7 January 2022 (UTC)
thread_title:  GDDR failed?