Talk:Front-side bus

message: —Preceding unsigned comment added by 74.128.236.56 (talk) 23:05, 11 January 2010 (UTC)
replies: text: The above signed fragment due to 74.128.236.56 removing their own comment  (2010 Jan 11; 22:06 UTC) that had been signed by SineBot.— al-Shimoni (talk) 02:07, 2 August 2020 (UTC)
thread_title: 74.128.236.56 removed their comment

message: Please do not add in processors that do not use a Front Side Bus, they are not relavent to the FSB chart.  —Preceding unsigned comment added by 69.248.120.203 (talk) 14:21, 9 May 2010 (UTC)
thread_title:  Non-FSB CPUs 

message: I just posted a discussion over on the Intel Core 2 discussion page about this -- why are we listing front side buses in megatransfers per second (MT/s)?  This article states (incorrectly, I might add) that, quote; "Many manufacturers today publish the speed of the FSB in megatransfers per second (MT/s), not the FSB clock frequency in megahertz (MHz)."  No manufacturer lists their front side bus in MT/s!  They may list the speed of their newfangled, high speed, point-to-point interconnects as MT/s... but no one measures their FSB in MT/s!  Look at any retail website selling these chips, or even retail websites selling complete systems.  Why not take it straight from the horse's mouth, from Intel's on-site documents ?
A Pickle (talk) 04:35, 29 June 2009 (UTC)
replies: text: Becaus ethey use fake MHz, they do not use the MHz the Bus runs at but instead the data rate (bus clock x data blocks transferred per clock). In effect they use MT/s but state is as MHz because it sounds and sells better to those who do not know much about computers. --Denniss (talk) 17:53, 29 June 2009 (UTC)
thread_title:  MT/s vs MHz:  The debate rages on, but why? 

message: having L2 cache on the processor die itself, this
It will be better if it changes to like this :
having L2 cache on the die of the processor itself, this  —Preceding unsigned comment added by 60.50.228.27 (talk) 02:12, 23 June 2008 (UTC)
thread_title:  Yes 

message: having L2 cache on the processor die itself, this
processor die? I'm no expert on buses, but either this was not intentional or this para graph needs changing.
:No, it's not an error- there is, as far as I know, actually a thing called the processor die.--Airplaneman (talk) 19:58, 29 May 2009 (UTC)
thread_title:  Gramatical error? 

message: There seem to be quite a few FSB800 Pentiums flying around these days: the article is either outdated or needs an explanation. --Tom Edwards 20:33, 17 July 2005 (UTC)
thread_title:  FSB chart 

message: Weird, my PC with an Athlon XP processor only supports FSB 100/133/166 o.Ô
:I have an Athlon XP 2600, which only goes upto 166mhz front side bus. This is thus 333MHz when doubled. I just recently put new RAM in the machine that is DDR-400 (400MHz memory speed when doubled, as per usual DDR semantics). My BIOS supports asynchronous bus speeds for FSB and RAM. This article seems to suggest that I should underclock my RAM to 333MHz to match the FSB of the CPU, without being explicit. What's the proper thing to do in my case, and can the article be expanded on to eliminate this ambiguity? 86.139.204.252 21:03, 3 May 2006 (UTC)
replies: text: Your XP runs with 166 MHz FSB and your memory with max 200 MHz. IF you have an nForce2 system then use both with 166 MHz unless you want to OC your CPU, using different speed on FSB and memory slows own your system. Most other Sockt-A system should run fine with memory clocked higher than FSB. --Denniss 22:59, 3 May 2006 (UTC)
thread_title:  Athlon XP 

message: wiki seaching fsb didnt point to this article
there are other uses to FSB. --202.71.240.18 07:11, 13 July 2006 (UTC)
thread_title:  abbreviation 

message: This is a really nicely formatted table, but does it really add to the article on FSB?  Is it too Intel-centric?  I removed it but copied it here because it has such nice format.
:Well, if this term is coined and generally used by Intel, it seems not surprising that it is Intel centric. Perhaps we need to clarify if it had uses outside of Intel and clone makers. W Nowicki (talk) 19:49, 27 May 2011 (UTC)
thread_title:  removed 

message: Why is it too intel-centric, when AMD products had been added into discussion?  —Preceding unsigned comment added by 60.50.228.27 (talk) 02:14, 23 June 2008 (UTC)
thread_title:  re:removed 

message: Processor Class	FSB Frequency	FSB Type	Theoretical Bandwidth</b></td></tr>
Pentium II66/100 MHzGTL+533/800 MB/s
Pentium III100/133 MHzGTL+800/1066 MB/s
Pentium 4*100/133/200 MHzAGTL+3200/4266/6400 MB/s
Pentium M*100/133 MHzAGTL+3200/4266 MB/s
Pentium D*133/200 MHzAGTL+4266/6400 MB/s
Pentium 4 EE*200/266 MHzAGTL+6400/8533 MB/s
Intel Core*133/166 MHzAGTL+4266/5333 MB/s
Intel Core 2*166/200/266 MHzAGTL+5333/6400/8533 MB/s
Xeon - P6 core100/133 MHzGTL+800/1066 MB/s
Xeon* - Netburst core100/133/166/200/266 MHzAGTL+3200/4266/5333/6400/8533 MB/s
Xeon* - Woodcrest core266/333 MHzAGTL+(with Dual Independent Buses)17066/21333 MB/s
Athlon/Duron**100/133 MHzEV61600/2133 MB/s
Athlon XP/Sempron**133/166/200 MHzEV62133/2666/3200 MB/s
Athlon 64/X2/Opteron***600/800/1000 MHzHypertransport7500/12800/14400 MB/s
PowerPC 970****450/500/625 MHzElastic7200/8000/10000 MB/s
Notes:* - Pentium 4, Pentium M, Pentium D, Pentium EE, Xeon, Intel Core, and Intel Core 2  processors use a front side bus that transfers data four times per cycle** - Athlon and Athlon XP processors use a front side bus that transfers data twice per cycle (Double data rate)*** - Athlon 64, FX, and Opteron processors have a memory controller on the CPU die, which replaces the traditional FSB.  The bus specifications given here are for the HyperTransport link and memory bandwidth.**** - PowerPC 970 processors use a front side bus that transfers data twice per cycle (Double data rate)
:If the PowerPC 970 has a FSB DDR, how does it get higher transfer speeds at a lower clock than other DDR FSBs? Or maybe I'm confused about that. - MSTCrow 16:36, 29 October 2006 (UTC)
replies: text: I think the speed entries for it are wrong.  According to PowerPC 970, the FSB runs at half the clock speed, and clock speed varies from 1.6GHz to 2GHz, so the FSB should be 800-1000MHz, not 450-625MHz as is in the table.  One of these is wrong, and as you point out a discrepancy in the table data, I'm inclined to believe it's the table. JulesH 09:43, 9 December 2006 (UTC)
thread_title: Some sample FSB frequencies and bandwidths

message: How do I include serial into the infobox, as Hypertransport can be serial in nature?  Also, I think the FSB can be a minimum of 2 or 4 bits in width.  Thanks. - MSTCrow 16:34, 29 October 2006 (UTC)
thread_title:  Serial FSB 

message: Near the end of the article, under "Overclocking," there is a sentence that reads: "Most motherboards allow the user to manually set the clock multiplier and FSB settings by changing jumpers or BIOS settings."
Where is the source for this?  The last time I checked, most PCs were bought pre-assembled and preloaded with software, from companies such as Dell, HP, eMachines, etc.  The majority of these PCs and motherboards within DO NOT allow you to change the FSB, much less multiplier.  Perhaps a change is needed?  The only motherboards that enable one to change the FSB and multiplier settings are chips purchased for custom-built computers, which represent a minority in the PC world.  Thoughts?  Opinions? -- Punchinelli 19:37, 2 November 2006 (UTC)
thread_title:  "Most motherboards allow overclocking?" 

message: That article is not much more than a sentence, I do not believe that it would really help unless someone disagrees with me.   VentusIgnis 13:18, 4 March 2007 (UTC)
thread_title:  Webopedia? 

message: Frontside - please check any dictionary to see that there is no such word in English. It is "Front side bus". --Kubanczyk 09:10, 24 September 2007 (UTC)
replies: text: Agreed. Also see the requested move below back to the pre-hyphenated spelling to match sources. W Nowicki (talk) 18:14, 27 May 2011 (UTC)
thread_title:  "Frontside" versus "Front side" 

message: The MT/s is affected by how many ticks are performed for each mhz, so if a motherboard has a 266MHz FSB and performs 4 transfers per clock tick, it has a total data transfer rate of 1066 MT/s. That is what the manufactures give as the speed of the FSB. Intel calls this technique which has 4 ticks per cycle Quad Pumping.
266 * 4 = 1064, not 1066. Should that be 266.5MHz, or is the 1066 MT/s wrong?  —Preceding unsigned comment added by 59.167.247.10 (talk) 05:48, 10 December 2007 (UTC)
thread_title:  Shonky math, or missing precision? 

message: It seems like this article is missing something. In the "pros and cons" section, it talks about the FSB like there are alternatives to it, but in the article above that, it talks as if there isn't any other way for the memory/system components/northbridge to communicate with the processor. This definitely needs to be fixed, because this reads sort of like a half-article right now. Like a lot of stuff was cut out of the article that made it make sense at some point in the past. (Some of which seems to be here on the talk page.) RobertM525 (talk) 01:40, 15 December 2007 (UTC)
replies: text: That entire section needs rewriting and sourcing as it currently reads like a personal analysis. The section should be titled something like "Criticism" or "Obsolescence". With regard to AMD specifically, the alternative being implied is HyperTransport. Ham Pastrami (talk) 17:17, 15 December 2007 (UTC)
thread_title:  Missing pieces 

message: I haven't found much in the way of a formal definition of "system bus".  I *think* that "system bus" is the same as "fsb", but I'm not sure.  Can anyone address this?--75.152.173.147 (talk) 18:50, 23 September 2008 (UTC)
replies: text: They are pretty much the same. Technically, "FSB" should be a subsection in an article titled "system bus", as "system bus" is the generic term and "FSB" is Intel terminology. Rilak (talk) 08:34, 24 September 2008 (UTC)
replies: text:  I've seen the term "PSB" (processor side bus) sporadically around the internet, with inconsistent definitions. What is the difference, if any, between "PSB" and "FSB"?132.38.190.10 (talk) 19:30, 29 July 2009 (UTC)

text: Well it has now been about two years and this needs to be revisited again. Related to the above discussion about being "Intel centric", adding AMD info that is Intel compatible is only one small aspect of the issue. Computers had system busses for decades before the personal computer. So I  propose to develope the system bus article into one about the generic concept and keep this one specific to the Intel implementation of this concept. W Nowicki (talk) 17:43, 18 May 2011 (UTC)
thread_title:  System Bus 

message: With 2009's processors such as AMD Athlon II/Phenom II and Intel's Nehalem microarchitecture, the northbridge no longer contains the memory controller, this function has moved into the CPU package.   This substantially changes the character of the front-side bus in terms of system performance.  Perhaps this article should be updated to reflect this. See Intel X58 for an example of this sort of architecture.
Burt Harris (talk) 17:41, 4 November 2009 (UTC)
thread_title:  Integrated memory controllers change the FSB story. 

message: Something's very wrong with the "Transfer rates" table. I have a Core 2 Duo CPU here, it has an FSB of 800MHz (or MT/s), the table says 10 times more or so..  —Preceding unsigned comment added by 85.249.223.23 (talk) 00:40, 16 January 2010 (UTC)
thread_title:  Transfer rates 

message: If the front side bus is "the bus that carries data between the CPU and the northbridge", and it is "an aging technology" - this would imply that in newer systems no data is being carried between the CPU and the northbridge. I can't really imagine that to be true. So either the definition is incomplete - the front side bus is one specific method of carrying that data, and then it should be stated which method; or something else is wrong. -- 92.229.92.20 (talk) 21:43, 27 April 2010 (UTC)
replies: text: The northbridge is the interface to memory; newer CPUs containing HyperTransport or QPI connections have their own memory controller on-die, thus making the northbridge itself obsolete. So in newer systems, the northbridge is inside the CPU and there is no FSB between them anymore. So the definition stated is actually correct. --141.44.162.92 (talk) 11:28, 9 June 2010 (UTC)
thread_title:  Ok, this doesn't make sense. 

message: It looks like User:Glrx reverted the proposed compromise again without discussion. To recap:
I was looking at improving this article (which was totally unsourced back in May), and noticed that reliable sources were inconsistent with their punctuation and capitalization of the term. Since the move had been done without any discussion, I started one on May 27. The discussion indicated that both "Front Side Bus" and "front-side bus" are used in sources, but the latter is generally more correct English usage.  I proposed a compromise of keeping the title but explaining the history of the term as being coined by Intel since I did not have strong feelings either way. We do this kind of thing all the time in biography articles: when more than one name is used, explain the history with sources briefly but otherwise use a name consistently. It is even an issue with technology history terms such as stored-program computer or Von Neumann architecture which change through time.
The move was closed with "no consensus" on June 11. In the meanwhile User:Dicklyon and I made some improvements (I hope!) to the article and added some citations and a diagram. I proposed again my compromise on this talk page on June 12, and added it since nobody objected. The next morning Glrx reverted the cited statement, with the summary "hypen usage is not history; article is not about WP". Could a third party please read the source ftp://download.intel.com/design/intarch/PAPERS/321087.pdf and see if I am imagining it? Read page 6, 9 or 10 for example "The name front side bus, came about when the original L2 cache was added to the CPUs." So that source did seem to me to be relevant to its history, being the closest to an "official" definition of the term.  (Although this 2009 document does use lower case in the body, upper case in other places; eventually I was going to add some other sources from earlier periods but they are harder to get. It might be only capital letters when intended as a proper name. see http://www.intel.com/technology/platforms/quickassist/index.htm and http://download.intel.com/support/processors/xeon/sb/25213506.pdf  ) 
I waited more than a day to see if any explanation would be added here. None was. Then on June 14 I added an explicit call for any better wording here, and added another attempt to the article without the self-referential language. I also included another source to an Intel document. I replaced some inline links with full live citations, and fixed some wording that had been discussed on this talk page. Within a few hours, again without any discussion here, Glrx reverted, including removing a citation to an Intel document (which luckily Anomiebot rescued). Glrx then added a template to my talk page warning that I could be banned for making "more than three reversions on a single page within a 24-hour period" because I was Wikipedia:Edit warring. However, that guideline clearly states that edit wars are when editors are not "trying to resolve the disagreement by discussion". It also says: "avoid relying solely on edit summaries and discuss the matter on the article's talk page." Could I have a third opinion on if I was trying in good faith to resolve by discussion? Also who was doing the reverting, and who was doing constructive edits that made the article agree with reliable sources? The edit summary on the revert was "article not moved; revert WP:POINTmaking; no need to explain punctuation". That guideline states it should be only invoked for disruptive edits. Is is disruptive to make article information consistent with sources? Or is removing well-cited content disruptive? Not even sure what "point" it was supposed to be making. It was just trying to add accurate verifiable content based on the discussion here. Certainly technical information should be the major content to this article, but one short sentence describing the evolution of the term from a proprietary proper noun to a generic term might be interesting to more general readers. 
That  guideline says "If direct discussion fails to resolve a problem, look into dispute resolution." And that  suggestion seems reasonable. I would appreciate help to get this (I thought minor) issue behind us and move on to more improvements to content. W Nowicki (talk) 18:28, 15 June 2011 (UTC)
replies: text: Oppose discussing hypenation or capitalization in the main article. Earlier, you proposed moving the article to the unhypenated name. There was no consensus for that move. You voiced your continued disagreement with not moving the article in the then-closed section. The material you added to the main article was more about the punctuation rather than the origin of the name. My edit summaries were that the article should not cover a minor matter such as WP's choice about punctuation. What significance is there in the loss of the hypen? Why would somebody who reads the article care? Your addition did, however, elevate an issue about which you are both interested (proposing the move) and unhappy (commenting after move did not achieve consensus). Apparently you also want to add material about capitalizing the term. If you can gain consensus, then you can the material. -- Glrx (talk) 19:22, 15 June 2011 (UTC)

text: I agree with Glrx.  Almost any multi-word technical term can be commonly found mis-punctuated and/or in title case in a number of sources, especially when it's being promoted by its originator or used to define an acronym.  In WP, we don't do it that way.  It's really not worth commenting on in an article on the topic.  Dicklyon (talk) 19:43, 15 June 2011 (UTC)
thread_title:  Another revert? 

message: After looking for information and to learn about FSB speeds, I came across this page. It took me some time to realize that the page wasn't outdated. The first thing that gets my attentions are tables and graphics, so when looking at the Intel table I just saw values up to 400 MHz, so therefore I was convinced that this information was quite old. After a while I finally realized that the values in the FSB Clock column is not the same as the FSB Speed used "normally". In this case I was looking at CPU and memory for some older Dell servers. My suggestion to clarify this is to add a column to the tables with the FSB speeds labeled "FSB Speed (MT/s)", but with MHz used in the cells. Dell mentions this as "Front-side bus (external) speed" (see example here).  Any objections? /PatrikN (talk) 22:27, 24 November 2012 (UTC)
thread_title:  Add FSB Speed to tables? 

message: The name, Front Side Bus (FSB), is essentially neutral. If a bus is able to connect CPU onto the mainboard, it should be called a Front Side Bus, no matter whether there would be a centric bridge chip (North Bridge) serving for it. Contrast to it, if a bus redirect its connection back its own physical package without indirectly extending out, it could be called a Back Side Bus (BSB), without having to connecting cache related devices. This concept should come with time, as technologies advancing... GoldenQR (talk) 22:18, 4 September 2015 (UTC)
thread_title:  The Concept of Front Side Bus Should Come with Time 

message: Please update link of 2nd reference of "EV6" text to "EV6" - its current link is stale. The first link to "Athlon" page is valid if indirect.
Typo369 (talk) 09:20, 12 February 2016 (UTC)
replies: text: Done EvergreenFir (talk) Please  18:47, 12 February 2016 (UTC)
thread_title:  Semi-protected edit request on 12 February 2016 

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