| {"bug_id": "rtl_001", "bug_type": "LATCH_INFERRED", "severity": "WARNING", "buggy_snippet": "always @(*) begin\n if (sel == 2'b00) out = a;\n else if (sel == 2'b01) out = b;\nend", "fixed_snippet": "always @(*) begin\n case (sel)\n 2'b00: out = a;\n 2'b01: out = b;\n default: out = '0;\n endcase\nend", "description": "Incomplete if-else in combinational always block infers latch on out", "fix_patch": "Replace if-else with case statement and add default branch", "verilog_ref": "mux.v:12", "tool": "OpenROAD"} |
| {"bug_id": "rtl_002", "bug_type": "MULTIDRIVEN_NET", "severity": "WARNING", "buggy_snippet": "assign net_reset_sync = rst_gen_out;\nassign net_reset_sync = por_cell_rst;", "fixed_snippet": "assign net_reset_sync = rst_gen_out | por_cell_rst;", "description": "Two concurrent assign statements drive the same net causing contention", "fix_patch": "Merge drivers using OR gate into single assign statement", "verilog_ref": "reset_ctrl.v:15", "tool": "OpenROAD"} |
| {"bug_id": "rtl_003", "bug_type": "TIMING_VIOLATION", "severity": "ERROR", "buggy_snippet": "always @(posedge clk) begin\n sum <= a + b + c + d + e + f;\nend", "fixed_snippet": "always @(posedge clk) begin\n stage1 <= a + b;\n stage2 <= c + d;\n stage3 <= e + f;\nend\nalways @(posedge clk) begin\n sum <= stage1 + stage2 + stage3;\nend", "description": "Deep combinational path in single-cycle adder causes WNS violation", "fix_patch": "Pipeline the adder across two clock cycles using intermediate registers", "verilog_ref": "adder.v:42", "tool": "OpenROAD"} |
| {"bug_id": "rtl_004", "bug_type": "COMBINATIONAL_LOOP", "severity": "ERROR", "buggy_snippet": "assign grant = req & ~busy;\nassign busy = grant & processing;", "fixed_snippet": "always @(posedge clk) begin\n grant <= req & ~busy;\nend\nassign busy = grant & processing;", "description": "Combinational feedback loop: req->grant->busy->grant", "fix_patch": "Register the grant signal to break the combinational loop", "verilog_ref": "scheduler.v:88", "tool": "OpenROAD"} |
| {"bug_id": "rtl_005", "bug_type": "CLOCK_DOMAIN_CROSSING", "severity": "WARNING", "buggy_snippet": "always @(posedge clk_fast) begin\n data_out <= data_in_slow;\nend", "fixed_snippet": "reg data_sync1, data_sync2;\nalways @(posedge clk_fast) begin\n data_sync1 <= data_in_slow;\n data_sync2 <= data_sync1;\nend\nassign data_out = data_sync2;", "description": "Direct sampling of slow-domain signal in fast-domain without synchronizer", "fix_patch": "Insert 2-flop synchronizer chain between clock domains", "verilog_ref": "cdc_bridge.v:34", "tool": "OpenROAD"} |
| {"bug_id": "rtl_006", "bug_type": "UNDRIVEN_PORT", "severity": "WARNING", "buggy_snippet": "module controller(\n input clk,\n input rst,\n input clk_en\n);\nalways @(posedge clk) begin\n if (!rst) state <= IDLE;\nend", "fixed_snippet": "module controller(\n input clk,\n input rst,\n input clk_en\n);\nalways @(posedge clk) begin\n if (!rst) state <= IDLE;\n else if (clk_en) state <= next_state;\nend", "description": "Input port clk_en declared but never used in logic", "fix_patch": "Use clk_en as clock enable condition in always block", "verilog_ref": "controller.v:8", "tool": "OpenROAD"} |
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