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any1/wlvncc | src/main.c | /*
* Copyright (c) 2020 <NAME>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <assert.h>
#include <errno.h>
#include <signal.h>
#include <getopt.h>
#include <sys/mman.h>
#include <aml.h>
#include <wayland-client.h>
#include <xkbcommon/xkbcommon.h>
#include "pixman.h"
#include "xdg-shell.h"
#include "shm.h"
#include "seat.h"
#include "pointer.h"
#include "keyboard.h"
#include "vnc.h"
struct buffer {
int width, height, stride;
size_t size;
enum wl_shm_format format;
struct wl_buffer* wl_buffer;
void* pixels;
bool is_attached;
};
struct window {
struct wl_surface* wl_surface;
struct xdg_surface* xdg_surface;
struct xdg_toplevel* xdg_toplevel;
struct buffer* front_buffer;
struct buffer* back_buffer;
};
static struct wl_display* wl_display;
static struct wl_registry* wl_registry;
struct wl_compositor* wl_compositor = NULL;
struct wl_shm* wl_shm = NULL;
static struct xdg_wm_base* xdg_wm_base;
static struct wl_list seats;
struct pointer_collection* pointers;
struct keyboard_collection* keyboards;
static enum wl_shm_format wl_shm_format;
static bool have_format = false;
static bool do_run = true;
struct window* window = NULL;
const char* app_id = "wlvncc";
static void on_seat_capability_change(struct seat* seat)
{
if (seat->capabilities & WL_SEAT_CAPABILITY_POINTER) {
// TODO: Make sure this only happens once
struct wl_pointer* wl_pointer =
wl_seat_get_pointer(seat->wl_seat);
pointer_collection_add_wl_pointer(pointers, wl_pointer);
} else {
// TODO Remove
}
if (seat->capabilities & WL_SEAT_CAPABILITY_KEYBOARD) {
// TODO: Make sure this only happens once
struct wl_keyboard* wl_keyboard =
wl_seat_get_keyboard(seat->wl_seat);
keyboard_collection_add_wl_keyboard(keyboards, wl_keyboard);
} else {
// TODO Remove
}
}
static void registry_add(void* data, struct wl_registry* registry, uint32_t id,
const char* interface, uint32_t version)
{
if (strcmp(interface, "wl_compositor") == 0) {
wl_compositor = wl_registry_bind(registry, id,
&wl_compositor_interface, 4);
} else if (strcmp(interface, "xdg_wm_base") == 0) {
xdg_wm_base = wl_registry_bind(registry, id, &xdg_wm_base_interface, 1);
} else if (strcmp(interface, "wl_shm") == 0) {
wl_shm = wl_registry_bind(registry, id, &wl_shm_interface, 1);
} else if (strcmp(interface, "wl_seat") == 0) {
struct wl_seat* wl_seat;
wl_seat = wl_registry_bind(registry, id, &wl_seat_interface, 5);
struct seat* seat = seat_new(wl_seat, id);
if (!seat) {
wl_seat_destroy(wl_seat);
return;
}
wl_list_insert(&seats, &seat->link);
seat->on_capability_change = on_seat_capability_change;
}
}
void registry_remove(void* data, struct wl_registry* registry, uint32_t id)
{
struct seat* seat = seat_find_by_id(&seats, id);
if (seat) {
wl_list_remove(&seat->link);
seat_destroy(seat);
}
}
static const struct wl_registry_listener registry_listener = {
.global = registry_add,
.global_remove = registry_remove,
};
static void buffer_release(void* data, struct wl_buffer* wl_buffer)
{
(void)wl_buffer;
struct buffer* self = data;
self->is_attached = false;
}
static const struct wl_buffer_listener buffer_listener = {
.release = buffer_release,
};
static struct buffer* buffer_create(int width, int height, int stride,
enum wl_shm_format format)
{
struct buffer* self = calloc(1, sizeof(*self));
if (!self)
return NULL;
self->width = width;
self->height = height;
self->stride = stride;
self->format = format;
self->size = height * stride;
int fd = shm_alloc_fd(self->size);
if (fd < 0)
goto failure;
self->pixels = mmap(NULL, self->size, PROT_READ | PROT_WRITE,
MAP_SHARED, fd, 0);
if (!self->pixels)
goto mmap_failure;
struct wl_shm_pool* pool = wl_shm_create_pool(wl_shm, fd, self->size);
if (!pool)
goto pool_failure;
self->wl_buffer = wl_shm_pool_create_buffer(pool, 0, width, height,
stride, format);
wl_shm_pool_destroy(pool);
if (!self->wl_buffer)
goto shm_failure;
close(fd);
wl_buffer_add_listener(self->wl_buffer, &buffer_listener, self);
return self;
shm_failure:
pool_failure:
munmap(self->pixels, self->size);
mmap_failure:
close(fd);
failure:
free(self);
return NULL;
}
static void buffer_destroy(struct buffer* self)
{
wl_buffer_destroy(self->wl_buffer);
munmap(self->pixels, self->size);
free(self);
}
static void shm_format(void* data, struct wl_shm* shm, uint32_t format)
{
(void)data;
(void)wl_shm;
if (have_format)
return;
switch (format) {
case WL_SHM_FORMAT_XRGB8888:
wl_shm_format = format;
have_format = true;
}
// TODO: Support more formats
}
static const struct wl_shm_listener shm_listener = {
.format = shm_format,
};
static void xdg_wm_base_ping(void* data, struct xdg_wm_base* shell,
uint32_t serial)
{
xdg_wm_base_pong(shell, serial);
}
static const struct xdg_wm_base_listener xdg_wm_base_listener = {
.ping = xdg_wm_base_ping,
};
void on_wayland_event(void* obj)
{
int rc = wl_display_prepare_read(wl_display);
assert(rc == 0);
if (wl_display_read_events(wl_display) < 0) {
if (errno == EPIPE) {
fprintf(stderr, "Compositor has gone away. Exiting...\n");
do_run = false;
} else {
fprintf(stderr, "Failed to read wayland events: %m\n");
}
}
if (wl_display_dispatch_pending(wl_display) < 0)
fprintf(stderr, "Failed to dispatch pending\n");
}
static int init_wayland_event_handler(void)
{
struct aml_handler* handler;
handler = aml_handler_new(wl_display_get_fd(wl_display),
on_wayland_event, NULL, NULL);
if (!handler)
return -1;
int rc = aml_start(aml_get_default(), handler);
aml_unref(handler);
return rc;
}
static void on_signal(void* obj)
{
do_run = false;
}
static int init_signal_handler(void)
{
struct aml_signal* sig;
sig = aml_signal_new(SIGINT, on_signal, NULL, NULL);
if (!sig)
return -1;
int rc = aml_start(aml_get_default(), sig);
aml_unref(sig);
return rc;
}
static void window_attach(struct window* w, int x, int y)
{
w->back_buffer->is_attached = true;
wl_surface_attach(w->wl_surface, w->back_buffer->wl_buffer, x, y);
}
static void window_commit(struct window* w)
{
wl_surface_commit(w->wl_surface);
}
static void window_swap(struct window* w, struct vnc_client* client)
{
struct buffer* tmp = w->front_buffer;
w->front_buffer = w->back_buffer;
w->back_buffer = tmp;
vnc_client_set_fb(client, window->back_buffer->pixels);
}
static void window_damage(struct window* w, int x, int y, int width, int height)
{
wl_surface_damage(w->wl_surface, x, y, width, height);
}
static void window_configure(struct window* w)
{
// What to do here?
}
static void xdg_surface_configure(void* data, struct xdg_surface* surface,
uint32_t serial)
{
struct window* w = data;
xdg_surface_ack_configure(surface, serial);
window_configure(w);
}
static const struct xdg_surface_listener xdg_surface_listener = {
.configure = xdg_surface_configure,
};
static void xdg_toplevel_configure(void* data, struct xdg_toplevel* toplevel,
int32_t width, int32_t height, struct wl_array* state)
{
// What to do here?
}
static void xdg_toplevel_close(void* data, struct xdg_toplevel* toplevel)
{
do_run = false;
}
static const struct xdg_toplevel_listener xdg_toplevel_listener = {
.configure = xdg_toplevel_configure,
.close = xdg_toplevel_close,
};
static struct window* window_create(const char* app_id, const char* title)
{
struct window* w = calloc(1, sizeof(*w));
if (!w)
return NULL;
w->wl_surface = wl_compositor_create_surface(wl_compositor);
if (!w->wl_surface)
goto wl_surface_failure;
w->xdg_surface = xdg_wm_base_get_xdg_surface(xdg_wm_base, w->wl_surface);
if (!w->xdg_surface)
goto xdg_surface_failure;
xdg_surface_add_listener(w->xdg_surface, &xdg_surface_listener, w);
w->xdg_toplevel = xdg_surface_get_toplevel(w->xdg_surface);
if (!w->xdg_toplevel)
goto xdg_toplevel_failure;
xdg_toplevel_add_listener(w->xdg_toplevel, &xdg_toplevel_listener, w);
xdg_toplevel_set_app_id(w->xdg_toplevel, app_id);
xdg_toplevel_set_title(w->xdg_toplevel, title);
wl_surface_commit(w->wl_surface);
return w;
xdg_toplevel_failure:
xdg_surface_destroy(w->xdg_surface);
xdg_surface_failure:
wl_surface_destroy(w->wl_surface);
wl_surface_failure:
free(w);
return NULL;
}
static void window_destroy(struct window* w)
{
if (w->front_buffer)
buffer_destroy(w->front_buffer);
if (w->back_buffer)
buffer_destroy(w->back_buffer);
xdg_toplevel_destroy(w->xdg_toplevel);
xdg_surface_destroy(w->xdg_surface);
wl_surface_destroy(w->wl_surface);
free(w);
}
void on_pointer_event(struct pointer_collection* collection,
struct pointer* pointer)
{
struct vnc_client* client = collection->userdata;
int x = wl_fixed_to_int(pointer->x);
int y = wl_fixed_to_int(pointer->y);
enum pointer_button_mask pressed = pointer->pressed;
int vertical_steps = pointer->vertical_scroll_steps;
int horizontal_steps = pointer->horizontal_scroll_steps;
if (!vertical_steps && !horizontal_steps) {
vnc_client_send_pointer_event(client, x, y, pressed);
return;
}
enum pointer_button_mask scroll_mask = 0;
if (vertical_steps < 0) {
vertical_steps *= -1;
scroll_mask |= POINTER_SCROLL_UP;
} else {
scroll_mask |= POINTER_SCROLL_DOWN;
}
if (horizontal_steps < 0) {
horizontal_steps *= -1;
scroll_mask |= POINTER_SCROLL_LEFT;
} else {
scroll_mask |= POINTER_SCROLL_RIGHT;
}
while (horizontal_steps > 0 || vertical_steps > 0) {
vnc_client_send_pointer_event(client, x, y, pressed | scroll_mask);
vnc_client_send_pointer_event(client, x, y, pressed);
if (--vertical_steps <= 0)
scroll_mask &= ~(POINTER_SCROLL_UP | POINTER_SCROLL_DOWN);
if (--horizontal_steps <= 0)
scroll_mask &= ~(POINTER_SCROLL_LEFT | POINTER_SCROLL_RIGHT);
}
}
void on_keyboard_event(struct keyboard_collection* collection,
struct keyboard* keyboard, uint32_t key, bool is_pressed)
{
struct vnc_client* client = collection->userdata;
// TODO handle multiple symbols
xkb_keysym_t symbol = xkb_state_key_get_one_sym(keyboard->state, key);
char name[256];
xkb_keysym_get_name(symbol, name, sizeof(name));
vnc_client_send_keyboard_event(client, symbol, key - 8, is_pressed);
}
int on_vnc_client_alloc_fb(struct vnc_client* client)
{
assert(!window); // TODO: Support resizing
int width = vnc_client_get_width(client);
int height = vnc_client_get_height(client);
int stride = vnc_client_get_stride(client);
window = window_create(app_id, vnc_client_get_desktop_name(client));
if (!window)
return -1;
window->front_buffer = buffer_create(width, height, stride,
wl_shm_format);
window->back_buffer = buffer_create(width, height, stride,
wl_shm_format);
vnc_client_set_fb(client, window->back_buffer->pixels);
return 0;
}
void on_vnc_client_update_fb(struct vnc_client* client)
{
if (!pixman_region_not_empty(&client->damage))
return;
if (window->back_buffer->is_attached)
fprintf(stderr, "Oops, back-buffer is still attached.\n");
window_attach(window, 0, 0);
int n_rects = 0;
struct pixman_box16* box = pixman_region_rectangles(&client->damage,
&n_rects);
for (int i = 0; i < n_rects; ++i) {
int x = box[i].x1;
int y = box[i].y1;
int width = box[i].x2 - x;
int height = box[i].y2 - y;
window_damage(window, x, y, width, height);
}
window_commit(window);
window_swap(window, client);
}
void on_vnc_client_event(void* obj)
{
struct vnc_client* client = aml_get_userdata(obj);
if (vnc_client_process(client) < 0)
do_run = false;
}
int init_vnc_client_handler(struct vnc_client* client)
{
int fd = vnc_client_get_fd(client);
struct aml_handler* handler;
handler = aml_handler_new(fd, on_vnc_client_event, client, NULL);
if (!handler)
return -1;
int rc = aml_start(aml_get_default(), handler);
aml_unref(handler);
return rc;
}
static int usage(int r)
{
fprintf(r ? stderr : stdout, "\
Usage: wlvncc <address> [port]\n\
\n\
-a,--app-id=<name> Set the app-id of the window. Default: wlvncc\n\
-c,--compression Compression level (0 - 9).\n\
-e,--encodings=<list> Set allowed encodings, comma separated list.\n\
Supported values: tight, zrle, ultra, copyrect,\n\
hextile, zlib, corre, rre, raw.\n\
-h,--help Get help.\n\
-n,--hide-cursor Hide the client-side cursor.\n\
-q,--quality Quality level (0 - 9).\n\
\n\
");
return r;
}
int main(int argc, char* argv[])
{
int rc = -1;
enum pointer_cursor_type cursor_type = POINTER_CURSOR_LEFT_PTR;
const char* encodings = NULL;
int quality = -1;
int compression = -1;
static const char* shortopts = "a:q:c:e:hn";
static const struct option longopts[] = {
{ "app-id", required_argument, NULL, 'a' },
{ "compression", required_argument, NULL, 'c' },
{ "encodings", required_argument, NULL, 'e' },
{ "help", no_argument, NULL, 'h' },
{ "quality", required_argument, NULL, 'q' },
{ "hide-cursor", no_argument, NULL, 'n' },
{ NULL, 0, NULL, 0 }
};
while (1) {
int c = getopt_long(argc, argv, shortopts, longopts, NULL);
if (c < 0)
break;
switch (c) {
case 'a':
app_id = optarg;
break;
case 'q':
quality = atoi(optarg);
break;
case 'c':
compression = atoi(optarg);
break;
case 'e':
encodings = optarg;
break;
case 'n':
cursor_type = POINTER_CURSOR_NONE;
break;
case 'h':
return usage(0);
default:
return usage(1);
}
}
int n_args = argc - optind;
if (n_args < 1)
return usage(1);
const char* address = argv[optind];
int port = 5900;
if (n_args >= 2)
port = atoi(argv[optind + 1]);
struct aml* aml = aml_new();
if (!aml)
return 1;
aml_set_default(aml);
if (init_signal_handler() < 0)
goto signal_handler_failure;
wl_display = wl_display_connect(NULL);
if (!wl_display)
goto display_failure;
if (init_wayland_event_handler() < 0)
goto event_handler_failure;
pointers = pointer_collection_new(cursor_type);
if (!pointers)
goto pointer_failure;
pointers->on_frame = on_pointer_event;
keyboards = keyboard_collection_new();
if (!keyboards)
goto keyboards_failure;
keyboards->on_event = on_keyboard_event;
wl_registry = wl_display_get_registry(wl_display);
if (!wl_registry)
goto registry_failure;
wl_list_init(&seats);
wl_registry_add_listener(wl_registry, ®istry_listener, wl_display);
wl_display_roundtrip(wl_display);
assert(wl_compositor);
assert(wl_shm);
assert(xdg_wm_base);
wl_shm_add_listener(wl_shm, &shm_listener, NULL);
xdg_wm_base_add_listener(xdg_wm_base, &xdg_wm_base_listener, NULL);
wl_display_roundtrip(wl_display);
wl_display_roundtrip(wl_display);
struct vnc_client* vnc = vnc_client_create();
if (!vnc)
goto vnc_failure;
vnc->alloc_fb = on_vnc_client_alloc_fb;
vnc->update_fb = on_vnc_client_update_fb;
if (vnc_client_set_pixel_format(vnc, wl_shm_format) < 0) {
fprintf(stderr, "Unsupported pixel format\n");
goto vnc_setup_failure;
}
if (encodings)
vnc_client_set_encodings(vnc, encodings);
if (quality >= 0)
vnc_client_set_quality_level(vnc, quality);
if (compression >= 0)
vnc_client_set_compression_level(vnc, compression);
if (vnc_client_connect(vnc, address, port) < 0) {
fprintf(stderr, "Failed to connect to server\n");
goto vnc_setup_failure;
}
if (init_vnc_client_handler(vnc) < 0)
goto vnc_setup_failure;
pointers->userdata = vnc;
keyboards->userdata = vnc;
wl_display_dispatch(wl_display);
while (do_run) {
wl_display_flush(wl_display);
aml_poll(aml, -1);
aml_dispatch(aml);
}
rc = 0;
if (window)
window_destroy(window);
vnc_setup_failure:
vnc_client_destroy(vnc);
vnc_failure:
seat_list_destroy(&seats);
wl_compositor_destroy(wl_compositor);
wl_shm_destroy(wl_shm);
xdg_wm_base_destroy(xdg_wm_base);
wl_registry_destroy(wl_registry);
registry_failure:
keyboard_collection_destroy(keyboards);
keyboards_failure:
pointer_collection_destroy(pointers);
pointer_failure:
event_handler_failure:
wl_display_disconnect(wl_display);
display_failure:
signal_handler_failure:
aml_unref(aml);
printf("Exiting...\n");
return rc;
}
|
any1/wlvncc | include/vnc.h | /*
* Copyright (c) 2020 <NAME>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#pragma once
#include <stdbool.h>
#include <unistd.h>
#include <pixman.h>
#include <wayland-client.h>
#include <rfb/rfbclient.h>
struct vnc_client {
rfbClient* client;
int (*alloc_fb)(struct vnc_client*);
void (*update_fb)(struct vnc_client*);
void (*cut_text)(struct vnc_client*, const char*, size_t);
void* userdata;
struct pixman_region16 damage;
};
struct vnc_client* vnc_client_create(void);
void vnc_client_destroy(struct vnc_client* self);
int vnc_client_connect(struct vnc_client* self, const char* address, int port);
int vnc_client_set_pixel_format(struct vnc_client* self,
enum wl_shm_format format);
int vnc_client_get_fd(const struct vnc_client* self);
int vnc_client_get_width(const struct vnc_client* self);
int vnc_client_get_height(const struct vnc_client* self);
int vnc_client_get_stride(const struct vnc_client* self);
void* vnc_client_get_fb(const struct vnc_client* self);
void vnc_client_set_fb(struct vnc_client* self, void* fb);
const char* vnc_client_get_desktop_name(const struct vnc_client* self);
int vnc_client_process(struct vnc_client* self);
void vnc_client_send_pointer_event(struct vnc_client* self, int x, int y,
uint32_t button_mask);
void vnc_client_send_keyboard_event(struct vnc_client* self, uint32_t symbol,
uint32_t code, bool is_pressed);
void vnc_client_set_encodings(struct vnc_client* self, const char* encodings);
void vnc_client_set_quality_level(struct vnc_client* self, int value);
void vnc_client_set_compression_level(struct vnc_client* self, int value);
void vnc_client_send_cut_text(struct vnc_client* self, const char* text,
size_t len);
|
jbrandwood/EditWith | source/su3shellx/config.h | // ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {36B40FAF-667E-4B19-8F41-DFEB32A370DC}
//
#define MY_COM_CLASS {0x36B40FAF,0x667E,0x4B19,{0x8F,0x41,0xDF,0xEB,0x32,0xA3,0x70,0xDC}}
#define MY_COM_TITLE L"EditWithSublimeText"
#define MY_WIN_CLASS_STR L"PX_WINDOW_CLASS"
// Sublime Text does not register itself like Microsoft recommends so try
// looking for it in the (64 or 32 bit) "Program Files" directory.
#define MY_APP_PATH_FIXED L"Sublime Text 3\\sublime_text.exe"
#define MY_EXE_NAME L"sublime_text.exe"
// Define this to disable multiple session support by default.
//
// This setting corresponds to this editor's default settings.
//
// It can be changed for the current user at any time in the registry.
//
// To do this, just run (double-click) on the "edit-single-session.js" or
// "edit-multi-sessions.js" files in this extensions's "build" directory.
//
// #define SINGLE_MY_APP_INSTANCE
#ifdef SINGLE_MY_APP_INSTANCE
#define MY_EXE_OPTS L""
#else
#define MY_EXE_OPTS L"-n"
#endif
// Sublime Text opens 2 windows if started with "-n" when no instance is running.
#define SKIP_OPTS_IF_NO_INSTANCE
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/ep3shellx/config.h | <gh_stars>1-10
// ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {3B8444F9-111B-4921-81D7-213276E36430}
//
#define MY_COM_CLASS {0x3B8444F9,0x111B,0x4921,{0x81,0xD7,0x21,0x32,0x76,0xE3,0x64,0x30}}
#define MY_COM_TITLE L"EditWithEP3"
// N.B. EditPlus uses a dynamic MFC window class name that can (and does) change.
// See MSDN article "TN070: MFC Window Class Names".
#define MY_WIN_CLASS_STR L"Afx:"
// The actual numbers can change with every new window, so limit the test length.
#define MY_WIN_CLASS_LEN 4
// Distinguish EditPlus from UltraEdit/UEStudio
#define MY_WIN_TITLE_STR L"EditPlus"
// Final test to ensure that we've got the right existing session window.
#define MY_EXE_IMAGE_CHK
#define MY_EXE_NAME L"editplus.exe"
#define MY_EXE_OPTS L""
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/pspshellx/config.h | // ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {ED90173A-3B4C-4E7E-B9CF-79714425D4B5}
//
#define MY_COM_CLASS {0xED90173A,0x3B4C,0x4E7E,{0xB9,0xCF,0x79,0x71,0x44,0x25,0xD4,0xB5}}
#define MY_COM_TITLE L"EditWithPSPad"
#define MY_WIN_CLASS_STR L"TfPSPad.UnicodeClass"
#define MY_EXE_NAME L"PSPad.exe"
// Define this to disable multiple session support by default.
//
// This setting corresponds to this editor's default settings.
//
// It can be changed for the current user at any time in the registry.
//
// To do this, just run (double-click) on the "edit-single-session.js" or
// "edit-multi-sessions.js" files in this extensions's "build" directory.
//
#define SINGLE_MY_APP_INSTANCE
#ifdef SINGLE_MY_APP_INSTANCE
#define MY_EXE_OPTS L""
#else
#define MY_EXE_OPTS L"/N"
#endif
#define MY_HEX_OPTS L" /H"
#define MY_DIFF_OPTS L" /D"
#define MAXIMUM_DIFF 2
// PSPad will not start a 2nd session with no files on the command line.
#define NO_INITIAL_DROP_ON_2ND
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/kshellx/config.h | // ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {7F38663E-04FA-4C75-8FAA-B5A73C8B9131}
//
#define MY_COM_CLASS {0x7F38663E,0x04FA,0x4C75,{0x8F,0xAA,0xB5,0xA7,0x3C,0x8B,0x91,0x31}}
#define MY_COM_TITLE L"EditWithKomodo"
// Komodo requires OLE instead of WM_DROPFILES.
#define USE_OLE_DODRAGDROP
// N.B. Komodo uses the same window class name as other Mozilla applications.
#define MY_WIN_CLASS_STR L"MozillaWindowClass"
// Distinguish Komodo Edit / Komodo IDE from other Mozilla applications.
#define MY_WIN_TITLE_STR L"Komodo "
// Final test to ensure that we've got the right existing session window.
#define MY_EXE_IMAGE_CHK
#define MY_EXE_NAME L"komodo.exe"
// Define this to disable multiple session support by default.
//
// This setting corresponds to this editor's default settings.
//
// It can be changed for the current user at any time in the registry.
//
// To do this, just run (double-click) on the "edit-single-session.js" or
// "edit-multi-sessions.js" files in this extensions's "build" directory.
//
// #define SINGLE_MY_APP_INSTANCE
#ifdef SINGLE_MY_APP_INSTANCE
#define MY_EXE_OPTS L""
#else
#define MY_EXE_OPTS L"-n"
#endif
// Komodo opens 2 windows if started with "-n" when no instance is running.
#define SKIP_OPTS_IF_NO_INSTANCE
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/seshellx/config.h | // ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {6A06A71E-CFFA-444C-B347-1B7898C9AB7B}
//
#define MY_COM_CLASS {0x6A06A71E,0xCFFA,0x444C,{0xB3,0x47,0x1B,0x78,0x98,0xC9,0xAB,0x7B}}
#define MY_COM_TITLE L"EditWithSlickEdit"
// SlickEdit requires OLE instead of WM_DROPFILES.
#define USE_OLE_DODRAGDROP
// N.B. SlickEdit uses the same generic window class name as other QT applications.
#define MY_WIN_CLASS_STR L"QWidget"
// Distinguish SlickEdit from other QT applications.
#define MY_WIN_TITLE_STR L"SlickEdit"
// Final test to ensure that we've got the right existing session window.
#define MY_EXE_IMAGE_CHK
#define MY_EXE_NAME L"vs.exe"
// Define this to disable multiple session support by default.
//
// This setting corresponds to this editor's default settings.
//
// It can be changed for the current user at any time in the registry.
//
// To do this, just run (double-click) on the "edit-single-session.js" or
// "edit-multi-sessions.js" files in this extensions's "build" directory.
//
#define SINGLE_MY_APP_INSTANCE
#ifdef SINGLE_MY_APP_INSTANCE
#define MY_EXE_OPTS L""
#else
// This only works properly if the user disables SlickEdit's options
// AutoRestoreFiles and AutoRestoreWorkspace.
#define MY_EXE_OPTS L"+new"
#endif
// http://community.slickedit.com/index.php/topic,9835.0.html
//
// The SlickEdit Community Forum suggests using ...
//
// #define MY_EXE_OPTS L"+new -snorestore -snoconfig"
//
// But that set of options screws up drag-and-drop on my
// SlickEdit 2012.
// SlickEdit will not start a 2nd session with no files on the command line.
#define NO_INITIAL_DROP_ON_2ND
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/uesshellx/config.h | <reponame>jbrandwood/EditWith<filename>source/uesshellx/config.h<gh_stars>1-10
// ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {ADE88F8C-82EC-4C30-941F-1240656F4EC8}
//
#define MY_COM_CLASS {0xADE88F8C,0x82EC,0x4C30,{0x94,0x1F,0x12,0x40,0x65,0x6F,0x4E,0xC8}}
#define MY_COM_TITLE L"EditWithUEStudio"
// N.B. UEStudio uses a dynamic MFC window class name that can (and does) change.
// See MSDN article "TN070: MFC Window Class Names".
#define MY_WIN_CLASS_STR L"Afx:"
// The actual numbers can change with every new window, so limit the test length.
#define MY_WIN_CLASS_LEN 4
// Distinguish UEStudio from UltraEdit/EditPlus
#define MY_WIN_TITLE_STR L"UEStudio"
// Final test to ensure that we've got the right existing session window.
#define MY_EXE_IMAGE_CHK
#define MY_EXE_NAME L"UEStudio.exe"
// Define this to disable multiple session support by default.
//
// This setting corresponds to this editor's default settings.
//
// It can be changed for the current user at any time in the registry.
//
// To do this, just run (double-click) on the "edit-single-session.js" or
// "edit-multi-sessions.js" files in this extensions's "build" directory.
//
// #define SINGLE_MY_APP_INSTANCE
#ifdef SINGLE_MY_APP_INSTANCE
#define MY_EXE_OPTS L""
#else
#define MY_EXE_OPTS L"/fni"
#endif
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/emeshellx/config.h | // ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {7B245014-8540-4190-936A-D0B89838CC40}
//
#define MY_COM_CLASS {0x7B245014,0x8540,0x4190,{0x93,0x6A,0xD0,0xB8,0x98,0x38,0xCC,0x40}}
#define MY_COM_TITLE L"EditWithEmEditor"
#define MY_WIN_CLASS_STR L"EmEditorMainFrame3"
// EmEditor does not register itself in "App Paths" so look for it in the
// older "Applications" key instead.
#define MY_APP_PATH_KEY L"Applications\\EmEditor.exe\\shell\\edit\\command"
#define MY_EXE_NAME L"EmEditor.exe"
// Define this to disable multiple session support by default.
//
// This setting corresponds to this editor's default settings.
//
// It can be changed for the current user at any time in the registry.
//
// To do this, just run (double-click) on the "edit-single-session.js" or
// "edit-multi-sessions.js" files in this extensions's "build" directory.
//
// #define SINGLE_MY_APP_INSTANCE
#ifdef SINGLE_MY_APP_INSTANCE
#define MY_EXE_OPTS L""
#else
#define MY_EXE_OPTS L"/sp"
#endif
#define GET_ICON_FROM_MY_EXE
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/scishellx/config.h | <reponame>jbrandwood/EditWith<filename>source/scishellx/config.h
// ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {8E4CFFE7-33C1-41B3-A52F-09842B8B8C9A}
//
#define MY_COM_CLASS {0x8E4CFFE7,0x33C1,0x41B3,{0xA5,0x2F,0x09,0x84,0x2B,0x8B,0x8C,0x9A}}
#define MY_COM_TITLE L"EditWithSciTE"
#define MY_WIN_CLASS_STR L"SciTEWindow"
// SciTE does not install ... and so does not register itself like Microsoft
// recommends. So try looking for it in the "Program Files" directory under
// it's default folder name.
#define MY_APP_PATH_FIXED L"wscite\\SciTE.exe"
#define MY_EXE_NAME L"SciTE.exe"
#define MY_EXE_OPTS L""
#define GET_ICON_FROM_MY_EXE
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/tpshellx/ResourceFuncs.h | // ****************************************************************************
// ****************************************************************************
//
// ResourceFuncs.h : Various utility funcs for accessing resource data.
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
#include <gdiplus.h>
//
// ****************************************************************************
//
// Fast access to internationalized string resources.
extern BOOL SetMyResourceStringModule (
HMODULE hModule );
extern BOOL SetMyResourceStringLanguage (
WORD wLanguage );
extern UINT GetMyResourceString (
UINT uResourceID, wchar_t * pBufPtr, UINT uBufLen );
// Load a GDI+ bitmap from a resource (GDI+ must already be initialized).
extern Gdiplus::Bitmap * LoadMyBitmapResource (
HINSTANCE hInstance, LPCTSTR lpBitmapName );
// Load an Exe's icon as a GDI+ bitmap (GDI+ must already be initialized).
extern Gdiplus::Bitmap * LoadMyAppIconAsBitmap (
LPCTSTR pExeFile, BYTE * pPixelData, UINT uIconSz );
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/EditWithMyApp.h | // ****************************************************************************
// ****************************************************************************
//
// EditWithMyApp.h : Declaration of CEditWithMyApp shell extension object
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
#include "config.h"
#include <shlobj.h>
#include <shellapi.h>
#define MAX_EXISTING_WINDOWS 16
#define PATH_BUFFER_CHARS 4096
#define OPTS_BUFFER_CHARS 128
#define MAX_FILE_DISPLAY_WIDTH 64
//
//
//
extern bool g_fRunningOnXP;
extern const CLSID CLSID_MyExtensionClass;
extern const wchar_t * szMyExtensionTitle;
//
// ****************************************************************************
//
class CEditWithMyApp :
public IShellExtInit,
public IContextMenu3
{
public:
CEditWithMyApp();
~CEditWithMyApp();
public:
// IUnknown members.
STDMETHOD( QueryInterface ) ( REFIID, LPVOID * );
STDMETHOD_( ULONG, AddRef ) ( void );
STDMETHOD_( ULONG, Release ) ( void );
// IShellExtInit members.
STDMETHOD( Initialize ) ( PCIDLIST_ABSOLUTE, IDataObject *, HKEY );
// IContextMenu members.
STDMETHOD( GetCommandString ) ( UINT_PTR, UINT, UINT *, LPSTR, UINT );
STDMETHOD( InvokeCommand ) ( LPCMINVOKECOMMANDINFO );
STDMETHOD( QueryContextMenu ) ( HMENU, UINT, UINT, UINT, UINT );
// IContextMenu2 members. (Only needed for rendering on WinXP)
STDMETHOD( HandleMenuMsg ) ( UINT, WPARAM, LPARAM );
// IContextMenu3 members. (Only needed for rendering on WinXP)
STDMETHOD( HandleMenuMsg2 ) ( UINT, WPARAM, LPARAM, LRESULT * );
protected:
ULONG m_uRefCount;
HINSTANCE m_hDllInstance;
BOOL OnCreation( void );
void OnDestruction( void );
HBITMAP GetMenuIcon( void );
// Separate the DLL & COM code from the actual functional implementation.
LPDATAOBJECT m_pDataObject;
STGMEDIUM m_cStgMedium;
HDROP m_hDrop;
UINT m_uNumFilesInList;
UINT m_uNumCharsInList;
wchar_t m_aAppOptions [OPTS_BUFFER_CHARS];
bool m_fShowExisting;
bool m_fShowDiff;
bool m_fShowHex;
UINT m_uNumExistingWindows;
HWND m_aWindowList [MAX_EXISTING_WINDOWS];
HWND m_hFoundWindow;
void FreeDataObject ( void );
bool GetFileList ( void );
char MenuCmdToAction( UINT uMenuCmd, UINT * pMenuCmd );
HRESULT SendFilesToNewAppInstance(
HWND hParent, const wchar_t * szExtraOpts );
HRESULT SendFilesToNewProcessWindow(
HWND hParent, PROCESS_INFORMATION &cPI );
HRESULT SendFilesToOldAppInstance(
HWND hParent, HWND hTarget );
bool LocateMyApp( wchar_t *aExecPath, DWORD nMaxChars );
void GetMyOptions( void );
static BOOL CALLBACK EnumWindowCallback(
HWND hWindow, LPARAM lParam );
#ifdef DROP_ON_CHILD_WINDOW
static BOOL CALLBACK EnumChildWindowCallbackFindClass(
HWND hWindow, LPARAM lParam );
#endif
static HBITMAP s_hIconBitmap;
static int s_iIconW;
static int s_iIconH;
public:
// To let the DLL free up our cached resources.
static void FreeStaticResources( void );
};
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/stdafx.h | <filename>source/stdafx.h
// stdafx.h : include file for standard system include files,
// or project specific include files that are used frequently,
// but are changed infrequently
#if !defined(AFX_STDAFX_H__951D8D82_8CE4_4847_93F6_36A0D9A05866__INCLUDED_)
#define AFX_STDAFX_H__951D8D82_8CE4_4847_93F6_36A0D9A05866__INCLUDED_
#if _MSC_VER > 1000
#pragma once
#endif
#ifndef STRICT
#define STRICT
#endif
#define _CRT_SECURE_NO_WARNINGS
#ifndef WIN32_LEAN_AND_MEAN
#define WIN32_LEAN_AND_MEAN
#endif
#include "targetver.h"
#include <windows.h>
#include <comdef.h>
#endif
|
jbrandwood/EditWith | source/tpshellx/config.h | <reponame>jbrandwood/EditWith
// ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {4A169362-D7BC-4428-9E21-D998BD37807F}
//
#define MY_COM_CLASS {0x4A169362,0xD7BC,0x4428,{0x9E,0x21,0xD9,0x98,0xBD,0x37,0x80,0x7F}}
#define MY_COM_TITLE L"EditWithTextPad"
#define MY_WIN_CLASS_STR L"TextPad7"
#define MY_EXE_NAME L"TextPad.exe"
// Define this to disable multiple session support by default.
//
// This setting corresponds to this editor's default settings.
//
// It can be changed for the current user at any time in the registry.
//
// To do this, just run (double-click) on the "edit-single-session.js" or
// "edit-multi-sessions.js" files in this extensions's "build" directory.
//
// #define SINGLE_MY_APP_INSTANCE
#ifdef SINGLE_MY_APP_INSTANCE
#define MY_EXE_OPTS L"-q"
#else
#define MY_EXE_OPTS L"-q -m"
#endif
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/vimshellx/config.h | <reponame>jbrandwood/EditWith<gh_stars>1-10
// ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {95FF2471-55D2-4B22-A352-B1299F199C29}
//
#define MY_COM_CLASS {0x95FF2471,0x55D2,0x4B22,{0xA3,0x52,0xB1,0x29,0x9F,0x19,0x9C,0x29}}
#define MY_COM_TITLE L"EditWithVim"
#define MY_WIN_CLASS_STR L"Vim"
// Vim does not register itself in "App Paths" so look for it in the
// older "Applications" key instead.
#define MY_APP_PATH_KEY L"Applications\\gvim.exe\\shell\\edit\\command"
#define MY_EXE_NAME L"gvim.exe"
#define MY_EXE_OPTS L"--literal"
#define MY_DIFF_OPTS L" -d"
#define MAXIMUM_DIFF 4
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/pn2shellx/config.h | // ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {6BD977B9-96E3-478C-B4EE-1DE777375A1A}
//
#define MY_COM_CLASS {0x6BD977B9,0x96E3,0x478C,{0xB4,0xEE,0x1D,0xE7,0x77,0x37,0x5A,0x1A}}
#define MY_COM_TITLE L"EditWithPN2"
#define MY_WIN_CLASS_STR L"ATL:006AD5B8"
// Final test to ensure that we've got the right existing session window.
#define MY_EXE_IMAGE_CHK
// Programmer's Notepad does not register itself in "App Paths" so look
// for it in the older "Applications" key instead.
#define MY_APP_PATH_KEY L"Applications\\pn.exe\\shell\\edit\\command"
#define MY_EXE_NAME L"pn.exe"
// Define this to disable multiple session support by default.
//
// This setting corresponds to this editor's default settings.
//
// It can be changed for the current user at any time in the registry.
//
// To do this, just run (double-click) on the "edit-single-session.js" or
// "edit-multi-sessions.js" files in this extensions's "build" directory.
//
// #define SINGLE_MY_APP_INSTANCE
#ifdef SINGLE_MY_APP_INSTANCE
#define MY_EXE_OPTS L""
#else
#define MY_EXE_OPTS L"--allowmulti"
#endif
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/bshellx/config.h | <reponame>jbrandwood/EditWith
// ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {30DB95DC-3D27-4B74-9B8E-44E99A320F06}
//
#define MY_COM_CLASS {0x30DB95DC,0x3D27,0x4B74,{0x9B,0x8E,0x44,0xE9,0x9A,0x32,0x0F,0x06}}
#define MY_COM_TITLE L"EditWithBrackets"
// Brackets requires OLE instead of WM_DROPFILES.
#define USE_OLE_DODRAGDROP
// Brackets will only open a new session if there are no files on the command line.
#define ALWAYS_DROP_ON_2ND
// Brackets doesn't like a drag-and-drop too quickly after a new session starts.
// Give it 4000ms to get it's act together.
#define INITIAL_DROP_DELAY 4000
// N.B. Brackets uses the same window class name as other ChromiumEmbedded applications.
#define MY_WIN_CLASS_STR L"CEFCLIENT"
// Secondary Brackets window are opened up as "CefBrowserWindow"
#define MY_WIN_CLASS_STR_2ND L"CefBrowserWindow"
// Distinguish Brackets from other ChromiumEmbedded applications.
#define MY_WIN_TITLE_STR L"Brackets"
// Final test to ensure that we've got the right existing session window.
#define MY_EXE_IMAGE_CHK
// Brackets does not register itself like Microsoft recommends so try
// looking for it in the (64 or 32 bit) "Program Files" directory.
#define MY_APP_PATH_FIXED L"Brackets\\Brackets.exe"
#define MY_EXE_NAME L"Brackets.exe"
// Define this to disable multiple session support by default.
//
// This setting corresponds to this editor's default settings.
//
// It can be changed for the current user at any time in the registry.
//
// To do this, just run (double-click) on the "edit-single-session.js" or
// "edit-multi-sessions.js" files in this extensions's "build" directory.
//
// #define SINGLE_MY_APP_INSTANCE
#ifdef SINGLE_MY_APP_INSTANCE
#define MY_EXE_OPTS L""
#else
#define MY_EXE_OPTS L""
#endif
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/vshellx/config.h | // ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {FE4E820B-A724-42C5-A552-0B2546DD7D1B}
//
#define MY_COM_CLASS {0xFE4E820B,0xA724,0x42C5,{0xA5,0x52,0x0B,0x25,0x46,0xDD,0x7D,0x1B}}
#define MY_COM_TITLE L"EditWithVedit"
#define MY_WIN_CLASS_STR L"vwCFrame"
#define MY_EXE_NAME L"vpw.exe"
#define MY_EXE_OPTS L"-s0 -e"
// #define MY_DIFF_OPTS L" -n 1 -x compare.vdm"
// #define MAXIMUM_DIFF 2
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/eppshellx/config.h | // ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {E8D5FF73-D41E-41CD-9779-E3B05DC5BA1F}
//
#define MY_COM_CLASS {0xE8D5FF73,0xD41E,0x41CD,{0x97,0x79,0xE3,0xB0,0x5D,0xC5,0xBA,0x1F}}
#define MY_COM_TITLE L"EditWithEditPad"
// EditPad Pro requires OLE instead of WM_DROPFILES.
#define USE_OLE_DODRAGDROP
#define MY_WIN_CLASS_STR L"TFormEditPadPro7"
#define MY_EXE_NAME L"EditPadPro7.exe"
// Define this to disable multiple session support by default.
//
// This setting corresponds to this editor's default settings.
//
// It can be changed for the current user at any time in the registry.
//
// To do this, just run (double-click) on the "edit-single-session.js" or
// "edit-multi-sessions.js" files in this extensions's "build" directory.
//
// #define SINGLE_MY_APP_INSTANCE
#ifdef SINGLE_MY_APP_INSTANCE
#define MY_EXE_OPTS L""
#else
#define MY_EXE_OPTS L"/newinstance"
#endif
//
// ****************************************************************************
//
|
jbrandwood/EditWith | source/meshellx/config.h | // ****************************************************************************
// ****************************************************************************
//
// config.h : Customization for this specific shell extension
//
// Copyright <NAME> 2014.
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
//
#if _MSC_VER > 1000
#pragma once
#endif
//
// Class ID = {762DB251-9E8E-44F5-B505-1770CEFBEB5D}
//
#define MY_COM_CLASS {0x762DB251,0x9E8E,0x44F5,{0xB5,0x05,0x17,0x70,0xCE,0xFB,0xEB,0x5D}}
#define MY_COM_TITLE L"EditWithMultiEdit"
#define MY_WIN_CLASS_STR L"MeXMain"
#define MY_EXE_NAME L"Mew32.exe"
// Define this to disable multiple session support by default.
//
// This setting corresponds to this editor's default settings.
//
// It can be changed for the current user at any time in the registry.
//
// To do this, just run (double-click) on the "edit-single-session.js" or
// "edit-multi-sessions.js" files in this extensions's "build" directory.
//
// #define SINGLE_MY_APP_INSTANCE
#ifdef SINGLE_MY_APP_INSTANCE
#define MY_EXE_OPTS L"/NoSplash"
#else
#define MY_EXE_OPTS L"/NI /NS /NoSplash"
#endif
//
// ****************************************************************************
//
|
ZhiangChen/ros_vision | terrain_following/include/terrain_following/perception_model_cpp.h | <filename>terrain_following/include/terrain_following/perception_model_cpp.h
/// Perception model for terrain following
/// <NAME>, 7/2019
/*The MIT License (MIT)
Copyright (c) 2019 <NAME>
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.*/
#ifndef Perception_Model_H_
#define Perception_Model_H_
#include <iostream> // for C++
#include <fstream>
#include <string>
#include <math.h>
#include <ros/ros.h> // for ROS
#include <sensor_msgs/PointCloud2.h>
#include <sensor_msgs/Image.h>
#include <tf/transform_listener.h>
#include <tf/transform_datatypes.h>
#include <tf2/LinearMath/Quaternion.h>
#include <geometry_msgs/Twist.h>
#include <geometry_msgs/TwistStamped.h>
#include <geometry_msgs/Point.h>
#include <geometry_msgs/PointStamped.h>
#include <geometry_msgs/PoseStamped.h>
#include <geometry_msgs/TransformStamped.h>
#include <message_filters/subscriber.h>
#include <message_filters/time_synchronizer.h>
#include <message_filters/sync_policies/approximate_time.h>
#include <actionlib/server/simple_action_server.h> // customized ROS messages
#include <terrain_following/terrainAction.h>
#include <nav_msgs/Path.h>
#include <pcl_ros/point_cloud.h> // for PCL
#include <pcl/conversions.h>
#include <pcl/point_types.h>
#include <pcl/point_cloud.h>
#include <pcl/common/common_headers.h>
#include <pcl/filters/passthrough.h>
#include <pcl/filters/voxel_grid.h>
#include <pcl/console/parse.h>
#include <pcl/common/transforms.h> // required for pcl::transformPointCloud
#include <pcl/filters/crop_box.h>
#include <pcl/kdtree/kdtree_flann.h>
#include <pcl/filters/statistical_outlier_removal.h>
#include <pcl/common/centroid.h>
#include <pcl/features/normal_3d.h>
#include <Eigen/Eigen> //for the Eigen library
#include <Eigen/Dense>
#include <Eigen/Geometry>
#include <Eigen/Eigenvalues>
using namespace std;
typedef message_filters::sync_policies::ApproximateTime<sensor_msgs::PointCloud2, geometry_msgs::PoseStamped> PC_POSE_POLICY;
#define BOX_X 0.5
#define BOX_Y 0.5
#define BOX_POINTS_THRES 10
#define Queue_Size 10
class Perception_Model
{
public:
Perception_Model(ros::NodeHandle *nh, string pc_topic);
Perception_Model(ros::NodeHandle *nh);
protected:
ros::NodeHandle nh_;
tf::TransformListener tf_listener_; // tf
tf::StampedTransform tf_transform_;
geometry_msgs::PoseStamped camera_pose_;
geometry_msgs::PoseStamped body_pose_;
Eigen::Affine3d T_camera2base_;
Eigen::Affine3d T_base2world_;
Eigen::Affine3d T_camera2world_;
nav_msgs::Path g_path_;
string pc_topic_; // pointcloud
bool pc_got_;
bool Tf_got_;
pcl::PointCloud<pcl::PointXYZRGB>::Ptr pcl_rgbd_ptr_;
pcl::PointCloud<pcl::PointXYZRGB>::Ptr pcl_ptr_;
pcl::PointCloud<pcl::PointXYZRGB>::Ptr pclTransformed_ptr_;
pcl::PointCloud<pcl::PointXYZRGB>::Ptr pclTransformed_ptr_copy_;
pcl::PointCloud<pcl::PointXYZRGB>::Ptr boxTransformed_ptr_;
pcl::PassThrough<pcl::PointXYZRGB> box_filter_;
pcl::PointCloud<pcl::PointXYZ>::Ptr pclTransformed_xyz_ptr_;
pcl::PointCloud<pcl::PointXYZ>::Ptr boxTransformed_xyz_ptr_;
Eigen::Vector4f box_centroid_pcl_;
Eigen::Vector3f box_centroid_;
Eigen::Vector3f no_translation_;
Eigen::Vector3f no_rotation_;
terrain_following::terrainFeedback feedback_; // action
terrain_following::terrainResult result_;
ros::Publisher pc_pub_; // service
ros::Publisher pose_pub_;
actionlib::SimpleActionServer<terrain_following::terrainAction> as_;
ros::Publisher path_pub_;
message_filters::Subscriber<sensor_msgs::PointCloud2> *mf_pc_sub_; // message filter
message_filters::Subscriber<geometry_msgs::PoseStamped> *mf_pose_sub_;
message_filters::Synchronizer<PC_POSE_POLICY> *pose_pc_sync_;
Eigen::Affine3d Posestamped2Affine3d_(geometry_msgs::PoseStamped stPose); // function
Eigen::Affine3d TF2Affine3d_(tf::StampedTransform sTf);
geometry_msgs::Pose Affine3d2Pose_(Eigen::Affine3d affine);
nav_msgs::Path getLocalPath(double x_des, double y_des);
void executeCB(const terrain_following::terrainGoalConstPtr &goal);
void mfCallback(const sensor_msgs::PointCloud2ConstPtr &cloud, const geometry_msgs::PoseStampedConstPtr &pose);
};
#endif
|
ZhiangChen/ros_vision | terrain_following/include/terrain_following/mavros_commander.h | <reponame>ZhiangChen/ros_vision
/// mavros commander
/// <NAME>, 7/2019
/*The MIT License (MIT)
Copyright (c) 2019 <NAME>
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.*/
#ifndef Mavros_Commander_H_
#define Mavros_Commander_H_
#include <iostream> // for C++
#include <fstream>
#include <string>
#include <math.h>
#include <ros/ros.h> // for ROS
#include <mavros_msgs/CommandBool.h>
#include <mavros_msgs/SetMode.h>
#include <mavros_msgs/State.h>
#include <mavros_msgs/ParamGet.h>
#include <mavros_msgs/WaypointClear.h>
#include <mavros_msgs/WaypointPush.h>
using namespace std;
class Mavros_Commander
{
public:
Mavros_Commander(ros::NodeHandle *nh);
void set_arm(bool arm, int timeout);
void set_mode(string mode, int timeout);
void clear_wps(int timeout);
void send_wps(int timeout);
protected:
ros::NodeHandle nh_;
ros::Subscriber state_sub_;
ros::ServiceClient get_param_client_;
ros::ServiceClient set_arming_client_;
ros::ServiceClient set_mode_client_;
ros::ServiceClient wp_clear_client_;
ros::ServiceClient wp_push_client_;
mavros_msgs::State current_state_;
void stateCallback_(const mavros_msgs::State::ConstPtr& msg);
};
#endif
|
ZhiangChen/ros_vision | terrain_following/include/terrain_following/waypoints_vel_controller.h | <reponame>ZhiangChen/ros_vision
/// waypoints_vel_controller.h
/// <NAME>, Aug 2019
/// MIT License
#ifndef WAYPOINTS_VEL_CONTROLLER_H_
#define WAYPOINTS_VEL_CONTROLLER_H_
#include <iostream> // for C++
#include <fstream>
#include <string>
#include <math.h>
#include <ros/ros.h> // for ROS
#include <sensor_msgs/PointCloud2.h>
#include <sensor_msgs/Image.h>
#include <tf/transform_listener.h>
#include <geometry_msgs/Twist.h>
#include <geometry_msgs/TwistStamped.h>
#include <geometry_msgs/Point.h>
#include <geometry_msgs/PointStamped.h>
#include <geometry_msgs/PoseStamped.h>
#include <geometry_msgs/TransformStamped.h>
#include <message_filters/subscriber.h>
#include <message_filters/time_synchronizer.h>
#include <message_filters/sync_policies/approximate_time.h>
#include <Eigen/Eigen> //for the Eigen library
#include <Eigen/Dense>
#include <Eigen/Geometry>
#include <Eigen/Eigenvalues>
#include <terrain_following/mavros_commander.h> // terrain following
#include <terrain_following/waypointsAction.h>
#include <terrain_following/terrainAction.h>
#include <actionlib/server/simple_action_server.h>
#include <actionlib/client/simple_action_client.h>
using namespace std;
class Waypoints_Vel_Controller
{
public:
Waypoints_Vel_Controller(ros::NodeHandle *nh);
protected:
ros::NodeHandle nh_;
Mavros_Commander* mavros_commander_;
actionlib::SimpleActionServer<terrain_following::waypointsAction> waypoints_server_;
actionlib::SimpleActionClient<terrain_following::terrainAction> terrain_client_;
ros::Publisher vel_setpoint_pub_;
void waypointsCallback_(const terrain_following::waypointsGoal::ConstPtr &goal);
};
#endif
|
suuhui/code | apue/processControl/prexit.c | <filename>apue/processControl/prexit.c<gh_stars>0
#include "../apueerr.h"
#include <sys/wait.h>
void pr_exit(int status)
{
if(WIFEXITED(status))
printf("normal termination, exit status = %d\n", WEXITSTATUS(status));
else if(WIFSIGNALED(status))
printf("abnormal termination, signal number = %d%s\n", WTERMSIG(status),
#ifdef WCOREDUMP
WCOREDUMP(status) ? " (core file generated" : "";
#else
"");
#endif
else if(WIFSTOPPEN(status))
printf("child stopped, signal number = %d\n", WSTOPSIG(status));
}
|
suuhui/code | apue/env/geten.c | <reponame>suuhui/code<filename>apue/env/geten.c
#include <stdio.h>
#include <stdlib.h>
int main()
{
const char *key = "PWD";
char *val;
int i = setenv("MY", "name", 1);
val = getenv("PATH");
printf("%s\n", val);
return 0;
}
|
suuhui/code | ComputerSystem/netp/hex2dd.c | <gh_stars>0
#include <csapp.h>
int main(int argc, char **argv)
{
struct in_addr inaddr;
unsigned int addr;
if(2 != argc) {
fprintf(stderr, "Usage %s <hex number>\n", argv[0]);
exit(0);
}
sscanf(argv[1], "%x", &addr);
inaddr.s_addr = htonl(addr);
printf("%d\n", htonl(addr));
printf("%s\n", inet_ntoa(inaddr));
}
|
suuhui/code | apue/signal/pr_mask.c | <filename>apue/signal/pr_mask.c
#include "../apueerr.h"
void pr_mask(const char *str);
int main()
{
}
void pr_mask(const char *str)
{
sigset_t sigset;
int errno_save;
errno_save = errno;
if(sigprocmask(0, NULL, &sigset) < 0)
err_ret("sigprocmask error");
else {
printf("%s", str);
if(sigismember(&sigset, SIGINT))
printf("SIGINT");
if(sigismember(&sigset, SIGQUIT))
printf("SIGQUIT");
if(sigismember(&sigset, SIGUSR1))
printf("SIGUSR1");
if(sigismember(&sigset, SIGALRM))
printf("SIGALRM");
printf("\n");
}
errno = errno_save;
}
|
suuhui/code | ComputerSystem/netp/hostinfo.c | #include <csapp.h>
int main(int argc, char **argv)
{
struct in_addr addr;
struct hostent *hostp;
char **pp;
if(2 != argc) {
fprintf(stderr, "Usage: %s <domain name or dotted-decimal>\n", argv[1]);
exit(0);
}
if(inet_aton(argv[1], &addr) == 0)
hostp = gethostbyname(argv[1]);
else
hostp = gethostbyaddr((const char *)&addr, sizeof(addr), AF_INET);
printf("official hostname is: %s\n", hostp->h_name);
for(pp = hostp->h_aliases; *pp != NULL; pp++)
printf("alias: %s\n", *pp);
for(pp = hostp->h_addr_list; *pp != NULL; pp++) {
addr.s_addr = ((struct in_addr *)*pp)->s_addr;
printf("address: %s\n", inet_ntoa(addr));
}
exit(0);
}
|
suuhui/code | ComputerSystem/prom/test43.c | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
char *getLine()
{
char buf[8];
char *result;
gets(buf);
result = malloc(strlen(buf));
strcpy(result, buf);
return result;
}
int main()
{
char *s;
s = getLine();
printf("%s\n", s);
}
|
suuhui/code | apue/env/jmp.c | <reponame>suuhui/code<gh_stars>0
#include "../apueerr.h"
#include <setjmp.h>
static void f1(int, int, int, int);
static void f2(void);
static jmp_buf jmpbuf;
static int globval;
int main(void)
{
int autoval;
register int regival;
volatile int volaval;
static int statval;
globval = 1;
autoval = 2;
regival = 3;
volaval = 4;
statval = 5;
if(setjmp(jmpbuf) != 0) {
printf("after longjmp:\n");
printf("glovalval = %d; autoval = %d; regival = %d; volaval = %d; statval = %d.\n", globval, autoval, regival, volaval, statval);
//f1(autoval, regival, volaval, statval);
exit(0);
}
globval = 95;
autoval = 96;
regival = 97;
volaval = 98;
statval = 99;
f1(autoval, regival, volaval, statval);
exit(0);
}
static void f1(int i, int j, int k, int l)
{
printf("in f1():\n");
printf("glovalval = %d; autoval = %d; regival = %d; volaval = %d; statval = %d.\n", globval, i, j, k, l);
f2();
}
static void f2(void)
{
longjmp(jmpbuf, 1);
}
|
suuhui/code | apue/apue.h | #ifndef _APUE_H
#define _APUE_H
#define _XOPEN_SOURCE 600 /* Single UNIX Specification, Version 3 */
#include <sys/types.h> /* some systems still require this */
#include <sys/stat.h>
#include <sys/termios.h> /* for winsize */
#ifndef TIOCGWINSZ
#include <sys/ioctl.h>
#endif
#include <stdio.h> /* for convenience */
#include <stdlib.h> /* for convenience */
#include <stddef.h> /* for offsetof */
#include <string.h> /* for convenience */
#include <unistd.h> /* for convenience */
#include <signal.h> /* for SIG_ERR */
#include <sys/wait.h>
#define MAXLINE 4096 /* max line length */
/*
* Default file access permissions for new files.
*/
#define FILE_MODE (S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH)
/*
* Default permissions for new directories.
*/
#define DIR_MODE (FILE_MODE | S_IXUSR | S_IXGRP | S_IXOTH)
typedef void Sigfunc(int); /* for signal handlers */
#if defined(SIG_IGN) && !defined(SIG_ERR)
#define SIG_ERR ((Sigfunc *)-1)
#endif
#define min(a,b) ((a) < (b) ? (a) : (b))
#define max(a,b) ((a) > (b) ? (a) : (b))
/*
* Prototypes for our own functions.
*/
char *path_alloc(int *); /* Figure 2.15 */
long open_max(void); /* Figure 2.16 */
void clr_fl(int, int); /* Figure 3.11 */
void set_fl(int, int); /* Figure 3.11 */
void pr_exit(int); /* Figure 8.5 */
void pr_mask(const char *); /* Figure 10.14 */
Sigfunc *signal_intr(int, Sigfunc *); /* Figure 10.19 */
int tty_cbreak(int); /* Figure 18.20 */
int tty_raw(int); /* Figure 18.20 */
int tty_reset(int); /* Figure 18.20 */
void tty_atexit(void); /* Figure 18.20 */
#ifdef ECHO /* only if <termios.h> has been included */
struct termios *tty_termios(void); /* Figure 18.20 */
#endif
void sleep_us(unsigned int); /* Exercise 14.6 */
ssize_t readn(int, void *, size_t); /* Figure 14.29 */
ssize_t writen(int, const void *, size_t); /* Figure 14.29 */
void daemonize(const char *); /* Figure 13.1 */
int s_pipe(int *); /* Figures 17.6 and 17.13 */
int recv_fd(int, ssize_t (*func)(int,
const void *, size_t));/* Figures 17.21 and 17.23 */
int send_fd(int, int); /* Figures 17.20 and 17.22 */
int send_err(int, int,
const char *); /* Figure 17.19 */
int serv_listen(const char *); /* Figures 17.10 and 17.15 */
int serv_accept(int, uid_t *); /* Figures 17.11 and 17.16 */
int cli_conn(const char *); /* Figures 17.12 and 17.17 */
int buf_args(char *, int (*func)(int,
char **)); /* Figure 17.32 */
int ptym_open(char *, int); /* Figures 19.8, 19.9, and 19.10 */
int ptys_open(char *); /* Figures 19.8, 19.9, and 19.10 */
#ifdef TIOCGWINSZ
pid_t pty_fork(int *, char *, int, const struct termios *,
const struct winsize *); /* Figure 19.11 */
#endif
int lock_reg(int, int, int, off_t, int, off_t); /* Figure 14.5 */
#define read_lock(fd, offset, whence, len) \
lock_reg((fd), F_SETLK, F_RDLCK, (offset), (whence), (len))
#define readw_lock(fd, offset, whence, len) \
lock_reg((fd), F_SETLKW, F_RDLCK, (offset), (whence), (len))
#define write_lock(fd, offset, whence, len) \
lock_reg((fd), F_SETLK, F_WRLCK, (offset), (whence), (len))
#define writew_lock(fd, offset, whence, len) \
lock_reg((fd), F_SETLKW, F_WRLCK, (offset), (whence), (len))
#define un_lock(fd, offset, whence, len) \
lock_reg((fd), F_SETLK, F_UNLCK, (offset), (whence), (len))
pid_t lock_test(int, int, off_t, int, off_t); /* Figure 14.6 */
#define is_read_lockable(fd, offset, whence, len) \
(lock_test((fd), F_RDLCK, (offset), (whence), (len)) == 0)
#define is_write_lockable(fd, offset, whence, len) \
(lock_test((fd), F_WRLCK, (offset), (whence), (len)) == 0)
void err_dump(const char *, ...); /* Appendix B */
void err_msg(const char *, ...);
void err_quit(const char *, ...);
void err_exit(int, const char *, ...);
void err_ret(const char *, ...);
void err_sys(const char *, ...);
void log_msg(const char *, ...); /* Appendix B */
void log_open(const char *, int, int);
void log_quit(const char *, ...);
void log_ret(const char *, ...);
void log_sys(const char *, ...);
void TELL_WAIT(void); /* parent/child from Section 8.9 */
void TELL_PARENT(pid_t);
void TELL_CHILD(pid_t);
void WAIT_PARENT(void);
void WAIT_CHILD(void);
#endif /* _APUE_H */
|
suuhui/code | apue/stdIO/ungetch.c | #include "../apueerr.h"
int main()
{
int sum = 0;
int num;
char ch;
while(scanf("%d", &num) == 1){
sum += num;
while((ch = getchar()) == ' ');
if(ch == '\n')
break;
ungetc(ch, stdin);
}
printf("sum is %d\n", sum);
printf("last char is %c\n", ch);
exit(0);
}
|
suuhui/code | apue/fileAndDir/chdir.c | #include "../apueerr.h"
int main()
{
char *path;
int size;
if(chdir("/tmp") < 0)
err_sys("chdir failed");
path = path_alloc(&size);
if(getcwd(path, size) == NULL)
err_sys("getcwd failed");
printf("cwd = %s\n", path);
exit(0);
}
|
suuhui/code | dsaa/list/test.c | #include <stdio.h>
typedef struct tnode *Treeptr;
typedef struct tnode {
char *word;
int count;
Treeptr *left;
} treenode;
int main()
{
int i = sizeof(treenode);
return 0;
}
|
suuhui/code | apue/fileAndDir/umask.c | <gh_stars>0
#include "../apueerr.h"
#include <fcntl.h>
#define RWRWRW S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH
int main()
{
umask(0);
if(creat("foo", RWRWRW) < 0)
err_sys("creat foo error!\n");
umask(S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH);
if(creat("bar", RWRWRW) < 0)
err_sys("creat bar error!\n");
exit(0);
}
|
suuhui/code | ComputerSystem/conc/echoserver.c | <filename>ComputerSystem/conc/echoserver.c
#include <csapp.h>
void echo(int connfd);
void sigchld_handler(int flag)
{
while(waitpid(-1, 0, WNOHANG) > 0)
;
return;
}
int main(int argc, char **argv)
{
int listenfd, connfd, port;
socklen_t clientlen = sizeof(struct sockaddr_in);
struct sockaddr_in clientaddr;
struct hostent *hp;
char *haddrp;
if(2 != argc) {
fprintf(stderr, "Usage: %s <port>\n", argv[0]);
exit(0);
}
port = atoi(argv[1]);
Signal(SIGCHLD, sigchld_handler);
listenfd = Open_listenfd(port);
while(1) {
connfd = Accept(listenfd, (SA *)&clientaddr, &clientlen);
if(Fork() == 0) {
Close(listenfd);
hp = Gethostbyaddr((const char *)&clientaddr.sin_addr.s_addr,
sizeof(clientaddr.sin_addr.s_addr), AF_INET);
haddrp = inet_ntoa(clientaddr.sin_addr);
printf("server connected to %s (%s)\n", hp->h_name, haddrp);
echo(connfd);
Close(connfd);
exit(0);
}
Close(connfd);
}
exit(0);
}
|
suuhui/code | apue/thread/deadlock.c | #include <stdio.h>
#include <stdlib.h>
#include <pthread.h>
#define NHASH 29
#define HASH(id) (((unsigned long)id) % NHASH)
struct foo *fh[NHASH];
pthread_mutex_t hashlock = PTHREAD_MUTEX_INITIALIZER;
struct foo {
int f_count;
pthread_mutex_t f_lock;
int f_id;
struct foo *f_next;
};
struct foo *foo_alloc(int id)
{
struct foo *fp;
int idx;
if((fp = malloc(sizeof(struct foo))) != NULL) {
fp->f_count = 1;
fp->f_id = id;
if(pthread_mutex_init(&fp->f_lock, NULL) != 0) {
free(fp);
return NULL;
}
idx = HASH(id);
pthread_mutex_lock(&hashlock);
fp->f_next = fh[idx];
fh[idx] = fp;
pthread_mutex_lock(&fp->f_lock);
pthread_mutex_unlock(&hashlock);
pthread_mutex_unlock(&fp->f_lock);
}
return fp;
}
void foo_hold(struct foo *fp)
{
pthread_mutex_lock(&fp->f_lock);
fp->f_count++;
pthread_mutex_unlock(&fp->f_lock);
}
struct foo *foo_find(int id)
{
struct foo *fp;
pthread_mutex_lock(&hashlock);
for ((fp = fh[HASH(id)]); fp != NULL; fp = fp->f_next) {
if(fp->f_id == id) {
foo_hold(fp);
break;
}
}
pthread_mutex_unlock(&hashlock);
return fp;
}
void foo_rele(struct foo *fp)
{
struct foo *tfp;
int idx;
pthread_mutex_lock(&fp->f_lock);
if(fp->f_count == 1) {
pthread_mutex_unlock(&fp->f_lock);
pthread_mutex_lock(&hashlock);
pthread_mutex_lock(&fp->f_lock);
if(fp->f_count != 1) {
fp->f_count--;
pthread_mutex_unlock(&fp->f_lock);
pthread_mutex_unlock(&hashlock);
return;
}
idx = HASH(fp->f_id);
tfp = fh[idx];
if(tfp == fp) {
fh[idx] = fp->f_next;
} else {
while (tfp->f_next != fp)
tfp = tfp->f_next;
tfp->f_next = fp->f_next;
}
pthread_mutex_unlock(&hashlock);
pthread_mutex_unlock(&fp->f_lock);
pthread_mutex_destroy(&fp->f_lock);
free(fp);
} else {
fp->f_count--;
pthread_mutex_unlock(&fp->f_lock);
}
}
int main()
{
struct foo *fp, *fp2;
fp = foo_alloc(1);
foo_hold(fp);
fp2 = foo_find(1);
foo_rele(fp);
foo_rele(fp);
printf("%d\n", fp->f_count);
return 0;
}
|
suuhui/code | ComputerSystem/netp/test.c | <filename>ComputerSystem/netp/test.c
#include <csapp.h>
#define M 128
int main()
{
int fd;
char *buf;
int i = 0;
rio_t rio;
fd = open("hex2dd.c", O_RDONLY, 0);
printf("fd is %d\n", fd);
Rio_readinitb(&rio, fd);
//rio_readnb(&rio, buf, 10240);
i = rio_readlineb(&rio, buf, M);
while(strcmp(buf, "{\n")) {
printf("%s", buf);
i = Rio_readlineb(&rio, buf, M);
}
while(i != 0) {
printf("%s", buf);
i = Rio_readlineb(&rio, buf, M);
}
Rio_readlineb(&rio, buf, M);
printf("last: %s", buf);
}
|
suuhui/code | apue/apueerr.h | <gh_stars>0
#include "apue.h"
#include <errno.h> /* for definition of errno */
#include <stdarg.h> /* ISO C variable aruments */
static void err_doit(int, int, const char *, va_list);
/*
* Nonfatal error related to a system call.
* Print a message and return.
*/
void
err_ret(const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
err_doit(1, errno, fmt, ap);
va_end(ap);
}
/*
* Fatal error related to a system call.
* Print a message and terminate.
*/
void
err_sys(const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
err_doit(1, errno, fmt, ap);
va_end(ap);
exit(1);
}
/*
* Fatal error unrelated to a system call.
* Error code passed as explict parameter.
* Print a message and terminate.
*/
void
err_exit(int error, const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
err_doit(1, error, fmt, ap);
va_end(ap);
exit(1);
}
/*
* Fatal error related to a system call.
* Print a message, dump core, and terminate.
*/
void
err_dump(const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
err_doit(1, errno, fmt, ap);
va_end(ap);
abort(); /* dump core and terminate */
exit(1); /* shouldn't get here */
}
/*
* Nonfatal error unrelated to a system call.
* Print a message and return.
*/
void
err_msg(const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
err_doit(0, 0, fmt, ap);
va_end(ap);
}
/*
* Fatal error unrelated to a system call.
* Print a message and terminate.
*/
void
err_quit(const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
err_doit(0, 0, fmt, ap);
va_end(ap);
exit(1);
}
/*
* Print a message and return to caller.
* Caller specifies "errnoflag".
*/
static void
err_doit(int errnoflag, int error, const char *fmt, va_list ap)
{
char buf[MAXLINE];
vsnprintf(buf, MAXLINE, fmt, ap);
if (errnoflag)
snprintf(buf+strlen(buf), MAXLINE-strlen(buf), ": %s",
strerror(error));
strcat(buf, " \n");
fflush(stdout); /* in case stdout and stderr are the same */
fputs(buf, stderr);
fflush(NULL); /* flushes all stdio output streams */
}
#ifdef PATH_MAX
static int pathmax = PATH_MAX;
#else
static int pathmax = 0;
#endif
#define SUSV3 200112L
static long posix_version = 0;
/* If PATH_MAX is indeterminate, no guarantee this is adequate */
#define PATH_MAX_GUESS 1024
char *
path_alloc(int *sizep) /* also return allocated size, if nonnull */
{
char *ptr;
int size;
if (posix_version == 0)
posix_version = sysconf(_SC_VERSION);
if (pathmax == 0) { /* first time through */
errno = 0;
if ((pathmax = pathconf("/", _PC_PATH_MAX)) < 0) {
if (errno == 0)
pathmax = PATH_MAX_GUESS; /* it's indeterminate */
else
err_sys("pathconf error for _PC_PATH_MAX");
} else {
pathmax++; /* add one since it's relative to root */
}
}
if (posix_version < SUSV3)
size = pathmax + 1;
else
size = pathmax;
if ((ptr = malloc(size)) == NULL)
err_sys("malloc error for pathname");
if (sizep != NULL)
*sizep = size;
return(ptr);
}
void pr_exit(int status)
{
if(WIFEXITED(status))
printf("normal termination, exit status = %d\n", WEXITSTATUS(status));
else if(WIFSIGNALED(status))
printf("abnormal termination, signal number = %d%s\n", WTERMSIG(status),
#ifdef WCOREDUMP
WCOREDUMP(status) ? " (core file generated" : "";
#else
"");
#endif
else if(WIFSTOPPED(status))
printf("child stopped, signal number = %d\n", WSTOPSIG(status));
}
|
suuhui/code | apue/fileAndDir/ftw.c | <reponame>suuhui/code
#include "../apueerr.h"
#include <dirent.h>
#include <limits.h>
/* function type that is called for each filename */
typedef int Myfunc(const char *, const struct stat *, int);
static Myfunc myfunc;
static int ftw(char *, Myfunc *);
static int dopath(Myfunc *);
static long nreg, ndir, nblk, nchr, nfifo, nslink, nsock, ntot;
int main(int argc, char **argv)
{
int ret;
if(argc != 2)
err_quit("Usage: ftw.exe <start-filename>\n");
ret = ftw(argv[1], myfunc);
ntot = nreg + ndir + nblk + nchr + nfifo + nslink + nsock;
if(ntot == 0)
ntot = 1;
printf("regular files = %7ld, %5.2f %%\n", nreg, nreg*100.0/ntot);
printf("directory fhles = %7ld, %5.2f %%\n", ndir, ndir*100.0/ntot);
printf("block files = %7ld, %5.2f %%\n", nblk, nblk*100.0/ntot);
printf("char specials = %7ld, %5.2f %%\n", nchr, nchr*100.0/ntot);
printf("FIFOS files = %7ld, %5.2f %%\n", nfifo, nfifo*100.0/ntot);
printf("symbolic files = %7ld, %5.2f %%\n", nslink, nslink*100.0/ntot);
printf("sockets files = %7ld, %5.2f %%\n", nsock, nsock*100.0/ntot);
exit(ret);
}
#define FTW_F 1 /* file */
#define FTW_D 2 /* directory*/
#define FTW_DNR 3 /* directory that can't be read */
#define FTW_NS 4 /* file that we can't stat */
static char *fullpath;
static int ftw(char *pathname, Myfunc *func)
{
int len;
fullpath = path_alloc(&len); /* malloc's for PATH_MAX+1 bytes */
strncpy(fullpath, pathname, len);
fullpath[len - 1] = 0;
return (dopath(func));
}
static int dopath(Myfunc *func)
{
struct stat statbuf;
struct dirent *dirp;
DIR *dp;
int ret;
char *ptr;
if(lstat(fullpath, &statbuf) < 0)
return (func(fullpath, &statbuf, FTW_NS));
if(S_ISDIR(statbuf.st_mode) == 0)
return (func(fullpath, &statbuf, FTW_F));
if((ret = func(fullpath, &statbuf, FTW_D) != 0))
return ret;
ptr = fullpath + strlen(fullpath);
*ptr++ = '/';
*ptr = 0;
if((dp = opendir(fullpath)) == NULL)
return (func(fullpath, &statbuf, FTW_DNR));
while((dirp = readdir(dp)) != NULL) {
if(strcmp(dirp->d_name, ".") == 0 || strcmp(dirp->d_name, "..") == 0)
continue;
strcpy(ptr, dirp->d_name);
if((ret = dopath(func) != 0))
break;
}
ptr[-1] = 0;
if(closedir(dp) < 0)
err_ret("cnat't close directory %s", fullpath);
return (ret);
}
static int myfunc(const char *pathname, const struct stat *statptr, int type)
{
switch(type) {
case FTW_F:
switch(statptr->st_mode & S_IFMT) {
case S_IFREG: nreg++; break;
case S_IFBLK: nblk++; break;
case S_IFCHR: nchr++; break;
case S_IFIFO: nfifo++; break;
case S_IFLNK: nslink++; break;
case S_IFSOCK: nsock++; break;
case S_IFDIR:
err_dump("for S_IFDIR is %s", pathname);
}
break;
case FTW_D:
ndir++;
break;
case FTW_DNR:
err_ret("can't be read dir %s", pathname);
break;
case FTW_NS:
err_ret("stat error for %s", pathname);
break;
default:
err_dump("unknow type %d for pathname %s", type, pathname);
}
return 0;
}
|
suuhui/code | dsaa/list/main.c | #include "./list.c"
int main()
{
lnode *head, node;
createList(head);
int i;
for(i=1; i<6; i++) {
node = createNode(i);
insert(node, head);
}
node = head->next;
while(node != NULL) {
print("%d\n", node->element);
node = node->next;
}
return 0;
}
|
suuhui/code | dsaa/list/list.h | #ifndef _LIST_H
#define _LIST_H
typedef int eType;
typedef struct node *Lnode;
typedef struct node
{
eType element;
Lnode *next;
}lnode;
typedef struct lnode *PtrToLnode;
typedef PtrToLnode list;
typedef PtrToLnode position;
lnode createNode(eType x);
lnode createList(lnode l);
list makeEmpty(list l);
int isEmpty(list l);
int isLast(position p, list l);
position find(eType x, list l);
eType ldelete(eType x, list l);
position findPrevious(eType x, list l);
void insert(position p, list l);
void deleteList(list l);
position header(list l);
position first(list l);
position advance(position p);
eType retrieve(position p);
#endif /* _LIST_H_ */
|
suuhui/code | pearls/sort/isort.c | #include <stdio.h>
void isort1(int *arr);
void isort2(int *arr);
int main()
{
int arr[] = {8,3,5,2,5,6,1};
int n = 7;
int i;
isort1(arr);
for(i=0; i<n; i++){
printf("%d ", arr[i]);
}
printf("\n");
}
void isort1(int *arr)
{
int i,j,t;
int n = 7;
int count = 0;
for(i=1; i<n; i++) {
printf("i is :%d and arr[%d] is : %d\n", i, i,arr[i]);
for(j=i; j>0 && arr[j-1] > arr[j]; j--) {
count++;
t = arr[j-1];
arr[j-1] = arr[j];
arr[j] = t;
printf("#### j is :%d and arr[%d] is : %d\n", j, j, arr[j]);
}
}
printf("count : %d\n", count);
}
void isort2(int *arr)
{
int i,j,t;
int count = 0;
int n = 7;
for(i=1; i<n; i++){
t = arr[i];
for(j=i; j>0 && arr[j-1] > t; j--) {
count++;
arr[j] = arr[j-1];
}
arr[j] = t;
}
printf("count : %d\n", count);
}
|
suuhui/code | apue/thread/thread_clean.c | #include "../apueerr.h"
#include <pthread.h>
void cleanup(void *arg)
{
printf("clean up: %s\n", (char *)arg);
}
void *thr_fn1(void *arg)
{
printf("thread 1 start\n");
pthread_cleanup_push(cleanup, "thread 1 first handler");
pthread_cleanup_push(cleanup, "thread 1 second handler");
printf("thread 1 push complete\n");
if(arg)
return ((void *)1);
pthread_cleanup_pop(0);
pthread_cleanup_pop(0);
return ((void *)1);
}
void *thr_fn2(void *arg)
{
printf("thread 2 start\n");
pthread_cleanup_push(cleanup, "thread 2 first handler");
pthread_cleanup_push(cleanup, "thread 2 second handler");
printf("thread 1 push complete\n");
if(arg)
pthread_exit((void *)2);
pthread_cleanup_pop(0);
pthread_cleanup_pop(0);
return ((void *)2);
}
int main(void)
{
int err;
pthread_t tid1, tid2;
void *tret;
err = pthread_create(&tid1, NULL, thr_fn1, (void *)1);
if(err != 0)
err_exit(err,"thread 1 create err");
err = pthread_create(&tid2, NULL, thr_fn2, (void *)2);
if(err != 0)
err_exit(err,"thread 2 create err");
err = pthread_join(tid1, &tret);
if(err != 0)
err_exit(err,"can't join with thread 1");
printf("thread 1 exit code %ld\n", (long)tret);
err = pthread_join(tid2, &tret);
if(err != 0)
err_exit(err,"can't join with thread 2");
printf("thread 2 exit code %ld\n", (long)tret);
exit(0);
}
|
suuhui/code | pearls/sort/rand.c | <filename>pearls/sort/rand.c<gh_stars>0
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
int randint(int l, int u);
int main(int argc, char *argv[])
{
if(argc != 3) {
printf("Usage: ./randint.exe [lower] [upper]\n");
return (1);
}
int t = randint(atoi(argv[1]), atoi(argv[2]));
printf("rand num is : %d\n", t);
return 0;
}
int randint(int l, int u)
{
srand(time(0));
return (rand() % (u - l + 1)) + l;
}
|
suuhui/code | pearls/sort/hsort.c | #include <stdio.h>
#include "../func.c"
#define M 21
#define MAX 1000
void swap(int *tree, int i, int j);
void hsort(int *tree, int n);
void siftup(int *tree, int n);
void siftdown(int *tree, int n);
int main()
{
int i, tree[M] = {12,23,23,76,3,686,2,43,1,78,89,60,30,70,68,489,40,9,11,12,34};
hsort(tree, M);
for(i=1; i<M; i++)
printf("%d\n", tree[i]);
printf("\n");
}
void hsort(int * tree, int n)
{
int i;
for(i=2; i<n; i++)
siftup(tree, i);
/* note: n is 21, when ergodic array from top ,init i=n-1 */
for(i=n-1; i>1; i--) {
swap(tree, 1, i);
siftdown(tree, i-1);
}
}
void siftup(int *tree, int n)
{
int i = n, p = i / 2;
while(tree[p] > tree[i] && i != 1) {
swap(tree, p, i);
i = p;
p = i / 2;
}
}
void siftdown(int *tree, int n)
{
int i = 1;
int c;
while(1) {
c = 2 * i;
if (c > n)
break;
if(c + 1 <= n && tree[c] > tree[c+1])
c++;
if(tree[c] > tree[i])
break;
swap(tree, c, i);
i = c;
}
}
void swap(int *tree, int i, int j)
{
}
int t;
t = tree[i];
tree[i] = tree[j];
tree[j] = t;
}
|
suuhui/code | apue/processControl/fork.c | #include "../apueerr.h"
int globvar = 6;
char buf[] = "write to stdout\n";
int main()
{
int var;
pid_t pid;
var = 88;
if(write(STDOUT_FILENO, buf, sizeof(buf) - 1) != sizeof(buf) - 1)
err_sys("write error");
printf("before fork\n");
if((pid = fork()) < 0)
err_sys("fork error");
else if(pid == 0) {
globvar++;
var++;
} else {
sleep(2);
}
printf("pid = %ld, glob = %d, var = %d\n", (long)getpid(), globvar, var);
return 0;
}
|
suuhui/code | pearls/func.c | <gh_stars>0
#define N 1000000
#define BITSPERWORD 32
#define SHIFT 5
#define MASK 0x1F
int bita[1 + N / BITSPERWORD];
int a[N];
int com(const void *a, const void *b)
{
return *(int *)a - *(int *)b;
}
int randInt(int min, int max)
{
srand((unsigned) time(NULL));
return min + rand() % (max - min + 1);
}
int swap_num(int *a, int *b)
{
int t;
t = *a;
*a = *b;
*b = t;
}
void set(int i)
{
bita[i >> SHIFT] != (1 << (i & MASK));
}
void clr(int i)
{
bita[i >> SHIFT] &= ~(1 << (i & MASK));
}
int test(int i)
{
return bita[i >> SHIFT] & (1 << (i & MASK));
}
|
suuhui/code | ComputerSystem/netp/echoserver.c | <reponame>suuhui/code<filename>ComputerSystem/netp/echoserver.c<gh_stars>0
#include <csapp.h>
void echo(int connfd);
int main(int argc, char **argv)
{
int listenfd, connfd, port, clientlen;
struct sockaddr_in clientaddr;
struct hostent *hp;
char *haddrp;
if(2 != argc) {
fprintf(stderr, "Usage: %s <port>\n", argv[0]);
exit(0);
}
port = atoi(argv[1]);
listenfd = Open_listenfd(port);
while(1) {
clientlen = sizeof(clientaddr);
connfd = Accept(listenfd, (SA *)&clientaddr, &clientlen);
hp = Gethostbyaddr((const char *)&clientaddr.sin_addr.s_addr,
sizeof(clientaddr.sin_addr.s_addr), AF_INET);
haddrp = inet_ntoa(clientaddr.sin_addr);
printf("server connected to %s (%s)\n", hp->h_name, haddrp);
echo(connfd);
Close(connfd);
}
exit(0);
}
|
suuhui/code | apue/fileIO/mydup2.c | <gh_stars>0
#include "../apueerr.h"
#include <fcntl.h>
#define MAX 4096
int mydup2(int filedes, int fileds2);
int main(int argc, char **argv)
{
int fd;
if(argc != 3) {
err_sys("Usage: ./mydup2 <file> <newfd>\n");
return -1;
}
char *name = argv[1];
fd = open((const char *)name, O_RDWR);
if(fd < 0) {
err_sys("open file error\n");
return -1;
}
fd = mydup2(fd, atoi(argv[2]));
printf("new fd is %d\n", fd);
return fd;
}
int mydup2(int f1, int f2)
{
int stack[MAX];
int top = 0;
int fd;
int i;
if(f1 > MAX || f2 < 0) {
err_sys("invalid fd");
return -1;
}
while((fd = dup(1)) < f2) {
if(fd == -1) {
err_sys("dup error");
return -1;
}
stack[top++] = fd;
}
for(i=0; i<top; i++) {
close(stack[i]);
}
return f2;
}
|
suuhui/code | apue/fileAndDir/link.c | <filename>apue/fileAndDir/link.c
#include "../apueerr.h"
int main(int argc, char **argv)
{
int ret;
ret = link("./stat.c", "stat.link");
printf("%d\n", ret);
}
|
suuhui/code | apue/signal/alerm.c | #include "../apueerr.h"
static void sig_alrm(int);
int main()
{
int n;
if(signal(SIGALRM, sig_alrm) == SIG_ERR){
err_sys("signam(SIGALRM) error");
}
alarm(10);
for(n=0; n<10; n++)
;
sleep(3);
n = alarm(2);
printf("%d\n", n);
sleep(3);
n = alarm(1);
printf("%d\n", n);
}
static void sig_alrm(int signo)
{
printf("alarm signal handle\n");
}
|
suuhui/code | comm/intToHex.c | #include <stdio.h>
#include <stdlib.h>
char *inttohex(long a);
char *buf;
int main(int argc, char *argv)
{
long n;
printf("please enter a number: ");
scanf("%ld", &n);
inttohex(n);
printf("%s\n", buf);
}
char *inttohex(long a)
{
int mod = 0;
int i=0;
long n;
do {
mod = a % 16;
buf[i] = mod < 10 ? mod + '0' : mod - 10 + 'A';
a = (long)(a / 16);
i++;
} while(a != 0);
buf[i] = '\0';
return buf;
}
|
suuhui/code | ComputerSystem/prom/fact_while.c | #include <stdio.h>
//int fact_while(int n);
/*
int main()
{
int r = fact_while(5);
printf("%d\n", r);
}
*/
int fact_while(int n)
{
int result = 1;
while(n > 1) {
result *= n;
n--;
}
return result;
}
|
suuhui/code | ComputerSystem/netp/dd2hex.c | #include <csapp.h>
int main(int argc, char **argv)
{
struct in_addr inaddr;
unsigned int hex;
if(2 != argc) {
fprintf(stderr, "Usage %s <dotted-decimal>\n", argv[0]);
exit(0);
}
if(inet_aton(argv[1], &inaddr) == 0) {
fprintf(stderr, "inet_aton error");
exit(0);
}
hex = ntohl(inaddr.s_addr);
printf("0x%x\n", hex);
}
|
suuhui/code | apue/fileAndDir/stat.c | <filename>apue/fileAndDir/stat.c
#include "../apueerr.h"
int main()
{
struct stat st;
stat("test.txt", &st);
if(S_ISREG(st.st_mode))
printf("regular file\n");
return 0;
}
|
suuhui/code | apue/fileAndDir/rename.c | <reponame>suuhui/code
#include "../apueerr.h"
int main(int argc, char **argv)
{
if(argc != 3)
err_quit("Usage: rename.exe <oldname> <newname>\n");
const char *oldname = argv[1];
const char *newname = argv[2];
int ret;
ret = rename(oldname, newname);
printf("ret is %d\n", ret);
exit(0);
}
|
suuhui/code | dsaa/list/list.c | <reponame>suuhui/code
#include "../comm.h"
#include "./list.h"
Lnode createNode(eType x)
{
Lnode l;
l = malloc(sizeof(lnode));
if(l == NULL) {
printf("malloc error");
exit(1);
}
l->element = x;
l->next = NULL;
return l;
}
lnode createList(lnode l)
{
l = createNode(0);
return l;
}
/* Return true if l is empty */
int isEmpty(list l)
{
return l->next == NULL;
}
/* Return true if p is the last position in list l */
int isLast(position p, list l)
{
if(isEmpty(l))
return FALSE;
return p->next == NULL;
}
/* return the postion of x in l; NULL if not found */
position find(eType x, list l)
{
if(isEmpty(l))
return FALSE;
position p;
p = l->next;
while(p != NULL && p->elemet == x)
p = p->next;
return p;
}
eType ldelete(eType x, list l)
{
position p, tmpCell;
p = findPrevious(x, l);
if(!isLast(p, l)) {
tmpCell = p->next;
p->next = tmpCell->next;
free(tmpCell);
}
}
position findPrevious(eType x, list l)
{
if(isEmpty(l))
return FALSE;
position p;
p = l->next;
while(p->next != NULL && p->next->element != x)
p = p->next;
return p;
}
void insert(position p, position head)
{
position tmp = head->next;
position q = head;
while(tmp != NULL) {
q = tmp;
tmp = tmp->next;
}
q->next = p;
p->next = NULL;
}
void deleteList(list l)
{
position p, tmpNode;
p = l->next;
l->next = NULL;
while(p != NULL) {
tmpNode = p->next;
free(p);
p = tmpNode;
}
}
postion header(list l)
{
return l->next;
}
eType retrieve(postion p)
{
return 1;
}
|
suuhui/code | ComputerSystem/netp/tiny.c | #include <csapp.h>
void doit(int fd);
void read_requesthdrs(rio_t *rp);
void read_requestbody(rio_t *rp);
int parse_uri(char *uri, char *filename, char *cgiargs);
void get_filetype(char *filename, char *filetype);
void serve_static(int fd, char *filename, int filesize);
void serve_dynamic(int fd, char *filename, char *cgiargs);
void clienterror(int fd, char *cause, char *errnum, char *shortmsg, char *longmsg);
int main(int argc, char **argv)
{
int listenfd, connfd, port, clientlen;
struct sockaddr_in clientaddr;
if(2 != argc) {
fprintf(stderr, "Usage: %s <port>\n", argv[0]);
exit(0);
}
port = atoi(argv[1]);
listenfd = Open_listenfd(port);
while(1) {
clientlen = sizeof(clientaddr);
connfd = Accept(listenfd, (SA *)&clientaddr, &clientlen);
doit(connfd);
Close(connfd);
}
}
void doit(int fd)
{
int is_static;
struct stat sbuf;
char buf[MAXLINE], method[MAXLINE], uri[MAXLINE], version[MAXLINE];
char filename[MAXLINE], cgiargs[MAXLINE];
rio_t rio;
Rio_readinitb(&rio, fd);
Rio_readlineb(&rio, buf, MAXLINE);
sscanf(buf, "%s %s %s", method, uri, version);
if(strcasecmp(method, "GET") == 0){
} else if(strcasecmp(method, "POST") == 0){
} else {
clienterror(fd, method, "501", "Not Implemented",
"Tiny does not implement this method");
return;
}
printf("####################request start########################\r\n");
/* output first request header */
printf("%s\n", buf);
/* output other request header */
read_requesthdrs(&rio);
//read_requestbody(&rio);
is_static = parse_uri(uri, filename, cgiargs);
if(stat(filename, &sbuf) < 0) {
clienterror(fd, filename, "404", "Not Found",
"Tiny could't found this file");
return;
}
if(is_static) {
/* Is this file regular file or Is user has permission to read */
if(!S_ISREG(sbuf.st_mode) || !(S_IRUSR & sbuf.st_mode)) {
clienterror(fd, filename, "403", "Forbidden",
"Tiny couldn't read the file");
return;
}
serve_static(fd, filename, sbuf.st_size);
} else {
if(!S_ISREG(sbuf.st_mode) || !(S_IXUSR & sbuf.st_mode)) {
clienterror(fd, filename, "403", "Forbidden",
"Tiny couldn't read the file");
return;
}
serve_dynamic(fd, filename, cgiargs);
}
}
void clienterror(int fd, char *cause, char *errnum, char *shortmsg,
char *longmsg)
{
char buf[MAXLINE], body[MAXLINE];
sprintf(body, "<html><title>Tiny Error</title>");
sprintf(body, "%s<body bgcolor=""#fff""\r\n", body);
sprintf(body, "%s%s: %s\r\n", body, errnum, shortmsg);
sprintf(body, "%s<p>%s: %s\r\n", body, longmsg, cause);
sprintf(body, "%s<hr><em>The Tiny Web Server</em>\r\n", body);
sprintf(buf, "HTTP/1.0 %s %s\r\n", errnum, shortmsg);
Rio_writen(fd, buf, strlen(buf));
sprintf(buf, "Content-type: text/html\r\n");
Rio_writen(fd, buf, strlen(buf));
sprintf(buf, "Content-length: %d\r\n\r\n", (int)strlen(body));
Rio_writen(fd, buf, strlen(buf));
Rio_writen(fd, body, strlen(body));
}
void read_requesthdrs(rio_t *rp)
{
char buf[MAXLINE];
int n;
n = Rio_readlineb(rp, buf, MAXLINE);
while(strcmp(buf, "\r\n")) {
printf("%s", buf);
n = Rio_readlineb(rp, buf, MAXLINE);
}
printf("#####################request end#######################\r\n");
return;
}
void read_requestbody(rio_t *rp)
{
char buf[MAXLINE];
int n; //size of read
printf("######################request body##########################\r\n");
n = Rio_readlineb(rp, buf, MAXLINE);
printf("%s", buf);
while(n != 0) {
n = Rio_readlineb(rp, buf, MAXLINE);
printf("%s", buf);
}
printf("####################request body end#####################\r\n");
return;
}
int parse_uri(char *uri, char *filename, char *cgiargs)
{
char *ptr;
if(!strstr(uri, "cgi-bin")) {
strcpy(cgiargs, "");
strcpy(filename, ".");
strcat(filename, uri);
if(uri[strlen(uri) - 1] == '/')
strcat(filename, "home.html");
return 1;
} else {
ptr = index(uri, '?');
if(ptr) {
strcpy(cgiargs, ptr + 1);
*ptr = '\0';
} else {
strcpy(cgiargs, "");
}
strcpy(filename, ".");
strcat(filename, uri);
return 0;
}
}
void serve_static(int fd, char *filename, int filesize)
{
int srcfd;
char *srcp, filetype[MAXLINE], buf[MAXBUF];
/* Send response headers to client */
get_filetype(filename, filetype);
sprintf(buf, "HTTP/1.0 200 OK\r\n");
sprintf(buf, "%sServer: Tiny Web Server\r\n", buf);
sprintf(buf, "%sContent-length: %d\r\n", buf, filesize);
sprintf(buf, "%sContent-type: %s\r\n\r\n", buf, filetype);
Rio_writen(fd, buf, strlen(buf));
printf("Response headers:\n");
printf("%s", buf);
/* Send response body to client */
srcfd = Open(filename, O_RDONLY, 0);
srcp = Mmap(0, filesize, PROT_READ, MAP_PRIVATE, srcfd, 0);
Close(srcfd);
Rio_writen(fd, srcp, filesize);
Munmap(srcp, filesize);
}
void get_filetype(char *filename, char *filetype)
{
if(strstr(filename, ".html"))
strcpy(filetype, "text/html");
else if(strstr(filename, ".gif"))
strcpy(filetype, "image/gif");
else if(strstr(filename, ".jpg"))
strcpy(filetype, "image/jpeg");
else if(strstr(filename, ".mp4"))
strcpy(filetype, "video/mp4");
else if(strstr(filename, ".mp3"))
strcpy(filetype, "audio/mpeg");
else
strcpy(filetype, "text/plain");
}
void serve_dynamic(int fd, char *filename, char *cgiargs)
{
char buf[MAXLINE], *emptylist[] = {NULL};
sprintf(buf, "HTTP/1.0 200 OK \r\n");
Rio_writen(fd, buf, strlen(buf));
sprintf(buf, "Server: Tiny Web Server\r\n");
Rio_writen(fd, buf, strlen(buf));
if(Fork() == 0) {
setenv("QUERY_STRING", cgiargs, 1);
Dup2(fd, STDOUT_FILENO);
Execve(filename, emptylist, environ);
}
Wait(NULL);
}
|
suuhui/code | ComputerSystem/conc/echo.c | <reponame>suuhui/code
#include <csapp.h>
void echo(int connfd)
{
size_t n;
char buf[MAXLINE];
rio_t rio;
Rio_readinitb(&rio, connfd);
while((n = Rio_readlineb(&rio, buf, MAXLINE)) != 0) {
printf("server received %d bytes\n", n);
printf("server received %s\n", buf);
Rio_writen(connfd, buf, n);
}
}
|
suuhui/code | pearls/sort/qsort.c | <filename>pearls/sort/qsort.c<gh_stars>0
#include <stdio.h>
void qsort(int *arr, int l, int u);
void swap(int *arr, int i, int j);
int main()
{
int arr[] = {5,2,67,3,77,32,64,23,86};
int n = 9;
qsort(arr, 0, n);
int i;
for(i=0; i<n; i++)
printf("%d\n", arr[i]);
printf("\n");
}
void qsort(int *arr, int l, int u)
{
printf("#############################################\n");
printf("l is: %d +++ u is: %d\n", l, u);
if(l >= u)
return;
int i=l, j=u, t=arr[l];
int tmp = 0;
int k=0;
while(i <= j) {
i++;
while(i<=j && arr[i]<t)
i++;
printf("new more than {%d} i is: %d and arr[%d] is: %d\n", t, i, i, arr[i]);
while(i<=j && arr[j]>t)
j--;
printf("new less than {%d} j is: %d and arr[%d] is: %d\n", t, j, j, arr[j]);
if(i > j)
break;
printf("swap i:%d and j:%d\n", i, j);
swap(arr, i, j);
}
swap(arr, l, j);
printf("-------------------\n");
for(k=0; k<9; k++)
printf("%d\n", arr[k]);
printf("-------------------\n");
printf("#############################################\n");
qsort(arr, l, j-1);
qsort(arr, j+1, u);
}
void swap(int *arr, int i, int j)
{
int t;
t = arr[i];
arr[i] = arr[j];
arr[j] = t;
}
|
suuhui/code | dsaa/introduction/select.c | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#define MAX 1000
int randint(int, int);
int main()
{
int arr[MAX];
int i;
int r = 0; //rand int;
int t = 0; //template number, for exchange;
int mid = MAX / 2; //
for(i=0; i<MAX; i++){
printf("%d\n", i);
arr[i] = i;
}
for(i=0; i<MAX; i++){
r = randint(i, MAX);
printf("%d\n", r);
t = arr[i];
arr[i] = arr[r];
arr[r] = t;
}
for(i=0; i<MAX; i++){
printf("%d\n", arr[i]);
}
}
int randint(int l, int u)
{
srand(time(0));
return (int)(rand()%(u - l + 1) + l);
}
|
suuhui/code | apue/fileIO/readAndWrite.c | <gh_stars>0
#include "../apueerr.h"
#include <fcntl.h>
#define MAX 1024
int main()
{
char buf[MAX];
int fd1, fd2;
const char *s1 = "hello world!\r\n";
const char *s2 = "world hello!\r\n";
fd1 = open("./a.txt", O_RDWR | O_APPEND);
fd2 = open("./a.txt", O_RDWR | O_APPEND);
write(fd1, (const void *)s1, strlen(s1));
write(fd2, (const void *)s2, strlen(s2));
return 0;
}
|
suuhui/code | tcpl/func.c | <filename>tcpl/func.c<gh_stars>0
#include <stdio.h>
#include <math.h>
int atoi(char *s);
int htoi(char *s);
int main(int argc, char *argv[])
{
char *s = "123";
int n = atoi(s);
printf("%d\n", n);
}
int atoi(char *s)
{
int n = 0;
int i = 0;
for(; s[i] >= '0' && s[i] <='9'; ++i) {
n = n * 10 + (s[i] - '0');
}
return n;
}
int htoi(char *s)
{
}
|
suuhui/code | ComputerSystem/conc/echoclient.c | <gh_stars>0
#include <csapp.h>
int main(int argc, char **argv)
{
int clientfd, port;
char *host, buf[MAXLINE];
rio_t rio;
if(3 != argc) {
fprintf(stderr, "Usage: %s <host> <port>\n", argv[0]);
exit(0);
}
host = argv[1];
port = atoi(argv[2]);
clientfd = Open_clientfd(host, port);
Rio_readinitb(&rio, clientfd);
while(Fgets(buf, MAXLINE, stdin) != NULL) {
Rio_writen(clientfd, buf, strlen(buf));
Rio_readlineb(&rio, buf, MAXLINE);
Fputs(buf, stdout);
}
Close(clientfd);
exit(0);
}
|
suuhui/code | apue/fileIO/fcntl.c | <reponame>suuhui/code
#include "../apueerr.h"
#include <fcntl.h>
int main(int argc, char **argv)
{
int val;
if(argc != 2)
err_quit("Usage: a.out <descriptor#>");
if((val = fcntl(atoi(argv[1]), F_GETFL, 0)) < 0)
err_sys("fcntl error for fd %d\n", atoi(argv[1]));
/* use mask word O_ACCMODE get access mode bit */
switch(val & O_ACCMODE) {
case O_RDONLY:
printf("read only");
break;
case O_WRONLY:
printf("write only");
break;
case O_RDWR:
printf("read write");
break;
default:
err_dump("unknown access mode");
}
if(val & O_APPEND)
printf(", append");
if(val &O_NONBLOCK)
printf(", nonblocking");
#if defined(O_SYNC)
if(val & O_SYNC)
printf(", synchronous write");
#endif
#if !defined(_POSIX_C_SOURCE) && defined(O_FSYNC)
if(val & O_FSYNC)
printf(", synchronous writes");
#endif
putchar('\n');
exit(0);
}
/* flags are file status flags to turn on
* Don't simply use F_SETFD or F_SETFL
* You should get flag first, and then modify it, at last
* set new flag
*/
void set_fl(int fd, int flags)
{
int val;
if((val = fcntl(fd, F_GETFL, 0)) < 0)
err_sys("fcntl F_GETFL error");
val |= flags; /* turn on flags */
if(fcntl(fd, F_SETFL, val) < 0)
err_sys("fcntl F_SETFL error");
}
/*
* turn of flags
*/
void clr_fl(int fd, int flags)
{
int val;
if((val = fcntl(fd, F_GETFL, 0)) < 0)
err_sys("fcntl F_GETFL error");
val &= ~flags; /* turn off flags */
if(fcntl(fd, F_SETFL, val) < 0)
err_sys("fcntl F_SETFL error");
}
|
suuhui/code | apue/processControl/compet.c | #include "../apueerr.h"
static void charatatime(char *);
int main(void)
{
pid_t pid;
if((pid = fork()) < 0){
err_sys("fork error");
} else if(pid == 0) {
charatatime("output from child\n");
} else {
charatatime("output from parent\n");
}
}
static void charatatime(char *s)
{
char *ptr;
int c;
setbuf(stdout, NULL);
for(ptr = s; (c = *ptr++) != 0; )
putc(c, stdout);
}
|
andyxwxu/tinyos | tos/chips/msp432/include/msp432p401r_classic.h | <filename>tos/chips/msp432/include/msp432p401r_classic.h
/******************************************************************************
*
* Copyright (C) 2012 - 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* MSP432P401R Register Definitions
*
* This file includes MSP430 style component and register definitions
* for legacy components re-used in MSP432
*
* File creation date: 2016-08-16
*
******************************************************************************/
#ifndef __MSP432P401R_CLASSIC_H__
#define __MSP432P401R_CLASSIC_H__
/* Use standard integer types with explicit width */
#include <stdint.h>
#include <msp_compatibility.h>
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************
* Device memory map *
******************************************************************************/
#define __MAIN_MEMORY_START__ (0x00000000) /*!< Main Flash memory start address */
#define __MAIN_MEMORY_END__ (0x0003FFFF) /*!< Main Flash memory end address */
#define __BSL_MEMORY_START__ (0x00202000) /*!< BSL memory start address */
#define __BSL_MEMORY_END__ (0x00203FFF) /*!< BSL memory end address */
#define __SRAM_START__ (0x20000000) /*!< SRAM memory start address */
#define __SRAM_END__ (0x2000FFFF) /*!< SRAM memory end address */
/******************************************************************************
* MSP-format peripheral registers *
******************************************************************************/
/******************************************************************************
* AES256 Registers
******************************************************************************/
#define AESACTL0 (HWREG16(0x40003C00)) /*!< AES Accelerator Control Register 0 */
#define AESACTL1 (HWREG16(0x40003C02)) /*!< AES Accelerator Control Register 1 */
#define AESASTAT (HWREG16(0x40003C04)) /*!< AES Accelerator Status Register */
#define AESAKEY (HWREG16(0x40003C06)) /*!< AES Accelerator Key Register */
#define AESADIN (HWREG16(0x40003C08)) /*!< AES Accelerator Data In Register */
#define AESADOUT (HWREG16(0x40003C0A)) /*!< AES Accelerator Data Out Register */
#define AESAXDIN (HWREG16(0x40003C0C)) /*!< AES Accelerator XORed Data In Register */
#define AESAXIN (HWREG16(0x40003C0E)) /*!< AES Accelerator XORed Data In Register */
/* Register offsets from AES256_BASE address */
#define OFS_AESACTL0 (0x0000) /*!< AES Accelerator Control Register 0 */
#define OFS_AESACTL1 (0x0002) /*!< AES Accelerator Control Register 1 */
#define OFS_AESASTAT (0x0004) /*!< AES Accelerator Status Register */
#define OFS_AESAKEY (0x0006) /*!< AES Accelerator Key Register */
#define OFS_AESADIN (0x0008) /*!< AES Accelerator Data In Register */
#define OFS_AESADOUT (0x000A) /*!< AES Accelerator Data Out Register */
#define OFS_AESAXDIN (0x000C) /*!< AES Accelerator XORed Data In Register */
#define OFS_AESAXIN (0x000E) /*!< AES Accelerator XORed Data In Register */
/******************************************************************************
* CAPTIO0 Registers
******************************************************************************/
#define CAPTIO0CTL (HWREG16(0x4000540E)) /*!< Capacitive Touch IO x Control Register */
/* Register offsets from CAPTIO0_BASE address */
#define OFS_CAPTIO0CTL (0x000E) /*!< Capacitive Touch IO x Control Register */
#define CAPTIO0CTL_L (HWREG8_L(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */
#define CAPTIO0CTL_H (HWREG8_H(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */
/******************************************************************************
* CAPTIO1 Registers
******************************************************************************/
#define CAPTIO1CTL (HWREG16(0x4000580E)) /*!< Capacitive Touch IO x Control Register */
/* Register offsets from CAPTIO1_BASE address */
#define OFS_CAPTIO1CTL (0x000E) /*!< Capacitive Touch IO x Control Register */
#define CAPTIO1CTL_L (HWREG8_L(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */
#define CAPTIO1CTL_H (HWREG8_H(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */
/******************************************************************************
* COMP_E0 Registers
******************************************************************************/
#define CE0CTL0 (HWREG16(0x40003400)) /*!< Comparator Control Register 0 */
#define CE0CTL1 (HWREG16(0x40003402)) /*!< Comparator Control Register 1 */
#define CE0CTL2 (HWREG16(0x40003404)) /*!< Comparator Control Register 2 */
#define CE0CTL3 (HWREG16(0x40003406)) /*!< Comparator Control Register 3 */
#define CE0INT (HWREG16(0x4000340C)) /*!< Comparator Interrupt Control Register */
#define CE0IV (HWREG16(0x4000340E)) /*!< Comparator Interrupt Vector Word Register */
/* Register offsets from COMP_E0_BASE address */
#define OFS_CE0CTL0 (0x0000) /*!< Comparator Control Register 0 */
#define OFS_CE0CTL1 (0x0002) /*!< Comparator Control Register 1 */
#define OFS_CE0CTL2 (0x0004) /*!< Comparator Control Register 2 */
#define OFS_CE0CTL3 (0x0006) /*!< Comparator Control Register 3 */
#define OFS_CE0INT (0x000C) /*!< Comparator Interrupt Control Register */
#define OFS_CE0IV (0x000E) /*!< Comparator Interrupt Vector Word Register */
/******************************************************************************
* COMP_E1 Registers
******************************************************************************/
#define CE1CTL0 (HWREG16(0x40003800)) /*!< Comparator Control Register 0 */
#define CE1CTL1 (HWREG16(0x40003802)) /*!< Comparator Control Register 1 */
#define CE1CTL2 (HWREG16(0x40003804)) /*!< Comparator Control Register 2 */
#define CE1CTL3 (HWREG16(0x40003806)) /*!< Comparator Control Register 3 */
#define CE1INT (HWREG16(0x4000380C)) /*!< Comparator Interrupt Control Register */
#define CE1IV (HWREG16(0x4000380E)) /*!< Comparator Interrupt Vector Word Register */
/* Register offsets from COMP_E1_BASE address */
#define OFS_CE1CTL0 (0x0000) /*!< Comparator Control Register 0 */
#define OFS_CE1CTL1 (0x0002) /*!< Comparator Control Register 1 */
#define OFS_CE1CTL2 (0x0004) /*!< Comparator Control Register 2 */
#define OFS_CE1CTL3 (0x0006) /*!< Comparator Control Register 3 */
#define OFS_CE1INT (0x000C) /*!< Comparator Interrupt Control Register */
#define OFS_CE1IV (0x000E) /*!< Comparator Interrupt Vector Word Register */
/******************************************************************************
* CRC32 Registers
******************************************************************************/
#define CRC32DI (HWREG16(0x40004000)) /*!< Data Input for CRC32 Signature Computation */
#define CRC32DIRB (HWREG16(0x40004004)) /*!< Data In Reverse for CRC32 Computation */
#define CRC32INIRES_LO (HWREG16(0x40004008)) /*!< CRC32 Initialization and Result, lower 16 bits */
#define CRC32INIRES_HI (HWREG16(0x4000400A)) /*!< CRC32 Initialization and Result, upper 16 bits */
#define CRC32RESR_LO (HWREG16(0x4000400C)) /*!< CRC32 Result Reverse, lower 16 bits */
#define CRC32RESR_HI (HWREG16(0x4000400E)) /*!< CRC32 Result Reverse, Upper 16 bits */
#define CRC16DI (HWREG16(0x40004010)) /*!< Data Input for CRC16 computation */
#define CRC16DIRB (HWREG16(0x40004014)) /*!< CRC16 Data In Reverse */
#define CRC16INIRES (HWREG16(0x40004018)) /*!< CRC16 Initialization and Result register */
#define CRC16RESR (HWREG16(0x4000401E)) /*!< CRC16 Result Reverse */
/* Register offsets from CRC32_BASE address */
#define OFS_CRC32DI (0x0000) /*!< Data Input for CRC32 Signature Computation */
#define OFS_CRC32DIRB (0x0004) /*!< Data In Reverse for CRC32 Computation */
#define OFS_CRC32INIRES_LO (0x0008) /*!< CRC32 Initialization and Result, lower 16 bits */
#define OFS_CRC32INIRES_HI (0x000A) /*!< CRC32 Initialization and Result, upper 16 bits */
#define OFS_CRC32RESR_LO (0x000C) /*!< CRC32 Result Reverse, lower 16 bits */
#define OFS_CRC32RESR_HI (0x000E) /*!< CRC32 Result Reverse, Upper 16 bits */
#define OFS_CRC16DI (0x0010) /*!< Data Input for CRC16 computation */
#define OFS_CRC16DIRB (0x0014) /*!< CRC16 Data In Reverse */
#define OFS_CRC16INIRES (0x0018) /*!< CRC16 Initialization and Result register */
#define OFS_CRC16RESR (0x001E) /*!< CRC16 Result Reverse */
/******************************************************************************
* DIO Registers
******************************************************************************/
#define PAIN (HWREG16(0x40004C00)) /*!< Port A Input */
#define PAOUT (HWREG16(0x40004C02)) /*!< Port A Output */
#define PADIR (HWREG16(0x40004C04)) /*!< Port A Direction */
#define PAREN (HWREG16(0x40004C06)) /*!< Port A Resistor Enable */
#define PADS (HWREG16(0x40004C08)) /*!< Port A Drive Strength */
#define PASEL0 (HWREG16(0x40004C0A)) /*!< Port A Select 0 */
#define PASEL1 (HWREG16(0x40004C0C)) /*!< Port A Select 1 */
#define P1IV (HWREG16(0x40004C0E)) /*!< Port 1 Interrupt Vector Register */
#define PASELC (HWREG16(0x40004C16)) /*!< Port A Complement Select */
#define PAIES (HWREG16(0x40004C18)) /*!< Port A Interrupt Edge Select */
#define PAIE (HWREG16(0x40004C1A)) /*!< Port A Interrupt Enable */
#define PAIFG (HWREG16(0x40004C1C)) /*!< Port A Interrupt Flag */
#define P2IV (HWREG16(0x40004C1E)) /*!< Port 2 Interrupt Vector Register */
#define PBIN (HWREG16(0x40004C20)) /*!< Port B Input */
#define PBOUT (HWREG16(0x40004C22)) /*!< Port B Output */
#define PBDIR (HWREG16(0x40004C24)) /*!< Port B Direction */
#define PBREN (HWREG16(0x40004C26)) /*!< Port B Resistor Enable */
#define PBDS (HWREG16(0x40004C28)) /*!< Port B Drive Strength */
#define PBSEL0 (HWREG16(0x40004C2A)) /*!< Port B Select 0 */
#define PBSEL1 (HWREG16(0x40004C2C)) /*!< Port B Select 1 */
#define P3IV (HWREG16(0x40004C2E)) /*!< Port 3 Interrupt Vector Register */
#define PBSELC (HWREG16(0x40004C36)) /*!< Port B Complement Select */
#define PBIES (HWREG16(0x40004C38)) /*!< Port B Interrupt Edge Select */
#define PBIE (HWREG16(0x40004C3A)) /*!< Port B Interrupt Enable */
#define PBIFG (HWREG16(0x40004C3C)) /*!< Port B Interrupt Flag */
#define P4IV (HWREG16(0x40004C3E)) /*!< Port 4 Interrupt Vector Register */
#define PCIN (HWREG16(0x40004C40)) /*!< Port C Input */
#define PCOUT (HWREG16(0x40004C42)) /*!< Port C Output */
#define PCDIR (HWREG16(0x40004C44)) /*!< Port C Direction */
#define PCREN (HWREG16(0x40004C46)) /*!< Port C Resistor Enable */
#define PCDS (HWREG16(0x40004C48)) /*!< Port C Drive Strength */
#define PCSEL0 (HWREG16(0x40004C4A)) /*!< Port C Select 0 */
#define PCSEL1 (HWREG16(0x40004C4C)) /*!< Port C Select 1 */
#define P5IV (HWREG16(0x40004C4E)) /*!< Port 5 Interrupt Vector Register */
#define PCSELC (HWREG16(0x40004C56)) /*!< Port C Complement Select */
#define PCIES (HWREG16(0x40004C58)) /*!< Port C Interrupt Edge Select */
#define PCIE (HWREG16(0x40004C5A)) /*!< Port C Interrupt Enable */
#define PCIFG (HWREG16(0x40004C5C)) /*!< Port C Interrupt Flag */
#define P6IV (HWREG16(0x40004C5E)) /*!< Port 6 Interrupt Vector Register */
#define PDIN (HWREG16(0x40004C60)) /*!< Port D Input */
#define PDOUT (HWREG16(0x40004C62)) /*!< Port D Output */
#define PDDIR (HWREG16(0x40004C64)) /*!< Port D Direction */
#define PDREN (HWREG16(0x40004C66)) /*!< Port D Resistor Enable */
#define PDDS (HWREG16(0x40004C68)) /*!< Port D Drive Strength */
#define PDSEL0 (HWREG16(0x40004C6A)) /*!< Port D Select 0 */
#define PDSEL1 (HWREG16(0x40004C6C)) /*!< Port D Select 1 */
#define P7IV (HWREG16(0x40004C6E)) /*!< Port 7 Interrupt Vector Register */
#define PDSELC (HWREG16(0x40004C76)) /*!< Port D Complement Select */
#define PDIES (HWREG16(0x40004C78)) /*!< Port D Interrupt Edge Select */
#define PDIE (HWREG16(0x40004C7A)) /*!< Port D Interrupt Enable */
#define PDIFG (HWREG16(0x40004C7C)) /*!< Port D Interrupt Flag */
#define P8IV (HWREG16(0x40004C7E)) /*!< Port 8 Interrupt Vector Register */
#define PEIN (HWREG16(0x40004C80)) /*!< Port E Input */
#define PEOUT (HWREG16(0x40004C82)) /*!< Port E Output */
#define PEDIR (HWREG16(0x40004C84)) /*!< Port E Direction */
#define PEREN (HWREG16(0x40004C86)) /*!< Port E Resistor Enable */
#define PEDS (HWREG16(0x40004C88)) /*!< Port E Drive Strength */
#define PESEL0 (HWREG16(0x40004C8A)) /*!< Port E Select 0 */
#define PESEL1 (HWREG16(0x40004C8C)) /*!< Port E Select 1 */
#define P9IV (HWREG16(0x40004C8E)) /*!< Port 9 Interrupt Vector Register */
#define PESELC (HWREG16(0x40004C96)) /*!< Port E Complement Select */
#define PEIES (HWREG16(0x40004C98)) /*!< Port E Interrupt Edge Select */
#define PEIE (HWREG16(0x40004C9A)) /*!< Port E Interrupt Enable */
#define PEIFG (HWREG16(0x40004C9C)) /*!< Port E Interrupt Flag */
#define P10IV (HWREG16(0x40004C9E)) /*!< Port 10 Interrupt Vector Register */
#define PJIN (HWREG16(0x40004D20)) /*!< Port J Input */
#define PJOUT (HWREG16(0x40004D22)) /*!< Port J Output */
#define PJDIR (HWREG16(0x40004D24)) /*!< Port J Direction */
#define PJREN (HWREG16(0x40004D26)) /*!< Port J Resistor Enable */
#define PJDS (HWREG16(0x40004D28)) /*!< Port J Drive Strength */
#define PJSEL0 (HWREG16(0x40004D2A)) /*!< Port J Select 0 */
#define PJSEL1 (HWREG16(0x40004D2C)) /*!< Port J Select 1 */
#define PJSELC (HWREG16(0x40004D36)) /*!< Port J Complement Select */
#define P1IN (HWREG8(0x40004C00)) /*!< Port 1 Input */
#define P2IN (HWREG8(0x40004C01)) /*!< Port 2 Input */
#define P2OUT (HWREG8(0x40004C03)) /*!< Port 2 Output */
#define P1OUT (HWREG8(0x40004C02)) /*!< Port 1 Output */
#define P1DIR (HWREG8(0x40004C04)) /*!< Port 1 Direction */
#define P2DIR (HWREG8(0x40004C05)) /*!< Port 2 Direction */
#define P1REN (HWREG8(0x40004C06)) /*!< Port 1 Resistor Enable */
#define P2REN (HWREG8(0x40004C07)) /*!< Port 2 Resistor Enable */
#define P1DS (HWREG8(0x40004C08)) /*!< Port 1 Drive Strength */
#define P2DS (HWREG8(0x40004C09)) /*!< Port 2 Drive Strength */
#define P1SEL0 (HWREG8(0x40004C0A)) /*!< Port 1 Select 0 */
#define P2SEL0 (HWREG8(0x40004C0B)) /*!< Port 2 Select 0 */
#define P1SEL1 (HWREG8(0x40004C0C)) /*!< Port 1 Select 1 */
#define P2SEL1 (HWREG8(0x40004C0D)) /*!< Port 2 Select 1 */
#define P1SELC (HWREG8(0x40004C16)) /*!< Port 1 Complement Select */
#define P2SELC (HWREG8(0x40004C17)) /*!< Port 2 Complement Select */
#define P1IES (HWREG8(0x40004C18)) /*!< Port 1 Interrupt Edge Select */
#define P2IES (HWREG8(0x40004C19)) /*!< Port 2 Interrupt Edge Select */
#define P1IE (HWREG8(0x40004C1A)) /*!< Port 1 Interrupt Enable */
#define P2IE (HWREG8(0x40004C1B)) /*!< Port 2 Interrupt Enable */
#define P1IFG (HWREG8(0x40004C1C)) /*!< Port 1 Interrupt Flag */
#define P2IFG (HWREG8(0x40004C1D)) /*!< Port 2 Interrupt Flag */
#define P3IN (HWREG8(0x40004C20)) /*!< Port 3 Input */
#define P4IN (HWREG8(0x40004C21)) /*!< Port 4 Input */
#define P3OUT (HWREG8(0x40004C22)) /*!< Port 3 Output */
#define P4OUT (HWREG8(0x40004C23)) /*!< Port 4 Output */
#define P3DIR (HWREG8(0x40004C24)) /*!< Port 3 Direction */
#define P4DIR (HWREG8(0x40004C25)) /*!< Port 4 Direction */
#define P3REN (HWREG8(0x40004C26)) /*!< Port 3 Resistor Enable */
#define P4REN (HWREG8(0x40004C27)) /*!< Port 4 Resistor Enable */
#define P3DS (HWREG8(0x40004C28)) /*!< Port 3 Drive Strength */
#define P4DS (HWREG8(0x40004C29)) /*!< Port 4 Drive Strength */
#define P4SEL0 (HWREG8(0x40004C2B)) /*!< Port 4 Select 0 */
#define P3SEL0 (HWREG8(0x40004C2A)) /*!< Port 3 Select 0 */
#define P3SEL1 (HWREG8(0x40004C2C)) /*!< Port 3 Select 1 */
#define P4SEL1 (HWREG8(0x40004C2D)) /*!< Port 4 Select 1 */
#define P3SELC (HWREG8(0x40004C36)) /*!< Port 3 Complement Select */
#define P4SELC (HWREG8(0x40004C37)) /*!< Port 4 Complement Select */
#define P3IES (HWREG8(0x40004C38)) /*!< Port 3 Interrupt Edge Select */
#define P4IES (HWREG8(0x40004C39)) /*!< Port 4 Interrupt Edge Select */
#define P3IE (HWREG8(0x40004C3A)) /*!< Port 3 Interrupt Enable */
#define P4IE (HWREG8(0x40004C3B)) /*!< Port 4 Interrupt Enable */
#define P3IFG (HWREG8(0x40004C3C)) /*!< Port 3 Interrupt Flag */
#define P4IFG (HWREG8(0x40004C3D)) /*!< Port 4 Interrupt Flag */
#define P5IN (HWREG8(0x40004C40)) /*!< Port 5 Input */
#define P6IN (HWREG8(0x40004C41)) /*!< Port 6 Input */
#define P5OUT (HWREG8(0x40004C42)) /*!< Port 5 Output */
#define P6OUT (HWREG8(0x40004C43)) /*!< Port 6 Output */
#define P5DIR (HWREG8(0x40004C44)) /*!< Port 5 Direction */
#define P6DIR (HWREG8(0x40004C45)) /*!< Port 6 Direction */
#define P5REN (HWREG8(0x40004C46)) /*!< Port 5 Resistor Enable */
#define P6REN (HWREG8(0x40004C47)) /*!< Port 6 Resistor Enable */
#define P5DS (HWREG8(0x40004C48)) /*!< Port 5 Drive Strength */
#define P6DS (HWREG8(0x40004C49)) /*!< Port 6 Drive Strength */
#define P5SEL0 (HWREG8(0x40004C4A)) /*!< Port 5 Select 0 */
#define P6SEL0 (HWREG8(0x40004C4B)) /*!< Port 6 Select 0 */
#define P5SEL1 (HWREG8(0x40004C4C)) /*!< Port 5 Select 1 */
#define P6SEL1 (HWREG8(0x40004C4D)) /*!< Port 6 Select 1 */
#define P5SELC (HWREG8(0x40004C56)) /*!< Port 5 Complement Select */
#define P6SELC (HWREG8(0x40004C57)) /*!< Port 6 Complement Select */
#define P5IES (HWREG8(0x40004C58)) /*!< Port 5 Interrupt Edge Select */
#define P6IES (HWREG8(0x40004C59)) /*!< Port 6 Interrupt Edge Select */
#define P5IE (HWREG8(0x40004C5A)) /*!< Port 5 Interrupt Enable */
#define P6IE (HWREG8(0x40004C5B)) /*!< Port 6 Interrupt Enable */
#define P5IFG (HWREG8(0x40004C5C)) /*!< Port 5 Interrupt Flag */
#define P6IFG (HWREG8(0x40004C5D)) /*!< Port 6 Interrupt Flag */
#define P7IN (HWREG8(0x40004C60)) /*!< Port 7 Input */
#define P8IN (HWREG8(0x40004C61)) /*!< Port 8 Input */
#define P7OUT (HWREG8(0x40004C62)) /*!< Port 7 Output */
#define P8OUT (HWREG8(0x40004C63)) /*!< Port 8 Output */
#define P7DIR (HWREG8(0x40004C64)) /*!< Port 7 Direction */
#define P8DIR (HWREG8(0x40004C65)) /*!< Port 8 Direction */
#define P7REN (HWREG8(0x40004C66)) /*!< Port 7 Resistor Enable */
#define P8REN (HWREG8(0x40004C67)) /*!< Port 8 Resistor Enable */
#define P7DS (HWREG8(0x40004C68)) /*!< Port 7 Drive Strength */
#define P8DS (HWREG8(0x40004C69)) /*!< Port 8 Drive Strength */
#define P7SEL0 (HWREG8(0x40004C6A)) /*!< Port 7 Select 0 */
#define P8SEL0 (HWREG8(0x40004C6B)) /*!< Port 8 Select 0 */
#define P7SEL1 (HWREG8(0x40004C6C)) /*!< Port 7 Select 1 */
#define P8SEL1 (HWREG8(0x40004C6D)) /*!< Port 8 Select 1 */
#define P7SELC (HWREG8(0x40004C76)) /*!< Port 7 Complement Select */
#define P8SELC (HWREG8(0x40004C77)) /*!< Port 8 Complement Select */
#define P7IES (HWREG8(0x40004C78)) /*!< Port 7 Interrupt Edge Select */
#define P8IES (HWREG8(0x40004C79)) /*!< Port 8 Interrupt Edge Select */
#define P7IE (HWREG8(0x40004C7A)) /*!< Port 7 Interrupt Enable */
#define P8IE (HWREG8(0x40004C7B)) /*!< Port 8 Interrupt Enable */
#define P7IFG (HWREG8(0x40004C7C)) /*!< Port 7 Interrupt Flag */
#define P8IFG (HWREG8(0x40004C7D)) /*!< Port 8 Interrupt Flag */
#define P9IN (HWREG8(0x40004C80)) /*!< Port 9 Input */
#define P10IN (HWREG8(0x40004C81)) /*!< Port 10 Input */
#define P9OUT (HWREG8(0x40004C82)) /*!< Port 9 Output */
#define P10OUT (HWREG8(0x40004C83)) /*!< Port 10 Output */
#define P9DIR (HWREG8(0x40004C84)) /*!< Port 9 Direction */
#define P10DIR (HWREG8(0x40004C85)) /*!< Port 10 Direction */
#define P9REN (HWREG8(0x40004C86)) /*!< Port 9 Resistor Enable */
#define P10REN (HWREG8(0x40004C87)) /*!< Port 10 Resistor Enable */
#define P9DS (HWREG8(0x40004C88)) /*!< Port 9 Drive Strength */
#define P10DS (HWREG8(0x40004C89)) /*!< Port 10 Drive Strength */
#define P9SEL0 (HWREG8(0x40004C8A)) /*!< Port 9 Select 0 */
#define P10SEL0 (HWREG8(0x40004C8B)) /*!< Port 10 Select 0 */
#define P9SEL1 (HWREG8(0x40004C8C)) /*!< Port 9 Select 1 */
#define P10SEL1 (HWREG8(0x40004C8D)) /*!< Port 10 Select 1 */
#define P9SELC (HWREG8(0x40004C96)) /*!< Port 9 Complement Select */
#define P10SELC (HWREG8(0x40004C97)) /*!< Port 10 Complement Select */
#define P9IES (HWREG8(0x40004C98)) /*!< Port 9 Interrupt Edge Select */
#define P10IES (HWREG8(0x40004C99)) /*!< Port 10 Interrupt Edge Select */
#define P9IE (HWREG8(0x40004C9A)) /*!< Port 9 Interrupt Enable */
#define P10IE (HWREG8(0x40004C9B)) /*!< Port 10 Interrupt Enable */
#define P9IFG (HWREG8(0x40004C9C)) /*!< Port 9 Interrupt Flag */
#define P10IFG (HWREG8(0x40004C9D)) /*!< Port 10 Interrupt Flag */
/* Register offsets from DIO_BASE address */
#define OFS_PAIN (0x0000) /*!< Port A Input */
#define OFS_PAOUT (0x0002) /*!< Port A Output */
#define OFS_PADIR (0x0004) /*!< Port A Direction */
#define OFS_PAREN (0x0006) /*!< Port A Resistor Enable */
#define OFS_PADS (0x0008) /*!< Port A Drive Strength */
#define OFS_PASEL0 (0x000A) /*!< Port A Select 0 */
#define OFS_PASEL1 (0x000C) /*!< Port A Select 1 */
#define OFS_P1IV (0x000E) /*!< Port 1 Interrupt Vector Register */
#define OFS_PASELC (0x0016) /*!< Port A Complement Select */
#define OFS_PAIES (0x0018) /*!< Port A Interrupt Edge Select */
#define OFS_PAIE (0x001A) /*!< Port A Interrupt Enable */
#define OFS_PAIFG (0x001C) /*!< Port A Interrupt Flag */
#define OFS_P2IV (0x001E) /*!< Port 2 Interrupt Vector Register */
#define OFS_PBIN (0x0020) /*!< Port B Input */
#define OFS_PBOUT (0x0022) /*!< Port B Output */
#define OFS_PBDIR (0x0024) /*!< Port B Direction */
#define OFS_PBREN (0x0026) /*!< Port B Resistor Enable */
#define OFS_PBDS (0x0028) /*!< Port B Drive Strength */
#define OFS_PBSEL0 (0x002A) /*!< Port B Select 0 */
#define OFS_PBSEL1 (0x002C) /*!< Port B Select 1 */
#define OFS_P3IV (0x002E) /*!< Port 3 Interrupt Vector Register */
#define OFS_PBSELC (0x0036) /*!< Port B Complement Select */
#define OFS_PBIES (0x0038) /*!< Port B Interrupt Edge Select */
#define OFS_PBIE (0x003A) /*!< Port B Interrupt Enable */
#define OFS_PBIFG (0x003C) /*!< Port B Interrupt Flag */
#define OFS_P4IV (0x003E) /*!< Port 4 Interrupt Vector Register */
#define OFS_PCIN (0x0040) /*!< Port C Input */
#define OFS_PCOUT (0x0042) /*!< Port C Output */
#define OFS_PCDIR (0x0044) /*!< Port C Direction */
#define OFS_PCREN (0x0046) /*!< Port C Resistor Enable */
#define OFS_PCDS (0x0048) /*!< Port C Drive Strength */
#define OFS_PCSEL0 (0x004A) /*!< Port C Select 0 */
#define OFS_PCSEL1 (0x004C) /*!< Port C Select 1 */
#define OFS_P5IV (0x004E) /*!< Port 5 Interrupt Vector Register */
#define OFS_PCSELC (0x0056) /*!< Port C Complement Select */
#define OFS_PCIES (0x0058) /*!< Port C Interrupt Edge Select */
#define OFS_PCIE (0x005A) /*!< Port C Interrupt Enable */
#define OFS_PCIFG (0x005C) /*!< Port C Interrupt Flag */
#define OFS_P6IV (0x005E) /*!< Port 6 Interrupt Vector Register */
#define OFS_PDIN (0x0060) /*!< Port D Input */
#define OFS_PDOUT (0x0062) /*!< Port D Output */
#define OFS_PDDIR (0x0064) /*!< Port D Direction */
#define OFS_PDREN (0x0066) /*!< Port D Resistor Enable */
#define OFS_PDDS (0x0068) /*!< Port D Drive Strength */
#define OFS_PDSEL0 (0x006A) /*!< Port D Select 0 */
#define OFS_PDSEL1 (0x006C) /*!< Port D Select 1 */
#define OFS_P7IV (0x006E) /*!< Port 7 Interrupt Vector Register */
#define OFS_PDSELC (0x0076) /*!< Port D Complement Select */
#define OFS_PDIES (0x0078) /*!< Port D Interrupt Edge Select */
#define OFS_PDIE (0x007A) /*!< Port D Interrupt Enable */
#define OFS_PDIFG (0x007C) /*!< Port D Interrupt Flag */
#define OFS_P8IV (0x007E) /*!< Port 8 Interrupt Vector Register */
#define OFS_PEIN (0x0080) /*!< Port E Input */
#define OFS_PEOUT (0x0082) /*!< Port E Output */
#define OFS_PEDIR (0x0084) /*!< Port E Direction */
#define OFS_PEREN (0x0086) /*!< Port E Resistor Enable */
#define OFS_PEDS (0x0088) /*!< Port E Drive Strength */
#define OFS_PESEL0 (0x008A) /*!< Port E Select 0 */
#define OFS_PESEL1 (0x008C) /*!< Port E Select 1 */
#define OFS_P9IV (0x008E) /*!< Port 9 Interrupt Vector Register */
#define OFS_PESELC (0x0096) /*!< Port E Complement Select */
#define OFS_PEIES (0x0098) /*!< Port E Interrupt Edge Select */
#define OFS_PEIE (0x009A) /*!< Port E Interrupt Enable */
#define OFS_PEIFG (0x009C) /*!< Port E Interrupt Flag */
#define OFS_P10IV (0x009E) /*!< Port 10 Interrupt Vector Register */
#define OFS_PJIN (0x0120) /*!< Port J Input */
#define OFS_PJOUT (0x0122) /*!< Port J Output */
#define OFS_PJDIR (0x0124) /*!< Port J Direction */
#define OFS_PJREN (0x0126) /*!< Port J Resistor Enable */
#define OFS_PJDS (0x0128) /*!< Port J Drive Strength */
#define OFS_PJSEL0 (0x012A) /*!< Port J Select 0 */
#define OFS_PJSEL1 (0x012C) /*!< Port J Select 1 */
#define OFS_PJSELC (0x0136) /*!< Port J Complement Select */
#define OFS_P1IN (0x0000) /*!< Port 1 Input */
#define OFS_P2IN (0x0000) /*!< Port 2 Input */
#define OFS_P2OUT (0x0002) /*!< Port 2 Output */
#define OFS_P1OUT (0x0002) /*!< Port 1 Output */
#define OFS_P1DIR (0x0004) /*!< Port 1 Direction */
#define OFS_P2DIR (0x0004) /*!< Port 2 Direction */
#define OFS_P1REN (0x0006) /*!< Port 1 Resistor Enable */
#define OFS_P2REN (0x0006) /*!< Port 2 Resistor Enable */
#define OFS_P1DS (0x0008) /*!< Port 1 Drive Strength */
#define OFS_P2DS (0x0008) /*!< Port 2 Drive Strength */
#define OFS_P1SEL0 (0x000A) /*!< Port 1 Select 0 */
#define OFS_P2SEL0 (0x000A) /*!< Port 2 Select 0 */
#define OFS_P1SEL1 (0x000C) /*!< Port 1 Select 1 */
#define OFS_P2SEL1 (0x000C) /*!< Port 2 Select 1 */
#define OFS_P1SELC (0x0016) /*!< Port 1 Complement Select */
#define OFS_P2SELC (0x0016) /*!< Port 2 Complement Select */
#define OFS_P1IES (0x0018) /*!< Port 1 Interrupt Edge Select */
#define OFS_P2IES (0x0018) /*!< Port 2 Interrupt Edge Select */
#define OFS_P1IE (0x001A) /*!< Port 1 Interrupt Enable */
#define OFS_P2IE (0x001A) /*!< Port 2 Interrupt Enable */
#define OFS_P1IFG (0x001C) /*!< Port 1 Interrupt Flag */
#define OFS_P2IFG (0x001C) /*!< Port 2 Interrupt Flag */
#define OFS_P3IN (0x0020) /*!< Port 3 Input */
#define OFS_P4IN (0x0020) /*!< Port 4 Input */
#define OFS_P3OUT (0x0022) /*!< Port 3 Output */
#define OFS_P4OUT (0x0022) /*!< Port 4 Output */
#define OFS_P3DIR (0x0024) /*!< Port 3 Direction */
#define OFS_P4DIR (0x0024) /*!< Port 4 Direction */
#define OFS_P3REN (0x0026) /*!< Port 3 Resistor Enable */
#define OFS_P4REN (0x0026) /*!< Port 4 Resistor Enable */
#define OFS_P3DS (0x0028) /*!< Port 3 Drive Strength */
#define OFS_P4DS (0x0028) /*!< Port 4 Drive Strength */
#define OFS_P4SEL0 (0x002A) /*!< Port 4 Select 0 */
#define OFS_P3SEL0 (0x002A) /*!< Port 3 Select 0 */
#define OFS_P3SEL1 (0x002C) /*!< Port 3 Select 1 */
#define OFS_P4SEL1 (0x002C) /*!< Port 4 Select 1 */
#define OFS_P3SELC (0x0036) /*!< Port 3 Complement Select */
#define OFS_P4SELC (0x0036) /*!< Port 4 Complement Select */
#define OFS_P3IES (0x0038) /*!< Port 3 Interrupt Edge Select */
#define OFS_P4IES (0x0038) /*!< Port 4 Interrupt Edge Select */
#define OFS_P3IE (0x003A) /*!< Port 3 Interrupt Enable */
#define OFS_P4IE (0x003A) /*!< Port 4 Interrupt Enable */
#define OFS_P3IFG (0x003C) /*!< Port 3 Interrupt Flag */
#define OFS_P4IFG (0x003C) /*!< Port 4 Interrupt Flag */
#define OFS_P5IN (0x0040) /*!< Port 5 Input */
#define OFS_P6IN (0x0040) /*!< Port 6 Input */
#define OFS_P5OUT (0x0042) /*!< Port 5 Output */
#define OFS_P6OUT (0x0042) /*!< Port 6 Output */
#define OFS_P5DIR (0x0044) /*!< Port 5 Direction */
#define OFS_P6DIR (0x0044) /*!< Port 6 Direction */
#define OFS_P5REN (0x0046) /*!< Port 5 Resistor Enable */
#define OFS_P6REN (0x0046) /*!< Port 6 Resistor Enable */
#define OFS_P5DS (0x0048) /*!< Port 5 Drive Strength */
#define OFS_P6DS (0x0048) /*!< Port 6 Drive Strength */
#define OFS_P5SEL0 (0x004A) /*!< Port 5 Select 0 */
#define OFS_P6SEL0 (0x004A) /*!< Port 6 Select 0 */
#define OFS_P5SEL1 (0x004C) /*!< Port 5 Select 1 */
#define OFS_P6SEL1 (0x004C) /*!< Port 6 Select 1 */
#define OFS_P5SELC (0x0056) /*!< Port 5 Complement Select */
#define OFS_P6SELC (0x0056) /*!< Port 6 Complement Select */
#define OFS_P5IES (0x0058) /*!< Port 5 Interrupt Edge Select */
#define OFS_P6IES (0x0058) /*!< Port 6 Interrupt Edge Select */
#define OFS_P5IE (0x005A) /*!< Port 5 Interrupt Enable */
#define OFS_P6IE (0x005A) /*!< Port 6 Interrupt Enable */
#define OFS_P5IFG (0x005C) /*!< Port 5 Interrupt Flag */
#define OFS_P6IFG (0x005C) /*!< Port 6 Interrupt Flag */
#define OFS_P7IN (0x0060) /*!< Port 7 Input */
#define OFS_P8IN (0x0060) /*!< Port 8 Input */
#define OFS_P7OUT (0x0062) /*!< Port 7 Output */
#define OFS_P8OUT (0x0062) /*!< Port 8 Output */
#define OFS_P7DIR (0x0064) /*!< Port 7 Direction */
#define OFS_P8DIR (0x0064) /*!< Port 8 Direction */
#define OFS_P7REN (0x0066) /*!< Port 7 Resistor Enable */
#define OFS_P8REN (0x0066) /*!< Port 8 Resistor Enable */
#define OFS_P7DS (0x0068) /*!< Port 7 Drive Strength */
#define OFS_P8DS (0x0068) /*!< Port 8 Drive Strength */
#define OFS_P7SEL0 (0x006A) /*!< Port 7 Select 0 */
#define OFS_P8SEL0 (0x006A) /*!< Port 8 Select 0 */
#define OFS_P7SEL1 (0x006C) /*!< Port 7 Select 1 */
#define OFS_P8SEL1 (0x006C) /*!< Port 8 Select 1 */
#define OFS_P7SELC (0x0076) /*!< Port 7 Complement Select */
#define OFS_P8SELC (0x0076) /*!< Port 8 Complement Select */
#define OFS_P7IES (0x0078) /*!< Port 7 Interrupt Edge Select */
#define OFS_P8IES (0x0078) /*!< Port 8 Interrupt Edge Select */
#define OFS_P7IE (0x007A) /*!< Port 7 Interrupt Enable */
#define OFS_P8IE (0x007A) /*!< Port 8 Interrupt Enable */
#define OFS_P7IFG (0x007C) /*!< Port 7 Interrupt Flag */
#define OFS_P8IFG (0x007C) /*!< Port 8 Interrupt Flag */
#define OFS_P9IN (0x0080) /*!< Port 9 Input */
#define OFS_P10IN (0x0080) /*!< Port 10 Input */
#define OFS_P9OUT (0x0082) /*!< Port 9 Output */
#define OFS_P10OUT (0x0082) /*!< Port 10 Output */
#define OFS_P9DIR (0x0084) /*!< Port 9 Direction */
#define OFS_P10DIR (0x0084) /*!< Port 10 Direction */
#define OFS_P9REN (0x0086) /*!< Port 9 Resistor Enable */
#define OFS_P10REN (0x0086) /*!< Port 10 Resistor Enable */
#define OFS_P9DS (0x0088) /*!< Port 9 Drive Strength */
#define OFS_P10DS (0x0088) /*!< Port 10 Drive Strength */
#define OFS_P9SEL0 (0x008A) /*!< Port 9 Select 0 */
#define OFS_P10SEL0 (0x008A) /*!< Port 10 Select 0 */
#define OFS_P9SEL1 (0x008C) /*!< Port 9 Select 1 */
#define OFS_P10SEL1 (0x008C) /*!< Port 10 Select 1 */
#define OFS_P9SELC (0x0096) /*!< Port 9 Complement Select */
#define OFS_P10SELC (0x0096) /*!< Port 10 Complement Select */
#define OFS_P9IES (0x0098) /*!< Port 9 Interrupt Edge Select */
#define OFS_P10IES (0x0098) /*!< Port 10 Interrupt Edge Select */
#define OFS_P9IE (0x009A) /*!< Port 9 Interrupt Enable */
#define OFS_P10IE (0x009A) /*!< Port 10 Interrupt Enable */
#define OFS_P9IFG (0x009C) /*!< Port 9 Interrupt Flag */
#define OFS_P10IFG (0x009C) /*!< Port 10 Interrupt Flag */
/******************************************************************************
* EUSCI_A0 Registers
******************************************************************************/
#define UCA0CTLW0 (HWREG16(0x40001000)) /*!< eUSCI_Ax Control Word Register 0 */
#define UCA0CTLW0_SPI (HWREG16(0x40001000)) /*!< eUSCI_Ax Control Word Register 0 */
#define UCA0CTLW1 (HWREG16(0x40001002)) /*!< eUSCI_Ax Control Word Register 1 */
#define UCA0BRW (HWREG16(0x40001006)) /*!< eUSCI_Ax Baud Rate Control Word Register */
#define UCA0BRW_SPI (HWREG16(0x40001006)) /*!< eUSCI_Ax Bit Rate Control Register 1 */
#define UCA0MCTLW (HWREG16(0x40001008)) /*!< eUSCI_Ax Modulation Control Word Register */
#define UCA0STATW (HWREG16(0x4000100A)) /*!< eUSCI_Ax Status Register */
#define UCA0STATW_SPI (HWREG16(0x4000100A))
#define UCA0RXBUF (HWREG16(0x4000100C)) /*!< eUSCI_Ax Receive Buffer Register */
#define UCA0RXBUF_SPI (HWREG16(0x4000100C)) /*!< eUSCI_Ax Receive Buffer Register */
#define UCA0TXBUF (HWREG16(0x4000100E)) /*!< eUSCI_Ax Transmit Buffer Register */
#define UCA0TXBUF_SPI (HWREG16(0x4000100E)) /*!< eUSCI_Ax Transmit Buffer Register */
#define UCA0ABCTL (HWREG16(0x40001010)) /*!< eUSCI_Ax Auto Baud Rate Control Register */
#define UCA0IRCTL (HWREG16(0x40001012)) /*!< eUSCI_Ax IrDA Control Word Register */
#define UCA0IE (HWREG16(0x4000101A)) /*!< eUSCI_Ax Interrupt Enable Register */
#define UCA0IE_SPI (HWREG16(0x4000101A)) /*!< eUSCI_Ax Interrupt Enable Register */
#define UCA0IFG (HWREG16(0x4000101C)) /*!< eUSCI_Ax Interrupt Flag Register */
#define UCA0IFG_SPI (HWREG16(0x4000101C)) /*!< eUSCI_Ax Interrupt Flag Register */
#define UCA0IV (HWREG16(0x4000101E)) /*!< eUSCI_Ax Interrupt Vector Register */
#define UCA0IV_SPI (HWREG16(0x4000101E)) /*!< eUSCI_Ax Interrupt Vector Register */
/* Register offsets from EUSCI_A0_BASE address */
#define OFS_UCA0CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */
#define OFS_UCA0CTLW0_SPI (0x0000) /*!< eUSCI_Ax Control Word Register 0 */
#define OFS_UCA0CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */
#define OFS_UCA0BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */
#define OFS_UCA0BRW_SPI (0x0006) /*!< eUSCI_Ax Bit Rate Control Register 1 */
#define OFS_UCA0MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */
#define OFS_UCA0STATW (0x000A) /*!< eUSCI_Ax Status Register */
#define OFS_UCA0STATW_SPI (0x000A)
#define OFS_UCA0RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */
#define OFS_UCA0RXBUF_SPI (0x000C) /*!< eUSCI_Ax Receive Buffer Register */
#define OFS_UCA0TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */
#define OFS_UCA0TXBUF_SPI (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */
#define OFS_UCA0ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */
#define OFS_UCA0IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */
#define OFS_UCA0IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */
#define OFS_UCA0IE_SPI (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */
#define OFS_UCA0IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */
#define OFS_UCA0IFG_SPI (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */
#define OFS_UCA0IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */
#define OFS_UCA0IV_SPI (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */
#define UCA0CTL0 (HWREG8_L(UCA0CTLW0)) /* eUSCI_Ax Control 0 */
#define UCA0CTL1 (HWREG8_H(UCA0CTLW0)) /* eUSCI_Ax Control 1 */
#define UCA0BR0 (HWREG8_L(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 0 */
#define UCA0BR1 (HWREG8_H(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 1 */
#define UCA0IRTCTL (HWREG8_L(UCA0IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
#define UCA0IRRCTL (HWREG8_H(UCA0IRCTL)) /* eUSCI_Ax IrDA Receive Control */
/******************************************************************************
* EUSCI_A1 Registers
******************************************************************************/
#define UCA1CTLW0 (HWREG16(0x40001400)) /*!< eUSCI_Ax Control Word Register 0 */
#define UCA1CTLW0_SPI (HWREG16(0x40001400)) /*!< eUSCI_Ax Control Word Register 0 */
#define UCA1CTLW1 (HWREG16(0x40001402)) /*!< eUSCI_Ax Control Word Register 1 */
#define UCA1BRW (HWREG16(0x40001406)) /*!< eUSCI_Ax Baud Rate Control Word Register */
#define UCA1BRW_SPI (HWREG16(0x40001406)) /*!< eUSCI_Ax Bit Rate Control Register 1 */
#define UCA1MCTLW (HWREG16(0x40001408)) /*!< eUSCI_Ax Modulation Control Word Register */
#define UCA1STATW (HWREG16(0x4000140A)) /*!< eUSCI_Ax Status Register */
#define UCA1STATW_SPI (HWREG16(0x4000140A))
#define UCA1RXBUF (HWREG16(0x4000140C)) /*!< eUSCI_Ax Receive Buffer Register */
#define UCA1RXBUF_SPI (HWREG16(0x4000140C)) /*!< eUSCI_Ax Receive Buffer Register */
#define UCA1TXBUF (HWREG16(0x4000140E)) /*!< eUSCI_Ax Transmit Buffer Register */
#define UCA1TXBUF_SPI (HWREG16(0x4000140E)) /*!< eUSCI_Ax Transmit Buffer Register */
#define UCA1ABCTL (HWREG16(0x40001410)) /*!< eUSCI_Ax Auto Baud Rate Control Register */
#define UCA1IRCTL (HWREG16(0x40001412)) /*!< eUSCI_Ax IrDA Control Word Register */
#define UCA1IE (HWREG16(0x4000141A)) /*!< eUSCI_Ax Interrupt Enable Register */
#define UCA1IE_SPI (HWREG16(0x4000141A)) /*!< eUSCI_Ax Interrupt Enable Register */
#define UCA1IFG (HWREG16(0x4000141C)) /*!< eUSCI_Ax Interrupt Flag Register */
#define UCA1IFG_SPI (HWREG16(0x4000141C)) /*!< eUSCI_Ax Interrupt Flag Register */
#define UCA1IV (HWREG16(0x4000141E)) /*!< eUSCI_Ax Interrupt Vector Register */
#define UCA1IV_SPI (HWREG16(0x4000141E)) /*!< eUSCI_Ax Interrupt Vector Register */
/* Register offsets from EUSCI_A1_BASE address */
#define OFS_UCA1CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */
#define OFS_UCA1CTLW0_SPI (0x0000) /*!< eUSCI_Ax Control Word Register 0 */
#define OFS_UCA1CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */
#define OFS_UCA1BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */
#define OFS_UCA1BRW_SPI (0x0006) /*!< eUSCI_Ax Bit Rate Control Register 1 */
#define OFS_UCA1MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */
#define OFS_UCA1STATW (0x000A) /*!< eUSCI_Ax Status Register */
#define OFS_UCA1STATW_SPI (0x000A)
#define OFS_UCA1RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */
#define OFS_UCA1RXBUF_SPI (0x000C) /*!< eUSCI_Ax Receive Buffer Register */
#define OFS_UCA1TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */
#define OFS_UCA1TXBUF_SPI (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */
#define OFS_UCA1ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */
#define OFS_UCA1IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */
#define OFS_UCA1IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */
#define OFS_UCA1IE_SPI (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */
#define OFS_UCA1IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */
#define OFS_UCA1IFG_SPI (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */
#define OFS_UCA1IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */
#define OFS_UCA1IV_SPI (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */
#define UCA1CTL0 (HWREG8_L(UCA1CTLW0)) /* eUSCI_Ax Control 0 */
#define UCA1CTL1 (HWREG8_H(UCA1CTLW0)) /* eUSCI_Ax Control 1 */
#define UCA1BR0 (HWREG8_L(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 0 */
#define UCA1BR1 (HWREG8_H(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 1 */
#define UCA1IRTCTL (HWREG8_L(UCA1IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
#define UCA1IRRCTL (HWREG8_H(UCA1IRCTL)) /* eUSCI_Ax IrDA Receive Control */
/******************************************************************************
* EUSCI_A2 Registers
******************************************************************************/
#define UCA2CTLW0 (HWREG16(0x40001800)) /*!< eUSCI_Ax Control Word Register 0 */
#define UCA2CTLW0_SPI (HWREG16(0x40001800)) /*!< eUSCI_Ax Control Word Register 0 */
#define UCA2CTLW1 (HWREG16(0x40001802)) /*!< eUSCI_Ax Control Word Register 1 */
#define UCA2BRW (HWREG16(0x40001806)) /*!< eUSCI_Ax Baud Rate Control Word Register */
#define UCA2BRW_SPI (HWREG16(0x40001806)) /*!< eUSCI_Ax Bit Rate Control Register 1 */
#define UCA2MCTLW (HWREG16(0x40001808)) /*!< eUSCI_Ax Modulation Control Word Register */
#define UCA2STATW (HWREG16(0x4000180A)) /*!< eUSCI_Ax Status Register */
#define UCA2STATW_SPI (HWREG16(0x4000180A))
#define UCA2RXBUF (HWREG16(0x4000180C)) /*!< eUSCI_Ax Receive Buffer Register */
#define UCA2RXBUF_SPI (HWREG16(0x4000180C)) /*!< eUSCI_Ax Receive Buffer Register */
#define UCA2TXBUF (HWREG16(0x4000180E)) /*!< eUSCI_Ax Transmit Buffer Register */
#define UCA2TXBUF_SPI (HWREG16(0x4000180E)) /*!< eUSCI_Ax Transmit Buffer Register */
#define UCA2ABCTL (HWREG16(0x40001810)) /*!< eUSCI_Ax Auto Baud Rate Control Register */
#define UCA2IRCTL (HWREG16(0x40001812)) /*!< eUSCI_Ax IrDA Control Word Register */
#define UCA2IE (HWREG16(0x4000181A)) /*!< eUSCI_Ax Interrupt Enable Register */
#define UCA2IE_SPI (HWREG16(0x4000181A)) /*!< eUSCI_Ax Interrupt Enable Register */
#define UCA2IFG (HWREG16(0x4000181C)) /*!< eUSCI_Ax Interrupt Flag Register */
#define UCA2IFG_SPI (HWREG16(0x4000181C)) /*!< eUSCI_Ax Interrupt Flag Register */
#define UCA2IV (HWREG16(0x4000181E)) /*!< eUSCI_Ax Interrupt Vector Register */
#define UCA2IV_SPI (HWREG16(0x4000181E)) /*!< eUSCI_Ax Interrupt Vector Register */
/* Register offsets from EUSCI_A2_BASE address */
#define OFS_UCA2CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */
#define OFS_UCA2CTLW0_SPI (0x0000) /*!< eUSCI_Ax Control Word Register 0 */
#define OFS_UCA2CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */
#define OFS_UCA2BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */
#define OFS_UCA2BRW_SPI (0x0006) /*!< eUSCI_Ax Bit Rate Control Register 1 */
#define OFS_UCA2MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */
#define OFS_UCA2STATW (0x000A) /*!< eUSCI_Ax Status Register */
#define OFS_UCA2STATW_SPI (0x000A)
#define OFS_UCA2RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */
#define OFS_UCA2RXBUF_SPI (0x000C) /*!< eUSCI_Ax Receive Buffer Register */
#define OFS_UCA2TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */
#define OFS_UCA2TXBUF_SPI (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */
#define OFS_UCA2ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */
#define OFS_UCA2IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */
#define OFS_UCA2IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */
#define OFS_UCA2IE_SPI (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */
#define OFS_UCA2IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */
#define OFS_UCA2IFG_SPI (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */
#define OFS_UCA2IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */
#define OFS_UCA2IV_SPI (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */
#define UCA2CTL0 (HWREG8_L(UCA2CTLW0)) /* eUSCI_Ax Control 0 */
#define UCA2CTL1 (HWREG8_H(UCA2CTLW0)) /* eUSCI_Ax Control 1 */
#define UCA2BR0 (HWREG8_L(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 0 */
#define UCA2BR1 (HWREG8_H(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 1 */
#define UCA2IRTCTL (HWREG8_L(UCA2IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
#define UCA2IRRCTL (HWREG8_H(UCA2IRCTL)) /* eUSCI_Ax IrDA Receive Control */
/******************************************************************************
* EUSCI_A3 Registers
******************************************************************************/
#define UCA3CTLW0 (HWREG16(0x40001C00)) /*!< eUSCI_Ax Control Word Register 0 */
#define UCA3CTLW0_SPI (HWREG16(0x40001C00)) /*!< eUSCI_Ax Control Word Register 0 */
#define UCA3CTLW1 (HWREG16(0x40001C02)) /*!< eUSCI_Ax Control Word Register 1 */
#define UCA3BRW (HWREG16(0x40001C06)) /*!< eUSCI_Ax Baud Rate Control Word Register */
#define UCA3BRW_SPI (HWREG16(0x40001C06)) /*!< eUSCI_Ax Bit Rate Control Register 1 */
#define UCA3MCTLW (HWREG16(0x40001C08)) /*!< eUSCI_Ax Modulation Control Word Register */
#define UCA3STATW (HWREG16(0x40001C0A)) /*!< eUSCI_Ax Status Register */
#define UCA3STATW_SPI (HWREG16(0x40001C0A))
#define UCA3RXBUF (HWREG16(0x40001C0C)) /*!< eUSCI_Ax Receive Buffer Register */
#define UCA3RXBUF_SPI (HWREG16(0x40001C0C)) /*!< eUSCI_Ax Receive Buffer Register */
#define UCA3TXBUF (HWREG16(0x40001C0E)) /*!< eUSCI_Ax Transmit Buffer Register */
#define UCA3TXBUF_SPI (HWREG16(0x40001C0E)) /*!< eUSCI_Ax Transmit Buffer Register */
#define UCA3ABCTL (HWREG16(0x40001C10)) /*!< eUSCI_Ax Auto Baud Rate Control Register */
#define UCA3IRCTL (HWREG16(0x40001C12)) /*!< eUSCI_Ax IrDA Control Word Register */
#define UCA3IE (HWREG16(0x40001C1A)) /*!< eUSCI_Ax Interrupt Enable Register */
#define UCA3IE_SPI (HWREG16(0x40001C1A)) /*!< eUSCI_Ax Interrupt Enable Register */
#define UCA3IFG (HWREG16(0x40001C1C)) /*!< eUSCI_Ax Interrupt Flag Register */
#define UCA3IFG_SPI (HWREG16(0x40001C1C)) /*!< eUSCI_Ax Interrupt Flag Register */
#define UCA3IV (HWREG16(0x40001C1E)) /*!< eUSCI_Ax Interrupt Vector Register */
#define UCA3IV_SPI (HWREG16(0x40001C1E)) /*!< eUSCI_Ax Interrupt Vector Register */
/* Register offsets from EUSCI_A3_BASE address */
#define OFS_UCA3CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */
#define OFS_UCA3CTLW0_SPI (0x0000) /*!< eUSCI_Ax Control Word Register 0 */
#define OFS_UCA3CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */
#define OFS_UCA3BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */
#define OFS_UCA3BRW_SPI (0x0006) /*!< eUSCI_Ax Bit Rate Control Register 1 */
#define OFS_UCA3MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */
#define OFS_UCA3STATW (0x000A) /*!< eUSCI_Ax Status Register */
#define OFS_UCA3STATW_SPI (0x000A)
#define OFS_UCA3RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */
#define OFS_UCA3RXBUF_SPI (0x000C) /*!< eUSCI_Ax Receive Buffer Register */
#define OFS_UCA3TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */
#define OFS_UCA3TXBUF_SPI (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */
#define OFS_UCA3ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */
#define OFS_UCA3IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */
#define OFS_UCA3IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */
#define OFS_UCA3IE_SPI (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */
#define OFS_UCA3IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */
#define OFS_UCA3IFG_SPI (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */
#define OFS_UCA3IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */
#define OFS_UCA3IV_SPI (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */
#define UCA3CTL0 (HWREG8_L(UCA3CTLW0)) /* eUSCI_Ax Control 0 */
#define UCA3CTL1 (HWREG8_H(UCA3CTLW0)) /* eUSCI_Ax Control 1 */
#define UCA3BR0 (HWREG8_L(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 0 */
#define UCA3BR1 (HWREG8_H(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 1 */
#define UCA3IRTCTL (HWREG8_L(UCA3IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
#define UCA3IRRCTL (HWREG8_H(UCA3IRCTL)) /* eUSCI_Ax IrDA Receive Control */
/******************************************************************************
* EUSCI_B0 Registers
******************************************************************************/
#define UCB0CTLW0 (HWREG16(0x40002000)) /*!< eUSCI_Bx Control Word Register 0 */
#define UCB0CTLW0_SPI (HWREG16(0x40002000)) /*!< eUSCI_Bx Control Word Register 0 */
#define UCB0CTLW1 (HWREG16(0x40002002)) /*!< eUSCI_Bx Control Word Register 1 */
#define UCB0BRW (HWREG16(0x40002006)) /*!< eUSCI_Bx Baud Rate Control Word Register */
#define UCB0BRW_SPI (HWREG16(0x40002006)) /*!< eUSCI_Bx Bit Rate Control Register 1 */
#define UCB0STATW (HWREG16(0x40002008)) /*!< eUSCI_Bx Status Register */
#define UCB0STATW_SPI (HWREG16(0x40002008))
#define UCB0TBCNT (HWREG16(0x4000200A)) /*!< eUSCI_Bx Byte Counter Threshold Register */
#define UCB0RXBUF (HWREG16(0x4000200C)) /*!< eUSCI_Bx Receive Buffer Register */
#define UCB0RXBUF_SPI (HWREG16(0x4000200C)) /*!< eUSCI_Bx Receive Buffer Register */
#define UCB0TXBUF (HWREG16(0x4000200E)) /*!< eUSCI_Bx Transmit Buffer Register */
#define UCB0TXBUF_SPI (HWREG16(0x4000200E)) /*!< eUSCI_Bx Transmit Buffer Register */
#define UCB0I2COA0 (HWREG16(0x40002014)) /*!< eUSCI_Bx I2C Own Address 0 Register */
#define UCB0I2COA1 (HWREG16(0x40002016)) /*!< eUSCI_Bx I2C Own Address 1 Register */
#define UCB0I2COA2 (HWREG16(0x40002018)) /*!< eUSCI_Bx I2C Own Address 2 Register */
#define UCB0I2COA3 (HWREG16(0x4000201A)) /*!< eUSCI_Bx I2C Own Address 3 Register */
#define UCB0ADDRX (HWREG16(0x4000201C)) /*!< eUSCI_Bx I2C Received Address Register */
#define UCB0ADDMASK (HWREG16(0x4000201E)) /*!< eUSCI_Bx I2C Address Mask Register */
#define UCB0I2CSA (HWREG16(0x40002020)) /*!< eUSCI_Bx I2C Slave Address Register */
#define UCB0IE (HWREG16(0x4000202A)) /*!< eUSCI_Bx Interrupt Enable Register */
#define UCB0IE_SPI (HWREG16(0x4000202A)) /*!< eUSCI_Bx Interrupt Enable Register */
#define UCB0IFG (HWREG16(0x4000202C)) /*!< eUSCI_Bx Interrupt Flag Register */
#define UCB0IFG_SPI (HWREG16(0x4000202C)) /*!< eUSCI_Bx Interrupt Flag Register */
#define UCB0IV (HWREG16(0x4000202E)) /*!< eUSCI_Bx Interrupt Vector Register */
#define UCB0IV_SPI (HWREG16(0x4000202E)) /*!< eUSCI_Bx Interrupt Vector Register */
/* Register offsets from EUSCI_B0_BASE address */
#define OFS_UCB0CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */
#define OFS_UCB0CTLW0_SPI (0x0000) /*!< eUSCI_Bx Control Word Register 0 */
#define OFS_UCB0CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */
#define OFS_UCB0BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */
#define OFS_UCB0BRW_SPI (0x0006) /*!< eUSCI_Bx Bit Rate Control Register 1 */
#define OFS_UCB0STATW (0x0008) /*!< eUSCI_Bx Status Register */
#define OFS_UCB0STATW_SPI (0x0008)
#define OFS_UCB0TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */
#define OFS_UCB0RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */
#define OFS_UCB0RXBUF_SPI (0x000C) /*!< eUSCI_Bx Receive Buffer Register */
#define OFS_UCB0TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */
#define OFS_UCB0TXBUF_SPI (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */
#define OFS_UCB0I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */
#define OFS_UCB0I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */
#define OFS_UCB0I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */
#define OFS_UCB0I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */
#define OFS_UCB0ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */
#define OFS_UCB0ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */
#define OFS_UCB0I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */
#define OFS_UCB0IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */
#define OFS_UCB0IE_SPI (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */
#define OFS_UCB0IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */
#define OFS_UCB0IFG_SPI (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */
#define OFS_UCB0IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */
#define OFS_UCB0IV_SPI (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */
#define UCB0CTL0 (HWREG8_L(UCB0CTLW0)) /* eUSCI_Bx Control 1 */
#define UCB0CTL1 (HWREG8_H(UCB0CTLW0)) /* eUSCI_Bx Control 0 */
#define UCB0BR0 (HWREG8_L(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 0 */
#define UCB0BR1 (HWREG8_H(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 1 */
#define UCB0STAT (HWREG8_L(UCB0STATW)) /* eUSCI_Bx Status */
#define UCB0BCNT (HWREG8_H(UCB0STATW)) /* eUSCI_Bx Byte Counter Register */
/******************************************************************************
* EUSCI_B1 Registers
******************************************************************************/
#define UCB1CTLW0 (HWREG16(0x40002400)) /*!< eUSCI_Bx Control Word Register 0 */
#define UCB1CTLW0_SPI (HWREG16(0x40002400)) /*!< eUSCI_Bx Control Word Register 0 */
#define UCB1CTLW1 (HWREG16(0x40002402)) /*!< eUSCI_Bx Control Word Register 1 */
#define UCB1BRW (HWREG16(0x40002406)) /*!< eUSCI_Bx Baud Rate Control Word Register */
#define UCB1BRW_SPI (HWREG16(0x40002406)) /*!< eUSCI_Bx Bit Rate Control Register 1 */
#define UCB1STATW (HWREG16(0x40002408)) /*!< eUSCI_Bx Status Register */
#define UCB1STATW_SPI (HWREG16(0x40002408))
#define UCB1TBCNT (HWREG16(0x4000240A)) /*!< eUSCI_Bx Byte Counter Threshold Register */
#define UCB1RXBUF (HWREG16(0x4000240C)) /*!< eUSCI_Bx Receive Buffer Register */
#define UCB1RXBUF_SPI (HWREG16(0x4000240C)) /*!< eUSCI_Bx Receive Buffer Register */
#define UCB1TXBUF (HWREG16(0x4000240E)) /*!< eUSCI_Bx Transmit Buffer Register */
#define UCB1TXBUF_SPI (HWREG16(0x4000240E)) /*!< eUSCI_Bx Transmit Buffer Register */
#define UCB1I2COA0 (HWREG16(0x40002414)) /*!< eUSCI_Bx I2C Own Address 0 Register */
#define UCB1I2COA1 (HWREG16(0x40002416)) /*!< eUSCI_Bx I2C Own Address 1 Register */
#define UCB1I2COA2 (HWREG16(0x40002418)) /*!< eUSCI_Bx I2C Own Address 2 Register */
#define UCB1I2COA3 (HWREG16(0x4000241A)) /*!< eUSCI_Bx I2C Own Address 3 Register */
#define UCB1ADDRX (HWREG16(0x4000241C)) /*!< eUSCI_Bx I2C Received Address Register */
#define UCB1ADDMASK (HWREG16(0x4000241E)) /*!< eUSCI_Bx I2C Address Mask Register */
#define UCB1I2CSA (HWREG16(0x40002420)) /*!< eUSCI_Bx I2C Slave Address Register */
#define UCB1IE (HWREG16(0x4000242A)) /*!< eUSCI_Bx Interrupt Enable Register */
#define UCB1IE_SPI (HWREG16(0x4000242A)) /*!< eUSCI_Bx Interrupt Enable Register */
#define UCB1IFG (HWREG16(0x4000242C)) /*!< eUSCI_Bx Interrupt Flag Register */
#define UCB1IFG_SPI (HWREG16(0x4000242C)) /*!< eUSCI_Bx Interrupt Flag Register */
#define UCB1IV (HWREG16(0x4000242E)) /*!< eUSCI_Bx Interrupt Vector Register */
#define UCB1IV_SPI (HWREG16(0x4000242E)) /*!< eUSCI_Bx Interrupt Vector Register */
/* Register offsets from EUSCI_B1_BASE address */
#define OFS_UCB1CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */
#define OFS_UCB1CTLW0_SPI (0x0000) /*!< eUSCI_Bx Control Word Register 0 */
#define OFS_UCB1CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */
#define OFS_UCB1BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */
#define OFS_UCB1BRW_SPI (0x0006) /*!< eUSCI_Bx Bit Rate Control Register 1 */
#define OFS_UCB1STATW (0x0008) /*!< eUSCI_Bx Status Register */
#define OFS_UCB1STATW_SPI (0x0008)
#define OFS_UCB1TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */
#define OFS_UCB1RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */
#define OFS_UCB1RXBUF_SPI (0x000C) /*!< eUSCI_Bx Receive Buffer Register */
#define OFS_UCB1TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */
#define OFS_UCB1TXBUF_SPI (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */
#define OFS_UCB1I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */
#define OFS_UCB1I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */
#define OFS_UCB1I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */
#define OFS_UCB1I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */
#define OFS_UCB1ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */
#define OFS_UCB1ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */
#define OFS_UCB1I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */
#define OFS_UCB1IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */
#define OFS_UCB1IE_SPI (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */
#define OFS_UCB1IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */
#define OFS_UCB1IFG_SPI (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */
#define OFS_UCB1IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */
#define OFS_UCB1IV_SPI (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */
#define UCB1CTL0 (HWREG8_L(UCB1CTLW0)) /* eUSCI_Bx Control 1 */
#define UCB1CTL1 (HWREG8_H(UCB1CTLW0)) /* eUSCI_Bx Control 0 */
#define UCB1BR0 (HWREG8_L(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 0 */
#define UCB1BR1 (HWREG8_H(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 1 */
#define UCB1STAT (HWREG8_L(UCB1STATW)) /* eUSCI_Bx Status */
#define UCB1BCNT (HWREG8_H(UCB1STATW)) /* eUSCI_Bx Byte Counter Register */
/******************************************************************************
* EUSCI_B2 Registers
******************************************************************************/
#define UCB2CTLW0 (HWREG16(0x40002800)) /*!< eUSCI_Bx Control Word Register 0 */
#define UCB2CTLW0_SPI (HWREG16(0x40002800)) /*!< eUSCI_Bx Control Word Register 0 */
#define UCB2CTLW1 (HWREG16(0x40002802)) /*!< eUSCI_Bx Control Word Register 1 */
#define UCB2BRW (HWREG16(0x40002806)) /*!< eUSCI_Bx Baud Rate Control Word Register */
#define UCB2BRW_SPI (HWREG16(0x40002806)) /*!< eUSCI_Bx Bit Rate Control Register 1 */
#define UCB2STATW (HWREG16(0x40002808)) /*!< eUSCI_Bx Status Register */
#define UCB2STATW_SPI (HWREG16(0x40002808))
#define UCB2TBCNT (HWREG16(0x4000280A)) /*!< eUSCI_Bx Byte Counter Threshold Register */
#define UCB2RXBUF (HWREG16(0x4000280C)) /*!< eUSCI_Bx Receive Buffer Register */
#define UCB2RXBUF_SPI (HWREG16(0x4000280C)) /*!< eUSCI_Bx Receive Buffer Register */
#define UCB2TXBUF (HWREG16(0x4000280E)) /*!< eUSCI_Bx Transmit Buffer Register */
#define UCB2TXBUF_SPI (HWREG16(0x4000280E)) /*!< eUSCI_Bx Transmit Buffer Register */
#define UCB2I2COA0 (HWREG16(0x40002814)) /*!< eUSCI_Bx I2C Own Address 0 Register */
#define UCB2I2COA1 (HWREG16(0x40002816)) /*!< eUSCI_Bx I2C Own Address 1 Register */
#define UCB2I2COA2 (HWREG16(0x40002818)) /*!< eUSCI_Bx I2C Own Address 2 Register */
#define UCB2I2COA3 (HWREG16(0x4000281A)) /*!< eUSCI_Bx I2C Own Address 3 Register */
#define UCB2ADDRX (HWREG16(0x4000281C)) /*!< eUSCI_Bx I2C Received Address Register */
#define UCB2ADDMASK (HWREG16(0x4000281E)) /*!< eUSCI_Bx I2C Address Mask Register */
#define UCB2I2CSA (HWREG16(0x40002820)) /*!< eUSCI_Bx I2C Slave Address Register */
#define UCB2IE (HWREG16(0x4000282A)) /*!< eUSCI_Bx Interrupt Enable Register */
#define UCB2IE_SPI (HWREG16(0x4000282A)) /*!< eUSCI_Bx Interrupt Enable Register */
#define UCB2IFG (HWREG16(0x4000282C)) /*!< eUSCI_Bx Interrupt Flag Register */
#define UCB2IFG_SPI (HWREG16(0x4000282C)) /*!< eUSCI_Bx Interrupt Flag Register */
#define UCB2IV (HWREG16(0x4000282E)) /*!< eUSCI_Bx Interrupt Vector Register */
#define UCB2IV_SPI (HWREG16(0x4000282E)) /*!< eUSCI_Bx Interrupt Vector Register */
/* Register offsets from EUSCI_B2_BASE address */
#define OFS_UCB2CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */
#define OFS_UCB2CTLW0_SPI (0x0000) /*!< eUSCI_Bx Control Word Register 0 */
#define OFS_UCB2CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */
#define OFS_UCB2BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */
#define OFS_UCB2BRW_SPI (0x0006) /*!< eUSCI_Bx Bit Rate Control Register 1 */
#define OFS_UCB2STATW (0x0008) /*!< eUSCI_Bx Status Register */
#define OFS_UCB2STATW_SPI (0x0008)
#define OFS_UCB2TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */
#define OFS_UCB2RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */
#define OFS_UCB2RXBUF_SPI (0x000C) /*!< eUSCI_Bx Receive Buffer Register */
#define OFS_UCB2TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */
#define OFS_UCB2TXBUF_SPI (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */
#define OFS_UCB2I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */
#define OFS_UCB2I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */
#define OFS_UCB2I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */
#define OFS_UCB2I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */
#define OFS_UCB2ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */
#define OFS_UCB2ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */
#define OFS_UCB2I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */
#define OFS_UCB2IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */
#define OFS_UCB2IE_SPI (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */
#define OFS_UCB2IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */
#define OFS_UCB2IFG_SPI (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */
#define OFS_UCB2IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */
#define OFS_UCB2IV_SPI (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */
#define UCB2CTL0 (HWREG8_L(UCB2CTLW0)) /* eUSCI_Bx Control 1 */
#define UCB2CTL1 (HWREG8_H(UCB2CTLW0)) /* eUSCI_Bx Control 0 */
#define UCB2BR0 (HWREG8_L(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 0 */
#define UCB2BR1 (HWREG8_H(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 1 */
#define UCB2STAT (HWREG8_L(UCB2STATW)) /* eUSCI_Bx Status */
#define UCB2BCNT (HWREG8_H(UCB2STATW)) /* eUSCI_Bx Byte Counter Register */
/******************************************************************************
* EUSCI_B3 Registers
******************************************************************************/
#define UCB3CTLW0 (HWREG16(0x40002C00)) /*!< eUSCI_Bx Control Word Register 0 */
#define UCB3CTLW0_SPI (HWREG16(0x40002C00)) /*!< eUSCI_Bx Control Word Register 0 */
#define UCB3CTLW1 (HWREG16(0x40002C02)) /*!< eUSCI_Bx Control Word Register 1 */
#define UCB3BRW (HWREG16(0x40002C06)) /*!< eUSCI_Bx Baud Rate Control Word Register */
#define UCB3BRW_SPI (HWREG16(0x40002C06)) /*!< eUSCI_Bx Bit Rate Control Register 1 */
#define UCB3STATW (HWREG16(0x40002C08)) /*!< eUSCI_Bx Status Register */
#define UCB3STATW_SPI (HWREG16(0x40002C08))
#define UCB3TBCNT (HWREG16(0x40002C0A)) /*!< eUSCI_Bx Byte Counter Threshold Register */
#define UCB3RXBUF (HWREG16(0x40002C0C)) /*!< eUSCI_Bx Receive Buffer Register */
#define UCB3RXBUF_SPI (HWREG16(0x40002C0C)) /*!< eUSCI_Bx Receive Buffer Register */
#define UCB3TXBUF (HWREG16(0x40002C0E)) /*!< eUSCI_Bx Transmit Buffer Register */
#define UCB3TXBUF_SPI (HWREG16(0x40002C0E)) /*!< eUSCI_Bx Transmit Buffer Register */
#define UCB3I2COA0 (HWREG16(0x40002C14)) /*!< eUSCI_Bx I2C Own Address 0 Register */
#define UCB3I2COA1 (HWREG16(0x40002C16)) /*!< eUSCI_Bx I2C Own Address 1 Register */
#define UCB3I2COA2 (HWREG16(0x40002C18)) /*!< eUSCI_Bx I2C Own Address 2 Register */
#define UCB3I2COA3 (HWREG16(0x40002C1A)) /*!< eUSCI_Bx I2C Own Address 3 Register */
#define UCB3ADDRX (HWREG16(0x40002C1C)) /*!< eUSCI_Bx I2C Received Address Register */
#define UCB3ADDMASK (HWREG16(0x40002C1E)) /*!< eUSCI_Bx I2C Address Mask Register */
#define UCB3I2CSA (HWREG16(0x40002C20)) /*!< eUSCI_Bx I2C Slave Address Register */
#define UCB3IE (HWREG16(0x40002C2A)) /*!< eUSCI_Bx Interrupt Enable Register */
#define UCB3IE_SPI (HWREG16(0x40002C2A)) /*!< eUSCI_Bx Interrupt Enable Register */
#define UCB3IFG (HWREG16(0x40002C2C)) /*!< eUSCI_Bx Interrupt Flag Register */
#define UCB3IFG_SPI (HWREG16(0x40002C2C)) /*!< eUSCI_Bx Interrupt Flag Register */
#define UCB3IV (HWREG16(0x40002C2E)) /*!< eUSCI_Bx Interrupt Vector Register */
#define UCB3IV_SPI (HWREG16(0x40002C2E)) /*!< eUSCI_Bx Interrupt Vector Register */
/* Register offsets from EUSCI_B3_BASE address */
#define OFS_UCB3CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */
#define OFS_UCB3CTLW0_SPI (0x0000) /*!< eUSCI_Bx Control Word Register 0 */
#define OFS_UCB3CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */
#define OFS_UCB3BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */
#define OFS_UCB3BRW_SPI (0x0006) /*!< eUSCI_Bx Bit Rate Control Register 1 */
#define OFS_UCB3STATW (0x0008) /*!< eUSCI_Bx Status Register */
#define OFS_UCB3STATW_SPI (0x0008)
#define OFS_UCB3TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */
#define OFS_UCB3RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */
#define OFS_UCB3RXBUF_SPI (0x000C) /*!< eUSCI_Bx Receive Buffer Register */
#define OFS_UCB3TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */
#define OFS_UCB3TXBUF_SPI (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */
#define OFS_UCB3I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */
#define OFS_UCB3I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */
#define OFS_UCB3I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */
#define OFS_UCB3I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */
#define OFS_UCB3ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */
#define OFS_UCB3ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */
#define OFS_UCB3I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */
#define OFS_UCB3IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */
#define OFS_UCB3IE_SPI (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */
#define OFS_UCB3IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */
#define OFS_UCB3IFG_SPI (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */
#define OFS_UCB3IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */
#define OFS_UCB3IV_SPI (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */
#define UCB3CTL0 (HWREG8_L(UCB3CTLW0)) /* eUSCI_Bx Control 1 */
#define UCB3CTL1 (HWREG8_H(UCB3CTLW0)) /* eUSCI_Bx Control 0 */
#define UCB3BR0 (HWREG8_L(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 0 */
#define UCB3BR1 (HWREG8_H(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 1 */
#define UCB3STAT (HWREG8_L(UCB3STATW)) /* eUSCI_Bx Status */
#define UCB3BCNT (HWREG8_H(UCB3STATW)) /* eUSCI_Bx Byte Counter Register */
/******************************************************************************
* PMAP Registers
******************************************************************************/
#define PMAPKEYID (HWREG16(0x40005000)) /*!< Port Mapping Key Register */
#define PMAPCTL (HWREG16(0x40005002)) /*!< Port Mapping Control Register */
#define P1MAP01 (HWREG16(0x40005008)) /*!< Port mapping register, P1.0 and P1.1 */
#define P1MAP23 (HWREG16(0x4000500A)) /*!< Port mapping register, P1.2 and P1.3 */
#define P1MAP45 (HWREG16(0x4000500C)) /*!< Port mapping register, P1.4 and P1.5 */
#define P1MAP67 (HWREG16(0x4000500E)) /*!< Port mapping register, P1.6 and P1.7 */
#define P2MAP01 (HWREG16(0x40005010)) /*!< Port mapping register, P2.0 and P2.1 */
#define P2MAP23 (HWREG16(0x40005012)) /*!< Port mapping register, P2.2 and P2.3 */
#define P2MAP45 (HWREG16(0x40005014)) /*!< Port mapping register, P2.4 and P2.5 */
#define P2MAP67 (HWREG16(0x40005016)) /*!< Port mapping register, P2.6 and P2.7 */
#define P3MAP01 (HWREG16(0x40005018)) /*!< Port mapping register, P3.0 and P3.1 */
#define P3MAP23 (HWREG16(0x4000501A)) /*!< Port mapping register, P3.2 and P3.3 */
#define P3MAP45 (HWREG16(0x4000501C)) /*!< Port mapping register, P3.4 and P3.5 */
#define P3MAP67 (HWREG16(0x4000501E)) /*!< Port mapping register, P3.6 and P3.7 */
#define P4MAP01 (HWREG16(0x40005020)) /*!< Port mapping register, P4.0 and P4.1 */
#define P4MAP23 (HWREG16(0x40005022)) /*!< Port mapping register, P4.2 and P4.3 */
#define P4MAP45 (HWREG16(0x40005024)) /*!< Port mapping register, P4.4 and P4.5 */
#define P4MAP67 (HWREG16(0x40005026)) /*!< Port mapping register, P4.6 and P4.7 */
#define P5MAP01 (HWREG16(0x40005028)) /*!< Port mapping register, P5.0 and P5.1 */
#define P5MAP23 (HWREG16(0x4000502A)) /*!< Port mapping register, P5.2 and P5.3 */
#define P5MAP45 (HWREG16(0x4000502C)) /*!< Port mapping register, P5.4 and P5.5 */
#define P5MAP67 (HWREG16(0x4000502E)) /*!< Port mapping register, P5.6 and P5.7 */
#define P6MAP01 (HWREG16(0x40005030)) /*!< Port mapping register, P6.0 and P6.1 */
#define P6MAP23 (HWREG16(0x40005032)) /*!< Port mapping register, P6.2 and P6.3 */
#define P6MAP45 (HWREG16(0x40005034)) /*!< Port mapping register, P6.4 and P6.5 */
#define P6MAP67 (HWREG16(0x40005036)) /*!< Port mapping register, P6.6 and P6.7 */
#define P7MAP01 (HWREG16(0x40005038)) /*!< Port mapping register, P7.0 and P7.1 */
#define P7MAP23 (HWREG16(0x4000503A)) /*!< Port mapping register, P7.2 and P7.3 */
#define P7MAP45 (HWREG16(0x4000503C)) /*!< Port mapping register, P7.4 and P7.5 */
#define P7MAP67 (HWREG16(0x4000503E)) /*!< Port mapping register, P7.6 and P7.7 */
/* Register offsets from PMAP_BASE address */
#define OFS_PMAPKEYID (0x0000) /*!< Port Mapping Key Register */
#define OFS_PMAPCTL (0x0002) /*!< Port Mapping Control Register */
#define OFS_P1MAP01 (0x0008) /*!< Port mapping register, P1.0 and P1.1 */
#define OFS_P1MAP23 (0x000A) /*!< Port mapping register, P1.2 and P1.3 */
#define OFS_P1MAP45 (0x000C) /*!< Port mapping register, P1.4 and P1.5 */
#define OFS_P1MAP67 (0x000E) /*!< Port mapping register, P1.6 and P1.7 */
#define OFS_P2MAP01 (0x0010) /*!< Port mapping register, P2.0 and P2.1 */
#define OFS_P2MAP23 (0x0012) /*!< Port mapping register, P2.2 and P2.3 */
#define OFS_P2MAP45 (0x0014) /*!< Port mapping register, P2.4 and P2.5 */
#define OFS_P2MAP67 (0x0016) /*!< Port mapping register, P2.6 and P2.7 */
#define OFS_P3MAP01 (0x0018) /*!< Port mapping register, P3.0 and P3.1 */
#define OFS_P3MAP23 (0x001A) /*!< Port mapping register, P3.2 and P3.3 */
#define OFS_P3MAP45 (0x001C) /*!< Port mapping register, P3.4 and P3.5 */
#define OFS_P3MAP67 (0x001E) /*!< Port mapping register, P3.6 and P3.7 */
#define OFS_P4MAP01 (0x0020) /*!< Port mapping register, P4.0 and P4.1 */
#define OFS_P4MAP23 (0x0022) /*!< Port mapping register, P4.2 and P4.3 */
#define OFS_P4MAP45 (0x0024) /*!< Port mapping register, P4.4 and P4.5 */
#define OFS_P4MAP67 (0x0026) /*!< Port mapping register, P4.6 and P4.7 */
#define OFS_P5MAP01 (0x0028) /*!< Port mapping register, P5.0 and P5.1 */
#define OFS_P5MAP23 (0x002A) /*!< Port mapping register, P5.2 and P5.3 */
#define OFS_P5MAP45 (0x002C) /*!< Port mapping register, P5.4 and P5.5 */
#define OFS_P5MAP67 (0x002E) /*!< Port mapping register, P5.6 and P5.7 */
#define OFS_P6MAP01 (0x0030) /*!< Port mapping register, P6.0 and P6.1 */
#define OFS_P6MAP23 (0x0032) /*!< Port mapping register, P6.2 and P6.3 */
#define OFS_P6MAP45 (0x0034) /*!< Port mapping register, P6.4 and P6.5 */
#define OFS_P6MAP67 (0x0036) /*!< Port mapping register, P6.6 and P6.7 */
#define OFS_P7MAP01 (0x0038) /*!< Port mapping register, P7.0 and P7.1 */
#define OFS_P7MAP23 (0x003A) /*!< Port mapping register, P7.2 and P7.3 */
#define OFS_P7MAP45 (0x003C) /*!< Port mapping register, P7.4 and P7.5 */
#define OFS_P7MAP67 (0x003E) /*!< Port mapping register, P7.6 and P7.7 */
/******************************************************************************
* REF_A Registers
******************************************************************************/
#define REFCTL0 (HWREG16(0x40003000)) /*!< REF Control Register 0 */
/* Register offsets from REF_A_BASE address */
#define OFS_REFCTL0 (0x0000) /*!< REF Control Register 0 */
#define REFCTL0_L (HWREG8_L(REFCTL0)) /* REF Control Register 0 */
#define REFCTL0_H (HWREG8_H(REFCTL0)) /* REF Control Register 0 */
/******************************************************************************
* RTC_C Registers
******************************************************************************/
#define RTCCTL0 (HWREG16(0x40004400)) /*!< RTCCTL0 Register */
#define RTCCTL13 (HWREG16(0x40004402)) /*!< RTCCTL13 Register */
#define RTCOCAL (HWREG16(0x40004404)) /*!< RTCOCAL Register */
#define RTCTCMP (HWREG16(0x40004406)) /*!< RTCTCMP Register */
#define RTCPS0CTL (HWREG16(0x40004408)) /*!< Real-Time Clock Prescale Timer 0 Control Register */
#define RTCPS1CTL (HWREG16(0x4000440A)) /*!< Real-Time Clock Prescale Timer 1 Control Register */
#define RTCPS (HWREG16(0x4000440C)) /*!< Real-Time Clock Prescale Timer Counter Register */
#define RTCIV (HWREG16(0x4000440E)) /*!< Real-Time Clock Interrupt Vector Register */
#define RTCTIM0 (HWREG16(0x40004410)) /*!< RTCTIM0 Register ? Hexadecimal Format */
#define RTCTIM0_BCD (HWREG16(0x40004410)) /*!< RTCTIM0 Register ? BCD Format */
#define RTCTIM1 (HWREG16(0x40004412)) /*!< Real-Time Clock Hour, Day of Week */
#define RTCTIM1_BCD (HWREG16(0x40004412)) /*!< RTCTIM1 Register ? BCD Format */
#define RTCDATE (HWREG16(0x40004414)) /*!< RTCDATE - Hexadecimal Format */
#define RTCDATE_BCD (HWREG16(0x40004414)) /*!< Real-Time Clock Date - BCD Format */
#define RTCYEAR (HWREG16(0x40004416)) /*!< RTCYEAR Register ? Hexadecimal Format */
#define RTCYEAR_BCD (HWREG16(0x40004416)) /*!< RTCYEAR Register ? BCD Format */
#define RTCAMINHR (HWREG16(0x40004418)) /*!< RTCMINHR - Hexadecimal Format */
#define RTCAMINHR_BCD (HWREG16(0x40004418)) /*!< RTCMINHR - BCD Format */
#define RTCADOWDAY (HWREG16(0x4000441A)) /*!< RTCADOWDAY - Hexadecimal Format */
#define RTCADOWDAY_BCD (HWREG16(0x4000441A)) /*!< RTCADOWDAY - BCD Format */
#define RTCBIN2BCD (HWREG16(0x4000441C)) /*!< Binary-to-BCD Conversion Register */
#define RTCBCD2BIN (HWREG16(0x4000441E)) /*!< BCD-to-Binary Conversion Register */
/* Register offsets from RTC_C_BASE address */
#define OFS_RTCCTL0 (0x0000) /*!< RTCCTL0 Register */
#define OFS_RTCCTL13 (0x0002) /*!< RTCCTL13 Register */
#define OFS_RTCOCAL (0x0004) /*!< RTCOCAL Register */
#define OFS_RTCTCMP (0x0006) /*!< RTCTCMP Register */
#define OFS_RTCPS0CTL (0x0008) /*!< Real-Time Clock Prescale Timer 0 Control Register */
#define OFS_RTCPS1CTL (0x000A) /*!< Real-Time Clock Prescale Timer 1 Control Register */
#define OFS_RTCPS (0x000C) /*!< Real-Time Clock Prescale Timer Counter Register */
#define OFS_RTCIV (0x000E) /*!< Real-Time Clock Interrupt Vector Register */
#define OFS_RTCTIM0 (0x0010) /*!< RTCTIM0 Register ? Hexadecimal Format */
#define OFS_RTCTIM0_BCD (0x0010) /*!< RTCTIM0 Register ? BCD Format */
#define OFS_RTCTIM1 (0x0012) /*!< Real-Time Clock Hour, Day of Week */
#define OFS_RTCTIM1_BCD (0x0012) /*!< RTCTIM1 Register ? BCD Format */
#define OFS_RTCDATE (0x0014) /*!< RTCDATE - Hexadecimal Format */
#define OFS_RTCDATE_BCD (0x0014) /*!< Real-Time Clock Date - BCD Format */
#define OFS_RTCYEAR (0x0016) /*!< RTCYEAR Register ? Hexadecimal Format */
#define OFS_RTCYEAR_BCD (0x0016) /*!< RTCYEAR Register ? BCD Format */
#define OFS_RTCAMINHR (0x0018) /*!< RTCMINHR - Hexadecimal Format */
#define OFS_RTCAMINHR_BCD (0x0018) /*!< RTCMINHR - BCD Format */
#define OFS_RTCADOWDAY (0x001A) /*!< RTCADOWDAY - Hexadecimal Format */
#define OFS_RTCADOWDAY_BCD (0x001A) /*!< RTCADOWDAY - BCD Format */
#define OFS_RTCBIN2BCD (0x001C) /*!< Binary-to-BCD Conversion Register */
#define OFS_RTCBCD2BIN (0x001E) /*!< BCD-to-Binary Conversion Register */
#define RTCCTL0_L (HWREG8_L(RTCCTL0)) /* RTCCTL0 Register */
#define RTCCTL0_H (HWREG8_H(RTCCTL0)) /* RTCCTL0 Register */
#define RTCCTL1 (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */
#define RTCCTL13_L (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */
#define RTCCTL3 (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */
#define RTCCTL13_H (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */
#define RTCOCAL_L (HWREG8_L(RTCOCAL)) /* RTCOCAL Register */
#define RTCOCAL_H (HWREG8_H(RTCOCAL)) /* RTCOCAL Register */
#define RTCTCMP_L (HWREG8_L(RTCTCMP)) /* RTCTCMP Register */
#define RTCTCMP_H (HWREG8_H(RTCTCMP)) /* RTCTCMP Register */
#define RTCPS0CTL_L (HWREG8_L(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */
#define RTCPS0CTL_H (HWREG8_H(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */
#define RTCPS1CTL_L (HWREG8_L(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */
#define RTCPS1CTL_H (HWREG8_H(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */
#define RTCPS0 (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */
#define RTCPS_L (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */
#define RTCPS1 (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */
#define RTCPS_H (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */
#define RTCSEC (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */
#define RTCTIM0_L (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */
#define RTCMIN (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */
#define RTCTIM0_H (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */
#define RTCHOUR (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */
#define RTCTIM1_L (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */
#define RTCDOW (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */
#define RTCTIM1_H (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */
#define RTCDAY (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */
#define RTCDATE_L (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */
#define RTCMON (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */
#define RTCDATE_H (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */
#define RTCAMIN (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */
#define RTCAMINHR_L (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */
#define RTCAHOUR (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */
#define RTCAMINHR_H (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */
#define RTCADOW (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */
#define RTCADOWDAY_L (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */
#define RTCADAY (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */
#define RTCADOWDAY_H (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */
/******************************************************************************
* TIMER_A0 Registers
******************************************************************************/
#define TA0CTL (HWREG16(0x40000000)) /*!< TimerAx Control Register */
#define TA0CCTL0 (HWREG16(0x40000002)) /*!< Timer_A Capture/Compare Control Register */
#define TA0CCTL1 (HWREG16(0x40000004)) /*!< Timer_A Capture/Compare Control Register */
#define TA0CCTL2 (HWREG16(0x40000006)) /*!< Timer_A Capture/Compare Control Register */
#define TA0CCTL3 (HWREG16(0x40000008)) /*!< Timer_A Capture/Compare Control Register */
#define TA0CCTL4 (HWREG16(0x4000000A)) /*!< Timer_A Capture/Compare Control Register */
#define TA0CCTL5 (HWREG16(0x4000000C)) /*!< Timer_A Capture/Compare Control Register */
#define TA0CCTL6 (HWREG16(0x4000000E)) /*!< Timer_A Capture/Compare Control Register */
#define TA0R (HWREG16(0x40000010)) /*!< TimerA register */
#define TA0CCR0 (HWREG16(0x40000012)) /*!< Timer_A Capture/Compare Register */
#define TA0CCR1 (HWREG16(0x40000014)) /*!< Timer_A Capture/Compare Register */
#define TA0CCR2 (HWREG16(0x40000016)) /*!< Timer_A Capture/Compare Register */
#define TA0CCR3 (HWREG16(0x40000018)) /*!< Timer_A Capture/Compare Register */
#define TA0CCR4 (HWREG16(0x4000001A)) /*!< Timer_A Capture/Compare Register */
#define TA0CCR5 (HWREG16(0x4000001C)) /*!< Timer_A Capture/Compare Register */
#define TA0CCR6 (HWREG16(0x4000001E)) /*!< Timer_A Capture/Compare Register */
#define TA0EX0 (HWREG16(0x40000020)) /*!< TimerAx Expansion 0 Register */
#define TA0IV (HWREG16(0x4000002E)) /*!< TimerAx Interrupt Vector Register */
/* Register offsets from TIMER_A0_BASE address */
#define OFS_TA0CTL (0x0000) /*!< TimerAx Control Register */
#define OFS_TA0CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA0CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA0CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA0CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA0CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA0CCTL5 (0x000C) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA0CCTL6 (0x000E) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA0R (0x0010) /*!< TimerA register */
#define OFS_TA0CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */
#define OFS_TA0CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */
#define OFS_TA0CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */
#define OFS_TA0CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */
#define OFS_TA0CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */
#define OFS_TA0CCR5 (0x001C) /*!< Timer_A Capture/Compare Register */
#define OFS_TA0CCR6 (0x001E) /*!< Timer_A Capture/Compare Register */
#define OFS_TA0EX0 (0x0020) /*!< TimerAx Expansion 0 Register */
#define OFS_TA0IV (0x002E) /*!< TimerAx Interrupt Vector Register */
/******************************************************************************
* TIMER_A1 Registers
******************************************************************************/
#define TA1CTL (HWREG16(0x40000400)) /*!< TimerAx Control Register */
#define TA1CCTL0 (HWREG16(0x40000402)) /*!< Timer_A Capture/Compare Control Register */
#define TA1CCTL1 (HWREG16(0x40000404)) /*!< Timer_A Capture/Compare Control Register */
#define TA1CCTL2 (HWREG16(0x40000406)) /*!< Timer_A Capture/Compare Control Register */
#define TA1CCTL3 (HWREG16(0x40000408)) /*!< Timer_A Capture/Compare Control Register */
#define TA1CCTL4 (HWREG16(0x4000040A)) /*!< Timer_A Capture/Compare Control Register */
#define TA1CCTL5 (HWREG16(0x4000040C)) /*!< Timer_A Capture/Compare Control Register */
#define TA1CCTL6 (HWREG16(0x4000040E)) /*!< Timer_A Capture/Compare Control Register */
#define TA1R (HWREG16(0x40000410)) /*!< TimerA register */
#define TA1CCR0 (HWREG16(0x40000412)) /*!< Timer_A Capture/Compare Register */
#define TA1CCR1 (HWREG16(0x40000414)) /*!< Timer_A Capture/Compare Register */
#define TA1CCR2 (HWREG16(0x40000416)) /*!< Timer_A Capture/Compare Register */
#define TA1CCR3 (HWREG16(0x40000418)) /*!< Timer_A Capture/Compare Register */
#define TA1CCR4 (HWREG16(0x4000041A)) /*!< Timer_A Capture/Compare Register */
#define TA1CCR5 (HWREG16(0x4000041C)) /*!< Timer_A Capture/Compare Register */
#define TA1CCR6 (HWREG16(0x4000041E)) /*!< Timer_A Capture/Compare Register */
#define TA1EX0 (HWREG16(0x40000420)) /*!< TimerAx Expansion 0 Register */
#define TA1IV (HWREG16(0x4000042E)) /*!< TimerAx Interrupt Vector Register */
/* Register offsets from TIMER_A1_BASE address */
#define OFS_TA1CTL (0x0000) /*!< TimerAx Control Register */
#define OFS_TA1CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA1CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA1CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA1CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA1CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA1CCTL5 (0x000C) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA1CCTL6 (0x000E) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA1R (0x0010) /*!< TimerA register */
#define OFS_TA1CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */
#define OFS_TA1CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */
#define OFS_TA1CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */
#define OFS_TA1CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */
#define OFS_TA1CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */
#define OFS_TA1CCR5 (0x001C) /*!< Timer_A Capture/Compare Register */
#define OFS_TA1CCR6 (0x001E) /*!< Timer_A Capture/Compare Register */
#define OFS_TA1EX0 (0x0020) /*!< TimerAx Expansion 0 Register */
#define OFS_TA1IV (0x002E) /*!< TimerAx Interrupt Vector Register */
/******************************************************************************
* TIMER_A2 Registers
******************************************************************************/
#define TA2CTL (HWREG16(0x40000800)) /*!< TimerAx Control Register */
#define TA2CCTL0 (HWREG16(0x40000802)) /*!< Timer_A Capture/Compare Control Register */
#define TA2CCTL1 (HWREG16(0x40000804)) /*!< Timer_A Capture/Compare Control Register */
#define TA2CCTL2 (HWREG16(0x40000806)) /*!< Timer_A Capture/Compare Control Register */
#define TA2CCTL3 (HWREG16(0x40000808)) /*!< Timer_A Capture/Compare Control Register */
#define TA2CCTL4 (HWREG16(0x4000080A)) /*!< Timer_A Capture/Compare Control Register */
#define TA2CCTL5 (HWREG16(0x4000080C)) /*!< Timer_A Capture/Compare Control Register */
#define TA2CCTL6 (HWREG16(0x4000080E)) /*!< Timer_A Capture/Compare Control Register */
#define TA2R (HWREG16(0x40000810)) /*!< TimerA register */
#define TA2CCR0 (HWREG16(0x40000812)) /*!< Timer_A Capture/Compare Register */
#define TA2CCR1 (HWREG16(0x40000814)) /*!< Timer_A Capture/Compare Register */
#define TA2CCR2 (HWREG16(0x40000816)) /*!< Timer_A Capture/Compare Register */
#define TA2CCR3 (HWREG16(0x40000818)) /*!< Timer_A Capture/Compare Register */
#define TA2CCR4 (HWREG16(0x4000081A)) /*!< Timer_A Capture/Compare Register */
#define TA2CCR5 (HWREG16(0x4000081C)) /*!< Timer_A Capture/Compare Register */
#define TA2CCR6 (HWREG16(0x4000081E)) /*!< Timer_A Capture/Compare Register */
#define TA2EX0 (HWREG16(0x40000820)) /*!< TimerAx Expansion 0 Register */
#define TA2IV (HWREG16(0x4000082E)) /*!< TimerAx Interrupt Vector Register */
/* Register offsets from TIMER_A2_BASE address */
#define OFS_TA2CTL (0x0000) /*!< TimerAx Control Register */
#define OFS_TA2CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA2CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA2CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA2CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA2CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA2CCTL5 (0x000C) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA2CCTL6 (0x000E) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA2R (0x0010) /*!< TimerA register */
#define OFS_TA2CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */
#define OFS_TA2CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */
#define OFS_TA2CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */
#define OFS_TA2CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */
#define OFS_TA2CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */
#define OFS_TA2CCR5 (0x001C) /*!< Timer_A Capture/Compare Register */
#define OFS_TA2CCR6 (0x001E) /*!< Timer_A Capture/Compare Register */
#define OFS_TA2EX0 (0x0020) /*!< TimerAx Expansion 0 Register */
#define OFS_TA2IV (0x002E) /*!< TimerAx Interrupt Vector Register */
/******************************************************************************
* TIMER_A3 Registers
******************************************************************************/
#define TA3CTL (HWREG16(0x40000C00)) /*!< TimerAx Control Register */
#define TA3CCTL0 (HWREG16(0x40000C02)) /*!< Timer_A Capture/Compare Control Register */
#define TA3CCTL1 (HWREG16(0x40000C04)) /*!< Timer_A Capture/Compare Control Register */
#define TA3CCTL2 (HWREG16(0x40000C06)) /*!< Timer_A Capture/Compare Control Register */
#define TA3CCTL3 (HWREG16(0x40000C08)) /*!< Timer_A Capture/Compare Control Register */
#define TA3CCTL4 (HWREG16(0x40000C0A)) /*!< Timer_A Capture/Compare Control Register */
#define TA3CCTL5 (HWREG16(0x40000C0C)) /*!< Timer_A Capture/Compare Control Register */
#define TA3CCTL6 (HWREG16(0x40000C0E)) /*!< Timer_A Capture/Compare Control Register */
#define TA3R (HWREG16(0x40000C10)) /*!< TimerA register */
#define TA3CCR0 (HWREG16(0x40000C12)) /*!< Timer_A Capture/Compare Register */
#define TA3CCR1 (HWREG16(0x40000C14)) /*!< Timer_A Capture/Compare Register */
#define TA3CCR2 (HWREG16(0x40000C16)) /*!< Timer_A Capture/Compare Register */
#define TA3CCR3 (HWREG16(0x40000C18)) /*!< Timer_A Capture/Compare Register */
#define TA3CCR4 (HWREG16(0x40000C1A)) /*!< Timer_A Capture/Compare Register */
#define TA3CCR5 (HWREG16(0x40000C1C)) /*!< Timer_A Capture/Compare Register */
#define TA3CCR6 (HWREG16(0x40000C1E)) /*!< Timer_A Capture/Compare Register */
#define TA3EX0 (HWREG16(0x40000C20)) /*!< TimerAx Expansion 0 Register */
#define TA3IV (HWREG16(0x40000C2E)) /*!< TimerAx Interrupt Vector Register */
/* Register offsets from TIMER_A3_BASE address */
#define OFS_TA3CTL (0x0000) /*!< TimerAx Control Register */
#define OFS_TA3CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA3CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA3CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA3CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA3CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA3CCTL5 (0x000C) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA3CCTL6 (0x000E) /*!< Timer_A Capture/Compare Control Register */
#define OFS_TA3R (0x0010) /*!< TimerA register */
#define OFS_TA3CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */
#define OFS_TA3CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */
#define OFS_TA3CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */
#define OFS_TA3CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */
#define OFS_TA3CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */
#define OFS_TA3CCR5 (0x001C) /*!< Timer_A Capture/Compare Register */
#define OFS_TA3CCR6 (0x001E) /*!< Timer_A Capture/Compare Register */
#define OFS_TA3EX0 (0x0020) /*!< TimerAx Expansion 0 Register */
#define OFS_TA3IV (0x002E) /*!< TimerAx Interrupt Vector Register */
/******************************************************************************
* WDT_A Registers
******************************************************************************/
#define WDTCTL (HWREG16(0x4000480C)) /*!< Watchdog Timer Control Register */
/* Register offsets from WDT_A_BASE address */
#define OFS_WDTCTL (0x000C) /*!< Watchdog Timer Control Register */
/******************************************************************************
* Peripheral register control bits (legacy section) *
******************************************************************************/
/******************************************************************************
* AES256 Bits (legacy section)
******************************************************************************/
/* AESACTL0[AESOP] Bits */
#define AESOP_OFS AES256_CTL0_OP_OFS /*!< AESOPx Offset */
#define AESOP_M AES256_CTL0_OP_MASK /*!< AES operation */
#define AESOP0 AES256_CTL0_OP0 /*!< AESOP Bit 0 */
#define AESOP1 AES256_CTL0_OP1 /*!< AESOP Bit 1 */
#define AESOP_0 AES256_CTL0_OP_0 /*!< Encryption */
#define AESOP_1 AES256_CTL0_OP_1 /*!< Decryption. The provided key is the same key used for encryption */
#define AESOP_2 AES256_CTL0_OP_2 /*!< Generate first round key required for decryption */
#define AESOP_3 AES256_CTL0_OP_3 /*!< Decryption. The provided key is the first round key required for decryption */
/* AESACTL0[AESKL] Bits */
#define AESKL_OFS AES256_CTL0_KL_OFS /*!< AESKLx Offset */
#define AESKL_M AES256_CTL0_KL_MASK /*!< AES key length */
#define AESKL0 AES256_CTL0_KL0 /*!< AESKL Bit 0 */
#define AESKL1 AES256_CTL0_KL1 /*!< AESKL Bit 1 */
#define AESKL_0 AES256_CTL0_KL_0 /*!< AES128. The key size is 128 bit */
#define AESKL_1 AES256_CTL0_KL_1 /*!< AES192. The key size is 192 bit. */
#define AESKL_2 AES256_CTL0_KL_2 /*!< AES256. The key size is 256 bit */
#define AESKL__128BIT AES256_CTL0_KL__128BIT /*!< AES128. The key size is 128 bit */
#define AESKL__192BIT AES256_CTL0_KL__192BIT /*!< AES192. The key size is 192 bit. */
#define AESKL__256BIT AES256_CTL0_KL__256BIT /*!< AES256. The key size is 256 bit */
/* AESACTL0[AESCM] Bits */
#define AESCM_OFS AES256_CTL0_CM_OFS /*!< AESCMx Offset */
#define AESCM_M AES256_CTL0_CM_MASK /*!< AES cipher mode select */
#define AESCM0 AES256_CTL0_CM0 /*!< AESCM Bit 0 */
#define AESCM1 AES256_CTL0_CM1 /*!< AESCM Bit 1 */
#define AESCM_0 AES256_CTL0_CM_0 /*!< ECB */
#define AESCM_1 AES256_CTL0_CM_1 /*!< CBC */
#define AESCM_2 AES256_CTL0_CM_2 /*!< OFB */
#define AESCM_3 AES256_CTL0_CM_3 /*!< CFB */
#define AESCM__ECB AES256_CTL0_CM__ECB /*!< ECB */
#define AESCM__CBC AES256_CTL0_CM__CBC /*!< CBC */
#define AESCM__OFB AES256_CTL0_CM__OFB /*!< OFB */
#define AESCM__CFB AES256_CTL0_CM__CFB /*!< CFB */
/* AESACTL0[AESSWRST] Bits */
#define AESSWRST_OFS AES256_CTL0_SWRST_OFS /*!< AESSWRST Offset */
#define AESSWRST AES256_CTL0_SWRST /*!< AES software reset */
/* AESACTL0[AESRDYIFG] Bits */
#define AESRDYIFG_OFS AES256_CTL0_RDYIFG_OFS /*!< AESRDYIFG Offset */
#define AESRDYIFG AES256_CTL0_RDYIFG /*!< AES ready interrupt flag */
/* AESACTL0[AESERRFG] Bits */
#define AESERRFG_OFS AES256_CTL0_ERRFG_OFS /*!< AESERRFG Offset */
#define AESERRFG AES256_CTL0_ERRFG /*!< AES error flag */
/* AESACTL0[AESRDYIE] Bits */
#define AESRDYIE_OFS AES256_CTL0_RDYIE_OFS /*!< AESRDYIE Offset */
#define AESRDYIE AES256_CTL0_RDYIE /*!< AES ready interrupt enable */
/* AESACTL0[AESCMEN] Bits */
#define AESCMEN_OFS AES256_CTL0_CMEN_OFS /*!< AESCMEN Offset */
#define AESCMEN AES256_CTL0_CMEN /*!< AES cipher mode enable */
/* AESACTL1[AESBLKCNT] Bits */
#define AESBLKCNT_OFS AES256_CTL1_BLKCNT_OFS /*!< AESBLKCNTx Offset */
#define AESBLKCNT_M AES256_CTL1_BLKCNT_MASK /*!< Cipher Block Counter */
#define AESBLKCNT0 AES256_CTL1_BLKCNT0 /*!< AESBLKCNT Bit 0 */
#define AESBLKCNT1 AES256_CTL1_BLKCNT1 /*!< AESBLKCNT Bit 1 */
#define AESBLKCNT2 AES256_CTL1_BLKCNT2 /*!< AESBLKCNT Bit 2 */
#define AESBLKCNT3 AES256_CTL1_BLKCNT3 /*!< AESBLKCNT Bit 3 */
#define AESBLKCNT4 AES256_CTL1_BLKCNT4 /*!< AESBLKCNT Bit 4 */
#define AESBLKCNT5 AES256_CTL1_BLKCNT5 /*!< AESBLKCNT Bit 5 */
#define AESBLKCNT6 AES256_CTL1_BLKCNT6 /*!< AESBLKCNT Bit 6 */
#define AESBLKCNT7 AES256_CTL1_BLKCNT7 /*!< AESBLKCNT Bit 7 */
/* AESASTAT[AESBUSY] Bits */
#define AESBUSY_OFS AES256_STAT_BUSY_OFS /*!< AESBUSY Offset */
#define AESBUSY AES256_STAT_BUSY /*!< AES accelerator module busy */
/* AESASTAT[AESKEYWR] Bits */
#define AESKEYWR_OFS AES256_STAT_KEYWR_OFS /*!< AESKEYWR Offset */
#define AESKEYWR AES256_STAT_KEYWR /*!< All 16 bytes written to AESAKEY */
/* AESASTAT[AESDINWR] Bits */
#define AESDINWR_OFS AES256_STAT_DINWR_OFS /*!< AESDINWR Offset */
#define AESDINWR AES256_STAT_DINWR /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */
/* AESASTAT[AESDOUTRD] Bits */
#define AESDOUTRD_OFS AES256_STAT_DOUTRD_OFS /*!< AESDOUTRD Offset */
#define AESDOUTRD AES256_STAT_DOUTRD /*!< All 16 bytes read from AESADOUT */
/* AESASTAT[AESKEYCNT] Bits */
#define AESKEYCNT_OFS AES256_STAT_KEYCNT_OFS /*!< AESKEYCNTx Offset */
#define AESKEYCNT_M AES256_STAT_KEYCNT_MASK /*!< Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */
#define AESKEYCNT0 AES256_STAT_KEYCNT0 /*!< AESKEYCNT Bit 0 */
#define AESKEYCNT1 AES256_STAT_KEYCNT1 /*!< AESKEYCNT Bit 1 */
#define AESKEYCNT2 AES256_STAT_KEYCNT2 /*!< AESKEYCNT Bit 2 */
#define AESKEYCNT3 AES256_STAT_KEYCNT3 /*!< AESKEYCNT Bit 3 */
/* AESASTAT[AESDINCNT] Bits */
#define AESDINCNT_OFS AES256_STAT_DINCNT_OFS /*!< AESDINCNTx Offset */
#define AESDINCNT_M AES256_STAT_DINCNT_MASK /*!< Bytes written via AESADIN, AESAXDIN or AESAXIN */
#define AESDINCNT0 AES256_STAT_DINCNT0 /*!< AESDINCNT Bit 0 */
#define AESDINCNT1 AES256_STAT_DINCNT1 /*!< AESDINCNT Bit 1 */
#define AESDINCNT2 AES256_STAT_DINCNT2 /*!< AESDINCNT Bit 2 */
#define AESDINCNT3 AES256_STAT_DINCNT3 /*!< AESDINCNT Bit 3 */
/* AESASTAT[AESDOUTCNT] Bits */
#define AESDOUTCNT_OFS AES256_STAT_DOUTCNT_OFS /*!< AESDOUTCNTx Offset */
#define AESDOUTCNT_M AES256_STAT_DOUTCNT_MASK /*!< Bytes read via AESADOUT */
#define AESDOUTCNT0 AES256_STAT_DOUTCNT0 /*!< AESDOUTCNT Bit 0 */
#define AESDOUTCNT1 AES256_STAT_DOUTCNT1 /*!< AESDOUTCNT Bit 1 */
#define AESDOUTCNT2 AES256_STAT_DOUTCNT2 /*!< AESDOUTCNT Bit 2 */
#define AESDOUTCNT3 AES256_STAT_DOUTCNT3 /*!< AESDOUTCNT Bit 3 */
/* AESAKEY[AESKEY0] Bits */
#define AESKEY0_OFS AES256_KEY_KEY0_OFS /*!< AESKEY0x Offset */
#define AESKEY0_M AES256_KEY_KEY0_MASK /*!< AES key byte n when AESAKEY is written as half-word */
#define AESKEY00 AES256_KEY_KEY00 /*!< AESKEY0 Bit 0 */
#define AESKEY01 AES256_KEY_KEY01 /*!< AESKEY0 Bit 1 */
#define AESKEY02 AES256_KEY_KEY02 /*!< AESKEY0 Bit 2 */
#define AESKEY03 AES256_KEY_KEY03 /*!< AESKEY0 Bit 3 */
#define AESKEY04 AES256_KEY_KEY04 /*!< AESKEY0 Bit 4 */
#define AESKEY05 AES256_KEY_KEY05 /*!< AESKEY0 Bit 5 */
#define AESKEY06 AES256_KEY_KEY06 /*!< AESKEY0 Bit 6 */
#define AESKEY07 AES256_KEY_KEY07 /*!< AESKEY0 Bit 7 */
/* AESAKEY[AESKEY1] Bits */
#define AESKEY1_OFS AES256_KEY_KEY1_OFS /*!< AESKEY1x Offset */
#define AESKEY1_M AES256_KEY_KEY1_MASK /*!< AES key byte n+1 when AESAKEY is written as half-word */
#define AESKEY10 AES256_KEY_KEY10 /*!< AESKEY1 Bit 0 */
#define AESKEY11 AES256_KEY_KEY11 /*!< AESKEY1 Bit 1 */
#define AESKEY12 AES256_KEY_KEY12 /*!< AESKEY1 Bit 2 */
#define AESKEY13 AES256_KEY_KEY13 /*!< AESKEY1 Bit 3 */
#define AESKEY14 AES256_KEY_KEY14 /*!< AESKEY1 Bit 4 */
#define AESKEY15 AES256_KEY_KEY15 /*!< AESKEY1 Bit 5 */
#define AESKEY16 AES256_KEY_KEY16 /*!< AESKEY1 Bit 6 */
#define AESKEY17 AES256_KEY_KEY17 /*!< AESKEY1 Bit 7 */
/* AESADIN[AESDIN0] Bits */
#define AESDIN0_OFS AES256_DIN_DIN0_OFS /*!< AESDIN0x Offset */
#define AESDIN0_M AES256_DIN_DIN0_MASK /*!< AES data in byte n when AESADIN is written as half-word */
#define AESDIN00 AES256_DIN_DIN00 /*!< AESDIN0 Bit 0 */
#define AESDIN01 AES256_DIN_DIN01 /*!< AESDIN0 Bit 1 */
#define AESDIN02 AES256_DIN_DIN02 /*!< AESDIN0 Bit 2 */
#define AESDIN03 AES256_DIN_DIN03 /*!< AESDIN0 Bit 3 */
#define AESDIN04 AES256_DIN_DIN04 /*!< AESDIN0 Bit 4 */
#define AESDIN05 AES256_DIN_DIN05 /*!< AESDIN0 Bit 5 */
#define AESDIN06 AES256_DIN_DIN06 /*!< AESDIN0 Bit 6 */
#define AESDIN07 AES256_DIN_DIN07 /*!< AESDIN0 Bit 7 */
/* AESADIN[AESDIN1] Bits */
#define AESDIN1_OFS AES256_DIN_DIN1_OFS /*!< AESDIN1x Offset */
#define AESDIN1_M AES256_DIN_DIN1_MASK /*!< AES data in byte n+1 when AESADIN is written as half-word */
#define AESDIN10 AES256_DIN_DIN10 /*!< AESDIN1 Bit 0 */
#define AESDIN11 AES256_DIN_DIN11 /*!< AESDIN1 Bit 1 */
#define AESDIN12 AES256_DIN_DIN12 /*!< AESDIN1 Bit 2 */
#define AESDIN13 AES256_DIN_DIN13 /*!< AESDIN1 Bit 3 */
#define AESDIN14 AES256_DIN_DIN14 /*!< AESDIN1 Bit 4 */
#define AESDIN15 AES256_DIN_DIN15 /*!< AESDIN1 Bit 5 */
#define AESDIN16 AES256_DIN_DIN16 /*!< AESDIN1 Bit 6 */
#define AESDIN17 AES256_DIN_DIN17 /*!< AESDIN1 Bit 7 */
/* AESADOUT[AESDOUT0] Bits */
#define AESDOUT0_OFS AES256_DOUT_DOUT0_OFS /*!< AESDOUT0x Offset */
#define AESDOUT0_M AES256_DOUT_DOUT0_MASK /*!< AES data out byte n when AESADOUT is read as half-word */
#define AESDOUT00 AES256_DOUT_DOUT00 /*!< AESDOUT0 Bit 0 */
#define AESDOUT01 AES256_DOUT_DOUT01 /*!< AESDOUT0 Bit 1 */
#define AESDOUT02 AES256_DOUT_DOUT02 /*!< AESDOUT0 Bit 2 */
#define AESDOUT03 AES256_DOUT_DOUT03 /*!< AESDOUT0 Bit 3 */
#define AESDOUT04 AES256_DOUT_DOUT04 /*!< AESDOUT0 Bit 4 */
#define AESDOUT05 AES256_DOUT_DOUT05 /*!< AESDOUT0 Bit 5 */
#define AESDOUT06 AES256_DOUT_DOUT06 /*!< AESDOUT0 Bit 6 */
#define AESDOUT07 AES256_DOUT_DOUT07 /*!< AESDOUT0 Bit 7 */
/* AESADOUT[AESDOUT1] Bits */
#define AESDOUT1_OFS AES256_DOUT_DOUT1_OFS /*!< AESDOUT1x Offset */
#define AESDOUT1_M AES256_DOUT_DOUT1_MASK /*!< AES data out byte n+1 when AESADOUT is read as half-word */
#define AESDOUT10 AES256_DOUT_DOUT10 /*!< AESDOUT1 Bit 0 */
#define AESDOUT11 AES256_DOUT_DOUT11 /*!< AESDOUT1 Bit 1 */
#define AESDOUT12 AES256_DOUT_DOUT12 /*!< AESDOUT1 Bit 2 */
#define AESDOUT13 AES256_DOUT_DOUT13 /*!< AESDOUT1 Bit 3 */
#define AESDOUT14 AES256_DOUT_DOUT14 /*!< AESDOUT1 Bit 4 */
#define AESDOUT15 AES256_DOUT_DOUT15 /*!< AESDOUT1 Bit 5 */
#define AESDOUT16 AES256_DOUT_DOUT16 /*!< AESDOUT1 Bit 6 */
#define AESDOUT17 AES256_DOUT_DOUT17 /*!< AESDOUT1 Bit 7 */
/* AESAXDIN[AESXDIN0] Bits */
#define AESXDIN0_OFS AES256_XDIN_XDIN0_OFS /*!< AESXDIN0x Offset */
#define AESXDIN0_M AES256_XDIN_XDIN0_MASK /*!< AES data in byte n when AESAXDIN is written as half-word */
#define AESXDIN00 AES256_XDIN_XDIN00 /*!< AESXDIN0 Bit 0 */
#define AESXDIN01 AES256_XDIN_XDIN01 /*!< AESXDIN0 Bit 1 */
#define AESXDIN02 AES256_XDIN_XDIN02 /*!< AESXDIN0 Bit 2 */
#define AESXDIN03 AES256_XDIN_XDIN03 /*!< AESXDIN0 Bit 3 */
#define AESXDIN04 AES256_XDIN_XDIN04 /*!< AESXDIN0 Bit 4 */
#define AESXDIN05 AES256_XDIN_XDIN05 /*!< AESXDIN0 Bit 5 */
#define AESXDIN06 AES256_XDIN_XDIN06 /*!< AESXDIN0 Bit 6 */
#define AESXDIN07 AES256_XDIN_XDIN07 /*!< AESXDIN0 Bit 7 */
/* AESAXDIN[AESXDIN1] Bits */
#define AESXDIN1_OFS AES256_XDIN_XDIN1_OFS /*!< AESXDIN1x Offset */
#define AESXDIN1_M AES256_XDIN_XDIN1_MASK /*!< AES data in byte n+1 when AESAXDIN is written as half-word */
#define AESXDIN10 AES256_XDIN_XDIN10 /*!< AESXDIN1 Bit 0 */
#define AESXDIN11 AES256_XDIN_XDIN11 /*!< AESXDIN1 Bit 1 */
#define AESXDIN12 AES256_XDIN_XDIN12 /*!< AESXDIN1 Bit 2 */
#define AESXDIN13 AES256_XDIN_XDIN13 /*!< AESXDIN1 Bit 3 */
#define AESXDIN14 AES256_XDIN_XDIN14 /*!< AESXDIN1 Bit 4 */
#define AESXDIN15 AES256_XDIN_XDIN15 /*!< AESXDIN1 Bit 5 */
#define AESXDIN16 AES256_XDIN_XDIN16 /*!< AESXDIN1 Bit 6 */
#define AESXDIN17 AES256_XDIN_XDIN17 /*!< AESXDIN1 Bit 7 */
/* AESAXIN[AESXIN0] Bits */
#define AESXIN0_OFS AES256_XIN_XIN0_OFS /*!< AESXIN0x Offset */
#define AESXIN0_M AES256_XIN_XIN0_MASK /*!< AES data in byte n when AESAXIN is written as half-word */
#define AESXIN00 AES256_XIN_XIN00 /*!< AESXIN0 Bit 0 */
#define AESXIN01 AES256_XIN_XIN01 /*!< AESXIN0 Bit 1 */
#define AESXIN02 AES256_XIN_XIN02 /*!< AESXIN0 Bit 2 */
#define AESXIN03 AES256_XIN_XIN03 /*!< AESXIN0 Bit 3 */
#define AESXIN04 AES256_XIN_XIN04 /*!< AESXIN0 Bit 4 */
#define AESXIN05 AES256_XIN_XIN05 /*!< AESXIN0 Bit 5 */
#define AESXIN06 AES256_XIN_XIN06 /*!< AESXIN0 Bit 6 */
#define AESXIN07 AES256_XIN_XIN07 /*!< AESXIN0 Bit 7 */
/* AESAXIN[AESXIN1] Bits */
#define AESXIN1_OFS AES256_XIN_XIN1_OFS /*!< AESXIN1x Offset */
#define AESXIN1_M AES256_XIN_XIN1_MASK /*!< AES data in byte n+1 when AESAXIN is written as half-word */
#define AESXIN10 AES256_XIN_XIN10 /*!< AESXIN1 Bit 0 */
#define AESXIN11 AES256_XIN_XIN11 /*!< AESXIN1 Bit 1 */
#define AESXIN12 AES256_XIN_XIN12 /*!< AESXIN1 Bit 2 */
#define AESXIN13 AES256_XIN_XIN13 /*!< AESXIN1 Bit 3 */
#define AESXIN14 AES256_XIN_XIN14 /*!< AESXIN1 Bit 4 */
#define AESXIN15 AES256_XIN_XIN15 /*!< AESXIN1 Bit 5 */
#define AESXIN16 AES256_XIN_XIN16 /*!< AESXIN1 Bit 6 */
#define AESXIN17 AES256_XIN_XIN17 /*!< AESXIN1 Bit 7 */
/******************************************************************************
* CAPTIO Bits (legacy section)
******************************************************************************/
/* CAPTIO0CTL[CAPTIOPISEL] Bits */
#define CAPTIOPISEL_OFS CAPTIO_CTL_PISEL_OFS /*!< CAPTIOPISELx Offset */
#define CAPTIOPISEL_M CAPTIO_CTL_PISEL_MASK /*!< Capacitive Touch IO pin select */
#define CAPTIOPISEL0 CAPTIO_CTL_PISEL0 /*!< CAPTIOPISEL Bit 0 */
#define CAPTIOPISEL1 CAPTIO_CTL_PISEL1 /*!< CAPTIOPISEL Bit 1 */
#define CAPTIOPISEL2 CAPTIO_CTL_PISEL2 /*!< CAPTIOPISEL Bit 2 */
#define CAPTIOPISEL_0 CAPTIO_CTL_PISEL_0 /*!< Px.0 */
#define CAPTIOPISEL_1 CAPTIO_CTL_PISEL_1 /*!< Px.1 */
#define CAPTIOPISEL_2 CAPTIO_CTL_PISEL_2 /*!< Px.2 */
#define CAPTIOPISEL_3 CAPTIO_CTL_PISEL_3 /*!< Px.3 */
#define CAPTIOPISEL_4 CAPTIO_CTL_PISEL_4 /*!< Px.4 */
#define CAPTIOPISEL_5 CAPTIO_CTL_PISEL_5 /*!< Px.5 */
#define CAPTIOPISEL_6 CAPTIO_CTL_PISEL_6 /*!< Px.6 */
#define CAPTIOPISEL_7 CAPTIO_CTL_PISEL_7 /*!< Px.7 */
/* CAPTIO0CTL[CAPTIOPOSEL] Bits */
#define CAPTIOPOSEL_OFS CAPTIO_CTL_POSEL_OFS /*!< CAPTIOPOSELx Offset */
#define CAPTIOPOSEL_M CAPTIO_CTL_POSEL_MASK /*!< Capacitive Touch IO port select */
#define CAPTIOPOSEL0 CAPTIO_CTL_POSEL0 /*!< CAPTIOPOSEL Bit 0 */
#define CAPTIOPOSEL1 CAPTIO_CTL_POSEL1 /*!< CAPTIOPOSEL Bit 1 */
#define CAPTIOPOSEL2 CAPTIO_CTL_POSEL2 /*!< CAPTIOPOSEL Bit 2 */
#define CAPTIOPOSEL3 CAPTIO_CTL_POSEL3 /*!< CAPTIOPOSEL Bit 3 */
#define CAPTIOPOSEL_0 CAPTIO_CTL_POSEL_0 /*!< Px = PJ */
#define CAPTIOPOSEL_1 CAPTIO_CTL_POSEL_1 /*!< Px = P1 */
#define CAPTIOPOSEL_2 CAPTIO_CTL_POSEL_2 /*!< Px = P2 */
#define CAPTIOPOSEL_3 CAPTIO_CTL_POSEL_3 /*!< Px = P3 */
#define CAPTIOPOSEL_4 CAPTIO_CTL_POSEL_4 /*!< Px = P4 */
#define CAPTIOPOSEL_5 CAPTIO_CTL_POSEL_5 /*!< Px = P5 */
#define CAPTIOPOSEL_6 CAPTIO_CTL_POSEL_6 /*!< Px = P6 */
#define CAPTIOPOSEL_7 CAPTIO_CTL_POSEL_7 /*!< Px = P7 */
#define CAPTIOPOSEL_8 CAPTIO_CTL_POSEL_8 /*!< Px = P8 */
#define CAPTIOPOSEL_9 CAPTIO_CTL_POSEL_9 /*!< Px = P9 */
#define CAPTIOPOSEL_10 CAPTIO_CTL_POSEL_10 /*!< Px = P10 */
#define CAPTIOPOSEL_11 CAPTIO_CTL_POSEL_11 /*!< Px = P11 */
#define CAPTIOPOSEL_12 CAPTIO_CTL_POSEL_12 /*!< Px = P12 */
#define CAPTIOPOSEL_13 CAPTIO_CTL_POSEL_13 /*!< Px = P13 */
#define CAPTIOPOSEL_14 CAPTIO_CTL_POSEL_14 /*!< Px = P14 */
#define CAPTIOPOSEL_15 CAPTIO_CTL_POSEL_15 /*!< Px = P15 */
#define CAPTIOPOSEL__PJ CAPTIO_CTL_POSEL__PJ /*!< Px = PJ */
#define CAPTIOPOSEL__P1 CAPTIO_CTL_POSEL__P1 /*!< Px = P1 */
#define CAPTIOPOSEL__P2 CAPTIO_CTL_POSEL__P2 /*!< Px = P2 */
#define CAPTIOPOSEL__P3 CAPTIO_CTL_POSEL__P3 /*!< Px = P3 */
#define CAPTIOPOSEL__P4 CAPTIO_CTL_POSEL__P4 /*!< Px = P4 */
#define CAPTIOPOSEL__P5 CAPTIO_CTL_POSEL__P5 /*!< Px = P5 */
#define CAPTIOPOSEL__P6 CAPTIO_CTL_POSEL__P6 /*!< Px = P6 */
#define CAPTIOPOSEL__P7 CAPTIO_CTL_POSEL__P7 /*!< Px = P7 */
#define CAPTIOPOSEL__P8 CAPTIO_CTL_POSEL__P8 /*!< Px = P8 */
#define CAPTIOPOSEL__P9 CAPTIO_CTL_POSEL__P9 /*!< Px = P9 */
#define CAPTIOPOSEL__P10 CAPTIO_CTL_POSEL__P10 /*!< Px = P10 */
#define CAPTIOPOSEL__P11 CAPTIO_CTL_POSEL__P11 /*!< Px = P11 */
#define CAPTIOPOSEL__P12 CAPTIO_CTL_POSEL__P12 /*!< Px = P12 */
#define CAPTIOPOSEL__P13 CAPTIO_CTL_POSEL__P13 /*!< Px = P13 */
#define CAPTIOPOSEL__P14 CAPTIO_CTL_POSEL__P14 /*!< Px = P14 */
#define CAPTIOPOSEL__P15 CAPTIO_CTL_POSEL__P15 /*!< Px = P15 */
/* CAPTIO0CTL[CAPTIOEN] Bits */
#define CAPTIOEN_OFS CAPTIO_CTL_EN_OFS /*!< CAPTIOEN Offset */
#define CAPTIOEN CAPTIO_CTL_EN /*!< Capacitive Touch IO enable */
/* CAPTIO0CTL[CAPTIOSTATE] Bits */
#define CAPTIOSTATE_OFS CAPTIO_CTL_STATE_OFS /*!< CAPTIOSTATE Offset */
#define CAPTIOSTATE CAPTIO_CTL_STATE /*!< Capacitive Touch IO state */
/******************************************************************************
* COMP_E Bits (legacy section)
******************************************************************************/
/* CE0CTL0[CEIPSEL] Bits */
#define CEIPSEL_OFS COMP_E_CTL0_IPSEL_OFS /*!< CEIPSEL Offset */
#define CEIPSEL_M COMP_E_CTL0_IPSEL_MASK /*!< Channel input selected for the V+ terminal */
#define CEIPSEL0 COMP_E_CTL0_IPSEL0 /*!< CEIPSEL Bit 0 */
#define CEIPSEL1 COMP_E_CTL0_IPSEL1 /*!< CEIPSEL Bit 1 */
#define CEIPSEL2 COMP_E_CTL0_IPSEL2 /*!< CEIPSEL Bit 2 */
#define CEIPSEL3 COMP_E_CTL0_IPSEL3 /*!< CEIPSEL Bit 3 */
#define CEIPSEL_0 COMP_E_CTL0_IPSEL_0 /*!< Channel 0 selected */
#define CEIPSEL_1 COMP_E_CTL0_IPSEL_1 /*!< Channel 1 selected */
#define CEIPSEL_2 COMP_E_CTL0_IPSEL_2 /*!< Channel 2 selected */
#define CEIPSEL_3 COMP_E_CTL0_IPSEL_3 /*!< Channel 3 selected */
#define CEIPSEL_4 COMP_E_CTL0_IPSEL_4 /*!< Channel 4 selected */
#define CEIPSEL_5 COMP_E_CTL0_IPSEL_5 /*!< Channel 5 selected */
#define CEIPSEL_6 COMP_E_CTL0_IPSEL_6 /*!< Channel 6 selected */
#define CEIPSEL_7 COMP_E_CTL0_IPSEL_7 /*!< Channel 7 selected */
#define CEIPSEL_8 COMP_E_CTL0_IPSEL_8 /*!< Channel 8 selected */
#define CEIPSEL_9 COMP_E_CTL0_IPSEL_9 /*!< Channel 9 selected */
#define CEIPSEL_10 COMP_E_CTL0_IPSEL_10 /*!< Channel 10 selected */
#define CEIPSEL_11 COMP_E_CTL0_IPSEL_11 /*!< Channel 11 selected */
#define CEIPSEL_12 COMP_E_CTL0_IPSEL_12 /*!< Channel 12 selected */
#define CEIPSEL_13 COMP_E_CTL0_IPSEL_13 /*!< Channel 13 selected */
#define CEIPSEL_14 COMP_E_CTL0_IPSEL_14 /*!< Channel 14 selected */
#define CEIPSEL_15 COMP_E_CTL0_IPSEL_15 /*!< Channel 15 selected */
/* CE0CTL0[CEIPEN] Bits */
#define CEIPEN_OFS COMP_E_CTL0_IPEN_OFS /*!< CEIPEN Offset */
#define CEIPEN COMP_E_CTL0_IPEN /*!< Channel input enable for the V+ terminal */
/* CE0CTL0[CEIMSEL] Bits */
#define CEIMSEL_OFS COMP_E_CTL0_IMSEL_OFS /*!< CEIMSEL Offset */
#define CEIMSEL_M COMP_E_CTL0_IMSEL_MASK /*!< Channel input selected for the - terminal */
#define CEIMSEL0 COMP_E_CTL0_IMSEL0 /*!< CEIMSEL Bit 0 */
#define CEIMSEL1 COMP_E_CTL0_IMSEL1 /*!< CEIMSEL Bit 1 */
#define CEIMSEL2 COMP_E_CTL0_IMSEL2 /*!< CEIMSEL Bit 2 */
#define CEIMSEL3 COMP_E_CTL0_IMSEL3 /*!< CEIMSEL Bit 3 */
#define CEIMSEL_0 COMP_E_CTL0_IMSEL_0 /*!< Channel 0 selected */
#define CEIMSEL_1 COMP_E_CTL0_IMSEL_1 /*!< Channel 1 selected */
#define CEIMSEL_2 COMP_E_CTL0_IMSEL_2 /*!< Channel 2 selected */
#define CEIMSEL_3 COMP_E_CTL0_IMSEL_3 /*!< Channel 3 selected */
#define CEIMSEL_4 COMP_E_CTL0_IMSEL_4 /*!< Channel 4 selected */
#define CEIMSEL_5 COMP_E_CTL0_IMSEL_5 /*!< Channel 5 selected */
#define CEIMSEL_6 COMP_E_CTL0_IMSEL_6 /*!< Channel 6 selected */
#define CEIMSEL_7 COMP_E_CTL0_IMSEL_7 /*!< Channel 7 selected */
#define CEIMSEL_8 COMP_E_CTL0_IMSEL_8 /*!< Channel 8 selected */
#define CEIMSEL_9 COMP_E_CTL0_IMSEL_9 /*!< Channel 9 selected */
#define CEIMSEL_10 COMP_E_CTL0_IMSEL_10 /*!< Channel 10 selected */
#define CEIMSEL_11 COMP_E_CTL0_IMSEL_11 /*!< Channel 11 selected */
#define CEIMSEL_12 COMP_E_CTL0_IMSEL_12 /*!< Channel 12 selected */
#define CEIMSEL_13 COMP_E_CTL0_IMSEL_13 /*!< Channel 13 selected */
#define CEIMSEL_14 COMP_E_CTL0_IMSEL_14 /*!< Channel 14 selected */
#define CEIMSEL_15 COMP_E_CTL0_IMSEL_15 /*!< Channel 15 selected */
/* CE0CTL0[CEIMEN] Bits */
#define CEIMEN_OFS COMP_E_CTL0_IMEN_OFS /*!< CEIMEN Offset */
#define CEIMEN COMP_E_CTL0_IMEN /*!< Channel input enable for the - terminal */
/* CE0CTL1[CEOUT] Bits */
#define CEOUT_OFS COMP_E_CTL1_OUT_OFS /*!< CEOUT Offset */
#define CEOUT COMP_E_CTL1_OUT /*!< Comparator output value */
/* CE0CTL1[CEOUTPOL] Bits */
#define CEOUTPOL_OFS COMP_E_CTL1_OUTPOL_OFS /*!< CEOUTPOL Offset */
#define CEOUTPOL COMP_E_CTL1_OUTPOL /*!< Comparator output polarity */
/* CE0CTL1[CEF] Bits */
#define CEF_OFS COMP_E_CTL1_F_OFS /*!< CEF Offset */
#define CEF COMP_E_CTL1_F /*!< Comparator output filter */
/* CE0CTL1[CEIES] Bits */
#define CEIES_OFS COMP_E_CTL1_IES_OFS /*!< CEIES Offset */
#define CEIES COMP_E_CTL1_IES /*!< Interrupt edge select for CEIIFG and CEIFG */
/* CE0CTL1[CESHORT] Bits */
#define CESHORT_OFS COMP_E_CTL1_SHORT_OFS /*!< CESHORT Offset */
#define CESHORT COMP_E_CTL1_SHORT /*!< Input short */
/* CE0CTL1[CEEX] Bits */
#define CEEX_OFS COMP_E_CTL1_EX_OFS /*!< CEEX Offset */
#define CEEX COMP_E_CTL1_EX /*!< Exchange */
/* CE0CTL1[CEFDLY] Bits */
#define CEFDLY_OFS COMP_E_CTL1_FDLY_OFS /*!< CEFDLY Offset */
#define CEFDLY_M COMP_E_CTL1_FDLY_MASK /*!< Filter delay */
#define CEFDLY0 COMP_E_CTL1_FDLY0 /*!< CEFDLY Bit 0 */
#define CEFDLY1 COMP_E_CTL1_FDLY1 /*!< CEFDLY Bit 1 */
#define CEFDLY_0 COMP_E_CTL1_FDLY_0 /*!< Typical filter delay of TBD (450) ns */
#define CEFDLY_1 COMP_E_CTL1_FDLY_1 /*!< Typical filter delay of TBD (900) ns */
#define CEFDLY_2 COMP_E_CTL1_FDLY_2 /*!< Typical filter delay of TBD (1800) ns */
#define CEFDLY_3 COMP_E_CTL1_FDLY_3 /*!< Typical filter delay of TBD (3600) ns */
/* CE0CTL1[CEPWRMD] Bits */
#define CEPWRMD_OFS COMP_E_CTL1_PWRMD_OFS /*!< CEPWRMD Offset */
#define CEPWRMD_M COMP_E_CTL1_PWRMD_MASK /*!< Power Mode */
#define CEPWRMD0 COMP_E_CTL1_PWRMD0 /*!< CEPWRMD Bit 0 */
#define CEPWRMD1 COMP_E_CTL1_PWRMD1 /*!< CEPWRMD Bit 1 */
#define CEPWRMD_0 COMP_E_CTL1_PWRMD_0 /*!< High-speed mode */
#define CEPWRMD_1 COMP_E_CTL1_PWRMD_1 /*!< Normal mode */
#define CEPWRMD_2 COMP_E_CTL1_PWRMD_2 /*!< Ultra-low power mode */
/* CE0CTL1[CEON] Bits */
#define CEON_OFS COMP_E_CTL1_ON_OFS /*!< CEON Offset */
#define CEON COMP_E_CTL1_ON /*!< Comparator On */
/* CE0CTL1[CEMRVL] Bits */
#define CEMRVL_OFS COMP_E_CTL1_MRVL_OFS /*!< CEMRVL Offset */
#define CEMRVL COMP_E_CTL1_MRVL /*!< This bit is valid of CEMRVS is set to 1 */
/* CE0CTL1[CEMRVS] Bits */
#define CEMRVS_OFS COMP_E_CTL1_MRVS_OFS /*!< CEMRVS Offset */
#define CEMRVS COMP_E_CTL1_MRVS
/* CE0CTL2[CEREF0] Bits */
#define CEREF0_OFS COMP_E_CTL2_REF0_OFS /*!< CEREF0 Offset */
#define CEREF0_M COMP_E_CTL2_REF0_MASK /*!< Reference resistor tap 0 */
#define CEREF00 COMP_E_CTL2_REF00 /*!< CEREF0 Bit 0 */
#define CEREF01 COMP_E_CTL2_REF01 /*!< CEREF0 Bit 1 */
#define CEREF02 COMP_E_CTL2_REF02 /*!< CEREF0 Bit 2 */
#define CEREF03 COMP_E_CTL2_REF03 /*!< CEREF0 Bit 3 */
#define CEREF04 COMP_E_CTL2_REF04 /*!< CEREF0 Bit 4 */
#define CEREF0_0 COMP_E_CTL2_REF0_0 /*!< Reference resistor tap for setting 0. */
#define CEREF0_1 COMP_E_CTL2_REF0_1 /*!< Reference resistor tap for setting 1. */
#define CEREF0_2 COMP_E_CTL2_REF0_2 /*!< Reference resistor tap for setting 2. */
#define CEREF0_3 COMP_E_CTL2_REF0_3 /*!< Reference resistor tap for setting 3. */
#define CEREF0_4 COMP_E_CTL2_REF0_4 /*!< Reference resistor tap for setting 4. */
#define CEREF0_5 COMP_E_CTL2_REF0_5 /*!< Reference resistor tap for setting 5. */
#define CEREF0_6 COMP_E_CTL2_REF0_6 /*!< Reference resistor tap for setting 6. */
#define CEREF0_7 COMP_E_CTL2_REF0_7 /*!< Reference resistor tap for setting 7. */
#define CEREF0_8 COMP_E_CTL2_REF0_8 /*!< Reference resistor tap for setting 8. */
#define CEREF0_9 COMP_E_CTL2_REF0_9 /*!< Reference resistor tap for setting 9. */
#define CEREF0_10 COMP_E_CTL2_REF0_10 /*!< Reference resistor tap for setting 10. */
#define CEREF0_11 COMP_E_CTL2_REF0_11 /*!< Reference resistor tap for setting 11. */
#define CEREF0_12 COMP_E_CTL2_REF0_12 /*!< Reference resistor tap for setting 12. */
#define CEREF0_13 COMP_E_CTL2_REF0_13 /*!< Reference resistor tap for setting 13. */
#define CEREF0_14 COMP_E_CTL2_REF0_14 /*!< Reference resistor tap for setting 14. */
#define CEREF0_15 COMP_E_CTL2_REF0_15 /*!< Reference resistor tap for setting 15. */
#define CEREF0_16 COMP_E_CTL2_REF0_16 /*!< Reference resistor tap for setting 16. */
#define CEREF0_17 COMP_E_CTL2_REF0_17 /*!< Reference resistor tap for setting 17. */
#define CEREF0_18 COMP_E_CTL2_REF0_18 /*!< Reference resistor tap for setting 18. */
#define CEREF0_19 COMP_E_CTL2_REF0_19 /*!< Reference resistor tap for setting 19. */
#define CEREF0_20 COMP_E_CTL2_REF0_20 /*!< Reference resistor tap for setting 20. */
#define CEREF0_21 COMP_E_CTL2_REF0_21 /*!< Reference resistor tap for setting 21. */
#define CEREF0_22 COMP_E_CTL2_REF0_22 /*!< Reference resistor tap for setting 22. */
#define CEREF0_23 COMP_E_CTL2_REF0_23 /*!< Reference resistor tap for setting 23. */
#define CEREF0_24 COMP_E_CTL2_REF0_24 /*!< Reference resistor tap for setting 24. */
#define CEREF0_25 COMP_E_CTL2_REF0_25 /*!< Reference resistor tap for setting 25. */
#define CEREF0_26 COMP_E_CTL2_REF0_26 /*!< Reference resistor tap for setting 26. */
#define CEREF0_27 COMP_E_CTL2_REF0_27 /*!< Reference resistor tap for setting 27. */
#define CEREF0_28 COMP_E_CTL2_REF0_28 /*!< Reference resistor tap for setting 28. */
#define CEREF0_29 COMP_E_CTL2_REF0_29 /*!< Reference resistor tap for setting 29. */
#define CEREF0_30 COMP_E_CTL2_REF0_30 /*!< Reference resistor tap for setting 30. */
#define CEREF0_31 COMP_E_CTL2_REF0_31 /*!< Reference resistor tap for setting 31. */
/* CE0CTL2[CERSEL] Bits */
#define CERSEL_OFS COMP_E_CTL2_RSEL_OFS /*!< CERSEL Offset */
#define CERSEL COMP_E_CTL2_RSEL /*!< Reference select */
/* CE0CTL2[CERS] Bits */
#define CERS_OFS COMP_E_CTL2_RS_OFS /*!< CERS Offset */
#define CERS_M COMP_E_CTL2_RS_MASK /*!< Reference source */
#define CERS0 COMP_E_CTL2_RS0 /*!< CERS Bit 0 */
#define CERS1 COMP_E_CTL2_RS1 /*!< CERS Bit 1 */
#define CERS_0 COMP_E_CTL2_RS_0 /*!< No current is drawn by the reference circuitry */
#define CERS_1 COMP_E_CTL2_RS_1 /*!< VCC applied to the resistor ladder */
#define CERS_2 COMP_E_CTL2_RS_2 /*!< Shared reference voltage applied to the resistor ladder */
#define CERS_3 COMP_E_CTL2_RS_3 /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */
/* CE0CTL2[CEREF1] Bits */
#define CEREF1_OFS COMP_E_CTL2_REF1_OFS /*!< CEREF1 Offset */
#define CEREF1_M COMP_E_CTL2_REF1_MASK /*!< Reference resistor tap 1 */
#define CEREF10 COMP_E_CTL2_REF10 /*!< CEREF1 Bit 0 */
#define CEREF11 COMP_E_CTL2_REF11 /*!< CEREF1 Bit 1 */
#define CEREF12 COMP_E_CTL2_REF12 /*!< CEREF1 Bit 2 */
#define CEREF13 COMP_E_CTL2_REF13 /*!< CEREF1 Bit 3 */
#define CEREF14 COMP_E_CTL2_REF14 /*!< CEREF1 Bit 4 */
#define CEREF1_0 COMP_E_CTL2_REF1_0 /*!< Reference resistor tap for setting 0. */
#define CEREF1_1 COMP_E_CTL2_REF1_1 /*!< Reference resistor tap for setting 1. */
#define CEREF1_2 COMP_E_CTL2_REF1_2 /*!< Reference resistor tap for setting 2. */
#define CEREF1_3 COMP_E_CTL2_REF1_3 /*!< Reference resistor tap for setting 3. */
#define CEREF1_4 COMP_E_CTL2_REF1_4 /*!< Reference resistor tap for setting 4. */
#define CEREF1_5 COMP_E_CTL2_REF1_5 /*!< Reference resistor tap for setting 5. */
#define CEREF1_6 COMP_E_CTL2_REF1_6 /*!< Reference resistor tap for setting 6. */
#define CEREF1_7 COMP_E_CTL2_REF1_7 /*!< Reference resistor tap for setting 7. */
#define CEREF1_8 COMP_E_CTL2_REF1_8 /*!< Reference resistor tap for setting 8. */
#define CEREF1_9 COMP_E_CTL2_REF1_9 /*!< Reference resistor tap for setting 9. */
#define CEREF1_10 COMP_E_CTL2_REF1_10 /*!< Reference resistor tap for setting 10. */
#define CEREF1_11 COMP_E_CTL2_REF1_11 /*!< Reference resistor tap for setting 11. */
#define CEREF1_12 COMP_E_CTL2_REF1_12 /*!< Reference resistor tap for setting 12. */
#define CEREF1_13 COMP_E_CTL2_REF1_13 /*!< Reference resistor tap for setting 13. */
#define CEREF1_14 COMP_E_CTL2_REF1_14 /*!< Reference resistor tap for setting 14. */
#define CEREF1_15 COMP_E_CTL2_REF1_15 /*!< Reference resistor tap for setting 15. */
#define CEREF1_16 COMP_E_CTL2_REF1_16 /*!< Reference resistor tap for setting 16. */
#define CEREF1_17 COMP_E_CTL2_REF1_17 /*!< Reference resistor tap for setting 17. */
#define CEREF1_18 COMP_E_CTL2_REF1_18 /*!< Reference resistor tap for setting 18. */
#define CEREF1_19 COMP_E_CTL2_REF1_19 /*!< Reference resistor tap for setting 19. */
#define CEREF1_20 COMP_E_CTL2_REF1_20 /*!< Reference resistor tap for setting 20. */
#define CEREF1_21 COMP_E_CTL2_REF1_21 /*!< Reference resistor tap for setting 21. */
#define CEREF1_22 COMP_E_CTL2_REF1_22 /*!< Reference resistor tap for setting 22. */
#define CEREF1_23 COMP_E_CTL2_REF1_23 /*!< Reference resistor tap for setting 23. */
#define CEREF1_24 COMP_E_CTL2_REF1_24 /*!< Reference resistor tap for setting 24. */
#define CEREF1_25 COMP_E_CTL2_REF1_25 /*!< Reference resistor tap for setting 25. */
#define CEREF1_26 COMP_E_CTL2_REF1_26 /*!< Reference resistor tap for setting 26. */
#define CEREF1_27 COMP_E_CTL2_REF1_27 /*!< Reference resistor tap for setting 27. */
#define CEREF1_28 COMP_E_CTL2_REF1_28 /*!< Reference resistor tap for setting 28. */
#define CEREF1_29 COMP_E_CTL2_REF1_29 /*!< Reference resistor tap for setting 29. */
#define CEREF1_30 COMP_E_CTL2_REF1_30 /*!< Reference resistor tap for setting 30. */
#define CEREF1_31 COMP_E_CTL2_REF1_31 /*!< Reference resistor tap for setting 31. */
/* CE0CTL2[CEREFL] Bits */
#define CEREFL_OFS COMP_E_CTL2_REFL_OFS /*!< CEREFL Offset */
#define CEREFL_M COMP_E_CTL2_REFL_MASK /*!< Reference voltage level */
#define CEREFL0 COMP_E_CTL2_REFL0 /*!< CEREFL Bit 0 */
#define CEREFL1 COMP_E_CTL2_REFL1 /*!< CEREFL Bit 1 */
#define CEREFL_0 COMP_E_CTL2_CEREFL_0 /*!< Reference amplifier is disabled. No reference voltage is requested */
#define CEREFL_1 COMP_E_CTL2_CEREFL_1 /*!< 1.2 V is selected as shared reference voltage input */
#define CEREFL_2 COMP_E_CTL2_CEREFL_2 /*!< 2.0 V is selected as shared reference voltage input */
#define CEREFL_3 COMP_E_CTL2_CEREFL_3 /*!< 2.5 V is selected as shared reference voltage input */
#define CEREFL__OFF COMP_E_CTL2_REFL__OFF /*!< Reference amplifier is disabled. No reference voltage is requested */
#define CEREFL__1P2V COMP_E_CTL2_REFL__1P2V /*!< 1.2 V is selected as shared reference voltage input */
#define CEREFL__2P0V COMP_E_CTL2_REFL__2P0V /*!< 2.0 V is selected as shared reference voltage input */
#define CEREFL__2P5V COMP_E_CTL2_REFL__2P5V /*!< 2.5 V is selected as shared reference voltage input */
/* CE0CTL2[CEREFACC] Bits */
#define CEREFACC_OFS COMP_E_CTL2_REFACC_OFS /*!< CEREFACC Offset */
#define CEREFACC COMP_E_CTL2_REFACC /*!< Reference accuracy */
/* CE0CTL3[CEPD0] Bits */
#define CEPD0_OFS COMP_E_CTL3_PD0_OFS /*!< CEPD0 Offset */
#define CEPD0 COMP_E_CTL3_PD0 /*!< Port disable */
/* CE0CTL3[CEPD1] Bits */
#define CEPD1_OFS COMP_E_CTL3_PD1_OFS /*!< CEPD1 Offset */
#define CEPD1 COMP_E_CTL3_PD1 /*!< Port disable */
/* CE0CTL3[CEPD2] Bits */
#define CEPD2_OFS COMP_E_CTL3_PD2_OFS /*!< CEPD2 Offset */
#define CEPD2 COMP_E_CTL3_PD2 /*!< Port disable */
/* CE0CTL3[CEPD3] Bits */
#define CEPD3_OFS COMP_E_CTL3_PD3_OFS /*!< CEPD3 Offset */
#define CEPD3 COMP_E_CTL3_PD3 /*!< Port disable */
/* CE0CTL3[CEPD4] Bits */
#define CEPD4_OFS COMP_E_CTL3_PD4_OFS /*!< CEPD4 Offset */
#define CEPD4 COMP_E_CTL3_PD4 /*!< Port disable */
/* CE0CTL3[CEPD5] Bits */
#define CEPD5_OFS COMP_E_CTL3_PD5_OFS /*!< CEPD5 Offset */
#define CEPD5 COMP_E_CTL3_PD5 /*!< Port disable */
/* CE0CTL3[CEPD6] Bits */
#define CEPD6_OFS COMP_E_CTL3_PD6_OFS /*!< CEPD6 Offset */
#define CEPD6 COMP_E_CTL3_PD6 /*!< Port disable */
/* CE0CTL3[CEPD7] Bits */
#define CEPD7_OFS COMP_E_CTL3_PD7_OFS /*!< CEPD7 Offset */
#define CEPD7 COMP_E_CTL3_PD7 /*!< Port disable */
/* CE0CTL3[CEPD8] Bits */
#define CEPD8_OFS COMP_E_CTL3_PD8_OFS /*!< CEPD8 Offset */
#define CEPD8 COMP_E_CTL3_PD8 /*!< Port disable */
/* CE0CTL3[CEPD9] Bits */
#define CEPD9_OFS COMP_E_CTL3_PD9_OFS /*!< CEPD9 Offset */
#define CEPD9 COMP_E_CTL3_PD9 /*!< Port disable */
/* CE0CTL3[CEPD10] Bits */
#define CEPD10_OFS COMP_E_CTL3_PD10_OFS /*!< CEPD10 Offset */
#define CEPD10 COMP_E_CTL3_PD10 /*!< Port disable */
/* CE0CTL3[CEPD11] Bits */
#define CEPD11_OFS COMP_E_CTL3_PD11_OFS /*!< CEPD11 Offset */
#define CEPD11 COMP_E_CTL3_PD11 /*!< Port disable */
/* CE0CTL3[CEPD12] Bits */
#define CEPD12_OFS COMP_E_CTL3_PD12_OFS /*!< CEPD12 Offset */
#define CEPD12 COMP_E_CTL3_PD12 /*!< Port disable */
/* CE0CTL3[CEPD13] Bits */
#define CEPD13_OFS COMP_E_CTL3_PD13_OFS /*!< CEPD13 Offset */
#define CEPD13 COMP_E_CTL3_PD13 /*!< Port disable */
/* CE0CTL3[CEPD14] Bits */
#define CEPD14_OFS COMP_E_CTL3_PD14_OFS /*!< CEPD14 Offset */
#define CEPD14 COMP_E_CTL3_PD14 /*!< Port disable */
/* CE0CTL3[CEPD15] Bits */
#define CEPD15_OFS COMP_E_CTL3_PD15_OFS /*!< CEPD15 Offset */
#define CEPD15 COMP_E_CTL3_PD15 /*!< Port disable */
/* CE0INT[CEIFG] Bits */
#define CEIFG_OFS COMP_E_INT_IFG_OFS /*!< CEIFG Offset */
#define CEIFG COMP_E_INT_IFG /*!< Comparator output interrupt flag */
/* CE0INT[CEIIFG] Bits */
#define CEIIFG_OFS COMP_E_INT_IIFG_OFS /*!< CEIIFG Offset */
#define CEIIFG COMP_E_INT_IIFG /*!< Comparator output inverted interrupt flag */
/* CE0INT[CERDYIFG] Bits */
#define CERDYIFG_OFS COMP_E_INT_RDYIFG_OFS /*!< CERDYIFG Offset */
#define CERDYIFG COMP_E_INT_RDYIFG /*!< Comparator ready interrupt flag */
/* CE0INT[CEIE] Bits */
#define CEIE_OFS COMP_E_INT_IE_OFS /*!< CEIE Offset */
#define CEIE COMP_E_INT_IE /*!< Comparator output interrupt enable */
/* CE0INT[CEIIE] Bits */
#define CEIIE_OFS COMP_E_INT_IIE_OFS /*!< CEIIE Offset */
#define CEIIE COMP_E_INT_IIE /*!< Comparator output interrupt enable inverted polarity */
/* CE0INT[CERDYIE] Bits */
#define CERDYIE_OFS COMP_E_INT_RDYIE_OFS /*!< CERDYIE Offset */
#define CERDYIE COMP_E_INT_RDYIE /*!< Comparator ready interrupt enable */
/******************************************************************************
* CRC32 Bits (legacy section)
******************************************************************************/
/* DIO_PAIN[P1IN] Bits */
#define P1IN_OFS ( 0) /*!< P1IN Offset */
#define P1IN_M (0x00ff) /*!< Port 1 Input */
/* DIO_PAIN[P2IN] Bits */
#define P2IN_OFS ( 8) /*!< P2IN Offset */
#define P2IN_M (0xff00) /*!< Port 2 Input */
/* DIO_PAOUT[P2OUT] Bits */
#define P2OUT_OFS ( 8) /*!< P2OUT Offset */
#define P2OUT_M (0xff00) /*!< Port 2 Output */
/* DIO_PAOUT[P1OUT] Bits */
#define P1OUT_OFS ( 0) /*!< P1OUT Offset */
#define P1OUT_M (0x00ff) /*!< Port 1 Output */
/* DIO_PADIR[P1DIR] Bits */
#define P1DIR_OFS ( 0) /*!< P1DIR Offset */
#define P1DIR_M (0x00ff) /*!< Port 1 Direction */
/* DIO_PADIR[P2DIR] Bits */
#define P2DIR_OFS ( 8) /*!< P2DIR Offset */
#define P2DIR_M (0xff00) /*!< Port 2 Direction */
/* DIO_PAREN[P1REN] Bits */
#define P1REN_OFS ( 0) /*!< P1REN Offset */
#define P1REN_M (0x00ff) /*!< Port 1 Resistor Enable */
/* DIO_PAREN[P2REN] Bits */
#define P2REN_OFS ( 8) /*!< P2REN Offset */
#define P2REN_M (0xff00) /*!< Port 2 Resistor Enable */
/* DIO_PADS[P1DS] Bits */
#define P1DS_OFS ( 0) /*!< P1DS Offset */
#define P1DS_M (0x00ff) /*!< Port 1 Drive Strength */
/* DIO_PADS[P2DS] Bits */
#define P2DS_OFS ( 8) /*!< P2DS Offset */
#define P2DS_M (0xff00) /*!< Port 2 Drive Strength */
/* DIO_PASEL0[P1SEL0] Bits */
#define P1SEL0_OFS ( 0) /*!< P1SEL0 Offset */
#define P1SEL0_M (0x00ff) /*!< Port 1 Select 0 */
/* DIO_PASEL0[P2SEL0] Bits */
#define P2SEL0_OFS ( 8) /*!< P2SEL0 Offset */
#define P2SEL0_M (0xff00) /*!< Port 2 Select 0 */
/* DIO_PASEL1[P1SEL1] Bits */
#define P1SEL1_OFS ( 0) /*!< P1SEL1 Offset */
#define P1SEL1_M (0x00ff) /*!< Port 1 Select 1 */
/* DIO_PASEL1[P2SEL1] Bits */
#define P2SEL1_OFS ( 8) /*!< P2SEL1 Offset */
#define P2SEL1_M (0xff00) /*!< Port 2 Select 1 */
/* DIO_P1IV[P1IV] Bits */
#define P1IV_OFS ( 0) /*!< P1IV Offset */
#define P1IV_M (0x001f) /*!< Port 1 interrupt vector value */
#define P1IV0 (0x0001) /*!< Port 1 interrupt vector value */
#define P1IV1 (0x0002) /*!< Port 1 interrupt vector value */
#define P1IV2 (0x0004) /*!< Port 1 interrupt vector value */
#define P1IV3 (0x0008) /*!< Port 1 interrupt vector value */
#define P1IV4 (0x0010) /*!< Port 1 interrupt vector value */
#define P1IV_0 (0x0000) /*!< No interrupt pending */
#define P1IV_2 (0x0002) /*!< Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */
#define P1IV_4 (0x0004) /*!< Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */
#define P1IV_6 (0x0006) /*!< Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */
#define P1IV_8 (0x0008) /*!< Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */
#define P1IV_10 (0x000a) /*!< Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */
#define P1IV_12 (0x000c) /*!< Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */
#define P1IV_14 (0x000e) /*!< Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */
#define P1IV_16 (0x0010) /*!< Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */
#define P1IV__NONE (0x0000) /*!< No interrupt pending */
#define P1IV__P1IFG0 (0x0002) /*!< Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */
#define P1IV__P1IFG1 (0x0004) /*!< Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */
#define P1IV__P1IFG2 (0x0006) /*!< Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */
#define P1IV__P1IFG3 (0x0008) /*!< Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */
#define P1IV__P1IFG4 (0x000a) /*!< Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */
#define P1IV__P1IFG5 (0x000c) /*!< Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */
#define P1IV__P1IFG6 (0x000e) /*!< Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */
#define P1IV__P1IFG7 (0x0010) /*!< Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */
/* DIO_PASELC[P1SELC] Bits */
#define P1SELC_OFS ( 0) /*!< P1SELC Offset */
#define P1SELC_M (0x00ff) /*!< Port 1 Complement Select */
/* DIO_PASELC[P2SELC] Bits */
#define P2SELC_OFS ( 8) /*!< P2SELC Offset */
#define P2SELC_M (0xff00) /*!< Port 2 Complement Select */
/* DIO_PAIES[P1IES] Bits */
#define P1IES_OFS ( 0) /*!< P1IES Offset */
#define P1IES_M (0x00ff) /*!< Port 1 Interrupt Edge Select */
/* DIO_PAIES[P2IES] Bits */
#define P2IES_OFS ( 8) /*!< P2IES Offset */
#define P2IES_M (0xff00) /*!< Port 2 Interrupt Edge Select */
/* DIO_PAIE[P1IE] Bits */
#define P1IE_OFS ( 0) /*!< P1IE Offset */
#define P1IE_M (0x00ff) /*!< Port 1 Interrupt Enable */
/* DIO_PAIE[P2IE] Bits */
#define P2IE_OFS ( 8) /*!< P2IE Offset */
#define P2IE_M (0xff00) /*!< Port 2 Interrupt Enable */
/* DIO_PAIFG[P1IFG] Bits */
#define P1IFG_OFS ( 0) /*!< P1IFG Offset */
#define P1IFG_M (0x00ff) /*!< Port 1 Interrupt Flag */
/* DIO_PAIFG[P2IFG] Bits */
#define P2IFG_OFS ( 8) /*!< P2IFG Offset */
#define P2IFG_M (0xff00) /*!< Port 2 Interrupt Flag */
/* DIO_P2IV[P2IV] Bits */
#define P2IV_OFS ( 0) /*!< P2IV Offset */
#define P2IV_M (0x001f) /*!< Port 2 interrupt vector value */
#define P2IV0 (0x0001) /*!< Port 2 interrupt vector value */
#define P2IV1 (0x0002) /*!< Port 2 interrupt vector value */
#define P2IV2 (0x0004) /*!< Port 2 interrupt vector value */
#define P2IV3 (0x0008) /*!< Port 2 interrupt vector value */
#define P2IV4 (0x0010) /*!< Port 2 interrupt vector value */
#define P2IV_0 (0x0000) /*!< No interrupt pending */
#define P2IV_2 (0x0002) /*!< Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */
#define P2IV_4 (0x0004) /*!< Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */
#define P2IV_6 (0x0006) /*!< Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */
#define P2IV_8 (0x0008) /*!< Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */
#define P2IV_10 (0x000a) /*!< Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */
#define P2IV_12 (0x000c) /*!< Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */
#define P2IV_14 (0x000e) /*!< Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */
#define P2IV_16 (0x0010) /*!< Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */
#define P2IV__NONE (0x0000) /*!< No interrupt pending */
#define P2IV__P2IFG0 (0x0002) /*!< Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */
#define P2IV__P2IFG1 (0x0004) /*!< Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */
#define P2IV__P2IFG2 (0x0006) /*!< Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */
#define P2IV__P2IFG3 (0x0008) /*!< Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */
#define P2IV__P2IFG4 (0x000a) /*!< Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */
#define P2IV__P2IFG5 (0x000c) /*!< Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */
#define P2IV__P2IFG6 (0x000e) /*!< Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */
#define P2IV__P2IFG7 (0x0010) /*!< Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */
/* DIO_PBIN[P3IN] Bits */
#define P3IN_OFS ( 0) /*!< P3IN Offset */
#define P3IN_M (0x00ff) /*!< Port 3 Input */
/* DIO_PBIN[P4IN] Bits */
#define P4IN_OFS ( 8) /*!< P4IN Offset */
#define P4IN_M (0xff00) /*!< Port 4 Input */
/* DIO_PBOUT[P3OUT] Bits */
#define P3OUT_OFS ( 0) /*!< P3OUT Offset */
#define P3OUT_M (0x00ff) /*!< Port 3 Output */
/* DIO_PBOUT[P4OUT] Bits */
#define P4OUT_OFS ( 8) /*!< P4OUT Offset */
#define P4OUT_M (0xff00) /*!< Port 4 Output */
/* DIO_PBDIR[P3DIR] Bits */
#define P3DIR_OFS ( 0) /*!< P3DIR Offset */
#define P3DIR_M (0x00ff) /*!< Port 3 Direction */
/* DIO_PBDIR[P4DIR] Bits */
#define P4DIR_OFS ( 8) /*!< P4DIR Offset */
#define P4DIR_M (0xff00) /*!< Port 4 Direction */
/* DIO_PBREN[P3REN] Bits */
#define P3REN_OFS ( 0) /*!< P3REN Offset */
#define P3REN_M (0x00ff) /*!< Port 3 Resistor Enable */
/* DIO_PBREN[P4REN] Bits */
#define P4REN_OFS ( 8) /*!< P4REN Offset */
#define P4REN_M (0xff00) /*!< Port 4 Resistor Enable */
/* DIO_PBDS[P3DS] Bits */
#define P3DS_OFS ( 0) /*!< P3DS Offset */
#define P3DS_M (0x00ff) /*!< Port 3 Drive Strength */
/* DIO_PBDS[P4DS] Bits */
#define P4DS_OFS ( 8) /*!< P4DS Offset */
#define P4DS_M (0xff00) /*!< Port 4 Drive Strength */
/* DIO_PBSEL0[P4SEL0] Bits */
#define P4SEL0_OFS ( 8) /*!< P4SEL0 Offset */
#define P4SEL0_M (0xff00) /*!< Port 4 Select 0 */
/* DIO_PBSEL0[P3SEL0] Bits */
#define P3SEL0_OFS ( 0) /*!< P3SEL0 Offset */
#define P3SEL0_M (0x00ff) /*!< Port 3 Select 0 */
/* DIO_PBSEL1[P3SEL1] Bits */
#define P3SEL1_OFS ( 0) /*!< P3SEL1 Offset */
#define P3SEL1_M (0x00ff) /*!< Port 3 Select 1 */
/* DIO_PBSEL1[P4SEL1] Bits */
#define P4SEL1_OFS ( 8) /*!< P4SEL1 Offset */
#define P4SEL1_M (0xff00) /*!< Port 4 Select 1 */
/* DIO_P3IV[P3IV] Bits */
#define P3IV_OFS ( 0) /*!< P3IV Offset */
#define P3IV_M (0x001f) /*!< Port 3 interrupt vector value */
#define P3IV0 (0x0001) /*!< Port 3 interrupt vector value */
#define P3IV1 (0x0002) /*!< Port 3 interrupt vector value */
#define P3IV2 (0x0004) /*!< Port 3 interrupt vector value */
#define P3IV3 (0x0008) /*!< Port 3 interrupt vector value */
#define P3IV4 (0x0010) /*!< Port 3 interrupt vector value */
#define P3IV_0 (0x0000) /*!< No interrupt pending */
#define P3IV_2 (0x0002) /*!< Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */
#define P3IV_4 (0x0004) /*!< Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */
#define P3IV_6 (0x0006) /*!< Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */
#define P3IV_8 (0x0008) /*!< Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */
#define P3IV_10 (0x000a) /*!< Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */
#define P3IV_12 (0x000c) /*!< Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */
#define P3IV_14 (0x000e) /*!< Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */
#define P3IV_16 (0x0010) /*!< Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */
#define P3IV__NONE (0x0000) /*!< No interrupt pending */
#define P3IV__P3IFG0 (0x0002) /*!< Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */
#define P3IV__P3IFG1 (0x0004) /*!< Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */
#define P3IV__P3IFG2 (0x0006) /*!< Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */
#define P3IV__P3IFG3 (0x0008) /*!< Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */
#define P3IV__P3IFG4 (0x000a) /*!< Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */
#define P3IV__P3IFG5 (0x000c) /*!< Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */
#define P3IV__P3IFG6 (0x000e) /*!< Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */
#define P3IV__P3IFG7 (0x0010) /*!< Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */
/* DIO_PBSELC[P3SELC] Bits */
#define P3SELC_OFS ( 0) /*!< P3SELC Offset */
#define P3SELC_M (0x00ff) /*!< Port 3 Complement Select */
/* DIO_PBSELC[P4SELC] Bits */
#define P4SELC_OFS ( 8) /*!< P4SELC Offset */
#define P4SELC_M (0xff00) /*!< Port 4 Complement Select */
/* DIO_PBIES[P3IES] Bits */
#define P3IES_OFS ( 0) /*!< P3IES Offset */
#define P3IES_M (0x00ff) /*!< Port 3 Interrupt Edge Select */
/* DIO_PBIES[P4IES] Bits */
#define P4IES_OFS ( 8) /*!< P4IES Offset */
#define P4IES_M (0xff00) /*!< Port 4 Interrupt Edge Select */
/* DIO_PBIE[P3IE] Bits */
#define P3IE_OFS ( 0) /*!< P3IE Offset */
#define P3IE_M (0x00ff) /*!< Port 3 Interrupt Enable */
/* DIO_PBIE[P4IE] Bits */
#define P4IE_OFS ( 8) /*!< P4IE Offset */
#define P4IE_M (0xff00) /*!< Port 4 Interrupt Enable */
/* DIO_PBIFG[P3IFG] Bits */
#define P3IFG_OFS ( 0) /*!< P3IFG Offset */
#define P3IFG_M (0x00ff) /*!< Port 3 Interrupt Flag */
/* DIO_PBIFG[P4IFG] Bits */
#define P4IFG_OFS ( 8) /*!< P4IFG Offset */
#define P4IFG_M (0xff00) /*!< Port 4 Interrupt Flag */
/* DIO_P4IV[P4IV] Bits */
#define P4IV_OFS ( 0) /*!< P4IV Offset */
#define P4IV_M (0x001f) /*!< Port 4 interrupt vector value */
#define P4IV0 (0x0001) /*!< Port 4 interrupt vector value */
#define P4IV1 (0x0002) /*!< Port 4 interrupt vector value */
#define P4IV2 (0x0004) /*!< Port 4 interrupt vector value */
#define P4IV3 (0x0008) /*!< Port 4 interrupt vector value */
#define P4IV4 (0x0010) /*!< Port 4 interrupt vector value */
#define P4IV_0 (0x0000) /*!< No interrupt pending */
#define P4IV_2 (0x0002) /*!< Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */
#define P4IV_4 (0x0004) /*!< Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */
#define P4IV_6 (0x0006) /*!< Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */
#define P4IV_8 (0x0008) /*!< Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */
#define P4IV_10 (0x000a) /*!< Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */
#define P4IV_12 (0x000c) /*!< Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */
#define P4IV_14 (0x000e) /*!< Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */
#define P4IV_16 (0x0010) /*!< Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */
#define P4IV__NONE (0x0000) /*!< No interrupt pending */
#define P4IV__P4IFG0 (0x0002) /*!< Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */
#define P4IV__P4IFG1 (0x0004) /*!< Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */
#define P4IV__P4IFG2 (0x0006) /*!< Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */
#define P4IV__P4IFG3 (0x0008) /*!< Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */
#define P4IV__P4IFG4 (0x000a) /*!< Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */
#define P4IV__P4IFG5 (0x000c) /*!< Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */
#define P4IV__P4IFG6 (0x000e) /*!< Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */
#define P4IV__P4IFG7 (0x0010) /*!< Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */
/* DIO_PCIN[P5IN] Bits */
#define P5IN_OFS ( 0) /*!< P5IN Offset */
#define P5IN_M (0x00ff) /*!< Port 5 Input */
/* DIO_PCIN[P6IN] Bits */
#define P6IN_OFS ( 8) /*!< P6IN Offset */
#define P6IN_M (0xff00) /*!< Port 6 Input */
/* DIO_PCOUT[P5OUT] Bits */
#define P5OUT_OFS ( 0) /*!< P5OUT Offset */
#define P5OUT_M (0x00ff) /*!< Port 5 Output */
/* DIO_PCOUT[P6OUT] Bits */
#define P6OUT_OFS ( 8) /*!< P6OUT Offset */
#define P6OUT_M (0xff00) /*!< Port 6 Output */
/* DIO_PCDIR[P5DIR] Bits */
#define P5DIR_OFS ( 0) /*!< P5DIR Offset */
#define P5DIR_M (0x00ff) /*!< Port 5 Direction */
/* DIO_PCDIR[P6DIR] Bits */
#define P6DIR_OFS ( 8) /*!< P6DIR Offset */
#define P6DIR_M (0xff00) /*!< Port 6 Direction */
/* DIO_PCREN[P5REN] Bits */
#define P5REN_OFS ( 0) /*!< P5REN Offset */
#define P5REN_M (0x00ff) /*!< Port 5 Resistor Enable */
/* DIO_PCREN[P6REN] Bits */
#define P6REN_OFS ( 8) /*!< P6REN Offset */
#define P6REN_M (0xff00) /*!< Port 6 Resistor Enable */
/* DIO_PCDS[P5DS] Bits */
#define P5DS_OFS ( 0) /*!< P5DS Offset */
#define P5DS_M (0x00ff) /*!< Port 5 Drive Strength */
/* DIO_PCDS[P6DS] Bits */
#define P6DS_OFS ( 8) /*!< P6DS Offset */
#define P6DS_M (0xff00) /*!< Port 6 Drive Strength */
/* DIO_PCSEL0[P5SEL0] Bits */
#define P5SEL0_OFS ( 0) /*!< P5SEL0 Offset */
#define P5SEL0_M (0x00ff) /*!< Port 5 Select 0 */
/* DIO_PCSEL0[P6SEL0] Bits */
#define P6SEL0_OFS ( 8) /*!< P6SEL0 Offset */
#define P6SEL0_M (0xff00) /*!< Port 6 Select 0 */
/* DIO_PCSEL1[P5SEL1] Bits */
#define P5SEL1_OFS ( 0) /*!< P5SEL1 Offset */
#define P5SEL1_M (0x00ff) /*!< Port 5 Select 1 */
/* DIO_PCSEL1[P6SEL1] Bits */
#define P6SEL1_OFS ( 8) /*!< P6SEL1 Offset */
#define P6SEL1_M (0xff00) /*!< Port 6 Select 1 */
/* DIO_P5IV[P5IV] Bits */
#define P5IV_OFS ( 0) /*!< P5IV Offset */
#define P5IV_M (0x001f) /*!< Port 5 interrupt vector value */
#define P5IV0 (0x0001) /*!< Port 5 interrupt vector value */
#define P5IV1 (0x0002) /*!< Port 5 interrupt vector value */
#define P5IV2 (0x0004) /*!< Port 5 interrupt vector value */
#define P5IV3 (0x0008) /*!< Port 5 interrupt vector value */
#define P5IV4 (0x0010) /*!< Port 5 interrupt vector value */
#define P5IV_0 (0x0000) /*!< No interrupt pending */
#define P5IV_2 (0x0002) /*!< Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */
#define P5IV_4 (0x0004) /*!< Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */
#define P5IV_6 (0x0006) /*!< Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */
#define P5IV_8 (0x0008) /*!< Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */
#define P5IV_10 (0x000a) /*!< Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */
#define P5IV_12 (0x000c) /*!< Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */
#define P5IV_14 (0x000e) /*!< Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */
#define P5IV_16 (0x0010) /*!< Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */
#define P5IV__NONE (0x0000) /*!< No interrupt pending */
#define P5IV__P5IFG0 (0x0002) /*!< Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */
#define P5IV__P5IFG1 (0x0004) /*!< Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */
#define P5IV__P5IFG2 (0x0006) /*!< Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */
#define P5IV__P5IFG3 (0x0008) /*!< Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */
#define P5IV__P5IFG4 (0x000a) /*!< Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */
#define P5IV__P5IFG5 (0x000c) /*!< Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */
#define P5IV__P5IFG6 (0x000e) /*!< Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */
#define P5IV__P5IFG7 (0x0010) /*!< Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */
/* DIO_PCSELC[P5SELC] Bits */
#define P5SELC_OFS ( 0) /*!< P5SELC Offset */
#define P5SELC_M (0x00ff) /*!< Port 5 Complement Select */
/* DIO_PCSELC[P6SELC] Bits */
#define P6SELC_OFS ( 8) /*!< P6SELC Offset */
#define P6SELC_M (0xff00) /*!< Port 6 Complement Select */
/* DIO_PCIES[P5IES] Bits */
#define P5IES_OFS ( 0) /*!< P5IES Offset */
#define P5IES_M (0x00ff) /*!< Port 5 Interrupt Edge Select */
/* DIO_PCIES[P6IES] Bits */
#define P6IES_OFS ( 8) /*!< P6IES Offset */
#define P6IES_M (0xff00) /*!< Port 6 Interrupt Edge Select */
/* DIO_PCIE[P5IE] Bits */
#define P5IE_OFS ( 0) /*!< P5IE Offset */
#define P5IE_M (0x00ff) /*!< Port 5 Interrupt Enable */
/* DIO_PCIE[P6IE] Bits */
#define P6IE_OFS ( 8) /*!< P6IE Offset */
#define P6IE_M (0xff00) /*!< Port 6 Interrupt Enable */
/* DIO_PCIFG[P5IFG] Bits */
#define P5IFG_OFS ( 0) /*!< P5IFG Offset */
#define P5IFG_M (0x00ff) /*!< Port 5 Interrupt Flag */
/* DIO_PCIFG[P6IFG] Bits */
#define P6IFG_OFS ( 8) /*!< P6IFG Offset */
#define P6IFG_M (0xff00) /*!< Port 6 Interrupt Flag */
/* DIO_P6IV[P6IV] Bits */
#define P6IV_OFS ( 0) /*!< P6IV Offset */
#define P6IV_M (0x001f) /*!< Port 6 interrupt vector value */
#define P6IV0 (0x0001) /*!< Port 6 interrupt vector value */
#define P6IV1 (0x0002) /*!< Port 6 interrupt vector value */
#define P6IV2 (0x0004) /*!< Port 6 interrupt vector value */
#define P6IV3 (0x0008) /*!< Port 6 interrupt vector value */
#define P6IV4 (0x0010) /*!< Port 6 interrupt vector value */
#define P6IV_0 (0x0000) /*!< No interrupt pending */
#define P6IV_2 (0x0002) /*!< Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */
#define P6IV_4 (0x0004) /*!< Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */
#define P6IV_6 (0x0006) /*!< Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */
#define P6IV_8 (0x0008) /*!< Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */
#define P6IV_10 (0x000a) /*!< Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */
#define P6IV_12 (0x000c) /*!< Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */
#define P6IV_14 (0x000e) /*!< Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */
#define P6IV_16 (0x0010) /*!< Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */
#define P6IV__NONE (0x0000) /*!< No interrupt pending */
#define P6IV__P6IFG0 (0x0002) /*!< Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */
#define P6IV__P6IFG1 (0x0004) /*!< Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */
#define P6IV__P6IFG2 (0x0006) /*!< Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */
#define P6IV__P6IFG3 (0x0008) /*!< Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */
#define P6IV__P6IFG4 (0x000a) /*!< Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */
#define P6IV__P6IFG5 (0x000c) /*!< Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */
#define P6IV__P6IFG6 (0x000e) /*!< Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */
#define P6IV__P6IFG7 (0x0010) /*!< Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */
/* DIO_PDIN[P7IN] Bits */
#define P7IN_OFS ( 0) /*!< P7IN Offset */
#define P7IN_M (0x00ff) /*!< Port 7 Input */
/* DIO_PDIN[P8IN] Bits */
#define P8IN_OFS ( 8) /*!< P8IN Offset */
#define P8IN_M (0xff00) /*!< Port 8 Input */
/* DIO_PDOUT[P7OUT] Bits */
#define P7OUT_OFS ( 0) /*!< P7OUT Offset */
#define P7OUT_M (0x00ff) /*!< Port 7 Output */
/* DIO_PDOUT[P8OUT] Bits */
#define P8OUT_OFS ( 8) /*!< P8OUT Offset */
#define P8OUT_M (0xff00) /*!< Port 8 Output */
/* DIO_PDDIR[P7DIR] Bits */
#define P7DIR_OFS ( 0) /*!< P7DIR Offset */
#define P7DIR_M (0x00ff) /*!< Port 7 Direction */
/* DIO_PDDIR[P8DIR] Bits */
#define P8DIR_OFS ( 8) /*!< P8DIR Offset */
#define P8DIR_M (0xff00) /*!< Port 8 Direction */
/* DIO_PDREN[P7REN] Bits */
#define P7REN_OFS ( 0) /*!< P7REN Offset */
#define P7REN_M (0x00ff) /*!< Port 7 Resistor Enable */
/* DIO_PDREN[P8REN] Bits */
#define P8REN_OFS ( 8) /*!< P8REN Offset */
#define P8REN_M (0xff00) /*!< Port 8 Resistor Enable */
/* DIO_PDDS[P7DS] Bits */
#define P7DS_OFS ( 0) /*!< P7DS Offset */
#define P7DS_M (0x00ff) /*!< Port 7 Drive Strength */
/* DIO_PDDS[P8DS] Bits */
#define P8DS_OFS ( 8) /*!< P8DS Offset */
#define P8DS_M (0xff00) /*!< Port 8 Drive Strength */
/* DIO_PDSEL0[P7SEL0] Bits */
#define P7SEL0_OFS ( 0) /*!< P7SEL0 Offset */
#define P7SEL0_M (0x00ff) /*!< Port 7 Select 0 */
/* DIO_PDSEL0[P8SEL0] Bits */
#define P8SEL0_OFS ( 8) /*!< P8SEL0 Offset */
#define P8SEL0_M (0xff00) /*!< Port 8 Select 0 */
/* DIO_PDSEL1[P7SEL1] Bits */
#define P7SEL1_OFS ( 0) /*!< P7SEL1 Offset */
#define P7SEL1_M (0x00ff) /*!< Port 7 Select 1 */
/* DIO_PDSEL1[P8SEL1] Bits */
#define P8SEL1_OFS ( 8) /*!< P8SEL1 Offset */
#define P8SEL1_M (0xff00) /*!< Port 8 Select 1 */
/* DIO_P7IV[P7IV] Bits */
#define P7IV_OFS ( 0) /*!< P7IV Offset */
#define P7IV_M (0x001f) /*!< Port 7 interrupt vector value */
#define P7IV0 (0x0001) /*!< Port 7 interrupt vector value */
#define P7IV1 (0x0002) /*!< Port 7 interrupt vector value */
#define P7IV2 (0x0004) /*!< Port 7 interrupt vector value */
#define P7IV3 (0x0008) /*!< Port 7 interrupt vector value */
#define P7IV4 (0x0010) /*!< Port 7 interrupt vector value */
#define P7IV_0 (0x0000) /*!< No interrupt pending */
#define P7IV_2 (0x0002) /*!< Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */
#define P7IV_4 (0x0004) /*!< Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */
#define P7IV_6 (0x0006) /*!< Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */
#define P7IV_8 (0x0008) /*!< Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */
#define P7IV_10 (0x000a) /*!< Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */
#define P7IV_12 (0x000c) /*!< Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */
#define P7IV_14 (0x000e) /*!< Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */
#define P7IV_16 (0x0010) /*!< Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */
#define P7IV__NONE (0x0000) /*!< No interrupt pending */
#define P7IV__P7IFG0 (0x0002) /*!< Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */
#define P7IV__P7IFG1 (0x0004) /*!< Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */
#define P7IV__P7IFG2 (0x0006) /*!< Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */
#define P7IV__P7IFG3 (0x0008) /*!< Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */
#define P7IV__P7IFG4 (0x000a) /*!< Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */
#define P7IV__P7IFG5 (0x000c) /*!< Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */
#define P7IV__P7IFG6 (0x000e) /*!< Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */
#define P7IV__P7IFG7 (0x0010) /*!< Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */
/* DIO_PDSELC[P7SELC] Bits */
#define P7SELC_OFS ( 0) /*!< P7SELC Offset */
#define P7SELC_M (0x00ff) /*!< Port 7 Complement Select */
/* DIO_PDSELC[P8SELC] Bits */
#define P8SELC_OFS ( 8) /*!< P8SELC Offset */
#define P8SELC_M (0xff00) /*!< Port 8 Complement Select */
/* DIO_PDIES[P7IES] Bits */
#define P7IES_OFS ( 0) /*!< P7IES Offset */
#define P7IES_M (0x00ff) /*!< Port 7 Interrupt Edge Select */
/* DIO_PDIES[P8IES] Bits */
#define P8IES_OFS ( 8) /*!< P8IES Offset */
#define P8IES_M (0xff00) /*!< Port 8 Interrupt Edge Select */
/* DIO_PDIE[P7IE] Bits */
#define P7IE_OFS ( 0) /*!< P7IE Offset */
#define P7IE_M (0x00ff) /*!< Port 7 Interrupt Enable */
/* DIO_PDIE[P8IE] Bits */
#define P8IE_OFS ( 8) /*!< P8IE Offset */
#define P8IE_M (0xff00) /*!< Port 8 Interrupt Enable */
/* DIO_PDIFG[P7IFG] Bits */
#define P7IFG_OFS ( 0) /*!< P7IFG Offset */
#define P7IFG_M (0x00ff) /*!< Port 7 Interrupt Flag */
/* DIO_PDIFG[P8IFG] Bits */
#define P8IFG_OFS ( 8) /*!< P8IFG Offset */
#define P8IFG_M (0xff00) /*!< Port 8 Interrupt Flag */
/* DIO_P8IV[P8IV] Bits */
#define P8IV_OFS ( 0) /*!< P8IV Offset */
#define P8IV_M (0x001f) /*!< Port 8 interrupt vector value */
#define P8IV0 (0x0001) /*!< Port 8 interrupt vector value */
#define P8IV1 (0x0002) /*!< Port 8 interrupt vector value */
#define P8IV2 (0x0004) /*!< Port 8 interrupt vector value */
#define P8IV3 (0x0008) /*!< Port 8 interrupt vector value */
#define P8IV4 (0x0010) /*!< Port 8 interrupt vector value */
#define P8IV_0 (0x0000) /*!< No interrupt pending */
#define P8IV_2 (0x0002) /*!< Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */
#define P8IV_4 (0x0004) /*!< Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */
#define P8IV_6 (0x0006) /*!< Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */
#define P8IV_8 (0x0008) /*!< Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */
#define P8IV_10 (0x000a) /*!< Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */
#define P8IV_12 (0x000c) /*!< Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */
#define P8IV_14 (0x000e) /*!< Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */
#define P8IV_16 (0x0010) /*!< Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */
#define P8IV__NONE (0x0000) /*!< No interrupt pending */
#define P8IV__P8IFG0 (0x0002) /*!< Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */
#define P8IV__P8IFG1 (0x0004) /*!< Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */
#define P8IV__P8IFG2 (0x0006) /*!< Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */
#define P8IV__P8IFG3 (0x0008) /*!< Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */
#define P8IV__P8IFG4 (0x000a) /*!< Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */
#define P8IV__P8IFG5 (0x000c) /*!< Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */
#define P8IV__P8IFG6 (0x000e) /*!< Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */
#define P8IV__P8IFG7 (0x0010) /*!< Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */
/* DIO_PEIN[P9IN] Bits */
#define P9IN_OFS ( 0) /*!< P9IN Offset */
#define P9IN_M (0x00ff) /*!< Port 9 Input */
/* DIO_PEIN[P10IN] Bits */
#define P10IN_OFS ( 8) /*!< P10IN Offset */
#define P10IN_M (0xff00) /*!< Port 10 Input */
/* DIO_PEOUT[P9OUT] Bits */
#define P9OUT_OFS ( 0) /*!< P9OUT Offset */
#define P9OUT_M (0x00ff) /*!< Port 9 Output */
/* DIO_PEOUT[P10OUT] Bits */
#define P10OUT_OFS ( 8) /*!< P10OUT Offset */
#define P10OUT_M (0xff00) /*!< Port 10 Output */
/* DIO_PEDIR[P9DIR] Bits */
#define P9DIR_OFS ( 0) /*!< P9DIR Offset */
#define P9DIR_M (0x00ff) /*!< Port 9 Direction */
/* DIO_PEDIR[P10DIR] Bits */
#define P10DIR_OFS ( 8) /*!< P10DIR Offset */
#define P10DIR_M (0xff00) /*!< Port 10 Direction */
/* DIO_PEREN[P9REN] Bits */
#define P9REN_OFS ( 0) /*!< P9REN Offset */
#define P9REN_M (0x00ff) /*!< Port 9 Resistor Enable */
/* DIO_PEREN[P10REN] Bits */
#define P10REN_OFS ( 8) /*!< P10REN Offset */
#define P10REN_M (0xff00) /*!< Port 10 Resistor Enable */
/* DIO_PEDS[P9DS] Bits */
#define P9DS_OFS ( 0) /*!< P9DS Offset */
#define P9DS_M (0x00ff) /*!< Port 9 Drive Strength */
/* DIO_PEDS[P10DS] Bits */
#define P10DS_OFS ( 8) /*!< P10DS Offset */
#define P10DS_M (0xff00) /*!< Port 10 Drive Strength */
/* DIO_PESEL0[P9SEL0] Bits */
#define P9SEL0_OFS ( 0) /*!< P9SEL0 Offset */
#define P9SEL0_M (0x00ff) /*!< Port 9 Select 0 */
/* DIO_PESEL0[P10SEL0] Bits */
#define P10SEL0_OFS ( 8) /*!< P10SEL0 Offset */
#define P10SEL0_M (0xff00) /*!< Port 10 Select 0 */
/* DIO_PESEL1[P9SEL1] Bits */
#define P9SEL1_OFS ( 0) /*!< P9SEL1 Offset */
#define P9SEL1_M (0x00ff) /*!< Port 9 Select 1 */
/* DIO_PESEL1[P10SEL1] Bits */
#define P10SEL1_OFS ( 8) /*!< P10SEL1 Offset */
#define P10SEL1_M (0xff00) /*!< Port 10 Select 1 */
/* DIO_P9IV[P9IV] Bits */
#define P9IV_OFS ( 0) /*!< P9IV Offset */
#define P9IV_M (0x001f) /*!< Port 9 interrupt vector value */
#define P9IV0 (0x0001) /*!< Port 9 interrupt vector value */
#define P9IV1 (0x0002) /*!< Port 9 interrupt vector value */
#define P9IV2 (0x0004) /*!< Port 9 interrupt vector value */
#define P9IV3 (0x0008) /*!< Port 9 interrupt vector value */
#define P9IV4 (0x0010) /*!< Port 9 interrupt vector value */
#define P9IV_0 (0x0000) /*!< No interrupt pending */
#define P9IV_2 (0x0002) /*!< Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */
#define P9IV_4 (0x0004) /*!< Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */
#define P9IV_6 (0x0006) /*!< Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */
#define P9IV_8 (0x0008) /*!< Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */
#define P9IV_10 (0x000a) /*!< Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */
#define P9IV_12 (0x000c) /*!< Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */
#define P9IV_14 (0x000e) /*!< Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */
#define P9IV_16 (0x0010) /*!< Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */
#define P9IV__NONE (0x0000) /*!< No interrupt pending */
#define P9IV__P9IFG0 (0x0002) /*!< Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */
#define P9IV__P9IFG1 (0x0004) /*!< Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */
#define P9IV__P9IFG2 (0x0006) /*!< Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */
#define P9IV__P9IFG3 (0x0008) /*!< Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */
#define P9IV__P9IFG4 (0x000a) /*!< Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */
#define P9IV__P9IFG5 (0x000c) /*!< Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */
#define P9IV__P9IFG6 (0x000e) /*!< Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */
#define P9IV__P9IFG7 (0x0010) /*!< Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */
/* DIO_PESELC[P9SELC] Bits */
#define P9SELC_OFS ( 0) /*!< P9SELC Offset */
#define P9SELC_M (0x00ff) /*!< Port 9 Complement Select */
/* DIO_PESELC[P10SELC] Bits */
#define P10SELC_OFS ( 8) /*!< P10SELC Offset */
#define P10SELC_M (0xff00) /*!< Port 10 Complement Select */
/* DIO_PEIES[P9IES] Bits */
#define P9IES_OFS ( 0) /*!< P9IES Offset */
#define P9IES_M (0x00ff) /*!< Port 9 Interrupt Edge Select */
/* DIO_PEIES[P10IES] Bits */
#define P10IES_OFS ( 8) /*!< P10IES Offset */
#define P10IES_M (0xff00) /*!< Port 10 Interrupt Edge Select */
/* DIO_PEIE[P9IE] Bits */
#define P9IE_OFS ( 0) /*!< P9IE Offset */
#define P9IE_M (0x00ff) /*!< Port 9 Interrupt Enable */
/* DIO_PEIE[P10IE] Bits */
#define P10IE_OFS ( 8) /*!< P10IE Offset */
#define P10IE_M (0xff00) /*!< Port 10 Interrupt Enable */
/* DIO_PEIFG[P9IFG] Bits */
#define P9IFG_OFS ( 0) /*!< P9IFG Offset */
#define P9IFG_M (0x00ff) /*!< Port 9 Interrupt Flag */
/* DIO_PEIFG[P10IFG] Bits */
#define P10IFG_OFS ( 8) /*!< P10IFG Offset */
#define P10IFG_M (0xff00) /*!< Port 10 Interrupt Flag */
/* DIO_P10IV[P10IV] Bits */
#define P10IV_OFS ( 0) /*!< P10IV Offset */
#define P10IV_M (0x001f) /*!< Port 10 interrupt vector value */
#define P10IV0 (0x0001) /*!< Port 10 interrupt vector value */
#define P10IV1 (0x0002) /*!< Port 10 interrupt vector value */
#define P10IV2 (0x0004) /*!< Port 10 interrupt vector value */
#define P10IV3 (0x0008) /*!< Port 10 interrupt vector value */
#define P10IV4 (0x0010) /*!< Port 10 interrupt vector value */
#define P10IV_0 (0x0000) /*!< No interrupt pending */
#define P10IV_2 (0x0002) /*!< Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */
#define P10IV_4 (0x0004) /*!< Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */
#define P10IV_6 (0x0006) /*!< Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */
#define P10IV_8 (0x0008) /*!< Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */
#define P10IV_10 (0x000a) /*!< Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */
#define P10IV_12 (0x000c) /*!< Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */
#define P10IV_14 (0x000e) /*!< Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */
#define P10IV_16 (0x0010) /*!< Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */
#define P10IV__NONE (0x0000) /*!< No interrupt pending */
#define P10IV__P10IFG0 (0x0002) /*!< Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */
#define P10IV__P10IFG1 (0x0004) /*!< Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */
#define P10IV__P10IFG2 (0x0006) /*!< Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */
#define P10IV__P10IFG3 (0x0008) /*!< Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */
#define P10IV__P10IFG4 (0x000a) /*!< Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */
#define P10IV__P10IFG5 (0x000c) /*!< Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */
#define P10IV__P10IFG6 (0x000e) /*!< Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */
#define P10IV__P10IFG7 (0x0010) /*!< Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */
/******************************************************************************
* EUSCI_A Bits (legacy section)
******************************************************************************/
/* UCA0CTLW0[UCSWRST] Bits */
#define UCSWRST_OFS EUSCI_A_CTLW0_SWRST_OFS /*!< UCSWRST Offset */
#define UCSWRST EUSCI_A_CTLW0_SWRST /*!< Software reset enable */
/* UCA0CTLW0[UCTXBRK] Bits */
#define UCTXBRK_OFS EUSCI_A_CTLW0_TXBRK_OFS /*!< UCTXBRK Offset */
#define UCTXBRK EUSCI_A_CTLW0_TXBRK /*!< Transmit break */
/* UCA0CTLW0[UCTXADDR] Bits */
#define UCTXADDR_OFS EUSCI_A_CTLW0_TXADDR_OFS /*!< UCTXADDR Offset */
#define UCTXADDR EUSCI_A_CTLW0_TXADDR /*!< Transmit address */
/* UCA0CTLW0[UCDORM] Bits */
#define UCDORM_OFS EUSCI_A_CTLW0_DORM_OFS /*!< UCDORM Offset */
#define UCDORM EUSCI_A_CTLW0_DORM /*!< Dormant */
/* UCA0CTLW0[UCBRKIE] Bits */
#define UCBRKIE_OFS EUSCI_A_CTLW0_BRKIE_OFS /*!< UCBRKIE Offset */
#define UCBRKIE EUSCI_A_CTLW0_BRKIE /*!< Receive break character interrupt enable */
/* UCA0CTLW0[UCRXEIE] Bits */
#define UCRXEIE_OFS EUSCI_A_CTLW0_RXEIE_OFS /*!< UCRXEIE Offset */
#define UCRXEIE EUSCI_A_CTLW0_RXEIE /*!< Receive erroneous-character interrupt enable */
/* UCA0CTLW0[UCSSEL] Bits */
#define UCSSEL_OFS EUSCI_A_CTLW0_SSEL_OFS /*!< UCSSEL Offset */
#define UCSSEL_M EUSCI_A_CTLW0_SSEL_MASK /*!< eUSCI_A clock source select */
#define UCSSEL0 EUSCI_A_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */
#define UCSSEL1 EUSCI_A_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */
#define UCSSEL_0 EUSCI_A_CTLW0_UCSSEL_0 /*!< UCLK */
#define UCSSEL_1 EUSCI_A_CTLW0_UCSSEL_1 /*!< ACLK */
#define UCSSEL_2 EUSCI_A_CTLW0_UCSSEL_2 /*!< SMCLK */
#define UCSSEL__UCLK EUSCI_A_CTLW0_SSEL__UCLK /*!< UCLK */
#define UCSSEL__ACLK EUSCI_A_CTLW0_SSEL__ACLK /*!< ACLK */
#define UCSSEL__SMCLK EUSCI_A_CTLW0_SSEL__SMCLK /*!< SMCLK */
/* UCA0CTLW0[UCSYNC] Bits */
#define UCSYNC_OFS EUSCI_A_CTLW0_SYNC_OFS /*!< UCSYNC Offset */
#define UCSYNC EUSCI_A_CTLW0_SYNC /*!< Synchronous mode enable */
/* UCA0CTLW0[UCMODE] Bits */
#define UCMODE_OFS EUSCI_A_CTLW0_MODE_OFS /*!< UCMODE Offset */
#define UCMODE_M EUSCI_A_CTLW0_MODE_MASK /*!< eUSCI_A mode */
#define UCMODE0 EUSCI_A_CTLW0_MODE0 /*!< UCMODE Bit 0 */
#define UCMODE1 EUSCI_A_CTLW0_MODE1 /*!< UCMODE Bit 1 */
#define UCMODE_0 EUSCI_A_CTLW0_MODE_0 /*!< UART mode */
#define UCMODE_1 EUSCI_A_CTLW0_MODE_1 /*!< Idle-line multiprocessor mode */
#define UCMODE_2 EUSCI_A_CTLW0_MODE_2 /*!< Address-bit multiprocessor mode */
#define UCMODE_3 EUSCI_A_CTLW0_MODE_3 /*!< UART mode with automatic baud-rate detection */
/* UCA0CTLW0[UCSPB] Bits */
#define UCSPB_OFS EUSCI_A_CTLW0_SPB_OFS /*!< UCSPB Offset */
#define UCSPB EUSCI_A_CTLW0_SPB /*!< Stop bit select */
/* UCA0CTLW0[UC7BIT] Bits */
#define UC7BIT_OFS EUSCI_A_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */
#define UC7BIT EUSCI_A_CTLW0_SEVENBIT /*!< Character length */
/* UCA0CTLW0[UCMSB] Bits */
#define UCMSB_OFS EUSCI_A_CTLW0_MSB_OFS /*!< UCMSB Offset */
#define UCMSB EUSCI_A_CTLW0_MSB /*!< MSB first select */
/* UCA0CTLW0[UCPAR] Bits */
#define UCPAR_OFS EUSCI_A_CTLW0_PAR_OFS /*!< UCPAR Offset */
#define UCPAR EUSCI_A_CTLW0_PAR /*!< Parity select */
/* UCA0CTLW0[UCPEN] Bits */
#define UCPEN_OFS EUSCI_A_CTLW0_PEN_OFS /*!< UCPEN Offset */
#define UCPEN EUSCI_A_CTLW0_PEN /*!< Parity enable */
/* UCA0CTLW0_SPI[UCSWRST] Bits */
//#define UCSWRST_OFS EUSCI_A_CTLW0_SWRST_OFS /*!< UCSWRST Offset */
//#define UCSWRST EUSCI_A_CTLW0_SWRST /*!< Software reset enable */
/* UCA0CTLW0_SPI[UCSTEM] Bits */
#define UCSTEM_OFS EUSCI_A_CTLW0_STEM_OFS /*!< UCSTEM Offset */
#define UCSTEM EUSCI_A_CTLW0_STEM /*!< STE mode select in master mode. */
/* UCA0CTLW0_SPI[UCSSEL] Bits */
//#define UCSSEL_OFS EUSCI_A_CTLW0_SSEL_OFS /*!< UCSSEL Offset */
//#define UCSSEL_M EUSCI_A_CTLW0_SSEL_MASK /*!< eUSCI_A clock source select */
//#define UCSSEL0 EUSCI_A_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */
//#define UCSSEL1 EUSCI_A_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */
//#define UCSSEL_1 EUSCI_A_CTLW0_UCSSEL_1 /*!< ACLK */
//#define UCSSEL_2 EUSCI_A_CTLW0_UCSSEL_2 /*!< SMCLK */
//#define UCSSEL_0 EUSCI_A_CTLW0_SSEL_0 /*!< Reserved */
//#define UCSSEL__ACLK EUSCI_A_CTLW0_SSEL__ACLK /*!< ACLK */
//#define UCSSEL__SMCLK EUSCI_A_CTLW0_SSEL__SMCLK /*!< SMCLK */
/* UCA0CTLW0_SPI[UCSYNC] Bits */
//#define UCSYNC_OFS EUSCI_A_CTLW0_SYNC_OFS /*!< UCSYNC Offset */
//#define UCSYNC EUSCI_A_CTLW0_SYNC /*!< Synchronous mode enable */
/* UCA0CTLW0_SPI[UCMODE] Bits */
//#define UCMODE_OFS EUSCI_A_CTLW0_MODE_OFS /*!< UCMODE Offset */
//#define UCMODE_M EUSCI_A_CTLW0_MODE_MASK /*!< eUSCI mode */
//#define UCMODE0 EUSCI_A_CTLW0_MODE0 /*!< UCMODE Bit 0 */
//#define UCMODE1 EUSCI_A_CTLW0_MODE1 /*!< UCMODE Bit 1 */
//#define UCMODE_0 EUSCI_A_CTLW0_MODE_0 /*!< 3-pin SPI */
//#define UCMODE_1 EUSCI_A_CTLW0_MODE_1 /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
//#define UCMODE_2 EUSCI_A_CTLW0_MODE_2 /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
/* UCA0CTLW0_SPI[UCMST] Bits */
#define UCMST_OFS EUSCI_A_CTLW0_MST_OFS /*!< UCMST Offset */
#define UCMST EUSCI_A_CTLW0_MST /*!< Master mode select */
/* UCA0CTLW0_SPI[UC7BIT] Bits */
//#define UC7BIT_OFS EUSCI_A_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */
//#define UC7BIT EUSCI_A_CTLW0_SEVENBIT /*!< Character length */
/* UCA0CTLW0_SPI[UCMSB] Bits */
//#define UCMSB_OFS EUSCI_A_CTLW0_MSB_OFS /*!< UCMSB Offset */
//#define UCMSB EUSCI_A_CTLW0_MSB /*!< MSB first select */
/* UCA0CTLW0_SPI[UCCKPL] Bits */
#define UCCKPL_OFS EUSCI_A_CTLW0_CKPL_OFS /*!< UCCKPL Offset */
#define UCCKPL EUSCI_A_CTLW0_CKPL /*!< Clock polarity select */
/* UCA0CTLW0_SPI[UCCKPH] Bits */
#define UCCKPH_OFS EUSCI_A_CTLW0_CKPH_OFS /*!< UCCKPH Offset */
#define UCCKPH EUSCI_A_CTLW0_CKPH /*!< Clock phase select */
/* UCA0CTLW1[UCGLIT] Bits */
#define UCGLIT_OFS EUSCI_A_CTLW1_GLIT_OFS /*!< UCGLIT Offset */
#define UCGLIT_M EUSCI_A_CTLW1_GLIT_MASK /*!< Deglitch time */
#define UCGLIT0 EUSCI_A_CTLW1_GLIT0 /*!< UCGLIT Bit 0 */
#define UCGLIT1 EUSCI_A_CTLW1_GLIT1 /*!< UCGLIT Bit 1 */
#define UCGLIT_0 EUSCI_A_CTLW1_GLIT_0 /*!< Approximately 2 ns (equivalent of 1 delay element) */
#define UCGLIT_1 EUSCI_A_CTLW1_GLIT_1 /*!< Approximately 50 ns */
#define UCGLIT_2 EUSCI_A_CTLW1_GLIT_2 /*!< Approximately 100 ns */
#define UCGLIT_3 EUSCI_A_CTLW1_GLIT_3 /*!< Approximately 200 ns */
/* UCA0MCTLW[UCOS16] Bits */
#define UCOS16_OFS EUSCI_A_MCTLW_OS16_OFS /*!< UCOS16 Offset */
#define UCOS16 EUSCI_A_MCTLW_OS16 /*!< Oversampling mode enabled */
/* UCA0MCTLW[UCBRF] Bits */
#define UCBRF_OFS EUSCI_A_MCTLW_BRF_OFS /*!< UCBRF Offset */
#define UCBRF_M EUSCI_A_MCTLW_BRF_MASK /*!< First modulation stage select */
/* UCA0MCTLW[UCBRS] Bits */
#define UCBRS_OFS EUSCI_A_MCTLW_BRS_OFS /*!< UCBRS Offset */
#define UCBRS_M EUSCI_A_MCTLW_BRS_MASK /*!< Second modulation stage select */
/* UCA0STATW[UCBUSY] Bits */
#define UCBUSY_OFS EUSCI_A_STATW_BUSY_OFS /*!< UCBUSY Offset */
#define UCBUSY EUSCI_A_STATW_BUSY /*!< eUSCI_A busy */
/* UCA0STATW[UCADDR_UCIDLE] Bits */
#define UCADDR_UCIDLE_OFS EUSCI_A_STATW_ADDR_IDLE_OFS /*!< UCADDR_UCIDLE Offset */
#define UCADDR_UCIDLE EUSCI_A_STATW_ADDR_IDLE /*!< Address received / Idle line detected */
/* UCA0STATW[UCRXERR] Bits */
#define UCRXERR_OFS EUSCI_A_STATW_RXERR_OFS /*!< UCRXERR Offset */
#define UCRXERR EUSCI_A_STATW_RXERR /*!< Receive error flag */
/* UCA0STATW[UCBRK] Bits */
#define UCBRK_OFS EUSCI_A_STATW_BRK_OFS /*!< UCBRK Offset */
#define UCBRK EUSCI_A_STATW_BRK /*!< Break detect flag */
/* UCA0STATW[UCPE] Bits */
#define UCPE_OFS EUSCI_A_STATW_PE_OFS /*!< UCPE Offset */
#define UCPE EUSCI_A_STATW_PE
/* UCA0STATW[UCOE] Bits */
#define UCOE_OFS EUSCI_A_STATW_OE_OFS /*!< UCOE Offset */
#define UCOE EUSCI_A_STATW_OE /*!< Overrun error flag */
/* UCA0STATW[UCFE] Bits */
#define UCFE_OFS EUSCI_A_STATW_FE_OFS /*!< UCFE Offset */
#define UCFE EUSCI_A_STATW_FE /*!< Framing error flag */
/* UCA0STATW[UCLISTEN] Bits */
#define UCLISTEN_OFS EUSCI_A_STATW_LISTEN_OFS /*!< UCLISTEN Offset */
#define UCLISTEN EUSCI_A_STATW_LISTEN /*!< Listen enable */
/* UCA0STATW_SPI[UCBUSY] Bits */
//#define UCBUSY_OFS EUSCI_A_STATW_BUSY_OFS /*!< UCBUSY Offset */
//#define UCBUSY EUSCI_A_STATW_BUSY /*!< eUSCI_A busy */
/* UCA0STATW_SPI[UCOE] Bits */
//#define UCOE_OFS EUSCI_A_STATW_OE_OFS /*!< UCOE Offset */
//#define UCOE EUSCI_A_STATW_OE /*!< Overrun error flag */
/* UCA0STATW_SPI[UCFE] Bits */
//#define UCFE_OFS EUSCI_A_STATW_FE_OFS /*!< UCFE Offset */
//#define UCFE EUSCI_A_STATW_FE /*!< Framing error flag */
/* UCA0STATW_SPI[UCLISTEN] Bits */
//#define UCLISTEN_OFS EUSCI_A_STATW_LISTEN_OFS /*!< UCLISTEN Offset */
//#define UCLISTEN EUSCI_A_STATW_LISTEN /*!< Listen enable */
/* UCA0RXBUF[UCRXBUF] Bits */
#define UCRXBUF_OFS EUSCI_A_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */
#define UCRXBUF_M EUSCI_A_RXBUF_RXBUF_MASK /*!< Receive data buffer */
/* UCA0RXBUF_SPI[UCRXBUF] Bits */
//#define UCRXBUF_OFS EUSCI_A_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */
//#define UCRXBUF_M EUSCI_A_RXBUF_RXBUF_MASK /*!< Receive data buffer */
/* UCA0TXBUF[UCTXBUF] Bits */
#define UCTXBUF_OFS EUSCI_A_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */
#define UCTXBUF_M EUSCI_A_TXBUF_TXBUF_MASK /*!< Transmit data buffer */
/* UCA0TXBUF_SPI[UCTXBUF] Bits */
//#define UCTXBUF_OFS EUSCI_A_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */
//#define UCTXBUF_M EUSCI_A_TXBUF_TXBUF_MASK /*!< Transmit data buffer */
/* UCA0ABCTL[UCABDEN] Bits */
#define UCABDEN_OFS EUSCI_A_ABCTL_ABDEN_OFS /*!< UCABDEN Offset */
#define UCABDEN EUSCI_A_ABCTL_ABDEN /*!< Automatic baud-rate detect enable */
/* UCA0ABCTL[UCBTOE] Bits */
#define UCBTOE_OFS EUSCI_A_ABCTL_BTOE_OFS /*!< UCBTOE Offset */
#define UCBTOE EUSCI_A_ABCTL_BTOE /*!< Break time out error */
/* UCA0ABCTL[UCSTOE] Bits */
#define UCSTOE_OFS EUSCI_A_ABCTL_STOE_OFS /*!< UCSTOE Offset */
#define UCSTOE EUSCI_A_ABCTL_STOE /*!< Synch field time out error */
/* UCA0ABCTL[UCDELIM] Bits */
#define UCDELIM_OFS EUSCI_A_ABCTL_DELIM_OFS /*!< UCDELIM Offset */
#define UCDELIM_M EUSCI_A_ABCTL_DELIM_MASK /*!< Break/synch delimiter length */
#define UCDELIM0 EUSCI_A_ABCTL_DELIM0 /*!< UCDELIM Bit 0 */
#define UCDELIM1 EUSCI_A_ABCTL_DELIM1 /*!< UCDELIM Bit 1 */
#define UCDELIM_0 EUSCI_A_ABCTL_DELIM_0 /*!< 1 bit time */
#define UCDELIM_1 EUSCI_A_ABCTL_DELIM_1 /*!< 2 bit times */
#define UCDELIM_2 EUSCI_A_ABCTL_DELIM_2 /*!< 3 bit times */
#define UCDELIM_3 EUSCI_A_ABCTL_DELIM_3 /*!< 4 bit times */
/* UCA0IRCTL[UCIREN] Bits */
#define UCIREN_OFS EUSCI_A_IRCTL_IREN_OFS /*!< UCIREN Offset */
#define UCIREN EUSCI_A_IRCTL_IREN /*!< IrDA encoder/decoder enable */
/* UCA0IRCTL[UCIRTXCLK] Bits */
#define UCIRTXCLK_OFS EUSCI_A_IRCTL_IRTXCLK_OFS /*!< UCIRTXCLK Offset */
#define UCIRTXCLK EUSCI_A_IRCTL_IRTXCLK /*!< IrDA transmit pulse clock select */
/* UCA0IRCTL[UCIRTXPL] Bits */
#define UCIRTXPL_OFS EUSCI_A_IRCTL_IRTXPL_OFS /*!< UCIRTXPL Offset */
#define UCIRTXPL_M EUSCI_A_IRCTL_IRTXPL_MASK /*!< Transmit pulse length */
/* UCA0IRCTL[UCIRRXFE] Bits */
#define UCIRRXFE_OFS EUSCI_A_IRCTL_IRRXFE_OFS /*!< UCIRRXFE Offset */
#define UCIRRXFE EUSCI_A_IRCTL_IRRXFE /*!< IrDA receive filter enabled */
/* UCA0IRCTL[UCIRRXPL] Bits */
#define UCIRRXPL_OFS EUSCI_A_IRCTL_IRRXPL_OFS /*!< UCIRRXPL Offset */
#define UCIRRXPL EUSCI_A_IRCTL_IRRXPL /*!< IrDA receive input UCAxRXD polarity */
/* UCA0IRCTL[UCIRRXFL] Bits */
#define UCIRRXFL_OFS EUSCI_A_IRCTL_IRRXFL_OFS /*!< UCIRRXFL Offset */
#define UCIRRXFL_M EUSCI_A_IRCTL_IRRXFL_MASK /*!< Receive filter length */
/* UCA0IE[UCRXIE] Bits */
#define UCRXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Offset */
#define UCRXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */
/* UCA0IE[UCTXIE] Bits */
#define UCTXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Offset */
#define UCTXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */
/* UCA0IE[UCSTTIE] Bits */
#define UCSTTIE_OFS EUSCI_A_IE_STTIE_OFS /*!< UCSTTIE Offset */
#define UCSTTIE EUSCI_A_IE_STTIE /*!< Start bit interrupt enable */
/* UCA0IE[UCTXCPTIE] Bits */
#define UCTXCPTIE_OFS EUSCI_A_IE_TXCPTIE_OFS /*!< UCTXCPTIE Offset */
#define UCTXCPTIE EUSCI_A_IE_TXCPTIE /*!< Transmit complete interrupt enable */
/* UCA0IE_SPI[UCRXIE] Bits */
//#define UCRXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Offset */
//#define UCRXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */
/* UCA0IE_SPI[UCTXIE] Bits */
//#define UCTXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Offset */
//#define UCTXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */
/* UCA0IFG[UCRXIFG] Bits */
#define UCRXIFG_OFS EUSCI_A_IFG_RXIFG_OFS /*!< UCRXIFG Offset */
#define UCRXIFG EUSCI_A_IFG_RXIFG /*!< Receive interrupt flag */
/* UCA0IFG[UCTXIFG] Bits */
#define UCTXIFG_OFS EUSCI_A_IFG_TXIFG_OFS /*!< UCTXIFG Offset */
#define UCTXIFG EUSCI_A_IFG_TXIFG /*!< Transmit interrupt flag */
/* UCA0IFG[UCSTTIFG] Bits */
#define UCSTTIFG_OFS EUSCI_A_IFG_STTIFG_OFS /*!< UCSTTIFG Offset */
#define UCSTTIFG EUSCI_A_IFG_STTIFG /*!< Start bit interrupt flag */
/* UCA0IFG[UCTXCPTIFG] Bits */
#define UCTXCPTIFG_OFS EUSCI_A_IFG_TXCPTIFG_OFS /*!< UCTXCPTIFG Offset */
#define UCTXCPTIFG EUSCI_A_IFG_TXCPTIFG /*!< Transmit ready interrupt enable */
/* UCA0IFG_SPI[UCRXIFG] Bits */
//#define UCRXIFG_OFS EUSCI_A_IFG_RXIFG_OFS /*!< UCRXIFG Offset */
//#define UCRXIFG EUSCI_A_IFG_RXIFG /*!< Receive interrupt flag */
/* UCA0IFG_SPI[UCTXIFG] Bits */
//#define UCTXIFG_OFS EUSCI_A_IFG_TXIFG_OFS /*!< UCTXIFG Offset */
//#define UCTXIFG EUSCI_A_IFG_TXIFG /*!< Transmit interrupt flag */
/******************************************************************************
* EUSCI_B Bits (legacy section)
******************************************************************************/
/* UCB0CTLW0[UCSWRST] Bits */
//#define UCSWRST_OFS EUSCI_B_CTLW0_SWRST_OFS /*!< UCSWRST Offset */
//#define UCSWRST EUSCI_B_CTLW0_SWRST /*!< Software reset enable */
/* UCB0CTLW0[UCTXSTT] Bits */
#define UCTXSTT_OFS EUSCI_B_CTLW0_TXSTT_OFS /*!< UCTXSTT Offset */
#define UCTXSTT EUSCI_B_CTLW0_TXSTT /*!< Transmit START condition in master mode */
/* UCB0CTLW0[UCTXSTP] Bits */
#define UCTXSTP_OFS EUSCI_B_CTLW0_TXSTP_OFS /*!< UCTXSTP Offset */
#define UCTXSTP EUSCI_B_CTLW0_TXSTP /*!< Transmit STOP condition in master mode */
/* UCB0CTLW0[UCTXNACK] Bits */
#define UCTXNACK_OFS EUSCI_B_CTLW0_TXNACK_OFS /*!< UCTXNACK Offset */
#define UCTXNACK EUSCI_B_CTLW0_TXNACK /*!< Transmit a NACK */
/* UCB0CTLW0[UCTR] Bits */
#define UCTR_OFS EUSCI_B_CTLW0_TR_OFS /*!< UCTR Offset */
#define UCTR EUSCI_B_CTLW0_TR /*!< Transmitter/receiver */
/* UCB0CTLW0[UCTXACK] Bits */
#define UCTXACK_OFS EUSCI_B_CTLW0_TXACK_OFS /*!< UCTXACK Offset */
#define UCTXACK EUSCI_B_CTLW0_TXACK /*!< Transmit ACK condition in slave mode */
/* UCB0CTLW0[UCSSEL] Bits */
//#define UCSSEL_OFS EUSCI_B_CTLW0_SSEL_OFS /*!< UCSSEL Offset */
//#define UCSSEL_M EUSCI_B_CTLW0_SSEL_MASK /*!< eUSCI_B clock source select */
//#define UCSSEL0 EUSCI_B_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */
//#define UCSSEL1 EUSCI_B_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */
//#define UCSSEL_0 EUSCI_B_CTLW0_UCSSEL_0 /*!< UCLKI */
//#define UCSSEL_1 EUSCI_B_CTLW0_UCSSEL_1 /*!< ACLK */
//#define UCSSEL_2 EUSCI_B_CTLW0_UCSSEL_2 /*!< SMCLK */
#define UCSSEL__UCLKI EUSCI_B_CTLW0_SSEL__UCLKI /*!< UCLKI */
//#define UCSSEL__ACLK EUSCI_B_CTLW0_SSEL__ACLK /*!< ACLK */
//#define UCSSEL__SMCLK EUSCI_B_CTLW0_SSEL__SMCLK /*!< SMCLK */
#define UCSSEL_3 EUSCI_B_CTLW0_SSEL_3 /*!< SMCLK */
/* UCB0CTLW0[UCSYNC] Bits */
//#define UCSYNC_OFS EUSCI_B_CTLW0_SYNC_OFS /*!< UCSYNC Offset */
//#define UCSYNC EUSCI_B_CTLW0_SYNC /*!< Synchronous mode enable */
/* UCB0CTLW0[UCMODE] Bits */
//#define UCMODE_OFS EUSCI_B_CTLW0_MODE_OFS /*!< UCMODE Offset */
//#define UCMODE_M EUSCI_B_CTLW0_MODE_MASK /*!< eUSCI_B mode */
//#define UCMODE0 EUSCI_B_CTLW0_MODE0 /*!< UCMODE Bit 0 */
//#define UCMODE1 EUSCI_B_CTLW0_MODE1 /*!< UCMODE Bit 1 */
//#define UCMODE_0 EUSCI_B_CTLW0_MODE_0 /*!< 3-pin SPI */
//#define UCMODE_1 EUSCI_B_CTLW0_MODE_1 /*!< 4-pin SPI (master or slave enabled if STE = 1) */
//#define UCMODE_2 EUSCI_B_CTLW0_MODE_2 /*!< 4-pin SPI (master or slave enabled if STE = 0) */
//#define UCMODE_3 EUSCI_B_CTLW0_MODE_3 /*!< I2C mode */
/* UCB0CTLW0[UCMST] Bits */
//#define UCMST_OFS EUSCI_B_CTLW0_MST_OFS /*!< UCMST Offset */
//#define UCMST EUSCI_B_CTLW0_MST /*!< Master mode select */
/* UCB0CTLW0[UCMM] Bits */
#define UCMM_OFS EUSCI_B_CTLW0_MM_OFS /*!< UCMM Offset */
#define UCMM EUSCI_B_CTLW0_MM /*!< Multi-master environment select */
/* UCB0CTLW0[UCSLA10] Bits */
#define UCSLA10_OFS EUSCI_B_CTLW0_SLA10_OFS /*!< UCSLA10 Offset */
#define UCSLA10 EUSCI_B_CTLW0_SLA10 /*!< Slave addressing mode select */
/* UCB0CTLW0[UCA10] Bits */
#define UCA10_OFS EUSCI_B_CTLW0_A10_OFS /*!< UCA10 Offset */
#define UCA10 EUSCI_B_CTLW0_A10 /*!< Own addressing mode select */
/* UCB0CTLW0_SPI[UCSWRST] Bits */
//#define UCSWRST_OFS EUSCI_B_CTLW0_SWRST_OFS /*!< UCSWRST Offset */
//#define UCSWRST EUSCI_B_CTLW0_SWRST /*!< Software reset enable */
/* UCB0CTLW0_SPI[UCSTEM] Bits */
//#define UCSTEM_OFS EUSCI_B_CTLW0_STEM_OFS /*!< UCSTEM Offset */
//#define UCSTEM EUSCI_B_CTLW0_STEM /*!< STE mode select in master mode. */
/* UCB0CTLW0_SPI[UCSSEL] Bits */
//#define UCSSEL_OFS EUSCI_B_CTLW0_SSEL_OFS /*!< UCSSEL Offset */
//#define UCSSEL_M EUSCI_B_CTLW0_SSEL_MASK /*!< eUSCI_B clock source select */
//#define UCSSEL0 EUSCI_B_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */
//#define UCSSEL1 EUSCI_B_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */
//#define UCSSEL_1 EUSCI_B_CTLW0_UCSSEL_1 /*!< ACLK */
//#define UCSSEL_2 EUSCI_B_CTLW0_UCSSEL_2 /*!< SMCLK */
//#define UCSSEL_0 EUSCI_B_CTLW0_SSEL_0 /*!< Reserved */
//#define UCSSEL__ACLK EUSCI_B_CTLW0_SSEL__ACLK /*!< ACLK */
//#define UCSSEL__SMCLK EUSCI_B_CTLW0_SSEL__SMCLK /*!< SMCLK */
//#define UCSSEL_3 EUSCI_B_CTLW0_SSEL_3 /*!< SMCLK */
/* UCB0CTLW0_SPI[UCSYNC] Bits */
//#define UCSYNC_OFS EUSCI_B_CTLW0_SYNC_OFS /*!< UCSYNC Offset */
//#define UCSYNC EUSCI_B_CTLW0_SYNC /*!< Synchronous mode enable */
/* UCB0CTLW0_SPI[UCMODE] Bits */
//#define UCMODE_OFS EUSCI_B_CTLW0_MODE_OFS /*!< UCMODE Offset */
//#define UCMODE_M EUSCI_B_CTLW0_MODE_MASK /*!< eUSCI mode */
//#define UCMODE0 EUSCI_B_CTLW0_MODE0 /*!< UCMODE Bit 0 */
//#define UCMODE1 EUSCI_B_CTLW0_MODE1 /*!< UCMODE Bit 1 */
//#define UCMODE_0 EUSCI_B_CTLW0_MODE_0 /*!< 3-pin SPI */
//#define UCMODE_1 EUSCI_B_CTLW0_MODE_1 /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
//#define UCMODE_2 EUSCI_B_CTLW0_MODE_2 /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
//#define UCMODE_3 EUSCI_B_CTLW0_MODE_3 /*!< I2C mode */
/* UCB0CTLW0_SPI[UCMST] Bits */
//#define UCMST_OFS EUSCI_B_CTLW0_MST_OFS /*!< UCMST Offset */
//#define UCMST EUSCI_B_CTLW0_MST /*!< Master mode select */
/* UCB0CTLW0_SPI[UC7BIT] Bits */
//#define UC7BIT_OFS EUSCI_B_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */
//#define UC7BIT EUSCI_B_CTLW0_SEVENBIT /*!< Character length */
/* UCB0CTLW0_SPI[UCMSB] Bits */
//#define UCMSB_OFS EUSCI_B_CTLW0_MSB_OFS /*!< UCMSB Offset */
//#define UCMSB EUSCI_B_CTLW0_MSB /*!< MSB first select */
/* UCB0CTLW0_SPI[UCCKPL] Bits */
//#define UCCKPL_OFS EUSCI_B_CTLW0_CKPL_OFS /*!< UCCKPL Offset */
//#define UCCKPL EUSCI_B_CTLW0_CKPL /*!< Clock polarity select */
/* UCB0CTLW0_SPI[UCCKPH] Bits */
//#define UCCKPH_OFS EUSCI_B_CTLW0_CKPH_OFS /*!< UCCKPH Offset */
//#define UCCKPH EUSCI_B_CTLW0_CKPH /*!< Clock phase select */
/* UCB0CTLW1[UCGLIT] Bits */
//#define UCGLIT_OFS EUSCI_B_CTLW1_GLIT_OFS /*!< UCGLIT Offset */
//#define UCGLIT_M EUSCI_B_CTLW1_GLIT_MASK /*!< Deglitch time */
//#define UCGLIT0 EUSCI_B_CTLW1_GLIT0 /*!< UCGLIT Bit 0 */
//#define UCGLIT1 EUSCI_B_CTLW1_GLIT1 /*!< UCGLIT Bit 1 */
//#define UCGLIT_0 EUSCI_B_CTLW1_GLIT_0 /*!< 50 ns */
//#define UCGLIT_1 EUSCI_B_CTLW1_GLIT_1 /*!< 25 ns */
//#define UCGLIT_2 EUSCI_B_CTLW1_GLIT_2 /*!< 12.5 ns */
//#define UCGLIT_3 EUSCI_B_CTLW1_GLIT_3 /*!< 6.25 ns */
/* UCB0CTLW1[UCASTP] Bits */
#define UCASTP_OFS EUSCI_B_CTLW1_ASTP_OFS /*!< UCASTP Offset */
#define UCASTP_M EUSCI_B_CTLW1_ASTP_MASK /*!< Automatic STOP condition generation */
#define UCASTP0 EUSCI_B_CTLW1_ASTP0 /*!< UCASTP Bit 0 */
#define UCASTP1 EUSCI_B_CTLW1_ASTP1 /*!< UCASTP Bit 1 */
#define UCASTP_0 EUSCI_B_CTLW1_ASTP_0 /*!< No automatic STOP generation. The STOP condition is generated after the user */
/* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
#define UCASTP_1 EUSCI_B_CTLW1_ASTP_1 /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */
/* UCBxTBCNT */
#define UCASTP_2 EUSCI_B_CTLW1_ASTP_2 /*!< A STOP condition is generated automatically after the byte counter value */
/* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */
/* threshold */
/* UCB0CTLW1[UCSWACK] Bits */
#define UCSWACK_OFS EUSCI_B_CTLW1_SWACK_OFS /*!< UCSWACK Offset */
#define UCSWACK EUSCI_B_CTLW1_SWACK /*!< SW or HW ACK control */
/* UCB0CTLW1[UCSTPNACK] Bits */
#define UCSTPNACK_OFS EUSCI_B_CTLW1_STPNACK_OFS /*!< UCSTPNACK Offset */
#define UCSTPNACK EUSCI_B_CTLW1_STPNACK /*!< ACK all master bytes */
/* UCB0CTLW1[UCCLTO] Bits */
#define UCCLTO_OFS EUSCI_B_CTLW1_CLTO_OFS /*!< UCCLTO Offset */
#define UCCLTO_M EUSCI_B_CTLW1_CLTO_MASK /*!< Clock low timeout select */
#define UCCLTO0 EUSCI_B_CTLW1_CLTO0 /*!< UCCLTO Bit 0 */
#define UCCLTO1 EUSCI_B_CTLW1_CLTO1 /*!< UCCLTO Bit 1 */
#define UCCLTO_0 EUSCI_B_CTLW1_CLTO_0 /*!< Disable clock low timeout counter */
#define UCCLTO_1 EUSCI_B_CTLW1_CLTO_1 /*!< 135 000 SYSCLK cycles (approximately 28 ms) */
#define UCCLTO_2 EUSCI_B_CTLW1_CLTO_2 /*!< 150 000 SYSCLK cycles (approximately 31 ms) */
#define UCCLTO_3 EUSCI_B_CTLW1_CLTO_3 /*!< 165 000 SYSCLK cycles (approximately 34 ms) */
/* UCB0CTLW1[UCETXINT] Bits */
#define UCETXINT_OFS EUSCI_B_CTLW1_ETXINT_OFS /*!< UCETXINT Offset */
#define UCETXINT EUSCI_B_CTLW1_ETXINT /*!< Early UCTXIFG0 */
/* UCB0STATW[UCBBUSY] Bits */
#define UCBBUSY_OFS EUSCI_B_STATW_BBUSY_OFS /*!< UCBBUSY Offset */
#define UCBBUSY EUSCI_B_STATW_BBUSY /*!< Bus busy */
/* UCB0STATW[UCGC] Bits */
#define UCGC_OFS EUSCI_B_STATW_GC_OFS /*!< UCGC Offset */
#define UCGC EUSCI_B_STATW_GC /*!< General call address received */
/* UCB0STATW[UCSCLLOW] Bits */
#define UCSCLLOW_OFS EUSCI_B_STATW_SCLLOW_OFS /*!< UCSCLLOW Offset */
#define UCSCLLOW EUSCI_B_STATW_SCLLOW /*!< SCL low */
/* UCB0STATW[UCBCNT] Bits */
#define UCBCNT_OFS EUSCI_B_STATW_BCNT_OFS /*!< UCBCNT Offset */
#define UCBCNT_M EUSCI_B_STATW_BCNT_MASK /*!< Hardware byte counter value */
/* UCB0STATW_SPI[UCBUSY] Bits */
//#define UCBUSY_OFS EUSCI_B_STATW_BUSY_OFS /*!< UCBUSY Offset */
//#define UCBUSY EUSCI_B_STATW_BUSY /*!< eUSCI_B busy */
/* UCB0STATW_SPI[UCOE] Bits */
//#define UCOE_OFS EUSCI_B_STATW_OE_OFS /*!< UCOE Offset */
//#define UCOE EUSCI_B_STATW_OE /*!< Overrun error flag */
/* UCB0STATW_SPI[UCFE] Bits */
//#define UCFE_OFS EUSCI_B_STATW_FE_OFS /*!< UCFE Offset */
//#define UCFE EUSCI_B_STATW_FE /*!< Framing error flag */
/* UCB0STATW_SPI[UCLISTEN] Bits */
//#define UCLISTEN_OFS EUSCI_B_STATW_LISTEN_OFS /*!< UCLISTEN Offset */
//#define UCLISTEN EUSCI_B_STATW_LISTEN /*!< Listen enable */
/* UCB0TBCNT[UCTBCNT] Bits */
#define UCTBCNT_OFS EUSCI_B_TBCNT_TBCNT_OFS /*!< UCTBCNT Offset */
#define UCTBCNT_M EUSCI_B_TBCNT_TBCNT_MASK /*!< Byte counter threshold value */
/* UCB0RXBUF[UCRXBUF] Bits */
//#define UCRXBUF_OFS EUSCI_B_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */
//#define UCRXBUF_M EUSCI_B_RXBUF_RXBUF_MASK /*!< Receive data buffer */
/* UCB0RXBUF_SPI[UCRXBUF] Bits */
//#define UCRXBUF_OFS EUSCI_B_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */
//#define UCRXBUF_M EUSCI_B_RXBUF_RXBUF_MASK /*!< Receive data buffer */
/* UCB0TXBUF[UCTXBUF] Bits */
//#define UCTXBUF_OFS EUSCI_B_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */
//#define UCTXBUF_M EUSCI_B_TXBUF_TXBUF_MASK /*!< Transmit data buffer */
/* UCB0TXBUF_SPI[UCTXBUF] Bits */
//#define UCTXBUF_OFS EUSCI_B_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */
//#define UCTXBUF_M EUSCI_B_TXBUF_TXBUF_MASK /*!< Transmit data buffer */
/* UCB0I2COA0[I2COA0] Bits */
#define I2COA0_OFS EUSCI_B_I2COA0_I2COA0_OFS /*!< I2COA0 Offset */
#define I2COA0_M EUSCI_B_I2COA0_I2COA0_MASK /*!< I2C own address */
/* UCB0I2COA0[UCOAEN] Bits */
#define UCOAEN_OFS EUSCI_B_I2COA0_OAEN_OFS /*!< UCOAEN Offset */
#define UCOAEN EUSCI_B_I2COA0_OAEN /*!< Own Address enable register */
/* UCB0I2COA0[UCGCEN] Bits */
#define UCGCEN_OFS EUSCI_B_I2COA0_GCEN_OFS /*!< UCGCEN Offset */
#define UCGCEN EUSCI_B_I2COA0_GCEN /*!< General call response enable */
/* UCB0I2COA1[I2COA1] Bits */
#define I2COA1_OFS EUSCI_B_I2COA1_I2COA1_OFS /*!< I2COA1 Offset */
#define I2COA1_M EUSCI_B_I2COA1_I2COA1_MASK /*!< I2C own address */
/* UCB0I2COA1[UCOAEN] Bits */
//#define UCOAEN_OFS EUSCI_B_I2COA1_OAEN_OFS /*!< UCOAEN Offset */
//#define UCOAEN EUSCI_B_I2COA1_OAEN /*!< Own Address enable register */
/* UCB0I2COA2[I2COA2] Bits */
#define I2COA2_OFS EUSCI_B_I2COA2_I2COA2_OFS /*!< I2COA2 Offset */
#define I2COA2_M EUSCI_B_I2COA2_I2COA2_MASK /*!< I2C own address */
/* UCB0I2COA2[UCOAEN] Bits */
//#define UCOAEN_OFS EUSCI_B_I2COA2_OAEN_OFS /*!< UCOAEN Offset */
//#define UCOAEN EUSCI_B_I2COA2_OAEN /*!< Own Address enable register */
/* UCB0I2COA3[I2COA3] Bits */
#define I2COA3_OFS EUSCI_B_I2COA3_I2COA3_OFS /*!< I2COA3 Offset */
#define I2COA3_M EUSCI_B_I2COA3_I2COA3_MASK /*!< I2C own address */
/* UCB0I2COA3[UCOAEN] Bits */
//#define UCOAEN_OFS EUSCI_B_I2COA3_OAEN_OFS /*!< UCOAEN Offset */
//#define UCOAEN EUSCI_B_I2COA3_OAEN /*!< Own Address enable register */
/* UCB0ADDRX[ADDRX] Bits */
#define ADDRX_OFS EUSCI_B_ADDRX_ADDRX_OFS /*!< ADDRX Offset */
#define ADDRX_M EUSCI_B_ADDRX_ADDRX_MASK /*!< Received Address Register */
/* UCB0ADDMASK[ADDMASK] Bits */
#define ADDMASK_OFS EUSCI_B_ADDMASK_ADDMASK_OFS /*!< ADDMASK Offset */
#define ADDMASK_M EUSCI_B_ADDMASK_ADDMASK_MASK
/* UCB0I2CSA[I2CSA] Bits */
#define I2CSA_OFS EUSCI_B_I2CSA_I2CSA_OFS /*!< I2CSA Offset */
#define I2CSA_M EUSCI_B_I2CSA_I2CSA_MASK /*!< I2C slave address */
/* UCB0IE[UCRXIE0] Bits */
#define UCRXIE0_OFS EUSCI_B_IE_RXIE0_OFS /*!< UCRXIE0 Offset */
#define UCRXIE0 EUSCI_B_IE_RXIE0 /*!< Receive interrupt enable 0 */
/* UCB0IE[UCTXIE0] Bits */
#define UCTXIE0_OFS EUSCI_B_IE_TXIE0_OFS /*!< UCTXIE0 Offset */
#define UCTXIE0 EUSCI_B_IE_TXIE0 /*!< Transmit interrupt enable 0 */
/* UCB0IE[UCSTTIE] Bits */
//#define UCSTTIE_OFS EUSCI_B_IE_STTIE_OFS /*!< UCSTTIE Offset */
//#define UCSTTIE EUSCI_B_IE_STTIE /*!< START condition interrupt enable */
/* UCB0IE[UCSTPIE] Bits */
#define UCSTPIE_OFS EUSCI_B_IE_STPIE_OFS /*!< UCSTPIE Offset */
#define UCSTPIE EUSCI_B_IE_STPIE /*!< STOP condition interrupt enable */
/* UCB0IE[UCALIE] Bits */
#define UCALIE_OFS EUSCI_B_IE_ALIE_OFS /*!< UCALIE Offset */
#define UCALIE EUSCI_B_IE_ALIE /*!< Arbitration lost interrupt enable */
/* UCB0IE[UCNACKIE] Bits */
#define UCNACKIE_OFS EUSCI_B_IE_NACKIE_OFS /*!< UCNACKIE Offset */
#define UCNACKIE EUSCI_B_IE_NACKIE /*!< Not-acknowledge interrupt enable */
/* UCB0IE[UCBCNTIE] Bits */
#define UCBCNTIE_OFS EUSCI_B_IE_BCNTIE_OFS /*!< UCBCNTIE Offset */
#define UCBCNTIE EUSCI_B_IE_BCNTIE /*!< Byte counter interrupt enable */
/* UCB0IE[UCCLTOIE] Bits */
#define UCCLTOIE_OFS EUSCI_B_IE_CLTOIE_OFS /*!< UCCLTOIE Offset */
#define UCCLTOIE EUSCI_B_IE_CLTOIE /*!< Clock low timeout interrupt enable */
/* UCB0IE[UCRXIE1] Bits */
#define UCRXIE1_OFS EUSCI_B_IE_RXIE1_OFS /*!< UCRXIE1 Offset */
#define UCRXIE1 EUSCI_B_IE_RXIE1 /*!< Receive interrupt enable 1 */
/* UCB0IE[UCTXIE1] Bits */
#define UCTXIE1_OFS EUSCI_B_IE_TXIE1_OFS /*!< UCTXIE1 Offset */
#define UCTXIE1 EUSCI_B_IE_TXIE1 /*!< Transmit interrupt enable 1 */
/* UCB0IE[UCRXIE2] Bits */
#define UCRXIE2_OFS EUSCI_B_IE_RXIE2_OFS /*!< UCRXIE2 Offset */
#define UCRXIE2 EUSCI_B_IE_RXIE2 /*!< Receive interrupt enable 2 */
/* UCB0IE[UCTXIE2] Bits */
#define UCTXIE2_OFS EUSCI_B_IE_TXIE2_OFS /*!< UCTXIE2 Offset */
#define UCTXIE2 EUSCI_B_IE_TXIE2 /*!< Transmit interrupt enable 2 */
/* UCB0IE[UCRXIE3] Bits */
#define UCRXIE3_OFS EUSCI_B_IE_RXIE3_OFS /*!< UCRXIE3 Offset */
#define UCRXIE3 EUSCI_B_IE_RXIE3 /*!< Receive interrupt enable 3 */
/* UCB0IE[UCTXIE3] Bits */
#define UCTXIE3_OFS EUSCI_B_IE_TXIE3_OFS /*!< UCTXIE3 Offset */
#define UCTXIE3 EUSCI_B_IE_TXIE3 /*!< Transmit interrupt enable 3 */
/* UCB0IE[UCBIT9IE] Bits */
#define UCBIT9IE_OFS EUSCI_B_IE_BIT9IE_OFS /*!< UCBIT9IE Offset */
#define UCBIT9IE EUSCI_B_IE_BIT9IE /*!< Bit position 9 interrupt enable */
/* UCB0IE_SPI[UCRXIE] Bits */
//#define UCRXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Offset */
//#define UCRXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */
/* UCB0IE_SPI[UCTXIE] Bits */
//#define UCTXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Offset */
//#define UCTXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */
/* UCB0IFG[UCRXIFG0] Bits */
#define UCRXIFG0_OFS EUSCI_B_IFG_RXIFG0_OFS /*!< UCRXIFG0 Offset */
#define UCRXIFG0 EUSCI_B_IFG_RXIFG0 /*!< eUSCI_B receive interrupt flag 0 */
/* UCB0IFG[UCTXIFG0] Bits */
#define UCTXIFG0_OFS EUSCI_B_IFG_TXIFG0_OFS /*!< UCTXIFG0 Offset */
#define UCTXIFG0 EUSCI_B_IFG_TXIFG0 /*!< eUSCI_B transmit interrupt flag 0 */
/* UCB0IFG[UCSTTIFG] Bits */
//#define UCSTTIFG_OFS EUSCI_B_IFG_STTIFG_OFS /*!< UCSTTIFG Offset */
//#define UCSTTIFG EUSCI_B_IFG_STTIFG /*!< START condition interrupt flag */
/* UCB0IFG[UCSTPIFG] Bits */
#define UCSTPIFG_OFS EUSCI_B_IFG_STPIFG_OFS /*!< UCSTPIFG Offset */
#define UCSTPIFG EUSCI_B_IFG_STPIFG /*!< STOP condition interrupt flag */
/* UCB0IFG[UCALIFG] Bits */
#define UCALIFG_OFS EUSCI_B_IFG_ALIFG_OFS /*!< UCALIFG Offset */
#define UCALIFG EUSCI_B_IFG_ALIFG /*!< Arbitration lost interrupt flag */
/* UCB0IFG[UCNACKIFG] Bits */
#define UCNACKIFG_OFS EUSCI_B_IFG_NACKIFG_OFS /*!< UCNACKIFG Offset */
#define UCNACKIFG EUSCI_B_IFG_NACKIFG /*!< Not-acknowledge received interrupt flag */
/* UCB0IFG[UCBCNTIFG] Bits */
#define UCBCNTIFG_OFS EUSCI_B_IFG_BCNTIFG_OFS /*!< UCBCNTIFG Offset */
#define UCBCNTIFG EUSCI_B_IFG_BCNTIFG /*!< Byte counter interrupt flag */
/* UCB0IFG[UCCLTOIFG] Bits */
#define UCCLTOIFG_OFS EUSCI_B_IFG_CLTOIFG_OFS /*!< UCCLTOIFG Offset */
#define UCCLTOIFG EUSCI_B_IFG_CLTOIFG /*!< Clock low timeout interrupt flag */
/* UCB0IFG[UCRXIFG1] Bits */
#define UCRXIFG1_OFS EUSCI_B_IFG_RXIFG1_OFS /*!< UCRXIFG1 Offset */
#define UCRXIFG1 EUSCI_B_IFG_RXIFG1 /*!< eUSCI_B receive interrupt flag 1 */
/* UCB0IFG[UCTXIFG1] Bits */
#define UCTXIFG1_OFS EUSCI_B_IFG_TXIFG1_OFS /*!< UCTXIFG1 Offset */
#define UCTXIFG1 EUSCI_B_IFG_TXIFG1 /*!< eUSCI_B transmit interrupt flag 1 */
/* UCB0IFG[UCRXIFG2] Bits */
#define UCRXIFG2_OFS EUSCI_B_IFG_RXIFG2_OFS /*!< UCRXIFG2 Offset */
#define UCRXIFG2 EUSCI_B_IFG_RXIFG2 /*!< eUSCI_B receive interrupt flag 2 */
/* UCB0IFG[UCTXIFG2] Bits */
#define UCTXIFG2_OFS EUSCI_B_IFG_TXIFG2_OFS /*!< UCTXIFG2 Offset */
#define UCTXIFG2 EUSCI_B_IFG_TXIFG2 /*!< eUSCI_B transmit interrupt flag 2 */
/* UCB0IFG[UCRXIFG3] Bits */
#define UCRXIFG3_OFS EUSCI_B_IFG_RXIFG3_OFS /*!< UCRXIFG3 Offset */
#define UCRXIFG3 EUSCI_B_IFG_RXIFG3 /*!< eUSCI_B receive interrupt flag 3 */
/* UCB0IFG[UCTXIFG3] Bits */
#define UCTXIFG3_OFS EUSCI_B_IFG_TXIFG3_OFS /*!< UCTXIFG3 Offset */
#define UCTXIFG3 EUSCI_B_IFG_TXIFG3 /*!< eUSCI_B transmit interrupt flag 3 */
/* UCB0IFG[UCBIT9IFG] Bits */
#define UCBIT9IFG_OFS EUSCI_B_IFG_BIT9IFG_OFS /*!< UCBIT9IFG Offset */
#define UCBIT9IFG EUSCI_B_IFG_BIT9IFG /*!< Bit position 9 interrupt flag */
/* UCB0IFG_SPI[UCRXIFG] Bits */
//#define UCRXIFG_OFS EUSCI_B_IFG_RXIFG_OFS /*!< UCRXIFG Offset */
//#define UCRXIFG EUSCI_B_IFG_RXIFG /*!< Receive interrupt flag */
/* UCB0IFG_SPI[UCTXIFG] Bits */
//#define UCTXIFG_OFS EUSCI_B_IFG_TXIFG_OFS /*!< UCTXIFG Offset */
//#define UCTXIFG EUSCI_B_IFG_TXIFG /*!< Transmit interrupt flag */
/******************************************************************************
* PMAP Bits (legacy section)
******************************************************************************/
/* PMAPCTL[PMAPLOCKED] Bits */
#define PMAPLOCKED_OFS PMAP_CTL_LOCKED_OFS /*!< PMAPLOCKED Offset */
#define PMAPLOCKED PMAP_CTL_LOCKED /*!< Port mapping lock bit */
/* PMAPCTL[PMAPRECFG] Bits */
#define PMAPRECFG_OFS PMAP_CTL_PRECFG_OFS /*!< PMAPRECFG Offset */
#define PMAPRECFG PMAP_CTL_PRECFG /*!< Port mapping reconfiguration control bit */
/* Pre-defined bitfield values */
/* PMAP_PMAPCTL[PMAPLOCKED] Bits */
#define PMAPLOCKED_OFS PMAP_CTL_LOCKED_OFS /*!< PMAPLOCKED Offset */
#define PMAPLOCKED PMAP_CTL_LOCKED /*!< Port mapping lock bit */
/* PMAP_PMAPCTL[PMAPRECFG] Bits */
#define PMAPRECFG_OFS PMAP_CTL_PRECFG_OFS /*!< PMAPRECFG Offset */
#define PMAPRECFG PMAP_CTL_PRECFG /*!< Port mapping reconfiguration control bit */
#define PM_NONE PMAP_NONE
#define PM_UCA0CLK PMAP_UCA0CLK
#define PM_UCA0RXD PMAP_UCA0RXD
#define PM_UCA0SOMI PMAP_UCA0SOMI
#define PM_UCA0TXD PMAP_UCA0TXD
#define PM_UCA0SIMO PMAP_UCA0SIMO
#define PM_UCB0CLK PMAP_UCB0CLK
#define PM_UCB0SDA PMAP_UCB0SDA
#define PM_UCB0SIMO PMAP_UCB0SIMO
#define PM_UCB0SCL PMAP_UCB0SCL
#define PM_UCB0SOMI PMAP_UCB0SOMI
#define PM_UCA1STE PMAP_UCA1STE
#define PM_UCA1CLK PMAP_UCA1CLK
#define PM_UCA1RXD PMAP_UCA1RXD
#define PM_UCA1SOMI PMAP_UCA1SOMI
#define PM_UCA1TXD PMAP_UCA1TXD
#define PM_UCA1SIMO PMAP_UCA1SIMO
#define PM_UCA2STE PMAP_UCA2STE
#define PM_UCA2CLK PMAP_UCA2CLK
#define PM_UCA2RXD PMAP_UCA2RXD
#define PM_UCA2SOMI PMAP_UCA2SOMI
#define PM_UCA2TXD PMAP_UCA2TXD
#define PM_UCA2SIMO PMAP_UCA2SIMO
#define PM_UCB2STE PMAP_UCB2STE
#define PM_UCB2CLK PMAP_UCB2CLK
#define PM_UCB2SDA PMAP_UCB2SDA
#define PM_UCB2SIMO PMAP_UCB2SIMO
#define PM_UCB2SCL PMAP_UCB2SCL
#define PM_UCB2SOMI PMAP_UCB2SOMI
#define PM_TA0CCR0A PMAP_TA0CCR0A
#define PM_TA0CCR1A PMAP_TA0CCR1A
#define PM_TA0CCR2A PMAP_TA0CCR2A
#define PM_TA0CCR3A PMAP_TA0CCR3A
#define PM_TA0CCR4A PMAP_TA0CCR4A
#define PM_TA1CCR1A PMAP_TA1CCR1A
#define PM_TA1CCR2A PMAP_TA1CCR2A
#define PM_TA1CCR3A PMAP_TA1CCR3A
#define PM_TA1CCR4A PMAP_TA1CCR4A
#define PM_TA0CLK PMAP_TA0CLK
#define PM_CE0OUT PMAP_CE0OUT
#define PM_TA1CLK PMAP_TA1CLK
#define PM_CE1OUT PMAP_CE1OUT
#define PM_DMAE0 PMAP_DMAE0
#define PM_SMCLK PMAP_SMCLK
#define PM_ANALOG PMAP_ANALOG
#define PMAPKEY PMAP_KEYID_VAL /*!< Port Mapping Key */
#define PMAPPWD PMAP_KEYID_VAL /*!< Legacy Definition: Mapping Key register */
#define PMAPPW PMAP_KEYID_VAL /*!< Legacy Definition: Port Mapping Password */
/******************************************************************************
* REF_A Bits (legacy section)
******************************************************************************/
/* REFCTL0[REFON] Bits */
#define REFON_OFS REF_A_CTL0_ON_OFS /*!< REFON Offset */
#define REFON REF_A_CTL0_ON /*!< Reference enable */
/* REFCTL0[REFOUT] Bits */
#define REFOUT_OFS REF_A_CTL0_OUT_OFS /*!< REFOUT Offset */
#define REFOUT REF_A_CTL0_OUT /*!< Reference output buffer */
/* REFCTL0[REFTCOFF] Bits */
#define REFTCOFF_OFS REF_A_CTL0_TCOFF_OFS /*!< REFTCOFF Offset */
#define REFTCOFF REF_A_CTL0_TCOFF /*!< Temperature sensor disabled */
/* REFCTL0[REFVSEL] Bits */
#define REFVSEL_OFS REF_A_CTL0_VSEL_OFS /*!< REFVSEL Offset */
#define REFVSEL_M REF_A_CTL0_VSEL_MASK /*!< Reference voltage level select */
#define REFVSEL0 REF_A_CTL0_VSEL0 /*!< REFVSEL Bit 0 */
#define REFVSEL1 REF_A_CTL0_VSEL1 /*!< REFVSEL Bit 1 */
#define REFVSEL_0 REF_A_CTL0_VSEL_0 /*!< 1.2 V available when reference requested or REFON = 1 */
#define REFVSEL_1 REF_A_CTL0_VSEL_1 /*!< 1.45 V available when reference requested or REFON = 1 */
#define REFVSEL_3 REF_A_CTL0_VSEL_3 /*!< 2.5 V available when reference requested or REFON = 1 */
/* REFCTL0[REFGENOT] Bits */
#define REFGENOT_OFS REF_A_CTL0_GENOT_OFS /*!< REFGENOT Offset */
#define REFGENOT REF_A_CTL0_GENOT /*!< Reference generator one-time trigger */
/* REFCTL0[REFBGOT] Bits */
#define REFBGOT_OFS REF_A_CTL0_BGOT_OFS /*!< REFBGOT Offset */
#define REFBGOT REF_A_CTL0_BGOT /*!< Bandgap and bandgap buffer one-time trigger */
/* REFCTL0[REFGENACT] Bits */
#define REFGENACT_OFS REF_A_CTL0_GENACT_OFS /*!< REFGENACT Offset */
#define REFGENACT REF_A_CTL0_GENACT /*!< Reference generator active */
/* REFCTL0[REFBGACT] Bits */
#define REFBGACT_OFS REF_A_CTL0_BGACT_OFS /*!< REFBGACT Offset */
#define REFBGACT REF_A_CTL0_BGACT /*!< Reference bandgap active */
/* REFCTL0[REFGENBUSY] Bits */
#define REFGENBUSY_OFS REF_A_CTL0_GENBUSY_OFS /*!< REFGENBUSY Offset */
#define REFGENBUSY REF_A_CTL0_GENBUSY /*!< Reference generator busy */
/* REFCTL0[BGMODE] Bits */
#define BGMODE_OFS REF_A_CTL0_BGMODE_OFS /*!< BGMODE Offset */
#define BGMODE REF_A_CTL0_BGMODE /*!< Bandgap mode */
/* REFCTL0[REFGENRDY] Bits */
#define REFGENRDY_OFS REF_A_CTL0_GENRDY_OFS /*!< REFGENRDY Offset */
#define REFGENRDY REF_A_CTL0_GENRDY /*!< Variable reference voltage ready status */
/* REFCTL0[REFBGRDY] Bits */
#define REFBGRDY_OFS REF_A_CTL0_BGRDY_OFS /*!< REFBGRDY Offset */
#define REFBGRDY REF_A_CTL0_BGRDY /*!< Buffered bandgap voltage ready status */
/******************************************************************************
* RTC_C Bits (legacy section)
******************************************************************************/
/* RTCCTL0[RTCRDYIFG] Bits */
#define RTCRDYIFG_OFS RTC_C_CTL0_RDYIFG_OFS /*!< RTCRDYIFG Offset */
#define RTCRDYIFG RTC_C_CTL0_RDYIFG /*!< Real-time clock ready interrupt flag */
/* RTCCTL0[RTCAIFG] Bits */
#define RTCAIFG_OFS RTC_C_CTL0_AIFG_OFS /*!< RTCAIFG Offset */
#define RTCAIFG RTC_C_CTL0_AIFG /*!< Real-time clock alarm interrupt flag */
/* RTCCTL0[RTCTEVIFG] Bits */
#define RTCTEVIFG_OFS RTC_C_CTL0_TEVIFG_OFS /*!< RTCTEVIFG Offset */
#define RTCTEVIFG RTC_C_CTL0_TEVIFG /*!< Real-time clock time event interrupt flag */
/* RTCCTL0[RTCOFIFG] Bits */
#define RTCOFIFG_OFS RTC_C_CTL0_OFIFG_OFS /*!< RTCOFIFG Offset */
#define RTCOFIFG RTC_C_CTL0_OFIFG /*!< 32-kHz crystal oscillator fault interrupt flag */
/* RTCCTL0[RTCRDYIE] Bits */
#define RTCRDYIE_OFS RTC_C_CTL0_RDYIE_OFS /*!< RTCRDYIE Offset */
#define RTCRDYIE RTC_C_CTL0_RDYIE /*!< Real-time clock ready interrupt enable */
/* RTCCTL0[RTCAIE] Bits */
#define RTCAIE_OFS RTC_C_CTL0_AIE_OFS /*!< RTCAIE Offset */
#define RTCAIE RTC_C_CTL0_AIE /*!< Real-time clock alarm interrupt enable */
/* RTCCTL0[RTCTEVIE] Bits */
#define RTCTEVIE_OFS RTC_C_CTL0_TEVIE_OFS /*!< RTCTEVIE Offset */
#define RTCTEVIE RTC_C_CTL0_TEVIE /*!< Real-time clock time event interrupt enable */
/* RTCCTL0[RTCOFIE] Bits */
#define RTCOFIE_OFS RTC_C_CTL0_OFIE_OFS /*!< RTCOFIE Offset */
#define RTCOFIE RTC_C_CTL0_OFIE /*!< 32-kHz crystal oscillator fault interrupt enable */
/* RTCCTL0[RTCKEY] Bits */
#define RTCKEY_OFS RTC_C_CTL0_KEY_OFS /*!< RTCKEY Offset */
#define RTCKEY_M RTC_C_CTL0_KEY_MASK /*!< Real-time clock key */
/* RTCCTL13[RTCTEV] Bits */
#define RTCTEV_OFS RTC_C_CTL13_TEV_OFS /*!< RTCTEV Offset */
#define RTCTEV_M RTC_C_CTL13_TEV_MASK /*!< Real-time clock time event */
#define RTCTEV0 RTC_C_CTL13_TEV0 /*!< RTCTEV Bit 0 */
#define RTCTEV1 RTC_C_CTL13_TEV1 /*!< RTCTEV Bit 1 */
#define RTCTEV_0 RTC_C_CTL13_TEV_0 /*!< Minute changed */
#define RTCTEV_1 RTC_C_CTL13_TEV_1 /*!< Hour changed */
#define RTCTEV_2 RTC_C_CTL13_TEV_2 /*!< Every day at midnight (00:00) */
#define RTCTEV_3 RTC_C_CTL13_TEV_3 /*!< Every day at noon (12:00) */
/* RTCCTL13[RTCSSEL] Bits */
#define RTCSSEL_OFS RTC_C_CTL13_SSEL_OFS /*!< RTCSSEL Offset */
#define RTCSSEL_M RTC_C_CTL13_SSEL_MASK /*!< Real-time clock source select */
#define RTCSSEL0 RTC_C_CTL13_SSEL0 /*!< RTCSSEL Bit 0 */
#define RTCSSEL1 RTC_C_CTL13_SSEL1 /*!< RTCSSEL Bit 1 */
#define RTCSSEL_0 RTC_C_CTL13_SSEL_0 /*!< BCLK */
#define RTCSSEL__BCLK RTC_C_CTL13_SSEL__BCLK /*!< BCLK */
/* RTCCTL13[RTCRDY] Bits */
#define RTCRDY_OFS RTC_C_CTL13_RDY_OFS /*!< RTCRDY Offset */
#define RTCRDY RTC_C_CTL13_RDY /*!< Real-time clock ready */
/* RTCCTL13[RTCMODE] Bits */
#define RTCMODE_OFS RTC_C_CTL13_MODE_OFS /*!< RTCMODE Offset */
#define RTCMODE RTC_C_CTL13_MODE
/* RTCCTL13[RTCHOLD] Bits */
#define RTCHOLD_OFS RTC_C_CTL13_HOLD_OFS /*!< RTCHOLD Offset */
#define RTCHOLD RTC_C_CTL13_HOLD /*!< Real-time clock hold */
/* RTCCTL13[RTCBCD] Bits */
#define RTCBCD_OFS RTC_C_CTL13_BCD_OFS /*!< RTCBCD Offset */
#define RTCBCD RTC_C_CTL13_BCD /*!< Real-time clock BCD select */
/* RTCCTL13[RTCCALF] Bits */
#define RTCCALF_OFS RTC_C_CTL13_CALF_OFS /*!< RTCCALF Offset */
#define RTCCALF_M RTC_C_CTL13_CALF_MASK /*!< Real-time clock calibration frequency */
#define RTCCALF0 RTC_C_CTL13_CALF0 /*!< RTCCALF Bit 0 */
#define RTCCALF1 RTC_C_CTL13_CALF1 /*!< RTCCALF Bit 1 */
#define RTCCALF_0 RTC_C_CTL13_CALF_0 /*!< No frequency output to RTCCLK pin */
#define RTCCALF_1 RTC_C_CTL13_CALF_1 /*!< 512 Hz */
#define RTCCALF_2 RTC_C_CTL13_CALF_2 /*!< 256 Hz */
#define RTCCALF_3 RTC_C_CTL13_CALF_3 /*!< 1 Hz */
#define RTCCALF__NONE RTC_C_CTL13_CALF__NONE /*!< No frequency output to RTCCLK pin */
#define RTCCALF__512 RTC_C_CTL13_CALF__512 /*!< 512 Hz */
#define RTCCALF__256 RTC_C_CTL13_CALF__256 /*!< 256 Hz */
#define RTCCALF__1 RTC_C_CTL13_CALF__1 /*!< 1 Hz */
/* RTCOCAL[RTCOCAL] Bits */
#define RTCOCAL_OFS RTC_C_OCAL_OCAL_OFS /*!< RTCOCAL Offset */
#define RTCOCAL_M RTC_C_OCAL_OCAL_MASK /*!< Real-time clock offset error calibration */
/* RTCOCAL[RTCOCALS] Bits */
#define RTCOCALS_OFS RTC_C_OCAL_OCALS_OFS /*!< RTCOCALS Offset */
#define RTCOCALS RTC_C_OCAL_OCALS /*!< Real-time clock offset error calibration sign */
/* RTCTCMP[RTCTCMP] Bits */
#define RTCTCMP_OFS RTC_C_TCMP_TCMPX_OFS /*!< RTCTCMP Offset */
#define RTCTCMP_M RTC_C_TCMP_TCMPX_MASK /*!< Real-time clock temperature compensation */
/* RTCTCMP[RTCTCOK] Bits */
#define RTCTCOK_OFS RTC_C_TCMP_TCOK_OFS /*!< RTCTCOK Offset */
#define RTCTCOK RTC_C_TCMP_TCOK /*!< Real-time clock temperature compensation write OK */
/* RTCTCMP[RTCTCRDY] Bits */
#define RTCTCRDY_OFS RTC_C_TCMP_TCRDY_OFS /*!< RTCTCRDY Offset */
#define RTCTCRDY RTC_C_TCMP_TCRDY /*!< Real-time clock temperature compensation ready */
/* RTCTCMP[RTCTCMPS] Bits */
#define RTCTCMPS_OFS RTC_C_TCMP_TCMPS_OFS /*!< RTCTCMPS Offset */
#define RTCTCMPS RTC_C_TCMP_TCMPS /*!< Real-time clock temperature compensation sign */
/* RTCPS0CTL[RT0PSIFG] Bits */
#define RT0PSIFG_OFS RTC_C_PS0CTL_RT0PSIFG_OFS /*!< RT0PSIFG Offset */
#define RT0PSIFG RTC_C_PS0CTL_RT0PSIFG /*!< Prescale timer 0 interrupt flag */
/* RTCPS0CTL[RT0PSIE] Bits */
#define RT0PSIE_OFS RTC_C_PS0CTL_RT0PSIE_OFS /*!< RT0PSIE Offset */
#define RT0PSIE RTC_C_PS0CTL_RT0PSIE /*!< Prescale timer 0 interrupt enable */
/* RTCPS0CTL[RT0IP] Bits */
#define RT0IP_OFS RTC_C_PS0CTL_RT0IP_OFS /*!< RT0IP Offset */
#define RT0IP_M RTC_C_PS0CTL_RT0IP_MASK /*!< Prescale timer 0 interrupt interval */
#define RT0IP0 RTC_C_PS0CTL_RT0IP0 /*!< RT0IP Bit 0 */
#define RT0IP1 RTC_C_PS0CTL_RT0IP1 /*!< RT0IP Bit 1 */
#define RT0IP2 RTC_C_PS0CTL_RT0IP2 /*!< RT0IP Bit 2 */
#define RT0IP_0 RTC_C_PS0CTL_RT0IP_0 /*!< Divide by 2 */
#define RT0IP_1 RTC_C_PS0CTL_RT0IP_1 /*!< Divide by 4 */
#define RT0IP_2 RTC_C_PS0CTL_RT0IP_2 /*!< Divide by 8 */
#define RT0IP_3 RTC_C_PS0CTL_RT0IP_3 /*!< Divide by 16 */
#define RT0IP_4 RTC_C_PS0CTL_RT0IP_4 /*!< Divide by 32 */
#define RT0IP_5 RTC_C_PS0CTL_RT0IP_5 /*!< Divide by 64 */
#define RT0IP_6 RTC_C_PS0CTL_RT0IP_6 /*!< Divide by 128 */
#define RT0IP_7 RTC_C_PS0CTL_RT0IP_7 /*!< Divide by 256 */
#define RT0IP__2 RTC_C_PS0CTL_RT0IP__2 /*!< Divide by 2 */
#define RT0IP__4 RTC_C_PS0CTL_RT0IP__4 /*!< Divide by 4 */
#define RT0IP__8 RTC_C_PS0CTL_RT0IP__8 /*!< Divide by 8 */
#define RT0IP__16 RTC_C_PS0CTL_RT0IP__16 /*!< Divide by 16 */
#define RT0IP__32 RTC_C_PS0CTL_RT0IP__32 /*!< Divide by 32 */
#define RT0IP__64 RTC_C_PS0CTL_RT0IP__64 /*!< Divide by 64 */
#define RT0IP__128 RTC_C_PS0CTL_RT0IP__128 /*!< Divide by 128 */
#define RT0IP__256 RTC_C_PS0CTL_RT0IP__256 /*!< Divide by 256 */
/* RTCPS1CTL[RT1PSIFG] Bits */
#define RT1PSIFG_OFS RTC_C_PS1CTL_RT1PSIFG_OFS /*!< RT1PSIFG Offset */
#define RT1PSIFG RTC_C_PS1CTL_RT1PSIFG /*!< Prescale timer 1 interrupt flag */
/* RTCPS1CTL[RT1PSIE] Bits */
#define RT1PSIE_OFS RTC_C_PS1CTL_RT1PSIE_OFS /*!< RT1PSIE Offset */
#define RT1PSIE RTC_C_PS1CTL_RT1PSIE /*!< Prescale timer 1 interrupt enable */
/* RTCPS1CTL[RT1IP] Bits */
#define RT1IP_OFS RTC_C_PS1CTL_RT1IP_OFS /*!< RT1IP Offset */
#define RT1IP_M RTC_C_PS1CTL_RT1IP_MASK /*!< Prescale timer 1 interrupt interval */
#define RT1IP0 RTC_C_PS1CTL_RT1IP0 /*!< RT1IP Bit 0 */
#define RT1IP1 RTC_C_PS1CTL_RT1IP1 /*!< RT1IP Bit 1 */
#define RT1IP2 RTC_C_PS1CTL_RT1IP2 /*!< RT1IP Bit 2 */
#define RT1IP_0 RTC_C_PS1CTL_RT1IP_0 /*!< Divide by 2 */
#define RT1IP_1 RTC_C_PS1CTL_RT1IP_1 /*!< Divide by 4 */
#define RT1IP_2 RTC_C_PS1CTL_RT1IP_2 /*!< Divide by 8 */
#define RT1IP_3 RTC_C_PS1CTL_RT1IP_3 /*!< Divide by 16 */
#define RT1IP_4 RTC_C_PS1CTL_RT1IP_4 /*!< Divide by 32 */
#define RT1IP_5 RTC_C_PS1CTL_RT1IP_5 /*!< Divide by 64 */
#define RT1IP_6 RTC_C_PS1CTL_RT1IP_6 /*!< Divide by 128 */
#define RT1IP_7 RTC_C_PS1CTL_RT1IP_7 /*!< Divide by 256 */
#define RT1IP__2 RTC_C_PS1CTL_RT1IP__2 /*!< Divide by 2 */
#define RT1IP__4 RTC_C_PS1CTL_RT1IP__4 /*!< Divide by 4 */
#define RT1IP__8 RTC_C_PS1CTL_RT1IP__8 /*!< Divide by 8 */
#define RT1IP__16 RTC_C_PS1CTL_RT1IP__16 /*!< Divide by 16 */
#define RT1IP__32 RTC_C_PS1CTL_RT1IP__32 /*!< Divide by 32 */
#define RT1IP__64 RTC_C_PS1CTL_RT1IP__64 /*!< Divide by 64 */
#define RT1IP__128 RTC_C_PS1CTL_RT1IP__128 /*!< Divide by 128 */
#define RT1IP__256 RTC_C_PS1CTL_RT1IP__256 /*!< Divide by 256 */
/* RTCPS[RT0PS] Bits */
#define RT0PS_OFS RTC_C_PS_RT0PS_OFS /*!< RT0PS Offset */
#define RT0PS_M RTC_C_PS_RT0PS_MASK /*!< Prescale timer 0 counter value */
/* RTCPS[RT1PS] Bits */
#define RT1PS_OFS RTC_C_PS_RT1PS_OFS /*!< RT1PS Offset */
#define RT1PS_M RTC_C_PS_RT1PS_MASK /*!< Prescale timer 1 counter value */
/* RTCTIM0[SECONDS] Bits */
#define SECONDS_OFS RTC_C_TIM0_SEC_OFS /*!< Seconds Offset */
#define SECONDS_M RTC_C_TIM0_SEC_MASK /*!< Seconds (0 to 59) */
/* RTCTIM0[MINUTES] Bits */
#define MINUTES_OFS RTC_C_TIM0_MIN_OFS /*!< Minutes Offset */
#define MINUTES_M RTC_C_TIM0_MIN_MASK /*!< Minutes (0 to 59) */
/* RTCTIM0_BCD[SECONDSLOWDIGIT] Bits */
#define SECONDSLOWDIGIT_OFS RTC_C_TIM0_SEC_LD_OFS /*!< SecondsLowDigit Offset */
#define SECONDSLOWDIGIT_M RTC_C_TIM0_SEC_LD_MASK /*!< Seconds ? low digit (0 to 9) */
/* RTCTIM0_BCD[SECONDSHIGHDIGIT] Bits */
#define SECONDSHIGHDIGIT_OFS RTC_C_TIM0_SEC_HD_OFS /*!< SecondsHighDigit Offset */
#define SECONDSHIGHDIGIT_M RTC_C_TIM0_SEC_HD_MASK /*!< Seconds ? high digit (0 to 5) */
/* RTCTIM0_BCD[MINUTESLOWDIGIT] Bits */
#define MINUTESLOWDIGIT_OFS RTC_C_TIM0_MIN_LD_OFS /*!< MinutesLowDigit Offset */
#define MINUTESLOWDIGIT_M RTC_C_TIM0_MIN_LD_MASK /*!< Minutes ? low digit (0 to 9) */
/* RTCTIM0_BCD[MINUTESHIGHDIGIT] Bits */
#define MINUTESHIGHDIGIT_OFS RTC_C_TIM0_MIN_HD_OFS /*!< MinutesHighDigit Offset */
#define MINUTESHIGHDIGIT_M RTC_C_TIM0_MIN_HD_MASK /*!< Minutes ? high digit (0 to 5) */
/* RTCTIM1[HOURS] Bits */
#define HOURS_OFS RTC_C_TIM1_HOUR_OFS /*!< Hours Offset */
#define HOURS_M RTC_C_TIM1_HOUR_MASK /*!< Hours (0 to 23) */
/* RTCTIM1[DAYOFWEEK] Bits */
#define DAYOFWEEK_OFS RTC_C_TIM1_DOW_OFS /*!< DayofWeek Offset */
#define DAYOFWEEK_M RTC_C_TIM1_DOW_MASK /*!< Day of week (0 to 6) */
/* RTCTIM1_BCD[HOURSLOWDIGIT] Bits */
#define HOURSLOWDIGIT_OFS RTC_C_TIM1_HOUR_LD_OFS /*!< HoursLowDigit Offset */
#define HOURSLOWDIGIT_M RTC_C_TIM1_HOUR_LD_MASK /*!< Hours ? low digit (0 to 9) */
/* RTCTIM1_BCD[HOURSHIGHDIGIT] Bits */
#define HOURSHIGHDIGIT_OFS RTC_C_TIM1_HOUR_HD_OFS /*!< HoursHighDigit Offset */
#define HOURSHIGHDIGIT_M RTC_C_TIM1_HOUR_HD_MASK /*!< Hours ? high digit (0 to 2) */
/* RTCTIM1_BCD[DAYOFWEEK] Bits */
//#define DAYOFWEEK_OFS RTC_C_TIM1_DOW_OFS /*!< DayofWeek Offset */
//#define DAYOFWEEK_M RTC_C_TIM1_DOW_MASK /*!< Day of week (0 to 6) */
/* RTCDATE[DAY] Bits */
#define DAY_OFS RTC_C_DATE_DAY_OFS /*!< Day Offset */
#define DAY_M RTC_C_DATE_DAY_MASK /*!< Day of month (1 to 28, 29, 30, 31) */
/* RTCDATE[MONTH] Bits */
#define MONTH_OFS RTC_C_DATE_MON_OFS /*!< Month Offset */
#define MONTH_M RTC_C_DATE_MON_MASK /*!< Month (1 to 12) */
/* RTCDATE_BCD[DAYLOWDIGIT] Bits */
#define DAYLOWDIGIT_OFS RTC_C_DATE_DAY_LD_OFS /*!< DayLowDigit Offset */
#define DAYLOWDIGIT_M RTC_C_DATE_DAY_LD_MASK /*!< Day of month ? low digit (0 to 9) */
/* RTCDATE_BCD[DAYHIGHDIGIT] Bits */
#define DAYHIGHDIGIT_OFS RTC_C_DATE_DAY_HD_OFS /*!< DayHighDigit Offset */
#define DAYHIGHDIGIT_M RTC_C_DATE_DAY_HD_MASK /*!< Day of month ? high digit (0 to 3) */
/* RTCDATE_BCD[MONTHLOWDIGIT] Bits */
#define MONTHLOWDIGIT_OFS RTC_C_DATE_MON_LD_OFS /*!< MonthLowDigit Offset */
#define MONTHLOWDIGIT_M RTC_C_DATE_MON_LD_MASK /*!< Month ? low digit (0 to 9) */
/* RTCDATE_BCD[MONTHHIGHDIGIT] Bits */
#define MONTHHIGHDIGIT_OFS RTC_C_DATE_MON_HD_OFS /*!< MonthHighDigit Offset */
#define MONTHHIGHDIGIT RTC_C_DATE_MON_HD /*!< Month ? high digit (0 or 1) */
/* RTCYEAR[YEARLOWBYTE] Bits */
#define YEARLOWBYTE_OFS RTC_C_YEAR_YEAR_LB_OFS /*!< YearLowByte Offset */
#define YEARLOWBYTE_M RTC_C_YEAR_YEAR_LB_MASK /*!< Year ? low byte. Valid values for Year are 0 to 4095. */
/* RTCYEAR[YEARHIGHBYTE] Bits */
#define YEARHIGHBYTE_OFS RTC_C_YEAR_YEAR_HB_OFS /*!< YearHighByte Offset */
#define YEARHIGHBYTE_M RTC_C_YEAR_YEAR_HB_MASK /*!< Year ? high byte. Valid values for Year are 0 to 4095. */
/* RTCYEAR_BCD[YEAR] Bits */
#define YEAR_OFS RTC_C_YEAR_YEAR_OFS /*!< Year Offset */
#define YEAR_M RTC_C_YEAR_YEAR_MASK /*!< Year ? lowest digit (0 to 9) */
/* RTCYEAR_BCD[DECADE] Bits */
#define DECADE_OFS RTC_C_YEAR_DEC_OFS /*!< Decade Offset */
#define DECADE_M RTC_C_YEAR_DEC_MASK /*!< Decade (0 to 9) */
/* RTCYEAR_BCD[CENTURYLOWDIGIT] Bits */
#define CENTURYLOWDIGIT_OFS RTC_C_YEAR_CENT_LD_OFS /*!< CenturyLowDigit Offset */
#define CENTURYLOWDIGIT_M RTC_C_YEAR_CENT_LD_MASK /*!< Century ? low digit (0 to 9) */
/* RTCYEAR_BCD[CENTURYHIGHDIGIT] Bits */
#define CENTURYHIGHDIGIT_OFS RTC_C_YEAR_CENT_HD_OFS /*!< CenturyHighDigit Offset */
#define CENTURYHIGHDIGIT_M RTC_C_YEAR_CENT_HD_MASK /*!< Century ? high digit (0 to 4) */
/* RTCAMINHR[MINUTES] Bits */
//#define MINUTES_OFS RTC_C_AMINHR_MIN_OFS /*!< Minutes Offset */
//#define MINUTES_M RTC_C_AMINHR_MIN_MASK /*!< Minutes (0 to 59) */
/* RTCAMINHR[MINAE] Bits */
#define MINAE_OFS RTC_C_AMINHR_MINAE_OFS /*!< MINAE Offset */
#define MINAE RTC_C_AMINHR_MINAE /*!< Alarm enable */
/* RTCAMINHR[HOURS] Bits */
//#define HOURS_OFS RTC_C_AMINHR_HOUR_OFS /*!< Hours Offset */
//#define HOURS_M RTC_C_AMINHR_HOUR_MASK /*!< Hours (0 to 23) */
/* RTCAMINHR[HOURAE] Bits */
#define HOURAE_OFS RTC_C_AMINHR_HOURAE_OFS /*!< HOURAE Offset */
#define HOURAE RTC_C_AMINHR_HOURAE /*!< Alarm enable */
/* RTCAMINHR_BCD[MINUTESLOWDIGIT] Bits */
//#define MINUTESLOWDIGIT_OFS RTC_C_AMINHR_MIN_LD_OFS /*!< MinutesLowDigit Offset */
//#define MINUTESLOWDIGIT_M RTC_C_AMINHR_MIN_LD_MASK /*!< Minutes ? low digit (0 to 9) */
/* RTCAMINHR_BCD[MINUTESHIGHDIGIT] Bits */
//#define MINUTESHIGHDIGIT_OFS RTC_C_AMINHR_MIN_HD_OFS /*!< MinutesHighDigit Offset */
//#define MINUTESHIGHDIGIT_M RTC_C_AMINHR_MIN_HD_MASK /*!< Minutes ? high digit (0 to 5) */
/* RTCAMINHR_BCD[MINAE] Bits */
//#define MINAE_OFS RTC_C_AMINHR__OFS /*!< MINAE Offset */
//#define MINAE RTC_C_AMINHR_ /*!< Alarm enable */
/* RTCAMINHR_BCD[HOURSLOWDIGIT] Bits */
//#define HOURSLOWDIGIT_OFS RTC_C_AMINHR_HOUR_LD_OFS /*!< HoursLowDigit Offset */
//#define HOURSLOWDIGIT_M RTC_C_AMINHR_HOUR_LD_MASK /*!< Hours ? low digit (0 to 9) */
/* RTCAMINHR_BCD[HOURSHIGHDIGIT] Bits */
//#define HOURSHIGHDIGIT_OFS RTC_C_AMINHR_HOUR_HD_OFS /*!< HoursHighDigit Offset */
//#define HOURSHIGHDIGIT_M RTC_C_AMINHR_HOUR_HD_MASK /*!< Hours ? high digit (0 to 2) */
/* RTCAMINHR_BCD[HOURAE] Bits */
//#define HOURAE_OFS RTC_C_AMINHR_HOURAE_OFS /*!< HOURAE Offset */
//#define HOURAE RTC_C_AMINHR_HOURAE /*!< Alarm enable */
/* RTCADOWDAY[DAYOFWEEK] Bits */
//#define DAYOFWEEK_OFS RTC_C_ADOWDAY_DOW_OFS /*!< DayofWeek Offset */
//#define DAYOFWEEK_M RTC_C_ADOWDAY_DOW_MASK /*!< Day of week (0 to 6) */
/* RTCADOWDAY[DOWAE] Bits */
#define DOWAE_OFS RTC_C_ADOWDAY_DOWAE_OFS /*!< DOWAE Offset */
#define DOWAE RTC_C_ADOWDAY_DOWAE /*!< Alarm enable */
/* RTCADOWDAY[DAYOFMONTH] Bits */
#define DAYOFMONTH_OFS RTC_C_ADOWDAY_DAY_OFS /*!< DayofMonth Offset */
#define DAYOFMONTH_M RTC_C_ADOWDAY_DAY_MASK /*!< Day of month (1 to 28, 29, 30, 31) */
/* RTCADOWDAY[DAYAE] Bits */
#define DAYAE_OFS RTC_C_ADOWDAY_DAYAE_OFS /*!< DAYAE Offset */
#define DAYAE RTC_C_ADOWDAY_DAYAE /*!< Alarm enable */
/* RTCADOWDAY_BCD[DAYOFWEEK] Bits */
//#define DAYOFWEEK_OFS RTC_C_ADOWDAY_DOW_OFS /*!< DayofWeek Offset */
//#define DAYOFWEEK_M RTC_C_ADOWDAY_DOW_MASK /*!< Day of week (0 to 6) */
/* RTCADOWDAY_BCD[DOWAE] Bits */
//#define DOWAE_OFS RTC_C_ADOWDAY_DOWAE_OFS /*!< DOWAE Offset */
//#define DOWAE RTC_C_ADOWDAY_DOWAE /*!< Alarm enable */
/* RTCADOWDAY_BCD[DAYLOWDIGIT] Bits */
//#define DAYLOWDIGIT_OFS RTC_C_ADOWDAY_DAY_LD_OFS /*!< DayLowDigit Offset */
//#define DAYLOWDIGIT_M RTC_C_ADOWDAY_DAY_LD_MASK /*!< Day of month ? low digit (0 to 9) */
/* RTCADOWDAY_BCD[DAYHIGHDIGIT] Bits */
//#define DAYHIGHDIGIT_OFS RTC_C_ADOWDAY_DAY_HD_OFS /*!< DayHighDigit Offset */
//#define DAYHIGHDIGIT_M RTC_C_ADOWDAY_DAY_HD_MASK /*!< Day of month ? high digit (0 to 3) */
/* RTCADOWDAY_BCD[DAYAE] Bits */
//#define DAYAE_OFS RTC_C_ADOWDAY_DAYAE_OFS /*!< DAYAE Offset */
//#define DAYAE RTC_C_ADOWDAY_DAYAE /*!< Alarm enable */
/* Pre-defined bitfield values */
#define RTCKEY RTC_C_KEY /*!< RTC_C Key Value for RTC_C write access */
#define RTCKEY_H RTC_C_KEY_H /*!< RTC_C Key Value for RTC_C write access */
#define RTCKEY_VAL RTC_C_KEY_VAL /*!< RTC_C Key Value for RTC_C write access */
/******************************************************************************
* Timer_A Bits (legacy section)
******************************************************************************/
/* TA0CTL[TAIFG] Bits */
#define TAIFG_OFS TIMER_A_CTL_IFG_OFS /*!< TAIFG Offset */
#define TAIFG TIMER_A_CTL_IFG /*!< TimerA interrupt flag */
/* TA0CTL[TAIE] Bits */
#define TAIE_OFS TIMER_A_CTL_IE_OFS /*!< TAIE Offset */
#define TAIE TIMER_A_CTL_IE /*!< TimerA interrupt enable */
/* TA0CTL[TACLR] Bits */
#define TACLR_OFS TIMER_A_CTL_CLR_OFS /*!< TACLR Offset */
#define TACLR TIMER_A_CTL_CLR /*!< TimerA clear */
/* TA0CTL[MC] Bits */
#define MC_OFS TIMER_A_CTL_MC_OFS /*!< MC Offset */
#define MC_M TIMER_A_CTL_MC_MASK /*!< Mode control */
#define MC0 TIMER_A_CTL_MC0 /*!< MC Bit 0 */
#define MC1 TIMER_A_CTL_MC1 /*!< MC Bit 1 */
#define MC_0 TIMER_A_CTL_MC_0 /*!< Stop mode: Timer is halted */
#define MC_1 TIMER_A_CTL_MC_1 /*!< Up mode: Timer counts up to TAxCCR0 */
#define MC_2 TIMER_A_CTL_MC_2 /*!< Continuous mode: Timer counts up to 0FFFFh */
#define MC_3 TIMER_A_CTL_MC_3 /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
#define MC__STOP TIMER_A_CTL_MC__STOP /*!< Stop mode: Timer is halted */
#define MC__UP TIMER_A_CTL_MC__UP /*!< Up mode: Timer counts up to TAxCCR0 */
#define MC__CONTINUOUS TIMER_A_CTL_MC__CONTINUOUS /*!< Continuous mode: Timer counts up to 0FFFFh */
#define MC__UPDOWN TIMER_A_CTL_MC__UPDOWN /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
/* TA0CTL[ID] Bits */
#define ID_OFS TIMER_A_CTL_ID_OFS /*!< ID Offset */
#define ID_M TIMER_A_CTL_ID_MASK /*!< Input divider */
#define ID0 TIMER_A_CTL_ID0 /*!< ID Bit 0 */
#define ID1 TIMER_A_CTL_ID1 /*!< ID Bit 1 */
#define ID_0 TIMER_A_CTL_ID_0 /*!< /1 */
#define ID_1 TIMER_A_CTL_ID_1 /*!< /2 */
#define ID_2 TIMER_A_CTL_ID_2 /*!< /4 */
#define ID_3 TIMER_A_CTL_ID_3 /*!< /8 */
#define ID__1 TIMER_A_CTL_ID__1 /*!< /1 */
#define ID__2 TIMER_A_CTL_ID__2 /*!< /2 */
#define ID__4 TIMER_A_CTL_ID__4 /*!< /4 */
#define ID__8 TIMER_A_CTL_ID__8 /*!< /8 */
/* TA0CTL[TASSEL] Bits */
#define TASSEL_OFS TIMER_A_CTL_SSEL_OFS /*!< TASSEL Offset */
#define TASSEL_M TIMER_A_CTL_SSEL_MASK /*!< TimerA clock source select */
#define TASSEL0 TIMER_A_CTL_SSEL0 /*!< TASSEL Bit 0 */
#define TASSEL1 TIMER_A_CTL_SSEL1 /*!< TASSEL Bit 1 */
#define TASSEL_0 TIMER_A_CTL_TASSEL_0 /*!< TAxCLK */
#define TASSEL_1 TIMER_A_CTL_TASSEL_1 /*!< ACLK */
#define TASSEL_2 TIMER_A_CTL_TASSEL_2 /*!< SMCLK */
#define TASSEL_3 TIMER_A_CTL_TASSEL_3 /*!< INCLK */
#define TASSEL__TACLK TIMER_A_CTL_SSEL__TACLK /*!< TAxCLK */
#define TASSEL__ACLK TIMER_A_CTL_SSEL__ACLK /*!< ACLK */
#define TASSEL__SMCLK TIMER_A_CTL_SSEL__SMCLK /*!< SMCLK */
#define TASSEL__INCLK TIMER_A_CTL_SSEL__INCLK /*!< INCLK */
/* TA0CCTLN[CCIFG] Bits */
#define CCIFG_OFS TIMER_A_CCTLN_CCIFG_OFS /*!< CCIFG Offset */
#define CCIFG TIMER_A_CCTLN_CCIFG /*!< Capture/compare interrupt flag */
/* TA0CCTLN[COV] Bits */
#define COV_OFS TIMER_A_CCTLN_COV_OFS /*!< COV Offset */
#define COV TIMER_A_CCTLN_COV /*!< Capture overflow */
/* TA0CCTLN[OUT] Bits */
//#define OUT_OFS TIMER_A_CCTLN_OUT_OFS /*!< OUT Offset */
//#define OUT TIMER_A_CCTLN_OUT /*!< Output */
/* TA0CCTLN[CCI] Bits */
#define CCI_OFS TIMER_A_CCTLN_CCI_OFS /*!< CCI Offset */
#define CCI TIMER_A_CCTLN_CCI /*!< Capture/compare input */
/* TA0CCTLN[CCIE] Bits */
#define CCIE_OFS TIMER_A_CCTLN_CCIE_OFS /*!< CCIE Offset */
#define CCIE TIMER_A_CCTLN_CCIE /*!< Capture/compare interrupt enable */
/* TA0CCTLN[OUTMOD] Bits */
#define OUTMOD_OFS TIMER_A_CCTLN_OUTMOD_OFS /*!< OUTMOD Offset */
#define OUTMOD_M TIMER_A_CCTLN_OUTMOD_MASK /*!< Output mode */
#define OUTMOD0 TIMER_A_CCTLN_OUTMOD0 /*!< OUTMOD Bit 0 */
#define OUTMOD1 TIMER_A_CCTLN_OUTMOD1 /*!< OUTMOD Bit 1 */
#define OUTMOD2 TIMER_A_CCTLN_OUTMOD2 /*!< OUTMOD Bit 2 */
#define OUTMOD_0 TIMER_A_CCTLN_OUTMOD_0 /*!< OUT bit value */
#define OUTMOD_1 TIMER_A_CCTLN_OUTMOD_1 /*!< Set */
#define OUTMOD_2 TIMER_A_CCTLN_OUTMOD_2 /*!< Toggle/reset */
#define OUTMOD_3 TIMER_A_CCTLN_OUTMOD_3 /*!< Set/reset */
#define OUTMOD_4 TIMER_A_CCTLN_OUTMOD_4 /*!< Toggle */
#define OUTMOD_5 TIMER_A_CCTLN_OUTMOD_5 /*!< Reset */
#define OUTMOD_6 TIMER_A_CCTLN_OUTMOD_6 /*!< Toggle/set */
#define OUTMOD_7 TIMER_A_CCTLN_OUTMOD_7 /*!< Reset/set */
/* TA0CCTLN[CAP] Bits */
#define CAP_OFS TIMER_A_CCTLN_CAP_OFS /*!< CAP Offset */
#define CAP TIMER_A_CCTLN_CAP /*!< Capture mode */
/* TA0CCTLN[SCCI] Bits */
#define SCCI_OFS TIMER_A_CCTLN_SCCI_OFS /*!< SCCI Offset */
#define SCCI TIMER_A_CCTLN_SCCI /*!< Synchronized capture/compare input */
/* TA0CCTLN[SCS] Bits */
#define SCS_OFS TIMER_A_CCTLN_SCS_OFS /*!< SCS Offset */
#define SCS TIMER_A_CCTLN_SCS /*!< Synchronize capture source */
/* TA0CCTLN[CCIS] Bits */
#define CCIS_OFS TIMER_A_CCTLN_CCIS_OFS /*!< CCIS Offset */
#define CCIS_M TIMER_A_CCTLN_CCIS_MASK /*!< Capture/compare input select */
#define CCIS0 TIMER_A_CCTLN_CCIS0 /*!< CCIS Bit 0 */
#define CCIS1 TIMER_A_CCTLN_CCIS1 /*!< CCIS Bit 1 */
#define CCIS_0 TIMER_A_CCTLN_CCIS_0 /*!< CCIxA */
#define CCIS_1 TIMER_A_CCTLN_CCIS_1 /*!< CCIxB */
#define CCIS_2 TIMER_A_CCTLN_CCIS_2 /*!< GND */
#define CCIS_3 TIMER_A_CCTLN_CCIS_3 /*!< VCC */
#define CCIS__CCIA TIMER_A_CCTLN_CCIS__CCIA /*!< CCIxA */
#define CCIS__CCIB TIMER_A_CCTLN_CCIS__CCIB /*!< CCIxB */
#define CCIS__GND TIMER_A_CCTLN_CCIS__GND /*!< GND */
#define CCIS__VCC TIMER_A_CCTLN_CCIS__VCC /*!< VCC */
/* TA0CCTLN[CM] Bits */
#define CM_OFS TIMER_A_CCTLN_CM_OFS /*!< CM Offset */
#define CM_M TIMER_A_CCTLN_CM_MASK /*!< Capture mode */
#define CM0 TIMER_A_CCTLN_CM0 /*!< CM Bit 0 */
#define CM1 TIMER_A_CCTLN_CM1 /*!< CM Bit 1 */
#define CM_0 TIMER_A_CCTLN_CM_0 /*!< No capture */
#define CM_1 TIMER_A_CCTLN_CM_1 /*!< Capture on rising edge */
#define CM_2 TIMER_A_CCTLN_CM_2 /*!< Capture on falling edge */
#define CM_3 TIMER_A_CCTLN_CM_3 /*!< Capture on both rising and falling edges */
#define CM__NONE TIMER_A_CCTLN_CM__NONE /*!< No capture */
#define CM__RISING TIMER_A_CCTLN_CM__RISING /*!< Capture on rising edge */
#define CM__FALLING TIMER_A_CCTLN_CM__FALLING /*!< Capture on falling edge */
#define CM__BOTH TIMER_A_CCTLN_CM__BOTH /*!< Capture on both rising and falling edges */
/* TA0EX0[TAIDEX] Bits */
#define TAIDEX_OFS TIMER_A_EX0_IDEX_OFS /*!< TAIDEX Offset */
#define TAIDEX_M TIMER_A_EX0_IDEX_MASK /*!< Input divider expansion */
#define TAIDEX0 TIMER_A_EX0_IDEX0 /*!< TAIDEX Bit 0 */
#define TAIDEX1 TIMER_A_EX0_IDEX1 /*!< TAIDEX Bit 1 */
#define TAIDEX2 TIMER_A_EX0_IDEX2 /*!< TAIDEX Bit 2 */
#define TAIDEX_0 TIMER_A_EX0_TAIDEX_0 /*!< Divide by 1 */
#define TAIDEX_1 TIMER_A_EX0_TAIDEX_1 /*!< Divide by 2 */
#define TAIDEX_2 TIMER_A_EX0_TAIDEX_2 /*!< Divide by 3 */
#define TAIDEX_3 TIMER_A_EX0_TAIDEX_3 /*!< Divide by 4 */
#define TAIDEX_4 TIMER_A_EX0_TAIDEX_4 /*!< Divide by 5 */
#define TAIDEX_5 TIMER_A_EX0_TAIDEX_5 /*!< Divide by 6 */
#define TAIDEX_6 TIMER_A_EX0_TAIDEX_6 /*!< Divide by 7 */
#define TAIDEX_7 TIMER_A_EX0_TAIDEX_7 /*!< Divide by 8 */
#define TAIDEX__1 TIMER_A_EX0_IDEX__1 /*!< Divide by 1 */
#define TAIDEX__2 TIMER_A_EX0_IDEX__2 /*!< Divide by 2 */
#define TAIDEX__3 TIMER_A_EX0_IDEX__3 /*!< Divide by 3 */
#define TAIDEX__4 TIMER_A_EX0_IDEX__4 /*!< Divide by 4 */
#define TAIDEX__5 TIMER_A_EX0_IDEX__5 /*!< Divide by 5 */
#define TAIDEX__6 TIMER_A_EX0_IDEX__6 /*!< Divide by 6 */
#define TAIDEX__7 TIMER_A_EX0_IDEX__7 /*!< Divide by 7 */
#define TAIDEX__8 TIMER_A_EX0_IDEX__8 /*!< Divide by 8 */
/******************************************************************************
* WDT_A Bits (legacy section)
******************************************************************************/
/* WDTCTL[WDTIS] Bits */
#define WDTIS_OFS WDT_A_CTL_IS_OFS /*!< WDTIS Offset */
#define WDTIS_M WDT_A_CTL_IS_MASK /*!< Watchdog timer interval select */
#define WDTIS0 WDT_A_CTL_IS0 /*!< WDTIS Bit 0 */
#define WDTIS1 WDT_A_CTL_IS1 /*!< WDTIS Bit 1 */
#define WDTIS2 WDT_A_CTL_IS2 /*!< WDTIS Bit 2 */
#define WDTIS_0 WDT_A_CTL_IS_0 /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */
#define WDTIS_1 WDT_A_CTL_IS_1 /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */
#define WDTIS_2 WDT_A_CTL_IS_2 /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */
#define WDTIS_3 WDT_A_CTL_IS_3 /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */
#define WDTIS_4 WDT_A_CTL_IS_4 /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */
#define WDTIS_5 WDT_A_CTL_IS_5 /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */
#define WDTIS_6 WDT_A_CTL_IS_6 /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */
#define WDTIS_7 WDT_A_CTL_IS_7 /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */
/* WDTCTL[WDTCNTCL] Bits */
#define WDTCNTCL_OFS WDT_A_CTL_CNTCL_OFS /*!< WDTCNTCL Offset */
#define WDTCNTCL WDT_A_CTL_CNTCL /*!< Watchdog timer counter clear */
/* WDTCTL[WDTTMSEL] Bits */
#define WDTTMSEL_OFS WDT_A_CTL_TMSEL_OFS /*!< WDTTMSEL Offset */
#define WDTTMSEL WDT_A_CTL_TMSEL /*!< Watchdog timer mode select */
/* WDTCTL[WDTSSEL] Bits */
#define WDTSSEL_OFS WDT_A_CTL_SSEL_OFS /*!< WDTSSEL Offset */
#define WDTSSEL_M WDT_A_CTL_SSEL_MASK /*!< Watchdog timer clock source select */
#define WDTSSEL0 WDT_A_CTL_SSEL0 /*!< WDTSSEL Bit 0 */
#define WDTSSEL1 WDT_A_CTL_SSEL1 /*!< WDTSSEL Bit 1 */
#define WDTSSEL_0 WDT_A_CTL_SSEL_0 /*!< SMCLK */
#define WDTSSEL_1 WDT_A_CTL_SSEL_1 /*!< ACLK */
#define WDTSSEL_2 WDT_A_CTL_SSEL_2 /*!< VLOCLK */
#define WDTSSEL_3 WDT_A_CTL_SSEL_3 /*!< BCLK */
#define WDTSSEL__SMCLK WDT_A_CTL_SSEL__SMCLK /*!< SMCLK */
#define WDTSSEL__ACLK WDT_A_CTL_SSEL__ACLK /*!< ACLK */
#define WDTSSEL__VLOCLK WDT_A_CTL_SSEL__VLOCLK /*!< VLOCLK */
#define WDTSSEL__BCLK WDT_A_CTL_SSEL__BCLK /*!< BCLK */
/* WDTCTL[WDTHOLD] Bits */
#define WDTHOLD_OFS WDT_A_CTL_HOLD_OFS /*!< WDTHOLD Offset */
#define WDTHOLD WDT_A_CTL_HOLD /*!< Watchdog timer hold */
/* WDTCTL[WDTPW] Bits */
#define WDTPW_OFS WDT_A_CTL_PW_OFS /*!< WDTPW Offset */
#define WDTPW_M WDT_A_CTL_PW_MASK /*!< Watchdog timer password */
/* Pre-defined bitfield values */
#define WDTPW WDT_A_CTL_PW /*!< WDT Key Value for WDT write access */
#ifdef __cplusplus
}
#endif
#endif /* __MSP432P401R_CLASSIC_H__ */
|
Emmie-He/fluid-simulation | code/src/temp/Particles.h | <reponame>Emmie-He/fluid-simulation<gh_stars>1-10
/*
* To change this license header, choose License Headers in Project Properties.
* To change this template file, choose Tools | Templates
* and open the template in the editor.
*/
/*
* File: Particles.h
* Author: swl
*
* Created on April 15, 2016, 12:16 PM
*/
#ifndef PARTICLES_H
#define PARTICLES_H
#include <glm/glm.hpp>
#include <vector>
#if defined(__APPLE_CC__)
#include <GLFW/glfw3.h>
#include <OpenGL/glu.h>
#include <GLUT/glut.h>
#else
#include <GL/glut.h>
#include <math.h>
#endif
#define IX(x, y, z) ((x) + (y) * N + (z) * N * N)
class Particles {
public:
int size;
float dt;
float diff;
float visc;
float *s;
float *density;
float *Vx;
float *Vy;
float *Vz;
float *Vx0;
float *Vy0;
float *Vz0;
Particles();
Particles(int size, int diffusion, int viscosity, float dt);
void render() const;
void step(){} // simulate one frame
void freeParticles();
void FluidCubeAddDensity(int x, int y, int z, float amount);
void FluidCubeAddVelocity(int x, int y, int z, float amountX, float amountY, float amountZ);
void set_bnd(int b, float *x, int N);
void lin_solve(int b, float *x, float *x0, float a, float c, int iter, int N);
void diffuse (int b, float *x, float *x0, float diff, float dt, int iter, int N);
void project(float *velocX, float *velocY, float *velocZ, float *p, float *div, int iter, int N);
void advect(int b, float *d, float *d0, float *velocX, float *velocY, float *velocZ, float dt, int N);
void FluidCubeStep();
private:
struct Particle
{
glm::dvec3 p;
glm::dvec3 v;
glm::dvec3 v_last;
};
std::vector<Particle> particles;
};
#endif /* PARTICLES_H */
|
Emmie-He/fluid-simulation | code/src/Particles.h | /*
* To change this license header, choose License Headers in Project Properties.
* To change this template file, choose Tools | Templates
* and open the template in the editor.
*/
/*
* File: Particles.h
* Author: swl
*
* Created on April 15, 2016, 12:16 PM
*/
#ifndef PARTICLES_H
#define PARTICLES_H
#include <glm/glm.hpp>
#include <vector>
#include <stdlib.h>
#include <unordered_set>
#include <unordered_map>
#include <iostream>
#if defined(__APPLE_CC__)
#include <GLFW/glfw3.h>
#include <OpenGL/glu.h>
#include <GLUT/glut.h>
#else
#include <GL/glut.h>
#include <math.h>
#endif
#include <CGL/vector3D.h>
using namespace std;
using namespace CGL;
#define DENSITY 1000
class Particles {
private:
struct Particle
{
Vector3D p;
Vector3D last_p;
Vector3D delta_p;
Vector3D v;
double lambda;
vector<Particle *> neighbors;
};
// components
vector<Particle> particles;
// spatial map
unordered_map<int, vector<Particle *> *> map;
// gravity
Vector3D g = Vector3D(0, -9.8, 0); // m per square s
double hn;
public:
// properties
// render radius is how big the particles are
double render_radius = 0.03;
double cube_length;
double bound; // bounding box - (- bound, - bound, - bound) to (bound, bound, bound)
int N; // number of particles per side
double d;
double h;
double initial_height;
double rho_0 = 100; // initial density
// ETA is a small relaxation parameter, I think it should be rho_0/20.0. I think it should be constant
double ETA = 3; //relaxing factor
double k = 0.0001;
double exp_n = 4;
double delta_q = 0.01;
//Vector3D gradient_eta = Vector3D(0.001, 0.001, 0.001);
int solverIterations = 10;
Particles();
Particles(int N, double height);
Particles(double cube_length, double bound, int N, double d, double h);
void render() const;
int hash_position(Vector3D pos);
void simulate(double frames_per_sec, double simulation_steps);// simulate one frame
void find_neighbors(Particle &par);
void build_spatial_map();
int hash_to_key(Vector3D hash);
void collision_handling(Particle &par);
void boundary_check(Particle &par);
};
#endif /* PARTICLES_H */
|
mastensg/backlightd | main.c | #define _DEFAULT_SOURCE
#include <stdio.h>
#include <stdlib.h>
#include <err.h>
#include <poll.h>
#include <sys/time.h>
#include <linux/input.h>
const int the_keyboard_steps[] = {0, 8, 16, 32, 64, 128, 192, 255};
size_t the_keyboard_numsteps =
sizeof(the_keyboard_steps) / sizeof(the_keyboard_steps[0]);
const int the_screen_steps[] = {0, 16, 32, 48, 64, 96, 128, 192,
256, 384, 512, 768, 1024, 1536, 2048, 2777};
size_t the_screen_numsteps =
sizeof(the_screen_steps) / sizeof(the_screen_steps[0]);
const char the_input_path[] =
"/dev/input/by-id/"
"usb-Apple_Inc._Apple_Internal_Keyboard___Trackpad_DQ64222B5JXF94QAJCA-"
"if01-event-kbd";
const char the_keyboard_path[] =
"/sys/devices/platform/applesmc.768/leds/smc::kbd_backlight/brightness";
const char the_screen_path[] =
"/sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/"
"intel_backlight/brightness";
static int query(const char *path) {
FILE *f;
int v;
if (NULL == (f = fopen(path, "r"))) {
err(EXIT_FAILURE, "fopen %s", path);
}
if (1 != fscanf(f, "%d\n", &v)) {
err(EXIT_FAILURE, "fscanf");
}
if (EOF == fclose(f)) {
err(EXIT_FAILURE, "fclose");
};
return v;
}
static void update(FILE *f, int v) {
if (0 > fprintf(f, "%d\n", v)) {
err(EXIT_FAILURE, "fprintf");
}
if (EOF == fflush(f)) {
err(EXIT_FAILURE, "fflush");
};
}
static int step(int x, const int *steps, size_t numsteps, int direction) {
if (1 == direction) {
for (size_t i = 0; i < numsteps; ++i) {
if (x < steps[i]) {
return steps[i];
};
}
return x;
}
for (size_t i = 0; i < numsteps; ++i) {
size_t j;
j = numsteps - 1 - i;
if (steps[j] < x) {
return steps[j];
};
}
return x;
}
int main() {
FILE *input_file;
FILE *keyboard_file;
FILE *screen_file;
struct input_event ie;
int keyboard_brightness;
int screen_brightness;
if (NULL == (input_file = fopen(the_input_path, "r"))) {
err(EXIT_FAILURE, "fopen %s", the_input_path);
}
keyboard_brightness = query(the_keyboard_path);
screen_brightness = query(the_screen_path);
if (NULL == (keyboard_file = fopen(the_keyboard_path, "w"))) {
err(EXIT_FAILURE, "fopen %s", the_keyboard_path);
}
if (NULL == (screen_file = fopen(the_screen_path, "w"))) {
err(EXIT_FAILURE, "fopen %s", the_screen_path);
}
struct timeval last_update_tv = {0};
for (;;) {
// Wait for keypress or timeout
int numevents;
{
int input_fd = fileno(input_file);
struct pollfd pfd = {.fd = input_fd, .events = POLLIN};
if (-1 == (numevents = poll(&pfd, 1, 1000))) {
err(EXIT_FAILURE, "poll");
}
}
struct timeval now_tv;
if (-1 == gettimeofday(&now_tv, NULL)) {
err(EXIT_FAILURE, "gettimeofday");
}
if (0 == numevents) {
goto no_command;
}
if (1 != fread(&ie, sizeof(ie), 1, input_file)) {
err(EXIT_FAILURE, "fread");
}
if (ie.value < 1 || 2 < ie.value) {
goto no_command;
}
switch (ie.code) {
case KEY_BRIGHTNESSDOWN:
screen_brightness =
step(screen_brightness, the_screen_steps, the_screen_numsteps, -1);
break;
case KEY_BRIGHTNESSUP:
screen_brightness =
step(screen_brightness, the_screen_steps, the_screen_numsteps, 1);
break;
case KEY_KBDILLUMDOWN:
keyboard_brightness = step(keyboard_brightness, the_keyboard_steps,
the_keyboard_numsteps, -1);
break;
case KEY_KBDILLUMUP:
keyboard_brightness = step(keyboard_brightness, the_keyboard_steps,
the_keyboard_numsteps, 1);
break;
default:
goto no_command;
}
update(screen_file, screen_brightness);
update(keyboard_file, keyboard_brightness);
last_update_tv = now_tv;
fprintf(stderr, "screen %4d; keyboard %3d\n", screen_brightness,
keyboard_brightness);
continue;
no_command:
if (last_update_tv.tv_sec < now_tv.tv_sec) {
update(screen_file, screen_brightness);
update(keyboard_file, keyboard_brightness);
last_update_tv = now_tv;
}
}
return EXIT_SUCCESS;
}
|
dwjackson/rbdym | ext/dym/dym.c | <reponame>dwjackson/rbdym
#include "ruby.h"
#include <dym.h>
#include <stdlib.h>
static VALUE rbdym_dl_edist(VALUE self, VALUE s1, VALUE s2);
static char *rstr2cstr(VALUE str);
void Init_dym()
{
VALUE mod = rb_define_module("DYM");
rb_define_method(mod, "edist", rbdym_dl_edist, 2);
}
static VALUE rbdym_dl_edist(VALUE self, VALUE s1, VALUE s2)
{
int dist;
char *cstr1;
char *cstr2;
VALUE rb_dist;
if (RB_TYPE_P(s1, T_STRING) != 1 || RB_TYPE_P(s2, T_STRING) != 1) {
return Qnil;
}
cstr1 = rstr2cstr(s1);
cstr2 = rstr2cstr(s2);
if (cstr1 == NULL || cstr2 == NULL) {
free(cstr1);
free(cstr2);
return Qnil;
}
dist = dym_dl_edist(cstr1, cstr2);
rb_dist = INT2NUM(dist);
free(cstr2);
free(cstr1);
return rb_dist;
}
static char *rstr2cstr(VALUE str)
{
size_t len;
char *cstr;
if (RB_TYPE_P(str, T_STRING) != 1) {
return NULL;
}
len = RSTRING_LEN(str);
cstr = calloc(len + 1, 1);
if (cstr == NULL) {
return NULL;
}
strncpy(cstr, RSTRING_PTR(str), len);
return cstr;
}
|
n-fallahinia/UoU_Genral_Class | include/Constants.h | <gh_stars>0
// Constants file
#ifndef UTAH_CONSTANTS
#define UTAH_CONSTANTS
// Error definitions
enum Utah_Errors
{
UTAH_NO_ERROR = 0,
UTAH_BAD_FILE_NAME
};
////////////////////////////////////////////////////////////////////////////////
// Mathematical constants
#define PI 3.141592
////////////////////////////////////////////////////////////////////////////////
// Maglev constants
// Number of directions used to represent pose in the MLHD
#define DATA_SIZE 6
// Number of control steps used to transition between controllers
#define NUM_TRANSITIONS 50.0
// Cutoff frequency (in Hertz) for the velocity filter
#define CUTOFF_FREQUENCY 100.0
// Frequency (in Hertz) at which to draw the Position
#define POSITION_FREQUENCY 10.0
////////////////////////////////////////////////////////////////////////////////
// BarPlot values
// Define vertical location for x-axis
#define X_AXIS 0.0
// Define title y-coordinate
#define TITLE_POSITION 9.0
// Define horizontal locations for (L)eft and (R)ight axis labels
#define L_AXIS -9.5
#define R_AXIS 7.0
// Define scales for (L)eft and (R)ight axes
#define L_SCALE 1.0
#define R_SCALE 1.0/30.0
////////////////////////////////////////////////////////////////////////////////
// TimePlot values
// Number of data points
#define NUM_DATA 200000
////////////////////////////////////////////////////////////////////////////////
// WorkspacePlot values
// Distance above and below z=0 to change colors
#define AXIS_TOL 4.0
// Maximum radius in (x,y,z) -- should replace this with the values from the maglev boundary
#define MAX_RADIUS 12.0
// Number of lines for drawing the Maglev position circle
#define NUM_LINES 36
////////////////////////////////////////////////////////////////////////////////
// main values
// Maximum value for position integral (to prevent integrator wind-up)
#define MAX_POSITION_INTEGRAL 1.0
// Maximum value for force integral (to prevent integrator wind-up)
#define MAX_FORCE_INTEGRAL 10.0
// Number of columns of data to save
#define NUM_COLUMNS 49
/////////////////////////////////////
// Trajectory data
// Stroke velocity, meters per second
#define STROKE_VELOCITY 0.005
// Stroke length, meters
#define STROKE_LENGTH 0.020
// Stroke Mean, meters
#define STROKE_MEAN 0.0
// Number of strokes to perform
#define NUM_STROKES 10
// Amount of time (in seconds) to give at the beginning of the trajectory
#define INITIAL_TIME 5.0
////////////////////////////////////////////////////////////////////////////////
// ForceSensor values
// Frequency at which to display the force readings
#define FORCE_FREQUENCY 10.0
// Not sure what these were for...
//#define RAW_TOL 9.0
//#define FORCE_TOL 0.75
#endif
|
n-fallahinia/UoU_Genral_Class | include/maglev/ml_api_1.h | <filename>include/maglev/ml_api_1.h<gh_stars>0
#ifndef __ML_API_1_H__
#define __ML_API_1_H__
#include "ml_api.h"
int invoke_local_function(ml_device_handle_t dev_hdl, ml_function_id_t* func_id,
char* args_in, char* args_out);
#endif // __ML_API_1_H__
|
n-fallahinia/UoU_Genral_Class | include/maglev/ml_api.h | /*! \file ml_api.h
\brief This is a header file for ml_api.c, which contains the api declaration
for both client side and server side of the Magnetic Levitation Haptic Interface API.
\author <NAME>
\date Created: Jul 14, 2005 \n Last Revision: Jul 14, 2005
\author <NAME>
\date Updated: Jul 14, 2006
\author <NAME>
\date Updated: Feb 01, 2007
\author <NAME>
\date Updated: Jan 23, 2008
<B>Supervisor:</B> \n
Dr. <NAME> \n\n
<B>Location:</B> \n
Carnegie Mellon University, Robotics Institute: \n
Microdynamic Systems Laboratory \n
*/
#ifndef _ML_API_H_
#define _ML_API_H_
#include "ml_error.h" // MLHI API error codes
#include "ml_constants.h" // MLHI API custom constants
#include "ml_types.h" // MLHI API custom types
//#include "ml_api_common.h" // MLHI common non-RPC types
#ifdef __cplusplus
extern "C"{
#endif
static const char * const CLIENT_VERSION = "1.5b";
static const int maglev_port = 5678;
/*******************************************************/
/*******************************************************/
/*** GAIN CONTROL FUNCTIONS ***/
/*******************************************************/
/*******************************************************/
//-----------------------------------------------//
// SIMPLE PID CONTROLLER (vector representation) //
//-----------------------------------------------//
// Resets the P, I, and D gain and FF force vectors to the system default values
int ml_ResetGainVecAxes(ml_device_handle_t dev_hdl,
ml_gainset_type_t gainset_type );
// Sets the P, I, and D gain vectors respectively
int ml_SetGainVecAxes(ml_device_handle_t dev_hdl,
ml_gainset_type_t gainset_type,
ml_gain_vec_t gains );
// Gets the P, I, and D gain vectors respectively (into the given pointers)
int ml_GetGainVecAxes(ml_device_handle_t dev_hdl,
ml_gainset_type_t gainset_type,
ml_gain_vec_t *gains );
// Sets the P, I, and D gain values for the given (axis)
int ml_SetGainVecAxis(ml_device_handle_t dev_hdl,
ml_gainset_type_t gainset_type,
ml_axis_index_t axis,
ml_gain_pid_t gain );
// Gets the P, I, and D gain values for the given (axis) (into the given ptr.)
int ml_GetGainVecAxis(ml_device_handle_t dev_hdl,
ml_gainset_type_t gainset_type,
ml_axis_index_t axis,
ml_gain_pid_t *gain );
// Sets the P, I, and D gain values for the grasp axis
int ml_SetGainVecGrasp(ml_device_handle_t dev_hdl,
ml_gain_pid_t gain );
// Gets the P, I, and D gain values for the grasp axis
int ml_GetGainVecGrasp(ml_device_handle_t dev_hdl,
ml_gain_pid_t *gain );
// Sets a single gain value for a given (axis) and (gaintype)
int ml_SetGainVecSingle(ml_device_handle_t dev_hdl,
ml_gainset_type_t gainset_type,
ml_axis_index_t axis,
ml_gain_type_t gaintype,
ml_gain_t value);
// Gets a single gain value for a given (axis) and (gaintype) (into the ptr)
int ml_GetGainVecSingle(ml_device_handle_t dev_hdl,
ml_gainset_type_t gainset_type,
ml_axis_index_t axis,
ml_gain_type_t gaintype,
ml_gain_t * value);
// Sets the limit on how fast flotor can move
int ml_SetSpeedLimits(ml_device_handle_t dev_hdl,
ml_velocities_t maxspeeds);
// Gets the limit on how fast flotor can move
int ml_GetSpeedLimits(ml_device_handle_t dev_hdl,
ml_velocities_t* maxspeeds);
/*******************************************************/
/*******************************************************/
/*** COMMUNICATION CONTROL FUNCTIONS ***/
/*******************************************************/
/*******************************************************/
// Initializes a communcation connection between the client and MLHI controller
int ml_Connect(ml_device_handle_t* dev_hdl,
const char* const addr );
// Closes a communication connection between the client and MLHI controller
int ml_Disconnect(ml_device_handle_t dev_hdl);
/*******************************************************/
/*******************************************************/
/*** CALLBACK FUNCTIONS ***/
/*******************************************************/
/*******************************************************/
// Add Callback Step #2: Add a callback registration function declaration here.
// Specifies action to take when button state changes
int ml_RegisterCallbackButtonPressed(ml_device_handle_t dev_hdl,
button_state_callback_func_t buttonCallbackFunc);
// Specifies action to take when flotor violates specified edge boundary
int ml_RegisterCallbackFlotorBoundaryViolation(ml_device_handle_t dev_hdl,
boundary_callback_func_t boundaryCallbackFunc);
// Specifies action to take when flotor coil(s) are believed to be overheating
int ml_RegisterCallbackOvertemp(ml_device_handle_t dev_hdl,
coil_overtemp_callback_func_t coilOvertempCallbackFunc);
// Specifies action to take if flotor signals it has shutdown
int ml_RegisterCallbackFault(ml_device_handle_t dev_hdl,
fault_callback_func_t faultCallbackFunc);
// Specifies action to take at the top of every servo interval
int ml_RegisterCallbackTick(ml_device_handle_t dev_hdl,
tick_callback_func_t tickCallbackFunc);
// Specifies action to take when button state changes
int ml_UnregisterCallbackButtonPressed(ml_device_handle_t dev_hdl);
// Specifies action to take when flotor violates specified edge boundary
int ml_UnregisterCallbackFlotorBoundaryViolation(ml_device_handle_t dev_hdl);
// Specifies action to take when flotor coil(s) are believed to be overheating
int ml_UnregisterCallbackOvertemp(ml_device_handle_t dev_hdl);
// Specifies action to take if flotor signals it has shutdown
int ml_UnregisterCallbackFault(ml_device_handle_t dev_hdl);
// Specifies action to take at the top of every servo interval
int ml_UnregisterCallbackTick(ml_device_handle_t dev_hdl);
/*******************************************************/
/*******************************************************/
/*** INTERACTION FUNCTIONS ***/
/*******************************************************/
/*******************************************************/
// Offsets the world coordinate frame by a given transformation
int ml_SetFrame(ml_device_handle_t dev_hdl,
ml_position_t frame);
// Gets the offset of the current world frame (into the given pointer)
int ml_GetFrame(ml_device_handle_t dev_hdl,
ml_position_t* frame);
// Sets a new desired position for the flotor
int ml_SetDesiredPosition(ml_device_handle_t dev_hdl,
ml_position_t position);
// Gets the current position of the flotor
int ml_GetActualPosition(ml_device_handle_t dev_hdl,
ml_position_t * read_position);
// Gets the current desired position of the flotor
int ml_GetDesiredPosition(ml_device_handle_t dev_hdl,
ml_position_t * desired_position);
// Applies a given velocity to the flotor via interpolation from the last pos.
int ml_SetVelocity(ml_device_handle_t dev_hdl,
ml_velocities_t velocity);
// Gets the current flotor velocity (into the given pointer)
int ml_GetVelocity(ml_device_handle_t dev_hdl,
ml_velocities_t * read_velocity);
// Applies a given wrench to all 6 degrees of freedom
int ml_SetForces(ml_device_handle_t dev_hdl,
ml_forces_t wrench);
// Applies a given wrench to the given axis
int ml_SetForceAxis(ml_device_handle_t dev_hdl,
ml_axis_index_t axis,
ml_force_t force);
// Reads the wrench currently being applied to all axes (into the given ptr.)
int ml_GetForces(ml_device_handle_t dev_hdl,
ml_forces_t* wrench);
// Reads the wrench currently being applied to one of the axes (into the ptr.)
int ml_GetForceAxis(ml_device_handle_t dev_hdl,
ml_axis_index_t axis,
ml_force_t* force);
// Entirely locks motion on a given axis in its current position
int ml_LockAxis(ml_device_handle_t dev_hdl,
ml_axis_index_t axis);
// Unlocks motion on a given axis (does nothing if already unlocked)
int ml_UnlockAxis(ml_device_handle_t dev_hdl,
ml_axis_index_t axis);
// Restricts motion on a specified axis to within specified bounds
int ml_ConstrainAxis(ml_device_handle_t dev_hdl,
ml_axis_index_t axis,
ml_coord_t minpos,
ml_coord_t maxpos);
// Returns axis mode for each axis.
int ml_GetAxisModes(ml_device_handle_t dev_hdl,
ml_axis_mode_vec_t * axis_mode_vec);
// Finds the orientation of the gravity vector in the current coordinate frame.
int ml_FindGravity(ml_device_handle_t dev_hdl,
ml_forces_t *gravity);
// Inputs a new vector to use as the gravity vector
int ml_SetGravity(ml_device_handle_t dev_hdl,
ml_forces_t garvity);
// Reads the gravity vector currently being used by the MLHI controller
int ml_GetGravity(ml_device_handle_t dev_hdl,
ml_forces_t* read_gravity);
// Causes the MLHI to resist gravity along the currently set gravity vector
int ml_DefyGravity(ml_device_handle_t dev_hdl);
// Transitions the flotor from an idle state to an initial, floating state.
int ml_Takeoff(ml_device_handle_t dev_hdl);
// Transitions the flotor from a floating state to an idle state.
int ml_Land(ml_device_handle_t dev_hdl);
// Sends a shutdown command to the MLHI controller
int ml_Shutdown(ml_device_handle_t dev_hdl);
// Get buttons status on the handle
int ml_GetButtonStatus(ml_device_handle_t dev_hdl,
ml_button_t *buton);
/*******************************************************/
/*******************************************************/
/*** UTILITY FUNCTIONS ***/
/*******************************************************/
/*******************************************************/
// Reads the estimated temperatures of the six coils
int ml_GetTemp(ml_device_handle_t dev_hdl,
ml_temps_t * read_temp);
// Returns the prevailing servo frequency.
int ml_GetServoFrequency(ml_device_handle_t dev_hdl,
float * servo_frequency);
// Sets the prevailing servo frequency.
int ml_SetServoFrequency(ml_device_handle_t dev_hdl,
float servo_frequency);
// Outputs specified voltage to Aux Diagnostic Output
int ml_SetAuxDac(ml_device_handle_t dev_hdl,
float voltage);
// Gets server and client api version
int ml_GetVersion(ml_device_handle_t dev_hdl,
char * client_version,
char * server_version);
/*******************************************************/
/*******************************************************/
/*** DIRECT HARDWARE FUNCTIONS ***/
/*******************************************************/
/*******************************************************/
// Set the currents to output to each of the six coils
int ml_SetCurrents(ml_device_handle_t dev_hdl,
ml_currents_t client_currents);
// Reads the currents currently being applied to the coils (into the ptr.)
int ml_GetCurrents(ml_device_handle_t dev_hdl,
ml_currents_t* read_currents);
// Sets the limit on how much current can be applied to each coil
int ml_SetCurrentLimits(ml_device_handle_t dev_hdl,
ml_currents_t maxcurrents);
// Gets the maximum current that can be applied to each coil (into the ptr.)
int ml_GetCurrentLimits(ml_device_handle_t dev_hdl,
ml_currents_t* maxcurrents);
// Sets the current to output to the grasp axis
int ml_SetGraspCurrent(ml_device_handle_t dev_hdl,
ml_current_t current);
// Gets the current being applied to the grasp axis
int ml_GetGraspCurrent(ml_device_handle_t dev_hdl,
ml_current_t* current);
// Sets the maximum current that can be applied to the grasp axis
int ml_SetGraspCurrentLimit(ml_device_handle_t dev_hdl,
ml_current_t maxcurrent);
// Gets the maximum current that can be applied to the grasp axis
int ml_GetGraspCurrentLimit(ml_device_handle_t dev_hdl,
ml_current_t* maxcurrent);
// Gets the maximum position of the LED position sensors
int ml_GetLatCellLimit(ml_device_handle_t dev_hdl,
float *limit);
// Sets a calibration offset for the LED position sensors
int ml_SetLatCellOffset(ml_device_handle_t dev_hdl,
ml_sensor_offset_t cella,
ml_sensor_offset_t cellb,
ml_sensor_offset_t cellc);
// Gets the calibration offset for the LED position sensors
int ml_GetLatCellOffset(ml_device_handle_t dev_hdl,
ml_sensor_offset_t* cella,
ml_sensor_offset_t* cellb,
ml_sensor_offset_t* cellc);
// Gets the raw cell position values and places them into the given addresses
int ml_GetCellPosition(ml_device_handle_t dev_hdl,
ml_sensor_t* cella,
ml_sensor_t* cellb,
ml_sensor_t* cellc);
// Gets the raw voltages coming off of the three lat cells
int ml_GetRawCellData(ml_device_handle_t dev_hdl,
ml_sensor_raw_data_t *sensorRaw);
// Read ADC values and store them into the buffer
int ml_RecordVoltages(ml_device_handle_t dev_hdl);
// Update the flotor position information
int ml_UpdatePosition(ml_device_handle_t dev_hdl);
// get radius of bounding sphere
int ml_GetBoundaryRadius(ml_device_handle_t dev_hdl,
float * radius);
// set radius of bounding sphere
int ml_SetBoundaryRadius(ml_device_handle_t dev_hdl,
float radius);
int ml_GetFault(ml_device_handle_t dev_hdl,
ml_fault_t * fault);
//bool * fault);
int ml_ResetFault(ml_device_handle_t dev_hdl);
#ifdef __cplusplus
}
#endif
#endif // __ML_API_H__
|
n-fallahinia/UoU_Genral_Class | include/maglev/ml_communication.h | #ifndef _SOCKET_EXPERIMENT_H
#define _SOCKET_EXPERIMENT_H
#ifdef WIN32
#include <winsock.h>
#else
#include <sys/socket.h>
#endif
#include <sys/types.h>
#include "ml_types.h"
#ifdef __cplusplus
extern "C"{
#endif
#define MAX_COMM_BUFFER_SIZE 512 // max buffer size sent between server and client
// routine which invokes remote functions (client -> server ml_* func, server -> client callback handler).
int invoke_remote_function(int socket, ml_device_handle_t dev_hdl, ml_function_id_t func_id,
void* args_in, void* args_out);
// functions which initializes communication with TCP
int connect_to_server_tcp(in_addr dst_host_address, int port_num);
int accept_connection_from_client_tcp(struct sockaddr_in* destSockAddr, int portnum);
// functions which actually does the communication job with TCP
int send_buffer_tcp(const char* const buffer_send, int dstSocket);
int receive_buffer_tcp(char* buffer_received, int dstSocket);
#ifdef __cplusplus
}
#endif
#endif
|
n-fallahinia/UoU_Genral_Class | include/UserInterface.h | <reponame>n-fallahinia/UoU_Genral_Class<gh_stars>0
// generated by Fast Light User Interface Designer (fluid) version 1.0302
#ifndef UserInterface_h
#define UserInterface_h
#include "main.h"
#include "TimePlot.h"
#include "BarPlot.h"
#include "WorkspacePlot.h"
#include "ForceSensor.h"
#include "MaglevControl.h"
#include "TimeHandler.h"
#include <FL/Fl_Double_Window.H>
#include <FL/Fl_Group.H>
#include <FL/Fl_Choice.H>
#include <FL/Fl_Button.H>
class UserInterface
{
public:
/////////////////////////////////////////////////
// Variables
Fl_Double_Window *main_window;
TimePlot *box_time;
BarPlot *bar_force;
WorkspacePlot *my_workspace;
MaglevControl *my_maglev;
ForceSensor *my_force;
TimeHandler *my_timer;
/////////////////////////////////////////////////
// Functions
UserInterface();
~UserInterface();
void make_window();
int start_controller();
int begin_experiment();
void readDesiredData(float* desired_data);
private:
/////////////////////////////////////////////////
// Variables
// Various Buttons and Combo Boxes
Fl_Group *group_options;
Fl_Choice *cmbTongue;
Fl_Choice *cmbProduct;
Fl_Choice *cmbHydration;
Fl_Button *btnStartController;
Fl_Button *btnTest;
Fl_Button *btnForceSensor;
/////////////////////////////////////////////////
// Functions
inline void cb_btnStartController_i(Fl_Button*, void*);
static void cb_btnStartController(Fl_Button*, void*);
inline void cb_btnTest_i(Fl_Button*, void*);
static void cb_btnTest(Fl_Button*, void*);
inline void cb_btnForceSensor_i(Fl_Button*, void*);
static void cb_btnForceSensor(Fl_Button*, void*);
};
extern void display_force_reading(void * v);
extern void display_position_reading(void * v);
#endif
|
n-fallahinia/UoU_Genral_Class | include/MaglevControl.h | <reponame>n-fallahinia/UoU_Genral_Class
// Header file for MLHD interaction functions
#ifndef MAGLEV_FUNCTIONS_H
#define MAGLEV_FUNCTIONS_H
// Included files
#include "ForceSensor.h"
#include "ml_api.h"
#include <string>
class MaglevControl
{
private:
/////////////////////////////////////////////////
// Variables
// Object for communicating with the MLHD
ml_device_handle_t* device_handler;
// Defines a vector to read the internal gains
ml_gain_vec_t gain_vector;
// Type of gains to read
ml_gainset_type_t gainset_type;
// Current fault condition
ml_fault_t current_fault;
// MLHD wrench estimate
ml_forces_t maglev_forces;
ml_temps_t maglev_temperatures;
ml_currents_t maglev_currents;
// Arrays of current gains to use in controllers
double current_gains_force[6][4];
double current_gains_position[6][4];
double current_gains_internal[6][4];
// Arrays of gains to achieve after transitions
double desired_gains_force[6][4];
double desired_gains_position[6][4];
double desired_gains_internal[6][4];
// Arrays of gains to start with for the transition
double starting_gains_force[6][4];
double starting_gains_position[6][4];
double starting_gains_internal[6][4];
// Arrays of gains stored in the file
double file_gains_force[6][4];
double file_gains_position[6][4];
// Array of directions for use in force control
bool force_control_directions[6];
// Array of desired position
double desired_position[6];
double desired_force[6];
// Array of current position
double current_position[6];
// Filter constant and proportionality constant for low-pass filter
double alpha, tau;
// Control frequency for MLHD
float control_freq;
// Counter tracking the number of times the control loop has run
unsigned long long int controller_counter;
unsigned long long int start_counter;
// Booleans indicating states
bool using_external_control;
bool in_transition;
// Controller gain file name
std::string gain_file_name;
// Output file name
std::string save_file_name;
/////////////////////////////////////////////////
// Functions
// Update the current estimate of the position
void update_position();
// Update the current estimate of the forces, temperatures and currents
void get_force();
void get_temperature();
void get_current();
// Update the current matrix of internal gains
void update_internal_gains();
// Determine whether the flotor is outside the workspace boundary
bool outside_boundary();
// Read the controller gains from the gain file
void read_file_gains();
public:
/////////////////////////////////////////////////
// Variables
// Determines whether or not to follow the desired trajectory
bool use_trajectory;
/////////////////////////////////////////////////
// Functions
// Constructor/Destructor definitions
MaglevControl();
~MaglevControl();
// Functions to retrieve states
bool is_using_external_control();
bool is_in_transition();
// Calculate the minimum value of an array (of positions?)
inline double minValue(double my_array[6]);
inline float minValue(ml_position_t my_position);
// Retrieve the position of the flotor in a 6-vector
void get_position(double * position);
// Retrieve the position in a single direction
double get_position(int dirIdx);
// Connect to/Disconnect from the MLHD
bool connect();
void turn_off();
// Set the desired position vector for the class
void set_desired_position(double position[6]);
// Set the desired wrench vector for the class
void set_desired_forces(double desired_wrench[6]);
// Set the desired position for the MLHD internal position controller to
// be the same as the desired position for the class.
// NOTE: This function does nothing if the internal position
// controller is turned off!
void update_internal_desired_position();
// Retrieve the internal gain from the current_internal_gain matrix
double get_internal_gain(int dirIdx, int gainIdx);
// Set the internal gains using the current_internal_gain matrix
void set_internal_gains();
// Update the internal controller gains
// If turn_on is true, sets to the default values
// If false, sets to 0.0
// Only applies to the BOUNDARY, LOCKED, and CONSTRAINED gain types
void set_other_internal_gains(bool turn_on);
// Set the internal gains and our gains to a transitional value based on
// the NUM_TRANSITIONS and the current counter value. If count_up is
// true, our controller will ramp-on while the internal controller
// ramps off. Otherwise, the internal controller will ramp-on while
// ours ramps off.
void transition_gains();
// Send a wrench command to the MLHD. pid_force must be a 6-vector.
void set_forces(double * pid_force);
// Print the entire set of gains (internal, position, and force) to stdout.
void print_gain_matrices();
// Start & stop our external controller
void start_external_controller();
void stop_external_controller();
// Set the save file name
int set_save_file_name(std::string file_name);
/////////////////////////////////////////////////
// Controller functions
// Everything below here must be defined in an external file.
// Position controller
void PositionController(double current_time);
// Hybrid position-force controller
void HybridController(double current_time, Reading current_force);
// Digital position controller
void DigitalController(double current_time);
// Saves the data to the file force_save_file_name
void save_force_data(char* force_save_file_name);
};
#endif
|
n-fallahinia/UoU_Genral_Class | include/maglev/ml_constants.h | /*! \file ml_constants.h
\brief This header file defines MLHI-specific constants used by
the ml_ API layer and ml_ communication layer code.
\author <NAME>
\date Created: June 15, 2007
<B>Location:</B> \n
Carnegie Mellon University, Robotics Institute: \n
Microdynamic Systems Laboratory \n
*/
#ifndef __ML_CONSTANTS_H__
#define __ML_CONSTANTS_H__
/* ---------------------------------------------------------------- */
/*! axis-related values
*/
#define ML_NUM_AXES 6
/*! coil-related values
*/
#define ML_NUM_COILS 6
/*! coil current (amplifier current) range
*/
#define ML_CURRENT_RANGE 3.5 /*!< coil current min/max values are +/- this value */
#define ML_CURRENT_MIN -3.5 /*!< max negative current default */
#define ML_CURRENT_MAX 3.5 /*!< max positive current default */
/*! coil temperature range
*/
#define ML_TEMP_MIN 0.0 /*!< minimum in-range coil temperature default */
#define ML_TEMP_MAX 250.0 /*!< maximum in-range coil temperature default */
/*! Default servo interval (Hz)
*/
#define ML_SERVO_INTERVAL_DEFAULT 1000.0 /*!< default servo interval (1 KHz) */
#define ML_SERVO_INTERVAL_MIN 100.0 /*!< minimum servo interval (100 Hz) */
#define ML_SERVO_INTERVAL_MAX 10000.0 /*!< maximum servo interval (10 KHz) */
/* ---------------------------------------------------------------- */
#endif /* __ML_CONSTANTS__H__ */
|
n-fallahinia/UoU_Genral_Class | include/Images.h | #ifndef IMAGES_H
#define IMAGES_H
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
class Images
{
public:
int cols;
int rows;
int inc;
// int num;
// int max_num;
Images();
Images(int, int, int );
Images(int, int, int, unsigned char *);
Images(Images *);
~Images();
void readImage(unsigned char *);
void writeImage(int, int, int, unsigned char *);
void writeImage(unsigned char *);
private:
unsigned char *data;
};
// Write the data array as a PPM image file
inline bool ppm_write(char *filename, int width, int height, unsigned char* data)
{
// Declare the variables
int num;
int size = width * height * 3;
// Attempt to open the file for writing
FILE *fp = fopen(filename, "wb");
if (!fp)
{
printf("Cannot open file %s for writing\n",filename);
exit(0);
}
// Write the first lines that declare the file to be a PPM
fprintf(fp, "P6\n%d %d\n%d\n", width, height, 255);
// Write the entire array
num = (int) fwrite((void *) data, 1, size, fp);
// Close the file
fclose(fp);
// Determine if the fwrite command wrote the correct number of points
if (num == size)
{
return(true);
}
else
{
return(false);
}
} // ppm_write
#endif
|
n-fallahinia/UoU_Genral_Class | include/maglev/ml_api_callback.h | /*! \file ml_api_callback.h
\brief This is a header file for ml_api_callback.c, which implements the callback api for the Magnetic Levitation Haptic Interface API.
\author <NAME>
\date Created: Apr 19, 2007 \n Last Revision: Apr 25, 2007
<B>Supervisor:</B> \n
Dr. <NAME> \n\n
<B>Location:</B> \n
Carnegie Mellon University, Robotics Institute: \n
Microdynamic Systems Laboratory \n
*/
#ifndef _MLHI_API_CALLBACK_H_
#define _ML_API_CALLBACK_H_
// rpc implementation
#include <rpc/rpc.h>
#include <netinet/in.h>
#include "ml_error.h" // MLHI API error codes
#include "ml_constants.h" // MLHI API custom constants
//#include "ml_types.h" // MLHI API custom types
#include "ml_api_common.h" // MLHI common non-RPC types
// ---- CLIENT-side functions ----
extern int _ml_RegisterCallbackServerWithServer(ml_device_handle_t dev_hdl,
ml_callback_server_info_t & callback_server_info);
extern int _ml_UnregisterCallbackServerWithServer(ml_device_handle_t dev_hdl,
ml_callback_server_info_t & callback_server_info);
extern int _ml_RegisterCallbackWithServer(ml_device_handle_t dev_hdl,
ml_callback_type_t callback_type,
void (*callback_func)(void));
extern int _ml_UnregisterCallbackWithServer(ml_device_handle_t dev_hdl,
ml_callback_type_t callback_type);
// ---- SERVER-side functions ----
extern int _ml_RegisterRemoteCallbackServer(in_addr_t ip_addr,
char * host_name,
ml_callback_server_info_t * csip,
CLIENT * client_hdl);
extern int _ml_UnregisterRemoteCallbackServer(in_addr_t ip_addr,
char * host_name,
ml_callback_server_info_t * csip,
CLIENT ** client_hdl_p);
extern int _ml_RegisterRemoteCallback(in_addr_t ip_addr,
char * host_name,
ml_callback_info_t * cip);
extern int _ml_UnregisterRemoteCallback(in_addr_t ip_addr,
char * host_name,
ml_callback_info_t * cip);
#endif // _ML_API_CALLBACK_H_
|
n-fallahinia/UoU_Genral_Class | include/maglev/ml_api_common.h | <filename>include/maglev/ml_api_common.h
/*! \file ml_api_common.h
\brief This header file defines MLHI-specific common data types
which are used by both RPC/client software and server-side software.
\author <NAME>
\date Created: May 15, 2007
<B>Location:</B> \n
Carnegie Mellon University, Robotics Institute: \n
Microdynamic Systems Laboratory \n
*/
#ifndef __ML_API_COMMON_H__
#define __ML_API_COMMON_H__
#include "ml_types.h"
/*! generic function pointer */
typedef void (*generic_func_t)(void);
// forward declarations to enable mutual dependence of data structures
struct ml_device_t;
typedef ml_device_t *ml_device_handle_t;
struct ml_button_t;
struct ml_boundary_violation_t;
struct ml_fault_t;
struct ml_button_t;
struct ml_temps_t;
struct ml_position_t;
struct ml_forces_t;
/* Add Callback Step #1: Add a callback function declaration here. */
/*! function prototype for button state change callback */
typedef int (*button_state_callback_func_t)(ml_device_handle_t, ml_button_t);
/*! function prototype for boundary violation callback */
typedef int (*boundary_callback_func_t)(ml_device_handle_t, ml_boundary_violation_t *);
/*! function prototype for coil overtemperature callback */
typedef int (*coil_overtemp_callback_func_t)(ml_device_handle_t, ml_temps_t *);
/*! function prototype for fault state change callback */
typedef int (*fault_callback_func_t)(ml_device_handle_t, ml_fault_t);
/*! function prototype for tick callback */
typedef int (*tick_callback_func_t)(ml_device_handle_t, ml_position_t *);
typedef int (*control_loop_func_t)(ml_device_handle_t, ml_position_t pos, ml_forces_t force);
#endif // __ML_API_COMMON_H__
|
n-fallahinia/UoU_Genral_Class | include/WorkspacePlot.h | // Class definition for WorkspacePlot class
//
// Written by <NAME>
// 24 June 2014
// University of Utah
// Biorobotics Lab
#ifndef WORKSPACEPLOT_H
#define WORKSPACEPLOT_H
#include <FL/Fl_Gl_Window.H>
#include <vector>
// Still need to add a bar on the side to better indicate the z-position
class WorkspacePlot : public Fl_Gl_Window
{
private:
/////////////////////////////////////////////////
// Variables
// Click-and-drag variables
int click_x, click_y;
double vx, vy, vz;
// Scaling values for position and rotation
float scale_position;
// Width and height scaling variables
int window_width, axis_end;
// Font variables
void *font;
// Position (x,y,z) of the current axes (axis) and the base axes (base)
float axis_pose[3];
float base_pose[3];
// Colors for each region and the base axes
float pos_axis_color[3];
float neg_axis_color[3];
float zer_axis_color[3];
float base_color[3];
// Line width of the current axes (axis) and the base axes (base)
float axis_size;
float base_size;
/////////////////////////////////////////////////
// Functions
// Draw the axes
void draw3DAxis();
// Draw a single axis
void drawAxes(float pose[3], float color[3], float size, bool base_frame);
public:
/////////////////////////////////////////////////
// Variables
/////////////////////////////////////////////////
// Functions
// Constructor
WorkspacePlot(int x, int y, int w, int h, const char *l=0);
// Draw the window
void draw();
// Update the axis values
void set3DAxis(double pose[3]);
void set3DAxis(float pose[3]);
void set3DAxis(std::vector<double> pose);
void set3DAxis(std::vector<float> pose);
void set_axis(double pose, int axisIdx);
void set_axis(float pose, int axisIdx);
// Retrieve the position offset values
//void get_offset(double position[3]) const;
// Handling idle-time and other events
//bool idle();
//int handle(int event);
//bool erase_box();
};
#endif
|
n-fallahinia/UoU_Genral_Class | include/TimePlot.h | <reponame>n-fallahinia/UoU_Genral_Class
// Plot 2D data with OpenGL
// It allows subplots in one window
// It allows multiple curves in one plot
// For each plot, the input is x, y[n], data_num, data_dim, title, xlable, ylabel
// It has options to show connected lines, dots only, or dots and lines
#ifndef TIMEPLOT_H
#define TIMEPLOT_H
#include <FL/Fl_Gl_Window.H>
#include <queue>
// Set up a data structure to hold a single reading
struct ReadingDisplay
{
double data;
double data_x;
};
class TimePlot : public Fl_Gl_Window
{
public:
///////////////////////////////////////////////////////////////////////////////////////////
// Variables
// Number of points actually in the queue, does not appear to be initialized
int data_size, desired_size;
// Maximum number of data points allowed
//unsigned int max_size;
///////////////////////////////////////////////////////////////////////////////////////////
// Functions
// Constructor
TimePlot(int x,int y,int w,int h,const char *l=0);
// Add the data in curr_force to the queue for display
void readData(float* current_position);
void readDesiredData(float* desired_position);
// Empty the current data queue & desired data vector
void clear_data();
void clear_desired();
// Redraws the widget
void draw();
private:
///////////////////////////////////////////////////////////////////////////////////////////
// Variables
// Desired data points for plotting
std::vector<ReadingDisplay> desired_data;
// Actual data points for plotting
std::queue<ReadingDisplay> data_display;
// Figure size variables, used to determine size of text and lines
// Set as fixed numbers
float width, height;
// Character array containing a string to display before the experiment begins
char instruction_string[200];
// Stores title, xlabel and ylabel for the figure
char title[200];
char xlabel[200];
char ylabel[200];
// Colors for plotting data
float desired_color[3];
float data_color[3];
float line_color[3];
// Scale and offset values for plotting
float x_scale, y_scale, x_offset, y_offset;
///////////////////////////////////////////////////////////////////////////////////////////
// Functions
// Draws the data
void drawData(int, int);
void drawDesired(int, int);
// Draws the title, xlabel and ylabel on the plot
void drawTitle();
void drawYLabel();
void drawXLabel();
// Draws the x-axis
void drawZeroLines();
// Draws the phrase used before the experiment begins
void drawInstruction();
};
#endif
|
n-fallahinia/UoU_Genral_Class | include/maglev/ml_types.h | <reponame>n-fallahinia/UoU_Genral_Class
/*! \file ml_types.h
\brief This header file contains the various non-standard types used by
the ml_ API layer and ml_ communication layer code.
\author <NAME>
\date Created: July 2, 2006
\author <NAME>
\date Created: Feb 1, 2007
\author <NAME>
\date Modified: Nov 26, 2007
<B>Location:</B> \n
Carnegie Mellon University, Robotics Institute: \n
Microdynamic Systems Laboratory \n
*/
#ifndef __ML_TYPES_H__
#define __ML_TYPES_H__
#ifdef WIN32
#include <Windows.h>
#include <winsock.h>
#else
#include <netinet/in.h>
#include <pthread.h>
#endif
#ifdef WIN32
typedef struct in_addr in_addr;
#define true 1
#define false 0
#endif
#ifdef __cplusplus
extern "C"{
#endif
//****************** BEGIN FORWARD DECLARATIONS **********************//
struct ml_device_t;
struct ml_button_t;
struct ml_boundary_violation_t;
struct ml_float6_t;
struct ml_position_t;
struct ml_fault_t;
typedef struct ml_float6_t ml_float6_t;
/*! vector of per-axis (6) temperatures */
typedef struct ml_float6_t ml_temps_t;
/*! typedef for 3 forces (N) and 3 torques (Nm) */
typedef struct ml_float6_t ml_forces_t;
typedef struct ml_device_t *ml_device_handle_t;
typedef struct ml_button_t ml_button_t;
//****************** END FORWARD DECLARATIONS **********************//
//****************** BEGIN CALLBACK FUNCTIONS **********************//
/*! generic function pointer */
typedef void (*generic_func_t)(void);
/* Add Callback Step #1: Add a callback function declaration here. */
/*! function prototype for button state change callback */
typedef int (*button_state_callback_func_t)(ml_device_handle_t dev_hdl, ml_button_t button);
/*! function prototype for boundary violation callback */
typedef int (*boundary_callback_func_t)(ml_device_handle_t, struct ml_boundary_violation_t *);
/*! function prototype for coil overtemperature callback */
typedef int (*coil_overtemp_callback_func_t)(ml_device_handle_t, ml_temps_t *);
/*! function prototype for fault state change callback */
typedef int (*fault_callback_func_t)(ml_device_handle_t, struct ml_fault_t);
/*! function prototype for tick callback */
typedef int (*tick_callback_func_t)(ml_device_handle_t, struct ml_position_t *);
//****************** END CALLBACK FUNCTIONS **********************//
/*! transient, client handle to MLHI device, returned by ml_Connect() */
// maglev api is designed such that
// 1. a client program can communicate with multiple servers simultaneously
// 2. more than one threads from the same client program cannot communicate with the same server simultanouesly
// 3. more than one client programs can communicate with the same server simultaneously
typedef struct ml_device_t
{
struct in_addr server_addr; /*< address of the server connected as in_addr */
int socket_ml_func; /*< socket used for calling server functions */
int socket_ml_callback; /*< socket used for invoking callbacks */
#ifdef WIN32
HANDLE callback_thread_id; /*< handle for callback thread */
HANDLE callback_thread_mutex; /*< used to wait for the callback thread to exit */
HANDLE comm_mutex; /*< used to avoid multiple threads talking to the same server simultaneously */
#else
pthread_mutex_t comm_mutex; /*< used to avoid multiple clients talking to the same server simultaneously */
pthread_t callback_thread_id; /*< handle for callback thread */
#endif
button_state_callback_func_t button_state_callback_func; /*< pointer to button callback handler function */
boundary_callback_func_t boundary_callback_func; /*< pointer to boundary callback handler function */
coil_overtemp_callback_func_t coil_overtemp_callback_func; /*< pointer to coil overtemp callback handler function */
fault_callback_func_t fault_callback_func; /*< pointer to fault callback handler function */
tick_callback_func_t tick_callback_func; /*< pointer to tick callback handler function */
};
//typedef struct ml_device_t ml_device_t;
/*! Enumeration capable of representing each of the valid fault types.
Note that they increase by a factor of two like 1,2,4,8....
*/
enum ml_fault_type_t
{
ML_FAULT_TYPE_CLEAR=0, /*!< Fault condition CLEARED */
ML_FAULT_TYPE_SENSOR_OUT_OF_RANGE=1, /*!< Fault: position sensor has no result */
ML_FAULT_TYPE_COIL_OVERTEMP=2, /*!< Fault: temperature model for one or more coils is high */
ML_FAULT_TYPE_COIL_OVERCURRENT=4, /*!< Fault: total current running on one or more coils over some period is high (approximately 2A on average over 1 minute) */
ML_FAULT_TYPE_FLOTOR_OVERSPEED=8 /*!< Fault: speed of the flotor is high */
};
/*! Enumeration capable of representing each of the valid callback types.
*/
enum ml_callback_type_t
{
ML_CALLBACK_TYPE_BUTTON_CHANGED=0, /*!< one or more buttons changed position */
ML_CALLBACK_TYPE_BOUNDARY, /*!< flotor position has violated the spherical boundary */
ML_CALLBACK_TYPE_COIL_OVERTEMP, /*!< a coil's temperature model indicates over-temperature */
ML_CALLBACK_TYPE_FAULT, /*!< controller fault state has changed */
ML_CALLBACK_TYPE_TICK, /*!< controller servo interval (tick) has started */
ML_CALLBACK_TYPE_SHUTDOWNCLIENT, /*!< internal command used to shut down client callback thread */
ML_CALLBACK_TYPE_SHUTDOWN /*!< internal command used to shut down event monitor */
};
/*! Enumeration capable of representing each of the valid axis modes.
When the MLHI device is in normal operation, each of the six
flotor axis is in one of the legal axis modes: normal, locked, or
constrained.
*/
enum ml_axis_mode_t
{
ML_AXIS_MODE_NORMAL, /*!< Axis position is under normal PID control */
ML_AXIS_MODE_LOCKED, /*!< Axis position is locked to a specific position */
ML_AXIS_MODE_CONSTRAINED, /*!< Axis position is constrained between lower and upper values */
ML_AXIS_MODE_BOUNDARY /*!< Internal use only */
};
/*! Enumeration capable of representing each of the valid gain set types. A gainset is a complete set of PID controller parameters, including Kp, Ki, and Kd gains and feedforward force term, for each of the six flotor axes.
*/
enum ml_gainset_type_t
{
ML_GAINSET_TYPE_NORMAL = 0, /*!< Designates the set of gains for normal (PID control) axis mode */
ML_GAINSET_TYPE_LOCKED, /*!< Designates the set of gains used for a locked axis */
ML_GAINSET_TYPE_CONSTRAINED, /*!< Designates the set of gains used outside constraints */
ML_GAINSET_TYPE_BOUNDARY /*!< Designates the set of gains used to determine boundary forces */
};
typedef enum ml_gainset_type_t ml_gainset_type_t;
/*! Enumeration defining symbolic constants to name individual axes. Any API call specifying a specific axis takes a simple integer parameter to designate the desired axis. This enumeration allows axes to be designated with symbolic names.
*/
enum ml_axis_index_t
{
ML_AXIS_0 = 0, /*!< "X position" Axis - Axis #0 */
ML_AXIS_X = ML_AXIS_0, /*!< (Alias for "X position" Axis - Axis #0) */
ML_AXIS_X_POS = ML_AXIS_0, /*!< (Alias for "X position" Axis - Axis #0)\n */
ML_AXIS_1 = 1, /*!< "Y position" Axis - Axis #1 */
ML_AXIS_Y = ML_AXIS_1, /*!< (Alias for "Y position" Axis - Axis #1) */
ML_AXIS_Y_POS = ML_AXIS_1, /*!< (Alias for "Y position" Axis - Axis #1)\n */
ML_AXIS_2 = 2, /*!< "Z position" Axis - Axis #2 */
ML_AXIS_Z = ML_AXIS_2, /*!< (Alias for "Z position" Axis - Axis #2) */
ML_AXIS_Z_POS = ML_AXIS_2, /*!< (Alias for "Z position" Axis - Axis #2)\n */
ML_AXIS_3 = 3, /*!< "X rotation" Axis - Axis #3 */
ML_AXIS_X_ROT = ML_AXIS_3, /*!< (Alias for "X rotation" Axis - Axis #3) */
ML_AXIS_PITCH = ML_AXIS_3, /*!< (Alias for "X rotation" Axis - Axis #3)\n */
ML_AXIS_4 = 4, /*!< "Y rotation" Axis - Axis #4 */
ML_AXIS_Y_ROT = ML_AXIS_4, /*!< (Alias for "Y rotation" Axis - Axis #4) */
ML_AXIS_ROLL = ML_AXIS_4, /*!< (Alias for "Y rotation" Axis - Axis #4)\n */
ML_AXIS_5 = 5, /*!< "Z rotation" Axis - Axis #5 */
ML_AXIS_Z_ROT = ML_AXIS_5, /*!< (Alias for "Z rotation" Axis - Axis #5) */
ML_AXIS_YAW = ML_AXIS_5, /*!< (Alias for "Z rotation" Axis - Axis #5)\n */
ML_AXIS_GRASP /*!< "Grasp" Axis - Axis #6 */
};
typedef enum ml_axis_index_t ml_axis_index_t;
/*! Enumeration defining per-axis PID controller parameters (gains, etc.) */
enum ml_gain_type_t
{
ML_GAIN_TYPE_P=0, /*!< Designates proportional gain type: Kp */
ML_GAIN_TYPE_I, /*!< Designates integral gain type: Ki */
ML_GAIN_TYPE_D, /*!< Designates derivative gain type: Kd */
ML_GAIN_TYPE_FF /*!< Designates feedforward force type: FF */
};
typedef enum ml_gain_type_t ml_gain_type_t;
/*! Enumeration capable of representing each of the functions.
*/
enum ml_function_id_t
{
ML_FUNCTION_ID_CONNECT=0,
ML_FUNCTION_ID_CONSTRAINAXIS,
ML_FUNCTION_ID_DEFYGRAVITY,
ML_FUNCTION_ID_DISCONNECT,
ML_FUNCTION_ID_FINDGRAVITY,
ML_FUNCTION_ID_GETACTUALPOSITION,
ML_FUNCTION_ID_GETAXISMODES,
ML_FUNCTION_ID_GETBOUNDARYRADIUS,
ML_FUNCTION_ID_GETBUTTONSTATUS,
ML_FUNCTION_ID_GETCELLPOSITION,
ML_FUNCTION_ID_GETCURRENTLIMITS,
ML_FUNCTION_ID_GETCURRENTS,
ML_FUNCTION_ID_GETDESIREDPOSITION,
ML_FUNCTION_ID_GETESTOP,
ML_FUNCTION_ID_GETFAULT,
ML_FUNCTION_ID_GETFORCEAXIS,
ML_FUNCTION_ID_GETFORCES,
ML_FUNCTION_ID_GETFRAME,
ML_FUNCTION_ID_GETGAINVECAXES,
ML_FUNCTION_ID_GETGAINVECAXIS,
ML_FUNCTION_ID_GETGAINVECGRASP,
ML_FUNCTION_ID_GETGAINVECSINGLE,
ML_FUNCTION_ID_GETGRASPCURRENT,
ML_FUNCTION_ID_GETGRASPCURRENTLIMIT,
ML_FUNCTION_ID_GETGRAVITY,
ML_FUNCTION_ID_GETLATCELLLIMIT,
ML_FUNCTION_ID_GETLATCELLOFFSET,
ML_FUNCTION_ID_GETRAWCELLDATA,
ML_FUNCTION_ID_GETSERVOFREQUENCY,
ML_FUNCTION_ID_GETSPEEDLIMITS,
ML_FUNCTION_ID_GETTEMP,
ML_FUNCTION_ID_GETVELOCITY,
ML_FUNCTION_ID_GETVERSION,
ML_FUNCTION_ID_LAND,
ML_FUNCTION_ID_LOCKAXIS,
ML_FUNCTION_ID_RECORDVOLTAGES,
ML_FUNCTION_ID_REGISTERCALLBACKBUTTONPRESSED,
ML_FUNCTION_ID_REGISTERCALLBACKFAULT,
ML_FUNCTION_ID_REGISTERCALLBACKFLOTORBOUNDARYVIOLATION,
ML_FUNCTION_ID_REGISTERCALLBACKOVERTEMP,
ML_FUNCTION_ID_REGISTERCALLBACKTICK,
ML_FUNCTION_ID_RESETFAULT,
ML_FUNCTION_ID_RESETGAINVECAXES,
ML_FUNCTION_ID_SETAUXDAC,
ML_FUNCTION_ID_SETBOUNDARYRADIUS,
ML_FUNCTION_ID_SETCURRENTLIMITS,
ML_FUNCTION_ID_SETCURRENTS,
ML_FUNCTION_ID_SETDESIREDPOSITION,
ML_FUNCTION_ID_SETFORCEAXIS,
ML_FUNCTION_ID_SETFORCES,
ML_FUNCTION_ID_SETFRAME,
ML_FUNCTION_ID_SETGAINVECAXES,
ML_FUNCTION_ID_SETGAINVECAXIS,
ML_FUNCTION_ID_SETGAINVECGRASP,
ML_FUNCTION_ID_SETGAINVECSINGLE,
ML_FUNCTION_ID_SETGRASPCURRENT,
ML_FUNCTION_ID_SETGRASPCURRENTLIMIT,
ML_FUNCTION_ID_SETGRAVITY,
ML_FUNCTION_ID_SETLATCELLOFFSET,
ML_FUNCTION_ID_SETSERVOFREQUENCY,
ML_FUNCTION_ID_SETSPEEDLIMITS,
ML_FUNCTION_ID_SETVELOCITY,
ML_FUNCTION_ID_SHUTDOWN,
ML_FUNCTION_ID_TAKEOFF,
ML_FUNCTION_ID_UNLOCKAXIS,
ML_FUNCTION_ID_UNREGISTERCALLBACKBUTTONPRESSED,
ML_FUNCTION_ID_UNREGISTERCALLBACKFAULT,
ML_FUNCTION_ID_UNREGISTERCALLBACKFLOTORBOUNDARYVIOLATION,
ML_FUNCTION_ID_UNREGISTERCALLBACKOVERTEMP,
ML_FUNCTION_ID_UNREGISTERCALLBACKTICK,
ML_FUNCTION_ID_UPDATEPOSITION,
NON_ML_FUNCTION_ID_TERMINATECALLBACKTHREADCLIENT,
NON_ML_FUNCTION_ID_TERMINATECALLBACKTHREADSERVER,
NON_ML_FUNCTION_ID_MAPCALLBACKSOCKET,
NON_ML_FUNCTION_ID_CALLBACK_TYPE_BUTTON_CHANGED_HANDLER,
NON_ML_FUNCTION_ID_CALLBACK_TYPE_BOUNDARY_HANDLER,
NON_ML_FUNCTION_ID_CALLBACK_TYPE_COIL_OVERTEMP_HANDLER,
NON_ML_FUNCTION_ID_CALLBACK_TYPE_FAULT_HANDLER,
NON_ML_FUNCTION_ID_CALLBACK_TYPE_TICK_HANDLER,
NON_ML_FUNCTION_ID_CALLBACK_TYPE_SHUTDOWN /*!< internal command used to shut down event monitor */
};
typedef enum ml_function_id_t ml_function_id_t;
/* ---------- gain types ---------- */
/*! simple gain type */
typedef float ml_gain_t;
/*! set of gains (and other params) for simple PID */
struct ml_gain_pid_t
{
ml_gain_t p; /*!< proportional gain value: Kp */
ml_gain_t i; /*!< integral gain value: Ki */
ml_gain_t d; /*!< derivative gain value: Kd */
ml_gain_t ff; /*!< feedforward force value: FF */
};
typedef struct ml_gain_pid_t ml_gain_pid_t;
/*! Vector of per-axis (6) PID controller parameter structures */
struct ml_gain_vec_t
{
struct ml_gain_pid_t values[6]; /*!< per-axis gains */
};
typedef struct ml_gain_vec_t ml_gain_vec_t;
/* --------------------------------
* interactive type
* --------------------------------
*/
/*! struct for the status of the two buttons on the flotor's handle */
struct ml_button_t
{
int left; /*!< status of left button: if non-zero, button is depressed */
int right; /*!< status of right button: if non-zero, button is depressed */
};
//typedef struct ml_button_t ml_button_t;
/*! struct for the fault status of the device */
struct ml_fault_t
{
unsigned int value; /*!< bitmap indicating the fault status of the device */
};
/*! typedef for the status of the two buttons on the flotor's handle */
typedef struct ml_fault_t ml_fault_t;
/*! typedef for the coordination */
typedef float ml_coord_t;
/*! typedef for the temperature */
typedef float ml_temp_t;
/*! typedef for the force (N) or torque (Nm) */
typedef float ml_force_t;
/*! struct for flotor's world coordinate position */
struct ml_position_t
{
int isOutOfRange; /*!< if true, cartesian position is outside legal flotor envelope */
float values[6]; /*!< array of per-axis values */
};
/*! typedef for flotor's world coordinate position */
typedef struct ml_position_t ml_position_t;
struct ml_boundary_violation_t
{
int values[7];
};
typedef struct ml_boundary_violation_t ml_boundary_violation_t;
/*! generic struct with 6 float array in it */
typedef struct ml_float6_t
{
float values[6]; /*!< array of per-axis values */
} ml_float6_6;
/*! typedef for velocities on x, y, z, and on the angle of x, y, z */
typedef struct ml_float6_t ml_velocities_t;
/*! struct containing 6 ml_axis_mode_t's */
struct ml_axis_mode_vec_t
{
enum ml_axis_mode_t axis_mode[6]; /*!< array of per-axis axis modes */
};
typedef struct ml_axis_mode_vec_t ml_axis_mode_vec_t;
/*! typedef for ml_axis_mode_vec_t
typedef struct ml_axis_mode_vec_t ml_axis_mode_vec_t;
/* -------------- hardware type ---------------- */
/*! struct for sensor position */
struct ml_sensor_t
{
float x; /*!< sensor calculated x coordinate */
float y; /*!< sensor calculated y coordinate */
int isValid; /*!< if true, sensor x/y coord can be trusted */
};
/*! typedef for sensor position */
typedef struct ml_sensor_t ml_sensor_t;
/*! struct for sensor position */
struct ml_sensor_offset_t
{
float x; /*!< sensor offset, x coordinate */
float y; /*!< sensor offset, y coordinate */
float t; /*!< sensor offset, rotation in xy plane */
};
/*! typedef for sensor offset */
typedef struct ml_sensor_offset_t ml_sensor_offset_t;
/*! struct for 3 sensors' raw data, to store 12 voltages */
struct ml_sensor_raw_data_t
{
float values[12]; /*!< 12 raw values from 3 optical position sensing devices (PSD's) */
};
/*! typedef for sensors' raw data */
typedef struct ml_sensor_raw_data_t ml_sensor_raw_data_t;
/*! typedef for the current, in ampere */
typedef float ml_current_t;
/*! typedef for the currents of 6 coils, in ampere */
typedef struct ml_float6_t ml_currents_t;
#ifdef __cplusplus
}
#endif
#endif /* __ML_TYPES__H__ */
|
n-fallahinia/UoU_Genral_Class | include/maglev/ml_serialization.h | #ifndef __ML_SERIALIZATION__
#define __ML_SERIALIZATION__
#include "ml_api.h"
// use int32_t as the standard int for communication
#ifdef WIN32
typedef int ml_int_t;
typedef unsigned int ml_uint_t;
#else
typedef int32_t ml_int_t;
typedef uint32_t ml_uint_t;
#endif
#ifdef __cplusplus
extern "C"{
#endif
static const int sizeof_ml_int_t = sizeof(ml_int_t);
static const int sizeof_ml_uint_t = sizeof(ml_uint_t);
// -------------- BEGIN handle primitive data types ----------------- //
int serialize_float(char* const serialized_data, const float* const raw_data);
int deserialize_float(const char* const serialized_data, float* const deserialized_data);
int serialize_int(char* const serialized_data, const int* const raw_data);
int deserialize_int(const char* const serialized_data, int* const deserialized_data);
int serialize_uint(char* const serialized_data, const unsigned int* const raw_data);
int deserialize_uint(const char* const serialized_data, unsigned int* const deserialized_data);
int serialize_ints(char* const serialized_data, const int* const raw_data, int num_ints);
int deserialize_ints(const char* const serialized_data, int* const deserialized_data, int num_ints);
int serialize_bool(char*const serialized_data, const int* const raw_data);
int deserialize_bool(const char* const serialized_data, int* const deserialized_data);
// -------------- END handle primitive data types ----------------- //
// -------------- BEGIN handle ml_* data types ----------------- //
int deserialize_ml_gain_pid_t(const char* const serialized_data, ml_gain_pid_t* const deserialized_data);
int serialize_ml_gain_pid_t(char* const serialized_data, const ml_gain_pid_t* const raw_data);
int deserialize_ml_gain_vec_t(const char* const serialized_data, ml_gain_vec_t* const deserialized_data);
int serialize_ml_gain_vec_t(char* const serialized_data, const ml_gain_vec_t* const raw_data);
int deserialize_ml_button_t(const char* const serialized_data, ml_button_t * deserialized_data);
int serialize_ml_button_t(char* serialized_data, const ml_button_t* const raw_data);
int deserialize_ml_position_t(const char* const serialized_data, ml_position_t* const deserialized_data);
int serialize_ml_position_t(char* const serialized_data, const ml_position_t* const raw_data);
int deserialize_ml_float6_t(const char* const serialized_data, ml_float6_t * deserialized_data);
int serialize_ml_float6_t(char* serialized_data, const ml_float6_t* const raw_data);
int deserialize_ml_axis_mode_vec_t(const char* const serialized_data, ml_axis_mode_vec_t * deserialized_data);
int serialize_ml_axis_mode_vec_t(char* serialized_data, const ml_axis_mode_vec_t* const raw_data);
int deserialize_ml_sensor_t(const char* const serialized_data, ml_sensor_t * deserialized_data);
int serialize_ml_sensor_t(char* serialized_data, const ml_sensor_t* const raw_data);
int deserialize_ml_sensor_raw_data_t(const char* const serialized_data, ml_sensor_raw_data_t * deserialized_data);
int serialize_ml_sensor_raw_data_t(char* serialized_data, const ml_sensor_raw_data_t* const raw_data);
int deserialize_ml_sensor_offset_t(const char* const serialized_data, ml_sensor_offset_t* deserialized_data);
int serialize_ml_sensor_offset_t(char* serialized_data, const ml_sensor_offset_t* const raw_data);
int deserialize_ml_boundary_violation_t(const char* const serialized_data, ml_boundary_violation_t* deserialized_data);
int serialize_ml_boundary_violation_t(char* serialized_data, const ml_boundary_violation_t* const raw_data);
// -------------- END handle ml_* data types ----------------- //
// -------------- BEGIN handle ml_* functions ----------------- //
int dealwith_function_argument_in(char* enc_data, ml_function_id_t ID_ML_FUNC, void* args);
int dealwith_function_argument_out(char* enc_data, ml_function_id_t ID_ML_FUNC, void* args);
// -------------- END handle ml_* functions ----------------- //
// -------------- BEGIN helper data types used for communication ----------------- //
struct ml_set_gain_vec_axes_t
{
ml_gainset_type_t gainset_type;
ml_gain_vec_t gains;
};
typedef struct ml_set_gain_vec_axes_t ml_set_gain_vec_axes_t;
struct ml_set_gain_vec_axis_t
{
ml_gainset_type_t gainset_type;
ml_axis_index_t axis;
ml_gain_pid_t gain;
};
typedef struct ml_set_gain_vec_axis_t ml_set_gain_vec_axis_t;
struct ml_get_gain_vec_axis_t
{
ml_gainset_type_t gainset_type;
ml_axis_index_t axis;
};
typedef struct ml_get_gain_vec_axis_t ml_get_gain_vec_axis_t;
struct ml_set_gain_vec_single_t
{
ml_gainset_type_t gainset_type;
ml_axis_index_t axis;
ml_gain_type_t gaintype;
ml_gain_t value;
};
typedef struct ml_set_gain_vec_single_t ml_set_gain_vec_single_t;
struct ml_get_gain_vec_single_t
{
ml_gainset_type_t gainset_type;
ml_axis_index_t axis;
ml_gain_type_t gaintype;
};
typedef struct ml_get_gain_vec_single_t ml_get_gain_vec_single_t;
struct ml_set_force_axis_t
{
ml_axis_index_t axis;
ml_force_t force;
};
typedef struct ml_set_force_axis_t ml_set_force_axis_t;
struct ml_constrain_axis_t
{
ml_axis_index_t axis;
ml_coord_t minpos;
ml_coord_t maxpos;
};
typedef struct ml_constrain_axis_t ml_constrain_axis_t;
struct ml_set_lat_cell_offset_t
{
ml_sensor_offset_t cells[3];
};
typedef struct ml_set_lat_cell_offset_t ml_set_lat_cell_offset_t;
struct ml_get_cell_position_t
{
ml_sensor_t cells[3];
};
typedef struct ml_get_cell_position_t ml_get_cell_position_t;
// -------------- END helper data types used for communication ----------------- //
#ifdef __cplusplus
}
#endif
#endif // __ML_SERIALIZATION__
|
n-fallahinia/UoU_Genral_Class | include/TimeHandler.h | <gh_stars>0
// All the functions that handle the timer
#ifndef TIMEHANDLER_H
#define TIMEHANDLER_H
#include <time.h>
class TimeHandler
{
private:
/////////////////////////////////////////////////
// Variables
// Number of clicks in one second
long long int current_clicks;
// Number of nanoseconds in one second
unsigned long long int nanoseconds;
// A timespec structure that will be set up to hold exactly 1 second
timespec one_second;
// Define the CPU core to use for tracking the time
int my_cpu;
// Initial time
double time_start;
/////////////////////////////////////////////////
// Functions
// Collects the time (in nanoseconds) from the CPU
inline unsigned long long int hpet_time();
// Determines the number of clicks in one second
inline long long int clicks_per_second();
public:
/////////////////////////////////////////////////
// Variables
/////////////////////////////////////////////////
// Functions
// Constructors
TimeHandler();
~TimeHandler();
// Retrieve the current time
double current_time();
// Resets the starting time
void reset_timer();
};
#endif
|
n-fallahinia/UoU_Genral_Class | include/BarPlot.h | <reponame>n-fallahinia/UoU_Genral_Class<filename>include/BarPlot.h
//
// "$Id: BarPlot.h 5519 2006-10-11 03:12:15Z mike $"
//
// BarPlot class definitions
//
// Created by <NAME>
// 12 June 2014
// University of Utah
// Biorobotics Lab
//
// Based on CubeView for the Fast Light Tool Kit (FLTK).
//
// Copyright 1998-2005 by <NAME> and others.
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Library General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Library General Public License for more details.
//
// You should have received a copy of the GNU Library General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
// USA.
//
// Please report all bugs and problems on the following page:
//
// http://www.fltk.org/str.php
//
#ifndef BARPLOT_H
#define BARPLOT_H 1
#include <FL/Fl_Gl_Window.H>
#include <vector>
#include <string>
class BarPlot : public Fl_Gl_Window
{
public:
//////////////////////////////////////////
// Variables
// Determines whether the display is active or not
bool flag_force_display;
////////////////////////////////////////////
// Functions
BarPlot(int x,int y,int w,int h,const char *l=0);
// Set the height of a given bar
void set_height(int dirIdx, double height);
// Set the height of all bars
void set_heights(double* heights);
// The widget class draw() override.
void draw();
private:
//////////////////////////////////////////
// Variables
// Height of each bar
std::vector<double> bar_height;
// Names of force directions
std::vector<std::string> force_names;
std::vector<int> force_dirs;
// Title, y-label and x-label
char title[200];
char y_left[200];
char y_right[200];
char xlabel[200];
// Ranges to display
float min_left, max_left, min_right, max_right;
float scale_left, scale_right;
// Number of bars to display
int num_bars;
// Bar width
float bar_width;
// Slope of the bar function
double bar_slope;
// The barIdx of the halfway point
double half_bar;
// Maximum bar position
double max_bar, mid_bar;
// Desired bar level, used to draw a line across the plot
float desired_level;
// Coordinates for the 8 vertices of a unit cube
float boxv0[3];float boxv1[3];
float boxv2[3];float boxv3[3];
float boxv4[3];float boxv5[3];
float boxv6[3];float boxv7[3];
// Display font properties
Fl_Font font_type;
Fl_Fontsize font_size;
//////////////////////////////////////////
// Functions
// Draw the cube boundaries
void drawCube();
void draw_title();
void draw_ylabels();
void draw_force_dir(double height, float x_offset, char* my_label);
};
#endif
//
// End of "$Id: BarPlot.h 5519 2006-10-11 03:12:15Z mike $".
//
|
n-fallahinia/UoU_Genral_Class | include/main.h | <reponame>n-fallahinia/UoU_Genral_Class<filename>include/main.h
#ifndef MAIN_H
#define MAIN_H
#include "UserInterface.h"
#include "Constants.h"
#include "ml_api.h"
// Function definitions
double get_desired_position(double current_time);
void read_trajectory();
void display_force_reading(void * v);
void display_position_reading(void * v);
int tick_callback_handler(ml_device_handle_t maglev_handle, ml_position_t *maglev_position);
#endif
|
n-fallahinia/UoU_Genral_Class | include/maglev/ml_error.h | /*! \file ml_error.h
\brief This header file defines the error codes used by the MLHI.
\author <NAME>
\date Created: July 6, 2005 \n Last Revision: July 14, 2005
<B>Supervisor:</B> \n
Dr. <NAME> \n\n
<B>Location:</B> \n
Carnegie Mellon University, Robotics Institute: \n
Microdynamic Systems Laboratory \n
*/
#ifndef _ML_ERROR_H_
#define _ML_ERROR_H_
#ifdef __cplusplus
extern "C"{
#endif
#define ML_STATUS_OK 0x0000 /*!< SUCCESS - no error */
// DATA ERRORS
#define ML_STATUS_DATA_GAIN_OUT_OF_RANGE 0x0001 /*!< requested gain value is outside maximum limits */
#define ML_STATUS_DATA_GAIN_FORMAT 0x0002 /*!< data is not in the desired format */
#define ML_STATUS_DATA_GAIN_INVALID_TYPE 0x0003 /*!< ?? */
#define ML_STATUS_DATA_AXIS_INVALID 0x0004 /*!< Axis is out of range - must be between 0 and 5 */
#define ML_STATUS_DATA_POS_OUT_OF_RANGE 0x0005 /*!< The requested position value for one or more axes are outside maximum limits */
#define ML_STATUS_DATA_FORCE_OUT_OF_RANGE 0x0006 /*!< The requested force values for one or more axes are outside maximum limits */
#define ML_STATUS_DATA_CURRENT_OUT_OF_RANGE 0x0007 /*!< The requested current values for one or more axes are outside maximum limits */
#define ML_STATUS_DATA_TIME_OUT_OF_RANGE 0x0008 /*!< The requested time value is outside maximum limits */
#define ML_STATUS_INVALID_DEVICE_HANDLE 0x0009 /*!< */
#define ML_STATUS_DATA_SPEED_OUT_OF_RANGE 0x000a /*!< speed must be non negative */
#define ML_STATUS_NULL_POINTER 0x000f /*!< A pointer parameter has a null value, and does not point to a valid parameter */
// COMMUNICATION ERRORS
#define ML_STATUS_COMM_CONNECTION 0x0010 /*!< A network communication problem has occurred */
#define ML_STATUS_COMM_DUPLICATE_COMMAND 0x0020
#define ML_STATUS_COMM_RECVONLY_MODE 0x0030
#define ML_STATUS_COMM_DUPLICATE_QUEUE 0x0040
#define ML_STATUS_COMM_NOT_QUEUEING 0x0050
// Resource errors
#define ML_STATUS_MEMORY_EXHAUSTED 0x0060 /*!< internal controller error - unable to allocate memory */
#define ML_STATUS_THREAD_ERROR 0x0061 /*!< unable to start a thread */
#define ML_STATUS_BLOCK_MATCH_ERROR 0x0062 /*!< A previously registered entity does not match any new request */
// Hardware / Flotor errors
#define ML_STATUS_FLOTOR_LANDED 0x0100
#define ML_STATUS_FLOTOR_TAKEN_OFF 0x0200
#define ML_STATUS_FLOTOR_OFFLINE 0x0300
#define ML_STATUS_FLOTOR_OVERHEAT 0x0400
//MLHI controller internal errors
#define ML_STATUS_MLHI_INT_TIMER 0x0800 /*!< internal error - timer cannot be set or started */
#define ML_STATUS_MLHI_REPLACE 0x0801 /*!< internal notification - new entity has overwritten a prior, old entity */
#ifdef __cplusplus
}
#endif
#endif
|
n-fallahinia/UoU_Genral_Class | include/ForceSensor.h | //This is a class to handle force sensor
//It start a force sensor, read it with a certain of frequency
//The reading is stored in a queue.
#ifndef FORCESENSOR_H
#define FORCESENSOR_H
#include <comedilib.h>
// Define a structure to hold a single force reading
struct Reading
{
double raw_force_signal[6];
double force[6];
};
// Define the class to hold all information relating to the force sensor
class ForceSensor
{
public:
/////////////////////////////////////////////////
// Variables
Reading curr_force;
/////////////////////////////////////////////////
// Functions
// Constructor/Destructor
ForceSensor();
~ForceSensor();
// Indicates that the sensor is turned on
bool enabled();
// Retrieve a new force reading
void read();
// Initialize the force sensor
bool connect();
private:
/////////////////////////////////////////////////
// Variables
// Handle for interacting with the Sensoray 626 card
comedi_t *device;
// References to the on-card devices for input and output
int analog_input, analog_output;
// Number of analog inputs and outputs on the card
int num_inputs, num_outputs;
// Channel range used to read the force sensor
int channel_start, channel_end;
// Name of the Sensoray 626 card according to the OS
char device_name[20];
// Stores the 'tare' for the force
double force_tare[6];
// Indicates the sensor is turned on
bool sensor_on;
/////////////////////////////////////////////////
// Functions
// Calculate the 'tare'
void calculate_tare();
// Read the raw voltage signals from the Sensoray
inline void read_voltage();
// Convert the voltage reading to a force reading
inline void convert_voltage();
// Apply the 'tare' to the input_force
inline void apply_tare();
};
#endif
|
turesnake/tprPixelGames | src/innTest/innTest.h | /*
* ======================== innTest.h ==========================
* -- tpr --
* CREATE -- 2020.01.01
* MODIFY --
* ----------------------------------------------------------
*/
#ifndef TPR_INN_TEST_H
#define TPR_INN_TEST_H
//=== *** glad FIRST, glfw SECEND *** ===
// Don't include glfw3.h ALONE!!!
#include<glad/glad.h>
#include<GLFW/glfw3.h>
namespace innTest {//---------- namespace: innTest --------------//
void innTest_main();
}//-------------------- namespace: innTest end --------------//
#endif
|
turesnake/tprPixelGames | src/Engine/tools/IntVec.h | <gh_stars>100-1000
/*
* ========================= IntVec.h ==========================
* -- tpr --
* CREATE -- 2018.11.28
* MODIFY --
* ----------------------------------------------------------
* 以像素为单位的 vec 向量。
* ----------------------------
*/
#ifndef TPR_PIX_VEC_H
#define TPR_PIX_VEC_H
//-------------------- CPP --------------------//
#include <cmath>
//-------------------- Engine --------------------//
#include "tprCast.h"
//--- [mem] --//
class IntVec2{
public:
IntVec2() = default;
IntVec2( int x_, int y_ ):
x(x_),
y(y_)
{}
IntVec2( size_t x_, size_t y_ ):
x(static_cast<int>(x_)),
y(static_cast<int>(y_))
{}
inline void clear_all() noexcept {
this->x = 0;
this->y = 0;
}
//--------
inline IntVec2& operator += ( IntVec2 a_ ) noexcept {
this->x += a_.x;
this->y += a_.y;
return *this;
}
inline IntVec2& operator -= ( IntVec2 a_ ) noexcept {
this->x -= a_.x;
this->y -= a_.y;
return *this;
}
inline IntVec2& operator *= ( int m_ ) noexcept {
this->x *= m_;
this->y *= m_;
return *this;
}
//-- 地板除法，向低取节点值 --
// -1- double 除法
// -2- math.floor()
inline IntVec2 floorDiv( double div_ ) const noexcept {
double fx = static_cast<double>(this->x) / div_;
double fy = static_cast<double>(this->y) / div_;
return IntVec2{ static_cast<int>(floor(fx)),
static_cast<int>(floor(fy)) };
}
//======== static ========//
static bool is_closeEnough( IntVec2 v1_, IntVec2 v2_, size_t off_ ) noexcept;
//======== vals ========//
int x {0};
int y {0};
};
//======= static =======//
// x/y 差值均小于 off_ 时，返回 true
inline bool IntVec2::is_closeEnough( IntVec2 v1_, IntVec2 v2_, size_t off_ ) noexcept {
size_t off_x = cast_2_size_t( std::abs( static_cast<double>(v1_.x-v2_.x) ) );
size_t off_y = cast_2_size_t( std::abs( static_cast<double>(v1_.y-v2_.y) ) );
// prevent std::abs ambiguous
return ( (off_x<off_) && (off_y<off_) );
}
// std::hash 特化
// IntVec2 可以成为 std::unordered_map / std::unordered_set 的 key
namespace std{
template<>
struct hash<IntVec2>{
hash()=default;
size_t operator()(IntVec2 iv_) const{
size_t key {};
int *ptr = (int*)(&key); //- can't use static_cast<>
*ptr = iv_.x;
ptr++;
*ptr = iv_.y;
//--------
return key;
}
};
}// namespace std
/* ===========================================================
* operator ==, !=
* -----------------------------------------------------------
*/
inline bool operator == ( IntVec2 a_, IntVec2 b_ ) noexcept {
return ( (a_.x==b_.x) && (a_.y==b_.y) );
}
inline bool operator != ( IntVec2 a_, IntVec2 b_ ) noexcept {
return ( (a_.x!=b_.x) || (a_.y!=b_.y) );
}
/* ===========================================================
* operator <
* -----------------------------------------------------------
* -- 通过这个 "<" 运算符重载，IntVec2 类型将支持 set.find()
* -- IntVec2 可以成为 std::map / std::set 的 key
*/
inline bool operator < ( IntVec2 a_, IntVec2 b_ ) noexcept {
if( a_.x == b_.x ){
return ( a_.y < b_.y );
}
return ( a_.x < b_.x );
}
/* ===========================================================
* operator +, -
* -----------------------------------------------------------
*/
inline IntVec2 operator + ( IntVec2 a_, IntVec2 b_ ) noexcept {
return IntVec2 { a_.x+b_.x, a_.y+b_.y };
}
inline IntVec2 operator - ( IntVec2 a_, IntVec2 b_ ) noexcept {
return IntVec2 { a_.x-b_.x, a_.y-b_.y };
}
/* ===========================================================
* operator *
* -----------------------------------------------------------
*/
inline IntVec2 operator * ( IntVec2 a_, int m_ ) noexcept {
return IntVec2 { a_.x*m_, a_.y*m_ };
}
inline IntVec2 operator * ( int m_, IntVec2 a_ ) noexcept {
return IntVec2 { a_.x*m_, a_.y*m_ };
}
/* ===========================================================
* floorDiv
* -----------------------------------------------------------
* -- 地板除运算 [通过 "double地板除"，解决了负数bug] --
* -1- double 除法
* -2- math.floor()
*/
inline IntVec2 floorDiv( IntVec2 a_, double div_ ) noexcept {
double fx = static_cast<double>(a_.x) / div_;
double fy = static_cast<double>(a_.y) / div_;
return IntVec2{ static_cast<int>(floor(fx)),
static_cast<int>(floor(fy)) };
}
/* ===========================================================
* floorMod
* -----------------------------------------------------------
* -- 取模运算 [通过 "double地板除"， 解决了负数bug] --
* -1- double 除法
* -2- math.floor()
*/
inline IntVec2 floorMod( IntVec2 v_, double mod_ ) noexcept {
double fx = ( static_cast<double>(v_.x) ) / mod_;
double fy = ( static_cast<double>(v_.y) ) / mod_;
double floorX = floor(fx) * mod_;
double floorY = floor(fy) * mod_;
return IntVec2{ v_.x - static_cast<int>(floor(floorX)),
v_.y - static_cast<int>(floor(floorY)) };
}
#endif
|
turesnake/tprPixelGames | src/Engine/gameObj/GoAltiRange.h | /*
* ========================= GoAltiRange.h ==========================
* -- tpr --
* CREATE -- 2019.01.05
* MODIFY --
* ----------------------------------------------------------
* go 高度区间, 不是 地图海拔，要和 Altitude 区分开来
* ----------------------------
*/
#ifndef TPR_ALTI_RANGE_H
#define TPR_ALTI_RANGE_H
//------------------- CPP --------------------//
#include <string>
#include <cstdint> // uint8_t
//------------------- Engine --------------------//
#include "tprAssert.h"
#include "tprMath.h"
// go 的高度区间
class GoAltiRange{
public:
//---- constructor -----//
GoAltiRange() = default;
GoAltiRange( double low_, double high_ ):
low(low_),
high(high_)
{ tprAssert(low <= high); }
inline void clear_all()noexcept{
low = 0.0;
high = 0.0;
}
inline void set( double low_, double high_ )noexcept{
tprAssert( low_ <= high_ );
low = low_;
high = high_;
}
inline bool is_collide( const GoAltiRange& a_ )const noexcept{
// 某个 碰撞体，高度间距几乎为0，直接判断不会发生碰撞
if( is_closeEnough<double>(this->low, this->high, 0.01) ||
is_closeEnough<double>(a_.low, a_.high, 0.01) ){
return false;
}
if( is_closeEnough<double>( low, a_.low, 0.01 ) ){
return true;
}else if( low < a_.low ){
return ((high>a_.low) ? true : false);
}else{
return ((a_.high>low) ? true : false);
}
}
//======== vals ========//
double low {0.0}; //- low <= high 其实相等是没有意义的，暂时保留
double high {0.0};
};
/* ===========================================================
* operator +, -
* -----------------------------------------------------------
*/
inline GoAltiRange operator + ( const GoAltiRange &a_, const GoAltiRange &b_ )noexcept{
return GoAltiRange{ a_.low + b_.low,
a_.high + b_.high };
}
inline GoAltiRange operator + ( const GoAltiRange &a_, double addAlti_ )noexcept{
return GoAltiRange{a_.low + addAlti_,
a_.high + addAlti_ };
}
/* ===========================================================
* is_GoAltiRange_collide
* -----------------------------------------------------------
*/
inline bool is_GoAltiRange_collide( const GoAltiRange& a_, const GoAltiRange& b_ )noexcept{
// 某个 碰撞体，高度间距几乎为0，直接判断不会发生碰撞
if( is_closeEnough<double>(a_.low, a_.high, 0.01) ||
is_closeEnough<double>(b_.low, b_.high, 0.01) ){
return false;
}
if( is_closeEnough<double>( a_.low, b_.low, 0.01 ) ){
return true;
}else if( a_.low < b_.low ){
return ((a_.high>b_.low) ? true : false);
}else{
return ((b_.high>a_.low) ? true : false);
}
}
// 一个 go数据中，可能有数个 不同的 GoAltiRange 数据
// 比如，大树小树 的高度
enum class GoAltiRangeLabel{
Default=0, // 只有一种时，推荐使用此值
// json 文件中，可以直接用 "" 表达
//---
Big,
Mid,
Sml,
};
GoAltiRangeLabel str_2_goAltiRangeLabel( const std::string &str_ )noexcept;
#endif
|
turesnake/tprPixelGames | src/Engine/multiThread/chunkCreate/Job_Field.h | /*
* ========================== Job_Field.h =======================
* -- tpr --
* CREATE -- 2019.10.08
* MODIFY --
* ----------------------------------------------------------
*/
#ifndef TPR_JOB_FIELD_H
#define TPR_JOB_FIELD_H
#include "pch.h"
//-------------------- Engine --------------------//
#include "Job_MapEnt.h"
#include "animSubspeciesId.h"
#include "mapEntKey.h"
#include "goLabelId.h"
#include "fieldFractType.h"
#include "GoDataForCreate.h"
// need:
class Job_Chunk;
// tmp data. created in job threads
class Job_Field{
// 按照规则将 mapents，合并为 halfField / Field
// 从而减少 go 的创建数量
template< typename T >
class Fract{
public:
Fract()
{
this->inHalfFields.resize( HALF_ENTS_PER_FIELD<size_t> * HALF_ENTS_PER_FIELD<size_t> );
}
inline void insert( IntVec2 mposOff_, const T &val_ )noexcept{
tprAssert( (mposOff_.x>=0) && (mposOff_.x<ENTS_PER_FIELD<>) &&
(mposOff_.y>=0) && (mposOff_.y<ENTS_PER_FIELD<>));
//--- field ---//
this->inField.insert(val_); // maybe
//--- halfField ---//
size_t hIdx = Fract::calc_halfFieldIdx(mposOff_);
tprAssert( this->inHalfFields.size() > hIdx );
this->inHalfFields.at(hIdx).insert(val_);
}
inline size_t get_inField_size()const noexcept{ return this->inField.size(); }
inline const std::set<T> &get_inField()const noexcept{ return this->inField; }
inline const std::vector<std::set<T>> &get_inHalfFields()const noexcept{ return this->inHalfFields; }
private:
inline static size_t calc_halfFieldIdx( IntVec2 mposOff_ )noexcept{
IntVec2 halfFieldPos = mposOff_.floorDiv( HALF_ENTS_PER_FIELD_D );
return cast_2_size_t( halfFieldPos.y * HALF_ENTS_PER_FIELD<> + halfFieldPos.x );
}
//========== vals ==========//
std::set<T> inField {};
std::vector<std::set<T>> inHalfFields {}; // 4 containers
// leftBottom, rightBottom, leftTop, rightTop
};
public:
//========== Self Vals ==========//
Job_Field( Job_Chunk &jChunkRef_, fieldKey_t fieldKey_ ):
fieldKey(fieldKey_)
{
//-- 二维数组 --
this->mapEntPtrs.resize( ENTS_PER_FIELD<size_t> ); // h
for( auto &c : this->mapEntPtrs ){
c.resize( ENTS_PER_FIELD<size_t> ); // w
}
}
// param: mposOff_ base on field.mpos
inline void insert_a_entInnPtr( IntVec2 mposOff_, Job_MapEnt *entPtr_ )noexcept{
tprAssert( (mposOff_.x>=0) && (mposOff_.x<ENTS_PER_FIELD<>) &&
(mposOff_.y>=0) && (mposOff_.y<ENTS_PER_FIELD<>));
//--- mapEntPtrs ---
this->mapEntPtrs.at(static_cast<size_t>(mposOff_.y)).at(static_cast<size_t>(mposOff_.x)) = entPtr_;
//--- is have border ent ---
if( entPtr_->get_isEcoBorder() && (!this->isHaveBorderEnt) ){
this->isHaveBorderEnt = true;
}
//--- ecoObjKey container ---
this->ecoObjKeys.insert( entPtr_->get_ecoObjKey() ); // maybe
colorTableIdFract.insert( mposOff_, entPtr_->get_colorTableId() );
bioSoupFract.insert( mposOff_, entPtr_->get_bioSoupState() );
}
void apply_bioSoupEnts();
void apply_groundGoEnts();
inline bool is_crossEcoObj()const noexcept{
return (this->ecoObjKeys.size() > 1);
}
inline bool is_crossColorTable()const noexcept{
return ( this->colorTableIdFract.get_inField_size() > 1 );
}
inline void insert_2_majorGoDataPtrs( const GoDataForCreate *ptr_ )noexcept{
this->majorGoDataPtrs.push_back( ptr_ );
}
inline void insert_2_floorGoDataPtrs( const GoDataForCreate *ptr_ )noexcept{
this->floorGoDataPtrs.push_back( ptr_ );
}
inline void insert_2_bioSoupGoDatas( std::unique_ptr<GoDataForCreate> uptr_ )noexcept{
this->bioSoupGoDatas.push_back( std::move(uptr_) );
}
inline const std::vector<const GoDataForCreate*> &get_majorGoDataPtrs()const noexcept{
return this->majorGoDataPtrs;
}
inline const std::vector<const GoDataForCreate*> &get_floorGoDataPtrs()const noexcept{
return this->floorGoDataPtrs;
}
inline const std::vector<const GoDataForCreate*> &get_bioSoupGoDataPtrs()const noexcept{
return this->bioSoupGoDataPtrs;
}
inline std::optional<const GoDataForCreate*> get_groundGoDataPtr()const noexcept{
if( this->groundGoData ){
return { this->groundGoData.get() };
}else{
return std::nullopt;
}
}
inline std::unordered_map<mapEntKey_t, std::unique_ptr<GoDataForCreate>> &get_nature_majorGoDatas()noexcept{
return this->nature_majorGoDatas;
}
inline std::unordered_map<mapEntKey_t, std::unique_ptr<GoDataForCreate>> &get_nature_floorGoDatas()noexcept{
return this->nature_floorGoDatas;
}
inline void copy_nature_majorGoDataPtrs()noexcept{
for( const auto &[iKey, iUPtr] : this->nature_majorGoDatas ){
this->majorGoDataPtrs.push_back( iUPtr.get() );
}
}
inline void copy_nature_floorGoDataPtrs()noexcept{
for( const auto &[iKey, iUPtr] : this->nature_floorGoDatas ){
this->floorGoDataPtrs.push_back( iUPtr.get() );
}
}
inline fieldKey_t get_fieldKey()const noexcept{ return this->fieldKey; }
inline bool get_isCoveredBy_InertiaBioSoup()const noexcept{ return this->isCoveredBy_InertiaBioSoup; }
inline IntVec2 get_fieldMidMPos()const noexcept{ return (fieldKey_2_mpos(this->fieldKey) + IntVec2{ HALF_ENTS_PER_FIELD<>, HALF_ENTS_PER_FIELD<> }); }
//===== static =====//
static void init_for_static()noexcept; // MUST CALL IN MAIN !!!
private:
void create_bioSoupDataUPtr( FieldFractType fieldFractType_,
IntVec2 mpos_,
gameObjs::bioSoup::State bioSoupState_,
MapAltitude mapEntAlti_ );
inline void copy_bioSoupGoDataPtrs()noexcept{
for( const auto &uptr : this->bioSoupGoDatas ){
this->bioSoupGoDataPtrs.push_back( uptr.get() );
}
}
// 同时包含 artifact/nature 两种蓝图数据
// 供 具象go类 访问，创建 go实例
std::vector<const GoDataForCreate*> majorGoDataPtrs {};
std::vector<const GoDataForCreate*> floorGoDataPtrs {};
std::vector<const GoDataForCreate*> bioSoupGoDataPtrs {};
// 人造物蓝图数据 实际存储区，不像人造物数据，被存储在 ecoobj 中
// 但是为了对外统一接口，还是会把 ptr 存储在一个容器中，以便具象类集中访问
std::unordered_map<mapEntKey_t, std::unique_ptr<GoDataForCreate>> nature_majorGoDatas {};
std::unordered_map<mapEntKey_t, std::unique_ptr<GoDataForCreate>> nature_floorGoDatas {};
// 临时方案，单独存储 bioSoup mp-go
std::vector<std::unique_ptr<GoDataForCreate>> bioSoupGoDatas {};
// 1个field，只能拥有一个 groundGo
// 如果本 field，被 Inertia-BioSoup 完全覆盖，则不会分配
std::unique_ptr<GoDataForCreate> groundGoData {};
//=== datas just used for inner calc ===
std::vector<std::vector<Job_MapEnt*>> mapEntPtrs {}; // 二维数组 [h,w]
//-- 在未来，元素type 会被改成 colorTableId_t ---
std::set<sectionKey_t> ecoObjKeys {};
Fract<gameObjs::bioSoup::State> bioSoupFract {};
Fract<colorTableId_t> colorTableIdFract {};
fieldKey_t fieldKey;
//===== flags =====//
bool isHaveBorderEnt {false}; //- 只要发现 border. 暂时无用
bool isCoveredBy_InertiaBioSoup {false};
// 若为 true，本 field 不再创建 groundGo, floorGo
};
#endif
|
turesnake/tprPixelGames | src/Engine/input/DirAxes.h | <reponame>turesnake/tprPixelGames
/*
* ========================= DirAxes.h ==========================
* -- tpr --
* CREATE -- 2019.05.12
* MODIFY --
* ----------------------------------------------------------
* InputINS 中 表达 方向的 数据
* 当数据源自 joystick 时，
* 值直接为 axis_0, axis_1
* 当数据源自 键盘
* 值被设置为 (-1.0, 0.0, 1.0) 三种之一
* ----------------------------
*/
#ifndef TPR_DIR_AXES_H
#define TPR_DIR_AXES_H
//--- glm - 0.9.9.5 ---
#include "glm_no_warnings.h"
//-------------------- CPP --------------------//
#include <cmath>
//-------------------- Engine --------------------//
#include "tprAssert.h"
#include "tprMath.h"
#include "NineDirection.h"
// 游戏世界 和 程序窗口， 存在 两套坐标系: world, origin
// 程序窗口 坐标系，是符合常规视觉的，直上直下的 坐标系，也对应 UI坐标系，对应 input坐标系
// 游戏世界 坐标系，则旋转了 30度
class DirAxes{
public:
DirAxes( double x_=0.0, double y_=0.0 )
{
this->innSet( x_, y_ );
}
explicit DirAxes( const glm::dvec2 &v_ )
{
this->innSet( v_.x, v_.y );
}
//inline void set( double x_, double y_ )noexcept{ this->innSet( x_, y_ ); }
//inline void set( const glm::dvec2 &v_ )noexcept{ this->innSet( v_.x, v_.y ); }
inline void clear_all()noexcept{
this->originVal = glm::dvec2{0.0, 0.0};
this->worldVal = glm::dvec2{0.0, 0.0};
}
inline const glm::dvec2 &get_worldVal()const noexcept{ return this->worldVal; }
inline const glm::dvec2 &get_originVal()const noexcept{ return this->originVal; }
// 0 代表 无方向。此时， worldVal 和 originVal 都会是 0，不矛盾
inline bool is_zero() const noexcept{
return is_closeEnough( this->worldVal, glm::dvec2{0.0, 0.0}, DirAxes::threshold );
}
//===== static =====//
static constexpr double threshold = 0.005; //- 阈值，[-0.01, 0.01] 区间的信号不识别
private:
inline void innSet( double x_, double y_ )noexcept{
//----------------//
// -1- 确保参数范围合法
//----------------//
tprAssert( (x_>=-1.0) && (x_<=1.0) &&
(y_>=-1.0) && (y_<=1.0) );
glm::dvec2 tmp { x_, y_ };
//----------------//
// -2- 检测死区
//----------------//
bool is_x_zero {false};
bool is_y_zero {false};
if( is_closeEnough<double>( tmp.x, 0.0, DirAxes::threshold ) ){
tmp.x = 0.0;
is_x_zero = true;
}
if( is_closeEnough<double>( tmp.y, 0.0, DirAxes::threshold ) ){
tmp.y = 0.0;
is_y_zero = true;
}
//----------------//
// -3- 转换为标准向量 存入 originVal
// -4- 旋转坐标系， 值存入 worldVal
//----------------//
if( !is_x_zero || !is_y_zero ){
this->limit_vals( tmp );
}else{
this->originVal = glm::dvec2{ 0.0, 0.0 };
this->worldVal = glm::dvec2{ 0.0, 0.0 };
}
}
void limit_vals( const glm::dvec2 val_ )noexcept;
//===== vals =====//
// Input坐标系 / UI坐标系 / 程序窗口坐标系
glm::dvec2 originVal {};
// 游戏世界 坐标系
//---
// 假设，originVal = {0,1}, 指向 正上方
// worldVal 会是 偏转后的，指向右上方的值，
// 这个值放进 游戏世界坐标系中，正式呈现为 视觉上的 正上方
glm::dvec2 worldVal {};
};
/* ===========================================================
* operator ==, !=
* -----------------------------------------------------------
* 这个实现，没有检测 origin 数据
*/
inline bool operator == ( DirAxes a_, DirAxes b_ ) noexcept {
return is_closeEnough( a_.get_worldVal(), b_.get_worldVal(), DirAxes::threshold );
}
inline bool operator != ( DirAxes a_, DirAxes b_ ) noexcept {
return !(a_==b_);
}
inline NineDirection dirAxes_2_nineDirection( const DirAxes &da_ )noexcept{
// 使用 符合 Input坐标系 的值，符合玩家视觉
// 现在，玩家输入的 left 方向，就能让 go 显示 left 方向，同时向 window left 方向移动
// 而不是 worldCoord 坐标系中的 left 方向
double x = da_.get_originVal().x;
double y = da_.get_originVal().y;
if( da_.is_zero() ){
return NineDirection::Center;
}
if( x == 0.0 ){
return (y > 0.0) ?
NineDirection::Top :
NineDirection::Bottom;
}
if( y == 0.0 ){
return (x > 0.0) ?
NineDirection::Right :
NineDirection::Left;
}
double rad = atan2( static_cast<double>(y), static_cast<double>(x) ); // (y,x)
double eighthPI = 3.1415926 / 8.0;
if( (rad < (-7.0 * eighthPI)) || (rad > (7.0 * eighthPI)) ){ return NineDirection::Left;
}else if( rad < (-5.0 * eighthPI) ){ return NineDirection::LeftBottom;
}else if( rad < (-3.0 * eighthPI) ){ return NineDirection::Bottom;
}else if( rad < (-1.0 * eighthPI) ){ return NineDirection::RightBottom;
}else if( rad < (1.0 * eighthPI) ){ return NineDirection::Right;
}else if( rad < (3.0 * eighthPI) ){ return NineDirection::RightTop;
}else if( rad < (5.0 * eighthPI) ){ return NineDirection::Top;
}else{ return NineDirection::LeftTop;
}
}
#endif
|
turesnake/tprPixelGames | src/Script/uiGos/allUIGoes.h | <filename>src/Script/uiGos/allUIGoes.h
/*
* ======================= allUIGoes.h ==========================
* -- tpr --
* CREATE -- 2019.08.25
* MODIFY --
* ----------------------------------------------------------
* 游戏中全体 uiGo 具象类 h文件 include
* ----------------------------
*/
#ifndef TPR_ALL_UI_GOES_H
#define TPR_ALL_UI_GOES_H
//---------- Script : uiGos --------------------//
#include "Script/uiGos/Button_SceneBegin_Archive.h"
#include "Script/uiGos/Button_SceneBegin_Pointer.h"
#endif
|
turesnake/tprPixelGames | src/Script/gameObjs/bioSoup/BioSoupColorTable.h | /*
* ==================== BioSoupColorTable.h ==========================
* -- tpr --
* CREATE -- 2020.03.06
* MODIFY --
* ----------------------------------------------------------
*/
#ifndef TPR_GO_BIO_SOUP_COLOR_TABLE_H
#define TPR_GO_BIO_SOUP_COLOR_TABLE_H
//-------------------- Engine --------------------//
#include "FloatVec.h"
namespace gameObjs::bioSoup {//------------- namespace gameObjs::bioSoup ----------------
struct BioSoupColorTable{
//-- base
FloatVec4 base_light;
FloatVec4 base_mid;
FloatVec4 base_dark;
//-- particle
FloatVec4 particle_light;
FloatVec4 particle_mid;
FloatVec4 particle_dark;
};
void write_ubo_BioSoupColorTable();
}//------------- namespace gameObjs::bioSoup: end ----------------
#endif
|
turesnake/tprPixelGames | src/Engine/json/json_oth.h | /*
* ======================= json_oth.h ==========================
* -- tpr --
* 创建 -- 2019.07.06
* 修改 --
* ----------------------------------------------------------
*/
#ifndef TPR_JSON_OTH_H
#define TPR_JSON_OTH_H
//--------------- CPP ------------------//
#include <utility>
#include <vector>
#include <string>
//--------------- Libs ------------------//
#include "rapidjson/document.h"
#include "rapidjson/writer.h"
#include "rapidjson/stringbuffer.h"
//--------------- Engine ------------------//
#include "tprAssert.h"
namespace json{//------------- namespace json ----------------
float get_float( const rapidjson::Value &val_ );
double get_double( const rapidjson::Value &val_ );
std::pair<bool, int> get_nullable_int( const rapidjson::Value &val_ );
enum class JsonValType : int{
Object,
Array,
Bool,
String,
Number,
Int,
Int64,
Uint,
Uint64,
Float,
Double
};
const rapidjson::Value &check_and_get_value( const rapidjson::Value &val_,
const std::string &name_,
JsonValType jsonValType_ );
void collect_fileNames( const std::string &headPath_,
const std::string &dirName_,
const std::string &headFileName_,
std::vector<std::string> &container_ );
inline std::string get_jsonFile_dirPath( const std::string &jsonFile_ )noexcept{
// 暂时只支持 Unix 风格的 path 格式
// 在本游戏中使用，暂无问题
tprAssert( jsonFile_.find('/') != std::string::npos );
size_t last_point_idx = jsonFile_.find_last_of( '/' ); //- 指向最后一个 '/'
auto lastIt = jsonFile_.begin();
std::advance( lastIt, last_point_idx ); //- advance 并不防止 溢出
std::string ret (jsonFile_.begin(), lastIt);
return ret;
}
}//------------- namespace json: end ----------------
#endif
|
turesnake/tprPixelGames | src/Engine/tprDebug/slicePic.h | <filename>src/Engine/tprDebug/slicePic.h
/*
* ========================= slicePic.h ==========================
* -- tpr --
* CREATE -- 2019.01.05
* MODIFY --
* ----------------------------------------------------------
*/
#ifndef TPR_SLICE_PIC_H
#define TPR_SLICE_PIC_H
//=== *** glad FIRST, glfw SECEND *** ===
// Don't include glfw3.h ALONE!!!
#include <glad/glad.h>
//-------------------- CPP --------------------//
#include <vector>
//-------------------- Engine --------------------//
#include "RGBA.h"
#include "IntVec.h"
namespace tprDebug {//---------- namespace: tprDebug --------------//
//-- 这段完全可以在 函数内创建...
inline RGBA e_ { 0,0,0,0 }; //- 空白
inline RGBA CO { 255,0,0,150 }; //- 有颜色
//-- mapEntSlice 使用的 “黄色边框” img
//-- 这个 边框宽度已经失效果了。
inline std::vector<RGBA> slicePic {};
inline IntVec2 slicePicSize { 64, 64 };
inline GLuint texName_slice {}; //- the only texName
//-- 一个 2*2 的小亮点
inline std::vector<RGBA> pointPic{
CO, CO,
CO, CO
};
inline IntVec2 pointPicSize { 2, 2 };
inline GLuint texName_pointPic {}; //- the only texName
}//-------------------- namespace: tprDebug end --------------//
#endif
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