{{위키데이터 속성 추적}}
{{다른 뜻 넘어옴|ARM8|ARMv8-A 아키텍처|ARMv8-A|ARMv8-R 아키텍처|ARMv8-R}}
다음은 [[ARM 홀딩스]]와 서드파티가 설계한 [[ARM 아키텍처|ARM]] 계열 [[명령어 집합]] 기반 [[마이크로아키텍처]] 목록이다.<ref>{{웹 인용| url = http://infocenter.arm.com/help/topic/com.arm.doc.faqs/attached/6745/0141_5linecard.pdf | title = ARM Powered Standard Products | format = PDF | year = 2005 | accessdate = 23 December 2017 | archive-url = https://web.archive.org/web/20171020195635/http://infocenter.arm.com/help/topic/com.arm.doc.faqs/attached/6745/0141_5linecard.pdf | archive-date = 20 October 2017 | url-status = live }}</ref> [[케일 (기업)|케일]] 또한 ARM 기반 프로세서의 벤더 요약을 제공한다.<ref>{{웹 인용|author= ARM Ltd and ARM Germany GmbH |url= http://www.keil.com/dd/parms/arm.htm |title= Device Database |publisher= Keil |accessdate= 6 January 2011 |archive-url= https://web.archive.org/web/20110110215343/http://www.keil.com/dd/parms/arm.htm |archive-date= 10 January 2011 |url-status= live }}</ref>

==ARM 코어==

=== ARM 설계 ===
{| class="wikitable" style="font-size: 85%; text-align: center"
|-
! ARM 계열
! ARM 아키텍처
! ARM 코어
! 기능
! [[CPU 캐시|캐시]] (I&nbsp;/&nbsp;D), [[메모리 관리 장치|MMU]]
! 일반 [[초당 명령 수|MIPS]] @ [[헤르츠|MHz]]
! 참조
|-
!ARM1
|ARMv1
|ARM1
|최초 구현
|없음
|
|
|-
!rowspan=2 | ARM2
|ARMv2
|ARM2
|ARMv2 added the MUL (multiply) instruction
|없음
|4&nbsp;MIPS @ 8&nbsp;MHz<br />0.33 [[드라이스톤]]/MHz
|
|-
|ARMv2a
|ARM250
|Integrated [[메모리 컨트롤러|MEMC]] (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructions
|없음, MEMC1a
|7&nbsp;MIPS @ 12&nbsp;MHz
|
|-
!ARM3
|ARMv2a
|ARM3
|First integrated memory cache
|4&nbsp;[[키비바이트|KB]] unified
|12&nbsp;MIPS @ 25&nbsp;MHz<br />0.50 DMIPS/MHz
|
|-
! rowspan=3 | ARM6
| rowspan=3 | ARMv3
|ARM60
|ARMv3 first to support 32-bit memory address space (previously 26-bit).<br>ARMv3M first added long multiply instructions (32x32=64).
|없음
|10&nbsp;MIPS @ 12&nbsp;MHz
|
|-
|ARM600
|As ARM60, cache and coprocessor bus (for FPA10 floating-point unit)
|4&nbsp;KB unified
|28&nbsp;MIPS @ 33&nbsp;MHz
|
|-
|ARM610
|As ARM60, cache, no coprocessor bus
|4&nbsp;KB unified
|17&nbsp;MIPS @ 20&nbsp;MHz<br />0.65 DMIPS/MHz
|<ref name="ARM610_Datasheet">{{웹 인용|title=ARM610 Datasheet |url=http://bitsavers.org/pdf/acorn/ARM_DDI_0004D_ARM610_Data_Sheet_Aug93.pdf |date=August 1993 |website=[[ARM 홀딩스]] |accessdate=January 29, 2019}}</ref>
|-
!rowspan=3 | [[ARM7]]
|rowspan=3 | ARMv3
|ARM700
|
|8&nbsp;KB unified
|40&nbsp;MHz
|
|-
|ARM710
|As ARM700, no coprocessor bus
|8&nbsp;KB unified
|40&nbsp;MHz
|<ref name="ARM710_Datasheet">{{웹 인용|title=ARM710 Datasheet |url=http://bitsavers.org/pdf/acorn/ARM_DDI_0024C_ARM710_Data_Sheet_Jul94.pdf |date=July 1994 |website=[[ARM 홀딩스]] |accessdate=January 29, 2019}}</ref>
|-
|ARM710a
|As ARM710
|8&nbsp;KB unified
|40&nbsp;MHz<br />0.68 DMIPS/MHz
|
|-
! rowspan=4 | [[ARM7T]]
| rowspan=4 | ARMv4T
|[[ARM7TDMI]](-S)
|3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM [[26-bit]] [[주소 공간|addressing]]
|없음
|15&nbsp;MIPS @ 16.8&nbsp;MHz<br />63 DMIPS @ 70&nbsp;MHz
|
|-
|ARM710T
|As ARM7TDMI, cache
|8&nbsp;KB unified, MMU
|36&nbsp;MIPS @ 40&nbsp;MHz
|
|-
|ARM720T
|As ARM7TDMI, cache
|8&nbsp;KB unified, MMU with FCSE (Fast&nbsp;Context Switch Extension)
|60&nbsp;MIPS @ 59.8&nbsp;MHz
|
|-
|ARM740T
|As ARM7TDMI, cache
|[[메모리 보호|MPU]]
|
|
|-
![[ARM7EJ]]
|ARMv5TEJ
|ARM7EJ-S
|5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructions
|없음
|
|
|-
!ARM8
|ARMv4
|ARM810
|5-stage pipeline, static branch prediction, double-bandwidth memory
| 8&nbsp;KB unified, MMU
| 84&nbsp;MIPS @ 72&nbsp;MHz<br />1.16 DMIPS/MHz
|<ref>{{웹 인용| url = https://www.hotchips.org/wp-content/uploads/hc_archives/hc08/2_Mon/HC8.S4/HC8.4.1.pdf | format = PDF | title = ARM810 – Dancing to the Beat of a Different Drum | author = ARM Holdings | publisher = [[Hot Chips]] | date = 7 August 1996 | accessdate = 14 November 2018 | archive-url = https://web.archive.org/web/20181224080542/https://www.hotchips.org/wp-content/uploads/hc_archives/hc08/2_Mon/HC8.S4/HC8.4.1.pdf | archive-date = 24 December 2018 | url-status = live }}</ref><ref name="eetimes 810">{{뉴스 인용| url=http://www.eetimes.com/document.asp?doc_id=1208831 | title=VLSI Technology Now Shipping ARM810 | work=[[EE Times]] | date=26 August 1996 | accessdate=21 September 2013 | archive-url=https://web.archive.org/web/20130926155924/http://www.eetimes.com/document.asp?doc_id=1208831 | archive-date=26 September 2013 | url-status=live }}</ref>
|-
! rowspan=4 | [[ARM9T]]
| rowspan=4 | ARMv4T
|[[ARM9TDMI]]
|5-stage pipeline, Thumb
|없음
|
|
|-
|[[ARM920T]]
|As ARM9TDMI, cache
|16&nbsp;KB / 16&nbsp;KB, MMU with FCSE (Fast Context Switch Extension)
|200&nbsp;MIPS @ 180&nbsp;MHz
|<ref>[http://infocenter.arm.com/help/topic/com.arm.doc.ddi0151c/I47491.html Register 13, FCSE PID register] {{Webarchive|url=https://web.archive.org/web/20110707164527/http://infocenter.arm.com/help/topic/com.arm.doc.ddi0151c/I47491.html |date=7 July 2011 }} ARM920T Technical Reference Manual</ref>
|-
|[[ARM922T]]
|As ARM9TDMI, caches
|8&nbsp;KB / 8&nbsp;KB, MMU
|
|
|-
|[[ARM940T]]
|As ARM9TDMI, caches
|4&nbsp;KB / 4&nbsp;KB, MPU
|
|
|-
! rowspan=5 | [[ARM9E]]
| rowspan=3 | ARMv5TE
|[[ARM946E-S]]
|Thumb, enhanced DSP instructions, caches
|Variable, tightly coupled memories, MPU
|
|
|-
|[[ARM966E-S]]
|Thumb, enhanced DSP instructions
|No cache, TCMs
|
|
|-
|[[ARM968E-S]]
|As ARM966E-S
|No cache, TCMs
|
|
|-
|ARMv5TEJ
|[[ARM926EJ-S]]
|Thumb, Jazelle DBX, enhanced DSP instructions
|Variable, TCMs, MMU
|220&nbsp;MIPS @ 200&nbsp;MHz
|
|-
|ARMv5TE
|[[ARM996HS]]
|Clockless processor, as ARM966E-S
|No caches, TCMs, MPU
|
|
|-
! rowspan=3 | ARM10E
| rowspan=2 | ARMv5TE
|ARM1020E
|6-stage pipeline, Thumb, enhanced DSP instructions, (VFP)
|32&nbsp;KB / 32&nbsp;KB, MMU
|
|
|-
|ARM1022E
|As ARM1020E
|16&nbsp;KB / 16&nbsp;KB, MMU
|
|
|-
|ARMv5TEJ
|ARM1026EJ-S
|Thumb, Jazelle DBX, enhanced DSP instructions, (VFP)
|Variable, MMU or MPU
|
|
|-
! rowspan=4 | [[ARM11]]
|ARMv6
|ARM1136J(F)-S
|8-stage pipeline, [[SIMD]], Thumb, Jazelle DBX, (VFP), enhanced DSP instructions, [[Bus error#Unaligned access|unaligned memory access]]
|Variable, MMU
|740 @ 532–665&nbsp;MHz (i.MX31 SoC), 400–528&nbsp;MHz
|<ref>{{웹 인용|url=http://www.arm.com/products/CPUs/ARM1136JF-S.html |title=ARM1136J(F)-S – ARM Processor |publisher=Arm.com |date= |accessdate=18 April 2009 |archiveurl=https://web.archive.org/web/20090321200633/http://www.arm.com/products/CPUs/ARM1136JF-S.html |archivedate=21 March 2009}}</ref>
|-
|ARMv6T2
|ARM1156T2(F)-S
|9-stage pipeline, [[SIMD]], Thumb-2, (VFP), enhanced DSP instructions
|Variable, MPU
|
|<ref>{{웹 인용|url=https://www.arm.com/products/processors/classic/arm11/arm1156.php|title=ARM1156 Processor|website=Arm Holdings|archive-url=https://web.archive.org/web/20100213205149/https://www.arm.com/products/processors/classic/arm11/arm1156.php|archive-date=13 February 2010}}</ref>
|-
|ARMv6Z
|ARM1176JZ(F)-S
|As ARM1136EJ(F)-S
|Variable, MMU + [[ARM 아키텍처]]
|965 DMIPS @ 772&nbsp;MHz, up to 2,600&nbsp;DMIPS with four processors
|<ref>{{웹 인용|url = http://www.arm.com/products/processors/classic/arm11/ |title = ARM11 Processor Family |publisher = ARM |accessdate = 12 December 2010 |archive-url = https://web.archive.org/web/20110115045355/http://www.arm.com/products/processors/classic/arm11/ |archive-date = 15 January 2011 |url-status = live }}</ref>
|-
|ARMv6K
|ARM11MPCore
|As ARM1136EJ(F)-S, 1–4 core SMP
|Variable, MMU
|
|
|-
! rowspan=3 | SecurCore
| ARMv6-M
| SC000
|
|
| 0.9 DMIPS/MHz
|
|-
| ARMv4T
| SC100
|
|
|
|
|-
| ARMv7-M
| SC300
|
|
| 1.25 DMIPS/MHz
|
|-
! rowspan=9 | [[ARM Cortex-M|Cortex-M]]
| rowspan=3 | ARMv6-M
|[[ARM Cortex-M0|Cortex-M0]]<ref name="M0-Spec">{{웹 인용|url=http://arm.com/products/processors/cortex-m/cortex-m0.php?tab=Specifications |title=Cortex-M0 Specification Summary; ARM Holdings. |access-date=13 June 2011 |archive-url=https://web.archive.org/web/20120321175611/http://arm.com/products/processors/cortex-m/cortex-m0.php?tab=Specifications |archive-date=21 March 2012 |url-status=live }}</ref>
|Microcontroller profile, most Thumb + some Thumb-2,<ref name="M0-InstrSet">{{웹 인용|url=http://archive.electronicdesign.com/files/29/20719/fig_01.gif|title=Cortex-M0/M0+/M1 Instruction set; ARM Holding.|archive-url=https://archive.today/20130418234149/http://archive.electronicdesign.com/files/29/20719/fig_01.gif|archive-date=18 April 2013}}</ref> hardware multiply instruction (optional small), optional system timer, optional bit-banding memory
|Optional cache, no TCM, no MPU
|0.84 DMIPS/MHz
|
|-
|[[ARM Cortex-M0+|Cortex-M0+]]<ref name="M0+-Spec">{{웹 인용|url=http://www.arm.com/products/processors/cortex-m/cortex-m0plus.php|title=Cortex-M0+ Specification Summary|website=Arm Holdings|access-date=21 July 2012|archive-url=https://web.archive.org/web/20120621091855/http://www.arm.com/products/processors/cortex-m/cortex-m0plus.php|archive-date=21 June 2012|url-status=live}}</ref>
|Microcontroller profile, most Thumb + some Thumb-2,<ref name="M0-InstrSet"/> hardware multiply instruction (optional small), optional system timer, optional bit-banding memory
|Optional cache, no TCM, optional MPU with 8 regions
|0.93 DMIPS/MHz
|
|-
|[[ARM Cortex-M1|Cortex-M1]]<ref name="M1-Spec">{{웹 인용|url=http://arm.com/products/processors/cortex-m/cortex-m1.php?tab=Specifications |title=Cortex-M1 Specification Summary; ARM Holdings. |access-date=13 June 2011 |archive-url=https://web.archive.org/web/20110707165410/http://arm.com/products/processors/cortex-m/cortex-m1.php?tab=Specifications |archive-date=7 July 2011 |url-status=live }}</ref>
|Microcontroller profile, most Thumb + some Thumb-2,<ref name="M0-InstrSet"/> hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memory
|Optional cache, 0–1024&nbsp;KB I-TCM, 0–1024&nbsp;KB D-TCM, no MPU
|136 DMIPS @ 170&nbsp;MHz,<ref>{{cite press |url=http://www.arm.com/news/17017.html |title=ARM Extends Cortex Family with First Processor Optimized for FPGA |publisher=ARM Holdings |date=19 March 2007 |accessdate=11 April 2007 |archive-url=https://web.archive.org/web/20070505180243/http://www.arm.com/news/17017.html |archive-date=5 May 2007 |url-status=live }}</ref> (0.8&nbsp;DMIPS/MHz FPGA-dependent)<ref>{{웹 인용|url=http://www.arm.com/products/CPUs/ARM_Cortex-M1.html |title=ARM Cortex-M1 |publisher=ARM product website |accessdate=11 April 2007 |archive-url=https://web.archive.org/web/20070401051142/http://www.arm.com/products/CPUs/ARM_Cortex-M1.html |archive-date=1 April 2007 |url-status=live }}</ref>
|
|-
|ARMv7-M
|[[ARM Cortex-M3|Cortex-M3]]<ref name="M3-Spec">{{웹 인용|url=http://arm.com/products/processors/cortex-m/cortex-m3.php?tab=Specifications |title=Cortex-M3 Specification Summary; ARM Holdings. |access-date=13 June 2011 |archive-url=https://web.archive.org/web/20120829045848/http://www.arm.com/products/processors/cortex-m/cortex-m3.php?tab=Specifications |archive-date=29 August 2012 |url-status=live }}</ref>
|Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory
|Optional cache, no TCM, optional MPU with 8 regions
|1.25 DMIPS/MHz
|
|-
| rowspan=2 |ARMv7E-M
|[[ARM Cortex-M4|Cortex-M4]]<ref name="M4-Spec">{{웹 인용|url=http://arm.com/products/processors/cortex-m/cortex-m4-processor.php?tab=Specifications |title=Cortex-M4 Specification Summary; ARM Holdings. |access-date=13 June 2011 |archive-url=https://web.archive.org/web/20120616150501/http://arm.com/products/processors/cortex-m/cortex-m4-processor.php?tab=Specifications |archive-date=16 June 2012 |url-status=live }}</ref>
|Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv4-SP single-precision [[부동 소수점 장치|FPU]], hardware multiply and divide instructions, optional bit-banding memory
|Optional cache, no TCM, optional MPU with 8 regions
|1.25 DMIPS/MHz (1.27 w/FPU)
|
|-
|[[ARM Cortex-M7|Cortex-M7]]<ref name="M7-Spec">{{웹 인용|url=http://arm.com/products/processors/cortex-m/cortex-m7-processor.php?tab=Specifications |title=Cortex-M7 Specification Summary; ARM Holdings. |access-date=24 September 2014 |archive-url=https://web.archive.org/web/20150923175111/http://www.arm.com/products/processors/cortex-m/cortex-m7-processor.php?tab=Specifications |archive-date=23 September 2015 |url-status=live }}</ref>
|Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv5 single and double precision [[부동 소수점 장치|FPU]], hardware multiply and divide instructions
|0−64&nbsp;KB I-cache, 0−64&nbsp;KB D-cache, 0–16&nbsp;MB I-TCM, 0–16&nbsp;MB D-TCM (all these w/optional ECC), optional MPU with 8 or 16 regions
|2.14 DMIPS/MHz
|
|-
| rowspan=3 |ARMv8-M
|[[ARM Cortex-M23|Cortex-M23]]<ref name="M23-Spec">[https://developer.arm.com/ip-products/processors/cortex-m/cortex-m23 Cortex-M23 Specification Summary; ARM Holdings.]</ref>
|Microcontroller profile, Thumb-1 (most), Thumb-2 (some), Divide, TrustZone
|Optional cache, no TCM, optional MPU with 16 regions
|0.99 DMIPS/MHz
|
|-
|[[ARM Cortex-M33|Cortex-M33]]<ref name="M33-Spec">[https://developer.arm.com/ip-products/processors/cortex-m/cortex-m33 Cortex-M33 Specification Summary; ARM Holdings.]</ref>
|Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor
|Optional cache, no TCM, optional MPU with 16 regions
|1.50 DMIPS/MHz
|
|-
|[[ARM Cortex-M35P|Cortex-M35P]]<ref name="M35P-Spec">{{웹 인용|url=https://developer.arm.com/ip-products/processors/cortex-m/cortex-m35p |title=Cortex-M35P Specification Summary; ARM Holdings. |access-date=29 April 2019 |archive-url=https://web.archive.org/web/20190508155414/https://developer.arm.com/ip-products/processors/cortex-m/cortex-m35p |archive-date=8 May 2019 |url-status=live }}</ref>
|Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor
|Built-in cache (with option 2–16&nbsp;KB), I-cache, no TCM, optional MPU with 16 regions
|1.50 DMIPS/MHz
|
|-
! rowspan="5" | [[ARM Cortex-R|Cortex-R]]
| rowspan=4 | ARMv7-R
|[[ARM Cortex-R4|Cortex-R4]]<ref name="R4-Spec">{{웹 인용|url=http://arm.com/products/processors/cortex-r/cortex-r4.php?tab=Specification |title=Cortex-R4 Specification Summary; ARM Holdings. |access-date=13 June 2011 |archive-url=https://web.archive.org/web/20110707163801/http://arm.com/products/processors/cortex-r/cortex-r4.php?tab=Specification |archive-date=7 July 2011 |url-status=live }}</ref>
|Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 [[부동 소수점 장치|FPU]], hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running [[Lockstep (computing)|lockstep]] with fault logic
|0–64&nbsp;KB / 0–64&nbsp;KB, 0–2 of 0–8&nbsp;[[메비바이트|MB]] TCM, opt. MPU with 8/12 regions
|1.67 DMIPS/MHz<ref name=":0">{{웹 인용|url=https://developer.arm.com/products/processors/cortex-r|title=Cortex-R – Arm Developer|publisher=Arm Ltd.|website=ARM Developer|language=en|access-date=2018-03-29|archive-url=https://web.archive.org/web/20180330080449/https://developer.arm.com/products/processors/cortex-r|archive-date=30 March 2018|url-status=live}}</ref>
|
|-
|[[ARM Cortex-R5|Cortex-R5]]<ref name="R5-Spec">{{웹 인용|url=http://arm.com/products/processors/cortex-r/cortex-r5.php |title=Cortex-R5 Specification Summary; ARM Holdings. |access-date=27 June 2012 |archive-url=https://web.archive.org/web/20120706031545/http://arm.com/products/processors/cortex-r/cortex-r5.php |archive-date=6 July 2012 |url-status=live }}</ref>
|Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP)<ref name="R5-PR">{{웹 인용|url=http://arm.com/products/arm-expands-unmatched-real-time-cortex-processor-portfolio.php |title=Cortex-R5 & Cortex-R7 Press Release; ARM Holdings; 31 January 2011. |access-date=13 June 2011 |archive-url=https://web.archive.org/web/20110707163818/http://arm.com/products/arm-expands-unmatched-real-time-cortex-processor-portfolio.php |archive-date=7 July 2011 |url-status=live }}</ref>
|0–64&nbsp;KB / 0–64&nbsp;KB, 0–2 of 0–8&nbsp;MB TCM, opt. MPU with 12/16 regions
|1.67 DMIPS/MHz<ref name=":0" />
|
|-
|[[ARM Cortex-R7|Cortex-R7]]<ref name="R7-Spec">{{웹 인용|url=http://arm.com/products/processors/cortex-r/cortex-r7.php?tab=Specification |title=Cortex-R7 Specification Summary; ARM Holdings. |access-date=19 November 2012 |archive-url=https://web.archive.org/web/20131212225127/http://arm.com/products/processors/cortex-r/cortex-r7.php?tab=Specification |archive-date=12 December 2013 |url-status=live }}</ref>
|Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic /  out-of-order execution / dynamic [[register renaming]] / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP<ref name="R5-PR" />
|0–64&nbsp;KB / 0–64&nbsp;KB, ? of 0–128&nbsp;KB TCM, opt. MPU with 16 regions
|2.50 DMIPS/MHz<ref name=":0" />
|
|-
|[[ARM Cortex-R8|Cortex-R8]]<ref name="R8-Spec">{{웹 인용|url=http://www.arm.com/products/processors/cortex-r/cortex-r8-processor.php |title=Cortex-R8 Specification Summary; ARM Holdings. |access-date=13 June 2016 |archive-url=https://web.archive.org/web/20160617051921/http://www.arm.com/products/processors/cortex-r/cortex-r8-processor.php |archive-date=17 June 2016 |url-status=live }}</ref>
|TBD
|TBD
|2.50 DMIPS/MHz<ref name=":0" />
|
|-
|ARMv8-R
|Cortex-R52<ref>{{웹 인용|url=https://developer.arm.com/products/processors/cortex-r/cortex-r52|title=Cortex-R52 – Arm Developer|publisher=Arm Ltd.|website=ARM Developer|language=en|access-date=2018-10-26|archive-url=https://web.archive.org/web/20181026182739/https://developer.arm.com/products/processors/cortex-r/cortex-r52|archive-date=26 October 2018|url-status=live}}</ref>
|TBD
|TBD
|2.16 DMIPS/MHz<ref>{{웹 인용|url=https://developer.arm.com/products/processors/cortex-r|title=Cortex-R – Arm Developer|publisher=Arm Ltd.|website=ARM Developer|language=en|access-date=2018-10-26|archive-url=https://web.archive.org/web/20180330080449/https://developer.arm.com/products/processors/cortex-r|archive-date=30 March 2018|url-status=live}}</ref>
|
|-
! rowspan=8 | [[ARM Cortex-A|Cortex-A<br/>(32비트)]]
| rowspan=7 | ARMv7-A
| [[ARM Cortex-A5|Cortex-A5]]<ref name="A5-Spec">{{웹 인용|url=http://arm.com/products/processors/cortex-a/cortex-a5.php?tab=Specifications |title=Cortex-A5 Specification Summary; ARM Holdings. |access-date=13 June 2011 |archive-url=https://web.archive.org/web/20110707171247/http://arm.com/products/processors/cortex-a/cortex-a5.php?tab=Specifications |archive-date=7 July 2011 |url-status=live }}</ref>
|Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 [[부동 소수점 장치|FPU]] / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)
|4−64&nbsp;KB / 4−64&nbsp;KB L1, MMU + TrustZone
|1.57&nbsp;DMIPS/MHz per core
|
|-
| [[ARM Cortex-A7|Cortex-A7]]<ref name="A7-Spec">{{웹 인용|url=http://arm.com/products/processors/cortex-a/cortex-a7.php?tab=Specifications |title=Cortex-A7 Specification Summary; ARM Holdings. |access-date=22 October 2011 |archive-url=https://web.archive.org/web/20120203163602/http://www.arm.com/products/processors/cortex-a/cortex-a7.php?tab=Specifications |archive-date=3 February 2012 |url-status=live }}</ref>
||Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, [[슈퍼스칼라]], 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), architecture and feature set are identical to A15, 8–10 stage pipeline, low-power design<ref name="Article-A7">{{뉴스 인용|url=https://www.theregister.co.uk/2011/10/20/details_on_big_little_processing/ |title=Deep inside ARM's new Intel killer |publisher=The Register |date=20 October 2011 |access-date=10 August 2017 |archive-url=https://web.archive.org/web/20170810205937/https://www.theregister.co.uk/2011/10/20/details_on_big_little_processing/ |archive-date=10 August 2017 |url-status=live }}</ref>
|8−64&nbsp;KB / 8−64&nbsp;KB L1, 0–1&nbsp;MB L2, MMU + TrustZone
|1.9 DMIPS/MHz per core
|
|-
|[[ARM Cortex-A8|Cortex-A8]]<ref name="A8-Spec">{{웹 인용|url=http://arm.com/products/processors/cortex-a/cortex-a8.php?tab=Specifications |title=Cortex-A8 Specification Summary; ARM Holdings. |access-date=13 June 2011 |archive-url=https://web.archive.org/web/20131212225332/http://arm.com/products/processors/cortex-a/cortex-a8.php?tab=Specifications |archive-date=12 December 2013 |url-status=live }}</ref>
|Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage [[슈퍼스칼라]] pipeline
|16–32&nbsp;KB / 16–32&nbsp;KB L1, 0–1&nbsp;MB L2 opt. ECC, MMU + TrustZone
|Up to 2000 (2.0&nbsp;DMIPS/MHz in speed from 600&nbsp;MHz to greater than 1&nbsp;[[헤르츠|GHz]])
|
|-
|[[ARM Cortex-A9|Cortex-A9]]<ref name="A9-Spec">{{웹 인용|url=http://arm.com/products/processors/cortex-a/cortex-a9.php?tab=Specifications |title=Cortex-A9 Specification Summary; ARM Holdings. |access-date=13 June 2011 |archive-url=https://web.archive.org/web/20111007092736/http://arm.com/products/processors/cortex-a/cortex-a9.php?tab=Specifications |archive-date=7 October 2011 |url-status=live }}</ref>
||Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, [[비순차적 명령어 처리|out-of-order]] [[speculative execution|speculative issue]] [[슈퍼스칼라]], 1–4 SMP cores, MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)
|16–64&nbsp;KB / 16–64&nbsp;KB L1, 0–8&nbsp;MB L2 opt. parity, MMU + TrustZone
|2.5 DMIPS/MHz per core, 10,000&nbsp;DMIPS @ 2&nbsp;GHz on Performance Optimized TSMC [[45 nm 공정|40G]] (dual-core)
|
|-
|[[ARM Cortex-A12|Cortex-A12]]<ref name="A12-Spec">{{웹 인용|url=http://www.arm.com/products/processors/cortex-a/cortex-a12-processor.php |title=Cortex-A12 Summary; ARM Holdings. |access-date=3 June 2013 |archive-url=https://web.archive.org/web/20130607135127/http://www.arm.com/products/processors/cortex-a/cortex-a12-processor.php |archive-date=7 June 2013 |url-status=live }}</ref>
||Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, [[비순차적 명령어 처리|out-of-order]] [[speculative execution|speculative issue]] [[슈퍼스칼라]], 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)
|32−64 KB
|3.0 DMIPS/MHz per core
|
|-
|[[ARM Cortex-A15|Cortex-A15]]<ref name="A15-Spec">{{웹 인용|url=http://arm.com/products/processors/cortex-a/cortex-a15.php?tab=Specifications |title=Cortex-A15 Specification Summary; ARM Holdings. |access-date=13 June 2011 |archive-url=https://web.archive.org/web/20110707171526/http://arm.com/products/processors/cortex-a/cortex-a15.php?tab=Specifications |archive-date=7 July 2011 |url-status=live }}</ref>
||Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, [[비순차적 명령어 처리|out-of-order]] [[speculative execution|speculative issue]] [[슈퍼스칼라]], 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline<ref name="Article-A7" />
|32&nbsp;KB w/parity / 32&nbsp;KB w/[[ECC 메모리|ECC]] L1, 0–4&nbsp;MB L2, L2 has ECC, MMU + TrustZone
|At least 3.5&nbsp;DMIPS/MHz per core (up to 4.01&nbsp;DMIPS/MHz depending on implementation)<ref name="A15-Performance">{{웹 인용|url=http://www.itproportal.com/2011/03/14/exclusive-arm-cortex-a15-40-cent-faster-cortex-a9/ |title=Exclusive : ARM Cortex-A15 "40 Per Cent" Faster Than Cortex-A9 {{!}} ITProPortal.com<!-- Bot generated title --> |access-date=13 June 2011 |archive-url=https://web.archive.org/web/20110721081000/http://www.itproportal.com/2011/03/14/exclusive-arm-cortex-a15-40-cent-faster-cortex-a9/ |archive-date=21 July 2011 |url-status=live }}</ref>
|
|-
|[[ARM Cortex-A17|Cortex-A17]]<ref name="A17-Spec">{{웹 인용|url=http://www.arm.com/products/processors/cortex-a/cortex-a17-processor.php |title=Cortex-A17 Specification Summary; ARM Holdings. |access-date=13 June 2016 |archive-url=https://web.archive.org/web/20160627233605/http://www.arm.com/products/processors/cortex-a/cortex-a17-processor.php |archive-date=27 June 2016 |url-status=live }}</ref>
||Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, [[비순차적 명령어 처리|out-of-order]] [[speculative execution|speculative issue]] [[슈퍼스칼라]], 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP
|32 KB L1, 256&nbsp;KB–8&nbsp;MB L2 w/optional ECC
|2.8&nbsp;DMIPS/MHz
|
|-
| rowspan=1 | ARMv8-A
|[[ARM 아키텍처|Cortex-A32]]<ref>{{웹 인용| url=http://www.arm.com/products/processors/cortex-a/cortex-a32-processor.php | title=Cortex-A32 Processor | publisher=[[ARM 홀딩스]] | accessdate=18 May 2016 | archive-url=https://web.archive.org/web/20160502070131/http://www.arm.com/products/processors/cortex-a/cortex-a32-processor.php | archive-date=2 May 2016 | url-status=live }}</ref>
|Application profile, AArch32, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline
|8–64&nbsp;KB w/optional parity / 8−64&nbsp;KB w/optional ECC L1 per core, 128&nbsp;KB–1&nbsp;MB L2 w/optional ECC shared
|
|
|-
! rowspan="11" |[[ARM Cortex-A|Cortex-A<br/>(64비트)]]
| rowspan="6" |ARMv8-A
|[[ARM 아키텍처]]<ref>{{웹 인용|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a34|title=Cortex-A34|last=Ltd|first=Arm|website=ARM Developer|language=en|access-date=2019-10-11}}</ref>
|Application profile, AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline
|8−64&nbsp;KB w/parity / 8−64&nbsp;KB w/ECC L1 per core, 128&nbsp;KB–1&nbsp;MB L2&nbsp;shared, 40-bit physical addresses
|
|
|-
|[[ARM 아키텍처|Cortex-A35]]<ref>{{웹 인용| url=http://www.arm.com/products/processors/cortex-a/cortex-a35-processor.php | title=Cortex-A35 Processor | publisher=[[ARM 홀딩스]] | accessdate=18 May 2016 | archive-url=https://web.archive.org/web/20160524125142/http://www.arm.com/products/processors/cortex-a/cortex-a35-processor.php | archive-date=24 May 2016 | url-status=live }}</ref>
|Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline
| 8−64&nbsp;KB w/parity / 8−64&nbsp;KB w/ECC L1 per core, 128&nbsp;KB–1&nbsp;MB L2&nbsp;shared, 40-bit physical addresses
|1.78 DMIPS/MHz
|
|-
| [[ARM Cortex-A53|Cortex-A53]]<ref>{{웹 인용| url=http://www.arm.com/products/processors/cortex-a50/cortex-a53-processor.php | title=Cortex-A53 Processor | publisher=[[ARM 홀딩스]] | accessdate=13 October 2012 | archive-url=https://web.archive.org/web/20121101102248/http://www.arm.com/products/processors/cortex-a50/cortex-a53-processor.php | archive-date=1 November 2012 | url-status=live }}</ref>
| Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline
| 8−64&nbsp;KB w/parity / 8−64&nbsp;KB w/ECC L1 per core, 128&nbsp;KB–2&nbsp;MB L2&nbsp;shared, 40-bit physical addresses
| 2.3 DMIPS/MHz
|
|-
| [[ARM Cortex-A57|Cortex-A57]]<ref>{{웹 인용| url=http://www.arm.com/products/processors/cortex-a50/cortex-a57-processor.php | title=Cortex-A57 Processor | publisher=[[ARM 홀딩스]] | accessdate=13 October 2012 | archive-url=https://web.archive.org/web/20121101102257/http://www.arm.com/products/processors/cortex-a50/cortex-a57-processor.php | archive-date=1 November 2012 | url-status=live }}</ref>
| Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline
|48 KB w/DED parity / 32&nbsp;KB w/ECC L1 per core; 512&nbsp;KB–2&nbsp;MB L2&nbsp;shared w/ECC; 44-bit physical addresses
|4.1–4.5&nbsp;DMIPS/MHz<ref>{{웹 인용| url=http://www.bitkistl.com/2015/03/cortex-ax-vs-performnace.html | title=Cortex-Ax vs performance | accessdate=5 May 2017 | archive-url=https://web.archive.org/web/20170615001530/http://www.bitkistl.com/2015/03/cortex-ax-vs-performnace.html | archive-date=15 June 2017 | url-status=live }}</ref><ref>{{웹 인용| url=http://www.cnx-software.com/2015/04/09/relative-performance-of-arm-cortex-a-32-bit-and-64-bit-cores | title=Relative Performance of ARM Cortex-A 32-bit and 64-bit Cores | accessdate=5 May 2017 | archive-url=https://web.archive.org/web/20170501055942/http://www.cnx-software.com/2015/04/09/relative-performance-of-arm-cortex-a-32-bit-and-64-bit-cores/ | archive-date=1 May 2017 | url-status=live }}</ref>
|
|-
| [[ARM Cortex-A72|Cortex-A72]]<ref>{{웹 인용| url=http://www.arm.com/products/processors/cortex-a/cortex-a72-processor.php | title=Cortex-A72 Processor | publisher=[[ARM 홀딩스]] | accessdate=3 February 2015 | archive-url=https://web.archive.org/web/20150207044624/http://www.arm.com/products/processors/cortex-a/cortex-a72-processor.php | archive-date=7 February 2015 | url-status=live }}</ref>
| Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width superscalar, deeply out-of-order pipeline
|48 KB w/DED parity / 32&nbsp;KB w/ECC L1 per core; 512&nbsp;KB–2&nbsp;MB L2&nbsp;shared w/ECC; 44-bit physical addresses
|4.7&nbsp;DMIPS/MHz
|
|-
| [[ARM Cortex-A73|Cortex-A73]]<ref>{{웹 인용| url=http://www.arm.com/products/processors/cortex-a/cortex-a73-processor.php | title=Cortex-A73 Processor | publisher=[[ARM 홀딩스]] | accessdate=2 June 2016 | archive-url=https://web.archive.org/web/20160602125819/http://www.arm.com/products/processors/cortex-a/cortex-a73-processor.php | archive-date=2 June 2016 | url-status=live }}</ref>
| Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width superscalar, deeply out-of-order pipeline
|64 KB / 32−64&nbsp;KB L1 per core, 256&nbsp;KB–8&nbsp;MB L2&nbsp;shared w/ optional ECC, 44-bit physical addresses
|4.8&nbsp;DMIPS/MHz<ref>{{웹 인용| url=http://www.bitkistl.com/2015/03/cortex-ax-vs-performnace.html | title=Cortex-Ax vs performance | accessdate=5 May 2017 | archive-url=https://web.archive.org/web/20170615001530/http://www.bitkistl.com/2015/03/cortex-ax-vs-performnace.html | archive-date=15 June 2017 | url-status=live }}</ref>
|
|-
| rowspan="7" |ARMv8.2-A
|[[ARM Cortex-A55|Cortex-A55]]<ref>{{웹 인용|url=https://developer.arm.com/products/processors/cortex-a/cortex-a55|title=Cortex-A55 – Arm Developer|publisher=Arm Ltd.|website=ARM Developer|language=en|access-date=2017-11-27|archive-url=https://web.archive.org/web/20170819232745/https://developer.arm.com/products/processors/cortex-a/cortex-a55|archive-date=19 August 2017|url-status=live}}</ref>
|Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline<ref>{{웹 인용|url=https://nl.hardware.info/reviews/7394/4/preview-arms-nieuwe-cpu--en-gpu-architecturen-cortex-a55-efficientie|title=Hardware.Info Nederland|website=nl.hardware.info|language=nl|access-date=2017-11-27|archive-url=https://web.archive.org/web/20181224080550/https://nl.hardware.info/reviews/7394/4/preview-arms-nieuwe-cpu--en-gpu-architecturen-cortex-a55-efficientie|archive-date=24 December 2018|url-status=live}}</ref>
|16−64 KB / 16−64&nbsp;KB L1, 256&nbsp;KB L2 per core, 4&nbsp;MB L3 shared
|
|
|-
|[[Arm Cortex-A65AE]]<ref>{{웹 인용|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65ae|title=Cortex-A65AE|last=Ltd|first=Arm|website=ARM Developer|language=en|access-date=2019-10-11}}</ref>
|Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, out-of-order pipeline, [[동시 멀티스레딩|SMT]]
|64 / 64 KB L1, 256&nbsp;KB L2 per core, 4&nbsp;MB L3 shared
|
|
|-
|[[ARM Cortex-A75|Cortex-A75]]<ref>{{웹 인용|url=https://developer.arm.com/products/processors/cortex-a/cortex-a75|title=Cortex-A75 – Arm Developer|publisher=Arm Ltd.|website=ARM Developer|language=en|access-date=2017-11-27|archive-url=https://web.archive.org/web/20170819233509/https://developer.arm.com/products/processors/cortex-a/cortex-a75|archive-date=19 August 2017|url-status=live}}</ref>
|Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline<ref>{{웹 인용|url=https://nl.hardware.info/reviews/7394/5/preview-arms-nieuwe-cpu--en-gpu-architecturen-cortex-a75-high-performancen|title=Hardware.Info Nederland|website=nl.hardware.info|language=nl|access-date=2017-11-27|archive-url=https://web.archive.org/web/20181224080458/https://nl.hardware.info/reviews/7394/5/preview-arms-nieuwe-cpu--en-gpu-architecturen-cortex-a75-high-performancen|archive-date=24 December 2018|url-status=live}}</ref>
|64 / 64 KB L1, 512&nbsp;KB L2 per core, 4&nbsp;MB L3 shared
|
|
|-
| [[ARM Cortex-A76|Cortex-A76]]<ref>{{웹 인용|url=https://developer.arm.com/products/processors/cortex-a/cortex-a76|title=Cortex-A76 – Arm Developer|publisher=Arm Ltd.|website=ARM Developer|language=en|access-date=2018-11-15|archive-url=https://web.archive.org/web/20181011133539/https://developer.arm.com/products/processors/cortex-a/cortex-a76|archive-date=11 October 2018|url-status=live}}</ref>
| Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way issue, 13 stage pipeline, deeply out-of-order pipeline<ref name=":1">{{웹 인용|url=https://anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse/2|title=Arm's Cortex-A76 CPU Unveiled: Taking Aim at the Top for 7nm|website=AnandTech|access-date=2018-11-15|archive-url=https://web.archive.org/web/20181116000840/https://www.anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse/2|archive-date=16 November 2018|url-status=live}}</ref>
|64 / 64 KB L1, 256−512&nbsp;KB L2 per core, 512&nbsp;KB−4&nbsp;MB L3 shared
|
|
|-
|[[ARM Cortex-A77|Cortex-A77]]<ref>{{웹 인용|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a77|title=Cortex-A {{!}} Cortex-A77|last=Ltd|first=Arm|website=ARM Developer|language=en|access-date=2019-06-16|archive-url=https://web.archive.org/web/20190619222014/https://developer.arm.com/ip-products/processors/cortex-a/cortex-a77|archive-date=19 June 2019|url-status=live}}</ref>
|Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 6-width instruction fetch, 12-way issue, 13 stage pipeline, deeply out-of-order pipeline<ref name=":1" />
|1.5K L0 MOPs cache, 64 / 64&nbsp;KB L1, 256−512&nbsp;KB L2 per core, 512&nbsp;KB−4&nbsp;MB L3 shared
|
|
|-
! rowspan="2" |Neoverse
|Neoverse N1<ref>{{웹 인용|url=https://developer.arm.com/ip-products/processors/neoverse/neoverse-n1|title=Neoverse N1|last=Ltd|first=Arm|website=ARM Developer|language=en|access-date=2019-06-16}}</ref>
|Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way dispatch/issue, 13 stage pipeline, deeply out-of-order pipeline<ref name=":1" />
|64 / 64 KB L1, 512−1024&nbsp;KB L2 per core, 2−128&nbsp;MB L3 shared, 128&nbsp;MB system level cache
|
|
|-
|Neoverse E1
|Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, 10 stage pipeline, out-of-order pipeline, [[동시 멀티스레딩|SMT]]
|32−64 KB / 32−64&nbsp;KB L1, 256&nbsp;KB L2 per core, 4&nbsp;MB L3 shared
|
|
|-   
! ARM 계열
! ARM 아키텍처
! ARM 코어
! 기능
! [[CPU 캐시|캐시]] (I&nbsp;/&nbsp;D), [[메모리 관리 장치|MMU]]
! 일반 [[초당 명령 수|MIPS]] @ [[헤르츠|MHz]]
! 참조
|}
As Dhrystone is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads{{snd}} use with caution.

=== 서드 파티 설계 ===
{| class="wikitable" style="font-size: 85%; text-align: center"
|-
! 코어 계열
! [[명령어 집합]]
! [[마이크로아키텍처]]
! 기능
! 캐시 (I&nbsp;/&nbsp;D), [[메모리 관리 장치|MMU]]
! 일반 [[초당 명령 수|MIPS]] @ MHz
|-
! rowspan=2 | [[StrongARM]]<br>([[디지털 이큅먼트 코퍼레이션|Digital]])
| rowspan=2 | ARMv4
| SA-110
| 5-stage pipeline
| 16&nbsp;KB / 16&nbsp;KB, MMU
| 100–233&nbsp;MHz<br />1.0 DMIPS/MHz
|-
| SA-1100
| derivative of the SA-110
| 16&nbsp;KB / 8&nbsp;KB, MMU
|
|-
! rowspan=7 | Faraday<ref>{{웹 인용|url=http://www.faraday-tech.com/html/Product/IPProduct/ProcessorCores/index.htm|title=Processor Cores|publisher=[[Faraday Technology]]|access-date=19 February 2015|archive-url=https://web.archive.org/web/20150219233845/http://www.faraday-tech.com/html/Product/IPProduct/ProcessorCores/index.htm|archive-date=19 February 2015|url-status=dead}}</ref><br>([[Faraday Technology]])
| rowspan=3 | ARMv4 || FA510 || rowspan=2 | 6-stage pipeline || Up to 32&nbsp;KB / 32&nbsp;KB cache, MPU || 1.26 DMIPS/MHz <br> 100–200&nbsp;MHz
|-
| FA526 || Up to 32&nbsp;KB / 32&nbsp;KB cache, MMU  || 1.26&nbsp;MIPS/MHz <br> 166–300&nbsp;MHz
|-
| FA626 || 8-stage pipeline || 32&nbsp;KB / 32&nbsp;KB cache, MMU || 1.35 DMIPS/MHz <br>500&nbsp;MHz
|-
| rowspan=4 | ARMv5TE || FA606TE || 5-stage pipeline || No cache, no MMU|| 1.22 DMIPS/MHz<br>200&nbsp;MHz
|-
| FA626TE || 8-stage pipeline|| rowspan=3 |32&nbsp;KB / 32&nbsp;KB cache, MMU || 1.43&nbsp;MIPS/MHz<br>800&nbsp;MHz
|-
| FMP626TE || 8-stage pipeline, SMP ||  1.43&nbsp;MIPS/MHz<br>500&nbsp;MHz
|-
| FA726TE ||13 stage pipeline, dual issue || 2.4 DMIPS/MHz<br>1000&nbsp;MHz
|-
! rowspan=3 | [[XScale]]<br>([[인텔]] / [[마벨 테크놀로지 그룹|Marvell]])
| rowspan=3 | ARMv5TE
| XScale
| 7-stage pipeline, Thumb, enhanced DSP instructions
| 32&nbsp;KB / 32&nbsp;KB, MMU
| 133–400&nbsp;MHz
|-
| Bulverde
| Wireless [[MMX (명령어 집합)|MMX]], wireless [[스피드스텝]] added
| 32&nbsp;KB / 32&nbsp;KB, MMU
| 312–624&nbsp;MHz
|-
| Monahans<ref name="intel-xscale3g">{{웹 인용|title=3rd Generation Intel XScale Microarchitecture: Developer’s Manual|url=http://download.intel.com/design/intelxscale/31628302.pdf|work=download.intel.com|publisher=Intel|accessdate=2 December 2010|date=May 2007|archive-url=https://web.archive.org/web/20080225120503/http://download.intel.com/design/intelxscale/31628302.pdf|archive-date=25 February 2008|url-status=live}}</ref>
| Wireless MMX2 added
| 32&nbsp;KB / 32&nbsp;KB L1, optional L2&nbsp;cache up to 512&nbsp;KB, MMU
| Up to 1.25&nbsp;GHz
|-
! rowspan=4 | Sheeva<br>(Marvell)
| rowspan=3 | ARMv5 || Feroceon || 5–8 stage pipeline, single-issue || 16&nbsp;KB / 16&nbsp;KB, MMU || rowspan=2|600–2000&nbsp;MHz
|-
| Jolteon || 5–8 stage pipeline, dual-issue || 32&nbsp;KB / 32&nbsp;KB, MMU
|-
| PJ1 (Mohawk) || 5–8 stage pipeline, single-issue, Wireless MMX2 || 32&nbsp;KB / 32&nbsp;KB, MMU || 1.46 DMIPS/MHz<br>1.06&nbsp;GHz
|-
| ARMv6 / ARMv7-A || PJ4 || 6–9 stage pipeline, dual-issue, Wireless MMX2, SMP || 32&nbsp;KB / 32&nbsp;KB, MMU || 2.41&nbsp;DMIPS/MHz<br>1.6&nbsp;GHz
|-
! rowspan=3 | [[스냅드래곤|Snapdragon]]<br>([[퀄컴]])
| rowspan=2 | ARMv7-A
| [[Scorpion (CPU)|Scorpion]]<ref name="Snapdragon-Spec">{{웹 인용|url=http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture |title=Qualcomm's New Snapdragon S4: MSM8960 & Krait Architecture Explored; Anandtech. |access-date=24 October 2012 |archive-url=https://web.archive.org/web/20121106064416/http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture |archive-date=6 November 2012 |url-status=live }}</ref>
| 1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 [[부동 소수점 장치|FPU]] / NEON (128-bit wide)
|256&nbsp;KB L2 per core
|2.1 DMIPS/MHz per core
|-
| [[크레이트 (CPU)|Krait]]<ref name="Snapdragon-Spec"/>
| 1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 [[부동 소수점 장치|FPU]] / NEON (128-bit wide)
|4&nbsp;KB / 4&nbsp;KB L0, 16&nbsp;KB / 16&nbsp;KB L1, 512&nbsp;KB L2 per core
|3.3 DMIPS/MHz per core
|-
| rowspan=1 | ARMv8-A
| [[Kryo (microarchitecture)|Kryo]]<ref name="Kryo-ann">{{웹 인용|url=https://www.qualcomm.com/news/snapdragon/2015/09/02/snapdragon-820-and-kryo-cpu-heterogeneous-computing-and-role-custom |title=Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute |publisher=Qualcomm |date=2015-09-02 |accessdate=2015-09-06 |archive-url=https://web.archive.org/web/20150905203003/https://www.qualcomm.com/news/snapdragon/2015/09/02/snapdragon-820-and-kryo-cpu-heterogeneous-computing-and-role-custom |archive-date=5 September 2015 |url-status=live }}</ref>
| 4 cores. || ? || Up to 2.2&nbsp;GHz
(6.3 DMIPS/MHz)
|-
! rowspan=8 | [[애플이 설계한 프로세서|Ax]]<br>([[애플|Apple]])
| rowspan=1 | ARMv7-A
| [[애플 A6|Swift]]<ref name="Swift-spec">{{웹 인용|url=http://www.anandtech.com/show/6292/iphone-5-a6-not-a15-custom-core|title=The iPhone 5's A6 SoC: Not A15 or A9, a Custom Apple Core Instead|publisher=[[AnandTech]]|date=15 September 2012|accessdate=15 September 2012|first=Anand|last=Lal Shimpi|archive-url=https://web.archive.org/web/20120915203513/http://www.anandtech.com/show/6292/iphone-5-a6-not-a15-custom-core|archive-date=15 September 2012|url-status=live}}</ref>
| 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 [[부동 소수점 장치|FPU]] / NEON
|L1: 32&nbsp;KB / 32&nbsp;KB, L2: 1&nbsp;MB
|3.5 DMIPS/MHz per core
|-
| ARMv8-A || [[애플 A7|Cyclone]]<ref name="anandtech-a8x">{{웹 인용|url=http://www.anandtech.com/show/8716/apple-a8xs-gpu-gxa6850-even-better-than-i-thought|title=Apple A8X's GPU - GAX6850, Even Better Than I Thought|first=Ryan|last=Smith|date=November 11, 2014|publisher=Anandtech|access-date=29 November 2014|archive-url=https://web.archive.org/web/20141130014356/http://www.anandtech.com/show/8716/apple-a8xs-gpu-gxa6850-even-better-than-i-thought|archive-date=30 November 2014|url-status=live}}</ref> || 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 [[부동 소수점 장치|FPU]] / NEON / [[ARM 아키텍처]] / [[AArch64]]. Out-of-order, superscalar. || L1: 64&nbsp;KB / 64&nbsp;KB, L2: 1&nbsp;MB, L3: 4&nbsp;MB || 1.3 or 1.4&nbsp;GHz
|-
| ARMv8-A || [[애플 A8|Typhoon]]<ref name="anandtech-a8x"/><ref>{{웹 인용|url=http://www.anandtech.com/show/9443/apple-refreshes-the-ipod-touch-with-a8-soc-and-new-camera |title=Apple Refreshes The iPod Touch With A8 SoC And New Cameras |first=Brandon |last=Chester |date=July 15, 2015 |publisher=Anandtech |accessdate=September 11, 2015 |archive-url=https://web.archive.org/web/20150905232041/http://anandtech.com/show/9443/apple-refreshes-the-ipod-touch-with-a8-soc-and-new-camera |archive-date=5 September 2015 |url-status=live }}</ref> || 2 or 3 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 [[부동 소수점 장치|FPU]] / NEON / [[ARM 아키텍처]] / [[AArch64]] || L1: 64&nbsp;KB / 64&nbsp;KB, L2: 1&nbsp;MB or 2&nbsp;MB, L3: 4&nbsp;MB || 1.4 or 1.5&nbsp;GHz
|-
| ARMv8-A || [[애플 A9|Twister]]<ref>{{웹 인용|url=http://www.anandtech.com/show/9662/iphone-6s-and-iphone-6s-plus-preliminary-results |title=iPhone 6s and iPhone 6s Plus Preliminary Results |first=Joshua |last=Ho |date=September 28, 2015 |publisher=Anandtech |accessdate=December 18, 2015 |archive-url=https://web.archive.org/web/20160526001956/http://www.anandtech.com/show/9662/iphone-6s-and-iphone-6s-plus-preliminary-results |archive-date=26 May 2016 |url-status=live }}</ref> || 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 [[부동 소수점 장치|FPU]] / NEON / [[ARM 아키텍처]] / [[AArch64]] || L1: 64&nbsp;KB / 64&nbsp;KB, L2: 2&nbsp;MB, L3: 4&nbsp;MB or 0&nbsp;MB || 1.85 or 2.26&nbsp;GHz
|-
| ARMv8.1-A || [[애플 A10|Hurricane and Zephyr]]<ref>{{웹 인용|url=http://www.anandtech.com/show/10685/the-iphone-7-and-iphone-7-plus-review |title=The iPhone 7 and iPhone 7 Plus Review |first=Joshua |last=Ho |date=September 28, 2015 |publisher=Anandtech |accessdate=September 14, 2017 |archive-url=https://web.archive.org/web/20170914220425/http://www.anandtech.com/show/10685/the-iphone-7-and-iphone-7-plus-review |archive-date=14 September 2017 |url-status=live }}</ref> || Hurricane: 2 or 3 cores. AArch64, 6-decode, 6-issue, 9-wide, superscalar, out-of-order<br/>Zephyr: 2 or 3 cores. AArch64. || L1: 64&nbsp;KB / 64&nbsp;KB, L2: 3&nbsp;MB or 8&nbsp;MB, L3: 4&nbsp;MB or 0&nbsp;MB || 2.34 or 2.38&nbsp;GHz
|-
| ARMv8.2-A || [[애플 A11|Monsoon and Mistral]]<ref>{{웹 인용|url=https://en.wikichip.org/wiki/apple/ax/a11 |title=A11 Bionic - Apple |publisher=WikiChip |accessdate=February 1, 2019}}</ref> || Monsoon: 2 cores. AArch64, 7-decode, ?-issue, 11-wide, superscalar, out-of-order<br/>Mistral: 4 cores. AArch64, out-of-order, superscalar. Based on Swift. || L1I: 128&nbsp;KB, L1D: 64&nbsp;KB, L2: 8&nbsp;MB, L3: 4&nbsp;MB || 2.39&nbsp;GHz
|-
| ARMv8.3-A || [[애플 A12|Vortex and Tempest]]<ref>{{웹 인용|url=https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-review-unveiling-the-silicon-secrets/ |title=The iPhone XS &amp; XS Max Review: Unveiling the Silicon Secrets |publisher=Anandtech |accessdate=February 11, 2019 |archive-url=https://web.archive.org/web/20190212070449/https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-review-unveiling-the-silicon-secrets/ |archive-date=12 February 2019 |url-status=live }}</ref> || Vortex: 2 or 4 cores. AArch64, 7-decode, ?-issue, 11-wide, superscalar, out-of-order<br/>Tempest: 4 cores. AArch64, 3-decode, out-of-order, superscalar. Based on Swift. || L1: 128&nbsp;KB / 128&nbsp;KB, L2: 8&nbsp;MB, L3: 8&nbsp;MB || 2.5&nbsp;GHz
|-
| ARMv8.4-A || [[Apple A13|Lightning and Thunder]]<ref>{{웹 인용|url=https://www.anandtech.com/show/14892/the-apple-iphone-11-pro-and-max-review|title=The Apple iPhone 11, 11 Pro & 11 Pro Max Review: Performance, Battery, & Camera Elevated|last=Frumusanu|first=Andrei|website=www.anandtech.com|access-date=2019-10-20}}</ref> || Lightning: 2 cores. AArch64, 7-decode, ?-issue, 11-wide, superscalar, out-of-order<br/>Thunder: 4 cores. AArch64, out-of-order, superscalar.|| L1: 128&nbsp;KB / 128&nbsp;KB, L2: 8&nbsp;MB, L3: 16&nbsp;MB || 2.66&nbsp;GHz
|-
! X-Gene<br>([[Applied Micro Circuits Corporation|Applied Micro]])
| ARMv8-A ||X-Gene || 64-bit, quad issue, SMP, 64 cores<ref>{{웹 인용|url=http://www.pcworld.com/article/2464600/appliedmicros-64core-chip-could-spark-off-arm-core-war.html |title=Archived copy |access-date=21 August 2014 |archive-url=https://web.archive.org/web/20140821175759/http://www.pcworld.com/article/2464600/appliedmicros-64core-chip-could-spark-off-arm-core-war.html |archive-date=21 August 2014 |url-status=live }}</ref> || Cache, MMU, virtualization || 3&nbsp;GHz (4.2 DMIPS/MHz per core)
|-
! [[Project Denver|Denver]]<br>([[엔비디아]])
| ARMv8-A || Denver<ref>{{웹 인용|url=http://www.anandtech.com/Gallery/Album/3847 |title=Archived copy |access-date=29 November 2014 |archive-url=https://web.archive.org/web/20141205022933/http://www.anandtech.com/Gallery/Album/3847 |archive-date=5 December 2014 |url-status=live }}</ref><ref>{{웹 인용|url=http://blogs.nvidia.com/blog/2014/08/11/tegra-k1-denver-64-bit-for-android/ |title=Archived copy |access-date=29 November 2014 |archive-url=https://web.archive.org/web/20140812090907/http://blogs.nvidia.com/blog/2014/08/11/tegra-k1-denver-64-bit-for-android/ |archive-date=12 August 2014 |url-status=live }}</ref> || 2 cores. [[AArch64]], 7-wide [[슈퍼스칼라]], in-order, dynamic code optimization, 128&nbsp;MB optimization cache,<br>Denver1: 28nm, Denver2:16nm || 128&nbsp;KB I-cache&nbsp;/&nbsp;64&nbsp;KB D-cache || Up to 2.5&nbsp;GHz
|-
! [[Project Denver|Carmel]]<br>([[엔비디아]])
| ARMv8(t.b.d.) || Carmel<ref>{{웹 인용|url=https://www.golem.de/news/nvidia-drive-xavier-fuer-autonome-autos-wird-ausgeliefert-1801-132035.html |title=Archived copy |access-date=5 March 2018 |archive-url=https://web.archive.org/web/20180305202753/https://www.golem.de/news/nvidia-drive-xavier-fuer-autonome-autos-wird-ausgeliefert-1801-132035.html |archive-date=5 March 2018 |url-status=live }}</ref><ref>{{웹 인용|url=https://wccftech.com/nvidia-drive-xavier-soc-detailed/ |title=Archived copy |access-date=5 March 2018 |archive-url=https://web.archive.org/web/20180224191519/https://wccftech.com/nvidia-drive-xavier-soc-detailed/ |archive-date=24 February 2018 |url-status=live }}</ref> || 2 cores. [[AArch64]], 10-wide [[슈퍼스칼라]], in-order, dynamic code optimization, ?&nbsp;MB optimization cache,<br>functional safety, dual execution, parity & ECC || ?&nbsp;KB I-cache&nbsp;/&nbsp;?&nbsp;KB D-cache || Up to ?&nbsp;GHz
|-
! [[Cavium ThunderX|ThunderX]]<br>([[Cavium]])
| ARMv8-A || ThunderX || 64-bit, with two models with 8–16 or 24–48 cores (×2 w/two chips) || ? || Up to 2.2&nbsp;GHz
|-
! [[AMD K12|K12]]<br>([[어드밴스트 마이크로 디바이시스]])
| ARMv8-A || K12<ref>{{웹 인용|url=http://www.anandtech.com/show/7990/amd-announces-k12-core-custom-64bit-arm-design-in-2016 |title=Archived copy |access-date=26 June 2015 |archive-url=https://web.archive.org/web/20150626102331/http://www.anandtech.com/show/7990/amd-announces-k12-core-custom-64bit-arm-design-in-2016 |archive-date=26 June 2015 |url-status=live }}</ref> || ? || ? || ?
|-
! rowspan="3" | [[삼성 엑시노스]]<br>([[삼성그룹]])
| ARMv8-A || M1/M2 ("Mongoose")<ref>{{웹 인용|url=http://www.anandtech.com/show/9781/samsung-announces-exynos-8890-with-cat1213-modem-and-custom-cpu|title=Samsung Announces Exynos 8890 with Cat.12/13 Modem and Custom CPU|work=AnandTech|access-date=18 December 2015|archive-url=https://web.archive.org/web/20151127053812/http://anandtech.com/show/9781/samsung-announces-exynos-8890-with-cat1213-modem-and-custom-cpu|archive-date=27 November 2015|url-status=live}}</ref> || 4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order || 64&nbsp;KB I-cache&nbsp;/&nbsp;32&nbsp;KB D-cache, L2: 16-way shared 2&nbsp;MB || 5.1 DMIPS/MHz
(2.6&nbsp;GHz)
|-
| ARMv8-A
| M3 ("Meerkat")<ref>{{웹 인용|url=https://www.anandtech.com/show/13199/hot-chips-2018-samsungs-exynosm3-cpu-architecture-deep-dive|title=Hot Chips 2018: Samsung’s Exynos-M3 CPU Architecture Deep Dive|work=AnandTech|access-date=20 August 2018|archive-url=https://web.archive.org/web/20180820203929/https://www.anandtech.com/show/13199/hot-chips-2018-samsungs-exynosm3-cpu-architecture-deep-dive|archive-date=20 August 2018|url-status=live}}</ref>
| 4 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order || 64&nbsp;KB I-cache&nbsp;/&nbsp;32&nbsp;KB D-cache, L2: 8-way private 512&nbsp;KB, L3: 16-way shared 4&nbsp;MB || ?
|-
|ARMv8.2-A
|M4 ("Cheetah")
|2 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order
|64&nbsp;KB I-cache&nbsp;/&nbsp;32&nbsp;KB D-cache, L2: 8-way private 512&nbsp;KB, L3: 16-way shared 4&nbsp;MB
|?
|-
|}

== ARM 코어 타임라인 ==
다음의 표는 발표 연도별 각 코어를 나열한다.<ref>{{웹 인용|url=http://www.arm.com/about/company-profile/milestones.php |title=ARM Company Milestones. |access-date=6 April 2014 |archive-url=https://web.archive.org/web/20140328171411/http://www.arm.com/about/company-profile/milestones.php |archive-date=28 March 2014 |url-status=live }}</ref><ref>{{웹 인용|url=http://www.arm.com/about/newsroom/index.php |title=ARM Press Releases. |access-date=6 April 2014 |archive-url=https://web.archive.org/web/20140409172237/http://arm.com/about/newsroom/index.php |archive-date=9 April 2014 |url-status=live }}</ref>  ARM7 이전 코어는 이 표에 포함되어 있지 않다.<!-- Please add older cores to this table! -->

{| class="wikitable" border="1"
|-
! rowspan=2 | 연도
! colspan=5 | 클래식 코어
! colspan=4 | Cortex 코어
! Neoverse 코어
|-
! [[ARM7]] !! ARM8 !! [[ARM9]] !! ARM10 !! [[ARM11]] !! [[ARM Cortex-M|마이크로컨트롤러]] !! [[ARM Cortex-R|실시간]] !! [[ARM Cortex-A|애플리케이션]]<br>(32비트) !! [[ARM Cortex-A|애플리케이션]]<br>(64비트) !! 애플리케이션<br>(64비트)
|-
! 1993
| ARM700 || || || || || || || || ||
|-
! 1994
| ARM710<br/>ARM7DI<br>ARM7TDMI || || || || || || || || ||
|-
! 1995
| ARM710a || || || || || || || || ||
|-
! 1996
| || ARM810 || || || || || || || ||
|-
! 1997
| ARM710T<br>ARM720T<br>ARM740T || || || || || || || || ||
|-
! 1998
| || || ARM9TDMI<br>ARM940T || || || || || || ||
|-
! 1999
| || || ARM9E-S<br>ARM966E-S || || || || || || ||
|-
! 2000
| || || ARM920T<br>ARM922T<br>ARM946E-S || ARM1020T || || || || || ||
|-
! 2001
| ARM7TDMI-S<br>ARM7EJ-S || || ARM9EJ-S<br>ARM926EJ-S || ARM1020E<br>ARM1022E || || || || || ||
|-
! 2002
| || || || ARM1026EJ-S || ARM1136J(F)-S || || || || ||
|-
! 2003
| || || ARM968E-S || || ARM1156T2(F)-S<br>ARM1176JZ(F)-S || || || || ||
|-
! 2004
| || || || || || Cortex-M3 || || || ||
|-
! 2005
| || || || || ARM11MPCore || || || Cortex-A8 || ||
|-
! 2006
| || || ARM996HS || || || || || || ||
|-
! 2007
| || || || || || Cortex-M1 || || Cortex-A9 || ||
|-
! 2008
| || || || || || || || || ||
|-
! 2009
| || || || || || Cortex-M0 || || Cortex-A5 || ||
|-
! 2010
| || || || || || Cortex-M4(F) || || Cortex-A15 || ||
|-
! 2011
| || || || || || || Cortex-R4<br>Cortex-R5<br>Cortex-R7 || Cortex-A7 || ||
|-
! 2012
| || || || || || Cortex-M0+ || || || Cortex-A53<br>Cortex-A57 ||
|-
! 2013
| || || || || || || || Cortex-A12 || ||
|-
! 2014
| || || || || || Cortex-M7(F) || || Cortex-A17 || ||
|-
! 2015
| || || || || || || || || Cortex-A35<br>Cortex-A72 ||
|-
! 2016
| || || || || || Cortex-M23<br/>Cortex-M33(F) || Cortex-R8<br/>Cortex-R52 || Cortex-A32 || Cortex-A73 ||
|-
! 2017
| || || || || || || || || Cortex-A55<br/>Cortex-A75 ||
|-
! 2018
| || || || || || Cortex-M35P(F) || || || Cortex-A65AE<br/>Cortex-A76<br/>Cortex-A76AE ||
|-
!2019
| || || || || || || || || Cortex-A77 || Neoverse E1<br/>Neoverse N1
|-
!2020
| || || || || || Cortex-M55(F) || || || Cortex-A78<br/> Cortex-X1<ref>https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging</ref> ||
|}

== 같이 보기 ==
* [[ARM 아키텍처]]

== 각주 ==
{{각주}}

{{애플리케이션 ARM 기반 칩}}

{{기본정렬:ARM 마이크로아키텍처}}

[[분류:마이크로프로세서 목록]]
[[분류:ARM 아키텍처| ]]
[[분류:ARM 마이크로프로세서| ]]