Patent GB-804809-A (GB)
Title: Electrostatic storage system
IPC: G11C11/23
Filed: 1955-07-15
Abstract: 804,809. Electric digital-data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. July 15, 1955 [July 19, 1954], No. 20520/55. Class 106 (1). An electrostatic storage system having an action cycle for effecting read-in to and read-out from a cathode-ray tube storage device for storing manifestations representative of preselected values and a regeneration cycle for regenerating values previously stored, includes amplifying means connected to amplify signals representing information read out from said storage device and manifest each bit thereof at at its output as a voltage pulse of time duration corresponding to the value represented thereby; circuit means coupling said amplifying means to the cathode-ray tube storage device and to gating means coupled to a data terminal for receiving at preselected time intervals during each cycle either information read out or fresh information to be read in; and control circuit means responsive to control pulses and connected to said circuit means and said gating means to cause said circuit means to transmit to the storage device either said information being read out or fresh information to be read in during each cycle. Two embodiments are described: one using binary coded decimal addresses, action cycles interspersed randomly amongst regeneration cycles and representing data by either a defocused dot or a focused dash, and the other using pure binary addresses, alternate action and regeneration cycles and representing data by either a defocused dot or a focused dash. For both embodiments detailed circuits comprising conventional electronic circuits such as tuned anode amplifiers, diode gating circuits, blocking oscillators, &c. are described. First embodiment.-In the first C.R.T. storage system described, Figs. 2A-2E, 2000 16-decimal-digit (64 bit) words are stored in parallel form in 256 cathode-ray tubes, the 2000 address positions being distributed over each of 64 C.R.T. storage units, each of which comprises 4 tubes A, B, C and D, and stores one bit of each of the 2000 words. A word can be read from or into any address of the store during an " action " cycle, which is of 8 clock pulses duration (8 micro-seconds) and during which the C.R.T. beams are positioned in accordance with an address applied in binary coded decimal form to terminals A1, A2 . . . A4000, Fig. 2A, and a word is regenerated during a " regeneration " cycle, which is also of 8 clock pulses duration, and in which the C.R.T. beams are positioned in accordance with the count reached by a regeneration counter. The regeneration counter and the address switch, shown in detail in Figs. 6A-6D, are so arranged that except when an action cycle is to occur (terminal AR, Fig. 6A, " down ") successive regeneration cycles occur (terminal AR, " up "), the counter advancing once for each regeneration cycle. Thus the words in the store are continually being successively regenerated under the control of the regeneration counter, this process only being interrupted when it is desired to read from or into a specified address, during which time advancement of the counter is inhibited. In each storage unit-only that for the 1-bits of the first digits of the 2000 words being shown in full in Figs. 2C and 2D-each cathode-ray tube stores 500 bits, tubes A and C containing the even addresses from 0-998 and 1000-1998 respectively, and tubes B and D the odd addresses from 1-999 and 1001-1999 respectively. Addresses are selected by similarly positioning the four beams of the tubes A-D and selecting one of the tubes. This is done by vertical and horizontal deflection circuits, Fig. 2B, which, under control of an address manifested by the address switch, apply appropriate voltages to the parallel connected plates of the four tubes, and by a tube selector, also controlled by the address switch, which energizes one of four leads TSA, TSB, TSC, TSD to open one of four gates 620a, 621a, 622a, 623a, Fig. 2D, thus allowing a signal (dot or dash) applied to the other commoned inputs of these gates to pass to the control grid of the selected tube. Regeneration cycle.-Each bit is entered into a tube by first writing a dot with the beam defocused, which dot is then either left unmodified to store a 0-bit or modified-by focusing the beam and moving it slightly diagonally-to store a 1-bit. A stored bit is read out by over-writing a dot (0-bit). During regeneration cycles addresses are selected under the control of the regeneration counter, the terminal AR being held " up." Half-way through each regeneration cycle an " on-pulse generator," Fig. 2D, applies a short pulse of half a clock pulse duration (from time 0.40-0.46) to a " pulse stretcher No. 2 " from where it passes via a selected one of gates 620a-623a to the control grid of the selected tube where it causes a dot to be written at the selected address which in turn induces a signal on the commoned pick-up plates representative of the bit that was previously recorded at the selected address. This signal passes via a video amplifier, a detector and pulse stretcher No. 1, and a gate to the pulse stretcher No. 2 where, if it represents a dash (1-bit), it causes the signal emitted by the No. 2 pulse stretcher to be lengthened from a duration of half a clock pulse to four clock pulses, thereby causing the dot written at the selected address to be changed to a dash. The signal read from the selected tube is also passed from the detector to a combined read in and out circuit and then to a terminal DL1-1, where a dot (0-bit) is represented by the absence of a signal during the sixth clock pulse (time 0.50-0.60) and a dash (1-bit) by the presence of a signal during this period. At the end of a regeneration cycle, if the terminal AR, Fig. 2A, remains " up," a further regeneration cycle ensues, the regeneration counter being " sensed " during the first clock-pulse and the count reached staticized for the remainder of the cycle by the pulse stretchers, Fig. 2A, and advancing one step during the second clock pulse. Action, cycle.-For an action cycle the terminal AR must be held " down " whereupon the regeneration counter does not advance one step and the address selected is that represented by the signals applied to terminals A1, A2 ... A8000. A " read-out " action cycle is exactly the same as a regeneration cycle, the selected address being both read and regenerated. During a " read-in " action cycle, a signal is applied to a terminal RIT, Fig. 2D, its main effect being to cause gate 605 to be blocked to signals from the detector, which signals still, however, pass via the read in and out circuits and appear at terminal DL1-1 during the sixth clock pulse (0.50-0.60). If a dot (0-bit) is to be read in no signal is applied to the terminal DL1-1 during the fifth clock pulse (0.40-0.50), then the dot signal applied by the on-pulse generator is passed via the pulse stretcher No. 2 and written at the selected address (this signal also causes the reading out from the selected address of what was already there), and if a dash (1-bit) is to be read in a signal is applied to terminal DL1-1 during the fifth clock pulse, then a signal passes from the read-in circuits to the pulse stretcher No. 2 causing the dot that is automatically written to be extended to a dash. Thus the terminal DL1-1 functions both as an input and as an output terminal, and in every cycle-even during read-in cycles-the data at the selected address appears at this terminal during the sixth clock pulse. Regeneration counter.-Each denomination, Fig. 5A, of the counter comprises an elementary binary adder having a first feed-back loop from its " sum output terminal 198-1 via four serially connected unit delays DC4, DC2, DC1, DC8 to one of its input terminals 195, and a second feed-back loop from its " carry " output terminal 197-1 via a delay DCC to another of its input terminals 194. Each delay is of the type described in Specification 719,418, [Group XL (c)], which is referred to and requires to be pulsed regularly with clamp and sync. pulses produced under the control of a master oscillator by a clamp and sync. inverter unit 295. By suppressing a sync. pulse, which is done by applying a positive clear pulse to the clamp and sync. inverter at the same time as the negative sync. signal is applied, each delay is " emptied " and the counter denomination is cleared. Each denomination of the counter has a circulationcycle of eight clock pulses, i.e. once a pattern of pulses is circulating, and if no further input counter advance pulses are applied, the number exhibited at the output terminals D4, D2, D8 and D1 at any instant, will again be exhibited after eight clock pulses. The manner in which counter advance pulses are registered is shown in Fig. 5C. Initially at time 0.00 the counter denomination is cleared (by suppressing a sync. pulse) and at time 0.10-one clock pulse latera counter advance pulse is entered. This causes a pattern of pulses to start circulating, as shown in Fig. 5C, and if the output terminals D1-D8 are sensed eight clock pulses later, at time 1.00, a one will be exhibited. Immediately after this, at time 1.10, a further counter advance pulse can be entered-Fig. 5C shows the result of doing this-but if a further counter advance pulse is not entered the one exhibited at time 1.00 at the output terminals will again be exhibited after a further eight clock pulses. Further counter advance pulses result in the patterns shown in Figs. 5C and 5D, until immediately after the tenth counter advance pulse, at time 9.20, a signal is produced by a gate 301a which clears the denomination and provides a carry signal to the next higher denomination. Thus the counter denomination shown in Fig. 5A operates with a radix of ten. The complete counter, Figs. 6A-6D, comprising four decimal denominations of the type shown in Fig. 5A, also comprises a diode input control gate 241, 247, Fig.