Patent GB-1366231-A (GB)
Title: Method of maufacturing a four zone semiconductor device
IPC: H01L29/749
Filed: 1973-04-09
Abstract: 1366231 Semi-conductor devices NATIONAL CASH REGISTER CO 9 April 1973 [20 April 1972] 16869/73 Heading H1K A 4 zone semi-conductor device, e.g. a MOST with 1st and 3rd zones of one conductivity and 2nd and 4th zones of a second conductivity is connected at 12 in a circuit 10 (Fig. 1) with a P-type anode and cathode base 14, 18 and a N- type anode base and cathode 16, 20. An insulated gate 22 spans cathode base 18 with electrode 26 of, e.g. Al overlying insulant 24. Battery 30 energizes anode 14 and cathode 20 over load resistor 22 and switch 36, while battery 30 energizes gate electrode over switch 44 by which it is alternatively grounded. In operation (Fig. 2) curve A represents conducting state and curve B nonconducting state, with a holding current at point E. Initially the gate electrode is grounded and the device is de-energized to be nonconducting. Closure of switch 36 develops a voltage/current characteristic B with operation at point D, the intersection of load line CD. Closure of switch 34 causes the device to assume its conductive characteristic A with operating point C. Restoration of switch 34 holds the device conducting until anode current is reduced below the holding value E, when the device resumes its nonconducting state. In fabrication an insulant, e.g. spinel support has grown thereon a semi-conductor crystal 42 of, e.g. high resistivity N-Si on which an insulant layer 44 of, e.g. SiO 2  is deposited or thermally grown, in which cathode and anode openings 46, 48 are etched. A layer 50 of a glass containing distributed P and N impurities, e.g. As and Bo is then, e.g. sputtered on and removed except in the region of the cathode opening and is overlain by a further layer of glass 52 containing only P-type impurities, e.g. Bo (Fig. 3c). The device is heated for thermal diffusion of the impurities into layer 42 so that P-regions 54, 58, 62 and N-regions 56, 60 exist therein; the P- impurities penetrating more deeply than the N- impurities. Regions 54, 58 are interconnected (not shown), and region 56 has a high concentration and low resistivity as cathode, region 58 has medium concentration and medium resistivity as cathode base, region 60 has high resistivity as anode, base and region 62 has high concentration and low resistivity as anode. The layer 44 is etched away to an appropriate depth (or directly to region 58 with subsequent regrowth) and conductive material, e.g. Al is deposited at 68, 70, 72 in openings 46, 64, 48 to contact region 50, insulant layer 66, and region 62, and may be connected to other points of an integrated circuit. (Fig. 3e.) In a modification, a N-type Si layer of high resistivity is grown epitaxially on a P-type Si substrate, an insulant layer is grown thereon, and P-type regions are diffused through openings into the N-type layer. Anode and cathode openings are etched in the insulant layer and a PN dopant source is applied as described and removed save for that in the anodic opening. A further P dopant source is deposited as described and the impurities are in-diffused to part depth of the epitaxial layer to leave a N-region in a P-region, and a P-region distinct therefrom, to form the required 4 zone device. A gate electrode is deposited in an opening of the insulant layer to span the first P-region, and metal layers are deposited in the openings to form a gate. (Figs. 4a to 4e, not shown.)