Patent GB-1148471-A (GB)
Title: Data processing apparatus
IPC: G06F9/38
Filed: 1966-04-04
Abstract: 1,148,471. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 4 April, 1966 [5 April, 1965], No. 14793/66. Heading G4A. In data processing apparatus, the operand for a given instruction is fetched from storage while the preceding instruction is being executed, an instruction being selected from a buffer loaded from storage as the preceding instruction is transferred to the instruction execution unit. The I-unit fetches instructions and operands from main storage and the E-unit executes the instructions, the two units being operable concurrently. The BCU co-ordinates storage access requests from the 1-unit and E-unit. Instruction fetch.-Each instruction is 1, 2 or 3 halfwords long, the length being specified by two bits of the op code. Two doubleword buffers A, B are used alternately each being reloaded from main storage via register SBO with a doubleword as it becomes empty, the instruction count (part of the programme status word in register PSW) being appropriately incremented at INCR before being used to address storage to obtain the doubleword. Loading operation registers.-Register GSR selects two adjacent instruction halfwords from A, B for gating to register IOP (the second being ignored in the case of a one-halfword instruction. In the case of a three-halfwords instruction the third halfword is obtained later when it is needed). IOP supplies the op code and a register designator field of the instruction to register BOP, the op code to register EOP and first and second operand length fields (when present in the instruction) to registers Y, Z respectively. The register designator in BOP is supplied to register ER1. The op code in EOP is transferred to register LCOP just before the last cycle of its execution to allow EOP to be preset with the next instruction's op code. The op code in IOP, BOP controls I-unit operations, and that in EOP controls E-unit operations except during the last cycle when LCOP controls them. Updating instruction count.-The instruction length bits from the current op code in IOP are added to the three low order bits of the instruction count from PSW at GSA, the result being stored in register GSR and also PSW. If a carry resulted it is added into the high order bits at INCR, the result being replaced in PSW. Fetching operands from storage.-IOP selects two of 16 general purpose registers GPR, their contents being added at AA to a field from IOP to address storage, the fetched operand being put in register J via register SBO. Fetching operands from addressable registers.- IOP selects one or two registers (general purpose registers GPR and/or floating point registers FP) to feed register RBL and/or register J via RBL. Register put-aways.-ER1 selects one or two (second by incrementing) GPRs or a FP to receive a result from register K or registers K and ER. Storing results.-Main storage is addressed as during fetching operands from storage and those bytes of the accessed location specified by a mark register MR are replaced by the corresponding bytes of the K register using register SB1. Fixed-point add/subtract.-This is done in adder AM using operands sent from register RBL via register M, the result going to register K prior to register put-away. Floating-point add/subtract.-The first and second operands are in registers RBL, J respectively. RBL is copied into M and the fraction in J is passed via adder AM into K. The exponents are subtracted in adder AE, the result going into register ER and shift counter SC. Exponents are equalized by shifting either K or M by repeated passes through AM, under control of SC. The aligned fractions are added or subtracted in AM, the result going to both K and M. The result exponent is the larger of the two operand exponents and is either transferred from M via AE, into ER or is reconstituted by adding the exponent in M to the difference in ER by means of AE the results going to ER, as appropriate. The results in K, ER can now be putaway. Variable-field-length operations.-For each of the two operands in turn, IOP selects a GPR whose contents are added at AA to a field from IOP and the operand length from Y or Z, to obtain an address which is used for addressing storage to obtain an operand doubleword which is passed via SBO, J, AM to K or L. The byte portion of the address is put into register T or S via register H. T and S gate (at LBG, RBG) successive pairs of bytes (one from K and one from L) to decimal adder AV for addition/subtraction, the result byte being put into K at the byte position selected by T which also sets a mark bit in the mark register MR for use during subsequent storing of the K register contents. T, S, Y, Z are decremented as successive pairs of bytes are added/subtracted until Y and Z indicate the operands have been completely processed. During this, successive operand doublewords are fetched from main storage as necessary, fetching in the case of the first operand (using K) being preceded by storing the contents of K (results) via SB1 and fetching in the case of the second operand involving prefetching into register M. Logical variable-field-length operations are mentioned. Interrupt.-The contents of the PSW are stored on interrupt.