baber/WOPTO huggingface dataset:
Patent TW-480688-B (TW)
Title: Window BGA package structure
Inventor: CHUNG CHO-LIANG
IPC: H01L23/28
Filed: 2001-05-28
Granted: 2002-03-21
Abstract: An integrated circuit package comprises: a chip, a circuit board, a plurality of metal bonding wires, a plurality of solder balls, a package body, and a plurality of bump spacers. The circuit board has a die-attaching surface, a ball-planting surface, and at least a window. The solder balls bond on the ball-planting surface. The chip locates on the die-attaching surface. The metal bonding wires connect the chip and the circuit board through the window. The bump spacers are between the chip and the circuit board to form an interval for the pre-curing package body flowing.
Patent TW-512288-B (TW)
Title: Multi-image automatic license plate recognition car control system
Inventor: JENG BO-SHUEN
IPC: G06K9/32
Filed: 2001-06-28
Granted: 2002-12-01
Abstract: A multi-image automatic license plate recognition car control system, which is composed of a front-view sensing unit, a rear-view sensing unit, a front-view CCD camera, a rear-view CCD camera, a frame grabber, an automatic license plate image recognition unit, and a recognition data integration unit. Those members can be used to generate a set of completely recognized license plates as the license number of that car, and the data for each passing car comprising the front-view single image, the rear-view single image, the front-view license number, the rear-view license number and the integrated license number after mutual compensation process as the basis for car control corresponding to the data of each passing card; and, further associating with the query of the user database, the electric fencing, the alarm lights, the alarm sounds for the control of the license plate identities of the passing cars.
Patent TW-I228057-B (TW)
Title: Improved system for fluidized catalytic cracking of hydrocarbon molecules
Inventor: SENIOR RICHARD CHARLES
IPC: B01F3/12
Filed: 2001-07-10
Granted: 2005-02-21
Abstract: A fluidized catalytic cracking system includes a riser for contacting catalyst and hydrocarbon feedstock. The riser has an inner surface that defines a central passage. The central passage acts as a flow path for the catalyst and the hydrocarbon feedstock. A plurality of ribs are disposed on the riser inner surface. The ribs increase the degree of mixing that occurs between the catalyst and the hydrocarbon feedstock within the central passage. In particular, each rib has a contoured inner wall. The contour of the inner wall forces a portion of the catalyst flow inward, toward the hydrocarbon-rich center of the central passage.
Patent TW-497244-B (TW)
Title: Method and system to adjust the electrical property of micro-electronic circuit-arrangements
Inventor: BRADL STEPHAN
IPC: H01L21/82
Filed: 2001-07-25
Granted: 2002-08-01
Abstract: This invention relates to adjust the electrical property of a micro-electronic circuit-arrangement (5) with at least one analog electronic unit (11, 12, 13). In a configuration-step, the analog units (11, 12, 13) are set in a state through sending-in and/or sending-out of the electrical charge. Said state determines the analog electrical property of the unit. Especially the floating-gate of an EEPROM-cell is charged to a charge-value that can be freely selected in a continuous region.
Patent TW-I277182-B (TW)
Title: Semiconductor device and manufacturing method thereof
Inventor: KURIHARA TOSHIMICHI
IPC: H01L23/34
Filed: 2001-08-30
Granted: 2007-03-21
Abstract: The lower end of a resin wall is bonded to a radiating plate, and a lead is fixed so as to extend through the resin wall. After a semiconductor chip is bonded thereto, a resin lid is put to seal the semiconductor chip. Recessed parts for burying the lower end of the resin wall are formed on the side parts of the radiating plate, and protruding parts are further provided within the recessed parts. The lead has holes formed on the package outer part and the resin wall inner part. The loading surface of the semiconductor chip is finished with silver plating, and the package exterior and the lead are plated with gold. The shape fitted to the resin wall is imparted to the resin lid, and the resin lid is further formed into a vertically plane symmetric shape.
Patent TW-523755-B (TW)
Title: Semiconductor memory device
Inventor: ITOU TAKASHI
IPC: G11C7/12
Filed: 2001-09-06
Granted: 2003-03-11
Abstract: A VBL generation circuit which normally outputs an equalizing potential outputs a potential corresponding to writing data in the test mode and this potential is collectively supplied to the bit lines by an equalizing circuit. In the test mode, a row decoder collectively activates the selected word lines by setting the pre-decode signals RXO to RX3 to the active condition and by controlling the pre-decode signals XO to X3 in accordance with the test signal. Accordingly, a writing in of a test pattern, wherein the detection of a short circuit between the storage nodes of memory cells is possible, can be carried out rapidly.
Patent TW-507301-B (TW)
Title: Semiconductor structure including a partially annealed layer and method of forming the same
Inventor: EISENBEISER KURT
IPC: H01L21/203
Filed: 2001-09-27
Granted: 2002-10-21
Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. To further relieve strain in the accommodating buffer layer, at least a portion of the accommodating buffer layer is exposed to a laser anneal process to cause the accommodating buffer layer to become amorphous, providing a true compliant substrate for subsequent layer growth.
Patent TW-528707-B (TW)
Title: Integrated operation mold of automatic warehousing
Inventor: CHENG ANDREW
IPC: B65G37/00
Filed: 2001-10-12
Granted: 2003-04-21
Abstract: The present invention is an integrated operation mold of automatic warehousing of which the steps comprise (a) providing first and second rows of shelves, (b) providing a crane located between the first and second rows of shelves, (c) providing a plurality of deposition units which are deposited on the first and second rows of shelves, (d) providing a plurality of distribution devices, (e) arranging first and second distribution zones, respectively located under the first and second rows of shelves with the cranes capable of moving the plurality of deposition units to the first and second distribution zones, and (f) providing a plurality of operators in the first and second distribution zones to retrieve cargos to be distributed from the deposition unit and position the cargos to be distributed into the plurality of distribution devices.
Patent TW-565817-B (TW)
Title: Display device and driving method thereof
Inventor: MIKAMI YOSHIRO
IPC: H05B44/00
Filed: 2001-10-24
Granted: 2003-12-11
Abstract: In an active matrix display device utilizing electro-optical elements such as organic EL elements capable of obtaining a high image quality with a low power, each pixel circuit is provided with: a sampling circuit for sampling a signal voltage on a signal wiring line synchronously with a scan pulse; a reference voltage; and a comparator circuit. In the pixel circuit, the sampled signal voltage is compared with the reference voltage and the display time of each EL element is controlled by the period until the relation between the signal voltage and reference voltage is inverted, to thereby control the light emission time in one frame period.
Patent TW-508805-B (TW)
Title: Memory architecture permitting selection of storage density after fabrication of active circuitry
Inventor: BYUN HYUN-GEUN
IPC: H01L27/02
Filed: 2001-11-22
Granted: 2002-11-01
Abstract: A generic wafer includes memory units separated by scribe lanes. Memory chips of different storage capacities can be produced from different numbers of memory units on the generic wafer by forming one or more interconnect layer specialized according to a desired storage capacity and cutting the wafer using a sawing pattern according to the desired storage capacity. The specialized layer can be formed using different masks sets that form a different conductive pattern for each storage capacity or forming a generic interconnect structure with fuses that are cut to select the storage capacity of the memory chips
Patent TW-I297367-B (TW)
Title: Dyeable polyolefin fibers and fabrics
Inventor: LI SHENG-SHING
IPC: A41D31/00
Filed: 2001-12-04
Granted: 2008-06-01
Abstract: Polyolefin fibers, filaments and fabrics made therefrom which comprise a melt blend which comprises(A) a polyolefin; and(B) at least one polyetheresteramide which contains aromatic diol-derived sections,exhibit excellent durable dyeability. The fabrics are useful in woven garments, carpeting, furniture and automobile upholstery, woven industrial fabrics, non-woven absorbents used in disposable diapers, non-woven garments including disposable medical garments, filter media, synthetic paper and the like.
Patent TW-511281-B (TW)
Title: A high performance intermediate stage circuit for a rail-to-rail input/output CMOS operational amplifier
Inventor: LIN XIJIAN
IPC: H03F3/45
Filed: 2001-12-11
Granted: 2002-11-21
Abstract: An intermediate stage for a rail-to-rail input/output CMOS opamp includes a floating current source separating two current mirrors (151-154, 155-158), where the ideal current source includes a floating current mirror (500, 501, 502, 503, 504, 505) enabling an output quiescent current to be provided which does not vary with changes in the voltage rails or the common-mode input voltage, and enabling elimination of input offset caused by the mismatch of the two current sources (164, 166). The NMOS transistor (502) has a source-drain path provided in series with a PMOS transistor (505) serving to connect the current mirrors (151-154) and (155-158) and to eliminate input offset. The source of transistor (500) is separated from the VSS and VDD rails by a PMOS transistor 503 and current source (508) enabling the current mirror (500, 501, 502, 503, 504, 505) to float so that transistors (502) and (505) will each have a gate to source bias voltage independent of changes in the voltage on the voltage supply rails VDD and VSS and independent of any input common-mode voltage offset. Voltage clamping transistors (600) and (602) can further be included to enable the current mirror transistors (151-154) and (155-158) to be low voltage devices to increase overall operation speed and device matching.
Patent TW-569425-B (TW)
Title: Dynamic flip flop
Inventor: SHIBUYA YOSHIHIRO
IPC: H03K19/00
Filed: 2001-12-11
Granted: 2004-01-01
Abstract: It is intended to provide a dynamic flip flop that prevents a floating signal from maintaining a voltage below a substrate voltage level in a P-type semiconductor substrate and that prevents a floating signal from maintaining a voltage exceeding the substrate voltage level in an N-type semiconductor substrate. In the dynamic flip flop, an N-type MOSFET (5) controlled by an output signal MX from an inverter (2) and an N-type MOSFET (6) controlled by an output signal Q from an inverter (4) are provided as switches for short-circuiting a signal M and a signal QX to be brought into a floating state to a substrate.
Patent TW-584790-B (TW)
Title: Method of using variably sized coating particles in a mono component developing system
Inventor: SCHEIN LAWRENCE B
IPC: G03G13/08
Filed: 2001-12-14
Granted: 2004-04-21
Abstract: The present invention is directed to a non-contact, single-component developing system for electrophotographic machines that effectively reduces the impact of adhesion forces on the development process. The developing system of the present invention utilizes a single-component toner that tends to reduce the adhesion forces that hold the toner particles on a toner support member. Preferably, the toner is combined with large and small silica particles having a concentration by weight that results in an optimum surface coverage of toner particles by large and small silica particles that facilitates a reduction in the adhesion forces holding the toner particles on the toner support member.
Patent TW-I228657-B (TW)
Title: Virtual set cache that redirects store data to correct virtual set to avoid virtual set store miss penalty
Inventor: HOOKER RODNEY E
IPC: G06F12/10
Filed: 2001-12-28
Granted: 2005-03-01
Abstract: A virtual set cache that avoids virtual set store miss penalty. During a query pass of a store operation, only the untranslated physical address bits of the store address are used to index the cache array. In one embodiment, the untranslated physical address bits select four virtual sets of cache lines. In parallel with the selection of the four virtual sets, a TLB translates the virtual portion of the store address to a physical address. Comparators compare the tags of all of the virtual sets with the translated physical address to determine if a match occurred. If a match occurs for any of the four virtual sets, even if not the set specified by the original virtual address bits of the store address, the cache indicates a hit. The matching virtual set, way and status are saved and used during the update pass to store the data.
Patent TW-593677-B (TW)
Title: Bio-chip-type flow cytometer (FCM) bio-detector with fiber optical type barcode carrier chip
Inventor: JANG RUNG-SEN
IPC: C12Q1/04
Filed: 2001-12-31
Granted: 2004-06-21
Abstract: A bio-chip-type flow cytometer (FCM) bio-detector with a fiber optical type barcode carrier chip mainly includes a bio particle (e.g. protein, antibody, bacteria, or deoxyribonucleic acid (DNA)) added on an optical fiber carrier installed with a barcode. The optical fiber carrier containing a bio particle is injected into a chip-type FCM according to the invention. The carrier is delivered to a detector in a cellular detection device hydraulically or by a suction force. The detector senses the barcode on the carrier for identifying the type, amount and other bio parameters of the bio particle assayed by the FCM.
Patent TW-528913-B (TW)
Title: Device and method for positional adjustment of light modulator
Inventor: KITABAYASHI MASASHI
IPC: G02B7/00
Filed: 2002-02-27
Granted: 2003-04-21
Abstract: The present invention discloses a device and method for positional adjustment of light modulator. The positional adjustment device comprises a luminous flux detector (40) capable of directly taking in a luminous flux ejected from a cross dichroic prism (150) by CCD cameras (41) through beam splitters (451), whereby the size of the positional adjusting device can be reduced remarkably since a position can be adjusted without using a conventional screen for projection, and a working area can be utilized efficiently since an installation space for the positional adjustment device is less required.
Patent TW-515766-B (TW)
Title: Method and device for detecting distance by car reversing radar
Inventor: LI SHR-SHIUNG
IPC: G01S15/931
Filed: 2002-03-08
Granted: 2003-01-01
Abstract: This invention provides a method and device for detecting distance by a car reversing radar. The method comprises the steps of: pre-storing a set of threshold values for determining distance in a memory; taking multiple samples of reflection signals measured by a plurality of sensing transceivers and comparing the sampled values to the threshold values so as to determine whether an obstacle is behind the car and the distance of the obstacle from the car body. A circuit adopted in this method includes: a CPU switching between multiple sensing transceivers via a channel selecting unit for controlling the surveying signals transmitted by the transceivers or receiving the reflection signals. The reflection signals as received are converted into digital signals by an A/D converting circuit and then input to the CPU for determination of the distance that represents the distance of the obstacles from the car body.
Patent TW-593708-B (TW)
Title: Ion-beam deposition process for manufacturing attenuated phase shift photomask blanks
Inventor: CARCIA PETER FRANCIS
IPC: G03F1/32
Filed: 2002-04-19
Granted: 2004-06-21
Abstract: An ion-beam deposition process for fabricating attenuating phase shift photomask blanks, capable of producing a phase shift of 180 DEG, and which can provide tunable optical transmission at selected lithographic wavelengths < 400 nm, comprising at least one layer of material of general formulae MzSiOxNy or MzAIOxNy, is described.
Patent TW-538328-B (TW)
Title: System and method for filtering output in mass flow controllers and mass flow meters
Inventor: TARIQ FAISAL
IPC: G01F1/00
Filed: 2002-04-26
Granted: 2003-06-21
Abstract: Embodiments of the present invention provide a method for filtering an indicated flow. One embodiment of the present invention can include the steps of (i) determining if the indicated flow is within an allowable deviation of a baseline, (ii) if the indicated flow is within the allowable deviation, outputting the indicated flow as the filtered indicated flow, and (iii) if the indicated flow is not within the allowable deviation, outputting a value that is within the predefined range as the filtered indicated flow. This embodiment of the present invention can also include determining if the indicated flow has exceed a buffer. If the indicated flow has not exceeded the buffer, one embodiment of the present invention can continue to output the value that is within the allowable deviation. If, however, the indicated flow has exceeded the buffer, a timer can be started. If the indicated flow does not return to within the allowable deviation before the timer reaches a clock limit, the embodiment of the present invention can output the indicated flow, which remains outside of the buffer, as the filtered indicated flow. Another embodiment of the present invention can include the steps of (i) filtering the indicated flow to derive an intermediate filtered indicated flow, (ii) deriving a weighted first derivative of the intermediate filtered indicated flow, and (iii) outputting a filtered indicated flow comprising the sum of the intermediate filtered indicated flow and the weighted first derivative of the intermediate filtered indicated flow.
Patent TW-563132-B (TW)
Title: Common DRAM controller supports double-data-rate and quad-data-rate memory
Inventor: LAI JIIN
IPC: G06F12/00
Filed: 2002-06-18
Granted: 2003-11-21
Abstract: A system of present invention uses single memory controller to support both double-data-rate (DDR) memory and quad-data-rate (QDR) memory. This memory controller provides the flexibility to support both DDR and QDR memory in the same system. Furthermore, since the memory controller allows dynamically switch between two operation modes, it allows to access both DDR and QDR memory in a cycle-by-cycle basis.
Patent TW-I306870-B (TW)
Inventor: YAMANE KAZUYUKI
IPC: C08G63/89
Filed: 2002-07-05
Granted: 2009-03-01
Abstract: The invention provides a polyester production process by bulk polymerization in a reactor, wherein the volume of the resulting polyester is shrunk for a release from the inner surface of the reactor, so that the polyester can be recovered in the form of a bulky mass. The invention also provides a reactor for bulk polymerization for polyester, which comprises an inner surface that enabling the resulting polyester to be released therefrom upon its volume shrinkage.
Patent TW-548845-B (TW)
Title: Schottky barrier diode and method for producing the same
Inventor: ASANO TETSURO
IPC: H01L29/47
Filed: 2002-07-22
Granted: 2003-08-21
Abstract: Conventionally, the miniaturization of chip for schottky barrier diode is difficult owing to the mesa etching and the thick polyimide layer, and the characteristics of schottky barrier diode is hard to enchanced for the distances between electrodes. Besides, the control of etching the schottky bonding spot when making a schottky barrier diode is also difficult. In the present invention, a planar schottky barrier diode of compound semiconductor without mesa and polyimide is obtainable by forming an InGaP layer on substrate surface and arranging an n-type ion implanting area. The reduction of chip and the enhancment of characteristics in high frequency is attainable because the distances between electrodes can be closer. In addition, a schottky barrier diode with good reappearance is producible because the etching of GaAs is no longer needed when forming a schottky electrode.
Patent TW-565896-B (TW)
Title: Silicon semiconductor substrate and process for producing the same
Inventor: TACHIKAWA AKIYOSHI
IPC: C30B15/00
Filed: 2002-08-08
Granted: 2003-12-11
Abstract: To extend the depth of the denuded zone or the depth of the void type defect and a locally densified portion produced by nitrogen segregation to a be deeper than 12 mum in a semiconductor substrate cut out from a silicon single crystal ingot produced by Czochralski method or magnetic field-applied Czochralski method. A semi conductor substrate after heat-treated in a non-oxidizing atmosphere has the characteristics that the depth of the denuded zone may be greater than 12 mum or the defect-free depth of the void type defect is greater than 12 mum and the substrate has a locally densified portion produced by nitrogen segregation and exhibiting a signal strength two or more times the average signal strength at the depth of 12 mum or more below the surface thereof when measuring the concentration of nitrogen by using secondary ion mass-spectroscopy, and the density of the crystal defect of oxygen precipitates is 5x10<8>/cm<3> or more, and the said substrate is produced by heat-treating for at least one hour at the temperature of 1200 DEG C or more in a non-oxidizing atmosphere.
Patent TW-550758-B (TW)
Title: Test key and test method for detecting whether the overlay of bit line contact and active area of DRAM is normal
Inventor: WU TIE-JIANG
IPC: G11C29/02
Filed: 2002-08-09
Granted: 2003-09-01
Abstract: A test key for detecting whether the overlay of bit line contact and active area of DRAM is normal. The test key is deposited in the scribe line region of a wafer. In the test key of the present invention, a banding active area is deposited in the scribe line region and has a center. A bit line contact is deposited at the center of the banding active area. A bit line has a center connects to the bit line contact, and has a first terminal and a second terminal, and the bit line is substantially perpendicular to the banding active area. Two plugs are deposited above the two ends of the banding active area respectively and are coupled to the banding active area below.
Patent TW-576968-B (TW)
Title: Computer hard disk group management system and method
Inventor: CHEN JR-WEI
IPC: G06F12/00
Filed: 2002-09-18
Granted: 2004-02-21
Abstract: A computer hard disk group management system and method can be adapted to be installed in a computer platform, such as a desktop computer, a notebook computer or a network server, and the computer platform is connected to at least two or more than two physical hard disk devices, such as internal hard disk of computer, external hard disk of computer, network hard disk externally connected and so forth, allowing user to conduct group management of these physical hard disks. The computer hard disk group management system is featured by providing user the following functions: a grouping function, an anti-grouping function, a file reorganizing function, a hard disk adding function and a hard disk removing function, allowing users to more efficiently carry out hard disk file management task.