Patent GB-1325019-A (GB)
Title: Semiconductor devices
IPC: H01L21/74
Filed: 1970-11-06
Abstract: 1325019 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 6 Nov 1970 [11 Nov 1969] 52916/70 Heading H1K An integrated semi-conductor circuit (Figs. 1, 2) comprises Si wafer 1 surface oxidized at 3 with N-type region 4 adjoining the surface, in which three lateral PNP transistors T 1 , T 2 , T 3  are provided with emitter and collector zones 18, 19 and a common N-type base zone which is part of region 4. A further transverse NPN transistor T 4  is formed having its collector in region 4, which comprises an epitaxial N-type Si layer on P-type substrate 5. P-type channels 6 extending through the epitaxial layer provide PN junctions 7 separating region 4 from the remainder of the body, and Al layers 8 on the oxide interconnect the transistors into the circuit of Fig. 3. To ensure equality of emitter currents in T 1 , T 2 , T 3  the emitters are D.C. connected over layers 8 to a bus 20 of Al or a highly doped diffused zone, and the active parts of the common base are held at the same potential by a highly doped N-type zone of region 4 comprising a diffused buried layer 9 and extensions 10 to the surface; surrounding transistors T 1 , T 2 , T 3  within the body which has higher conductivity than region 4; so that the common base currents flow entirely in the highly doped zone, which comprises a diffused highly doped N-type partition 12 separating the individual transistors T 1 , T 2 , T 3 , while transistor T 4  is outside the doped zone. The PN junction between the collector zone of T 3  and extension 10 is shorted at the surface by collector contact 13 in a window of the oxide layer and the collector of T 4  is connected over this contact and the doped zone to the common base of T 1 , T 2 , T 3 . In fabrication layer 9 is As diffused into P-type substrate and covered with epitaxial layer 4 on which oxide layer 3 is thermally formed. Windows are etched over photo-resist for Bo diffusion to form P channels 6, and regions 10, 12 are formed by P diffusion over photomasks. The base of T 4  and collector and emitter zones of T 1 , T 2 , T 3  are simultaneously in-diffused, followed by indiffusion of the emitter of T 4 . Contact windows are etched, and Al layers and contacts are provided by masking, etching, and vapour deposition. In a modification (Figs. 4, 5, not shown) the highly doped zone may be entirely covered by the oxide layer, with external connections of the collectors of T 3  and T 4  and an interposed aluminium interconnection overlying the oxide layer. In further modifications the highly doped zone may comprise a buried N-type layer and partitions in-diffused from the surface leaving a small gap of lower doped material therebetween (Fig. 6, not shown) or partitions out-diffused from the buried layer towards the surface from which they are separated by a small gap of lower doping (Fig. 7, not shown); two lateral transistors being provided within the highly doped zone.  Dissimilar elements may be provided within the enclosure of the highly doped zone, e.g. an NPN and a PNP transistor with respective collector and base forming a common N-type zone held at uniform potential by the highly doped zone (Fig. 8, not shown); the latter being provided with a surface contact on a partition thereof. The highly doped regions may be formed by epitaxial deposition or ion implant, and other semi-conductor materials may be used, silicon nitride or alumina used for surface insulation, or the conductivity types reversed. The structure is applicable to plural PN diodes, Schottky diodes, or lateral thyristors having common zones.