baber/WOPTO huggingface dataset:
Patent TW-470928-B (TW)
Title: Write drive apparatus
Inventor: VEENSTRA HUGO
IPC: G11B5/09
Filed: 2000-07-24
Granted: 2002-01-01
Abstract: The invention provides a write driver circuit for writing an information signal on a magnetic record carrier. The write driver circuit comprises a first and a second input terminal (20, 22) for receiving the information signal. A first current sink (24) is available, having a first transistor (T3) of a first type, having a first main electrode coupled to the first point of constant potential (+), having a second main electrode coupled to the first input (34) of a write head combination (32) via a first impedance (38), and a control electrode coupled to the first input terminal (20). A second current sink (28) is available having a second transistor (T4) of the first type, having a first main electrode coupled to the first point of constant potential (+), having a second main electrode coupled to the second input (36) of the write head combination via a second impedance (42), and a control electrode coupled to the second input terminal (22). A first current source (26) is available having a third transistor (T1) of the first type, having a first main electrode coupled to the first input (34) of the write head combination, having a second main electrode coupled to a second point of constant potential (-), and a control electrode coupled to the first input terminal (20). Further, a second current source (30) is available having a fourth transistor (T2) of the first type, having a first main electrode coupled to the second input (36) of the write head combination, having a second main electrode coupled to the second point of constant potential (-), and a control electrode coupled to the second input terminal (22).
Patent TW-472213-B (TW)
Title: Method of and apparatus for displaying measured quantity, recording medium, and program
Inventor: SHICHISAWA TAKAMASA
IPC: G04G9/00
Filed: 2000-09-08
Granted: 2002-01-11
Abstract: First and second block groups(110, 112) are arrayed and displayed around respective circles of smaller and larger diameters. A measured physical quantity is expressed by the positional relationship of blocks (114a, 116a) to be colored among blocks (114, 116) of the block groups (110, 112) and the amounts of coloring on the blocks (114a, 116a) to be colored.
Patent TW-483293-B (TW)
Title: Circuit daughter board and circuit board structure for stabilizing power source and strengthening grounding
Inventor: JANG NAI-SHUEN
IPC: H05K1/14
Filed: 2000-11-10
Granted: 2002-04-11
Abstract: The present invention relates to a kind of circuit daughter board for stabilizing power source and strengthening grounding. The invention uses a double-layer printed circuit daughter board having large area power source layer and grounding layer to cover motherboard signal line with insufficient grounding and to connect the grounding as well as power source of motherboard signal line with insufficient grounding so as to reach the purpose of stabilizing power source and strengthening grounding, and to prevent the signal line from being interfered. Therefore, both stability and reliability of signal line are increased.
Patent TW-575838-B (TW)
Title: Automatic recovery method of BIOS memory circuit in memory apparatus containing dual BIOS memory circuits
Inventor: LIN HUO-YUAN
IPC: G06F9/06
Filed: 2000-12-07
Granted: 2004-02-11
Abstract: An automatic recovery method of defective BIOS memory circuit in a computer system having memory apparatus containing dual BIOS memory circuits is disclosed in the present invention. A computer system contains a memory apparatus that includes a main BIOS memory circuit and a recovery BIOS memory circuit, which respectively store the first BIOS program and the second BIOS program for starting the operation of computer system. In addition, the main BIOS memory circuit or the safe recovery BIOS memory circuit even contains a BIOS flash utility such that, when the computer system is boosted, the chip enable circuit in the computer system first enables the recovery BIOS memory circuit and uses an error detection circuit to check and find if there is any error contained in the first BIOS program stored in the main BIOS memory circuit. If the first BIOS program stored in the main BIOS memory circuit contains error, the content of safe recovery BIOS memory circuit is used to program the main BIOS memory circuit via the BIOS flash utility. Then, the chip enable circuit disable the safe recovery BIOS memory circuit and enable the main BIOS memory circuit so as to continue the boosting procedure of computer system from main BIOS memory circuit.
Patent TW-I224098-B (TW)
Title: High yields, high purity melamine manufacturing process
Inventor: NOE SERGIO
IPC: C07D251/62
Filed: 2000-12-08
Granted: 2004-11-21
Abstract: The process to recover both melamine and oxyaminotriazines (OAT) from the mother liquors of melamine crystallisation comprising the following steps: (a) addition to a melamine and OAT containing aqueous solution at high temperature of an alkaline agent until the solution pH reach a value equal or higher than 11; (b) most of melamine crystallisation by solution cooling; (c) separation and recovery of precipitated melamine; (d) acidification of the obtained solution, after precipitated melamine separation, in order to reach a pH of about 7; (e) the suspension obtained in (d) above after precipitated melamine recovery, is subject to filtration according to tangential filtration technique obtaining a clear permeate which contains as a solution all melamine which did not precipitate in step (b) and a retentate comprising of OAT dispersion; (f) OAT deprived mother liquors from (e) are recycled to row melamine solution preparation step; in such a way almost the total amount of melamine, which did not precipitate in step (b), is recovered; (g) OAT are recovered from step (e) retentate by using any conventional separation technics.
Patent TW-550940-B (TW)
Title: An apparatus for determining the best image from a dual resolution photo sensor
Inventor: SPEARS KURT E
IPC: H04N1/193
Filed: 2001-01-02
Granted: 2003-09-01
Abstract: A method of combining the low resolution, higher signal-to-noise information with the high resolution, low signal-to-noise information created by a dual resolution CCD is disclosed. A method of combining low-resolution information with high-resolution information created by a dual resolution photo-sensor array, comprising: determining a high-resolution signal for a high-resolution pixel; determining a noise level (308) for the high-resolution pixel; determining a low-resolution signal for a corresponding low-resolution pixel; replacing the high-resolution signal (310) with the low-resolution signal as a function of the high-resolution signal, the low resolution signal, and the noise level of the high-resolution pixel.
Patent TW-497122-B (TW)
Title: Semiconductor device and manufacturing method thereof
Inventor: YAMAZAKI SHUNPEI
IPC: G02F1/136
Filed: 2001-03-07
Granted: 2002-08-01
Abstract: A means of forming unevenness for preventing specular reflection of a pixel electrode, without increasing the number of process steps, is provided. In a method of manufacturing a reflecting type liquid crystal display device, the formation of unevenness (having a radius of curvature r in a convex portion) in the surface of a pixel electrode 108d is performed by the same photomask as that used for forming a channel etch type TFT, in which the convex portion is formed in order to provide unevenness to the surface of the pixel electrode and give light scattering characteristics.
Patent TW-527408-B (TW)
Title: Method for polishing a memory or rigid disk with an amino acid-containing composition
Inventor: FANG MINGMING
IPC: B24B37/00
Filed: 2001-03-30
Granted: 2003-04-11
Abstract: A method of planarizing or polishing the surface of a memory or rigid disk comprising abrading at least a portion of the surface with (i) a polishing composition comprising an oxidizing agent selected from the group consisting of persulfates and peroxides, an amino acid, and water, and (ii) an abrasive.
Patent TW-562952-B (TW)
Title: Rod lens array
Inventor: FUKUZAWA TAKASHI
IPC: G02B13/00
Filed: 2001-04-12
Granted: 2003-11-21
Abstract: A rod lens array has a construction in which a number of rod-shaped lens elements are arrayed in at least one row between two side plates, and the clearances are filled with resin to form a single integral unit. Two side plates are formed of glass plates, the surfaces of these two glass plates facing the lens elements are flat and smooth, the outer surfaces on the opposite sides are formed with reflection-preventing portions, the side surfaces of both of the glass plates on the beam-exit side are formed with beam-shielding zones from the outer edges inwardly along almost the whole length. The width of the light-tight zone Ts satisfies the relation; Tg > Ts > Tg-ZxDx{2+3< 1/2> x(n-1/{2x(Tc-Z, where Tg is a thickness of the glass plate, D is a diameter of lens element, Z is a length of lens element, Tc is a conjugate length, and n: number of columns of lens element. The glass plate may be made thinner instead of providing a light-tight zone.
Patent TW-508694-B (TW)
Title: Devices and methods for addressing optical edge effects in connection with etched trenches
Inventor: HSHIEH FWU-IUAN
IPC: H01L21/8242
Filed: 2001-07-16
Granted: 2002-11-01
Abstract: In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided. The structure comprises: (l) a substrate of a first conductivity type; (2) a body region on the substrate having a second conductivity type, wherein the peripheral and internal trenches extend through the body region; (3) an insulating layer that lines each of the peripheral and internal trenches; (4) a first conductive electrode overlying each insulating layer; and (5) source regions of the first conductivity type in the body region adjacent to the each internal trench, but not adjacent to the at least one peripheral trench.
Patent TW-526437-B (TW)
Title: Photolithography rework analysis method and system
Inventor: LI KUEN-BEI
IPC: H01L21/66
Filed: 2001-08-08
Granted: 2003-04-01
Abstract: A photolithography rework analysis method and system, wherein the photolithography rework analysis method is applied in the network server and the user computer system containing browser interface. The photolithography rework analysis method comprises: storing the initial data of each machine in the network database, wherein the network database stores the rework data of the machine conducting the photolithography rework operation; then, inputting the analysis time point from the browser interface, and transmitting the analysis time point to the network server; when the network server obtains the corresponding request data from the network database based on the analysis time point, it will display the request data on the browser interface; wherein, the rework data contained in the network database comprises the report generation time, product number, production line ID, station ID, department ID, product ID, mask, rework sheet counts, measuring machine, production machine, worker name, rework reason ID, rework reason name, current status, chip lot notes, rework time and working area.
Patent TW-I231086-B (TW)
Title: Device for controlling interactive voltage/current converter with a single bus
Inventor: LIU JING-MENG
IPC: H02M1/00
Filed: 2001-08-20
Granted: 2005-04-11
Abstract: This invention relates to a device for controlling interactive voltage/current converter with a single bus. Its hardware structure comprises of the devices, which make use of the electric characteristics for the circuit hardware to generate and receive a tri-state control signal waveform structure of three control signals. The circuit also carries out post-reception interpretation to realize control over the interactive voltage/current converter with the feature of one single bus. It reduces bus layout area and reduces wiring costs.
Patent TW-594313-B (TW)
Title: Frame for holding a rectangular display panel having an image display surface and image display device
Inventor: NATSUYAMA YOSHIFUMI
IPC: G02F1/1333
Filed: 2001-08-22
Granted: 2004-06-21
Abstract: An upper frame comprises a base part, end parts and side walls. The base part has a picture-frame shape continuous in the circumferential direction. The base part has four inner limbs, and the end parts extend from the inner limbs. In a state in which the end parts do not press a liquid crystal display panel, the end parts are bent relative to the base part in the direction of the liquid crystal display panel which is to be placed, i.e., in the direction in which the liquid crystal display panel is to be pressed. Considering the relation to the side walls, each of the end parts forms an acute angle. The side walls are pendent from outer limbs of the base part at a substantially right angle and are continuous in the circumferential direction.
Patent TW-526276-B (TW)
Title: Device for especially depositing crystalline layers on one or more crystalline substrates
Inventor: JUERGENSEN HOLGER DR
IPC: C30B25/14
Filed: 2001-08-24
Granted: 2003-04-01
Abstract: The invention relates to a device for depositing especially, crystalline layers onto one or more substrates, especially substrates which are also crystalline, in a process chamber (1): using reaction gases guided into the process chamber (1) undergo pyrolytic reaction; the device comprises a rear-heatable support plate (3) which forms a wall of the process chamber, can especially be heated with a high frequency, consisting of especially inertly coated graphite; a gas inlet mechanism (6) which is located in the center of the process chamber (1) having a circular cross-section, and which is allocated to a cover plate (4) parallel to the support plate (3); and a gas outlet ring (5) which forms the outer wall of the process chamber (1) and which has a plurality of radial gas outlets (25). According to the invention, the gas outlet ring (5) consists of solid graphite in order to keep the isothermal profile inside the process chamber as flat as possible.
Patent TW-524915-B (TW)
Title: Soundproof wall structure
Inventor: PARK KI-SOUNG
IPC: E04B1/74
Filed: 2001-09-10
Granted: 2003-03-21
Abstract: This invention provides a soundproof wall structure to be used at places normally of heavy noise, such as super highways, general roads, subways, high-speed rails, factories, schools, hospitals, and airports. The glass velvet (polyester fiber) firmly fixed in between the front and back soundproofing boards will widen sound-absorbing areas to enhance sound-absorbing effects. One of the characteristics of this invention is that it is able to reduce most noise of impact sound and unregulated wind caused by high-speed vehicles.
Patent TW-543256-B (TW)
Title: Cable and wire connector
Inventor: LIN YOU-JIA
IPC: H02G15/02
Filed: 2001-10-08
Granted: 2003-07-21
Abstract: The present invention relates to a cable and wire connector. Particularly, the invention provides a cable connector capable of making the covering object and insulating body of cable conduct simple and true connection and branching with the adjacent cable without having any gap. The connector structure is provided with the followings: plural connection pins for directly inserting each conduction wire terminal having plural conduction wires and cables; an insulating handle portion for holding connection of plural connection pins; an insertion auxiliary implement, which is inserted in between the conduction cable wires; and an outer fixing metal component, which is mounted on the cable terminal part inserted by the connection pin. Through the use of plural connection pins at both terminals of the connector and the conformation to the separating cable wire strands of insertion auxiliary implement, plural connection pins are directly inserted by corresponding to each wire strand of both connecting cables, and are fixed by the corresponding clamp of the outer fixing meal component. Thus, it is capable of easily and quickly obtaining the connection or branching of cable. In addition, these plural connection pins are wrapped by the cable strands when being inserted to connect, thereby obtaining an excellent conduction function of connection.
Patent TW-523850-B (TW)
Title: Apparatus for measuring temperatures of plural physically separated locations on a substrate in a plasma processing system
Inventor: JOHNSON SHANE R
IPC: G01K11/12
Filed: 2001-10-12
Granted: 2003-03-11
Abstract: A method and system for using specular reflection spectroscopy to measure a temperature of a substrate. By reflecting light from a substrate, the temperature of the substrate can be determined using the band-edge characteristics of the wafer. This in-situ method and system can be used as a feedback control in combination with a variable temperature substrate holder to more accurately control the processing conditions of the substrate. By utilizing a multiplicity of measurement sites the variation of the temperature across the substrate can also be measured.
Patent TW-514621-B (TW)
Title: Improved method of fabricating thin film bulk acoustic resonator (FBAR) and FBAR structure embodying the method
Inventor: RUBY RICHARD C
IPC: H01L41/22
Filed: 2001-11-01
Granted: 2002-12-21
Abstract: A method for fabricating an acoustic resonator, for example a thin film bulk acoustic resonators (FBAR), on a substrate (302). A depression (306) is etched and filled with sacrificial material. The FBAR is fabricated on the substrate (302) spanning the depression (306), the FBAR having an etch hole (320). The depression (306) may include etch channels (307) in which case the FBAR may include etch holes (322, 324) aligned with the etch channels (307). A resonator resulting from the application of the technique is suspended in air and includes at least one etch hole (320) and may include etch channels (307).
Patent TW-542776-B (TW)
Title: Method for producing acrylic diamond-shaped decoration of metal core without stem
Inventor: JIAN YUNG-TIE
IPC: B29C43/00
Filed: 2001-12-13
Granted: 2003-07-21
Abstract: A method for producing an acylic diamond-shaped decoration of a metal core without stem comprises designing a screw nail hole at the center of a plated metal body of an acrylic diamond-shaped decorative; screwing in a screw nail having a cut face on the stem thereof into the hole; installing the nail stem into the fastening hole at the center of the bottom of the mold chamber fastening by a pneumatic stem; squeezing a molten acrylic into the mold; and demolding the product to form an acrylic diamond-shaped decorative of metal core without stem.
Patent TW-516181-B (TW)
Title: Manufacturing method of semiconductor device dual damascene structure
Inventor: JANG DING-JANG
IPC: H01L21/768
Filed: 2001-12-31
Granted: 2003-01-01
Abstract: A manufacturing method of semiconductor device dual damascene structure is disclosed, which utilizes x-ray to selectively solidify the low dielectric constant dielectric layer that is deposited by spin coating. The part of dielectric layer not solidified will dissolve in the spin coating solvent that is used to form dielectric material of the dielectric layer and the needed dual damascene structure is obtained. The traditional photolithography and etch steps are not necessary according to the invented method. Besides, because the x-ray wavelength is very short, high-resolution pattern definition can be provided to apply to the nano-meter grade semiconductor process.
Patent TW-533542-B (TW)
Title: Manufacturing method of damascene copper wire
Inventor: JENG SHUANG-MING
IPC: H01L21/768
Filed: 2002-01-15
Granted: 2003-05-21
Abstract: The present invention provides a manufacturing method of damascene copper wire, which comprises first providing a semiconductor substrate having a surface formed thereon a dielectric layer which has a trench; then, forming a diffused barrier layer in the trench and using an electro-chemical depositing method to form a copper layer filled in the trench; next, forming a nucleation layer on the surface of the copper layer to provide nucleation sites for the copper layer; and making the copper layer nucleate and crystallize from the nucleation sites, thereby forming a copper layer with crystal. In accordance with the manufacturing method of the present invention, it is able to make the copper crystal structure more complete and fine, thereby solving the problem of having defects on the surface of copper wire.
Patent TW-594931-B (TW)
Title: Method for preparing nano-carbon and nano-carbon prepared by such method and composite material or mixed material containing nano-carbon and metal fine particle, apparatus for preparing nano-carbon, method for patterning nano-carbon and nano carbon
Inventor: TAKIKAWA HIROFUMI
IPC: C01B31/02
Filed: 2002-03-06
Granted: 2004-06-21
Abstract: A method and a device for preparing electron emission source are disclosed wherein said electron emission source is made by arc discharge to evaporize the subject material so as to generate soot on base plate. Arc discharge is obtainable by using an arc torch for welding or a unit having similar configuration. The subject material contains carbon as main composition. In this invention, a process container is not necessarily required. Torch electrode 10 of arc torch as first electro de and subject material 2 using graphite as second electrode are disposed in opposite. Potential is supplied between torch electrode 10 and subject material 2 to generate arc discharge. Graphite on the end of subject material is exposed to arc discharge to produce soot making it adhered on thee surface of base plate opposite to arc discharge area with a mask having patterned opening interposed there between.
Patent TW-548885-B (TW)
Title: Trainable laser optical sensing systems and methods
Inventor: TATUM JIMMY A
IPC: G01S7/41
Filed: 2002-04-12
Granted: 2003-08-21
Abstract: A laser optical sensing system and method for detecting target characteristics are disclosed. The system includes a laser source (105) with at least two emission apertures from which laser signals are emitted. The system also includes at least one detector (103), which is operationally responsive to the laser source (105). The system includes a microprocessor (101) that is operationally coupled at least one detector (103) for processing signal data, a memory (102) accessible by the microprocessor (101) for storing target characteristics (e.g., unique signals), and at least one software module (106) accessible by the microprocessor for enabling system training and detection operations. In operation, the laser source emits (111) into an environment at least two laser signals, one from each emission aperture. The detector detects (112) the laser signals after the signals pass through the environment, which is occupied by a target, and the microprocessor determines (114) target characteristics based on the matching of laser signals received (113) by the detector(s) and characteristics stored in memory.