Patent EA-001838-B1 (EA)
Title: A multi-functional arithmetic apparatus with multi value states
IPC: G06F7/00
Filed: 1998-02-25
Abstract: 1. A multi-value states multi-functional arithmetic apparatus, characterized in that said apparatus comprises a gating array, which is made of gating devices based on the structure of n rows x m columns, each gating device has at least two input pins and at least one output pin; one of the input pins of each of the gating devices on the same row is connected to each other as a row input contact, the other input pin of each of the gating devices on the same column is connected to each other as a column input contact, variable input value states ( weight ) exist between the row input contacts, similarly, variable input value states ( weight ) exist between the column input contacts, and, there is a correspondence relationship between the input value state of each gating device and its position in the array, the value of the input value state of the row input contact shall be in the range of 0 to (n-1), while the value of the input value state of the column input contact shall be in the range of 0 to (m-1); each output pin of that gating device also has an output value state, an arithmetic relationship exists between the output value state of each gating device and its input value state based on the self organization principle model of the integer cluster, the output pins of those gating devices with the same operational output value state are connected together via an isolating circuit as an output contact, the output value state of the output contact shall be within the range of 0 to (n+m-1); while the output of the output value state is determined via gating of the gating device. 2. The multi-value states multi-functional arithmetic apparatus according to Claims 1, characterized in that said operation relationship is an addition operation, the output value states of each of said gating device is equal to the addition of its row input value state and column input value state; the number of row input contacts is n, the number of column input contacts is m, the number of output contacts is (n+m-1). 3. The multi-value states multi-functional arithmetic apparatus according to Claims 1, characterized in that said operation relationship is subtraction operation, the output value states of each of said gating device is equal to the difference of its row input value state and column input value state; the number of row input contacts is n, the number of column input contacts is m, the number of output contacts is (n+m-1). 4. The multi-value states multi-functional arithmetic apparatus according to Claim 1, characterized in that said operation relationship is a combination of one addition operation and one subtraction operation, the output pins of the gating devices with the identical output value states that are determined by the addition operation relationship are connected together via an isolation circuit as the addition output contact, the output pins of the gating devices with the identical output value states that are determined by the subtraction operation relationship are connected together via an isolation circuit as the subtraction output contact, the number of said row input contacts is n, the number of said column input contacts is m, to number of said output contacts is 2(n+m-1). 5. The multi-value states multi-functional arithmetic apparatus according to Claim 1, characterized in that said operation relationship of said n row x m column gating array is addition, said row input contacts are connected to an input port (A1), said column input contacts are connected to an input port (B1), said output contacts are connected to an output port (C1); wherein further including two n row x m column gating arrays with the operation relationship being subtraction, for one of said two arrays, the row input contacts are connected to an input port (C2), the column input contacts are connected to an input port (B2), the output contacts are connected to an output port (A2); for another of said two arrays, the row input contacts are connected to an input port (C3), the column output contacts are connected to an input port (A3), the output contacts are connected to an output port (B3), the input port (A1) is connected to port (A3), the input port (B1) is connected to the port (B2), the input port (C2) is connected to the port (C3). 6. The multi-value states multi-functional arithmetic apparatus according to any of Claims 1 to 5, characterized in that said gating device is a digital gate, the isolation circuit is digital OR gate. 7. The multi-value states multi-functional arithmetic apparatus according to any of Claims 1 to 5, characterized in that said gating device is an analog transmission gate, said isolation circuit is an operational amplifier. 8. The multi-value states multi-functional arithmetic apparatus according to any of Claims 1 to 7, characterized in that said gating array can form a multi-value states multi-functional arithmetic unit bit slice if equipped with additional external circuits. 9. The multi-value states multi-functional arithmetic apparatus according to Claim 8, characterized in that n = 8, m = 8, said operational relationship of said gating array is an addition operation, said external circuits include: a shifter which accepts lower bit inputs and then takes outputs, a decoder that pre-selects the number system or defines the value states, a number system determination circuit, said bit slice has two input ports, one output port, one pin for carry input, and one pin for carry output. 10. The multi-value states multi-functional arithmetic apparatus according to Claim 8, characterized in that n = 8, m =8, said operational relationship of said gating array is subtraction operation, said external circuits include: a shifter which accepts lower bit borrow inputs and then takes outputs, a decoder that pre-selects the number system or defines the value states, a complementary conversion circuit, a number system determination circuit, said bit slice has two input ports, one output port, one pin for input of the complementary conversion circuit, one pin for output of the complementary conversion circuit, one pin for borrow input, and one pin for borrow output. 11. The multi-value states multi-functional arithmetic apparatus according to Claim 9 or 10, characterized in that the value state and number system are selected and set via said decoder, i.e. the upper limit and number system of the input value states are selected and set within a specific value states range using the decoder. 12. The multi-value states and multi-functional arithmetic apparatus according to Claim 9 or 10, characterized in that said bit slice can not only construct the addition and subtraction arithmetic unit by the form of multiple bit cascade, but also expand the value range of a bit slice via splicing.