Patent UA-93721-U (UA)
Title: generator of a SINGLE PACKAGE CONTAINING FOUR SYMMETRICAL CODE pulse SERIES with programmable time parameters
Inventor: KOROBKOV MYKOLA HRYHOROVYCH
IPC: H03K3/78
Filed: 2014-05-19
Abstract: A driver of a single package which comprises four symmetrical code pulses series with programmable timing parameters multiples of the period of continuous periodic pulse sequence supplied to the input from the crystal oscillator output that comprises two reversible binary counterы having input of synchronization pulses, input of adjustment to addition / subtraction mode , input of permit of synchronous parallel load and input of data loading, input of permit of count mode, input of asynchronous installation of zero state, the overflow output; first (four-input), second (three-input) and third (two-input) elements OR; two inverters; chain of connected in series resistor and capacitor; synchronous D- flip-flop with input of asynchronous installation of zero state; first and second two-input AND elements; first and second OR elements; the common point of connected in series resistor and capacitor is connected to the data input of the first D-flip-flop, to one input of AND elements; output of first AND element is connected to the input of asynchronous installation of D-flip-flop to zero state; the clock input of D-flip-flop forms the input for start pulses; the second input of second AND element is connected to the output of the second OR element one input of which is connected to the output of the D-flip-flop; the output of the second AND element is connected to the inputs of asynchronous installation of counters to zero state; outputs of the bits of the second counter are connected to the inputs of the first element OR; clock inputs of the counters are connected together to form the driver input - input for supply of continuous periodic pulse sequence from the output of external oscillator; parallel loading inputs of the first counter form the driver inputs of adjustment to output pulse set parameters. There are introduced two synchronous DL-flip-flops with inputs of asynchronous installation to zero state; third reversible binary counter which has a synchronization pulse input, input for adjustment to the addition / subtraction mode, input of permit of synchronous parallel loading and inputs for supply loading data, input of permit of count mode, input of asynchronous installation to zero state, the overflow output; fourth element OR; first and second two-input AND-NOT elements, wherein the overflow output of the third counter which forms the output of the driver is connected to the input of permit of synchronous parallel loading, input of the fourth OR element, input of the second counter count mode permit, and the input of the first inverter, its output is connected to the input of permit of counting mode of the third counter, the second input of the first AND element, and inputs of the first and second o AND-NOT elements; the output of the first OR element is connected to the second input of the fourth OR element and the input of the second inverter, which output is connected to the first input of the third OR element and the second input of the first AND-NOT element which output is connected to the counting mode permit input of the first counter; the output of the fourth OR element is connected to the second input of the second OR element and inverted inputs L of the DL-flops; direct output of the first DL-flip-flop is connected to the input D of the second DL-flip-flop and third input of the second OR element; direct output of the second DL-flip-flop is connected to the fourth input of the second OR element; inverted output of the second DL- flip-flop is connected to the D input of the first DL-trigger; the outputs of the bits of the second counter are connected to inputs of the third counter loading data; first counter overflow output is connected to the second input of the third OR element and the second input of the second AND-NOT element; output of the third OR element is connected to the input of adjustment to the summation / subtraction mode of the second counter; output of the second AND-NOT element is connected to the load permit input of the first counter; the clock inputs of the third counter and DL-triggers are connected to the clock inputs of the first and second counters; inputs of asynchronous installation to zero state of DL- triggers and the third counter are connected to the output of the second element AND.