Patent GB-1501608-A (GB)
Title: Multiplexer apparatus
IPC: H04L5/22
Filed: 1975-03-05
Abstract: 1501608 Time division multiplex systems WESTERN ELECTRIC CO Inc 6 March 1975 [11 March 1974] 9069/75 Heading H4M In a T.D. multiplex arrangement two sets of control bits are combined with input data bit streams into a multiplexed output stream. Each multiplex frame includes at predetermined locations a first control bit and its complement and a pair of second control bits. The first and second control bits in a plurality of sequential frames respectively represent two characteristics of the input data streams. The first bits and their complements appear in the first two bit positions of each frame throughout a 24 frame superframe and provide marker bits (101), line protection switching bits (000 or 111) and 18 bits, 3 per multiplexed channel, indicating whether stuffing occurs during the superframe for the particular channel. The second bit pairs appear half way through a frame and indicate the position either of all the odd bits in a frame or all the even bits, alternately frame by frame. These two sets of bits are used in conjunction at the demultiplexer for synchronizing the demultiplexing operation and destuffing. At the multiplex arrangement (Fig. 1) 6 channels carrying data asynchronously at 45 Mk/s. (perhaps derived from a lower rate multiplex) are respectively connected to channel synchronizers 101-106. The channel data bits are stored here and read out on command by read clock signals 109 delivered from a synchronization control 101 under the control of a clock 130. The clock 130 provides signals at the output bit rate of the multiplex. If the number of bits in the synchronizer register falls below a predetermined amount, stuffing is needed and a request is delivered on line 107 to the control circuit 110. This causes the read clock signal 107 to be inhibited so that the input data is not read, and a stuff command is delivered over line 113 or 114 to the multiplexer 121, 122. The system incorporates two multiplexers 121, 122 for odd and even data channels respectively and these operate to interleave data channels and control signals such that frames are formed comprising a single bit and its complement from the control circuit 110, 16 groups of channel bits, two identical parity bits and a further 16 groups of channel bits (Fig. 3 line C). The sequence delivered from each multiplexer is delivered to a modulo 2 adder 145 or 146 where it is scrambled with pseudo random words from a generator 140 (the word complements being applied to 146). Thereafter the two multiplex sequences are interleaved by combiner 180 and passed via a repeater 190 to the output line 200. The parity of the odd and even channels, per frame, is evaluated at 160, 170 respectively and the results combined at 150 such that priority bits for odd and even channels are inserted into alternate frames. The S bits, which are inserted one at the beginning of each frame, together with a complement constitute a word over 24 frames which enables synchronization (by reference to the first three marker bits 101) and destuffing to be established and operates under the control of the clock 180 and the stuff repeat signals derived in turn from the different channels. The demultiplex arrangements (Fig. 2, not shown) are in the main complemntary to the multiplex arrangements in Fig. 1. The received data frames first pass to a repeater which extracts the clock in order to govern the framing and timing control. Thereafter they are applied to a splitter which directs the bits alternately via modulo 2 adders where they are descrambled to demultiplex circuits for the odd and even channels respectively. The demultiplex circuits operate in accordance with commands from a framing control circuit (230) which initially must guess at where the superframes and frames start. Having made the guess, the supposed S and P bits are extracted by the demultiplexer and returned to the framing control where they are inspected using exclusive OR circuits, to determine whether the S bits in three successive frames are 101 and whether, in every appropriate pair of bit positions thereafter (96 bits later) there are two identical (parity) bits. If this condition is not established, then slip commands are given by the framing control to the demuliplexers and the splitter control frame and superframe are correctly positioned. Then the full S bit word from the superframe can be correctly obtained by an S bit receiver (210) and the clock to the desynchronizers in the individual output channels controlled such that appropriate destuffing takes place. Moreover the pseudo random word generator, at the receiver, identical to that at the transmitter, can be appropriately reset and synchronized.