Patent GB-1336542-A (GB)
Title: System for tranferring information
IPC: H04Q11/04
Filed: 1972-02-01
Abstract: 1336542 Automatic exchange systems  PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 1 Feb 1972 [4 Feb 1971] 4710/72 Heading H4K [Also in Division G4] In a system in which an incoming bit stream is initially synchronized against a local clock and then stored in a data store from which any data word can be read out in a different numbered time slot from that in which it arrived, the act of synchronizing may cause data words to be repeated or deleted and this is overcome according to the invention by reading-out each data word at least three times per frame from the data store and then cancelling all the redundant words. The considered TDM, PCM transit telephone exchange of Fig. 1 comprises groups of eight, 32-channel receive highways 100-1, 100-8 which are each terminated by a synchronizer 101. The latter contains four word storage positions into which the contents of successive channels are written at the bit rate of the incoming stream. The positions are read-out at the bit rate of a local clock on to eight-wire highways 102 whereby each incoming serial-bit word is converted into parallel format and occupies a time slot dictated by the local clock. A signal in the synch. channel of each receive highway is effective to set a modulo 32 counter which provides each word read-out of the synchronizer with an identifying time slot number, this being transmitted over highway 103 to a multiplexer 104. The latter multiplexes the 32 words from each of the eight highways in a group into the first 256 of the 512 slots available within an exchange time frame and causes them to be written into respective locations of a data store 107 under the control of time slot address words accompanying them on highway 106. A cyclic control store 109 is primed with the necessary instructions as to when each location should be read out on to superhighway 108, i.e. a time slot interchange function. A receiver 100 is provided for responding only to data words relating to signalling information, such words occupying a particular time slot in each frame. It is the cancellation or repetition of these words that may give rise to errors and which it is the purpose of the invention to overcome. Synchronization.-Each highway incorporates a synchronizer 101 consisting of four wordstorage positions which are accessed sequentially by incoming words formed by eight serial bits. The words are read-out in similar sequential manner but in eight parallel bit format under local clock control. In view of phase differences between the incoming and local clock bit rates a situation can occur where a same word position is being simultaneously read and written. To prevent this, a word, preferably that in the synch. channel, is deleted if the incoming bit rate exceeds the clock, i.e. read-out, rate and is repeated if the clock rate is the higher. This action has the effect of reducing or prolonging by one time slot the period between successive samples of a same channel in their passage along highways 102 and 105. Such a change is not apparent on highway 108 which means that occasionally words will be skipped over or repeated twice during read-out of store 107. So far as speech is concerned this is of little consequence but it is of importance for signalling. Figs. 2 and 3 illustrate the cases where a frame is effectively prolonged and reduced respectively, utilizing as a model a group of three highways each having four channels that are multiplexed into 12 of 24 subslots of a superhighway wherein the first half of a subslot is used for writing purposes and the second half for reading. The corresponding words of a same channel in successive frames are referenced A, B, C, D. Due to repeated reading of a synch. word in the incoming synchronism, the period between the appearance of successive samples of a same speech channel is increased so that during write-in to store 107, a sample B will occur during the second, and not the first, time slot of a succeeding frame, c.f. Fig. 2a, where sample A occurs in the first subslot of the first time slot 1À1 whereas samples B (and of course C, D &c.) occur in the first subslot of the second time slots 2À1 of subsequent frames. It should be realized that this seeming change in position of a channel within a frame is of no consequence to the communicating parties, i.e. cross-talk does not occur, since the identity of every sample is known by virtue of the accompanying time slot number and thus the entry of the sample into the correct word location of store 107 is assured. During non-destructive read-out from the store, however, it will happen that the considered location will be accessed by control store 109 at exactly the same time in every frame, e.g. in the fifth subslot of the first time slot 1À5, so that in the second frame the same word A will be read-out again as the new word has not yet arrived, c.f. Fig. 2b. In the opposite case, i.e. when a synch. word is deleted, the effect in store 107 will be that a new data sample will be written in before a preceding one is read-out, thus causing loss of the said preceding one, c.f. missing C in Fig. 3b. The Figs. 2c and 3c indicate how this defect is overcome by reading each storage location three times, during the fifth subslots of the first, second and third time slots (remember that it is only the signalling word that is of prime interest so that the effective loss of two channels by such. repeated reading is not of too much importance). In the first case, A is read out four times and B only twice but this is sufficient to ensure that B is not lost and that it is authentic. In the second case, it is sample C that is only read twice but again the point is that it is not lost. A logic circuit (Fig. 4, not shown) incorporates a shift register into which the word samples read-out during the three successive slots 1À5, 2À5, 3À5 are fed and comparators for determining the contents of the stages of the shift register and for ensuring that each word is only applied once and then in its appropriate time slot to the signalling data utilization signal.