Patent SE-308468-B (SE)
Inventor: VAN T SLOT A
IPC: H03K3/45
Filed: 1961-04-19
Abstract: 928,742. Electric selective signalling systems. PHILIPS ELECTRICAL INDUSTRIES Ltd. April 19, 1961 [April 22, 1960], No. 14150/61. Class 40 (1). [Also in Group XIX] The invention provides means for switching between information sources, e.g. incoming telegraph line buffer memories, and information receivers, e.g. the inputs to an electronic computer. The circuitry includes gating means for interconnecting the sources and receivers, it being so arranged that, if a source contains information to be transmitted, it is connected as rapidly as possible to a free receiver, it being immaterial to which receiver the source is connected. A priority system may be arranged whereby particular sources are more likely to catch a free receiver than are other sources. A circuit arrangement according to the invention is characterized in that each information source has at least two control signal outlets and one control signal inlet for delivering a control signal indicating whether the information source has or has not to offer information intended for transmission, for delivering a control signal indicating that the information source has transmitted a complete amount of information, and for receiving a control signal indicating that the relevant information source may start to transmit the information stored therein. Each information receiver comprises at least as many control signal outlets as there are information sources for delivering control signals indicating whether the relevant information receiver is free or busy, which control signals are delivered in cyclic order by the control signal outlets of an information receiver at moments of the pulse cycles which are characteristic of the relevant information receiver and which are different for the various information receivers. Each information receiver also has a control signal inlet for receiving a control signal busying the relevant information receiver. Each information source has associated with it a control circuit having at least three control signal inlets, two of which are individually connected to the control signal outlets of the relevant information source and the third of which is multipled to control signal outlets of the information receivers, whilst the control circuit has 2n + 1 control signal outlets, of which n outlets are individually connected to the control terminals of the gates giving the relevant information source access to the information receivers, of which n further outlets are connected to control signal inlets of the information receivers, and of which the (2n + 1)st control signal outlet is connected to the control signal inlet of the relevant information source. Each control circuit is designed so that the reception of the control signal indicating that the relevant information source contains information intended for transmission renders the control circuit sensitive to handling the control signals indicating that an information receiver is free. In the sensitive state, the reception of a control signal indicating that a given information receiver is free causes the transmission of a signal opening the gate which connects the relevant information source to the free information receiver, the transmission of a control signal which makes busy the relevant information receiver, and also of a control signal which allows the relevant information source to transmit information stored therein. The control circuit is simultaneously made insensitive for handling further control signals emanating from the information receivers. The identity of the information receiver giving the control signal " free " is derived from the timing of the pulse cycles at which the relevant signal is received. The control circuit becomes insensitive before it can receive from another information receiver a control signal indicating that it is free. The reception of the control signal indicating that the relevant information source has transmitted a complete amount of information results in the control signal which keeps open a gate of the switching matrix being interrupted, the control member remaining insensitive, however, for handling control signals delivered by the information receivers. A system involving two sources A 1 , A 2  and three receivers C 1 , C 2 , C 3  comprises control circuits F 1 , F 2  and gates P. Each receiver emits a pulse train if it is free, alternate pulses of each train being fed to F 1  and F 2 , and each receiver being characterized by the time position of these pulses in the cycle time of the system. If, for example, C 2 , C 3  emit pulse trains at t 3 , t 5  respectively, and if A 1  indicates it has information to transmit at t 7 , gate P 12  or P 13  will be opened to establish the connection, dependent upon which of the two free receivers is first to send a pulse to control circuit F. A priority system is described with reference to Fig. 2 (not shown), and details of the circuits F, gates P and receivers C are given.