Patent GB-1082873-A (GB)
Title: Apparatus,for example computors, including logic circuits
IPC: H03K19/16
Filed: 1965-02-04
Abstract: 1,082,873. Magnetic core circuits; transistor logic circuits. SIEMENS A.G. Feb. 4, 1965 [Feb. 4, 1964], No. 4978/65. Headings H3B and H3T. A logic device includes a bi-stable magnetic core having control windings and an output winding, at least one control winding being associated with each phase of an N-phase system of N non-coincident pulse trains of equal repetition rate, where N is at least three. One control winding receives pulses of a pulse train of a first phase and these pulses also actuate a switch connected in the circuit of an electronic switching device connected to the output winding. At least two other control windings receive pulses of pulse trains of at least two other phases. In operation, at least one control winding receives all the pulses of its associated pulse train, and at least one of the other control windings receives selected pulses of its associated pulse train, the arrangement being such that the electronic switching device is operated by the switch when the latter receives a pulse, so that a logic operation is performed upon those of the selected pulses received by the logic circuit after receipt by the switch of the immediately preceding pulse of its associated pulse train. Symbolic representation. Figs. 1 and 2 both represent an AND-circuit including a bi-stable core K1. Fig. 2 is a conventional representation, the broken conductors connected to windings 1 and 2 indicating that these conductors are supplied with selected pulses of pulse trains T1, T2. Winding 3 receives all the pulses of pulse train T3. Switch M may be a transistor. In Fig. 1, a black triangle indicates the direction of magnetization of core K1 resulting from current flow in a particular direction in a winding. A horizontal line is provided adjacent the triangle if the winding is to be supplied with selected pulses of a pulse train. The white triangle Dindicates the arrangement comprising transistor Tr1, base winding 4 and output winding 5 shown in Fig. 2. Symbol H represents switch M, the suffix 2 indicating that it is operated by pulses in pulse train T2. The windings associated with the different pulse trains are shown on different sections of core K1, the sections being separated by two horizontal lines. The output appears at 1A. Operation. In the AND-gate the core is set to its " 1 " state by a pulse IT11 and is later switched to its " O " state by pulse IT32. Since no pulse in pulse train T2 was received, switch M (H2) is unactuated and no output results. Pulse IT12 is followed by a pulse IT21 which closes switch H2 and also starts to switch the core to its " O " state. The flux change sets up a base-emitter current in Tr1 which allows emitter-collector current to flow to provide an output. The output current assists switching of core K1. Inhibiting circuit. One arrangement (Fig. 4, not shown), is similar to the AND-circuit except that the switch H is controlled by pulses of the third pulse train T3. An output appears only when a pulse in train T1 is not followed by a pulse in train T2. In a second inhibiting circuit (Fig. 6, not shown), all the pulses of train T1 are supplied to winding 1, selected pulses of train T2 are supplied to winding 2 and selected pulses of train T3 to winding 3, the latter pulses also controlling the switch H. An output is produced only if a pulse of train T3 is not preceded by a pulse of train T2. Inverter (Fig. 8, not shown). All the pulses of train T1 are supplied to winding 1 and all those of train T3 to winding 3 and to the switch H. Winding 2 receives selected pulses of train T2 for inversion. NOR-circuit (Fig. 10, not shown). This is similar to the inverter circuit except that winding 2 is replaced by three separate windings, each supplied with selected pulses from train T2. An output is produced only when none of the windings 2 receives a pulse in the interval between a pulse of train T1 and a pulse of train T3. OR-circuit (Fig. 12, not shown). Two windings (1a 1b are associated with the first phase and each receive selected pulses of train T1, and two windings (a2, b2) are associated with the second phase and each receive selected pulses of train T2. Each of these windings magnetizes the core to its " 1 " state when energized. The third winding and the switch H receive all the pulses of train T3. An input on any winding (1a, 1b 2a, 2b) between consecutive pulses on winding 3 produces an output. Apparatus including a plurality of logic circuits may have a common transistor functioning as switch M for all the logic circuits. The controlling pulses are supplied between the emitter and base of the transistor, the emitterbase circuits of the transistors Tr1 being connected between the emitter and collector of the common switching transistor. An additional switching transistor may be provided for those logic circuits of the apparatus requiring switches controlled by the other phases of the system (Fig. 14, not shown). The switching transistors are in a common emitter configuration. In a modification (Fig. 15) the load current of transistor Tr1 does not flow through the switching transistor, and a bias source is provided, connected to the base of Tr1 to maintain it non-conductive when transistor switch N is open.