Patent GB-1325882-A (GB)
Title: Integrated transistorised buffer circuits for coupling a low output impedance driver to a high input impedance load
IPC: H03K17/567
Filed: 1970-09-07
Abstract: 1325882 Semi-conductor devices RCA CORPORATION 7 Sept 1970 [15 Sept 1969] 42707/70 Heading H1K A PNP bipolar transistor 12 has grounded base 14, low impedance input emitter 16, and collector 20 coupled to load 22 comprising P- conductivity MOS transistor 24 having common source with collector 20, drain 26 connected to negative potential and gate 30 connected to DC bias or a clocked bias signal minimizing power distribution. A common substrate (Fig. 1B) is grounded; and the impedance of 24 is a function of forwatd gate-source bias, while it comprises spaced P-regions 20, 26 defining a conduction channel; the space being overlain by e.g. SiO 2  insulant 31 and superimcumbent gate electrode 30. The source 20 is at positive potential rereferred to drain 26, for one sense of conduction, and the polarities are reversible for the opposite sense. P-region 16 as emitter is spaced by N- substrate 14 as base from P-region 20 as common collector of PNP lateral bipolar transistor 12 and transistor 24. In operation, pulses between +V and O are applied to emitter-base of 12 to produce pulsed current I E  and collector current I c  = αI e  flowing into the high drain-source impedance presented by MOS transistor 24 to produce large voltage swing at source 20, which may be coupled to DTL or TTL logic circuits or linear circuits. In a modification (Fig. 2A) transistor 12 has multiple emitters receiving plural input signals e 1 , e 2 , e 3  and the load 22 incorporates transistor 24 with drain and gate interconnected to a clock signal # 1  with a capacitor 40 interconnecting 20 to a clock signal # 2  also gating a transistor 42 in the output signal. Structurally, a substrate 14 (Fig. 2B) forms a base region containing an emitter region 16a and a collector region 20 also serving as source (or drain) of FET 24 with region 26 as drain (or source); the emitters being multiplied (Fig. 3, not shown). Capacitor 40 comprises an insulant layer overlying part of region 20 and a superimcumbent metallic electrode 41 receiving clock signal # 2 . In operation, clock signal # 1 , precharges 20 negatively if and only if input voltage to 16a, 16b, 16c #0, and 20 is clamped to ground if positive voltage appears on any input and the transistor 12 is conducting. Gating transistor 42 is enabled by clock signal # 2  when it is at -V volts to transmit signal from 20 to the output, and when transistor 12 is conducting the output voltage is held at zero, while when it is non- conducting 20 is pulsed negative by clock signal, and more negative by # 2  across the inherent capacitance between 20 and 14; so that a larger amplitude voltage then -V is coupled out when transistor 42 is enabled. For input, positive is logic 1 and ground is logic 0, while for output ground is logic 0 and negative is logic 1; so that output Vc e 1  + e 2  + e 3  and the circuit functions as a NOR gate for multiple inputs or a logic inverter for single input. The circuit is applicable to memory or multiplex decoding, and the conductivity types may be reversed.