Patent ES-358253-A1 (ES)
Title: A calculator system. (Machine-translation by Google Translate, not legally binding)
IPC: G06F9/355
Filed: 1968-09-17
Abstract: Data processing apparatus comprises a store of which a first portion constitutes a plurality of working registers and a second portion is assigned to general storage, the first and second portions having associated accessing means controlled from logical circuitry and a memory address register respectively, there being control means effective to set the memory address register by reference to an instruction address word accessed from the first portion to access an instruction from the second portion, the instruction being transferred to the first portion, and to set the memory address register using an address from the instruction to access an oper- and from the second portion, the operand being transferred to the first portion. The stored words are of 4, 8 or 16 bytes, each of 8 bits, instruction words being of 4 bytes. The memory address register is a 14-bit (binary) incrementable storage address counter which can address a half-byte in store and can address in either portion of the store. The first (working registers) portion can also be addressed from control logic in dependence on the operation code of the current instruction. A 5-bit digit counter and a 4-bit utility counter can be used for addressing, as alternatives to each other and to the lowest stages of the storage address counter. The digit counter normally counts from 0 to 7 or the reverse, use of the highest and next to highest order stages being permitted only in the cases of 16 and 8 byte words respectively. The utility counter counts down only. During execution of subtract, compare, add and transfer instructions, the storage address counter is set with the address of the first byte of an operand, the digit counter being used to address successive bytes. If complementing of the result is required, the storage address counter can thus address the first byte immediately. During execution of a pack instruction, the storage address counter retains the address of the first byte, successive bytes being addressed using the utility counter which is preset in accordance with the operand length. The utility counter holds a length count in the case of a move instruction also. A working register in the first portion of store holds a 4-byte instruction address word which is read out to the storage address counter via an accumulator which adds 4 to it (since an instruction word has 4 bytes) and also sends it back into store. The storage address counter then addresses store to obtain the next instruction which is used to set an operation code register and is also stored in an 8-byte working register in the first store portion. The instruction may specify the addresses of two operands in direct or indexed form, in the second case referring to selected index registers in the first (working registers) store portion and also specifying displacements to be added to or subtracted from their contents (according to sign bits appended to the index register addresses). In this case the second operand address is calculated and inserted into the storage address counter to access the operand which is then placed in a 16-byte working register in the first store portion. The first operand address is then calculated and inserted into the storage address counter. Both operands are now addressable directly, the second by the logical circuitry and control logic mentioned. Alternatively, the instruction may specify one operand address as above and may either contain the other operand or the address of one of the index registers which contain it. Operation is as before except in connection with the said other operand. The working register portion of store also includes an 8-byte word of command key conditions which can be set or reset manually or can be reset by the programme, and a plurality of 4-byte inputoutput channel registers. An accumulator circuit operable in either binary or decimal mode is provided.