Patent FR-2822309-A1 (FR)
Title: Circuit for translating input switching signals, comprises bistable circuit with two branches and associated current mirror circuits for accelerating the switching of bistable circuit
Inventor: DEBATY PASCAL
IPC: H03K17/10
Filed: 2001-03-19
Abstract: The circuit (100) for translating at least one input switching signal, in particular a pair of mutually inverted signals (PDNI, PDI), comprises a bistable circuit implemented in CMOS technology and having two branches (10, 20) connected between a positive supply voltage terminal (Vcc) and a lower, that is negative or null, supply voltage terminal (Gnd), and associated current mirrors (11, 21) for accelerating the switching of the bistable circuit with the branches (10, 20) allowing the switching of the output transistor of each branch to nonconducting state when the input transistor of that branch switches to conducting state.  Each branch (10, 20) comprises an input transistor (MN1, MN2) and an output transistor (MP1, MP2), and the drain of output transistor of each branch is connected to the drain of input transistor of the same branch by the intermediary of at least one, in particular two voltage-clamping transistors (MC1, MC2; MC3, MC4) connected in series in each branch. The associated current mirror (11, 21) generates the blocking current of the output transistor (MP1, MP2) of that branch which is determined on the basis of the conducting current of the input transistor (MN1, MN2) of that branch. The gate of the first and/or second voltage-clamping transistor (MC1, MC2) of one branch (10) is connected to the gate of the respective voltage-clamping transistor (MC3, MC4) of the other branch (20), and is maintained at a first voltage level (2/3Vcc) and/or at a second voltage level (1/3Vcc); the first voltage level is between the positive supply voltage (Vcc) and the second voltage level (1/3Vcc), and the second voltage level is between the first voltage level (2/3Vcc) and the lower supply voltage (Gnd). The current mirror (11, 21) associated with one branch (10, 20) is connected between the gate of output transistor (MP1, MP2) and the gate of input transistor (MN1, MN2) of that branch. Each current mirror comprises a cascade transistor (MC5, MC6) for cutting the current outside the switching phase. The cascade transistor (MC5, MC6) is of the same type, n or p, as the input transistor (MN1, MN2). The gates of input transistors (MN1, MN2) are controll ed by the input switching signals (PDNI, PDI). In a variant of the circuit, the input transistor (MN1) of branch (10) is controlled by the input switching signal (PDNI), while the gate of the input transistor (MN2) of branch (20) is connected to the drain of the first transistor (MN1) so that the circuit is controlled by one switching signal; a coupling capacitor is connected to the current mirror associated with the other branch (20) for generating the blocking current for the output transistor (MP2) when the input switching signal passes to low logic level. In another variant of the circuit, the input transistors (MN1, MN2) are of p-MOS type, and the output transistors (MP1, MP2) are of n-MOS type, that is opposite to the conductivity types of the main embodiment.