Patent GB-1176919-A (GB)
Title: Control of Drive Pulse Configurations
Inventor: HEIGHTLEY JOHN DONNELL
IPC: H03K5/01
Filed: 1968-10-30
Abstract: 1,176,919. Data store. WESTERN ELECTRIC CO. Inc. 30 Oct., 1968 [1 Nov., 1967], No. 51393/68. Heading G4C. [Also in Division H3] A pulse generator suitable for use in a storage matrix comprises an asymmetrically conductive charge storage device which may be selectively charged to different levels and discharged into a load. Pulses of selectable magnitude may thus be produced. The invention is described as applied to the word driver circuits for the coils (Fig. 2, not shown) of a plated wire memory matrix in which a low level charge provides a low amplitude non-destructive readout pulse (Fig. 3), a higher level charge produces a destructive read out and write pulse of larger amplitude and a further circuit may provide a current, following that provided by the charge, to prolong the pulse and allow read, write, rewrite and other modification of the information. In the word driver of Fig. 5 the diode 47 is charged, upon the application of a "charge diode pulse", from a battery 51 via a balanced choke 52 transistors 49 and 50 and via resistor 57 or transistor 76. When transistor 76 is rendered conductive by a "switch amplitude" pulse, resistor 57 is short circuited and a larger charge is applied to the diode. The diode is discharged into the word drive line load 33 when a "common timing pulse" renders transistor 62 conductive, the rate of discharge being controlled by an adjustable voltage applied to the circuit from a potentiometer 71 via a balanced choke 70. The different charge levels provide current pulses of different amplitude. The prolonged "read modify" pulse is produced by applying a "hold" pulse at 43 when the diode discharge commences to decay so that transistor 79 conveys from a supply 80 to the load to a current which is set by a potentiometer 81 to be equal to the diode peak discharge current. A simplified circuit (Fig. 6) uses a single supply 90 for charging the diode through 49, 50 and 57 or 76, for discharging it through 93, 62 via the load and for prolonging the pulse by making 49 conduct. Instead of having different amplitude charging currents for "read only" and "write" pulses different duration currents may be used and these may be timed by selecting one or two mono-stable control circuits of different periods (Fig. 1a, not shown). Fig. 1 (not shown), illustrates the random axis plated wire memory matrix sytem employing the above word driver. It comprises a central control controlling the address unit, the length of the pulse provided by the word driver and the timing circuits. The rewriting of the data may be effected after destructive read out. The lower amplitude read only pulse (Fig. 3) provides non-destructive read out, a write only pulse provides destructive read out during the rising flank and a writing period during the falling flank for restoring the destroyed data or writing new data. During the long "read modify" pulse information may be transferred to a disc and then other information from the disc to the store and a flag bit may be tested. Interspersing pulses of different length permits high speed asynchronous operation.