Patent GB-1178441-A (GB)
Title: Improvements in or relating to Communication Switching Systems.
Inventor: DUTHIE ROBERT WILSON
IPC: H04Q3/545
Filed: 1967-06-29
Abstract: 1,178,441. Read only stores. AUTOMATIC ELECTRIC LABORATORIES Inc. 29 June, 1967 [15 July, 1966], No. 30016/67. Heading G4A. [Also in Division H4] In an automatic exchange of the stored programme type, the lines are scanned for a calling condition by the arrangements for selecting the instructions. A single central store with four sections is used. One section stores instructions which are selected sequentially as in " one address " programming. A second section functions as a translator and gives at locations corresponding to directory numbers, the line equipment number, the ringing code (for party line ringing) and the class of service. The class of service may include hot line, direct distance dialling restriction, push-button dialling, abbreviated dialling, home extension intercom service and multi-party line. The third section functions as detailed below to determine the status or calling condition of any line, trunk, junctor, register, the marker, or a peripheral unit. The fourth section functions to provide tables of constants and other data. Store construction.-As shown, the main store comprises twenty large magnetic cores MC1 to MC20, one per binary bit, through which word wires are selectively threaded, storing one bits in bit positions associated with the linked cores. The wires are individually selected on a code point basis in accordance with a four digit number in a memory input register (not shown). Since each digit is represented by four binary bits, the digits have fifteen possible values. All values for the first and third digit and eleven values for the second and fourth digits are utilized. Those numbers including only decimal values are used for directory numbers, while other numbers are used for equipment number addresses and programme addresses. To read out a particular word the four digit number is entered into the memory input register in binary form. The first two digits are decoded into a signal on one out of fifteen and one out of eleven lines respectively, the lines being coupled in pairs to transistor drive gates D. A single gate is thus primed at two inputs and is enabled by a clock pulse. The output of the enabled driver is multipled on to a plurality of the word wires at terminals D.T.A. The last two digits are similarly used to select and enable a gate S, multipled on terminals STA. A unique word wire is thus enabled at both ends and can pass a read-out pulse. The passage of such pulse produces pulses in appropriate sense windings connected to sense amplifiers SA1 to SA20 and leading to a memory output register MOR1- 20. Two word wires selectable by a programme switch PGM.SW may be used at a single storage location. A flip-flop E, set and reset by timing pulses, blocks the output of the sense amplifiers while the number in the memory input register is changed to eliminate errors due to switching noise. Status (busy, free or calling) determination.- The third storage section includes two drivers D for some addresses. Each is connected to a different word wire. The two word wires at an address link different cores such as MC1 and MC2 then pass via a cable SS to the register or line circuit with which they are associated. After passing through a pair of status contacts of relays in that register or line circuit as indicated at REG-BO11 and LC-C1111 the wires are combined through diodes in a single wire leading to a terminal STA. By selecting this address and thus pulsing both wires simultaneously, the settings of the two relays in the corresponding register or line circuit are detected and entered in flip-flops MOR1 and MOR2. Four possible combinations exist. These are interpreted as idle, calling, busy or engaged and lock-out respectively. Any address without a word wire gives an all zero output and this is used to route the call to an operator. Registers.-The registers (Figs. 16 and 17, not shown) are of relay construction and include a relay counter in which dialling pulses of a received digit can be counted, four storage locations in each which the output of the counter after binary coding can be stored and additional relay circuitry adapted to respond to instructions received from the processor to receive and store one, three or four digits before calling for further instructions. The processor; general operation,-Instructions are normally sequentially selected from the programme store under the control of an instruction counter. The instruction cause various sequences such as the scanning of the registers and lines to be effected. At points at which a branch could occur, a constant is read out of the fourth section of storage and used to mask selected bits of another word. The result is then compared with this or another constant and a jump to one of two locations depending on the comparison is made. Thus a single bit can be tested in a search for a calling line or a free register or junctor or a group of bits can be tested to detect say the last line or register address to be scanned or a fault. When a calling line is detected it is connected to a register which returns dial tone. The register receives the first dialled digit then puts in a call for service. The processor determines whether this designates a trunk call and if so connects the call to an outgoing line so that subsequent digits are dialled directly into a distant exchange, or to a register sender. If the digit designates a local call, a relay is set in register, instructing it to wait for two more digits and the processor again returns to scanning. When these two digits have been received, the register again calls for service. Assuming the call to be a local one, the processor sets another relay in the register instructing it to wait for four further digits. When these have been received, the connection can be completed. Switching network.-The switching network is of the type described in U.S. Patent No 2,573,889 and comprises three stages. Each stage comprises a number of switching stages incorporating switching matrices having a single input connectable to any one of 100 outputs on operation of a " tens " and a " units " relay. The second stage has the matrices split and connected in groups to form switches with 25 inputs connectable to any of 25 outputs. The lines have appearances at both ends of the switching network and if a call cannot be completed in one direction, an attempt is made to find a path in the other direction. The lines are arranged in 100 line groups. The first and third stage switches associated with each group can connect any line to any terminal leading to a second stage switch. The second stage switches connect to one such terminal of each first stage and one such terminal of each third stage. The terminating junctors include equipment to supervise the connection including the supply of transmission current, ring signals and ring- ing tone, with ringing for individual or party lines and to provide for metallic cut through on trunk calls, and provide for reverting calls. They also detect on hook condition at the end of the call and releases the connection. A fault buffer (FB, Fig. 1, not shown) monitors the operation of the system and determines which of the duplicated units in the central processor, marker and memory are in active service.