Patent GB-1436439-A (GB)
Title: Semiconductor memory cell
IPC: G11C11/404
Filed: 1973-11-15
Abstract: 1436439 Transistor memory circuits INTERTIONAL BUSINESS MACHINES CORP 15 Nov 1973 [29 Dec 1972] 52960/73 Heading H3T [Also in Division H1] A semi-conductor charge storage memory cell comprises a first substrate or one conductivity type for a FET, a second substrate of opposite conductivity type within the first substrate for a second FET with a capacitance from the second substrate to the first substrate, and input lines switching on the first FET to charge the capacitance, and to subsequently turn on the second FET to sense the stored charge. A memory cell 1 (Fig. 1) comprises a pair of complementary FETs T 1 , T 2 , with a word line 2 connected to the parallel gates 3, 4 so that a pulse thereon turns T 1 , T 2  on and off respectively and vice versa according to its polarity. A write line 5 is connected to a diffusion region 6 of T 2  and a read line 7 to a diffusion region 8 of T 2 , while diffusion region 9 of T 1  is connected to substrate 10 of T 2  and diffusion region 13 of T 2  is grounded together with substrate 12 of T 1 . Parasitic capacitor 11 is composed of junction and oxide capacitances. Operationally, to write binary 1 or 0 into capacitor 11, a negative voltage pulse on word line 2 and a negative or zero voltage pulse representing binary 0 or 1 (Fig. 2, not shown) on write line 5 are applied to cause T 1  to conduct or not conduct and to charge or not charge capacitor 11. When the latter is charged to the pulse potential of write line 5 and zero potential is applied to the latter, the capacitor is discharged over T 1  and similarly when it is not charged to this potential application of a pulse to the write line produces no discharge. During write in, FET T 2  is isolated from T 1  and the capacitor except insofar as its substrate potential is similar to that in capacitor 11, and T 2  is held non-conductive by negative potential on line 2. A positive pulse on this line however permits conduction so long as the potential on gate 4 exceeds that on substrate 10. With the capacitor charged to binary "0" condition, a positive pulse is applied on word line 2 during a read interval and a positive pulse on read line 7 to activate T 2 . The pulse on line 2 is such that the negative voltage on substrate 10 from capacitor 11 sets the threshold of T 2  to inhibit conduction. But when voltage on substrate 10 is zero, the pulse on line 2 permits conduction since it exceeds the threshold voltage, and this is governed by the charged or uncharged state of the capacitor. When it is charged to binary "0", substrate 10 of T 2  is driven negative, and a positive pulse (Fig. 2, not shown) is applied to word line 2 during a read interval, while positive pulse is applied to read line 7 to actuate T 2 . A negative voltage on substrate 10 adjusts the threshold of T 2  to inhibit conduction while a zero voltage thereon permits conduction, since potential on gate 4 exceeds the threshold. During reading time word line potential is positive and renders T 1  non-conductive while T 2  is conductive, and a direct current flows to ground in read bit line 7. The PNP and NPN FETs T 1 , T 2  may be interchanged with reversal of pulse polarities.