Patent GB-1089094-A (GB)
Title: Improvements in or relating to circuit arrangements for controlling the transmissionof digital information
Inventor: ARNOLD JOHN SPENCER
IPC: H04Q3/42
Filed: 1964-01-17
Abstract: 1,089,094. Automatic exchange systems. AUTOMATIC TELEPHONE & ELECTRIC CO. Ltd. Jan. 13, 1965 [Jan. 17, 1964], No. 2112/64. Heading H4K. In a register-sender a four-bit binary counter transmits impulses corresponding to a dialling digit by counting down from a digit set in it to zero and times the interdigital pauses and the pause preceding the transmission of the first digit by making additional, counting actions. The counter is formed by bi-stable elements MAF to MEF, with the last element MEF providing a parity stage, and stores the digit in inverse binary form, i.e. " 1 "s and " 0 "s interchanged and reading from left to right. All the digits are stored in the normal form in a store of which only the last stage is shown by bi-stable elements MAR to MER and from which the digit is transferred to the counter via gates PRA to PRE. The counter and store are driven by clock pulses appearing on leads AD and AP. When the register is first seized the counter and store bi-stable elements are all in the set position (1-bits all present). The counter driven by AD clock pulses then proceeds to set itself into the next position (0-bits all present) ready to receive digits from the store where they are meanwhile accumulating. The absence of a digit in the store elements MAR to MER at the present state of the counter opens gate GRS and via gate GPS inhibits gate GAD so preventing AD pulses from driving the counter any further. Upon the storage of a digit the presence of 1-bits in the store elements MAR to MDR inhibits its associated gate PRA to PRE which gates determine whether the counter elements are set or not, so that the inverse form of the digit appears in the counter. The counter then counts down to the inverse form of zero (the set state) and a digit pulse for transmission will appear on lead IPR as gate GPR is held open for each state of the count. The bi-stable elements MAX to MDX form a control circuit for determining the time lengths of the interdigital pauses and the pause preceding the first digit and provides three distinct combinations of pauses say A, B, C, where A<B<C. The combination depends upon the setting of strap SLD and whether a signal appears on lead T11. With a signal on T11 and strap SLD present the pause preceding the first digit is C and all subsequent interdigital pauses B, with the strap absent the preceding pause is A, the first interdigital one B and subsequent ones C, with no signal on T11 all pauses are C. The different pause lengths are achieved by additional counting by the counter. Pause A is the time taken for the counter to be driven from its set state at seizure to its reset state when it is in a position to accept a digit from the store. Pause B is made longer because when the counter has reached this reset state it is sent into the set state again as gate PXCO opens and then takes time to reset itself. Pause C is achieved by setting a number up in the counter at the reset state by means of straps SIP which direct setting pulses to the counter elements from a bi-stable element MS as gate PXC1 opens. Which of these gates, PXCO or PXCI, opens and hence whether pause B or C occurs, depends upon setting of bi-stable element MCX which inhibits one or the other of them. The setting of MCX depends upon the signal on T11, which if present changes MBX from its reset state at seizure to its set state thereby not inhibiting gate PXBO and allowing MCX to be set when required and making the interdigital pause B. Without a signal on T11 MCX can never be set, PXCO can never open and all pauses are C. The presence or absence of the strap in combination with the signal on T11 either sets MDX or leaves it to react initially and determines the preceding pause and the first interdigital pause.