baber/WOPTO huggingface dataset:
Patent TW-463421-B (TW)
Title: Multipolar connector
Inventor: SHICHIDA AKIHITO
IPC: H01R13/703
Filed: 2000-05-09
Granted: 2001-11-11
Abstract: The multipolar electrical connector of the present invention uses a single-head plug as a counter connector, which won't prevent the miniaturization and multipole can be obtained. A boss portion 30 is protruded out of the body case 10 of a lower body shape. Plural predetermined contact pieces are incorporated into the body 10, so that plural poles are ensured by the predetermined contact pieces. A required number of first additional contact pieces 40 and second additional contact pieces 50 are placed on the outer and inner peripheral sides of the boss portion 30, so that two or more poles are ensured by the additional contact pieces 40 and 50.
Patent TW-476975-B (TW)
Title: AC plasma display with dual discharge sites and contrast enhancement bars
Inventor: MARCOTTE ROBERT G
IPC: H01J11/24
Filed: 2000-08-07
Granted: 2002-02-21
Abstract: An AC PDP incorporating the invention includes a first substrate having plural elongated address electrode structures, which include sets of color phosphors. A second substrate is opposed to the first substrate and encloses a dischargeable gas therebetween. The second substrate supports a plurality of scan loops and sustain loops that are interdigitated with the scan electrode loops. Gas discharges occur at intersections between address electrodes and both traces of a scan loop to which a scan voltage is applied and a single side of each adjacent sustain loop to which a sustain voltage is applied. This action creates wall charges at each of two subpixel sites for each color subpixel. Thereafter, sustain signals applied to sustain and scan electrode loops causes discharges at each of the dual subpixel sites at which wall charges exist. Electrically isolated contrast enhancement bars are placed within scan and sustain electrode loops and act to block ambient light from reflecting off the phosphor layer. Accordingly, ambient room contrast ratio of the PDP is enhanced due to the reduced reflection of the room light off the phosphor. Brightness reduction is minimized by the contrast bars being placed in the center of the loops where light is not produced.
Patent TW-465073-B (TW)
Title: Low temperature coefficient resistor (TCRL)
Inventor: HEMMENWAY DONALD
IPC: H01L21/265
Filed: 2000-06-12
Granted: 2001-11-21
Abstract: A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. In an integrated circuit, a precision polysilicon resistor comprising: an insulation layer covering a substrate; a layer of polysilicon deposited on the insulation layer, said layer of polysilicon having a relatively high dopant concentration and characterized by substantial unannealed implant damage.
Patent TW-457078-B (TW)
Title: Buckle
Inventor: SATO TOMOAKI
IPC: A44B11/25
Filed: 2000-07-28
Granted: 2001-10-01
Abstract: This invention provides a buckle which has male and female members readily engageable with each other, and which is releasable only by a particular operator having a releasing member. This buckle has a female member B, a male member A having an elastic engaging piece 20 inserted from one side of the cylindrical part 40 of the female member B, and a releasing member C having an insertion part 80, which is removably inserted from the other side of the cylindrical part 40. The female member B has a guide part 74 which warps the elastic engaging piece 20 inserted into the cylindrical part 40, and an engaging part 75 with which the elastic engaging piece 20 is engaged by being sprung back. The releasing member C has a guide face 82c which makes contact with the elastic engaging piece 20 engaged with the engaging part 75 when the insertion part 80 is inserted into the cylindrical part 40, to warp the elastic engaging piece 20 in the direction for disengaging it from the engaging part 75. The elastic engaging piece 20 is inserted into the cylindrical part 40 of the female member B and engaged therewith, and can be disengaged therefrom by insertion of the releasing member C into the cylindrical part 40.
Patent TW-I260332-B (TW)
Title: Compositions, methods of forming low dielectric coefficient film using the composition, low dielectric coefficient films, and electronic components having the film
Inventor: NARITA TAKENORI
IPC: C08L101/00
Filed: 2000-08-21
Granted: 2006-08-21
Abstract: A composition obtained by evenly dissolving (a) a thermally decomposable polymer and (b) a siloxane oligomer in (c) an organic solvent; a composition comprising (a) a thermally decomposable polymer, (b) a siloxane oligomer, and (c)' an organic solvent in which both of the ingredients (a) and (b) are soluble; a method of forming a low-permittivity film characterized by applying the composition to a substrate to form a composite film comprising the thermally decomposable polymer and the siloxane oligomer evenly compatibilized therewith and then heating the resultant film to condense the siloxane oligomer and remove the thermally decomposable polymer; a method of forming a low-permittivity film characterized by applying the composition to a substrate to form a composite film comprising the thermally decomposable polymer and the siloxane oligomer evenly compatibilized therewith, subsequently conducting a first heating step in which the siloxane oligomer is crosslinked while keeping the thermally decomposable polymer remaining in the film, and then conducting a second heating step in which the thermally decomposable polymer is removed; and a low-permittivity film formed by either of the methods for low-permittivity film formation.
Patent TW-466783-B (TW)
Title: The semiconductor luminescence devices of III group nitrides and their preparation
Inventor: UDAGAWA TAKASHI
IPC: H01L33/00
Filed: 2000-09-05
Granted: 2001-12-01
Abstract: It suggest to suitably form the added p type impurity semiconductor layers of III group nitrides, which is laminated-structure of low-resistance p type III group nitrides in as-grown state. And to avoid the device driven current flow into vertical zone of p type chassis electrodes. The semiconductor layers of the second n type III group nitrides are laminated on the semiconductor layers of p type III group nitrides. The second n type chassis electrodes are formed on the said surface of semiconductor layers of the second n type III group nitrides, and the second n type chassis electrodes form upon the p-n joining which is formed from the contact of the semiconductor layers of the second n type III group nitrides with the semiconductor layers of the second p type III group nitrides.
Patent TW-480469-B (TW)
Title: Photoelectric device and electronic apparatus therewith and driver IC for display device
Inventor: ISHIYAMA HISANOBU
IPC: G09G3/20
Filed: 2000-09-25
Granted: 2002-03-21
Abstract: Disclosed is a liquid crystal device having a display section with a plurality of X electrodes and a plurality of Y electrodes, a master X driver IC and a slave X driver IC for driving plural X electrodes, and a Y driver for driving plural Y electrodes. The master IC has a display control signal generation section, which generates a display control signal based on a signal from an external MPU and an output terminal (or input/output terminal) which outputs the display control signal. Each of the master IC and slave IC has an input terminal for receiving the display control signal from the master IC through an external wiring. This liquid crystal device can eliminate a luminance difference within the display screen driven by the master IC and the slave IC.
Patent TW-484257-B (TW)
Title: Frequency mixer of communication system
Inventor: WU JUANG-SHIUNG
IPC: H03D7/14
Filed: 2000-10-06
Granted: 2002-04-21
Abstract: The invention relates to a frequency mixer of communication system. The communication system includes an antenna, a low noise amplifier, a frequency mixer, a local oscillator and an intermediate frequency filter, in which the frequency mixer further includes a mixer circuit, a gain amplifying circuit, a voltage auto-tracking circuit and a DC voltage generating circuit. The use of DC voltage generation circuit can reduce the output power of the local oscillator, extend the operation time of battery for mobile communication system, and lower the harmonic wave deformation and noise index of the frequency mixer. The use of voltage auto-tracking circuit and gain amplifying circuit to increase the linearity and adjust the conversion gain of the frequency mixer by varying load resistance.
Patent TW-455661-B (TW)
Title: Compact gate valve
Inventor: YOO WOO-SIK
IPC: H01L21/02
Filed: 2001-02-20
Granted: 2001-09-21
Abstract: A gate valve assembly, which may be used to seal a semiconductor processing chamber to isolate the chamber and/or maintain pressure or vacuum therein. The invention includes a gate coupled to a linear axial shaft. The axial shaft is driven using a single action actuator. The gate of the present invention has an inclined surface to the shaft. Because the surface is inclined, the gate can be forced by the movement of the axial shaft against a similarly inclined gate seat surface. The angled surface translates the axial sealing force provided by the axial shaft into a positive lateral sealing force without the need for lateral movement of the gate.
Patent TW-473825-B (TW)
Title: Thermal flow lithography process
Inventor: HUANG YI-SHIUNG
IPC: H01L21/027
Filed: 2000-12-22
Granted: 2002-01-21
Abstract: This invention provides a thermal flow lithography process, which consists of firstly providing a thermal flow photoresist, adding a cross-linking agent into the thermal flow photoresist to form a cross-linking thermal flow photoresist, providing a substrate with an insulating layer, forming a cross-linking thermal flow photoresist layer on the insulating layer, and subsequently, performing an exposure process, a development process and a thermal flow process sequentially.
Patent TW-496067-B (TW)
Title: Apparatus for communication of chat messages and method therefor
Inventor: BURGAN JOHN M
IPC: H04L12/18
Filed: 2001-02-14
Granted: 2002-07-21
Abstract: A wireless communication system (10) includes a system controller (22), at least one radio frequency transmitter (26), at least one radio frequency receiver (28), at least one transmit antenna (30), at least one receive antenna (40), a chat server (48) and a plurality of wireless communication devices (36). The chat server (48) manages the communication of a plurality of chat discussions, facilitating substantially real time communication among the plurality of wireless communication devices (36) within the wireless communication system (10).
Patent TW-495845-B (TW)
Title: Semiconductor wafer and its manufacturing method
Inventor: KANZAWA YOSHIHIKO
IPC: H01L21/20
Filed: 2001-03-27
Granted: 2002-07-21
Abstract: First, anneal the Si substrate 1 that was stacked SiGeC crystal layer 8 and form a annealed SiGeC crystal layer 10 that contains matrix SiGeC crystal layer 7 with relaxed lattice and almost without dislocation and SiC micro-crystal 6 distributed in the matrix SiGeC crystal layer 7 on the Si substrate 1. Then, form less dislocation strained Si crystal layer 4 via depositing Si epi-layer on the annealed SiGeC crystal layer 10.
Patent TW-497270-B (TW)
Title: Method for making semiconductors
Inventor: IIDA IZUO
IPC: H01L27/105
Filed: 2001-05-23
Granted: 2002-08-01
Abstract: The present invention provides a method of manufacturing a semiconductor device to form a nonvolatile memory cell and a high breakdown voltage MOS transistor on the same semiconductor chip without changing characteristics of the memory cell. A gate insulating film (13) of a MOS transistor is formed using the steps of forming an oxide film (12) formed on a floating gate (14) of a split-gate type non-volatile memory cell and of forming a tunneling insulating film (16) formed on the floating gate (14) and the oxide film (12). The gate insulating film (13) of the MOS transistor is formed by a stacked layer of the oxide film (12) and tunneling insulating film (16). Thus, the quantity of heat treatment in the entire production process undergoes no change, and the optimized characteristic of the non-volatile memory undergoes no change.
Patent TW-517241-B (TW)
Title: Method and system for reversed-sequence code loading into partially defective memory
Inventor: LIN SHI-TRON
IPC: G06F9/445
Filed: 2001-08-02
Granted: 2003-01-11
Abstract: A computer system is provided that loads a computer program, in a reverse order, into a memory device having one or more defective memory cells. The program is organized into code modules with each code module including at least one complete instruction, or data block. The last code module of the program is loaded first into the last or highest addresses of the address space allocated in the memory for the program. Thereafter, the code module preceding the last loaded code module of the program is loaded into the addresses preceding the previously-loaded addresses. The subsequent code modules are loaded into successively lower memory addresses in a reverse fashion until the first code module of the program is loaded into memory. As each code module, or the codes that make up the code module, are loaded, each loaded memory address is checked for a defective cell. A JUMP instruction is created and inserted into the original program code preceding the defective memory address to bypass any defective memory cell without interrupting the intended operation of the instruction steps that are loaded into the memory. In addition, a JUMP instruction is inserted into the memory start address so that a processor is forced to begin execution at the memory address containing the first byte of the first code module. Certain byte codes that include referenced addresses are then modified to correct any address-referencing that may be changed due to the insertion of the JUMP instructions, and then loaded into the appropriate addresses in the memory.
Patent TW-511198-B (TW)
Title: Semiconductor device and method of manufacturing the same
Inventor: NONAKA YASUNORI
IPC: H01L21/301
Filed: 2001-08-14
Granted: 2002-11-21
Abstract: There are contained the steps of forming a plurality of semiconductor elements on surface sides of a plurality of operational unit areas defined on a semiconductor substrate respectively, then connecting the semiconductor elements only in the operational unit areas by wirings, and then forming recesses from the back side of the semiconductor substrate in the situation that a connection layer for connecting mechanically the semiconductor elements only in the operational unit areas is formed on the surface side of the semiconductor substrate, whereby the semiconductor substrate is separated between the semiconductor elements. Accordingly, there is provided a method of manufacturing a semiconductor device having a plurality of semiconductor elements, that is capable of preventing electrical interference between a plurality of semiconductor elements that are connected mutually via wirings and also suppressing variation a width of a recess that separates respective semiconductor elements.
Patent TW-571160-B (TW)
Title: Transflective liquid crystal display with backlight and reflection film
Inventor: TANADA TETSUSHI
IPC: G02F1/1335
Filed: 2001-08-17
Granted: 2004-01-11
Abstract: A liquid crystal display includes a pair of substrates which oppose each other with a liquid crystal layer therebetween; a light source provided on the exterior of one of the substrates; and at least an organic film, a metallic reflection film, an overcoat film, an electrode layer, and an alignment film formed on the inner face of one of the substrates. Many concaves are contiguously formed on a surface of the organic film, the inner surface of each concave constituting a part of a spherical surface. The metallic reflection film has a thickness of 80 to 500 Å. A transflector and a liquid crystal display including the transflector are also disclosed.
Patent TW-513738-B (TW)
Title: Semiconductor device and its manufacturing method
Inventor: HIGASHI KAZUYUKI
IPC: H01L23/52
Filed: 2001-08-24
Granted: 2002-12-11
Abstract: This invention provides a semiconductor device using the existing multi-layer wiring process to form a ground plane without making significant alteration of the manufacture process. For example, on a silicon substrate 11, an interlayer insulator layer 14 is formed on an insulator layer 12 where the lower layer signal wires 13A, 13B are provided. Via holes 14a, 14b, penetrating the interlayer insulator layer 14 and connecting to the lower layer signal wires 13A, 13B are then formed. A metal liner 15a and a plug metal 15b are deposited in the individual via holes 14a, 14b. The excessive plug metal 15b is removed after the via holes are filled. A barrier layer 15c is then globally formed. A resist pattern 21 is used as a mask to pattern the metal liner 15a and the barrier layer 15c to form connecting wires 15A, 15B and a ground plane 15C.
Patent TW-518736-B (TW)
Title: Gate-driven or gate-coupled electrostatic discharge protection circuit
Inventor: HUNG GEN-GANG
IPC: H02H3/00
Filed: 2001-09-06
Granted: 2003-01-21
Abstract: A kind of gate-driven or gate-coupled electrostatic discharge (ESD) protection circuit is disclosed in the present invention. The first voltage source and the second voltage source are provided to the ESD protection circuit. The ESD protection circuit includes the first resistor, a capacitor, an inverter, the second resistor, the first NMOS, and the second NMOS. In the invention, the voltage division principle from the inverter output resistance and the first NMOS output resistance is used to make the gate electrode of the second NMOS have an appropriate voltage to speed the parasitic BJT conduction of the second NMOS for entering the Snapback region so as to even effectively release the instantaneously large current generated by the ESD pulse. By appropriately adjusting the ratio between the inverter output resistance and the first NMOS output resistance, it is capable of controlling the biased voltage on the gate of the second NMOS to avoid damage on the gate oxide layer of the second NMOS generated due to too high voltage.
Patent TW-I247380-B (TW)
Title: Asymmetric channel and source/drain manufacturing method
Inventor: GUO JYH-CHYURN
IPC: H01L21/768
Filed: 2001-09-06
Granted: 2006-01-11
Abstract: The present invention provides an asymmetric channel and source/drain manufacturing method, which is suitable for a semiconductor substrate. The manufacturing method comprises the following steps of: forming a gate structure upon the semiconductor substrate; performing a bag-shaped ion implantation process upon the destined area for the extended source and extended drain of first side and the second side of gate structure on the semiconductor substrate respectively; performing an extended source/drain implantation process upon the destined area for the extended source and extended drain on the semiconductor substrate; performing a bag-shaped ion implantation process upon the extended source on the semiconductor substrate; performing an extended source implantation process for the extended source area upon the semiconductor substrate; forming an insulating sidewall layer of the gate on sidewalls at both sides of the gate structure; forming the source/drain area upon both sides of the gate structure of the semiconductor substrate; and lastly forming a self-aligned metal silicide layer upon the gate structure and source/drain area.
Patent TW-I225177-B (TW)
Title: Manufacturing method of thin film transistor (TFT) liquid crystal display (LCD)
Inventor: LIN MING-TIAN
IPC: G02F1/1335
Filed: 2001-09-12
Granted: 2004-12-11
Abstract: The present invention provides a manufacturing method of thin film transistor (TFT) liquid crystal display (LCD), which includes the following steps: providing a first substrate and a second substrate and installing the two substrates face to face with each other; forming a black matrix layer on the surface of the first substrate and allowing the black matrix layer to have an opening for the surface of the first substrate to expose; forming a coating layer on the black matrix layer and the opening's surface; forming a light shielding layer, whose area is larger than the area of the opening, on the surface of the second substrate, the shielding layer being opposite to the opening; forming an insulation layer on the light shielding layer and the second substrate's surface, and (6) forming a sealing layer between the coating layer and the insulation layer. By means of the TFT-LCD manufacturing method, the adhesiveness between the black matrix and the substrate can be improved significantly to prevent any black matrix from peeling off from the glass even after the manufactured TFT-LCD is affected by the vibration of an external force.
Patent TW-522406-B (TW)
Title: Semiconductor data storing circuit device, method of checking the device and method of relieving the device from defective cell
Inventor: NAKANO HIROFUMI
IPC: G01R31/28
Filed: 2001-09-24
Granted: 2003-03-01
Abstract: A memory core of a semiconductor data storing circuit device in a semiconductor chip is composed of a memory cell array having memory cells of rows and columns, data input/output circuits of a normal operation in which a data input line and a data output line for one bit of data are arranged at every four columns of the memory cell array, and checking circuits of a test operation in which a test data input line and a test data output line for one bit of test data are arranged at every eight (or two) columns of the memory cell array. In cases where the test data input/output lines for one bit of test data are arranged at every eight columns, because the number of test data input/output lines is lower than the number of data input/output lines, the number of input/output pins for the test operation can be reduced. Also, in cases where the test data input/output lines for one bit of test data are arranged at every two columns, because the number of test data input/output lines is higher than the number of data input/output lines, the number of memory cells simultaneously checked is increased, and a test operation time in the manufacturing of the memory cell array can be shortened.
Patent TW-538591-B (TW)
Title: Support method for power supply planning
Inventor: HASHIMOTO HIROYUKI
IPC: G06Q50/00
Filed: 2001-10-05
Granted: 2003-06-21
Abstract: When a power supply company executes demand adjustment by means of discount, demand adjustment quantity and cost can not be estimated appropriately. Therefore, the object of the present invention is to provide a support method for in planning of power supply schedule such that operation schedule of generators and purchase schedule of power are planned while taking into account of power demand adjustment in which the concept of demand adjustment can be reflected easily on a calculation expression presenting information of power supply schedule, appropriate demand regulation quantity and cost can also be presented.