Patent GB-1129956-A (GB)
Title: Electronic computing and accumulating device
IPC: H03K23/84
Filed: 1966-03-09
Abstract: 1,129,956. Counter using silicon controlled rectifiers. NATIONAL REJECTORS Inc. 9 March, 1966 [10 March, 1965], No. 10313/66. Heading G4A. [Also in Division H3] A control device includes a first and a second controlled rectifier having outputs coupled together via a rectifier means that renders the first controlled rectifier non-conductive when the second controlled rectifier conducts but prevents the second controlled rectifier from being rendered non-conductive when the first controlled rectifier conducts. The Specification describes a counter comprising silicon-controlled rectifiers 1, 2, 3 connected in series with loads 4, 5, 6 respectively to voltage supply lines 26, 27. Pulses to be counted appear on lines 28 or 29, the pulses comprising a negative pulse followed by a positive pulse. Assuming all S.C.R.'s are non- conducting, representing 000, and hence capacitors 21, 74, 37 are charged a negative pulse on line 28 causes capacitor 30 to discharge and capacitor 8 to charge via load 5 and resistor 9. Diode 20 is biased non-conductive. When a positive pulse is applied to line 28 capacitor 8 discharges via loads 4 and 5 and diode 7 and capacitor 30 is charged, the current flowing through resistors 16, 13 causing S.C.R. 1 to conduct. Diode 20 then conducts and allows the positive pulse on line 28 to keep capacitor 21 charged. The counter now stores 001. The next negative pulse causes capacitor 8 to be charged and capacitors 30 and 21 to be discharged. When the positive pulse appears capacitor 30 is charged but S.C.R. 1 is conducting so this has no effect, capacitor 21 is charged since diode 20 is now biased conducting and the current through resistors 14, 17 renders S.C.T. 2 conducting. Capacitor 8 discharges through S.C.R. 2 and causes an inverse current to pass through S.C.R. 1 rendering it non-conductive. Capacitor 8 then recharges with the left-hand terminal positive but by then capacitor 30 is fully charged with its upper terminal close to zero so S.C.R. 1 remains non-conducting and capacitor 21 is charged. Capacitor 11 becomes charged via load 6, resistor 12 and S.C.R. 2 and capacitor 24 becomes discharged, diode 20 is biased non-conducting and the counter stores 010. The next negative pulse discharges capacitors 8 and 30. The next positive pulse charges capacitor 30 and causes S.C.R. 1 to become conductive. Diode 20 conducts and the pulse maintains capacitor 20 charged. The counter stores 011. The next negative pulse discharges capacitor 30. The next positive pulse charges capacitors 30, 21, 24, the latter two capacitors being discharged when the S.C.R.s 1 and 2 respectively conduct, and causes S.C.R. 3 to conduct. This causes capacitor 11 to discharge via S.C.R. 3 and causes an inverse current to pass through S.C.R.'s 1 and 2 thus rendering them nonconducting. The process can be repeated over several stages. The counter may be used to count coins, a 5 pfennig coin operating a switch to apply the negative and positive pulses to line 28 and a 10 pfennig coin applying similar pulses to line 29 which causes a count similar to that described above but with S.C.R. 2 as the last significant stage and operating such as not to switch off S.C.R. 1 when S.C.R. 2 conducts.