baber/WOPTO huggingface dataset:
Patent TW-561163-B (TW)
Title: Process for preparing polypropylene terephthalate/polyethylene terephthalate copolymers
Inventor: KUO TUNG-YING
IPC: C08G63/78
Filed: 1999-12-31
Granted: 2003-11-11
Abstract: The present invention provides a method for preparing polypropylene terephthalate/polyethylene terephthalate (PPT/PET) copolyester, which comprises a group of processes from (a) to (e). Process (a) comprises subjecting bis-2-hydroxyethyl terephthalate (BHET), pure terephthalic acid (PTA) and 1,3-propanediol (1,3-PDO) to undergo esterification reaction to produce BHET and bis-2-hydroxypropyl terephthalate (BHPT), and then subjecting BHET and BHPT to undergo copolymerization reaction. Process (b) comprises subjecting PTA and 1,3-PDO to undergo esterification reaction to produce BHPT, adding BHET, and then subjecting BHET and BHPT to undergo copolymerization reaction. Process (c) comprises subjecting BHET and BHPT to undergo copolymerization reaction. Process (d) comprises subjecting PTA, ethylene glycol (EG) and 1,3-PDO to undergo esterification reaction to produce BHET and BHPT, and then subjecting BHET and BHPT to undergo copolymerization reaction. Process (e) comprises subjecting BHPT, PTA and EG to undergo esterification reaction to produce BHPT and BHET, and then subjecting BHET and BHPT to undergo copolymerization reaction. The obtained preferred PPT/PET copolyester of the present invention has the following properties: intrinsic viscosity (IV) > 0.6 dl/g, acid value (-COOH amount) < 40 meq/kg, melting point = 190 DEG C to 250 DEG C, L* > 60, and b* < 12. Therefore, the PPT/PET copolyester of the present invention is suitable for use as fiber and engineering plastic.
Patent TW-557317-B (TW)
Title: Process for the preparation of an impact-resistant polymer composition
Inventor: BRULS WILHELMUS GERARDUS MARIE
IPC: C08L21/00
Filed: 2000-03-03
Granted: 2003-10-11
Abstract: The invention relates to a process for the preparation of an impact-resistant polymer composition comprising 0.5-75 parts by weight of a rubber composition (per 100 parts by weight of matrix polymer) by (a) melt mixing of matrix polymer A with a composition comprising the rubber composition dispersed in a matrix polymer B, with B optionally being A, and (b) the dispersion of said rubber composition in matrix polymer B has been obtained by melt mixing of matrix polymer B with a rubber composition containing at least one functionalized rubber and at least one non-functionalized rubber. The composition according to the process of the invention exhibits an improved impact resistance at less to no creep and is suitable inter alia for use in plugs, as a heat bridge in aluminium windows and profiles and in hammer heads.
Patent TW-451373-B (TW)
Title: Wire bonding device
Inventor: SHIMURA MASAYUKI
IPC: H01L21/60
Filed: 2000-04-27
Granted: 2001-08-21
Abstract: To tightly contact the tip end of a lead to a frame placement stage using simple structure. A groove 8 is disposed at a corresponding part which receives the tip end of a pressing part 4a of a frame presser 4 on the upper surface of a frame placement stage 3.
Patent TW-471083-B (TW)
Title: Systems and methods for dry cleaning process chambers
Inventor: SALEH ZAKI
IPC: H01L21/64
Filed: 2000-06-09
Granted: 2002-01-01
Abstract: Chlorine trifluoride (ClF3) is an excellent chemistry for in-situ cleaning of process equipment for chemical vapor deposition (CVD) of metals. ClF3 is a weakly-bound molecule that breaks down exothermically on contact with most hot conducting films such as Ti and TiN without plasma, giving it an advantage over other chemistries. The energy released from the reaction is used to volatize the reaction byproducts. Cooler reactor surfaces, however, are coated with a halogen-rich, less conductive film that may not be as reactive with ClF3. To improve the ClF3 reaction, additives such as nitrous dioxide are employed. These additives react with ClF3 and supply reactive ions energetic enough to volatize the byproduct.
Patent TW-552705-B (TW)
Title: Flash EEPROM cell and method of manufacturing the same
Inventor: LEE MIN-KYU
IPC: H01L27/115
Filed: 2000-06-29
Granted: 2003-09-11
Abstract: The invention relates to a flash EEPROM cell and method of manufacturing the same. The method of manufacturing a flash EEPROM cell includes sequentially forming a tunnel oxide film, a polysilicon layer for a floating gate and a hard mask layer on a semiconductor substrate; patterning the hard mask layer and then forming a hard mask layer spacer at the etching side of the patterned hard mask layer; removing the exposed portion of the polysilicon layer for the floating gate by etching process using the patterned hard mask layer and the hard mask layer spacer as etching masks thus to form first and second patterns that are separated in two; removing the patterned hard mask layer and the hard mask layer spacer and then depositing a dielectric film and a polysilicon layer for a floating gate on the entire structure, thus forming a first floating gate, a second floating gate and a control gate by self-aligned etching process; and forming a drain junction and a source junction by cell source/drain ion implantation process. Thus, the present invention can prevent lower of the quality of the tunnel oxide film and thus increase the coupling ratio.
Patent TW-467777-B (TW)
Title: Method for producing metal casting using temperature-resistant and pressure-resistant prototype duplication technique
Inventor: MAU TZUO-FEI
IPC: B22C9/04
Filed: 2000-07-18
Granted: 2001-12-11
Abstract: This invention relates to a method for producing a metal casting using temperature-resistant and pressure-resistant prototype duplication technique, substantially comprising: utilizing a product prototype, which can not sustain high temperature and high pressure and can not be damaged, to produce a silicone mold in advance; mixing and stirring evenly metal powder or carborundum, etc. into temperature-resistant resin to form a high performance powder resinous molding material; after degasing the material by a vacuum injection machine, filling the mixed resin into the mold in vacuum; curing the mixed resin by the heating of an oven after completion, thereby obtaining a temperature-resistant and pressure-resistant prototype; using the temperature-resistant and pressure-resistant prototype to produce a silicone rubber rapid mold under high temperature and high pressure state; and producing a metal casting using a centrifugal casting process, thereby achieving the practical objective of shortening the product developing process and producing accurate sample, and enabling producing metal sample or performing the production in small or medium quantities.
Patent TW-466738-B (TW)
Title: Semiconductor structures and manufacturing methods
Inventor: SUMMERER CHRISTIAN
IPC: G03F9/00
Filed: 2000-12-12
Granted: 2001-12-01
Abstract: A semiconductor body having an alignment mark comprising a material adapted to absorb impinging light and to radiate light in response to the absorption of the impinging light, such radiated light being radiated with a wavelength different from the wavelength of the impinging light. Also a method and apparatus for detecting an alignment mark on a semiconductor body. The method and apparatus successively scan an alignment illumination comprising the impinging light over the surface of the semiconductor surface and over the alignment mark. The impinging energy is reflected by the surface of the semiconductor when such impinging light is over and is reflected by the surface of the semiconductor. The impinging energy is absorbed by the material and is then radiated by the material when such impinging energy is scanned over such material. The reflected light is selectively filtered while the radiated light is passed to a detector.
Patent TW-461032-B (TW)
Title: Manufacturing process of semiconductor device with a silicon island
Inventor: TSENG HORNG-HUEI
IPC: H01L21/76
Filed: 2000-11-21
Granted: 2001-10-21
Abstract: There is provided a manufacturing process of semiconductor device having thin foot on the device bottom of the silicon substrate. The structure has a silicon isolation device with high operating speed. In different embodiments, the present invention comprises forming a first diffusion barrier layer on the semiconductor structure; patterning the first diffusion barrier layer and forming a trench with a predetermined depth in the silicon substrate; then, forming a second diffusion barrier layer; patterning the second diffusion barrier layer, and forming a first spacer on the sidewall of the trench; next, performing a directional etching process to expose part of the position of the trench side wall, and implanting doped material into the exposed sidewall to form a doped area around the sidewall; afterwards, performing an isotropic etching process by halogens gas plasma, so as to easily and quickly etch off the doped silicon since the etching rate of doped silicon is larger than the undoped silicon, and expose the position of the undoped silicon, thereby forming thin foot on the bottom of the silicon island by decreasing the etching rate or stopping etching.
Patent TW-503349-B (TW)
Title: Technique of defending against network connection flooding attacks
Inventor: ATTWOOD KIRA STERLING
IPC: H04L29/12
Filed: 2000-12-04
Granted: 2002-09-21
Abstract: The invention prevents server overload and possible server crippling due to a flooding of connect requests caused by intentional attack or otherwise. In response to a connection request from a host for a specified port, the number of connections to the port that are assigned to the host are determined. If this number exceeds a first threshold, the request is denied. It is possible to override this denial if a quality of service parameter pertaining to the host permits such an override. However, if the number of available connections to the port is less than a second threshold, the connection request is denied in any event.
Patent TW-506030-B (TW)
Title: Testing method for nonvolatile memory
Inventor: CHEN WEI-SHIN
IPC: G11C29/08
Filed: 2001-03-30
Granted: 2002-10-11
Abstract: A testing method for nonvolatile memory is disclosed. The feature of this method is to write the customer assigned program code into at least one nonvolatile memory and disable the write enable pin to prevent wrong writing. When the tester restarts, read the program code of the nonvolatile memory and compare to program code catched by the tester control program. If they are identical, it means that the tester control program obtains the right program code, and vice versa
Patent TW-498566-B (TW)
Title: Reduction of ambient-light-reflection in organic light-emitting devices
Inventor: HUNG LIANG-SUN
IPC: H01L51/52
Filed: 2001-04-06
Granted: 2002-08-11
Abstract: An organic light-emitting device capable of reducing ambient-light reflection from a cathode includes a light-transmissive substrate, a light-transmissive anode, an organic hole-transporting layer, and an organic electron transporting layer. A reflection-reducing structure disposed between the electron-transporting layer and a light-reflective cathode is capable of providing electron injection into the electron-transporting layer and of substantially reducing reflection of ambient-light entering the device.
Patent TW-486836-B (TW)
Title: Process for producing lithium battery positive material in liquid phase
Inventor: LIN JIUN-REN
IPC: H01M4/04
Filed: 2001-04-17
Granted: 2002-05-11
Abstract: The present invention uses the property of lithium carbonate dissolving in an aqueous solution in a high pressure CO2 atmosphere to make an acid solution of Co, Mn and Ni react with lithium carbonate in a liquid phase, thereby forming a solid mixture oxide of Li-Co, Li-Ni or Li-Mn. The present invention provides a novel synthesis method that can use cheap reactants, accurately control formed grain size and composition of the compounds, and greatly reduce the reaction time. The invention provides the industry with a lithium battery positive material that can be rapidly produced and has a good quality.
Patent TW-I234275-B (TW)
Title: Method of fabricating a flash memory cell
Inventor: CHOU KUO-YU
IPC: H01L29/788
Filed: 2001-05-25
Granted: 2005-06-11
Abstract: A semiconductor substrate is provided with a V-shape structure positioned in the semiconductor substrate. A first ion implantation process is then performed to form a first doping region around the V-shape structure in the semiconductor substrate. Following this, a first dielectric layer is formed on surfaces of the semiconductor substrate and the first doping region. A floating gate is formed on the first dielectric layer over the first doping region and a second dielectric layer is formed on the floating gate, respectively. A controlling gate is then formed on the second dielectric layer. Finally, a second ion implantation process is performed utilizing the controlling gate as a mask to form a second doping region in the semiconductor substrate.
Patent TW-495819-B (TW)
Title: Method and system for electronic commerce of semiconductor product, system and method of production, and design system, design method and manufacturing method of production equipment
Inventor: MITSUTAKE KUNIHIRO
IPC: G06Q30/00
Filed: 2001-05-30
Granted: 2002-07-21
Abstract: A kind of electronic commerce system for semiconductor product is equipped with the followings: a virtual production line 13, in which the same function as that of an actual production line actually manufacturing the semiconductor products is built in a computer to computes a way of carrying out optimum lots; and a connection server 12, which connects the virtual production line 13 to a client terminal 11 through a network 10. Conditions inputted from the client terminal 11 are transferred by the connection server 12 to the virtual production line 13 such that whether productions can be manufactured by the virtual production line 13 under the transferred conditions or not is simulated in real time; and business is carried out according to the simulation result after the simulation result is transferred by the connection server 12 to the client terminal 11.
Patent TW-511082-B (TW)
Title: Method of erasing a flash memory cell
Inventor: LEE HEE-YOUL
IPC: H01L27/115
Filed: 2001-06-15
Granted: 2002-11-21
Abstract: There is disclosed a method of erasing a flash memory cell. The flash memory cell used in the present invention includes a gate in which a tunnel oxide film, a floating gate, a dielectric film and a control gate are stacked on a semiconductor substrate, and a junction region formed in the semiconductor substrate at the both sides of the gate, which is constructed to be programmed as hot electrons are injected into the floating gate and is also erased as the electrons injected into the floating gate are discharged by means of a F-N tunneling effect depending on the potential difference between the floating gate having the potential induced by a bias voltage applied to the control gate and the semiconductor substrate. A method of erasing a flash memory cell of the present invention comprises the steps of applying a negative bias voltage to the control gate, applying a positive bias voltage to the well and making the junction region floated; and from the step. Sequentially applying a ground voltage to the well, the control gate and the junction region.
Patent TW-509959-B (TW)
Title: Temperature fuse
Inventor: MIYASHITA IKUHIRO
IPC: H01H85/00
Filed: 2001-07-27
Granted: 2002-11-11
Abstract: The purpose of the present invention is to have a temperature fuse capable of providing low resistance when conducting electricity and having no melting problem on the movable electrode (4) and the leading line (2) even when the machine temperature of the connecting temperature fuse is increased slowly. Thus, for the invented temperature fuse, the load of compressed spring (9) is eliminated when temperature sensitive material (7) is operated and is melted due to temperature; additionally, the movable electrode (4), which is compressed and contacted by the compressed spring (9) due to the stretch of compressed spring (9), can be separated from the leading wire (2) so as to terminate the current. The invention is featured with the followings. The movable electrode (4) is obtained from an alloy after it is undergone with an internal oxidization treatment, in which the alloy is composed of 100 weighting parts containing 99 to 80 weighting parts of Ag (silver) and 1 to 20 weighting parts of Cu (copper). The thickness of the pretty thin oxide layer on the material surface is smaller than 5 μm, and the average particle diameter of the oxide particles in the material is 0.5 to 5 μm.
Patent TW-554530-B (TW)
Title: Insulating nitride layer and process for its forming, and semiconductor device and process for its production
Inventor: NAKAMURA FUMIHIKO
IPC: H01L21/205
Filed: 2001-08-07
Granted: 2003-09-21
Abstract: Disclosed herein is an insulating nitride layer suitable for group III-V nitride semiconductor devices. It has a high resistance and good insulating properties and hence it electrically isolates elements, without the active layer decreasing in conductivity. Disclosed also herein is a process for forming said nitride layer and a semiconductor device having the nitride layer for improved characteristic properties. The semiconductor device is an AlGaN/GaN HEMT or the like which has a GaN active layer 4 and an insulating nitride layer 3c formed thereon from a group III-V nitride compound semiconductor heavily doped mostly with a group IIB element (particularly Zn) in an amount not less than 1x10<17>/cm<3>.
Patent TW-513297-B (TW)
Title: Auxiliary device for propping up mouth for medical use
Inventor: HUANG YUNG-SHUEN
IPC: A61B1/24
Filed: 2001-09-04
Granted: 2002-12-11
Abstract: The present invention relates to an auxiliary device for propping up mouth for medical use, particularly a device for assisting mouth to open easily for any medical treatment in the mouth. The device comprises a C-shaped lip frame and a pivotal biting block, in which the C-shaped lip frame has an U-shaped cross-section and the frame body has an outward opening and forms a protrusion ear extending towards one side from a middle bent region. A longitudinal pivotal post protrudedly installed on the connection arm, which is transversally extended, is used to assemble the longitudinal biting block to the pivotal hole of the protrusion ear of the C-shaped lip frame so that the biting block can extend into the mouth to be fastened by biting by the teeth in order to support the C-shaped lip frame to prop up the lip on the outer edge of the mouth.
Patent TW-593645-B (TW)
Title: Novel additives for chemical-mechanical polishing slurries
Inventor: KUO PING-LIN
IPC: C09K3/14
Filed: 2001-09-03
Granted: 2004-06-21
Abstract: The present invention provides the utilization of novel additives for preparing the slurries for chemical-mechanical polishing (CMP). The additives are composed of carbon or silicone type of polymer grafted with the nonionic, anionic and cationic groups. These additives, when present in the CMP slurries, provide the electrostatic barrier and/or steric hindrance to prevent the coagulation of abrasive particles and to stabilize the slurry system, so that high removal rate and low non-uniformity for polishing process can be achieved.
Patent TW-587072-B (TW)
Title: Catalyst for the preparation of methacrylic acid, coated catalyst, and process therefor
Inventor: SEO YOSHIMASA
IPC: B01J27/199
Filed: 2001-09-20
Granted: 2004-05-11
Abstract: The present invention relates to a catalyst for producing methacrylic acid by the vapor-phase catalytic oxidation of methacrolein, comprising Mo, V, P and Cu as the indispensable active components, in which copper acetate is used for all or a part of the necessary amount of a material for the Cu, a coated catalyst and a method for manufacturing the coated catalyst, and methacrolein is reacted in a high conversion and methacrylic acid is produced in a high selectivity by use of the catalyst of the present invention, and the catalyst can be used for reaction under high loading condition.
Patent TW-516133-B (TW)
Title: Method of manufacturing semiconductor device
Inventor: GOTOU MASAKATSU
IPC: H01L25/07
Filed: 2001-09-27
Granted: 2003-01-01
Abstract: The improvement of the yields of semiconductor devices is intended. In a method for manufacturing a semiconductor device, a resin enclosure is formed for block-molding a plurality of semiconductor chips by placing a plurality of semiconductor chips inside a cavity of a molding die along with a substrate and then injecting a resin from a first side to a second side of a main surface of the substrate, in which the plurality of semiconductor chips are mounted on the main surface of the substrate from the first side to the second side of the main surface with a predetermined space and the second side faces to the first side. Furthermore, the method also includes applying a cleaning treatment to the main surface of the substrate before forming the resin enclosure.
Patent TW-506072-B (TW)
Title: Dual damascene process of using metal hard mask
Inventor: SHIU JEN-CHIOU
IPC: H01L21/768
Filed: 2001-10-16
Granted: 2002-10-11
Abstract: A kind of dual damascene process at least includes the following steps: providing a semiconductor substrate, which contains a conducting wire structure, a dielectric separating layer, a dielectric layer with low dielectric constant, a first hard mask of a metal material and a second hard mask of a metal material; forming a first opening in the second hard mask; forming a second opening in the first hard mask, in which the second opening is under the first opening and the aperture of the second opening is smaller than that of the first opening; stripping off the dielectric layer, which is not covered by the first hard mask, till the dielectric separating layer is exposed so as to form a dielectric via; stripping off the first hard mask that is not covered by the second hard mask; and stripping off the dielectric layer, which is not covered by the first hard mask, till a predetermined depth is reached so as to form a trench on top of the dielectric via, in which the dielectric via and the trench form a dual-damascene opening.
Patent TW-I234857-B (TW)
Title: Structure of the ball-grid array packaged substrate with the heat sink layer containing function of grounding layer and manufacturing method of the same
Inventor: HE KUEN-YAU
IPC: H01L23/28
Filed: 2001-10-19
Granted: 2005-06-21
Abstract: The present invention relates to one kind of substrate structure for improving efficiency of the heat sink layer of a ball-grid array packaged (BGA) substrate and manufacturing method of the same, wherein the disclosed BGA substrate contains a single pattern layer which is used as a connection of the solder ball and the conductor pattern. On the other side of the substrate is bonded with one heat sink layer, which provides the BGA substrate with grounding function to disperse the necessary area required for the grounding conductive pattern of the pattern layer of the BGA substrate whose solder balls for ground are connected by utilizing the sprocket holes which are filled with conductive adhesives.