Patent GB-715461-A (GB)
Title: Improvements in electrical communication switching systems
Inventor: FLOWERS THOMAS HAROLD
IPC: H04J3/12
Filed: 1949-09-06
Abstract: 715,461. Automatic exchange systems. POSTMASTER GENERAL. Aug. 21, 1950 [Sept. 6, 1949], No. 23082/49. Class 40 (4) In a multiplex telecommunication exchange system of the type described in Specification 694,092 in which a line finder or selector is required to produce pulses at a position in a time cycle determined by a single input pulse, an electronic counter circuit is used to determine the interval between the pulses. These pulses are required for suppressing calling pulses once a calling pulse has seized an idle finder/selector link and also for gating pulses in the time positions of the calling and called subscribers into the finder/selector link. Fig. 1c shows equipment required for producing pulses required for operation of the counting devices subsequently described. The "calling" pulse is fed over lead 11 to a trigger circuit 20 which is operated by a pulse on 11 and released by the cessation of a "hold" signed on lead 12, the said hold signal being obtained from the finder-selector link during the whole of the time the link is in use. The operation of the trigger circuit causes an output pulse over lead 21 coincident with the calling pulse and the operated state of the trigger circuit is also indicated by potential on lead 22. This potential is also applied via a delay line 25 to cause a gate circuit 24 to pass to lead 23 all the pulses of a common pulse series CP subsequent to that coincident with the calling pulse. The series CP consists of pulses coincident with those of every channel of the multiplex. In one embodiment, Fig. 2, of the counting circuit employing a counter CTR of scale N, equal to the number of common pulses occurring between two pulses of a channel pulse series, the counter is started by a pulse from lead 11 or 21 and maintained in operation by common pulses CP admitted to lead 29 by the gate 28, held open by a hold signal over lead 12 or 22. Pulses are also fed to the counter over lead 27, to which they are admitted by the gate 26 which is open except at an instant shortly after the counter is in the zero position under control of the lead 00. Thus when the hold signal is removed the counter receives impulses over lead 27 to restore it to its zero position. The output from the counter is applied over condenser Q to a further delay line OPDL to time the pulse more accurately as a pulse suppression pulse. Alternatively the pulse from Q may be applied to open a gate 40 to pass a pulse from a series CPP slightly delayed with respect to the series CP. In an alternative embodiment, Fig. 3 (not shown), the counter is run from lead 23, being restored to zero after pulses on 23 have ceased in the manner above-described the required pulses being derived from a lead energised when the counter is in the (N-1)th position. Alternatively, Fig. 4 (not shown) a counter set by pulses from lead 23 may be set to zero by an over-riding signal on the hold lead. In a further modification, Fig. 5 (not shown) the counter is stepped both by pulses over leads 21 and 23 the output being taken from the zero position. In an arrangement, Fig. 6, in which the scale N of the counter is greater than the number of pulses M in the cycle the counter is stepped by pulses over lead 23 and when the counter reaches the (M-1)th position a signal is transmitted to the gate 30 which thereupon admits a pulse from the common pulse series CP which over-rides the pulse from lead 23 to zeroize the counter. Cessation of the hold signal over 12 or' 22 also zeroizes the counter. Electronic circuits for carrying out the embodiments shown in Figs. 2 and 6 are given in Figs. 7, 8 (not shown).