Patent GB-1340189-A (GB)
Title: Data processing systems
IPC: G06F17/40
Filed: 1970-12-16
Abstract: 1340189 Data processing systems COPYCOMPOSER CORP 16 Dec 1970 [16 Dec 1969] 59794/70 Heading G4A Data and text characters are entered from one or more terminals, Fig. 2, and a stored program processor processes unit records comprising one or more data characters supplied by the or each terminal in accordance with the particular control characters supplied therewith. The embodiment described is concerned with storing, editing and displaying/printing text, but other applications such as credit-checking, accounting, and inventory control are mentioned. In a SELECT mode of operation the processor is programmed to control a multiplexer 11, Fig. 2, to continuously scan terminal line buffers 65 which assemble unit records for example a line of text supplied by the associated terminal, each record ending with a carriage return character and a data ready signal being generated when a complete record has been assembled. On sensing a "ready" terminal, the record is transferred from the TLB65 to a working store WS72 via ILB66 and I/O buffer 68 for processing and subsequent storage in memory 82. A data record may be transferred in the opposite direction from MEM82 to a terminal. In either case, a new program and operating mode is selected in accordance with a control character supplied by a terminal or a previously selected program is resumed at an address stored in PSR67 for the terminal. The multiplexer is halted when a change from the SELECT mode to another mode is made, and only resumes scanning when a complete line has been processed. To prevent overloading of the processor, the number of terminals allowed to produce a ready signal at any one time may be limited, Fig. 7 (not shown). Input mode is selected by entering "begin text" and carriage return characters on a keyboard at one of the terminals, and on next scanning that terminal, the multiplexer is halted and the "line" (which always ends in a carriage return character) is passed into WS72. The begin text character causes the address of the next available memory page, e.g. disc track, to be transferred to page counter 83 from NVM84, a bit in a stage of memory index register 81 to be set to indicate that the page is no longer vacant, and register 81 to be scanned to find the next available memory page, the address of which is then placed in NVM84. The page number is transmitted to the terminal for display via WS, ILB and TLB so that the operator can subsequently identify the document. The entry address for the input mode program is placed in the PSR67 for that terminal. Successive lines of text are then entered from the terminal, each line being stored at the next memory line segment in sequence, and PSR67 being updated for use when the next line is entered. When a memory page has been filled, a match between LC75 and a predetermined number is obtained, and the contents of NVM and an end of page character are automatically inserted as the last line of the page, so that the pages are chained together for subsequent lines, and since the next available page has now been allocated, index 81  and NVM are updated. Entry of text is ended by entering special control characters to return the processor to the SELECT mode for that terminal. Errors may be corrected during entry by backspacing to a single character error and retyping or using special control characters to delete a complete word or line. Print/list modes are selected by entering a control character identifying the mode required and numbers identifying the first and last page and line of the text required. The text identifying numbers and the entry address of the appropriate program are subsequently stored in PSR67 for that terminal. When the terminal is ready to receive data, the next scan by the multiplexer transfers the contents of PSR67 to MAS85. Included in this information is the justified line length which is then transferred to ISWC69 which is decremented for each character subsequently read out from WS, the text required being transferred line by line from MEM82 to WS. Counter ISWC controls the insertion of inter-word spaces to justify each line for display/print-out at the requesting terminal. If required to complete a justified line, part of the next line may be merged with a short line, the next displayed line commencing where the previous displayed line finished. The required information to allow this to be done is stored between multiplexer cycles. Lines may also be displayed without justification or aligned with a left or right margin or symmetrically arranged about the centre line of the display area.  Edit mode.-A line to be corrected is designated by the operator and displayed at the terminal. A correction line is then entered having spaces at character positions where no alteration is to be made and control characters at positions where insertions and deletions are to be made. The correction line is entered in WS and is followed by the original line retrieved from memory 82. Character counters 70, 73 control the deletion and sustitution of characters according to the control characters in the correction line. For insertions, an insertion control character followed by the page number and line number 1 of the next available memory page are entered at the appropriate position in the line in WS. The line is then transferred to its allocated position in memory 82. The new page identity for the insertion is stored in PSR67 ready for entry of one or more insertion lines from the terminal, which lines will be recorded at the new allocated page in memory 82. Special print/list mode.-One terminal K has a special printer, disc, core memory or tape unit which can record text originally supplied by other terminals. If this mode is selected, the control data for the requesting terminal is transferred to PSR67K to control transfer of the required text. The terminal K may be used for off-line storing of documents from any terminal and for consolidating documents stored in scattered memory pages to enable efficient use of the memory capacity. System control.-The instruction memory 160, Fig. 3, (which may be read-only) is normally addressed sequentially by counter 61. Instructions are of one, two and 3-word length. The first type comprises bits indicating the instruction type, an OP code, and source and sink units such as registers, counters. This type of instruction is dealt with solely by decoder 62. The second type comprises a first word similar to type (1), but its type indicator causes readdressing of memory 160 at the next sequential location and entry of the second word into a next address register 63 to effect an unconditional branch operation by presetting counter 61. The third type comprises a first word similar to type (1), but its type indicator causes the next two words to be read from memory 160 into NAR63 and a match character register 64 respectively. The contents of MCR may be used for example to determine the control character which has terminated a data transfer between a TLB and ILB, e.g. is it a carriage return character? If a match is detected then counter 61 is preset by NAR to effect a conditional branch. Timing.-A clock-driven ring counter, Fig. 5C (not shown), is controlled to cycle over a variable number of cycles determined by the type of instruction being executed. The various counter stages enable different operations such as instruction memory read, increment counter 61, in the appropriate sequence. Incrementing of counter 61 may be inhibited to cause repetition of certain data transfer instructions or to retain a channel interrogate instruction when a scanned terminal is found to be not ready.