Patent GB-990602-A (GB)
Title: Electronic display system
IPC: G09G1/10
Filed: 1963-04-19
Abstract: 990,602. Cathode-ray tube displays; semi-conductor circuits. CONTROL DATA CORPORATION. April 19, 1963 [April 20, 1962], No. 15615/63. Headings H3T and H4T. In an arrangement for deflecting the beam of a cathode-ray tube to display graphic data, signals characterizing the origin of the display are stored in a register in terms of a set of digits after which signals characterizing segmental portions of the display are entered in the register in terms of increments of the set of digits all digital signals being converted to analogue signals and employed to control the deflection of the beam of the display tube. Additionally, digital signals which are converted into signals for controlling the intensity of the tube beam are employed. The data comprise digitally coded words representative of graphic indicia including alpha-numeric and other symbolic characters and may be derived from any source including as shown in Fig. 1, a computer 11 provided with an input-output register I/O. The word output of the latter, which is handled a byte at a time, each byte consisting of four bits which are individually significant (i.e. the bytes are coded to represent binary digits), is fed via a gate circuit, controlled by a circuit 13, to an auxiliary memory device 12 comprising a rotating magnetizable disc on a plurality of concentric tracks of which and in a particular sector of which the words are recorded. Sixteen sectors of 22¢ are provided, each being identified by a signal produced by reading heads and on correspondence of a sector signal in addressing circuits 14 with a sector selection signal supplied by the computer 11 the writing circuits are conditioned to record the information in memory 12 on the occurrence of the next clock pulse produced by the latter. The control circuit 13 also controls the reading circuits which supply outputs to a decoder 16 the decoded signals comprising binary digits being fed to the beam intensity control circuit 29 and to registers 17 and 18 appropriate to the X and Y beam deflections respectively. The registers first respond to the original characterizing signals by operating as shift registers and supply output signals which, after conversion to corresponding analogue signals in 21, 22, are fed via sample and hold circuits (see Fig. 10) to the X and Y deflection circuits 26, 27 which operate such that, when the beam is subsequently brightened by control circuit 29, the spot produced on the screen of tube 19 is at the desired position of the origin of the trace. At this point all the stages in the registers 17, 18 are occupied. The next signals supplied by decoder 16 correspond to segmental portions of the display and the registers then operate as accumulators and increase or decrease the count in accordance with the particular one of the four quadrants on the tube screen in which the segments are to be produced. A maximum of thirty-two segments are available the number used to form a particular line or other piece of graphic data depending on the length of the latter. The disc in memory 12 rotates at 1800 w.p.m. so that the trace is regenerated 30 times per second thus ensuring flicker-free display. Fig. 10, shows circuit details of the sample and hold circuits 23 or 24 of Fig. 1, the purpose of such circuits being to receive the analogue signals from the convertors 21, 22 and then hold such signals at a constant level for a short period independently of variations in the input signals. In the circuit of Fig. 10, the transistors 1016 and 1021 with respective input and output terminals 1011 and 1012 act as impedance matching devices and are supplied from regulated current sources including transistors 1017 and 1022. During the sampling operation transistors 1026 and 1027 are held in the conductive state by the charge on capacitor 1029 (supplied by the circuit including transistor 1028) so that input signal at terminal 1011 from the digital-to-analogue converters 21 or 22 (Fig. 1) charge capacitors 1046, 1047. The holding operation is then initiated by a timing pulse at terminal 1013 the effect of which is to cause a normally cut-off transistor 1037 to conduct and thereby remove the back-bias on diode 1042 so that capacitor 1029 discharges and cuts-off transistors 1026, 1027. The input terminal 1011 is then isolated from the output terminal 1012 so that the voltage between the latter and ground is maintained constant by capacitors 1046, 1047. The cycle then repeats.