Patent GB-942153-A (GB)
Title: Improvements in or relating to data processing apparatus
Inventor: HAZARD ROBIN FRANK
IPC: G06F9/42
Filed: 1961-01-26
Abstract: 942,153. Digital computers. INTERNATIONAL COMPUTERS & TABULATORS Ltd. Jan. 17, 1962 [Jan. 26, 1961], No. 3085/61. Heading G4A. The selection of instructions in an internally programmed digital computer is determined by address indicators which are words comprising two addresses of which the less significant address represents the location of the current instruction and is incremented (usually by one) to give the address of the next instruction. To call in a subroutine an unconditional jump is made to the address indicator controlling that subroutine, and the address of the main progam address indicator is entered as the first (more significant) address of subroutine address indicator. Word format: The word length is 26 bits. An instruction word (IW) comprises two octal function (F) digits (six bits), an N field (seven bits) used for counting and modification, and an X field (thirteen bits) specifying either an address or in modification operations, an operand. An address indicator (AI) is in two parts each of thirteen bits. The more significant part contains the address of another address indicator, the less significant part the address of the current IW. If the N field of an IW is other than 0 or 127 the X field is modified by the addition of 1 to the X field. Unless the value of the N field is 0 or 127, this is also modified by the addition of 1. If the IW is an unconditional jump and the N field value is 127 the IW is unmodified. All stores are preferably magnetic core stores such as are described in Specification 848, 858, but controlled by three signals; I, reset cores; II, condition readout amplifiers; and III, condition write drivers. If the store is to receive information from another source signals I and III are applied simultaneously. If non-destructive readout is wanted signals I, II and III are applied. The machine cycle consists of at most five beats controlled by a ring of bi-stable circuits the condition of which is identified by one circuit being on a different stable state to the others. The output of the one circuit is gated by signals from function decoder 8 to produce the required I, II and III signals (Fig. 2, not shown). A beat. The P register 6 holds the address of the current AI. This is transferred to A register 20 where it is used to readout the AI to store register 2. The AI is returned to store 1 with its second part incremented by one. The second part of the AI is transferred to the A register. B beat. IW at address in the A register to store register 2. X field to A register. Function digits to F register 7. Depending on the nature of the instruction as explained above the IW is returned to store modified or unmodified. C beat. A register used to readout operand to store register. The operand is returned to store unmodified. D beat. Store register is dynamicized into the arithmetic unit. Arithmetic operation performed. If it is required that the result is to be placed in the store register,the result is staticized in the register 2 during this beat. E beat. Contents of store register returned to X-address of IW (still held in A register). In the next A beat the AI is again read out and it is found that the next IW is at the address of the previous IW plus one. To call in a subroutine the IW an unconditional jump is made to the address of the AI containing the address of the first IW of the subroutine. In the A beat the main program AI is read out to the store register 2 as before. Its second address is transferred to the A register and also returned incremented by one to the store 1. The IW specified by the address in the A register is an unconditional jump. At the beginning of the B beat this IW is read out and its F digits and X field staticized in the F and A registers. The remainder of the B beat is modified by the function digits. The P register is transferred to the more significant half of register 2 while the X field of the jump IW containing the address of the AI for the subroutine is entered in the P register. At the end of this beat register 2 contains in its more significant half the address of the main program AI and in its less significant half the address of the subroutine AI. In the C beat only the less significant half of the subroutine AI is read into register 2, and the complete contents of the store register are returned to store unmodified. The machine cycle is complete since no arithmetic operation is required. The next cycle, which staticizes and performs the first IW of the subroutine, then starts. It is envisaged that a request from input/output equipment will be treated as an unconditional jump calling in a subroutine appropriate to the equipment making the request. The Specification describes the steps necessary to return to main program.