Patent GB-1248947-A (GB)
Title: Magnetic analog memory
Inventor: OLSEN EVERETT OSCAR
IPC: G11C27/02
Filed: 1968-12-19
Abstract: 1,248,947. Magnetic analogue storage apparatus. FOXBORO CO. 19 Dec., 1968 [28 Dec., 1967], No. 60491/68. Heading H3B. In an analogue memory circuit in which the analogue of an input signal is stored as a remanent flux level of a rectangular hysteresis loop magnetic core a winding of the core is connected in one arm of a bridge circuit such that when an A.C. current is applied across one diagonal of the bridge circuit an output signal is produced at the other diagonal representative of the analogue of the input signal. The operation of the memory is based on the fact that when a relatively low amplitude A.C. signal is applied to a magnetic core the slopes of the minor hysteresis loops 13 to 17, Fig. 1, at the various levels of remanent flux 13a to 17a differ as shown so that an output signal may be produced which will be related to the magnetization of the core. Read out is obtained by connecting winding 23a of the magnetic core in one arm of bridge 22. If the degree of magnetization of core 23 and hence its permeability is set by the magnitude of an input signal on winding 23b then when an A.C. signal 42 is applied across the bridge diagonal 27, 28 the bridge is unbalanced and the resulting A.C. output at 29, 30 is rectified at 35 and filtered at 35a to produce a D.C. output signal at 36, 37 representative of the remanence condition of core 23, the D.C. signal being fed back over resistor 40 to point 27. The arrangement is such as to tend to rebalance the bridge as core 23 has different analogue values stored therein. In a further bridge provided with a feedback loop the linear inductance 24 of Fig. 2 is replaced by a non- linear inductance and the feedback is applied to the junction of a capacitor and the non-linear inductance in the arm 28, 30. In order to improve linearity the circuit of Fig. 4 is employed including a feedback loop from output terminal 36 to input terminal 58 of an amplifier 43. If the output signal at terminal 36 differs from the magnitude of the input signal applied to terminals 33, 34 a differential signal appears at 58 which is amplified by amplifier 43 and coupled to magnetizing coil 23b of core 23 so that the output signal at 36 is made more closely equal to the input signal at 33, 34. Switch 48 is cycled several times during the period of the input signal. Lag circuit 46, 44 prevents a new level of input signal from being compared with a greatly divergent output signal. As an alternative to storing the magnitude of an input signal the analogue memory may be altered by incrementing the stored value to a new level, Fig. 5 (not shown), in which a variable capacity bridge circuit is employed and the feedback resistor 45, Fig. 4, is replaced by a capacitor, the circuit being analogous to an integrating amplifier. Instead of using input pulses the magnitude of which is indicative of the analogue to be stored the circuits may be employed in the case where the input signal is in a time duration form when an integrating circuit, Fig. 6 (not shown), is inserted between the input terminals and the amplifier 43.