Patent GB-797736-A (GB)
Title: Electrical switching circuits
IPC: G11C19/28
Filed: 1955-12-09
Abstract: 797,736. Electric digital-data storage apparatus. WESTERN ELECTRIC CO., Inc. Dec. 9, 1955 [Dec. 13, 1954], No. 35433/55. Class 106 (1). [Also in Group XXVIII] An electric switching circuit comprises OR units connected to the inputs of an AND unit, a signal from one OR unit only being transmitted through the AND unit at any time, signal(s) to the other OR unit(s) being obliterated or " swamped " by control pulses. Fig. 1 illustrates the principle of the invention. Each of the OR units 21, 22 ... 23 has a signal input P, Q . . . T and a control input A, B ... E. To enable, e.g., the signal pulse train 26 at P to be transmitted through the AND unit 24, continuous trains of pulses like 28 are applied to - inputs B ... E so as to " swamp " the other signals, while input A is de-energized. A further control input (Fig. 2, not shown) may be connected to the AND unit to inhibit the latter when no signal is required. The OR units may each have more than one control input, the inputs being energized according to a binary - combination code. An AND unit, Fig. 4, maycomprise a positive-pulse-coincidence diode circuit 52-54 whose output is applied to the emitter of a transistor 45 in a pulse regeneration amplifier circuit. The output pulses applied via transformer 58 and diode 57 to terminal 46 are timed by clock pulses applied from 47 to the transistor base. An OR unit may be similar except that the input diodes are reversed; alternatively the amplifier circuit may be omitted, and the OR unit (indicated by OR(+), see, e.g., 206, Fig. 11) formed from the diodes such as 57 at the outputs of AND or other units. Various switching arrangements are described including a computer programme matrix and a converging " tree " switch (see Group XXXVIII). Shift register. Each of the stages 201, 202 ... 203 of a shift register, Fig. 11, comprises two OR units, such as 206, 207, connected to the inputs of an AND unit (208), the amplifier circuits, such as 211, being shown separately. Information is entered serially via 191 and OR unit 206, and the output of unit 208 is connected D through 211, a - delay unit 209 (where D is a 2 digit period) and a further amplifier 213 to the signal inputs of both OR unit 207 and the lefthand OR unit in the next stage 202. Since each D amplifier provides a delay of -, the loop circuit 4 207, 208, 209 and the similar circuits in higher stages, will each store one digit. Input 214 controls the left-hand OR units 206 &c. directly, and the right-hand units 207 &c. through inhibit unit or negator 215, whereby control pulses at 214 " swamp " the signal inputs to 206 &c. and the stored digits circulate through the delay loops including 207 &c., while, when a control pulse is absent, the output from 215 " swamps " the recirculated digits at 207 &c., but allows such digits to be entered into the next higher stages and input digits to be entered from 191. Delay line storage registers. The register 101, Fig. 8, forming part of a computer storage unit, stores a 16-digit binary number in a delay loop comprising AND unit 121, OR unit 122 and delay units 123, 124. The register is selected by a signal on lead 132 in combination with a " gate address " signal at 139 which cause AND unit 141 to transmit a set " 0 " pulse to delay loop memory unit 144 which, in the " 1 " state, applies a pulse, every digit interval, to OR unit 149 and through a delay to OR unit 135. To write a number on lead 126 into the register, a " write order " signal is applied also to lead 131, thus inhibiting unit 138 connected to the other input of OR unit 135. Unit 135 is therefore not energized, thus removing inhibition from unit 129 to which the number is applied, and inhibiting AND unit 121 in the register recirculation loop. If the " write order " signal is not applied, unit 129 remains inhibited, and the stored number is read out via OR unit 149, lead 159, Figs. 8 and 10, AND units 156, 161, AND unit 165 (which receives a continuous train of pulses on its second input during read-out) and OR unit 171 which is " swamped " by a write order. The storage unit comprises 11 further registers whose outputs are each connected via an OR unit like 149 and a lead such as 87, 88 to one of 4-input AND units 156-158; since only one register is selected at a time, the other register outputs are " swamped " by the pulses from associated memory units like 144. The first eleven registers may be cleared by deenergization of lead 91 connected to the recirculation AND units such as 121. The twelfth register (Fig. 9, not shown) is modified so as to permit concurrent writing in and reading out.