Patent GB-1076632-A (GB)
Title: Improvements in or relating to process control timers
Inventor: REEVES ALBERT GEORGE MICHAEL
IPC: G05B19/07
Filed: 1964-03-19
Abstract: 1,076,632. Timed control of electric circuits. PLESSEY-UK Ltd. Feb. 26, 1965 [March 19, 1964], No. 11698/64. Heading G3T. In a process control timer, clock pulses are fed to a binary counter, B1, B2 . . . Bp, of which the outputs go to pairs of diode AND gates which control bi-stable switches operating electric load switches according to a timed programme. Each AND gate actuates the corresponding switches ON and OFF at pre-set numbers, and at a number determining the end of a cycle the counter resets. For economy of binary stages and inputs per diode gate where a large number of load circuits is required, the counter may be reset for each discrete interval of the cycle. Thus in a modification, Fig. 2 (not shown) the counter provides OFF pulses which cause the bi-stable switch that is ON to switch OFF and in so doing to switch ON a bistable switch that is next in sequence, whilst the counter is reset to zero. A new count actuates the gate of the second bi-stable switch, which is turned OFF and a third one ON, the counter again going to zero. The last switch in going OFF turns the first one ON and the cycle is repeated. An output from each load switch as it comes on resets the counter. False operation of the gates is prevented by a disabler or monostable switch (A) which cuts off supply from all the gates for a finite time which is less than the unit pulse time but greater than the resetting time. A variant system, Fig. 3 (not shown) is used where all dwell times are the same. Bi-stable stages are arranged so that an ON state is passed from one to the next by a pulse on a common shift line. Through OR gates as shown, only the AND gate relating to the one bi-stable switch at ON receives the counter signal. This turns the switch OFF and a second one is turned ON, signalling to the OR gate controlling the AND gate of this second switch to prepare it for the appropriate count which starts simultaneously. On actuation by this count, an OFF signal goes to the second switch and a third switch goes ON. When the last is OFF the cycle repeats. Economy in the number of load switches is effected by another arrangement, Fig. 4 (not shown) wherein N loads L 1  to Lmn are arranged in a cross-point switching matrix. Horizontal scan switches H 1  to H n  control vertical switch lines in the matrix, whilst vertical scan switches V 1  to Vm control horizontal switch lines. A resetting circuit (not shown) ensures that one and the same load is always switched on at the start. On switching on from zero, only V 1  and H 1  are ON and only L 1  energized. A suitable output voltage from H provides an input to the column of gates D 1  to D m . The other input to each gate will have been connected to the timing gate which will give each load its required ON time. The diodes in the remaining columns of the matrix will be inhibited. When the end of ON for L 1  is reached a pulse will occur at the output of the timing gate. This will be repeated at the output of D 1  and appear at the input of the bi-stable stage of V 1 . The latter will go OFF and L 1  be de-energized, whilst a pulse will go to the disabler (A) to reset. V 2  will come ON and energize L 2 . The total ON time for the N loads is exactly the sum of the individual ON times. In case the number of loads is not factorizable so that m x n switching points will control only (m x n - l) loads, a modification, Fig. 5 (not shown) enables the last l in any vertical column (say the last one) to be skipped. There are no load connections at these points but at the one directly following the last load a pulse generator circuit is arranged and the isolated output from this point goes to the common shift line of the horizontal scan. When this point goes ON the scan changes from H n  to H 1  and the last l cross points are omitted. In a simplified arrangement, Fig. 6 (not shown) the cycle is divisible into regular subcycles. The number of vertical scan switches becomes equal to the number of time intervals in a sub-cycle and the number of horizontal scan switches equals the number of sub-cycles. The appropriate time pulse goes directly to each vertical scan switch and the feedback from each horizontal scan switch is omitted. The counter resets after each sub-cycle. Where frequent changes of time and load pattern are required, a plug board may be inserted between the gates and the diode matrix. Load skipping means may also be provided.