Patent GB-1400901-A (GB)
Title: Measuring system
IPC: A01K67/00
Filed: 1973-01-02
Abstract: 1400901 Measuring temperature electrically: voltage measuring MAY & BAKER Ltd 7 Dec 1973 [2 Jan 1973] 218/73 Headings G1N and G1U [Also in Division H3] A measuring system has a signal processor 34 in which a signal representative of the instantaneous value of a parameter being measured e.g. temperature, is utilized as a reference signal against which the next following signal is compared and so on and in which only signals identical to or within a predetermined limit of the immediately preceding signal are passed to the output. The temperature of thermistor 10 varies the interval between 12 millisecond pulses from a multi-vibrator including transistors 15, 16 and the resulting signal is applied to a crystal controlled transmitter 11, 12, 13 which therefore produces 12 millisecond pulses of frequency 28-28À5 MHz separated by the temperature dependent intervals in the region of 2-3 seconds. There may be ten transmitters each as in Fig. 1, each with a different frequency. The radio signal from each is transmitted to a separate superlet receiver 32 where it is demodulated and the resulting pulse passed to a pulse width discriminator which accepts pulses of greater than ten and less than sixteen milliseconds duration and produces for each pulse accepted an output pulse of fixed duration, say 100 micro-seconds. The resulting pulse track passes to the processor 34, which turns the incoming signals into a 10-bit binary number representing the period between successive pulses. The processor is set initially with a first 10-bit counter 41 at zero and a second counter 42 holding the count previously held_in the counter 41, the input pulse producing a Q output from flip-flop 44 to gate clockpulses from generator 40 through NAND gate 43 into the first counter which counts up, and to the second counter which counts down. If the second counter reaches zero whilst the first counter is still increasing then flip-flop 46 changes state via NOR gates 47, 48, 49, NAND gate 50 and inverter 51, in response to a zero signal from the second counter, whereby NAND gate 52 is gated "on" while NAND gate 45 is gated "off" so that the second counter 42 also begins to count up. When the next signal is received from the pulse width discriminator 33, Fig. 2 its leading edge changes the state of the flip-flop 44 so that the gate 43 is inhibited and the counts in the counters are frozen. The count in counter 41 now contains the measured value of the last period and the count in counter 42 contains the difference between this and the previously. measured value of period. The trailing edge of the input signal triggers a "transfer" monostable which produces a positive output at terminal 56 and a negative output at terminal 57 which samples the output of counter 42 and if this is within three counts of zero, the transfer pulse gates NOR gate 58 to switch flip-flop 59 and after inversion at 60 the pulse passes to an appropriate channel memory in converter 35, Fig. 2 which includes NOR gates 61-70, the other input to each of which is a signal from the channel selector 30. The least significant bits of counter 42 connect to NOR gate 47 and the eight most significant bits are connected in groups of four to NOR gates 48, 49. If a count of three or less is in the counter 42 than there is either no signal or signals appearing on one or both of the leads connected to NOR gate 47 whilst there will be no signals from the counter to NOR gates 48, 49. Thus NAND gate 80 (which receives the Q output from flip-flop 81) passes a pulse to NOR gate 58 which also receives the Q output from the transfer monostable 55. Thus NOR gate 58 pulses the clock input of flipflop 59. But if counter 42 contains a count of four or more flip-flop 59 receives no clock input pulse. Where the count is within three of zero, the Q output of monostable 56 acts via "load" monostable 85 which loads the last measurement from counter 41 into counter 42. Also "reset" monostable 88 acts to reset flip-flops 44, 46, 59 and 81 and to clear counter 41. A "channel acquired" output signal is transmitted to the channel selector 30 to index it to interrogate the next transmitter. The measured value is also passed to D-A converter 35 when the count in the second counter is within three of zero. Although the measured value is not passed to the converter when the count of counter 42 is not within three of zero still the count in the counter 41 is passed into the counter 42 to await the beginning of the next cycle. An alarm device 39 connected to channel selector 30 is actuated if a channel produces an, unacceptable signal after being sampled a given number of times.