Patent UA-93742-U (UA)
Title: driver of single package that contains a programmable number of SYMMETRIC CODE SERIES of pulses with programmable time parameters
Inventor: KOROBKOV MYKOLA HRYHOROVYCH
IPC: H03K3/78
Filed: 2014-05-19
Abstract: Driver of a single packet which contains a programmable number of symmetrical code series of pulses with programmable timing parameters multiples of the period of continuous periodic pulse sequence supplied to the input from quartz oscillator output comprises two reversible binary counters having input of synchronization pulses, input of adjustment to addition / subtraction mode, input of permit of synchronous parallel loading and inputs of loaded data, input of count mode permit, input of asynchronous installation to zero state, the overflow output; first (four-input), second (three-input) and third (two-input) OR elements; two inverters; circuit of connected in series resistor and capacitor; synchronous D-flip-flop with input asynchronous of installation of zero state; first and second two-input elements AND, the first and second elements OR; common point of the connected in series resistor and capacitor is connected to the data input of the first D-flip-flop, to one input of AND gates; output of first AND element is connected to the input of asynchronous installation of D-flip-flop to zero state; the clock input of D-flip-flop forms the input of start pulses; the second input of second AND element is coupled to the output of the second OR gate one input of which is connected to the output of the D-flip-flop; the output of the second AND gate is connected to the inputs of t asynchronous installation to zero state of counters; outputs of bits of the second counter are connected to the inputs of the first element OR; clock inputs of the counters are connected together to form the driver input - input for supply of continuous periodic pulse sequence from the output of external oscillator; parallel loading inputs of the first counter form the inputs of adjustment of the driver to given parameters of output pulses. There are included: the third and fourth reversible binary counters having input of synchronization pulses, input of adjustment to addition / subtraction mode, input of permit of synchronous parallel loading and inputs of loading data, input of count mode permit, input of asynchronous installation to zero state, an overflow outlet ; fourth and fifth elements OR; first and second two-input AND-NOT elements, wherein the overflow output of the third counter which forms the output of the driver is connected to the input of permit of synchronous parallel loading, input of the fourth OR gate, input of the second counter count mode permit and the input of the first inverter, output of that is connected to the input of the third counter counting mode permit, the second input of the first AND gate, and inputs of first and second AND-NOT elements; output of the first OR gate is connected to the second input of the fourth OR gate and the input of the second inverter, its output is connected to the first input of the third OR gate and the second input of the first AND-NOT element output of which is connected to the input of permit of the first counter counting mode; the output of the fourth OR gate is connected to the second input of the second OR gate, the input of the fifth OR element and the input of the fourth counter counting mode permit; the second input of the fifth OR gate is connected to the third input of the second OR gate and the output of the fourth counter overflow; the output of the fifth OR gate is connected to the input of permit of the fourth counter loading mode; first counter overflow output is connected to the second input of the third OR gate and the second input of the second AND-NOT element; output of the third OR gate is connected to the input of adjustment to addition / subtraction mode of the second counter; output of the second AND-NOT element is connected to the loading permit input mode of the first counter; the clock inputs of the third and fourth counters are connected to the clock inputs of the first and second counters; inputs of asynchronous installation to zero state of the third and fourth counters are connected to the output of the second element AND.