Patent GB-938517-A (GB)
Title: Apparatus for the digital coding of analogue quantities
IPC: H03M1/00
Filed: 1961-12-18
Abstract: 938,517. Electric selective signalling systems. GRETAG A.G. Dec. 18, 1961 [Dec. 21, 1960], No. 45330/61. Class 40 (1). In a voltage digitizing system an unknown voltage VE is compared with a known voltage VH by a vibrating contact 5 and the resulting square-wave, at E, which represents the direction and magnitude of the difference by its phase and amplitude, is amplified and used to control the feed of clock pulses V1A to a threedenominational accumulator 14h, 14z, 14e which appropriately alters the known voltage VH until the difference between it and the unknown voltage is less than the smallest change that can be made in the known voltage. The signal produced at E by the vibrating contact 5 represents, by its peak-to-peak amplitude, the magnitude of the difference and by its phase, the direction of the difference, and these two aspects of the same signal are used (a) to select that denomination of the accumulator into which clock-pulses are to be fed and (b) to select whether the clock pulses are added or subtracted. (a) Denomination selection. The signal at E is amplified, phase-split PK and its peak-topeak amplitude is applied via rectifying network C4, C5, D3, D4 to a first threshold circuit MM1 and to a second threshold circuit MM2 via a ten-times amplifier 46. These circuits so control an attenuator 6 via forward and reverse solenoids SV, SR that the amplitude of the voltage reaching E is maintained within certain limits. Thus if the attenuator is on its rest contact r<1> and if the unknown input voltage VE changes, by a large amount, suddenly, then the amplitude of the signal at E will rise and the threshold circuits will respond to step the attenuator through its contacts el, z<1>, h<1>, in turn, until the amplitude of the signal at E is within the set limits. At the same time a denomination selecting bank 35 is stepped in such a way that if a high attenuation is required then a high denomination of the accumulator is selected to which the clock pulses V1A are fed, and these clock pulses, when received by the accumulator tend to reduce the amplitude of the signal at E so that eventually the threshold circuits will respond again to reduce the degree of attenuation, which in turn, causes a lower denomination of the accumulator to be selected. (b) Selection of addition or subtraction. The clock pulses which are applied to the denomination-selection bank 35, and thence to the accumulator are synchronized with the contact 5 and each occurs when the contact 5 is sampling the known voltage VH. Also the signal which reaches E, having had its D.C. component removed by a blocking capacitor C1, will be positive at the instants when the contact 5 samples the known voltage if the known voltage is larger than the unknown voltage, or alternatively, if the known voltage is less than the unknown voltage the signal at E will be negative when the contact 5 samples the known voltage. This fact is used to select whether clock pulses sent to any denomination of the accumulator are to be added or subtracted by means of the phase-splitter PR and two diode gates 31, 33 in each denomination of the accumulator. Thus when a clock pulse arrives at the pair of gates 31, 33 in any denomination only the appropriate one will be open. The other one will, of course, open afterwards but its opening will not coincide with a clock pulse. The system described can digitize both positive and negative input voltages, their sign being determined by a unit BS. This unit is controlled by carry pulses from the highest denomination 14h of the accumulator as it carries negatively from 0 to 9. Thus, if, as shown, the circuit is set to digitize a positive voltage and a negative voltage is entered then immediately clock pulses are applied to the highest denomination in an attempt to reduce the known voltage to the level of the negative input voltage and then will result in the highest denomination passing from 0 to 9. This fact is recognized by the unit B5 which then interchanges the connections PW4, PW5 from the phase splitter to diode gates 31, 33. The unit BS also provides a visual indication of the sign of the input voltage by a flag 48. Specificaion 918,940 is referred to.