Patent GB-933066-A (GB)
Title: Computer indexing system
IPC: G06F9/355
Filed: 1961-07-25
Abstract: 933,066. Digital electric calculating-apparatus. SPERRY RAND CORPORATION. July 25, 1961 [July 25, 1960], No. 26942/61. Class 106(1). A stored programme computer comprises a memory for storing instructions and operands, means for selecting said instruction in a predetermined sequence, circuits for manipulating said operands in response to said instructions, one or more addressable registers for storing operands for modifying said instructions, means responsive to an instruction for altering the contents of a selected addressable register as a function of the contents thereof, and means responsive to the altered contents of said selected addressable register for predetermining the subsequent sequence in which instructions are to be selected. The concept of modifying an address within a machine instruction by a modifying factor and thereafter changing the modifier itself is called " indexing." General arrangement.-The computer described operates in parallel mode employing words of 12 decimal digits each decimal digit being represented by 4 binary bits plus a checking bit. The computer comprises a memory 152, an arithmetic unit 131, instruction registers IR1 (101) and IR2 (107-8), control counters 104, 106, control circuits 148, a B or modification adder 139 and a plurality of addressable registers 121. A normal instruction such as an " add " instruction has the form, II AA BB MMMMM where the I digits specify the required function, the A digits specify the address of an addressable register 121, the B digits specify the address of an addressable register 121 in the case when a portion of the contents of such register are used to modify the M digits, and the M digits refer to the address in the memory of an operand or instruction and may be altered by addition or subtraction of the contents of an addressable register selected by the B digits. The computer operates with minor cycles of eight pulse times t 0 -t 7  each. Normal instruction.-A normal instruction such as an " add " instruction comprises 6 minor cycles. On starting the computer the first instruction is called for and during the first minor cycle the contents of the control counter 104 are added to zeros supplied by a circuit 147 in the B adder 139. The output of the B adder is supplied to an address decoder 141 for the memory 152, the contents (N) of the selected memory location N being read out on to a bus HSB-R during the second minor cycle and applied to the register 101 and the B digits are applied via a gate 117 to a register selector register 118 to select an addressable register 121, the five least significant digits of the selected register being applied together with the M digits from the register 101 to the B adder 139. The modified M digits are now applied to select an operand from the memory 152. The instruction digits I are passed to section 107 of the instruction register IR2 where they are arranged to cause selection of further control signals from the circuits 148. During the third minor cycle, the A digits are effective to cause the contents of a selected addressable register 121 to be read out as an operand to the arithmetic unit 131, together with the operand from the memory 152. During the fourth minor cycle, the desired operation is effected in the airthmetic unit 131 and the result becomes available at a gate 126 for entry with the circulation path of the registers 121. During the fifth minor cycle the contents of the counter 104 are passed to the B adder 139 where they are increased by one and the next succeeding instruction is called for via the address decoder 141. Indexing instruction.-The contents of a typical B register may be designated as NNN DDDD bbbbb where the N digits form a counter for counting the number of repetitions of a given programme loop and the D digits an increment used to vary the modifier portion b which is added to the memory address MMMMM of the instruction. There are provided six different indexing instructions, the M digits of these designating an address to which control is to be transferred. The operations in a typical indexing instruction are as follows. The N digits of the addressable register designated by AA have unity subtracted from them and are then tested to see if they are zero. If they are zero, the contents of the control counter 104 are passed through the B adder, increased by unity and the next instruction is extracted for normal continuance of the programme. In any case, the D digits are added to the modifier portion b and if the counter is not zero, a signal is produced by the arithmetic unit to cause transfer of control to the memory address designated by the M digits. Thus a series of instructions forming a loop may be terminated with an indexing instruction of this type, the M portion designating the first instruction in the loop, which is then reiterated N times. Specification 824,968 is referred to.