Patent GB-1480534-A (GB)
Title: Switching arrangements
IPC: G06F13/40
Filed: 1974-12-12
Abstract: 1480534 Data processing COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII-HONEYWELL BULL 12 Dec 1974 [12 Dec 1973] 53830/74 Heading G4A In a data processing system comprising a plurality of central processing units CPUA, CPUB (Fig. 1) ... CPUN selectively connectable to any of a plurality of peripheral units E1, E2 ... EP by an individual transfer channel A1, A2 ..., B1, B2 ... each processor has an associated switching assembly 102 with gates PA1, ... PAP; PB1 ... PBP; ... PN1 ... PNP and each peripheral has an associated switching assembly 104 with gates DA1 ... DN1; ... DAP ... DNP, distibution blocks BSDA, BSDB ... (there being one for each processing unit) controlling the switching assemblies 102 and control blocks BCS1, BCS2 ... (there being one for each peripheral) controlling switch assemblies 104. Whenever a processor, e.g. CPUA is in communication with a peripheral, e.g. E1, any other processor, e.g. CPUB may be in communication with any peripheral other than El. Request for access by CPU.-If CPU A requests access to a peripheral it sends data to recorder-decoder RA in the first distribution block. If peripheral E1 is requested an output signal (RA1, Fig. 2A, not shown) renders conductive control signals (CRA1, CSA1) and enables gate PA1. Provided that the peripheral is available, indicated by bi-stable BE1 being in its "1", gate CPA1 is enabled to (1) reset bistable BE1 and (2) signal a control register K1 in the first control block associated with peripheral El which provides a signal on an output (K1A, Fig. 2B, not shown) to enable gate DA1 to transmit the information on channel A1 to the peripheral. If CPUB then requests access to the same peripheral since the bi-stable is in its reset state, instead of a first gate (CPB1) being enabled a second gate (CEB1) is enabled to provide a signal (1) to CPUB that it has not been granted access and (2) to a deferred register J1 associated with the first peripheral to provide a signal (J1B). When the CPUA finishes its transfer of data a path SRA causes the recorderdecorder RA and bistable BE1 to be reset and set respectively after a delay. Circuit CJ1B, connected to the register J1, then feeds a signal to processor CPUB to indicate that the peripheral El is free. Request for access by peripheral.-When peripheral El requests access, its request signal is fed, provided the bi-stable BE1 is set via gate (CE1, Fig. 2B, not shown) to a gate (GK1) to permit transfer of data from a back up register M1 (associated with the peripheral and holding the name of the channel with which the peripheral was previously in communication, e.g. CPUA) to the control register Kl. This results in an output signal (K1A) from the register to activate gate D1A. If CPUA is available the gate (FA1) is enabled by the signal to enable, via OR gate (MF1) and circuit (CK1A), the input of recorder-decoder RA associated with the first peripheral El so that it provides an output signal (RA1) to enable gate PA1 to put the peripheral in communication with the CPU. If the CPU is non-operational or linked to another peripheral the control register K1 is arranged to supply a signal on its next output (K1B) so that if the next CPU i.e. CPU-B is available it is put into communication with it. The back up registers are never reset to zero so that if a peripheral which has not been in communication requests a CPU it first addresses the one in its back up register.