Patent GB-701619-A (GB)
Title: Improvements in or relating to electronic counters
IPC: H03K23/82
Filed: 1951-11-30
Abstract: 701,619. Digital electric calculating apparatus. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. Nov. 30, 1951 [Nov. 30, 1950], No. 28211/51. Class 106 (1) In an electronic counter comprising a plurality of bi-stable trigger stages connected in cascade by means of inter-stage coupling circuits so that each stage when triggered from its actuated state to its state of rest triggers the next succeeding stage there is included a feed back connection from each of several stages to the next preceding stage, the arrangement being such that when one of the first mentioned stages is triggered from its state of rest to its actuated state the next preceding stage is triggered from its state of rest to its actuated state by an impulse fed back by the feed back connection. Fig. 1 shows five flip-flop stages connected in cascade and denoted I to V. Stage I is provided with a symmetrical input to its two tubes as indicated, inter-stage coupling connections 2, 3, 4 and 5 are taken from the tubes which are " on " in the state of rest of each stage and these connections are connected to symmetrical actuation inputs of the next succeeding stages II to V respectively. From the output 7 of the tube which is "off" when the stage II is in a state of rest there is provided a feed back connection comprising a network II having a time constant equal to at least the change-over time of a stage. Similar feed back connections are provided between the other stages as shown at 8, 9 and 10. Starting from a state of rest in all stages, i.e. zero count the first pulse applied to terminal 1 triggers this stage to its actuated state. The second pulse applied to terminal 1 resets the stage 1 to its state of rest. A negative pulse is transmitted by the connection 2 and stage II is triggered to its actuated state the resultant negative impulse delivered by the output 7 of stage II is fed back through the network 11 to the tube which is now " on " of stage I and promptly triggers this stage back to its actuated state. Two impulses has thus been applied to the counter and the first two stages are in the actuated state. The third impulse received at 1 resets stage 1 and produces an output pulse which resets stage II and the output in turn triggers stage III. Stage III is thus brought to the actuated state and through its output 8 delivers a negative impulse which is fed back to stage II through network 12. The stage II is reset to its actuated state and in turn resets stage I to its actuated state in like manner. Three impulses have been applied to the counter and the first three stages are in the actuated state. The same process is repeated for each impulse received until the counter is filled when the next impulse resets it to zero. If now the feed back connection is omitted from stage II as shown'in Fig. 3, the counter constitutes a scale of ten counters, because the stage I will deliver only one actuative pulse to stage II for every two impulses applied to I. The first impulse of each pair of impulses brings the stage I to its actuated state, and the second impulse resets it to its state of rest, hence the stage II is triggered when the second impulse is received. In such a coded decimal system as this it will be noted that the stage I records the digit One, and each of the stages II to V records the digit two, so that the numbers 0 to 9 are recorded by combinations of the values 1, 2, 2, 2 and 2. Two actuative inputs 49 and 50, Fig. 3, can be provided introducing coded trains of pulses made up on the above basis, the first pulse being applied to the terminal 49 and the remaining four to the terminal 50 by means of a gating arrangement of known type. The arrangement described with reference to Fig. 3 may be modified in which case the first four stages record in step by step fashion as in the arrangement described with reference to Fig. 1, while the fifth stage acts as a binary scale of two stages, i.e. there is no feed back connection from the fifth stage to the preceding stage. The code for expressing numerical values from 0 to 9 is now represented by the values 1, 1, 1, 1, 5. For recording and adding such coded trains the first four pulses will be applied to the input of the first stage, and the fifth pulse is applied to the fifth stage input of the scale of the counter. In each of the Figs. 1 and 3 an output impulse appears at 6 when the counter resets to zero which may be fed forward into a counter of higher denomination. If it is desired to clear the counter at an intermediate phase, impulses are applied at terminals 15, 16, 17, 18, 19 simultaneously. These impulses serve to reset each stage of zero by operating on the valves which may be " on " in the actuated state of each stage to return them to the " off " state and thus restore each stage to its state of rest. Specification 683,180, [Group XL(b)], is referred to.