baber/WOPTO huggingface dataset:
Patent JP-H07111341-A (JP)
Title: Current control type light emitting device array
Inventor: UTSUKI KOJI
IPC: H01L27/32
Filed: 1993-10-12
Abstract: PURPOSE:To enable an active matrix type light emitting device array wherein current control type emitting devices such as ELs or LEDs are arranged in array to be lessened in overall length and number of intersections of wirings, reduced in occurrence rate of troubles caused by disconnections or short circuits of wirings, and improved in display quality by a method wherein various wirings required for driving the light emitting device array are lessened in kinds. CONSTITUTION:The source electrode (opposed to an electrode located on the side of a light emitting device) of a current control transistor QI and one electrode of a capacitor C are connected to a scanning electrode wire 3N of a column (N-th column in a selection figure) different from one (N+1st column) to which a unit pixel 10 containing the transistor QI and the capacitor C belong. When a forward diode Di is inserted between a power supply electrode 5 and a light emitting device EL, the light emitting device EL can be prevented from deteriorating in performance due to that the light emitting device EL of a non-selective pixel is reversely biased.
Patent JP-S63106807-A (JP)
Title: Industrial robot
Inventor: KUBOTA HITOSHI
IPC: G05B19/4068
Filed: 1986-10-24
Abstract: PURPOSE:To improve the debug efficiency by tracing an operating program accurately at the next operation and tracing back a path reversely traced at the next operation accurately at the reversing. CONSTITUTION:A next operation confirming means 100 to confirm the operation of the next step of an operating program, a reverse confirming means 101 to confirm the operation of the reverse step of the operation program, a means 103 executing the next operation through the operation of the next operation confirming means, converting an instruction into the instruction for the reversing and storing the instruction into a reverse operation trace buffer 106, and a trace buffer read means extracting the said instruction from the reverse operation trace buffer and sending it to an execution means 104 when an instruction exists in the reverse trace buffer in executing the reversing through the operation of the reversing confirming means 101 are provided. The operation program is traced accurately at the execution of the next operation and the locus executed at the next operation is traced accurately reversely at the execution of the reverse operation. Thus, the debug efficiency of the operating program of the robot is improved.
Patent JP-2000084683-A (JP)
Title: Method and device for abnormality monitoring at laser beam welding
Inventor: INOUE HISASHI
IPC: B23K26/00
Filed: 1998-09-08
Abstract: PROBLEM TO BE SOLVED: To increase an information quantity in welding, to extract an abnormal cause as well as to monitor in process by measuring plasmatic potential generated from laser irradiation on front/rear face of a work and monitoring welding abnormality based on plasmatic potential. SOLUTION: A shield gas is injected from a nozzle 2 to a weld zone of a work and a laser beam L irradiates a weld zone. Among ionized plasmas, an electron of a negative electric charge is light, a gas body of a positive electric charge is heavy. Thus, metal vapor plasma 11 forms a positive electric field near the work 1 and a negative electric field apart from the work. The shield gas plasma 12 coming out from the nozzle 2 forms a positive electric field near the nozzle 2 and a negative electric field apart from the nozzle. An oscilloscope 5 is connected between the work 1 and the nozzle 2 to measure an electric potential, at a rear side of the work 1, the electric potential between the work 1 and an electrode 4 is measured by an oscilloscope 6.
Patent JP-H04133187-A (JP)
Title: Picture checking method
Inventor: YUSE CHIKARA
IPC: G06T7/00
Filed: 1990-09-26
Abstract: PURPOSE:To share evaluation value tables to reduce the memory capacity by discriminating picture information of each picture element of a check picture by a map table to select allowable picture information level and evaluation value table and discriminating success or failure by the evaluation value. CONSTITUTION:A map table 12 where a ground color part, a multicolor part, and the other part are preliminarily classified and evaluation value tables 13 for picture levels of respective colors of individual picture elements corresponding to the map table 12 are generated with respect to a reference picture 11, and a part out of the ground color part, the multicolor part, and the other part which picture information of each picture element of the taken-in check picture corresponds is discriminated by the map table 12 to select allowable picture information level and evaluation table 13, and success or failure is discriminated by the evaluation value. Thus, tables are shared by the fact that most of picture information is in the ground color of a print object, and the memory capacity is reduced.
Patent JP-S61131993-A (JP)
Title: Chrominance signal adjuster
Inventor: MOCHIZUKI KAZUO
IPC: H04N9/68
Filed: 1984-11-30
Abstract: PURPOSE:To reduce the size of a circuit scale and realize a full digital signal processing by realizing with a common circuit the functions to adjust hue and chromatic degree of saturation by multiplying the chrominance signal by a factor. CONSTITUTION:The chrominance signals that underwent a switching unit 3 and one that passed through a latch circuit 10 and a switching unit 5 are supplied respectively to multiplier 7 and 8 where they are multiplies by a multiplying factor. Respective products are subtracted 9, and are made chrominance signals. And when the signal S is '1' during the retrace line cycle, the switching unit 3-6 are made change to the input positions B, at the same time, the hue adjusting factor cos phi and the chromatic degree of saturation adjusting factor C are inputted to the multiplier 7. And to the multiplier 8, likewise, sinphi and the C are inputted. The respective product-outputs, C.cosphi and C.sinphi are held by latches 11, and 12 at the first transition of a signal SP. In cycles other than the retrace line cycle, the chrominance signals are respectively multiplied by the holding factors of the circuits 11 and 12 by multiplication 7 and 8, and the calculation is performed for adjusting hue and chromatic degree of saturation.
Patent JP-S63109160-A (JP)
Title: Thin organic film forming device
Inventor: FUJIKAWA HIROYUKI
IPC: C23C14/24
Filed: 1986-10-24
Abstract: PURPOSE:To deposit a thin org. material film which has high adhesiveness and is dense and smooth by evaporation on a substrate surface without impairing the properties thereof by evaporating an org. material by a emitter on a specific metallic wire and accelerating the vapor thereof by a unipotential lens at the time of forming the thin org. material film on the surface of the substrate consisting of various kinds of materials. CONSTITUTION:An org. high-polymer raw material 7 such as PE, polyamide or polystyrene is coated on the surface of the emitter 1 having the sharply pointed extremely fine acicular crystal on the W wire. The emitter 1 is energized to heat and melt the raw material 7 and the high-polymer material 7 is formed into fine particles by utilizing an electric field elimination method without decomposing said material. The particles of the high-polymer material are passed through a window hole 4a of an emitter case 4 and a window hole 8a of a counter electrode 8 impressed with a negative voltage, then the particles are converged by the unipotential lens 3. The thin film of the high-polymer material is thus formed on the surface of the substrate 6 consisting of metals, ceramics, inorg. materials or org. materials.
Patent JP-H06112215-A (JP)
Title: Manufacture of self-matching bi-polar transistor
Inventor: IMAI KIYOTAKA
IPC: H01L29/732
Filed: 1992-09-24
Abstract: PURPOSE:To prevent drop of shut-off frequency by making the concentration of a base layer different from that of a link polysilicon layer at growth, for lower base resistance. CONSTITUTION:An N<+>-type buried layer 2, an N-type connector layer 3, a field oxide film 45 and a collector draw-out layer 5 are formed on a p-type silicon substrate 1, and a silicon oxide film 6 (film thickness 40-150nm) is grown all over the surface, and then, a P<+>-type polycrystal silicon 7 and a silicon 7 and a silicon nitride film 8 are formed, and further, patterning is executed with anisotropic dry etching. Then, a P<+>-type base polysilicon electrode 7a is formed, and an emitter is opened at its center. The first side wall 9 is formed on its side wall, and isotropic wet etching is made for removing the silicon oxide film 6 inside the opening, for receding from the edge of the opening. On the N-type collector layer 3 from which the silicon oxide film 6 has been removed, the first link polysilicon layer 11 is grown from the eaves of the base electrode 7a and a silicon epitaxial layer 10 (film thickness 3-10nm), far lower base resistance.
Patent JP-S62112405-A (JP)
Title: Piezoelectric resonator and fm demodulation circuit using said piezoelectric resonator
Inventor: YAMAMOTO TAKASHI
IPC: H03H9/205
Filed: 1985-11-11
Abstract: PURPOSE:To simplify the circuit by using an adhesive to stick two 3-terminal piezoelectric vibrating elements thereby making the pass band center of the amplitude characteristic coincident with a point of phase angle 90 deg. of the phase shift characteristic and using said piezoelectric resonator for the phase shift circuit of an FM demodulation circuit. CONSTITUTION:The piezoelectric resonator 1 is constituted by using an adhesives 3 so as to stick two 3-terminal piezoelectric vibrating elements 2, 3 formed symmetrically to the right/left. The elements 2, 2 are the piezoelectric vibration elements of the energy confinement type and thickness vibration mode in which split electrodes 5, 5 are formed to one side of the base 4 and a common electrode 6 is formed to the ground side. In the sticking above, the common electrodes 6 are overlapped and the split lead-out electrodes 7, 7' are directed upward for the one base 4 and directed downward at the other base 4. The electrodes 8 of the two bases are connected and led out and one set of electrodes in the opposite two-sets of split electrodes 7, 7' are connected so as to be crossed via the base and the split electrodes of the other set are led out to form IN, OUT, GND terminals respectively. Thus, in the resonator 1, the pass band center of the amplitude characteristic and the frequency at a point of phase angle 90 deg. of the phase shift characteristic are made coincident. The resonator 1 is used for the phase shift circuit of the qudrature type FM detection circuit, then a conventional RLC circuit is not required.
Patent JP-H0974261-A (JP)
Title: Terminal pin mounting structure in printed circuit
Inventor: YAMASHITA SHIYUUYA
IPC: H05K1/18
Filed: 1995-09-07
Abstract: PROBLEM TO BE SOLVED: To provide a terminal pin mounting structure, wherein terminal pins are mounted in a board in a state vertical truly to the board and at the same time, a reduction in a space is contrived for using a circuit board with printed circuits formed on both surfaces of the board and a jumping wire and through holes are dispensed with. SOLUTION: In a printed circuit of a structure, wherein circuits are respectively printed on both surfaces of a board 2 using each conductive member 3, a mounting hole 4 is bored in such a way that it is made to penetrate the member 3 on the surface on one side of the surfaces of the printed circuit and the board 2, a mounting hole 4 is bored in such a way that it is made to penetrate the member 3 on the other surface of the printed circuit and the board 2 and with mounting holes 4 bored in such a way that they are made to penetrate the members 3 on both surfaces of the printed circuit and the board 2, the outer diameters of the base parts 1b of terminal pins 1 are made to form into a diameter equal or somewhat larger with or than the inner diameters of the holes 4, the pins 1 are respectively made to insert forcedly in each mounting hole and the pins 1 are soldered to the members 3.
Patent JP-H1099250-A (JP)
Title: Wet wiper
Inventor: KADOTA MASARU
IPC: A61L2/16
Filed: 1996-09-26
Abstract: PROBLEM TO BE SOLVED: To give an excellent antibacterial performance and antibacterial persistence to an arbitrary matters such as office appliances, office goods, kitchen utensils and toiletries, a wall, a floor, etc., by wiping with a wet wiper. SOLUTION: This wet wiper is made by impregnating liquid for impregnating containing one or more antibacterial components into nonwoven fabric or wet strength paper, and at least one of the antibacterial components contained in the impregnating liquid contains antibacterial inorganic oxide microparticles constituted of an antibacterial metal component and inorganic oxide except for the said antibacterial metal component. The average particle diameter of the antibacterial inorganic oxide microparticles is 3-500nm, and the solid concentration of said antibacterial inorganic oxide microparticles contained in the impregnating liquid is preferable to be in a range of 0.003-0.05wt.%.
Patent JP-H03117026-A (JP)
Title: Filter and phase locked loop circuit
Inventor: OKUI TAMIO
IPC: H03L7/093
Filed: 1989-09-28
Abstract: PURPOSE:To easily adjust the control characteristic of a PLL circuit with use of the direct current voltage at a connecting point between a capacitor and a variable resistor by forming a filter, which is used for a loop filter, etc., to be a specified circuit. CONSTITUTION:For the filter to be used for the loop filter of the PLL circuit, a resistor R1 is connected between an input terminal 11 and an output terminal 12, one end of a capacitor C is connected to the output terminal 12, the other end is connected to one end of a resistor R3 and the other end of the resistor R3 is connected to the positive pole of a direct current voltage source V. The negative pole is grounded and a variable resistor R2 is connected between the other end of the capacitor C and the ground. Thus, the modulation gain of a voltage controlled oscillator 24 can easily be calculated from the direct current voltage of the connecting point between the capacitor C and the variable resistor R2.
Patent JP-H0970266-A (JP)
Title: Sushi rice enduring low temperature treatment
Inventor: SUZUKI KISAKU
IPC: A23L7/10
Filed: 1995-09-06
Abstract: PROBLEM TO BE SOLVED: To produce a sushi rice enduring low temperature handling, even when stored at a low temperature as well as at ambient temperature, preventing aging, deteriorating and spoiling the gustatory feeling. SOLUTION: The preparation process of vinegared rice 3 by adding mixed vinegar 4 containing pectin is repeated, as cold air is allowed to flow, to form pectized layers 6, 7, 8, for moisture retention and water holding, on the surface of each grain 5a of sushi rice 5.
Patent JP-H02103734-A (JP)
Title: Tracking controller
Inventor: MATSUSHITA MACHIKO
IPC: G11B7/0025
Filed: 1988-10-12
Abstract: PURPOSE:To prevent a malfunction by detecting whether the time when a tracking error signal whose level exceeds a certain range exists exceeds a prescribed time or not and starting a tracking servo loop at the time when it exceeds the prescribed time. CONSTITUTION:An auto-tracking (AT) error signal is inputted to a controller 10 through an A/D converter 8, and level decision of the AT error signal and counting of the time when the level is higher than a prescribed level are performed in a CPU of the controller 10 by software. The duration time for which the tracking error signal exceeds a certain range is added as a timing decision condition of transition from the turning-off state to the turning-on state of the tracking serov. Thus, stable track jump and tracking-on operations independent of minute defects or the like on an information recording carrier which are actually scattered are performed, and the malfunction due to minute defects, namely, AT deviation is prevented.
Patent JP-H0595061-A (JP)
Title: Semiconductor device
Inventor: OZAKI HIROSHI
IPC: H01L23/40
Filed: 1991-10-02
Abstract: PURPOSE:To penetrate a fixture through a heat dissipation fin mounting hole and mount the heat dissipation fins to a semiconductor device removably by boring the heat dissipation fin mounting holes to the semiconductor device on the heat dissipation fins and also boring the heat dissipation fin mounting holes on the semiconductor device to which the semiconductor fins are to be mounted. CONSTITUTION:Mounting holes 13 are bored at four corners of a flat bar 11 of a heat dissipation fin 1 so as to mount the heat dissipation fin 1 to a semiconductor device 12. On the other hand, even at the four corners of a heat diffusion plate 2 of the semiconductor device 12, there are bored mounting holes 14 to mount the heat dissipation fin 1. The rear side of the flat bar 11 of the heat dissipation fin 1 is made to abut on the front surface of the heat diffusion plate 2 of the semiconductor device 12 where a wire 10 is inserted into the hole 14 from the hole 13 and the wire 10 is bent so as to mount the heat dissipation fin 1 to the semiconductor device 12. This construction makes it possible to separate the heat dissipation fin 1 from the semiconductor device 12, and what is more, mount them separately.
Patent JP-2001076001-A (JP)
Title: Method for providing event information
Inventor: OMORI NOBUYUKI
IPC: G06Q10/06
Filed: 1999-09-09
Abstract: PROBLEM TO BE SOLVED: To provide event information such as an advertisement corresponding to a user's schedule, without having a user explicitly retrieve it. SOLUTION: In a calendar service providing device 1 providing service enabling the user to register and refer to an individual's or group's schedule via a network 2, an action object extracting part 103 extracts the behavior of the user from the schedule inputted by the user. An advertisement selection part 104 selects advertisement data to be sent according to the extracted behavior from an advertisement selection table 106 into which display conditions of the advertisement are entered previously. An advertisement transmission part 105 transmits the selected advertisement data or the URL for the advertisement data to a user terminal 3. Plural words which are 'action' and 'object' are extracted as the extracted from the schedule, and these key words are used to perform retrieval from the advertisement selection table 106.
Patent JP-2001074688-A (JP)
Title: Oxygen sensor element and formation method for lead part in oxygen sensor element
Inventor: SHIONO KOJI
IPC: G01N27/409
Filed: 1999-09-09
Abstract: PROBLEM TO BE SOLVED: To obtain an oxygen sensor element which is operated normally in such a way that the electric resistance of a lead part is not raised to such an extent that the oxygen sensor element cannot be operated even when the lead part is exposed to a gas, to be measured, having a reducing property. SOLUTION: A solid electrolyte body 2 which comprises a measuring electrode on the outside face on the side of a blocked end is provided with a first lead part 40 which is passed through a flange part G from the side of the blocked end and which is formed on the side of an open end. The solid electrolyte body is provided with a second lead part 42 which is formed so as to cover a part near the flange part G in a state that the first lead part 40 is formed. The respective lead parts 40, 42 are formed of platinum. Even when the first lead part 40 is formed to be thin on the corner part R1 of the flange part G, the lead parts as a whole satisfy a layer thickness of 10 μm or higher because the second lead part 42 is laminated on it.  As a result, even when the respective lead parts are exposed to a gas, to be measured, having a reducing property, it is possible to prevent the platinum from being sublimated to such an extent that this oxygen sensor element cannot be operated, and it is possible to prevent the layer thickness from being reduced.
Patent JP-H08123357-A (JP)
Title: Image display position setting circuit
Inventor: ISHII HIROBUMI
IPC: G09G3/20
Filed: 1994-10-20
Abstract: PURPOSE: To adjust an image display position in a PDP or LCD. CONSTITUTION: This circuit is equipped with a display control signal generating part 1 which generates a horizontal direction display control signal to display the screen left end of the PDP, etc., as a start point and a vertical direction display control signal to display the upper end of the screen as the start point based on the synchronizing signal So of a reference video signal, a first delay circuit 2 which outputs a required kind of horizontal direction display control signal based on the horizontal direction display control signal from the generating part, a first selector 3 which selects a required display control signal from signals from the delay circuit 2, a second delay circuit 4 which outputs a required kind of vertical direction display control signal with different delay time based on the vertical direction display control signal from the generating part,  a second selector 5 which selects a a required kind of display control signal from the signals from the delay circuit 4, and a synthesizing part 6 which synthesize each direction display control signal selected by each selector, and the image display position can be decided by a synthesized control signal.
Patent JP-S62117974-A (JP)
Inventor: TAKAHASHI EIJI
IPC: E06B3/58
Filed: 1985-11-13
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H0195603-A (JP)
Title: Phase adjustment type power synthesizing amplifier
Inventor: AKIBA YASUHIRO
IPC: H03F3/60
Filed: 1987-10-08
Abstract: PURPOSE:To simplify the phase adjustment by adjusting the length of a probe of plural hybrid integrated circuit amplifiers in parallel operation so as to adjust the phase. CONSTITUTION:A microwave RF passes through a waveguide 1 and is given to each hybrid integrated circuit amplifier 4 by using a probe 1 while its power is reduced by 3dB, and then the power is increased by 3dB and then combined. The amplifiers whose probe length differs and whose thickness of phase adjusting spacer 2 is varied are prepared and the phase is varied to match the phase of each hybrid integrated circuit amplifier 4 by varying the length (l). Thus, no conductor rod nor conductor spacer is used and the phase adjustment is facilitated.
Patent JP-S62111589-A (JP)
Inventor: HENRII GAATON RUISU JIYUNIA
IPC: H04N7/18
Filed: 1986-10-29
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H0895062-A (JP)
Title: Liquid crystal display element
Inventor: SHIMOMAKI SHINICHI
IPC: G02F1/1337
Filed: 1994-09-27
Abstract: PURPOSE: To provide a liquid crystal display element of which liquid crystal can be oriented in a favorable state with little turbulence and driven by low voltage. CONSTITUTION: A recessed part 31 is formed on a substrate 11 for forming TFT of a liquid crystal display element, and the TFT 14 is formed in the recessed part 31. A picture element electrode 13 connected to the active element 14 is formed on the main face of the base plate 11. A flattening film 17 is formed on the active element 14 and the picture element electrode 13 while filling the recessed part 31, and an orientation film 18 is formed thereon. The maximum inclination (ϕ) due to the recessed and projecting part of the surface of the orientation film 18 is made smaller than the cone angle (θ) of ferroelectric liquid crystal 23, and the turbulence of orientation due to the recessed and projecting part is restrained at minimum.