Patent SG-11201810373Y-A (SG)
Title: Method for patterning a substrate using a layer with multiple materials
Inventor: DEVILLIERS ANTON J
IPC: H01L21/768
Filed: 2017-05-17
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property 1111111011111111101 1111111111111111111111111111111111111111111111111111111111111111111 Organization International Bureau (10) International Publication Number (43) International Publication Date ......0\" WO 2017/205136 Al 30 November 2017 (30.11.2017) WIPO I PCT (51) International Patent Classification: KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, HO1L 21/027 (2006.01) HO1L 21/768 (2006.01) MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, HO1L 21/3065 (2006.01) PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, (21) International Application Number: SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, PCT/US2017/033051 TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (22) International Filing Date: (84) Designated States (unless otherwise indicated, for every 17 May 2017 (17.05.2017) kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, (25) Filing Language: English UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, (26) Publication Language: English TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, (30) Priority Data: MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, 62/340,279 23 May 2016 (23.05.2016) US TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). (71) Applicant: TOKYO ELECTRON LIMITED [JP/JP]; Akasaka Biz Tower, 3-1 Akasaka 5-chome, Minato-ku, Published: Tokyo 107-6325 (JP). — with international search report (Art. 21(3)) (71) Applicant (for JP only): TOKYO ELECTRON U.S. HOLDINGS, INC. [US/US]; 2400 Grove Boulevard, Austin, Texas 78741 (US). (72) Inventors: DEVILLIERS, Anton J.; 734 Tanner Rd., = Clifton Park, New York 12065 (US). MOHANTY, Nihar; = Nanofab 300 South, 255 Fuller Rd., Suite 244, Albany, New _ York 12203 (US). = (74) Agent: MATHER, Joshua D.; Tokyo Electron U.S. Hold- = ings, Inc., 2400 Grove Boulevard, Austin, Texas 78741 (US). = (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, = = CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, = DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, = = HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, = = (54) Title: METHOD = = = — = - Il FOR PATTERNING A SUBSTRATE USING A LAYER WITH MULTIPLE MATERIALS 1 1 141-) 121 (57) : Techniques herein enable integrating stack mate- rials and multiple color materials that require no corrosive gases for etching. Techniques enable a multi-line layer for self-aligned pattern shrinking in which all layers or colors or materials can be limited to silicon-containing materials and organic materials. Such techniques enable self-aligned block integration for 5 nm back- end-of-line trench patterning with an all non-corrosive etch com- patible stack for self-aligned block. Embodiments include using lines of a same material but at different heights to provided etch V::+ M Il kr) 0 ei IN © ei d i FIG. ..................> PIA selectivity to one of several lines based on type of material and/or 110 height of material and etch rate. 107 0