Patent MY-6900188-A (MY)
Title: Semiconductor devices
IPC: H01L27/06
Filed: 1969-12-30
Abstract: 1,001,908. Semi-conductor devices. TEXAS INSTRUMENTS Inc. Dec. 31, 1962 [Aug. 31, 1962], No. 49041/62. Heading H1K. [Also in Division H3] Interconnections between the various parts of a solid circuit formed in a semi-conductor wafer are made by depositing conductive material over the entire insulation coated face of the wafer to make contacts through opertures in the coating and then selectively removing it to leave only the required interconnections. A wafer containing a plurality of groups of transistors, capacitors, diode rectifiers and resistors, each capable of providing several different circuits with suitable interconnections is fabricated as follows: A 10- 15 ohm. cm. doped P-type silicon wafer, after polishing, etching and cleaning is coated with oxide by heating in steam. A repeating pattern of the group of apertures shown in Fig. 6 is formed in the oxide by photo-resist masking and etching techniques. Phosphorus is deposited and diffused into the wafer through the apertures to form N regions constituting the spiral and linear, resistor tracks, collector zones of the transistors, cathode zones of the diodes and zones of the NPN capacitors. During the process the oxide reforms in the apertures. A different pattern of apertures is then formed in register with the first by the same method and boron diffused through the apertures to form P zones constituting the transistor base zones, diode anode zones and the P zones of the capacitors. The transistor emitter zones and the outer N zones of the capacitors are next formed by diffusion from a mixture of oxygen and phosphorus pertoxide vapour through a third mask. Finally, apertures are formed in the oxide layer by a photo-resist masking and etching process to expose a portion of each zone of each circuit element. Each group of elements then appears as shown in Fig. 1, and consists of transistors 28-34, PN diodes 35-41, linear tapped resistors 25-27, spiral resistors 19-24 attached to an N zone of the NPN capacitors 13-18 respectively and large NPN capacitors 11 and 12. The logic circuits of Figs. 22 and 25 (not shown), and the flipflop circuit of Fig. 27 (not shown), can be formed from each group of elements in the resulting wafer by deposition of appropriate aluminium interconnections as in Figs. 21, 24 and 26 respectively (also not shown). This process is effected by vacuum evaporation of aluminium while the wafer is heated to slightly below the temperature of the aluminium-silicon eutectic. The energy of the bombarding aluminium atoms raises the temperature locally to the eutectic to form good atomic contact with the silicon in the apertures. A further photo-resist masking and etching step is used to remove the unwanted aluminium between the desired interconnections. After etching the back surface to reduce the wafer to the desired thickness it is scribed and broken up into single circuits. Each of these is mounted by solder glass on a ceramic wafer and connected by gold wires to metal tabs extending through the solder glass sealing a ceramic ring about the circuit. After applying varnish over the circuit and wires a lid is placed on the ceramic ring to form a hermetic enclosure. Use of germanium and A m B v  compounds in place of silicon is also suggested. Specification 958,241 is referred to.