Patent GB-1417410-A (GB)
Title: Buffer drive circuit for a metal oxide semiconductor memory system
IPC: G11C11/408
Filed: 1972-12-22
Abstract: 1417410 MOST gating circuits HONEYWELL INFORMATION SYSTEMS Inc 22 Dec 1972 [3 Jan 1972] 59462/72 Heading H3T [Also in Division G4] In a buffer drive circuit for a MOS memory system including an input gate 101, Fig. la, and an output driver 102, a first timing signal #1 is applied to initially condition the input gate 101 for sampling and storing an input signal Ao, to precharge the input circuit 102-14, 102-16 of the output driver 102 and to apply voltage signals of a first predetermined state to both output terminals Ao<SP>1</SP>, Ao<SP>1</SP> of the output driver 102 for the duration of the first timing signal and a second timing signal # 1 * is applied to condition the output driver 102 so as to select predetermined complementary states for signals on the output terminals Ao<SP>1</SP>, Ao<SP>1</SP> upon application of a third timing signal # 1  which applies the selected complementary drive signals to the output terminals Ao<SP>1</SP> and Ao<SP>1</SP>. In the buffer citcuit shown in Fig. 1a the first clock pulse #1 (Fig. 2, not shown) operates transistors 101-8 and 101-9 which sets the state of the transistors 102-2 and 102-6 so that the outputs Ao<SP>1</SP> and Ao<SP>1</SP> are at the first predetermined state. The state of the address input signal at Ao is stored on the capacitance 101-5 so that when the second clock pulse #1* occurs the transistor 102-2 or 102-6 is conditioned depending on the input information stored on the capacitance 101-5. The input at Ao is now represented by the voltage on the capacitances 102-16, 102-7 or 102-14, 102-3 and when the third clock pulse #1 is applied the transistor 102-2 and 102-8 or 102-6 and 102-4 change state to switch one of the output terminals Ao<SP>1</SP> or Ao<SP>1</SP> to the second state. Bootstrapping capacitors 102-3 and 102-7 are provided to enhance the switching speed of the transistor pairs 102-1, 102-5. Also the bootstrapping capacitors increase the conduction of the conducting one of the driver transistors 102-4, 102-8 such that the output level of Ao<SP>1</SP>, Ao<SP>1</SP> approximate the voltage level corresponding to the clock signal # 1 . The clock pulse sources # 1 * and #1 are derived from the clock pulses #1 in a clock inverter, Fig. 1b. The input clock pulses #1 are inverted by FET 110-1 to provide the clock pulses #1* and a capacitor 110-8 functions to provide a delay in turning off of FET's 110-4, 110-5 when the input clock pulse #1 is applied to provide a delayed clock pulse #1. A MOS memory chip is disclosed which uses the buffer circuits of Fig. 1a as Y and X select buffer circuits (100-1 to 100-11, Fig. 1, not shown). The outputs of the X and Y buffer circuits are applied via X and Y address decoder circuits (20-, 30) to condition one of transistors (60-1 to 60-32) and one of a selected pair of transistor circuits 70-1 to 70-15) so that information may be written into and read out of a selected FET memory cell (10) of an array of rows and columns of memory cells (10) via a digit/sense line (D/Sq to D/S32) by a write circuit (52) and a read circuit (92).