Patent GB-1397438-A (GB)
Title: Data processing system
IPC: G06F9/46
Filed: 1972-10-02
Abstract: 1397438 Priority interrupt handling system INTERNATIONAL BUSINESS MACHINES CORP 2 Oct 1972 [27 Oct 1971] 45303/72 Heading G4A A data processing system includes a central control unit and a plurality of external units, the central unit being arranged to transfer priority level defining signals to any selected external unit, the external units being arranged to transfer a service request signal together with a previously received priority level defining signal to the central unit, and the central unit including an addressable store, logic circuitry, a plurality of control circuits each associated with a respective priority level and each being arranged independently to control the logic circuitry, and actuating means responsive to service request signals and associated priority level defining signals from the external units to actuate only that control circuit corresponding to the highest priority level defining signal present. The system is used to control in real time a number of I/O devices and may be connected to a further data processor to relieve that further processor of control of the I/O devices. The Specification gives full details of the various operations, e.g. program branch on condition, add, AND, shift etc. performed in response to particular instruction formats. The logic circuit is arranged to add or subtract 16 bit words in parallel and data is handled in 16 bit words with (8 bit) byte parity bits. The I/O devices may operate on one of four priority levels each of which is subdivided into sixteen sublevels which are treated as having equal priority. To initialize the system a " prepare " command is executed which causes the central unit to load a resigter in each I/O device with priority and sub-priority level signals, marks etc. When a device wishes to present an interrupt request it sends a signal together with an indication of its priority level. A buffer (INT BUFFER REGS) is provided with one register per priority level. If the corresponding buffer register is not full additional data is requested from the device, viz. the priority sublevel, the device address, and a status bit. If the buffer is already full the device is instructed to store its request. When, subsequently, the buffer is emptied a signal is sent to all devices which present any stored interrupt request signals. When a buffer register is loaded the corresponding interrupt request latch is set. A further set of four latches (CURRENT LEVEL LATCHES) indicate the priority level on which the processor is at present working and a further four latches (IN PROCESS LATCHES) indicate levels on which a routine has started but been subsequently interrupted by a higher level request, these last latches being used to control a return to an interrupted routine. To avoid the time consuming routines normally required to save program status when an interrupt is granted the processor has a number of registers provided in sets of four, e.g. the instruction counter, so that when an interrupt is granted control of the instruction sequence is merely given to the appropriate registers. The registers from each set of four corresponding to a particular level form a control circuit which is actuated when an interrupt on the appropriate level is granted. The status presented to the processor from an interrupting device consists, in the first instance, of a single bit S. If the S bit is zero the interruption is due to normal operating conditions and no further status is required. If however the S bit is one then an error in the device is indicated and a routine is followed to acquire further status data. In this way the time consuming operations required to acquire status data are normally avoided. Index addressing is utilized to save time in selecting the appropriate routine when an interrupt is granted. A data store contains table pointers for tables giving the instruction addresses of the first instruction of routines for handling interrupts on the four levels. A first level table has four entries, one for each level, which point to four tables each of sixteen entries, one for each sublevel. A mask register is provided in each device whereby selected ones or all priority levels may be prevented from interrupting. A further mask latch is provided in each device to prevent that device from issuing an interrupt signal. The system also includes the facility whereby the processor itself may initiate an interruption, e.g. in response to a program instruction, power failure etc. An additional four register buffer (SET INTERRUPT BUFFER) is provided for handling processor initiated interrupts in order to ensure that such an interrupt is registered, e.g. the buffer register used for external interrupts on the corresponding level may be full.