Patent GB-976631-A (GB)
Title: Multiplying apparatus
IPC: G06F7/491
Filed: 1961-04-04
Abstract: 976, 631. Electric digital multipliers. POBINIA A.B. April 4, 1961 [April 5, 1960], No. 12018/61. Heading G4A. In an arrangement for multiplying two multidigit decimal numbers, the multiplicand is stored in binary coded decimal form, the multiplier is employed in decimal form and the product is obtained in a decimal counter digit by digit commencing with the lowest denomination. As described, the arrangement is applied to a quantity x price calculation in an automatic weighing and labelling machine, the price per unit weight being entered, e.g. by a keyboard in a multiplicand register M comprising two groups of crossing leads, one group corresponding to the digits α 4 α 3 α 2 α 1  of a four digit multiplicand. The multiplier is entered by a keyboard or from a weighing machine on a register K consisting also of a contact field, but with ten output lines for the decimal digits 0-9 of a four decimal digit multiplier b 4 b 3 b 2 b 1 . The multiplication operation is controlled by three shift registers S1, S2, S3 each comprising four bi-stable transistor stages, one stage in each register being "set", the output of the last stage of the register S3 being connected to the first stage of the register S2 and the output of the last stage of the register S2 being connected to the first stage of the register S1 so that one complete cycle of register S1 corresponds to four cycles of register S2 and sixteen cycles of register S3, the operation being completed during the course of two cycles of S1. The multiplication procedure is as shown in Fig. 7, the product digits c 8 -c 1  being formed commencing with the lowest digit c 1 , each such digit corresponding to a step of the shift register S 1 . The multiplicand decimal digits a 1 -a 4  are selected by a diode matrix GV (Fig. 8, not shown), which receives inputs from registers S1, S2, the multiplier digits b 1 -b 4  being selected by the shift register S2. Assuming that a particular multiplicand decimal digit a 1 -a 4  has been selected, the register S 3  has its stages V1-V4 successively activated, which stages correspond to the "1", "2", "4", "8" bits of the multiplicand digits respectively. A circuit GN tests whether each bit is "0" or not, and if it is "1", a flip-flop BS is changed over to gate pulses from a generator A via a gate GR to a stage a-d of a binary counter BA having stages a-g, and to a 4-stage decimal counter DR, Fig. 4, which accumulates the product result. The stage of the decimal counter DR to which the pulses are fed is determined by the shift register S1 each stage being fed in turn commencing with the lowest stage, the product digits after they are formed being transferred to an 8-stage decimal result register (not described) so that the counter DR can be utilized twice, corresponding to two cycles of the shift register S1, during the multiplication operation. The pulses are counted by the stages d-g of the counter BA until a comparison network GA detects that the count total (in binary form) equals the decimal multiplier digit in the register K which is at present selected by the shift register S2. The network GA then produces an output which changes over the flip-flop BS cutting off the pulses to the counter BA and result counter DR and causing a pulse from the generator A to step on the shift register S3 by one stage thereby indicating a new operation for the next bit of the current multiplicand binary coded decimal digit. Decimal counter. The decimal counter DR comprises four stages such as the stage shown in Fig. 4, each comprising four bi-stable transistor stages d 1 -d 4 , so interconnected that the respective stages when set are indicative of digits 1,2,1 and 5 input pulses applied to the input terminal i 8. Input terminal i 7 receives carry signals from the next lower decade and output terminal u 16 provides a carry for the next higher decade.