Patent EP-0020931-A1 (EP)
Inventor: BLISS FLOYD RUSSELL
IPC: G06F9/38
Filed: 1980-04-25
Abstract: 1. A device for executing program interrupt operations in a data processing system comprising a storage (12) for storing data and instructions, a processor (10) operating in accordance with cycles of instructions and carrying out the operations determined by the instructions of a program, circuits (140) for processing interrupt requests from peripheral devices and received by the processor, said system operating in the mode called instruction anticipated call mode in which a given instruction is extracted from the storage during the execution of the instruction preceding said given instruction in the program to be executed, said device comprising an instruction address register (24) connected to said storage and containing the address of the next instruction which must be the object of an anticipated call in a series of instructions to be executed, a storage address register (26) connected to said instruction address register as also to the storage and provided for loading the address of the next instruction while executing the current instruction, a first latch (214) for receiving and storing an interrupt request from one of the peripheral devices, a second latch (212) connected to the output of the first latch and to the storage and controlled by instructions so as to authorize or forbid the interrupt requests stored in said first latch, an interrupt register (170) for storing, when an interrupt request has been accepted, the address contained in said instruction address register, condition information relating to the processor arithmetic and logic unit (82) as well as information relating to the storage data pages and resetting means (140, 184) for resetting the page condition information and the instruction address by transmitting the contents of said interrupt register to the processor at the end of the execution of the interrupt operations so as to reset the processor into the condition if had when the interrupt was accepted in order to allow the processor to resume the program execution where it was interrupted, said device being characterized in that it comprises : link registers (46, 50, 54) connected to the instruction address register for storing the values contained in said register when an interrupt request is received from one of the peripheral devices, interrupt means (234, 246, 250) connected to said first and second latches for inhibiting the loading into said instruction address register, of the address of the reset instruction which should be the object of an anticipated call during the first cycle relating to an interrupt request taken into account in said first latch, means (24) connected to said first and second latches and in response to a connecting operation comprising a connecting step and resulting from an instruction contained in said instruction address register, for inhibiting the operation of said interrupt means until said connecting operation is executed, and means (240) connected to said first and second latches and, in response to a storage access operation, for inhibiting the operation of said interrupt means up to the end of the execution of the storage access operation.