Patent GB-921885-A (GB)
Title: Data processing system
IPC: G06F13/40
Filed: 1961-12-27
Abstract: 921,885. Digital computing systems. TELEREGISTER CORPORATION. Dec. 27, 1961 [Dec. 30, 1960], No. 46238/61. Class 106 (1). A data processing system comprises a plurality of data processors which may be selectively connected to a plurality of terminal units and is characterized in that when a data processor has been connected to a particular terminal unit, interlock means are effective to prevent the establishment of another connection of a data processor to the selected terminal unit until release means responsive to signals from the data processors have released the interlock means. As described, data processors 10, 12, 14, Fig. 1, may be selectively connected to terminal units 16-21 arranged in sub-systems 16-18, 19-21. The units as described are magnetic drums but may be magnetic tapes, typewriters, punches, readers, &c. When a prosessor requires access to a terminal unit 16-21, means in the processor are activated for testing whether the sub-system of that particular unit is busy. If it is, the programme branches to another instruction. If not, the required connection is established. When the processor 10, for example, requires access to one of the units 16-18, it transmits a " seize " signal over lines 34, 36 to a " seize circuit " 28 where a circuit comprising gates 38, 42, 48, 56 and a feedback lead 54, Fig. 2, is latched, the output CP1 on a lead 60 being applied to a logic circuit 32 to provide a signal over a cable 62 back to the processor 10 which then transmits to the circuit 32 a series of control digits to determine the subsequent operations. These control digits identify the particular unit 16-18 required and the desired address in the unit. Desired data read from the selected unit is transmitted back to the processor 10 via a lead 68, logic circuit 32 and cable 62. While data transfer is taking place, access to the units 16-18 is denied to the other data processors 12, 14 by an inhibiting connection from the feedback lead 54 to gates 70, 72. Circuits 26 are conditioned in response to the output CP1<SP>1</SP> of the gate 42 to apply a " busy " signal over a cable 86 should any of processors 10, 12, 14 carry out a " test for busy " instruction. When the control digits are transferred from the processor 10, a " busy " flip-flop (not shown) is set to cause a gate 90 to produce a low output while data transfer takes place. A gate 92 produces a high output whenever one of the units 16-18 is in operation thereby providing a " busy " signal for the processor 10 should it attempt to acquire access to the subsystem. When the data transfer is completed, the " busy " flip-flop is reset and the subsystem will be available to the processor 10. If the processor 10 does not require access to the sub-system," it places a high signal on a release line 94 to set a "release " flip-flop 104 to close " and " gate 56 thereby breaking the latching circuit. Assuming that none of the other processors 12, 14 requires immediate access to the sub-system, the flip-flop 104 is reset and the sub-system then becomes available when required. An interlock circuit 140, Fig. 1, is provided and is arranged to reserve access to one or more terminal units required by a particular processor, although that processor may be communicating with other units at the time.