Patent EP-4120339-A2 (EP)
Title: Space efficient flip chip joint design using different pillar designs
Inventor: MIRPURI KABIR
IPC: H01L21/48
Filed: 2022-06-30
Abstract: An apparatus includes an Integrated Circuit (IC) (12). A first pillar (14) includes a first end (44) and a second end (42). The first end (44) is connected to the IC (12) and the second end (42) includes a first attachment point (22) colinear with a first central axis of the first pillar (14). The first attachment point (22) includes a first solder volume capacity. A second pillar (16a-16d) includes a third end (54) and a fourth end (52). The third end (54) is connected to the IC (12) and the fourth end (52) includes a second attachment point (26a-26d) disposed on a side of the second pillar (16a-16d) facing the first pillar (14). The second attachment point (26a-26d) includes a second solder volume capacity being less than the first solder volume capacity. A first distance (40) between the first end (44) and the second end (42) is less than a second distance (50) between the third end (54) and the fourth end (52) (i.e., the height of the second pillar (16a-16d) is larger than the height of the first pillar (14)). The second pillar (16a-16d) may be one of a plurality of pillars, each disposed to surround the first pillar (14) and comprising a respective side attachment point (26a-26d) facing the first pillar (14), wherein the plurality of pillars (16a-16d) are symmetrically disposed to surround the first pillar (14). The first pillar (14) may comprise a cylindrical shape. The second pillar (16a-16d) may comprise a rectangular shape. A first cross-sectional area of the first pillar (14) may be greater than a second cross-sectional area of the second pillar (16a-16d). The first attachment point (22) of the first pillar (14) may be connected, through the first solder volume, to a top facet of a pad block (164) of an assembly substrate (162) and the second attachment point (26a-26d) of the second pillar (16a-16d) may be connected, through the second solder volume, to a side facet of the pad block (164), the side facet being orthogonal to the top facet and being formed by removing a section of a corresponding pad (114a-114d, 118a-118d). The IC (12) and the assembly substrate (162) may be encapsulated. The high solder volume pillar (14) may be used for signals requiring high current density or having high signal frequencies, while the low solder volume pillar (16a-16d) may be used for signals having lower current density or lower signal frequencies. A third, tall cylindrical pillar (18a-18f) including a fifth end (64) and a sixth end (62) may be provided, wherein the fifth end (64) is connected to the IC (12) and the sixth end (62) includes a third solder attachment point (24a-24d), colinear with a central axis of the third pillar (18a-18f), wherein the third attachment point (24a-24d) may be connected to respective substrate pads (120a-120r, 182, 184, 186, 188) and the tall, cylindrical pillar (18a-18f) may be intended for a high frequency and/or high current signal. The IC (12) may comprise a plurality of the first cylindrical pillars (14) and a plurality of the third, tall cylindrical pillars (18a-18f).