Patent GB-1195569-A (GB)
Title: Data Processing
Inventor: CHINLUND THOMAS JOSEPH
IPC: G06F9/42
Filed: 1967-08-15
Abstract: 1,195,569. Data processor. WESTERN ELECTRIC CO. Inc. 15 Aug., 1967 [16 Aug., 1966; 11 May, 1967], No. 37371/67. Heading G4A. A data processor having a memory storing instructions includes means for registering selection code information definitive of which one or ones of a set of instructions in the memory is or are to be selected for accessing and means responsive to said information for controlling an instruction location means without reference to the memory, to reference only the selected one or ones of the instructions of that set in successive machine cycles. Instructions in a memory are accessed and supplied to a buffer storage register under control of data applied to a store access decoder. Part of the word accessed is applied to an address register from which it can be incremented or modified in accordance with the contents of an index register and then applied to the store access decoder to cause retrieval of a data word. Included in the processor is a set of selection registers each storing a 16 bit word and each able to transfer its word to a 16 bit controlling selection register which is also a shift register. A programme such as shown at the left in Fig. 3 is carried out, the instructions being accessed, decoded and executed as usual until the instruction stored at SAFT is reached. This loads one of the selection registers with a word from a specified location in the main memory. The programme is continued until the intruction at SATR is reached. This defines an s address, such as THME and a selection register, such as register 6. The address SATR + 1 is stored in an instruction location counter. Instructions are then accessed beginning at THME under control of the word in register 6. The word in register 6 is transferred to the controlling selection register where the most significant bit is tested to determine the mode of operation. Assuming this is "1" the most significant eleven bits of the word are shifted one bit to the left with a "1" written in the vacant least significant place of the eleven. The next most significant bit is tested and if a "0" the word in location THME is accessed and executed and the address counter incremented to THME + 1; if "1" the word is ignored but the counter incremented. The register contents are shifted again and the most significant bit tested and the least significant bit rewritten as "1". Thus only instructions corresponding to "0"s in the word from register 6 are executed. When the register contains all "1"s the five least significant bits of the 16 bit word is examined and if they are all "0" selective access is terminated and the address SATR + 1 is retrieved. If the five bits are not all zero a further selection register is accessed, defined by the number represented by the five bits and the process is continued. If the most significant bit of the accessed 16 bit number is 0 a jump mode selective access ensues. The next seven most signification bits define a number to be added to the address counter, the most significant digit of the seven defining the sign of the number. The next three significant digits define any conditions required for the jump to be executed.