Patent GB-1317878-A (GB)
Title: Frame synchronization system
IPC: H04J3/06
Filed: 1971-08-26
Abstract: 1317878 Multiplex pulse code signalling INTERNATIONAL STANDARD ELECTRIC CORP 20 August 1971 [24 Aug 1970] 39155/71 Heading H4L In a frame synchronizing arrangement for a time division multiplex P.C.M. system in which the incoming signal includes a synchronization component, means are provided to examine successive bits of the incoming signal to recognize the synchronization component and produce as the result of each examination an output signal and the complement of said output signal and means responsive to the present state of said output signal and one of N cumulative functions of previous states and to the present state of the complement of said output signal and one of N cumulative functions of previous states of the complement of said output signal, where N is an is an integer equal to at least one, provide a control signal to adjust the locally generated timing signals, when said output signal indicates loss of synchronism, until synchronization is restored. The arrangement is a modification of that disclosed in Specification 1,264,023. System using distributed type sync. code.-This type of code uses one bit per frame and two or more frames per multiframe. As described, Fig. 1, the frame rate is 8 Kc/s and the sync. bit is alternatively 1 and 0 in successive frames so that the pattern is 1, 0 in each multiframe. Incoming signals from source 2 are supplied to an EXCLUSIVE OR circuit 5 together with a timing signal REF from logic circuitry 4, the output MMF of the gate 5 being binary 1 only if the two inputs do not coincide. Pulses at bit rate from clock 1 are supplied via gate 3 to the binary counters and logic circuitry 4 to produce the various timing signals comprising the 4 Kc/s square wave REF, a sync. bit time signal ST of constant width of one clock period, a halt time signal HT having a variable width equal to the width of a HALT pulse plus the width of a clock period and a shift register timing signal SH having a variable width equal to the width of N clock periods plus the width of a HALT pulse. Signal HT prevents the system from locking in an unsynchronized condition when initially switched on. The signal MMF is supplied to a bi-stable 6 triggered by the output of AND gate 7 during pulses ST so that if the signal MMF is binary 1, respresenting a mismatch, the output of bi-stable 6 will be a 1 and due to the inverter 8 will be a 0 when signal MMF is binary 0. The output of the bi-stable 6 is supplied to a decision circuit 9 of the type described in the prior Specification which includes a Miller integrator whose output voltage is compared with a reference voltage providing a decision level and arranged so that signal SL is binary 1 denoting lack of synchronism when the output voltage is below the reference value. Circuit 9 also provides a signal SM which is binary 1 when the system is in a search mode. The signal MMF is also supplied OR gate 10 and inverter 12 to respective inputs of bi-stable B N  of an N + 1 stage shift register 11 which is triggered by pulses SHC from AND gate 13 controlled by clock 1 and the output of OR gate 14 receiving pulses ST and SH. The output of bi-stable B N  is supplied via AND gate 15 and inverter 16 to the respective inputs of stage B N-1  of the shift register and the output of the shift register is coupled via AND gate 17, which is enabled via inverter 18 only when signal ST is in the binary 0 condition, to the OR gate 10. By this means information relating to all but the first of the N + 1 previous samples of the MMF signal is shifted through AND gate 17 and OR gate 10 to supply a cumulative function of the MMF signal of each frame which is stored in turn in register 11. Pulses SHC consist of N + 1 + H consecutive clock pulses per frame where H is the number of clock pulses inhibited by the HALT signal from gate 20. With a binary 0 output (no HALT signal) from gate 20, the gate 15 allows information to be shifted from stage B N  to B N-1  of shift register 11 and in one round trip it will return to its original position each frame period with the exception of the bit stored at B 0  since gate 17 is blocked at this stage, normal counting continuing in circuit 4. When a HALT signal appears at the output of gate 20 it is inverted at 19 gate 15 is blocked and a zero condition is shifted into stage B N-1  so that subsequently new information MMF is gated in via OR gate 10, the H additional clock pulses causing the information in register 11 to be shifted H positions more than a round trip, this being repeated until H new bits of signal MMF are in the H left-most stages of the register. A second N + 1 stage shift register 11<SP>1</SP> is connected similarly to register 11 and operates in the same manner but due to the inverter 21 it receives the complement of the signal MMF. An AND gate 20 receives outputs SL and SM from circuit 9, outputs from bi-stables B N  and B<SP>1</SP> N  and the signal HT from circuit 4. Signal SL is binary 1 when circuit 9 shows loss of synchronism, SM is binary 1 when the system is in a search mode and when OR gates 10 and 22 indicate a mismatch there will be a binary 1 at the outputs of bi-stables B N , B<SP>1</SP> N . Under these conditions the resulting output of gate 20 is inverted at 19 to produce a "O" output which is the HALT pulse applied to AND gate 3 to inhibit clock pulses from clock 1 and stop the counters in circuit 4 with resulting shift in the timing signals until synchronism is recovered. Modifications.-The system may be adapted for use with a lumped type sync. code, i.e. of the type in which the code consists of a predetermined pattern of a plurality of bits in each frame, by substituting a shift register for the EXCLUSIVE OR circuit 5, Fig. 2 (not shown), the output stages of the shift register being connected to recognize the code pattern and coupled to an AND gate providing an output when the code is detected at the correct time. The system may also be adapted for use with a combined lumped and distributed code, which would have two or more bits per frame and two or more frames per multiframe, the bit combination being different in each frame of a multiframe. The EXCLUSIVE OR gate 5 is dispensed with, Fig. 3 (not shown), and replaced by shift register and logic means for detecting the two sync. codes appearing in a two frame multiframe.