Patent GB-1116057-A (GB)
Title: Analog to digital conversion system
IPC: H03M1/00
Filed: 1967-02-16
Abstract: 1,116,057. A-D converters. INTERNATIONAL BUSINESS MACHINES CORPORATION. 16 Feb., 1967 [23 Feb., 1966], No. 7487/67. Heading G4H. An analogue-to-digital conversion system comprising a plurality of analogue input devices (one of which is shown in Fig. 2a), a digital counter 14 associated with each input device, a digital-to-analogue converter 111 (Fig. 2b) supplied with the output of a selected digital counter, a comparator 131, a first input of which is the output of the digital-to-analogue converter 111 and the second input to which is the analogue output of the input device associated with the selected digital counter, and including means for incrementing the selected digital counter when the first input is less than the second input. The application is particularly described for determining the peaks in an input signal. The input signal may come from a photo detecting device at a photo-analysis station at which liquid biological specimens, e.g. blood, are separated from one another by an interspersing agent such as air and moved in front of a beam of light of a given frequency. In the embodiment described two uniselector switches 105, 106 sequentially connect each terminal with a central control station. When, for example, the first terminal is so connected the input analogue signal 11a to this terminal is connected to a differential amplifier 131 where it is compared with the output from a digitalto-analogue converter 111 the output from which represents the state of the counter 14 at the terminal 1. When during one of the sampling intervals the analogue signal becomes greater than the count, a polarity detector 133 gives a negative output signal which after inversion enables an AND gate 137 to supply pulses on conductor 10e via AND gate 18 enabled by the signal on 10a from uniselector switch 105 to increment a counter 14 (the counter may only be incremented upwards). If at the start of a subsequent sampling interval the stored count is greater than the analogue signal on conductor 11a, implying that the peak value has been passed, the output of plurality detector 133 on conductor 10g is positive whilst a positive signal also exists on conductor 10f since the latter receives a pulse after a fixed delay for each pulse on lead 10a. AND gate 24 is then enabled to set a trigger circuit 36 to its " 1 " state and prepare gate 28 which is enabled during the next sampling interval if the input analogue signal is still less than the count held in counter 14. A signal on lead 11g is then transmitted to AND gate 139 to enable gate 141. The state of the counter 14, which holds the maximum value of the input analogue signal, together with signals on leads 117a, 117b (indicating from which terminal the count is being read) and a signal from a binary coded counter 16 counting each pulse from a gate 26 which indicates the number of the peak is then entered into a buffer 143. The output from AND gate 26 also resets the counter 14. When the fixed length pulse on conductor 10f terminates AND gate 28 is closed and the signal on conductor 11g becomes negative and AND 139 is then closed. This switches a trigger 145 to its set state so that a signal is transmitted to a recorder to indicate that there is data in buffer register 143. If after the analogue signal has dropped to below the value of the count in counter 14 during one time interval but in the subsequent time interval becomes greater than the count, the output of polarity detector 133 does not become positive at the beginning of this latter time interval so that AND gates 18, 38 are not inhibited and a counter can be incremented.