Patent GB-904234-A (GB)
Title: System for determining and selecting free aligned telecommunication channels
IPC: H04Q3/42
Filed: 1960-10-14
Abstract: 904,234. Automatic-exchange systems. STANDARD TELEPHONES & CABLES Ltd. Oct. 14, 1960 [Oct. 20, 1959], No. 35320/60. Class 40 (4). In a time division multiplex exchange having a plurality of highways each offering N time channels, connections are established over chosen sets of at most R highways in series using the same time channel in each highway, and for the purpose of selecting a channel free in each of a set of highways over which a connection is required, each highway has a row of N memory cells which store the free or busy condition of the N channels of the highway; a register reading out the memory cells of all rows associated with the set of highways and all the memory cells pertinent to each channel marking a coincidence gate particular to each channel channel the output of each gate indicating that a channel is free throughout the set; and a lockout chain selecting one of the channels marked free over the gates and causing the associated memory cells in each highway of the set to be marked busy. The channel selection arrangement is wholly subservient to the register the details of which are not described. At the start of a connecting operation the register indicates which highways are concerned and receives the number of a free channel in those highways. When the connection is released the register again indicates the highways involved and also the channel employed so that the channel may be marked free in the memory cells. The type of highway trunking used is shown in Fig. 2, where terminal highways such as A or B are grouped with intermediate highways such as C interconnecting highways of one group with highways of another group, and intermediate highways such as Ci interconnecting highways of the same group. This distribution of highways, described in Specification 904,232, uses two channels to connect terminals on the same highway, one channel connecting one subscriber to a storage device SSD and this device being connected to the other subscriber in the other channel. Connection of tones and ringing control is made by finding a channel free in the one or each of the terminal highways involved and connecting them to a common wire TC fed from generators T.G. The selection arrangement just, therefore, be able to find one, two, or three channels. As shown in Fig. 1, the N memory cells of each of the G terminal highways form a row of ferrite cores in a storage matrix GM, while the N memory cells of each of the L intermediate highways form a row of ferrite cores in a storage matrix LM. A read-out cycle of the stores GM, LM, comprises at least six time positions t1 to t6 and is of longer duration than a time channel of the multiplex cycle. For a threehighway connection the register is possessed of the identities of two rows of store GM and one of store LM. At time t1 all the cores of one GM row are read out into buffer bi-stable stores 1A to NA and sets to the 1 state all those buffers for which the corresponding channel is busy. At time t2 all the cores of another GM row are read out to similarly set up the buffers 1B to NB. Also at time t1 a row of store LM is read out to set up buffers 1C to NC. At time t3, therefore, the 0 state outputs of like numbered buffers 1A, 1B, 1C, &c. mark correspondingly numbered clincidence gates 1D0 to ND0. A lock-out chain S selects the lowest numbered output present from the coincidence gates and, over a lead from S1 to SN and an encoder Ech, signals the register. If no channel is free the coincidence gates have no output and lock-out chain S marks a lead S (N+1) to the register. The read-out and re-write arrangements for the Kth columns of stores GM, LM, are shown in Fig. 3. All the buffers are initially in their 0 states. One row of GM and one row of LM are read out at time t1 to buffers KA, KC, and another row of GM is read out to buffer KB at time t2. If the channel is busy in the A, B or C highway the corresponding buffer is set to its 1 state. At t3, on command from the register over gate PS, the coincidence gates such as KD test for the coincidences of 0 states from all three buffers to indicate the Kth channel free in all three highways. The lock-out chain S, which can have two forms to be described later, selects the lowest numbered output which, if it is the output KD shown in Fig. 3, appears at SK for encoding in Ech and is used to set the buffers KA, KB, KC, to their 1 states. At t4 the states of buffers KA and KC are re-written into stores GM and LM over amplifiers WKG and WKL by way of gates K4A, K4C, and at t5 the state of buffer KB is re-written into GM over K5B and WKG. At t6 the buffers are re-set to their 0 states ready for another selecting cycle. If only one or two highways are involved the register will read out of only one or two rows of the stores and two or one of the buffers will stay idly in their 0 states. Since the idle buffer or buffers always exhibit a 0 state they will not interfere with the coincidence gate KD which detects an idle channel in as many highways as the register dictates. Where connections over highways C<SP>1</SP>, Fig. 2, require two separate channels, two separate selecting cycles are required. Alternatively, by providing more than six time positions a double selection of simple channels on the same highway may be effected. It is suggested, however, that the buffers such as KA, KB, KC will fail safe if they are initially in their 1 states since a failure to detect a busy channel will not have the effect of offering this channel for use, while failure to detect an idle channel will merely show this channel as busy. The details of this modification are not set out. At the end of a call the register takes the selection arrangement into use to free the channel and cycles the arrangement as before until, at time positions t3, over decoder Dch the buffers KA, KB, KC, marking the channel busy by their 1 states, are re-set to 0 by a lead FK over gates KFA, KFB, KFC, so that at t4 and t5 there is no re-write and stores GM, LM mark the channel free. A first lock-out chain S is shown in Fig. 4, the outputs of the coincidence gates being shown as 1D0, 2D0... ND0, each of which over an inversion gate becomes 1D1, 2D1 ... ND1. The outputs of the chain are shown as S1, S2 ... S(N+1), output S1 being the coincidence gate output 1D0 direct and outputs S2 onwards depending, in the case of output SR for instance, on the presence of coincidence gate output RD0 and the absence of all preceding outputs 1D0 to (R-1) D0, which is to say the presence of RD0 and 1D1 to (R- 1) D1. The output S(N+1) indicates no outputs 1D0 to ND0, i.e. no free channel through the set. Instead of using inverters to obtain the signals 1D1 to ND1, the 1 state outputs of buffers KA, KB, KC, may be passed over an OR gate direct to the lock-out chain as shown in Fig. 3. A second lock-out chain S is shown in Fig. 5 where, instead of accumulating the negative signals 1D1 to ND1 at each output S2 to SN, these are relayed in sequence over AND gates S<SP>1</SP>3 to S<SP>1</SP>N. The output SR will be chosen, therefore, if S<SP>1</SP>R has all the negative signals 1D1 to (R- 1) D1 relayed to it and the signal RDO is present. The absence of RD1 locks out all outputs S(R+1) onwards. The outputs S1 to S(N+1) may be grouped, each group being arranged as in Fig. 5, and the collection of groups being arranged as in Fig. 4. Specifications 765,681 and 822,297 also are referred to.