Patent SG-11201811063Q-A (SG)
Title: Array data bit inversion
Inventor: INGALLS CHARLES
IPC: G11C11/22
Filed: 2017-06-01
Abstract: b-1 425-b-2 r -1- 1 115-b DLREF DL 420-a WL 7110-b 105 -b 420-b 105-c WE 110-ci Cell 240-c 240-d PL 210-b l 400-a \ -210-a 410 430 FIG. 4A (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 28 December 2017 (28.12.2017) WI P0 I PC T Iiiimmomiolollmolommoolomomolomommovom (10) International Publication Number WO 2017/222775 Al (51) International Patent Classification: Gl1C 11/22 (2006.01) (21) International Application Number: PCT/US2017/035452 (22) International Filing Date: 01 June 2017 (01.06.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/188,890 21 June 2016 (21.06.2016) US (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way, Boise, ID 83716-9632 (US). (72) Inventors: INGALLS, Charles, L.; 8000 S. Federal Way, Boise, ID 83716-9632 (US). DERNER, Scott, J.; 8000 S. Federal Way, Boise, ID 83716-9632 (US). (74) Agent: HARRIS, Philip, W.; Holland & Hart LLP, P.O. Box 11583, Salt Lake City, UT 84147 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). (54) Title: ARRAY DATA BIT INVERSION (57) : Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state. [Continued on next page] WO 2017/222775 Al IMEDIMOMMIONOIDEMEEHOHMEMERVOIMIE Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(H)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3))