Patent EP-0119280-A1 (EP)
Inventor: PFEIFER HEINRICH DIPL-ING
IPC: H04H20/00
Filed: 1983-03-11
Abstract: 1. Integrated Circuit for decoding traffic information regional tone signals whose frequency, the regional tone frequency, is the information on the region, the regional tone signals being contained in the form of a carrier amplitude-modulated therewith in a received broadcast signal which has already been demodulated in a conventional radio receiver (ds), characterized by the following features : - The demodulated broadcast signal (ds) is fed to a mixer (ms) whose local-oscillator frequency (fm) is higher than the highest regional tone frequency ; - the output of the mixer (ms) is coupled to the input of an analog-to-digital converter (aw) through an analog low-pass filter (af) whose upper cutoff frequency is not higher than half the sampling frequency (fa) of the analog-to-digital converter (aw) ; - the output of the analog-to-digital converter (aw) is coupled to the input of a digital band-pass filter (bp) whose mid-frequency (fc) is equal to the difference between the carrier frequency (ft) and local-oscillator frequency (fm), and to the first input of a multiplier (m) having its second input connected to the output of a digital clamping circuit (kl) whose input is connected to the output of the digital band-pass filter (bp), and which clamps positive and negative input signals to the positive and negative maximum values, respectively, which are determined by the numbers of digits of said input signals ; - the multiplier (m) is followed by several signal paths (a, b, f), one for each regional tone frequency, each of which consists of a digital resonance filter (ra, rb, rf) followed by a digital absolue value former (ba, bb, bf) and a digital low-pass filter (pa, pb, pf) whose upper cutoff frequency is smaller than twice the smallest regional tone frequency ; - each of the low-pass filters (pa, pb, pf) has one its outputs connected to one of the inputs of a multiple comparator (vk) whose first and second maximum outputs (mx1, mx2) are connected to the control inputs of a first electronic multiple switch (s1) and a second electronic multiple switch (s2), respectively ; - of each of the inputs of the first and second electronic multiple switches (s1, s2) one is connected to one of the outputs of one of the low-pass filter (pa, pb, pf) ; - the first maximum switch (s1) is connected to the input with the first maximum value by the first maximum output (mx1), and the second multiple switch (s2) is connected to the input with the second maximum value by the second maximum output (mx2) ; - the output of the first multiple switch (s1) is coupled through a first constant multiplier (m1) to the minuend input of a first comparator (k1) having its substrahend input connected to the output of a multiple adder (ad) which has one of each of its inputs connected to the output of one of the low-pass filters (pa, pb, pf), an through a second constant multiplier (m2) to the minuend input of a second comparator (k2) having its subtrahend input connected to the output of the second multiple switch (s2) ; - the first maximum output (mx1) of the multiple comparator (vk) is connected to a delay element (vg) which feeds the minuend input of a third comparator (k3) having its subtrahend input connected to the first maximum output (mx1) ; - the minuend-equal-to-subtrahend output of the third comparator (k3) is coupled through an inverter (it) to the reset input (er) of a counter (z) whose count input is fed with a clock signal (t) and whose outputs are connected to the minuend input of a fourth comparator (k4) whose subtrahend input is fed with a constant (k) serving as a threshold value ; - the digital band-pass filter (bp) is followed by an addional digital absolute-value former (bw) followed, in turn, by an additional digital low-pass filter (pw) whose upper cutoff frequency is equal to that of the low-pass filter (pa, pb, pf), and whose output is coupled through third and fourth constant multipliers (m3, m4) to the subtrahend inputs of a fifth comparator (k5) and a sixth comparator (k6), respectively, which have their minuend inputs connected to the output of the first multiple switch (s1) ; - the minuend-greater-than-subtrahend output of the fifth comparator (k5) and the minuend-smaller-than-subtrahend output of the sixth comparator (k6) are each connected to one of the two inputs of a first AND gate (u1) ; - the four inputs of the second AND gate (u2) are connected, respectively, to the minuend-greater-than-subtrahend outputs of the first comparator (k1), the second comparator (k2), and the fourth comparator (k4), and to the output of the first AND gate (u1), and - the first maximum output (mx1) of the multiple comparator (vk) is connected to the first parallel input of a multiple AND gate (vu) whose output is the regional-tone-signal output (sa) of the integrated circuit, and the output of the second AND gate (u2) is connected to all terminals of the second parallel input of the multiple AND gate (vu).