Patent GB-1158533-A (GB)
Title: Data Processing Apparatus
IPC: G06F9/38
Filed: 1968-01-04
Abstract: 1,158,533. Computer programme control. INTERNATIONAL BUSINESS MACHINES CORP. 4 Jan., 1968 [13 Jan., 1967], No. 625/68. Heading G4A. Data processing apparatus comprises an instruction buffer for storing a programme loop, which receives instructions as they are executed and can deliver the instructions for subsequent executions. Instruction buffering.-A computer contains a main memory addressed by an instruction counter IC to access instructions, and a socalled internal memory (instruction buffer) IM addressed by a counter lm. Decoding of a CLI instruction sets a CLI latch and effectively resets the buffering system (box 28 in Fig. 2). Thenceforth until the CLI latch is reset by a special instruction, a change in machine operating mode or initial start, each successive instruction is obtained from the buffer IM if it is in the latter (see below) and if it is not it is obtained from main memory and besides being executed it is stored in the buffer IM provided the system has " room " (see below). Were the CLI latch reset, every instruction would be obtained from the main memory. The buffering facilities are intended for programme loops. A first loop starts with the CLI instruction causing the instruction count to be placed in a counter j and in a first origin register. The CLI instruction and subsequent instructions are stored in the buffer IM with incrementing of counter lm to select successive addresses in buffer IM, of counter j and of a first LP counter. Jumping to a second loop is detected by inequality between the instruction counter IC and the counter j and causes the instruction count to be placed in counter j and a counter k to be incremented. The latter selects a second origin register which now receives the instruction count (i.e. at the beginning of the second loop) and a second LP counter to be incremented as successive instructions in the second loop are entered into buffer IM. Jumping to a third loop increments counter k again similarly to select a third origin register and LP counter. Instructions are only stored in the buffer IM provided there is room (as indicated by counter lm) and provided the supply of origin registers and LP counters has not run out (as indicated by counter k). On subsequent executions of loops stored in the buffer, the instructions are obtained from the buffer IM as implied above, since they are now present therein. Whether a given instruction is in the buffer IM is decided by setting a further counter (l) from the counter k and decrementing it successively to consider each loop (or part loop since buffer space may have run out in the middle of a loop) in the buffer IM in turn to see if it contains the instruction required, until the required instruction has been formed or all the loops have been considered. The instruction is in a given loop (or part loop) if the corresponding LP counter is non-zero and the instruction count is greater than or equal to the contents of the corresponding origin register and the instruction count is equal to or less than the contents of the origin register plus one less than the contents of the corresponding LP counter. If an instruction is to be obtained from the buffer IM, its address therein is calculated from the instruction count IC and the contents of the origin registers and LP counters in accordance with which loop it is in as indicated by the contents of the further counter (l) when the presence of the instruction in the buffer IM was ascertained. Adders, subtractors and comparators are provided as necessary. As a modification only one programme section (loop) could be stored in buffer IM, loading of the buffer being terminated by the first jump instruction after the CLI instruction. Interpretive implementation.-To permit interpretive implementation of a programming language having a block structure (e.g. ALGOL or PL/1) which requires a number of dataaddress base registers equal to the number of blocks enclosing the current instruction, these registers could be provided in the buffer IM, the part of the buffer still available for instruction buffering being indicated by a " pointer " register updated by incrementing and decrementing on leaving and entering blocks respectively.