Patent GB-1280022-A (GB)
Title: Improvements in and relating to semiconductor devices
Inventor: BEALE JULIAN ROBERT ANTHONY
IPC: H01L27/092
Filed: 1968-08-30
Abstract: 1280022 Semi-conductor devices MULLARD Ltd 22 Aug 1969 [30 Aug 1968] 41476/68 Heading H1K In an I.C. comprising an epitaxial layer deposited on a substrate of the same conductivity type and having two buried regions of the opposite conductivity type at the epitaxial layersubstrate interface and associated with separate circuit elements, a buried isolation region of the first conductivity type and having a lower resistivity than the substrate and epitaxial layer is provided at the said interface to interrupt a parasitic channel of the opposite conductivity type formed between the other two buried regions. Parasitic channels may form when the epitaxial layer is deposited due to impurities diffusing from the buried regions into the atmosphere and thus inverting the conductivity type of the initial deposited material. In a first embodiment, Figs. 5 and 6 (not shown), and Fig. 7, phosphorus and boron are diffused into separate selected parts of a P-type silicon substrate (11) to form N<SP>++</SP> type regions (12) surrounded by a P-type grid (27). A P-type epitaxial layer 14 is deposited on the surface, the phosphorus diffusing during the deposition to form an N-type region 16 extending to the surface of the epitaxial layer and containing buried N<SP>+</SP>-type regions 17 corresponding to the initially formed N<SP>++</SP>-type regions (12). The boron also diffuses into the epitaxial layer to a smaller extent to form an isolating grid 27 which interrupts any N-type parasitic channels formed at the epitaxial layer-substrate interface 17. P- type base regions 18 and N<SP>+</SP>-type emitter regions 19 are formed by planar diffusion in the N-type islands 16 which form the collector regions and N<SP>+</SP> type collector contact regions 24 are also provided at the surface. In a modification, Fig. 8 (not shown), the collector contact regions are extended downwards to form an N<SP>+</SP> -type wall (26) which contacts the N<SP>+</SP> -type buried collector region (17) and a P-type grid (28) is diffused into the surface of the epitaxial layer above the buried grid (27) to interrupt any parasitic surface channels between the islands. In a second embodiment, Figs. 9 to 11 (not shown), the buried layer out-diffusion stops short of the surface of the epitaxial layer (34) and annular N<SP>+</SP>-type walls (37) are formed to complete the isolation thus leaving enclosed portions (36) of the P-type epitaxial layer into which P-type base regions and N<SP>+</SP>-type emitter regions are diffused, the buried regions (36) forming the collectors of the transistors and the N<SP>+</SP>-type walls (37) the collector contact regions. In a modification, Fig. 12 (not shown), the annular N<SP>+</SP>-type walls are extended to contact the heavily doped parts (35) of the initially formed buried layer and a P-type surface grid (48) is provided. The collector junction may be profiled by increasing the impurity concentration of that part of the N<SP>+ </SP><SP>+</SP> -type layer which is to directly underlie the emitter region, or by using an impurity of higher diffusivity in this region. In another embodiment, Fig. 13 (not shown), a pair of complementary enhancement mode IGFETs are produced by diffusing boron and phosphorus into parts of the surface of an N-type substrate (61) to form a P<SP>++</SP>-type region surrounding an annular N-type region. An N-type epitaxial layer (64) is deposited, the boron outdiffusing to form a P-type island (65). N<SP>+</SP>-type source and drain regions (66, 67) are found in the P-type island (65) and P<SP>+</SP>-type source and drain regions (72, 73) are formed in the N-type epitaxial layer outside the island. Gate electrodes (71, 76) are provided on an insulating layer (68). The annular N-type buried region (81) interrupts any surface channel formed between P-type islands. In a modification, Fig. 14 (not shown), an N<SP>+</SP>-type annular region (82) is formed in the surface surrounding the P-type island to prevent induced surface inversion layers under conductive leads. In a further embodiment, Fig. 15 (not shown), N<SP>++</SP>-type regions (93) surrounded by a P-type grid (98) are formed in a P--type substrate (90) and a P<SP>-</SP>-type epitaxial layer (91) deposited, the impurities out-diffusing to a small extent only. Annular N<SP>+</SP>-type regions (94) are diffused through the epitaxial layer to contact the buried N<SP>++</SP>-type collector regions (93) and to surround and isolate portions (95) of the epitaxial layer which form the base regions into which N<SP>+</SP>-type emitter regions (96) are diffused. In a modification, Fig. 16 (not shown), the P-type grid (99) is formed as a surface layer in the substrate between the N<SP>++</SP>-type layers (93) and the impurity concentration of the surface of the P-- type epitaxial layer (91) is increased by diffusion to provide a P-type layer (100) to provide an impurity concentration gradient in the base regions (95) of the transistors.