Patent GB-1462823-A (GB)
Title: Area navigation computer
IPC: G06G7/78
Filed: 1974-05-17
Abstract: 1462823 Navigational computers UNITED AIRCRAFT CORP 17 May 1974 [4 June 1973] 22081/74 Heading G4G [Also in Division H4] An on-board aircraft navigation computer receives range and bearing signals from a ground station VOR, Fig. 2, and combines them with signals representing the range and bearing of the station to a chosen waypoint WP to produce a signal having an amplitude representing the distance of the aircraft from the waypoint and a phase representing the bearing (a so-called "phasor" signal). The phasor signal is resolved into orthogonal components which are separately subjected to rate-limited filtering and then reconstituted to form a filtered phasor. As shown, the VOR emits a 9960 Hz F.M. signal comprising a 30 Hz reference phase related to true north (N), and a 30 Hz A.M. signal whose phase varies from 0 to 360 degrees to indicate the bearing # 1  of the VOR station. The signals are received by the on-board receiver 20, Fig. 1, and after filtering and detection, are fed respectively to a N-reference clock generator 36 and to a variable phase-generator 38. The variable phase and clock signals are fed to a sinewave generator 44 which also receives from the DME 50 a slant-range connected signal representing the range of the VOR. The latter determines the amplitude of the sinewave (phasor). Signals representing the range # and bearing # 2  of the waypoint from the VOR are selected from a digital store 70 and, after conversion to analogue form, are fed to a waypoint bearing generator 66 and to a second sinewave generator 60 the output of which is a second phasor representing ## 2 . The phasors from the generators 44, 60 are subtracted in amplifier 56 to produce an aircraftto-waypoint phasor representing # 3  and DWP. This signal is resolved in resolver 86 into N and E components which are separately filtered in rate-limited filters 92. The waypoint phasor is then reformed in the circuit 98. The circuit 36, Fig. 1, shown in detail in Fig. 3, provides N- bearing clock signals and various other reference signals for the stages of the computer. The 30 Hz reference signal is converted to a square wave in a limiter 120 and fed to a phase-locked loop comprising a 4096 : 1 counter 134 and a VCO operating at a frequency of 4096 x 30 Hz. The loop ensures that the 30 Hz squared signal on output line 122 is in constant phase relation to the 122À88 kHz signal on output line 126, the latter being available for accurate gating purposes. A 240 Hz N signal on output line 128 is derived from an appropriate tap on the counter 134. The 122À88 kHz signal is used in synchronizing gate 140 to provide a gated 30 Hz north squared signal on line 142 which is used in turn to clear or re-set a 4096 : 1 countdown counter 144 clocked by the 122À88 kHz signal. The output of the counter is a 30 Hz N demodulator signal on line 146 and, through D-type flip-flop 152, an E demodulator signal on line 156. The output is also applied to a 2 : 1 counter 148 to provide a 15 Hz N signal on line 150. An appropriate stage in the counter is tapped to provide a 480 Hz N signal on output line 158. The variable phase generator 38, Fig. 1, shown in detail in Fig. 4, provides a variable 480 Hz signal on line 40 and a 30 Hz variable "pre-set" signal on line 42. The former is generated by a 251 : 1 counter 160 clocked by the 122À88 kHz signal and re-set by the 30 Hz N signal which is synchronized to the clocking signal. The sinewave (phasor) synthesizer, Figs. 6, 7, comprises a counter-controlled multiplex circuit 166 of which the input is the corrected range of the VOR (from the DME) on line 46, and which is clocked by the 480 Hz variable signal on line 40. The circuit 166 responds to the 30 Hz "pre-set" signal on line 42 such that the leading edge of this signal establishes a chosen lag or lead in the output sinewave. In this case, a 22À5 degrees lead is established to compensate for delay in subsequent filters. The 16 channels of the multiplex circuit are weighted by resistances 172, related to the gains of output amplifiers 178, 180, each resistor being selected twice as the counter rolls from 0 to 7 and twice again as it rolls from 8 to 16. The output on channels 0 to 7 is double-inverted, since both amplifiers are in circuit. The amplitude of the output sinewave is proportional to the range signal on line 46 and the phase is determined by the signals on lines 40, 42. The circuits 60, 66, Fig. 1, for generating the waypoint phasor are similar to the circuits 44, 38. The DWP phasor is resolved in N and E synchronous demodulators using the demodulator signals on lines 146, 156, Fig. 3. The orthogonal signals are then passed through 3-pole 6 Hz LP filters to respective constant slew-rate filters 92, shown in detail in Fig. 9. The filters each comprise an integrator circuit including a high-gain limiter/amplifier 216, capacitor 222 and resistors 218, 232. The output of the integrator is applied negatively to the input in the summing circuit 226. A switch 234 in series with resistor 232 enables the time constant of the integrator to be decreased in response to a signal on line 242 which appears whenever the waypoint signal changes suddenly (e.g. with change of waypoint). The filters then operate in a "fast catch-up" mode. The switching signal on line 242 is supplied through OR gate 240 either from a bi-stable 236 set by a waypoint signal on line 78, or by the output of a counter 245 which is stepped by a 30 Hz signal on line 122 whenever a forced reset signal is not present on line 248. The signal on line 242 actuates a blocking circuit 250, 252 in line 122 whereby counting ceases and the last stage of the counter continues to provide the switching signal. The forced reset signal on line 248 is generated by inverter 254 in response to lack of signal from OR gate 256 which has three inputs. One of these, on line 238, indicates a change of waypoint and causes the reset signal to disappear so that counter 245 starts to count. Half-way through the count (e.g. after 4 sees.), a signal on line 258 resets bi-stable 236. If the filters are still lagging at this time, this fact is sensed by one or other of the comparators 260, 270 connected to the remaining two inputs of OR gate 256. An output from one of the comparators causes the count to continue for the full count (e.g. for a further 4 sees.) after which the counter provides a fast catch-up signal on line 244. The comparators compare the positive and negative signals from the amplifiers 216 with reference signals from sources 268, 274. The outputs of the rate-limiting filters are fed to N and E phasor synthesizers (Fig. 8, not shown) which use the same 30 Hz signal on line 142 for preset, and the same 480 Hz signal on line 158 for clock. The synthesizers are preset to operate in quadrature. Their outputs are summed to provide a filtered waypoint phasor. The 30 Hz N signal is applied to the rotor of a resolver set to the desired course α and the sine and cosine outputs applied to opposite ends of a RC bridge the output of which is of the form K sin (#t+ α+45 degrees). A subsequent 30 Hz low-pass filter provides a lag of 45 degrees. The signal K sin (#t + α) is squared and synchronized with the 122À88 kHz signal on line 126 for application to a 4096 : 1 counter, thereby to provide a 30 Hz signal the phase of which is the desired course α. By means of a flip-flop clocked by a 60 Hz signal, a further course signal of phase α+90 degrees is produced, and the two quadrature waypoint signals used as inputs to a pair of synchronous demodulators, the signal input of which is the rate-filtered distance-to-waypoint phasor. The outputs of the demodulators are signals representing along-track and cross-track vectors. The former is used to operate a to/from indicator and the latter a cross-track error meter. The distance-to-waypoint signal is used to operate a digital distance indicator.