Patent GB-921363-A (GB)
Title: Improvements in or relating to simultaneous linear equation computer systems
IPC: G06G7/34
Filed: 1959-07-09
Abstract: 921,363. Electric analogue calculating. COMPAGNIE GENERALE DE TELEGRAPHIE SANS FIL, and SOCIETE MAROCAINE DE RECHERCHES D'ETUDES ET DE DEVELOPPEMENTS SOMAREDE. July 9, 1959 [July 11, 1958], No. 23636/59. Class 37. An analogue computer solving n linear simultaneous equations numbered 1 to n in p unknowns numbered 1 to p comprises p generator means for providing at their respective outputs adjustable voltages each simulating the unknown of the same number, a feedback loop connected respectively to the inputs of the generators for controlling their output voltages to respective equality with the roots of the equations; inserted in the feedback loop error calculating means coupled to the outputs for calculating n respective values of the n equations on incorporation therein of the respective voltage magnitudes to provide n error signals numbered 1 to n, each corresponding to the equation of similar number; a translating network comprising n sets numbered 1 to n of p reversible adjustable passive four-terminal networks numbered 1 top; the network numbered i in set j being designated ij and simulating the coefficiency of the unknown numbered i in the equation numbered j and each network having two inputs and two outputs; the inputs of each set being connected to respectively collect the error signals having the same number and the outputs of each four terminal network in each set being coupled to the outputs of the networks bearing the same number 1 to p in each other set and to the control input of the generator means having such same number. The equations have the general form: For solution of simultaneous equations: generators CX, CY (Fig. 1) supply voltage signals representing roots x, y together with a unity voltage 1 to error calculator EC adjustable to insert coefficients and to simulate the above equations to provide error signals # 1 , # 2  &c. corresponding to the computed equation values for instantaneous values of x, y which are fed to input channels A 1 , A 2  &c. of a translating network ER as described below adjustable for coefficients, to collect at B 1 , B 2  correction signals UxUy respectively in terms of x, y only, which are fed back to CX, CY to regulate their outputs to root values of x, y, at which the computed values of the equations are reduced to zero. The generators are constructed so that dx/dt = - Ux/k, dy/dt = - Uy/k , where k is a constant and t is time. The translating network which receives signals representing functions of plural roots (x and y) and yields at output channels control magnitudes which are functions respectively of each singular root is built up from reversible quadripolar networks of the kind set forth in Specification 703,178 comprising two inputs and two outputs respectively interconnected by reactances of predetermined sign, with reactances of opposite sign connecting each input to each output, and the latter reactances made variable so that their mathematical sum remains constant. A matrix is constructed representing the array of equations to be solved comprising n such quadripoles disposed horizontally in line and p quadripoles disposed vertically in column as shown in Figs. 2-5. In Fig. 2, quadripoles are arranged in columns j, j + 1 and lines i, i + 1 and inputs of the corresponding lines are connected in parallel to respective error current signals # i , # i  +  1  while outputs of corresponding columns are connected in parallel to yield correction voltage signals Vx j , Vx j  +  1  for the respective unknowns. It is shown mathematically that if signals x, y from corresponding generators are applied to an error calculator EC (Fig. 1) adjustable for coefficients to represent equations (2) above and the error signals # 1 , # 2  are given for any value of x by: 3  and applied to the appropriate input terminals of the quadripole matrix also adjusted for coefficients, the combined output signals U j , V j  + 1 represent functions respectively of x and y only which if fed back to the control terminals of the generators regulate their outputs to the respective values of x, y required for the solution of the equations. Other matrix arrangements comprise (Fig. 3) quadripolar networks in which voltage inputs derive voltage outputs and the inputs are series fed to quadripoles of corresponding lines while the outputs are derived in parallel from quadripoles of corresponding columns ; (Fig. 4) in which current inputs derive current outputs and the inputs are parallel fed to quadripoles of corresponding lines, while outputs are derived in series from those of corresponding columns; or (Fig. 5) in which voltage inputs derive voltage outputs and inputs and outputs are both series fed along respective lines and columns. Fig. 6 shows a system for solving equations (2) above wherein generators Cx, Cy energized from a steady source apply voltage signals analogous to x, y in parallel to an error calculator comprising quadripoles 101, 201 and 102, 202 respectively and a unity voltage is supplied to quadripoles 103, 203; the quadripoles respectively having coefficient variable admittances a 1 , a 2 , b 1 , b 2  and s 1 , s 2  respectively and being connected in two lines of three columns of quadripoles to simulate the equations (2) above so that the outputs represent error signals # 1 , # 2  for the two equations, which are fed to a translating network as in Fig. 2 above comprising two lines of two columns of quadripoles 1, 2, 3, 4 having coefficient variable admittances a 1 , b 1 , a 2 , b 2  respectively and parallel outputs from a 1 , a 2 , b 1 , b 2  developing control signals adjusting generators C x , C y  to develop x, y signals representing the equations roots. Impedance matching circuits may be inserted in the error signal connections between the error calculator and the translating network (Fig. 7, not shown). In a modification (Fig. 8, not shown) with a translating network of the kind shown in Fig. 3, the quadripoles of the error calculator comprise columns of coefficient adjustable transformers energized in parallel from the x and y generators and from a steady source; the outputs of each line of which are connected in series to develop error signals at the inputs of the switching circuit, also comprising coefficient adjustable transformers energized in series along each line from the error signals and developing control signals in parallel along each column for application to the respective generators. In a further modification (Fig. 9, not shown) similar to Fig. 6 with the interposition of impedance matching circuits in the error signal connections, the corresponding quadripoles of the error calculator and translating networks are associated for ganged coefficient adjustment, and the generator control signals operate respective servo systems of the kind described in Specification 902,534 to automatically adjust multipliers operating on the generator voltages to produce error signal nulls at which such voltages represent the roots of the equations. The invention is applicable to the solution of any number of equations with a corresponding number of unknowns by increasing the numbers of the generators and the quadripole lines and columns in the error calculator and the translating network.