Patent GB-748012-A (GB)
Title: Improvements in or relating to information storage circuits
Inventor: WRIGHT ESMOND PHILIP GOODWIN
IPC: G11C19/28
Filed: 1951-08-01
Abstract: 748,012. Digital electric calculating-apparatus; electric digital-data-storage apparatus. STANDARD TELEPHONES & CABLES, Ltd. July 25, 1952 [Aug. 1, 1951], No. 18187/51. Class 106 (1). In information storage equipment comprising a chain of interconnected " static electric switches " on which information may be stored as a pattern of operated and unoperated switches, which pattern may be caused to progress as a whole along the chain, a particular part of a pattern of stored information may be selected, or a stored item of information may be progressed to a predetermined position. A " static electric switch " is defined as a device having a permanently positioned electrical path, the impedance of which may be changed from one to the other of two values by a change in a controlling electric field from one stable condition to another. In the apparatus shown, for use e.g. in an electronic computer, binary numbers are stored in independent sections of a pattern movement register PMR, Fig. 3, similar to that described in Specification 663,574, [Group XXXIX], comprising a chain of cold cathode gas-discharge tube stages 1-36, each section comprising, e.g. nine stages. Entry is made in telegraph code into a decoder, Fig. 1, by a teleprinter operating a relay TR, firstly of an address number which causes PMR to be stepped to position a selected number with its least significant digit in stage 36, and secondly of a number to be added to the selected number. The circuits of the apparatus consist primarily of multi-cathode discharge tubes such as TA-TC, Fig. 1, e.g. as described in Specification 692,415, trigger pairs of cold cathode discharge tubes such as TS, and metal-rectifier coincidence gates such as the 3-threshold gate G1. Decoder.-This is similar to the apparatus described in Specification 732,346 and comprises trigger pairs PE, A, B, Fig. 1, of tubes M, S arranged to respond to " mark," " space," respectively in the received coded character which is represented by five elements preceded by a "space " (start element) and followed by a " mark " (stop element). The starting " space " shifts contacts tr1 to operate PES and render tube TST of start trigger pair TS conducting. This starts a time-scale control circuit, similar to that described in Specification 692,436, comprising tubes TA, TB, TC which are stepped by 5 kc/s. pulses P1 through a single cycle, as indicated in Fig. 20, and reset when tube TSZ is re-fired by a pulse through gate G1, Fig. 1, when the tubes are discharging at positions TC6, TB9 and TA9. Time positions t0, t1-t5, t6, Figs. 1 and 20, correspond to the midpoints of the character elements, and triggers A, B are set by the first and second significant elements respectively so as to select one of four multi-cathode "resolver" tubes RA-RD. Stepping of the discharge in the selected tube is effected by pulses from Z at t3a and at the further times t3<SP>1</SP>, t4<SP>1</SP>, t4<SP>11</SP>, t5<SP>1</SP>-t5<SP>1111</SP>, if the element in the third, fourth or fifth position is a " space," by causing PES, through cathode follower CFS, to apply an opening potential to gate G4. The outputs of tubes RA-RD, when they represent an address, control the arrest of the stepping of PMR through gates G9-G40, Fig. 3 and, when they represent a decimal digit to be added to a number in PMR, control cathode follower gates DF1, DF2, DF4, DF8, Fig. 4, as described in Specification 732,341, to produce a binary translation of this digit. (1) The addresscontrol and (2) the adding operations are described separately below. Operation-(1). When TST operates at the beginning of entry of an address, trigger pair N-P, Fig. 3, is switched to the P-conducting condition so that pulse tm, Fig. 20, which occurs after the address number has been set on tubes RA-RD, Fig. 1, is allowed through gate G6 to switch trigger pair DS, Fig. 3, to the condition with DST conducting. This opens gate G72 to allow stepping of PMR by 2 kc/s. pulses P2 and of a distributer comprising four multicathode tubes DA-DD (Fig. 2, not shown), in synchronism therewith. The outputs of these tubes open the gates G9-G40 in succession to allow the operative output from RA-RD to reset DS and arrest the stepping at the required position. Operation-(2). The second operation of TST restores N-P to the N-conducting condition so that the next pulse tm is allowed through gate G75, Fig. 3, to cause AST of trigger pair AS to conduct, and also causes entry of the binary number represented by the outputs of DF1, DF2, DF4, DF8, Fig. 4, through gates G50-G53, Fig. 6, to trigger pairs ID-OD1, OD2, OD4, OD8 which form a binary counter and auxiliary stepping register. AST opens gate G76, Fig. 3, to cause pulses P1 to step cyclically a scale-of-three distributer SC (similar to those described in Specification 677,872) having outputs Pa, Pb, Pc. Every Pa pulse causes the output of PMR36 to be added into counter trigger pair ID1-OD1, Fig. 6, through gate G54 or G65, carries being effected through gates G55, G56, G90, G91, G92 and G93. The following Pb pulse passes through gate G78 to step PMR so that the next digit is in position 36, and, position 1 is free to receive the digit registered on ID1-OD1 through gate G57 during the Pc pulse, the output of ID1 being obtained from cathode follower CF5. The Pc pulse also causes stepping down of the number in the auxiliary register through gates G60, G61, G59, G62, G58, G63 and G64. The sum of the selected number in PMR and the number in the auxiliary register is thus formed and fed back to PMR in place of the original number, the normal connection between PMR36 and PMR1 being inhibited. After 36 cycles of SC, AS is returned to normal and the auxiliary register is cleared by pulse t2, Fig. 20, which also passes through gate G70, Fig. 3, to reoperate DST to step PMR back to its original condition when DS is reset by the output DA1 of the distributer DA-DD (not shown) applied through gate G74. To clear a section of PMR, a character which sets the decoder to RA6 is used. The pulse tm then operates trigger pair COK-COL, Fig. 3, through gate G77, so that input gate G57 to PMR1 is inhibited during nine cycles of SC (assuming there are nine digits in a section) when the trigger pair is reset by pulse tx. Modification.-The distributer DA-DD could continue to step while the new number was being added. The trigger pair P-N could be modified for enabling a series of numbers to be added successively in the same position of PMR. Arithmetic operations other than addition may be performed, e.g. multiplication, division and subtraction as described in Specification 727,012.