Patent GB-1522098-A (GB)
Title: Digital raster display system
IPC: G09G5/02
Filed: 1976-10-29
Abstract: 1522098 Image generators for raster display systems SPERRY RAND CORP 29 Oct 1976 [11 Nov 1975] 45120/76 Heading H4T A raster display system utilizing a cathode-ray tube comprises digital generating means 40 for synchronously generating a raster and reading-out the contents of a memory 14 having storage locations corresponding one-to-one with display locations or cells, the memory providing address signals corresponding to locations in a symbol memory 16 which stores symbols or patterns each occupying a display cell. As shown, a c.r.t. line and frame generating circuit 33, 36 is synchronized by a timing circuit comprising a clock 41 and two 9- stage counters 42, 44 respectively providing horizontal and vertical sync. pulses. The raster thus comprises 512 lines each containing 512 dots and the display may be regarded as a 32 X 32 matrix of cells, each cell containing a matrix of 16 X 16 dots. Each cell corresponds to a unique storage location in a map memory 14 containing a 32 x 32 array of locations. The five MSB's in the output of counter 42 uniquely define an X co-ordinate in the memory 14 and the five MSB's in the output of the counter 44 uniquely define a Y co-ordinate. These signals are fed over lines 47, 50, 52 to the memory 14 and read out the contents thereof synchronously with generation of the raster. Each 16-bit word stored in memory 14 comprises a 6-bit address position fed to a symbol memory 16, a 2-bit video portion fed to a video gate 63 and a 2-bit priority portion fed to a priority selector 65. The symbol memory (Fig. 3) comprises 64 "pages" each consisting of a pattern of dots formed from a 16 Î 16 array (three examples shown), corresponding to the 16 Î 16 dot array of a display cell. The address signals from map memory 14 are multiplexed with a signal from Y-counter 44 on line 56 consisting of the four LSB's of the output of this counter. This signal changes at line frequency and goes through a complete cycle every 16 lines. It is used to read out row by row the page of memory 16 addressed by the map memory 14. The lines are loaded into a parallel-to-series shift register 19 on receipt of a "load" signal from X-counter 42 which occurs every 16 pulses from the clock 41. The clock signal is also used to shift the line out of the register 19 at raster dot rate into the selector 65 via gate 63. The latter is fed with the video portion of the 16-bit word read from map memory 14 which is used to determine the grey level of the display dots. The elements 14, 16, 19, 63 comprise a channel I of the system which also contains channels 2-4 comprising like elements and having outputs applied over line 70 to the selector 65. The selector 65 comprises logic circuitry for selecting that channel having highest priority and a ONE on the associated "enable" line, or, in the case of two or more equal channels, the channel with the highest video signal. Thus the system is capable of multiple pattern overlay down to dot level since the selector 65 operates at dot rate. The map memory 14 and symbol memory 16 are updated during frame flyback time from a computer over address bus 72 and data bus 73. In general the symbol memory need only contain as many storage locations as there are symbols to be refreshed.