Patent WO-2023027811-A1 (WO)
Inventor: CHEN YUJEN
IPC: H01L23/485
Filed: 2022-06-30
Abstract: An integrated device (e.g., a flip chip) (100) comprises: a die portion (102) comprising a plurality of pads (107a, 107b) and a plurality of under bump metallization interconnects (109a, 109b) coupled to the plurality of pads (107a, 107b); and a plurality of pillar interconnects (104a, 104b) coupled to the plurality of under bump metallization interconnects (109a, 109b), wherein the plurality of pillar interconnects (104a, 104b) comprises a first pillar interconnect (104a) comprising a first cavity (209) and a second pillar interconnect (104b) comprising a second cavity (209). The cavity (209) may extend partially through a height of the pillar interconnect (104a, 104b). A planar cross section that extends through the cavity (209) of the pillar interconnect (104a, 104b) may comprise an O shape. A plurality of solder interconnects (106a, 106b) may be coupled to the plurality of pillar interconnects (104a, 104b) and may comprise solder interconnects (106a, 106b) located in the cavities (209) of the pillar interconnects (104a, 104b). The pillar interconnect (104a, 104b) may comprise: a first pillar interconnect portion (204) comprising a first width; and a second pillar interconnect portion (206) comprising a second width that is different (e.g., smaller) than the first width, wherein the cavity (209) of the pillar interconnect (104a, 104b) may be located in the second pillar interconnect portion (206). The pillar interconnect (104a, 104b) may comprise a shape of a top hat. A method (700) for fabricating the integrated device (100) may comprise providing the die portion (102) and forming the plurality of pillar interconnects (104). Forming the plurality of pillar interconnects (104) may comprise: forming and patterning a first photoresist layer (600) over the die portion (102); forming a first pillar interconnect portion (602) (e.g., ring-shaped); removing the first photoresist layer (600); forming and patterning a second photoresist layer (610) over the die portion (102) (e.g., with a circular pattern with a diameter between the inner and outer diameter of the ring-shaped first interconnect portion (602)); and forming a second pillar interconnect portion over the first pillar interconnect portion (602) such that the first cavity (209) is formed in the second pillar interconnect portion. Forming the plurality of pillar interconnects (104) may further comprise forming the solder interconnects (106) over the cavities (209) of the pillar interconnects (104). The second photoresist layer (610) may be removed after the formation of the first solder interconnects (106). Portions of the under bump metallization layer (109) may then be removed and the plurality of solder interconnects (106) may be reflowed. A package (400) comprises a substrate (402) and the integrated device (100) coupled to the substrate (402) through the plurality of pillar interconnects (104a, 104b) and the plurality of solder interconnects (106a, 106b). The solder interconnect (106a, 106b) may comprise an intermetallic compound (IMC) (406a, 406b), which may be formed when metal from a substrate interconnect (422a, 422b) and/or the pillar interconnect (104a, 104b) diffuses in the solder interconnect (106a, 106b) upon solder reflow process used to couple the integrated device (100) to the substrate (402). The cavities (209) allow more surface area for the solder interconnects (106a, 106b) to couple to, thus providing a more robust and reliable joint between the integrated device (100) and the substrate (402). The cavities (209) also allow more solder interconnect (106a, 106b) to be located between the pillar interconnects (104a, 104b) and the substrate (402), without causing a short between neighbouring interconnects (104a, 104b) of the substrate (402).