Patent GB-936306-A (GB)
IPC: G11C11/44
Abstract: 936,306. Cryotron stores; sorting data. INTERNATIONAL BUSINESS MACHINES CORPORATION. July 29, 1960 [Aug. 28, 1959], No. 26457/60. Class 106 (1). A data store, preferably employing cryotrons, may be used in two ways : (a) as an associative memory, in which a data word is read out not by specifying its address but by specifying a part or all of the word; or (b) as a data sorter, in which successively entered words are ordered within memory in respect of part or all of the data word, overflow resulting in the ordered sequence being read out. For forward sorting (ordering from low to high) a word is read in in parallel to entry register 20 (Fig. 1) during a cycle A. During a cycle B the contents of register 20 are transferred to that dummy register 28 above the word register 26 containing the first word of the sequence higher than the entered word, and all words above the dummy register containing the new word are shifted up one register. On the next cycle A a new word is read in to register 20 and all the words above and including the word entered on the previous A cycle are shifted up one register so that the contents of memory are ordered in the word registers from low at the top to high. When a word is in the forward exit register either having been shifted in from word register 1 or read in directly it is read out but not destroyed and in the next A cycle is entered in the echo exit register 36. A word in the entry register is compared with the contents of the echo exit register and if found to be low is entered in the bottom dummy register, the backward exit register and all words above are given a distinguishing auxiliary bit. This prevents spoiling a sequence by causing, e.g. a 10 to be read out after an 11. Incoming words are then entered in either the old sequence or the new sequence starting with the word in the backward exit register. The memory is symmetrical and a backward sort from high to low is merely a forward sort with words moving downwards instead of upwards and the terms high and low interchanged. Words having the same comparison value are read out in the order they were read in, A cryotron flip-flop using thin film cryotrons is shown in Fig. 3b. Application of negative potential to terminal 88 causes current flow in the control coil of cryotron 76 rendering the gate conductor 80 resistive. Current from terminal 64 then flows through the left-hand path 66 through the control coil of read out cryotron 92 sending the gate conductor 100 resistive and through the control coil of cryotron 62 which sends conductor 72 in the right-hand path 68 resistive and thus maintains bi-stable operation. Read out is by current from terminal 96 which flows through the superconductive gate 98 since no current is flowing through the resistive right-hand path 68 and the gate control coil is not energized. Forward entry (sorting from low to high). Control circuits (Fig. 4c) operate to produce current flow in superconductive lines when conditions exist that are determined by the setting of a timing signal (TS) switch 110, an entry-exit switch 180 and a forward-backward switch 262. TS switch 110 is controlled from the computer and sets a trigger 136 which gates current to read-out lines TS on 160, 162 and 164, and TS off 166, 168, 170. TS off line 166 feeds entryexit switch 180, which sets trigger EE1, and continues as a read out line for trigger EE2 which is set by TS on line 160 (254) which in turn reads out EE1. Thus the state of read-out lines 220, 222, 224, 226 is determined by the setting of switches 110, 180 in combination. These lines merge to form entry and exit lines 202, 198 respectively. The forward-backward switch 262 sets a trigger which controls read-out lines 280, 282. A terminal 298 provides current on lines 332, 342 if the TS off-entry conditions exist with switch 262 forward or backward respectively. The entry register (Figs. 4a, 4b) has storage flip-flops for a vacancy bit (the function of which will appear hereafter) an auxiliary bit and data bits and for mask bits which determine on which bit positions the comparison between the contents of the entry register and the words in memory. Current from terminal 520 flows through a typical mask bit switch 350 at TS on (conductor 988 resistive) to set a flip-flop. If the switch is set to 0 current flows in control coil 538, steering current to the right-hand path 540 of the flip-flop with the result that gate 542 conducts and a no compare signal issues on line 544. If the switch is set to 1, gate 528 is conductive and the data bit d flip-flop steers current to one of the compare lines 532, 536. With TS on, gate 988 is conductive and the state of lines 532, 536 and 544 is maintained. Data bit d flip-flop also steers current from terminal 580 at TS on to one of lines 2038 or 1018 if an entry operation is taking place and it stores 0 or 1 respectively, and at TS off to one of lines 580, 572 if an exit operation is taking place. Figs. 4d to 4f show the forward exit echo and forward exit registers with word register 1, the latter being typical of the dummy and word registers respectively. Current from terminal 700 (Fig. 4d) flows through the flip-flops of word register 1 to compare their settings with those of the flipflops of the entry register. The compare circuits are used only if the vacancy bit of the word register is 1 when current flows in conductor 702 (current flowing in left-hand path of vacancy bit flip-flop). Conductor 702 splits into four at the auxiliary bit flip-flop. The upper path contains gates which are resistive if a no compare signal on line 384 is present, the entry register flip-flop is at 0 or the word register flip-flop is at 1. If none of these conditions exist current is steered to the low line 714. The other three paths include gates which as appropriate steer current to equal or high lines. If comparison of the auxiliary bit gives equal, current is directed to the data bit d compare circuit and if again equal from there to the data bit d-1 and so on. Comparison takes place as soon as the circuit are stable and may be considered as occurring during cycle B, i.e. with TS on. At TS on in an entry operation, current on the low or equal lines passes gate 832 or 744 (Fig. 4f) respectively and steers current from the entry line 202 into a no previous select line 918 and thereafter sets a remembering trigger to 0 by energizing the gate control line 840. If a high comparison exists the previous select line 752 is rendered conductive, which inhibits action in any lower register, and the remembering trigger is set to 1. At TS off the remembering trigger maintains the state of lines 752, 918, through read-out conductors. After having set the remembering trigger the high line becomes select line 1060, the current flowing in which causes the contents of the entry register to be read in to the dummy register-in this case the forward exit registerimmediately above the word register at which the first high comparison is made. The first high comparison is chosen since the previous select line controls gates in lower registers (not shown) to inhibit a select signal. The entry of data is made by current on the entry 1 and 0 lines from the entry register, e.g. lines 2038 and 1018 (Fig. 4d) controlling gates which steer current in the select line to one side or the other of the data storage flip-flops of the dummy register. To effect transfer up of the contents of the forward exit register to the forward exit echo register current from terminal 2452 appears on line 2450 at TS off and makes resistive gates 2452, 2464 . . . used in transfer down and continues as the dummy out line 2472. The current then sets gates in the echo register according to the setting of the flip-flop of the exit register: e.g. current flows in gate 2476 of the echo register flip-flop sending its right-hand path resistive if and only if the gate 2480 in the echo register flip-flop is conductive due to the right-hand path being resistive. In lower registers the transfer up signal is inhibited by a previous select signal. A word when entered in the forward exit register energizes read-out coils (not shown). The contents, which do not include an auxiliary bit, of the echo register are also included in any comparison, an equal or low resulting in current appearing on line 484, a high energizing line 486, resulting in the auxiliary bit in the entry register being set to 0 or 1 respectively. The auxiliary bit of the forward exit register is examined at each TS off by current on line 332 (Fig. 4d). If the bit is 1, all auxiliary bits are set to 0, current flowing in the right-hand paths of the flip-flops, but if 0, gate 420 is conductive and no change is made. Thus, the effect of setting the auxiliary bit of entry register to 1 is to make the contents of that register high with respect to the contents of all other registers and the new word is sent to the bottom dummy register. Exit operation.-It is assumed that all words have a vacancy bit 1. Comparison is made between the part of the word in the entry register selected by setting mask bit switches to 1 and similar parts of words in the memory. On equality being found the word is read out. Assuming that word register 1 contains the required word, current flows on the equal line 728 and diverts current on the exit line 198 to previous match line 784, thereafter setting the remembering trigger to 1 to maintain current in the line 784 at TS off and becoming the match line 740. This is similar to the select line and causes the state of the data storage triggers to be reflected in the stage of the entry 1 and 0 lines which enter the contents of register 1 into the forward exit register. This is then read out as before. If equality is found in two or more registers the previous match signal inhibits read-out of the lower registers. If the vacancy bit in the entry register is 0 the contents of all registers above the high