Patent GB-1480907-A (GB)
Title: Data analysis device for a transit exchange
IPC: H04L12/52
Filed: 1974-07-29
Abstract: 1480907 Data exchanges TELEFONAKTIEBOLAGET L M ERICSSON 29 July 1974 [10 Aug 1973 7 June 1974] 33466/74 Heading H4P In a data analysis device for use in a transit exchange for transmission of asynchronous data signals with known character structure and known signalling rate which are sampled in the exchange in synchronism with a clock pulse several times per data pulse for establishment of the binary content of the data signals, a clock pulse counter KR, Fig. 3, has a first summation circuit SK1 for summation of clock pulses occurring during a data pulse and a first decoder AK1 delivers indication signals ACU at specific positions of the summation circuit. An accumulator AC has a second summation circuit SK2 for counting the number of sampling pulses with a given binary value during an interval determined by indication signals from the first decoder AK1 and a control logic AL permits elimination of sampling pulses coinciding with clock pulses during initial and final phases of a data pulse in the summation. A second decoder AK2 delivers an indication signal when the second summation circuit SK2 has reached a specific counting position. The analysis device further includes a first logic circuit 1L which in dependence on whether the second summation circuit SK2 has or has not reached the specific counting position when the first summation circuit SK1 has reached a position corresponding to the final phase of the data pulse, delivers a binary signal at ACU for indication of the binary value of the data pulse.  The analysis device can further contain a logic circuit KL, ER, EL which includes a counter ER for the number of received data pulses, a third summation circuit SK3 for summation of the number of data pulses arriving after a start pulse and a third decoder AK3 which delivers indication signals at specific positions of the summation circuit. The logic circuit EL starts the counter ER when the binary value 1 has on the first occasion been indicated by the first logic circuit 1L after which the counter is stepped every time the clock pulse counter has completed one cycle so that in the specific phase it delivers a final signal corresponding to all pulses associated with a character being received and that all circuits in the analysis device are to be restored to the starting position. An analysis device can be decoder memory equipment (AKM, Fig. 1, not shown) in a transit exchange for serving incoming subscriber lines on the TDM principle. Specification 1,480,906 is referred to regarding the transit exchange. Such a decoder memory (AKM) is disclosed (Fig. 5, not shown) which in addition to clock pulse counter KR (KRM), the accumulator AC (ACM), the element counter ER (ERM) and control logic circuits KL (KRL), AL (ACL) and EL, RL (ERL) of Fig. 3 includes an element value register (EVM/ELV) for storage of character elements after each analysis cycle and a flag bit register (FBM/FBL) which indicates completion of analysis cycle. Output (AKU) from decoder logic (AKL) associated with the decoder memory (AKM) provides information concerning the analysed character element which is transferred to control equipment (SU, Fig. 1, not shown) of the exchange to be stored in a memory (MBM) in the memory position associated with the incoming subscriber's line. A modified form of Fig. 3 is disclosed (Fig. 6, not shown) having a supervisory logic AND gate (CL) with which the clock pulse counter KR can be restored after an initial analysis phase and a control logic (DL) including on AND gate (D1) and on (OR) gate D2 which functions to reverse the accumulator AC when a subtraction is to be made in the accumulator during the initial analysis phase.