Patent GB-996407-A (GB)
Title: Signal sequence detector
IPC: H03K17/82
Filed: 1963-11-12
Abstract: 996,407. Circuits employing bi-stable magnetic elements. AMP Inc. Nov. 12, 1963 [Nov. 13, 1962], No. 44559/63. Heading H3B. [Also in Division G4] A binary signal sequence detector may be programmed to respond to any predetermined signal sequence. The device comprises, for each signal of the sequence, a stage switchable between first and second conditions in which it can store one or other binary digit from the signal source, the stages being coupled so that when a digit is stored in one stage an output is produced to actuate the next stage, the last stage of the detector being coupled to means for generating a success signal when all the stages have generated an output signal. In Figs. 1 and 2 each stage comprises three multi-aperture magnetic cores 1 to 3, 4 to 6, 7 to 9 and 10 to 12. The device is programmed by turning the switch 35 of each stage to either the " 1 " or the " 0 " contact, thus setting the first core and clearing the third core of a stage, or vice versa. When core 2 has been set by energizing winding 39 the first signal digit is supplied to winding 37. If the digit is a " 1 " the core material around aperture 21 is primed, whereas if the digit is a " 0 " the material around aperture 20 is primed. At the same time the material surrounding apertures 20 of cores 1 and 3 is primed by windings 22, 23 (Fig. 2). Winding 15 is then energized to clear all the cores of the first stage. If the first stage is programmed to store a " 1 " and has received a " 1 " the clearing of core 2 will generate an output in transfer winding 26 to set core 5 of the second stage. Clearing of core 1 generates a signal in transfer winding 25 in such a sense as to have no effect on core 5. Core 3 is already clear so no switching occurs. If the first stage was programmed to store a " 0 " and receives a " 0 " transfer winding 25 is energized to set core 5, while the current in winding 26 has no effect. If the stage was programmed to store a " 1 " and receives a " 0," aperture 20 of core 2 would be primed and when cleared would produce a signal in winding 25 in opposition to that produced by clearing core 1. Winding 26 would not be energized so core 5 would not be set. Subsequent signal digits would not ther produce an output from the stage programmec to receive them since the stages would not be set. If each digit is correct each stage is set in turn and finally output core 13 is set anc winding 41 is energized to indicate success. In a modification, Fig. 3, each stage consists of two multi-aperture cores and a smaller single aperture core. The device is programmed by setting or clearing cores 44, 46, 48 by means o: windings 56 or 55. If the first stage is pro grammed to store a " 1 " and a " 1 " is received from signal source 60, the second stage will be set, as follows. The signal digit primes the material around aperture 52 of core 44 and also sets core 44<SP>1</SP>. Core 43 having previously been set by energizing winding 66, all the cores of the stage are cleared by energizing winding 61. Clearing of cores 44, 44<SP>1</SP> produces equal and opposite currents in transfer winding 68, while the clearing of core 43 induces a current to set core 45. If a " 0 " digit had been received the material around aperture 53 of core 44 would have been primed, while core 44<SP>1</SP> would have remained in its clear state. Subsequent clearing of the cores would induce equal and opposite currents from switching of cores 43 and 44, and no current from switching core 44<SP>1 </SP>so core 45 would not be set. If the stage had been programmed to store a " 0 " and a " 0 " was received the clearing operation would induce an output due to switching of core 43 only, which would then set core 45. Since core 44 was in its clear state due to the programming operation it would produce no output. If a " 1 " were to be supplied to a " 0 " responsive stage the outputs produced by clearing cores 43 and 44<SP>1</SP> would cancel, core 44 again having no effect. When all the stages have produced an output core 49 is set, and when it is subsequently cleared will generate a success signal. Specification 899,366 is referred to.