Patent GB-823513-A (GB)
Title: An electrical arrangement for converting decimal numbers into binary numbers or viceversa
IPC: H03M7/08
Filed: 1958-03-19
Abstract: 823,513. Electric selective signalling systems. TELEFUNKEN G.m.b.H. March 19, 1958 [March 20, 1957], No. 8787/58. Class 40 (1). [Also in Group XIX] An electrical arrangement for converting decimal numbers into binary numbers or vice versa is provided with a two-section shift register having a first section which takes up the decimal number in a binary coded form and a second section which takes up the binary number, means for shifting the number from one register section into the other by repeated multiplication (left shift) or division (right shift) by two, and means for testing for pseudo-decimals and overflows occurring between two shifts by one position and for performing the corresponding corrections. Two embodiments are described a first for converting binary-coded-decimal numbers into pure binary numbers, or vice versa, and a second for converting floating point binary-coded-decimal numbers into floating point pure binary numbers or vice versa. In both embodiments the conversion is effected mainly by repeated halving or doubling by means of a shift register. In the first embodiment, Fig. 1, a binary-coded-decimal fraction D, having three decimal digits I, II and III with the decimal point coming at the left of digit I, is inserted into a shift register, as shown, and is converted into a pure binary fraction in ten steps (one step for each binary digit), each step comprising a left shift together with a correcting cycle. For example, if D = 0.413 the following steps occur : During each correcting period of each step certain stages of the shift register are changed over, these being indicated in the table by an x, to take into account the fact that since each decimal digit is coded in pure binary a left shift only correctly doubles it when it is less than 5. The corrections that have to be made during any step are determined by an array of gates (Fig. 2, not shown). The final result in the B half of the shift register, after step 10 in the table, is the pure binary fraction that corresponds to the decimal number 0.413, ten binary places being taken since 2<SP>10</SP> 10<SP>3</SP>. In the second embodiment, Fig. 3, a floating point decimal number D having an exponent stored in a counter P is converted into a floating point binary number B having an exponent stored in a counter Q. The conversion is in two parts: first the binary exponent Q is determined and then the binary number B is determined. Consider, for example, the conversion of the decimal number 10<SP>-2</SP>. 0.100, then the following operations take place : Each multiplication by 2 is achieved by one left shift followed by appropriate corrections and each division by 10 by four right shifts-no correction being necessary. Multiplications by 2 are performed repeatedly together with the subtraction of unity from the counter Q until a carry from the decimal part of the shift register to the binary part occurs, this being indicated by an X in the table. Division by 10 is then effected together with the addition of unity from the counter P. This sequence of operations is repeated until the counter P reaches zero. The conversion process then follows the pattern of operations described with reference to Fig. 1. Binary to decimal conversions are performed by reversing the above operations.