Patent SG-11201900093V-A (SG)
Title: Mechanism to accelerate graphics workloads in a multi-core computing architecture
Inventor: BENTHIN CARSTEN
IPC: G06F9/50
Filed: 2017-07-12
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property 1111111111 01110101011111011111010011101011110011111110101111111011110111111 Organization International Bureau (10) International Publication Number (43) International Publication Date .....0\"\" WO 2018/026482 Al 08 February 2018 (08.02.2018) WIP0 I PCT (51) International Patent Classification: (74) Agent: MALLIE, Michael J. et al.; BLAKELY GOOF 9 / 3 0 (2006.01) GOOF 9 / 50 (2006.01) SOKOLOFF TAYLOR & ZAFMAN LLP, 1279 Oakmead Parkway, Sunnyvale, California 94085 (US). (21) International Application Number: PCT/US2017/041746 (81) Designated States (unless otherwise indicated, for every (22) International Filing Date: kind of national protection available): AE, AG, AL, AM, 12 July 2017 (12.07.2017) AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, (25) Filing Language: English DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, (26) Publication Language: English HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, (30) Priority Data: MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, 15/229,550 05 August 2016 (05.08.2016) US OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, (71) Applicant: INTEL IP CORPORATION [US/US]; 2200 TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. Mission College Boulevard, Santa Clara, California 95054 (US). (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, (72) Inventors: BENTHIN, Carsten; Kinzigweg 10 V, 66333 GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, Volklingen (DE). WOOP, Sven; Tannenweg 9, 66333 UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, Volklingen (DE). WALD, Ingo; 10631 Chestnut Ridge TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, Road, Austin, Texas 78726 (US). — EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, = (54) Title: MECHANISM = = = = = = = 1512 CORE 0 1610 TO ACCELERATE GRAPHICS WORKLOADS IN A MULTI-CORE COMPUTING ARCHITECTURE — 1 • CORM I 1610 I 1 ------------------, CORE N 1610 = = — FPGAO 1620 FPGA1 1620 0 0 0 FPGA N 1620 = = = _ = ,ir = LLC CACHE 1640 II LLC CACHE 1640 1-1 .4 oc 7r ei =, (57) : c 3 - 1 -5 core and a second ,1 execution of graphics 0 accelerate execution ei N FIG. 16A A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate workloads processed at the first processing core and a second FPGA coupled to the second processing core to of workloads processed at the second processing core. C [Continued on next page] WO 2018/026482 Al MIDEDIMOMOIDIDIROHOIDOMOIOHIODHIMMOIllii0VOIMIE TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))