Patent EP-0053650-A2 (EP)
Inventor: ACHTSTATTER GERHARD ING GRAD
IPC: H04N3/16
Filed: 1981-06-16
Abstract: 1. Monolithic integrated vertical-deflection circuit for television sets with tangent-corrected line-frequency-derived digital generation of the pulsewidth-modulated signal for directly driving a class-D push-pull vertical-deflection stage or for driving a class-B push-pull analog vertical-deflection stage via an integrator and with an up-counter (VZ), with a first programmable read-only memory (PROM1), with a second programmable read-only memory (PROM2), which holds a digital word corresponding the deflection current at the top or bottom of the image, with a first clock generator (TG1) whose frequency is on the order of the color-subcarrier frequency, with a first counter which participates in the generation of the drive signal for the upper (or lower) half of the image, and with a second counter which participates in the generation of the drive signal for the lower (or upper) half of the image, the count inputs of said first and second counters being coupled to the output of the first clock generator (TG1), characterized by the following features : The count input (Ez) and the reset input (Er) of the up-counter (VZ) are fed with the horizontal deflection pulses (HA) and the vertical synchronizing pulses (VS), respectively, and the count outputs of the up-counter (VZ) are connected to the address inputs (Ea) of the first programmable read-only memory (PROM1) via a decoder (DC) ; the S-shaped characteristic of the deflection-stage current is approximated by portions of constant slope whose associated slope values are stored in the first programmable read-only memory (PROM1) under one address each ; the output of a second clock generator (TG2) is connected via one of the input-output paths of a first AND gate (UG1) to the count input (Ez) of a first presettable down-counter (RZ1), whose parallel preset input (Ev) is connected to the parallel output of the first programmable read-only memory (PROM1) via first input-output paths of a first multiple AND gate (MU1), and whose zero-state output (A0) is coupled to the other input of the first AND gate (UG1), while the second inputs of the first multiple AND gate (MU1) are fed with the horizontal-deflection pulses (HA) ; the output of the first AND gate (UG1) is connected via a frequency divider (FT) to the count input (Ez) of a first presettable up-counter (VV1) whose preset enable input (Es) is fed with the vertical synchronizing pulses (VS) and whose parallel preset input (Ev) is connected to the parallel input of the second programmable read-only memory (PROM2), the reset input (Er) of the frequency divider (FT) being fed with the vertical synchronizing pulses (VS) ; the output of the first clock generator (TG1) is connected via one of the input-output paths of a second AND gate (UG2) to the count input of a second presettable down-counter (RZ2) forming the first counter, and via one of the input-output paths of a third AND gate (UG3) to the count input of a second presettable up-counter (VV2) forming the second counter ; the count outputs of the first presettable up-counter (VV1) are connected to the parallel preset input (Ev) of the second presettable down-counter (RZ2) via first input-output paths of a second multiple AND gate (MU2) ; the second inputs of the second multiple AND gate (MU2) are fed with the horizontal-deflection pulses (HA), and the third inputs of the second multiple AND gate (MU2) are connected to the output of an inverter (IV) having its input connected to the output (Am) of the first presettable up-counter (VV1) for the most significant bit ; the count outputs of the first presettable up-counter (VV1) are connected to the parallel preset input (Ev) of the second presettable up-counter (VV2) via first input-output paths of a third multiple AND gate (MU3) ; the second inputs of the third multiple AND gate (MU3) are fed with the horizontal-deflection pulses (HA), and the third inputs of the third multiple AND gate (MU3) are connected to the output (Am) of the first presettable up-counter (VV1) for the most significant bit ; the count outputs of the second presettable down-counter (RZ2) are connected via a first multiple OR gate (MO1) to the drive-signal output (A') for one half of the image, which output is also connected to the other input of the second AND gate (UG2) ; the count outputs of the second presettable up-counter (VV2) are connected via a second multiple OR gate (MO2) to the drive-signal output (A") for the other half of the image, which output is also connected to the other input of the third AND gate (UG3), and the frequency of the second clock generator (TG2) is chosen so that when the first presettable down-counter (RZ1) is set to the highest slope value, its zero state is reached within one line period.