Patent TW-283802-B (TW)
Title: CMOSFET fabrication process with short time
Inventor: SONQ JIANN-MAY
IPC: H01L27/105
Filed: 1995-01-12
Granted: 1996-08-21
Abstract: A fabrication process of implementing CMOSFET on semiconductor substrate comprises the steps of: implementing field oxide on the above semiconductor substrate; growing first insulator on the above semiconductor substrate which is not covered by field oxide; forming photoresist pattern on specific area of the above semiconductor substrate; doping first impurity ion on the above semiconductor substrate which is not covered by photoresist to form N well area; doping second impurity ion on the above semiconductor substrate to from P well area under the above photoresist without affecting the above substrate N well area which is not covered by the above photoresist; removing the above photoresist; doping third impurity ion on the above semiconductor substrate which is not covered by the above field oxide; removing the above firs insulator; growing second insulator on the above semiconductor substrate which is not covered the field oxide to implement gate insulator; depositing one polysilicon on the above gate oxide and field oxide; doping fourth impurity ion on the above polysilicon; depositing one third insulator on the above polysilicon gate structure, the above gate oxide which is not covered by the above polysilicon gate structure and the above field oxide; anisotropicaly etching the above third insulator to form insulating sidewall spacer of the above polysilicon gate structure; doping fifth impurity ion on P well area which is not covered by the above polysilicon gate structure, but implanting to below the above insulating sidewall spacer to form lightly doped drain and source area; doping sixth impurity ion on P well area which is not covered by the above polysilicon gate structure and the above insulating sidewall spacer to form highly doped drain and source area; removing the above photoresist; on highly doped drain/source of the above P well area growing one thick fourth insulator, and growing one thin fourth insulator on highly doped drain/source of the above N well area which is not covered by the above polysilicon gate structure; removing thin fourth insulator of the above N well area to leave some thick fourth insulator on highly doped drain/source of the above P well area; depositing one BPSG on thick fourth insulator above highly doped drain/source of the above P well and on highly doped drain/source of the above N well; by rapid thermal processing forming highly doped drain/source on the above N well area which is not covered by the above polysilicon gate structure; removing the above BPSG and thick fourth insulator covering on highly doped drain/source of the above P well area; depositing fifth insulator on the above P well and N well; depositing one photoresist covering the above fifth insulator, which has one wider via forming initial state right on the highly doped drain/source of the above P well and N well; on the above fifth insulator using wide via on the above photoresist to remove top part of the above fifth insulator by anisotropic dry etch, in which a portion of via enters the above fifth insulator; removing the above photoresist; depositing one photoresist to cover the above fifth insulator, in which the photoresist has one narrower via right on the highly dopeddrain/source of the above P well and N well to expose the above wide via of the above fifth insulator to form second state; on the above fifth insulator using narrow via on the above photoresist to implement highly doped drain/source contact window with P well and N well by anisotropic dry etch, in which the contact window has narrower bottom and wider top; removing the above photoresist; depositing one metallization and implementing metal structure.