baber/WOPTO huggingface dataset:
Patent TW-200730702-A (TW)
Title: Construction method of partition or decoration
Inventor: CHANG LIANN-BE
IPC: E04B2/74
Filed: 2006-02-08
Abstract: The present invention provides a construction method of partition or decoration that can lower electromagnetic radiation. Slot racks are installed at two sides of each wall in an interior space, and a plurality of upright columns with various shapes are fixed between the slot racks. Then electromagnetic gas tight partitions or decoration sheets are fixed between the slot racks and the upright columns with various shapes. With the electromagnetic gas tight galvanized partitions or decoration sheets, an electric closed circuit is formed between the slot racks and the upright columns with various shapes. With respect to the wavelength of the electromagnetic wave to be shielded, the diameter of the electromagnetic hole of the partitions or the decoration sheets is smaller than a quarter of the wavelength in all directions; and lining sheets with various shapes are used to allow the width and the length of the jointing seam of the electromagnetic gas tight partitions or decoration sheets of the space , with respect to the wavelength of the electromagnetic wave to be shielded , smaller than a quarter of the wavelength in the width and smaller than two times of the wavelength in the length. Thus, the construction method of partition or decoration that can lower electromagnetic radiation is provided.
Patent TW-200710925-A (TW)
Title: Method for optimising transistor performance in integrated circuits
Inventor: HUGHES PETER WILLIAM
IPC: H01L21/00
Filed: 2006-02-17
Abstract: A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.
Patent TW-200732657-A (TW)
Title: Cantilever resistive humidity detection structure and method for manufacturing the same
Inventor: CHEN JUNG-TAI
IPC: G01N27/12
Filed: 2006-02-24
Abstract: The present invention provides a cantilever resistive humidity detection structure and a method for manufacturing the same. The invented structure includes: a substrate providing a first surface and a second surface, in which the first surface and the second surface of the substrate are formed with a first oxide layer and a second oxide layer by an oxidation process. The first oxide layer of the substrate is sequentially formed with a resistance sensing layer and a humidity sensing layer. Furthermore, the substrate is formed with an opening penetrating the first oxide layer and the second oxide layer. A cantilever is retained in the opening so that the cantilever of the substrate has a humidity sensing layer and a resistance sensing layer. As a result, the humidity sensing layer changes its volume due to a change in humidity so that the resistance sensing layer produces deformation to be used for the detection of environmental humidity.
Patent TW-200703958-A (TW)
Title: Power control and quality of service(QoS) implementation in a communication system
Inventor: MESE MURAT
IPC: H04B7/005
Filed: 2006-03-03
Abstract: For Quality of Service (QoS) implementation in a multiple-access communication system, a base station processes data transmissions from terminals for all QoS classes supported by the system and obtains status information for the data transmissions. The status information may indicate whether each packet is decoded correctly or in error and the delay for each packet. For each QoS class, the base station derives one or more metrics based on the status information for data transmissions from disadvantaged terminals and updates the QoS parameter based on the metrics and requirements for the QoS class. The QoS parameter for each QoS class determines the transmit powers for the data transmissions sent for that QoS class. The base station broadcasts the QoS parameters for all QoS classes. Each terminal uses the QoS parameter for an applicable QoS class for power control of the data transmission sent to the base station.
Patent TW-200711043-A (TW)
Title: Method of forming an electronic device
Inventor: LIM SANG-WOO
IPC: H01L21/70
Filed: 2006-03-07
Abstract: A method of forming an electronic device (100) includes etching a portion of a first gate dielectric layer (104) to reduce a thickness of the gate dielectric layer (304) within that portion. In one embodiment, portions not being etched may be covered by mask (206). In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer (402) may be formed over the first gate dielectric layer (104, 504, 304) after etching the portion. The second gate dielectric layer (402) can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer (104, 504, 304). Subsequent gate electrode (606) and source/drain region (802) formation can be performed to form a transistor structure (20, 22, 24).
Patent TW-200734906-A (TW)
Title: Keyboard
Inventor: WONG SHIH-FANG
IPC: G05D27/02
Filed: 2006-03-10
Abstract: A keyboard can detect its present ambient signal automatically by real-time sampling and processing. After an analog/digital conversion, the present analog ambient signal converts to digital ambient signal. An ambient process module compares the digitalized ambient signal with the ideal ambient signal stored in a storage unit. The adjustment device reacts to adjust the ambient reference to an ideal ambient state if the present ambient signal is out of the range of the ideal ambient signal. The ambient process module can shut down the function of the adjustment device if the present ambient signal falls in the range of the ideal ambient signal while the adjustment device is under an operational state. By the real-time detecting and adjustment, the keyboard is always under a comfortable operation state.
Patent TW-200704326-A (TW)
Title: Multilayer wiring structure and method of manufacturing the same
Inventor: MURAKAMI AKISHIGE
IPC: H05K3/46
Filed: 2006-03-13
Abstract: A method of manufacturing a multilayer wiring structure is disclosed. The method comprises a step of forming a via post on a first metal wiring element, a step of printing an interlayer insulation film on the first metal wiring element, with use of a screen mask having a non-ejection area slightly larger than a head of the via post, such that the interlayer insulation film has an upper surface at the level lower than the head of the via post, while generally aligning the non-ejection area with the head of the via post, a step of curing the interlayer insulation film, and a step of forming a second metal wiring element in contact with the via post on the interlayer insulation film such that the first metal wiring element and the second metal wiring element are connected through the via post.
Patent TW-200737446-A (TW)
Title: Package structure
Inventor: HUANG CHENG-WEI
IPC: H01L23/31
Filed: 2006-03-24
Abstract: A package structure is disclosed herein. The package structure comprises a first substrate and a second substrate. A first seal ring having a first height is disposed around a predetermined area of the first substrate, and between the first substrate and the second substrate. A second seal ring having a second height is disposed around the outside of the first seal ring, and on the first substrate. A sealant is provided between the first seal ring and the second seal ring to seal up the package structure.
Patent TW-200701277-A (TW)
Title: Multilayer capacitor
Inventor: TOGASHI MASAAKI
IPC: H01G4/30
Filed: 2006-03-24
Abstract: To provide a multilayer capacitor in which equivalent series resistance can be increased. A lamination 1 is constituted by laminating a plurality of dielectric layers 11-22 and first and second internal electrodes 31-34 and 31-34 alternately. The first internal electrodes 31-34 are interconnected electrically through a first connection conductor 7. The first internal electrode 31 is connected electrically with a first terminal electrode 3 through a lead-out conductor 37. The second internal electrodes 41-44 are interconnected electrically through a second connection conductor 9. The second internal electrode 44 is connected electrically with a second terminal electrode 5 through a lead-out conductor 47. The first internal electrode 31 and the second internal electrodes 44 are arranged symmetrically to the central position M of the lamination 1 in the laminating direction.
Patent TW-200643067-A (TW)
Title: Surface modifier
Inventor: ITAMI YASUO
IPC: G02B1/11
Filed: 2006-03-31
Abstract: A surface modifier comprising an organosilicone compound represented by General Formula (A) and/or General Formula (B): wherein q is an integer from 1 to 3; m, n, and o are independently integers from 0 to 200; p is 1 or 2; X is O or a bivalent organic group; r is an integer from 2 to 20; R1 is a C1-22 linear or branched hydrocarbon group; a is an integer from 0 to 2; and X' is hydrolysable group; and, , wherein q is an integer from 1 to 3; m, n, and o are independently integers from 0 to 200; p is 1 or 2; X is O or a bivalent organic group; r is an integer from 2 to 20; R1 is a C1-22 linear or branched hydrocarbon group; a is an integer from 0 to 2; X' is hydrolysable group; and z is an integer from 0 to 10 when a is 0 or 1.
Patent TW-200723445-A (TW)
Title: Technique for forming interconnect structures with reduced electro and stress migration and/or resistivity
Inventor: BUCHHOLTZ WOLFGANG
IPC: H01L21/768
Filed: 2006-03-31
Abstract: By improving the purity of metal lines and the crystalline structure, tile overall performance of metal lines, especially of highly scaled copper-based semiconductor devices, may be enhanced. The modification of the crystalline structure of the metal lines may be performed by a heat treatment generating locally restricted heating zones, which are scanned along the length direction of the metal lines, and/or a heat treatment comprising a heating step in a vacuum ambient followed by a heating step in a reducing ambient.
Patent TW-200738431-A (TW)
Title: Injection flow diverging device of hot runner
Inventor: Zhang zhen-han
IPC: B29C45/17
Filed: 2006-04-11
Abstract: An injection flow diverging device of hot runner comprises an injection device, a male mold and a female mold. The injection device comprises a hot feed plate, a heater and plural injection nozzles. The hot feed plate is provided with a sprue, which extends to a designed runner. Below the hot feed plate there are plural runner openings at the terminal of the runner, and heaters are disposed on the upper and lower sides of the hot feed plate. A diverging plate is disposed below the hot feed plate. The diverging passage is provided inside the diverging plate; the upper diverging opening of the diverging passage corresponds to runner opening of the hot feed plate and the lower diverging opening is disposed with plural injection nozzles. By the installation of a diverging plate between the hot feed plate and injection nozzle for the adjustment of feeding position, re-making of hot feed plate in the case of changing design of plastic parts can be avoided to achieve the purpose of saving the cost of hot feed plate.
Patent TW-200739453-A (TW)
Title: Method for processing colors and method for converting images using the same
Inventor: Zhang wen-wu
IPC: G06T9/00
Filed: 2006-04-12
Abstract: A method for processing color images is provided. Firstly, the method performs an ungroup procedure and according to a plurality of color pixel values to distribute a plurality of pixels to a first predetermined group. Then, according to the frequency of the use of each color pixel within each group to select the first predetermined candidate color. Secondly, selecting a second predetermined candidate color as representative color from the first predetermined candidate color for a color palette, wherein the second predetermined number of candidate color is less than the first predetermined number. Finally, performing index procedure which according to a color similarity between the color value of each pixel and the candidate color of the color palette, and converting the color value of the pixel as a selected candidate color. The index procedure is repeated until the system can convert the plurality of color pixels to one of the candidate colors in the color palette.
Patent TW-200640046-A (TW)
Title: LED illumination lamp
Inventor: KANAMORI MASAYOSHI
IPC: F21W107/10
Filed: 2006-04-12
Abstract: The present invention provides an LED illumination lamp which is configured with a polygonal column shaped supporting member having a plurality of rectangular side surfaces, a plate shaped wing member extending from each ridge formed in between two neighboring rectangular side surfaces of the supporting member, the wing member having at least two back-to-back rectangular surfaces abutting each other, and a plurality of LED elements disposed on the rectangular side surfaces of the supporting member and the rectangular surfaces of the wing member. The LED lamp thus configured ensures a sufficient brightness of illumination while maintaining a compactness of the entire shape of the supporting member.
Patent TW-200706253-A (TW)
Title: Shower plate and method for manufacturing the same
Inventor: OKESAKU MASAHIRO
IPC: B05B7/14
Filed: 2006-04-17
Abstract: A compatible shower plate of constant quality in which a process gas blow-out hole has a simple structure and can be machined easily, the blow-out hole has dimensions of high precision and uneven blow-out of process gas and generation of particles are eliminated. Ceramic material-use powder of low dielectric constant is press-formed into disc-shape having overall dimensions where sintering shrinkage and finish allowance are taken into account. In the stage of disc-like molding, a molding hole for a gas introduction passage (3) and the blow-out hole (2) is bored before sintering. Subsequently, the gas introduction passage (3) and the blow-out hole body portion (2b) are polished to provide surface roughness within 1s. A lapping wire having a tapered distal end is then inserted into an ejection opening (2a) and slid sequentially to the side of larger wire diameter while reciprocating it. Finishing work is performed to attain dimensional accuracy within +-0.002 mm and surface roughness within 1s when the diameter is in the range of 0.1-0.3 mm.
Patent TW-200714400-A (TW)
Title: Non-copper-plated welding wire
Inventor: SHIMIZU HIROYUKI
IPC: B23K35/365
Filed: 2006-04-28
Abstract: Disclosed herein is a non-copper-plated welding wire which permits CO2 gas shield arc welding under the condition that the average current is 150 to 170 A, the tip has a current supply length of 2 to 4 mm, the distance between the tip and the parent material is 20 'to 24 mm, and the free loop due to wire winding has a diameter of 750 mm, such that there is a probability higher than 70% of the voltage drop exceeding 0.41 V between said welding wire and the tip under the condition that the average current is 140 to 180 A, and which carries 0.25 to 1.5 g of oil per 10 kg thereof on the surface thereof, said oil being at least one species selected from vegetable oil, animal oil, mineral oil, and synthetic oil. The welding wire undergoes stable melting at the sliding contact point between it and the tip at the time of welding and is free from sudden solidification that otherwise occurs at the sliding contact point at the time of continuous welding. The welding wire excels in wire feedability and arc stability. It is also superior in welding workability with a minimum of spatter and fume.
Patent TW-200704252-A (TW)
Title: Method and system for preventing high speed downlink packet access transmission loss
Inventor: CASTOR DOUGLAS R
IPC: H04W72/12
Filed: 2006-05-02
Abstract: The present invention is related to a method and system for preventing high speed downlink packet access (HSDPA) transmission loss due to transmission gap in compressed mode in a wireless transmit/receive unit (WTRU). In accordance with one embodiment, a Node-B receives a compressed mode transmission gap schedule of a WTRU, identifies HSDPA transmission time intervals (TTIs) that are affected by the WTRU compressed mode transmission gap schedule and schedules the HSDPA transmissions not to overlap the WTRU compressed mode transmission gap schedule. In accordance with another embodiment, the Node-B may inform the HSDPA transmission schedule to a radio network controller (RNC) and the RNC coordinates the HSDPA transmission schedule and a compressed mode transmission gap schedule of the WTRU.
Patent TW-200743890-A (TW)
Title: Method for triggering strobe of image-capturing device
Inventor: YHE JEFF
IPC: G03B15/05
Filed: 2006-05-30
Abstract: A method for triggering a strobe of an image-capturing device is disclosed. The method uses a focusing parameter, which is generated during the focusing procedure of the image-capturing device, to estimate a shooting distance. Then, the method dynamically determines a trigger strength of the strobe according to the shooting distance, thereby obtaining improved exposure effect. In addition, since the preflash of the strobe is omitted, the method can save power and shorten the shooting time, thereby upgrading the performance of the image-capturing device and the strobe.
Patent TW-200803172-A (TW)
Title: Clock tree for programmable logic array devices
Inventor: WANG TAI-CHENG
IPC: H03K19/177
Filed: 2006-06-14
Abstract: A clock tree for PLAD is provided, with each logic element having an embedded circuit having a buffer connecting vertical bus wires to horizontal bus wires so that the clocks on each horizontal bus wire are synchronized, because the every horizontal wire gets the same capacitor and the same clock propagation gate delay,and the clock signals among the logic elements have the minimal clock skew.
Patent TW-200707653-A (TW)
Title: Two-sided surround access transistor for a 4.5F2 DRAM cell
Inventor: JUENGLING WERNER
IPC: H01L21/8242
Filed: 2006-06-23
Abstract: An isolation transistor having a grounded gate is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell.
Patent TW-200715495-A (TW)
Title: Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion
Inventor: ARANA LEONEL
IPC: H01L23/28
Filed: 2006-06-29
Abstract: A method, apparatus and system with an electrically conductive through hole via of a composite material with a matrix forming a continuous phase and embedded particles, with a different material property than the matrix, forming a dispersed phase, the resulting composite material having a different material property than the matrix.
Patent TW-200713264-A (TW)
Title: Program/erase waveshaping control to increase data retention of a memory cell
Inventor: FANG TZU-NING
IPC: G11C11/21
Filed: 2006-07-24
Abstract: System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell is detected and a lower input pulse is sent to the memory cell. Application of the lower pulse controls the data retention of the memory cell without disturbing the final programming state of the memory cell.
Patent TW-200740775-A (TW)
Title: Macrocylic inhibitors of hepatitis C virus
Inventor: RABOISSON PIERRE JEAN-MARIE
IPC: A61P31/14
Filed: 2006-07-28
Abstract: Inhibitors of HCV of formula (I), and the N-oxides, salts, or stereoisomers thereof, wherein each dashed line (represented by -----) represents an optional double bond; X is N, CH and where X bears a double bond it is C; R1 is -OR6, -NH-SO2R7; R2 is hydrogen, and where X is C or CH, R2 may also be C1-6 alkyl; R3 is hydrogen, C1-6alkyl, C1-6alkoxyC1-6alkyl, or C3-7 cycloalkyl; n is 3, 4, 5, or 6; R4 and R5 independently from one another are hydrogen, halo, hydroxy, nitro, cyano, carboxyl, C1-6 alkyl, C1-6alkoxy, C1-6alkoxyC1-6alkyl, C1- 6alkylcarbonyl, C1-6alkoxy-carbonyl, amino, azido, mercapto, C1-6alkylthio, polyhaloC1-6alkyl, aryl or Het; W is aryl or Het; R6 is hydrogen; aryl; Het; C3-7cycloclkyl optionally substituted with C1-6alkyl; or C1-6alkyl optionally substituted with C3-7cycloalkyl, aryl or with Het; R7 is aryl; Het; C3-7cycloalkyl optionally substituted with C1-6alkyl; or C1-6alkyl optionally substituted with C3-7cycloalkyl, aryl or with Het; aryl is phenyl or naphthyl, each optionally substituted with1-3 substituents; Het is a 5 or 6 membered saturated, partially unsaturated or completely unsaturated heterocyclic ring containing 1-4 heteroatoms each independently selected from N, O or S, and optionally substituted with 1-3 substituents; pharmaceutical compositions containing compounds (I) and processes for preparing compounds (I). Bioavailable combinations of the inhibitors of HCV of formula (I) with ritonavir are also provided.
Patent TW-200721097-A (TW)
Title: Semiconductor device, display device and electronic device equipped with the semiconductor device
Inventor: KIMURA HAJIME
IPC: G09G3/30
Filed: 2006-08-02
Abstract: The present invention provides a semiconductor device which can prevent a current from flowing into a display element at a signal writing operation, without increasing power consumption and without changing a potential of a power supply for supplying a current to a load in each row. When a predetermined current is supplied to a transistor to set a gate-source voltage of the transistor, a potential of a gate terminal of the transistor is adjusted so as to prevent a current from flowing into a load which is connected to a source terminal of the transistor. Thus, a potential of a wire connected to the gate terminal of the transistor is made different from that of a wire connected to a drain terminal of the transistor. At that time, an operation of a transistor is shifted so as to allow a large amount of current to flow, and influences by intersection capacitance parasitic to a wire or the like or wire resistance are hardly caused, and a set operation is conducted quickly.
Patent TW-200718112-A (TW)
Title: Wireless communication device with physical-layer reconfigurable processing engines
Inventor: CHAPYZHENKA ALIAKSEI
IPC: H04W8/24
Filed: 2006-08-21
Abstract: Embodiments of a system and method for signal processing in a wireless communication device are generally described herein. Other embodiments may be described and claimed. In some embodiments, the wireless communication device may include two or more reconfigurable processing engines that may be reconfigured to perform various baseband processing operations and decoding operations.
Patent TW-200812105-A (TW)
Title: Vertical conductive GaN LED structure and the method for manufacturing
Inventor: WANG CHIEN-JEN
IPC: H01L33/00
Filed: 2006-08-21
Abstract: Disclosed is a vertical conductive GaN light emitting diode (LED) structure and the method for manufacturing. The vertical conductive GaN light emitting diode includes a plurality of layers. The multi-layer structure includes a metal conductive layer. The metal conductive layer improves the performance of LED, and provides a protect material on the side wall of LED. The invention uses laser dicing to dice the wafer into single vertical conductive GaN LED, and avoids damaging the property of GaN LED.