Patent GB-1121183-A (GB)
Title: Pulse analysing apparatus
IPC: G06V30/224
Filed: 1966-01-11
Abstract: 1,121,183. Character recognition. INTER. NATIONAL BUSINESS MACHINES CORP. 11 Jan., 1966 [14 Jan., 1965], No. 1159/66. Heading G4R. In pulse analysing apparatus, representations of whether or not a discrete pulse occurs in each of a plurality of successive time zones are gated to storage means under control of the pulses, a clock-fed accumulator being reset at the end of each pulse with the contents of a counter to which further clock pulses were fed during the duration of the pulse. Characters to be recognized are printed in magnetic ink in a fount in which the amount of ink detected in a single horizontal scan across the character undergoes marked changes at (selected) boundaries of a number of vertical zones into which the character can be considered to be divided. During such a scan, a quantizer responds to positive and negative transitions by producing bit pulses on corresponding lines (12, 94, Fig. 2d, not shown). A clock pulse generator (19) produces "full-rate" clock pulses (48 per zone width) and drives a half-rate generator (20) to produce " half-rate " clock pulses. Response to representative zones of a representative character will now be described. A normal width bit pulse (half the zone width) on the positive line (12) in the first zone gates (21) half-rate clock pulses to a width counter (22) as long as it is present. When a count of three is reached, the width counter (22) sets a minimum width latch (25) via an AND gate (23) and as this has been done when the input pulse (on line 12) ends, the count in the width counter (22) is set into an accumulator (52), a " one " is stored in the first (left hand) stage of a plus register (14), the plus register (14) and a minus register (57) are shifted one place to the right, and a zone counter (58) is incremented by one. The minimum width latch (25) and the width counter (22) are reset. If a normal width bit pulse had occurred on the negative line (94) instead of the positive line (12), the sequence of operations would have been the same except that a " one " would have been stored in the minus register (57), not the plus register (14). The accumulator (52) is driven by (counts) full-rate clock pulses, normally being reset to 24 on reaching a count of 72, but can be set to other values, e.g. it was set to 12 by the width counter (22) in the description above. During the second zone, in which it is assumed that no bit pulse occurs, the accumulator (52) on reaching a count of 72 causes itself to be reset to 24 and enables an AND gate (32) to respond to the (stored) absence of a bit pulse to store " zero " in the first stage of both the plug and minus registers (14, 57), shift these one place, and increment the zone counter (58). In the third zone, a double width positive bit pulse (equal to the zone width) is assumed to occur. When the accumulator (52) reaches 72 it is reset to 24. When the bit pulse ends, the count in the width counter (22) viz. 24 for the double width bit pulse, is set into the accumulator (52), the width counter (22) is reset to zero, a " one " is stored in the plus register (14), the plus and minus registers (14, 57) are shifted and the zone counter (58) is incremented. In the sixth zone a positive bit pulse of nearly double width starts, extending slightly into the seventh zone. The bit pulse gates half-rate clock pulses to the width counter (22) as usual. When the accumulator (52) reaches 72, it is reset to 24 and the fact that the bit pulse is still occurring at this time causes subsequently detected (62) equality between the contents of the width counter (22) and accumulator (52) to set a zero store latch (70). When the bit pulse ends, the contents of the width counter (22) are set into the accumulator (52), and an AND gate (71) is caused to respond to the set state of the zero store latch (70) to store a " zero " in the plus and minus registers (14, 57), shift these, and increment the zone counter (58). The width counter (22) is reset to zero, and since inter alia the minimum width latch (25) is set, a " one " is inserted into the first stage of the plus register (14), the plus and minus registers (14, 57) are shifted and the zone counter (58) is incremented. The zero store and minimum width latches (70, 25) are reset. The double insertion in the plus register (14) in zones 6-7 occurred instead of the single insertion of zone 3, for example, because the accumulator reset occurred prior to the mid-point of the bit pulse rather than after it as in zone 3. During operation, bit latches (77-81, Fig. 2e, not shown) are selectively set under control of the zone counter (58), the plus and minus registers (14, 57), a 24-count signal from the width counter (22), and a negative bit signal if present, the presence of the 24-count signal being necessary in all oases. When a bit latch is set, the width counter (22) is reset to 16, and the zero store latch (70) is reset preventing a second insertion of the type described above for zone 6. When the first " one " entered into the plus register (14) reaches the last stage thereof, character recognition gates (Figs. 4a-4c, not shown) fed by the plus and minus registers (14, 57) and the bit latches (77-81) are enabled to indicate the character.