Patent GB-1144328-A (GB)
Title: Solid-state circuit consisting of a semiconductor body with active components, passive components, and conducting paths
IPC: H01L21/762
Filed: 1966-05-04
Abstract: 1,144,328. Semi-conductor devices. TELEFUNKEN PATENTVERWERTUNGS G.m.b.H. 4 May, 1966 [7 May, 1965], No. 19762/66. Heading H1K. A solid-state circuit comprises a wafer in which are provided active components and "leadthroughs" which interconnect arrangements of passive components and/or conductive tracks applied to insulating coatings on both major faces of the wafer. As shown. Fig. 1, a monocrystalline semiconductor wafer 1 is provided with an insulating layer 2, which may be an oxide layer, and a temporary support layer 3 of polycrystalline material. The wafer is then etched using a double masking process to form region 4 and a plurality of lead-through regions 5. The surfaces of regions 4 and 5 are provided with low resistivity layers 6 either by diffusing-in an impurity of the same type as the regions or by depositing a metal layer which may be alloyed to the semi-conductor. Insulating layers 7 are then provided and a substrate 8 of polycrystalline semi-conductor material is deposited, bevelled by mechanical grinding and reduced to the broken line in Fig. lb to expose the ends of regions 5. An insulating layer 9 is provided on the lower face of the resulting wafer and the temporary support layer 3 is removed. A transistor 10 is formed in region 4 and during the emitter diffusion low resistivity layers 1.2  may be formed in regions 5. A collector resistor 13 is applied to the lower face of the wafer and connected to the collector contact of transistor 10 by conductive tracks 14, 15 which are interconnected by lead-through region 5, ohmic contacts 11 being provided by alloying. In a modification, Fig. 2 (not shown), the lead-through regions (16) have the same height as the active device region (4) and the polycrystalline layer (8) is levelled and then selectively etched to form pits which expose the lower ends of the lead-through regions (16). In a second modification, Fig. 3 (not shown), the lead-through region is replaced by an annular region (18) and the polycrystalline material is heavily doped, the portion (19) of the polycrystalline substrate (8) lying inside the annular region (18) being utilized as the lead-through. This modification may also be applied to the embodiment of Fig. 2. In a further modification, Fig. 4 (not shown), the lead-through regions are removed by selective etching after applying the polycrystalline substrate (8) to form apertures through the wafer on the walls of which conductive interconnections may be provided. Apertures may also be directly etched in a wafer, the walls being covered with insulating material before applying the conductive tracks. Instead of the "top support" method the circuit can be fabricated by forming mesas in a monocrystalline wafer, covering these with the insulating layer and polycrystalline substrate which is levelled, and then removing material from the top of the original wafer until isolated monocrystalline regions are produced. The semi-conductor starting wafer may comprise an epitaxial layer on a high conductivity substrate in which case the diffusion to produce low resistivity layer 6 may be omitted.