Patent GB-1452581-A (GB)
Title: Multiplexer/demultiplexer apparatus
IPC: H04J3/00
Filed: 1974-06-20
Abstract: 1452581 Electric multiplexing/demultiplexing WESTERN ELECTRIC CO Inc 20 June 1974 [26 June 1973] 27354/74 Heading H4M In a combined multiplexer-demultiplexer for exchanging data signals between a time division highway and a plurality of lines signals from the highway are received by a highway register during one multiplex frame while simultaneously data signals received from line registers during the preceding frame are transmitted by the highway register to the highway. The line regiters receive data signals from the lines during the frame and simultaneously transmit over the lines data signals received from the highway register during the preceding frame. Data signals are interchanged between the line registers and highway register during a period at the end of a frame which is not used for data. The multiplex frame contains 193 bits, allowing room for 24 8 bits bytes with an additional bit for synchronizing &c. 23 bytes are used for data, the last one (bits 185-192) is used for control purposes. The multiplexer/demultiplexer (Fig. 1) contains 6 sections 101-106, to each of which the input received from the time division highway at terminal 114 can be applied, via gates 107-112 respectively, and each of which can apply an output to the highway terminal 115 via gate 113. The inputs and outputs to the individual lines L1-L23 are associated in groups of four (in one case 3) with the sections. Each section operates in sequence through the multiplex frame under the control of appropriate clock and timing waveforms produced by circuit 100 (explained in detail with respect to Fig. 5, not shown). Each section, e.g. 101 contains four highway register portions 20, 40, 60, 80 (Fig. 3) and four line register portions 10, 30, 50, 70. Each such portion consists of an 8 stage shift register. At the appropriate time during the multiplex frame, the input gate 107 to the section is opened, and 8 bit data bytes enter the register 89. The output of this is applied to the register 60 and so on to 40 and 20, so that as four data bytes are progressively applied to the section, the first passes through to register 20, the second to 40 and so on. Meanwhile the data stored in the highway registers as a result of operations during the proceeding multiplex frame is driven out on to the highway from the Q output of register 20 via gates 334 and 113. At the end of the four byte period, the gates are changed such that the four data bytes continuously circulate through the registers for the period of the TDM frame up to the end of byte 23. Meanwhile, at intervals throughout the multiplex frame the input lines L1-L4 are periodically sampled and the samples entered into shift registers 10, 30, 50, 70 respectively. Their existing contents are progressively driven out to the lines via line flip-flops 15, 35, 55, 75. During the 24th byte of the multiplex frame, the gates and timing signals in the sytem are so operated that each line register, e.g. 10 is driven out into an adjacent highway register, e.g. 20, via gate 306 while the contents of the highway register are driven out to another line register (e.g. highway register 30 is driven into line register 70 via gate 328). Thus the contents of highway and shift registers are interchanged and during the following frame, the data originally in the line registers will proceed on to the highway in an appropriate time slot, while data bytes from the highway will be passed to corresponding lines.