Patent GB-1261447-A (GB)
Title: Multiplex transmission system
IPC: H04J3/06
Filed: 1969-02-20
Abstract: 1,261,447. Multiplex pulse code signalling. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 20 Feb., 1969 [23 Feb., 1968], No. 9176/69. Heading H4L. In a time division multiplex delta modulation transmission system, the frame synchronizing signal is a repetitive pseudo-random pulse pattern of a sequence not occurring normally in the signal channels and the receiver includes a synchronization detector which converts the received sync. signal into a series of equidistant pulses which are integrated to control via a threshold device a resetting circuit for the channel distributer. Transmitter.-As described, the system comprises fifteen speech channels C1 to C15, Fig. 1, and a synchronization channel C16, the speech signals being supplied via delta modulators 3, 4 etc. to a channel distributer 6 together with the frame sync. signals derived from a pulse pattern generator 37. The distributer is controlled by a clock pulse generator 10, counter 9 and a plurality of AND-gates 16 controlled in the appropriate sequence to supply the signals to the transmission path 11. The pulse pattern generator 37 comprises a feedback shift register 38 controlled by channel clock pulses from the counter 9, modulo-2-adders 44, 45 and a source of constant signal value 46 which is connected to the input of the shift register. The resulting pseudorandom pulse sequence is supplied via an INHIBIT gate 47 to the distributer 6. Should faulty operation of the generator 37 cause a continuous series of pulses to be generated, an AND gate 48 provides an output to inhibit the gate 47 and block the sync. signal. Receiver.-The received signal is supplied to a pulse regenerator 12 and to a clock frequency extractor 13 comprising a limiter 14, differentiator 15, full-wave rectifier 16 and phase discriminator 17. A local clock pulse generator 18 supplies a second signal to the phase discriminator, and also controls the pulse regenerator 12, the output of the phase discriminator being smoothed at 19 and supplied to a frequency corrector 20 controlling the generator 18. The output of the regenerator 12 is supplied to a channel distributer 21 controlled by the generator 18 via a counter 24 which counts up to sixteen. The speech channels include digital-toanalogue converters in the form of integrators 28, 29 etc., which via filters 30, 31 supply signals to the users 32, 33 etc. In the frame sync. channel C16 the pulses are regenerated at 27 and supplied to a synchronism detector 34 which controls a setting circuit 35 for the distributer 21 which when the system is synchronized is blocked so that the local clock pulses can pass via gate 36 to the distributer 21. In the synchronism detector 34, a pulse pattern converter 49 converts the received sync. pulse pattern to a series of equidistant pulses which are integrated at 51 and supplied to a threshold device 52, so that a gate 54 is inhibited only when the correct sync. signal is received to overcome the threshold value of device 52. A test pulse generator 53 in the form of a counter supplies a pulse having a duration equal to that of a local clock pulse after receiving a predetermined number of channel pulses, the test pulses having a repetition period which is larger than the time taken for a signal starting at zero in the integrator 51 to reach the threshold value of device 52. When the system is not synchronized the test pulses are supplied via gate 54 to reset a bi-stable 55 which has been set by the local clock pulses so that the distributer 21 is not switched to the next position. The local clock pulse immediately following the test pulse sets the bi-stable 55 again so that the distributer operates under the control of the local clock pulses until the next test pulse is passed by the gate 54. This cycle is repeated until the system is synchronized and the gate 54 is blocked. Pulse pattern converter details.-The converter 49, Fig. 3, comprises shift register 56 connected in an inverse manner to the pulse pattern generator 37 at the transmitter, the contents of the shift register being shifted with a shift period D under the control of pulses from the counter 24 so that a series of equidistant pulses is supplied via gate 64. Besides the sync. pulse pattern, an uninterrupted pulse series would provide a similar output signal and if this should occur an AND gate 65 provides a signal to inhibit the gate 64. The output of gate 64 is supplied via an interference suppression circuit 66 to an integration circuit 50, the pulses being supplied via an AND gate 68, which converts them to pulses of width D/2, and INHIBIT gate 69 to a counter 67 which is reset by the test pulses from counter 53. In this case the threshold value is the final position of counter 67 in which a signal is supplied to inhibit the gate 54 and block the setting circuit 35. Interference suppression.-If a single interference pulse should appear in the sync. pulse pattern while the system is synchronized it will occur three times at the output of circuit 49 with delay times of zero, 2D and 5D due to the three separate paths it can follow, and each of these pulses would result in the substitution of 0 for 1 in the pulse train supplied to the integrator 50. To prevent this, a circuit 66 is provided which comprises a shift register 70 with modulo-2- adders 77, 78, 79, inverters 80, 81, 82 and AND gate 83 connected as shown. When an interference pulse, i.e. a 0 appears at the output of gate 64 it will be registered as 011010 in the shift register 70 so that an output appears at AND gate 83 which is shifted through the modulo-2- adders 77, 78, 79 by the next shift pulse into shift register elements 72, 75 and also appears at the output of the shift register. Thus the effect of interference pulses is reduced when the system is synchronized, but the correction circuit has no influence in the absence of synchronism. Modifications.-The circuit 66 may be replaced by an additional element and a gate in the shift register 49, Fig. 4 (not shown), the gate being controlled in accordance with the state of the output of integrator 50 to control a feedback circuit in the shift register 49. In a further arrangement, Fig. 5 (not shown), the receiver is provided with a sync. pulse pattern generator identical to that provided at the transmitter which is supplied to a comparator together with the received signal the resulting output controlling the local clock pulse generator. Fig. 6 (not shown) relates to a similar arrangement in which the control is of digital form. In a further arrangement, Fig. 7 (not shown), a shift register having a number of elements corresponding to the number of channel clock periods in the sync. pulse pattern has the outputs of the individual elements connected directly or inverted, in correspondence with the pulse pattern, to a common output resistor so that a series of equidistant pulses of a maximum value is only obtained in response to the reception in the shift register of the sync. pulse pattern in the correct phase.