baber/WOPTO huggingface dataset:
Patent TW-466684-B (TW)
Title: Method for forming deep trench capacitor under shallow trench isolation structure
Inventor: WU DE-YUAN
IPC: H01L21/8242
Filed: 2000-09-29
Granted: 2001-12-01
Abstract: There is provided a method for forming deep trench capacitor under shallow trench isolation structure. On a substrate, there are sequentially formed a pad oxide layer, a first mask layer, a second mask layer, and a photoresist layer. The photoresist layer has a thicker part and a thinner part. The thinner part is predefined to be formed with a shallow trench isolation structure. There is an opening between the thicker part and the thinner part for etching and forming a deep trench in the substrate. The photoresist layer and the second mask layer under the thinner part are removed to expose the first mask layer. The buried capacitor of the capacitor is formed on the bottom of the deep trench. An oxide collar layer is formed on the sidewall of the deep trench. A selective polysilicon layer is formed to fill up the deep trench, which has a height lower than the first mask layer but higher than the surface of the substrate. By using the self-alignment feature, the selective polysilicon layer and the substrate are etched to from a self-aligned shallow trench opening, thereby completing the shallow trench isolation structure.
Patent TW-454275-B (TW)
Title: Diode metal substrate package attached with substrate enhancement plate
Inventor: WU JIAN-CHANG
IPC: H01L21/56
Filed: 2000-10-16
Granted: 2001-09-11
Abstract: The present invention adheres a substrate enhancement plate between a first metal substrate and a second metal substrate of a diode in a bridge configuration, thereby enhancing the rigidity between the first metal substrate and the second metal substrate, and further enhancing the rigidity and reliability of the whole package.
Patent TW-486671-B (TW)
Title: Method of an universal calculator core program which is expandable
Inventor: CHEN HUAI-YAN
IPC: G06F9/44
Filed: 2000-10-25
Granted: 2002-05-11
Abstract: The present invention is a method of a universal calculator core program which is expandable, wherein a core program processing module is established on the application program of the calculator, and the related information such as the common operation number, operand and error message, etc. used in various models of calculator (such as commercial, engineering or scientifi, etc.) is installed in a core component, so that the required operation number, operand and error message in the practical computation can be used to merge into the core program processing module for computation through the corresponding function in the core program processing module (e.g. operation number function, operand function and error message handling function, etc.) according to the command inputted from the input device by the users when the application program of the calculator is used, and output the computational result to the output device, thus, when the designer/manufacturer intends to modify or expand the type of the calculator, it only needs modify or expand the related data such as common operation number, operand and error message in the core component, and adjust the corresponding function in the core program processing module, the purpose of modifying the calculator version can be accomplished easily, and which is suitable for use in different platforms, it's not necessary to greatly modify the original program or insert lots of subroutine in the original program according to different types of calculator.
Patent TW-584669-B (TW)
Title: Method of making low magnetic permeability cobalt sputter targets
Inventor: SNOWMAN ALFRED
IPC: C23C14/34
Filed: 2001-02-20
Granted: 2004-04-21
Abstract: The present invention provides a high purity cobalt sputter target having a single phase h.c.p. structure and a magnetic permeability less than the intrinsic magnetic permeability of the material. Substantially pure cobalt is cast and slowly cooled, such as at a rate of 15 DEG C/min. or less, to form a cast target of single phase h.c.p. crystallographic structure. This cast target is hot worked at a temperature of at least about 1000 DEG C to impart a strain of about 65% or greater into the cobalt material, followed by a slow, controlled cooling to room temperature, such as at a rate of 15 DEG C/min. or less, to maintain the single phase h.c.p. crystallographic structure. The cooled target is then cold worked at substantially room temperature to impart a strain of about 5-20%. The sputter target of the present invention processed by this method has a magnetic permeability of less than about 9, grain sizes in the size range of about 70-160 mum and average grain size of about 130 mum.
Patent TW-I251478-B (TW)
Title: A hair braider and an auxiliary device thereof
Inventor: LEE MYUN-WOO
IPC: A45D1/00
Filed: 2001-02-02
Granted: 2006-03-21
Abstract: This invention relates to a hair braider and its auxiliary device, which are portable and braids three bunches of hair into a strand. The hair braider has a substantially figure '8'-configured cam track allowing three carriers to move along the cam track for a '8' track motion. Three carriers combined detachably with three grabbing members accommodating three bunches of hair therein travels along the cam track as a couple of rotors rotate in opposite direction. While three hair grabbing member held on the holders of the carriers conduct the figure '8' motion, three bunches of hair in three hair grabbing members are braided into one strand.
Patent TW-478132-B (TW)
Title: Self-aligned SOI structure and the lamination structure thereof
Inventor: LI CHIOU-DE
IPC: H01L23/522
Filed: 2001-02-05
Granted: 2002-03-01
Abstract: The present invention proposes a self-aligned SOI structure which comprises: an insulation layer, a semiconductor device located on the insulation layer, an interconnection layer having plural interconnects; plural bonding pads located on the interconnection layer, wherein the interconnection is used to connect the semiconductor device to the bonding pad; a passivation layer located on the bonding pad, which has plural alignment openings on it; plural contact pillars, each having one end embedded into the interconnection layer, and the other end penetrating through the insulating layer, wherein the position of contact pillar respectively corresponds to the alignment opening.
Patent TW-487740-B (TW)
Title: Method and device for the hot-dip coating of metal strip in particular steel strip
Inventor: BUENTEN ROLF
IPC: C23C2/24
Filed: 2001-03-20
Granted: 2002-05-21
Abstract: The invention relates to method and device for the hot-dip coating of metal strip (1), in particular, steel strip, whereby the metal length (1) is fed vertically through a container (3) for accommodating the molten coating metal (2) and a guide channel (4) in series. The coating metal (2) is retained by the effect of an electromagnetic force. There is provided a measuring means to adjust the position of the metal strip (1) in the guide channel (4) and/or the container (3) for the coating metal (2), whereby the metal strip (1) is stabilized in position and form, by hydrostatic or hydrodynamic forces perpendicular to the metal strip surface (1a), during the passage through the container (3) and/or guide channel (4).
Patent TW-513318-B (TW)
Title: Components for breathing circuit
Inventor: SMITH DANIEL JOHN
IPC: A61M16/00
Filed: 2001-05-07
Granted: 2002-12-11
Abstract: A breathing circuit component includes an inlet, an outlet and an enclosing wall. The enclosing wall defines a gases passageway between the inlet and the outlet. At least a region of the enclosing wall is formed from a breathable material that allows the passage of water vapour without allowing the passage of liquid water or respiratory gases. The breathing circuit component may be the expiratory limb of a breathing circuit.
Patent TW-486761-B (TW)
Title: Electroplating apparatus and electroplating method
Inventor: MATSUDA TETSUO
IPC: H01L21/288
Filed: 2001-05-22
Granted: 2002-05-11
Abstract: This invention provides an electroplating apparatus and an electroplating method. In an electroplating apparatus, an electrolytic agent is filled into the portion between an anode and a dummy cathode which is opposite substantially face to face and parallel to the anode, and an electric current is supplied to this portion, thereby suppressing changes in properties of a black film during the period in which plating to a substrate to be processed is stopped. In particular, by applying an electric current to the anode immediately before plating to the substrate is resumed, the film formation characteristics of plating to the substrate can be maximally stabilized. This can reduce the consumption power and dissolution of the anode. This apparatus is particularly effective in copper plating in which the formation of a black film is significant.
Patent TW-511081-B (TW)
Title: Integrated memory with memory-cells with magnetoresistive storage-effect
Inventor: HARTMANN UDO
IPC: H01L21/8246
Filed: 2001-06-19
Granted: 2002-11-21
Abstract: An integrated memory includes memory-cells (MC) with magnetoresistive storage-effect as well as column-lines (BLo to BLn) and row-lines (WLo to WLm). The memory-cells (MC) are connected respectively between one of the column-lines (BLo to BLn) and one of the row-lines (WLo to WLm). They are formed so that they are separable from respective column-line (BLo to BLn) and/or row-line (WLo to WLm) by means of a current through respective memory-cell (MC). Thus in the case of an existing defect memory-cell (MC12) a smaller repair-expense of the memory is possible.
Patent TW-516245-B (TW)
Title: Evaluation method of semiconductor wafer and its apparatus
Inventor: KOBAYASHI TAKESHI
IPC: G01N1/28
Filed: 2001-06-26
Granted: 2003-01-01
Abstract: The present invention discloses an evaluation method of a semiconductor wafer and its apparatus employ copper deposition method. Through copper concentration managed and evaluated, stable observation of defect is enabled, distribution and density of defects can be precisely analyzed, irregularity between apparatuses, between batches, etc., is restrained and stable estimation is enabled, furthermore, Cu standard solution is used, time for pretreatment can be shortened, and quick evaluation is enabled. A Cu deposition method, according to the invention, is constituted of a process for forming an insulating film having a prescribed thickness on a surface of a semiconductor wafer; and a process, in which the insulating film on a defect part position which is formed in the vicinity of the surface of the semiconductor wafer is destroyed, and copper in solvent is deposited in the defect part position. By using the Cu deposition method, copper concentration in the solvent is adjusted in a range of 0.4-30 ppm, and the evaluation is performed.
Patent TW-519673-B (TW)
Title: Plasma processing apparatus
Inventor: HIROSE EIJI
IPC: H05H1/46
Filed: 2001-07-17
Granted: 2003-02-01
Abstract: The present invention concerns a plasma processing apparatus for processing a processing object by applying two types of high-frequency power with different frequencies to generate plasma. A first high-frequency line is provided with a first filter circuit for attenuating a high-frequency current from a second high-frequency power supply. A second high-frequency line is provided with a second filter circuit for attenuating a high-frequency current from a first high-frequency power supply. The first filter circuit is provided with a variable capacitor for changing a circuit constant. For changing the circuit constant, the variable capacitor is varied so that a resonance point becomes greater than an optimum resonance point most attenuating a high frequency in the second high-frequency power supply. Doing so decreases a sputter rate of the generated plasma affected on a wall surface of the processing chamber.
Patent TW-498515-B (TW)
Title: Flip chip type semiconductor package piece with flash prevention structure and its manufacture method
Inventor: CHAI TING-KE
IPC: H01L23/28
Filed: 2001-08-01
Granted: 2002-08-11
Abstract: This invention provides a flip chip type semiconductor package piece and its manufacture method. A substrate is prepared having a chip attachment area on the top surface, in which the chip attachment area has at least one ventilation hole penetrating through. A circular resin dam is set up on the top surface of the substrate to surround the ventilation hole. A semiconductor chip is electrically connected onto the chip attachment area through a plural number of solder bumps and a sealing resin is formed on the substrate to encapsulate the semiconductor chip. Because the mold flow of the sealing resin is retarded by the circular resin dam surrounding the ventilation hole and thus the mold flow rate decreases, viscosity of the sealing resin increases by rapid heat absorption from package mold. This can prevent the occurrence of flash on the backside of the substrate and does not influence the attachment between solder bumps and the substrate.
Patent TW-I288847-B (TW)
Title: Reflection liquid crystal display, method for producing the same, and method for driving the same
Inventor: SUZUKI MASAYOSHI
IPC: G02F1/1335
Filed: 2001-08-27
Granted: 2007-10-21
Abstract: A reflection liquid crystal display is such that a transparent substrate is opposed to the first substrate with a liquid crystal layer placed therebetween, and the transparent substrate is disposed forward to the first substrate in the light-incident direction. A quarter-wavelength plate is disposed in the transparent substrate, and a polarization plate is disposed on the surface at the forward side thereof in the light-incident direction. And, a reflection layer besides acting as a color filter consisting of a cholesteric liquid crystal is disposed inside liquid crystal cells of the first substrate. In the case of a wide field-of-view angle, a scattering film is disposed forward to the polarization plate in the light-incident direction.
Patent TW-508638-B (TW)
Title: Method for producing micro-electromechanical component
Inventor: JANG DING-JANG
IPC: H01L21/00
Filed: 2001-09-12
Granted: 2002-11-01
Abstract: A method for producing a micro-electromechanical component comprises, after the production of a polysilicon frame, performing a selective metal tungsten chemical vapor phase deposition to form a tungsten surface film on the polysilicon frame; performing a nitridation process to react the tungsten surface film into a tungsten nitride surface film; and performing an thermal annealing process to densify the tungsten nitride surface film. Since the hardness of the tungsten nitride is higher than that of the polysilicon, the micro-electromechanical component has a higher wear resistance so as to prolong the operation life of the component.
Patent TW-I231416-B (TW)
Title: Heat sink module for notebook computer
Inventor: LAI CHIH-HSI
IPC: H05K7/20
Filed: 2001-09-27
Granted: 2005-04-21
Abstract: The present invention provides a heat sink module for a notebook computer, which is used to reduce the surface temperature on the chip in the notebook computer. The module comprises: a heat conduction structure configured inside the notebook computer and contacted with the chip for conducting heat from the chip; a fan configured inside the notebook computer and comprising the inlet and the outlet for causing air flowing; and, a heat sink configured at the fan and coupled with the heat conduction structure, and further including an outlet heat sink portion configured at the outlet; and, an inlet heat sink portion configured at the inlet.
Patent TW-497258-B (TW)
Title: NROM cell structure with dual-top oxide layer and method for producing the same
Inventor: LIOU JEN-CHIN
IPC: H01L27/115
Filed: 2001-10-05
Granted: 2002-08-01
Abstract: The present invention discloses a NROM cell structure with a dual-top oxide layer and a method for producing the same. The method uses a high temperature chemical vapor deposition oxidation (HTO) to deposit an oxide layer on an ONO structure used as floating gate in a NROM cell to be used as a passivation layer of the silicon nitride layer in the ONO structure, thereby effectively capturing electric charges in the silicon nitride layer and avoiding the electric charges in the silicon nitride layer from dissipating from the interface between the polysilicon layer and the silicon nitride layer, and enhancing the reliability of the memory.
Patent TW-535351-B (TW)
Title: Fan control device and method
Inventor: CHEN JIAN-RUNG
Filed: 2001-12-27
Granted: 2003-06-01
Abstract: The present invention relates to a fan control device and method for controlling the operation of a fan set comprising a separated first fan and second fan. The control device includes a control unit electrically connected to the fans and a temperature sensing unit electrically connected to the fan set and the control unit. With a temperature sensing step, the temperature sensing unit senses the temperatures of the driving motors of the fans. Based on the temperature of the driving motor of one fan, the control unit outputs a corresponding control signal to adjust the rotating speed of another fan, so that another fan can quickly increase the operating performance to continue a state of highly efficient heat dissipation when a fan is out of order.
Patent TW-567120-B (TW)
Title: Catalytic reactive pad for metal CMP
Inventor: GRUMBINE STEVEN K
IPC: B24B37/24
Filed: 2001-12-31
Granted: 2003-12-21
Abstract: A polishing pad including a polishing pad substrate and a catalyst having multiple oxidation states wherein the catalyst containing polishing pad is used in conjunction with an oxidizing agent to chemically mechanically polish metal features associated with integrated circuits and other electronic devices.
Patent TW-550900-B (TW)
Title: Data packet transmission method and network switch using same
Inventor: CHEN WEIPIN
IPC: H04L12/46
Filed: 2002-01-30
Granted: 2003-09-01
Abstract: A data packet transmission method and a network switch using this method are disclosed. The network switch includes a plurality of connecting ports, a tag replacement rule table, a multicasting table, a VLAN table and a tag-setting device. The method includes steps of receiving a data packet; realizing a multicasting port mask, a tag replacement rule and a tagging rule according to multicasting information of said data packet, said tag replacement rule table and said VLAN table; and outputting said data packet to a corresponding connecting port according to said multi-cast port mask, and optionally adding a VLAN tag to said data packet according to said tagging rule and said tag replacement rule.
Patent TW-544731-B (TW)
Title: Exhaust heat recovery system, exhaust heat recovery method and semiconductor manufacturing facility
Inventor: SUENAGA OSAMU
IPC: F24D3/02
Filed: 2002-02-20
Granted: 2003-08-01
Abstract: An exhaust heat recovery system, which can achieve energy saving of a semiconductor manufacturing facility, can be constructed by reusing heated cooling water discharged from a semiconductor manufacturing apparatus as a heat source. Supply low-temperature cooling water having a temperature substantially equal to a room temperature to a semiconductor manufacturing apparatus (2, 4, 6, 8, 10) via a low-temperature cooling water supply line (12). Supply medium-temperature cooling water discharged from the semiconductor manufacturing apparatus and having a temperature higher than a room temperature to the semiconductor manufacturing apparatus (8) via a medium-temperature cooling water supply line (30). Supply high-temperature cooling water discharged from the semiconductor manufacturing apparatuses (2, 4) and having a temperature further higher than the medium-temperature cooling water to the semiconductor manufacturing apparatuses (6, 10) via a high-temperature cooling water supply line (32).
Patent TW-556235-B (TW)
Title: Integrated toroidal coil inductors for IC devices
Inventor: ACOSTA RAUL E
IPC: H01F17/06
Filed: 2002-03-11
Granted: 2003-10-01
Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP. After planarization the fabrication of the remaining part of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil part of it may be built by electrodeposition through a mask on top of the BEOL layers.
Patent TW-536860-B (TW)
Title: Bandwidth enhanced self-injection locked DFB laser with narrow linewidth
Inventor: HSU TSUNG-YUAN
IPC: H01S5/12
Filed: 2002-03-26
Granted: 2003-06-11
Abstract: A laser system and method for self-injection locking. The system includes a laser having a laser output at a frequency omega0. An optical port provides a portion of the laser output at the port and a modulator, coupled to the port, is driven by a RF signal at a frequency omegam generates two sidebands at omega0 ± omegam. A filter passes one of the two sidebands; and an optical path couples an output of the filter to the laser for injection locking.
Patent TW-554550-B (TW)
Title: Forming low resistivity p-type gallium nitride
Inventor: STOCKMAN STEPHEN A
IPC: H01L21/205
Filed: 2002-04-26
Granted: 2003-09-21
Abstract: One embodiment of a process that forms low resistivity III-V nitride (e.g., GaN) p-type layers removes all sources of hydrogen (typically NH3) in the epitaxial growth chamber during the post growth cool-down process. By eliminating sources of hydrogen during the cool-down process, any additional passivation of the acceptor impurities (e.g., Mg) by hydrogen atoms during cool-down is avoided. After the cool-down process, the wafer is annealed at a relatively low temperature (e.g., below 625 DEG C) to remove nearly all of the hydrogen from the Mg-doped layers. The anneal can take place at a low temperature since the diffusivity of H in the p-type GaN layers is much higher than in i-type GaN layers. If the p-type layers are used in an LED, since the low temperature anneal does not degrade the GaN layers' crystallinity, the intensity of the LED's emitted light is not decreased by the anneal process. In other embodiments, the Mg-doped GaN layers are capped with an n-type GaN layer or any n-type semiconductor layer during epitaxial growth, prior to cool-down, to block the in-diffusion of H during the cool-down period. The n-type cap is then removed prior to the low-temperature anneal step. In other embodiments, the Mg-doped GaN layers are made slightly p-type after the cool-down but prior to annealing. This may be done using various processes.