Patent GB-818338-A (GB)
Title: Improvements in or relating to electric pulse-delay networks employing transistors
IPC: H03H11/26
Filed: 1958-01-24
Abstract: 818,338. Pulse delaying circuits using transistors. SIEMENS & HALSKE A.G. Jan. 24, 1958 [Jan. 29, 1957], No. 2507/58. Addition to 756,398. Class 40 (6). A pulse delay network as described in the parent Specification which comprises a number of cascade connected amplifying stages, each of which is arranged to be rendered operative during the coincidence of a pulse from a common generating stage and when an oscillatory circuit is shock excited by the pulse from a proceeding stage and in which the first half-cycle of oscillation blocks the succeeding stage and the second half cycle renders it conductive, the oscillatory circuits being damped and phase-displaced pulses being derived from each of the amplifying stages is modified by constituting each amplifier stage by a junction transistor having a unidirectional conductor connected between its base and the voltage supply source to the emitter. The oscillatory circuits are connected in series with the emitter/collector path so that the oscillatory current from the circuit flows alternately through the base emitter path of the transistor and through the unidirectional conductor in dependence upon the direction of oscillatory current. Fig. 1 shows a pulse delaying circuit comprising PNP junction transistors T1, T2 ... Tn and in which the damped oscillatory circuits in the collector-base coupling circuits comprise a coil, auch as L2, coupled to the succeeding' network, the transistor being controlled by the current through the damping resistor of the preceding network. Each transistor is blocked by means of a positive bias voltage +Uv fed through the resonant circuit and damping resistor, to the base and also by pulses fed from. generator P via switch S so that the current flows through any given transistor only when the voltage +Uv is rendered ineffective and the switch S is simultaneously closed. If it is considered that a negative pulse is fed from the tuned circuit in the collector of transistor Tn to the base of transistor T1 when a pulse is simultaneously applied from generator P via switch S the transistor T1 is in the conductive condition and its associated tuned circuit is shock-excited. The first half cycle is positive-going and the current flows through the damping resistor R1 and diode G2 to earth. The next half cycle is negative-going so that the transistor T2 conducts due to the incidence of the pulse from generator P. This process continues along the chain, the impulse transit time between two stages being equal to the duration of a cycle of the pulse from generator P. The PNP transistors may be replaced by NPN transistors. Fig. 2 shows transistor Tp1 arranged in a conventional oscillator circuit to generate sinusoidal oscillations which are clipped to form rectangular pulses by transistor Tp2, thus constituting the generator P of Fig. 1. These are then applied to the base of a transistor Ts which is connected in common to the emitters of the transistors T1, T2 ... Tn, Fig. 1, and constitutes the switch S. Fig. 3a shows a modification of a single amplifier stage which enables current pulses to be taken from the output terminal E of any stage, the transistor T20 being the complement of transistor T2. Fig. 3b shows a further modification in which each of the transistors T30, T3, Ts3 is the complement of the corresponding transistor shown in the circuit of Fig. 3a. If the consecutive stages of the delay network are constituted by circuits as shown in Fig. 3a and Fig. 3b they may be combined to feed current from their emitters collectors through a common load V as shown in Fig. 4 so that the two stages T20, T30 constitute a simple AND gate.