Patent EP-0154086-A3 (EP)
IPC: H04B3/06
Filed: 1984-11-29
Abstract: A data recovery circuit for a data recording/transmission 
system wherein information is encoded in an equalised data 
signal comprising at least partly doublet pulses, each valid 
doublet pulse comprising two adjacent opposite polarity 
pulses, the data recovery circuit being arranged to disting­
uish individual doublets from noise in the equalised data 
signal, receiving the equalised data signal, and responsive 
thereto supplying a doublet indentification signal identifying 
individual portions of the equalised data signal as constitut­
ing doublets, comprises a differentiator (11) connected to 
receive the equalised data signal to provide an output signal 
having a waveform following the time derivative of the 
equalised data signal, and having a predetermined delay 
time. A first comparator (15, 16) is connected to receive an 
output of the differentiator (11) for providing, as an output, a 
logic level signal having first, second and third instantaneous 
states indicating that the output signal of the differentiator is 
respectively less than, within, or greater than a first predeter­
mined signal range whose minimum corresponds to an 
equalised data signal slope smaller than a first predeter­
mined negative slope, and whose maximum corresponds to 
a slope greater than a second predetermined positive slope. 
An amplifier (20) is connected to receive a delayed equalised 
data signal for supplying an amplified output signal having a 
waveform following the equalised data signal and delayed 
by a predetermined delay time therefrom, A delay element is 
connected to receive the equalised data signal, for supplying 
the delayed equalised data signal to the amplifier (20). An 
analog gate (23, 24) is connected to receive the amplified 
output signal from the amplifier and the logic level signal 
from the first comparator (15) for supplying an output signal 
including a first portion following the amplified output signal 
while the logic level of the first comparator means has 
exclusively its first state and a second portion following the 
amplified output signal while the logic level signal of the first 
comparator has exclusively its third state, each portion 
having a predetermined level otherwise. A second compara­
tor (27) is connected to receive the output of signal of the 
analog gate (23, 24) for producing responsive thereto, a logic 
signal having first, second and third instantaneous states, 
the first state and the third state of the second comparator 
indicating, respectively, that the first portion and the second 
portion of the output signal of the analog gate are outside a 
second predetermined signal range, and the second state of 
the second comparator indicating that, both first and second 
portions of the output signal of the analog gate are within the 
second predetermined range, the second predetermined 
signal range substantially corresponding to the minimum 
excursion of the equalised data signal between points (i) 
having slopes corresponding to the first and second prede­
termined slopes and (ii) between peaks of a valid doublet 
pulse, the second comparator producing a doublet identifica­
tion signal.