Patent GB-1093175-A (GB)
Title: Memory systems
Inventor: HARDING PHILIP A
IPC: G11C7/02
Filed: 1964-12-11
Abstract: 1,093,175. Circuits employing bi-stable magnetic elements. WESTERN ELECTRIC CO. Inc. Dec. 11, 1964 [Dec. 13, 1963], No. 50511/64. Heading H3B. [Also in Division G4] In a matrix memory array, the drive and sensing windings are each arranged in groups in different ways thereby reducing noise effects in a sensing operation. Drive plane circuits are divided into a plurality of groups along different lines from the division lines of the sensing plane circuits. The memory described, Fig. 1, is a 3-dimensional array of apertured ferrite plates divided into four quarters by an A-B division plane for the sense circuits and a G-H division plane for the drive circuits. As shown in Fig. 1, the memory is further divided into 16 sub-modules arranged in four modules 1-4 forming four horizontal layers. Each Y drive winding, such as that between terminals 28, 29, Fig. 2, extends through only one half of the array and further is itself arranged in two halves in staggered vertical planes in the A and B halves respectively. Each horizontal row of the matrix stores two independent words whose bits are interlaced and threaded by respective X windings arranged as shown in Fig. 3 (not shown). Each inhibit, i.e. " digit " winding, Fig. 4 (not shown), is arranged in either the G or H half of the memory thereby reducing the coupling between the inhibit circuit and a sensing circuit in the same plane so that a smaller time guard space is required between memory read and write cycles. Each sensing circuit, Fig. 5 (not shown), lies in either the A or the B half of the memory and further is arranged in two halves each threading the parts of two adjacent digit planes which correspond to a vertical stack of four sub-modules of the memory. The two halves of the sensing winding are connected to an output transformer via windings poled in such a manner that a stored " 1 " bit produces output pulses of opposite polarity in the two halves. The Y windings are plaited in an in-out weave pattern on the ferrite sheets, the remaining windings being threaded. The X wires are threaded in a non- flux-locking wiring scheme, such as is shown for the wire 79, Fig. 7 (not shown), for reducing the possibility of a locked flux path being generated round two neighbouring holes. The sensing winding, Fig. 8 (not shown), utilizes a skipping in-out weave called " complementary winding " effective to reduce transmission line distortion and to improve local noise cancellation of shuttle noises coupled from the Y drive circuit. Modifications.-The X plane circuits may be divided at the A-B division plane to achieve further sensing circuit noise reduction (Fig. 9 not shown), two more selected switches plus access diodes being required (Fig. 9A, not shown). In a modified inhibit circuit division (Fig. 10, not shown) the G-H plane is employed as before for dividing the X and Y circuits but the inhibit circuit is divided so that the first part extends between modules 1 and 4, Fig. 1 and the second part between modules 2 and 3. Further drive pulse stabilization is achieved with the inhibit circuit arrangement of Fig. 11 (not shown), in which all the digit plane inhibit circuits are driven from a single source using control gates operated jointly by drive signals, address signals, data signals and clock signals to substitute an equivalent impedance in the series drive connection for any digit plane where a " 1 " is to be written. A further noise reduction is effected by the inhibit circuit arrangement of Fig. 13 (not shown) in which the inhibit circuit portions in each half of each digit plane are electrically separate circuits and corresponding ones of such separate circuits in each module are connected in series through the G and H halves of the memory to form a single inhibit circuit for each half of the folded digit plane. Further, the inhibit circuits may be crossconnected a number of times during each passage between the front and rear of the memory, to form a checkerboard pattern (Figs. 14, 15, not shown).