Patent SG-11201906878S-A (SG)
Title: Multiple gate-induced drain leakage current generator
Inventor: SAITO MASANOBU
IPC: H01L27/12
Filed: 2017-08-11
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 02 August 2018 (02.08.2018) WIP0 I PCT ill 1111u°11111OlDIIl °nolo olomons mourn° oimIE (10) International Publication Number WO 2018/140084 Al (51) International Patent Classification: HO1L 27/12 (2006.01) (21) International Application Number: PCT/US2017/046561 (22) International Filing Date: 11 August 2017 (11.08.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/416,870 26 January 2017 (26.01.2017) US (63) Related by continuation (CON) or continuation-in-part (CIP) to earlier application: US 15/416,870 (CON) Filed on 26 January 2017 (26.01.2017) (71) Applicant: MICRON TECHNOLOGY, INC [US/US]; 8000 So. Federal Way, Boise, Idaho 83716-9632 (US). (72) Inventors: SAITO, Masanobu; Inagedai-Cho 23-5, Chi- ba City, Inageku, Chiba, 263-0032 (JP). TANAKA, Shu- ji; 1308-1-201 Iwase, Kamakura, Kanagawa, 247-0051 (JP). SATO, Shinji; 2501-6-Enzo, Kanagawa, Kanagawa, 2530084 (JP). (74) Agent: WOO, Justin N. et al.; Schwegman Lundberg & Woessner, P.A., P.O. Box 2938, Minneapolis, Minnesota 55402 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). (54) Title: MULTIPLE GATE-INDUCED DRAIN LEAKAGE CURRENT GENERATOR W O 20 18/ 14008 4 Al 270, 355- BLO 331 286, --343 o rs —317 280_1A GG, 295_1 286, D3 280_113 GG 0 —316 261 - , 348 D4 281, SID -0-315 241< 314--- 262, 344 D2 MB SOD, 314 355- 231, —345 fi m T1 -0-313 223, W30 213 301 D1 222 0 WL2, 1' 1 312 355- 212 DI 221 0 T1 -0.- 311 211 303 DI 220 0 ( 0 355- 210 DI 28% —309 241 . < 355- 3 \" D2 281A —308 263 , D4 287_1 —307 286_113 GG, -346 (57) : Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the ap- paratus, a pillar including a length extending between the first and second conduc- tive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive ma- terial and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor. 200 FIG. 3 [Continued on next page] WO 2018/140084 Al MIDEDIMOMOIDEIRDEIDIOMOIOMONIRMOHMOVOIMIE Published: — with international search report (Art. 21(3))