Patent GB-842042-A (GB)
Title: Electrical calculating system
IPC: G06F7/50
Filed: 1956-10-26
Abstract: 842,042. Circuits employing bi-stable magnetic elements. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 26, 1956 [Oct. 31, 1955], No. 32684/56. Class 40 (9). [Also in Group XIX] An electrical calculating system comprises a storage matrix, two summation matrices of bi-state elements, and a temporary storage group of bi-state elements. A quantity stored in the storage matrix is read out and transferred partly to the temporary storage group and partly to a first one of the summation matrices, the contents of the group and the matrix then being read out and transferred to the second summation matrix. During the transfer operation, the information being transferred undergoes modification by switching means actuated in accordance with the value of a quantity to be added to the quantity originally stored in the storage group. The sum of the two quantities can then be read out of the second summation matrix. As shown, Figs. 1a, 1b, there are provided a 7 Î 10 matrix 24 of bi-state magnetic cores capable of storing a ten-decimal-digit number in biquinary code, a temporary storage group of five cores 39 corresponding to the quinary part of the number stored in the matrix 24, a 3 x binary adder matrix 68, a 5 X 6 quinary adder matrix 38, and a mechanical storage device adapted to store the digits of the number to be added in. An additional pair of carry cores 23 is provided in association with the matrix 24 to indicate decimal carry. The number to be added is entered by keys into the mechanical storage device, Figs. 8, 10, commencing with the most significant digit, and is read out therefrom for transfer to the 7 x 10 storage matrix 24 commencing with the least significant digit. The entry of each digit is determined by a combination of key storage switches 28-31 which are actuated by code pins 233, Fig. 10, in four discs 234 which are rotated step-by-step. For each decimal digit to be entered, the following cycle of operations occurs. The binary part of the digit stored in the appropriate row of the matrix 24 is transferred to the binary adder matrix 68, being modified on the way by a switch 28 whose state depends on the units digit of the binary form of the decimal digit being entered. The quinary part of the digit is transferred to the temporary storage group of cores 39. A read pulse on the wire 77 then causes information to be sent from the adder 68 through switches whose state depends on the higher binary denominational digits of the binary form of the decimal digit being entered to the columns of the adder matrix 38, and from the temporary storage group 39 to the rows of the quinary adder matrix 38. The information thus written into the matrix 38 is read out and transferred to the storage matrix 24 which will then hold the sum of the decimal digit originally stored therein and the digit entered and also the carry digit if any. Operation.-A digit to be entered is introduced by energizing appropriate ones of the key storage switches 29-31. The timings in an entry cycle are shown in Fig. 7. The three circuit-breakers 64, 69, 49 close simultaneously. Closure of the circuit-breaker 64, Fig. la, connects a D.C. bias to the temporary storage group 39. Closure of the circuit-breaker CB69 primes a thyratron (Fig. 3, not shown), to send a read pulse on the line 58 through the units row of cores of the matrix 24. Closure of the circuitbreaker CB49 closes a circuit to an emitter switch which directs the read pulse sequentially to the denominational rows of the matrix 24, so that the read pulses will pass first to the units row. Shortly afterwards, the circuit-breaker CB50 operates to actuate a trigger circuit, thereby firing a thyratron which transmits a read pulse 70a along the units row of the 7 x 10 matrix 24. The quinary part of the units digit is transferred to the temporary storage group 39. The binary part goes directly to the adder 68. The decimal carry part passes to the appropriate columns of the adder 68 via the key storage switch 28 whose state depends on the binary units digit of the decimal digit being entered. Thus an appropriate core of the 3 x 2 adder is switched. The circuit-breakers 64, 69, 49, 50 are now returned to their former state. The circuit breaker CB161 operates to connect a D.C. bias over the wires 58 and 59 so that the units row of the 7 X 10 matrix 24 is prepared to receive the sum units digit. The circuit-breaker CB163 also operates to prime a thyratron 76 so that a triggering signal generated as before by the operation of the circuit-breaker 50 causes it to fire and pass a read pulse 76a through a wire 77 threading the cores of the temporary storage group 39 and also all the cores of the binary adder 68. The information from the temporary storage group 39 is thereby sent to a row of the quinary adder matrix 38. The information from the binary adder matrix 68 passes through a primary of one of the transformers 84, 145, the secondary of which sends a pulse to the appropriate thyratron 45 or 46 which fires to send a write pulse to one of the binary columns of the 7 Î 10 matrix 24 thereby switching the appropriate core in the units row thereof corresponding to the binary part of the sum decimal-units digit. The information from the 3 x 2 adder then passes through a series of switches 29-31, whose state depends on the higher order binary digits of the decimal digit being entered. The result is that a core of the 5 x 6 adder 38 will be switched, this core corresponding to the quinary part of the sum decimal-units digit and to the carry state. On closure of the circuit-breaker CB166 and subsequent closure of the circuitbreaker CB50, the thyratron 94 is fired to pass a read pulse 94a through a read wire 95 threading the adder 38. Consequently the switched core thereof will be returned to its former state and an output pulse will be produced which, after amplification, is split into two paths, the pulse on one path firing one of the thyratrons 40-44 to send a write pulse which switches the appropriate quinary core of the units row of the 7 Î 10 storage matrix 24. The pulse on the other path passes to one of the thyratrons 47, 48 which fires to send a pulse and thereby switch one of the carry cores 56, 110 to indicate whether decimal carry is to take place in the next operational digit cycle. This completes the operational cycle for the decimal units digit. The key storage mechanism now clears and is set up to represent the tens digit of the number being entered. A corresponding operational cycle is now performed for the tens and higher denominational rows of the 7 x 10 storage matrix 24 which are sequentially connected for a read pulse by the emitter switch. At the conclusion of the complete entry operation, the number to be entered has been added to that originally standing in the 7 X 10 matrix 24. Total read-out.-To take a total reading of the number standing in the 7 X 10 matrix 24 at any time, a relay 115 is energized to switch the associated contacts which are in the output of the write thyratrons 40-48, to connect this output through terminals 120-124 to the print magnet solenoids of a typewriter, one such magnet being energized for each decimal digit of the number as read out (Fig. 4, not shown). The 7 x 10 matrix 24 is scanned by employing a total emitter switch commencing with the highest denominational order. A total may be typed out but not removed from the 7 Î 10 matrix 24 by allowing the typing mechanism to actuate the key storage mechanism and then proceed through a number entry cycle as described above. Subtraction.-Subtraction is effected by complementing and adding the complement. Operation of the relay 181 causes connection of the complementary circuits in the output from the temporary storage group 39. Operation of the relay 182 causes connection of the complementary circuits leading to the write thyratrons 40-46. The relays 181, 182 may be combined into a single relay. Component details.-Each of the cores in the 7 X 10 storage matrix 24 consists of four separate cores with a single turn output winding, this arrangement being adopted so as to obviate a tendency to switch the other nine cores in the column which would be present if four turns on one core were employed. To avoid back transfer to a core preceding a switching core producing an output pulse the read winding of the switching core is wound through the preceding core in a direction to oppose the back transfer. The mechanical storage device, Fig. 8, comprises a continuously-driven shaft 193 which supplies power to the shaft 203 through a onerevolution clutch which, when energized, drives the shaft 203 through one revolution to provide an accumulate cycle. Another one-revolution clutch is adapted to drive the shaft 204 for one revolution when a total read-out cycle is required. For entering the digits of a number into the mechanical storage device, the shaft 208 is driven through a one-sixth revolution clutch and this motion is transferred to onetenth revolution steps of the shaft 267 through suitable gearing. The operation of an input key corresponding to a decimal digit of a number being entered actuates appropriate ones of the solenoids 228-231 to displace pins 233 carried by discs 234 fixed to the shaft 267. The disc 234 is so constructed that each of the pins 233 is biased to one of two positions, a normal position, and a displaced position wherein one end of the pin extends out from the surface of the disc 234 into the path of a spring-biased follower arm 235. Each follower arm is arranged to actuate one of the key storage switches such as 31, Figs. 1b 10. During an accumulate cycle, all of the pins which were displaced during the keying-in operation will be returned by an arm 239. The emitter switch 25, Fig. 8, is also rotated by the shaft 203 so that it makes a complete revolution during the accumulate cycles. The cam discs 252 on the shaft 203 actuate the circuit