Patent SG-11201810104V-A (SG)
Title: Method for fabrication of a semiconductor structure including an interposer free from any through via
Inventor: NGUYEN BICH-YEN
IPC: H01L21/762
Filed: 2017-05-24
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property MD 1101111 0 111010101111101011111 0 01010 11111111 001110111011111011110111111 Organization International Bureau (10) International Publication Number (43) International Publication Date ......0\"\"1 WO 2017/207390 Al 07 December 2017 (07.12.2017) WIP0 I PCT _ (51) (21) (22) (25) Filing Language: (26) (30) (71) (72) (74) (81) International Patent Classification: DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, H01L 21/48 (2006.01) H01L 21/56 (2006.01) HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, H01L 21/60 (2006.01) H01L 25/065 (2006.01) KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, H01L 21/683 (2006.01) H01L 21/98 (2006.01) MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, H01L 21/762 (2006.01) H01L 23/485 (2006.01) PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, International Application Number: SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, PCT/EP2017/062556 TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. International Filing Date: (84) Designated States (unless otherwise indicated, for every 24 May 2017 (24.05.2017) kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, English UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, Publication Language: English TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, Priority Data: MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, 1654831 30 May 2016 (30.05.2016) FR TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Applicant: SOITEC [FR/FR]; Parc Technologique des Fontaines, Chemin des Franques, 38190 BERNIN (FR). Published: Inventors: NGUYEN, Bich-Yen; 110 S. Laurelwood Dri- — with international search report (Art. 2 1 (3)) ye, AUSTIN, Texas 78733 (US). ECARNOT, Ludovic; — before the expiration of the time limit for amending the 407 Avenue du golf, 38410 VAULNAVEYS-LE-HAUT claims and to be republished in the event of receipt of (FR). BEN MOHAMED, Nadia; 5, avenue Paul Eluard, amendments (Rule 48.2(h)) 38130 ECHIROLLES (FR). MALVILLE, Christophe; 90 me du Château, 38660 LA TERRASSE (FR). Agent: BREESE, Pierre; IP TRUST, 2 rue de Clichy, 75009 Paris (FR). Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, = = = = ei hydrogen and © backside Title: METHOD FOR FABRICATION OF A SEMICONDUCTOR STRUCTURE ANY THROUGH VIA INCLUDING AN INTERPOSER FREE Figure 7 (4--- 5 = (54) = FROM = = = 7b = 5a 7a 1 . 4 4 4 4 4 ;4 444 - lairm- = ► 4 g ag = - 5a 1-1 © C:r M IN (57) 0 ei _ part — 2 introducing, at selected conditions, (2) at a predetermined depth therein, forming on the temporary support (1) an layer (5); assembling a stiffener (8) on a support (1) to detach the residual free from any through via. Il interconnection : The invention concerns a method of forming a semiconductor structure comprising: and helium species (e.g., ions) in a temporary support (1) to form a plane of weakness to define a superficial layer (3) and a residual part (4) of the temporary support (1); layer (5); placing at least one semiconductor chip (6) on the interconnection of the at least one semiconductor chip (6); and providing thermal energy to the temporary (4) and provide the semiconductor structure. The interconnection layer (5) forms an interposer