Patent GB-1340057-A (GB)
Title: Display cell for a memory
IPC: G06F12/10
Filed: 1970-12-18
Abstract: 1340057 Data processing system PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 18 Dec 1970 [23 Dec 1969] 60251/70 Heading G4A A data processing system has an addressable storage system including a plurality of data stores of different access speeds comprising a working, relatively high speed data store and a backing, relatively low speed data store of larger capacity than the working store, the data processing system being arranged to process programs stored in said working store, the programs being of the kind comprising a number of nested program routines arranged on a number of hierarchically related levels such that each routine, except those on the highest level, is dependent on a routine on the next higher level, the storage system containing a number of program sections each containing one or more hierarchically related routines and being arranged to transfer program sections between the backing and working stores in order to enable them to be processed, and the data store of the highest access speed containing, for each program section in the storage system, a display cell in which is stored an address in the storage system by means of which the associated program section may be addressed and the address in the storage system of the display cell associated with that program section which contains the routine on which the highest level routine in said associated section is dependent when such a routine exists and otherwise an indication that no such routine exists. General.-The system may include one or more processors connected to a large capacity, slow access backing store, e.g. slow core, disc, tape &c., and a high speed working store, e.g. a high speed core memory. The display cells may be located in a separate very high speed section of the working stored formed of e.g. integrated circuits. Program structure.-A suitable structure is illustrated in Fig. 1, B 1 <SP>0</SP> is the highest level program routine which controls program routines B 2 <SP>0</SP> and C 2 <SP>0</SP> which in turn control program routines B 3 <SP>0</SP> and B 4 <SP>0</SP>, and C 3 <SP>0</SP> and C 4 <SP>0</SP> respectively. Details.-The programs are stored in the memory in sections, each of which contains one or more program routines which are related within the nesting structure, see, e.g. Fig. 9, where section ST1 contains routines B 1 , C 2 , and C 3 . Each section may include free areas (shaded, Fig. 9) in which data developed during processing may be stored. During execution of a program the relevant sections are located in the working store, the remainder being in the backing store. The system is arranged to ensure that all the sections required for a task are located in the working store prior to execution of the task by determining from the program address of a required program instruction the physical store addresses of that instruction and of any higher level controlling program routines which are required. Two embodiments are described. In the first embodiment, Fig. 9, two sections ST1 and ST2 are shown together with respective display cell address tables DCT1 and DCT2 and a number of display cells, one for each program routine in the two sections. Each display cell, e.g. b 4 , contains the physical base address in the memory, B 4 , of the associated program routine (the address may be in the main or backing store) and the address b 2  of the display cell relating to the next higher level controlling program routine (in this case B 2 ). Thus given that a particular program routine is required it is possible to access the corresponding display cell via the display cell address table and to determine (see below) by running through the connected series of display cells, e.g. b 4 , b 2 , b 1 , and examining the corresponding base addresses, B 4 , B 2 , B 1 , whether all the required sections are located in the working store. In the second embodiment, Fig. 10, only one display cell, DCS, is provided for each section. In this case the display cell address tables DT 1 , and DT 2 , contain the address of the corresponding display cell and the base addresses of each program within the section relative to the base of that section, e.g. rb 4 , rb 2 . If an instruction in program B 2  is addressed the entry st 2 , rb 2  in table DT 2  is addressed. The address st 2  addresses display cell st 2  in which the physical base address ST 2  of section ST 2  is stored. The base address of program B 2  relative to ST 2 , i.e. rb 2  is then added to ST 2  to give the physical base address of program B 2 . Instructions within that program are accessed by a further indexing step. The display cell st 2  is also used to check the location in the storage system of controlling programs on higher levels in the same way as in the first embodiment (see below). When the base addresses of related programs are determined by running through a series of display cells a word V is constructed by writing a 1 in each bit position when the corresponding section is located in the working store and a 0 otherwise. When a complete chain of display cells has been examined and the corresponding word V established a further word W having a 1 in each bit position corresponding to a section in the series of related sections which is not required for the task in hand and a 0 in each bit position corresponding to a section which is required is OR-ed with the word V to determine whether all required sections are present in the working store. The task is then executed or placed in a waiting list accordingly. The word W may be used to activate a program for transferring required sections from the backing store to the main store. Modifications.-The display cells may contain, in addition to the address of the corresponding program in store and of the next higher level related display cell, further data, e.g. the length of the associated section, memory protection data (i.e. what storage operations are allowed in the associated section), a bit indicating whether the associated section is in the main or backing stores (so that examination of the base address is not required) &c.