Patent GB-767708-A (GB)
Title: Improvements in electronic multiplying machines
IPC: G06F7/52
Filed: 1955-01-13
Abstract: 767,708. Digital electric calculating-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Jan. 13, 1955 [,Jan. 15, 1954], No. 1068/55. Class 106 (1). ). In an electronic multiplying machine each digit of a multiplier is taken in turn to form with a multiplicand left-hand and right-hand partial products which are individually summed and the two results added. As described during the first 10 points of a first 14-point mechanical cycle a multiplier MP and a multiplicand MC, both of two decimal digits, are read from a first record punch card 1, Fig. 1a, into two registers MP and MC, Fig. 1c; at some time during the remaining 4 points of the first cycle the product is computed electronically and entered into a product register; during the first ten points of the second cycle simultaneously a second card is read and the first product is punched on to the first card. This process is continued, each card being read and then punched with the product, until a complete pack has been processed when the machine automatically stops. The principal employed in multiplication is that the digits of the multiplier are taken in turn, each selecting a corresponding one of nine gating circuits known as " X plates " which provide pulses representative of the left-hand and right-hand digits of the product of the number associated with the plate and all the numbers 0 to 9. These pulses are filtered through the multiplicand register and those that are not stopped, which represent the product of the current multiplier digit and the multiplicand, are passed to left and right-hand accumulators. When each digit of the multiplier has been dealt with the contents of the lefthand accumulator are added to the right-hand accumulator which then registers the required product. Input. In synchronism with the sensing of the first nine rows of a record card 1, Fig. la, nine pulses from a cam-controlled hard valve trigger are applied to four pentode gates, one in each decimal denomination of the multiplier MP register, Fig. 1a, and multiplicand MC register, Fig. 1c. Each of these gates is opened as a hole in the corresponding column of the card is sensed, allowing a number of pulses equal to the value of the hole sensed to pass through and step an " on " condition along a chain of ten cascade-connected triggers, thus registering the value of the hole sensed. Accumulators. Each decimal denomination of the binary-coded decimal left-hand components accumulator, Fig. 1d, consists of four triggers S1, S2, S4, S8, two monostable devices D1, D2, and a carry trigger CY. The monostable devices D1 and D2 are so arranged that after they have both been put " on simultaneously, which happens each time trigger S8 goes " on," first D1 goes " off " and in so doing changes over. trigger S2, thus adding two to the count registered, and then D2 goes " off " and in so doing changes over trigger S4, thus adding four to the count registered, the net result being that each time trigger S8 goes " on six is added to the count registered, thus causing the four triggers S1, S2, S4 and S8 to count on a decimal radix. The four binary bits of a decimal digit are entered successively to their appropriate stages at a speed sufficiently slow to permit of both interstage binary carry and the addition of two successive pulses from the devices D1 and D2 each time trigger S8 goes " on." Any carry digit from the counter, which arises each time the trigger S8 goes " off " is stored in the carry trigger CY until entry has finished and is transferred to the next higher denomination during a special carry period. The right-hand accumulator is similar to the left-hand accumulator. The multiplication " X " plates. Each of the nine X plates, that for digit 8 being shown in Fig. 1d, consists of two groups of diode gates for forming the left-hand and right-hand digits. Each plate is fed with -1-, -2-, -4- and -8- pulses produced by a compute commutator CC, Fig. 1a, when a calculation is in progress. When a plate, say the X8 plate, is selected, each of the diode gates (shown as contacts), is opened (i.e. the contacts are closed) allowing particular combinations of the pulses -1-, -2-, -4-, -8-, to pass to a number of output terminals. In the particular example shown for 8 Î 9, the LHX8 group provides three pulses -1-, -2-, -4-, on lead 13 (representing 7) and one pulse -2- on lead 14 (representing 2) which as a digit 9 is registered in the MC register will be gated to the left- and right-hand accumulators respectively. Operation. The particular example 83 Î 91 will be described. During the first 10 points of a mechanical cycle the card is read and the numbers 83 and 91 entered in the MP and MC registers. As a result stages S8 and S3 of the tens and units denominations respectively of the MP register will be " on " and steps S9 and S1 of the MC register will be " on ". Associated with each stage of each denomination of the MP register is an output gate pentode which feeds a cathode follower, and associated with each stage of the MC register are two gate pentodes. Soon after the numbers 83 and 91 are registered a compute commutator, which produces pulses as shown on six leads, is started by a cam produced pulse, and the first stage CST of a column shift commutator CSC is put " on thus opening all the output pentode gates of the tens denomination of the MP register, and directing the left- and right-hand product digits to the appropriate denomination of the accumulators by a diode switching circuit CSS. During the first electronic cycle multiplication by 8 takes place. The tens denomination of the MP register selects the X8 plate whose output leads are connected appropriately to the output pentode gates of each stage of the MC register, only those leads going to stages S9 and S1 being shown since as these stages are the only stages " on " only their associated output gates will be open. Pulses passed by these four pentode gates are directed to the appropriate denominations of the two accumulators by the column shift switch via a distributer consisting of a matrix of pentode gates, the gates in each column being opened by the pulses -1-, -2-, -4- and -8-. After pulse -8-, the pulses C1 and C2 are produced which control interdenominational carry in the accumulators. In the actual machine described the duration of only one pulse C1 is sufficient for all carries to be transferred, but if the number of denominations were increased the duration of two pulses might be necessary. At the end of the first electronic cycle the column shift commutator is advanced to energize lead CSU and multiplication by the units digit of the multiplier takes place. During the third electronic cycle the number registered in the lefthand accumulator is transferred to the righthand accumulator by the use of a set of doubletriode " and " gates which are pulsed in sequence by the pulses -1-, -2-, -4-, -8-. During this transfer suppression gates are provided to prevent the binary bits -2- and -4- being transferred if S8 is " on " since otherwise six more than the true number would be transferred. Thus, after three electronic cycles, the product is in the right-hand accumulator. During the first 10 points of the second mechanical cycle a second card is read, the MP and MC registers having been cleared, and 10 cam-produced pulses are applied to each denomination of the right-hand accumulator to produce differentially timed firing of the carry triggers, the outputs of which are used to control the punching of the first product into the first card. A zero analyser is provided which, if any digit of the multiplier is a zero, causes the column shift commutator to omit the denomination containing zero. In a modification the multiplicand register MC is constructed in a similar way to the accumulators. Then, since more than one stage of each denomination of the MC register may be " on at the same time, it is necessary to multiply each stage separately by the current multiplier digit to prevent the possibility of several pulses reaching the accumulators simultaneously. This is achieved by a secondary commutator which advances one stage for each electronic cycle, the column shift commutator then being advanced once for each cycle of the secondary commutator. Specifications 588,167, 598,565 and 656,139 are referred to.