Patent GB-899259-A (GB)
Title: A time-delay line incorporating an electric analogue differential analyser
Inventor: BORSKY VLADIMIR
IPC: H03H11/26
Filed: 1959-01-07
Abstract: 899,259. Electric analogue calculating. TESLA, NARODNI PODNIK. Jan. 7, 1959, No. 640/59. Class 37. A delay line comprises an electric analogue differential analyser arranged to solve the wave equation with initial conditions for t = 0 and boundary conditions for x = 0 and for x = X, an arbitrary limiting value of x. where x, t are independent variables of space and time; v is a constant velocity of propagation; u(x,t) is a function of the independent variables; f (t) represents the function of time which is to be delayed. The general solution of (1) has the form where F1(t) and F2(t) represent arbitrary functions of t and the terms in F1 and F2 represent generated and reflected waves; so that for non-reflection F2 = 0 when equation 5 is satisfied. It is shown that, by the method of differences, wherein interval [0, X] is divided into n parts over which x acquires discrete values xk fulfilling x0 = 0; xk > xk - 1 for k = 1, 2, 3 .... ... n; xn = X the solution of equation 1 under the prescribed conditions is approximately the solution of equations where u0(t) = f (t) #x X and it is shown that for # = #- and #x = - v n Equations 9, 10 are soluble by a delay line (Fig. 1) comprising two double summation integrators In-2 and In-1 of the kind described in Specification 868,612 followed by a simple integrator In in tandem. Each generalized integrator (k = n, n - 1, n 2, &c.) Ik has a D.C. amplifier A whose input is earthed over capacitance C1 in series with resistance Ro; the generalized node Sk (k = n, n 1, n - 2, &c.) of Ro and C1 being connected to the preceding integrator over R1, to the amplifier output over feed-back resistance R¢ (= ¢R1) and to the output of the succeeding integrator over feed-back resistance R1. Amplifiers A are shunted by capacitors C2, C2 in series whose junction is earthed over R2. Integrator In comprises an amplifier A shunted by R3 and C3 with R3 in series with its input. In operation the input signal - Un-3 to be delayed is fed to the input of the first double summation integrator; e.g. to node Sn-2 as shown with S and S<1> disconnected, developing a signal +Án-2 at node Sn-1 and a signal - un-1 at node Sn so that the signal output +Án appears on the output tn of the simple integrator In as the required delayed signal. Additional delay may be introduced by adding further integrators In-3 and In-4 (not shown) in tandem ahead of In-2 and connected to inputs S and S<1> thereof similarly to the connection between In-2 and In-1. Component values are established by the relations An alternative form of delay line is described (Figs. 2a, 2b, 2c, not shown) comprising an electric analogue differential analyser chain embodying modified integrators wherein each integrator has two series resistance inputs and two series resistance outputs; the inputs being connected to the outputs of the preceding and next preceding integrators and the outputs to the outputs of the succeeding and the next succeeding integrators; the system giving greater accuracy. A mathematical analysis is given. The passive elements may be mounted on panels with remote amplifiers, and interconnected by patch connectors; and the time delay of the line may be regulated in steps of # from # to n#, and may be arranged to yield n output signals delayed by successive steps; given by which may be combined to simulate the weighting function of a generalised four-terminal network. Waveforms may be generated by energizing the line with a Heaviside unit function voltage, and multiplying and combining the individual delayed output voltages by appropriate weighting values.