Patent GB-905276-A (GB)
Title: Improvements in or relating to electrical switching circuits
Inventor: TOMLINSON TERENCE BERNARD
IPC: H03K19/173
Filed: 1958-06-05
Abstract: 905,276. Binary adders and subtractors. COMPUTER DEVELOPMENTS Ltd. June 4, 1959 [June 5, 1958; Aug. 29, 1958], Nos. 18568/59 and 27791/58. Divided out of 905,275. Class 106 (1). [Also in Group XL (c)] A switching circuit comprises at least three non-linear resistive elements 41A, 41B, &c. in which the current reaches a saturation value as the voltage applied thereto is increased, one terminal of each element being connected to a respective switching voltage source 44A, 44B, &c., the other terminals of all the elements being connected together and to an output circuit 45. Each non-linear element may be constituted by a pair of semi-conductor diodes connected back-to-back or by an equivalent single element incorporating two junctions so as to obtain a symmetrical characteristic each half of which corresponds to the reverse characteristic of one of the diodes; alternatively a symmetrical transistor connected so as to have a constant base current may be used; Fig. 1a shows a further construction in which each element comprises a silicon or germanium rod provided with an impurity region 50 giving rise to a local PN junction, this junction acting to restrict the flow of current above a limiting value. In the embodiments described the switching voltage sources each have two alternative output voltages, viz. zero and V volts, the result being such that when a majority of the elements have a voltage V applied thereto a voltage approaching V is passed to the output circuit while when the majority of the elements have a zero voltage applied thereto a voltage approaching zero is passed to the output circuit. Fig. 7 shows the use of a plurality of such circuits in a circuit for performing either binary addition or subtraction. The inputs A, B represent corresponding digits of two binary numbers which are to be added or subtracted while the input C represents " carry " or " borrow " digits resulting from the act of adding or subtracting the immediately lower order digits of the two numbers. With switch 79 as shown, the circuit operates to add. Circuit 61 gives unity output when two or three of the digits A, B, C are unity. This is the condition for a " carry" " to be generated; hence a unity output is sent to the " carry/  borrow" circuit 81; at the same time the output is inverted at 85 to give a zero input to elements 66, 67 so that circuit 60 operates as an AND gate giving a unity output which passes to the " sum/difference " circuit 75 when each of A, B, C are unity. Further, when only one of A, B, C is unity, no carry is generated, unity input is applied to elements 66, 67 so that circuit 60 operates as an OR gate and again passes a unity output to the circuit 75. In subtraction the same conditions apply for the difference digit as applied for the sum digit; hence circuits 60, 61 remain connected to the " sum/difference " circuit as before. However, switch 79 is changed over to use circuit 62 and inverter 86 to obtain the " borrow " digit, this resulting when A is zero and B and/or C are unity or when A, B and C are all unity. The circuit may either form one element of a device for performing parallel addition or subtraction or, by incorporating a delay in the path between the " carry/borrow " input and output, may be made to perform a complete addition or subtraction in serial fashion. Fig. 8 (not shown), shows the equivalent of the addition portion of the circuit of Fig. 7 with, however, transistor amplifiers inserted between the digit inputs and circuits 60, 61, between circuits 61 and 60 to act as an inverter and in the output to the circuit 75.