Patent GB-1300029-A (GB)
Title: Information buffer unit
IPC: G06F5/10
Filed: 1971-07-22
Abstract: 1300029 Digital transmission PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 22 July 1971 [25 July 1970] 34366/71 Heading H4P A buffer unit which converts information characters synchronized with a first clock into a sequence controlled by an independent second clock comprises a first cyclic address unit for directing the characters into a group of store locations, and a second cyclic address unit for selecting the locations in the same sequence and directing the information to an output under the control of the second clock. A phase comparison and correcting unit receiving signals from both clocks is provided to limit the phase difference between clock signals. An information buffer unit includes a known random access store 103 in which a location is selected on application of a coded address to terminal A. Information bits are then written in through terminals D1, D2 depending on the binary values 1, 0. Information may be read out via terminal OT in different sub intervals partly determined by selector 104 which receives line clock pulse 101 and local clock pulses 102. Selection of write intervals is described in detail with reference to Figs. 2, 3 (not shown). One output of selector 104 derives a modulo - n counter 108, where n = number of store locations in 103, the position of counter 108 being represented in binary code in parallel form at terminal 109 connected to the input of a multiple AND gate 110 having a further input P/Q from selector 104 and an output to terminal A. When signal P/Q = 1, AND gate 110 passes the address from counter 108 in a time interval (m, n). Fig. 2 (not shown) allowing the bit sensed by AND gates 105, 106 to be written in the selected store location after which counter 108 is reset to the next position by a signal S6/S14 hence store locations are selected cyclically in a fixed sequence. Read out is through a pair of corresponding gates 113, 114 controlled by a read interval selector 111 and modulo - n counter 112 passing through gate 118 opened by signals S1/S9 in similar manner to the write in. If the line clock has a higher speed than the local clock, store 103 will become full and address counter 108 will catch up with counter 112 hence new bits will be written on top of bits which have not yet been read out hence these bits will be lost. Conversely if information bits are read out quicker than written in, if reading is non destructive bits written in will be read again, or if reading is destructive a series of O's will be obtained. If the cycle of counter 112 has shifted 180 degrees in phase relative to the counter 108, the buffer unit can compensate for positive and negative phase differences between line and local clocks to a maximum of n x 180 degrees. A phase difference of 180 degrees means that store 103 contains n/2 bits which have not yet been read hence can accommodate or supply n/2 bits before it is full or empty representing the phase difference of n x 180 degrees. In placing the buffer unit in operation counters 112, 108 may be started with a difference of 180 degees which ensures that no bits are lost or read twice provided such phase difference remains smaller than n Î 180 degree which is particularly advantageous in asynchronous conditions. To accommodate a greater difference than this counter 112 may perform an extra step when the store is almost full and a suitable choice of the instant only predetermined bits may be skipped and if these are redundant bits no information is lost; similarly a step may be deleted when the store is almost empty hence it is ensured that the phase of counters 112, 108 remains with in the range 0-360 degrees and averages 180 degrees over a period. In another arrangement described in the Specification reading may be temporarily delayed or advanced by one half of a local time interval which produces correction of the phase of counter 112 without information being lost or repeated. A decoder 120 recognizes the number 0 in counter 108 and supplies a 1 to gate 125; decoders 121, 122 also recognize the numbers 0, 1, 2 and 30, 31 respectively in counter 112 and these are passed through OR gates 123, 124 to AND gates 126, 127 setting flip flops 128, 129. If line clock speed is greater than the local clock, a flip flop 128 will be set to '1' and conversely if lower flip flop 129 to '1' giving outputs V, L respectively which through selector 111 resets counter 112 and also supplies a signal RS to reset flip flops 128, 129, the internal operation of 111 being described in greater detail with reference to Fig. 4 (not shown). If m-bit characters are to be processed in parallel the block shown by broken line must be provided m times: alternatively the store 103 may comprise m storage planes having one common address unit.