Patent FR-1346327-A (FR)
IPC: H03M7/48
Filed: 1962-10-24
Granted: 1963-12-20
Abstract: 1,018,465. Multiplex pulse code signalling. INTERNATIONAL BUSINESS MACHINE CORPORATION. Oct. 24, 1962 [Oct. 24, 1961 (3)], No. 40292/62. Heading H4L. A time division multiplex system comprises apparatus for transmitting a signal which is dependent on whether the pulse coding in successive frames of binary data shows any change. As shown in Fig. 1, binary coded signals from a plurality of sources 10a to 10n e.g. in a space vehicle, are multiplexed at 12 and supplied to a delay line 16 providing a delay equal to one frame period, and via a switch 13 to an EXCLUSIVE OR gate 14 providing an output pulse only when the two input signals disagree. An output from gate 14 is supplied to a counter 18 and AND gates 20, 22. If the capacity of the counter 18 is exceeded a signal appears on overflow line 24 to switch a counter flip-flop 26 to its ONE state. The flip-flop 26 conditions either an AND gate 28 or 30 which are simultaneously pulsed at the end of each frame by a signal from clock 31. The outputs of AND gates 28, 30 are supplied to the ONE and ZERO terminals respectively of a Code/No-code flip-flop 34 whose outputs condition either AND gate 20 or AND gate 22. The output from AND gate 30 is also applied to reset the flip-flop. 26. Any output from gate 22 is supplied via an OR gate 40 to the output line 42. A Run-length counter 50 is stepped by pulses from clock 31 in synchronism with the comparisons in EXCLUSIVE OR circuit 14 and has a capacity sufficient to count the comparisons in one frame. Any output from AND gate 20 is supplied via OR gate 46 to reset the counter 50 and cause its contents to be passed via delay line 52 and OR gate 40 to the output line 42, and to cause " Flag " generator 48 to transmit a signal consisting for example of a sequence of two or more bits via Or gate 40 to the output line. The delay 52 ensures that the signal denoting the count of counter 50 follows the " flag" signal. The end-of-frame signal from clock 31 resets counter 18 and through OR gate 46 is applied to counter 50 and generator 48. Before the first frame is transmitted a control signal, e.g. from the earth station, energizes a relay 58 to change over switch contact 13 so that the first frame is transmitted to earth in conventional binary form and stored as a reference frame. For subsequent frames the relay is not energized and contact 13 is as shown. The results of the first scan (frame) are stored in the delay line 16 and are fed into the EXCLUSIVE OR gate 14 in synchronism with the signals comprising the second frame. If there has been no change in the input signals there will be no outputs from gate 14 during the second frame and the end-of-frame pulse from clock 31 will find counter 18 empty, counter 50 full, flip-flop 26 in its ZERO state and flip-flop 34 in its ONE state. The end-of-frame pulse will cause generator 48 to generate a flag signal and will reset counter 50 and its full count will follow the flag signal on the output line, thus indicating to a receiver that there has been no change since the last scan. In the case where there are only a small number of changes between the first and second frames, when the first change appears a signal is produced by gate 14 which finds AND gate 20 conditioned and is passed via OR gate 46 to energize generator 48 to pass a signal to the output line indicating that a change has occurred and to reset counter 50 to pass its count to the output line to indicate at the receiver which bit in the frame has changed. By knowing the previous signal and where in the frame the change has occurred it is possible to determine at the receiver which input signal has changed and by how much. The counter 50 will then start counting again and will count until another signal is provided by gate 14 or until the end of the frame, whichever comes first. Each signal from gate 14 steps the counter 18 one position but since there are only a few changes in the frame it does not reach its full count and flip-flop 26 will remain at ZERO. The end-of-frame pulse operates as before except that a smaller sum will be read out of the counter 50. Assuming that there are a large number of changes in the input signals between two scans each change will cause a signal from gate 14 to pass via gates 20 and 46 to cause a flag signal followed by a binary sequence representing the count of counter 50 to be supplied to output line 42. Each signal from gate 14 is also counted at 18 and when the capacity of the counter is exceeded the flip-flop 26 is transferred to its ONE state. The end-of-frame pulse will find AND gate 30 conditioned and flip-flop 34 will be switched to its ZERO or NO-CODE condition, and flip-flop 26 returned to its ZERO condition. Counters 18 and 50 will be reset as before to cause a flag signal and the count of counter 50 to be applied to the output line 42. The next frame will find AND gate 22 conditioned and the output signals from gate 14 pass directly via OR gate 40 to the output line thus changing from " run length coding " to " direct transmission." A counter similar to counter 18 at the ground station provides information that the changeover has taken place and correct positioning of the " directly transmitted " ONE bits may be ensured by normal synchronizing equipment. During the frame of direct transmission counter 18 is operating and if it exceeds its capacity again the flip-flop 26 will be switched to its ONE state. The end-of-frame pulse will sample AND gates 28 and 30 to determine in which mode the transmitter will operate during the next frame. The circuit may be modified by removing the connection 64 to AND gate 22 and connecting AND gate 22 to the side of the switch 13 feeding gate 14 so that during " direct transmission " the binary signal in its conventional form is transmitted. This has the advantage of updating the data stored at the ground station at random intervals, thus reducing the possibility of errors. A one-frame delay line may be introduced at the point 70, so that at the end of the frame the data passed by the AND gate 20 or 22 is that which caused them to be appropriately conditioned. A modification, Fig. 3 (not shown) is arranged to make use of the fact that the probability of the most significant bit in a particular input signal changing is much lower than the probability of the least significant bit changing. In a further embodiment, Fig. 4 (not shown) the digital signal from each source is preceded by a coded identification signal and a count representing the number of frames in which a signal from a given source has not changed is also transmitted.