baber/WOPTO huggingface dataset:
Patent TW-510043-B (TW)
Title: Semiconductor device
Inventor: HARUHANA HIDEYO
IPC: H01L21/822
Filed: 2001-10-04
Granted: 2002-11-11
Abstract: At least one diffusion region exists between a plurality of resistors formed on an element isolation layer, and the plurality of resistors and the diffusion regions are arranged such that all distances between the respective resistors and the diffusion regions around the corresponding resistors are equal to each other.
Patent TW-518496-B (TW)
Title: Management method and system of delivering goods
Inventor: LIAU YI-MING
IPC: G06Q10/00
Filed: 2001-10-19
Granted: 2003-01-21
Abstract: There are provided a management method of delivering goods and its system for connecting the enterprise partners located at various places to a management system of delivering goods via the Internet, so that the enterprise can control the business track record and surplus flowing through the management system. When receiving a purchasing order from a product order customer side, the management system marks the data of non-local product identification number in the purchasing order to indicat that the product is produced by a third party, and assigns a first partner for receiving the purchasing order data. Next, the purchasing order is stored in a customer purchasing order database of the management system. Then, the management system establishes production order-making data for use as a reference of producing products by the second partner based on the purchasing order data, and stores the same in a production order-making database of the management system for being accessed at any time by the second partner as a reference of producing products, wherein the production order-making data corresponding to each item of purchasing order data has the same non-local product identification number, and the production order-making data comprises a dedicated non-local product identification number, at least one product model code and a production related message of factory for receiving the purchasing order. Next, the second partner responsible for production retrieves the production order-making data from the production order-making database for production. If the production is completed and the product is delivered to the customer, the item of production order-making data related to the delivered product in the production order-making database is deleted. Then, the management system further deletes the item of purchasing order data corresponding to the delivered product in the customer purchasing order database.
Patent TW-531781-B (TW)
Title: Method and apparatus for making an integrated circuit using polarization properties of light
Inventor: WANG RUOPING
IPC: G03F1/30
Filed: 2001-11-26
Granted: 2003-05-11
Abstract: A method and apparatus for making an integrated circuit takes advantage of both polarized and phase shifted light in order to achieve a fine feature. The feature on the integrated circuit is obtained by exposing a first region to light that has a first polarization state, exposing a second portion of the wafer to polarized light in the first polarization state but which is also phase shifted about 180 degrees. A region between the first and second region may be unexposed to light. The region between the first and the second region is the position of the fine feature. In areas where the first region and the second region need to be joined together but no feature is intended to be formed, there is a third region between the first and second regions which is exposed to polarized light that has a second polarization state which is orthogonal to that of the polarized light which exposes the first and second regions. The result is that the boundary between either the first or second region and the third region is fully exposed. Thus there is no artifact or extra feature formed in this boundary area between the first and second regions. Masks are made with corresponding regions to the first, second, and third regions so that the light in these polarized and phase shifted states is properly provided to the integrated circuit.
Patent TW-I248469-B (TW)
Title: Manufacturing method of zinc oxide nanowires
Inventor: TING JYH-MING
IPC: H01L21/285
Filed: 2001-12-25
Granted: 2006-02-01
Abstract: This invention is related to a manufacturing method of zinc oxide nanowires which is mainly related to use a technology of sputter deposition on a copper metallized base material to form zinc oxide nanowires.
Patent TW-584950-B (TW)
Title: Chip packaging structure and process thereof
Inventor: LI JIN-YUAN
IPC: H01L23/498
Filed: 2001-12-31
Granted: 2004-04-21
Abstract: The invention provides a chip packaging structure and process thereof, which is to paste the chip on a ceramic substrate, and form a laminated circuit layer on the chip and ceramic substrate, wherein the laminated circuit layer has an external circuit, which is electrically connected to the metal pad on the chip, and part of the external circuit extends to the area outside the top of the active surface of the chip, so as to fan-out the metal pad of the chip. In addition, the active surface of the chip further has an external circuit and plural active devices, and the signal can be transmitted from the active device to the external circuit through the internal circuit, and further be transmitted from the external circuit to the other active devices through the internal circuit. Furthermore, various chips with the same or different functions can be integrated in the same package, and the chips can be electrically connected through the external circuit.
Patent TW-546657-B (TW)
Title: Semiconductor memory device
Inventor: OKUDA MASAKI
IPC: G06F12/16
Filed: 2002-01-17
Granted: 2003-08-11
Abstract: A semiconductor memory device is capable of simultaneously reading data and refreshing data and checking whether a data restoring function is operating normally. A data inputting circuit receives data inputted from an external circuit. A parity generating circuit generates parity data from the data input from the data inputting circuit. A memory stores the data input from the data inputting circuit and the parity data generated by the parity generating circuit. A refreshing circuit refreshes the memory. A reading circuit reads the data from the memory. A restoring circuit restores data to be refreshed by the refreshing circuit from other data read normally and corresponding parity data, while the reading circuit is reading data. A data outputting circuit outputs the data read by the reading circuit and the data restored by the restoring circuit. A parity outputting circuit directly reads and outputs the parity data stored in the memory.
Patent TW-578290-B (TW)
Title: Electrostatic discharged protection device
Inventor: HOU JIAN-DI
IPC: H01L23/60
Filed: 2002-03-04
Granted: 2004-03-01
Abstract: A kind of electrostatic discharged protection device is revealed in the present invention. The invention includes a silicon-controlled rectifier (SCR), a trigger voltage adjusted network and a maintaining voltage adjusted network. The trigger voltage adjusted network and the maintaining voltage adjusted network are coupled to the SCR. In the invention, it is capable of adjusting the trigger voltage of SCR and the maintaining voltage to change the characteristic relationship between its current versus voltage (I-V) to fulfill specific request of different kinds of chip so as to effectively prevent the chip from being damaged by electrostatic discharge.
Patent TW-564559-B (TW)
Title: Method for fabricating heterojunction bipolar transistors
Inventor: JAGANNATHAN BASANTH
IPC: H01L21/265
Filed: 2002-03-27
Granted: 2003-12-01
Abstract: A method for fabricating a heterojunction bipolar transistor having collector, base and emitter regions is disclosed. In an exemplary embodiment of the invention, the method includes forming a silicon epitaxial layer upon a substrate, the silicon epitaxial layer defining the collector region. An oxide stack is formed upon the silicon epitaxial layer and a nitride layer is then formed upon the oxide stack. Next, an emitter opening is defined within the nitride layer before a base cavity is formed within the oxide stack. The base cavity extends laterally beyond the width of the emitter opening. A silicon-germanium epitaxial layer is grown within the base cavity, the silicon-germanium epitaxial layer defining the base region. Finally, a polysilicon layer is deposited upon said silicon-germanium epitaxial layer, the polysilicon layer defining the emitter region.
Patent TW-I289027-B (TW)
Title: Patterning method
Inventor: KAWASE TAKEO
IPC: H05B33/12
Filed: 2002-04-01
Granted: 2007-10-21
Abstract: A patterning method comprises selectively depositing droplets of a first material solvent solution onto a layer of a second material. The solvent is chosen to dissolve both materials, which are selected so as to exhibit phase separation upon the removal of the solution to provide domains of the first material embedded in and extending through the second material. By selection of appropriate materials the patterning method may be used, for example, to fabricate light emitting devices, optical colour filters, or vertical interconnects in electronic devices.
Patent TW-558808-B (TW)
Title: Chip packaging structure and substrate therein
Inventor: JANG NAI-SHUEN
IPC: H01L23/498
Filed: 2002-05-22
Granted: 2003-10-21
Abstract: The present invention provides a chip packaging structure and substrate therein, in which the power area of the power pin connected to the core of each control unit of the die is at least divided into two parts, and at least a pi-type filter is used to separate different power areas of the substrate, thereby avoiding mutual interference of noise and making the operation of the chip more stable. In addition, the pi-type filter is arranged at a corner connecting two edges on a substrate, so that the circuit layout on te substrate is easier to implement.
Patent TW-564302-B (TW)
Title: Back light unit with high heat transfer rate
Inventor: HSIEH CHIN-KUN
IPC: F21V29/505
Filed: 2002-08-09
Granted: 2003-12-01
Abstract: A back light unit with high heat transfer rate disposed under a display panel is disclosed. The back light unit includes a light source generator for generating light beams, a diffusing plate positioned between the light source generator and the display panel for scattering the light beams to the display panel, and a reflecting sheet position under the light source generator for reflecting the light beams upward. The reflecting sheet has at least one opening for increasing the heat transfer rate of the back light unit.
Patent TW-550803-B (TW)
Title: Method of fabricating deep trench capacitor
Inventor: TSAI HONG-HSIANG
IPC: H01L27/108
Filed: 2002-08-30
Granted: 2003-09-01
Abstract: A method of fabricating a trench capacitor. A substrate is provided. A patterned mask layer to expose a portion of the substrate where a trench is to be formed. The exposed portion of the substrate is etched to form a trench. A conductive diffusion region is formed in the substrate surrounding a lower portion of the trench. A dielectric layer along an inner surface of the trench. The trench is filled with a first doped polysilicon layer. The first doped polysilicon layer and the dielectric layer are etched back to a first depth, so that a first recess is formed on the first doped polysilicon layer to expose an upper portion of the inner sidewall of the trench. A collar dielectric layer is formed on the exposed inner sidewall of the trench. The first recess is filled with a second doped polysilicon layer. The second doped polysilicon layer is etched back to a second depth, so that a second recess is formed on the second doped polysilicon layer to expose a part of the upper portion of the inner sidewall of the trench. The collar dielectric layer is etched until a surface level thereof is lower than a surface level of the second doped polysilicon layer, so that a gap is formed on the collar dielectric layer between the exposed inner sidewall of the trench and the second doped polysilicon layer. The gap is filled with a doped polysilicon layer converted from an undoped polysilicon layer. The patterned mask layer is removed, and a drain region adjacent to the doped polysilicon layer is formed.
Patent TW-I290942-B (TW)
Title: Resin composition, prepreg, laminated board and semiconductor package
Inventor: HOSOMI TAKESHI
IPC: H05K1/03
Filed: 2002-09-02
Granted: 2007-12-11
Abstract: This invention provides a resin composition for forming a prepreg having a flexible characteristics and capable of avoiding a crack. This invention also provides a prepreg having a flexible characteristics and capable of avoiding a crack. The prepreg also has an excellent working processed even when the resin composition contained in the prepreg is not yet cured. The invention further provides a printed circuit bard containing such prepreg. The prepreg is impregnated with the resin composition to form a sheet like prepreg 1, and the resin composition contains a first thermosetting resin, a second thermosetting resin having a weight average molecular weight lower than that of the first thermosetting resin, a hardener, and a filler. The prepreg 1 of this invention is prepared by impregnating the substrate 11 with the above said resin composition. The printed circuit board of this invention is prepared by laminating a metal foil 22 on the above said prepreg, and then the laminate is pressed under heat. The package 3 of this invention is prepared by mounting an IC chip 33 on the prepreg 31 having a metal foil 34 laminated therewith.
Patent TW-586026-B (TW)
Title: Method of coating color filter
Inventor: CHANG CHIH-NENG
IPC: G02B5/23
Filed: 2002-10-09
Granted: 2004-05-01
Abstract: A method of coating a color filer, including the steps of: forming a first photoresist on a substrate, forming at least an alignment pattern and a first color film pattern on the first photoresist by exposure and development process, coating a first dye in the first color film pattern and the alignment pattern, removing the first photoresist, forming a second photoresist on the substrate on which the alignment pattern and the first color film pattern are formed, aligning position using the alignment pattern on the substrate so as to form a second color film pattern on the second photoresist by exposure and development process, coating a second dye in the second color film pattern, and removing the second photoresist.
Patent TW-578180-B (TW)
Title: Sintered metal flakes
Inventor: RASIAH IGNATIUS J
IPC: H01L23/373
Filed: 2002-10-18
Granted: 2004-03-01
Abstract: A porous, flexible, resilient heat transfer material which comprises network of metal flakes. Such heat transfer materials are preferably produced by first forming a conductive paste comprising a volatile organic solvent and conductive metal flakes. The conductive paste is heated to a temperature below the melting point of the metal flakes, thereby evaporating the solvent and sintering the flakes only at their edges. The edges of the flakes are fused to the edges of adjacent flakes such that open pores are defined between at least some of the adjacent flakes, thereby forming a network of metal flakes. This network structure allows the heat transfer material to have a low storage modulus of less than about 10 GPa, while having good electrical resistance properties.
Patent TW-I291033-B (TW)
Title: Battery capacity control method and its device, and capacity control device of a battery for vehicle power
Inventor: OOHORI NORIKO
IPC: B60L11/18
Filed: 2002-10-24
Granted: 2007-12-11
Abstract: To determine a total real capacity of a battery subjected to repeated charging and discharging. A battery capacity control device comprises discharging stop judgement means 11 for detecting a no-load condition of a battery; battery voltage detection means 31 for detecting an open voltage of the battery in a no-load condition detected by the discharging stop judgement means 11; relative capacity calculation means 13 for detecting, from an open voltage, a relative, capacity SOC of the battery 51 corresponding to the open voltage in advance; discharge current integration means 17 for calculating an amount of integrated discharge current of the battery 51 during the time of a load condition before the no-load condition is reached; and total real capacity calculation means 14 for calculating a total real capacity of the battery 51 based on the relative capacity SOC and the amount of integrated discharge current.
Patent TW-I238433-B (TW)
Title: Plasma display panel and method of driving same
Inventor: KOBAYASHI KENICHI
IPC: H04N5/66
Filed: 2002-11-08
Granted: 2005-08-21
Abstract: The present invention provides a plasma display panel and method of driving same. The plasma display panel comprises a selective row electrode Z extending in the row direction in a position between the row electrode pairs (X, Y) adjacent to each other in the column direction, and a discharge device formed by dividing the second transverse wall 15B of the spacer 15 on its surrounding; a display discharge device C1 provided opposite to the transparent electrodes Xa, Ya of paired row electrodes X, Y for realizing a continuous discharge; a reset/address discharge device C2 provided opposite to the selective row electrode Z for performing a reset discharge and an address discharge between the selective row electrode Z and the column electrode D; and a gap r provided for communication between the display discharge device C1 and the reset/address discharge device C2.
Patent TW-I257628-B (TW)
Title: Cascode sense amp and column select circuit and method of operation
Inventor: FLANNAGAN STEPHEN T
IPC: G11C11/419
Filed: 2002-11-28
Granted: 2006-07-01
Abstract: A sense amplifier uses a cascode stage (76 or 100) that receives a predetermined bit line pair differential signal and provides an output. The cascode stage output is coupled to a true and a complement output of the sense amplifier. In one form, a pair of pass transistors (77, 78) and an amplifier (79) are coupled to the cascode stage and to complementary outputs and are controlled by a sense enable signal. The amplifier is operative only when the pair of pass transistors are made nonconductive. In another form, the cascode stage is connected directly to a bit line pair differential signal and to sense nodes (82, 86) that are separately coupled to a data line pair by a coupler (102) and an amplifier (104).
Patent TW-I226259-B (TW)
Title: Process and module for treating a gaseous exhaust containing volatile organic compounds by cyclic adsorption and desorption
Inventor: CHEN JIA-YUAN
IPC: B01D53/02
Filed: 2002-12-11
Granted: 2005-01-11
Abstract: The present invention discloses a module for treating a gaseous exhaust containing volatile organic compounds (VOCs) including an adsorption device and a moving-bed desorption device, which are integrally formed into a module. The adsorption device contains a bag filter and a fluidized adsorbent bed. The module of the present invention has a wide range of operational space velocity, an enhanced capability of VOCs adsorption, and a less complicated pipelining, and thus a reduced operational cost and an easier maintenance. The present invention also discloses a process for treating a gaseous exhaust containing volatile organic compounds (VOCs) by using the module of the present invention.
Patent TW-575946-B (TW)
Title: Non-volatile memory and fabricating method thereof
Inventor: CHANG CHING-YU
IPC: H01L21/8246
Filed: 2002-12-23
Granted: 2004-02-11
Abstract: A method of fabricating a non-volatile memory is provided. A longitudinal strip of stacked layer is formed over a substrate. The longitudinal strip is a stacked layer comprising a gate dielectric layer, a conductive layer and a cap layer. A buried bit line is formed in the substrate on each side of the longitudinal strip. The longitudinal strip is patterned to form a plurality of stacked blocks. Thereafter, a dielectric layer is formed over the substrate. The dielectric layer exposes the cap layer of the stacked blocks. Some cap layers of the stacked blocks are removed to expose the conductive layer underneath. A word line is formed over the dielectric layer to connect stacked blocks in the same row serially together.
Patent TW-I273144-B (TW)
Title: Container for loading solid organic metal compound and method for loading the same
Inventor: TOMIYASU SHIZUO
IPC: C23C16/18
Filed: 2003-01-27
Granted: 2007-02-11
Abstract: A novel loading container can provide a solid organic metal compound at a constant concentration to a gas phase epitaxial growth device such as a MOCVD device, etc. over a long period of time. The invented solid organic metal compound loading container having a carrier gas inlet (2) and a carrier gas outlet (3) is characterized in: dividing the interior of the loading container into a plurality of longitudinal spaces, and using a carrier gas flow direction reversing mechanism (6) to downwardly guide the carrier gas introduced by the carrier gas inlet (2) to each longitudinal space and discharging from the carrier gas outlet (3).
Patent TW-580800-B (TW)
Title: Method and device for adjusting phase of clock signal
Inventor: SHEN RICH
IPC: H03L7/085
Filed: 2003-03-13
Granted: 2004-03-21
Abstract: A method and a device for adjusting phase of clock signal to be applied in a circuit unit with an internal chip allowing clocking between the external and internal clock signal of the chip being performed in a given best made is provided, proceeding contrast between wherein the external and internal clock signals of the chip are compared by dynamic phase shift control module of the circuit unit, and a phase difference between the two signals is provided to design engineers for them to adjust the phase difference to a preferred range. As a result, the clocking is able to be performed in accordance with the best mode as designed, and the integrity of the output signal is to be maintained without occurring any clock skew.
Patent TW-I256390-B (TW)
Title: Nitrogenous heterocyclic compound and pharmaceuticals thereof
Inventor: OZAKI FUMIHIRO
IPC: A61P3/10
Filed: 2003-03-14
Granted: 2006-06-11
Abstract: A compound represented by the general formula (I), a salt thereof, or a hydrate thereof: (I) wherein X1, X2, X3, and X4 each independently means a single bond, or C1-6 alkylene, etc.; A2 means optionally substituted phenyl, etc.; A1 means an optionally substituted group represented by -C(=Q1)- [wherein Q1 means oxygen, sulfur, or a group represented by =N-R11 (wherein R11 means hydrogen or C1-6 alkyl)], and a 5- to 7-membered nitrogenous heterocyclic group, etc.; and Z1 means piperidin-2-yl, etc.
Patent TW-I235401-B (TW)
Title: A method for making a field emission device
Inventor: LIU LIANG
IPC: H01J1/304
Filed: 2003-04-04
Granted: 2005-07-01
Abstract: The present invention relates to a method for making a field emission display device. The method includes the following steps: providing a work plate, depositing gate electrodes at relative areas on the work plate according to predetermined display pixels, forming an insulative film covering the gate electrodes and the work plate, depositing a layer of catalyst on the insulative film, forming barriers of insulative materials on the layer of catalyst according to the predetermined display pixels so that defining separated growing spaces, growing arrays of carbon nanotubes on the layer of catalyst within the growing spaces via CVD method, depositing cathode electrode on the arrays of carbon nanotubes, packaging a base plate with the cathode electrode and removing the work plate, etching the relative areas of the insulative film according to the arrays of carbon nanotubes, and packaging a phosphor having an anode cathode so that forming the field emission display device.