Patent GB-1415091-A (GB)
Title: Aplification of analogue signals prior to analogue-to- digital conversion
IPC: H03M1/40
Filed: 1973-01-09
Abstract: 1415091 Amplifier and analogue to digital converter SOC D'ETUDES BECHERCHES ET CONSTRUCTIONS ELECTRONIQUES 9 Jan 1973 [11 Jan 1972] 1221/73 Heading H3H A system for amplification and analogue to digital conversion with floating point coding comprises an amplifier circuit with a basic gain between input and output, a delay circuit connected with its input to the amplifix output and its output to the amplifix input and a comparator for comparing the amplifier output with a reference. The amplifier may be switched for unity gain, a gain of two or four or to give an output 2U-V where U is the input and V a reference. The comparator may have a positive reference or both a positive and negative reference and preferably also a zero reference. The delay may be a delay line or two capacitors linked in series or parallel by switches and, on amplifier to give unity gain. The amplifier is preferably inserted between two serial capacitors and may be a twin of the amplifier/comparator circuit. Circuit construction. The embodiment shown comprises amplifier 110, comparator 130 and delay 120. The amplifier may have unity gain (S116, S118 and S119 open), a gain of 4 (S116 only closed) or supply a signal equal to 2V E -V 0  (either S118 or S119 closed depending on V E  polarity). The comparator comprises two differential amplifiers C133, C134 with reference voltages VR1 respectively and C133 may also have reference VR 2  = 0. The store comprises capacitors M124, M127 with serial switches S123 and S126 of which one is always open and the other closed. The switches are controlled from sequence controller 180 (shown diagramatically). The input to be digitized is VE fed via switch S150. Operation. (a) Deviation of exponent.-In the example, V 0  and VR1 are 10 volts and VE is 1À5 volt. During an initial period t 0 , S150 is closed and 1À5 volt is applied to the input of amplier which has unity gain. 1À5 volt is applied to capacitor M124 via switch S123. This is then opened, S126 closed, S140 closed and S150 opened (t 1 ) and maintaining 1À5 volt at the amplifier input. At t 2 , S116 closes giving the amplifier a gain of 4 and S123 also closes supplying the 6 volts amplifier output to M124. The comparator produces as 0 output as the 6 volts is less than the 10 volts reference. At t 3  switches S123 and S126 change supplying 6 volts to the amplifier input, the amp. output esceeds 10 volts and saturates and a 1 is generated by the comparator. S123 closes, capacitor M124 saturates and S126 opens. As a 1 output was generated, S126 does not close for the next reading and a 1 is again generated at t 6 . The number of noughts at t 2 , t 4  and t 6  is the value of the exponent. (b) Deviation of sign.-At t s  switches S135 and S137 open and S136 closes making the comparator reference zero. S116 opens bringing the amplifier gain to unity. The amplifier input of the 6 volts in M127 produces an output of 6 volts which produces a 1 from the comparator indicating a positive voltage. (c) Deviation of binary number.-As the number is positive S118 is closed so that the amplifier output is now 2V-10 volts where V is its input. The 6 volt input produces a 22V output (t 9 ) and a 1 from the comparator. The 2V signal is transferred to M124 and then to M127 (t 11 ) and produces -6V at the amplifier output and a 0 output. When the -6V reaches M127 it changes over switches S118 and S119 so that the amplifier output is 2V+10 volts. The resulting -2V generates a 0 output (t 13 ) and the + 6V of the next stage a 1 output (t 15 ). After this step (t 17 ) the switches are returned to their original positions ready for the next cycle. The resulting output is an eight digit number, the first three digits representing the exponent, the next the sign and the last four the number. It is in the form 1À001 2  Î 4<SP>-1</SP> Vref where Vref is 5 volts.