Patent GB-781817-A (GB)
Title: Electrical apparatus for reducing the access time for a storage register
Filed: 1955-07-14
Abstract: 781,817. Digital electric calculating-apparatus; electric digital-data-storage apparatus. NATIONAL CASH REGISTER CO. July 14, 1955 [Aug. 17, 1954], No. 20404/55. Class 106 (1). In an electric data storage apparatus comprising a magnetic drum having storage channels each containing arcs or separate " storage registers," each channel is, provided with a number of equally spaced transducing heads, and the head next to be traversed by a required arc is determined by logical circuiting responsive to signals read from an " arc address " channel on the drum and from a recirculating register in which the address of the required arc is stored. General. The computer described is generally similar to that of Specification 770,952, only the address selection for the magnetic drum store being described in detail. Each of the main memory channels Ch0-Ch9, Fig. 1, of the drum 101 can store 100 words in arcs or " storage registers " defined by consecutive numbers in arc address channel 114, and has ten equally spaced read/record heads HdO-Hd9. Gating circuits 104 enable only one head at a time to be connected to arithmetic unit 103. The drum provides also G and H one-word-length recirculating registers, the recirculating loops including bi-stable trigger circuits or " flip-flops " G1, H1 and a logical diode gating network 137, Fig. 9, in the arithmetic unit. Each word period is divided into eleven groups D0-D10 of four binary digit periods P0-P3 by counters 125, 124 controlled by clock pulses from channel 112. The operating sequence is controlled by a programme counter 105 which steps to the next count or stays in the same condition, at the end of each word period, according to whether flipflop Nd is in its " true " or " false " state. During a " look-up " routine, comprising three programme counter steps such as PC6-PC8, the contents of the storage register defined by an address contained in. the H register is selected and read out to the G register. The routine includes a calculation to select the correct head in accordance with the position of the required storage register on the drum, and a comparison to determine when this storage register has reached the selected head. Word code. Each period D0-D10 within a word contains a decimal digit in the excess three binary code. The word may be a nine-digit decimal number with sign, or a command, Fig. 2, with instruction I, in D10, and addresses ml, m2, m3 in D9-D1 ; each address comprises a two-digit " a " (arc) portion and a one-digit " c " (channel) portion. Head selection. Fig. 6 shows a cross-section of the drum through channel ChO. The winding on each of the heads Hd0-Hd9 is connected between the grid of a triode such as 134 and a line 127 ; only if the latter is marked with a relatively positive potential will the triode be enabled to respond to pulses induced in the winding and thereby produce an output at common point 136 connected through amplifying circuit 128a to memory read flip.flop Me. Only one line is selected by diode matrices controlled by channel and head selector registers 142, 143, Figs. 1 and 9, each comprising four chain-connected flip-flops on which a decimal digit is set up in the excess three code in accordance with the required address previously placed in periods D4-D6 of the H register. The " c " portion in D6 is stepped via H1 directly into 142 (see Fig. 9), while the " a " portion in D4-D5 has the arc address, read from channel 114 by head 115, subtracted therefrom, the output of H1 together with the complementary output Wc<SP>1</SP> of flip-flop Wc being applied to adding circuits including a stepping register of chain-connected flip-flops A13- A16, and a carry storage flip-flop K1. Since only four register flip-flops are provided, only the tens decimal digit of the sum is retained (see line VI of example, Fig. 18) and this sum digit is given the usual correction, according to the excess three code, during period D6 in which the amount in the stepping register (lines VI and VII, Fig. 18) has three (line VIII, Fig. 18) or thirteen added thereto according to whether or not flip-flop K3 has been set by a final carry in K1, flip-flop K2 being used for carry storage. The corrected sum digit (line X, Fig. 18) is passed to register 143, Fig. 9, and in the example of Fig. 18 selects head Hd5 as being the next to sense the required storage register 75. As illustrated in Fig. 18, the heads HdO-Hd9 simultaneously sense every tenth storage register, while the head 115 senses an arc address number one unit more than that assigned to the storage register being sensed by HdO. Read-out comparison. The units digits or D4 portions of the arc addresses from H1 and Wc, Fig. 9, are passed also to comparing circuits which, on disagreement, trigger flip-flop Nd to the false state. However, when these digits agree (e.g. when head 115 senses 25 in Fig. 18 while head Hd5 is sensing 74), flip-flop Nd remains true at the end of the word period, and the programme counter proceeds through a delaying step (PC7) to one (PC8) in which network 137 connects line GO to the output Mc whereby the required word is read out by the selected head to the G-register.