Patent GB-979592-A (GB)
Title: Improvements in or relating to electrical code translator equipment
IPC: H04Q3/00
Filed: 1962-02-12
Abstract: 979,592. Translation circuits. NIPPON ELECTRIC CO. Ltd. Feb. 12, 1962 [Feb. 14, 1961], No. 5307/62. Heading H4K. A translation circuit comprises at least two code expansion circuits, each having an expansion terminal which is marked in accordance with a code applied to input terminals of the circuit, jumper wires interconnecting corresponding expansion terminals and a coincidence circuit connected to said jumper wires to determine when each of the associated terminals is marked; the arrangement being such that translations between codes can be obtained in either direction, by applying a code to be translated to the input terminals of one expansion circuit and applying a succession of codes to the input terminals of the other expansion circuit until coincidence is registered. Fig. 4 illustrates the basic translation circuit, designed for translating one set of two digit numbers into a second set. The tens and units outputs from circuits ASCT, ASCU applied via gating circuits mark a corresponding one of a hundred expansion terminals A00 . . . A99 which are in turn jumpered each to one of one hundred expansion terminals B00 . . . B99 corresponding to the translations. Each of this latter set is similarly connected via gating circuits to the outputs of circuits BSCT, BSCU. The gating circuits are connected to an output terminal Q, so that when circuits BSCU, BSCT are set to the translation of the number registered in ASCT, ASCU and output is obtained which sets the flip-flop FF1. Thus to obtain a translation the circuits BSCU, BSCT may be caused to assume in succession different values of the translation, until the flip-flop is operated. In practice, the duration of this operation is reduced by first causing circuit BSCU to provide outputs on all its leads and stepping the circuit BSCT. When the flip-flop FF1 operates, the cycling of BSCT is stopped, and the outputs on all the leads from BSCU are removed and then BSCU is stepped until the flip-flop FF1 is again operated. The process is reversible, i.e. if instead the translation is fed to BSCU, BSCT, the circuits ASCT, ASCU may be stepped in the same manner to obtain the original number. A single stepping register may be used for determining the translations in either direction. As shown in Fig. 7, numbers requiring translation may be applied either to F1 or F3 according to the required direction of translation and these are applied together with signals from a stepping circuit to a transfer gating circuit TFG. If the translation is in the forward direction lead CH 1 is marked to cause the signals on F1 to be applied to the portion GGA of the circuit and signals from the stepping circuit to GGB. If translation is required in the reverse direction, lead CH 2  is marked to cause signals on F3 to be fed to GGB and signals from the said stepping circuit tolpass to GGA. With the counter FF2, FF3 in the OO position gates g<SP>1</SP>00 . . . g<SP>1</SP>19 energize all the tens and units outputs and the hundreds counter SCH is stepped until FF1 operates to actuate the control circuit CONT which steps the counter FF2, FF3 to the O1 position and stops the stepping of SCH. The counter FF2, FF3 now opens all the gates g<SP>1</SP>00 . . . g<SP>1</SP>09 to energize all the units outputs and SCT is stepped. When FF1 again operates, FF2, FF3 removes all the units outputs and SCU is stepped until FF1 again operates. SCH, SCT, SCU now contains the translation. More than two expansion circuits may be jumpered together, e.g. in order to determine from the directory number of a subscriber, both his equipment number and his class of service; or from an exchange code, both routing information and the identity of free trunks in the wanted outgoing direction. Reference is also made to more complicated systems in which several expansion circuits have thin expansion terminals jumpered together, and whereby different groups may be specified by appropriate marking of the input terminals of some of the expansion circuits, whereby common members of the groups may be determined; and further selection from amongst these common members may be effected using further ones of the expansion circuits.