Patent GB-1086097-A (GB)
Title: Improvements in or relating to tunnel diode circuits
IPC: H03K19/10
Filed: 1964-12-23
Abstract: 1,086,097. Binary adders. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 23, 1964 [Dec. 31, 1963], No. 52301/64. Heading G4A. [Also in Division H3] A logic circuit for providing " sum " and " carry " signals comprises two pairs of seriesconnected tunnel diodes, each pair being joined between power supply terminals, and a plurality of parallel circuit paths connected between the mid-points (nodes) of the two series-pairs and arranged so that current can be selectively drained from one node in accordance with the potential at the other node. In Fig. 13 the tunnel diode pair 28, 29 is biased so that if-the node drain current IT is 0 or 1 unit the diodes will be in the high-voltage state and the output at 52 will be high (representing binary 1); if IT is 2 or 3 units the diodes will be in the lowvoltage state and the output at 52 will be low (representing binary 0). The value of -IT depends on the inputs at X, Y and Z; if these are all zero transistors 54a, 55a and 56a will be cut off and transistors 54b, 55b and 56b will be conducting, providing three units for IT. Each input at X, Y or Z causes the corresponding upper transistor to conduct and the lower to be cut off, reducing I T  by one unit for each input. The output voltage at 52 also operates transister 57b so that the upper transistor 57a conducts for binary 0 at 52 and is cut off for binary 1 at 52; when conducting, transistor 57a contributes 2 units of current to I<SP>1</SP>T in the upper line 59 while the X, Y, Z inputs contribute one unit each. The current I<SP>1</SP>T is therefore the-sum of the complements of the signals at X, Y and Z, together with twice the complement of the signal at 52. The tunnel diode pair 40, 41 is biased to be in the low voltage state if I<SP>1</SP>T is 3 units and the high voltage state if I<SP>1</SP>T is 2 units. Thus the output at 47 is the complement of the binary sum of the signals at X, Y and Z and the output at 52 is the appropriate " carry " signal. The signal at 47 can be invented to obtain the true " sum " signal. if the X, Y, Z signals are applied to the lower transistors of the pairs 54, 55, 56 (Fig. 14, not shown) the output at 47 will be the true sum and the output at 52 will be the complement of the carry signal. This latter output is useful when cascading circuits for a plurality of binary orders. Thus, in an adder for the n order, the input X to transistor 54a is the complement of the carry signal at 52 in the adder for the (n - 1) order (Fig. 15, not shown). Exclusive-OR circuits.-The circuit of Fig. 13 can be modified to provide an Exclusive-OR function (Fig. 16, not shown) by omitting the stage 54 and altering the bias on the diodes. The upper diode pair is biased to give an output 1 if the node drain current is 1 unit and output 0 if the node drain current is 2 units. If the input signals are both zero the stage 57 draws 2 units to provide an output 0. By changing the bias on the lower diode pair also, stage 57 operates to draw 2 units if neither or only one of the X, Y units is present. The output from the upper diode pair is then 1 for a node current drain of 2 units and zero for a node current drain of 3 units. The circuit then produces a negation of the Exclusive-OR function (parity check). Symmetric function logic.-The arrangement of Fig. 13 can also be used to determine whether or not a predetermined number of inputs has a prescribed state (Fig. 23, not shown). Thus, with four signal inputs an output is obtained if only one is in the state 1 but no output if 0, 2, 3 or 4 are in state one. This is achieved by biasing the lower pair of diodes to give an output for 1-4 signal inputs present but not zero input, and biasing the upper pair to give an output for one unit of current but not for 2-4 units. For zero input the stage (86) provides 2 units of current so that no output is obtained. The number of such units provided by stage (86) is varied in accordance with the predetermined number of inputs which is to be detected. This circuit arrangement may be inverted in the same way as Fig. 14 (Fig. 26, not shown). Sum modulo two function.-This function is achieved by providing two cross-coupling stages 86 and 88 (Fig. 29, not shown) which operate in the same way as stage 57 in Fig. 13 but provide different numbers of units of current. With four inputs A, B, C, D a comparison is made between A and B to give a signal if they are different, and another comparison gives a signal if C and D are different. These two signals are then compared and an output is obtained if they are different (Exclusive-OR).