baber/WOPTO huggingface dataset:
Patent TW-578402-B (TW)
Title: Window-based polling scheme for a wireless communications protocol
Inventor: JIANG SAM SHIAW-SHIANG
IPC: H04L12/00
Filed: 2001-04-03
Granted: 2004-03-01
Abstract: A window-based polling scheme for a wireless communication protocol uses a transmitter to transmit the second layer protocol data unit (PDU) containing n-bit sequence number. The polling method comprises the following procedures: obtaining a basis sequence number VT(A) to mark a starting sequence number of one transmission window of transmitter; obtaining the difference between a current sequence number VT(S) and the basis sequence number VT(A) added with 2n to get a first value; dividing the first value by 2n to get the remainder as a second value; dividing the second value by the transmission window length to get a test value; when the test value is greater than or equal to a polling value, activating the polling scheme, wherein the polling value also represents the percentage of PDU transmission progress in the transmitter's transmission window.
Patent TW-473450-B (TW)
Title: Wafer load/unload apparatus
Inventor: SHIE CHANG-YOU
IPC: B65G49/07
Filed: 2001-04-03
Granted: 2002-01-21
Abstract: The present invention relates to a wafer load/unload device especially with fine sensing effect with a plate, which a loading opening is set on and is locked in a workstation; a loading flat building set in the middle part of the plate with a loading base to load a wafer conveying box; a loading opening sheathing set on the loading opening to close with the plate; and a sensor setup on the periphery of the loading opening to sense the reaching correct position of the conveying box and matching the loading opening after loading the wafer conveying box on the loading base.
Patent TW-540152-B (TW)
Title: Semiconductor integrated circuit and design method and manufacturing method of the same
Inventor: SATO MASAYUKI
IPC: H01L21/822
Filed: 2001-04-04
Granted: 2003-07-01
Abstract: A conventional system for testing a semiconductor integrated circuit has a problem that the time required for the test is long, the cost required for the test increases, and yields are reduced due to the occurrence of a failure in a test circuit itself. The invented integrated circuit, in which there are a plurality of programmable logic cells (LCL) having storage elements (MC1 through MC4) and each capable of outputting an arbitrary logic output corresponding to an input according to the information stored in each storage element are spread over areas other than the circuit blocks (CPU, ROM, etc.) on a semiconductor chip without space. Each in-chip circuit block is tested by use of the programmable logic cell.
Patent TW-I272063-B (TW)
Title: Agrochemical preparation for paddy field and method for scattering the same
Inventor: FUJITA SHIGEKI
Filed: 2001-06-04
Granted: 2007-02-01
Abstract: To provide a composition hardly allowing agrochemical active ingredients to stay at the treated point, and having excellent dispersibility in an agrochemical preparation to be scattered by directly thrown in a paddy field in a flooding state, and especially to provide a labor-saving scattered preparation including a liquid agrochemical component at normal temperature, and the agrochemical preparation including the agrochemical component liquid at the normal temperature in high concentration, which are conventionally difficult. This agrochemical preparation for the paddy field is characterized in that a granular composition obtained by allowing the agrochemical active ingredient liquid at the normal temperature, a surfactant and a material exhibiting thickening or gelatinizing activities in water, to be carried by a granular cores, is folded in a bag of a water-soluble film. The method for scattering the agrochemical active ingredient comprises directly throwing 2-20 pieces of the agrochemical preparation per 10 a in the paddy field in the flooding state.
Patent TW-501345-B (TW)
Title: Timing difference division circuit and signal controlling method and apparatus
Inventor: SAEKI TAKANORI
IPC: H03K5/13
Filed: 2001-04-17
Granted: 2002-09-01
Abstract: The subject of the present invention is to provide a timing difference division circuit with a high operating speed, a small area, and assuring broadband operation. The invention includes a logic circuit L1, which generates and outputs the first gate signal and the second gate signal based on the first input signal and the second input signal; the first switch element, which is connected across the first power source and an inner node, and has a control terminal where the first gate signal is inputted; the first series circuit, which is formed by the second switch element and the first constant current source; and the second series circuit, which is formed by the third switch element and the second constant current source. The first and the second series circuits are connected in parallel across the inner node and the second power source. The first and the second gate signals are connected to the control terminals of the second and third switches, respectively. The circuit also includes a plurality of MOS capacitors, in which the connection of the MOS capacitors to the inner node is separately controlled by a control signal. The input terminal of the buffer circuit is connected to the said inner node, the output signal value of a buffer circuit is determined according to the inner node potential and the magnitude of the threshold voltage. The overlap period during which the first and the second gate signals outputted from the logic circuit are both activated to turn on the second and the third switch elements can be adjusted freely.
Patent TW-565928-B (TW)
Title: Electrostatic discharge protection circuit using Zener diode
Inventor: TANG TIAN-HAU
IPC: H01L23/60
Filed: 2001-05-23
Granted: 2003-12-11
Abstract: A kind of electrostatic discharge (ESD) protection circuit device structure and its manufacturing method are revealed in the present invention, in which the ESD protection circuit device structure is under a bonding pad for protecting the internal circuit. The ESD protection circuit device has a bonding pad contact via under the bonding pad and includes a semiconductor substrate having a P-well and an N-well, in which a boundary is formed between the P-well and the N-well. A predetermined region and the bonding pad contact via are selected in the substrate; and the first, the second and the third shallow trench isolation structures are formed in the bonding pad contact via. An n-type doped region is formed in P-well and N-well, respectively. The first and the second p-type doped regions are formed in P-well and the N-well, respectively. The first Zener diode is formed in the N-well and the second Zener diode is formed in the P-well.
Patent TW-530275-B (TW)
Title: Display panel having sustain electrodes and sustain circuit
Inventor: DERKSEN SANDER
IPC: G09G3/296
Filed: 2001-06-06
Granted: 2003-05-01
Abstract: A display device comprises groups of scan electrodes (X1, X2) and groups of sustain electrodes (Y1-Y2) forming groups of electrode pairs (X1-Y1, X1-Y2, X2-Y1, X2-Y2). The sustain discharge for at least one of these groups occur at a different time than for at least one other group. The currents during sustain discharge are then distributed in time, reducing the peak heights and reducing losses and stray electromagnetic radiation.
Patent TW-I226915-B (TW)
Title: Process for sizing paper
Inventor: LINDGREN ERIK
IPC: D21H17/14
Filed: 2001-07-31
Granted: 2005-01-21
Abstract: A process for sizing paper comprising adding to an aqueous suspension containing cellulosic fibres, and optional fillers, an anionic or cationic sizing dispersion, and a sizing promoter comprising a cationic polymer having an aromatic group; and an anionic polymer having an aromatic group selected from step-growth polymers, polysaccharides and naturally occurring aromatic polymers, wherein the sizing dispersion and sizing promoter are added separately to the aqueous suspension.
Patent TW-552779-B (TW)
Title: A method and an apparatus for granting use of a session of a packet data transmission standard designated by an identifier
Inventor: BENDER PAUL E
IPC: H04L12/56
Filed: 2001-08-14
Granted: 2003-09-11
Abstract: A method and an apparatus granting a terminal, which requests a communication with a network access server using a session of a standard for packet data transmission designated by an identifier, use of the requested session, when a security association between the access terminal and the network access server is verified.
Patent TW-548630-B (TW)
Title: System and method for automatic voice recognition using mapping
Inventor: QI YINGYONG
IPC: G10L15/12
Filed: 2001-09-07
Granted: 2003-08-21
Abstract: A method and system that combines voice recognition engines 104, 106, 108, 112, 114 and resolves differences between the results of individual voice recognition engines 104, 106, 108, 112, 114 using a mapping function. Speaker independent voice recognition engines 104 and speaker-dependent voice recognition engines 106 are combined. Hidden Markov model (HMM) engines 108, 114 and dynamic time warping (DTW) engines 104, 106, 112 are combined.
Patent TW-563104-B (TW)
Title: Extractive multiple CD collection box
Inventor: SHIE JIN-MING
IPC: G11B33/00
Filed: 2001-09-13
Granted: 2003-11-21
Abstract: A kind of extractive multiple CD collection box comprises: at least one drawer with a bottom support body and a pillar, in which the bottom support body has a bottom support body surface and the pillar is located on the bottom support body surface; and a drawer carrier with a hollow portion, a first opening and a corresponding second opening, in which the hollow portion is located between the first opening and the second opening, the hollow portion penetrates through the first opening and the second opening of the drawer carrier and the drawer can be inserted to the hollow portion from the first opening or the second opening of the drawer carrier.
Patent TW-536918-B (TW)
Title: Method to increase the temporal resolution of continuous image series
Inventor: SHIU JIUN-WEN
IPC: H03M13/00
Filed: 2001-11-01
Granted: 2003-06-11
Abstract: A method to increase the temporal resolution of continuous image series is disclosed, which comprises: selecting a first viewing frame in the continuous image series which is divided into plural blocks according to a preset value; select a second viewing frame in the continuous image series; searching for the most similar block in the second viewing frame as the corresponding block; calculating the motion vector in the first viewing frame and the second frame; calculating the motion vector obtained to estimate the pixel value of the corresponding block in the first viewing frame and the second viewing frame at a certain time, and assembling the estimated block pixel value to generate a reconstruction viewing frame; applying a median value filtering process to the reconstruction viewing frame; applying a spatial low-pass filtering process to the reconstruction viewing frame after the median value filtering process.
Patent TW-583318-B (TW)
Title: Iron golf club head material
Inventor: LEE HOU-TENG
IPC: C22C38/18
Filed: 2001-11-08
Granted: 2004-04-11
Abstract: An iron golf club head material comprises C, Si, Mn, Cu, Ni, Cr, Mo, and Fe according to their percentages. The Mo element with a specific percentage content increases the mechanical properties, low temperature heat treatment conditions, and electroplating properties of the material.
Patent TW-520524-B (TW)
Title: Semiconductor device and method for the fabrication
Inventor: INBE TAKASHI
IPC: H01L27/148
Filed: 2001-11-23
Granted: 2003-02-11
Abstract: The object of the present invention is to provide a semiconductor device and its fabrication method that is suitable for neutron detection with small-size and less cost. A semiconductor integrated device includes a boron containing layer 4 containing an isotope 10B formed on a semiconductor substrate 1. Neutrons irradiated to the boron containing layer 4 are brought into a reaction with the isotope 10B to emit Α rays which are then rushed into the semiconductor substrate 1 to generate electron-positive hole pairs 8 in a P-N junction layer. Thus, neutrons are detected.
Patent TW-522664-B (TW)
Title: Rake receiver
Inventor: ALI DANISH
IPC: H04B1/707
Filed: 2001-11-23
Granted: 2003-03-01
Abstract: A Rake receiver suitable for receiving, for example, direct sequence CDMA signals, in which the pilot code used to correlate the received signal in each Rake finger (RF1, RF2, RFN) is interpolated prior to the correlation.
Patent TW-I281734-B (TW)
Title: Wafer level chip-scale package and manufacturing method thereof
Inventor: BAIK HYUNG-GIL
IPC: H01L23/28
Filed: 2001-12-17
Granted: 2007-05-21
Abstract: A wafer level chip scale package and a method for manufacturing the same are provided to easily control the thickness of a metal wire and to simplify manufacturing processes without using a sputtering by forming a glue layer between a substrate and the metal wire. A semiconductor chip (200) has a plurality of chip pads (202). A metal wire (209) is formed on the semiconductor chip (200) and has an opening (214) for exposing the chip pad (202) and a ball land (210). A glue layer (206) is formed between the semiconductor chip (200) and the metal wire (209). A conductive layer (216) is filled in the opening (214) so as to electrically connect with the chip pad (202) and the metal wire (209). A molding body (230) is covered to the metal wire and the conductive layer, and exposed the ball land (210). A conductive ball (220) is formed on the exposed ball land and mounted on a substrate (240).
Patent TW-535074-B (TW)
Title: Information provider device, information provider system and advertising method
Inventor: KUNIKIYO TATSUYA
IPC: G06Q30/02
Filed: 2001-12-19
Granted: 2003-06-01
Abstract: A server or a standalone-type computer stores graphical information on a structure of a semiconductor device (CP1) and information on IP of function block or a semiconductor manufacturing apparatus (IF2) and outputs these informations linked to each other. Further, it is designed that an information terminal can access the server through a network to purchase the IP, a recipe of the semiconductor manufacturing apparatus, other softwares and the like through electronic commerce. Furthermore, an advertising agency operates the server and advertising expenditure and IP royalty are exchanged among a maker of semiconductor device, an IP vender and a vender of semiconductor manufacturing apparatus. Thus, an information provider device and an information provider system for providing the information on the structure of the semiconductor device and the information on design, which allows specific grasp of an image of applying the IP and the semiconductor manufacturing apparatus to actual manufacture of the semiconductor device, can be achieved, and an advertising method which ensures a high advertising effect can be provided.
Patent TW-I243171-B (TW)
Title: Process for making substituted 8-arylquinolinium benzenesulfonate
Inventor: DESMOND RICHARD
IPC: A61P11/00
Filed: 2001-12-19
Granted: 2005-11-11
Abstract: A substituted 8-aryl quinoline and its benzenesulfonic acid salt is synthesized. A method of forming a reaction product mixture substantially containing formula, said method comprising: reacting formula, with in the presence of an effective amount of an initiator.
Patent TW-517417-B (TW)
Title: Spatially modulated reflector for an optoelectronic device
Inventor: MORGAN ROBERT A
IPC: H01S5/028
Filed: 2001-12-28
Granted: 2003-01-11
Abstract: Improved resonant reflectors (54, 70, 90) are provided for increased mode control of optoelectronic devices (10). Some of the resonant reflectors (54, 70) provide improved mode control while not requiring significant additional processing steps, making them ideal for commercial applications. Other resonant reflectors (90) reduce or eliminate abrupt changes in the reflectively of the resonant reflector (90) across an optical cavity of an optoelectronic device (10), allowing them to reduce or eliminate undesirable diffraction effects that are common in many resonant reflectors.
Patent TW-548857-B (TW)
Title: A light-emitting semiconductor device with a surface-mounted and flip-chip structure
Inventor: LIN MING-DER
IPC: H01L33/00
Filed: 2002-02-08
Granted: 2003-08-21
Abstract: A light-emitting semiconductor device with a surface-mounted and flip-chip structure is disclosed. The light-emitting semiconductor device includes an insulation substrate and a LED. The insulation substrate is equipped with two electrode layers. The two electrode layers are disposed on the two sidewalls of the insulation substrate respectively and each extends toward the upper and lower surface of the insulation substrate. The LED includes a transparent substrate, a first type semiconductor layer, a second type semiconductor layer, a plurality of first ohmic electrode points, a plurality of second ohmic electrode points, a reflective metal layer, an insulation layer, a first solder bump and a second solder bump. The invention is characterized in that the light-emitting semiconductor device is possessed with better ohmic contact by utilizing the plural first and second electrode points. Besides, the light-emitting semiconductor device has higher brightness because the LED is installed onto the insulation substrate with flip-chip packaging method. Moreover, the LED can be installed onto the electrode layers of the insulation substrate with surface-mounted method through the first solder bump and the second solder bump.
Patent TW-544604-B (TW)
Title: Derivation method of equivalent circuit model for passive element, simulator and storage medium
Inventor: MAESHIMA HIROYUKI
IPC: G06F17/50
Filed: 2002-02-26
Granted: 2003-08-01
Abstract: This invention relates to a derivation method of equivalent circuit model for passive elements which comprises: a first step of inputting a frequency characteristic provided by a condenser; a second step of using any one of RC circuit, RL circuit and RCL circuit that can be simulated in the time domain and in which the resistance (R), capacitance (C), inductance (L) are independent from the frequency to form an equivalent circuit model; a third step of synthesizing evaluation function for judging the accuracy of the equivalent circuit model formed in the second step; and a fourth step of minimizing the synthesized evaluation function to determine the circuit constant, a simulator based on the method, and a storage medium stored with a computer readable program. By using a common procedure independent from the kind of the passive elements, the equivalent circuit model that can be simulated can be derived in the time domain.
Patent TW-546623-B (TW)
Title: Amplitude varying circuit
Inventor: TOBITA YOUICHI
IPC: H03K19/00
Filed: 2002-03-12
Granted: 2003-08-11
Abstract: The invention provides an amplitude varying circuit, wherein the voltage level converter (3) comprises the first and second P-type TFT (5, 6) and the first and second N-type TFT (7, 8) which are used to latch the voltage level of first and second output nodes (N5, N6); the third and fourth N-type TFT (9, 10) which are used to set the voltage level of first and second output nodes; and the first and second impedance components (11, 12) and the first and the second capacitors (13, 14) which are used to separately apply the voltage (6V) which is higher than the amplitude voltage (3V) of input signal (VI) to the gate and source of third and the fourth N-type TFT (9, 10) in response to the upward and downward edges of input signal (VI).
Patent TW-567413-B (TW)
Title: Apparatus, method and computer program product for privatizing operating system data
Inventor: MATHEWS THOMAS STANLEY
IPC: G06F9/50
Filed: 2002-03-12
Granted: 2003-12-21
Abstract: The present invention provides an apparatus, method and computer program product for privatizing operating system data. With the apparatus, method and computer program product of the present invention, a block of memory is allocated and divided into identical, smaller, properly aligned storage areas, each dedicated to a single processor in a multiprocessor system. The storage areas are allocated either initially when the system is initialized or on an as needed basis. Each sub-allocation request is made to use storage at the same location relative to the start of that processor's storage space. Because each processor's storage is isomorphic to all other processors, only one allocation record for all processors is needed, thereby reducing the overhead of the data privatization scheme. By allocating memory in this manner, cache line contention is minimized.
Patent TW-563286-B (TW)
Title: Power generating system
Inventor: NAKATA JOSUKE
IPC: G05F1/67
Filed: 2002-04-03
Granted: 2003-11-21
Abstract: A power generating system 1 is provided with a power generator 2 for generating DC power, and a converter circuit 3 for converting DC power into AC power, in which the power generator 2 has a plurality of power generating modules 21 to 28 each comprising plural power generating units 30. A plurality of the first switch means S11 to 17 for connecting/separating the positive electrodes 62 of plural power generating modules 21 to 28 with/from a positive bus 6 are disposed. A plurality of the second switch means S11 to 17 for connecting/separating the positive electrodes 62 of plural power generating modules 21 to 28 with/from the negative electrodes 60 of the power generating modules 21 to 27 contiguous to one side are disposed. A plurality of the third switch means S1 to 7 for connecting/separating the negative electrodes 60 of plural power generating modules 21 to 27 with/from a negative bus 7 are disposed such that DC output voltage can be increased/decreased stepwise by changing the switch means S1 to S7, S11 to 17.
Patent TW-I224353-B (TW)
Title: Semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions
Inventor: KRISHNAN SRINATH
IPC: H01L29/45
Filed: 2002-04-10
Granted: 2004-11-21
Abstract: A semiconductor-on-insulator (SOI) device (10). The SOI device includes a semiconductor substrate layer (18); an insulator layer (16) disposed on the substrate layer; a semiconductor active region (19) disposed on the insulator layer, the active region including a source (20), a drain (22), and a body (24) disposed therebetween, at least one of the source and the drain forming a hyperabrupt junction (40, 42) with the body; and a gate (46) disposed on the body such that the gate, source, drain and body are operatively arranged to form a transistor. The at least one of the source and drain forming the hyperabrupt junction with the body includes a silicide region (54, 56). The silicide region has a generally vertical interface (70, 74), which is laterally spaced apart from the hyperabrupt junction by about 60 Å to about 150 Å.