Patent GB-832370-A (GB)
Title: Improvements in or relating to systems for translating the individual digits of decimal numbers from a first notation to a second notation
IPC: H04Q3/42
Filed: 1957-02-21
Abstract: 832,370. Electric selective signalling systems. SIEMENS & HALSKE A.G. Feb. 21, 1957 [March 6, 1956], No. 5944/57. Class 40 (1). [Also in Groups XIX and XXXIX] In a system for translating the individual digits of a decimal member from a first to a second notation, an electrical pulse train representing each digit in the first notation is applied to a first register in which the digit is stored in elements each of which has a number of states equal to the radix of the first notation, and the digit is transferred from the first register to a second register whose storage elements each have a number of states equal to the radix of the second notation, an electrical pulse train representing. the digit in the second notation being derived from the second register. In the code-translator shown, which forms part of a telecommunication system, the digits of a decimal number are entered each in binary-coded serial form and read out in pulse-number-coded form. When the translator is ready to receive a decimal digit, a voice frequency pulse is sent to a preceding exchange over conductors aI, bI. The exchange sends the digit in the form of binary-coded pulses on conductors aII, bII, " 0 " and " 1 " being represented by two different voice frequencies which operate through a tone-discriminating receiver to cause energization of relays Ja, Jb and relay Ja alone respectively. Where Ja only is energized, one of relays Ya, Yb, Yc, Yd (corresponding to 1, 2, 4, 8 respectively) is operated through contacts of the J-relays and of sequencing relays X1, X3, whereby the X-relays register the entered digit in binary form. At completion of the entry, relays Q, Qh are energized whereby a further pulse is sent over aI, bI and a pulse is applied to the primary I of a saturable core transformer EU. The secondary is split into sections 1-6 which are selectively brought into circuit by Y-relay contacts so that for each decimal digit value, an output pulse of corresponding amplitude is obtained at xx and applied through shifted contacts 56q, 57m1 to a coil on storage element Z1 comprising a magnetic core having a substantially rectangular hysteresis loop and magnetizable in steps from a zero saturation condition. The succeeding decimal digits are similarly set up on the Y-relays and passed to magnetic storage elements Z2-Z10 which are selected in turn under control of contacts of sequence relays M1-M9 (Fig. 1b, not shown). The storage elements are similarly selected for read-out, by contacts of sequence relays N1-N8 (not shown). The selected element is read out by applying thereto uniform-amplitude stepping down pulses via transformer AU and relay E under control of a self-interrupting relay which applies a corresponding number of pulses to an output line (not shown). When the element is restored to' its zero saturation condition it presents a low impedance so that E is energized to interrupt the production of pulses. A time lag determined by the discharge of a capacitor is introduced between read-out of successive storage elements. The magnetic cores may be replaced by capacitor storage elements, a digit value being represented by the magnitude of charge.