Patent GB-947770-A (GB)
Title: Transistor having a thin base region
Inventor: STEVENSON ALDEN
IPC: H01L29/00
Filed: 1960-05-05
Abstract: 947,770. Transistors. PACIFIC SEMI-CONDUCTORS Inc. May 5, 1960, No. 15950/60. Heading H1K. In a transistor in which the base comprises first and second contiguous regions of like conductivity type, the first base region being thinner and of lower impurity concentration than the second base region, and the first base region forming junctions with emitter and collector regions, the centre planes of the first and second base regions extend perpendicular to the path of minority carriers between emitter and collector and are spaced from one another longitudinally of said path. As shown, Fig. 3, a wafer of N-type silicon has an N+ region 21 formed within its periphery by any known method. As described, a number of wafers in a quartz boat and a crucible containing phosphorus pentoxide are heated together in a quartz tube, the temperature distribution along which is about 1300‹ C. at the wafers, and 400‹ C. at the phosphorus pentoxide. Nitrogen is passed through the tube for the first 15 minutes during which time phosphorus pentoxide vaporizes and deposits on the wafers, phosphorus diffuses into the wafers, and a vitreous coating 24, probably of phosphorus pentoxide and silicon dioxide, forms on the surface of the wafers. Next, oxygen is passed through the tube for about 17 hours, during which time the formation of the vitreous coating and the diffusion of phosphorus into the wafers continue. When cool, each wafer is lapped and etched down to the out line in Fig. 3 to expose the original N-type region 22, Fig. 5, in which a P+ region 26 is now formed by heating the wafers and a supply of boron trioxide together to a temperature around 1200‹ C. in an atmosphere of wet nitrogen for about 1¢ hours; the vitrous coating 24 masks the N+ region 21 against boron diffusion, and a second vitreous coating 27, probably of boron trioxide and silicon dioxide, is formed around the whole wafer. The whole bottom surface 31 and part of the top surface 30 of the wafer are covered in etch-resistant wax and the wafer is immersed in a mixture of hydrofluoric acid, nitric acid, and acetic acid for about 20 seconds to form a step in the top surface 30, Fig. 6, and to expose a portion of the N-type region 22. Preferably, the vitreous coatings are removed by etching in pure hydrofluoric acid prior to the main etching step. A P-type base region 41, Fig. 8, thinner than P+ region 26 with which it is contiguous, is formed in the newly exposed portion by a two-step diffusion process; a plurality of wafers are placed upon a flat of quartz or silicon &c. in a boat, the open top of which is closed by a quartz plate having a film of boron trioxide deposited over its lower surface, and heated to about 950‹ C. in a nitrogen atmosphere for 30 minutes; boron trioxide deposits on the wafers, a vitreous coating is formed, and some diffusion in of boron occurs. When cool, the vitreous coating is removed with hydrofluoric acid and the wafers are re-heated in an atmosphere of wet oxygen or wet hydrogen to around 1100‹ C. for 2 hours to effect diffusion in of excess boron from the surface of the silicon, a new vitreous coating of silicon dioxide being formed around the wafer ; in this way the surface concentration of boron is reduced to, at the most, 5 x 10<SP>18</SP> atoms/c.o. The vitreous coating is next removed from part of the base region, the silicon below which is converted to N-type to form an emitter region 43, by diffusing in phosphorus from a phosphorus pentoxide source at 1100‹ C. for ten minutes. Electrodes are connected to the base region 41 via P+ region 26, and to the emitter region 43, while a broad contact is made to the collector region 22 via N + region 21. Modifications.-In Fig. 11, the thin base region 51 and the emitter region 50 occupy a central hollow region within the collector 53, while in Fig. 12, they are formed around an upstanding central portion 67 of the collector 63 on which is located the thicker base contact region 66. The invention is applicable also to PNP transistors, in which case surface concentration of phosphorus on the base region may be limited by the two step diffusion process, and to transistors comprising an intrinsic region.