Patent GB-985535-A (GB)
Title: Apparatus and method for testing an electronic device
IPC: G01R31/26
Filed: 1962-04-12
Abstract: 985, 535. Testing transistors; time interval measurements. SPERRY RAND CORPORATION. April 12, 1962 [June 30, 1961], No.14195/62. Heading G1U. Apparatus for testing an electronic discharge device to determine whether the changeover time from a first to a second operational state is within or without a predetermined time interval, applies a first timed impulse to the device to indicate the changeover, senses the changeover in means providing a signal in completion, and applies a second impulse time displaced from the first impulse to the signal producing means, whereby the appearance of the signal indicates changeover within the predetermined time interval, and absence of such signal indicates the reverse. In Fig. 1 a timing chain including inverters 10, 12, 14 and a tapped delay line 16 has a recirculation connection 18 from the output of 16 to the input of 10 so that a single pulse fed in at 20 provides a cyclically repetitive train of timing signals. The leading edge of a pulse A (Fig. 2) appears at the output 22 of inverter 12 at time T 0 , and the leading edge of an inverted pulse B appears at time T 1  at a variable tap 26 of the delay line. The leading edge of inverted pulse C appears at time T 2  at variable tap 30 and similarly the trailing edge of inverted pulse D appears at time T 4  at a third variable tap 32 of the delay time. The leading edge of inverted pulse E appears at time T 5  at the output 36 of inverter 10. This series of signals is repeated cyclically. A transistor under test is connected in test circuit 42, and conduction control circuit 24 responsive to pulses A and C is triggered at time T 0  to drive the transistor base to initiate conduction from cutoff to a first threshold. A sensing signal arises at the collector after a time delay and trips rise trigger 28 to develop a signal at 48 unless pulse B at time T 1  occurs before the rise, when the rise trigger is disabled and no output is developed; thus indicating an unacceptable response time of the transistor. The critical time (T 1  - T 0 ) depends on the adjustment of tap 26. Pulse C at T 2  intermediate of T 1  and T 3  drives the conduction control circuit 24 to initiate a high level of conduction, and the trailing edge of pulse A at T 3  drives the control circuit to indicate return of the transistor to cutoff. A sensing signal arising at the collector after a time delay trips fall trigger 34 to develop a signal at 50 unless pulse D at time T 4  occurs before cutoff, when the fall trigger is disabled and no output is developed; thus indicating a further unsatisfactory response time. The critical time (T 4  - T 3 ) again depends on the adjustment of tap 32 of the delay line. An output signal for trigger 28 turns over flip-flop 38 to produce a signal at 52 and a similar output for fall trigger 34 turns over flip-flop 40 to provide inputs to AND gate 56, so that on presence of both outputs for correct transistor response accept indicator 62 is operated and reject indicator 64 is disabled. Absence of one or both signals leaves indicator 64 operated. A single indicator may be used instead. After indication, pulse E at time T 5  resets the flip-flops. Repetitive tests may be performed on a single transistor to raise its internal temperature and thus to test it over a higher duty cycle. A further AND gate may be connected in the recirculation path opened by the output of AND circuit 54, so that a single failure to meet an acceptable response time specification arrests the test cycle and indicates unacceptability. The testing circuit elements are fully transistorized and detailed circuits are given (Figs. 3, 3A not shown).