Patent SG-11201900913V-A (SG)
Title: Defect marking for semiconductor wafer inspection
Inventor: SHORTT DAVID W
IPC: H01L21/67
Filed: 2017-09-26
Abstract: COMPUTING SYSTEM 130 12 COMPUTING SYSTEM 143 144 INSPECTION TOOL 100 135 MATERIAL REMOVAL TOOL 141 146 DEFECT VERIFICATION TOOL 142 MARKING TOOL 120 149 103 WAFER POSITIONING SYSTEM 114 WAFER POSITIONING SYSTEM 147 r r 1-1 N 71- O O GC O 1-1 C (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 05 April 2018 (05.04.2018) WIP0 I PCT olimion °nolo omoiloomonminio oimIE (10) International Publication Number WO 2018/064072 Al (51) International Patent Classification: HOlL 21/66 (2006.01) HOlL 21/67 (2006.01) (21) International Application Number: PCT/US2017/053540 (22) International Filing Date: 26 September 2017 (26.09.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 62/400,182 27 September 2016 (27.09.2016) US 15/430,817 13 February 2017 (13.02.2017) US (71) Applicant: KLA-TENCOR CORPORATION [US/US]; Legal Department, One Technology Drive, Milpitas, Cali- fornia 95035 (US). (72) Inventors: SHORTT, David W.; 116 Campos Verde, Los Gatos, California 95032 (US). LANGE, Steven R; 51 In- cline Green Lane, Alamo, California 94507 (US). WEI, Junwei; 1102 S. Abel Street, Unit 236, Milpitas, Califor- nia 95035 (US). KAPP, Daniel; 1921 Greenwood Road, Pleasanton, California 94566 (US). AMSDEN, Charles; 37139 Denning Terrace, Apt 398, Fremont, California 94536 (US). (74) Agent: MCANDREWS, Kevin et al.; KLA-Tencor Corp., Legal Department, One Technology Drive, Milpitas, Cali- fornia 95035 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, (54) Title: DEFECT MARKING FOR SEMICONDUCTOR WAFER INSPECTION 150 170 FIG. 1 (57) : Methods and systems for accurately locating buried defects previously detected by an inspection system are described herein. A physical mark is made on the surface of a wafer near a buried defect detected by an inspection system. In addition, the inspection system accurately measures the distance between the detected defect and the physical mark in at least two dimensions. The wafer, an indication of the nominal location of the mark, and an indication of the distance between the detected defect and the mark are transferred to a material removal tool. The material removal tool (e.g., a focused ion beam (FIB) machining tool) removes material from the surface of the wafer above the buried defect until the buried defect is made visible to an electron-beam based measurement system. The electron-beam based measurement system is subsequently employed to further analyze the defect. [Continued on next page] WO 2018/064072 Al 11111111111111111110111111111110111110100111011101M011111111111111111110111111111111 KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))