Patent GB-992516-A (GB)
Title: Data memory system
IPC: G11C29/00
Filed: 1962-09-11
Abstract: 992, 516. Data storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 11, 1962 [Sept. 18, 1961], No. 34718/62. Heading G4C. When a word is read from a store 20 to a register 22, its parity is checked before being passed to a utilization device 28. If the check shows an error, the word is corrected and is stored at an auxiliary address in the memory. The auxiliary address is stored at the original address if this is possible, otherwise the auxiliary address is stored with the original address in a location in a matching register. The auxiliary and matching registers are parts of the main memory, being defined only by the addresses allotted to them. Each word in memory comprises twenty bits: sixteen data bits, two parity bits and two error bits. If the error bits are both zero the word has previously been found to be effective and may contain the auxiliary address at which the correct word is now stored, or may contain defective information in which case reference to the matching register is necessary. Read operation. The address is set in memory address register 23 and is sent to the addressing circuit 21, after which the word required is read out to register 22. Assume that at least one of the error bits in the word is a binary one. The word is then sent to parity checking circuits 27 which if no error is detected transmit it to the device 28. If an error is found the word is sent to the correcting device 29 which is not described in detail but which causes the word to be corrected either automatically or by the operator. When this is done device 29 emits a signal initiating the safe storage of the corrected word and its new address. The corrected word is returned to register 22 and an address set up on counter 30 is entered in alternate address register 31. The error bits positions in register 22 are both set to one. The word in register 22 is read into memory at the address specified by register 31. The contents of the spare address counter are then sent to the left and right halves of register 22 via gate 62 and cables 22A, 22B. Bits 32, 33 of register 22 are set to zero. Register 22 is then read into the original storage location, the address of which is still in register 23, and after a short delay is read back into register 22. A parity check is made in circuits 41, 42 of the two halves of register 22. If the parity of at least one of the halves is correct it is known that the auxiliary address is safely stored at the original address, and the operation concludes by reading the original data from the axiliary address, still in register 31, to register 22, and advancing counter 30. If the parities are both wrong the address in counter 30 is entered in the left half of register 22 and the address in register 23, the original address, in the right half of register 22. An address is supplied to selection circuits 21 from matching register controls 40 and register 22 read into this address. Finally, the data word is read from the auxiliary address to register 22. If, on reading a word into register 22 it is found that the error bits are both zero, the parities of the two halves of the word are checked in circuits 41, 42. If the parity of one of the halves is correct, the address contained in that half is sent to address register 31 and the required data word is read into register 22. If neither parity is correct the address in the memory address register 23 is sent to a comparison circuit 50. Under the control of circuits 40 the words in the matching register are sequentially read out to register 22 and their right half compared with the address in the comparison circuit. When equality is found, the left half of the word then in register 22 is the required auxiliary address. To reduce the chance of a long search the first matching register address read out is the last one to have been used. Alternatively,the matching register could be an associative circuit in which a substantially immediate comparison of the contents of all locations can be made. When a new word is to be written into memory, the contents of the location into which it is to be written are first read out to register 22. If both error bits are zero, the above procedure is then followed to allot an auxiliary address to the word.