baber/WOPTO huggingface dataset:
Patent JP-H0333434-A (JP)
Title: Engine vibration reducing device
Inventor: KUMANO SHOHEI
IPC: F02B77/00
Filed: 1989-06-30
Abstract: PURPOSE:To reduce vibration by supporting a plurality of auxiliary units with a low rigidity supporting bracket in such a way as adjoining to the front of an engine in the direction up and down, and coupling adjoining auxiliary units through a coupling part made from vibro-suppressive steel plates which admits relative movement. CONSTITUTION:At the front of an engine A, a plurality of auxiliary units (aux. generator 1 and airconditioning compressor 2) are installed with the aid of low rigidity brackets 5a, 5b, and 6 and driven by a crank pulley 4 and a belt 3. The generators 1 and compressors 2 are surrounded by a common coupling member 8 made from vibro-suppressing steel plates alongside the contour. This coupling member 8 consists of an outer steel plate 8a, middle visco-elastic layer 8c, and inner steel plate 8b. The outer steel plate 8a is fixed to the generator 1 with bolt 5a1 while the inner steel plate 8b fixed at the end to the compressors 2 with bolts 63, 64. In the middle part, the outer steel plate 8a is secured to the generators 1 with bolts S1, S2 through a circular opening while the inner steel plate 8b secured to the compressors 2 with bolts S3, S4. Thus the generators 1 permit relative movement of the compressors 2. This prevents superposition of resonance, and vibrations will be reduced.
Patent JP-S6228861-A (JP)
Title: Data transfer system
Inventor: MIYATA KENJI
IPC: G06F13/28
Filed: 1985-07-30
Abstract: PURPOSE:To improve the efficiency of data transfer by transferring data stored in a host computer to an external device at a DMA transfer speed of the host computer. CONSTITUTION:When a DMA request signal is transmitted from a central processing means 9 in the external device 2 to a central processing means 3 in the host computer 1 through a control bus 6, the means 3 ends a job in executing and opens a data bus 4 and an address bus 5. A DMA checking signal is outputted from a DMA control means 8 to the bus 6 and inputted to the gate of a three-state buffer 12 and a read signal and a write signal are transmitted to a memory 7 and a buffer memory 10 respectively. At that time, data to be transferred to the data bus 4 are outputted and transferred and stored to/in one specified address in the buffer memory 10. Thereby, data transfer can be executed at the DMA transfer speed of the computer 1 independently of the data processing speed of the external device 2.
Patent JP-2001001042-A (JP)
Title: Die for micro-crystallizing grain size
Inventor: MIMAKI TAKUO
IPC: B21C23/00
Filed: 1999-06-16
Abstract: PROBLEM TO BE SOLVED: To provide a die used for micro-crystallizing grain size of a metal work by an ECAP method which is easy in manufacture and withstandable against the extruding pressure of the metal work. SOLUTION: In the die for micro-crystallizing the grain size of a work metal by extruding the metal work through a passage of a die having a tunnel-like extrusion passage in which an inlet side straight passage is connected to an outlet side straight passage at a bend part, and applying the large shear strain in the work metal, the die 1 is of the two-split structure, grooves 21, 21a to divide a passage 11 into two sections at the plane including the axis of the extrusion passage 11 are formed on butting surfaces of both die halves 2, 2a, and bend parts of the grooves 21, 21a of the die halves 2, 2a are formed on a cemented carbide.
Patent JP-H0334362-A (JP)
Title: Monolithic integrated circuit
Inventor: ARA YOICHI
IPC: H01L27/06
Filed: 1989-06-29
Abstract: PURPOSE:To enable a monolithic integrated circuit to be possessed of properties such as a required gain, a required output power, and the like without any additional component externally fitted by a method wherein a resistor formed under the same condition with the active layer of a field effect transistor is added to the bias decision resistor of the field effect transistor. CONSTITUTION:An N channel field effect transistor 1 and resistors 2, 3, and 4 which directly determine a gate bias are formed on the same substrate through an ion implantation technique respectively to constitute a monolithic integrated circuit, where the field effect transistor 1 is made to operate in such a state that its source is grounded and its drain electrode is connected to a positive voltage power source 5, the first gate bias decision resistor 2 formed under a usual resistor ion implantation condition is connected to the positive voltage power source 5 and the gate electrode of the field effect transistor 1, the second gate bias decision resistor 3 is connected to the gate electrode and a negative power source 6, and the third resistor 4 formed under the same condition with the active layer of the electric field effect transistor 1 at the same time is connected with the second transistor 3 in parallel. By this setup, when a manufactured electric field effect transistor varies in direct current characteristic, a bias decision resistor formed under the same condition with the active layer of the electric field transistor also varies characteristics in the same direction with the transistor so that a monolithic integrated circuit of this design can be restrained, from deviating from a drain current set on design.
Patent JP-H0672538-A (JP)
Title: Cargo carriage escalator system
Inventor: GYODA KAZUO
IPC: B65G47/57
Filed: 1993-06-15
Abstract: PURPOSE:To improve efficiency of an escalator for cargo carriage by transferring and placing a cargo safely, speedily and highly efficiently on a movable step provided on a wrapping link continuously driven. CONSTITUTION:Transportation of a cargo is carried out between upper and lower frames LS, US by driving an endless chain 13 with steps 3 to place the cargo by a motor, and simultaneously, smooth transfer and placing of the cargo is carried out between the steps 3 by providing an endless chain driven by the motor so as to transfer the cargo at roughly the same speed as the endless chain 13 on the upper and lower frames LS, US.
Patent JP-H0334581-A (JP)
Title: Nonvolatile semiconductor storage device and manufacture thereof
Inventor: ENDO TETSUO
IPC: G11C16/04
Filed: 1989-06-30
Abstract: PURPOSE:To enlarge the coupling capacity between a floating gate and a control gate so as to realize high integration by putting the floating gate, which is formed through the first gate insulating film on a semiconductor substrate, in the shape that it has a cavity inside, and providing a control gate so that it may oppose the inner face and the outer face through the second gate insulat ing film. CONSTITUTION:A hole 10 is opened at the top of a floating gate 5, and the second insulating film 6 is formed at the inner face and the outer face of the floating gate 5. A control gate 7 consists of the part buried inside the floating gate 5 and the part laminated outside, and these are connected in a body through the hole 10. That is, the control gate 7 is so formed as to oppose the inner face and the outer face of the floating gate 5 through the second gate insulating film 6. N<+>-type diffusion layers 8 and 9 to become a drain and a source are formed in a substrate with these gate regions in between. The float ing gates 5 are independently provided in every memory, and the control gates 7 are arranged continuously in common to memory cells usually in one direction thereby constituting a word line.
Patent JP-S6147561-A (JP)
Title: Sample preparation apparatus for analysis on o2 in steel
Inventor: TAKAHASHI TAKAMASA
IPC: G01N1/32
Filed: 1984-08-14
Abstract: PURPOSE:To enable simultaneous and quick preparation of a plurality of samples through electropolishing, by immersing an anode securely housing a plurality of samples into and withdrawing them from an electrolytic tank and a washing tank sequentially with a driver operated by a timer. CONSTITUTION:An anode 1 comprises a shaft rod section 2 and a circular shallow dish-shaped sample housing section 3 and the sample housing section 3 is divided with a radial partition 4 to house 12 samples 23 at a time with a net 5 applied on the bottom surface thereof. A cylindrical platinum or copper cathode 13 is placed in a glass electrolytic tank 12. A drive motor 10 for moving an anode support 7 vertically and a drive motor for rotating a turntable 17 are connected to a constant current power source 20 and operated according to the setting of a timer 19. Washing tanks 14, 15 and 16 are moved to the upper part of an ultrasonic oscillator 21 to perform an ultrasonic washing. An air blowing port 22 is provided surrounding the anode support 7 to dry the sample by air.
Patent JP-S6147519-A (JP)
Title: Optical fiber transmission type weight measuring apparatus
Inventor: YAMASHITA SHIGEYUKI
IPC: G01G19/18
Filed: 1984-08-14
Abstract: PURPOSE:To inhibit various noise from invading into a signal transmission line and to attain to enhance a S/N ratio, by attaching only a sensor part in the vicinity of the hook of a crane cable and connecting the sensor part and a main body by an optical fiber but not by a conductive wire. CONSTITUTION:A sensor part consists of two sensors, that is, load cells 4, an accelometer 5, preamplifiers PAM1, PAM2 respectively amplifying the output signals thereof and a transmission unit TU. A main body consists a receiving unit RU which receives the optical digital signal transmitted from the transmission unit TU through an optical fiber 12 and demodulates signals corresponding to the outputs of the load cells 4 and the accelometer 5, preamplifiers AMP1, AMP2 respectively amplifying the signals corresponding to the outputs of the load cells 4 and the accelometer 5, a divider circuit DIV for calculating the ratio of the outputs of the load cells 4 and a divider circuit output circuit OC. When the signals respectively corresponding to the outputs of the load cells 4 and the output of the accelometer 5 are sent from the transmission unit to the receiving unit as optical digital signals, two signals can be discriminated by a usual method.
Patent JP-S6061994-A (JP)
Title: Control circuit of dynamic memory
Inventor: YANAGI TOSHIO
IPC: G11C11/34
Filed: 1983-09-14
Abstract: PURPOSE:To prevent reduction of the processing speed of a data processor by performing a data refresh action of a memory block at the other side in the same memory cycle of the other memory block while an access is given to either one of even and odd memory blocks. CONSTITUTION:The least significant bit address 35 among addresses of an address bus 13 is set at level ''0'', and a row address strobe signal 19 given from a timing generating circuit 15 is lowered down to level ''0''. Under such conditions, memory blocks 24 and 25 of the ven side receive accesses to a request given from a processor 11 and perform the transfer of data with a data bus 14 via data buses 29 and 30. For memory blocks 26 and 27 of the odd side, an address which is designated by a refresh address address 75 is refreshed since the supply is inhibited for a column address strobe signal 39 by an NAND gate 34. When the address 35 is set at level ''1'', the data receives an access at blocks 26 and 27. Then the data is refreshed at blocks 24 and 25.
Patent JP-H0923525-A (JP)
Title: Method and tool for processing terminal of woven type shielded cable
Inventor: WATANABE KUNIHIKO
IPC: H02G1/14
Filed: 1995-07-05
Abstract: PROBLEM TO BE SOLVED: To adapt the terminal processing of a cable to its automatization, by opening expansively the opening end edge of the woven sheath of the cable through a pressurized air before inserting a needle into the woven sheath, and by performing thereafter the inserting of the needle from the opening end edge opened expansively. SOLUTION: A step of disposing the end of a needle 11 of a terminal processing tool 10 concentrically with a shielded cable 1 to oppose it to an opening end edge 3A of a woven sheath 3, a step of feeding a pressurized air from a pressuerized-air feeding source to the inside of the needle 11 via its air connection port, a step of rolling up the woven sheath 3 ranging from an end surface 21A of a clamping member 21 to its end to open expansively the opening end edge 3A of the woven sheath 3, a step of inserting in this state the needle 11 in between a conductor 2 of the cable 1 and the woven sheath 3, a step of releasing the clamping of the woven sheath 3 by the clamping member 21 to continue the inserting of the needle 11, and a step of inserting smoothly a taper portion 11B of the needle 11 in between the conductor 2 and the woven sheath 3 are provided respectively. Thereby, the terminal processing of the shielded cable 1 can be performed automatically.
Patent JP-S6149284-A (JP)
Title: Optical character reading device
Inventor: TOYODA TAKETO
IPC: G06K9/03
Filed: 1984-08-16
Abstract: PURPOSE:To enable to execute an efficient optical character reading work by one person by printing in parallel image data and recognition data of character data written in a document. CONSTITUTION:Character data 5 written on a document 4 are irradiated by a lamp 6 and converted to an electric signal by a scanner 7. Here, the character data 5 is scanned electrically in the horizontal direction like a facsimile and scanned by transportation of the document as shown by an arrow mark 8 in the longitudinal direction. Image data 2 of the character data converted to the electric signal are accumulated in an image buffer 9 for a prescribed line number (minimum one line) only. The image data 2 are fetched into a character recognizing unit 10, the character data 5 is recognized and the data 2 is also fetched into a controller 11. The controller 11 outputs the image data 2 together with a recognizing data 3 to a printer 12. Then, the printer 12 prints the image data 2 and the recognizing data 3 on a printing paper.
Patent JP-H0866110-A (JP)
Title: Riding-type rice transplanter
Inventor: NAKA HIROKAZU
IPC: A01B63/10
Filed: 1995-07-05
Abstract: PURPOSE: To provide a riding-type rice transplanter having a small-sized controller capable of performing precise rolling control. CONSTITUTION: An output of a rolling motion mechanism 38 which is placed roughly above a rolling shaft core is connected to one end of each of left and right springs 39, which are placed in left-and-right direction of a seedling table 19, and one of the left and right supporting bodies is connected to the other end. The front view of a seedling transplanting apparatus 17, the left and right springs 39a and the left and right supporting bodies forms a quadrilateral frame. The upside of the front-view quadrilateral frame consisting of the output of the rolling motion mechanism 38 and the left and right springs 39a is slid in left-and-right direction to perform a rolling motion of the seedling transplanting apparatus 17.
Patent JP-H0521290-A (JP)
Title: Solid electrolytic capacitor
Inventor: KURANUKI KENJI
IPC: H01G9/15
Filed: 1991-07-10
Abstract: PURPOSE:To provide a solid electrolytic capacitor which can be applied to various electronic apparatuses, can withstand a thermal shock applied to the capacitor especially at the time of surface mounting and, further, has excellent solderability and high reliability. CONSTITUTION:A capacitor element 21 and parts of a lead frame 22 are covered with molding resin to form a solid electrolytic capacitor. Solder alloy layers or tin metal layers having copper metal layers as foundation layers are formed on the surfaces of the parts of the lead frame 22 which are not brought into contact with the molding resin and only the copper metal layers are formed on the surfaces of the lead frame 22 which are brought into contact with the molding resin and, further, the surface is roughed.
Patent JP-H089917-A (JP)
Title: Production of nonfreezing fruit
Inventor: KOREEDA SABURO
IPC: A23L19/00
Filed: 1994-06-29
Abstract: PURPOSE:To produce a nonfreezing fruit which keeps texture, taste and flavor same as those of naturally fresh fruits by impregnating the fruit with saccharides and alcohol without destruction of the fruit tissue. CONSTITUTION:A natural fruit is soaked in n aqueous solution containing saccharides and alcohol, deaerated under a reduced pressure and the solution is concentrated under heating until the concentration of the total saccharides reaches the Brix degree of 115-80 degrees, and the pressure is restored to normal whereby the nonfreezing fruits are obtained.
Patent JP-S6230970-A (JP)
Title: Semiconductor measuring apparatus
Inventor: NAGASE MASASHI
IPC: G01R31/26
Filed: 1985-08-01
Abstract: PURPOSE:To achieve a higher measuring accuracy, by changing the combination of cable blocks according to the procedure computed according to the type of semiconductors to be measured to complete connection between a socket board and a pin electronics board. CONSTITUTION:Connection information from a data input circuit 57 is inputted to be stored into a memory circuit 66 temporarily. Then, an arithmetic control circuit 68 determines the procedure for shifting a cable block 41 from a block fixing frame 34 to frame 35 based on wiring information of the cable block 41 stored in the frame 34 for storage and array information of the block 41 to be stored into the cable block fixing frame 35 for measurement in transit memorized in the circuit 66, the procedure for avoidance of entanglement of a cable 40 in transit of the block 41 and collision with a transfer mechanism memorized in a memory circuit 67 and the like. According to the results, step ping motors 71A 71J are controlled to shift the combination of the block 41 according to the type of an IC31 to be measured. This enables the connection for a higher measuring accuracy.
Patent JP-S5793728-A (JP)
Title: Semiconductor switch
Inventor: MUKAI KANJI
IPC: H03K17/16
Filed: 1980-12-02
Abstract: PURPOSE:To prevent malfunction due to voltage with steep leading edge applied across a switch, by short-circuiting a PN junction of a thyristor at two parts of P and N gates of the thyristor. CONSTITUTION:When a voltage with steep leading edge is applied to an anode terminal 11, a current flows through an emitter-base junction of a transistor(TR) 7 and a capacitor 8. This current flows to the base of a TR9 to short-circuit a P gate and a cathode of a thyristor 10 and at the same time short-circuite an N gate and an anode of the thyristor 10 by the TR7.
Patent JP-H0810724-A (JP)
Title: Washing device
Inventor: HAMADA MAKOTO
IPC: B05B1/20
Filed: 1994-06-29
Abstract: PURPOSE:To enable an operator to efficiently carry out a washing operation without moving the operating position in the case of washing of the outside peripheries of objects to be washed. CONSTITUTION:Plural washing water ejection holes which eject washing water into the closed space formed by closing two pieces of freely openably and closably disposed hollow pipes 27 are formed at the front end of a washing nozzle supporting part 26. As a result, an insulator 41 is positioned into the closed space formed when the hollow pipes 27 are actuated to be closed by actuating the hollow pipes 27 to open. The washing water is ejected from the washing water ejection holes by supplying the washing water from a washing water supplying source 24 in the closed state, by which the outer peripheries of the insulators 41 are simultaneously washed.
Patent JP-S6058957-A (JP)
Inventor: RUDORUFU BURATSUTONAA
IPC: C07C303/32
Filed: 1984-08-16
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H0729029-A (JP)
Title: Parallel address generation device using three-dimensional digital differential analyzer
Inventor: KATAYAMA YOICHI
IPC: G06T13/80
Filed: 1993-07-09
Abstract: PURPOSE:To realize three-dimensional DDA and a parallel processing by realizing two-dimensional DDA on planes which are mutually orthogonal by connecting two stage pipe lines. CONSTITUTION:Data is linearly read from a three-dimensional memory 31 by the address of an address generation circuit 11 executing two-dimensional DDA. Data is written into three-dimensional memories 32, 33 or 34 and 35 in a second stage, which have double buffer constitution. Data is linearly read by the addresses which a two-dimensional DDA generation circuit 12 or 13 in the second stage gives to the three-dimensional memories 32 and 34 or 35 and 36 in the same way as the three-dimensional memory 31 and data are transferred to a data bus 43. Multiplexers 61-63 connected to the data bus 43 respectively fetch data of calculation areas of which they themselves take charge in accordance with the address generation circuits 13-15 and they process data by processors 70-72. Thus, three-dimensional DDA is continuously processed in parallel.
Patent JP-H0726940-A (JP)
Title: Exhaust emission control device
Inventor: TANIGUCHI HIROYUKI
IPC: F02B3/06
Filed: 1993-07-09
Abstract: PURPOSE:To prevent the regeneration rate of a filter from varying due to variation in applied voltage, by controlling the duty rate of current for energizing electrically heating means for regenerating the filter in accordance with a detected voltage and a detected current so as to set the power for carrying current to the electrically heating means to a predetermined desired power value. CONSTITUTION:Particulate in exhaust gas discharged from a Diesel-engine 20 are trapped by a filter 2. Pressures of the exhaust gas upstream and downstream from the filter 2 are detected by pressure sensors 7, 17, and the volume of trapped particulate is calculated from the result of the detection and outputs from an engine speed sensor 8 and an exhaust gas temperature sensor 6. If the calculated value exceeds a threshold value, the filter is regenerated. That is, a blower 13 is driven so as to feed air into the filter 2 while a heater 11 is energized so s to burn the particulate. Further, at this time, the duty rate of current for energizing the heater 11 is controlled in accordance with outputs from voltage detecting means 58 and current detecting means 59 so as to set the power energizing the heater 11 to a predetermined desired power value, thereby it is possible to restrain the heating value from varying.
Patent JP-H0816568-A (JP)
Title: Character code assigning method
Inventor: KOUNO MASANORI
IPC: G06F17/21
Filed: 1994-06-29
Abstract: PURPOSE:To reduce the data quantity of a character string by expressing a HIRAGANA (cursive form of Japanese syllabary) by a few number of bit. CONSTITUTION:The most significant bit of a character code is detected (1), 1-byte is detected when the bit is 0 (2), and whether the character code is a control code or not is discriminated (3). In the case of the control code, a mode is switched to the mode showing the control code (4), 1-byte of the next character code is detected (5) and a character is outputted (6). When the character code is not the control code, the character is outputted by the present mode (6), whether the next character code exists or not is detected (7), the step is returned to a step 1 if the code exists and the step is terminated if the code does not exist. When the most significant bit is 1, whether the mode is the HIRAGANA mode or not is discriminated (8). When the mode is not the HIRAGANA mode, the mode is changed to the HIRAGANA mode (9), the character codes corresponding to 2-bytes are detected (10) and a KANJI (Chinese character) showen by the character codes of 2-bytes is outputtedthe step is returned to the step 1 if the code exists and the step isterminated if the code does not exist.