Patent GB-861125-A (GB)
Title: Improvements in or relating to electric and circuits
Inventor: WRIGHT ESMOND PHILIP GOODWIN
IPC: H03K3/45
Filed: 1956-03-23
Abstract: 861,125. Circuits employing bi-stable magnetic elements. STANDARD TELEPHONES & CABLES Ltd. March 22, 1957 [March 23, 1956], No. 36216/60. Divided out of 861,124. Class 40 (9). [Also in Group XIX] A circuit having an overall AND function comprises an OR gate having inverter circuits connected to its output and to each of its inputs. Gates. A magnetic AND gate is shown in Fig. 3 which comprises input windings A1-A4, a common bias and control winding B and an output winding C, the characteristics of the applied pulses being shown at A and B in Fig. 6. A represents the cumulative effect of the input pulses while B illustrates the bias and control pulses, the magnitude of the bias pulse being such that the simultaneous application of input pulses on all the windings A1-A4 is necessary to set the core. The core is reset by a control pulse of over-riding magnitude which establishes an output pulse in winding C. The same pulsing sequence is applied to a magnetic OR gate, Fig. 7, comprising cores 10, 11, 12, each having a separate input winding A1, A2, A3, the magnitude of any input pulse being sufficient to overcome the bias and set the associated core. Frequency division. A two column pulserepetition-frequency divider is shown in Fig. 9, comprising a magnetic matrix store having two column wires A, B and row wires 1, 2, 3, 4 ... N. Each row is scanned in turn by an access selector (not shown) which applies a read-out pulse followed by a half-write pulse. To start the circuit, a half-write pulse is applied to the two column wires A and B by an amplifier W. The start is random with respect to the access selector, so that the first half-write pulse from selector will register a " 1 " in column A in the row being scanned at that time. As the halfwrite pulse to column B is impeded by a delay circuit D, registration in this column is not effected until the next row is scanned. The read-out circuit comprises a number of the monostable triggers shown in Fig. 10 which operate as inverter amplifiers AR, AW, BR, BW and OW in association with magnetic gates AG, BG and SG. The gates are arranged to be changed from one magnetic state to the other by a pulse in winding i, while a pulse in winding w restores them to their initial state and at the same time generates suitable output pulses in windings e and q. An overall AND circuit is provided by the gates AG, BG and inverters AR, BR and OW. Each row is interrogated in turn by the access selector, and the information read out is applied over inverter amplifiers AR, BR to gates AG, BG which produce an output pulse whenever an " 0 " registration is detected. The information read out in column A is restored in the same row by an inverter amplifier AW. On the other hand, a registration detected in a row in column B is re-registered in the next row over a circuit comprising an amplifier and delay device AD, gate SG and an inverter amplifier BW. A number of reading and writing cycles must therefore take place before a " 1 " registration in column B is stepped to the same row as the " 1 " registration in column A. At this point the read-out operation produces no output pulse from either of the gates AG, BG so that an effective pulse output is provided by an inverter amplifier OW. Monostable trigger circuits. Each inverter amplifier may comprise the monostable trigger circuit shown in Fig. 10. The trigger circuit may receive its input signal from the output winding C of a magnetic gate and is subjected to control pulses at +V, an input pulse causing a transistor T1 to conduct so that a core F1 is set by current in a winding W1. As each control pulse acts in winding W2 to reset the core, an output pulse is induced in winding W3 which disables a transistor T2 in the circuit between the control pulse source and output TRA so that an output pulse is obtained only in the absence of an input pulse. Specification 760,048 is referred to.