Patent GB-1275984-A (GB)
Title: Clock synchronizing arrangement for cooperative collision avoidance system
IPC: G01S11/08
Filed: 1969-11-07
Abstract: 1275984 Aircraft collision avoidance system BENDIX CORP 7 Nov 1969 [3 Dec 1968] 54564/69 Heading H4D Relates to a clock synchronizing arrangement for a co-operative radio aircraft collision avoidance system (CAS) of the type in which each participating station (fixed or mobile) carries a clock unit comprising a clock counter 22 and slot counter 40, Fig. 3, whose time cycle comprises repeating epochs of three seconds duration, each epoch comprising 2,000 time slots each of duration 1500 Ás and the time cycles of all the stations being maintained in absolute synchronism with a standard (socalled world-wide) time cycle by means of a two-speed sync. counter 24 capable of counting at a rate of 5 MHz or 10 MHz.  As described each station transmits a coded epoch-start signal ES at the commencement of each locally defined epoch and each aircraft is allotted a unique own time slot during which it transmits: (1) a so-called Doppler-burst range signal comprising a 200 Ás RF pulse commencing 15 Ás after the start of the own slot period as shown in Fig. 1, the time of reception of said range signal at another station giving the distance between the two stations (i.e. one-way ranging), and (2) other flight data signals, e.g. altitude and altitude rate, for use in a known manner by other participating aircraft to evaluate collision threats. A unique RF frequency may be assigned to each time slot as described in Specification 1,194,470. During certain specified epochs a particular aircraft (designated a request aircraft) uses its Dopplerburst range signal as a sync. request signal SR to synchronize its clock unit with that of another station (designated donor station). The operation of the invention is described with reference to Figs. 1 and 2, the times shown therein (expressed in micro seconds, Ás) being slot time at the donor station. In a normal sync. mode, Fig. 1, the sync counter 24 at the request aircraft starts counting at the 5 MHz rate on completion of the sync. request signal SR (i.e. at local slot time 215 Ás) and the donor sync. counter 24 starts counting at the 10 MHz rate at its local slot time 15 Ás and then changes to the 5 Hz rate on receipt of the sync. request signal SR. When the donor count reaches a predetermined value 7021, the donor station transmits a coded sync. response signal SRp which is received by the request aircraft and changes the counting rate of the request sync. counter to 10 MHz such that, provided any time difference error #t between the time cycles of the two stations is less than a predetermined value #T, the request sync. counter always reaches a predetermined count of 6725 at a time instant 1500 Ás after commencement of the donor time slot regardless of the distance between the two stations and at said instant the sync. counter 24 produces a clock reset pulse CRP which resets the clock counter 22 at the request aircraft so that the next time slot is synchronized with the donor station time cycle. Fig. 1 shows the situation when the time cycles of the two stations are synchronized in which case the sync. response signal SRp is received at the request aircraft at a predetermined time interval of 1440 Ás after the start of its own time slot; it can be shown that for a timing error of #t, the time of reception at the request aircraft of the sync. response signal SRp lags or leads the 1440 Ás local time point by 2#t and this error is automatically corrected by the subsequent higher counting rate (10 MHz) of the request sync. counter. When a request aircraft first enters a CAS zone, coarse synchronization is effected ((standby mode) operation) by the epoch start signals ES from other synchronized stations in the zone but if the distance of the entering aircraft from the nearest synchronized (donor) station is such that the resultant time lag error #t exceeds the allowable value #T as shown in Fig. 2A then: (1) the time cycle of the request aircraft is advanced by a predetermined time interval, e.g. 600 Ás, so that it now leads the donor time cycle, see Fig. 2B, (2) the duration of the own time slot is doubled, and (3) the count number in the request sync. counter 24 producing the clock reset pulse CRP is increased from 6725 to 21,725 by an amount 15,000 corresponding to one slot period at the 10 MHz counting rate. In this mode of operation the sync. response signal SRp produced at the donor station during one time slot is received at the request aircraft during the next donor time slot and the clock reset pulse  CRP is produced at the end of said next donor time slot. Detailed operation.-The operation of Fig. 3 is described as used at the request aircraft. In the normal sync. mode, during each own slot the sync. counter 24 is started at local slot time 215 Ás by a start signal SS from the clock counter 22 and the slot counter 40 produces an own slot signal OSS which enables: (1) a gate 42 to apply a sync. request trigger SRT from the clock counter 22 to the transmitter, and (2) a gate 12a to apply the decoded sync. response signal SRp from a decoder 12 to change the counting speed of the sync. counter 24 (from 5 MHz to 10 MHz), the clock counter 22 being reset by the reset pulse CRP from the sync. counter 24 when the count therein reaches 6725. The sync. response signal SRp also turns OFF a normally ON first bi-stable latch 16 (see below). If no sync. response signals SRp are received within a predetermined period, a timer 20 resets and stops the clock counter 22 and slot counter 40; the system then operates in the standby mode. During the standby mode coarse (epoch) synchronization is effected by applying a decoded received epoch-start signal ES from a decoder 10 to start the clock counter 22 and to trigger a second bi-stable latch 18 to produce a first trial signal TS1 on output line 18a which enables a gate 26. If sync. response signals SRp are then received, fine synchronization is effected as described above but if no sync. response signal is received (i.e. #t>#T, see above) the sync. counter 24 does not change speed and when it reaches its final count of 6725 it produces an output control signal CS on line 24b which passes through the enabled gate 26 to again rest and stop the counters 22 and 40. When the next epoch-start signal ES is received it again restarts the counters 22, 24 and also triggers the second bi-stable latch 18 to produce a second trial signal TS2 on output line 18b which enables a gate 27 so that if again no sync. response signal SRp is received then the output control signal CS from the sync. counter 24 on line 24b passes through the gate 27 to: (1) advance the clock counter 22 by a number of counts corresponding to 600 Ás thereby ensuring reception of a subsequent sync. response signal SRp as described above, and (2) trigger a third bi-stable latch 32 to enable gates 28 and 29. Clock counter 22 when advanced ignores subsequent epoch-start signals and the next (time advanced) own slot signal OSS on line 40a passes through the enabled gate 29 to: (1) the sync. counter 24 to increase the final count number therein from 672 to 21725, (2) the clock counter 22 to double the duration of the own slot periods, and (3) enable gates 36 and 38 so that the subsequent sync. response signal SRp from the decoder 12 and the sync. counter final output control signal CS on line 24b each advance the slot counter 40 by one count to compensate for the loss of two slot counts from the clock oscillator 22 due to the 600 Ás advance and the lengthening of the own slot period. If no sync. response signal SRp is received during the extended own slot then the control signal CS from the sync. counter 24 passes through the gates 28 and 30 to reset the counters 22, 40 and disable the latch 32 thereby returning the system to the condition that existed when the latch 18 first generated the second trial signal TS2; hence the system will alternately seek to obtain synchronization at standard range and at extended range. Any circuit delays, e.g. in the decoders 10 and 12, may be compensated by suitably biasing the counters 22, 23, 40.