Patent GB-1342493-A (GB)
Title: Calculator apparatus
IPC: G06F15/00
Filed: 1971-02-18
Abstract: 1342493 Calculators COMPUTER DESIGN CORP 18 Feb 1971 4948/71 Heading G4A An electronic calculator includes a keyboard 60 (Figs. 1, 9), an instruction register 66 and a compiler 62, the latter including two registers 268, 272, multibit data entered using the keyboard being initially fed into register 268 and then in dependence on the type of key operated the data is either fed directly to the instruction register 66 (if for example a reset, function or print key is operated) or transferred to register 272 (if for example the "equal" key is pressed) or register 272 is read out (if for example addition or multiplication keys are operated). When numeric data is entered a third register 276 is used, a generic numeric entry code being entered into the register and shifted out to the instruction register. Flags 266 are selectively set in dependence on the keys actuated. The locic controlling the read out from the registers is designed so that the compiler converts input data in algebraic notation into Polish notation. The calculator also includes a display or print unit 90, an accumulator shift register 24, an entry shift register 26 and a bank of shift registers constituting the calculator memory, an adder 34 having an input from the accumulator register 24 and a second input which may be selectively coupled to any of the other registers. Each register comprises a 68 bit shift register serially connected to a four bit register, data being stored in binary-coded decimal form with 15 four bit digits for the mantissa, 2 digits for the exponent and a further digit for the mantissa and exponent signs. The registers are split into two portions since the other requires four bits of a binary coded decimal digit to perform an operation resulting in a four bit delay. The calculator is controlled both by data entered from the keyboard and from a program read-only memory 70. The instructions may be of three types-address modification, data modifications and control instructions, the latter controlling such operations as the setting of the flag.  Address modification. - Normally address counter 74 for the program read only memory 70 is incremented by one (by a unit 82, Fig. 4, not shown) at each instruction. When however the instruction represents a branch, the address in the counter 74 is incremented and held in a last in-first out type store 80 and the new address for the instruction register is entered into the counter. At the end of the branch routine the last entered address in the store 80 is recalled. When the instruction represents a skip the program counter 74 is incremented by two. Data address modification instructions.-These identify a location in memory 52 to cause serial read out of a 22 bit control word of which 9 bits are held in a register in memory output control logic 36, 10 bits are held in a register in memory input control logic 30 and 3 bits are held in a register in the adder circuitry 34. Of the 10 bits stored in control logic 30, two bits determine a group of four registers, two bits define the register in the group to which the adder is to be connected, two bits define an operation, e.g. shift right, to be performed with respect to the data from the accumulator 24, entry register 26 or adder bus, two bits define the register in the group to which the adder sum is to be connected, one bit defines whether the contents of this register should be recirculated or updated and one bit controls an exponent store. Of the nine bits in the control logic 36, four bits define which register is to be read out (by enabling a gate 22), two bits define special instructions, e.g. change sign, two bits specify a time interval in the memory cycle and one bit enables the accumulator input to the adder 34. The three bits in the register in the adder circuitry are fed to an adder control circuit (200, Fig. 8, not shown) to determine the operation to be performed, e.g. compare, add, add and repeat. The adder control also receives the sign bit and an indication of which of the numbers applied at its terminals is the larger to control gates so that from two input signals A, B an output signal A+B, A, and the 9s complement of A may be selectively gated out to a selected register. The signal B or its inverse is applied to a second output lead so that data may be transferred from one register to another. Addition.-To add two numbers which are entered into the accumulator and entry register the depression of the add key results in a branch add sub-routine being called up to align the numbers in the registers by shifting right of the data in one register and incrementing the corresponding exponent until the exponents are equal. Addition is then effected followed by a justify sub-routine to determine the proper exponent for the sum. The calculator will perform inter alia add, subtract, multiplication and division operations, calculate logs, sine, cos, sine to the minus 1 cos to the minus 1 and square roots of a data entry or a stored number and raise a stored number to the power designated by a data entry key. The calculator may be modified to incorporate a learn mode programme by having an alterable programme memory which acts in a similar manner to the read only memory of the embodiment of Fig. 1. The programme may be loaded either from punched cards or an additional keyboard (Fig. 13, not shown).