baber/WOPTO huggingface dataset:
Patent JP-2008028401-A (JP)
Title: Interconnection structure for semiconductor device
Inventor: YOON JAE-MAN
IPC: H01L21/3213
Filed: 2007-07-23
Abstract: <P>PROBLEM TO BE SOLVED: To provide a manufacturing technology of a semiconductor device and, more specifically, an interconnection structure of the semiconductor device and its manufacturing method.  <P>SOLUTION: The interconnection structure for the semiconductor device, which has: a region arranged so as to comprise at least an interior region; an intermediate region located in at least one side of the interior region; an exterior region arranged in at least one side of the intermediate region so as to face the interior region, comprises one or more pairs of first and second signal lines. Each pair extends from the interior region to the intermediate region. First parts and second parts of the first signal line and the second signal line are parallel, respectively, and the first parts are located in the interior region. The first and second parts of the first signal line at least are not located on the same straight line, and an inter-pair line-spacing in each pair contains d2 in the interior region and d2' in the intermediate region, wherein d2 in the interior region is smaller than d2' in the intermediate region.  <P>COPYRIGHT: (C)2008,JPO&INPIT
Patent JP-2009032610-A (JP)
Title: Fuel cell system
Inventor: MANABE KOUTA
IPC: H01M8/00
Filed: 2007-07-30
Abstract: <P>PROBLEM TO BE SOLVED: To provide a fuel cell system which carries out a sufficient scavenging in the system operation this time even if a sufficient scavenging is not performed at the system shut-down of the last time.  <P>SOLUTION: When a control device 7 detects that a starting command of the system is inputted and a low-temperature mode flag 80 is switched on, the control device 7 compares the measured impedance Im at the time of the last system shut-down stored in a measured impedance memory 91 and the low-temperature starting target impedance It stored in a reference impedance memory 92, and determines whether a scavenging treatment carried out at the last system shut-down is insufficient. When the control device 7 determines that the scavenging treatment was insufficient, the control device 7 promptly increases the temperature by performing a rapid warm-up operation during the system operation this time.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2009031202-A (JP)
Title: Automatic analyzer
Inventor: SOMA KUNIHIKO
IPC: G01N35/02
Filed: 2007-07-30
Abstract: <P>PROBLEM TO BE SOLVED: To provide an automatic analyzer capable of shortening the period spent for analysis by measuring a blank value of each reaction vessel.  <P>SOLUTION: The automatic analyzer is provided with: a reaction vessel for storing a sample and reagent; a cleaning mechanism for cleaning the reaction vessel; and an analyzing mechanism for photo-metering and inspecting the reaction of the reagent with the sample. The automatic analyzer has a blank value comparing function of comparing a precedence blank value 1 measured before photometry inspection of the reaction by a first device starting operation performed first time with a following blank value 2 measured after photometry inspection of the reaction by service operation performed continuously after the first device starting operation.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2008281975-A (JP)
Title: Pattern forming method, resist composition for negative development or multiple development to be used in the pattern forming method, developing solution for negative development to be used in the pattern forming method, and rinsing solution for negative development to be used in the pattern forming method
Inventor: HOSHINO WATARU
IPC: G03F7/038
Filed: 2007-07-30
Abstract: <P>PROBLEM TO BE SOLVED: To provide a method for stably forming a high-accuracy fine pattern to be used in the production process of a semiconductor such as IC, in the production of a circuit board of liquid crystal, thermal head and the like or in other photofabrication processes, a resist composition to be used in the method, a developing solution to be used in the method and a rinsing solution to be used in the method.  <P>SOLUTION: The pattern forming method includes: (1) coating a resist composition including a resin that includes a specific repeating unit and increases the polarity by the action of an acid, wherein the composition decreases the solubility in a negative developing solution upon irradiation with actinic rays or radiation; (2) exposing; and (3) developing with a negative developing solution. There are also provided the resist composition to be used in the method, the developing solution to be used in the method and the rinsing solution to be used in the method.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2009033045-A (JP)
Title: Adjustment method, exposure method, device manufacturing method and exposure apparatus
Inventor: SHINODA KENICHIRO
IPC: G03F7/20
Filed: 2007-07-30
Abstract: <P>PROBLEM TO BE SOLVED: To provide an adjustment method for measuring the polarization state under actual exposure conditions and adjusting the polarization state.  <P>SOLUTION: The adjustment method for adjusting the illumination state in illuminating an original plate by using an illumination optical system and projecting an image of a pattern formed on the original plate onto a substrate via an projection optical system has a measurement step of measuring the polarization state of a light which has passed through the illumination optical system, the original plate and the projection optical system, in a state where the original plate is disposed on the object plane of the projection optical system; and an adjustment step of adjusting the polarization state of the light, on the basis of the result of measurement in the measurement step.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2009034174-A (JP)
Title: Game machine
Inventor: WADA HIDEAKI
IPC: A63F5/04
Filed: 2007-07-31
Abstract: <P>PROBLEM TO BE SOLVED: To provide a game machine capable of announcing an internally winning combination many times even if a plurality of times is determined as the number of times of announcement.  <P>SOLUTION: An announcement frequency determining means determines the number of times of announcement for announcing information on a termination combination for preventing establishment of a high-probability replay game state terminating combination according to a prescribed condition in an advantageous state if the high-probability replay game state terminating combination is determined as the internal winning combination. An announcement means announces the information on the termination combination if the number of times of announcement indicated in the announcement frequency information is at least "1" and if the high-probability replay game state terminating combination is determined as the internal winning combination.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2009038112-A (JP)
Title: Printed wiring board structure and electronic equipment
Inventor: KOGA YUICHI
IPC: H05K3/46
Filed: 2007-07-31
Abstract: <P>PROBLEM TO BE SOLVED: To provide a printed wiring board structure with which high-density wiring and high-density packaging can be expected, and a bus connection interface mechanism between mounted devices can be raised in speed.  <P>SOLUTION: BGA components 20 and 30 are mounted on component mounting surfaces of a printed wiring board 10 in position relation such that substrates 22 and 32 overlap partially with each other and are arranged successively on a straight line while solder balls 23 and 33 arrayed at the overlap portion are electrically joined (soldered) to a through conductor 11 arranged at an inter-chip connection portion (V0), and source synchronous bus connections (25a, 25b and 25c to 35a, 35b and 35c) and differential signal line connections (26a and 26b to 36a and 36b) are made on the substrates 22 and 32.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2009036672-A (JP)
Title: Apparatus and method for measuring pressure, and apparatus and method for measuring frictional stress
Inventor: NAITO HIDEJI
IPC: G01L1/22
Filed: 2007-08-02
Abstract: <P>PROBLEM TO BE SOLVED: To provide a technology for improving the measurement accuracy of a measurement apparatus for measuring the pressure or frictional stress applied to a to-be-measured part in a member to be measured.  <P>SOLUTION: The measurement apparatus 2 is provided with four beams 4a, 4b, 6a, 6b which extend from a back face of the to-be-measured part 8a; a linking plate 14 for linking them and formed with a thickness at which a distortion is generated by the pressure applied to the part to be measured 8a and has a local maximum; and four distortion sensors 10a, 10b, 12a, 12b provided to a lower face of the linking plate 14. A first group of the distortion sensors 10a, 10b measure distortions generated in the linking plate 14, in the direction of a first pair of the juxtaposed beams 4a, 4b. A second group of the distortion sensors 12a, 12b measure distortions generated in the linking plate 14 in the direction of a second pair of the juxtaposed beams 6a, 6b. The measuring apparatus 2 calculates the pressure or the frictional stress applied to the part to be measured 8a from the distortion measured by the distortion sensors 10a, 10b, 12a, 12b.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2009038752-A (JP)
Title: High-frequency circuit
Inventor: FUJITA RIKUO
IPC: H01F27/00
Filed: 2007-08-03
Abstract: <P>PROBLEM TO BE SOLVED: To provide a high-frequency circuit which can reduce the calorific value in a circuit portion, related to a predetermined inductance value and facilitate adjustment of the inductance value.  <P>SOLUTION: The circuit portion of the predetermined inductance value of the high-frequency circuit is configured by connecting in parallel, plural inductors L2a and L2b, L4a and L4b, and L6a and L6b, and arranging these inductors on front and back surfaces of a circuit board 3. More specifically, the inductors L2a, L2b, L4a, L4b, L6a and L6b are configured by winding wires 7a, 7b, 8a, 8b, 9a and 9b around toroidal cores 4a, 4b, 5a, 5b, 6a and 6b, respectively, for a predetermined number of times, while the paired inductors L2a and L2b, L4a and L4b, and L6a and L6b are connected in parallel with each other and are arranged respectively on the front and back surfaces of the board 3.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2008063328-A (JP)
Title: Curative agent for glomerular disease
Inventor: NAKAGAWA TAKASHI
IPC: A61P13/12
Filed: 2007-08-06
Abstract: <P>PROBLEM TO BE SOLVED: To provide a pharmaceutical composition effective for preventing or treating glomerular diseases, particularly progressive chronic glomerular diseases such as IgA nephropathy, focal glomerulosclerosis, membranous nephropathy, membranoproliferative nephritis, diabetic nephropathy or nephrotic syndrome, through solving such problems that, it has been considered as a critical problem in particular in the progression of nephropathy that, in the glomerular sites in progressive naphropathy, mesangium cell proliferation and mesangium substrate proliferation are seen, and such disorder sites often reach not only glomeruri but also the uriniferous tubules and/or interstitial tissue regions therearound.  <P>SOLUTION: The pharmaceutical composition as a prophylactic or curative agent for glomerular diseases comprises pyridoxamine or a salt thereof and dilazep or a salt thereof.  <P>COPYRIGHT: (C)2008,JPO&INPIT
Patent JP-2009040090-A (JP)
Title: Roof support structure of open roof car
Inventor: OKADA TAISUKE
IPC: B60R21/13
Filed: 2007-08-06
Abstract: <P>PROBLEM TO BE SOLVED: To provide a roof support structure of an open roof car, capable of securing an occupant space in a rollover of a vehicle.  <P>SOLUTION: This roof support structure of the open roof car has a collapsible roof 2 openably-closably arranged in an upper part of the vehicle 1 and a roll bar 7 forming an inverse U shape and protecting a head part of an occupant by projecting upward in the rollover of the vehicle. A projecting member 9 is arranged on the upper end of the roll bar 7, and a recessed member 10 is arranged on an inner surface of the collapsible roof 2, respectively. When the roll bar 7 projects upward, the upper end of the roll bar 7 and the collapsible roof 2 are joined by fitting the projecting member 9 in the recessed member 10.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2008064309-A (JP)
Title: Washer and nut
Inventor: TANAKA KEIZO
IPC: F16B43/00
Filed: 2007-08-07
Abstract: <P>PROBLEM TO BE SOLVED: To facilitate work of checking a nut for fastening to avoid failure of fastening the nut, prevent a nut from loosening and facilitate inspection of fastening after a large number of washers and nuts are fastened, in various fastening work of fastening materials employing bolts, nuts and washers in various industries.  <P>SOLUTION: A fixing material 7 is fixed by an penetration groove 10 on the nut side and an extrusion port 4 in a washer with the passage of time by including an indentation in a washer, penetration grooves for a binder and extrusion port in a washer and nut. By so doing, the washer and nut are made to be a loosening preventer. Likewise, the fixing material 7 extruded from an extrusion groove 5 in the washer is extruded onto a fastening material and converted to a binder to be a loosening preventer. The exposure of the binder allows the visual confirmation of the completion of fastening.  <P>COPYRIGHT: (C)2008,JPO&INPIT
Patent JP-2009042043-A (JP)
Title: Sound field analyzer
Inventor: TANIGAWA MASAKI
IPC: G06F17/50
Filed: 2007-08-08
Abstract: <P>PROBLEM TO BE SOLVED: To provide an analyzer of a sound field around an optional scattered body.  <P>SOLUTION: This analyzer is equipped with a direct wave Fourier expansion means for performing Fourier expansion of a direct wave based on inputted sound wave incidence condition information; a scattered wave Fourier expansion means for performing Fourier expansion of a scattered wave based on inputted scattered body shape information; a boundary condition expansion means for inputting inputted boundary condition information, direct wave expansion information outputted from the direct wave Fourier expansion means, and scattered wave expansion information outputted from the scattered wave Fourier expansion means, and expanding the boundary condition based on the scattered body shape information; an equation deriving means for deriving a simultaneous linear equation from expanded boundary condition information outputted from the boundary condition expansion means; a scattered wave calculation means for calculating scattered wave information by solving the simultaneous linear equation derived by the equation deriving means; and a synthesizing means for synthesizing the direct wave expansion information outputted from the direct wave Fourier expansion means with the scattered wave information outputted from the scattered wave calculation part, and outputting the result.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2009044443-A (JP)
Title: Receiver and receiving method
Inventor: MATSUMURA KOJI
IPC: H04J11/00
Filed: 2007-08-08
Abstract: <P>PROBLEM TO BE SOLVED: To provide a receiver which can change a curvature of an interpolation curved line consecutively in response to a fluctuation of a speed of a mobile to acquire a transmission line characteristic accurately, and also suppresses a trend toward a large size and a complication in the receiver.  <P>SOLUTION: When a spline interpolation is carried out to a direction of a temporal axis with respect to an SP symbol, a second-order differential value at points (points of t=t<SB>i-1</SB>, t<SB>i+2</SB>) at both ends is made as a value which is not limited to 0 complying with the speed of the mobile. With such an arrangement, it becomes possible to acquire interpolation curved lines S<SB>ia</SB>, S<SB>ib</SB>in which the curvature complies with the speed of the mobile.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2007287332-A (JP)
Title: Semiconductor device
Inventor: OISHI TSUKASA
IPC: G11C11/15
Filed: 2007-08-09
Abstract: <P>PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a MRAM simplifying a write driver controlling a bit line current during data write.  <P>SOLUTION: Two write current control lines (WCL1 and /WCL1, WCL2 and /WCL2) are arranged respectively along a row direction at both sides of respective memory blocks MB1 to MB3. Connection control parts 110, 120 are controlled by write control circuits 130, 135, connect one write current control line to power source voltage Vcc, while connect the other write current control line to ground voltage GND, in accordance with write data DIN. A bit line corresponding to a selected memory cell is connected between write current control line of both sides of the corresponding memory block by turning on transistor switches 102, 103 in response to activation of a column selection line CSL shared between memory blocks, and a data write current flows.  <P>COPYRIGHT: (C)2008,JPO&INPIT
Patent JP-2009039685-A (JP)
Title: Centrifuge
Inventor: MATSUMOTO TAKASHI
IPC: B04B3/00
Filed: 2007-08-10
Abstract: <P>PROBLEM TO BE SOLVED: To provide a centrifuge realizing structural simplification by eliminating a cake scraper.  <P>SOLUTION: An opening in the peripheral wall section 101 of a basket 1 is opened straightly in the axial direction. A filter 20 integrally constituted of a barrel section 20a formed in a tubular shape fitted to the inner face of the peripheral wall section 101 of the basket, an end plate section 20b provided to close one end of the barrel section 20a in the axial direction and formed to fit to the inner face of the bottom wall section of the basket and an annular end section wall 20c protruded from the other end of the barrel section 20a in the axial direction to the inner side in the radial direction is inserted into the basket 1. After a cake block is formed in the filter 20, the filter 20 together with the cake formed inside of the filter 20 is drawn out of the basket through the opening in the peripheral wall section of the basket.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2009044974-A (JP)
Title: Method for constructing prediction model for predicting quality of cell, program for constructing prediction model, recording medium recording the program, and device for constructing prediction model
Inventor: HONDA HIROYUKI
IPC: C12Q1/02
Filed: 2007-08-16
Abstract: <P>PROBLEM TO BE SOLVED: To provide an information-treating model for predicting a quality on the culture of cells.  <P>SOLUTION: This method for constructing a prediction model for predicting the quality of cells comprises (1) a step for preparing two or more samples obtained culturing the same kinds of cells; (2) a step for photographing the cells of the samples to obtain the images, respectively, at two or more time points (predicted times) different in culture times; (3) a step for analyzing the images obtained in the step (2) to produce numeral value data on two or more indexes related to the forms of the cells; (4) a step for preparing the measured data of predicted targets for each sample; and (5) a step for subjecting the numeral value data produced in the step (3) as input values and the measured data prepared in the step (4) as teacher values to a fuzzy neural network analysis to calculate output values on the basis of a fuzzy rule exhibiting an index combination effective to prediction.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2009048323-A (JP)
Title: Simulation of logic circuit
Inventor: TERABE MIKI
IPC: G06F17/50
Filed: 2007-08-16
Abstract: <P>PROBLEM TO BE SOLVED: To perform high-precision timing analysis within a practical period of time.  <P>SOLUTION: A logic circuit is divided into a plurality of division circuits 30 to 39. Forward tracing is performed from the starting point 40 of a path for timing analysis and back tracing is performed from the end point 42 of the path. A definite value corresponding to timing analysis requirements is made to propagate from an input pin other than the starting point of the path. The division circuit traced by the forward tracing and the back tracing and including one or more transistors whose definite values do not reach an effective level is sampled as the division circuit that makes up a path circuit. The division circuits 34, 35 connected to the input of the path circuit are sampled as auxiliary division circuits. Simulation calculations are performed with respect to a partial circuit comprising the division circuits sampled.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2009047948-A (JP)
Title: Second image forming apparatus
Inventor: OIKE HIDEAKI
IPC: G03G21/00
Filed: 2007-08-21
Abstract: <P>PROBLEM TO BE SOLVED: To accurately determine the service life, while using a common process cartridge, in a different type of image forming apparatus.  <P>SOLUTION: A second image forming apparatus (U') is provided with: image carrier units (UY to UK) which have storage members (My to Mk) storing the remaining film thickness information of image carriers (Py to Pk) and the film decrease coefficient of a first image forming apparatus and can be attached and detached to and from the first image forming apparatus (U) and the second image forming apparatus (U'); remaining film thickness calculating means (C6b and C6b1') which calculate the remaining film thickness of the image carriers (Py to Pk), on the basis of the rotational time of the image carriers (Py to Pk) and the correction coefficient of the film decrease coefficient of the second image forming apparatus (U'); service life discriminating means (C6c and C6c') which discriminate the service life of the image carriers (Py to Pk), on the basis of the service life judgment information and remaining film thickness; and an informing means (C7) which notifies of the service life of the image carriers (Py to Pk).  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2008004957-A (JP)
Title: Transistor and display comprising it
Inventor: MORITA SATOSHI
IPC: G02F1/1368
Filed: 2007-08-23
Abstract: <P>PROBLEM TO BE SOLVED: To provide a structure of a transistor, which prevents a parasitic capacitance of the transistor from fluctuating and contributes to image quality homogenization of a display.  <P>SOLUTION: A transistor 1 has a source electrode 9 and a drain electrode 10, which face each other and between which a semiconductor layer 7 is sandwiched, on a gate electrode 5. The drain electrode 10 is formed in a rod shape. The source electrode 9 is long and narrow and has a recessed portion 9a on the side facing the drain electrode 10 to allow the tip portion 10a of the drain electrode 10 in. Furthermore, portions of the semiconductor layer 7 protrude out of the gate electrode 5. Those portions are located at the source electrode 9 and the drain electrode 10, where the source electrode 9 and the drain electrode 10 do not overlap the gate electrode 5 in plan view. The protruding portions located at the source electrode 9 and at the drain electrode 10 are shielded by the gate electrode 5 and electromagnetically independent from each other.  <P>COPYRIGHT: (C)2008,JPO&INPIT