Patent GB-1256068-A (GB)
Title: Improvements in or relating to logic circuit arrangements
Inventor: KREBS PETER ERIC
IPC: H03K23/00
Filed: 1967-12-07
Abstract: 1,256,068. Transistor pulse circuits. PLESSEY CO. Ltd. 24 Jan., 1969 [7 Dec., 1967], No. 55798/67. Heading H3T. [Also in Divisions G1 and H1] In a logic circuit, a capacitance C O , Fig. 3, which is inherent in a device such as a MOST M1 receiving an information input V I , accepts and stores the information under the control of a clock pulse #, applied through a capacitor C and supplying the power for the logic circuit. The circuit acts as an inverter; a negative input ("1") turns on the MOST M1, and the capacitor C O  maintains O V  output; a zero voltage input ("0") turns M1 off and the output V O  is a negative pulse derived from the negative clock pulse by the potential divider C, Co. A delay element (Fig. 4, not shown) uses two of the Fig. 3 inverters in cascade, and controlled from separate clock pulse sources # 1  and # 2 . Two (or more) of these elements form a delay line (Fig. 6, not shown), in which the clock pulses must overlap if a two phase source is used, but not if three or more phases are used. "Write-in" to an intermediate stage of such a two-phase delay line is effected (Fig. 9, not shown) by a series pair of MOST's (M16, M17) receiving respectively a negative control pulse and the information input, so that when both are negative, the next MOST stage (M13) is turned on; at the same time the control pulse turns on a MOST (M15) in parallel with a preceding stage MOST (M11) to inhibit same. In an alternative "write-in" arrangement, the pair (M16, M17) is replaced by a gating MOST (M19) with its source-drain path in the input line to the gate of one stage (M14) of the delay line, the gating MOST (19) having the control input at its gate. Shift/storage circuits use bi-stable pairs of the Fig. 3 inverters (Figs. 11, 12, 13, not shown). A plurality of cascaded inverters (Fig. 15, not shown) operates from a single phase clock pulse source, but the number of stages is limited due to the progressive reduction of pulse amplitude and steepness of pulse edges through the stages. A counter/register (Fig. 18, not shown), said to be known, is constructed with the Fig. 3 inverters and consists of: three MOST's (M33, M34, M35, Fig. 19, not shown) with a common drain capacitor (C19) receiving # 1  clock pulese, forming a NOR gate; an AND gate having MOST's (M37, M38) fed from the NOR gate and from an input Do and controlled over capacitors (C20, C21) from the two phases of the clock source; and a bi-stable delay stage (as in Fig. 13, not shown) comprising three MOST's (M39, M40, M42) and an inhibit MOST (41). An integrated circuit construction is disclosed. Bipolar transistors may be used. Instead of a MOST, an opto-electronic diode (Do, Fig. 24, not shown) may be used as the device whose inherent capacitance stores the information. Here, the clock pulse, or "address", is applied through a capacitor (C26) as before to charge the diode Do capacitance. If the information input, in the form of light falling on the diode, causes the capacitance to discharge, then a predetermined voltage signal applied subsequently to C26 fails to turn on a MOST (M52); but if the diode (Do) has held its charge, the predetermined voltage will be sufficient to turn on the MOST (M52).