Patent GB-1311489-A (GB)
Title: Adjustable telecommunication signal converter
IPC: H04Q3/00
Filed: 1970-10-15
Abstract: 1311489 Code converters PLESSEY CO Ltd 6 Sept 1971 [15 Oct 1970] 48982/70 Heading G4H [Also in Division H4] A bi-directional code-converter for identifying a calling line or marking a called line comprises logic responsive to a pulse on a single input wire to produce a succession of pulses on a selection of a plurality of output wires, or, in response to the latter plural pulse marking on a plurality of input wires to apply a single pulse to one only from a plurality of output wires. An additional pulse may be produced for indicating to the common control the type of digit sending that will be adopted by a calling subscriber. Each line has an individual logic (c.f. Figs. 7-10, not shown) consisting of an array of MOST gates formed as an integrated circuit chip and mounted on a private circuit board which is of the type described in Specification 1,311,342. Code used is of the 2-out-of five type whereby in order to identify one out of a 1000 subscriber lines, pulses are applied to a different pair out of five wires a, b, c, d, e, during each of four successive time slots P, Q, R, S (Figs. 3 and 4). General description Fig. 1.-The subscribers lines S1 ... S3 appearing at a main distribution frame are jumpered to respective line circuits l1...l3 each of which incorporates a pair of unidirectional signal wires that are connected, inter alia, to respective jack contacts 5 of a line identifying circuit SC unique to each line. The unidirectional wires constitute the wires carrying a single pulse which if it is on lead i1 indicates that a translation is required for finding the (calling) lines directory number whereas if it is on wire o1 indicates that this is the called line corresponding to a known directory number. The latter is applied to all the identifying circuits via marking multiple hi or is derived from an identifying circuit via multiple ho. The P, Q, R, S timing pulses are applied over multiple tt while r battery is applied over bus 2a, 2b. Special information about a line under investigation, e.g. the type of digit reader it will use, is transferred over multiple y. The multiples terminate at common control equipment for the exchange and during any particular time frame carry information exclusively in respect of a single line. Particular description (Figs. 6a, 6b).-Each identification circuit is identical in construction, their unique responses being governed by means of plugs W, 3P-3S (right of Fig 6b) which are inserted into a card prior to its being jacked into a position on the multiples. The plugs serve to connect an enabling earth on battery bus 2a to two gates in the array of gates AaP ... AeS during each of the four time slots P, Q, R, S. For example in the case of line number 2840, plug 3P allows gates AaP and AcP to be marked whereby during time slot P when timing pulse t1 is applied to all the AxP (x=a...e) gates the two marked gates will open and apply pulses to the a and c wires represented by gates Ga and Gc so as to signify the initial digit 2. The remaining plugs 3P ... 3S similarly allow wires be, ad and de to be marked during slots Q, R, S thereby-signifying digits 8, 4, 0. Translation in first direction the multiple ho will be marked by the just-described set of pulses once during the first set of timing pulses following the appearance of a request for identification signal (which lasts for at least the duration of a set of timing pulses) at input terminal i1. The latter signal sets bi-stable BA so as to open gate G8 thereby permitting gates Ga... Ge to open as indicated above and pass the set of marking pulses via delivery gates Da ... De to the multiple ho. Gate G2 is closed after the pulses have been transmitted by the resetting of BA due to the setting of BB which cannot be reset until the signal on i1 is removed. Translation in other direction.-In this case the set of pulses is applied to multiple hi whereby during each time slot either G9 or G10 and G11 and hence G8 opens. The latter again permits gates Ga...Ge to transmit any markings they may carry to coincidence gates Ca ... Ce. Thus during slot P gates Ga and Ge are opened so that in conjunction with the pulses on wires a and c of the multiple hi coincidence gates Ca and Cc open to open gate G12 and hence set BP which is the first stage of a four stage counter. Obviously a similar process occurs in all other identification circuits which, are plugged-up in respect of the initial digit 2. The pulses occurring during subsequent slots cause the counters to step-on but since only one circuit is (or rather, should be) plugged up for the number 2840, only this circuit counter will attain its final step thereby delivering a single output marking pulse to terminal ol. During the succeeding set of timing pulses t1...t4 the stages of the counter (and similarly operative stages in other counters) are reset one by one so as to remove the single marking signal. The MO, ST logic includes arrangements for ensuring that only 2 out of 5 markings are effective.