Patent GB-945773-A (GB)
Title: Variable increment computer
IPC: G06F17/10
Filed: 1960-04-22
Abstract: 945,773. Electric calculating apparatus. GENERAL ELECTRIC CO. April 22, 1960 [April 29, 1959], No. 14204/60. Heading G4A. An increment computer (i.e. one using the change in the input variables to up-date the previously computed output function of these variables) selects as input increments so-called "optimum" increments each of which is that power of the computer radix nearest to the actual increment. By this means arithmetical operations in the computer are made rapid (multiplication and division become simply shift operations) while allowing more rapid following of input changes than are possible with increments limited to  1. The embodiment described is a binary series-mode computer utilizing magnetic core logic and arithmetic elements and a magnetic drum for storing the program and timing signals, and designed around the algorithm U i #T i  + V i-i #W i  = S#Z i  which by suitable definitions of T-W can be used for the four operations of arithmetic. In this algorithm U i  &c. = present value of U &c. V i-1  &c. = previous value of V &c. #T i  = T i  - T i-1  S = scale factor. For example, to compute the increment of Z if sZ = aX + bY s#Z i  = a#X i  + b#Y i , so that U and V are made constants, and T and W equated with X and Y if sZ = XY S#Z i  = #X i Y i-1  + X i #Y i , so that U and W are equated with X, and V and T are equated with Y. For division the last equation is rewritten #Y i  = s#Z i -Y i-1 #X i ,/X i  Z being regarded as an input variable and Y as the quotient. Since the result of an arithmetic operation may itself be required for further calculation, the increment calculated, as well as the increments of the input variables, must be converted to optimum form; and this requires modification of the above algorithm to include a remainder term. Optimum increments (i.e. powers of two nearest to the increments of the variables) are indicated by primes, e.g. X i <SP>1</SP> is the ith optimum increment of X. Fig. 3 shows the computer in block diagram form. The blocks shown on the broken line are tracks on a magnetic drum which store system variables, the program, timing signals, and addresses in a random-access memory 70 used to store sampled variables, increments &c. The timing signals will depend on the arithmetic operation required, and a timing word is written on to a track 62 from the program and shifted through a register 66 by clock pulses CL to provide them. The operation of Fig. 3 for multiplication (i.e. in which U = W = X, V = T = Y) will now be described, it being assumed that initial information has been entered on the various tracks. X o  is read from 12, and X i <SP>1</SP> from the memory 70 under control of the program, to be added at 68, the new value (X i ) being written back on to 12 and also passing to multiplier 76 where it is multiplied (by a simple shift) by Y l <SP>1</SP> entered via 78. At the same time Y o  is gated via 88 to be multiplied by X l <SP>1</SP> (fed from 70 via 92) at 90 and the two products are added at 84, and pass to 98. At this point track 58 will be empty, and the increment will pass unchanged through 98 and 108 to an increment selector 112 (Fig. 9, not shown) which selects as Z 1 <SP>1</SP> the nearest power of 2 and writes it away in 70. The actual increment is written on to track 58 and on the next iteration step is added to the new increment at 98, while sZ 1 <SP>1</SP> is subtracted at 108, so that the new increment is effectively increased by the previous remainder before passing to the increment selector. Circuit 130 is used in division, where an "optimised" value of V (= X) is necessary for the division, which takes place in unit 112. Fig, 4 shows a magnetic core serial adder for use at 84 for example. Addend and augend are entered at U and V into cores A7 and A8 in synchronizm with the negative half-cycles of generator 216. At the next positive half-cycle A7 and A8 receive re-setting currents; if both were previously set the output voltage in winding 214 of A8 diverts the resetting current of A8 through an input winding on core A6, while if A8 only was set it will flow partly through this winding and partly through that on A5 (210) and 214 of A7. The resetting current of A7 will flow through 222 and 214 of that core if A7 was not set, or if both were set; if A7 only was set it will flow through 210, and 214 of A8. Thus A8 is transferred to A6, and A5 registers the sum digit. At the next negative-going cycle a 1 in A6 is shifted to A4 if not inhibited by the output of A5 (this represents a carry formed by two input 1's), and the next pair of bits is entered in A7 and A8. At the same time a temporary sum digit 1 is transferred from A5 to output core A3 if not inhibited by a carry from A1; if A5 contains a 0 then a carry from A1 is transferred to A3. At the next positive cycle any carry from A4 is entered into the core pair A1, A2 where it remains until it can be entered into A3 for output (this is inhibited by any pulse from A5). The Specification also describes, and illustrates schematically, magnetic core logic circuits for (for example) multiplying by powers of two (by gating out from an appropriate point of a shift register, Fig. 8, not shown), "optimising" increments (Fig. 9, not shown, which produces signals in a binary order if a "1" is sensed in that order, or if "1's have been sensed in the two preceding orders, and utilizes the most significant of such signals as an optimum increment) &c. using the techniques of Fig. 4.