Patent GB-1457253-A (GB)
Title: Semiconductor charge transfer devices
IPC: G11C27/04
Filed: 1972-12-01
Abstract: 1457253 Capacitive storage MULLARD Ltd 27 Nov 1973 [1 Dec 1972] 55563/72 Heading G4C [Also in Division H1] A semi-conductor charge storage device comprises (Fig. 1) a p-type Si substrate 1 with a ntype epitaxial layer 2 thereon covered with insulant SiO 2  layer 3. Thereon are disposed plural spaced conductive grouped gate electrodes G 1 , G 2 , G 3  wherein G 1  and G 2  are of strip form and G 3  of annular form, which are respectively connected to common lines # 1 , # 2 , # 3  with input and output insulated gate electrodes G I  and G O  at opposite ends. P-type surface regions 4, 5 are associated with the input and output electrodes for the supply and removal of charge. Circular n<SP>+</SP> regions 6, 7 in the surface of n-layer 2 are bounded by insulated gate electrodes G 3  while metallic layers 11, 12 are ohmically connected to these regions at openings of layer 3. Further metallic layers 16, 17 are ohmically connected to p-type regions 4, 5 while connections S, Sub are made to layers 2, 1. Regions 6, 7 and their connections function as drain electrodes of FET structures whose sources have common connection S and whose gates are the surrounding G 3  electrodes. The arrangement of Figs. 10 to 12 comprises a 1024 bit random access memory having a high resistivity p-type Si substrate 61 with thereupon an n-type Si epitaxial layer 62 divided into 32 islands by a submerged locally oxidised pattern 63 extending into the substrate. A further oxide layer with thick and thin portions 64, 65 overlies the epitaxial, and the islands are arranged in parallel columns (e.g. 1, 2, 30, 31, 32 in Fig. 10). Plural two phase charge transfer device electrodes extend over the surface of the insulant layer 63, 64, 65 and comprises 32 electrode strips connected to common line # 1  alternating with 32 further interleaved electrode strips # 2,1  to # 2,32  transversely of the columns; each pair of adjoining electrodes # 1 , # 2  forming 1 bit with #, and extending partly over the thicker and partly over the thinner oxide layer portions. Electrodes # 2 , 1 , # 2 , 2 , # 2 , 3 , # 2 , 4 , # 2 , 30 , # 2 , 31  and # 2 , 32  are shown as examples in Fig. 10, and the CTD electrodes comprise 32 input gates G x (CTD) where x is 1 to 32 individually electrically accessable and associated with the column or islands of the epitaxial layer, with an output gate electrode G o/p (CTD). The input gate electrodes G x (CTD) overlap p<SP>+</SP> surface region near the ends of the epitaxial columns to provide sources of holes for injection into the depletion region of the n-type epitaxial layer of the CTD input electrodes; the p<SP>+</SP> regions being connected to a common CTD source line Si(CTD). The common output gates electrode G o+p (CTD) overlaps p<SP>+</SP> surface regions near the opposite ends of the epitaxial columns to provide drains removing holes from the depletion region associated therewith; these p<SP>+</SP> regions being returned to a common drain line DC(CTD). At opposite ends of the columns n<SP>+</SP> surface regions form sources and drains of deep depletion FET structures where electrodes are respectively connected to common source line S t (FET) and separate drain lines D x (FET) where x is 1 to 32; the gate being that part of any electrode # 2 , x  lying on the thinner oxide portion 65; i.e. with 32 gates per column any one of which is operable at a time to modulate the column or FET channel current. In operation (Figs. 12a, 12b, 12c) a memory bit is defined in a column by electrode pair # 1 , # 2 , x  e.g. in column 31 (Fig. 10) two bits are defined by electrodes # 1 , # 2 , 1  and # 1 , # 2 , 30  in which information is stored as depletion region charge in the n-layer associated with the part of electrodes # 2 , x  overlying the thinner oxide layer 65. This is fed into the several columnar bits by 2 phase CTD action using input gates G x (CTD) to control the charges fed in and clocking electrodes # 1 , # 2 , x  with the latter connected in common; to achieve the conditions of Fig. 12(a) e.g. for the 31st column in which "0" or "1" logic corresponds to a small or large charge respectively determining the extent of the depletion regions of the individual electrodes, e.g. (Fig. 12a) "1" logic is stored in the bits defined by # 1 , # 2 , and # 1 , # 2 , 31  while "0" logic is stored in the bits defined by # 1 , # 2 , 30  and # 1 , # 2 , 32  and the column or FET channels are unblocked. In read out e.g. of the 31st column defined by electrodes # 1 , # 2 , 1  (Figs. 12, 12b) the potential on electrode # 2 , 1  is increased by a preset value while the remaining electrodes # 2 , x  are held constant. Then potential is applied between drain D 31 (FET) and source S t (FET) and the FET channel current measured as output voltage across resistor V o , so that due to the larger charge stored the FET channel is unblocked and the large current indicates logic "1". Similarly for the bit defined by # 1 , # 2 , 30  (Fig. 12c) the potential on electrode # 2 , 30  is increased by a preset value and electrodes # 2 , x  are held constant, while potential is applied between source and drain. Due to the smaller charge stored the FET channel is blocked and the small current indicates logic "0". The preset readout increase of potential is such that there is no punch through from the depletion regions to the pn junction between the epitaxial layer and the substrate, so that readout is non-destructive. Further write in is effected by 2 phase CTD action with clock voltages on lines # 1  and commoned # 2 , x ; the charge at the ends of the CTD lines of the columns being removed over the p<SP>+</SP> regions commoned to the drain line D C (CTD). In a further modification (Fig. 13, not shown) the charge transfer and storage means employs M.O.S. "bucket brigade" array integrally combined with plural deep depletion FET structures; and comprises a high resistivity p-type substrate with a n-type epitaxial layer thereon overlain by a SiO 2  layer of uniform thickness. The epitaxial layer has a n<SP>+</SP> upper surface and plural spaced p<SP>+</SP> regions, of which the first is connected to an input line and the remainder are coupled as a "bucket brigade" over a series of electrodes on the insulant layer alternately connected to common lines # 1 , # 2 . The epitaxial layer between the p<SP>+</SP> regions are ohmically connected to a plurality of lines, and the connections form drains of plural deep depletion FET structures whose sources are returned in common to the n-layer, while the channel currents are modulated in response to the potentials of the respective p<SP>+</SP> regions and to the charges stored by the associated electrodes. The MOS transistors transfer charges sequentially between adjacent storages constituted by the electrodes, the oxide layer, and the underlying p<SP>+</SP> regions while the electrode lines are alternately clocked by switching voltage. Readout is non-destructive by applying potential between FET drains and the common source, and the device may be constructed as a display, imaging device, or solid state memory. Specifications 1,391,934; 1,444,541; 1,444,542; 1,444,543; 1,444,544 are referred to.