Patent GB-1314841-A (GB)
Title: Asynchronous circuits and logic
IPC: G06F7/501
Filed: 1970-04-14
Abstract: 1314841 Shift register, adder, multiplier DYAD SYSTEMS Inc 14 April 1970 [16 April 1969 26 March 1970] 17802/70 Headings G4A and G4C [Also in Division H3] A control circuit in an asynchronous digital system, e.g. a shift register, comprises two Nand gales 71, 74 (Fig. 4) cross-coupled output-toinput and a third Nand gate 67 supplying one input of gate 71 and having one of its input terminals connected to the output of gate 74 and another connected in common with an input of gate 74 to a signal source which causes cycling of the circuit. As shown, lowering the input 58i+1), Fig. 4, at time t 0  causes the gate outputs to change in the sequence illustrated to produce a steady state during time t 3  - t 4 . Restoring the input returns the circuit to the original steady state at time t 9 . During the periods t 4  - t 9  gate 67 changes state and back again (graph 67i) in the manner of a monostable circuit, providing a delayed pulse spanning the period t 5  to t 9 , of nominal width equal to three gave delay periods. The circuit is described as used as an inter-stage feedback control in an asynchronous shift register and to applications of the register. The circuit is adapted to avoid race and false signal conditions previously encountered. A circuit of similar configuration is also used as the storage element in each stage of the register to provide two storage states and a neutral state. Further adaptions can provide additional storage states and these may be used in ternary or higher order logic or, it is suggested, for computer housekeeping facilities, e.g. end of message, mode of operation or error detection function. The Nand gates may comprise a diode AND gate followed by a transistor inverter (Fig. 1, not shown).  Fig. 3 shows two stages i, (i + 1) of an asynchronous shift register in which the stages have the conventional complimentary information storage states 0, 1 and 1, 0 at 72i and 73i and a neutral state 1, 1 (which may be a stable state) in which the stage is able to receive information. Each stage includes a control circuit 67i, 71i, 74i is accordance with the invention which controls the stage in accordance with the state of the next stage and provides a control signal, in accordance with the state of the associated stage, to the previous stage. Thus, if stage (i + 1) is in the neutral state the voltage at control terminal 58 (i + 1) is zero and data transfer gates 68i and 69i are opened by the control output of stage. Data (if any) in stage i therefore transferred to stage i + 1 and upon this being completed the control circuit of stage i+1 provide a ONE at terminal 58 (i+1) whereupon the control circuit in stage i, after its delay closes the transfer gates 68i and 69i and sets stage i to its neutral state. Data is thus transferred between the stages. The input of the stages is directly connected to the next transfer gates and accordingly if a plurality of adjacent stages are in the neutral state, data will pass along the stages with only two switching delays in each stage i.e. a delay of gate 68 or 69 and that of 67. The register is therefore of the so called "elastic" type. Higher speed may be obtained by using a different control circuit (Fig. 24, not shown) in which the output of gate 67 is connected to the data transfer gates 68 and 69 instead of gate 71. Modifications to provide read in, read out, fan in, fan out, presetting, resetting, forward and reverse operation adding and multiplying are described with reference to other Figures (not shown) as follows: Serial read-in may be effected (Fig. 3, not shown) in response to a "data available" signal applied (at 94) to a control circuit in accordance with the invention and which, as previously explained, provides a pulse of three gate delay length momentarily to open data transfer gates (81, 82). The delay which, exists before gating, can be increased by connecting the input of the transfer gates through an inverter to the output of gate 87. Where the delays of the interface gates may be different from other gate delays the operation of the data transfer gate (81, 82) may be controlled also by a control circuit (67, 71, 74) controlled by the first stage of the register (Fig. 7). A reduction to a two gate delay transfer time could be effected by connecting one input (96) of the transfer gate via an inverter to the output (58) of the control circuit of the first stage instead of to the output of the additional control circuit (67, 71, 74). The control circuit of the first stage alternatively may be used (Fig. 8) not only to open the input transfer gates (81, 82) but to operate a further control circuit (84, 86, 87) used as a delay to initiate the supply of the next data first by stepping an input register along. Where new data is not immediately available, further delay in gating in information may be provided using an additional control circuit according to the invention (Fig. 9). Serial read out is effected (Fig. 10) using output transfer gates with feedback including a further control circuit (116) according to the invention to effect self cycling in response to a transfer order applied from a bi-stable circuit. Cycling delay may be reduced (Fig. 12) by using a further gate (123) which senses the onset of information at the output terminals and can cause the control circuit (67i, 71i, 74i) to restore the stage i to a neutral state after a delay. In this condition, data is received and also gate 123 is satisfied, causing the control circuit to restore the circuit again to its neutral state. Read-out alternatively can be effected merely by applying shift pulses to the feedback control terminal of the output stage. Parallel read-in or resetting to the neutral state may be effected (Fig. 13) by supplying the data to the terminals 56, 57 or terminal 58 respectively, preferably via a logic circuit. Parallel read-out is effected in conventional manner, the necessary indication that all stages are full being obtainable either by detecting the passing of the maximum filling delay or by a counter (Fig. 14). Where two registers are being used as an adder, a gate may be provided to detect both final stages full before output transfer gates are enabled (Fig. 15). Fan-in to the register from similar registers may be controlled by a bi-stable circuit having its output fed to the control inputs of the output stages of the input registers (Fig. 16). Additional input registers may be selected in a similar manner or counter whereby coding and multiplexing may be effected. Fan-out from the register may be effected in a similar manner by applying a signal to the control circuit of the first stage of the parallel output registers (Fig. 17) Serial addition of two numbers (Fig 18) stored in chains (173 and 174) is effected by a Nand gate switching network (179) the result being transferred to an output register 176. Carry bits are stored (in 177) and transferred (2178) when required. It is explained that the system is "autosynchronous" that is, the summing network (179) gives no valid output unless they are the correct ones, regardless of how many valid inputs are available to it and of the time sequence in which the inputs are applied. Neutral outputs will be given whenever a correct valid output value cannot be given. A higher speed modification (Fig. 21) eliminates the transfer gates and may use two level logic. Fig. 28 shows the addition of a presetting facility. Stepping of parallel registers may be synchronized (Figs. 19 and 22). Forward and reverse flow of information may be effected in by providing parallel reversely arranged registers and enabling the respective one of the control circuits (Fig. 20). Fig. 25 illustrates how information may be cleared from the stages or selected stages. Fig. 26 illustrates fan out through respective one-bit multipliers. In these multipliers two gates are connected in series with each input lead to each of the succeeding registers (gates 247, 243, 248, 244) and the multiplicand (S, Y) is applied to the first gate in the one path and the second gate in the other whereby the single multiplicand is effectively converted into a complementary pair of signals. In a multiplier (Fig. 27) the output of corresponding stages of an a register and a, b registers are applied to respective single digit multipliers of the type described with reference to Fig. 26 and the output of these multipliers are appropriately summed. Initial presetting can be effected (Fig. 28). Combined serial multiplication and addition may also be effected (Figs. 29 and 30). The Specification also describes, with reference to Fig. 2, a prior non-synchronous shift register in which the stages again have 0, 1 and neutral states but in which the transfer is controlled by a feed forward ready-to-transmit and a feedback ready-to-receive control system and in which the storage section of each stage is back-coupled to the input transfer gate to provide a system having several stable states.