Patent GB-1252555-A (GB)
IPC: H04J3/10
Filed: 1970-02-17
Abstract: 1,252,555. Multiplex pulse code signalling. STANDARD TELEPHONES & CABLES Ltd. 17 Feb., 1970, No. 7530/70. Heading H4L. A time division multiplex P.C.M. system is provided with means for using one or more channels for the transmission of data at a number of different bit rates. In the system described there are twenty-four speech channels per frame each channel having eight bits one of which is used for synchronizing or signalling purposes. When a channel is used for the transmission of data only a maximum of six of the seven available bits are used for the data, the seventh bit being used as a marker to indicate the data bit rate. The channel repetition frequency is 8 kc./s. giving a basic clock frequency of 1536 kc./s. Data bit rates of 16, 24, 32, 40 and 48 kc./s. require 2, 3, 4, 5 and 6 bits per frame respectively, which follow the sync. or signalling bit and are immediately followed by a 1 which is the marker bit, the remaining bit places being filled by binary 0's. For example a data bit rate of 16 is represented by XX10000 in which X represents a data bit, which follows the sync. bit. Incoming data is stored every frame period in a buffer store at the transmitter and a count made of the number of data bits stored per frame. This count determines the position of the marker bit. At the receiver the position of the marker bit is recognized and used to control a phase locked oscillator which reads out the stored data. If the data is synchronous with the P.C.M. signals a constant number of data bits occurs per frame, but if it is not synchronous the counter adopts one of two states depending on which frequency range is appropriate to the data bit rate. To determine the mean frequency the receiver integrates these counts over a long period. Data transmitter, Fig. 1.-Incoming data is fed into a shift register SR once per frame under the control of the data clock and after the end of the frame is read out by the 1536 kc./s. P.C.M. digit clock into the channel n to be used, by means of a bi-stable A which is set at bit position D3 of channel n for the present example. Thus the data passes via sequentially controlled gates and via NOR gate G1 to the output via bi-stable JK controlled by bi-stable C, a bistable F having been set at D1 of channel n to open a gate G2. After the last bit has passed, bi-stable E is reset (D8) to cut off the P.C.M. digit clock pulses and the store SR is ready to receive more data. To ensure that data is not written into SR during read-out, a gated bistable HSR is set by the data clock and a blanking pulse which are gated together. The blanking pulse is provided by bi-stable B and extends from channel (n-1) digit 8 to channel (n + 1) digit 2. The inverse of the data clock is used to reset bi-stable B. A counter CC, controlled by the bi-stable HSR, counts the data clock pulses during a frame period and is reset via gate G3 at the end of each frame. This count indicates the number of data bits in the shift register and the counter also controls the read-out from SR. A bi-stable F is set at channel n, digit 1 and is reset by the output of counter CC to control the position at which the marker pulse is inserted via gate G4, any remaining bit spaces being filled with 0 bits.  Data receiver, Fig. 2.-Incoming data is fed via buffer B2 to shift register SR1 or SR2 respectively, controlled by writing clock pulses at the P.C.M. bit rate via gate G10 or G11, the shift registers being operated alternately by a bi-stable JKA at the incoming frame rate, the data being written in and read out serially. Gates P1 and bi-stable P control the time at which the output gates of the shift registers are opened. The data clock frequency of the receiver is determined by averaging the bit frequency of the incoming data over a large number of frames and this sets the receiver data clock to the rate at which data is to be read out of the shift registers. If the previous data channel was stored in SR1, this is read out by the data clock over the next frame period, data signals being written into SR2 during that frame. When SR1 is emptied this is detected by gate G12 and the reading clock is switched to SR2 by a bi-stable JKB. Gate G13 co-operates similarly with SR2. Automatic frequency control of the data clock oscillator is provided by comparing in an EXCLUSIVE OR gate the phase of a 4 kc./s. square wave A generated by bi-stable JKA with the 4 kc./s. waveform B generated by bi-stable JKB which is controlled by the time at which SR1 and SR2 are read out. The set and clear inputs of JKB are connected directly to the outputs of JKA and are only gated through to the store on the negative transitions of the data clock. If the data clock frequency is too high the shift register is read early in the frame but JKB will not change state until after JKA changes state at channel (n-1) digit 8 period. This effects a control if the data clock is too fast and prevents reading out a shift register before it has been written into. If the reading clock frequency is too low the shift register is not completely emptied during the frame period so that JKB is not switched over via gate G12 or G13 but is triggered by a channel (n-1) D2 pulse. This allows the maximum period of time for each shift register to be read. When the reconstructed data bit frequency is correct the EXCLUSIVE OR phase comparator provides an output having a duty cycle dependent on the phase relationship of inputs A and B which controls a phase-locked oscillator supplying the local clock signals.