Patent GB-804810-A (GB)
Title: Checking circuit
IPC: G06F11/10
Filed: 1955-10-27
Abstract: 804,810. Electric digital-data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 27, 1955 [Oct. 27, 1954], No. 30750/55. Class 106 (1). A checking circuit for a regenerative storage system in which a plurality of multi-digit words is manifested sequentially by the electrical condition of a plurality of data lines, includes first means for detecting an error in any one or more of said words and second means, responsive to said first means, for indicating the addresses of the words in which errors have been detected. The system described, Fig. 2A, comprises the cathode-ray tube storage system D3750 described in Specification 804,809 combined with the checking circuit D4474 described in Specification 790,323, in such a way that each word appearing on the 66 datalines of the store is checked with its checking symbol, together with 66 modulo 2 latches, D266, which, once an erroneous word has been detected by the checking circuit D4474 are used to locate the erroneous bits in the word. The checking circuit D4474 has associated with it an indicating device comprising four lamps La- Ld, and four cathode-ray tubes V1A-V1D, synchronized with the cathode-ray tube units of the store D3750 and arranged to normally display a single dot at positions corresponding to the 2000 addresses within the store. When an error is detected by the checking circuit an additional displaced dot is displayed at a position corresponding to the address of the erroneous word, and, as a guide to the operator, one of the four lamps La-Ld is turned on. Thus once an erroneous word has been detected its address will be continually indicated on the four tubes V1A-V1D until it is corrected, as the error will be re-detected during each complete regeneration cycle of the store. The 66 modulo 2 latches, one for each of the 66 bit denominations, are controlled by a control device D262 so that each of them counts on a modulus of 2 the number of zeros appearing on the corresponding data line only during read-in cycles of the store: in this way the 66 modulo 2 latches indicate, by means of 66 associated lamps, the parity of the number of zeros in each bit denomination of the store. Assuming that 2000 words have been entered into the store correctly then when an erroneous word has been detected by the checking circuit D4474 (the error being caused by a spurious pulse in the regeneration circuit) and its address indicated by the cathode-ray tube display unit, the particular bit (or bits) in error can be determined by depressing one of four push-buttons labelled " count modulo 2 " which causes, during the next complete regeneration cycle of the store, all the zeros to be counted again by the modulo 2 latches, and after which, as each zero in the store will have been counted twice, all the 66 modulo 2 lamps should be out: those lamps which are not out therefore indicate the erroneous bits. At this stage the operator would normally withdraw the erroneous word, correct it manually, and re-enter it. He can then either depress a "C.R.T. check reset" push-button which causes the modulo 2 lamps and the error indicating lamps to be turned off, and which also then causes the modulo 2 latches, after having been reset, to make a count of the number of zeros in the store during the next complete regeneration cycle of the store; or alternatively, before depressing the " C.R.T. check reset " push-button, the operator can depress a " modulo 2 reset " push-button followed by two depressions of the " count modulo 2 " pushbutton which causes the zeros in the store to be counted twice, and after which all the modulo 2 lamps should be out. Specifications 719,418, [Group XL (c)], 721,180 and 796,347 also are referred to.