Patent GB-1068101-A (GB)
Title: Improvements in or relating to television standards conversion
Inventor: DAVIES ROBIN EVAN
IPC: H04N7/01
Filed: 1965-02-04
Abstract: 1,068,101. Television standards conversion. BRITISH BROADCASTING CORPORATION. Jan. 25, 1966 [Feb. 4, 1966], No. 4965/65. Addition to 1,052,438. Heading H4F. Input signals at the 525/60 standard are applied to a delay line system 13 made up of 3 1/3 ms. sections 15-18 and output signals are taken from switch 12 which changes con. tact in the sequence, 1, II, III, IV, V, I &c. at the 50 frame/sec. rate (i.e. after each 20 ms.) whereby there is produced a first intermediate signal comprising five out of each six input fields (the sixth, which is within the delay line system, being discarded when the switch moves from contact V to contact I) and in which each 60 c/s. field of 16 2/3 ms. is followed by a redundant information or blank interval of 3 1/3 ms. to make up the 20 ms. appropriate to a 50 c/s. signal. This signal is then applied to a binary delay store 19 which is arranged to increase its delay by 12À7 Ás. following each input line interval. A second intermediate signal is thus produced in which the 525/2 lines of each input field are distributed uniformly throughout the 20 ms. interval of a 50 c/s. field. In effect the 3À33 ms. interval produced by delay system 13 at the end of each field is broken up into 525/2 12À7Ás. intervals throughout the field. Finally, a signal at the 625/50 standard is produced from the second intermediate signal by a line store converter 20 which may be of the type described in Specifications 928,730, 966,318 or 1,025,512. Delay line system 13 is similar to that described with reference to Fig. 1 of the parent Specification. The binary delay store 19 is arranged as described with reference to Figs. 5(a) and 5 (b) of the parent Specification. A modified system, Fig. 2 (not shown), utilizes a binary store which introduces a delay of approximately one line duration following each five or six input lines. Thus the 3À33 ms. interval is redistributed less frequently into bigger intervals. In this arrangement the line converter store is based on the interpolation system of Specification 1,025,512 to allow for the fact that the input lines are not uniformly spaced in time. In this modification the binary store is of a modified form, Fig. 5 (not shown). An arrangement for converting from 625/50 to 525/60 signals is described with reference to Fig. 3 (not shown). The input signal is first applied to a binary store which is arranged to reduce the delay by 10À7 Ás following each input line whereby 10À7 Ás of information is discarded from each line, which is thus reduced from 64 to 53À3 Ás. Furthermore, the shortened lines in the output signal follow each other without gaps whereby the 625/2 of each field are compressed to 16 2/3 ms., leaving a gap of 3 1/3 ms. before the next field. These gaps are then removed by a delay line system which is similar to 13 in Fig. 1, but has five sections and is operated with reducing delay (i.e. the switch rotates in the opposite direction to that in Fig. 1) so that the output signal consists of 16 2/3 ms. fields assembled without gaps and with the fifth field repeated (when the switch moves back from the first to last contact) so as to give six output fields for each five input fields. Finally, the signal passes to a line store converter to convert the 625 lines to 525 and produce an output signal at the 525/60 standard. As a consequence of the contraction of the lines to 53À3 Ás. by the binary store only 1À3 Ás. is left available for synchronizing and switching operations, since the active line duration is 52 Ás. If this is insufficient, the whole system is preceded by a line contraction store consisting of input and output switch rings interconnected by capacitors. The time clock for the output ring is such that it runs slightly faster than the writing clock so as to contract the read-out line length. The binary store delay of 10À7 Ás. may be increased to a value intermediate 10À7 Ás. and the 12À7 Ás. employed in the converter of Fig. 1. By this means a converter which is adaptable to convert either way between 525/60 and 625/50 signals may be produced. A modified system for converting from 625/50 to 525/60, Fig. 4 (not shown), is based on a binary store using delays of approximately one line. The incoming signal is applied to a delay line system based on 3 1/3 ms. sections and controlled to reduce the delay whereby the input 20 ms. fields are contracted to 16 2/3 ms. deletion of the last 3 1/3 ms. and each fifth field is repeated. The lost information in the 3 1/3 ms. intervals is made available at a second output of the system switch which operates one contact ahead of the other. The two output signals are applied to the binary store which operates with reduction in delay to delete one line after every five. Incoming 625 lines are thus reduced to approximately 525 lines. Finally, the signal passes to a line store converter which merely makes timing corrections to delete every sixth line. It is necessary to redistribute the information content in the remaining lines to allow for their subsequent retiming into regular sequence in the final signal. This is done by preceding the whole system by interpolator circuits similar to those described in Specification 1,025,512. The Specification discusses generally a number of minor variations which are necessary to allow for manufacturing errors in the delay elements and lack of a precise phase relationship between input and output signals.