Patent GB-1049812-A (GB)
IPC: G06F13/26
Abstract: 1,049,812. Data processing apparatus. SPERRY RAND CORPORATION. March 20, 1964 [April 1, 1963], No. 11892/64. Heading G4A. A data processor is connected over input and output channels to peripheral devices which may include another data processor, certain of the peripheral devices being connected to the central processor by two input or output channels so that double-length words can be transferred. Data transfers occur at the request of the peripheral devices which may signal an input request, an output request or an external interrupt, and each of these types of transfer may take place in single channel mode or dual channel mode according to the word length required by the requesting peripheral device. For dual mode transfer two memory access cycles are required in the data processor. Means are provided for allotting priority to the peripheral devices on the basis of the type of function requested and the number of the channel making the request, and thereby generating a memory address at which a control word consisting of the memory address of the last data word of a block of data words transmitted over a particular channel is to be stored. The address of the control word is used to derive the address of a current control word specifying the address at which the next word is to be read out or stored, this word subsequently being incremented by one or two according as the single or dual mode of transfer is in operation. In the case of an external interrupt operation, two control words are generated, one designating the address at which the incoming word is stored and the other designating the address of a jump instruction controlling a subroutine to take appropriate action according to the nature of the interrupt. General arrangement.-The data processor described is a medium sized digital computer 31-1, Fig. 31 (not shown), having an 18-bit word length and peripheral equipment such as a drum, tape or printer requiring 18-bit transfers. The computer 31-1 is connected also to a further peripheral device in the form of a large digital computer 31-2 employing 36-bit words so that data transfers between the two computers are of double length. The peripheral devices are connected to the control computer over 18-bit input and/or output channels which are numbered consecutively, transfer of a 36-bit word taking place over adjacent even and odd numbered channels, the even-numbered channel being for the least significant digits. As shown in Fig. 1 (not shown), the computer has eight input channels CH-0 to CH-7 and eight output channels CH-0 to CH-7, all the channels being connected to the Z register (memory buffer register) via cables 1-2, 1-6. The memory 1-4 is addressed by the S-register which can receive the contents of the P register via cable 1-7, the contents of the P register being applied via the X register and a cable 1-9 to an adder (which is of the subtractive type, as described in Specification 1,015,175), where the desired increment Œ 1, Œ from the D register is added, the result being returned to the P register. The adder is also used to compare the terminal control word with the current control word during an input or output operation, the terminal control word being read out from the memory to the X register whence its complement is entered via cable 1-13 in the D register. The current control word is then read out of the memory to the X register, the contents of the D and X registers are applied to the adder, and if the control words are equal, a signal X=D<1> is emitted to terminate the transfer. Execution sequencing.-The execution of instructions is controlled by a sequence control circuit 1-28, there being an I sequence in which an instruction is withdrawn from the memory, an RC sequence in which a control word is read from the memory for an input or output operation, a WC sequence which modifies and returns to the memory a current control word, and an R/W sequence in which transfer of a data word takes place. These sequences are executed under the control of sequence control circuits (Fig. 3, not shown). Channel controls.-The channel controls 1-30, Fig. 1 (not shown), shown in more detail in Fig. 2 (not shown), are effective inter alia to general six bits of the address of the terminal control word in an input or output operation and to generate six bits of the address at which an incoming code word is to be stored in an external interrupt operation. In request oneshot circuits, out request one-shot circuits and EI one-shot circuits are connected to the input and output channels and are effective to store any requests received. The various one-shot circuits are connected to function priority circuits 2-1, Fig. 2, and to channel priority circuits 2-2. Output requests have the highest priority, followed by input requests, followed by external interrupts. When the highest priority function has been determined, signals are produced onlines 2-17 which prevent all signals except those of the highest priority from setting the channel priority circuits 2-2, which circuits include an 8-stage register allotting priority to the eight channels in numerical order, channel 8 having the highest priority. The channel priority circuits 2-2 generate a 3-bit binary representation of the channel which is to be effective, this representation being applied to a V register and translator 2-3, the V-register providing enabling signals for other registers in Fig. 2 and the translator providing three bits of a memory control word address on leads 2-21, three further bits being provided by the function priority circuits 2-1. There is also provided an input acknowledge register which transmits a signal when storage has been completed in an input operation; and an output acknowledge register which transmits a signal to a requesting peripheral device when a word is stored in the C register, Fig. 1, for transmission to the device. Mode selection.-Switches S1, S3, S5, S7, Fig. 5D (not shown), are provided, and if changed over will cause the dual transfer mode to be selected when the corresponding channel 1, 3, 5 or 7 initiates a request. Circuit details.-The Specification describes in detail the various circuits shown in block form in Figs. 1 and 2 and also describes in detail the performance of a data transfer operation.