Patent GB-1165268-A (GB)
Title: PCM Synchronisation Circuit
IPC: H04J3/06
Filed: 1967-03-03
Abstract: 1,165,268. Multiplex pulse code-signalling. INTERNATIONAL STANDARD ELECTRIC CORP. 3 March, 1967 [9 March, 1966], No. 10176/67. Heading H4L. In an electrical synchronization circuit arrangement for an exchange to which are connected a number of pulse code modulated trunks, desynchronization due to frequency drift of the trunks is eliminated by a first section of the arrangement wherein:- (a) each incoming trunk carries m (e.g. 24) channels, one of which (the 24th) carries a frame synchronization code while the other M-1 channels carry message codes and each code is an n bit serial code; (b) the incoming trunks are assembled into groups of n trunks (1 to n); (c) a clock CU, Fig. 2, produces channel pulses t 1  to t 24 , bit pulses M1 to M6 within each channel pulse, and basic time pulses a, b, c, d within each bit pulse; (d) each code is received serially from each trunk and thereafter is dealt with in parallel format during a bit pulse appropriate to code's trunk, e.g. a message code in the 10th channel of the 4th trunk is dealt with during the bit pulse t 10 .m 4 ; (e) each incoming trunk has a repeater 101, Fig. 3 which operates on the incoming codes serially to produce corresponding codes at 11, free of jitter and comprising pulses having widths equal to a basic time pulse, and reference signals Y at the mean frequency of the code bits, which by means of counter 113, produce six cyclically appearing pulses at said mean bit rate, K1, K 2 - K6, each K6 pulse producing by means of counter 112 three cyclically appearing pulses at the mean channel rate, g 1 , g 2 , g 3 ; (f) a phase correction memory 111 having six columns and three rows stores the codes at 11 under the control of the pulses K1 ... K6 and g 1  ... g 3  and the codes are read out of the memory in parallel forward during the appropriate bit pulse as defined in (c) above; (g) a frequency drift detector 130 compares the time positions of pulses K1... K6 and g 1  . ., g 3  with those of locally generated bit time pulses and gives a drift signal N<SP>1</SP> on P<SP>1</SP> indicative of the direction of drift whenever frequency drift on the trunk exceeds a predetermined value; (h) each group of n trunks has a group data store 200, Fig. 4 with non storage sections to which the read out pulses from memory 111 are fed; (i) a detector DS produces a desynchronization signal if a frame synchronization code CSy is not received from memory 111 during channel pulse t24; (j) the frequency drift signals of (g) above are recorded in the appropriate portion of a group instruction store 151, comprising six rows, one per trunk and when read out therefrom at the appropriate bit pulse cause a drift correction consisting firstly of the application of a lead or a lag correction to the reading means of memory 111 and secondly of a lag or lead correction to the write means of said group data store, so that all message codes received for that trunk are written without error or omission into said group data store. Frame synchronization of all the incoming trunks is controlled by a second section of the arrangement wherein:- (k) all the groups of trunks are selected cyclically until a desynchronization signal is detected (see (i) above), said signal then stopping said selection; (1) all the trunks of the faulty group are selected cyclically until the desynchronized trunk is detected, whence said trunk is connected to a synchronization circuit wherein; (m) the frame synchronization code is examined three times successively during channel times t24, detected synchronization causing the cyclic trunk selection of (1) to be resumed, and detected desynchronization causing examination of all the received codes until the frame synchronization code is detected; (n) the time between the occurrence of said detected code and its assumed position (t24) is used as a phase correcting signal in the manner given in (j) above. Extensive logic diagrams of all circuits are given.