Patent GB-1233601-A (GB)
IPC: G06F9/48
Filed: 1968-04-26
Abstract: 1,233,601. Data processor. PLESSEY CO. Ltd. 24 March, 1969 [26 April, 1968], No. 20063/68. Heading G4A. The invention relates to a priority interrupt system for use in multi-programme time-sharing data processors. Each programme and each peripheral equipment served by the processing device has its own interrupt channel containing a flip-flop ITN raising an interrupt demand. The channel circuits are divided into groups of eight, each group served by an address generator AG and a demand sorter DS. Demand leads 1-8 in one group are fed in priority order to the sorter DS, the lowest number having the highest priority. In the embodiment described the channels are allocated to three system programmes, two peripheral devices and three working programmes in that order of priority. In normal operation at least one working programme must be raising an interrupt demand assuming that the lowest priority programme is running. A Parameters Address List store PAL has eight locations each corresponding to an interrupt channel and each with an address corresponding to the address generated by the channel, the data in the locations holding the addresses in a main store ST at which parameters for programmes allocated to the interrupt channels may be found. If a higher priority interrupt demand occurs, e.g. on line 6, while a current instruction is being processed, Signal IDS from the Interrupt Buffer Control Logic is 0 and inhibits the new demand from generating signal INT. At the completion of the current instruction IDS becomes " I " an INT signal is generated and address generator AG generates 101 on leads DAL 1-3. The address is written into an Incoming Priority Register IPR and compared with the address in the Current Priority Register CPR by comparator PAC. If a difference occurs, PAC generates an Internal Interrupt II if the current priority level is greater than the incoming level and an External Interrupt EI otherwise, the latter occurring in the present case. The EI signal is received at control IBCL as an interrupt and causes activation of micro-commands which cause storage of the parameters of the interrupted programme and read out of the PAL store location 6. The parameters of the interrupting programme are then obtained. If a lower priority programme is required, its interrupt flip-flop remains set until the programme can be used. A programme which is running may require one of the peripheral devices in which case the current programme must be suspended and the generally slower working peripheral device is ready to perform the required transfer. This allows any lower priority intercept to have priority while the higher priority programme is suspended. When the peripheral device is ready to transfer it generates a high priority intercept which also releases the programme requiring transfer from suspension so that after transfer the programme continues. If the lower priority B programme occurring when the first programme A was suspended required an interrupt then programme A would be interrupted when the peripheral device was ready for transfer but would be resumed afterwards. Processor controlled instructions allow priority levels to be changed or overcome.