Patent GB-761968-A (GB)
Title: Improvements in or relating to multiplying arrangements for digital computing machines
Inventor: WILLIAMS FREDERIC CALLAND
IPC: G06F7/52
Filed: 1952-01-31
Abstract: 761,968. Digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Jan. 23, 1953 [Jan. 31, 1952], No. 2640/52. Class 106 (1). A multiplying arrangement for an electronic binary digital computer includes a multiplier circuit in which an x-digit multiplicand signal is entered in parallel while a multiplier signal is entered in serial form, the multiplicand being read out from storage means in separate x-digit sections, and control means operated by a single programme instruction signal by which a first x-digit multiplicand section is applied to the parallel inputs of the multiplier circuit while the whole multiplier is applied to the serial input, and a second x-digit multiplicand section and the multiplier are thereafter similarly applied, the first and second partial product signals thus produced being combined in accumulator means. General arrangement. The multiplying arrangement, the main portions of which are shown diagrammatically in Figs. 10a-10c, includes the units shown in Fig. 1 which form part of a machine similar to that described in Specification 742,522. The basic waveforms, including those shown in Fig. 11 (a)-(f) and Fig. 12 (a)-(p), are generated in unit WGU. The main store MS includes 16 C.R.T.'s each having 64 20-digit lines which are selected by the e and digits respectively of an instruction, Fig. 11 (j), registered on the staticisor MSTR, Fig. 10a. A control unit CL causes present instructions PI to be selected from the store MS sequentially by control instructions CI, (see Fig. 12), which are increased by "1" at the beginning of each operation or " bar ". The accumulator A and multiplier M, Figs. 1 and 10a and 10c, each have a C.R.T. with 4 lines to accommodate respectively an 80-digit product and two 40-digit factors. A multiplying operation involves two instructions which are carried out in 5- and 11- beat bars respectively, Fig. 12. The first instruction causes the transfer of the multiplicand D to two lines d 0 , d 1  of the multiplier tube MT, Fig. 10a, and has two variants S<SP>1</SP>D, SD used according to whether or not the number D is of signed form (in which a negative number is represented by its complement with a " 1 ", representing " minus ", in the most significant pulse position). The second instruction causes the transfer of the multiplier R to lines r 0 , r 1  of tube MT and the multiplication of the whole of R successively by the first and second 20 digits respectively of D to form two partial products which are combined in the accumulator, and has four variants SR, S<SP>1</SP>.R, - SR, - S<SP>1</SP>.R used according to whether the number R is of signed or unsigned form and whether the partial products are to be added or subtracted in the accumulator by means of unit AU or SU respectively, Fig. 10c. The four lines of the tubes MT, AT, Figs. 10a and 10c, are selected by Y-shift generators MYG, AYG Fig. 18 (not shown), each controlled by two trigger circuits F31, F32 or AYCO, AYC1. Circuit symbols; delay networks. The symbols used in Figs. 10a-10c for " and " and " or " gates, differentiating circuits and bi-stable trigger circuits are similar to those employed in Specification 742,522. Fig. 7a shows the symbol used for a one-digit-delay network, Fig. 7b, which is primarily controlled by positive " pause " pulses, Fig. 11 (b), applied at 44 which occur during every digit period except in the " black-out " period defined by waveform BO, Fig. 11 (c). Thus a negative pulse, e.g. in a number signal, Fig. 11 (i), will normally be delayed by one digit period, but a pulse occurring in position P19, Fig. 11 ( f will be delayed until position P 0'  Fig. 11 (d), of the following beat. Addition and subtraction. The adding and subtracting devices employed, such as AU, SU, Fig. 10c, may include gates inverters or " not " devices and a " carry " delay network arranged as shown in Figs. 8b and 9b respectively. Multiplication; sequence of operations. For a D-operation, the address portion (l and e digits, Fig. 11 (j)) of the D-instruction selects the first or lower 20-digit portion of D which is read out from the main store MS through gate G 113 during beat A2 and passed to line d 0  of tube MT owing to the condition in which triggers F31, F32 (see Fig. 12 (r) and (s)) are set by the output of gate G118. At the beginning of the following beat A3, " 1 " is added into the address-section of the staticizor MSTR to select the second 20-digit portion of D which is passed to line d 1  of MT since F31 is switched over by the differentiated BO waveform. Also during A2, the function digits f, Fig. 11 (j), of the D- instruction control gates G130, G131, Fig. 10b, whereby trigger F34 is set so as to apply a relatively positive or negative potential on line 135 according to whether or not D is of.signed form. For an R-operation, which need not follow immediately a D-operation, the first 20-digit portion of D is read out through gate G115 during beat S2 and set up on staticisor MTR, Fig. 10c, comprising trigger. circuits W0-W19 which are previously reset by a pulse P20 applied to gate G117. During the following beats A2, A3 the first and second 20-digit portions of R are read out from MS and passed to lines r 0 , r 1  of MT, trigger F32 being switched to its reset state (see Fig. 12 (r)) by the output of gate G121. Also, the conditions of the MG and MCd waveforms, Figs. 12 (g) and (r), obtained from triggers F33 and F32, Fig. 10a, allow R to be passed through gate G137 and complement converter CCV to line 205 connected to gates G219- G200, Fig. 10b, controlled by the outputs of triggers W19-W0 respectively; these gates form part of a multiplying circuit similar to that described in Specification 705,476 and also including series-connected delay networks DL19- DL1 and adding devices AD18-AD0. The output on line 202 representing the first partial product is passed to the accumulator tube AT the four lines a 0 -a 3  of which are scanned sequentially starting with beat A2 (see Fig. 12). The formation of this partial product requires four beats A2, A3, S3, B4, Fig. 12, and during the next beat S5, the defining waveforms for which are obtained from F35, Fig. 10a, which is triggered during R-operations through gate G200, triggers F31, F32 are set so that line d 1 , containing the second (more significant) portion of D is read out through gate G115 to set up staticisor MTR. During the next three beats S6, S7, B8, the number R is read out from MT through gate G137 and the second partial product is formed and sent to lines a 1'  a 2 , a 3  of AT. The first two beats of the next bar may overlap the R-operation bar as shown in Fig. 12, and the next prepulse, which would otherwise occur after A3, is inhibited until S7 by waveform INV 7S, Fig. 10b. If D is of signed form, the normal negative inhibiting potential on line 135 is removed during beats S6, S7, B8 so that the pulse train representing R obtained from gate G219, if there is a " 1 " in the most significant position of D registered on W19, is complemented in circuit CDV (Fig. 17, not shown) instead of being passed through unaltered. If R is of signed form, a negative operative potential is applied from gate G127, Fig. 10a, to complement converter CCV (Fig. 16, not shown) during beats A3, S3, B4, S7, B8, which causes the most significant digit of R (which is applied to CCV at pulse time P19 of beats A3, S7) to be repeated, so that R is extended to allow for the fact that the product registered on A has 80 digits. Other features. The staticisor MTR, Fig. 10c, may be used also for magnetic instructions involved in transfers between the main store and a subsidiary magnetic drum store as described in Specification 742,522. The connections for the units ADO, AU, SU, Figs. 10b and 10c, may be modified (Fig. 20, not shown) to permit compensation for unwanted delays, e.g. in the unit ADO. Specification 705,477, [Group XL(c)], also is referred to, and in the Provisional Specification reference is made to Specifications 705,479 and 731,341.