Patent GB-1456659-A (GB)
Title: Receiver for a facsimile system of run-length type
IPC: H03M7/46
Filed: 1973-11-15
Abstract: 1456659 Data transmission; facsimile systems MATSUSHITA ELECTRIC INDUSTRIAL CO Ltd 15 Nov 1973 [15 Nov 1972 (2)] 22940/76 Divided out of 1456658 Headings H4P and H4F The description is the same as Specification 1,456,658 from which the present application has been divided but the claims are directed towards a facsimile receiver having a timing generator producing clock, horizontal sync. and blanking pulse trains, with a demodulator and decoder producing run length mark/space codes feeding selectively into a memory of two or more registers, which are sequentially read (then cleared) into a reconverting circuit producing the original run length mark and space signals. Receiver.-Clock pulse generator 90 output is successively divided at 91-93, the latter producing a horizontal sync. train and blanking pulse train. Demodulator 81 receives c.w. signals and produces marks and spaces also a vertical sync. train and preferably utilizes a train from divider 92 as a sub-carrier by modulating it with received c.w., the resultant being envelope detected. Decoder 92 includes a vertical sync. pulse separator. A circuit 97 adjusts timing pulses to incoming signals. A higher 0 bit separator 99 issues pulses representing higher 0 bits which are clocked through controller 100, disabled at certain intervals by the vertical sync. train, into counter 102. Separator 99 also applies a shift train in sync. with clock pulses to register 103 and when coincidence is reached with 102, matrix 101 produces an output. SR103 may be connected selectively to SR106 or SR107 through selector 105 in accordance with address from controller 108: more than two registers may be provided. Reconverting circuit 84 has an AND 111 passing clock pulses to counter 112 when pulsed by sweep gate generator 104, counter 112 being reset when priming ceases. Another counter 115 is reset by vertical sync. pulses 115, also receiving clock pulses through AND 113 and primed by a mark or space signal from FF114. Coincidence of 112, 115 is detected by 116 which resets FF114 hence 115 accumulatively memorizes numbers corresponding to run lengths produced by FF114. Output of AND 113 is also passed through 1 bit eliminator 117 into a third counter 118 which is cleared by the trailing edge of each output pulse of FF114. When content of counter 118 compared with a selected one of registers 106, 107 is detected by coincidence circuit 119, flip-flop 114 is reset. A mark and space identifying circuit 120 produces a 1 output to prime AND 121 thus pass only marks from flip-flop 114. The recorder (Fig. 13c, not shown) has a tube (122) with a flying spot moving in horizontal direction by a deflection element (124) across a fibre optic face plate (123) when element (124) is energized by a sawtooth deflecting voltage, and an accelerating voltage from (126) is applied to appropriate electrodes. A recording medium (127) is actuated intermittently by a stepping motor. The flying spot is modulated in intensity by (131) in accordance with mark pulses through AND 121. The equipment at transmitting end to produce run length marks and spaces (Fig. 5a, not shown) is of similar configuration and includes a fibre optic cathode ray tube (20) and face plate (21).