baber/WOPTO huggingface dataset:
Patent TW-417300-B (TW)
Title: Manufacturing process of vehicle rectifier
Inventor: LIN JIN-FENG
IPC: H01L29/00
Filed: 1999-04-23
Granted: 2001-01-01
Abstract: The present invention relates to a manufacturing process of a vehicle rectifier. At least a piece of cotton cloth is selected and cut to have a shape corresponding to the shaping mold of the vehicle rectifier, and is placed on a mold plate. The shaping mold is placed on the mold plate. In each small hole of the shaping mold, there is placed a semi-product to be encapsulated. A piece of cotton cloth is covered on the shaping mold. There is an aperture defined in the cotton cloth, and the injection opening is directed to the opening of the cotton cloth. Finally, a mold injection process for shaping is executed until a product is completed. The cotton cloth is able to effectively restrict the range of the epoxy resin on the vehicle rectifier, and thus the step to cut off the excessive epoxy resin is not required, thereby decreasing the waste of material, saving processing time and enhancing the quality of the product.
Patent TW-429696-B (TW)
Title: Synchronization acquisition apparatus and method thereof
Inventor: KIM SI-HYEON
IPC: H04B1/7075
Filed: 1999-05-29
Granted: 2001-04-11
Abstract: A synchronization acquisition apparatus and a method thereof are disclosed. The apparatus includes a first comparator for comparing the maximum value detected by the detector and a first threshold value, a second comparator for comparing the maximum value and a second threshold value, a first block for updating the maximum value among the values integrated over the first integration interval to the maximum value, a third comaprator for comparing the maximum value and a third threshold value, a second block for initializing the count, a fourth comparator for comparing the PN code offset and the PN code period, a third block for increasing the count, a fifth comparator for comparing the count and a post detection search time (PDT), a fourth block for increasing the PN code offset, a sixth comparator for comparing a second integration value integrated over the second integration interval and a fourth threshold value, a seventh comparator for comparing the second integration value and a fifth threshold value, a fifth blocd for updating the maximum value among the values integrated over the second integration interval to a second integration result value, and a plurality of switches for selectively outputting the output of the variable integrator to the detector or the sixth comparator, for thereby obtaining a reliable signal level under any environment and implementing a quick synchronization acquisition without checking all PN code offset.
Patent TW-446896-B (TW)
Title: System and method for creating an object workspace
Inventor: NOTANI RANJIT N
IPC: G06Q10/00
Filed: 1999-08-17
Granted: 2001-07-21
Abstract: A computer workspace comprises a plurality of memory slots, the memory slots each operable to store at least one object. The computer workspace further comprises a permissibility framework in communication with the computer workspace, the permissibility framework maintaining access rights to each memory slot. The computer workspace further comprises an event manager in communication with the memory slots and the permissibility framework, the event manager being operable to generate messages in response to the memory slots being accessed and further in response to the access rights maintained by the permissibility framework.
Patent TW-441156-B (TW)
Title: Starting method for DC brushless motor and the device thereof
Inventor: WANG KING-YIN
IPC: H02P6/21
Filed: 1999-06-08
Granted: 2001-06-16
Abstract: The present invention relates to a starting method for DC brushless motor and the device thereof, especially to a starting method for open-loop single phase DC brushless motor and the device thereof. According to the disclosed technique, the starting of the motor is divided into the oscillation swinging stage and the starting operation stage. At the beginning of the motor starting, firstly sending an oscillation signal to the driver to make the motor rotate forward and backward; when the motor rotor leaves the starting dead point position, it immediately sends an operating signal to make the motor rotor rotate in single direction; therefore, when starting the motor, the rotor can leave the starting dead point so that the motor can operate under a low cogging torque.
Patent TW-I228311-B (TW)
Title: Method of preventing corrosion of the metal wire exposed from the unlanded via
Inventor: TAU HUNG-YUAN
IPC: H01L23/522
Filed: 1999-06-14
Granted: 2005-02-21
Abstract: This invention is to provide a method of preventing corrosion of the metal wire exposed from the unlanded via, which is suitable for the semiconductor substrate on which the metal wire is formed. The present invention comprises the following steps: First, form a layer of low dielectric material onto the semiconductor substrate on which metal wires are formed; secondly, selectively etch the above-mentioned layer of low dielectric material to form a via with exposure of part of the above-mentioned metal wires, in which the above-mentioned via is the unlanded via; then, form a thin oxidation protection layer onto the surface of the afore-mentioned exposed metal wire by utilizing the treatment of H2O plasma or H2O/N2 plasma. By the disclosed method, the via poison phenomenon can be improved, and corrosion in the metal wire can be prevented.
Patent TW-451584-B (TW)
Title: Reducing striped noise in CMOS image sensors
Inventor: MERRILL RICHARD B
IPC: H04N5/3745
Filed: 1999-06-17
Granted: 2001-08-21
Abstract: A pixel sensor array structure which reduces the amount of striped fixed pattern noise includes a plurality of pixel sensors arranged in an array; a column line for each column in the array, each column line coupled to the pixel sensors associated with that column; a plurality of load devices, each load device coupled to one of the column lines and to a column reset reference potential; a plurality of column select switches, each column select switch coupled to one of the column lines; and a common line, the common line coupled to the column select switches and to a buffer amplifier. A unity-gain buffer amplifier may be coupled to the common line and to a driven shield, which acts to reduce the effective capacitance of the common line. The column select switches transistors may be designed with an annular layout to reduce the capacitance they add to the common line. The load devices may be designed with a relatively large length and width to minimize variations in their bias currents. Alteratively, the load devices may be operated as column reset switches. The pixel values of a specific row may then be read out by discharging all of the column lines in the array to ground using column reset switches; turning off column reset switches and driving a row-select line high for an appropriate row, which connects source followers to the column lines; waiting a predetermined time for the column lines to be charged; selecting one column line at a time to connect to the common line, thereby sharing the charges between the selected column line and the common line; and buffering the voltages on the common line. A two-tap FIR filter may be coupled to the array amplifier to correct pixel values which may be blurred when fast multiplexing is used. The array structure may be designed such that the fixed pattern noise due to random variations in the pixels is at least 100 times the variance of the fixed pattern noise due to striped noise, so that any striped noise that appears will be much less noticeable.
Patent TW-416125-B (TW)
Title: Semiconductor device and its manufacturing method
Inventor: MOCHIZUKI HIDENORI
IPC: H01L21/768
Filed: 1999-06-17
Granted: 2000-12-21
Abstract: A semiconductor device and its manufacturing method are provided. There is formed an insulation film 3 on a semiconductor substrate 1, having a gate electrodes 22 and source/drain electrodes 12. There are formed contact holes 41, 42 through this film by exposing the top of the adjacent gate and source/drain regions. In the contact holes, there are formed conductive plugs 61, 62. A film is formed on the top of the conductive plugs and insulation film. When etching the conductor film to form a lower wiring 7, a cover 8 made by the conductor film is formed on the conductive plug that is not connect to the wiring. With the present method, it is able to prevent the conductive plug 61 from being damaged, and the number of steps required for manufacturing a semiconductor device than in the prior art is reduced.
Patent TW-524036-B (TW)
Title: Electronic machine and manufacturing method and punching apparatus for frame of electronic machine
Inventor: HOSOI TAKASHI
IPC: H05K5/04
Filed: 1999-06-17
Granted: 2003-03-11
Abstract: The present invention relates to a manufacturing method for frame (30) of electronic machine, especially a manufacturing method for a frame (30) equipped with a rib (32) of a certain height and has a plug-hole (33) formed in the width direction on the inner side of the rib (32). The present invention is characterized in including a metallic die forming process, an installation process, and a hole-punching process. The metallic die forming process is to form a finished metallic die (50) that has a rib (32) of a certain height and, in the width direction on the inner side of the rib (32), a recess (51) of the base wall (52). The installation process is to use a recess press die (64) that is formed corresponding to the recess (51) and has a punch plug-hole (65) in its inner side and seized on the base wall (52) for securing the finished metallic die (50). The hole-punching process is, by using a punch (66) to punch the base wall (52) on the inner side of the punch plug hole (65), to form a plug-hole (33) on the opposite side of the base wall (52) seized by the recess press die (64) of the finished metallic die (50).
Patent TW-460801-B (TW)
Title: Debugging client server programs from third party workstations
Inventor: MASTRANGELO COLETTE A
IPC: G06F11/36
Filed: 1999-07-30
Granted: 2001-10-21
Abstract: A debugging apparatus for debugging a particular application, session or transaction in a computer network environment. The environment includes a plurality of clients in processing communication with one another. The apparatus comprises identifying means for identifying a debugging mechanism to the computing environment, a debug table accessible to the debugging apparatus for storing any pertinent information relating to said debugging apparatus, identifying means for identifying at least one client present in the environment. The debug table stores any and all pertinent information about any identified clients as well as whether or not a particular application, session or transaction needs to be debugged. A determining means is also provided for determining if a particular application, session or transaction needs debugging so that debugging operation can be started accordingly.
Patent TW-466897-B (TW)
Title: Method of manufacturing laminate and grommet used for the method
Inventor: NAKAJIMA SHIGEKI
IPC: H05K3/46
Filed: 1999-08-16
Granted: 2001-12-01
Abstract: A method of manufacturing a laminate obtained by laminating a plurality of plate members such as wiring plates (1) and prepregs (2), comprising: a step of temporarily fixing the plate members by a grommet (3) having plural resin filling holes (9) formed on the side surface thereof to obtain a temporarily-fixed laminate (5); and a step of heating and pressurizing the temporarily-fixed laminate (5) to fill the resin melted from the prepregs (2) of the temporarily-fixed laminate (5) through the resin filling holes (9) of the grommet (3) into the throughhole (6) of the grommet (3).
Patent TW-426919-B (TW)
Title: Method for performing a low-temperature thermal annealing process on a gate oxide
Inventor: YANG SHIN-JIA
IPC: H01L21/324
Filed: 1999-08-17
Granted: 2001-03-21
Abstract: There is disclosed a method for using active atoms to performing a low-temperature thermal annealing process for MOS devices, which comprises: providing a semiconductor substrate; depositing an insulation layer on the semiconductor substrate; using active atoms to perform a thermal annealing process for the insulation layer, so as to repair the defects of the atoms in the insulation layer, thereby decreasing the leakage current of the insulation layer, wherein the active atoms are selected from the group consisting of active nitrogen atoms, active oxygen atoms, and an arbitrary combination of the two atoms; and forming a gate on the insulation layer, and the gate, the insulation layer and the semiconductor substrate forming a MOS structure.
Patent TW-476021-B (TW)
Title: A water-dispersible negative-type photosensitive composition
Inventor: LIN HSIEN-KUANG
IPC: G03F7/038
Filed: 1999-09-08
Granted: 2002-02-11
Abstract: A water-dispersible negative-type photosensitive composition is disclosed. It is suitable to be used as an etching resist or a solder resist in the printed circuit board. The photosensitive composition comprises (a) a carboxyl-group containing acrylic resin with Tg in the range of 95 to 135 DEG C; (b) 5 to 20 parts by weight of a photoinitiator, based on 100 parts by weight of an acrylic resin in (a); (c) 10 to 15 parts by weight of an unsaturated photomonomer with the number of unsaturated groups being equal to or greater than 5; (d) an alkaline which neutralizing more than 40% of carboxyl groups in the acrylic resin; and (e) 0. 2 to 5 parts of a water-souble resin which being selected from the groups of cellulose resin, gelatin, polyvinyl alcohol and copolymer of acrylamide. Water is served as a main solvent of the photosensitive composition disclosed in the invention. The amount of an organic solvent replaced by water could be more than 90%. The performances of this photodensitive composition are the same as the traditional solvent type.
Patent TW-446953-B (TW)
Title: Method and structure for testing embedded memories
Inventor: RAJSUMAN ROCHIT
IPC: G06F11/267
Filed: 1999-10-11
Granted: 2001-07-21
Abstract: A method and structure for testing embedded memories in an integrated circuit chip having a microprocessor core therein. The method includes the steps of: testing the microprocessor by applying thereto a test pattern and evaluating the resultant output of the microprocessor; applying an assembly language test program to the microprocessor; generating a memory test pattern by the microprocessor based on the assembly language test program; applying the memory test pattern to the embedded memory and evaluating the resultant response of the embedded memory by comparing the response with the original data.
Patent TW-416845-B (TW)
Title: Liquid transport member, liquid transport system, article comprising a liquid transport member of a liquid transport system, and method for manufacturing a liquid transport member
Inventor: EHRNSPERGER BRUNO JOHANNES
IPC: B65D47/20
Filed: 1999-10-13
Granted: 2001-01-01
Abstract: The present invention is a liquid transport member with significantly improved liquid handing properties, having at least one bulk region completely circumscribed by a wall region, and which comprises at least one port region, where the product of the bubble point pressure of the port region multiplied with the bulk region permeability is higher than half of the product of the porosity of the member multiplied by the surface tension of the transported liquid.
Patent TW-436925-B (TW)
Title: Apparatus for forming coating film
Inventor: HAYASHI SHINICHI
IPC: B05C11/08
Filed: 1999-10-28
Granted: 2001-05-28
Abstract: This invention provides an apparatus for forming a coating film, including: a treatment portion for performing a series of treatment processes to form a coating film on a substrate; a common transport mechanism for transporting the substrate in the treatment portion; the treatment portion including: a cooling unit for cooling the substrate; a coating unit for coating the substrate with a coating liquid containing a first solvent to form a coating film; an aging unit for transforming the sol in the coating film formed by the coating unit into gel; a solvent exchange device for exchanging the first solvent in the coating film for a second solvent by contacting the coating film with the second solvent that has a composition different from that of the first solvent with the coating film; a curing treatment unit for heating and cooling the substrate in a low oxygen concentration gas environment to thereby cure the coating film; and a heating unit for heating the coating film on the substrate.
Patent TW-480711-B (TW)
Title: Method for forming self-aligned, rugged, and extended crown-shaped capacitor of high density random access memory (RAM)
Inventor: WU SHIE-LIN
IPC: H01L27/108
Filed: 1999-11-04
Granted: 2002-03-21
Abstract: The invented method comprises: forming a first oxide layer on a substrate; forming a nitride layer on the first oxide layer; forming a second oxide layer on the nitride layer; forming a first silicon layer on the second oxide layer; defining an electrode opening in the first silicon layer, the second oxide layer and the nitride layer; forming a sidewall structure on the two sides of the electrode opening; defining a contact opening in the first oxide layer and removing the nitride layer on the sidewall structure and the portion near the electrode opening to form an undercut structure below the second oxide layer; forming a second silicon layer uniformly covering in the contact opening, the undercut structure, the electrode opening, and on the first silicon layer; forming and defining an electrode upper end definition layer on the second silicon layer to retain an electrode upper end definition region; removing the second silicon layer and a portion of the first silicon layer not covered by the electrode upper end definition region; forming a silicon sidewall on the sidewall of the electrode upper end definition region, in which the silicon sidewall forms a conformal electrical connection with the second silicon layer and the first silicon layer in order to form an electrode; removing the electrode upper end definition region and the second oxide layer; removing the nitride layer; forming a dielectric layer uniformly covering on the electrode; and forming a conductive layer on the dielectric layer.
Patent TW-479241-B (TW)
Title: Method of recording a multi-layer optically recordable information carrier
Inventor: WIERENGA HARM ALBERT
IPC: G11B7/0045
Filed: 1999-11-08
Granted: 2002-03-11
Abstract: The application relates to a method of and an apparatus for writing information onto a multi-layer optical information carrier (1). In an optical recording system information can be written onto a selected layer (41) of a multi-layer carrier (1) by focusing the laser beam (2) onto the selected layer. Intermediate layers (42) interact with the laser beam (2). An important property in writing information onto a multi-layer carrier (1) is the transmission coefficient of these intermediate layers (42). The transmission coefficient depends on the physical properties of the intermediate layer (42) and on whether or not information has been recorded. The apparatus includes a circuit (55) which derives information (711) about the changes of the transmission coefficients of the layers (41 through 43) when information is written onto these layers. On the basis of this information (711) a circuit determines the sequence in which the layers (41 through 43) are to be recorded. The sequence can be selected so as to minimize the intensity of the laser beam (2), thereby precluding unnecessary heating of the carrier (1) and allowing comparatively simple and cheap laser beam sources (3) to be used.
Patent TW-504568-B (TW)
Title: Ultrasonic flowmeter
Inventor: IWANAGA SHIGERU
IPC: G01F1/66
Filed: 2000-03-17
Granted: 2002-10-01
Abstract: An ultrasonic flow meter of the present invention includes: a measurement flow path 6 through which a fluid to be measured flows; ultrasonic transducers 8 and 9 provided respectively on an upstream side and a downstream side with respect to each other along the measurement flow path 6; an upstream aperture hole 11 and a downstream aperture hole 12 for exposing the ultrasonic transducers 8 and 9 to the measurement flow path 6; a first influent suppressor 15 provided in a vicinity of at least the downstream aperture hole 12 for reducing inflow of the fluid to be measured into the aperture hole 12; a second influent suppressor 16 provided on an upstream side of the measurement flow path 6 for reducing the inflow of the fluid to be measured into the aperture holes 11 and 12; a measurement control section 19 for measuring a propagation time of an ultrasonic wave between the ultrasonic transducers 8 and 9; and a calculation section 20 for calculating a flow rate based on a signal from the measurement control section 19. The first influent suppressor 15 provided for the downstream aperture hole 12 comprises an aperture hole sealing section 21 having at least one ultrasonically transmissive hole 22. Thus, it is possible to stabilize the flow between the ultrasonic transducers so as to enhance the ultrasonic reception level, thereby increase the measurement precision and the upper limit value for the flow rate measurement, and reduce the driving input for the ultrasonic transducers.
Patent TW-523462-B (TW)
Title: Method for making a seamless apertured metal belt
Inventor: MCGUIRE KENNETH STEPHEN
IPC: B29D28/00
Filed: 2000-04-08
Granted: 2003-03-11
Abstract: The present invention provides a method for making a seamless apertured belt comprising the steps of: (a) providing a strip of material having two opposing ends and having a length at least equal to a finished belt length; (b) providing an aperture pattern having a length substantially equal to the finished belt length, the pattern including a plurality of two-dimensional geometrical shapes, the pattern having opposing end edges which can be tiled together; (c) removing a pre-determined portion of each end of the pattern and joining the pre-determined portions to one another along the opposing end edges to form a re-etch pattern; (d) forming apertures in the strip corresponding to the two-dimensional geometrical shapes in the pattern, the strip remaining free of apertures in regions near each end comprising fusion zones; (e) fusing the ends of the strip to one another such that the fusion zones form a common fusion zone; and (f) forming apertures in the common fusion zone corresponding to the re-etch pattern. In a preferred embodiment, the two-dimensional pattern is an amorphous two-dimensional pattern of interlocking two-dimensional geometrical shapes. The strip of material may comprise a material selected from the group consisting of metal, plastic, fabric, rubber, and combinations thereof.
Patent TW-526294-B (TW)
Title: Multi-step potentiostatic/galvanostatic plating control
Inventor: CHUNG DEAN S
IPC: C25D7/12
Filed: 2000-05-17
Granted: 2003-04-01
Abstract: A method and apparatus are provided for the electroplating of a substrate such as a semiconductor wafer which provides a uniform electroplated surface and minimizes burn-through of a seed layer used on the substrate to initiate electroplating. The method and apparatus of the invention uses a specially defined multistep electroplating process wherein, in one aspect, a voltage below a predetermined threshold voltage is applied to the anode and cathode for a first time period followed by applying a current to the anode and cathode for a second time period the current producing a voltage below the predetermined threshold voltage. In another aspect of the invention, a current is applied to the anode and cathode substrate which current is preprogrammed to ramp up to a current value from a first current value which current produces a voltage below a predetermined threshold voltage. Electroplated articles including copper electroplated semiconductor wafers made using the apparatus and method of the invention are also provided.