Patent GB-1474235-A (GB)
Title: Data monitoring systems
IPC: G06F11/16
Filed: 1974-05-15
Abstract: 1474235 Computer monitoring WESTERN ELECTRIC CO Inc 15 May 1974 [18 May 1973] 21432/74 Heading G4A As a result of a particular preselected programme instruction being executed in a computer 10, a comparator 14 initiates monitoring of the hardware of software events occurring during the operation of the computer. A buffer 13 receives storage requests from different units in the computer 10 and processes them in priority order. The software word supplied on leads 12 includes the identity of the originating unit and the event which the word represents, e.g. routine entry/exit, and a data field which may be the contents of a particular register or storage location. Each software word is passed by buffer 13 to matcher logic 14 where its various fields are masked by and compared with initialization constants entered at 16. Equality of the event and unit identities with stored constants allows the result of comparison of the data field with a stored data value to be gated out. The mask and compare circuits may be paired and the greater than, G, less than, L, and equal, E, outputs of the data field comparators combined, B. to indicate if the data field lies between two stored constants. The outputs of matcher logic 14 control filter circuits 15, 18 to allow or prevent the occurrence of a particular monitoring function as a result of comparing the outputs L, E, G and B with initializing constants entered at 17, 19. Thus for each counter in the monitoring system a set of comparators is provided to determine which matcher output L, E, G and B for a selected event is to turn the counter on/off, to increment it, and to read it. Similarly for each output store section filters 15 determine which if the matcher outputs is to initiate or terminate storage functions in the store section. The monitor counters 20 have an associated set of input switches with a selection register which is initialized to determine which counter is to be associated with each hardware or software event to be monitored. The counters may operate in Gray code and be followed by conversion to natural binary code. The interval between selected events may be determined by gating clock pulses to a selected counter 20 between the occurrence of a start event and a stop event. The counters may also be paired so that while one counts events the other counts a timing signal. The store input circuits include registers to receive a counter word, a software word, a "time of day" word and a status word indicating the status parts of the monitor including data word parity error. The status word is also compared with initialized error conditions to initiate a status entry when a change in status occurs or when a preselected set of conditions exists. Requests for storage of data, count, time of day and status are dealt with in order of priority to supply the contents of the corresponding input register to the output store buffer 23, e.g. a magnetic core matrix. The buffer 23 may be operated in a linear, sequentially addressed mode or a cricular sequentially addressed mode in which, when full, overwriting of data occurs, or two sections of the buffer may be used simultaneously for the different modes. For this purpose two read and two write address counters are provided, and the capability exists for reading out data to different tape units 25 in blocks consecutively or concurrently according to the recording speed required.