Patent GB-1207747-A (GB)
Title: Signal correlator
IPC: G06G7/19
Filed: 1968-11-12
Abstract: 1,207,747. A/D converters. PRINCETON APPLIED RESEARCH CORP. 12 Nov., 1968 [13 Nov., 1967], No. 53690/68. Heading G4H. [Also in Divisions G1 and H4] In a system for correlating two input signals Ea, Eb in which the correlation functions for different delays between Ea and Eb are determined simultaneously the first signal Ea is fed to a signal converter 14 which produces an output waveform which takes either binary one or nought levels, the probability of the output being a one less the probability of it being a nought being proportional to the input. This output is passed to a shift register system 30 wherein it is stored and successively delayed as it passes through the stages of the register system. Each stage of the register provides an output binary pulse train, and these output trains are simultaneously multiplied with the second input signal Eb in a series of corresponding multipliers 32 to which Eb is applied in parallel. The multipliers produce either the positive or negative value of Eb, depending on whether the delayed output replica is in a one or nought state. The multiplier outputs are passed via an operate/stand by switch 38 to averaging and store circuits, each of which provides an output representing the average of the individual delayed output replica and the second input signal. These outputs are sequentially sampled by the switching system 42 operated by the readout clock 62 and scanning matrix 64, to provide a sequence of outputs which can be applied to the Y-plates of an oscilloscope to display a correlogram indicating the value of the correlation function between Ea and Eb for different delays.  The delays introduced along the register 30 may be equal at each stage, alternatively they may be made unequal by introducing further delays 72. The initial operation of the system may be delayed at 70. Signal converter 14.-This incorporates a quantizer and sampler operating such that the quantizer produces a pulse train whose symmetry depends on the value of the input, the output of the quantizer being sampled at regular intervals non-coherently by the sampler. Thus the difference between binary ones and binary zeros per unit time will depend on the input. In the quantizer (Fig. 3), the input Ea is applied via an emitter follower to one input of a comparator Q2, Q3 whose other input is provided by the rectified and smoothed output of the quantizer. The collector voltages for the two halves of the comparator are applied to the bases of a bi-stable multivibrator (Q4, Q5) to control the mark-space ratio of the output therefrom. The outputs from the two sides of the multivibrator are applied via a delay line to the sampler circuit (Fig. 4) in which the two outputs are applied via transistors (Q12, Q13) in common base configuration to the bases of emitter coupled transistors (Q14, Q15). Clock sample pulses are applied to the emitters. The resulting collector potentials which are in antiphase, are passed via emitter followers to the shift register 30. Shift register and multipliers.-Each shift register stage incorporates a bi-stable multivibrator having output transistors (Q20, Q21, Fig. 5), cross coupled by networks including emitter followers (Q22, Q23) to provide high switching speed. Steering gates including diodes (D12, D13) ensure that the multivibrator assumes the binary state of the preceding stage before a shift pulse is applied from a clock oscillator. Complementary outputs from the preceding stage are applied to these diodes. The complementary outputs from the multivibrator are applied to the gates of a pair of field effect transistors (Q24, Q25) to switch either the positive or negative value of the second input Eb to an integrator circuit 43 via the operate/stand by switch 38. The average value stored by the integrator corresponds to the instantaneous correlation function for the particular delay corresponding to the shift register stage.