Patent GB-811990-A (GB)
Title: Improvements in or relating to information transmitting circuits
Inventor: BROADHURST SIDNEY WALTER
IPC: H04Q11/04
Filed: 1954-04-15
Abstract: 811,990. Automatic exchange systems. POSTMASTER GENERAL. April 15, 1955 [April 15, 1954], No. 11240/54. Class 40 (4). Signals such as those indicating digits of telephone numbers are received from several sources and stored on time division basis as a combination of pulses, and means are provided for reducing the stored number in steps by changing the combinations stored and emitting a signal at each change of combination thereby reading out the stored digit. The pulses may be stored in the same time position in combinations of stores indicative of the digit, or in different combinations of time positions in the same store. In a first embodiment, Fig. 1, pulses are received from a control circuit, e.g. as described in Specification 804,691, in a position in a cycle of 99 such pulses each indicative of a source, e.g. a register, the pulses occurring on a combination of two out of five of the leads PL401.... PL405 said combination being indicative of the value of a digit to be transmitted. Not all pulses in this position are received, but only those coincident with one of a set of 14 " position pulses " PP1 ... PP14, the said position pulse indicating the digital position of the digit to be transmitted. Thus the first digit to be transmitted will be indicated bv the existence on two of leads PL401 ... PL405 of a register pulse train coincident with position pulse PP1 and so on. The positions of digits to be transmitted are fed to the circulating system TD607 over lead PL473 in the form of register pulse trains coincident with the appropriate position pulses. TD607 is sufficiently long to store 14 x 99 bits of information. On the outgoing side the dialled digits are fed to common lead PL602 in the form of register pulse trains modulated in gate PCG618 by dial impulses XP601. At the end of each impulse a device E601 produces a pulse of length at least equal to the time of a 14 x 99 bit delay line. This pulse fed to gate PCGG19 causes the feeding of at least one PP12 pulse for each register pulse train to the 14 x 99 bit delay line TD611. Only first PP12 pulse for each register passes gate PSG617 to lead PL603, said pulse occurring immediately after each dial impulse XP601. The arrangement contains four counting circuits one for counting down digits stored by the presence of a register pulse train in two out of five of the short (99 bits) delay lines TD601 ... TD605, and the other comprising delay lines TD608 ... 610 for counting dial pulses as a measure of the intertrain pause. The counting down of the digit ten in the first circuit will be considered as an example. This digit is represented by the combination TD601, TD602. The pulses to be counted are fed from gate PCG617 (a) to three "2" gates PCG610, PSG612, PSG613 so arranged that only one can operate at a time and then only if its associated delay line TD601 ... TD603 contains the appropriate pulse; and (b) to " 3 " gates PCG611, PCG612. PCG613 and PCG614, each of which is operated only if the fed-in pulse coincides with pulses in both adjacent delay lines; e.g. PCG611 must be fed by pulses from both TD601., TD602. The outputs of the " 2 " gates are overridden by the outputs of corresponding " 3 " gates. Thus with TD601, TD602 containing pulses, the first pulse applied to PCG611 deletes the pulse from TD602 and inserts it in TD603. The second pulse passes gate PCG610 to delete this pulse in TD601 and insert it in TD602. The third pulse passes gate PCG612 to delete the pulses in TD602, TD603 and insert the pulse in TD601, TD604. The fourth pulse passes through PCG610 to transfer the pulse from TD601 to TD602 and the fifth pulse passes PSG612 to transfer the pulse from TD602 to TD603. The sixth pulse then passes gate PCG613 to delete the pulse from TD603, TD604 and insert it in TD601, TD605. The seventh, eighth and ninth transfer the TD601 pulse to TD602, TD603, TD604 respectively in similar manner. The tenth pulse operating through gate PCG614 deletes the pulse from TD604, TD605 so that none of the delay lines now contain pulses. so that gate PCG618 is now closed to stop the transmission of further impulses. Furthermore the inhibition on gate PSG614 is now removed and the " end of dial impulse" pulses from PCG617 are now passed to the binary counting down mechanism including delay lines TD608 ... TD610 each of which at this moment is carrying the register pulse train. This mechanism times an intertrain pause equal to that of 7 dial impulses, i.e. 700 ms. The first pulse passes gate PCG620 to delete in gate PSG608 the pulse from TD608. The second pulse passes through gate PSG615 to delete in gate PSG609 the pulse from TD609 and to re-insert the pulse in TD608 via gate PSG608. The third pulse passes through gate PCG620 to delete the pulse from TD608. The fourth pulse passes gate PSG616 to delete the pulse from TD610 and reinsert it in TD608, TD609. The fifth, sixth and seventh pulses operate on TD608, TD609 as for the first, second and third pulses so that after the seventh pulse, the pulse is deleted from all three delay lines. The complete operation is thus as follows: lead PL134 is fed with a burst of register pulse trains for the register requiring to transmit the digits and this train is stored in the short (99 bit) delay line TD606 and long delay line TD607 contains the digital positions of digits to be transmitted. The register pulse train on lead PL134 is fed to delay line TD610 via gate PSG610 to register the digit 4 in this system. Gate PCG617 is thus opened to permit end of dial impulse " pulses to pass to the counting system TD608 ... TD610 which is then counted down to zero in 400 msecs. to provide a preparatory period. This arrangement also prevents the transmission of clipped dial impulses. When the pulse is absent from TD608 ... TD610 the inhibition on gate PSG606 is removed (from position. PP13 onwards, positions PP13 and PP14 not being used for digit storage). Thus the next register pulse coinciding with a PPI pulse is passed from the delay line TD607 to gates PCG601 ... PCG605 to admit the first digit to delay lines TD601 ... TD605. This pulse is also passed via, gate PCG609 to suppress gate PSG607 and so remove this pulse from TD607; and also via PSG608 ... PSG610 to store the digit 7 in the counting system TD608 ... TD610. The counting arrangement TD601 ... TD605 is then counted down and dial impulses transmitted as previously described. When this has occurred PCG618 is closed to terminate the impulse series, the inhibition on PSG614 is removed to cause TD608 ... TD610 to be counted down to provide the 700 msec. intertrain pause. Gate PSG606 is then opened to admit a PP2 pulse from TD607 and the second digit is received and retransmitted and so on. The pulse train in TD606 is removed by means not shown when the register is released. A second embodiment consists of an impulse regenerator common to a plurality of circuits and is identical with that described with reference to Fig. 3 of Specification 809,152.