Patent GB-1229091-A (GB)
IPC: G06F9/46
Filed: 1969-06-19
Abstract: 1,229,091. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 19 June, 1969 [5 July, 1968 (2)], No. 30978/69. Heading G4A. In data processing apparatus, concurrent entry by a plurality of active units into the same section of a common programme or data is prevented using a location in a store accessible to each of the units, the location containing a first or second bit configuration respectively indicating that the section is already in use by one of the units or is available for use, each unit comprising means for determining which configuration is present, and if it is the first, causing suspension of processing activity relative to the section in the unit performing the determination and if it is the second storing the first configuration in the location to lock out the other units from entering the section, there also being means for storing the second configuration in the location and for broadcasting a signal to at least one of the other units that the section is now available. A section of programme which must not be in process of execution by more than one unit (processor) at a time, e.g. a section of the supervisory programme allocating memory storage, starts with a TZW (test for zero and wait) instruction and ends with an RI (reset interlock) instruction. In a first embodiment, when a processor attempts to enter the section it executes the TZW instruction which addresses common main memory (or separate registers) to obtain the bit configuration which is tested to see if the section is already in use. If it is, a wait flip-flop in the processor is set and the processor holds its present state (with the TZW instruction still in the instruction register, &c.) until the wait flip-flop is reset (see below) when it resumes. If the section is not in use, the processor changes the bit configuration to indicate the section is in use, re-stores it, and continues executing the section. The RI instruction addresses the bit configuration, changes it to indicate the section is not in use, re-stores it, broadcasts a resume signal to all the processors and continues operation with the instructions after the section. The resume signal causes those processors in the wait state to reset their wait flip-flops and thus continue operation with a re-execution of the TZW instruction still in their instruction registers. A second embodiment differs in that when a processor has been in the wait state for a predetermined duration specified by a field in the TZW instruction (or from a register specified by the TZW instruction, or the duration may be fixed), the waiting, task is dumped on to a task queue and the processor proceeds with a ready task from the queue. In the above embodiments, if two or more processors attempt to execute a TZW instruction simultaneously, memory request resolution facilities permit them to gain access to the memory only one at a time so the first enters the section and locks out the others. A third embodiment differs from the first in that a processor, on broadcasting a resume signal, sends its "class" as well. Any processor in the wait state determines the highest priority resume signal it is receiving, according to a fixed priority order of the processors, and compares the class of the corresponding processor with its own class, the wait flip-flop being reset if equality is found. The class may be the address field in the TZW and RI instructions, this address modulo a quantity, or another quantity contained in these instructions or in a register or memory location addressed by them. A fourth embodiment differs from the first in that the bit configuration location contains one bit to indicate section available or in use, and a bit for each processor to indicate if it is waiting, the resume signal being sent to only the highest priority of these waiting processors according to a fixed priority order. Alternatively the processor waiting bits could be replaced by a code or address to indicate the processor to receive the resume signal. Execution of an RI instruction by a given processor when the preceding TZW instruction was executed by another processor could be prevented by storing the processor number in the bit configuration location on execution of a TZW instruction and comparing on it when an RI instruction is reached, or identification of a set of processors in registers may replace the processor number. The bit configuration (a single bit) could be held in the TZW or RI instructions themselves.