Patent GB-1120975-A (GB)
Title: Data communication system
IPC: H04J11/00
Filed: 1967-03-06
Abstract: 1,120,975. Pulse modulation systems; data transmission systems. INTERNATIONAL BUSINESS MACHINES CORP. 6, March 1967 [14 June, 1966], No. 10380/67. Headings H4L and H4P. To reduce the effects of noise in a data transmission system the input information digits are presented in parallel to a number of multipliers, one digit to each multiplier, for multiplication with the bits of successive words in a repeating sequence of quasi-random words generated by a shift register. For each successive word the multiplier outputs are added, the series of signals so obtained forming a composite signal for transmission. At the receiver the inverse operation takes place; noise affecting the composite signal has little effect on the receiver output. Transmitter, Fig. 1.-Serial 8-bit binary signals 1 are converted to parallel and stored on S 1 -S 8 . The serial signals are also integrated at 3 and passed to the transmitter output as the first part of the composite transmitted signal. A feed-back shift register SS 2 -SS 8 , started from a preset pattern, generates seven successive 7-bit quasi-random words, the parallel bits of which feed multipliers M 2 -M 8 . After each shift pulse applied to the register the outputs of S 1  and of M 2 -M 8  are added and the sum is transmitted. The composite signal thus consists of eight multilevel parts. Receiver, Fig. 2.-Feed-back shift register SS 2 -SS 8  generates a word sequence identical to that at the transmitter and applies the words to multipliers M 2 -M 8 . The first part of the received composite signal passes to all the integrators I 1 -I 8  via gate 14. The succeeding parts feed direct to I 1  and via the multipliers to I 2 -I 8 . The integrators feed threshold units D 1 -D 8 , the outputs of which correspond to the original input digits. The digits are then serialized. Synchronisation.-One or more of the input digits may be permanently set to a given value so that the corresponding receiver integrators will reach a maximum at the end of the transmission cycle, i.e. at the end of the composite signal. This peak signal is used to synchronize the timer 12. The polarity of the given value may be changed in a set sequence, the changes being in sync. with the changes in the register to avoid the possibility of locking on to spurious cross-correlation peaks. Alternatively, the outputs of the integrators are used: those outputs exceeding certain levels are selected and integrated, these levels corresponding to the auto-correlation peaks. General.-The input signals to the transmitter may be binary (polar or unipolar) or ternary or in differential code. They may be pulse amplitude modulated signals derived from a continuously variable source. A multiplex system is obtained if stores S 1 -S 8  are fed by a plurality of sources rather than from the serial-parallel converter. The level of the transmitted signal may be varied according to the number of 1 bits in the binary signal stored on S 1 -S 8  so that the energy per transmitted word is constant. The decision level of the threshold circuits at the receiver may be varied correspondingly by the output of that integrator I 1 -I 8  which corresponds to a store S 1 -S 8  permanently set to 1.