Patent GB-1186422-A (GB)
Title: Electronic Computer for the Series-Parallel Processing of Decimal Numbers
IPC: G06F7/38
Filed: 1967-03-22
Abstract: 1,186,422. Arithmetic circuits. ANKER. WERKE A.G. 22 March, 1967 [28 April, 1966], No. 13359/67. Heading G4A. An electronic computer for the serial-parallel processing of decimal numbers comprises ring- core decoding matrices feeding a ring-core adding matrix, each matrix being sub-divided into two sub-matrices, write conductors for each matrix passing through cores of both submatrices in two different directions. Two operands in 2.out-of-6-coded-decimal form are received serially by decimal digit, parallel by bit. One operand comes from an accounting machine or storage, the decimal digit being applied to a transfer decoder CE (Fig. 2) at 20a-20f, each line going through two sub-matrices 23, 24 of magnetic, cores as shown. One sub-matrix is inhibited (but excluding the cores A to E) depending on the state of a carry flip-flop 47, a core in the non- inhibited sub-matrix being switchedif both the lines threading it are pulsed. The input at 20a- 20f is thus incremented by one, or not, and decoded into a 1-out-of-n indication on sense lines such. as 36 feeding respective. output lines 39/A to 39/10. An output of ten 39/10 causes a pulse on the 0 line, 39/0, and the setting of the carry flip-flop 47 via transformer 41 and line 45. The other operand comes from an " accumulator " (AK) which is simply a magnetic core store for 30 six-bit decimal digits, one of the 30 digits being selected by a magnetic core selector matrix. (AS) driven by two ring counters (116, 117). The selected decimal digit is supplied to a "complementary" decoder (KE) generally similar to the " transfer" decoder of Fig. 2 except that which of the sub-matrices is inhibited depends on whether addition, or subtraction of the operands is required, the decoder accordingly decoding the decimal digit or its nines complement into 1 out of 10 form on the core sense lines. These lines are joined to the corresponding numerical output lines, 39/0 to 39/9, of the " transfer " decoder (Fig. 2), the junctions being connected to the inputs. 40/0 to 40/9 of the adder (F´g. 3). If the two decimal digits are unequal, two of the lines 40/0 to 40/9 will be energized and three of the cores of the matrix will have both. windings energized. However, the line 30 will receive a double-level pulse which will switch a core 81 thus inhibiting the cores of the leading diagonal of the matrix, i.e. two of the three cores mentioned will be inhibited. If the two decimal digits are equal, only one of the lines 40/0 to 40/9 will be energized, and that core which is passed through twice by the line will be switched. Thus in either case only one core of the matrix will switch, to produce a sum pulse on one of 18 sense lines 67/0 to; 67/18 (only two shown). These are combined to give a 1-out-of-10 indication of the sum decimal digit at 72/0 to 72/9, any carry being " detected " by a multiprimary, single-secondary transformer 73/10 to 73/18, 74 on a line 46 to set the carry flip-flop 47 of Fig: 2. The adder output at 72/0 to 72/9 is recoded to 2-out-of-6 form by a diode matrix (CW) and restored in. the accumulator position from which the corresponding digit of the second operand came. The circles shown are transistors. The accumulator can communicate with the accounting machine or storage from which the first operand came. It is mentioned that multiplication and division can be carried out by additions and subtractions respectively.