Patent GB-1418005-A (GB)
Title: Programmable logic controller
IPC: G05B19/045
Filed: 1972-11-30
Abstract: 1418005 Program control MATSUSHITA ELECTRIC INDUSTRIAL CO Ltd 30 Nov 1972 [30 Nov 1971 (2) 17 March 1972] 55439/72 Heading G4A [Also in Division G3] A programmable device arranged to control one or more devices in response to program instructions includes a program memory storing output instructions, in response to which a controlled action is performed, and input instructions, in response to which the state of an input is tested, belonging to a plurality of programs, an address memory storing one instruction address for each of the programs, and a pointer counter arranged to select one of the addresses in the address memory and to sequence the programs in a time shared manner. In a first embodiment, Fig. 4, address memory 3 is loaded with the addresses (in a read-only diode matrix program store 1) of the first instructions in each of three stored programs, one for each of three controlled stations containing a controlled device. The program instructions comprise 7 bits specifying one of the outputs of device 11 (connected to the controlled devices), a command bit specifying the required operation to be performed by the device connected to the selected output, 7 bits specifying an input to device 13, a test bit specifying the required state of that input, and two addresses in program store 1 specifying the next instruction for when the test fails and succeeds, in the former case the next instruction being the same test instruction. Pointer counter 4 is set into its first state to access the corresponding address from address memory 3 and, thus, the first instruction from program store 1 which is loaded in register 5. The output operation specified is executed and the input test performed. In response to the test result one of gates 14, 15 is enabled to load the appropriate next instruction address in address memory 3 in place of the first address therein, and pointer counter 4 is incremented and the procedure repeated for the next program. A second embodiment, Fig. 9 (not shown), is similar to the first except that the instructions are of ten bits including two operation or test bits and eight bits identifying an input or output. Following an input test instruction a tenbit address is stored specifying the next instruction address where the test failed, i.e. the same test instruction which is repeated. Operation is similar to that of the first embodiment, instructions for a program being accessed sequentially by incrementing the address read from the address memory in a program counter, the program counter being incremented twice following each successful test instruction. Where a test fails the program counter is incremented once to access the address of the next instruction to be performed, this address being loaded into the address memory in place of the address used initially to access the current program, and the pointer counter being incremented to access the next program. A third embodiment, Fig. 11 (not shown), is generally similar to the second except that each controlled station has two controlled devices, there being six programs, six addresses in address memory 3, and six states of program counter 4. Operation is as in the second embodiment except that the address in address memory 4 may be overwritten and pointer counter 4 incremented to access the next program in response to a test instruction irrespective of its result. The controlled stations may include an arm moved up and down and rotated under program control. The arms may be held in a given position for a period determined by a timer, the states of the timers being investigated by the test instructions. Unconditional program jumps may be performed by providing a dummy input whose state is fixed and a test instruction such that the test fails, the address at which the program continues being a jump address rather than the same test instruction.