Patent EP-0218414-A2 (EP)
Inventor: MASSE MICHEL STEPHANE
IPC: H02M7/5387
Filed: 1986-09-24
Abstract: A static inverter is disclosed which contains a circuit for synthesizing a periodic electrical waveform of a predetermined shape. The synthesized waveform appears at a capacitor which is periodically charged and discharged through several resistors. Some of the resistors are shorted out by this circuit at selected times during the charging and discharging cycles, so that the voltage appearing at the capacitor consists of a series of varying slopes; the slopes, corresponding to the RC time constants in the circuits, and the times at which the resistors are shorted out, determine the shape of the waveform. Control of the times at which the charging and discharging takes place, and at which the resistors are shorted out, may be accomplished by an oscillator circuit which provides a series of pulses of a fixed frequency to a counter, which in turn provides the required signals to the switches shorting out the resistor and to the switch which connects the RC circuit to either the charging or discharging voltage. Further disclosed is a circuit which controls the charging and discharging voltages, and thereby the output power of the static inverter, in response to a comparison of feedback signals proportional to the output current of the static inverter and to the output currents of parallel static inverters. Further disclosed is a temperature compensated oscillator circuit. consisting of a pair of NOR gates operating as logic inverters. with an RC network determining the frequency of oscillation. The temperature compensation of the oscillator is achieved by including a resistor in series with the power supply to the NOR gates which compensates for the temperature variation of the value of the capacitor, as the capacitor used has a positive temperature coefficient. Further disclosed is a circuit which boosts the DC voltage necessary for the portions of the static inverter which uses FETs as switches. This circuit consists of a comparator which compares a voltage proportional to the input DC voltage to a reference voltage. Upon the input DC voltqge falling below a certain level, the comparator will close a switch (consisting of another FET) which connects the tap at the primary of a center tap transformer to the input DC voltage. A voltage Will then be induced in the secondary of the center tap transformer, which has its tap connected to the input DC voltage, thereby boosting the voltage at the terminals of the secondary to a higher voltage. Furtber disclosed is a circuit which provides for "four-quadrant" operation of the static inverter by allowing the static inverter to absorb energy stored by a reactive load: s.uch absorption js necessary so that the output waveform is not disturbed by the reactive load. This circuit consists of FETs connected between each output terminal and a common node, with logic controlling the gate voltage of the FETs so that the FETs are conductive for a brief period of time when the static inverter is not sourcing power. and so that a "hard" turn-off voltage is briefly applied to the gates of the FETs as the static inverter begins to source power again.