Patent GB-1278636-A (GB)
Title: Clock synchronization techniques
IPC: G01S11/08
Filed: 1969-08-15
Abstract: 1278636 Radionavigation SIERRA RESEARCH CORP 15 Aug 1969 [20 Aug 1968] 40943/69 Heading H4D Relates to means for absolutely synchronizing the clock counter 43, 44, Figs. 1 and 3, of a known form of airborne co-operative radio collision avoidance system (CAS) 41 to a remote ground master clock 16 when the airborne station 40 includes a known form of distancemeasuring secondary pulse radar (so called standard DME) 46 operating in conjunction with a fixed ground station 10, e.g. a VOR/DME, TACAN or VORTAC station, which includes a DME transponder, said synchronising means also comprising a fixed interrogator 20 synchronized with said master clock 16 and located a known distance d from the ground station 10. As described the CAS time cycle comprises recurrent epochs of duration #T = 3 secs. each divided into 2000 time slots each of duration #t = 1500 Ás. The master clock 16 produces sync pulses A, Fig. 2, of recurrence period 2#T = 6 secs. corresponding to the start of every other epoch, e.g. the start of each odd epoch, and these sync pulses A are transmitted to the interrogator 20 through a phasing unit 18 which compensates for the known transmisson delay. The interrogator 20 derives from the received pulses A a train of coded interrogation sync pulse signals 32<SP>1</SP> (code 1), Fig. 2E, of recurrence period 8#t = 12,000 Ás, the pair of signals 32<SP>1</SP> at the end of each 2#T period being replaced by differently coded signals 34<SP>1</SP> (code 3) and 36<SP>1</SP> (code 2) and the signals 32<SP>1</SP>, 34<SP>1</SP>, 36<SP>1</SP> being time advanced in accordance with the distance d of the interrogator 20 from the station 10 as shown in Fig. 2E so that the corresponding sync reply signals 32<SP>11</SP>, 34<SP>11</SP>, 3611, Fig. 2F, transmitted by the DME transponder at station 10 are in absolute synchronism with the master clock 16. At the airborne station 40 the received delayed sync reply signals are compared in a time comparator 49 with corresponding local signals from the counter 44 which have been delayed in accordance with the variable distance R between the airborne station 40 and the ground station 10 as determined by the DME 46 so that if the clock counter 43, 44 is in absolute synchronism with the master clock 16 the two sets of signals applied to the comparator 49 will coincide exactly. Any synchronization error will result in a time displacement e(t) between the two sets of signals which is used to actuate a synchronizer 45 to control the counter 44 and clock 43 so as to automatically reduce the error e(t) to zero as described below with reference to Fig. 3, the pulses of any one pulse train being identified by the corresponding interpulse period, e.g. pulses referred to as 1500 Ás pulses are pulses with an interpulse period of 1500 Ás. As shown in Fig. 3 the received coded sync reply signals 3211, 3411, 3611 are selected and converted into corresponding single pulse signals by respective decoders 60, 76, 78. Clock pulses from the 5 MHz clock pulse oscillator 43 are applied via OR gates 72, 80 and a normally enabled gate 62 to a divide-by 7500 counter 50 to give 1500 Ás slot pulses (as in Fig. 2B) which are applied to a divide-by 8 counter 52 to give 12,000 Ás pulses each of which turns ON a bistable 53 to enable a gate 55 thereby applying clock pulses to a delay counter 54 which is preset by the digital range output from the DME 46 to read the complement of the range R so that when the counter 54 overflows the resultant output pulse is delayed in accordance with the range R. Each R-delayed 12,000 Ás output pulse from the delay counter 54 resets the bi-stable 53 and produces in a gate generator 56 a pair of early and late gate pulses (each of duration t(g)) which are applied to the time comparator 58 together with the output 12,000 Ás pulses from the decoder 60. The 12,000 Ás pulses from the counter 52 are also applied to a divide-by 8 counter 66 to give 96,000 Ás pulses each of which triggers a one-shot 68 whose output pulses are applied to normally inhibited gates 64, 70 and to a normally enabled gate 79. If the time error e(t) is greater than the comparator gate duration t(g) there is no output from the comparator 58 and each output pulse from the one-shot 68 is applied through the normally enabled gate 79 to the clock pulse OR gate 80 thereby adding an extra count which advances the output from the counter 52. This " strobing " operation continues until e(t) is less than t(g) when there will be an early or late output from the comparator 58 which inhibits the strobing gate 79. If the counter chain 50, 52, 54 is running late, the resultant late output from the comparator 58 enables the gate 70 to apply each output pulse from the one-shot 68 to the clock pulses OR gate 72 thereby advancing the output from the counter 52 and this process continues until e(t) is reduced to zero; conversely if the counter chain 50, 52, 54 is running early the resultant early output from the comparator 58 enables the gate 64 to apply each output pulse from the one-shot 68 to inhibit the clock pulse gate 62 thereby blocking one clock pulse and so retarding the output from the counter 52. The early-late output signals from the comparator 58 are also applied to control the frequency of the clock-oscillator 43. The 1500 Ás slot pulses from the counter 52 are also applied to a divide-by 4000 counter 74 to produce local odd-epoch start signals which reset the CAS slot counter 44 and are synchronized with the corresponding master clock signals A, Fig. 2, by applying the decoded code 2 and code 3 sync reply signals from the decoders 78 and 76 to reset the counter 74.