Patent GB-1132728-A (GB)
Title: Apparatus and method for fabricating an interconnected circuit
IPC: H01L27/00
Filed: 1966-11-15
Abstract: 1,132,728. Choosing positions on a substrate for circuit elements. INTERNATIONAL BUSINESS MACHINES CORP. 15 Nov., 1966 [1 Dec., 1965], No. 51120/66. Heading G4A. [Also in Division G3] Circuit elements are assigned to positions on a substrate to make up an interconnected circuit, by utilizing information of the required interconnections to determine the order in which the elements are to be assigned to positions, assigning the first element (to be assigned) to a selected position, and assigning each subsequent element to the best of a number of candidate positions for that element, the candidate positions having been selected in each case in accordance with their relation to positions which had already had an element assigned to them. An integrated circuit is created on a monolithic crystal wafer bearing individual circuit elements, by a wiring device which establishes interconnections between the elements by wrapping wires around selected pins or by moving the wafer relative to a light beam (for photoetching) or a depositing device. The wiring device is controlled by a wiring pattern determining system which is fed with circuit design and interconnection weighting data from punched cards or magnetic tape and with the output of a placement system. The placement system is fed with the circuit design and weighting data above, and with data from a wafer tester optionally via punched cards or magnetic tape. The data from the wafer tester comprises the size (maximum values of X and Y coordinates) and shape of the wafer and which positions on the wafer are not usable. The placement system decides which circuit elements are to be assigned to which positions on the wafer. As a modification, the output of the placement system may be printed out. Placement system.-A 3-dimensional matrix memory (W matrix) is loaded with the weights of the interconnections, the weight of an interconnection to carry a signal from the ith element to the jth element being stored at the intersection of the ith row and jth column. If an interconnection doesn't exist, the intersection stores zero. A core memory (MACM) has a word location for each position on the wafer and an indicator bit therein which is reset from 1 to 0 if the position is not usable. A W<SP>1</SP> list is set up by storing for each element in turn the sum of the weights of all interconnections between that element and other elements, the weights being obtained from the W matrix. Elements are now placed in a T list in the order in which they are to be assigned to positions on the wafer, as follows. The element with the highest entry in the W<SP>1</SP> list is stored as the first entry in the T list, and the elements connected to it are stored in a J list. Corresponding to each entry in the J list, an entry is established in a D list giving the sum of the weights of the interconnections between that element and those (so far only one) in the T list. Each of the remaining positions in the T list is filled in turn by looking for the maximum value in the D list. If this value is not zero and only one element has this maximum value, that element is picked for the T list. If more than one element has this non-zero maximum value in the D list, that one of these elements having the highest value in the W<SP>1</SP> list is picked for the T list. If two or more elements have this highest value in the W<SP>1</SP> list, one is picked arbitrarily. In any event, the J and D list entries for the picked element are set to zero. Then those elements interconnected with the picked element are identified by looking for non-zero weights in the W matrix, and stored in the J list if not already present, the D list also being updated. These operations are repeated until the maximum value in the D list is zero when the T list is complete. The first entry in the T list is now assigned to a fixed position (or one preselected by the operator) near the centre of the wafer, by placing the element's name in the appropriate word location in the core memory (MACM). If this position is unusable, the first usable position in a spiral path progressing outwards from the centre could be taken. The following sequence is now repeated, once to assign each of the remaining elements in the T list. The X and Y co-ordinates of usable positions, if any, on the wafer which are one position to the left, to the right, above or below the position last assigned an element are placed in a candidate position list provided they are not already in it, and the indicator bits in the core memory (MACM) for these positions are reset to 0. It is the indicator bits which are used to determine if a possible position is usable and not already in the candidate position list. If at this point there are no entries in the candidate position list, the criterion for inclusion in the list is broadened e.g. all usable unfilled positions may be placed in the list (if there are none, the wafer is rejected). Alternatively positions two positions away could be used, or diagonal positions, or a new position could be chosen for the first element in the T list along the spiral path mentioned. With at least one entry present in the candidate position list, the next element in the T list to be assigned is taken (by incrementing a T counter) and for each element already assigned to a wafer position the sum of the weights of the interconnections between the two elements, if non-zero (indicating there are interconnections), is stored in an F list, with the name of the already assigned element being placed in a corresponding position in a B list. The element to be assigned is now assigned to the best of the positions in the candidate position list, the best candidate being that which minimizes the cost of the choice, defined as: the sum over all elements in the B list (already assigned elements interconnected with the element to be assigned) of the product of the weight of the interconnection times the sum of the squares of the X and Y distances between the B list element position and the candidate position. During the computations to find the minimum cost choice, the minimum cost so far is retained as is the location of the best position so far (i.e. that associated with the minimum cost so far) and the sum over all elements in the B list of the difference between the X and Y distances between the B list element and the best so far candidate position. If a computed cost is equal to the minimum so far cost, the choice for which this difference is the smaller is retained as the best so far. With the element assigned to the best position, the position is removed from the candidate position list. The hardware includes two associative memories, each having a maskable argument register for the data to be matched against and a data register for data read-out from or to be written into the memory, the data register being fed from the memory via a first (read) mask and feeding the memory via a second (write) mask. The associative memories store the candidate position list and the other lists respectively.