Patent UA-47842-U (UA)
Title: Integrated circuit of semiconductor memory with built-in self-testing capabilities
Inventor: UTKINA TETIANA YURIIVNA
IPC: G11C7/00
Filed: 2009-09-07
Abstract: The integrated circuit of semiconductor memory with built-in self-testing capabilities comprises memory cell array provided for X, Y address decoders, the inputs being connected to communication switch 1 and communication switch 2 outputs correspondingly, reading amplifiers, the input/outputs being connected to the first selector input/outputs and the first data comparator inputs, the second selector input/outputs are connected to the first elements input/outputs of the input/output, the second input/outputs being connected to data integrated circuit outputs, the third element inputs of the input/output and the second reading amplifier outputs are connected to the first instruction memory, the inputs being connected to program counter outputs, the first input being connected to an integrated circuit output where a starting signal ST is fed, the second instruction memory outputs are connected to the first instruction sequence controller inputs, the third instruction memory outputs are connected to address inputs of an arithmetic logic unit (ALU), the fourth instruction memory are connected to the first data ALU inputs, the first outputs being connected to the third selector inputs and the second data ALU inputs are connected to the second data comparator unit, the first output being connected to an integrated circuit output where a test result T1 is generated, the first commutation switch 1 and commutation switch 2 outputs are connected to address buffer outputs, the inputs being address integrated circuit inputs, the second and third address ALU outputs are connected to the commutation switch 1 and commutation switch 2 inputs correspondingly, the first instruction sequence controller outputs are connected to the first program counter inputs and a group of instruction sequence controller outputs is used to operating mode control of integrated circuit components providing for self-testing performance, the integrated circuit controller inputs are connected to integrated circuit outputs where actuating signals CS, AS, WE, OE are fed and these controller outputs are used for signal generation defining operating modes of the integrated circuit. The integrated circuit comprises a Walsh function code shaper, a buffer element and an output for CLK synchronizing signal injection where the first Walsh function code shaper inputs are connected to the third ALU address, the second Walsh function code shaper inputs are connected to the fifth instruction memory outputs, the third Walsh function code shaper outputs are connected to the second instruction sequence controller outputs, the first Walsh function code shaper outputs are connected to the second data ALU inputs, the second Walsh function code shaper outputs are connected to the first instruction sequence controller inputs, the buffer element input is connected to a CS integrated circuit output and a buffer element output is connected to the second instruction sequence controller input, the third, the fourth and the fifths inputs being connected to an integrated circuit output where a CLK synchronizing signal is fed, the second data comparator unit output and the third ALU address correspondingly, the sixth instruction memory outputs are connected to the program counter inputs, the second outputs being connected to the fifth instruction sequence controller inputs.