Patent GB-1111795-A (GB)
Title: Frequency synthesizers
Inventor: TREADWELL CYRIL GORDON
IPC: H03B21/04
Filed: 1965-08-27
Abstract: 1,111,795. Frequency generating circuits. STANDARD TELEPHONES & CABLES Ltd. 27 Aug., 1965, No. 36918/65. Headings H3F and H3T. A digital frequency synthesizer comprises a multifrequency generator having a group of output frequencies to which is connected a plurality of circuits for selecting and dividing any one of the group of frequencies down to a value within a respective one of the orders of digits, and in addition means connected to each of the circuits to add algebraically the selected and divided signals to produce the synthesized output frequency. In an embodiment, the multifrequency generator 1, Fig. 1, generates the frequencies 10, 9 . . . 1 Mcs. and comprises a 10 Mcs. master crystal oscillator 2 which is connected via a shaping circuit 3 producing a pulse train of the same frequency to subtraction circuit 4. It is also connected to dividing circuits 8 and 12 in which the frequency is respectively divided x 2 and x 10 to produce 5 and 1 Mcs. respectively. Divider 12 is followed by sawtooth generator 13 the output of which forms the second input of subtraction circuit 4, whereby 9 Mcs. is obtained: further subtraction circuits 5, 6, 7 are coupled in sequence and to circuit 4, being each fed also with 1 Mcs. from generator 13 so as to obtain 8, 7, 6 Mcs. by successive subtraction. 4 Mes. and 3 Mcs. are obtained by division in circuits 9, 10 respectively of the 8 and 6 Mes. from subtracting circuits 5, 7 respectively, while further division in circuit 11 gives 2 Mcs. The selecting and dividing circuits comprise switches 21-24 each with fixed contacts 10 connected to circuits 4-10 and circuit 3 or earth; switch 21 is connected directly to addition circuit 41, while switches 22-24 are connected to addition circuits 42- 44 respectively via dividing circuits 32-35. The addition circuits are connected in sequence so that the summation frequency has a value defined by successive orders of digits as selected by switches 21-24: this output, on line 51, has a pulse form and a final sinusoidal output is obtained by means of a locked oscillator 52. Addition circuit (Fig. 2, not shown).-The two frequencies to be added are converted to sawtooth waveforms having equal amplitudes, which are superimposed (Fig. 3, not shown) and the combined waveform limited at a level equal to the peak amplitude of one constituent waveform. The resultant is then differentiated: the sawtooth wave of higher frequency is phasereversed and also differentiated and the two differentiated waveforms added, the resultant being a pulse train whose repetition rate is the desired summation frequency. Subtraction circuit (Fig. 4, not shown).-The two frequencies are converted to sawtooth waves of the same amplitude and are superimposed (Fig. 5, not shown). The combined waveform is limited at a level equal to the peak amplitude of one constituent waveform and then differentiated: the resultant waveform is applied to a rectifier, the output of which comprises a pulse train whose repetition rate is the desired difference frequency. Frequency generator of extended range (Fig. 6, not shown).-The range of the generator may be extended upward in frequency by feeding the output from the addition circuits to a seriesconnected chain of further addition circuits, each of which in succession adds 10 Mcs. derived from shaping circuit 3: a switch is provided whereby the final output may be derived from the output of any of the further addition circuits or the input thereto. In this embodiment switched filters are used instead of a locked oscillator, in deriving a sinusoidal output. Stepped waveform generator.-At low frequencies very good linearity of the sawtooth generators is called for, but this may be avoided by using stepped waveforms (Fig. 7, not shown). A stepping signal comprising 10 Mcs. square waves is applied to the base of transistor VT2, Fig. 8, driving it to saturation on each positive swing, so that its emitter potential then rises nearly to the collector potential; i.e. the emitter potential of transistor VT1. The positive pulses at the emitter of transistor VT2 are fed via an attenuator, which controls the amplitude and hence the number of steps, blocking condenser C2 and D.C. restoring diode MR1 to the base of emitter follower VT3. This has a low value emitter resistance R3 and feeds a cup and bucket circuit comprising capacitors C c , C B : a further emitter follower VT4 has its emitter back-coupled via diode MR4 to the output of capacitor C c  so as to clamp the potential of this point for the duration of each step. Stepwise charging of capacitor C B  continues until the potential across it equals that on the " low H.T. " line, whereupon diode MR5 becomes conductive, triggering blocking oscillator VT5 which thereupon discharges capacitor C B . An inverse charge is prevented from building up on this capacitor by means of clamping diode MR2. The whole cycle then repeats. The timing of the discharge of capacitor C B  is controlled by an accurately timed pulse from one of the dividers in the main circuit, which, with the stepped output waveform is fed into an amplitude comparator: the output of this is applied to the base of transistor VT2 and so varies the emitter potential, which is also the collector potential of stepping transistor VT2 as to adjust the amplitude of the steps so that their sum is the corerct voltage.