Patent GB-1170469-A (GB)
Title: Improvements relating to Impedance Network Hybrid Computers
Inventor: MALAVARD LUCIEN C
IPC: G06G7/46
Filed: 1967-11-17
Abstract: 1,170,469. Impedance network hybrid computer. CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE. 17 Nov., 1967 [18 Nov., 1966], No. 52376/67. Headings G4A and G4G. Theory.-In a resistance network of arms R joining peripheral nodes at potentials V 1 , V 2 , V 3 , V 4  and a control node at potential V 0  receiving current I 0 . 1. (V 1  - V 0 ) + (V 2  - V 0 ) + (V 3  - V 0 ) + (V 4  - V 0 ) = -RI 0  for each nodal point, and for a physical problem in two dimensions represented by a regular network of lines and columns defined by Poisson's equation where #, F are functions of variables x and y; 2. (# 1  - # 0 ) + (# 2  - # 0 ) + (# 3  - # 0 ) + (# 4  - # 0 ) = - α<SP>2</SP>F 0  where # 0 , # 1 , # 2 , # 3 , # 4  represent the values of # at nodes M 0 , M 1 , M 2 , M 3 , M 4  of the network; and F 0  is the value of F at M 0 .  α is the nodal displacement from M 0 , so that the problem is soluble by an electrical impedance network with nodal potential representing #, nodal injection currents representing F, and the impedances representing the physical displacement between nodal points, while the peripheral energization represents the boundary conditions of #. Structure.-Analogue values of injection currents are digitized to binary digital values, and ternary injectors are controlled during successive cycles to inject each node with positive or negative unit currents if the digit of a given binary weight of the current binary code value for the node is unity, and respectively positive or negative polarity or zero current if the digit of the binary weight is zero; the injection cycles being associated with successive binary weights; while apparatus is provided for scanning the nodes between successive injection cycles to derive analogue component values of the nodal potentials and forming therefrom component binary coded values which are respectively totalized in accumulator means pertaining to the several nodes. An impedance network 1 of sixty impedances, e.g. 101 with thirty-six nodes designated 10 11  to 10 16 ; 10 21  to 20 26  . . . 10 61  to 10 66  is nodally associated with an array of thirty-six ternary injectors designated 20 11  to 20 16 ; 20 21  to 20 26  . . . 20 61  to 20 66  each having supply, sign, and code inputs and an injection output 20 pq  connected to corresponding node 10 pq . Operation.-Analogue data input from board 4 is transferred in A/D converter 5 selectively connected to thirty-six registers 6 1  to 6 36 , each comprising a sign stage S and twelve binary code stages 0 to 11; each digitized data item being switched to the appropriate register, which is filled with the binary values of the currents to be nodally injected and their signs, and are commutated to the injector array 2 by unit 7. Sign stages S of the registers are gated at 10 s,1  to 70 s,36  to the sign terminals of injectors 20 11  to 20 66  and the stages of given binary weight, e.g. 11 and 0 are gated to the code terminals of the injectors at 70 11,1  to 70 11,36  and 70 0,1  to 70 0,36  respectively. These gates are successively -controlled by timebase 10, so that the injectors are supplied simultaneously with the binary sign digits and successively with the binary digits stored in stages 11 to 0, and corresponding analogue potentials appear at the respective nodes. These are gated from the several nodes in sequence to A/D converter 5 over gates 80 1  to 80 36  of commutator 8 operated by timebase 10 to scan thirty-six nodal positions between successive conditions of gating commutator 7. The A/D converter output is gated at 81 1  to 81 36  to thirty-six storage registers 9 1  to 9 36  retaining in binary form the nodal potentials of a complete scan following one injection, and are selectively connected to an accumulator 12 comprising two input registers 121, 122 and adder 125 and an output register 123 selectively connected to the thirty-six storage registers, with a register shift control circuit 124 effecting a one-position binary shift of the translation of each nodal analogue potential with respect to the preceding; equivalent to division by two of the corresponding analogue potential. Access gates (not shown) are provided for the storage registers connected to the accumulator input registers, and for the accumulator output register connected to the storage registers, and a given storage register content is transferable into the first accumulator input register 121, whose content is transferred on the next scan into the second accumulator input register 122; the total contents being transferred from adder 25 into output registers 123 and into the appropriate storage register, which contains at any instant the accumulated total of the successive potential components of the node corresponding to the register. After twelve scans, the output registers 9 1  to 9 36  contain the values of # at the respective nodes of the network. Initially, input registers 6 1  to 6 36  are charged with approximate injection values, for first iteration, and thereafter the contents of input registers 9 1  to 9 36  are applied to a digital computer 13 determining F as a function of # for the several nodes, which values are introduced to registers 6 1  to 6 36  for further iteration, repeated until the Poisson equation is resolved. Modifications.-An application is described to the further Poisson equation in which The commutator 8 may comprise (Fig. 2, not shown) a matrix of thirty-six relays, one per node, and the impedance network is divided into e.g. four domains in each of which corresponding sides of the relay windings are connected together to one contact of a first selector switch, while the remaining windings are connected by six corresponding vertical bus-bars to the contacts of a second selector switch. The relay contacts are connected between respective nodes and six corresponding horizontal bus-bars connected to the contacts of a third selector switch. The first switch is cycled by a stepping motor and its arm is retained to the A/D converter 5 (Fig. 1) while after a cycle is completed the stepping motor of the first switch is energized to sequentially excite the columns of relays of the first domain, after which the stepping motor of the third switch is energized and the columns of relays of the second domain are sequentially excited, and so on, to explore the nodes of all four domains in twelve cycles of the first switch. An injector (Fig. 3, not shown) comprises two polarized locking relays for sign and for code; the fixed contacts of the first being connected to opposite poles of a centre grounded D.C. source. The fixed contacts of the second are respectively connected to the moving contact of the first, and left unconnected, while the moving contact of the second relay is connected to a node over a high value resistance, and the relay energization terminals are connected to the sign and code sources. The apparatus may be applied to a threedimensional network for resolution of a Poisson equation ## = - F in which #, F are functions of the spatial variables x, y, z.