baber/WOPTO huggingface dataset:
Patent JP-S5758285-A (JP)
Title: Bubble magnetic domain generator
Inventor: OOTAKE ITARU
IPC: G11C11/14
Filed: 1980-09-22
Abstract: PURPOSE:To prevent occurrences of excess bubbles so that operations may be made under a stable condition, by making the conductor pattern in a double structure which is composed of a loop which generate bubbles at the inner side and another loop which repels bubbles at the outer side. CONSTITUTION:A conductor pattern is made in a double structure, and bubbles are generated in a bubble generating section (a) at a conductor gap G1 and, at the same time, its circumference is surrounded by a conductor gap G2, which repels bubbles. Since the magnetic pole which attracts bubbles unevenly exists in the head part of pickax of a permalloy pattern 20, deformations of stripe-shaped magnetic domains due to movements of the magnetic pole of the permalloy pattern 20 are restrained and a plural number of bubbles are not generated, and thus, the generator operates stably even at a high temperature side.
Patent JP-H05326446-A (JP)
Title: Manufacture of semiconductor device
Inventor: KAWASAKI SATOKO
IPC: H01L21/288
Filed: 1992-05-25
Abstract: PURPOSE:To obtain a good interfacial electric characteristic by including a process wherein a metal layer is formed while a natural oxide film on the surface of a silicon substrate inside a contact hole is eliminated, by protecting the surface of the silicon substrate until wiring material is deposited, and by reducing a contact resistance. CONSTITUTION:A wafer which has a part of the surface of a silicon substrate 1 exposed in a contact hole 5 which is formed after deposition of an interlayer insulating film 2 is treated with a dilute hydrofluoric acid solution including Cu which has a smaller ionization tendency than Si to eliminate a natural oxide film 6 on the surface of the silicon substrate 1. At the same time, the surface of the silicon substrate is selectively coated with a Cu layer 3a. During this treatment, the Cu layer 3b might be attached even to the interlayer insulating film 2. Therefore, after this treatment, the wafer is washed with a dilute hydrofluoric acid solution including no metal to selectively remove the Cu layer 3b attached to the interlayer insulating film 2. After that, wiring material 4 is deposited.
Patent JP-S5357843-A (JP)
Title: Simultaneous exposure and charging device
Inventor: NISHIKAWA MASAHARU
IPC: G03G15/02
Filed: 1976-11-05
Abstract: PURPOSE: To prevent the flowingof a corona ion current into the light source in the copier of an electrostatic type by making a recording paper to an exposure via an insulating light transmitting material provided at the corona shield. 
     COPYRIGHT: (C)1978,JPO&Japio
Patent JP-H10321921-A (JP)
Title: Thermoelectric conversion module and its manufacture
Inventor: IMANISHI YUICHIRO
IPC: H01L35/14
Filed: 1997-05-22
Abstract: PROBLEM TO BE SOLVED: To provide a thermoelectric conversion module and its manufacturing method, wherein the loss of power output due to heat dissipation from the part between semiconductor elements and convection of an air layer and the deterioration of power output due to the oxidation and scattering of semiconductor components are prevented, high efficiency of power generation can be obtained, and a high-temperature side surface and a low-temperature side surface can be constituted in arbitrary shapes proper in height precision. SOLUTION: A module core 5 is formed by alternately arranging P-type semiconductor elements 1 and N-type semiconductor elements 2, which are inserted in through-holes formed in an insulating honeycomb structure body 3, via-insulating filler 4 composed of an alkali metal silicate based inorganic adhesive agent or sol gel glass. The end surfaces of the module core 5 are polished. The adjacent P-type and N-type semiconductor elements are subjected to cascade connection via electrodes 7. On one surface and on the other surface of the honeycomb structure body.
Patent JP-S62290326-A (JP)
Inventor: MORINAGA HIDEKI
IPC: H02H9/02
Filed: 1986-06-06
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H10324631-A (JP)
Title: Immunoglobulin e antibody formation inhibitor
Inventor: SEKI NOBUO
IPC: C07D513/06
Filed: 1997-05-22
Abstract: PROBLEM TO BE SOLVED: To obtain the subject inhibitor that has an inhibitory action to inhibit the formation of IgE antibody produced against extraneous antigens by using a specific compound as an active ingredient. SOLUTION: This inhibitor contains, as an active ingredient, a compound represented by formula I [R<1> is H, a lower alkyl, a lower alkoxy; R<2> is hydroxy, a halogen; R<3> is H, an organic group; Z is O, formula II (n is 0, 1, 2)] or its pharmaceutically acceptable salt. This compound can be orally or parenterally administered in a dose of 3.2-32 mg/kg and gives a composition that is effective for treatment and prevention of the inflammation and pains in joints and muscles, collagen diseases and a variety of immunological disease in human and animals.
Patent JP-S5656659-A (JP)
Title: Semiconductor device
Inventor: HARADA NOZOMI
IPC: H01L23/29
Filed: 1979-10-16
Abstract: PURPOSE:To increase the reliability of the device by a method wherein a semiconductor chip is fixed in a package by using a bonding agent and later all the exposed surfaces of the package, chip and a bonding wire are coated with a film of Si3N4 or SiO2. CONSTITUTION:The semiconductor chip 1 is fixed to the bottom surface of a stepped concavity provided in the package 2 by using the bonding agent 4 and an electrode formed on the chip are bonded to a lead provided on the step part of the concavity through wires 5-1-5-n. Next, the device thus constituted is mounted on substrates 9-1 and 9-2 with a window in the central part thereof, with the open end of the package 2 being directed downward, and the exposed surfaces of the package 2 and the chip 1 are heated to the temperature of 200-350 deg.C by using an infrared heater 10. After that, by utilizing the excited reaction of plasma, the film of Si3N4 or SiO2 is applied to cover all the exposed surfaces of the package 2, the chip 1 and the bonding wires 5-1-5-n. Then the package 2 is separated from the substrates 9-1 and 9-2 and the open end of the package 2 is covered with a seal plate 3.
Patent JP-H06322224-A (JP)
Title: Resin composition
Inventor: WATANABE AKIHIRO
IPC: C08L69/00
Filed: 1993-05-11
Abstract: PURPOSE:To obtain a resin composition improved in impact resistance and flow by mixing an aromatic polycarbonate resin with a rubber-reinforced styrene resin and a specified copolymer. CONSTITUTION:The composition is prepared by mixing 30-80wt.% aromatic polycarbonate resin having a viscosity-average molecular weight of 10000-100000 with 5-69wt.% rubber-reinforced styrene resin, and 1-15wt.% copolymer comprising 20-90wt.% structural units of formula I (wherein R1 is H or methyl; and R2 is H or 1-5C alkyl), 10-80wt.% structural units of formula II (wherein R3 is 1-20C alkyl, cycloalkyl or phenyl) and 0-50wt.% structural units of formula III (wherein R4 is R3) and having a reduced viscosity of 0.1-2.0dl/g (as measured in chloroform in a concentration of 0.5g/dl at 25 deg.C).
Patent JP-S5466031-A (JP)
Title: Code input device
Inventor: SATOU TAKESHI
IPC: G06F17/22
Filed: 1977-11-07
Abstract: PURPOSE: To eliminate the need of code conversion, and to improve the operation of an operator by reading out code information added to characters on a character code board.  
     CONSTITUTION: With switch 4 1  of indication pen 4 ON, monostable multivibrator 10 is triggered to allow circuit 11 to generate a driving signal for emitting light from luminous element 4 2 , and code information B equivalent to the selected element on character code board 1 is projected upon photoelectric converter 3 via fly-eye lens 2. Generator 13, on the other hand, supplies clock pulses to converter 3 in sequence by the output of monostable multivibrator 10, so that information B will be outputted by an electric signal and stored in memory 14 in sequence through the control of circuit 12. Therefore, Chinese-character codes equivalent to indicated elements are ctored in memory 14. 
     COPYRIGHT: (C)1979,JPO&Japio
Patent JP-H10313870-A (JP)
Title: New cell b surface protein and dna encoding the same
Inventor: MIYAKE KENSUKE
IPC: C07H21/04
Filed: 1997-05-22
Abstract: PROBLEM TO BE SOLVED: To obtain the subject new DNA encoding a protein having a specific amino acid sequence and related to the proliferation or stimulation of B cells or the apoptosis suppression or induction of the B cells, and useful for treating or diagnosing autoimmune diseases, allergic diseases, etc. SOLUTION: This DNA encodes a protein having an amino acid sequence of the formula, or the amino acid sequence of the formula in which one or several amino acids are substituted, deleted, inserted or added and which has properties related to the proliferation or stimulation of B cell or the apoptosis suppression or induction of the B cell, or the DNA encodes at least a portion of the protein. The DNA is utilized for producing medicines for treating or diagnosing diseases related to the antibody production of B cells, autoimmune diseases, allergic diseases, asthma, atopic dermatosis, etc. The DNA is obtained by separating mRNA from the lymphoma cells of human B cells, forming a cDNA library from the mRNA, and subsequently selecting a cDNA clone.
Patent JP-S5256798-A (JP)
Title: Sprinkler head
Inventor: YOSHIMURA HIROYUKI
IPC: A62C37/21
Filed: 1975-10-31
Abstract: PURPOSE: To provide a sprinkler head characterized in that its reuse is possible and water supply stops only after complete extinction of fire. 
     COPYRIGHT: (C)1977,JPO&Japio
Patent JP-S5357388-A (JP)
Title: Nuclear reactor
Inventor: SHIRAKAWA TOSHIHISA
IPC: G21C1/04
Filed: 1976-11-05
Abstract: PURPOSE:To minimize the output peaking factor by distributing the fission material to make the infinite multiplication factor of the central portion smaller than the infinite multiplication factor of the edge portion by dividing the reactor core of the nuclear reactor into the central zone and the edge zone.
Patent JP-S5922031-A (JP)
Title: Liquid crystal display device
Inventor: KANZAKI SHIYUUICHI
IPC: G02F1/1335
Filed: 1982-07-28
Abstract: PURPOSE:To display a hue having a high grade in a liquid crystal display device of a twisted nematic field effect type (TN-FEM type) by using a polarizer and an analyzer having high transmittances on the short wavelength side and disposing both at a specific angle of intersection. CONSTITUTION:A liquid crystal layer 5 having a twisted nematic structure is inserted in the spacing (a symbol 6 is a spacer) between two sheets of glass substrates 2, 2' provided with transparent electrodes 3 and insulation films 4 for orienting liquid crystals on the inside surface, and a polarizer 1 and an analyzer 7 are disposed respectively on the outside of the substrates 2, 2', thereby forming a liquid crystal display device of a TN-FEM type. The polarizer and analyzer having the max. transmittance at 400-500nm wavelength are used in the above-mentioned device; furthermore, the polarizer and analyzer are so disposed that the angle between the axis of polarization of the polarizer 1 and the angle of polarization of the analyzer 7 attains (i) 90-110 deg. when the product of the refractive anisotropy (DELTAn) of the liquid crystal and the thickness (d) of the liquid crystal layer is around 0.5mum, and (ii) 94-120 deg. when around 1mum.
Patent JP-S6028599-A (JP)
Inventor: TAKAHASHI KENICHI
IPC: D21H17/28
Filed: 1983-07-22
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H04358230-A (JP)
Title: Method for confirming operation between cpus
Inventor: TANIMOTO TOMOAKI
IPC: G06F11/16
Filed: 1991-06-04
Abstract: PURPOSE:To secure the operations of two CPUs to exchange data through a dual port RAM. CONSTITUTION:The specified address of the dual port RAM is respectively allocated to the respective CPU, the respective CPU change the data at the respective specified addresses according to an initial routine, and it is investigated whether the data at the specified address of the counter CPU are changed or not. Until this data change is detected, the respective CPU repeat the similar operations, when the change is detected, the operation of the counter CPU is judged normal, and the following normal operation is started.
Patent JP-H11318186-A (JP)
Title: Equipment for detecting jamming in rocking rack of threshing and sorting machine
Inventor: MIZUMOTO TAKESHI
IPC: A01F12/44
Filed: 1998-05-15
Abstract: PROBLEM TO BE SOLVED: To early and surely find the clogging of threshed crop on the rocking shelves. SOLUTION: A contact sensor 37 for the detection of clogging is provided in the casing in the neighborhood of discharge part of a transverse fan 34. As straw refuse clogs the fan 34, the straw refuse contacts with the sensor 37, which leads to the generation of electromotive force to make the detection of clogging of the fan 34 possible. The clogging of the fan 34 causes the holdup of threshed crops on a rocking shelf 9, resulting in the clogging of the shelf itself.
Patent JP-S5833516-A (JP)
Title: Vehicular air conditioning equipment
Inventor: MITSUI MASATOSHI
IPC: B60H1/32
Filed: 1981-08-25
Abstract: PURPOSE:To improve the comfortability and reduce th power consumption of the equipment by a method wherein the required blowoff air temperature of an  evaporator is calculated on the outside temperature, insolation rate and compartment temperature and a compressor is controlled to be put into operation and out of operation so as to bring the actual blowoff air temperature to coincide with the calculated blowoff air temperature. CONSTITUTION:The compartment temperature 10, the insolation rate 11, the outside temperature 12 and the blowoff air temperature 13 of the evaporator 8 are inputted to a controller 16 respectively. The controller 16 calculates the blowoff air temperature of the evaporator 8 necessary for maintaining the set compartment temperature on the compartment temperature 10, the insolation rate 11 and the outside temperature 12. The calculated result is compared with the detected blowoff air temperature 13 of the evaporator 8 in order to control the ON-OFF action of the compressor 2 so as to make the detected temperature equal to the calculated value. Owing to the method as described above, the maintenance of agreeable compartment temperature and as well as the reduction of power consumption can be resulted.
Patent JP-H0428262-A (JP)
Title: Bimos semiconductor integrated circuit
Inventor: HANIBUCHI TOSHIAKI
IPC: H01L21/331
Filed: 1990-05-23
Abstract: PURPOSE:To enhance a BiMOS semiconductor integrated circuit in switching speed by a method wherein a P channel MOS transistor is turned ON when an N channel MOS transistor is turned ON, and the potential of the output terminal is transmitted to the base of an NPN bipolar transistor. CONSTITUTION:A PMOS 6 is provided in parallel with an NMOS 2, and a signal of an inverted gate input of the NMOS 2 is inputted into the gate of the PMOS 6. Therefore, when an input voltage changes from L to H, H of an output terminal 4 is transmitted to the base of a transistor (TR) Q2 through the intermediary of the PMOS 6 as it is, so that the TR Q2 is intensely turned ON and a large amount of charge is extracted from a terminal 4. In result, while the TR Q2 is kept intensely turned ON, an output voltage V4 drops more sharply and a switching speed that the voltage V4 is made to change from H to L is accelerated. The PMOS 6 is provided, whereby a high voltage can be applied to the base of the TR Q2, it is not necessary that the NMOS 2 is formed large in size, and a chip can be prevented from increasing in area.
Patent JP-H01302394-A (JP)
Title: Action condition display circuit for computer
Inventor: KONDO TOSHIHARU
IPC: G08B5/36
Filed: 1988-05-31
Abstract: PURPOSE:To correctly display the fact that a computer is normally operated by providing an exclusive-use routine to blink-display a light-emitting element and blinking the light-emitting element by means of the execution of the routine at the time of the normal action of the computer. CONSTITUTION:The Q terminal of an I/O port 2 is connected to the input side of an inverter 3, and the output side is connected through a resistor 4 and a light-emitting diode 5 to a power terminal 6 to which a positive direct current voltage +B is supplied. In such a case, when a signal at a high level '1' is outputted from a CPU 1, the signal at the high level '1' is outputted to the Q terminal of the I/O port 2, the signal at a low level '0' is outputted to the output side of the inverter 3, thereby, a current is made to flow, and the light- emitting diode 5 is lighted up. To the contrary, when the signal at the low level '0' is outputted from the CPU 1, the light-emitting diode 5 is not lighted up. Thus, even when a software is run away and the driving circuit of the light-emitting element is troubled itself, the fact that the computer is normally operated can be correctly displayed without executing a misdisplay.
Patent JP-H0574087-A (JP)
Title: Floating type magnetic head
Inventor: KAZAMA TOSHIO
IPC: G11B21/21
Filed: 1991-06-04
Abstract: PURPOSE:To maintain a stable floating condition even when a big acceleration is apllied, to improve a stability especially at a starting or a stopping time without causing a contact between a slider and a magnetic recording medium and further to improve a followup ability for the surface vibration of the magnetic recording medium and a projection, etc., by dust and texture at the floating type magnetic head where the centroid of the slider and the position of a pivot are coincided. CONSTITUTION:A recessed part is formed on the flexure attaching surface of the slider, the flexure is attached to the bottom surface of the recessed part and thus, the centroid of the slider and the position of the poivot are made coincident.
Patent JP-H01300930-A (JP)
Title: Tonometer
Inventor: KOBAYAKAWA YOSHI
IPC: A61B3/16
Filed: 1988-05-31
Abstract: PURPOSE:To obtain a highly accurate measured value, by a method wherein an index light source and a light receiving part are arranged so that both of them become conjugated relation through corneal reflex when the cornea is deformed to a predetermined curvature. CONSTITUTION:An optical system for optically detecting the deformation of the cornea Ec is constituted of an index light source 7 for illuminating the cornea Ec and a light detection part 4 consisting of two or more photodetectors arranged at the positions becoming the conjugated relation to the index light source 7 through corneal reflex light when the cornea Ec is deformed to a predetermined curvature. When the cornea Ec is not deformed, the corneal reflex light expands to two or more photodetectors of the light detection part 4 and, when the cornea Ec is deformed to a predetermined curvature by an air stream, the corneal reflex light is condensed only to the central photodetector of the light detection part.
Patent JP-H10307501-A (JP)
Title: Fixing device
Inventor: HIRAI KAZUMASA
IPC: G03G15/20
Filed: 1997-05-23
Abstract: PROBLEM TO BE SOLVED: To provide a fixing device which can prevent wrinkling on transfer paper, supplies a sufficient amount of heating value to toner, and prevent the transfer paper from being wound around a fixing belt immediately after passing through a fixing nip part. SOLUTION: This fixing device is provided with a fixing roller 2, a heating roller 1, an endless fixing belt 3, a pressurizing roller 4, and a heater 5 for heating the fixing belt, whereby the pressurizing roller 4 does not apply some pressure to the fixing roller 2, but the fixing belt 3 to form a first fixing process part, the pressurizing roller 4 applies some pressure to the fixing roller 2 through the fixing belt 3 to a second fixing process part, and the fixing roller 2 involves a foaming body layer.
Patent JP-H11327114-A (JP)
Title: Driving mechanism for photosensitive material transport device in photographic processing machine
Inventor: UEDA TETSUYA
IPC: G03D13/00
Filed: 1998-05-15
Abstract: PROBLEM TO BE SOLVED: To provide a driving mechanism for a photosensitive material transport device capable of driving a drive part on the side of a loop-forming part, and hence carrying a photosensitive material into the loop-forming part and/or carrying the photosensitive material out of the loop-forming part surely by means of a driving source of the drive part of a transport part in a development processing unit. SOLUTION: By linking a first drive part 5 for driving a transport device for transporting a photosensitive material in a development processing part with a second drive part 6 for driving a transport device for carrying the photosensitive material into the loop-forming part, the driving source of the first drive part 5 is configured for enabling driving the second drive part 6 through the first drive part 5. A power actuator 7 for interrupting the transmission of power to the transport device in the loop-forming part is provided in the second drive part 6.
Patent JP-H05328623-A (JP)
Title: Overdischarge protecting circuit for battery
Inventor: AMAYA HIDETOSHI
IPC: H02H7/18
Filed: 1992-05-26
Abstract: PURPOSE:To use battery capacity effectively regardless of discharge current value. CONSTITUTION:A discharge current detecting circuit 5 detects discharge current supplied from a battery 1 to a load. An overdischarge protecting circuit 3 changes protection voltage so that the protection voltage may be low when this discharge current is large, and that the protection voltage may be high when the discharge current is small. And the overdischarge protecting circuit 3 opens a switch 2 and interrupts the discharge current from the battery 1 to the load, if the voltage of the battery 1 detected by the overdischarge protecting circuit 3 lowers up to the protection voltage.
Patent JP-H07142990-A (JP)
Title: Level conversion circuit
Inventor: DANIERU SARAERUTSU
IPC: H03K19/0185
Filed: 1994-06-15
Abstract: PURPOSE: To provide the level conversion circuit in which a drop of a voltage fed to transistors(TRs) of the circuit is set to an absolute value limited to a maximum input voltage without the need for a complementary input signal. CONSTITUTION: A digital input signal changing between 1st and 2nd voltages is converted into a digital output signal changing between a 1st level and a 3rd voltage level, the series connection of a 1st TR N2 and a 2nd TR N1 is included between terminals VDD2, VSS of a DC power supply and input signal is fed to a control electrode of the 2nd TR N1, load impedance sets P2, P3, N2 are connected between the 1st DC power supply terminal VDD2 and an output terminal OUT of the level conversion circuit, the 2nd N channel TR N1 is connected in parallel with a main path of a 3rd P channel TR P1 being an opposition conduction type and a prescribed DC bias voltage is given to the control electrode of the 3rd TR P1 and the control electrode of the 1st TR N2.