baber/WOPTO huggingface dataset:
Patent TW-531782-B (TW)
Title: System and method for calibrating mirrors of a stage assembly
Inventor: BINNARD MIKE
IPC: G12B5/00
Filed: 2001-11-27
Granted: 2003-05-11
Abstract: A stage assembly (10) for moving and positioning a device (26) is provided herein. The stage assembly (10) includes a stage base (12), a device table (48), a stage mover assembly (16), a measurement system (20), and a control system (22). The stage mover assembly (16) moves the device table (48) along an X axis, along a Y axis, and about a Z axis relative to the stage base (12). The measurement system (20) includes a first X mirror (25A) for monitoring the position of the device table (48) in an alignment position (31 A) and a second X mirror (25B) for monitoring the position of the device table (48) in an operational position (31B). In one embodiment, the stage assembly (10) includes a first fiducial mark (76) and a second fiducial mark (78) that are secured to the device table (48) to determine the relative position of the X mirrors (25A)(25B). Alternately, in another embodiment, the stage assembly additionally includes a third fiducial mark (80) secured to the device table (48) for determining the relative positions of the X mirrors (25A)(25B). In both embodiments, the control system (22) utilizes the measured position of the fiducial marks relative to the first X mirror (25A) and the second X mirror (25B) to determine the position of the first X mirror (25A) relative to the second X mirror (25B). These features allow for more accurate positioning of the device (26) by the stage assembly (10) and better performance of the stage assembly (10).
Patent TW-I245080-B (TW)
Title: Alloy galvanized steel plate having excellent slidability
Inventor: FUJIMOTO KYOKO
IPC: G01N33/20
Filed: 2001-12-05
Granted: 2005-12-11
Abstract: An alloyed hot-dip galvanized steel sheet is obtained by forming a hot-dip galvanized layer on the surface of the steel sheet and then alloying the steel sheet. The steel sheet exhibits a potential of -850 mV or less when it is immersed in a zinc sulfate-sodium chloride electrolyte. Alternatively, when it is electrolyzed according to constant potential electrolysis process in a zinc sulfate-sodium chloride electrolyte at a potential in a range from -940 mV to -920 mV, the quantity of electricity consumed is less than or equal to 0.5 C/cm<2>. The steel sheet exhibits excellent processability and particularly excellent sliding property.
Patent TW-504428-B (TW)
Title: Vibration-resistant lead-free solder composition
Inventor: LIU CHUAN-SHENG
IPC: B23K35/22
Filed: 2001-12-21
Granted: 2002-10-01
Abstract: The present invention provides a vibration-resistant lead-free solder composition, which comprises: (1) 4.0 to 7.0 wt% of Zn; (2) 0 to 3.5 wt% of Ag; (3) 0 to 3.5 wt% of rare earth metal; and (4) 86 to 96 wt% of Sn. The lead-free solder has a high vibration resistance and a good anti-oxidation performance by reducing the amount of Zn in the solder and adding Ag and a small amount of rare earth metal.
Patent TW-526640-B (TW)
Title: Manufacturing method of fiber module
Inventor: HAN SHIN-TSO
IPC: G02B6/32
Filed: 2001-12-27
Granted: 2003-04-01
Abstract: The present invention provides a manufacturing method of fiber module, wherein the fiber module includes an optical device, and a fiber side jointer for jointing with the fiber device. The fiber module manufacturing method comprises providing an optical device side jointer whose joint surface has protrusions and ferruling and fixing the same to the optical device; next, aligning the optical device and the fiber side jointer; and finally applying current to melt the protrusions of the optical device side jointer, thereby jointing the optical device side jointer with the fiber side jointer.
Patent TW-595043-B (TW)
Title: Layout for multi-antenna loops of the electromagnetic-induction system
Inventor: CHAO CHING-CHUAN
IPC: G06F3/046
Filed: 2002-01-28
Granted: 2004-06-21
Abstract: In accordance with the present invention, a new layout for multi-antenna loops of the electromagnetic-induction system is provided. The layout of multi-antenna loops in this invention comprises: a plurality of antenna loops, wherein one terminal of each antenna loop is electrically coupled with an antenna switch and the other terminal is electrically connected to a ground wire. All antenna loops are symmetrical antenna loops each of which contains a plurality of n-shaped sections to form sawtooth-shaped regions and compound into a plurality of dummy closed regions. If the symmetrical antenna loops are in-phase state, the plurality of sawtooth-shaped regions are consisted of the plurality of n-shaped sections with the non-interlaced method; if the symmetrical antenna loops are oppositephase state, the plurality of sawtooth-shaped regions are consisted of the n-shaped sections with the interlaced method.
Patent TW-530379-B (TW)
Title: Poly-silicon spacer manufacturing method of split gate flash memory cell
Inventor: OUYANG SHIOU
IPC: H01L21/764
Filed: 2002-02-01
Granted: 2003-05-01
Abstract: A poly-silicon spacer manufacturing method of split gate flash memory cell is disclosed. When the main split-gate structure of the flash memory cell is completed, the structure is covered with a poly-silicon layer and then further covered with a hard mask layer formed of oxynitride or nitride layer. Through the protection of this hard mask layer, the punches are prevented to be formed in the substrate, which may result in forming a vertical spacer, when proceeding the poly-silicon spacer etching. Besides, oxygen plasma is further used to form an oxide layer on the poly-silicon layer for use as the sacrificial hard mask when the spacer etching proceeds a span. The sacrificial hard mask can avoid forming a dish on the spacer, so that the shape of the spacer approximates to a square.
Patent TW-570911-B (TW)
Title: Process for preparation of epsilon-caprolactam
Inventor: TSUNODA TAKASHI
IPC: C07D201/04
Filed: 2002-02-15
Granted: 2004-01-11
Abstract: This invention discloses a process for preparing epsilon-caprolactam by bringing cyclohexanone oxime into contact with a solid acid catalyst under gas-phase reaction conditions to conduct the rearrangement of cyclohexanone oxime, characterized in that the solid acid catalyst is one obtained by firing a dry catalyst precursor comprising zeolite, crystalline clay minerals, and an inorganic oxide of a group 4, or 13 element of the periodic table which is different from the oxides contained in crystalline clay minerals in the form of crystalline structures and/or a compound capable of forming such an inorganic oxide through firing or in that the above rearrangement is conducted in the presence of a polyhydric alcohol derivative represented by the general formula: R1-O-R2-OH (in which R1 is C1-5 alkyl or phenyl; and R2 is C2-5 alkylene).
Patent TW-I224792-B (TW)
Title: Non volatile data storage system and data storaging method
Inventor: SHIBUYA HIROFUMI
IPC: G06F21/79
Filed: 2002-03-06
Granted: 2004-12-01
Abstract: This invention realizes separate control for each memory area. A memory unit is structured by including a semiconductor memory device capable of memorizing information, the aforementioned memory device is divided into plural memory areas logically and also management table, which is capable of controlling separately each aforementioned memory area for accessing from the outside, is tabled, control information, which prohibits accessing the prescribed memory area of the aforementioned plural memory areas, is provided in the aforementioned management information, and it is prohibited to access the specified memory area from the outside in accordance with control information.
Patent TW-567650-B (TW)
Title: A pair of electric connectors using resin welding flux on one side
Inventor: HOSAKA TAIJI
IPC: H01R12/57
Filed: 2002-03-08
Granted: 2003-12-21
Abstract: The objective of the present invention is to provide an electric connector, which allows passage of a larger current in comparison with terminals formed by MID, can be molded into a variety of configurations according to the applications and does not require the soldering work. On the pair of electric connectors using resin in one connector according to the present invention, the first electric connector (100) comprises a first housing (110), which is made of a synthetic resin, and a first terminal (120), which has a contacting part (121) and a connecting part (122) both being exposed on the surface of the first housing (110), is integrally formed with the first housing (110) and is made of a lead-free ultrahigh-conductive plastic being a conductive resin composite. The second electric connector (200) comprises a second housing (210), which is made of an insulating material, and a second terminal (220), which is made of a conductive material of which elasticity is higher than that of the lead-free ultrahigh-conductive plastic, has a contacting part (221), which contacts the contacting part (121) of the first terminal (120), and a connecting part (222), which is exposed on the surface of the second housing (210), and is provided with the second housing (210).
Patent TW-533678-B (TW)
Title: Reference voltage circuit
Inventor: KUO CHENG-HSIUNG
IPC: H03G3/00
Filed: 2002-03-19
Granted: 2003-05-21
Abstract: A reference voltage circuit is disclosed. The reference voltage circuit comprises: an amplifier having a first input terminal, a second input terminal and an output terminal; a first pnp BJT transistor whose gate and collector are grounded; a first resistor, wherein one terminal of first resistor is connected with a emitter of the first pnp BJT transistor, and another terminal of first resistor is connected with the first input terminal of amplifier; a second resistor whose resistance is ((1/a)-1) times as much as that of the first resistor, and one terminal of second resistor is connected with the first input terminal of amplifier, and another terminal of second resistor is connected with the output terminal of amplifier; a fifth resistor; several second pnp BJT transistors whose gate and collector are grounded and emitters are connected electrically to one terminal of fifth resistor; a third resistor, wherein one terminal of third resistor is connected electrically with the second input terminal of amplifier, and another terminal of third resistor is connected electrically with another terminal of fifth resistor; a fourth resistor whose resistance is ((1/a)-1) times as much as that of third resistor, and one terminal of fourth resistor is connected with the second input terminal of amplifier, and another terminal of fourth resistor is connected with the output terminal of amplifier. Since the voltages at two input terminals of amplifier are increased appropriately, the NMOS transistor of amplifier is driven effortlessly at high temperature. Therefore, an accurate reference voltage is provided at high temperature by utilizing the reference voltage circuit of the present invention.
Patent TW-538548-B (TW)
Title: Process for producing gallium nitride crystal substrate, and gallium nitride crystal substrate
Inventor: SHIBATA MASATOMO
IPC: H01L21/205
Filed: 2002-03-26
Granted: 2003-06-21
Abstract: A metal film is deposited on a starting substrate, which is any one of a single crystal sapphire substrate, a substrate comprising a single crystal gallium nitride film grown on a sapphire substrate, and a single crystal semiconductor substrate, and a gallium nitride film is deposited on the metal film to form a laminate substrate. By virtue of the above construction, after the growth of the gallium nitride film, the gallium nitride film can be easily separated from the starting substrate, and a gallium nitride crystal substrate, which has low defect density and has not been significantly contaminated with impurities, can be produced in a simple manner.
Patent TW-552648-B (TW)
Title: Methods for forming ultrashallow junctions with low sheet resistance
Inventor: DOWNEY DANIEL F
IPC: H01L21/265
Filed: 2002-04-02
Granted: 2003-09-11
Abstract: Methods and apparatus are provided for forming ultrashallow junctions in semiconductor wafers. The method includes the step of introducing into a shallow surface layer of a semiconductor wafer a dopant material that is selected to form charge carrier complexes, such as exciton complexes, which produce at least two charge carriers per complex. The semiconductor wafer containing the dopant material may be processed, such as by thermal processing, to form the charge carrier complexes. The charge carrier complexes are interstitial and therefore are not subject to the limitations imposed by the electrical solubility limits resulting from incorporation into substitutional sites. Thus, low sheet resistance can be obtained.
Patent TW-563355-B (TW)
Title: Method for operating a CMOS image sensor with increased sensitivity
Inventor: GRUPP JOACHIM
IPC: H04N3/15
Filed: 2002-05-28
Granted: 2003-11-21
Abstract: There is disclosed a method for operating a CMOS image sensor including a plurality of pixels (50) each of the pixels including a photo-sensor element (PD) producing charge carriers in proportion to its illumination and storage means (C1) capable of being coupled and uncoupled from the photo-sensor element at a determined instant in order to store, on a memory node (B) of the pixel, a measuring signal representative of the charge carriers produced by said photo-sensor element. Each pixel includes at least first MOS transistor (M2) connected via its source and drain terminals respectively to the photo-sensor element and to the storage means. At least during the pixel exposure step, an intermediate level voltage (VINT) is applied to the gate terminal of the first transistor, said intermediate voltage being selected so that the charge carriers produced by the photo-sensor element are entirely transferred via the first transistor onto the storage means.
Patent TW-544992-B (TW)
Title: Semiconductor device with delay correction function
Inventor: YAZAWA MINOBU
IPC: H03K5/13
Filed: 2002-07-04
Granted: 2003-08-01
Abstract: A semiconductor device includes a delay amount measuring unit, multiple delay sections and a correction signal generating unit. The delay amount measuring unit for measures an actual delay amount corresponding to a specified delay amount by supplying a clock signal with a known period to multiple 1-ns-delay strings with a preassigned delay amount, and by detecting phase variations of the clock signal by the 1-ns-delay strings. The delay sections includes a delay string capable of freely adjusting a connection number of its delay elements. The correction signal generating unit generates a correction signal for enabling each of the delay sections to correct the connection number of the delay strings such that each delay section has a desired delay amount, in accordance with the actual delay amount corresponding to the specified delay amount and measured by the delay measuring unit.
Patent TW-583364-B (TW)
Title: A weft measuring length storing device of measuring length storing amount adjusting device in a loom
Inventor: TSUJIMOTO KOUICHI
IPC: D03D47/36
Filed: 2002-07-05
Granted: 2004-04-11
Abstract: The present invention is provide a measuring length storing amount adjusting device in flavor of cost. The measuring length storing amount adjusting device is composed of a circular base frame 23 which engages with a cylinder portion 151 of supporting substrate 15, an indication body 24 which is moveably mounted on the base frame 23 5 and a screw 25 which is to used to mount the indication body 24 onto the base frame 23. The front portion of the indication body is bent into a right angle-shaped, so as to form a position limit piece 241. The adjustment of measuring length storing amount is carried out by engaging a weft engaging surface 193 of winding weft surface 19 with a limit surface 242 of the position limit piece 241 through engaging the base frame 23 with the cylinder portion 151.
Patent TW-593037-B (TW)
Title: An improved bicycle saddle
Inventor: GIRARDI ANTONIO
IPC: B62J1/00
Filed: 2002-07-10
Granted: 2004-06-21
Abstract: An improved saddle, in particular for sports bicycles, mountain trail bicycles, city bicycles and others is of the type which has an opening with a longitudinal profile. This opening engages substantially the central portion of the bearing body and partially also the front portion which is more tapered. The saddle is characterized by the fact that the longitudinal opening is padded with a material different with respect to the material which constitutes the padding of the remainder of the saddle.
Patent TW-I255695-B (TW)
Title: Method and device for producing ultrafine dispersion of noble metal
Inventor: HIRATA YOSHIHIRO
IPC: A23L1/304
Filed: 2002-09-27
Granted: 2006-06-01
Abstract: By using a devise equipped with a high-voltage discharging power supply, a high-voltage discharging device for the noble metal electrode and the counter electrode, water-containing tank, water intrance of the tank and outlet for the aqueous ultrafine dispersion of the noble metal ultramicrons, an isoionic gaseous discharge between the noble metal electrode and the counter electrode is performed in water, and the noble metal steam may be contacted with water then be finely disperseed. Through the high-safety device, an aqueous ultrafine dispersion of noble metal at adjustable concentration can be efficiently produced. The water produced according to the present invention is healthful.
Patent TW-591167-B (TW)
Title: Seismic isolation bearing
Inventor: LEE GEORGE C
IPC: E04H9/02
Filed: 2002-10-24
Granted: 2004-06-11
Abstract: A seismic isolation bearing comprises a lower plate, an upper plate, and a cylindrical roller in rolling contact with an upwardly facing bearing surface of the lower plate and a downwardly facing surface of the upper plate. The lower plate is fixable to a base, while the upper plate is fixable to a superstructure, for example a bridge deck. One or both bearing surfaces are sloped to form a central trough at which the cylindrical roller resides under normal weight of the superstructure, and toward which the roller is biased when relative displacement between the lower and upper plates occurs to provide a constant restoring force. A pair of sidewall members are fixed to the lower plate to withstand strong forces directed laterally with respect to the isolation axis along which rolling displacement occurs, and a pair of sliding guides carried one at each end of the roller provide dry frictional damping as they engage an inner wall surface of a corresponding sidewall member. The isolation bearing preferably comprises a locking mechanism that prevents relative displacement under normal non-seismic horizontal loading, but allows the bearing to function as intended under seismic loading. Visco-elastic or viscous dampers, linear springs, and nonlinear springs such as hardening springs are preferably mounted between the lower and upper plates to reduce bearing displacement, dissipate energy, and otherwise adjust periodic motion characteristics of the bearing. Further embodiments providing isolation along orthogonal X and Y axes are also disclosed.
Patent TW-I233425-B (TW)
Title: Aggregation of radially-protruding sharp end multi-layer carbon nanotubes and method for producing thin same
Inventor: IIJIMA SUMIO
IPC: C01B31/02
Filed: 2002-11-04
Granted: 2005-06-01
Abstract: An aggregation composed of a plurality of sharp end multi-layer carbon nanotubes which protrude radially is produced by introducing a carbon rod into a flame of a plasma generated in an atmosphere of an inert gas with hydrogen gas added therein so that the carbon can be evaporated and then deposited on a surface of the carbon rod so as to form the aggregation. The sharp end multi-layer carbon nanotube in the aggregation has a novel carbon nanotube structure and can be used as a probe for a STM or a AFM, a field emission electron source for a display element or a display, etc..
Patent TW-I232441-B (TW)
Title: Starting method after completing acceleration of optical disc writing procedure
Inventor: HUANG LIANG-TANG
IPC: G11B7/004
Filed: 2002-12-17
Granted: 2005-05-11
Abstract: A starting method after completing acceleration of optical disc writing procedure for use in the recording control of chipset inside the optic-disc recording machine is provided in the present invention. After the optic-disc recording machine completes the write-in procedure and when the reading procedure is started, the chipset directly uses the track information in the memory block and the focus server parameter to directly read the recorded data on the optical disc. Therefore, the invention is capable of saving time consumed in reading the procedure for the conventional optical disc recording machine.
Patent TW-I248680-B (TW)
Title: Lateral-type junction field effect transistor and its manufacturing method
Inventor: FUJIKAWA KAZUHIRO
IPC: H01L29/808
Filed: 2002-12-20
Granted: 2006-02-01
Abstract: In the invented lateral-type junction field effect transistor, the first gate layer (18A) containing p-type impurity concentration higher than the impurity concentration of the second semiconductor layer (12) is disposed between the source/drain region layers (6, 8) in the third semiconductor layer (13) so as to cross over the second semiconductor layer (12) and the third semiconductor layer (13) with its lower side extending to the second semiconductor layer (12). In addition, the second gate layer (18B) containing p-type impurity concentration roughly equal to that of the first gate layer (18A) and having the same electric potential as that of the first gate layer (18A) is disposed between the source/drain region layers (6, 8) in the fifth semiconductor layer (15) with its lower side extending to the fourth semiconductor layer (14). Therefore, it is capable of providing a kind of lateral-type junction field effect transistor having a structure that can reduce the conduction resistance under the condition of maintaining excellent voltage endurance.
Patent TW-582139-B (TW)
Title: Integrated circuit and circuit arrangement for converting a single-rail signal into a dual-rail signal
Inventor: KUENEMUND THOMAS
IPC: H04L9/10
Filed: 2003-01-13
Granted: 2004-04-01
Abstract: The invention proposes an integrated circuit for converting a single-rail signal into a dual-rail signal, where a conversion means (500) is connected between a data input (501) and a data output (502, 503). The conversion means (500) comprises a memory cell whose input (SZE) is connected to the data input (501) on the integrated circuit and whose output connections (SZA1, SZA2) in the transparent state of the memory cell provide the logically valid dual-rail signal. Arranged between the output connections (SZA1, SZA2) of the memory cell (SZ) and the output connections (502, 503) of the integrated circuit is a circuit arrangement (520) which precharges the output lines connected to the output connections and ensures a direct passage from the precharge phase to the logic state on the output lines, and vice versa.