Patent GB-1420863-A (GB)
Title: Apparatus for handling arrays of semi-conductor chips
IPC: H01L21/00
Filed: 1973-03-19
Abstract: 1420863 Handling semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 19 March 1973 [31 March 1972] 13011/73 Heading H1K A handling fixture 10 for integrated semiconductor chips comprises a housing 12 (Fig. 1) containing a vacuum chamber 14 with top surface 16 receiving a semi-conductor wafer comprising plural integrated circuit chips 20. The surface contains for each integrated chip (Figs. 2, 3) plural vacuum passages 22 extending therethrough and a chip placement access passageway 24 intersecting the top surface. A chip placement tube 26 engages housing 12 and is reciprocable normally to surface 16 through passageway 24; and is provided one for each chip or is alternatively made movable to register with successive passageways. A registration slot of the housing engages a member 32 forming part of chip handling apparatus incorporating the fixture. In operation, the wafer 18 prior to placement is diced, e.g. by a laser beam into individual chips 20 without disturbing the orientation maintained by the vacuum passages 22. The fixture 10 is inverted and mounted on placement apparatus incorporating X-Y positioning apparatus 34 positioning a selected chip, e.g. 36 over contact lands (not shown) in a modular substrate 38 by traversing the fixture 10, the substrate, or both along X and Y axes (Fig. 4). Mechanical traversing means 39 serve to displace other substrates to the position of substrate 38 when required, and the contact lands thereon are accurately aligned with contact pads on chips 36 using, e.g. positioned mirrors and a split field microscope (not shown). After alignment the chip placement tube is lowered through passageway 24 and vacuum is applied to support chip 36, and the vacuum through passageways 22 is broken so that the chip is lowered on to the substrate. Vacuum in tube 26 is removed to release the chip and the placement tube is retracted so that another chip may be registered for placement on substrate 38. Other vacuum passageways 22 and chip placement access passageways 24 from which chips have been detached for placement are shown. Production proceeds according to a flow chart (Fig. 5, not shown) in which after alignment of the wafer on the fixture the chips are D.C. and A.C. tested and visually inspected and the qualities of the chips are recorded. Thereafter the wafer is laser diced and residues removed without disturbing orientation. The chips are treated with flux and after placing are solder reflow bonded to the substrates and cleaned, after which the applied chips are tested and if satisfactory are assembled into packaged integrated circuit modules. Unsatisfactory chips are removed using the apparatus described in Specification 1,372,144 and replaced. They may be sorted, reworked, retested, and returned to the flow if satisfactory. The chip alignment system may be incorporated in a multistation production line comprising alignment, testing, inspection, dicing, chip placement testing, and defect removal stations; with a defect recycling and testing station; all under control of a central computer (Fig. 6, not shown).