Patent GB-835562-A (GB)
Title: Improvements in or relating to devices for counting and shaping electrical pulses
IPC: H03K3/45
Filed: 1956-10-23
Abstract: 835,562. Circuits of multistable magnetic elements. KIENZLE APPARATE G.m.b.H. Oct. 23, 1956 [Oct. 25, 1955; Oct. 12, 1956], No. 32263/56. Class 40 (9). [Also in Group XIX] A device for counting electrical pulses comprises a counting transformer with a core of substantially rectangular hysteresis loop and including circuit means controlled by the pulses to be counted operative to stepwisely magnetize the core from one stable state to the other. As shown in Fig. 1, negative pulses to be counted are applied at terminal 12 to a pulse shaping stage 1, the output pulses from which have a predetermined voltage-time integral and are fed to a decimal or other counter comprising stages 2, 4 ... , &c. The transformers of the various stages 1, 2, 4 ... have cores of a material with a substantially rectangular hysteresis loop. Input-pulse shaping.-Each negative pulse from terminal 12 passes through the winding 16 to the base of a normally blocked transistor 10 which commences to pass current through the winding 17. Magnetic feedback to the winding 16 results in the transistor being acceleratingly sent into fully conducting condition. The core is thus reversely magnetized and a positive output driving pulse is induced in a winding 19 to be passed to the first counting stage 2. When the core is fully saturated, no more current is induced in its windings and the negative rest voltage in the winding 18 returns it to its original saturation condition ready for the next pulse shaping operation. Decimal counting, first embodiment.-The pulses applied to the units, tens, &c. transformers 2, 4, &c. are such that each core is carried from one saturation condition to the other by ten pulses. Each counting transformer such as 2 has an input winding 21, an oppositely wound compensating winding 24 connected thereto at 23, an output winding 27 to the next stage and a reset winding 26. Driving pulses of constant voltage-time integral from the pulseshaping transformer 1 are fed to the input winding 21. Each such pulse changes the flux level of the core of the transformer 2 by onetenth of the total flux difference between the two stable saturation levels. Each driving pulse results in a voltage drop at point 23 of the resistance 22, such that the voltages induced in the compensating winding 24 ensure that no pulse appears at the point 25 during the first nine driving pulses. When the tenth driving pulse arrives, however, the state of the core is so near saturation that substantially no compensating voltage is induced in the winding 24. Hence the voltage drop at the point 23 will pass to the base of a transistor 3 causing it to conduct and thereby pass a current to the reset winding 26 to return the core to its original saturation condition, whereupon transistor 3 will return to its normally cut-off state since no more voltages will be induced in the core windings. Possible unwanted voltage peaks are obviated by integration over a time a little greater than the duration of one pulse by an R-C circuit 30, 31. Feedback of unwanted voltages to the previous stage is obviated by a diode 20. The negative pulse from the output winding 27 produced by the tenth driving pulse is fed to the next (tens) counter stage 4 and so on. The counter is zeroized by a positive pulse applied over the terminal 61. The counter may be provided with means for indicating the counting operation, Fig. 5 (not shown), comprising high-vacuum tubes coated with a fluorescent material which conduct when a transfer occurs. Second embodiment, Fig. 3.-The units stage counting transformer 2 has five windings coupled to an auxiliary resetting transformer 200 with two windings. Pulses are fed to the input winding 21 of the transformer 2 from a winding 19 on the pulse-shaping stage over a transistor 201 which is normally cut off. The pulse pair occurring at the-windings 19, 15 of the transformer 1 unblock the transistor 201, thereby stepping the flux in the core 2 incrementally from its normal saturation condition. A positive pulse is induced in the compensation winding 24 at each step. Simultaneously, the transistor 201 energizes the winding 221 of the resetting transformer 200 such that a negative pulse is induced in the winding 224 thereof. These two pulses effectively cancel for the first nine steps so the transistor 3 is unaffected. The tenth input pulse, however, effects substantially no more flux change and the uncompensated negative pulse induced in the winding 224 unblocks the transistor 3. The winding 26 therefore passes current to back magnetize the core 2 to its original state. During this period a positive transfer pulse is passed to the next counter stage by the output winding 27.