baber/WOPTO huggingface dataset:
Patent JP-2005072153-A (JP)
Title: Far-infrared light emitting device and far-infrared laser
Inventor: KOMIYAMA SUSUMU
IPC: H01S5/30
Filed: 2003-08-21
Abstract: <P>PROBLEM TO BE SOLVED: To provide a small and low power-consumption far-infrared light emitting device which is capable of emitting far-infrared light and has a wavelength variable function.  <P>SOLUTION: The far-infrared light emitting device has, on a two-dimensional electron system 4 formed in a solid material such as Si, GaAs, or the like, a disk-like source electrode 5, an annular gate electrode 6 which is formed outside the source electrode 5 and has a cutout 6a in part of the annulus ring, a first gate electrode 7 formed at a given distance away from the cutout 6a outside the gate electrode 6, and a drain electrode 8 formed further outside the first gate electrode 7. The far-infrared light emitting device 1 is made into a quantum hall state of a Landau level filling rate of 4. By applying voltage to the first gate electrode 7 to set a Landau level filling rate below the first gate electrode 7 to 2 and by adjusting a potential difference between the source electrode 5 and the drain electrode 8, a difference in energy between a lower Landau level 9a and an upper Landau level 9b is made to become a chemical potential difference the same as or above Landau level energy (cyclotron energy).  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2004088109-A (JP)
Title: Wafer table and semiconductor package manufacturing apparatus using it
Inventor: KIM JAE-HONG
IPC: H01L21/68
Filed: 2003-08-22
Abstract: <P>PROBLEM TO BE SOLVED: To provide a wafer table which can hold a wafer without using a wafer tape and transfers each of chips separately without mechanical interference between the transferred chip and the adjacent chip, and to provide a semiconductor package manufacturing apparatus using the wafer table.  <P>SOLUTION: The wafer table 40 is equipped with a suction plate 41, a chip suction device 51, a vacuum port and an operation means. The suction plate 41 is to hold the wafer and has an upper surface for holding a first principal surface of the wafer. Each of the chip suction devices 51 is located on a lower portion of each of a plurality of chips 14. Each of the vacuum ports is located on each of the chip suction device 51 to apply a vacuum on a part of the first principal surface of the above wafer, adjacent to the chip suction device 51 selectively. The operation means elevates each of the chip suction devices 51 by a predetermined distance upper the plane corresponding to the surface of the suction plate 41.  <P>COPYRIGHT: (C)2004,JPO
Patent JP-2005071166-A (JP)
Title: Atm status display system
Inventor: GOTANDA SAYURI
IPC: G06Q40/00
Filed: 2003-08-26
Abstract: <P>PROBLEM TO BE SOLVED: To provide a system which displays vacant situation of automatic teller machines (ATMs) on a large size display, relating with what vacant situation of ATMs is displayed on a large size display.  <P>SOLUTION: In this system, ATMs 1 transmit information on situation contents to an ATM monitoring apparatus 2, after customers begin transactions. The ATM monitoring apparatus 2 transmits the received information on the situation contents of the specific ATM to a large size display control apparatus 3. The large size display control apparatus 3 creates a situation display screen which shows the location of the ATM whose situation is changed based on the information on situation contents of the specific ATM from the ATM monitoring apparatus 2, and displays the situation display screen on a large size display 4.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005070607-A (JP)
Title: Method and structure for splicing optical fiber
Inventor: TAKAI SHINJI
IPC: H01S3/06
Filed: 2003-08-27
Abstract: <P>PROBLEM TO BE SOLVED: To provide an optical fiber splicing method in which a double-clad fiber having a second clad with a plurality of slots can be spliced to an optical fiber, with the respective cores accurately aligned.  <P>SOLUTION: The method for splicing a double-clad fiber 20 and a single mode fiber 30 to each other includes a fiber end machining process in which the fiber end of the double-clad fiber 20 is etched so that the core 1 of the fiber end is visible from the side of the fiber, and also includes a fiber splicing process in which the end of the double-clad fiber 20 worked in the fiber end machining process and the end of the single mode fiber 30 are spliced by abutting on each other.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005070686-A (JP)
Title: Pasting sheet combination object
Inventor: TAKAHASHI KAZUHIRO
IPC: C09J7/02
Filed: 2003-08-28
Abstract: <P>PROBLEM TO BE SOLVED: To provide a pasting sheet combination object which is a pasting sheet for advertisement and propaganda adequate for use by being glued to a floor surface and is constituted in such a manner that the simple pasting sheet capable of dealing with patterns of a small lot in diversified kinds can be supplied.  <P>SOLUTION: The pasting sheet combination object consists of two sheets; a printing receptive tacky adhesive sheet 20 which can be printed with the patterns for advertisement and propaganda and a surface protective tacky adhesive sheet 10 for protecting the surface of the printing receptive tacky adhesive sheet after printing. The printing receptive tacky adhesive sheet 20 is formed by laminating, successively from the surface, a printing acceptive base material sheet 21 having printing receptivity at least on its surface, a tacky adhesive layer 22 and a releasable release sheet 23 in this order. The surface protective tacky adhesive sheet 10 is formed by laminating, successively from the surface, a transparent surface resin layer 11 containing inorganic particles 11a having the hardness higher than the hardness of the cured matter of an ionization radiation curable resin in the cured matter, a transparent base material sheet 12 consisting of a thermoplastic resin, a transparent tacky adhesive layer 13, and a releasable release sheet 14 in this order.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005076212-A (JP)
Title: Ground improvement body creating device and its construction method
Inventor: TANAKA NORIO
IPC: E02D3/12
Filed: 2003-08-28
Abstract: <P>PROBLEM TO BE SOLVED: To provide a ground improvement body creating device and its construction method for preventing excessive agitation of a hardener, and improving agitating efficiency.  <P>SOLUTION: This ground improvement body creating device 10 has a rod part 11 capable of advancing/retreating and rotating and a monitor part 12, for creating a solidification body by injecting the hardener into a drilled hole formed in the object ground. The monitor part 12 has a pair of agitating blades 13a and 13b mutually vertically extending in the opposite direction to a shaft, and at least a pair of nozzle ports 14a and 14b opening in a side surface for injecting the hardener. The respective nozzle ports 14a and 14b are arranged for injecting the hardener toward any one tip of the pair of agitating blades 13a and 13b while inclining in the vertical direction to the shaft.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005079199-A (JP)
Title: Semiconductor manufacturing method
Inventor: UEHARA TADAO
IPC: H01L21/60
Filed: 2003-08-28
Abstract: <P>PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method which performs polymer elimination comparatively easily without increasing processor, improves adhesiveness of a bonding pad opening and wire bonding without generating abnormal growth of metal wiring of a lower layer, and improves yield.  <P>SOLUTION: Elimination treatment of polymer which adheres to a metal film surface layer after bonding pad opening treatment is performed by surface etching treatment using O<SB>2</SB>+ CF<SB>4</SB>in an identical treatment room or a following chamber or another equipment chamber after bonding pad opening treatment. Concerning a sample subjected to the O<SB>2</SB>+ CF<SB>4</SB>plasma treatment, O and F are not detected on the metal film surface, so that it can be confirmed that there is countermeasure validity to deposition film elimination by the O<SB>2</SB>+ CF<SB>4</SB>plasma treatment.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005075085-A (JP)
Title: Mounting structure of weather strip with built-in sensor to flange of slide door
Inventor: UCHIDA TAKESHI
IPC: B60J10/08
Filed: 2003-08-29
Abstract: <P>PROBLEM TO BE SOLVED: To prevent a sensor of a weather strip with a built-in sensor from being crushed.  <P>SOLUTION: In this mounting structure, the flange 114 of a slide door is clamped between the first side wall part and the second side wall part of the weather strip 1 with a built-in sensor, which is provided with a welt part 9 formed in an almost U-shape by the first and the second side wall parts 5, 6 arranged at a prescribed interval and a third side wall part 7 connecting those side wall parts, having a sensor housing part 8 integrally formed in the third side wall part, and a hollow seal part 10 provided in the first side wall part 5 of the welt part, thereby mounting the weather strip to the flange at the rim part of an inner panel and an outer panel. The first side wall part is provided with notches 11, 12 for overlapping the first side wall part of the welt part overlapped on the door outer panel side of the flange to the door inner panel side of the flange at the fold part 117 of the flange 114.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005078524-A (JP)
Title: Card delivery device
Inventor: ITO YOSHIHIDE
IPC: G06K13/103
Filed: 2003-09-02
Abstract: <P>PROBLEM TO BE SOLVED: To reduce the number of component; to simplify a structure; and to miniaturize a device.  <P>SOLUTION: A moving member 25 moving in the direction of an arrow A-B of figure (a) is provided with a mounting part 25a for mounting cards C, and a claw part 25c higher than the mounting part 25a. A roller 26 is rotatably supported to the moving member 25 in the direction of an arrow B of figure (b) on the side opposite to a card delivery direction as compared with the claw part 25c. The upper end of the roller 26 is so formed as to be higher than the claw part 25c and lower than the thickness 2t of two of the cards C from the mounting part 25a.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005074401-A (JP)
Title: Active microbe supplying apparatus and method for treating waste water by using the same
Inventor: SUGAI KENICHI
IPC: C02F3/00
Filed: 2003-09-03
Abstract: <P>PROBLEM TO BE SOLVED: To provide an active microbe supplying apparatus by which waste water can be treated by decreasing the usage of a microbial cell activating agent.  <P>SOLUTION: This active microbe supplying apparatus 10 is constituted so that a microbe is activated by using the waste water in a waste water treating tank 40 and the obtained active microbe-cultured liquid is supplied again to the waste water treating tank 40. This apparatus 10 is composed of two tanks of a waste water exchanging tank 20 and a microbe keeping tank 30 adjacent to the waste water exchanging tank 20. The waste water exchanging tank 20 is provided with: a waste water introducing pipe 21 communicating with the waste water treating tank 40 for pumping the waste water from the waste water treating tank 40; a microbe-cultured liquid sucking pipe 22 for sucking the active microbe-cultured liquid activated in the waste water exchanging tank 20; a microbe-cultured liquid discharging pipe 24 connected to the microbe-cultured liquid sucking pipe 22 for discharging the active microbe-cultured liquid to the waste water treating tank 40; and a circulation pipe 31 for supplying the waste water in the waste water exchanging tank 20 to the microbe keeping tank 30. The waste water exchanging tank 20 and the microbe keeping tank 30 are provided respectively with air diffusing pipes 33, 34 connected to air pumps 35, 36.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005079070-A (JP)
Title: Board-to-board electrode jointing method and structure
Inventor: AKAIKE MASATAKE
IPC: H01L21/60
Filed: 2003-09-04
Abstract: <P>PROBLEM TO BE SOLVED: To provide a method for jointing board-to-board electrodes which stably keeps electrical conduction, and also to provide a structure composed by carrying out that kind of jointing.  <P>SOLUTION: In this board-to-board electrode jointing method, conductor electrode parts 6 and 8 having projecting parts 8 are formed on one-side board 2; conductor electrode parts 5 and 7 having recessed parts 9 are formed on the other-side board 1; thereafter the one-side board 2 and the other-side board 1 are faced with each other; and the projecting parts 8 are inserted into the recessed parts 9 and a load is applied to the boards 1 and 2, whereby the insertion parts are plastically deformed to joint them to each other.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005085872-A (JP)
Title: Semiconductor element and method of manufacturing the same
Inventor: TAKAHASHI KUNIMASA
IPC: H01L29/12
Filed: 2003-09-05
Abstract: <P>PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor element in a normally-off state which can allow the flow of a drain current of higher current density.  <P>SOLUTION: The semiconductor element comprises an n-type drift layer 2 formed on a silicon carbide substrate 1, a p-type well region 3 formed on the upper part of the drift layer, an n-type accumulation channel layer 6 formed on the n-type drift layer 2 and the p-type well region 3, a gate insulating film 5 and a gate electrode 8 formed and provided on the accumulation channel layer 6, a first p-type impurity-doped layer 7a which is formed to the region located at the lower part of both ends of the gate electrode 8 in the accumulation channel layer 6 and includes a carrier of a concentration higher than that of the p-type well region 3, an n-type source contact region 4 and a second p-type impurity-doped layer 7b formed on the p-type well region 3, a source electrode 9 provided on the source contact region 4, and a drain electrode 10 provided on the rear surface of the silicon carbide substrate 1.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005080910-A (JP)
Title: Game machine
Inventor: ITO SATOSHI
IPC: A63F7/02
Filed: 2003-09-09
Abstract: <P>PROBLEM TO BE SOLVED: To attain a rendition corresponding to a matter that a player has strong desire to know previously.  <P>SOLUTION: The combination of ready-for-win indicated in (b) of a figure is generated in a first pattern combination game in a visible display part H, so as to be losing. Then, in the second pattern combination game in the visible display part H, the combination of ready-for-win indicated in (c) of the figure is generated and becomes losing. Then, in the third pattern combination game in the visible display part H, the combination of ready-for-win indicated in (e) of the figure is formed and becomes losing. In the fourth pattern combination game in the visible display part H, the combination of ready-for-win indicated in (g) of the figure is generated, and then, the combination of a big hit indicated in (h) of the figure is derived and becomes winning. Consequently, as indicated in (a) of the figure, a continuous read-for-win rendition, based on patterns belonging to a big-three-dragon group started from the first pattern combination game, is realized.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005084013-A (JP)
Title: Voltage monitoring circuit
Inventor: TAKEDA AKIRA
IPC: H03K19/00
Filed: 2003-09-11
Abstract: <P>PROBLEM TO BE SOLVED: To provide a voltage monitoring circuit operated stably with a low current consumption and a low voltage.  <P>SOLUTION: This voltage monitoring circuit is constituted as follows: a depression type MOS transistor 101 and an enhancement type MOS transistor 102 are connected in series respectively; the first voltage supply terminal 103 is provided on a drain of the depression type MOS transistor; the second voltage supply terminal 104 is provided on a source one transistor of the enhancement type MOS transistor; the gate of the depression type MOS transistor is connected to the second voltage supply terminal 104; the output of dividing resistances 107, 108 for dividing the voltage between the gate of the enhancement type MOS transistor and a monitoring voltage terminal 106 at a prescribed ratio is applied; and a mutual connection endpoint node between the depression type MOS transistor and the enhancement type MOS transistor is used as an output terminal 105.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005086777-A (JP)
Title: Wireless communication channel selection method, wireless communication channel selection method for master unit, and wireless data communication method for slave unit
Inventor: TERADA KAZUHIKO
IPC: H04W48/02
Filed: 2003-09-11
Abstract: <P>PROBLEM TO BE SOLVED: To attain effective utilization of a band for data communication.  <P>SOLUTION: A master unit determines a communication time required for a slave unit on the basis of terminal type information included in a connection request signal from the slave unit (STA4). Then the master unit selects one of a plurality of data communication channels and discriminates whether or not the determined communication time can be allocated for the selected data communication channel (STA5). Further, the master unit transmits a connection request response signal including information of the selected data communication channel to the slave unit (STA6).  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005093815-A (JP)
Title: Semiconductor device manufacturing method
Inventor: HAYASHI KIYOSHI
IPC: H01L29/78
Filed: 2003-09-18
Abstract: <P>PROBLEM TO BE SOLVED: To reduce the gate electrode depletion layer, and to decrease the threshold voltage absolute value.  <P>SOLUTION: A channel region is positioned in the surface layer of a silicon substrate 1 and is sandwiched in between N-type source/drain regions 31. A gate insulating film 21, which is a positive charge containing HfO<SB>2</SB>film, is formed directly on the channel region. A metal gate electrode 41, which is a metal film having the Fermi level equivalent to that of the channel region, is formed on the insulating gate 21.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005093965-A (JP)
Title: Method for manufacturing metal-ceramic bonded circuit board
Inventor: OSANAI HIDEYO
IPC: H05K3/10
Filed: 2003-09-22
Abstract: <P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a metal-ceramic bonded circuit board wherein a fine pattern can be formed and an etching time can be shortened even in the case that a metal plate for a circuit is thick, when metal melt is brought into contact with a ceramic substrate and cooled and solidified, the metal plate for a circuit is bonded to the ceramic substrate, the etching of the metal plate is performed, and a metal circuit board of a desired circuit pattern is formed.  <P>SOLUTION: The metal melt is brought into contact with both surfaces of the ceramics substrate 10 and cooled and solidified. The metal plate 12 for a circuit is bonded to one surface of the ceramics substrate 10, and a metal base plate 14 is bonded to the other surface of the ceramics substrate 10. An etching resist 16 is printed to the metal plate 12 for a circuit, etching is performed, and the metal circuit board 12 of a desired circuit pattern is formed. In the above case, a shape of the metal circuit board 12 which is bonded to the ceramics substrate 10 is made a shape beforehand similar to the circuit pattern.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2004115803-A (JP)
Title: Inkjet ink with reduced puddling using additive
Inventor: UHLIR-TSANG LINDA C
IPC: B41J2/01
Filed: 2003-09-24
Abstract: <P>PROBLEM TO BE SOLVED: To provide inkjet ink improved in puddling at a print head and a method for reducing the puddling of inkjet ink.  <P>SOLUTION: A puddling additive comprising an anionic polar group and a 6-30C hydrocarbon chain line is used to improve the puddling in inkjet ink. The anionic polar group is a carboxylate group, and the 6-30C hydrocarbon chain line is a saturated or unsaturated 6-30C hydrocarbon chain. The inkjet ink contains the puddling additive, a dye, and an inkjet vehicle. The method reduces the puddling of inkjet ink and includes the addition of the puddling additive to the inkjet ink.  <P>COPYRIGHT: (C)2004,JPO
Patent JP-2005096203-A (JP)
Title: Line dot recording device
Inventor: TSUJI HIROFUMI
IPC: B41J2/01
Filed: 2003-09-24
Abstract: <P>PROBLEM TO BE SOLVED: To provide a line dot recording device that moves a printing medium by a rotating drum, solves a decrease (lengthening of time) in a throughput (printing time per sheet) when an image is formed in a prescribed printing area of the medium by multipass dot recording and efficiently forms a high quality image on a plurality of printing mediums.  <P>SOLUTION: The line dot recording device A has a nozzle head 1 having a recording element using many inkjet ink discharge openings (nozzles) as a recording head, a rotary drum 2, the outside periphery of which is provided close thereto, a paper feeding means 3 feeding papers to the drum, a mounting/holding means 4 mounting and holding the four sheets of papers on the drum and a paper delivery means 5 to deliver the papers. By rotating the drum 4 at four times the speed by a four-pass multipass method, the recording device forms an image by four rotations, solves a decrease in a throughput, and obtains a high quality image.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005101206-A (JP)
Title: Package for housing semiconductor element, and semiconductor device
Inventor: OSADA TOMOICHI
IPC: H01L23/02
Filed: 2003-09-24
Abstract: <P>PROBLEM TO BE SOLVED: To surely and efficiently input/output a high-frequency signal into/from a package for housing a semiconductor element which has a coaxial connector to which a coaxial cable is connected.  <P>SOLUTION: The package for housing a semiconductor element comprises a base 1 having a placement 1a for placing a semiconductor element 5, a metallic frame body 2 formed with a through hole 2b on a side, and the coaxial connector 3 which consists of a peripheral conductor 3a, a central conductor 3b, and an insulator 3c, and which is set in the through hole 2b. On top face of a shelf 2a formed on the inner surface of the frame body 2 or on an upper-side principal plane of the base 1, a circuit board 6 is disposed which is formed on top face thereof with a line conductor 6a with one and the other ends electrically connected to the central conductor 3b and the semiconductor element 5 respectively and common-plane grounded conductors 6b which are formed at equal intervals on both sides of the line conductor 6a. Central conductor 3b-side ends of the line conductor 6a and the common-plane grounded conductors 6b do not reach a central conductor 3b-side end face of the circuit board 6.  <P>COPYRIGHT: (C)2005,JPO&NCIPI
Patent JP-2005098221-A (JP)
Title: Exhaust gas recirculation system
Inventor: KUROKI RENTARO
IPC: F02D41/02
Filed: 2003-09-25
Abstract: <P>PROBLEM TO BE SOLVED: To provide an exhaust gas recirculation system capable of improving a combustion state etc. of an auxiliary engine by supplying required recirculated gas with excellent controllability, regardless of an operating state of the auxiliary engine.  <P>SOLUTION: The exhaust gas recirculation system 1 is provided with a main EGR pipe 30M recirculating part of exhaust gas exhausted from a main engine 10 to an intake pipe 220 of a subengine 20 and a main EGR valve 31M adjusting amount of exhaust gas recirculated by the main EGR pipe 30M. The main EGR valve 31M adjusts the amount of exhaust gas recirculated in accordance with an operating state of the main engine 10 and an operating state of the subengine 20.  <P>COPYRIGHT: (C)2005,JPO&NCIPI