Patent GB-845466-A (GB)
Title: Electrical coded decimal arithmetic unit
IPC: G06F7/50
Filed: 1958-03-05
Abstract: 845,466. Coded decimal adders and subtractors. NATIONAL CASH REGISTER CO. March 5, 1958 [April 2, 1957], No. 7026/58. Class 106 (1). An electrical coded decimal arithmetic unit for summing pairs of decimal digits comprises a first adder unit 61 supplied with input signals representing one decimal digit in binary coded form and the other decimal unit in binary " excess 6 " form, and a second adder unit 62 supplied with signals representing both decimal digits in binary coded form, the adder units receiving signals also from a carry storage device Ka. Binary coded outputs of the two adder units are gated to sum output lines selectively according to whether or not the sum of the digits is greater than nine. As shown in Fig. 1, the digits of two decimal numbers to be added are applied serially to lines G1-G4 and H1-H4, respectively, each digit being represented in parallel according to the 1, 2, 4, 8 code; and the signals on lines H1-H4 are converted in diode network 21 (Fig. 2, not shown), into the " excess 6 " form on lines He1-He4. The first adder unit 61 produces sum signals on parallel lines Sel, Se2, Se3<SP>1</SP> and Se4, and decimal carry signal Ke4<SP>1</SP> which, through inverters 69, 77, supplies complementary signals to opposite sides of carry storage trigger Ka and gates 65-67. The second adder unit 62 produces partial sum signals on parallel lines Sb2, Sb3<SP>1</SP> and Sb4; and according to whether signal Ke4<SP>1</SP> (no carry) or Ke4 (carry) is operative, gates 65-67 pass the latter signals or the signals from Se2, Se3<SP>1</SP>, Se4 to sum lines S2, S3 (through inverter 81) and S4, the line S1 (for code element " 1 ") being connected directly to Se1. The adder unit 61 has four binary adder stages E1-E4, Fig. 4, each comprising transistor switching circuits as described in Specification 844,966. The carry signals Ka and Ka<SP>1</SP> from the storage trigger are applied to the first stage E1, but the following stages each receive only one form of carry signal from the preceding stage, i.e. the signal is not passed through an inverter, thus shortening the carry propagation time. The carry circuit of stage E2 thus receives the direct carry signal Kel, and the signal on G2 inverted at 83, and therefore produces the inverted form of carry output signal Ke2<SP>1</SP>. Stage E3 therefore produces the inverted form of sum signal Se3<SP>1</SP> and the direct carry signal Ke3. Stage E4, like E2, produces an inverted form of carry output. The adder unit 62 similarly comprises four stages B1-B4, but stage B1 (no sum output) and stage B4 (no carry output) are simplified. The inverters, such as 69, and gates, such as 65, also may comprise transistor circuits (Figs. 6 and 7, not shown). In an add/subtract arrangement, Fig. 8, if signal A1 is operative to open transistor gates 102, the digit signals are entered into adder units 61, 62 as in Fig. 1, whereby addition is performed; if, however, signal All is operative, transistor inverter gates 103 are opened, whereby complementary digit signals, for the number on lines H1-H4, are entered into the adder units, and trigger Ka is initially set to " 1 " (by means not shown), thus performing subtraction.