baber/WOPTO huggingface dataset:
Patent TW-401657-B (TW)
Title: Input circuit, output circuit and input/output circuit
Inventor: KAWANO HARUMI
IPC: H03K19/0175
Filed: 1998-03-31
Granted: 2000-08-11
Abstract: A kind of output circuit, which could output the voltage signal to a circuit of the power voltage of which the power voltage is higher than the power voltage of the output circuit, which the advantage is that the voltage signal could rapidly soar to the  power voltage of the output circuit; and such an input circuit could receive the voltage signal output by the circuit of the power voltage higher than the power voltage of the output circuit, to transmit forwardly the voltage signal to the power voltage equivalent with the output circuit, which advantage is that the voltage of the transmitting forwardly signal is equilivent with the power voltage of the input circuit; and an input/output circuit, which has the above-mentioned two advantages. Even, such output circuit comprising: a field effect transistor with its first normal closed state, which has the channel with electrically conductive state connects to the gate of the first node, connects to the first electrode of the first power, and the second electrode connects to the second node; a field effect transistor with its second normal closed state, which has the channel with electrically conductive state connects to the gate of the third node, the first electrode  connects to the above-mentioned the second node, the second electrode connects to the fourth node, and the bae connects to the fifth node; a field effect transistor with its third normal closed state, which has the channel with electrically conductive state connects to the gate of the sixth node, connects to the first electrode of the above-mentioned third node, connects to the second electrode of the fourth node, and the base connects to the above-mentioned fifth node; a field effect transistor with its fourth normal closed state, which has the channel with reverse electrically conductive state connects to the gate of the above-mentioned sixth node, connects to  the first electrode of the above-mentioned third node, connects to the second electrode of the second power; and a reverse phase apparature, which input terminal connects to the above-mentioned the fourth node, its output terminal connects to the above-mentioned sixth node.
Patent TW-428183-B (TW)
Title: Magnetic core and method of manufacturing the same
Inventor: MATSUTANI NOBUYA
IPC: H01F1/26
Filed: 1998-04-08
Granted: 2001-04-01
Abstract: A magnetic core of a compressed compact comprises a mixture of magnetic powder and a spacing material, wherein the distance between adjacent magnetic powder particles is controlled by the spacing material. In this constitution, a magnetic core low in core loss, high in magnetic permeability, and excellent in direct-current superposing characteristic is realized.
Patent TW-404925-B (TW)
Title: Small-size rapid cooling system, thermal insulating method and the thermal insulating bag
Inventor: TAKASUGI MITSUO
IPC: B65D88/74
Filed: 1998-06-10
Granted: 2000-09-11
Abstract: The small-size rapid cooling system comprises a liquefied gas cylinder, a supporting body used to hold the cylinder, and an operation chest installed on said cylinder supporting body, which is characterised by that: the operation chest is provided with a nozzle which could utilize a solenoid valve to inject the liquefied gas supplied from the above-mentioned liquefied gas cylinder, and further provided with an operation switch to facilitate the inject control.
Patent TW-398970-B (TW)
Title: Method of producing an apertured covering sheet for an absorbent article and a material produced in accordance with the method
Inventor: THOREN AGNETHA
IPC: A61F5/44
Filed: 1998-06-16
Granted: 2000-07-21
Abstract: A method of manufacturing a fluid permeable covering sheet (9) for an absorbent article such as a diaper, a sanitary napkin, an incontinence protector or the like, wherein heated needles (4) are brought to penetrate a sheet of textile material (1) comprising at least one thermoplastic component, whereby the thermoplastic component closest to the needles (4) melts, whereafter the needles (4) are removed and the heated material (1) is passed through at least one nip of rollers (7) so that the thermoplastic component closest around the apertures is smoothed out into a substantially smooth material surface around the apertures, whereafter the thermoplastic component is brought to solidify. The invention further pertains to an apertured covering sheet (201,301) for an absorbent article manufactured in accordance with the method, and an absorbent article (300) provided with a covering sheet manufactured in accordance with the method.
Patent TW-497094-B (TW)
Title: Optical recording medium and optical recording device
Inventor: ONUKI SATORU
IPC: G11B7/24
Filed: 1998-08-07
Granted: 2002-08-01
Abstract: A magneto-optical recording medium (400) comprises a protective layer (51), having a self-lubricating property, formed on the uppermost layer at the side opposite to a substrate (56) wherein a recording or reproducing light beam incidents. The thickness and the refractive index of the protective layer (51) are selected under predetermined conditions depending on whether or not evanescent light is transmitted through the protective layer (51). It is possible to perform high density recording and reproduction thereof by utilizing the evanescent light. A protective layer having a self-lubricating property may be also formed on a bottom surface of an optical head opposing to the optical recording medium. Even when the optical head contacts the surface of the optical recording medium, the sliding scratch scarcely occurs. This is because the optical head smoothly glides on the recording medium surface. It is possible to reduce the influence of multiple interference of light which present in an air layer between the optical recording medium and the optical head, and it is possible to suppress variation in reproduced signal intensity.
Patent TW-494130-B (TW)
Title: Coating composition based on epoxy group-containing silanes
Inventor: BIER PETER
IPC: C09D183/06
Filed: 1998-08-10
Granted: 2002-07-11
Abstract: The present invention provides a coating composition which comprises at least one silicon compound (A) which has at least one radical which is bonded directly to Si, is not able to be separated hydrolytically and contains an epoxy group, a particulate material (B) which is selected from among oxides, oxide hydrates, nitrides and carbides of Si, Al and B and of transition metals and has a particle size within the range 1 to 100nm, a Si, Ti, Zr, B, Sn or V compound (C) and at least one hydrolysable Ti, Zr or Al compound (D), which comprises the following ratio1 mol of the silicon compound (A), 0.42 to 0.68 mol of the particulate material (B), 0.28 to 1.0 mol of the compound (C) and 0.23 to 0.68 mol of the compound (D).
Patent TW-358902-B (TW)
Title: Multi-layer light mask structure and the manufacturing method
Inventor: LIN SZU-MIN
IPC: G03F1/00
Filed: 1998-09-18
Granted: 1999-05-21
Abstract: Manufacturing method of a multi-layer light mask, including: providing a transparent substrate; forming on the transparent substrate a first barrier; defining the first barrier, forming a plurality of barrier blocks; forming in the barrier blocks a transparent layer, and with an opening in the barrier regions; forming in the barrier blocks a second barrier layer on the transparent layer, and stuffing the opening; and polishing the second barrier layer, until the transparent layer exposes.
Patent TW-446836-B (TW)
Title: Method and apparatus for manufacturing liquid crystal displays
Inventor: SAKONG DONG-SIK
IPC: G02F1/13
Filed: 1998-10-29
Granted: 2001-07-21
Abstract: A liquid crystal material is injected into a liquid crystal cell while a voltage is applied to the liquid crystal cell rendering the liquid crystal molecules parallel to the substrates. The temperature of the vacuum chamber during injection of liquid crystal material is higher than the room temperature to reduce the viscosity of the liquid crystal material, and below the liquid crystal-isotropic transition temperature to maintain the liquid crystal state. To avoid the evaporation of the liquid crystal material, the temperature is preferably lower than the clearing point of the liquid crystal material. The voltage applied to the liquid crystal cell is over the threshold voltage so that the liquid crystal molecules align themselves parallel to the substrate, and the AC voltage having a low frequency of equal to or lower than 60 Hz is preferably used to make the liquid crystal material oscillate laterally. Then, the steric hindrance and interaction between the homeotropic alignment films and the liquid crystal material is reduced and thereby reducing the injection time. In the end seal process, a voltage is applied to the liquid crystal cell as in the filling process to render the liquid crystal molecules parallel to the substrates and make the excess liquid crystal material to discharge easily, and then the injection hole is sealed.
Patent TW-407107-B (TW)
Title: A method for making tyres for vehicle wheels
Inventor: CARETTA RENATO
IPC: B29D30/38
Filed: 1998-12-24
Granted: 2000-10-01
Abstract: A first carcass ply (3) is formed by depositing onto a toroidal support (11), strip-like lengths (13) cut to size from a continuous strip-like element and each comprising longitudinal thread-like elements (14) incorporated into a layer of elastomer material (17). The strip-like lengths are laid down sequentially in mutual circumferential side by side relationship, to form side portions (25) partly superposed on each other and crown portions (24) in mutual circumferential side by side relationship. Associated with the carcass ply (3) are annular structures (4) comprising a first and a second circumferentially inextensible annular inserts (27, 28) and an elastomer filling (29) interposed therebetween. A second carcass ply (31) is made in superposed position to the first carcass ply (3) and the annular structures (4). A belt structure (5), a tread band (8) and sidewalls (9) are combined with the carcass structure (2) thus formed, to define a tyre (1) to be vulcanized.
Patent TW-406425-B (TW)
Title: Active matrix substrate for liquid crystal display devices and liquid crystal display device using the same
Inventor: TAMURA TATSUHIKO
IPC: H01L21/336
Filed: 1999-02-24
Granted: 2000-09-21
Abstract: This invention relates to an active matrix substrate used for liquid crystal display devices which constitutes of active elements and address wiring disposed on aninsulating substrate. The active elements and address wiring are covered with a transparent insulating layer, and the transparent display electrodes are placed on the transparent insulating layer. The transparent display electrodes are connected to the active elements through the through-holes opened through the transparent insulating layer. The difference of refractive index between the element insulating layer which forms a portion of the active elements and that of the transparent insulating layer is controlled to be less than 0.2 to provide a liquid crystal display having a high display quality.
Patent TW-471059-B (TW)
Title: Selective treatment of the surface of a microelectronic workpiece
Inventor: AEGERTER BRIAN
IPC: H01L21/3213
Filed: 1999-03-11
Granted: 2002-01-01
Abstract: The invention provides a process for treating a workpiece having a front side, a back side and an outer perimeter. In accordance with the process, a processing fluid as selectively applied or excluded from an outer peripheral margin of at least one of the front or back sides of the workpiece. Exclusion and/or application of the processing fluid occurs by applying one or more processing fluids to the workpiece as the wordpiece and corresponding reactor are spinning about an axis of rotation that is generally parallel (or antiparallel) to the vector defining the face of the workpiece being processed. The flow rate of the one or more processing fluids, fluids pressure, and/or spin rate are used to control the extent to which the processing fluid is selectively applied or excluded from the outer peripheral margin.
Patent TW-I235179-B (TW)
Title: L-glutamic acid-producing bacterium and method for producing L-glutamic acid
Inventor: MORIYA MIKA
IPC: C12P13/14
Filed: 1999-03-18
Granted: 2005-07-01
Abstract: L-glutamic acid is produced by culturing in a liquid culture medium a microorganism belonging to the genus Enterobacter or Serratia and having an ability to produce L-glutamic acid, which increases in an activity of enzyme catalyzing a reaction for L-glutamic acid biosynthesis, or which decreases in or is deficient in an activity of an enzyme catalyzing a reaction branching from a pathway for L-glutamic acid biosynthesis and producing a compound other than L-glutamic acid, and collecting produced L-glutamic acid from the culture medium.
Patent TW-421743-B (TW)
Title: Fabricating method of dynamic random access memory module
Inventor: GUO LI-YU
IPC: G06F13/00
Filed: 1999-03-24
Granted: 2001-02-11
Abstract: This invention is about fabricating method of dynamic random access memory module, in which plural inner-circle contact points and outer-circle contact points are symmetrically disposed and arranged on both sides of a long sheet-shaped, double-side circuit board. In addition, at least one zero ohm surface mounted resistor is connected to the inner-circle contact point. By using liquid to package COB (chip on board) on both sides of the double-side circuit board so as to install the memory chip on each inner-circle contact point individually. The reliability test is then performed onto the double-side circuit board that has completed the installation of memory chip. If one of the memory chips is damaged, the surface mounted resistor connected to the inner-circle contact point is removed in order to make the memory chip installed on the inner-circle contact point become ineffective. After that, a completed memory product with plastic package and normal function is installed on the outer-circle contact point such that the damaged memory chip is replaced. Therefore, the damaged memory chip can be repaired during the fabrication process so as to preserve the other normal memory chips and reduce the production cost.
Patent TW-425564-B (TW)
Title: Self calibrating self-regenerative comparator circuit and method
Inventor: KUIJK MAARTEN
IPC: G11C7/06
Filed: 1999-05-04
Granted: 2001-03-11
Abstract: First and second currents can be compared and an output generated at first and second output nodes 3 and 4. First, the first and second output nodes 3 and 4 are calibrated such that the first output nodes 3 reaches a first real equilibrium voltage and the second output nodes 4 reaches a second real equilibrium voltage. The first real equilibrium voltage is not necessarily equal to the second real equilibrium voltage. At the active edge of a clock signal , the difference between the first and second currents can be amplified by causing the voltage at the first output nodes 3 to become lower than the voltage at the second output nodes 4 when the first current is greater than the second current. On the other hand, the voltage at the first output node 3 to becomes higher than the voltage at the second output node 4 when the first current is less than the second current. With some modifications, voltage comparisons can similarly be achieved.
Patent TW-444180-B (TW)
Title: Computer processor with a replay system
Inventor: MERCHANT AMIT A
IPC: G06F9/38
Filed: 1999-05-31
Granted: 2001-07-01
Abstract: A computer processor includes a multiplexer having a first input, a second input, and an output, and a scheduler coupled to the multiplexer first input. The processor further includes an execution unit coupled to the multiplexer output. The execution unit is adapted to receive a plurality of instructions from the multiplexer. The processor further includes a replay system coupled to the second multiplexer input and the scheduler. The replay system replays an instruction that has not correctly executed by sending a stop scheduler signal to the scheduler and sending the instruction to the multiplexer.
Patent TW-498117-B (TW)
Title: Pair of weft carrying and drawing grippers for weaving looms
Inventor: FRNAZ ERMANNO
IPC: D03D47/23
Filed: 1999-07-19
Granted: 2002-08-11
Abstract: A pair of weft carrying and drawing grippers in a shuttleless loom - of the type controlled by straps caused to perform a to-and-fro motion with the grippers fixed at the ends thereof - comprises: a stiff structural support element (1; 11) formed with oriented carbon fibers poltruded with a thermosetting material; a metal body (2; 12) carrying the weft yarn gripping devices (P); a wearplate(5; 15) to protect the front-bottom part of the gripper; and at least an abutting element (7; 17-17') of filled thermoplastic material. The strap (N), the stiff support element (1; 11), the metal body (2; 2) and the wearplate (5; 15) are connected together by screws (4-6-8; 14-16-18), engaged into threaded metal, seats inserted into said abutting element (7; 17-17'), or formed into said metal body (2; 12), or into the weft yarn gripping devices (P).
Patent TW-452743-B (TW)
Title: Low noise signal generator for use with an RFID system
Inventor: GALLAGHER WILLIAM F III
IPC: G08B13/24
Filed: 1999-07-30
Granted: 2001-09-01
Abstract: Noise reduction schemes are provided in a radio frequency identification (RFID) system for use with RFID intelligent tags. Amplitude and phase noise is minimized by starting with a low noise crystal oscillator having an output frequency which is an integer multiple n of the desired RF field frequency, and then dividing this frequency by the integer multiple n. One or more cascaded flip-flops are used for the frequency dividing. Both outputs of the final stage flip-flop are used to drive the transmitter antenna to produce a continuous wave signal.
Patent TW-425696-B (TW)
Title: Semiconductor memory device having capacitor encapsulated with multiple layers and method of manfacturing the same
Inventor: LEE YONG-TAK
IPC: H01L27/10
Filed: 1999-09-15
Granted: 2001-03-11
Abstract: A semiconductor memory device having a capacitor which is encapsulated with multiple layers, and a method for manufacturing the same. The capacitor of the semiconductor memory device is covered with the multi-layered encapsulating layer. The encapsulating layer includes at least a blocking layer and a capacitor protection layer. The blocking layer is formed of a material layer capable of preventing a capacitor dielectric layer from volatilizing and/or capable of preventing a reaction between a material layer under the blocking layer and the capacitor protection layer. The capacitor protection layer is formed of a material capable of preventing diffusion of hydrogen into a capacitor dielectric layer. The encapsulating layer can prevent deterioration of the capacitor dielectric layer during an interlayer dielectric (ILD) process, an intermetal dielectric (IMD) process and a passivation process.
Patent TW-454177-B (TW)
Title: Information carrier with a compact header format and apparatus
Inventor: SPRUIT JOHANNES HENDRIKUS MARI
IPC: G11B7/004
Filed: 1999-10-14
Granted: 2001-09-11
Abstract: Information carrier (1) comprising a pattern of substantially parallel tracks, in which a track comprises a number of sectors (5), which comprise an address-information area (18) and an accompanying data area (21). The address information areas (18), the so-called headers, are aligned with the data areas (21). These headers are composed of at least one address information field (19) and at least one synchronization field (20), in which the address information areas in adjacent tracks overlap each other. The address information fields (19) in adjacent tracks are positioned free of overlap relative to each other while adjacent synchronization fields (20) overlap address information fields. In this way a compact header is realized. The invention is further related to an apparatus for reading the information carrier (1). Using a synchronization or a lock-in signal (31) resulting from the reading of the synchronization fields (20), the length of the synchronization fields is detected enabling a reliable read-out of the address information fields.
Patent TW-440995-B (TW)
Title: Semiconductor integrated circuit device and the manufacturing method thereof
Inventor: NISHIMURA ASAO
IPC: H01L21/82
Filed: 1999-12-21
Granted: 2001-06-16
Abstract: The present invention relates to the semiconductor integrated circuit device and the manufacturing method thereof, and also to a flip-chip binding semiconductor integrated circuit employing the laser blowing fuse to prevent significant reliability reduction. The solution is to apply the circuit with programming unit such as anti-fuse in the flip-chip binding semiconductor integrated circuit. The composition of the programming unit is to form a predetermined potential in the current path so as to irreversibly convert the status of the current path from high impedance to low impedance, or from low impedance to high impedance; and, the input terminal for supplying the voltage to form the potential are pad electrodes.
Patent TW-448572-B (TW)
Title: High voltage device structure and the manufacturing method thereof
Inventor: YANG SHENG-SHIUNG
IPC: H01L27/115
Filed: 1999-12-29
Granted: 2001-08-01
Abstract: A high voltage device whose structure comprises: a gate structure on a substrate; a first well region of the first conductive type located in the substrate on one side of the gate structure; a shallow trench isolation located in the first well region; a first doped region of the second conductive type located in the first well region under the shallow trench isolation; a second doped region of the second conductive type located in the first well region under first doped region; and the second well region of the second conductive type located in the substrate on the other side of the gate structure; a third well region of the second conductive type located in the second well region in which the gate structure extends and covers part of the first well region, the second well region, the third well region and the shallow trench isolation. The source region of the first conductive type is located in the first well region exposed by the gate structure and the shallow trench isolation, and the drain region of the first conductive type is located in the third well region exposed from the gate structure.
Patent TW-430874-B (TW)
Title: Wafer fixing device used in an etcher
Inventor: KUO LI-YING
IPC: H01L21/02
Filed: 1999-12-29
Granted: 2001-04-21
Abstract: A wafer fixing device used in an etcher is provided to fix a semiconductor wafer. The etcher includes a hollow housing, and the wafer fixing device is installed in the hollow housing. The wafer fixing device includes a wafer seat installed at the bottom of the hollow housing. A suspension arm is elevatably installed on the upper portion of the hollow housing and disposed on the wafer seat. A wafer ring clamp is installed at the lower side of the suspension arm. The wafer ring clamp includes an exterior ring fixed on the lower side of the suspension arm, and an opening in the inner side. An interior ring is changeably fixed on the inner edge of the opening of the exterior ring. A round hole is defined in the inner side of the interior ring. The wafer seat has a first tilted face surrounding the edge of the upper side of wafer seat. A second tilted face is provided along the edge of the round hole at the lower side of the interior ring. When the semiconductor wafer is in etching, the suspension arm enables the wafer ring clamp to move downwardly, such that the second tilted face of the interior ring is interacted with the first tilted face of the wafer seat to clamp the semiconductor wafer. Thus, the etcher is able to etch the semiconductor wafer downwardly via the round hole of the interior ring.