Patent GB-1295099-A (GB)
IPC: G01R31/3193
Filed: 1969-10-17
Abstract: 1295099 Testing logic circuits HONEYWELL INFORMATION SYSTEMS ITALIA SpA 17 Oct 1969 [17 Oct 19681 51195/69 Heading G1U [Also in Divisions G4, H3] A system for testing digital type logic circuits comprises a reading device for reading information stored in a storage member identifying (a) the input and output terminals of the logic circuit to be tested, (b) a code pattern of input signals to be applied to that circuit, (c) the expected code pattern of output signals from the circuit when the said code pattern is applied thereto and is such that the reading device supplies signals in accordance with the input code pattern to the identified terminals of the circuit under test, via a suitable connector, and in accordance with the expected output code pattern to first inputs of a comparison circuit, which receives on second inputs signals from the output terminals of the circuit under test identified by the reading device. An indicating arrangement responsive to the comparison circuit compares the signals on the first and second inputs and indicates any discrepancy between their patterns. The input code patterns and expected code patterns are recorded in rows on a programme card SP, which may be an aluminium sheet, binary ones being represented by protuberances. Each particular row, corresponding to a particular input pattern and expected output, is read by a row of contacts CE. The circuit under test, e.g. an integrated circuit card, is connected to a connector CS having pins S. The pins S and contacts CE are connected to comparing circuits DC, each of the switch units CM being set in accordance with whether the related pin S is an input (I) or output (U) of the test circuit. The test for each programme pattern is initiated by operating the manual button ST of a timing device DT which controls the comparing devices DC, to accept and store the pattern being read from the card CE. The signals from output pins are fed to the comparing device while the signals to be applied to input pins are derived from the memory parts of the comparing devices and applied via the switches CM to the appropriate input pins. The outputs from the comparing devices are passed to evaluating circuits, which operate only following a delay relative to the initiation of a test, to enable the test circuit to reach a steady state condition. The evaluation circuits energise lamps LS if a discrepancy between the expected and actual outputs are obtained, and the actual pattern of illuminated lamps enables the particular type of fault to be determined. The circuit DP enables a preliminary test to be carried out on the operation of the system before a test card is introduced. The switches CM are initially set in accordance with a first programme sequence on the programme card with no circuit under test present. The switches CM are all set to output, so that binary ones appear on all lines from the pins S. The programme card indicates by binary O's those pins on a corresponding test circuit which should be inputs, and lamps corresponding to these pins will illuminate. When the corresponding switches are changed, the lamps are extinguished. Details of the timing and comparison circuits are given (see Division H3) and of the programme card reader (see Division G4).