Patent UA-93736-U (UA)
Title: driver of a SINGLE package WHICH CONTAINS THREE SYMMETRIC CODE pulse SERIES with programmable time parameters
Inventor: KOROBKOV MYKOLA HRYHOROVYCH
IPC: H03K3/78
Filed: 2014-05-19
Abstract: Driver of single package that contains three symmetrical code series of pulses with programmable timing parameters, multiples of the period of continuous periodic pulse sequence supplied to the input from the quartz oscillator output comprises: two reversible binary counters having of synchronization pulses, input for adjustment to summation / subtraction mode, input of permit of synchronous parallel loading and inputs of loading data, input of permit of count mode, input of asynchronous installation to zero state, the overflow output; first (four-input), second (three-input) and third (two-input) OR elements; two inverters; circuit of connected in series resistor and capacitor; synchronous D-flip-flop with input of asynchronous installation to zero state; first and second two-input AND gates; first and second OR elements; the common point of connected in series resistor and capacitor is connected to the data input of the first D-flip-flop, to one input of AND gates; output of first AND element is connected to the input of asynchronous installation of D-flip-flop to zero state; the clock input of D-flip-flop forms the input of start pulses; the second input of second AND element is connected to the output of the second OR gate, one input of this is connected to the D-flip-flop output; output of the second AND gate is connected to the inputs of asynchronous installation to zero state of counters; outputs of bits of the second counter are connected to the inputs of the first element OR; clock inputs of the counters are connected together to form the driver input - input of supply of continuous periodic pulse sequence from the output of external oscillator; parallel loading inputs of the first counter form driver inputs for adjustment to given parameters of output pulses. There are included: the first JK-flip-flop which has two inputs J, one of those is direct, the second inverted, and connected by AND, one inverted input and K and input of asynchronous installation to zero state; the second JK-flip-flop, which has two inputs K, one of those is direct, the second inverted, and connected by AND, one inverted input J and input of asynchronous installation to zero state; third reversible binary counter which has input of synchronization pulses, input of adjustment to addition / subtraction mode, input of permit of synchronous parallel loading and inputs of loading data, input of permit of count mode, input of asynchronous installation to zero state, the overflow output; fourth element OR; first and second two-input AND-NOT elements, wherein the overflow output of the third counter which forms the output of the driver is connected to its input of permit of synchronous parallel loading, input of the fourth OR gate, input of permit of the second counter count mode, and the input of the first inverter, its output is connected to the input of permit of the third counter counting mode, the second input of the first AND gate, and inputs of the first and second elements AND-NOT; output of the first OR gate is connected to the second input of the fourth OR gate and the input of the second inverter, output of this is connected to the first input of the third OR gate and the second input of the first AND-NOT element, its output is connected to the input of permit of the first counter counting mode; output of the fourth OR gate is connected to the second input of the second OR gate and the inverted J and K inputs of JK-flip-flops; inverted output of the first JK-flip-flop is connected to the direct input of the second JK-flip-flop; inverted output of the second JK-flip-flop is connected to the direct input K of the second JK-flip-flop; direct output of the second JK-flip-flop is connected to the third input of the second OR element; bit outputs of the second counter are connected to data inputs of the third counter; first counter overflow output is connected to the second input of the third OR gate and the second input of the second AND-NOT element; output of the third OR gate is connected to the input of adjustment to the summation / subtraction mode of the second counter; output of the second AND-NOT element is connected to the input of loading mode permit of the first counter; the clock inputs of the third counter and the JK-flip-flops are connected to the clock inputs of the first and second counters; inputs of asynchronous installation to zero state of JK-flip-flops and the third counter are connected to the outputs of the second element AND.