baber/WOPTO huggingface dataset:
Patent JP-H09232187-A (JP)
Title: Trimmer capacitor
Inventor: AKIHAMA RYOZO
IPC: H01G5/00
Filed: 1996-02-27
Abstract: PROBLEM TO BE SOLVED: To be excellent in setting precision, large in rotation torque and excellent in capacitance by a method wherein an undercut from an installment reference plane of a reverse face of a stator is within a specific dimension. SOLUTION: In a trimmer capacitor comprising: a stator provided with a fixed electrode; a rotor having a rotor electrode counter to a stator electrode via a dielectric; and a cap 1 for housing rotatably the rotor, an undercut from an installment reference plane of a reverse face of the stator is within 20μm. Further, in the thus-structured trimmer capacitor, the cap 1 has a structure capable of caulking fixedly the stator at three points and houses the rotor in a circular part 2 centering a substantially middle point of a triangle abc formed with three points a, b, c of middle points of a caulking fixing part. Thereby, it is possible to manufacture readily and at low price the trimmer capacitor excellent in stabilization of capacitance with reliability.
Patent JP-S57197659-A (JP)
Title: Data processing device
Inventor: KOMADA YASUTAKE
IPC: G06F9/312
Filed: 1981-05-29
Abstract: PURPOSE:To speed up the data processing, by fetching data to an internal data register with a data pickup device in the order requested by an operation processing device. CONSTITUTION:A memory data register 43 which reads out data in 11 units of memory interface bounder from a storage device 10 and stores it temporarily, is provided. Further, a merge register 44 storing the content of the register 43, a byte selector 45, a byte circular register 22, and a data pickup device 40 controlling the register 22 and the selector 45 according to the instruction from an operating processing device 20 are provided. The content of the storage device 10 is stored in an internal register 21 in the order in accordance with the instruction from the operating processing device 20.
Patent JP-H11280015-A (JP)
Title: Concrete type covered conduit
Inventor: KAWAHARA KEISUKE
IPC: E01C11/22
Filed: 1998-03-27
Abstract: PROBLEM TO BE SOLVED: To prevent generation of a slip accident of a vehicle by providing water collecting windows receiving flowing water from a road pavement surface at an upper part at one side of a covered conduit body having a flow water hole and at an upper part at the other side thereof. SOLUTION: A water collecting window holes 8A, 8B receiving flowing water from a road pavement surface 4 at an upper part at one side of a covered conduit body 1 having a flow water hole 2 and at an upper part of the other side thereof. Rain fallen on a road is turned into flow water W1 , W2 flowing toward the body 1. The water W1 flows in from the hole 8A facing an end 4a of the surface 4 and is collected, and then it is made to flow from the upstream side to the downstream side through the hole 2 of the body 1. The water W2 flows toward a top surface 1a of the block 1 and flows into the body 1 from the hole 8B through a cut-out slant surface part 7b, then it is combined with the water W1 and they are made to flow from the upstream side to the downstream side.  Accordingly, even if there is much rain, no road pavement surface is immersed with water, and thereby generation of a slip accident can be prevented.
Patent JP-H05281024-A (JP)
Title: Preamplifier integrated circuit for receiving light
IPC: H01L27/04
Filed: 1992-04-03
Abstract: PURPOSE:To provide a preamplifier integrated circuit for receiving light, which can easily evaluate the characteristics of an electric system and a light receiving system and is of high quality. CONSTITUTION:An integrated circuit 1 for evaluation and an integrated circuit 2 for package mounting are disposed adjacent to each other on a wafer 3 and manufactured to make both circuits of uniform characteristics. Or the power supply terminal 6 and input and output terminals 4, 5 of the integrated circuit 21 for evaluation are disposed and manufactured in such a manner as to conform with the tie-in positions of the respective terminals of the wafer probe 8 on evaluation side. The evaluation integrated circuit and the package mounting integrated circuit are manufactured in such a manner as to have the same circuit configuration and different constants to be stabilized for a wafer for evaluating the electric system. In order to easily evaluate the electric system, the circuit constant of the evaluation integrated circuit is set to attain impedance matching with that of the evaluation wafer to manufacture the circuits.
Patent JP-H08278114-A (JP)
Title: Surface contour measuring method and surface contour measuring instrument
Inventor: SUZUKI MASANORI
IPC: G01B11/14
Filed: 1995-04-07
Abstract: PURPOSE: To measure a surface contour in a non-contact state and with high accuracy. CONSTITUTION: An acoustic optical element 8 causes the frequency shift of double-channel light. Also, a reduction optical system 18 throttles the beam shape of another double-channel light for causing the light to be made incident on a wafer 20. Furthermore, a beam splitter 11 causes the light after the frequency shift and reflected light from the wafer 20 to interfere with each other in the form of optical heterodyne interference, and a polarized beam splitter 12 separates the light into two interference beams having a different polarized plane. Thus, a photoelectric detector 15 finds the first and second beat signals on the basis of the first interference beam, while another photoelectric detector 16 finds the third and fourth beat signals on the basis of the second interference beam.  A control section 17 calculates a step formed on the wafer 20 on the basis of the phase differences of the first and third beat signals, and the second and fourth beat signals.
Patent JP-H09272309-A (JP)
Title: Pneumatic radial tire
Inventor: DOBASHI KENSUKE
IPC: B60C3/00
Filed: 1996-04-04
Abstract: PROBLEM TO BE SOLVED: To prevent generation of the buckling phenomenon of cords forming a carcass ply which is apt to be generated at manufacturing a tire having a special carcass line, and provide high motional performance and stable operational stability. SOLUTION: In this pneumatic tire in which it is a recessed form toward the tire inside at about 2/3 height of the tire at charging inner pressure of 0.2kg/cm<2> , and it is a projecting form toward the outside at charging inner pressure of 2.0kg/cm<2> , the cords of a carcass ply are formed out of polyethyleneterephtalate of which thermal shrinkage factor is not less than 0.7% or less at 177 deg.C and under 0.10g/D, and thermal shrinkage factor is not less than 2% at 177 deg.C and 0.03g/D. After completing the vulcanizing process, a post-cure inflation process is performed by the charging inner pressure of 70-150% of the regular service inner pressure of the tire.
Patent JP-S58200531-A (JP)
Title: Manufacture of semiconductor device
Inventor: HOUGEN HIROSHI
IPC: H01L21/28
Filed: 1982-05-18
Abstract: PURPOSE:To decrease the line width of an electrode wiring pattern, and to increase the degree of integration of an element by selectively forming an oxidation-resistant layer to the surface of a metallic layer and thermally treating the oxidation-resistant layer, converting the metallic layer into a silicon compound and oxidizing, evaporating and removing the metallic layer not coated with the oxidation-resistant layer. CONSTITUTION:A contact hole is formed, and the surface is coated with a molybdenum film 19. Molybdenum is changed into molybdenum oxide through thermal oxidation, but molybdenum oxide sublimes. Molybdenum being in contact with a silicon film reacts with silicon at a temperature of approximately 500 deg.C or more to form a molybdenum silicide, but an oxide film is formed to the surface even through thermal oxidation in the molybdenum silicide, and the molybdenum silicide does not change. Accordingly, when a structure is treated at a high temperature in an oxygen atmosphere, molybdenum and silicon react in the bottom of the contact hole 15, and the molybdenum silicide 22 is formed. The molybdenum film 19 coated with a silicon nitride film 20 is not oxidized, while the molybdenum not coated with the silicon nitride film 20 is oxidized and evaporates.
Patent JP-S60226220-A (JP)
Title: Fm muting circuit
Inventor: YASUI HIROSHI
IPC: H03G3/34
Filed: 1984-04-23
Abstract: PURPOSE:To make a noise level of an FM detection circuit output constant independently of an output level of an intermediate frequency amplifier by applying muting depending on the level of a high frequency noise component. CONSTITUTION:The high frequency noise component from an FM detection circuit output signal is detected by a high pass filter 7, the output of which controls a muting control signal generating means 8 comprising capacitors C1, C2 converting the output of the high pass filter, diodes D1, D2 and resistors R1, R2 dividing a DC and the result is impressed to a base of a transitor (TR). A muting control signal is impressed to the base of the TR depending on the level of the noise component.
Patent JP-H03283090-A (JP)
Title: Semiconductor storage device
Inventor: SHINKAI EIJI
IPC: G11C11/409
Filed: 1990-03-29
Abstract: PURPOSE:To accelerate signal transmission by alternately arranging respective signal lines based on plural address signals as signal lines adjacent to the respective I/O bus lines of plural I/O bus lines. CONSTITUTION:As the signal lines adjacent to each I/O bus line in plural I/O bus lines 1-8, signal lines 9-16 are alternately arranged based on each address signal in the signal lines based on the plural address signals. Since these signal lines 9-16 are set to a fixed potential based on the adjacent address signals in a period when the I/O bus lines 1-8 are changed from a high level to a low level or from the low level to the high level, only charging or discharging is exerted upon a capacitor between wirings. Therefore, the time is shortened for changing the data of the I/O bus lines 1-8 from the high level to the low level or from the low level to the high level. Thus, the signal transmission can be accelerated.
Patent JP-H02260067-A (JP)
Title: Transmission processing system for executing instruction of image registering process
Inventor: SAKATA TOMOMI
IPC: G06T1/00
Filed: 1989-03-31
Abstract: PURPOSE:To simplify the operation of the subject processing system by scheduling the transfer of a specification drawing file to be registered in a data transmission form, transferring automatically the subject file when the file transfer process is started and carrying out an image registering process. CONSTITUTION:In an image registering process executing instruction transmission program, the corresponding register subject specification drawing file is allocated by a register subject specification drawing allocation means 21 so that the transmission program works on a CPU 2. A register subject specification drawing reading means 22 edits the information on the drawing file in a designated format during execution of the transmission program. Then the information on the drawing file is sent to an external storage 5 as the data via a register subject specification drawing information transmission means 23. This transmission is continued until a register subject specification drawing information transmission end recognizing means 24 recognizes the end of transfer of the file information on the CPU 2. When the transmission of data is through, the CPU 2 sends the next image registering process executing instruction to an image processor 3.
Patent JP-S61240499-A (JP)
Title: Nonvolatile semiconductor memory
Inventor: IWAHASHI HIROSHI
IPC: G11C17/00
Filed: 1985-04-18
Abstract: PURPOSE:To suppress power consumption of the address decoder circuit to low level by minimizing the potential difference between the source-gate of the transistor for loading address decoder circuit at the time of data programming. CONSTITUTION:At the time of reading data, high voltage VP and ordinary voltage VC is impressed on power source terminal 1 of the gate potential switching circuit 10 according to the data programming, and '1', '0' level is applied on the input node 12 mutually connected between the gates of transistors T6, T7. At the time of reading data, grounding potential is applied on the gate of the transistor T1 for loading the address decoder circuit from the output node 11. At the time of data programming an electric potential (VP-VTH5) higher than the grounding potential is applied and the potential difference between the source-gate of the transistor T1 for load use becomes VTH5 which is smaller than usual. The VTH5 herein is the threshold voltage of the transistor T5.
Patent JP-H11284746-A (JP)
Title: Telephone reception management system and its method
Inventor: HASEGAWA MITSUKI
IPC: G06F3/0487
Filed: 1998-03-30
Abstract: PROBLEM TO BE SOLVED: To provide a telephone reception management system by which an instruction from a manager is delivered in good timing without interrupting reception of phone calls and reception of customers by an agent is improved. SOLUTION: A speech monitor section 4 stores received information from a customer for each extension telephone set 13, a PBX function section 3 references the speech monitor section 4 to connect an external line phone call to an idle extension telephone set 13. A received information display section 26 reads all received information and displays it on a display 22, and a speech content display section 28 displays a speech content shown on a display 14 of an agent having received information desired to be monitored among all the received information sets onto the display 22, and a manager side instruction text processing section 25 sends an instruction to agent terminal equipment 19 of the agent having the received information desired to be monitored. An instruction information display 18 displays the sent instruction on part of the screen of the display 14.
Patent JP-H05246004-A (JP)
Title: Guiding method and guiding device of web
Inventor: NISHIWAKI NOBUHIKO
IPC: B41F13/06
Filed: 1992-03-05
Abstract: PURPOSE:To contrive a reliable guide and reduction of friction of a web, by a method wherein the web generating a progressive oscillation and performing running is brought into contact with the surface of an oscillating member provided on a guide device of the web and deterioration of working environment by a blow-off of air and complication in the working are eliminated. CONSTITUTION:When alternate current voltage 17, 18 are applied to electrode groups 13, 14 by an electric circuit 16, a piezoelectric element 12 is extended and shrunken partly and a standing wave 51 corresponding to the voltage 17 and a standing wave 52 corresponding to the voltage 18 are generated on an oscillation member 11. Consequently, the standing waves 51, 52 are joined together and a progressive wave 53 of an arrow direction is generated on the member 11. A cross point of a perpendicular line DE of the member 11 with a guide surface 11a, that is, an arbitrary point E on the surface 11a is displaced by an oval locus of left turn like E1 E2 E3 E4 E1. In other words, the tops of the progressive wave 53 of the surface are all displaced in the direction opposite to an advancing direction of the progressive wave 53. Then when the web W is brought into contact with the guide surface 11a, since force of the opposite direction to the progressive wave 53 is applied to the web W, the web W is moved in an arrow F direction, that is in the running direction of the web W and guided positively.
Patent JP-H07290663-A (JP)
Title: Biaxially orientated polyester film
Inventor: ABE KOICHI
IPC: B32B27/36
Filed: 1994-04-21
Abstract: PURPOSE:To obtain a polyester film in which generation of powder due to scraping of a surface scarcely occurs even if the film is fed at a high speed. CONSTITUTION:A biaxially orientated film is obtained by laminating polyester composition containing particles at least on one side surface of polyester composition in such a manner that t/d of a ratio of a thickness (t) of a laminated part to a mean particle size (d) of a particle is 0.1-10, a surface protrusion interval P on a surface is 0.1-50mum and a product P.PHI<1/2> of a root PHI<1/2> of an index of number of particles contained in the laminated part is in a range of 0 to 50.
Patent JP-H03283856-A (JP)
Title: Multifunctional telephone set with telephone directory function
Inventor: ONAKA TOSHIYUKI
IPC: H04M1/57
Filed: 1990-03-30
Abstract: PURPOSE:To easily perform the registration work of a new opposite party by providing a profile storage part which stores user information including the name, the company name, and the telephone number of a user, and a telephone directory storage part which stores the content of opposite information received with a multifrequency signal reception part as telephone directory data. CONSTITUTION:When a callee A registers the information of a caller B, profile data such as the name, the company name, and the telephone number of the caller B is registered in a profile storage part 8 in advance by a key switch 2 in a multifunctional telephone set at a caller B side, and a main control part 3 at the caller B side sends out the profile data from the profile storage part 8 to a telephone line as an MF signal via an MF signal sending part 10 and a network control part 5. Meanwhile, a main control part at the multifunctional telephone set at a callee A side receiving the MF signal from the caller B via the telephone line 20 receives the opposite profile data of the caller B via an MF signal reception part 9, and accumulates it in the telephone directory storage part 7. Thereby, it is possible to easily perform the registration work of the nev opponent.
Patent JP-H04294653-A (JP)
Title: Ring line concentrator
Inventor: NAKAGAWA KAZUTAKA
IPC: H04Q3/60
Filed: 1991-03-22
Abstract: PURPOSE:To detect a fault of a transmission line due to a DC current by circulating the DC current to a ring transmission line independently of the presence of connection of a station to the ring transmission line via the ring line concentrator in a ring network system. CONSTITUTION:A DC bypass circuit 5 is added between In and OUT signal transformers 3,4 of a ring line concentrator 1. A transmission signal in the transmission signal and a DC current coming from a transmission line IN side 20-1 passes through a relay circuit 2-2 as it is and is sent to a station via the IN side signal transformer 3, and the DC current flows to a DC bypass circuit 5 and sent to a transmission line OUT side 20-2 via the OUT side signal transformer 4 and a relay circuit 2-1.
Patent JP-H09282470-A (JP)
Title: Graphic processing system
Inventor: ONO MAKOTO
IPC: G06T15/04
Filed: 1996-04-05
Abstract: PROBLEM TO BE SOLVED: To allow each node processor of a geometry subsystem to operate without considering memory resources on the side of a raster subsystem by providing a texture memory and a texture memory managing means. SOLUTION: A merge processor 30 includes a texture list 30-1 for managing the contents of a texture memory 45 being the memory resource of a raster subsystem. When texture ID designated by a texture command outputted by each geometry node processor 20 is absent, the merge processor 30 issues an interruption request to a resource managing unit 35. The resource managing unit 35 downloads texture data corresponding to texture ID designated by the request to the texture memory 45. Texture memory is downloaded without regard to geometry processing.
Patent JP-H09271909-A (JP)
Title: Cooling base board for producing quenched metal thin strip
Inventor: YAMADA TOSHIO
IPC: B22D11/06
Filed: 1996-04-05
Abstract: PROBLEM TO BE SOLVED: To prevent generation of air pocket and to uniformize and improve magnetic characteristic and mechanical characteristic of a metal thin strip by forming V-shaped grooves on the surface of a cooling base board (roll) used for producing the metal thin strip. SOLUTION: V-shaped grooves are formed on the surface of the moving cooling base board and constituted so as to direct the closed direction of these grooves to the moving direction (the arrow mark) of the cooling base board. By this constitution, atmospheric gas entrapped between molten metal and the cooling base board is efficiently ejected to the side direction of a paddle and the generation of the air pocket is prevented and cooling speed of the thin strip can be quickened.  In this case, the angle θ of the V-shaped grooves is >0 deg. to <90 deg. angle to the upstream direction, desirably 20-70 deg. by using the moving axis of the cooling base board as a reference. further, the V grooves can be arranged at the different angle in the right and left sides, such as the figure (b), to the shifting axis of the cooling base board passing the closed part, but in this case, the difference of the θs at the right and the left sides is within ±10 deg. to stabilize the paddle.
Patent JP-H0959733-A (JP)
Title: Hydrogen storage alloy
Inventor: KAKEHASHI SHINICHIRO
IPC: C22C19/00
Filed: 1996-04-05
Abstract: PROBLEM TO BE SOLVED: To utilize the catalysis of La(Ce)-Ni alloy phases in a formed structure and to improve hydrogen-absorbing and hydrogen-releasing velocities and initial activity characteristic by specifying the composition of a cast Zr-Ni-Mn alloy and also controlling its structure. SOLUTION: This alloy has a composition consisting of, by weight ratio, 25-45% Zn, 1-12% Ti, 10-20% Mn, 2-12% V, 0.6-5% La and/or Ce, and the balance >=25% Ni with inevitable impurities. Simultaneously, the cast structure of the alloy is controlled so that lumpy La(Ce)-Ni alloy phases are dispersedly distributed along the crystalline grain boundaries of Zn-Ni-Mn alloy phases forming a matrix, and further, lamellar Ni-Zr alloy phases are discontinuously distributed, in the state adjacent to the above phases, along the crystalline grain boundaries of the Zr-Ni-Mn alloy phases as a matrix. Moreover, this alloy is used after being subjected to melting in an Ar atmosphere, to casting in a water cooled copper mold, and then to ordinary hydrogenation crushing or to mechanical crushing into crushed grains.
Patent JP-H05299618-A (JP)
Title: Cmos type gate array lsi
Inventor: YAMAZAKI HIROETSU
IPC: H01L27/118
Filed: 1992-04-07
Abstract: PURPOSE:To prevent the generation of the difference of the transmission time while effectively utilizing input-output blocks by using a gate for an output having large driving capacity when a signal from the outside of an LSI is transmitted over a logic circuit. CONSTITUTION:Output from the gates 14 for inputs of input-output blocks 13 are connected to inputs to gates 15 for outputs, and outputs from the gates 15 for the outputs are connected to a plurality of logic circuits in an LSI.
Patent JP-S60227516-A (JP)
Title: Semiconductor integrated circuit
Inventor: ITOU TOORU
IPC: H01L27/092
Filed: 1984-04-25
Abstract: PURPOSE:To suppress the drop of the output voltage of an output circuit to improve the output characteristic of the circuit, by suppressing the occurrence of abnormal operation phenomena caused by the impact from the outside by means of a CMOSIC. CONSTITUTION:nMOS transistors (TR)305 and 306 are respectively installed to the P-wells 307 and 208 of a semiconductor integrated circuit and the TRs 305 and 306 are connected to an output terminal 304 and, at the same time, the TRs 305 and 306 are connected between a positive voltage supplying line 301 and negative voltage supplying line 302. Moreover, dummy-like inverters respectively composed of nMOS TRs 310 and 311 are respectively installed to P-wells 312 and 313 and the TRs 310 and 311 are connected to the voltage supplying lines 301 and 302. Outputs of the dummy-like inverters are connected with the P-well 307 containing the TR305 for pulling up an output circuit. Furthermore, a signal supplying point 303 to the output circuit is connected with the TR310 through a CMOS inverter 309 together with the TR313. Thus the occurrence of abnormal operation phenomena caused by impacts from the outside is prevented and drop in the output voltage of the output circuit is suppressed.