Patent GB-1108800-A (GB)
Title: Improvements in or relating to electronic data processing machines
Inventor: AMDAHL GENE MYRON
IPC: G06F3/00
Filed: 1965-03-31
Abstract: 1,108,800. Electric digital calculators and data-storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. 31 March, 1965 [6 April, 1964], No. 13606/65. Headings G4A and G4C. In a data processor, variable-format macroinstructions read from a main memory into selected registers control accessing of a microprogramme read-only store. Data representations-The machine can handle: (a) Fixed-point numbers which are signed binary numbers of one of two lengths. (b) Floating-point numbers (signed) consisting of a " fraction " field of single or double precision length containing binary-coded hexadecimal digits, the fraction field being considered multiplied by 16 raised to the power of a number given in a 7-bit " characteristic " field. (c) Decimal numbers containing a variable number of binary-coded decimal digits, the code 1101 being used to indicate " minus " and the other unused four-bit codes to indicate " plus." Two BCD digits occupy an 8-bit byte in the so-called packed format, or the byte contains one digit plus zone bits in the unpacked (or zoned) format. (d) Logical information in various length fields. Macro-instruction format.-(Figs. 21-25, not shown). Each macro-instruction contains besides an operation code, either (a) the addresses of two operands (RR), or (b) the address of one operand, and two fields which when added give the address of a register containing a number to be added to another field in the instruction to give a second operand address (RX), or (c) two operand addresses and a field to be added to the contents of a register specified by another field in the instruction to give a third operand address (RS), or (d) fields specifying the lengths of two operands, the addresses of two registers and two numbers which when added to the contents of the registers respectively give the addresses of the left-most bytes of the two operands (SS), or (e) one operand (directly) and the address of a register the contents of which are to be added to those of another field in the instruction to get the address of a single-byte second operand (SI). The formats used for different types of operations are as follows: floating-point (RR, RX), fixed-point (RR, RX, RS), decimal (SS), logical (RR, RX, RS, RI, SS). In all macro-instructions, the first two bits of the operation code portion specify the instruction format and length. Programme status words (Fig. 27a, not shown).-One of these words partially controls machine operation at any one time. When operation is interrupted (e.g. for I/O servicing), the current programme status word (PSW) is stored and another is introduced. The PSW has fields to specify: (a) which possible sources of interruption are permitted to cause interruption, (b) storage protection key, (c) whether detection of a machine malfunction is to result in interruption, and execution of diagnostic procedures, (d) whether the CPU is running or waiting, (e) whether the CPU is executing a problem programme or a monitor programme, (f) cause of interruption, (g) length of last instruction executed, (h) condition code, (i) which of four events are to result in interruption, the events being fixed-point overflow, decimal overflow, exponent overflow, and " significance " (i.e. the occurrence of an allzero fraction in the result of a floating-point addition or subtraction), (j) address of next macro-instruction. Possible sources of interruption.-(a) Request for I/O operation. (b) Programme interruption due to programme error. (c) Monitor call. (d) External, e.g. when a timer value is decremented beyond zero, when an operator presses a button or when an external unit (e.g. another CPU) signals on any one of six lines provided. (e) Detection of machine malfunction. A predetermined priority order is provided for simultaneous interrupt attempts. If the storage protection feature is not provided in the computer, detection of a non-zero protection key in the PSW causes an immediate interruption. Manual controls.-These include: (a) A rate switch determining whether the machine will operate continuously on being started, or perfoim one macro-instruction and then stop until restarted. (b) Address keys to address a storage location within a storage area selected by a storage selection switch. (c) Data keys for specifying data to be stored in an addressed location, (d) A button to cause display of information in an addressed location. (e) Address compare switches to set an address on recognition of which the CPU will stop. Read-only storage.-(Figs. 4am, 45a-45c, 46a-46d, not shown).-Two decoders select a driver transistor by signals applied to the base and emitter terminals respectively to read out two words in a capacitive read-only store to sense-amplifiers, the outputs of half the amplifiers being stored in latches under control of a further address bit. By this scheme the number of drivers is halved by doubling the number of amplifiers. Alternatively, each driver may read out four words, the number of amplifiers being twice as large again, and so on. Arithmetic and logic unit and checking. (Figs. 35a-35i, not shown).-The ALU can perform addition or subtraction (binary or decimal) or AND, OR, EXCLUSIVE-OR functions, depending on control signals. Operations are done on the normal and inverted forms of the operands and the results compared to give an error indication if inconsistent. Multiplication.-Binary multiplication is done utilizing tables in which the multiplier is stored in both single and doubled form. Decimal multiplication is done by an algorithm involving successive subtractions followed by multiplicand end digit testing operations and shift of multiplier. Division.-Binary division is by repeated addition or subtraction operations of the divisor to/from the dividend, each followed by shift of the dividend, whether the addition or subtraction operation is used at any time depending on the sign of the result of the last operation. Decimal division is done by repeated subtraction. Other features.-The Specification describes a complete micro-programme-controlled computer in considerable detail, including for instance a complete dictionary of micro-instruction words, and micro-programmes for representative macroinstructions. Also described are details of control of input/output (I/O) operations, editing, branching, memory protection and other features, which are, however, the subject of separate patents.