Patent GB-1136399-A (GB)
Title: Data processor
Inventor: MUIR DAVID
IPC: G11C19/00
Filed: 1965-12-20
Abstract: 1,136,399. Shift circuit in a data processor. WESTERN ELECTRIC CO. Inc. 20 Dec., 1965 [23 Dec., 1964], No. 53883/65. Addition to 1,136,246. Heading G4C. A unidirection rotate circuit is described allowing both left and right shifts and rotates on a data word to be effected while the word is being transferred within a data processing arrangement. A relay circuit and an electronic circuit incorporating transistor gates are described for use with a twenty bit word. Sets of nodes A receive the appropriate bits of a word from a memory or register. Sets of nodes B, C, D, E, F then receive the bits either shifted or rotated 1, 2, 4, 8, or 16 stages to their right respectively or retained in the same stage. A circuit (Fig. 9, not shown) receives an instruction word and enters the magnitude of a shift on lines (X1, X2, X4, X8, X16) for right shifts and rotates and complements the number for left shifts and rotates. In the electronic circuit (Figs. 11-16, not shown) gates connect the nodes, each node being connected to the output of two gates and to the input of two further gates, one of each pair allowing a rotate to or from the right, the other allowing a move to or from another node in the same bit position. On a right shift operation certain of the gates are inhibited if the shift would move the appropriate bits from the least significant bit position, bit 0 to the most significant position. Using transistor NAND gates, having an inverting action the disablement of gates having inputs from nodes A,C,E, is obtained by providing inputs #HR which is 0 only for right shifts to the gates providing the unrequired right shifts i.e. the diagonal gates having inputs from nodes OA, 0C-3C, 0E-15E, since a zero input causes the output of the gate to be high and thus write a "0" in the next stage. Due to the inverting action of the gates this procedure cannot be applied to gates having inputs from nodes B, D so it is arranged that the appropriate inputs to these gates are zero, if the bit to be written there would be shifted out of the right hand end of the circuit. This is done by inhibiting the gates feeding e.g. nodes 0B 1B by applying an input Z18 which normally enables the gates but inhibits them to write "0"s during right shifts when X2 = 1 for the gates connected to OB, 1B or when X8 = 1 for the gates connected to 0D- 7D. To enable left shifts to be performed, the shift number is complemented with respect to the number 20 and then rotated right but the numbers which do not leave the right hand end of the circuit have to be rewritten as zeroes. This is done in a similar manner to that carried out for right shifts by inhibiting the appropriate gates. For instance the gates joining nodes 0E-4E to nodes 0F to 4F can be inhibited by applying to their inputs HL which is "0" only if a left shift operation is taking place. This causes an 0 to be effectively written in nodes 0F to 4F. Similarly the gate joining 16C-16D can be unconditionally inhibited by input HL. However the gates joining 13C-15C to 13D- 15D must be conditionally inhibited by a signal (Z15, Fig. 10, not shown), which inhibits during a left shift only when X16 = 0. As in the right shift case the inhibiting signals cannot be applied to the gates joining nodes B to C or D to E but must cause the inputs to nodes B and D to write zero in the appropriate stages. The relay circuit (Figs. 4-7, not shown) is constructed in a tree like form with the X1, #X1 . . . X16, #X16 signals operating relays to determine whether the data bits follow the diagonal or vertical paths (see Fig. 3), the unconditional #HR, #HL signals operating relays rendering nonconductive the appropriate paths and relays operating paths in parallel with the #HL signals for the conditional cases where the transmission depends on the presence or absence of an X4, X8, or X16 signal. In this case, since there are no inverting units all the appropriate relays can be inhibited.