Patent GB-1511401-A (GB)
Title: Electronic timepieces
IPC: G04G5/00
Filed: 1976-04-29
Abstract: 1511401 Electronic timepieces DAINI SEIKOSHA K K 29 April 1976 [1 May 1975] 17546/76 Heading G3T [Also in Division H4]  An electronic timepiece e.g. a watch, has an electro-optical matrix indicator with two sets of mutually perpendicular electrodes, and circuitry to produce a T.V. picture and time of day display, selectively on the said indicator. The display indicator may comprise liquid crystal P.L.Z.T., or electro-chromic materials between the electrodes or LEDS, or a magnetic bubble domain element. Common to both systems is a horizontal driving circuit 26, Fig. 3 which produces a voltage to drive the X electrodes (X 1  to X 100 ), Fig. 2 (not shown) via a ring counter 27, a switch circuit 24, and a vertical driving circuit 25 which produces voltages to drive the Y electrodes (Y 1  to Y 100 ). A selecting switch button (3), Fig. 1 (not shown) is coupled to switches S1, S2, S3 to select the display mode, the positions depicted calling for T.V. signal display. Other button switches, not illustrated, are provided for setting and broadcast frequency selection. TIMEKEEPING SYSTEM A crystal (e.g. thickness shear type) controlled oscillator 28 is followed by a frequency divider 29 to produce a 1HZ timing signal which is applied to a timekeeping counter system 30. A transducer 31 converts the content of counter system 30 to a suitable coded signal which is converted into a series of signals by a transducer 32 for application to the Y electrodes, via, switching circuit 24 and drive circuit 25, under the control of the Q2 output of a counter 34. The latter produces a pulse each time it counts 100 pulses from a 3HZ signal derived by a variable divider 33. The 3HZ signal also clocks the serial transducer 32 and the ring counter 27 coupled to the X electrodes, and synchronism of the driving of X and Y electrodes is obtained. The ring counter 27 is in two parts; one part drives the odd numbered electrodes X 1 , X 3  &c. sequentially and then the counter 27 is reset by a pulse from output Q 1  from counter 34 whereupon the even numbered electrodes X 2 , X 4  &c. are driven sequentially. A pulse from Q 1  occurs each time counter 34 counts 50 pulses at 3HZ. In the embodiment described liquid crystal material at the junction points of energized electrodes, is activated to indicate the time. VIDEO SYSTEM The T.V. display is used particularly to display a broadcast visual time check. A frequency converter 9 produces an intermediate frequency from a received radio frequency vision signal by means of an oscillator and mixer (not shown). A detector 11 detects the output of i,f amplifer 10 and produces an output which is separated into vertical and horizontal synch. signals by a synch. separator 12. The separator output is integrated at 13 and differentiated at 14 and wave shapers 15 respectively produce vertical and horizontal synch. pulse. signals. A comparator 17 compares the video signal level with a reference level slightly higher than white level, from a source (not shown) and divides the video signal into white and black level signals giving a "0" output in response to black and a "1" in response to white. A 5-stage ring counter 18 is stepped by the horizontal synch. pulses at C and is reset at each vertical synch. pulse. An oscillator 19 having an output of 1.87 MHZ, produces a number of pulses corresponding to the number of Y electrodes during the effective scanning period of 53À5Ásec. A gate circuit 20 passes the oscillator output to clock a shift register 22, each time it is opened by a "1" signal from output a2 of ring counter 18. Thus 120 clockpulses are passed during each period of the horizontal synch. pulses, the register having 120 bit capacity. The video signal from the comparator is written into terminal D of the register and corresponds to one effective scanning line, taking up 100 bits while the fly-back signal is written into the rest of the register. S.R.22 is cleared by a reset signal from output a 5  of the ring counter 18. The first 100 bit content of the register is written into a memory 23 which is clocked by the output a 4  of the ring counter 18 and at each clock signal memorizes the video signal fed in. The stored video signal is fed via the switch circuit 24 and drive circuit 25 to drive the Y electrodes. The ring counter 18 output a 4  also clocks the ring counter 27, both counters being reset by the output of shaper 15, and counter 27 feeds the X electrodes. A lamp or luminous diode may be used to illuminate the liquid crystal display.