Patent GB-1485578-A (GB)
Title: Apparatus for providing a regulated output potential in an mos-ccd memory
IPC: G11C19/28
Filed: 1975-10-14
Abstract: 1485578 Regulating the output voltage of an MOS-CCD shift register memory INTEL CORP 14 Oct 1975 [27 Dec 1974] 42034/75 Heading G4C Apparatus for providing a regulated output potential Vp, Fig. 1, in an MOS-CCD memory (not shown) which includes a plurality of' charge-coupled memory shift registers for storing information, comprises pulse suuply means 10, 13 and a dummy charge-coupled shift register 14, 16 for generating a register reference output signal on a line 19, a dummy sensor 18 having an output on a line 21 and an input sensing the register reference output signal on line 19, regulating means 22, 23, 25, 28, 29 controlled by the output of sensor 18 for providing the regulated output potential Vp on a line 30, and feedback means for feeding back on a line 31 at least a portion of the regulated output potential Vp to the sensor 18, whereby the potential Vp may be used in the sensing of information on an output line 24, Fig. 2, of the memory. Such apparatus is used to compensate the output voltage of an MOS-CCD memory for variations due to manufacturing tolerances or the effects of high temperature and/or low operating frequency. The apparatus together with the memory may be fabricated on a single silicon substrate, and the memory may comprise sixty-four 256-bit shift registers utilizing fourphase clock pulses. The channels 14, 16 of the dummy charge-coupled shift register may have the same general geometry as those of the storage shift registers, each storage shift register including four channels in contrast to the two channels 14, 16 of the dummy charge-coupled shift register. Inputs of binary "0"s and "1"s to the respective channels 14, 16 from pulse supply means 10, 13 occur at the same rate as information is supplied to the memory, a mixing channel 15 interconnecting the channels 14, 16 and causing their outputs to assume values approximately midway between those representing binary "0" and binary "1". Detailed circuit diagrams of the channels 14, 16, the sensor 18 and the pulse supply means 10, 13 are given in Fig. 3 (not shown). The regulating means may comprise respective fixed and variable current sources 22, 25, variable current source 25 being controlled by the signal on line 21; each of the current sources may comprise one stage of an MOS-CCD shift register, Fig. 4 (not shown). As shown, current sources 22, 25 feed the line 30 via an output transistor 29, but in a modification the line 21 is connected directly to transistor 29, the current sources 22, 25 being omitted. The channel 16 may be omitted in a further modification. The potential Vp is used to precharge the line 24 and hence to adjust the output voltage remaining thereon. The potential Vp is adjusted as a function of the outputs of the dummy shift register channels 14, 16 so that the final potential remaining on the gate of an output transistor (45) of the apparatus is close to the threshold of transistor (45). Thus a sensor transistor 34 will conduct when a "0" is sensed on line 24 and will not conduct when a "1" is sensed on line 24. Should the charge shifted along channels 14, 16 diminish for some reason, the charge shifted along the storage shift registers will also diminish, but the potential on line 24 will be compensated by a decrease in the regulated output potential Vp. The converse will happen should the charge shifted along channels 14, 16 increase. The signal on the sensor output line (Fig. 2) may feed an output detector of the memory or a refreshing amplifier thereof.