Patent GB-1132168-A (GB)
Title: Data processing apparatus
IPC: G06F7/52
Filed: 1967-09-04
Abstract: 1,132,168. Division apparatus. INTERNATIONAL BUSINESS MACHINES CORP. 4 Sept., 1967 [29 Sept., 1966], No. 40315/67. Heading G4A. Apparatus performing division by a series of binary reduction operations includes means for correcting the quotient when a zero remainder occurs with a negative dividend. The divisor and dividend are binary numbers with a sign bit which is 1 for negative and 0 for positive, negative numbers being in twoscomplement form and the dividend being twice as long as the divisor. The divisor is placed in the A register and the dividend in the B and BX registers (a half in each). The sign of the quotient is determined from the signs of the divisor and dividend. A counter counts down the iterations. During a first iteration, if the quotient is positive the divisor is complemented by inverting each bit in the A register and applying a low order 1 carry-in to carry-lookahead unit CLA and whatever the quotient sign the following operations then occur: the contents of the B register are repeated in the C register, the contents of the A register are applied via the funnel to the B and C registers, each of which develops the exclusive-or of the input bits with the corresponding bits already stored therein to form the half-sum of the divisor (complemented or not) and the high order part of the dividend in both the B and C registers, and the CLA develops carries in response to the A and C registers, its output being applied to the B register via the funnel to form a final sum. If there was a high-order carry out 1 from the CLA, indicating a positive result, this indicates that the quotient cannot be expressed in the same number of bits as used for the divisor, but otherwise further iterations follow as below, preceded by a one-bit shift to the left of the B and BX registers so that the highestorder bit in the BX register is transferred into the B register (low order end). This shift also occurs after every subsequent iteration except the last. In each of these further iterations, a 1 is inserted in the low-order end of the BX register as a quotient bit if the high-order carry-out from CLA is 1 in the case of positive dividend or 0 in the case of negative dividend. The divisor is complemented for the next iteration if the high-order carry-out from CLA is 1 in the case of positive divisor or 0 in the case of negative divisor. If the B register ever holds all zeros, a zero detector sets a " possible zero remainder " latch RZR LCH, this latch being reset by any 1 remainder bit appearing in the highest order stage of the BX register. If the latched RZR LCH is set after the whole dividend has been dealt with and the dividend is negative, the B register is reset and a loworder 1 is added into the quotient using the CLA unit. However, this latter addition is not done if the quotient is negative (see below). If the quotient is negative, it is finally complemented by interchanging the contents of the B and BX registers, resetting the A register to zero, repeating the contents of B in C, inverting each bit of the B and C registers (by gating an all-ones field to both), applying a low-order 1 carry-in to the CLA (except in the case of zero remainder and negative dividend), then gating the CLA through the funnel to the B register, producing the final quotient in B and leaving the remainder in BX. Thus a low-order 1 carry-in is applied to the CLA if the final quotient has to be put in complement form because it is negative, or if the conjunction of zero remainder and negative dividend requires a correction to the quotient, but not if both situations exist since then the effects of the two ones would cancel out. The division above is of the non-restoring type but the invention is also applicable to restoring division.