Patent GB-683765-A (GB)
Title: Improvements in and relating to calculating apparatus
IPC: G06F7/52
Filed: 1949-03-24
Abstract: 683,765. Digital electric calculating-apparatus. BRITISH TABULATING MACHINE CO. Ltd., HILL, W., WOODS-, and DAVIS, D. T. March 7, 1950 [March 24, 1949], No. 8053/49. Class 106 (i). In an electronic divider comprising divisor, dividend and quotient counters 2, 1, 5, Fig. 1, and a pulse emitter 7, the divisor is first repeatedly doubled until numerically greater than a predetermined value not less than the dividend and the divisor value is then repeatedly halved, compared with the dividend value and subtracted therefrom when it is not greater, one then being entered in the quotient counter 5, the value in which is doubled for each halving operation. General operation. The apparatus shown is for dividing a 3-digit dividend (entered in the top 3 denominations of counter 1) by a 3-digit divisor (entered in the bottom 3 denominations of counter 2) to give a 6-digit quotient. The emitter 7 is similar to that used in the multiplier described in Specification 674,952 and comprises 20 units operated successively under control of a pulse generator 14 to supply control pulses through gate valves 10 which are controlled by potentials on lines 11 and 12 connected to control unit 13 (similar to the half cycle control unit of the multiplier). When the emitter sequence is started by closing key or relay contacts in start control unit 15, the lower gate valves 10, connected to line 11, are open to pulses from emitter units 7(1) to (12) which effect doubling of the divisor. When unit 7(12) is switched back a pulse is sent through gate valve 24 to line 20, unit 15 and line 19 to unit 7(1) to start another emitter doubling cycle. This sequence continues until the divisor value overflows into register 3 when unit 13 is switched over by a pulse sent over line 29 and through gate valve 58, so that the potentials on lines 11 and 12 are changed over. The upper gate valves 10 and gate valve 23 will then be opened to control dividing operations proper. During the following cycles, a pulse on line 26 from unit 7(12) will switch over unit 7(13) and the sequence will continue to unit 7(20) which will send back a pulse through line 27 and amplifier 28 to line 20 and unit 15 as before. The repeatedly halved divisor values are compared with the dividend value by units 4, and are transmitted to the dividend counter 1, for subtraction, through valves 6. When the number of divisor-halving. cycles equals the number of divisor-doubling cycles, as determined by a cycle counter 8, operations are terminated by a pulse sent over line 21 to unit 15. The denominations of counters 1, 2 and 5 each comprise a binary counter consisting of four trigger stages representing values 1, 2, 4 and 8 respectively. Cycle counter. During each cycle a pulse is sent from emitter unit 7(11) through amplifier 28 to line 35 and is applied to the first of five trigger stages V40-V44, Fig. 2, connected to count in the binary system. The pulses are added or subtracted according to the condition of a trigger stage V45. During the divisordoubling cycles the left-hand valve V45 is conducting and therefore the potential on line 34 will be greater than that on line 33, these lines being connected to the suppressor grids of associated gate valves V47-V65. Thus when any of the stages V41-V44 is switched back to the normal state (left-hand valve conducting) the resulting positive pulse applied through condenser 48 to the control grid of one of valves V49, V51, V53, V55 will cause an anode pulse to be sent to the next higher stage V40-V43 to effect addition. Stage V45 (31 in Fig. 1) is switched with unit 13 by a pulse over line 32 which also switches over a trigger stage 54. Subsequently, subtract valves V47, V48, V50, V52, V54 will be operative so that a pulse will be sent to the next higher stage when any of stages V41-V44 is switched over from normal. When the counter passes through zero, stage V40 is switched over and a pulse is sent through condenser 53 and gate valve V47 to the line 21. This pulse occurs after the correct number of cycles since an additional pulse is entered subtractively when trigger stage 54 is switched back by the first pulse on line 27. Auxiliary control units. Trigger stage 140, Fig. 1, is similar to stage 31 (V45, Fig. 2), and the lines corresponding to 33, 34, are connected through cathode follower stages 141, 142 to lines 131, 132 which control the doubling and halving of the divisor. Various isolating cathode follower stages 63, amplifiers 28 (similar to those of the multiplier described in Specification 674,952, which reverse the polarity of pulses received, and trigger stages such as 76 which determine the potential on lines such as 71, are also provided. Registering, doubling and halving the divisor. The divisor counter 2, Fig. 1, combines the features of the multiplier and multiplicand registers described in Specification 674,952. Fig. 3 shows one denomination comprising four registering trigger stages V23-V26, a carry down stage V27, carry up stage V22 and gate valves V28-V39 associated with lines 131, 132. The divisor digit is entered by applying pulses to lines 158. During the doubling cycles, line 131 is at higher potential and valves V28, V29, V30, V32, V34 and V36 are operative. Pulses from emitter units 7(1) to (4) are sent successively over lines 65-68 to switch to normal (left-hand valve conducting) stages V23-V26, pulses being sent through valves V30, V32, V34, V36 to the next higher stage or, via valve V59, to carry up stage V22. An additional six is added by pulses from units 7(5) and (6) over lines 69 and 70 to stages V25, V24. If no carry has been registered, the control grids of valves V28, V29 will be at high potential so that the pulses from units 7(8) and (9) over lines 72, 73, reversed in polarity by amplifiers (not shown) and applied to the suppressor grids, will produce negative anode pulses which cause a correcting ten (2+8) to be added. Trigger 76 is switched by unit 7(7) so that line 71 is then at low potential thus isolating carry stage V22. If a carry has been registered the control grid of gate valve V21 will be raised, so that the pulse over emitter line 74 will produce a carry pulse on line 191. The carry stage is reset by a pulse on line 75. Trigger stage 140 is switched with unit 13 by a pulse over line 168, so that at the beginning of the halving cycles line 132 is at the higher potential and carry down gate valves V31, V33, V35, V37 are operative. After halving within the denominations has been effected, stage 140 is switched back by a pulse on line 178 from emitter unit 7(5) thus enabling " five " to be carried down to the next denomination by emitter pulses on lines 80, 81 through gate valves V39, V38 to lines 133, 134, if a carry has been registered in stage V27. Dividend counter. Fig. 3 shows one denomination comprising four registering trigger stages V13-V16, a carry stage V12 and gate valves V3-V10 which are controlled by potentials on subtract and add lines 97, 98 corresponding to lines 33, 34 respectively of the cycle counter, Fig. 2. The dividend is entered additively and the divisor values are subsequently subtracted by applying pulses to lines 96. During the divisor-halving-and-subtracting cycles, if any carry has been registered via valve V57 (similar to V59 of counter 2) an emitter pulse from line 88 is sent through gate valve V11 to line 100a and the next higher denomination, and the carry stage is reset by a pulse on line 94. Consequent carries are transmitted through valve V58 whose suppressor grid potential is controlled from trigger stage 102 through line 103. Subsequently, six is subtracted by emitter pulses on lines 90 and 91 to stages V15, V14 respectively, and if the carry stage V12 has not been switched over a correcting value of ten is subtracted by pulses to stages V15, V13 via lines 101, 93 and gate valves V2, V1, Dividend/divisor comparison. Valves such as V17, Fig. 3, of comparing units 4, Fig. 1, are so connected to corresponding registering trigger stages of counters 1 and 2 that their suppressor grids are below cut-off potential unless the registered divisor value (binary digit) is greater than the dividend value, and their control grids are above cut-off unless the divisor value is less. Thus an emitter pulse over line 82 to the control grid of the highest comparing valve will be reproduced at the screen grid and applied to the control grid of the next lower valve and so on down the valve chain until two unequal values are encountered. If the divisor is greater than the dividend a pulse will be produced on the anode line 157 at this point and will switch over the divisorsubtraction control trigger stage 87. Transmission of divisor to dividend counter. Valves 6, Fig. 1 (V65, Fig. 5), are connected to corresponding registering trigger stages of counters 1 and 2 through lines 96, 95, Fig. 3. If trigger stage 87 has not been switched by a pulse on line 157 it will allow pulses through the upper gate valves 10 of emitter units 7(8) to (1)) (not connected to line 12) to lines 167(8), (4), (2), (1) connected to the suppressor grids of valves 6 so as to cause anode pulses representing values 8, 4, 2, 1 to be sent successively to the dividend counter whenever the control grid potentials are raised due to these values being registered in the corresponding denominations of the divisor counter. Quotient counter. This is similar to the multiplicand register described in Specification 674,952. Whenever the divisor is sent to the dividend counter, a pulse from emitter unit 7(11) over line 9 adds one to the quotient. Doubling pulses are sent over lines 76-79 and the additional six and ten are added on the lines which effect subtraction of these values in the dividend counter.