Patent GB-830782-A (GB)
Title: Improvements in or relating to electronic digital computing machines
Inventor: KILBURN TOM
IPC: G06F5/01
Filed: 1955-04-07
Abstract: 830,782. Digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. March 29, 1956 [April 7, 1955], No. 10202/55. Class 106 (1). In an electronic digital computing machine operating with a floating radix point, the exponent-representing portions of two numbers involved in a calculation are subtracted and the difference signal controls a variable delay device arranged in one of two channels through which the number-representing portions of the two number signals respectively are directed, the one passing through said one channel being selected under the control of a signal representing the sign of the said difference. The two number-representing portions of the number signals are thus presented for calculation in correct denominational alignment. The invention is described as applied to a binary machine similar to that disclosed in Specification 786,734 in which calculations are performed in the series mode although the main data-store (comprising ten cathode-ray tubes) operates in parallel manner. The main store accommodates 10-digit numbers and consequently the machine operates in beats or minor cycles of 10-digits, these being alternately scan (store-regeneration) and action beats. Number representation.-Numbers are represented in the computing portion of the machine in the form x.2<SP>y</SP> by a long (30-digit) signal representing x and by a 10-digit signal representing the exponent y. Negative values of x and y are represented in complementary form with a 1 as the most significant digit, a 0 in this position indicating a positive number. A standard form of number is employed in which + ¢ # x # + “ for positive numbers and - “ # x # - ¢ for negative numbers. Such standard numbers have the property that the two most significant digits are always different from one another, 0.01 ... in the case of positive numbers and 0.10 ... in the case of negative numbers. The second most significant digit position in the exponent numbers y is left as an " overflow " position. Accumulator.-The input from the main store, Fig. 1f (not shown), to the accumulator, Figs. 1b-1d, is by way of a lead 100 and the output from the accumulator to the store is by way of a lead 101. Arranged between input busbars A, B and C and an output bus-bar O are the following registers-for add/subtract operations, a 30-digit register XA (for x) and a 10- digit register YA (for y); for multiplication, registers XD and YD (similar to XA and YA respectively) for the multiplicand, and a 30- digit register XR for the multiplier; and eight B registers, Fig. 1e (not shown), used in known manner for modifying instructions. The register XR is also used in the assembling of numbers. The registers XD, YD and XR are associated with a multiplying circuit, Fig. 1a (not shown), similar to that described in Specification 788,927. All of the registers are composed of 10-digit delay lines which may be constructed as described in Specification 776,143. The busbar A is connected through a complementer CM1 either through a fixed delay DL3 to the input a4 of a computing unit CMU or through the variable delay device VDC referred to below, to the input b4 of that unit. The bus-bar C is connected through an extender circuit EXC and to inputs a4 and b4 of the computing unit in a similar manner. Gates G2-G5 are connected in these alternative routes and are controlled by a trigger FF2 as described below. The computing unit, Fig. 5 (not shown), which is of the amplitude discriminator type, is similar to that described in Specifications 693,424 and 683,882. A trigger FF5 registers the sign of a number being received from the main store and a trigger FF2 registers the sign of the difference (#) between two exponent portions, as described below. Means are described with reference to Fig. 1g (not shown) for deriving the various control waveforms indicated in the Figures. Orders are represented in the latter in brackets and the full order code is set out in the Specification. Variable delay unit.-This comprises a fixed delay of 2 digit periods (microsecs.) and delays of 16, 8, 4, 2 and 1 units, each of which can be rendered effective, in series. The delay lines are of the distributed capacitance type and each, e.g. DL61a, Fig. 6c, is effective when its capacitive electrode is held at earth potential and ineffective when the input signal is applied to the capacitive electrode as well as to the inductive element. The delay lines are controlled by respective gates, e.g. CG61, Fig. 6b, controlled either by signals, e.g. Z5, from the Z counter or by the pulses of a train passing from the input terminal a1<SP>xx</SP>, Fig. 1c, through unit delays DL67 &c. A control waveform on lead 62 derived from gates G67 and G68, opens the gates CG61 &c. when required. The latter exercise their control of the delay lines through condenser memory circuits, e.g. CM61, which are reset by pulses on a lead 61 derived at appropriate times. Each delay line, e.g. DL61a, has its two elements connected to the cathodes of similar cathode followers V30, V31 to which the input is applied, and its output is applied to an amplifier V32. The cathode of valve V31 is connected to the cathode of a further cathode follower V33 of the condenser memory unit CM61. The grid of V33 is connected to an earthed condenser C30 normally discharged but charged negatively when a positive pulse is applied to the grid of amplifier V34 from the diode gate CG61. The valve V33 is then cut off so that the cathode of V31 can follow the input signals. When the condenser C30 is discharged, V33 is conductive and its cathode holds the capacitive electrode at earth potential. The control pulses on the lead 62 are positive and these are passed by the diode gate CG61, to render the delay DL61a ineffective, unless both the signal Z5 from the Z counter and the point 65, in the series of unit delays DL67 &c., are at their normal relatively high potential. If a " 1 " signal (negative) is passing point 65 or if the signal Z5 is effective (negative), the delay DL61a is effective. Z counter.-The first of five counting sections C1, Figs. 4a and 4b, comprises a valve V10 which conducts during a KD pulse at the beginning of a digit period. A negative pulse is thus applied to V11 to produce a negative output pulse at its cathode (and terminal 155) which persists until a condenser C10 is discharged by the next KB pulse at the end of the digit period. The output pulse is fed through a ¢ unit delay DL30 to the grid of V10 where it cancels the next KD pulse. Consequently output pulses are produced in alternate digit periods only. The other sections C2, C4, C8 and C16 are similar but have delays of 1¢, 3¢, 7¢ and 15¢ units respectively. The effect is that the five sections together produce in successive digit periods parallel binary signals corresponding to 31, 30, 29 ... 0, under the general control of a T<SP>1</SP> waveform. The outputs of the sections are connected through respective diode gates, e.g. G61, opened by a read pulse applied to terminal 156 and derived as described below, to condenser memory circuits, e.g. CM1. The latter are re-set by positive erase pulses applied to terminal 157. The cathodes of the cathode followers V12 of the memory circuits provide the Z signals, e.g. Z1. These may be dynamicized by a control pulse from a gate G66 which opens diode gates, e.g. G75, to apply the Z signals to points along a line of unit delays connected to an output terminal 135. The read and erase pulses for application to the terminals 156 and 157 are obtained from the answer pulse train passing from the computing unit CMU, Fig. 1c, to an input 134. This pulse train is applied directly, and via a unit delay, to a notequivalent circuit NEC, which consequently produces an output when there is a changeover of the digits. The output signal is passed by a gate G11 to the erase and read terminals 157, 156 through ¢ and 1 unit delays and inverters. Thus the final Z signals represent the denominational position of the last changeover in digits in the answer pulse train and are used, as described below, to determine the extent of the .shift necessary to standardize the answer number. Entry into accumulator. -The exponent portion y of a number first appears in serial form on lead 100 in the fourth scan beat (S4) of the bar, and is passed by a gate G1 to bus-bar A. It then passes through the complementer, which is inoperative at this time, gate G2, computing unit CMU, a gate G7, and a delay DL33, to bus-bar O, the total delay being 2 beats (20 digits). From bus-bar O, the portion y passes in beat S5 through a gate G18 to the register YA (for addition). The components x1, x2 and x3 (most significant) of the x portion are stored so that they become available in beats S6, S5 and S7 respectively on lead 100. In beat S5, x2 is passed through a gate G32 to register XR. x1 and x3 then pass in beats S6 and S7 respectively to the same register which then stores the complete portion x in proper order. The most significant digit representing the sign of x is delivered in parallel form from the main store in beat A6 and over a lead 174 sets a trigger FF5 accordingly. The assembled portion x is then fed in beats A7, S8 and A8 to register XA (for addition) by way of gate G26, lead 148 and gate G49. In the case of a multiplicand the x and y portions are passed to registers XD and YD. Addition and subtraction.-During beat; S3 the exponent portion of a number already registered in the accumulator, yA, passes through a gate G19 from the register YA to busbar B and from there, through a delay line DL22, the computing unit CMU (inoperative) and delay DL33 to bus-bar O. During beat S4, yA is directly returned to bus-bar B as the exponent portion of the store number, yS, arrives through gate G21 to bus-bar A. The complementer CM1 is effective at this time and gate G2 opens so that the portions yS (complemented) a