Patent EA-002110-B1 (EA)
Title: Conversion of a pcm signal into a upwm signal
Inventor: RISBO LARS
IPC: H03M5/08
Filed: 1997-03-26
Abstract: 1. A signal converter for converting a PCM input signal into a UPWM output signal, the signal converter comprising: a UPWM converter being adapted to receive a UPWM converter input signal and to generate the UPWM output signal in the form of output pulses of variable widths based on the UPWM converter input signal, a first set of correction signal paths being adapted to receive a PCM signal and to generate a first set of respective correction signals, each correction signal path of the first set comprising a non-linear generator function in series with a linear correction filter, a summing unit adapted to combine the first set of respective correction signals with a first PCM signal to provide an error corrected PCM signal, the error corrected PCM signal suppressing non-linearity and/or noise generation within the signal converter caused by the conversion of the PCM input signal into the UPWM output signal. 2. A signal converter according to claim 1, further comprising: a second set of correction signal paths being adapted to receive a second PCM signal and to generate a second set of respective correction signals, each correction signal path of the second set comprising a non-linear generator function in series with a linear correction filter, the second set of correction signal paths comprising one or several correction signal paths. 3. A signal converter according to claim 1 or 2, wherein the summing unit is adapted to combine the first set of respective correction signals and the second set of respective correction signals with the first PCM signal to provide error corrected PCM signal. 4. A signal converter according to claim 1 or 2, wherein each correction signal path of the first set of correction signal paths forms part of a respective feed-forward loop within the signal converter, the first set of respective correction signals thereby correcting earlier occurring signal samples of the first PCM signal. 5. A signal converter according to claim 1 or 2, wherein each correction signal path of the first set of correction signal paths forms part of a respective feed-back loop within the signal converter, the first set of respective correction signals thereby correcting later occurring signal samples of the first PCM signal. 6. A signal converter according to claim 1 or 2, wherein each correction signal path of the first set of correction signal paths forms part of a respective feedforward loop within the signal converter, and each correction signal path of the second set of correction signal paths forms part of a respective feed-back loop within the signal converter, the summing unit being adapted to combine the first and second sets of correction signals with the first PCM signal to provide the error corrected PCM signal. 7. A signal converter according to claim 4, further comprising: a linear signal path being adapted to receive the PCM signal and to generate the first PCM signal in response to the PCM signal, thereby forming the error corrected PCM signal by combining the first PCM signal generated by the linear signal path and the first set of respective correction signals in the summing unit. 8. A signal converter according to claim 7, wherein the PCM signal is constituted by the PCM input signal of the signal converter or an associated PCM signal derived from the PCM input signal, the first set of correction signal paths and the linear signal path thereby forming a feed forward structure that generates the error corrected PCM signal. 9. A signal converter according to claim 7 or 8, wherein the linear signal path comprises a time delay having a time delay of K samples, K being a positive integer number, the time delay of one sample being the reciprocal of a sampling frequency of the first PCM signal. 10. A signal converter according to claim 9, wherein each of the linear correction filters of the first set of correction paths is adapted to provide a time delay of substantially K samples in the respective correction signal. 11. A signal converter according to any one of claims 7 to 10, wherein the error corrected PCM signal from the summing unit is applied to a noise shaper, the noise shaper being adapted to generate a quantised and noise shaped PCM signal in response to the error corrected PCM signal. 12. A signal converter according to claim 11, wherein the UPWM converter is adapted to receive the quantised and noise shaped PCM signal of the noise shaper. 13. A signal converter according to claim 6, further comprising: a noise shaping signal path adapted to receive the PCM signal and having the summing unit arranged in series with a noise shaper to provide a quantised and noise shaped PCM signal, the first set of respective correction signals being fed-forward to the summing unit and the second PCM signal being constituted by the quantised and noise shaped PCM signal so that the second set of respective correction signals is fed-back to the summing unit, whereby the error corrected PCM signal provided by the summing unit is applied to the input of the noise shaper to suppress intermodulation noise in the UPWM output signal due to the non-linear UPWM conversion process being applied to the noise shaper output signal. 14. A signal converter according to claim 5, wherein the UPWM converter comprises a quasi-symmetrical UPWM converter generating the UPWM output signal in the form of symmetrical and asymmetrical output pulses of variable widths in response to the PCM signal, the first set of correction signal paths comprising at least one correction signal path with a non-linear generator function adapted to provide a generator signal in response to a dynamic indication of a symmetry form of the symmetrical and asymmetrical output pulses to provide the first set of respective correction signals, thereby forming the error corrected PCM signal by feed-back of the first set of respective correction signals from the input of the quasi-symmetrical UPWM converter to the summing unit so as to suppress an inherent non-linearity of the quasi-symmetrical UPWM converter. 15. A signal converter according to claim 14 further comprising: a noise shaper, the noise shaper being adapted to receive the error corrected PCM signal from the summing unit and to generate a quantised and noise shaped PCM signal in response to the error corrected PCM signal, and wherein the quantised and noise shaped PCM signal constitutes the PCM signal fed to the input of the quasi-symmetrical UPWM converter. 16. A signal converter according to either of claims 14 or 15, wherein the at least one correction signal path adapted to provide the generator signal comprises a scaling function adapted to multiply the generator signal with a constant of:   wherein Tb is the cycle time of the bit clock, ΔT represents a cycle time of the UPWM signal. 17. A signal converter according to claim 16, wherein the generator signal g(k) is given by: g(k)=s(k)(x(k)+1) where the quantity ΔT * (x(k)+1)/2 represents a width of the output pulse of the UPWM output signal at time index k, s(k) is the signal providing the dynamic indication of the symmetry form of the variable width output pulse and represents a time shift with respect to symmetrical modulation of the output pulse at time index k expressed in half bit clock periods. 18. A signal converter according to claim 12, further comprising: a third set of correction signal paths being adapted to receive a third PCM signal and to generate a third set of respective correction signals, each correction signal path of the third set comprising a non-linear generator function in series with a linear correction filter, the third set of correction signal paths comprising one or several correction signal paths, a second summing unit arranged in series with the noise shaper and adapted to combine the second set of respective correction signals and the third set of respective correction signals to provide a second error corrected PCM signal, the second set of correction signal paths being adapted to receive the error corrected PCM signal to generate the second set of respective correction signals, the noise shaped PCM signal of the noise shaper being applied to the third set of correction signal paths to generate the third set of respective correction signals. 19. A signal converter according to claim 18, further comprising: a quasi-symmetrical UPWM converter generating the UPWM output signal in the form of symmetrical and asymmetrical output pulses of variable widths in response to a fourth PCM signal, a fourth set of correction signal paths being adapted to receive the fourth PCM signal and to generate a fourth set of respective correction signals, each correction signal path of the fourth set comprising a non-linear generator function in series with a linear correction filter, the fourth set of correction signal paths comprising at least one correction signal path having a non-linear generator function adapted to provide a generator signal in response to a dynamic indication of a symmetry form of the symmetrical and asymmetrical output pulses to provide the fourth set of respective correction signals, a third summing unit adapted to combine the fourth set of respective correction signals and the error corrected PCM signal to provide a third error corrected PCM signal, the third summing unit providing the third error corrected PCM signal to the input of the second summing unit. 20. A signal converter according to any one of the preceding claims, wherein at least one of the linear correction filters comprises a Finite Impulse Response (FIR) filter on an Infinite Impulse Response (IIR) filter or wherein the linear correction filters of one or several sets of correction signal paths comprise respective FIR filters or IIR filters. 21. A signal converter according to any one of the preceding claims, wherein the linear correction filters of one or several sets of correction signal paths are constituted by respective F