Patent GB-1369685-A (GB)
Title: Time-division multiplex switching circuitry
IPC: H04Q11/04
Filed: 1971-09-20
Abstract: 1369685 Automatic exchange systems SOC LANNIONNAISE D'ELECTRONIQUE and COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 20 Sept 1971 [18 Sept 1970 11 Feb 1971] 43813/71 Heading H4K In a TDM exchange in which time slot interchange between channels of an incoming highway and channels of an outgoing highway is effected by intermediate storage of the data occurring in a channel, the data in respect of a same call is always stored in a particular memory word whose address is cyclically generated during the time slots allotted to the call on the incoming and outgoing highways so that write-in and read-out may occur in synchronism therewith. In Fig. 1 the intermediate storage used for selectively connecting any one of the e channels of an incoming highway to the s channels of an outgoing highway is provided by a memory 2 having a capacity of K words each of x bits. In setting up a connection between a particular input channel Ei and an output channel Sj a route finder (not shown) allots a free memory word Kl to the call and causes this to be written into write control memory MCE, 10 and read control memory MCL, 11 at addresses associated with the incoming and outgoing channels respectively. The two control memories have capacities of e words each of log 2  k bits and s words each also of log 2  k bits respectively. Strict synchronization on the incoming highways is not necessary since the instant occurrence of each channel is detected by control circuitry that delivers signals he and Te corresponding respectively to channel number and frame start to an address generator 6 which thereupon delivers the address Ei. The latter is used to read-out from memory 10 the associated word Kl thereby permitting data in channel Ei on the incoming highway to be written into this word in memory 2. Read-out from memory 2 on to the channel Sj of the outgoing highway is accomplished in an exactly analogous manner by the read-out circuitry MCL. In Fig. 2 the read and write control memories MCEo 27 and MCLo 28 have a capacity of k words of log 2  e bits and k words of log 2  s bits respectively. In this case, during the establishment of a connection involving an incoming channel whose address is Ei, this address Ei is written at the position Kl corresponding to the allotted free data memory word for this connection. During the channel time of the incoming channel the address Ei supplied by generator 6 is compared with the addresses stored in memory 27 until coincidence is found whereupon the location Kl of the coincidence is passed to the memory 2 to permit write-in of data from the incoming highway. Again read-out control by circuitry MCLo is analogous. A plurality of incoming or outgoing highways may be accommodated by providing each of them with a data memory 2 and corresponding .write-in MCE or read-out MCL control circuits respectively. Read-out or write-in from the data memories is controlled by a single circuit MCL or MCE respectively, these having a capacity K equal to the total number of channels on the set of incoming or outgoing highways with which they are associated (Figs. 8 and 9, not shown). The memories may be of static or dynamic, e.g. recirculating shift register, type and various forms of addressing circuit therefor are described with reference to Figs. 3-7 (not shown). The memories and address logic may be implemented by TTL and be formed as integrated circuits.