Patent GB-1144005-A (GB)
Title: Data transfer system
Inventor: PEARS DAVID ASHLEY
IPC: G06F3/06
Filed: 1966-09-01
Abstract: 1,144,005. Digital data storage. SCIENTIFIC DATA SYSTEMS Inc. 1 Sept., 1966, No. 39078/66. Heading G4C. Binary 0's are represented by an additional transition between two transitions denoting a bit period recorded on a magnetic tape, and the read logic, Fig. 3 (not shown), includes a counter (RDA-RDD) cycled by clock pulses having a repetition frequency 12 times the nominal bit rate, the transition pulses being gated with the counter states to produce a binary output (RF) which is determined by which one of two ranges of counts the transition occurred in. A tolerance of 25% in the time of arrival of a transition pulse is allowed. Transitions occurring outside the two ranges cause a gap signal (RG) to be generated. The read logic also includes preamble and postamble detectors, a parity checker and a bit-rate clock output (RC). Write logic, Fig. 9 (not shown), includes a counter (WCA-WCD) for the high rate clock pulses which provides two trains of antiphase pulses (WCP1 and WCP0). One pulse train (WCP1) is used to trigger a write flip-flop (WF) continuously, whereas the other train (WCP0) is gated with data from a register 500 and applied to produce an additional transition from (WF) for each binary 0 in the data. The pulse trains are also used in the generation of the preamble (eight 1's followed by a 0) and the postamble (0 followed by eight 1's) in the CS 1 and CS3 states of the programmer described below. Register converter 500, Fig. 12, acts as a temporary buffer for data transferred between a computer and the tape or as a counter for monitoring delay periods preceding or succeeding the reading or writing of a series of bits, depending on the particular one of a sequence of control signals developed by programmer 600 in response to computer commands. A flip-flop for each bit of a character HR00-HR06 each has four possible inputs from gates 501-504 to 561-564. When programmer state CS2 is reached in the write mode, CE CF is turned on and gate 570 issues SPG (shift parallel gate) to open gates 501, 511-561 to enter a character in parallel from the computer. CECF is then turned off and SFG (shift forward gate) is developed by gate 571 whereby HR00-HR06 are connected as a shift register receiving shift pulses from gates 581, 580 and providing a serial output to the write logic from #HR00. Clock pulses WCP0 are synchronized with the zero-representing tape transitions. Parallel loading and serial unloading continues under control of CECF which is turned on and off once per character until the computer issues an end of data command W5 causing change over from CS2-CS3 for postamble generation; followed by CS4 for completion of the read-after write check. During forward reading (CS7 and #C12M), gate 571 produces SFG to connect HR00-HR06 as a shift register, and since #W9 (not write) is on, the output RF from the read head is shifted in via gates 572, 562, shift pulses being supplied by gates 582, 580. After each character transfer is effected via gates 507-567 in parallel. During reverse reading gate 575 develops SRG (shift reverse gate) so that HR00-HR06 are again connected as a shift register, but this time the read logic input is to gate 503 and shifting takes place in the reverse direction. Gate 576 issues CBG to connect HR00-HR06 as a binary counter in states CS0, CS4-CS6 and counts character clock pulses WG01 applied to gate 505, so as to monitor gap lengths as described below. Programmer 600, Fig. 13, comprises a register CSA-CSC (called a state counter) which is settable to any one of states CS0-CS7 and which assumes predetermined sequences of such states under control of commands W5, W9-W11 issued by the computer, control flip-flops C12M-CERF, and a detector 550 which responds to specific counts attained by converter register 500 when acting as a counter. State CS0 corresponds to an idle condition and is attained by the computer issuing #W11 to turn off CSA-CSC. State CS1 corresponds to the formation of a preamble code in the write mode, and is attained in response to W9 when detector 550 issues STGD indicating that a period sufficient to allow the tape to run up to normal speed has elapsed, CS0 (gate 607) limiting the transition to CS0-CS1. State CS1 can also be attained from state CS5 when writing is to be continued. The transition CS5-CS1 requires CSA to be reset, and this is effected by gate 608 in response to command W9 at the expiry of the gap delay CUWD. State CS2 corresponds to the writing of data serially by character and bit and always follows CS1. The transition CS1-CS2 is effected when the final bit of the preamble has been written, signalled by CEFC being turned off, thus turning CSB on and CSC off. State CS3 always follows CS2 and corresponds to the formation of a postamble code. The transition CS2-CS3 is effected by turning on CSC in response to W5 signalling the end of data from the computer. State CS4 corresponds to a delay period equivalent to the time taken for a given point on the tape to pass between the read and write heads. For the transition CS3- CS4, CSA is turned on and CSB is turned off by coincidence of CS3 and CECF, the latter occurring at the end of the postamble. CSC is turned off in response to coincidence of CECF with #W10 (no erasing in progress) or C12M (tape running in reverse). State CS4 can also be reached from CS7 at the end of reading. During reading, CERF is on until a gap at the end of a record is detected, and CSB, CSC are reset by coincidence of CERF and CS7, CSC also requiring C12M since the transition CS7-CS4 only occurs in reverse running of the tape. State CS5 corresponds to a waiting period, with the tape still running, during which the computer issues a decision on whether operation is to continue. In the CS4 state, a minimum delay WTRD occurs between the end of a record passing the leading and trailing heads. During reverse read, the transition CS4-CS5 occurs on coincidence of W9 and WTRD to set CSC via 606, 606<SP>1</SP> and 617. During writing, which always takes place forwards, W9 is on, and CSC is set via 613, CERF turning off at the end of the read-after-write check. The transition CS4-CS5 is also forced when no erasing is taking place (W10 off), the waiting period IHGD being larger than WRTD in case the tape is running slowly or the end of a record has been missed. CS5 can also be reached from CS7 (reading) by turning off CSB as described for transition CS7-CS4. State CS6 corresponds to the shutdown sequence and is reached from CS5 after a delay SPGD during which the computer issues a decision to shut down (absence of a start pulse to turn on CUFF) so that gate 616 turns CSB on and CSC off. CS6 can also be reached from CS4 by means of gate 618 turning on CSB. State CS7 corresponds to reading, forwards or backwards, and is reached from CS0 as follows. For forward reading; the read head will be situated some distance from the first record to be read, and to avoid extensive reading of the gap condition, the transition CS0-CS7 is delayed until IHGD is issued. For reverse reading; the read head is close to the first record to be read, and CS7 is reached immediately upon issuance of W9 (not write) provided C12M (tape in reverse) is on, by way of gate 609. State CS7 can also be reached from CS5 when reading is to be continued. For forward reading, a start pulse turns on CUFF during CS5, and after a delay CURD, the transition CS5-CS7 takes place via gate 619. For reverse reading, transitions occur in the order CS7, CS4, CS5, CS7, and since CS4 includes a delay WTRD before CS4-CS5, a further delay SPGD before CS5-CS7 is all that is required in reverse reading (WTRD + SPGD is approximately equal to CURD), so CSB is turned on via gate 619.