Patent GB-1380830-A (GB)
Title: Memory arrangement
IPC: G11C11/415
Filed: 1972-06-23
Abstract: 1380830 Data store INTERNATIONAL BUSINESS MACHINES CORP 23 June 1972 [30 June 1971] 29421/72 Heading G4C  A memory includes an array of storage cells, two groups of decoders 50 for selectively accessing the cells, each decoder including a bi-stable latch, which, when in a first state, enables the decoder, in combination with a decoder of the other group, to access a particular cell and when in the other state prevents access to the particular cell, a plurality of address lines for each decoder by means of which address signals are supplied to determine the state to be occupied by the latches on receipt of a momentary trigger signal, the latches being arranged to hold their state following termination of the trigger signal without the supply of power through the address lines. As described a monolithic 4 x 4 memory array 10 is connected to X and Y addressing circuits 14 and 12 repsectively. It is stated that the memory cells may be of any suitable type, including read only devices. X and Y address signals are applied to true/complement generators 20, 22, 38 and 40 and respective, the X and Y decoders 50 being connected to a unique combination of true/complement address lines as shown. The decoders have a cell select output 52 which in combination with a similar output of a further decoder is effective to address a cell in accordance with conventional matrix addressing schemes. Three embodiments of the decoders 50 are described all involving a semi-conductor controlled rectifier 74 illustrated schematically as two transistors 86, 88. In the first embodiment, Fig. 2, the combination of address lines unique to the decoder (in this case Y1, Y2), are applied via diodes 70, 72 acting as an AND gate. When both address inputs are up and a momentary SET pulse is applied via input 76 and SCR latches into its low impedance state in which power is drawn from the +4 volt supply. As a result the output voltage Vout on line 84 is raised to approximately + 3 volts and a cell select signal is provided which, in combination with the select signal from the selected X decoder, accesses a particular memory cell. The non-selected X and Y decoders remain in their high impedance state. When the access cycle is complete each decoder is supplied with a RESET pulse which places all decoders in the high impedance state. The additional elements in chain lines in Fig. 2, merely provide a negative (complement) cell select signal on line 114. The arrangement is such that a selected decoder consumes no power from the address inputs. Non-selected cells consume a small amount of power but only when the SET inputs are pulsed. The two other embodiments, Figs. 3 and 4 (not shown), differ only in the way in which the address and SET/RESET inputs are connected to the SCR. In one embodiment the address inputs are connected to respective emitters of a multiemitter transistor whose base receives the SET/RESET signals and whose collector is connected to the base of transistor 86. In the other embodiment the SET, RESET, and address inputs are connected via appropriately poled diodes to a common point which is connected to the base of transistor 86. The Specification describes an integrated circuit construction of the decoders, Fig. 5 (not shown).