Patent GB-938949-A (GB)
IPC: G06Q10/02
Abstract: 938,949. Data retrieval system; reserving seats &c. TELEREGISTER CORPORATION. July 3, 1962 [July 7, 1961], No. 25412/62. Classes 106 (1) and 106 (3). An on-line data processing system for processing call requests from input-output devices in the form of key sets comprises a central processor having a high speed store, and a plurality of peripheral units including backing storage units controlled by the central processor in accordance with received call requests to transfer data between the peripheral units and the central processor. The peripheral equipment can include magnetic tapes or magnetic drums. The arrangement may be applied to aircraft seat reservation control systems or to other applications. Data transfer to or from the peripheral equipments is performed concurrently with arithmetic processor operations, the operation of the processor being " interrupted when a data transfer is required. A plurality of peripheral equipments may be transferring data to or from the processor at the same time and transfer is controlled by assigning priorities to the various peripheral units since the central processor high speed memory can only deal with one item of data at a time. The slower equipments (e.g. tapes) are assigned the higher priorities. The peripheral equipments have individual control registers which control a data transfer operation involving the associated equipment which thus are enabled to sequence through a series of operational steps independently of the central processor. The flip-flop circuits employed in the system include transistors. Central processor.-The central processor 12, Fig. 1, comprises a high speed core memory 14 containing 10,000 locations, each for storing a binary-coded decimal digit. The processor is connected to a drum peripheral equipment 16 (shown in detail in Figs. 4A-4C), a tapes peripheral equipment 24 (not described in detail) and a set of message registers MR, 36 for storing the 10-decimal-digit call words from the various key sets (not shown). When a message register MR contains a call word it causes a seeker 34 to connect it to the processor which receives the word and ascertains the required data which is sent via that message register back to the calling key set. The next message register MR then receives attention. Each processor instruction word consists of eight decimal digits: two operation digits, two field length digits and four memory location digits. Instructions are executed sequentially under the control of an instruction control register ICR, 40 which registers the 4-decimal-digit address of the next memory location. A memory control register MCR has 12 decimal digits divided into a 6-digit " working " section and a 6-digit " retained " section for controlling the extraction of operands from the memory. An accumulator control register ACR, 44 has 10 decimal digits comprising a 6-digit retained section and a 4-digit working section deferring the location of the accumulator in the memory 14. An order select register OSR registers the two operation digits of an instruction for controlling a function table 48. Instructions are normally performed in two phases: a " readout " phase and an " execute " phase, a " readout " phase requiring four " machine cycles " in each of which two decimal digits of an instruction are read out and an " execute " phase requiring a variable number of machine cycles. Fig. 2 shows in schematic form the initial steps of a processor programme. In step I, a " 99 " instruction causes the seeker 34 to be tested. If the seeker is busy," it is repeatedly tested until a " ready " signal is obtained, whereupon, in step II, the contents of the calling message register MR, which consists of the call number " 0367932651 " is transferred to memory location 2100-2109, this address being registered in the accumulator register ACR in step III. In steps IV, V the first digit of the call number is compared with a series of standard digits until an equality is obtained to indicate the type of call (e.g. " sell," " cancel " &c.) in question. When this has been ascertained, step VI causes a 13-digit control word to be transferred from memory locations 2350-2362 to a drum control register DCR, 102, Figs. 4A-4C. The processor now repeats the above operations for a new incoming call or " idles " in a closed loop. The programme can be interrupted at any time by a " bid " request from a peripheral equipment. Peripheral drum equipment. Figs. 4A-4C. The 13-digit drum control word is entered in the register DCR, 102 which comprises 13 stages, each stage comprising four transistor flip-flops for storing a binary-coded decimal digit. In the register 102, the first stage 104 determines whether reading or writing is required, the next two stages 106 select a particular head from a set of 100 transducing heads 156, the next three stages 108 determine the first digit position required on the selected track, the next three stages 110 determine the length of the data word to be read out and the last four stages 112 determine the address in the core memory 14 from or to which the data is to be transferred. In the example described, data is read from the drum and transferred to the core memory. In such a read-out operation, a comparator 166 indicates when the desired position on the selected track is reached, the decimal digit stored there being read out into the first decimal-digit stage of a 4-decimal-digit synchronizing register included in the circuitry 162 (Figs. 5A-5F, not shown), and unity being added to the " first digit position " register 108. On the subsequent occurrence of a clock pulse associated with the core memory, a " bid " signal is produced on a line 288 connected to one terminal 290 of a priority selector circuit 292 (also shown, unreferenced, in Fig. 1) to which are connected corresponding lines from the other peripheral equipments (not shown). Assuming that no higher priority equipment is currently " bidding," an " allow " signal is produced on a line 309 to set an " allow " flop 310 thereby causing transfer of the decimal digit from the first stage of the register in the circuit 162 to the core memory 14 over a line 362 to the address selected by the register section 112. The priority selector circuit 292 also produces an " interrupt " output on a line 332 to halt the operation of the function table 48 of the central processor, which is thus conditioned to receive the digit from the circuit 162. In the meantime the next digit from the drum has been read into the next one of the four stages in the synchronizing register in the circuit 162. If during the read-out of data from the drum, a peripheral equipment of higher priority makes a " bid " signal to the priority selector circuit 292, the read-out from the synchronizing register is temporarily halted. Retrieval of data from the drum continues until the register stages 110 have been counted back to zero to produce an output on a line 406. Specification 841,283 and U.S.A. Specifiction 2,564,410 are referred to.