Patent GB-1265530-A (GB)
Inventor: TERRY J B
IPC: H04L7/06
Filed: 1969-08-30
Abstract: 1,265,530. Multiplex pulse code signalling. MARCONI CO. Ltd. 22 July, 1970 [30 Aug., 1969], No. 43277/69. Heading H4L. A synchronizing arrangement includes a source of a bipolar signal at a fundamental synchronizing frequency in every nth cycle of which the portion of time in the half-cycle occupied by a signal of one sense is varied with respect to the portion of time occupied by said signal of one sense in other half-cycles and means for detecting the signal excurson variations so as to provide a sync. signal at 1/n of the fundamental frequency. -Preferably, to produce a symmetrical signal for every time variation of the signal excursion in one sense there is a corresponding variation of the signal excursion in the opposite sense. An arrangement for a PCM system is described which provides a fundamental clock frequency at 2À56 MHz, a frame sync. signal at (2.56/320) MHz and a multiframe sync. signal at (2.56x16/320) MHz. Sync. signal generator.-2À56 MHz and 5À12 MHz pulse signals are supplied to terminals 1, 2 respectively, Figs. 1 and 2, the 5À12 MHz signal being used to clock a bi-stable 3 on the transition from 0 to 1 and also being supplied via an inverter 5 to a NOR gate 6 and to clock a bi-stable 7 on the transition from 1 to 0, the 2-56 MHz signal being supplied to one input of the bi-stable 3 and via an inverter 4 to the other input. A multi-frame modulation signal to produce the multi-frame sync. Signal is supplied via terminal 8 to one input of the bi-stable 7 and through an inverter 9 to the other input. The resulting outputs A, B of the bi-stable 3 are supplied to inverting AND gates 10, 11 respectively which receive also -the output E from NOR gate 6. Gates 10, 11 provide outputs F, G which are combined at 12 where the signal from 10 is inverted and added to the signal from 11 after this has been given a negative D.C. shift, the resultant bipolar signal X being transmitted via line 13. A frame modulation signal which consists of two spaced pulses each of half the duration of that of the multi-frame modulation signal is supplied to terminal 8, Fig. 3, providing a-frame sync. signal as at X in which there is an extension of time occupied by a negative-going excursion from a quarter-cycle to a half-cycle and a similar extension of the positive going excursion one cycle later, only the negative-going excursion being used for synchronizing.  Synchronizing signal detection.-A received signal including the multi-frame sync. signal as at X, Fig. 5, is supplied via line 13, Fig. 4, and transformer 14 to threshold circuits 15, 16, producing outputs A and B. respectively which are supplied to cross-coupled NAND gates.21, 22 producing two synchronizing signals in phase opposition at the basic frequency of 2À56 MHz, that at terminal 24 being shown in line Y. Signals A and B. are also applied to clock the bi-stables 17, 18, respectively at transitions from 1 to 0, signal A also being applied to directly to one input of bi-stable 18 and inverted to the other input and signal B being similarly applied to the inputs of bistable 17. By this means a frame sync. signal C is developed at terminal 25 which is also supplied to an inverting AND gate 26 together with the output of bi-stable 18, a multiframe sync. pulse Z being, developed; at. terminal 27 whenever a positive pulse C is present: at..the same time as a. pulse D at the output of bi-stable 18. When the input signal is of the form shown at X, Fig. 3, a frame sync. signal appears at 25 but there will be no signal at 27, Fig. 6 (not-shown).