Patent GB-1118714-A (GB)
Title: A parallel adder circuit
IPC: G06F7/50
Filed: 1966-04-07
Abstract: 1,118,714. Parallel binary adder. VYZKUMNY USTAV MATEMATICKYCH STROJU. 7 April, 1966 [8 April, 1965], No. 15617/66. Heading G4A. A parallel binary adder comprises, for each bit of the number concerned, a synchronous unit 100, 101, 102 (Fig. 4) connected to the source of the input signals Xi, Yi, Xi-1, Yi - 1, Xi + 1, Yi + 1 respectively, and forming the logical sum modulo 2 and its negation at its output, an asynchronous transfer circuit 200, 201, 202 connected to trigger circuits 60, 70, 61, 71, 62, 72 respectively, the trigger circuits receiving the signals Xi - 1, Yi-1 of the adjacent least significant bit and the output Ci - 1 of the adjacent least significant transfer circuit, the transfer circuit producing a transfer signal Ci and its negation Ci, two output circuits 30, 40, 31, 41, 32, 42 which form a logical product and receive or form on their inputs the signals Si, Si, Si - 1, Si - 1, Si + 1, Si + 1 from data supplied by the synchronous units and the outputs Ci, Ci, Ci - 1, Ci - 1, #Ci + 1, Ci + 1 of the transfer circuit, and an OR gate 50, 51, 52 receiving the outputs of the output circuits. The logic elements or gates used in the units 100, 30<SP>1</SP>, 40<SP>1</SP>, 50 (Fig. 5) comprise a ferrotransistor cell (300, Fig. 6, not shown) which consists of a ferrite core (320) having five windings and a transistor (350) to the base of which is connected one lead of the output winding. The windings comprise two input windings (330, 331), an inhibitor winding (332) which prevents energization of the core when the winding receives a pulse, a transport or read winding (333) which switches the core to a logical zero and receives the synchronizing clock pulses and the output winding (334). Logical unit 100 receives inputs Xi, Yi at gates 110, 120 which pass on the signal when enabled by clock pulse a 1 . The output of gate 110 passes to an input winding of gate 130 and to the inhibit winding of gate 140. Similarly gate 120 is connected to gates 130, 140 as shown. Gates 130, 140 are enabled by clock pulse b 1  and pass signals to gates 300, 400, gate 30 receiving inputs from gates 130, 140 on its input windings and gate 40 receiving inputs on two inhibit windings. Outputs from gates 110, 120 are also connected to flip-flops or trigger circuits 61, 71 of the asynchronous unit which can be reset by signal r. The outputs of these go to unit 201 which also receives Ci from the adjacent least significant unit 200 and performs the logical operations C i+1  = Ci(X i  + Y i ) + Xi Yi, the transistor circuit of the unit being illustrated in Fig. 9 (not shown). The outputs produced are C i+1  and #C i+1  which may be taken directly from the circuit illustrated or may be applied to a Schmidt trigger circuit (Fig. 10, not shown) each stage of which is connected to the inhibitor windings of gates 300, 400. In either case the outputs Ci, #C i  are connected to the inhibitor windings of gates 300, 400 respectively. The outputs of gates 300, 400 enabled by clock pulses a, are then combined in OR gate 500 enabled by clock pulse b 2 . In operation, a two phase clock is used (Figs. 7, 8, not shown) pulses b, b 2  being interlaced between pulses a 1 , a 2 , a 3 . Pulses Xi, Yi are passed through gates 110, 120 and to flipflops 61, 71 at time a 1 . Pulses pass gates 130, 140 at time b 1 , and gates 300, 400 at time a 2  at which time the reset pulse r resets the flip-flops 61, 71, the operations requiring the output of the asynchronous unit being complete by then. The pulses finally pass gate 500 at time b 2 . If an exclusive OR operation is to be performed instead of an addition, for purposes of comparison, then the reset pulse r is applied at the same time as pulse al (Fig. 8, not shown) causing the inputs to unit 201 to be zero and enabling only the gate 400.