Patent GB-1014635-A (GB)
Title: Data processing system
IPC: G06F9/30
Filed: 1963-06-26
Abstract: 1,014,635. Electronic digital computers. RADIO CORPORATION OF AMERICA. June 26, 1963 [July 31, 1962], No. 25455/63. Heading G4A. In a computer, the elementary operations required to perform an instruction are controlled by " machine words " stored in the computer memory, thereby avoiding the necessity for wired sequence control circuits. The machine words can be handled in the computer in a similar way to the instructions, for instance direct and indirect addressing, conditional branching &c. can be used. In a modification, wired sequence control circuits can be provided for certain instructions required to be performed at high speed. Word format.-The computer described is of the 3-address type having an 18-bit word length. An elementary operation (machine word) consists of one 18-bit word and considered as 6-octal-digit word is of the form D6 D5 D4 D3 D2 D1 where D1 = 7 is a class digit, D2-D5 are control digits varying for the various elementary operations and D6 is an operation code specifying the type of operation to be executed. An instruction comprises four 18-bit words, including an operation word and three address words, the opera. tion word taking the form D6 D5 D4 D3 D2 D1 where D1 = 0 is a class digit, D2-D4 are control digits and D5, D6 are the operation code. General arrangement.-As shown in Fig. 2, the computer comprises a conventional magnetic core memory 1, input-output elements 4, processing circuits 5, an instruction control counter (IC) 6, an instruction register (IR) 12 and staticizing control circuits 16. To control the elementary operations, there are provided an elementary control counter (EC) 20, an elementary operation register (EOR) 22 and elementary operation (EO) control circuits 24. The processing circuits include an 18-bit parallel binary adder. Operation.-The Specification describes the performance of a single programme, Fig. 7, comprising stages (A) to (E). Stage (A) is an instruction IN2 requiring the addition of a constant (1) to the operand M in a memory location, the result being registered in the accumulator (ACC) 124, Fig. 3D. Stage (B) is an elementary operation EO1 requiring the addition of the contents of the accumulator to another operand N, the result being returned to the accumulator. Stage (C) is an elementary operation EO2 transferring the accumulator contents to the memory work area. Stage (D) is an instruction IN1 which transfers the work area data to a write-out area. Stage (E) is an elementary operation EOO which stops the computer. The address of the first instruction IN2 is inserted in the instruction counter 6, Fig. 3A, from paper tape input-output equipment or from normal switches. The instruction IN2 is then read out in four cycles from the four successive memory locations it occupies, the contents thereof being directed to the instruction register (IR) 12, Fig. 3C, and the X counter (XC), Y counter (YC) and Z counter (ZC) registers, Fig. 3B, respectively. The addition instruction IN2 is performed by executing in sequence four elementary operations (EO) stored in the memory, the commencing address of the EO operation being defined by the operation digits in the instruction. Machine control is transferred from the instruction counter (IC) 6, Fig. 3A, to the elementary operation counter (EC) 20, Fig. 3A, and the elementary operation counter 20 and elementary operation register 22 are effective to control the retrieval from the memory and execution of these elementary operations. Thus the first elementary operation (EO) retrieved is 137077, digit D6 = 1 indicating that the EO is for setting a register, digit D5 = 3 specifying the register (in this case the X counter), which contains the storage address of the word to be placed in the receiving register. Digit D4 = 7 indicates that the transferring register is to be incremented by one unit. The receiving register (in this case the accumulator 124, Fig. 3D) is indicated by digits D3, D2 = 0, 7. The staticizing control circuits 16 are effective to produce the required control pulses. Thus decoder 58 produces a signal AXC (address with X counter) and subsequently an AND gate 61 is opened to generate a TXC (trigger X counter) signal, thereby incrementing the X counter by one unit. The effect of the first elementary operation is to read out the constant (1) to the accumulator 124. The second elementary operation effects the addition of the operand M whose address is in the Y counter, Fig. 3B, to the constant (1) in the accumulator, by means of the adder 116, Fig. 3D. The third elementary operation stores the accumulator contents in the memory location specified by the Z counter, but the accumulator is not reset. The fourth elementary operation EO4 is the last elementary operation for the " add " instruction and causes the next instruction in the programme to be read out. This instruction, stage (B) of the programme is in fact itself an elementary operation and is detected as such by a circuit 48, Fig. 3C, which senses the class digits in the instruction register so that the elementary operation control circuits are effective. The remaining programme stages are performed similarly. The use of elementary operations as well as instructions in the computer programme, effects the equivalent of single address operation using an assumed address (the X, Y or Z counter). Modifications.-As shown in Fig. 13, an instruction control module 220 comprising a permanent matrix array of diodes or read-only magnetic elements may be provided to control the sequencing for one or more instructions which it is required to execute at high speed. In another embodiment, Fig. 16, two separate memories with interlaced operating cycles are employed, the first memory 250 storing instructions and data and the second memory 252 storing elementary operations, the elementary operation memory 252 being arranged to be read when the first memory 250 is in the regeneration portion of a read cycle. In a further embodiment (Fig. 17, not shown), instruction words have twice as many bits as an elementary operation word and two EO words are read out simultaneously from the memory to separate elementary operation register, a switch including 18 AND gates being employed to selectively connect one of the registers to the EO control circuits.