Patent GB-1218529-A (GB)
Title: Improvements in or relating to redundancy reduction systems
Inventor: MOUNTS FRANK WILLIAM
IPC: H04N21/236
Filed: 1969-07-30
Abstract: 1,218,529. Television. WESTERN ELECTRIC CO. Inc. 30 July, 1969 [2 Aug., 1968], No. 38220/69. Heading H4F. Transmission apparatus for reducing the redundancy in a video signal consisting of frames and lines, Fig. 8, comprises sampling means 330, Fig. 3, a frame memory 104, Fig. 4, for storing a complete frame of samples, means 105, determining whether a difference exists between each real time sample of said signal and its stored counterpart in said memory 104, a buffer memory 115 for storing real time samples for transmission, means 403, 406, 407, 411, 412, for writing a real time sample into said buffer memory if a said difference is found to exist, means 309 defining each sample's position address in a line and for writing (121) into said buffer the said address of said written-in sample, means 328 and 323/120 for writing the addresses of the first sample of a frame and the first sample of each line in said buffer memory as they occur, and means 414, 415 for reading out the samples and addresses stored in said buffer memory and coupling them to a transmission channel 419, 127. The total picture frame, Fig. 8, comprises 183 lines, 171 of which form the picture and the rest (12) are used for the frame flyback, and each line is divided into 140 picture elements or sample areas, of which 120 comprise the visible (active) portion and 20 are used for the line flyback. The horizontal and vertical sync pulses (324, 329) as well as the line samples are defined by two 8-stage counters 309, 319, the former being fed with the sampling pulses # from clock 308. The first 7 stages of counter 309 sequentially produce address words 0 to 120 for the active line samples and these are fed via OR gate 353 to buffer memory 115. The state that all 8 stages equal 0 represents the start of a line and is detected by logic gate 323, the output therefrom being fed to the camera horizontal sync circuit 324, to AND gate 327 and to AND gate 407 via OR gate 406. Counter 309 resets to zero at the count of 140 and the reset pulses are fed to counter 319 which resets at 183 and produces a " first line " (all stages equal) 0 signal from logic gate 325, to produce a start of frame signal which is fed to the camera vertical sync circuit 329 and also to AND gate 327. Gate 327 thus produces a signal defining the first picture element or sample in the frame and causes the generation by means 328 of a unique seven bit "start of frame" word for transmission via OR gate 353 to buffer memory 115. The reset signal # f  of counter 319 is at the frame rate, and sets a bi-stable circuit 338 at the beginning of the frame. Circuit 338 is reset at the end of the 171st line by AND gate 343 receiving the reset signal of counter 309 and the output of logic gate 342. A bi-stable circuit 339 is likewise set at the beginning of each line and reset at the end thereof. The outputs of the bi-stable circuits are fed to AND gate 337, to produce a signal defining the active region of the frame. Such signal enables AND gate 407 to pass through the start of line signals from logic gate 323 to the " write " instruct input of buffer memory 115. The address of each line start as well as the start of frame word are thus fed into memory 115 on seven of its fifteen available channels. The camera video signal is sampled at 330 and the analogue samples are converted to an eight bit P.C.M. digital format in encoder 331. The digital sample is fed to input M of subtractor circuit 105. Input N of circuit 105 is fed with the corresponding digital sample from frame memory 104 (an eight strip acoustic delay line having a one-frame period delay). If there has been a change in the sample from the previous frame to the present, circuit 105 produces a proportional signal. If this change is significant (as explained later) control logic produces a signal P which, via OR gate 406 and AND gate 407 enables the " write " instruct import of the buffer memory 115 whereby the " updated " video sample is written into the buffer memory. Signal P also enables AND gate 401 so that the " up dated " video sample is fed to the frame memory. If no change has occurred in the sample, inhibited AND gate 410 is enabled whereby the output of the frame memory is fed back to its input for restorage. The clock pulses # are given a system delay at 344 and fed as pulses # 1  to the digital transmitter 419. As a band compression ratio of fifteen is chosen, every fifteenth # 1  pulse is fed by transmitter 419 to the " read " instruct input of the buffer memory so that whole " words " of fifteen bits, i.e. 8 bits video sample and 7 bits address are read out of the buffer memory in parallel into store 415 via gate 414, and thence into transmitter 419. In transmitter 419 the parallel data is converted into serial data. In order that the reduced transmissions rate, i.e. one fifteenth the sampling rate shall not produce undue degradation of a fast moving picture, i.e. one changing from frame to frame and that the buffer memory 115 does not get overloaded by such a picture, the " threshold " that the difference or change signal from circuit 105 must attain such that control logic produces a signal P is greater the nearer memory 115 is to full capacity. The fullness of memory 115 is determined by forward-backward counter 404, counting forward every write pulse and backwards every read pulse. This variation of the probability of omission of Signal P is shown diagrammatically in Fig. 10 e.g. if there are between 2048 and 4096 words in buffer memory 115 then there must be a difference signal indicated by circuit 105 greater than 4. Also if there are less than 128 words in buffer memory 115 then a signal P will be produced and a sample written into the memory even if no difference between consecutive frames is detected. This ensures an average content of one fifteenth that of frame memory 104. At the receiver, Figs. 5 and 6, the serial fifteen bit signal is received and converted into a parallel bit format by receiver 500. The fifteen word bits are fed on one line 501 to a buffer memory 203 for writing therein. Line and frame counters 509 and 519 operate the same as counters 309 and 319 respectively and are fed with pulses # synchronous with the sampling pulses #. Pulses # w  at the rate of #/15 are produced by receiver 500 when a whole word is available and causes the write-in of said words into said buffer memory 203 by means of the buffer " write " instruct input. A counter 204 detects when memory 203 is full and then allows the commencement of the readout of the memory. A readout word is held in bi-stable store 615 and its address is compared at 645 with the address output of OR circuit 562. The first compared address will be the start of frame word and when this is established, comparator 645 enables gate 644 via gate 646 and causes the readout of the next word from the buffer memory 203 into the store 615. The video sample section of the word (i.e. bits 1 to 8) stored in 615 is fed to the reproducer 222 via gates 644, 652 and decoder 218 when its address is reached by counter 509, the sample thereby being placed in its correct position in the displayed frame. The video sample also passes to up-date the contents of frame memory 216. In the intervals when the video sample address in store 615 is not equalled by the output of OR circuit 562 (i.e. an average 14/15 of the time) gate 644 is disabled but gate 647 becomes uninhibited whereby the video sample at the output of frame memory 216 is recirculated to its input for restorage and display by the reproducer 222. At the beginning of operation of the system frame memories 104 and 216 must have equal contents for a frame change difference detected at the transmitter to give the correct picture at the receiver. Thus at the beginning of operation, generator 332 is activated, this causing bi-stable 335 to be set for one field period and word generator 347 to generate 1 bits on all eight channels into the frame memory 104 for said one field. Clear word generator 418 is also activated which thereupon feeds a characteristic signal (all 1 on all fifteen channels). This signal is detected at the receiver by detector 504 which causes word generator 603 to similarly fill frame memory with #1 bits.