Patent GB-1101295-A (GB)
Title: Improvements in or relating to apparatus for relaying information
IPC: G06F13/22
Filed: 1966-02-28
Abstract: 1,101,295. Input-output control for data processors. BURROUGHS CORPORATION. 28 Feb., 1966 [1 March, 1965], No. 8716/66. Heading G4A. The invention relates to data transfer between a central station and a plurality of remote inputoutput units. Window machines for bank tellers are associated in groups with terminal units, each of which communicates via telephone lines with a respective channel control unit. The channel control units communicate via a central control unit with a data processor. The teller inserts a passbook into his window machine, and keys in the account number, previous balance, and amount to be deposited or withdrawn. This information is transmitted to the data processor which up-dates the balance and calculates the interest, the resulting information being transmitted back to the window machine which prints it in the passbook. Central control unit (e.g. Fig. 5).-An S- counter is provided for selecting, CDS-1 to CDS-6, the channel control units in turn and concurrently selecting associated pairs of buffers, i.e. planes in a core memory 50. A flipflop SIF selects the odd or even plane (buffer) of the selected pair and an X-register selects a 12-bit column of the selected plane. An O- register contains the order currently being executed, a P-register counts the number of clock periods so far gone through in executing the order once and a Q-register counts the number of times the particular order has been executed. The core memory 50 is used as a buffer between the channel control units and the data processor and also stores control data, viz. (Fig. 6, not shown) settings for the oddeven flip-flop SIF and the O, Q, and X-registers and a Z-register, window machine addresses (WMA), parity characters and status bits. The status bits (two per channel) indicate whether the (core-plane) buffer is in input (00), output (01) or system (10) status, the first two referring to communication from a window machine to the central control unit and vice versa respectively, and the last referring to communication between central control unit and data processor. A 3-character (i.e. 12-bit) D-register 60 is provided for read-out and read-in of the core memory 50. The S-counter is incremented by control pulses provided at least one channel is not busy, " ACANS " and the channel currently selected is busy, " not-CANS," to select successive channels. As a channel is selected, the status of its two buffers is examined (Fig. 8, not shown, in which A and B are the buffers) and the channel polled for input or output unless both buffers are in system status. During the examination, an E-register, provided for holding the window machine address, is incremented by one, if the result of a comparison indicates this to be necessary to prevent both buffers relating to the same window machine address. Polling involves sending a window machine address, followed by a control character which interrogates the window machine to see whether it is ready for input or output as the case may be, followed by a parity character. If the window machine is ready, it returns the same message, whereas if it is not another (" not ready ") control character is substituted in the return message, causing polling of other window machines to commence, a bit Q8 in the Q-register being set to indicate this. In the input case, if the window machine is ready to send data, three characters are sent from the central control unit again but with the control character being a transmit command. The output case is similar but the control character is a motor bar code to position the printer carriage in the window machine, and 12 data characters may also be present in the message whether these are present or not being indicated by a particular bit in the motor bar code. An order causing the transfer of one character is executed only once before the other window machines are polled, the character position in the D-register to provide or receive the character being indicated by the Z-register. When a given window machine is left, the contents of the X- and Z- registers are stored in the core memory 50 to specify the position in the message reached. The Z-register can be incremented, and its overflow increments the X-register. The X, O and Q-registers, besides being settable from the core memory 50, can be selectively set from control circuitry, and their contents can be stored in the core memory. The P-register can also be selectively set by control circuitry. Channel control unit (Fig. 2, not shown).- This includes a one-character buffer (B REG) which communicates with the central control unit, parallel by bit, and with the corresponding terminal unit serial by bit, the buffer gating for the latter mode being controlled by a counter (430). Terminal unit (Fig. 13, not shown).-A onecharacter input register (504) is provided on the channel side, together with registers for the window machine address (512), control character (514) and parity character (516). A buffer register (502) is also associated with each window machine. A sequence control unit (508) is under control of the control character register (514), the latter register being settable by control circuitry as well as by characters received from the channel. Error features.-Parity checking is provided in the terminal units in which the poll is ignored in the case of parity error as it is if two consecutive window machine addresses received from the central control unit are not equal. The terminal units also detect reception of control characters which are incorrect for the current status of the terminal units, giving an alarm and sending the " not ready " control character to the central control unit. If data is received correctly at a terminal unit, it turns off the telephone carrier to signal this fact. In the central control unit, parity checks are also made. In addition, returned window machine addresses are compared with those sent out, a bit Q4 being set in the Q-register to indicate error if unequal. This bit is also set if a control character returned is not one which could properly result from the control character sent out.