Patent GB-954082-A (GB)
Title: Improvements in or relating to automatic telephone exchange apparatus
IPC: H04Q3/54
Filed: 1961-07-07
Abstract: 954,082. Automatic exchange systems. PHILIPS ELECTRICAL INDUSTRIES Ltd. July 7, 1961 [July 12, 1960], No. 24668/61. Heading H4K. In an automatic exchange each line circuit, such as LSL 1  (Fig. 1), has a signal wire, such as 1 1 , over which the state of the corresponding line is passed to a subscriber's memory A.G. in which the instantaneous state of each line is recorded on an element, such as core 21, individually associated with the line, this element together with a number of further store elements of the memory AG (cores 3 1 , 4 1 , and 5 1 ) individually associated with the line storing the state of the subscriber's set, such as " free," " requires dial tone," " busy." These elements are scanned and the information stored therein is read cyclically to a logical member LO which informs the common control circuit of actions needed, and updates the states of the subscriber sets in the memory accordingly. The scanning may be interrupted by the common control circuit which then requests the logical member to determine the state of a particular subscriber set and the response of the logical member on receipt of information as a result of the scanning of the memory differs from that on receipt of information read from the memory in answer to a request by the common control circuit. The cores associated with the line circuits LSL 1 , LSL 2  . . . LSLn are scanned in that order under control of the counting circuit SR, which applies a read pulse to all the cores associated with a line circuit LSL 1  at time t 1  and a halfwrite pulse to the 3 1 , 4 1  and 5 1  cores at t 5 . The core 2 1  is set to the " 1 " state by the line loop current. At t 1  the state of the subset Ab 1  is thus read into the logical member LO, " 1 " from core 2 1  denoting " line loop closed " and the states of 3 1 , 4 1  and 5 1  denoting in a 2-outof-3 code the remainder of the information. The logical member LO applies half-write pulses at t 5  to the relevant cores of 3 1 , 4 1 , 5 1  to write the same state back into the memory except when the state read indicates " requires dialling tone," in which case the state " is dialling or is busy " is written back and the common control circuit is signalled to apply dialling tone; or indicates " has replaced handset after having lifted it and being registered as not dialling," in which case the state " free " is written back. If the common control circuit wishes to know the state of a particular subset, as for example when that set is called, it sends the identity of the subset concerned to the counting circuit SR which suspends normal scanning and causes the stores of that subset to read out to the logical member to which is also applied a pulse at t 3 . In addition to its writing functions the logical member then signals the " free " or " busy " state of that subset to the common control circuit. Logical member LO (Fig. 9).-This member employs so-called " storing pulse generators " such as that indicated by the symbol at 26, having at least one setting terminal indicated by a cross-line in the lead thereto, an input terminal and an output terminal. Such a generator supplies an output pulse (fires) only when first a setting pulse of correct polarity and adequate amplitude is applied to the, or each, setting terminal and then a pulse of the correct polarity and adequate amplitude is applied to the input terminal. The setting of a generator which is already set is without effect, and a generator which has been fired cannot give another output pulse without being first re-set. An embodiment of such a generator (Fig. 7) includes a rectangular hysteresis loop core 101 and a PNP transistor 102, the voltages of sources B<SP>11</SP>+ and B<SP>1</SP>+ being such that 102 is normally non-conductive. Application of a pulse to the setting terminal 103 sets the core to state " 1 " ; application of a pulse to the input terminal 104 starts driving the core to the state " 0 " and the voltage induced in winding 109 renders the base of 102 negative with respect to its emitter. Transistor 102 conducts and delivers an output at its collector, the resulting current in the feedback winding 108 aiding the input pulse, and even replacing it if it ceases before the core has reached the state " 0." The output pulse has a sharply defined duration and amplitude substantially independent of the form of the input pulse. The logical member LO distinguishes between its two responses according as a pulse is, or is not, received from the common control circuit at t 3 . If this pulse is present the pulse generator 27 delivers a pulse v at t 4  ; if it is not, generator 26 gives an output pulse u at t 4 . If the loop is open (core 2 1  gives no output pulse), generator 28 produces a pulse x at t 4 ; if it is closed, generator 29 produces a pulse y at t 4 . The code group (000, 110, 101, or 011) is read from the cores 31, 41, 51 via pulse amplifiers 36, 37, 38. If the group is 000, the generator 31, set at t 6 , delivers a pulse at t 4 ; but if it is not, a pulse passes through the gate 30 at t 1  and fires generator 31, without effect. For the groups other than 000, the relevant generator of 32, 33, 34 delivers a pulse at t 4 . The group read from AG is thus converted into a pulse on one of the leads 39, 40, 41, 42, and the gates 43 to 50 and generators 51 to 54 convert this pulse and pulses x, y, u, v, if present, into the corresponding 2-out-of-3 code for storing on cores 56 to 65, from which the information is transferred to AG at t 5 . The pulse v from generator 27, if present, causes the necessary signals to be returned to the common control circuit.