Patent GB-1439579-A (GB)
Title: Digital speech detector
IPC: H04J3/17
Filed: 1974-06-18
Abstract: 1439579 Detecting pulse train characteristics INTERNATIONAL STANDARD ELECTRIC CORP 18 June 1974 [18 June 1973] 26928/74 Heading G1U [Also in Division H4] A speech detector for assessing whether speech, represented by PCM samples is present on a speech channel incorporates an instantaneous detector for determining whether the absolute values of individual quantized amplitudes of speech samples exceed a threshold and a system of count logic operating such that a counter is incremented or decremented, depending on whether the instantaneous detector indicates speech present above the threshold or not, the counter recording the cumulative effect of taking successive samples. When the count exceeds a given value a signal indicating that there is speech activity is delivered, and when it subsequently falls below a value lower than the given one, a different signal indicating an absence of speech activity is delivered. The detector is for use in a TASI system which will be outlined first. TASI system Fig. 2. 48 speech channels in the form of 6 bit PCM samples in the time slots of a TDM frame are applied to interface circuits and serial/parallel converter 8 so that the PCM samples can be applied in parallel form to the speech detector 9. In this the instantaneous samples are compared with threshold levels (see below). Speech activity on the particular sampled channel is recorded by a status word relating to the channel held in a status memory 10 which stores data relating to the samples taken from all the 48 channels. The status word, which consists of an integrated count related to successive samples of a particular channel, passes to an activity simulator 11, which recognises an active channel and passes a signal to an assignment control circuit 13. By means of the simulator, random or steady activity of channels selected from the front panel 12 can be simulated. The assignment control circuit controls the connection of the 48 input PCM channels to the 19 outgoing TASI channels, the particular channel assignments being stored in the assignment memory 14. The speech codes for the different input channels are passed from the interface 8 to the speech memory 15 where they are stored in locations determined by the assignment memory 14. The speech codes for the different input channels are passed from the interface 8 to the speech memory 15 where they are stored in locations determined by the assignment memory 14. If no TASI channel is assigned, a blank is delivered by the assignment memory and the PCM code is not stored. The codes stored in the memory 15 are read out in the TASI sequence, pass through an elastic memory 16 which corrects timing variations and thereafter are multiplexed with an overhead channel carrying the data relating to the TASI assignments and frame sync, converted to serial form and passed via an interface to a transmitter. At the receiver, the 19 channels transmitted are recovered and assigned to appropriate ones of the 48 PCM channels in accordance with the assignment information transmitted in the overhead channel. Noise from an idle noise generator is applied to the remaining 29 channels. Speech detector Figs. 25, 39A-B, D. The speech detector is arranged to operate at very low speech levels (-32dbmO), to operate for a minimum of time on line noise and to minimize the number of times that a talker is switched. It has a fast response time (about 6msec) and a slow release time, corresponding to one speech syllable. Once operated, release is deferred. The reasons for the choice of the various operating levels, response and release times are extensively discussed in the specification. The parallel PCM pulses representing a given speech sample are first converted to absolute value by means of an exclusive OR operation with the inverted sign digit and then applied to a comparator 81, wherein the sample is compared with a PCM word set by a threshold patch 80 and representing a level in the region of -32dbmO. An output representing speech activity if the absolute value of the PCM speech sample is greater than the threshold is delivered to the D input of a D type flip-flop 83, where it is sampled by a 2304 KHz clock (operating at the TD bit rate). The flip-flop delivers a signal on its 'I' or 'O' output, depending on whether activity has been registered or not, to NAND gate 89 or 91. The pulses are used to increment or decrement respectively a count representing the cumulative effect of previous speech samples in accordance with the mode of operation shown in Fig. 25. Once a minimum count, indicated by line ACEGH is reached, samples indicating activity cause the count to be incremented rapidly, as shown by slope S 1, until a threshold B is reached. The speech detector circuit delivers a signal at this threshold to the assignment control circuit, Fig. 2 requesting a TASI channel. Following this threshold, further samples indicating activity increment the counter more slowly (slope S3) until a maximum count is reached at F. Should inactive samples be obtained during the S 1 period, the count is rapidly decremented (slope SO). Should inactive samples be obtained after the turn on threshold has been reached, but before the maximum count, the counter is rapidly decremented (slope-S2) and if this reaches the minimum count, the activity signal to the assignment control is turned off, thus freeing the TASI channel. If inactivity is detected following the maximum count, the decrement rate is relatively slow (slope- S4), and increments would also be slow after this time (slope S5). To achieve this operation the status memory 10, Fig. 2 holds for each speech channel, in addition to the absolute count value representing the cumulative effect on the count of previous samples, status bits indicating the relationship of the count to the different thresholds and thus the count rates corresponding to the slopes in the different count modes S1/SO, S3/S2, S4/S5. These status bits are applied to gates 84-87 to enable either a 2000pps or 500pps bit stream, generated from the 2304KHz clock by counting and gating logic as in Fig. 39C to be passed to the gates 89, 91, depending on the appropriate mode, so that a related number of pulses from the D type flip-flop 83 will be passed. The up and down pulses are applied to the up-down adder 124 whose output is transferred to the status memory. The contents of the status memory are compared in comparator 121, 90 with the maximum count, to provide an output closing the up gate 89, so that further up counting does not occur. They are also compared with the appropriate threshold level in comparators 118, 155, from which a signal indicating that a threshold has been reached during an up count is delivered to gates 97, 96, by means of which, in appropriate combination with status bits, a signal requesting a TASI channel is sent to the assignment control. The contents of the status memory are also connected to gates 92, 93 so arranged that when the count falls to the minimum value, this is detected and a signal delivered to gate 100 to turn off the request signal and to the gate 91 to prevent further counting down.