Patent GB-1162366-A (GB)
Title: Improvements in Time Division Multiplex Electrical Signalling Systems
Inventor: MUMFORD HOWARD
IPC: H04J3/06
Filed: 1965-12-13
Abstract: 1,162,366. Multiplex pulse code signalling. BRITISH TELECOMMUNICATIONS RESEARCH Ltd. 12 Dec., 1966 [13 Dec., 1965], No. 52857/65. Heading H4L. In a time division multiplex P.C.M. system employing a plurality of exchanges, timing of signals outgoing from an exchange is effected by a timing clock which is arranged to be adjusted in discrete steps dependent on the amount of information in a store which records the incoming signal elements at a speed dependent on their speed of arrival and from which retransmission takes place at a speed determined by the clock. As described, there are twentyfive 8-bit channels and each frame includes a synchronizing signal which in its normal form is the 8-bit sequence 01111110. Loss of synchronism is avoided by adding one bit to or subtracting one bit from the sync. signal so that it may take the form 011111110 or 0111110. Receiving clock; detecting the sync. signal.- Incoming signals in alternating binary form are rectified at SR, Fig. 6, and control a toggle ML whose output L is fed to the store, Fig. 9, both outputs L and L being used as control signals. Pulses Sr at the digit repetition frequency are extracted at DR to control the receiving clocks which consist of an 8-state ring counter MA to MD producing outputs R1 to R8 and a 25-state channel clock RCF, Fig. 7, which in the position S (the sync. channel position) gives an output C s- . If any 0's occur during the sync. channel position other than during periods R1, R8, toggle ME will be set via gate G1 and during the next period R1 when Cs is not present, toggle MF is set via gate G2 to provide an output F and ME is reset. When clock RCF completes another cycle, if a 0 is received during any period except R8, on position S outputs are obtained from gates G3 and G4 which preset toggles MA to MD to the state corresponding to R1 and when a 1 is next received the clock is allowed to run normally as long as 1's are received. However, if another 0 is received the clock is returned to the R1 state. When five successive 1's are received, the clock is on state R6 (MA, MB reset and MC, MD set). If the seventh digit is a 0 it is regarded as the final digit of a shortened sync. signal and output L via gate G4 resets toggle MD, so that on the next pulse S p  the clock omits the R8 stage and moves to R1. However, a pulse R8 is required to drive the channel clock RCF and this is provided via gate G5 and at the same time the pulse R7 is suppressed. If the seventh digit is a 1 MD is not reset and the pulse R7 is supplied via gate G6, gates G5 and G7 being blocked. If the eighth digit is a 0 this denotes the end of a normal sync. signal and MD is reset via gates G8, G9, the pulse R8 is produced via gate G7 and the clock moves to the R1 state. If the eighth digit is a 1 MD is not reset and the clock remains in state R8 until a 0 is received and a pulse R8 is produced and the clock advanced normally, toggle MF being reset via gate G10. Toggles ME and MF provide a flywheel effect so that hunting for the sync. pattern takes place only in response to the reception of more than one incorrect digit. Exchange clock, Fig. 8.-The eighth state T8 of a counter MZ to MW producing pulses T1 to T8 gates a clock pulse Sx derived from a stable oscillator SG to drive a 25-state channel clock ECF and also a 3-state channel clock ECT which is to provide junction delay compensation. In position S of clock ECF a signal QS is obtained. Pulse T1 of the clock MZ to MW presets the toggles MY to MW each time the clock reaches the T1 state and the next pulse Sx drives the clock to the T2 position and the presetting signal is removed. In certain cases it is necessary to suppress or duplicate the pulse TY in the period of signal QS. To duplicate TY the toggle MV is set in a manner to be described, there is no input to OR gate G13 and gate G11 is blocked and MX is not reset. Toggle MV is reset at the next timing pulse via gates G14, G15 so that MX is reset and the clock resumes its normal operation. To suppress TY toggle MV is set and during state T6 toggle MX is reset via gate G16 so that the clock moves from T6 to T88. Delay compensation.-In order to compensate for variations in transmission time due to temperature variations a 3-state clock RCT, Fig. 7, comprising toggles MG, MH controlled by pulses R8 and supplying pulses J1, J2, J3 co-operates with the 3-state clock ECT to ensure that signal elements are assigned to definite positions in the store (Fig. 9) and read in correct sequence. Initially, the first pulse C s  from the receiving channel clock RCF in general will not coincide with pulse J1 and toggle MN will be set via gate G17. The next time Qs coincides with P1 (which must be within 3 channel periods) toggle MM is also set via gate G18 and the outputs of toggles MN and MM set the clock RCT to state J2 via gate G19. When Cs occurs again, MM is reset and the clock RCT continues its cycle and on the occurrence of R8 at the end of the C s  period changes to state J3. Thus C s  now coincides with J2, position 1 of RCF with J3, position 2 with J1 and so on. Due to the pre-arranged signal delay Q s  occurs soon after C s  and coincides with P2, position 1 of ECF coincides with P3, position 2 with P1 and so on so that the " J " pulses have been put into the same relationship with the pulses from RCF as the " p " pulses have with the pulses from ECF these leading the pulses from RCF by less than three channel periods. The next time Q s  coincides with P1 toggle MM is set again but does not adjust the clock RCT because MN has been reset by the coincidence of C s  and J immediately before. After one cycle of the clock RCF toggle MM is reset and MN set but this also does not affect the clock RCT. Signal store.-The received binary signals L are gated sequentially by pulses J1, J2, J3 and then by pulses R1 to R8 digit by digit into the storage locations SL, Fig. 9, and are read out similarly by pulses P1, P2, P3 and T1 to T8. The output signals control a toggle MI which is reset by pulses Sx and the output of toggle MI is retimed by a toggle MK under the control of pulses Sx. Since MK introduces a delay of one digit this is corrected by reading out by pulses P1 and T8 the digits gated in by pulses J2 and R1 and so on. If the incoming signal rate is lower than the exchange digit rate the digits will be read out faster than they are written in and when a state is reached in which the digits are being read out less than four digits after being written in this is detected by gate G20, Fig. 8. A signal W is obtained from the exchange clock during states T1 to T4 and if this signal is present during period P1 the gate is primed. If pulse R5 in period J1 occurs while the gate is primed the toggle M will be set to cause state T7 of the exchange clock to be duplicated as previously described. If the digts are being written in faster than they are being read out this is detected by gate G21 also primed by W and P1. A pulse R2 occurring in period J1 1 when the gate is primed will set toggle MU to cause state T7 of the clock to be suppressed as described previously. Gates G20, G21 will be provided for each incoming signal path and connected via OR gates to control the toggles MV, MU respectively. In the outgoing signal the existing sync. signal pattern is removed by the first pair of gates following toggle MK, Fig. 9, and the second set of gates introduces 1's for all digits other than T1 and T8. If the sync, signal has been shortened or lengthened this will be reproduced in the outgoing signal.