baber/WOPTO huggingface dataset:
Patent TW-408116-B (TW)
Title: Carbapenem intermediates 1, 8-naphthosultams and preparation thereof
Inventor: HUMPHREY GUY R
IPC: C07C311/16
Filed: 1998-05-11
Granted: 2000-10-11
Abstract: A process for synthesizing a compound of formula I: is disclosed wherein R represents halo or C1-6 alkyl, unsubstituted or substituted with OP, wherein P represents a protecting group, comprising: (a) reacting a compound of the formula II: with chlorosulfonic acid to produce a compound of formula III: (b) reacting compound III with NHRaRb, wherein Ra and Rb represent H or C1-6 alkyl, to produce a compound of formula IV; (c) reacting compound IV with HNO3 to produce a compound of formula V: (d) reacting compound V with a reducing agent to produce a compound of formula VI: and (e) reacting compound VI with acid to produce a compound of formula I. Intermediate compounds that are useful in the synthesis of carbapenem side chains are included as well.
Patent TW-400651-B (TW)
Title: The semiconductor device with high voltage CMOS structure and the manufacture method thereof
Inventor: KOBAYASHI KIYONARI
IPC: H01L29/786
Filed: 1998-10-20
Granted: 2000-08-01
Abstract: This invention discloses a second electrically conductive transistor with an LMOS structure, and a first electrically conductive transistor with an LDMOS structure, among which the first electrically conductive transistor has a drain-base layer, whose function is the same as that of a drain offset diffused layer, and is formed individually on the substrate from a source-base diffused layer. The first electrically conductive transistor, the same as the second electrically conductive transistor, has a stable breakdown voltage and a low on-resistance.
Patent TW-I249410-B (TW)
Title: Enteric coated pharmaceutical extended release dosage form of a H+, K+-ATPase inhibitor
Inventor: KAREHILL PER-GUNNAR
IPC: A61P1/04
Filed: 1998-12-09
Granted: 2006-02-21
Abstract: An enteric coated pharmaceutical extended release dosage form of a H+, K+-ATPase inhibitor giving an extended plasma concentration profile of a H+, K+-ATPase inhibitor. The extended plasma profile is obtained by a pharmaceutical composition which comprises a core material of a hydrophilic or hydrophobic matrix, and the H+, K+-ATPase inhibitor and optionally pharmaceutically acceptable excipients. The dosage form may be administered once daily.
Patent TW-403931-B (TW)
Title: Electron emitting apparatus, manufacturing method therefor and method of operating electron emitting apparatus
Inventor: OKITA MASAMI
IPC: H01J3/02
Filed: 1998-12-31
Granted: 2000-09-01
Abstract: An electron emitting apparatus having excellent mechanical strength and capable of satisfactorily emitting electron even if a high electric field is applied and a manufacturing method therefore are disclosed. The electron emitting apparatus according to the present invention incorporates a first gate electrode formed on a substrate, a cathode formed on the first gate electrode through a first insulating layer and having a projection projecting over the first insulating layer and a second gate electrode formed on the cathode through a second insulating layer. The electron emitting apparatus has the cathode structured such that the projection has an inclined surface, the thickness of which is reduced toward the leading end.
Patent TW-419642-B (TW)
Title: Display device and its driving method
Inventor: FUJIYOSHI TATSUMI
IPC: G09G3/20
Filed: 1999-02-06
Granted: 2001-01-21
Abstract: The subject of the present invention is to provide a display device that can miniaturize the respective device without any significant increase in the production cost and achieve the optimum effect in the reduction of power consumption by switching between the driving methods. The ultimate solution to the present invention is a display device having the characteristics described as follows: an adding machine 14 for adding digital signals for one picture plane by receiving and adding one image element at a time the digital signal of each picture element to compose an image signal for one image plane, and a comparator for comparing the result of addition for the digital signal to compose the image signal of one picture plane before obtained by the adding machine 14 with the result of addition of the digital signal to compose the image signal of the present picture plane, inside its circuit, and moreover has an animation-stationary picture judging circuit 11 which, when the results of addition are different, the picture is judged to be an animation from the result of comparison, and when the results of addition are equal, the picture is judged as a stationary picture, and outputs a judging signal in compliance with the above judgment.
Patent TW-403937-B (TW)
Title: Exposure device and method of manufacturing semiconductor device
Inventor: TAKAHASHI TETSUO
IPC: G03F9/00
Filed: 1999-03-04
Granted: 2000-09-01
Abstract: The relative position between a mask and a wafer is adjusted at any time even during an exposure process by registering a displacement of a pattern image due to the position change a change in position of reflectors. The solving means comprise: detectors (13, 14) to detect the displacements of reflectors (M1, M2) from their respective reference positions. Based on the detected displacements, an arithmetic system (15) determines a corrective quantity for at least either a photosensitive substrate (4) or a mask (2) for effectively positioning the photosensitive substrate relative to the pattern image formed out of place. At least either the mask or the photosensitive substrate is moved according to the determined corrective quantity.
Patent TW-441009-B (TW)
Title: Passivation film structure and its manufacturing method
Inventor: LEE JIA-SHENG
IPC: H01L21/762
Filed: 1999-03-26
Granted: 2001-06-16
Abstract: The present invention provides a passivation film structure on a semiconductor chip. The semiconductor chip includes a dielectric layer, a patterned conductive layer formed on the surface of the dielectric layer, and a passivation layer formed on the surface of the conductive layer and on the surface of the dielectric layer that is not covered by the conductive layer. The passivation film includes a lower supporting layer, an upper supporting layer formed on the lower supporting layer, and a filling layer for filling up the gap between the lower supporting layer and the upper supporting layer. Because the lower supporting layer and the upper supporting layer can support the periphery of the conductive layer that is not covered, the electromagnetic force and twisting force applied on the conductive layer in electrical operation can be effectively eliminated.
Patent TW-374839-B (TW)
Title: Device and method for regulation of pressure for prevention of potential high voltage in pipelines
Inventor: Ceng heng-yi
IPC: F17D5/00
Filed: 1999-04-13
Granted: 1999-11-21
Abstract: This invention discloses a device and method of regulation of pressure for prevention of potential high voltage in pipelines generated by, when repairing a vacuum system, as formed by pumps, pipelines and reactor chambers, including the first gate valve, the second gate valve for opening or closing the pipeline, and the automatic release device. When the system is shut down, the first gate valve and the second gate valve would close both at the same time, with introduction of cleaning gas in this section of closed pipeline and installation of the automatic release device in the system, for the release of the pressure in the pipeline and over the safety standard. Based on this system, a method for proposal of a set of regulation of pressure in the pipeline preventing the potential hazards created by the pressure in the pipeline from causing damages.
Patent TW-403948-B (TW)
Title: Method of manufacturing a short-channel nMOSFET having a self-aligned silicide contact
Inventor: WU SHIE-LIN
IPC: H01L21/28
Filed: 1999-04-23
Granted: 2000-09-01
Abstract: This invention provides a method for manufacturing a short-channel nMOSFET device by a method of self-aligned silicide contact. Form an oxide layer on the substrate and deposit a non-doping polysilicon layer, and then deposit a first dielectric layer and a photoresist layer. Define the gate electrode area on the photoresist layer and etch the gate electrode area until its width shrinks into a size that the traditional photolithography process cannot make. The remains of the photoresist layer is used as a mask to etch the first dielectric layer, and then the remains of the photoelectric layer and the first dielectric layer are used as a mask to etch he non-doping polysilicon layer to form a short channel gate electrode. Then deposit a phosphorus silicon glass (PSG) film by chemical vapor deposition, and etch back to form a spacer on the sidewall of the PSG. Remove the first dielectric layer, deposit the noble metal or temperature-resisting metal on all areas. Arsenic or phosphorus ions of high concentration are implanted through the metal to the substrate to form the source/drain electrode area. A two-stage rapid thermal process (RTP) is performed to form a self-aligned silicide contact to produce a short-channel nMOSFET.
Patent TW-517077-B (TW)
Title: Inhibited metal pigment pastes containing molybdate pigments and suitable for aqueous coating compositions
Inventor: KEEMER CRAIG B
IPC: C09D17/00
Filed: 1999-06-04
Granted: 2003-01-11
Abstract: Metal particles useful for coating compositions, particularly aqueous coating compositions, are produced by treating the metal particles with a molybdate pigment. The molybdate pigment reacts with the surface of the metal particles. The molybdate pigment may be a salt such as a molybdate, phosphomolybdate or silicomolybdate salt, and the salt may include a multivalent cation such as calcium, strontium, barium, magnesium, zinc and aluminum. The metal particles show improved resistance to attack by water.
Patent TW-520363-B (TW)
Title: Process for the preparation of 4,6-disubstituted 2-isocyanatopyrimidines and process for using them as intermediates for preparing further processing products
Inventor: FORD MARK JAMES
IPC: A01N47/36
Filed: 1999-07-21
Granted: 2003-02-11
Abstract: Isocyanates of the formula (I) in which X and Y are defined as in formula (I) of claim 1 can be prepared by reacting a compound of the formula (II) or its salts in which X and Y are defined as in formula (I) with 1 to 6 mol of phosgene per mole of compound of the formula (II) in the presence of 2 to 3.5 molar equivalents of a base per mole of compound of the formula (II) and in the presence of an aprotic organic solvent at a reaction temperature in the range from -30 to +60 DEG C to give the compound of the formula (I). The compounds (I) can be converted by reaction with nucleophiles to give addition products, such as carbamates ureas and sulfonylureas and corresponding products, e.g. herbicidal sulfonylureas.
Patent TW-468343-B (TW)
Title: Interactive television program guide system that serves as a portal
Inventor: ELLIS MICHAEL D
IPC: H04N5/445
Filed: 1999-09-27
Granted: 2001-12-11
Abstract: A system is provided in which an interactive television program guide application and non-program-guide applications are at least partially implemented on user television equipment. A program guide program application interface is provided that is used to maintain a consistent user interface between the program guide application and the non-program-guide applications. Non-program-guide applications may be launched by the program guide application. The user may select certain non-program-guide applications as favorites and may set parental controls for certain non-program-guide applications. The program guide application may run in the background while a non-program-guide application operates. While the non-program-guide application operates, the program guide may check for events that require immediate attention. When such an event is detected, operation of the non-program-guide application may be suspended and the user may be asked whether the detected event should take place or whether operation of the non-program-guide application should be resumed. The applications may be located at a remote location such as on a server at a cable system headend or on a server on the internet. The program application interface may perform authentication and access rights determination functions. Reminders may be set for the content of non-program-guide applications.
Patent TW-441063-B (TW)
Title: Barrier layer used for preventing metal layer diffusion and its fabricating method
Inventor: HUANG MING-CHING
IPC: H01L23/52
Filed: 1999-09-02
Granted: 2001-06-16
Abstract: This invention is about the barrier layer of copper damascene process and its fabricating method, in which a compound layer is used to replace the conventional barrier layer. The compound layer is composed of a conventional barrier layer and a layer of porous material. The effects of increasing the suppression of copper atom diffusion can be obtained when porous material layer is formed either on top of the barrier layer or under the barrier layer. Better results are obtained when porous material layer is formed on top of the barrier layer.
Patent TW-479419-B (TW)
Title: Jig for the batch production of optical communication apparatuses, and method using the same
Inventor: KOH HAN-JUN
IPC: H01S5/022
Filed: 1999-09-20
Granted: 2002-03-11
Abstract: A jig for the batch production of optical communication apparatuses includes a jig body whose upper surface is provided with a plurality of U-shaped recesses arranged in a matrix array to receive silicon bases each carrying optical devices and a plurality of vacuum holes vertically formed through the jig body, to communicate with the respective bottom surfaces of the U-shaped recesses. The silicon bases received by the U-shaped recesses are held onto the bottom surfaces thereof when a vacuum is applied thereto through the vacuum holes. A method using the jig enables batch production by simultaneously processing many silicon bases.
Patent TW-442787-B (TW)
Title: Layout of pull-up and pull down devices for off chip driver
Inventor: SHIAU TZ-JE
IPC: G11C11/00
Filed: 1999-09-23
Granted: 2001-06-23
Abstract: This invention is about the layout of pull-up and pull down devices for off chip driver, in which it is not necessary to reserve layout space in between the adjacent pads such that layout area can be greatly diminished and the advantage of simple layout is obtained. In addition, when the distance between the disposed positions of pull-up driver as well as pull down driver and the corresponding pads is very large, the problem of causing the increase of layout area will not occur. Furthermore, since the way of layout of this invention can greatly shorten the layout length of conducting wire, signal transmission speed can be faster.
Patent TW-522317-B (TW)
Title: Subtitle display device of multi-language man-machine interface and method thereof
Inventor: JIAN JENG-BANG
IPC: G06F17/30
Filed: 1999-10-18
Granted: 2003-03-01
Abstract: The present invention relates to a subtitle display device of multi-language man-machine interface and a method thereof for memory space saving and easy program maintenance. Firstly, a bitmap data file for each individual character is created in accordance with the size and the symbol of the character before being converted into assembly language and stored as a character database. Then, contents of ""word string label name"", ""character assembly label name"", ""multi-language character assembly label name"", and the required character database of a control program are setup. In actual applications, the control program is used to call the required word string before determining the applied language and, in accordance with the characters contained in the required word string, finding the required characters one after the other in their respective order from the character database. Finally, the required word string is printed and displayed on a display screen.
Patent TW-473400-B (TW)
Title: Modified photocatalyst sol
Inventor: NAKABAYASHI AKIRA
IPC: C09D183/04
Filed: 1999-11-20
Granted: 2002-01-21
Abstract: Disclosed is a modified photocatalyst sol comprising a liquid medium having dispersed therein particles of a modified photocatalyst, wherein the modified photocatalyst particles are prepared by subjecting particles of a photocatalyst to a modification treatment with at least one modifier compound selected from the group consisting of different compounds each of which independently comprises at least one structural unit selected from the group consisting of a monooxydior-ganosilane unit, a dioxyorganosilane unit and a difluoromethylene unit, and wherein the modified photocata-lyst particles have a specific volume mean particle diameter. Also disclosed is a modified photocatalyst composition comprising the modified photocatalyst sol and a functional substance. Also disclosed are a film formed using the above-mentioned modified photocatalyst sol or modified photocatalyst composition, a functional composite comprising the film and a substrate covered with the film, and a shaped article produced by shaping the above-mentioned modified photocatalyst composition.
Patent TW-434839-B (TW)
Title: DRAM cell fabricated using a modifed logic process and method for operating same
Inventor: LEUNG WINGYU
IPC: G11C5/14
Filed: 1999-12-03
Granted: 2001-05-16
Abstract: A memory system that includes a dynamic random access memory (DRAM) cell that includes an access transistor and a storage capacitor. The storage capacitor of the DRAM cell is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. After the first set of the thermal cycles are complete, shallow P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide. The DRAM cell is operated in response to a word line driver that is controlled to provide a positive boosted voltage and a negative boosted voltage to the word line, thereby controlling access to the DRAM cell. The positive boosted voltage is greater than Vdd but less than Vdd plus the absolute value of a transistor threshold voltage Vt. Similarly, the negative boosted voltage generator is less than Vss by an amount less than Vt.
Patent TW-478922-B (TW)
Title: Method for maintaining aquaculture pond
Inventor: TZENG GUO-TANG
IPC: A01K61/00
Filed: 2000-01-10
Granted: 2002-03-11
Abstract: The present invention relates to a method for maintaining an aquaculture pond, which comprises: drawing out the water in the aquaculture pond; exposing the aquaculture pond under sunshine for a certain period of time; using an incineration truck to dig out the sludge at the bottom of the aquaculture pond, feeding the sludge into the incineration truck for incineration, and refilling the incineration residue back to the pond; filling the pond with fresh water, and using a heat treatment to convert the sludge in the pond into an organic fertilizer so that the sludge can be recycled for cultivating algae, fish and shrimp.
Patent TW-515074-B (TW)
Title: Integrated semiconductor memory arrangement with self-buffering of supply voltage
Inventor: CHRYSOSTOMIDES ATHANASIA
IPC: H01L27/105
Filed: 2000-01-18
Granted: 2002-12-21
Abstract: This invention relates to an integrated semiconductor memory arrangement with several memory cell arrays (1 to 8), they are connected to each other through low resistance power supply lines (11 to 14), which forms a power supply network. This power supply net work is connected to a voltage generator (9) through a high resistance supply line (10). For this activation, an activated memory cell array (for example 6) is supplied through self-buffering by the remaining memory cell arrays (1 to 5, 7 and 8).
Patent TW-439291-B (TW)
Title: Layout design of thin film transistor
Inventor: YANG JIAN-SHENG
IPC: H01L29/772
Filed: 2000-01-21
Granted: 2001-06-07
Abstract: A layout design of thin film transistor, which can avoid the problem of different regional luminosity on the liquid crystal display caused by stitching problem. It comprises a transparent insulative substrate on which the first gate electrode and the second gate electrode are disposed. The first gate electrode and the second gate electrode are disposed in parallel on the substrate and are connected with each other electrically. Then, the first symmetric source electrode and the second source electrode are disposed, wherein the first symmetric source electrode and the second symmetric source electrode are disposed in parallel on the substrate and are connected with each other electrically. The first symmetric source electrode and the second symmetric source electrode surround and clamp from the exterior the first gate electrode and the second gate electrode in a symmetric way, respectively. Thereby two thin-film transistors arranged in parrallel will be formed in each pixel, so that the misalignment in the horizontal or vertical direction can be mutually cancelled.
Patent TW-444343-B (TW)
Title: Manufacturing method of inter-level dielectrics
Inventor: JANG SYUN-MING
IPC: H01L21/768
Filed: 2000-02-22
Granted: 2001-07-01
Abstract: The present invention provides a manufacturing method of inter-level dielectrics, which is able to obtain a dielectric layer with a good gap filling capability and also avoid damaging the device by plasma charging. In accordance with the present invention, an undoped silicon glass layer is deposited by high-density plasma CVD. Then, a mobile ion gettering layer is deposited. If required, another undoped silicon glass layer can be deposited to make the subsequent CMP process easy.
Patent TW-454342-B (TW)
Title: Semiconductor memory device
Inventor: ITOU TAKASHI
IPC: G11C7/00
Filed: 2000-05-04
Granted: 2001-09-11
Abstract: The semiconductor memory device includes normal word lines, spare word lines and bit lines. Space between the spare word lines is made wider than the space between the normal word lines. Further, the space between the normal word line and the spare word line is also made wider. Thus possibility of contact defect caused by a foreign matter in the steps of manufacturing can be reduced. Further, the size of the storage node of a spare memory cell is made larger than that of the storage node of a normal memory cell. Thus capacitance of the spare memory cell can be increased. Thus possibility of defects in spare memory cells is reduced ensuring repairment.
Patent TW-463235-B (TW)
Title: Techniques for improving etch rate uniformity
Inventor: DAUGHERTY JOHN E
IPC: H01L21/302
Filed: 2000-06-28
Granted: 2001-11-11
Abstract: Improved methods and apparatus for ion-assisted etch processing in a plasma processing system are disclosed. In accordance with various aspects of the invention, an elevated edge ring, a grooved edge ring, and a RF coupled edge ring are disclosed. The invention operates to improve etch rate uniformity across a substrate (wafer). Etch rate uniformity improvement provided by the invention not only improves fabrication yields but also is cost efficient and does not risk particulate and/or heavy metal contamination.