Patent TW-201423402-A (TW)
Title: General purpose digital data processor, systems and methods
Inventor: FRANK STEVEN J
IPC: H04L12/933
Filed: 2012-12-12
Abstract: The invention provides improved data processing apparatus, systems and methods that include one or more nodes, e.g., processor modules or otherwise, that include or are otherwise coupled to cache, physical or other memory (e.g., attached flash drives or other mounted storage devices)-collectively, ''system memory.'' At least one of the nodes includes a cache memory system that stores data (and/or instructions) recently accessed (and/or expected to be accessed) by the respective node, along with tags specifying addresses and statuses (e.g., modified, reference count, etc.) for the respective data (and/or instructions). The tags facilitate translating system addresses to physical addresses, e.g., for purposes of moving data (and/or instructions) between system memory (and, specifically, for example, physical memory-such as attached drives or other mounted storage) and the cache memory system. Within one or more of the processor modules, an event table maps events-such as, by way of non-limiting example, hardware interrupts, software interrupts and memory events-to respective threads. Devices and/or software (e.g., applications, processes and/or threads) register, e.g., with a default system thread or otherwise, to identify event-processing services that they require and/or that they can provide. That thread or other mechanism continually matches those and updates the event table to reflect the best mapping of events to threads, based on the demands and capabilities of the overall environment. Processor modules permit application and operating system-level threads to be transparently executed across different devices (including mobile devices) and which enables such devices to automatically off load work to improve performance and lower power consumption. An event delivery mechanism delivers events-such as, by way of non-limiting example, hardware interrupts, software interrupts and memory events-to respective threads. A preprocessor (or other functionality), e.g., executed by a designer, manufacturer, distributor, retailer, post-sale support personnel, end-user, or other responds to expected core and/or site resource availability, as well as to user prioritization, to generate default system thread code, link parameters, etc., that optimize thread instantiation, maintenance and thread assignment at runtime. Arithmetic logic or other execution units execute selected processor-level instructions by encoding and storing to one (or more) of the register(s) a stripe column for bit plane coding within JPEG2000 EBCOT (Embedded Block Coding with Optimized Truncation). The arithmetic logic units may also execute selected processor-level instructions by storing to that/those register(s) value(s) from a JPEG2000 binary arithmetic coder lookup table. In addition, the arithmetic logic units may execute selected processor-level instructions specifying arithmetic operations with transposes by performing the specified arithmetic operations on one or more specified operands, e.g., longwords, words or bytes, contained in respective ones of the registers to generate and store the result of that operation in transposed format, e.g., across multiple specified registers. A processor module can include an arithmetic logic or other execution unit that is in communications coupling with one or more registers, as well as with cache memory. Functionality associated with the cache memory works cooperatively with the execution unit to vary utilization of the cache memory in response to load, store and other requests that effect data and/or instruction exchanges between the registers and the cache memory. The modules may execute pipelines of software components in lieu of like pipelines of hardware components of the type normally employed by prior art devices.