Patent GB-1255490-A (GB)
Title: Centralized vehicle traffic control system
Inventor: AUER JOHN HENRY JR
IPC: G08G1/081
Filed: 1968-12-19
Abstract: 1,255,490. Road traffic signalling systems. GENERAL SIGNAL CORP. 19 Dec., 1968 [19 Dec., 1967], No. 60456/68. Heading G4Q. A vehicle traffic control system for controlling sets of traffic lights comprises a master station generating a successive series of time spacing pulses to define the operational cycles and having means (Fig. 3), including a shift register 134 communicating to the sets of traffic signals a single train of pulses during part only of each operational cycle and means, including a pulse stretcher 131, for encoding part only of each train of pulses with control information by governing the duration of the pulses in part by the duration of the output of the pulse stretcher and in part by the output of the shift register and at each set of traffic lights decoding means (Fig. 7), including a receiving shift register 154, for separating the time spacing pulses from that portion of the encoded control information received, readout means 156 arranged to respond to each entire train of pulses and a controller 163 responsive to the readout means to control its associated set of traffic lights in accordance with the control information in respect of cycle time, split and offset. In the encoder of Fig. 3 the cycle time is obtained from a 60 c/s. source 125 feeding a Schmitt trigger 126, binary divider 127, and five and six stage binary counters 128, 137. The code read into each of these counters may be checked by code check circuits 129, 136 and the cycle can be selected by a cycle select circuit 149. Pulse generators 130 and 135 are energized by the code check circuits when the correct code is obtained so that the output from the six stage binary counter 137 provides pre-sync pulses which control via gates 138, 140-144 the entrance of information (split, offset and tag) into the shift register 134. The cycle time and coded information are passed from the 60 c/s. source 125 and register 134 to a pulse shaper 132 which under the control of pulse stretcher 131 and the output from the register 134 provide a normal short duration pulse at the output of shaper 132 with zero or clear state output from the register 134 or a longer duration pulse whenever other than zero bit pulse is transmitted into the last stage of the register 134. The control information is in the form of lengthened line pulses (Fig. 6, not shown). The last tag pulse from the shift register operates AND gates 145, 146 and 133 to prevent further shifting so as to indicate the end of the coded message has occurred. The output from the shaper 132 is fed via a two wire line or a radio channel to the decoder of Fig. 7. The decoder has a receiver circuit 150 which includes two timing circuits which may have RC networks in combination with unijunction transistors. One of these timing circuits is capable of producing an output signal upon occurrence of a pulse greater than a particular duration corresponding to the lengthened information pulses " B " while the other produces pulses corresponding to the cycle pulses " A ". These separated signals are fed via bi-stable 151, flip-flop 152 and AND gate 153 to read the information into shift register 154. When the complete code is within the register 154 it is read out by circuit 156 and the offset and split information is then stored for operation of the local signal controller 163. The system in accordance with the invention as described above forms a modification of a system incorporating an encoder and decoder (Figs. 1A and 1B, not shown). In such a system the encoder (Fig. 1A, not shown) has ring counters (13, 14) driven by cycle rate pulses " A " which are PFM and are reset to zero by sync. pulses applied via a reset (15). At appropriate counts the outputs from counters 13, 14 feed a shift register (10) to remove information stored in this shift register and to cause the required information on split and offset from (11) to be read into the shift register (10). Cycle rate pulses " A " advance the information in the register (10) and information in the last stage gives a binary " 1 " output to trigger a monostable multivibrator (22). At the end of the trigger pulse produced by (22) a further monostable multivibrator (23) is triggered to provide the output pulse " B " representing a Pulse Code Modulation (PCM) according to the information fed into the register (10). In the decoder (Fig. 1B, not shown), the first information " B " tag pulse resets a shift register (100).  The information " B " pulses are similarly read into the shift register (100) and advanced by the " A " pulses until the tag pulse is obtained in the last stage RJ. On the tag pulse then passing to the output of the shift register (100) on occurrence of the next " A " pulse the output from the register (100) then triggers monostable multivibrator (104) which resets bi-stables (116, 121, 122) providing offset and split signals to the local controller. Then at the end of the monostable period gates (105-113) read out the code stored in the register (100) to effect the split and offset control of the traffic signals. If a special offset switch (119) is closed then the NOT circuit (118) does not energize AND gates (108-113) so that only the special offset from gate (107) is used. If no offset information is present in the register (100) NOR circuit (120) energizes an output from a gate (115).