Patent ES-349577-A1 (ES)
Title: Cross point switching network in a telecommunication system
IPC: H04Q3/545
Filed: 1968-01-20
Abstract: A modular network has line switching frames each comprised of units serving groups of lines and having outlets separately grouped to serve each side of an associated junctor switching frame, each such junctor switching frame being comprised of switching units having an outgoing and an incoming section each outgoing section having access to all the incoming sections of all junction switching frames. Figs. 3 and 4 show the switch distribution of a single module. Line circuits LC and incoming junctions IJ are served by switch arrays A and A1, the switches being two-stage relay matrices and the switches for each group of lines served being illustrated as a plane. A switch array C provides a further two stages of relay matrices which mix the b and b1 links from the A and A1 arrays and give full access to junctors JC. Access is also to be had from the e-links of the junctor switching network to outgoing junctions OJ by way of the single-stage relay matrices A11. The matrices A11 may have two stages and may be preceded by a mixing stage to give full access between e-links and the outgoing junctions OJ. The junctor switching frame, Fig. 4, has stages G and H, the stages G providing the outgoing sections and the stages H the incoming sections. The G sections comprise two arrays in parallel the outlets of array G00 to G07 giving access to even numbered modules while array G10 to G17 gives access to odd numbered modules. Supposing there are four modules and the module illustrated is of even number, four parallel arrays are provided in the H stage, the array H00 to H07 being coupled to corresponding matrices of the array G00 to G07 of the same module and a similar array H00 to H07 in the other even numbered module being similarly coupled to the same G array in common. The other arrays H 10 -H 17 to H 30 -H 37 are similarly coupled to two corresponding G arrays in other modules. Corresponding outlets of the H arrays are commoned to e-links giving access to the C switches of the line switching frame as well as to the A11 switches serving the outgoing junctions OJ. While the G and H arrays provide paths for both intramodule and extramodule connections, further paths for intramodule connections are provided by arrays in the junctor frame having stages E and F between junctor outlets and links e. While the line switching arrays provide one path between any given terminal on the line side and any given junctor, the stages E and F in the junctor network provide sixteen possible paths between any line side terminal and a given junctor outlet. The composition of the individual relay matrices of the line junctor network is chosen to minimize the number of cross-points per line served. The arrangement illustrated in Fig. 4 in which there are two groups of 64 g-links between the G and H arrays is compared with an arrangement having 64 (N-1) g-links in each group, N being the number of modules interconnected by the g-links. One arrangement proves to be more economical with cross-points for six or more modules while the other is more economical for four modules. The cross-point ratio is the same for both arrangements when five modules are interconnected. Otherwise the nature of a module itself is only affected by the number of modules interconnected to form an exchange of a given size to the extent that there should be as many H matrix arrays as there are modules. Control of an exchange employing such modules is governed by a pair of central processors working to a stored programme and with peripheral equipment provided in common for each pair of modules. Such peripheral equipment is shown in Fig. 2 in association with a single module, a signal unit SU also being illustrated which unit would normally be shared with another module. The peripheral equipment PC has line test circuits LNT, circuits CCT for testing trunk, junctor, and signalling unit conditions, and circuits LKT for testing link states with an associated marker crosspoint driver MD and buffer register BR accepting processor instructions. General communication with the processor is by way of buffer register PR and a data highway PB. The signal unit SU has a group of receiver/transmitters STC connectible into the network paths by a matrix switch SN which may have two stages. Special tone receivers for push-button dialling are grouped at PBR for connection between the outlets of the line switching network LGN and the junctors JC as required. their own time which is to say asynchronously with respect to the processors. Data is transmitted between the processors over channels a, b, containing interprocessor registers IRAB, IRBA. The data transmitted from one processor to the other in respect of each connection comprises the equipment number of a line found in the calling state and not given service by the other processor the identity of a junctor seized for a connection the equipment number of the called line a code indicating that the call is in the ringing phase a code indicating that the call is in the conversation phase and the junctor identity to indicate when this is released to break down the connection. Processor malfunction.-If the number of connections served by one processor falls substantially and consistently below the number of connections served by the other, the lagging processor is put out of service. To judge the situation a count is taken of the number of items of information sent from each processor to the other. An item of information sent from CPA to CPB steps a unidirectional counter CA and a reversible counter RC in one direction. Similarly, an item of information sent from CPB to CPA steps unidirectional counter CB and the reversible counter RC in the other direction. If either CA or CB reach a count of 1024 before RC wanders from its centre point by as much as 256 in either direction, all the counters are set to zero to start a fresh period of supervision. If RC deviates as much as 256 before CA or CB reach 1024, a bi-stable BSA or BSB corresponding to the processor of low activity is set and this in turn sets a bi-stable PAOO or PBOO in one processor to indicate that the other is being put out of service. When put back into service a processor, on lead k or l, resets the bi-stables. Test points in each processor and in the network control circuits are examined in the course of a base level maintenance programme and a fault detected by this means produces a signal on lead m or n to set the bistable BSA or BSB. When by means of the bi-stable PAOO or PBOO one processor finds that the other is put out of service, it examines its record of connections signalled as under control of the other processor and takes over fully only those connections in the conversation phase. Connections in any other phase of development are taken over only for the purpose of effecting their immediate release. Main processor circuits.-Each processor has a number of buffers, which store variable data in addresses rigidly associated with network and processor devices, and a number of hoppers which store variable items of information in a queue pending the appropriate programmed treatment. Junctor status buffers are provided for each junctor and indicate which processor serves the connection using the junctor, the phase to which the connection has progressed, and the address and type of register currently in service. Line input buffers each serve a line and indicate the state of the line loop and cut-off relay. Junctor input buffers, one for each junctor, indicate the state of the loop between junctor and subscriber. Register buffers have a time counter, a pulse counter and a digit counter, and record the calling line equipment number, called line directory or equipment number, and junctor address, as well as recording a sequence bit and bits to indicate whether the timer should time at a low or a high rate. Register buffers supervise a call up to the point of ringing, the phase of a connection from ringing to reply being supervised by an auxiliary register buffer which effects timing and records the address of the junctor employed for the connection. Buffers are also provided for supervising release of a connection, for recording the address of the register in service for a transaction between a processor and a tester-marker-driver, and for recording a clock-interrupt message from the other processor. Hoppers are provided to store the equipment number of originating calls, to store the equipment number of called lines next in process and the address of the register buffer in service, to store the equipment numbers of called lines in process, to store the various items of information for transfer between processors, and to store the buffer address of the register, auxiliary register, or supervisory in service for a connection and subject of a processor-testermarker-driver transaction. Each processor also has tables to discriminate two digit prefixes, to obtain directory to equipment number translations, and to establish class of service. Programme structure.-An interprocessor output interrupt programme controls transmission between the interprocessor communication hopper and the interprocessor register in the direction of the other processor. An interprocessor input interrupt programme controls the corresponding transmission in the other direction. A clock interrupt programme is initiated every 14 ms. to compare present with previous states of lines at line circuits and on both sides of junctors, and to inspect the nextin-process called line hopper. One-eleventh of the total scan is undertaken at each clock interrupt so that one complete scan is made each 154 ms. The clock interrupts in one processor start midway between the clock interrup