Patent GB-987732-A (GB)
Title: Variable frequency oscillator
IPC: H03L7/081
Filed: 1963-02-12
Abstract: 987,732. Automatic frequency control systems; radar; diode gating circuits. RAYTHEON CO. Feb. 12, 1963 [April 25, 1962], No. 5710/63. Headings H3A, H3P and H4D. An oscillator comprises a source of signal of one frequency and means arranged to shift the phase of the signal successively by predetermined amounts in response to a digital error signal to produce a second signal of different frequency. The oscillator may be used in a moving target pulse radar system shown in Fig. 1 wherein signals at a frequeney # 0 # x , where # x  is the Doppler frequency, are mixed in mixer 3 with a signal of effective frequency f 0 +f 1 f x , and the difference frequency is amplified in amplifier 4 and fed to a discriminator 5 which produces an error signal used to correct the frequency of oscillator 2. The oscillator 2 operates at a fixed frequency f 0 +f 1  and the error signal is used to produce a phase shift in the output of the oscillator such that the oscillator is equivalent to one of frequency f 0 +f 1 f x . In one arrangement, Fig. 4, the error signal is fed to a variable pulse rate generator 21 which produces pulses at a rate proportional to the error. These pulses are fed over line 21a or 21b, according to the sign of the error, to an N stage reversible binary counter, so that the number stored in the counter represents f x . A generator 24 produces clock pulses at a rate of 2 M + P per second, and these are counted in an M stage counter 23 to represent time (M is equal to N). The product of time and the difference frequency f x  gives the phase error of oscillator 28 and this product is produced in multiplier unit 25 and fed to a register 27. Since whole numbers of cycles are not material the register 27 uses only the P binary digits past the binary point 33 to operate the phase shifter 32. The multiplier 25 is gated at the pulse recurrence frequency by unit 26, and oscillator 28 is also similarly gated, after a delay sufficient to allow the multiplication to take place, so that the phase of the oscillator is altered for each pulse but not during a pulse. The number N is determined by the desired frequency range and may be 17, P is determined by the smallest phase shift increment and may be 6, and the clock pulse frequency may be 2<SP>23</SP>. Taking P as 6, the smallest phase increment is #/32, and the least significant bit in register 27 may be used to control a delay line giving a phase shift of #/32, the next bit to control a delay of #/16, and so on. In a modification, Fig. 5 (not shown), for use with continuous waves, the gating is omitted and the nth stage of counter 22 is coupled with the (N - n)th stage of the clock pulse counter in an AND gate, and the outputs of the AND gates are fed to a reversible counter which controls the phase shift in the same way as register 27, the phase adjustment being continuous in this case. Diode gating circuits.-An input signal pulse is applied to resistance 72, Fig. 7, and amplified before passing to the input 88 of a switching circuit 77. If a switching pulse is applied to diode 85 it conducts and lowers the potential of point 89 so that diode 82 cuts off and the signal passes through diode 81 to condenser 91 and the output. Similarly, if a switching pulse is applied to diode 84, diode 81 cuts off and the signal passes through diode 82 and a delay line 78 to the output.