Patent GB-1333610-A (GB)
Title: Methods of manufacturing semiconductor devices with a multilayer wiring structure
IPC: H01L23/522
Filed: 1970-12-23
Abstract: 1333610 Semi-conductor devices FUJITSU Ltd 23 Dec 1970 [25 Dec 1969] 61300/70 Heading H1K A semi-conductor integrated circuit (Fig. 3) comprising plural interconnected planar circuit elements in the surface of the substrate is covered with an insulant SiO 2  film 31 having windows 32a, 32b overlying contact areas of the circuit elements of which one is shown, and which may be, e.g. PN-diodes, semi-conductor resistors, or Schottky diodes as well as transistors. Ohmic contacts 33a, 33b of Al enter and surround the windows, and may be of platinum silicide or precipitated Cu. A mixed film of metal oxide and SiO 2 , e.g. a copper silicate glass 34 is deposited from organic bases on the substrate to overly the electrodes and the insulant, and is thermally oxidized in O 2  to a Cu-Si oxide film into which P 2 O 5  may be introduced. This is thermally reduced in H 2  through a vacuum deposited Mo mesh photoetched to expose selected parts of the film; to leave wiring layers 34a, 34b connected to the ohmic contacts, after which the mask is etched off. A further mixed film 35 is deposited, and a conductively-plugged aperture 35a contacting a wiring layer of the first film is similarly formed by reduction. Thereafter a third mixed film is deposited in which a second wiring layer 36a is similarly formed by reduction and connected to the first wiring layer through plug 35A. Then a fourth mixed film 37 is deposited and a conductively plugged aperture is formed by reduction as before, and a final wiring path 38 is formed by reduction or by deposition of e.g. an Al layer. In a modification (Fig. 4) an ultimate mixed film is deposited on the third mixed film 36 and etched to form a pit corresponding to plug 37a with HF and HNO 3  acids, and a wiring pattern is formed by reduction of the film surface and the base of the pit, connected to the underlying wiring paths. In a further modification (Fig. 5) a second mixed film is coated on the first, and an aperture is photoetched therein, after which a second wiring path is formed by selective reduction of the second film, and the process is repeated for a third mixed film. Thereafter a high conductivity metal, e.g. Al is coated as reinforcement on the third wiring path. The metallic element of the mixed film may be Cu, Ag, Te, Tl, Pd, Ni or Cb and it may be formed by gaseous phase growth, e.g. from an organometallic complex and a silane or by sputtering or painting.  The metal complex may be obtained by reaction with acetyl acetone, cyclopentadienyl, tropolene glycine, aminobutyrate, or aminoazobenzene which is then thermally decomposed in O 2  to form metallic oxide in the presence of SiH 4  and PH 3 ; the composition being MOSiO 2  or MO-5iO 2 -P 2 O 5  where M is the metal, and the O 2  may be derived from an organosilane, e.g. Si (OR) 4  or (SiR 2 ) 2 O where R is an alkyl radical, and the O 2  may contain O 3  to reduce the necessary working temperature. Reduction is by heating in H 2  or immersion in HF sodium thiosulphate, or HCl (or both in succession) and the mask may be As, Mo, Al or a photoresist. Specifically, the mixed layers are produced in a reaction vessel containing the substrate, fed with PH 3 , monosilane, and ozonated O 2  through valves and flow meters together with a carrier gas, e.g. N for the thermally vaporized metal complex, e.g. cupric acetylacetonate, and reduction is carried out in a heated quartz enclosure.