Patent GB-1254881-A (GB)
Title: Driving skill testing apparatus
Inventor: ASO KAZUO
IPC: G09B9/05
Filed: 1968-09-12
Abstract: 1,254,881. Driver training apparatus. MITSUBISHI PRECISION K.K. 12 Sept., 1968, No. 43333/68. Heading B7H. [Also in Division G4] Apparatus for conducting motor vehicle driving tests comprises (Fig. 1) plural simulated driving positions 10 having the normal controls and instruments (Fig. 3, not shown), a projection screen 12 visible from the positions, and a control console 14 having a motion picture projector 16 of sequential scenes presenting problems to the examinees, and a sound effect and commentary loud-speaker 18. Erroneous operations are identified by comparison of examinee reactions with a predetermined programme of instructions synchronous with the scenic sequence, transmitted to the driving positions, each of which has an error indicator 20 operated from the console, and also an error counter 24 and an error recording tape puncher 22. The projector 16 (Fig. 2) contains film and sound track; the latter having superimposed successively recorded audio pulse signals at selected locations defining positions for test, such signals being filtered from the sound effect and commentary signals for reproduction, and converted to rectangular pulses applied to reader 28 of a test programme tape, which produces signals decoded at 30 to energize operation determination circuitry 34 at each examinee position, which monitors reactions to the displayed scenes and detects correct or erroneous responses. The latter energize indicator 20, error counter 24, and tape puncher 22 recording the types and number of erroneous responses. Speed instruction signals are applied to a comparison circuit 36 in the console, one for each position, also receiving a set in simulated speed signal from the appropriate position to provide an error signal for record when the simulated speed under control of the examinee lies outside preset limits. A computer circuit at each position (Fig. 4) calculates from the control settings a simulated speed compensated for ascent or descent conditions set in from the control console. An ignition switch closes relay contacts K 2  to energize with voltage V the potentiometer R11, VR1, R12 varied by the accelerator pedal, and the resultant voltage is applied to delay network R13, C11 simulating the delay in simulated engine RPM in response to acceleration, and the output is applied to series resistors R14, R17, R18, R19 switchable by relay contacts K5, K6, K7 responsive to gear shift. Capacitor C12 and series resistors R20, R21 simulate acceleration delay in top, middle and bottom gears respectively, and variable resistor VR 3  and relay contact K4 simulate clutch action; depression of clutch pedal increasing VR3 up to half stroke and thereafter disconnecting it by opening K4. Series resistors R15, R 16 and relay contacts K14, K15 are series connected to voltage sources ŒV, and a programmed ascent from the control console closes contacts K15 to introduce negative voltage and reduce the speed simulating signal, while for a programmed descent contacts K16 close to introduce positive voltage to increase the speed simulating signal; the rates of change being determined by R15, R16. Simulated hand brake application closes relay contacts K9 to apply negative voltage over R23 to capacitor C12, while simulated foot brake application closes relay contacts K3 to apply negative voltage thereto over variable resistor VR2 and resistor R24; VR2 being varied by applied brake pressure. Deceleration is thus simulated by reduction of the speed analogue voltage. Diode CR11 across C12 holds the speed analogue voltage positive, while resistor R22 simulates decrease of speed on the overrun, and the resultant corrected speed analogue voltage is applied over transistor Q 1  to speedometer 56, and to the comparison circuit 36 together with the speed instruction signal.  A tape perforated in an 8-unit code (Fig. 5a, not shown) represents a programme for successive correct operation of the controls; a 5-unit group determining the specific controls and a 3-unit group the required manner of their operation. The operation tape is stepped by the rectangular pulses and read by appropriate contacts to impose tests such as trafficator operation, speed, brake, clutch, gearshift, steering, in conjunction with the visual scenes presented. Correct or erroneous operations in response thereto are code punched on a further tape (Fig. 5b, not shown) and arranged to operate the error indicators. Simulated speed signals are compared with the outputs of a function generator producing upper or lower speed limits, whereby outputs are produced by logic circuits when simulated speed is in excess or in defect of the preset limits; the errors being recorded and operating corresponding indicator lamps. Other codes operate logic circuits to introduce simulated ascent and descent variations of speed by operation of relay contacts K14, K15; during which the tape puncher is inhibited. Charts (Figs. 8a, 8b, not shown) are provided showing the intinerary covered by the coded programme, and a multicolour matrix on which the punched error record may be superimposed in register, with each colour corresponding to a different driving function. Numbers spaced longitudinally along the matrix identify test positions on the itinerary corresponding to different scenes of the displayed sequence, so that a pupil may examine the situations of the tests to which erroneous responses were made. In a more detailed embodiment (Fig. 6a) comprising projector 116 and loud-speakers 118, the audio pulses P 1  denote positions for monitoring driver performance, and are separated by filter 126, shaped to rectangular pulses P 2  (Fig. 7, not shown), and applied through amplifier 162 to energize tape transport magnets to step the programme tape once. Pulse P 2  also operates multivibrators 164, 165 to derive a lagging read-out pulse P 4 , while a lagging pulse P 3  operates multivibrators 166, 167 to derive pulse P 6  terminating simultaneously with the readout pulse P 4  to operate inhibit circuit 168 and emitter follower transistor 169. Tape reader 128 has plural contact sets K aligned with channels A, B, C, X, Y, Z, V, W of the programme tape for closure by a perforation denoting binary 1; with the open condition indicating binary 0. The reader derives outputs A to W and complements A to W through NOT circuits. The decoder comprises a group of logic elements for contacts K A  to K C  of the reader 128, denoted by M; and a further group for the remaining contacts denoted by T, one input of which receives read-out pulse P 4 . A coded perforation instructing left indicator is read out, and outputs X, Y, Z are applied to AND circuit T6, while A, B, C are applied to AND circuit M6 to provide # = ABC. Read-out P 4  to input of T6 produces W=XYZ P 4 , and W, # are applied to AND circuit 6L to provide output over a series diode to contacts K11, whose arm is normally as shown and changes over on non-operation of left traffic indicator. As shown, transistor Q6 conducts to energize magnets M6 to prepare punch magnet PM of the appropriate recording channel. Pulse P 6  renders transistor Q p  conducting to energize the punch magnet, after which the record tape is stepped one position, error indicator 20 (Fig. 2) operates, and the error counter 24 registers. Correct operation of the traffic indicator changes over K11, disabling transistor Q 6  and magnet SM6 so that the record tape steps without perforation. A similar process obtains for the right traffic indicator over contacts K10; and other circuits operating similarly monitor accelerator, brake, steering, and gear operation to register incorrect operation, so that pulses P 2  initiate successive tests in accordance with the tape programme. A speed test code energizes AND gate T2 to output S = YZP 4 , while A, B, C signals are applied to A/D converter 170, and produce, e.g., a 30-50 km./h. speed range test; the analogue output controlling function generator 171 to provide the upper and lower limits. A simulated speed signal from the driver's position is applied to comparators 136 H, L to produce outputs when the simulated speed is respectively above or below the preset limits; which are connected to OR gate 2 energizing AND gate 2 together with the output of AND gate T2. Operation of the AND gate 2 by incorrect speed drives transistor Q2 conducting to energize selector magnet SM2 to prepare the speed channel recording punch for operation by pulse P 6 . A programme code VW to introduce slope operates AND gate S whose output Q is applied to AND gates SU, SD; SR which also receive code A to indicate ascent, operating gate SU to trigger flip-flop 172 energizing relay K<SP>1</SP>15 closing ascent contacts K15 (Fig. 4). To remove slope simulation, level code AB is applied to AND gate SR to reset flip-flop 172 and release relay K<SP>1</SP>15 to open the ascent contacts K15 (Fig. 4). A descent code B operates flip-flop 172<SP>1</SP> and energizes relay K<SP>1</SP>14 to close contacts K14 (Fig. 4) while a level code AB similarly resets the contacts thereafter. The AND gate S inhibits gate 168 on arrival of a slope code to prevent application of punch pulse P 6 . Initially, a starting code ABCXYZW is generated which has no effect, and operation of the projector generates code P 2  to excite feed magnets FM1, FM2 over clutch driver 162 to step the programme tape. Code ABCXYZVW indicates readiness, and its complement energizes a tree of NOR gates (Fig. 6b, not shown) together with pulse P 4  to energize the selection magnets SM1 to SM8 over transistors Q 1  to Q 8  (of which only SM2, SM6 and Q 2 , Q 6  are shown) to ready the punches, for response to pulse P 6 . This punches an initial series of 8 perforations on the record, followed by tape stepping. The series of simulated tests are conducted under control of the programme and pulses P 2 , P 4  and the error record for each driver in associationwith the tes