Patent GB-799550-A (GB)
Title: Improvements in or relating to electronic computing apparatus
Inventor: YANDELL RONALD PERCY BAWDEN
IPC: G06F7/00
Filed: 1956-02-03
Abstract: 799,550. Digital electric calculating-apparatus. POWERS-SAMAS ACCOUNTING MACHINES, Ltd. Jan. 3, 1957 [Feb. 3, 1956], No. 3511/56. Class 106 (1). In electronic computing apparatus for effecting the arithmetic functions Î 10, ¸ 10 or ¸ 2, a number read from a store is applied serially as digit-representing potentials to a gating matrix GM having further potentials applied thereto representative of the functions to be performed, and the outputs from the matrix are applied to an adding unit AU. General. The computer described comprises a magnetic storage drum D, Fig. 4, in which digits are recorded in parallel on four track sections corresponding to the elements of the 1, 2, 4, 8 code, each number location being divided into 20 digit positions DP1-DP20, Fig. 3. The amounts are recorded within positions DP3-DP18, a negative sign is represented by a "1 " in position DP2 and by " 1 " and " 8 " in position DP19, and position DP2 is used also to indicate whether an amount is decimal or sterling (" 8 " for decimal). A check digit may be recorded in DP20. The highways H1, H2 for conveying amounts from the drum to adding unit AU, the return highway H3 and the digit input lines 19, 20, 21, 25 and 26 for matrix GM each comprise a group of parallel lines for the 1, 2, 4, 8 digit elements. The " 8 " digit in position DP2 is applied over line 74 to decimal/sterling control circuit DSI, the digit periods being marked by the decoded outputs on lines 3 of a scale-of-20 counter DTC which receives drum clock pulses over line APL. An order decoding unit OAD energizes a line 13, 14 or 15 for the functions ¸ 2, Î 10 or ¸ 10 respectively, and the number on which this function is to be performed is selected from an immediate access recirculating loop store 33 or 34 by energizing line 11 or 12. Each store comprises portions of 4 parallel drum track sections each with associated read, write and erase heads RH, WH and 6, the spacing between RH and WH being chosen to make a total recirculating time of 20 digit periods. For store 34 the output from each head RH amplified and shaped in a read circuit 7 (Fig. 11, not shown) is passed through unit-digit delay circuits UD1, UD2 and recirculation gate 9 to write circuit 10 and head WH. An energizing potential on line 12 closes gate 9, and opens write gate 38 for highway H3 and read gates 35, 36, 37 which supply amounts 2 digits early, 1 digit early and normally timed to lines 20, 21 and H1, 19 respectively. The output of 37 is applied also to further delay circuits UD3, UD4 whereby amounts delayed by 1 and 2 digit periods are supplied to lines 25 and 26. Store 33 is similar but includes only one delay circuit, UD5, in the recirculation loop whereby an amount can be supplied 1 digit early or up to 2 digits late. The gates in GM to which the digit components are applied are so controlled by the outputs from OAD and DSI and by lines 18 which are each energized during predetermined digit periods through a selection time circuit STU that the outputs on lines 30, 31, 32 applied to the number and carry inputs of AU represent the resultant number or components thereof. Example of operation. ¸ 10, Fig. 7, shows the operations that must be effected on the different digits of a sterling amount to perform the function ¸ 10. Where the next lower denomination is in scale-of-ten, the operation is generally a denominational shift which can be obtained merely by gating through the matrix the inputs on 21; exceptions occur only for the denominations in DP12, DP10 and DP9. The sign digit in DP19 is preserved by being allowed through highway gate HIG, as well as being shifted to DP18 to preserve the nines complementary form of a negative number. Fig. 8 illustrates how the function ¸ 10 would be performed on ú96 15s. 11d. recorded in store 34 as indicated in Fig. 3. The digits " 9 " and " 1 " in the ú10 and 10s. positions DP13 and DP11 are merely shifted to the next lower positions, the ú6 in DP12 becomes 10 + 2 shillings, the 5 shillings in DP10 becomes 6 pence, and the 11 pence in DP9 becomes 1.1 pence, the matrix outputs being added to form the final result ú9: 13: 7.1d. Circuit details, modifications. The circuits consist primarily of diode gates and bi-stable flip-flop circuits. For example, each delay unit (UD) comprises a pair of flip-flop circuits controlled by staggered timing pulses. The storage drum may be replaced by a nickel delay line or capacitor matrix and other scales of notation may be dealt with, e.g. avoirdupois.