Patent GB-1484365-A (GB)
Title: Digital processing system
IPC: G06F17/10
Filed: 1974-10-21
Abstract: 1484365 Data processing RAYTHEON CO 21 Oct 1974 [2 Nov 1973] 45481/74 Heading G4A A pipe-lined data processing system includes an arithmetic unit 14 including a plurality of serially coupled processing levels and a controller 26 having a like plurality of serially coupled control levels, each control level controlling a corresponding one of the processing levels. Each processing level includes a selector 48, 74 or 98 selectively connecting its inputs to its outputs, data to be processed being supplied on line 62 to the selector 48 of the first processing level. The selector 48 of the first processing level also receives inputs from t vo data me:n ories 18, 20, one output of the selector 48 being supplied via registers 50, 56 to the second processing level and the other output of selector 48 being supplied via a register 52 to a complex multiplier 60 which also receives a coefficient from a memory 22 via a register 54. The second processing level includes a complex adder 80 and a complex subtractor 82. The third processing level provides a system output on line 107 and signals on lines 104, 106 which are supplied to memories 20, 18. The controller includes in each control level a decoder 30, 40 or 44, e.g. a ROM decoding an applied macroinstruction, certain of the control levels includng one or more registers 34, 36, 38 to provide to the macroinstructions delays corresponding to those experienced by the data in the corresponding processing levels. Instruction words are stored in a core memory 10 and each includes five fields. Three of these fields respectively control address generators 108, 110 and 112 to provide read addresses to data memories 18, 20 and coefficient memory 22, each of the generators 108, 110 also supplying, via a delay corresponding to the delay experienced by the data passing through the arithmetic unit 14, a write signal to the respective memory 18, 20. Each of the generators 108, 110, 112 is controlled either to increment the address by a specified amount or to set the address at a specified initial value. Each instruction word also includes a macroinstruction control field, which includes a number portion and a control portion and which controls a generator 28 to produce the macroinstructions supplied to decoders 30, 40 and 44. The control portion may specify that the next macroinstruction is to be as specified in the number portion, or that the next macroinstruction is to be the same as the present macroinstruction, or that the next macroinstruction is to be derived from a macro memory addressed by the present macroinstruction. Each instruction further includes a program control field which is supplied to a controller 24 to derive the following address for memory 10. Each program control field includes a "next address" portion, a "number of times" portion and a "control" portion. The "control" portion may take one of four values. If the "control" portion is TRA the instruction indicated by the "next address" portion is next addressed; if the "control" portion is LUP the presently addressed instruction is read out for the number of clock periods indicated by the "number of times" portion and then the instruction indicated by the "next address" portion is read out. If the "control" portion is XRT the instruction indicated by the "next address" portion is read out for the designated "number of times" whereupon a control signal is produced for subsequent use by an XJP instruction. If the "control" portion in XJP operation is as for XRT except that when the instruction has been selected for the designated "number of times" the address for the following clock period is generated by adding one to the present address, or by adding two to the present address if the control signal produced by XRT operation has previously been produced. The system may provide, for example, a moving target indicator process or fast Fourier transform of radar signals. The utilization device connected to output line 107 may be controlled to respond only to the data provided at a certain period of operation when the final data is being produced.