Patent GB-1233714-A (GB)
IPC: G06F15/16
Filed: 1968-12-02
Abstract: 1,233,714. Parallel digital computer system. BURROUGHS CORP. 2 Dec., 1968 [20 Dec., 1967], No. 57099/68. Heading G4A. A digital electric data processing system comprises one or more modules 19, 21, 23, 25 (each comprising a control unit CU, an array of processing elements (PE's) and a memory) and a control computer 27. The number of modules involved can be varied during problem operations. A programme is entered through peripheral devices 29 and the computer 27, by means of a supervisory programme in its memory, translates the programme into machine language. The programme for each CU is sent to its respective memory by way of a buffer memory 35, an input/output controller 31 and a switch 33 and data is sent there from a mass memory 37 having a priority unit. Interrupt and diagnostic programmes can also be sent to the modules. The modules can act separately, or combine into two double module arrays, or combine into a four module array as instructed by the computer 27. Each module memory stores that module's data and part of the programme for its CU and each CU can decode and execute its own control programme as well as decoding and broadcasting instructions for controlling its PE's. Processing elements.-Each array has 64 PE's in the same physical location, each PE having a memory (PEM) associated therewith. Each PE may use a 64-bit word in either a fixed or floating point mode in parallel. The 64-bit word may be subdivided into two 32-bit floating point or eight 8-bit fixed point subprocessors. The PE's of each module may route either end around for independent module operation or be routed intermodule for multi-module operation. Each PE is connectible to at least four other PE's. Multiplication and division can be carried out in the 32- or 64-bit mode, using shifting. For the 64-bit mode the multiplication is carried out in 9 clock cycles, examining eight multiplier bits per cycle and using carry look ahead. Division uses one's complement subtraction over 55 clock cycles. Addition and subtraction take five clock cycles and the processing elements are stated to be capable of use for OR, AND, or exclusive OR operations. PE memories.-Each PEM may be a 2048 word thin film memory and the CU fetches its instructions therefrom eight words at a time, using a 32 x 32 transistor matrix for destructive read out. Control units (Figs. 9A and 9E, not shown).- Instructions are received from a store of an instruction look ahead unit one at a time by an ADVAST register which determines whether it is an ADVAST instruction for execution by the CU or a FINST instruction for controlling the PE's. If it is an ADVAST, it is decoded and the operation timing is worked out &c., but a FINST instruction joins a queue of up to eight FINST instructions. The FINST instructions are decoded and sent to the PE's in parallel. Some overlap between a FINST instruction being executed and the succeeding one is possible. When changing from one module to multimodule operation the modules are first synchronized. In multi-module operation the programme and operands can be stored in any of the modules involved and the number of modules involved can be changed during the running of a problem. Parity bits are used for error checking and interrupt. Real time data such as radar can be fed to the PEM's.