Patent GB-1081814-A (GB)
Title: Data handling system
Inventor: DOBLMAIER ANTON HENRY
IPC: G06F9/30
Filed: 1964-10-13
Abstract: 1,081,814. Automatic exchange systems. WESTERN ELECTRIC CO. Inc. Oct. 13, 1964 [Dec. 31, 1963], No. 41685/64. Heading H4K. [Also in Division G4] In a data processing system, program overlap is achieved by causing order words incoming from a memory to the central processor to be initially stored in a buffer order word register (BOWR) where the word may be subjected to data processing whereafter, under control of a clock source, the word is transferred to an order word register (OWR) where it is further processed and wherein, during the latter process, a program address register PAR addresses the memory so as to cause the next order word to be introduced into the BOWR. By means of the BOWR it is thus possible to effectively process one word per machine cycle (5.5 Ásec.) even though the actual processing time of each word is at least 1<SP>1</SP>/ 3  machine cycles. In the event that a word requires more time for processing, e.g. because data must be read from a memory before the order word can be fully executed or because an error is detected whereby a fault detection and correction sequence must be run through, the PAR may be interrupted (but not necessarily) so as to delay the introduction of the next order word. The system is applied to a program-controlled telephone exchange of the type described in Specification 904,164. The speech switches used are of the reed relay type. Other aspects of the system, e.g. those relating to error detection and correction, the arrangement of the stores, central control and the interconnecting buses and the relationships between the switching network and the processor, are described in Specifications 1,081,811, 1081,812, 1,081,813, 1,081,815, 1,081,816 and 1,081,817. Particular description.-The address of the next order word (X) in the program store PS which is to be gated into the central processor is set up in the program address register during phase 1, (#1, Fig. 71) of the machine cycle 1. During cycle 1 and part of cycle 2, the preceding order word (X-1) is processed. At some time during phases 3 and 1 of these cycles the order X is gated into a buffer order word register BOWR. (The exact time depends on the physical distance between the particular PS's and ABOWR's used, since both are duplicated although this is not shown in Fig. 9). The order comprises three multibit words of which the " hamming and parity bits " word and the " data-address field " word viz.: a word comprising data to be stored in flip-flop registers in central control or a word to be used for addressing a memory in order to obtain more data, are gated directly into vacant positions in the BOWR, while the " operation field " word, viz. a word which defines the operational actions to be performed, is gated into an auxiliary buffer order word register ABOWR until the operation field word of order X-1 is gated out of the BOWR at the end of #3 of cycle 1 whereafter the operation field is transferred to the BOWR. During phases 2 and 3 of cycle 2, order X is processed, if necessary, by the logic and arithmetic units of central control and it is also gated into the order word register OWR. Meanwhile the PAR applies to the program store for the next order word X + 1. The buffer and order word decoders BOWD and OWD then "decode " the order and transmit the relevant information to the combining gates OCG which control the execution of the order. The mixed decoder MXD ensures that data required by order X and which was made available by order X-1 is provided directly to the units controlled by order X and not as is more usual stored in flip-flop registers since this would entail loss of time in execution of the order. As can be seen from Fig. 71, each order requires a length of time considerably longer than a machine cycle for its processing and execution but by overlapping the orders in the manner above described the system effectively executes one order per machine cycle.