Patent SE-310197-B (SE)
Inventor: FISCH A
IPC: H04Q11/04
Filed: 1963-09-03
Abstract: 1,062,214. Automatic exchange systems. SIEMENS & HALSKE A.G. Sept. 2, 1963 [Sept. 4, 1962], No. 34529/63. Heading H4K. In a time-division multiplex exchange in which an operator or subscriber is enabled to break into an existing conversation, arrangements are provided whereby the pulse phase in use for an existing conversation can be ascertained, whereupon the address of the breakerin is written at that phase into a circulating memory controlling the connection of the breaker-in to the speech multiplex highway. Break-in by exchange operator.-The system envisaged is one in which normal conversations are effected by writing the addresses of the calling and called subscribers in circulating t ores Ua, Ub respectively at the same phase. Thus it is assumed that in this case a connection is established between subscribers N1 and Nx at phase P10. However, when an operator wishes to call a number that number is inserted in Ua at the phase P1 taken into use by the operator. The operator VPl1, when attempting to set up the call, will have taken into use one of a hundred " ringing sets " ARS11 whose address will have been written at phase P1 in store Up. The addresses of these ringing sets are emitted in succession by address generators ZP. When an operator attempts to establish a call to a busy subscriber, an allocated pulse P1 is inserted into store Up to store the identity of the ringing set, and also in Ub to inidcate the identity of the wanted line. The operator also provides a special break in marking, which during the scanning period of the associated ringing set marks common lead qsmnl to cause SQ to operate in the control circuit at the beginning of each information cycle. During this cycle comparator VP compares ZP with the outputs of store Up so producing a P1 output which is fed to the 100 Ásec. delay line APh and also to gate G2. Gate G2 also establishes that the various conditions necessary for a break-in exist principally that (a) P1 does not exist in Uda or Udb (i.e. that no connection has been put through at this phase) and (b) P1 exists in the store Usi indicating that the wanted line has tested busy. If these conditions hold, trigger X1 is operated and SQ and X1 together operate trigger Y1 to initiate an operation cycle in which G10 is open to pass the P1 pulse received from Aph to store UQ. Counter QZ steps to position 1. When AZ reaches the address of the wanted line, presence of that address in Ua at P1 in conjunction with the P1 output from UQ opens gate G15 to operate X2. At P10, provided there is no output on lead r from Vsi (indicating that the subscriber is not being rung at this time) and that there is no pulse in store Vp at this phase, then assuming the wanted member is being stored in Ub (and possibly that an appropriate class of service signal is emitted from the converter UM) the comparator output pulse at P10 from AB is gated through G20 and G19 to operate X3. P10 from G19 also passes to the delay line Zph. With X2, X3 operated and QZ in position 1, G23 operates Y2 to open G26 to pass the P10 pulse from Zph to the store UQ during the operation cycle and to step QZ to position 2. When ZP next scans circuit ARS11, comparator VP again emits P1 which is inserted into delay line Aph. VP also pulses G27 simultaneously with P1 from UQ to trigger X4. SQ operates as previously described. G28 thus opens to operate Y3, so causing G29 to feed out P1 received from Aph which cancels P1 in Udp and also in UQ. Also at P10 which is not present in Up, absence of output from VP together with a pulse from UQ causes P10 to be inserted into Zph and X5 to operate followed by Y4. G35 thereupon emits P10 to operate D5 to cause the ringing circuit's address to be written into Up at that phase, and also into Udp. Thus, VPl1 is connected to the speech multiplex at P10 and so breaks in on the existing connection. The G35 output also deletes P10 from UQ and G<SP>1</SP>35 feeds P1 to lead lb to cancel P1 in store Ub.G39 then zeroizes QZ. Break-in by subscriber.-Fig. 2. Assume that subscriber N2 is busy having originated a call to subscriber Nx which call is now in progress using pulse phase P10. Assume further that subscriber N1 has seized pulse phase P1 and is attempting to call N2. Then at P10, N2's address is in Ua and Nx's address is in Ub and P10 is present in Uda, Udb. Also at P1, N1's address is in Ua and N2's address is in Ub. P1 is in Uda but not Udb. Store Usi emits a busy marking at P1 on lead bs. N1 then sounds a special signal which is received in an allocated digit receiver (e.g. ZEX) and transmitted via circuit Z and lead as to bring up SSQ. When AZ emits the address of N1, comparator AA emits P1 which in conjunction with the P1 conditions mentioned above triggers SS1. P1 is also stored in 100 Ásec. delay line Aph. In the subsequent operation cycle YY1 is operated to cause the P1 pulse to be stored in UQ and sequence switch QZ is stepped to position 1. When AZ next emits the identity N1, the P1 pulse in UQ now brings up S1 and P1 is inserted in Aph. During the subsequent operation cycle YY2 operates to pass the stored P1 pulse to D6 which causes the address of N2 stored in Ub to be passed to the static register R. QZ advances to position 2. In the next information cycle at P1 comparator VR in comparing the address in Ub with that in R emits a pulse which in conjunction with (inter alia) the P1 pulse from UQ opens to G65 to set trigger S2. In the same cycle at P10, VR compares the address N2 stored in R with that in Ua and so emits a P10 pulse on vr/va, which acts amongst others to open G67 to pass P10 to delay line Zph and to operate S3. In the subsequent operation cycle YY3 operates to open G71 to pass the stored P10 pulse to UQ, to zeroize register R and to step QZ to position 3. When next AZ marks N1, G74 is opened at P1 by the UQ output and tests that the wanted line is busy, whereupon S4 is set. Simultaneously, store Aph receives P1 from comparator AA. At P10 the UQ pulse tests that Ua stores a complete marking and that Uda, Udb contain the pulse, gate G76 thereupon opening to set S5, S4 and S5 thereupon set YY4 to cause G81 to emit P1 from Aph to open D8 to store in R the marking N1 at present in Ua. QZ goes to position 4. During the next information cycle, at P1, G82 is opened inter alia by a pulse from UQ and from lead vr/va indicating that R agrees with Ua at this point. This sets S6. At P10, G84 conducts to pass P10 to store Zph and to set S7. In the subsequent operation cycle YY5 is operated to pass P10 from Zph to D4, thus causing the passing of the N1 address from R to store UMn at phase P10, the cancellation of P10 in UQ, and the removal of N1 from R. QZ goes to position 5. In the next information cycle, at P1, G89 receives inter alia a class of service signal from UM authorizing break-in, and a pulse from lead a/va comparator AA.P1 is also inserted in Aph. This brings up S8. At P10, G91 receives inter alia a pulse from comparator VM, and a class of service authorization from UM and opens to pass P10 to store Zph, and also to set S9. In the succeeding operation cycle Y6 comes up to pass the Zph pulse through G95 to insert the pulse in Udm. Y6 also opens G<SP>1</SP>94 to pass the P1 pulse from Aph to cause deletion of P1 from Ua and Ub. G96 then emits a pulse to zeroize QZ. The N1 address in UMn at phase P10 thus completes a connection from N1 to the other subscribers who are also using P10.