Patent GB-757356-A (GB)
Title: Control arrangements for electronic digital computers
Inventor: CLAYDEN DAVID OSWALD
IPC: G06F9/30
Filed: 1953-12-04
Abstract: 757,356. Digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Nov. 26, 1954 [Dec. 4, 1953], No. 33751/53. Class 106 (1). In a programmed electronic digital computer additional triggers are provided between the control unit and the data storage devices whereby a new instruction may be staticized in the control unit during the last minor cycle for which the current instruction is operative. The " next instruction source ", " source " and " destination " portions of an instruction, Fig. 2, having " wait " and " timing " numbers which determine how long to wait after an instruction is staticized before it shall be operative and for how long the instruction shall be operative, respectively, are staticized, Fig. 1, and determine between which of a set of delay line stores DL1, DL2, &c., only DL4 and DL5 being shown, a transfer shall take place and from which the next instruction shall come. Suppose an instruction requiring a transfer of nine words from delay line DL5 to delay line DL6 is operative and that the next instruction is to come from delay line DL4. Then for the first eight minor cycles of the transfer the " next instruction source ", " source " and " destination " portions of the instruction remain staticized, each energizing one output lead of their associated trees, the signals appearing at the beginning of each minor cycle on the output leads of which being registered under the control of a P32¢ pulse by triggers IT1, IT2, &c., ST1, ST2, &c., DT1, DT2, &c., only IT4, ST4, ST5, DT4 and DT5 of which being shown, which constitute the additional triggers and which control, via associated gates, the flow of data words between the delay line stores and the main data highway which is entered via a lead HWE and left via a lead HWL, and also the flow of instruction words from the delay line stores to an instruction highway ISH. Thus in the present example, for the first eight minor cycles of the transfer gates IG4, SG5 and DG6 are held open, and gates G1, G2 are held open by a signal TP from an instruction control unit C. At the beginning of the ninth and last minor cycle of a transfer specified by the current instruction the control unit C simultaneously emits a " clear instruction staticizer " pulse CLS and a one minor cycle signal TC1, which opens a gate 20 allowing the next instruction to flow from the instruction highway to the control unit and to the staticizers, but not withstanding this the tree outputs corresponding to the current instruction are still registered by the additional triggers, so that for the rest of the ninth minor cycle the control exercized by the additional triggers is the same as that which would have been exercised by the current instruction if it were still staticized and if the addition triggers were omitted. Approximately half-way through (P20) the ninth minor cycle the signal TP ceases closing gates Gland G2, rendering the destination tree inoperative, and does not occur again until approximately halfway through (P22) the minor cycle immediately before that in which the next transfer is about to commence. The construction and function of the control unit C, Fig. 4, is similar to that described in Specification 719,066 to which reference is made. Continuing with the above example, at the beginning of the ninth and last minor cycle of the current instruction a trigger TC1, Fig. 4, is put " on " and a pulse CIS is produced. During the ninth minor cycle the next instruction flows via the gate 20 into a loop circuit containing a none minor cycle delay tank " count " around which it circulates, and the address portions are staticized. At time P20 of the ninth minor cycle the signal TP is terminated by a pulse P20 applied to a trigger Q which puts " off triggers R and P via end elements 18, 12 respectively. During each complete circulation of the instruction in the loop containing the tank count the " weight " and " timing " numbers of the next instruction are each diminished by unity, by inverting the least significant digits up to and including the first " one " and then taking the remainder of the number unchanged. This is performed by a trigger CA, a half-digit delay 6 and gates 1, 5, 4, 7. At P22 time in the first minor cycle after the " weight " number has become zero, a P22 pulse produces a TP pulse via a gate 10, trigger R, beginning element 11 and trigger P. As soon as trigger P goes " on ", gates G1 and G2, Fig. 1, are opened and the transfer specified by the next instruction can begin. At P30 time in the first minor cycle after the " timing " number has become zero, a P30 pulse puts " on " the trigger Q via a gate 16. This minor cycle is arranged to be the penultimate minor cycle of the transfer specified by the next instruction and at the end of it a P32¢ pulse, via a gate 19, simultaneously puts " on" the trigger TC1, generating a TC1 signal, and produces a CIS pulse which clears the staticizers in preparation for a further instruction. The digit in position 10 of an instruction is usually zero, when the operation of the circuit is as described above. However, when it is a " one " signifying a " serial " transfer, the transfer last for only one minor cycle irrespective of the timing number, which under these circumstances merely determines when the next instruction shall be staticized, i.e. the timing number controls the production of the TC1 and CIS signals but has no control over the TP signal. The invention is also described as applied to a parallel-mode computer (Fig. 5, not shown). Specification 717,114 also is referred to.