Patent GB-1385710-A (GB)
Title: Circuit for processing a time sequence of signals
IPC: G01S3/809
Filed: 1972-07-21
Abstract: 1385710 Directional reception of waveenergy signals FRIED KRUPP GmbH 21 July 1972 [18 Dec 1971] 26538/74 Divided out of 1385709 Heading H4D In a beam-forming and processing system the m receiving transducers (e.g. sonar ones) of an array are individually interrogated in succession repetitively, the interrogated signals are read-in to a memory and are moved step-wise through consecutive locations in the memory, read-out from the memory takes place at those memory locations which correspond to the time delays required to produce co-phasal outputs from a group of n(<m) adjacent transducers in response to an incident wavefront, the read-out signals are added in a circuit to form a group signal, successive group signals associated with respective different directions of the beam being formed as the interrogation proceeds, and the adding circuit output is fed via a multiplier circuit to an integrator which effectively weights and sums the recurrent group signals associated with a given direction of the beam to improve the signal-to-noise ratio. For the Fig. 3 embodiment the interrogation signals from transducers W1...Wm move step-wise through memory 6, each step correponding to a switching (at 4) between successive transducers. Outputs from the appropriate memory locations are summed at 8 to form a group signal for transducers W1-Wn, then a group signal for transducers W2-Wn + 1, and and so on. Each group signal may be formed, as in the parent invention, as two partial group signals for respective sub-groups each of ¢n transducers, the two sub-groups being symmetrically disposed about the beam axis. Multiplier 21 has a first input connected directly to the output of adding circuit 8; a second input can be connected (Fig. 4, not shown) either directly or via one of two comparator circuits to the circuit 8 output so that the multiplier provides, respectively, either quadratic, half-wave or full-wave rectification of the group signal. Alternatively, when circuit 8 forms two partial group signals, the multiplier 21 inputs can be connected (Fig. 5, not shown) to the circuit 8 outputs either both directly, both via comparators, or one directly and the other via a comparator, so as to effect respectively crosscorrelation, polarity-coincidence cross-correlation, or phase-controlled correlation of the two partial group signals. For simple binary processing, multiplier 21 is an exclusive NOR gate (Fig. 8, not shown). Integrator 22 comprises a memory 24 of the delay line or shift register type, providing a delay equal to the interval between the occurrence of a group signal for a given beam direction and the next occurrence of the group signal for the same beam direction. The memory output is weighted at 25 by a factor k<1 then fed back to the memory input and summed at 23 with the prevailing input signal at 23À1. The prevailing signal at 23À1 may also be weighted and added to the memory output (Fig. 9, not shown). The weighting by factor k may involve analogue or digital multiplication or (Figs. 7 and 8, not shown) binary addition in conjunction with bit-significanceshifting.