Patent GB-1188339-A (GB)
Title: Digital Bearing Measuring System
IPC: G01S19/04
Filed: 1967-08-17
Abstract: 1,188,339. Radio navigation. INTERNATIONAL STANDARD ELECTRIC CORP. 17 Aug., 1967 [25 Aug., 1966], No. 37857/67. Addition to 1,147,552. Heading H4D. Specification relates to a digital TACAN receiver of the type described in parent Specification 1,147,552 with the addition of circuit means to compensate for variations in the rotational velocity of the beacon antenna. Thus the receiver comprises; a first digital counter 10, Fig. 1; means, Fig. 3 for phase locking the counter 10 to the north reference signals; a second digital counter 22; means for deriving a clock signal from the first counter and applying said clock signal to the second counter; means 26 for comparing the instances of arrival of the first and second counters at equal counts to thereby derive a beacon rotation velocity error signal; means 15 for advancing or retarding the first counter in dependance on said error signal; a third digital counter 11, Fig. 1, means Fig. 9 for phase locking said third digital counter to the fundamental and harmonic modulation waves and means responsive to the quantities held in the first and third counters to yield a measurement of bearing. In Fig. 3, the counter 10 fed with 216,000 bits/sec from clock 14 has a capacity of 14,400 bits whereby it cycles 0 degrees to 360 degrees, fifteen times a second, and generates early and late gates Fig. 4, via generator 16. These are supplied together with the reference pulses to a gating logic 17. The reference pulses are distributed between late and early outputs of the logic in a manner dependant on the phase error of the counter as shown in Fig. 4. Pulses at the early output cause by means of logic circuit 15, pulses to be added to those passing from the clock to the counter and pulses at the late output cause said clock pulses to be retarded. Whilst a large degree of out of synchronism prevails, the pulses from the logic 17 pass directly via AND gates 20/21 to the logic 15 and via divide-byfour circuits 18/19 when the degree of out of synchronism has been reduced. Pulses from the À2 degree stage of counter 10 are fed via logic circuit 23 to the second or velocity, counter 22 and are added to or retarded as are the clock pulses to counter 10, but since rotational velocity error of the beacon will only show over a plurality of successive cycles, the early and late pulses from logic 17 are divided by eight in means 24 and 25 before being applied to logic circuit 23. Corresponding stages in counters 10 and 22 each representing 20 degrees are connected to time comparison logic circuit 26 wherein a difference in the live times of said stages, indicating said velocity error produces further pulses for feeding to logic circuit 15 and causing further supplementation or retardation of the clock pulses fed to counter 10. A similar velocity error correction process is used for the third counter 11, Fig. 9. Instead of early and late gates however the amplitude modulated pulses B, Fig. 11, after removal of the 15 c.p.s. modulation, are sampled by a two level threshold signal E generated in synchronism with the counter 11, equal numbers of pulses being detected, above the two levels when the threshold waveform is correctly placed in phase with the maximum and minimum peaks of the modulation waveform.