Patent GB-988924-A (GB)
Title: Error detection and correction apparatus
IPC: G06F11/10
Filed: 1964-03-02
Abstract: 988,924. Error detection and correction. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 2,1964 [March 4, 1963], No. 8653/64. Heading G4R. Apparatus for checking and correcting readings by a character reading device of character groups each comprising a number of data characters and a redundant check character whose value causes a group to satisfy an arithmetic checking formula, includes a first store for storing correctly read characters of a group and a second store for storing at least two uncertainty characters for each uncertainty character position of the group, and means to present the correctly read characters with all possible combinations of the uncertainty characters and to determine which, if any, of the combinations satisfy the arithmetic checking formula. In the particular embodiment, a character group comprises five (four data and one check) decimal digits, the check digit being chosen so that all the digits add up to an integral multiple of ten. The digits are read (no details of reading) in turn from a document, each character causing the energization of one of ten lines 24 ideally (Fig. 4a). If the character is dubious, two or more of the lines will be energized, and if the character reader cannot even make "guesses" in this manner a separate "failure to recognise" line 46 is energized. Energization of one or more of the lines 24 triggers off a chain of latches 36 and delays 38 to sample the ten lines 24 in turn, each one which is energized being recoded by a coding network 25 (AND-gates) into pure binary form on leads 41. If more than one of the lines 24 are energized at a time, a "two or more signals detector" 42 (a magnetic core) produces an "uncertainty" signal on line 43 which gates the binary signals on loads 41 into a shift register (Fig. 4d). This shift register comprises bi-stable units (SRUs) 90 to 97 for the highest binary order and similar units (not shown) for the other three binary orders. If the two or more "uncertainty characters" (i.e. possibilities for the uncertain character), the first goes into SRUs 90 and the second into SRUs 94. If there is no uncertainty about the character (only one of lines 24 energized), the binary signals on loads 41 are instead gated into an output buffer 26 (shift register or magnetic drum). In the case of an uncertain character or a "failure to recognise", 1111 is read into output buffer 26. When two or more failures to recognise, or an uncertainty together with a failure, occur in a given character group, the document is rejected (top left, Fig. 4a). Correct characters, besides being read into output buffer 26, are also applied to a modulus-10 adder 27 (Fig. 4b). If the adder output is zero (as tested by an AND-gate 68) and there are no uncertainties or failures, AND-gate 70 (Fig. 4b) responds to indicate "character group read correctly" in which case the contents of output buffer 26 are passed to an output device (not shown). If there is one failure and no uncertainties, the complemented adder output is stored in latches (flip-flops) 88, and during readout of output buffer 26,the 1111 character is detected by an AND-gate 83 (Fig. 4a) which substitute the contents of latches 88 for it. Otherwise the adder output is passed along lines 104 to the shift register, the highest order bit being stored in both SRUs 90 and 94,for example (previous data stored in these having been shifted along as necessary). This adder output is then shifted out of the shift register with each possible set of possibilities for the uncertain characters, in turn, the shifted out bits being reinserted into the shift register (through OR-gates 103) and also fed to the adder 27. The various possible sets are obtained by shifting out of the SRUs 90 or 93 and 94 to 97 alternately, there being provision for interchanging the contents of SRUs 92 and 96 and also SRUs 93 and 97. This interchanging is done by outputs from a binary counter comprising latches 150, 170,171, (bottom, Fig. 4d) which is fed a number of pulses FC7 equal to two to the power of the number of uncertainties as evidenced by the state of a counter comprising latches 110 to 113 (Fig. 4c) which counted the number of pulses produced by the "two or more signals detector" 42 (Fig. 4a). Every time a pulse FC7 is produced in response to pulses PP applied to a terminal 125 (Fig. 4c), a binary counter comprising latches 127 to 130 (Fig. 4c) increases by one and when the count reaches the number stored in latches 110 to 113, one of three AND-gates 134 to 136 produces an output to stop production of FC7 pulses. The latches 110 to 113 also ensure that the document is rejected if there are more than three uncertainties. Each time bits from the SRUs are shifted out into adder 27, the adder output is tested by AND-gates 68 to see if it is zero. The first zero output results in the current count of the binary counter 150, 170, 171 being stored in a set of latches 190 (Fig. 4d). Any second zero will result in the rejection of the document (Fig. 4b, bottom right). After the required number of shiftings out to adder 27, pulses RG3 are produced and used to cycle the binary counter 150, 170,171 to the value stored in latches 190 (Fig. 4d) equality being detected by AND-gates 205, 207. The contents of the output buffer 26 (Fig. 4a) are then read out to the output device, except that characters 1111 (as detected by AND-gate 83) are replaced by the correct characters stored in the shift register SRUs (Fig. 4d). The ten inputs to the coding network 25 (Fig. 4a) are provided with plug connections so that the inputs may be effectively interchanged: this is equivalent to changing the code and allows likely pairs of mutually-cancelling reading errors to be made non-cancelling. In a modification, the order of the lines 24 from the character reader may be changed to ensure that the two most likely possibilities for some commonly uncertain characters are stored in the SRUs (since only the first two are stored), or more SRUs may be provided. Letters as well as numbers may be dealt with.