Patent GB-1471888-A (GB)
Title: Synthetic aperture radar
IPC: G01S13/90
Filed: 1973-06-07
Abstract: 1471888 Radar EMI Ltd 20 May 1974 [7 June 1973] 27263/73 Heading H4D A synthetic aperture radar, comprises mounted, e.g. on an aircraft passing along a path OX, Fig. 1, past a target T, an aerial and transmitter having a lobe and a p.r.f. such that N successive transmitted pulses intercept the target and produce N successive echo signals A i+n .e<SP>-j(#-#</SP>i+n<SP>)</SP> (where i is the number of the aerial array being synthesized, n is the number of the transmitted pulse used in the synthesis of said ith array, and goes from O to N, A i+n  is thus the amplitude of the (i+n)th echo, # is the phase of the transmitted pulses (assumed constant or coherent) and # i+n  is the phase shift of the (i+ n )th echo), a set of weighting means for weighting each of the echo signals by a respective group of factors F n =W n e<SP>-j#n</SP>, to give a group of weighted signals which are stored, and means for combining the stored weighted signals with other weighted signals produced from different echo signals to give a running output signal Sx having a maximum value when the target T is abreast of the aircraft. The running output signal Sx synthesizes the output of the synthetic aerial array and has a magnitude (ignoring the constant factor e<SP>i#</SP>) given by This signal is produced in terms of its real and imaginary parts In a first embodiment, Fig. 2, which shows the means for obtaining either the real or the imaginary parts (depending on the signs of the inputs to amplifiers Al-AN), the echo signal has been divided into its A l Cos# l  and A l Sin# l  components. For the first echo in a particular ith synthesis, the component A l Cos# l  is multiplied by factor W 1 Cos# 1  by means of a resistor RC1 to give | A l Cos# l .W 1 Cos# 1  |. Similarly component A l Sin# l  is multiplied by W 1 Sin# 1  by resistor RS1 to give | A l Sin# l .W 1 Sin# 1  |. The two weighted components are combined in amplifier A1 and stored in shifting-and summing register L1. At the next p.r.p. the content of register L1 is shifted into register L2 where it is summed with the output of amplifier A2, i.e. Thus at the end of N p.r.p's. the original content of register L1 has shifted to register LN accumulating further amplifier outputs as it goes, to give in register LN the real or imaginary part of | Sx |. At the next p.r.p., the content of register LN - will be said part corresponding to the synthetic array formed from aircraft positions P i+1  to P i+N+1 . In a second embodiment, Fig. 3, which shows the means for obtaining the real part of | Sx | , the components A i Sin# i  and A i Cos# i  of the first echo are stored during a p.r.p. at 4 and 3 respectively so that they can be multiplied at 8 and 7 with the outputs of signal generators 6 and 5, i.e. W 1 Cos# 1 , W 2 Cos# 2  ... W N Cos# N  and W 1 Sin# 1 , W 2 Sin# 2  ... W N Sin# N  respectively. The product signals are combined in adder 9 to give a sequence of signals starting with (A i Cos# i .W 1 Cos# 1 +A i Sin# i .W 1 Sin# 1 ), followed by (A i Cos# i W 2 Cos# 2 +A i Sin# i .W 2 Sin# 2 ), followed by &c., until the sequence is finished by (A i Cos# i .WCos N # N +A i Sin# i .W N Sin# N ). The sequence of signals is progressively fed along N + 1 stage shift register until at the end of the sequence the signal (A i Cos# i .W 1 Cos# 1  + A i Sin# i .W 2 Sin# 2 ) is stored in stage LN and the last signal (A i Cos# i .W N Cos# N +A i Sin# i .W N . Sin# N ) is stored in stage L1. By the addition of a voltage at 11 and the subtraction of that voltage at 12, both positive and negative values of the signals can be stored. During the next p.r.p.; the process is repeated using the components A i+1 .Sin# i + 1  and A i+1 .Cos# i+1 . As the sequence of product/sum signals is fed into the register a feed back loop adds the content of the (N+1)th stage to the next signal to be stored in the 1st stage. An accumulation process thus takes place over (N+1) p.r.p's. during which the terms of R | Sx | are accumulated in a stage of the register which advances from the 1st to the (N+1)th whence R | Sx | is read out over line 14. The circuit of Fig. 3 is for one range increment only since the weighting factors, performing as they do a focusing action, are different for each increment. However the change in weight factors from one increment to the next is small enough for groups of increments to be treated in the same circuit, the circuit having the components for the successive increments successively applied to it, uses a respective shift register for each increment, Fig. 4 (not shown). To overcome the necessity for the plural shift registers to shift at a greater speed than that of Fig. 3, the shift registers may be connected in series and clocked sequentially, Fig. 5 (not shown).