Patent RU-2152685-C1 (RU)
Title: Multiple-channel pulse counter
Inventor: EGOROV L B
IPC: H03K23/66
Filed: 1999-01-19
Granted: 2000-07-10
Abstract: FIELD: automation and computer engineering. SUBSTANCE: device has random access memory unit 1, initial setting unit 2, control unit 3, initial setting line 4, address line 5, parity flip-flop 6, carry flip-flop 7, N XOR gates 8-1, 8-2, ..., 8-N, N OR gates 9-1, 9-2, ..., 9-N, N NOR gates 10-1, 10-2, ..., 10-N. Random access memory unit is designed as N memory registers 11-1, 11-2, ..., 11-N, which address inputs are connected to address line 5. their access inputs are connected to control output of initial setting unit 2. The first storage inputs of memory registers 11-1, 11-2, ..., 11-N are connected to second input of initial setting unit 2 and storage line 12. The first information inputs of memory registers 11-1, 11-2, ..., 11-N are connected to respective information outputs of initial setting unit 2. The second information input and direct output of memory registers 11-1, 11-2, ..., 11-N is connected to respectively first and second inputs of respective XOR gate 8-1, 8-2, ..., 8-N. The second storage inputs of memory registers 11-1, 11-2, ..., 11-N are connected to outputs of respective NOR gates 10-1, 10-2, . . ., 10-N. The inverting outputs of memory registers 11-1, 11-2, ..., 11-N-1, except the last one, are connected to first inputs of the respective next NOR gate 10-2, 10-3, ..., 10-N. The first inputs of XOR gates 8-1, 8-2, . . ., 8-N-1, except the last one, are connected to output of the respective next NOR gate 8-2, 8-3, ..., 8-N. The first input of the last XOR gate 8-N is connected to first output of control unit 3. The output of first XOR gate 8-1 is connected to first input of control unit 3 and information input of parity flip-flop 6. The clock input and output of parity flip- flop 6 are connected to respectively second and third inputs of control unit 3. High-bit row feature line 13 and clock synchronization line 14 are connected to second and fourth inputs of control unit 3, respectively. Second and third outputs of control unit 3 are connected to first inputs of respectively first OR gate 9-1 and NOR gate 10-1, which respective second inputs are connected to fourth outputs of control unit 3. The direct outputs of memory registers 11-1, 11-2, . .., 11-N-1, except the last one, are connected to first inputs of the respective next OR gate 9-2, 9-3, ..., 9-N, which second inputs are connected to output of previous OR gates 9-1, 9-2, ..., 9-N-1, and second input of NOR gate 10-2, 10-3, ..., 10-N. Output of last OR gate 9-N is connected to information input of carry flip-flop 7, which clock input is connected to low-bit row feature line 15, and which output is connected to fifth input of control unit 3. The access line 12 and locking line 17 are connected to respectively third and fourth inputs of initial setting unit 2. EFFECT: increased stability to noise due to Gray code operations and usage of non-volatile random access memory unit, possibility of software alteration of bit-length of counting channels due to temporal connection between low and high parts of counting channels using carry and parity flip-flops. 4 cl, 2 dwg