Patent GB-918556-A (GB)
Title: Improvements in or relating to receiving apparatus for electric signalling systems of the kind in which binary information is signalled
Inventor: HAKIM SAHIR SABIR
IPC: H04L27/156
Filed: 1960-04-08
Abstract: 918,556. Frequency shift signalling; transistor pulse circuits. GENERAL ELECTRIC CO. Ltd. July 10, 1961 [April 8, 1960], No. 12603/60. Classes 40 (5) and 40 (6). In a system wherein binary information is signalled by selectively transmitting oscillations having one or other of two frequencies, the receiver includes a frequency multiplier to which the input oscillations are fed via a transistoramplifier-limiter provided with negative D.C. feed-back to stabilize the operating conditions of the transistors in the amplifier and negative A.C. feed-back to stabilize the gain thereof. As described, the sinusoidal input signal, Fig. 3 (a), is applied at 2, 3 to the amplifier limiter 1, (Fig. 1) comprising cascade connected transistors 4, 5 and 6. Noise is limited by a diode 9, and emitter-follower stages 7, 8 equalize the A.C. and D.C. loads of transistors 4, 5. Negative D.C. feed-back paths 14, 15 stabilize operation of the amplifier and a negative A.C. feed-back path 16 stabilizes gain and increases the input impedance. The output, Fig. 3 (b), of limiter 1, is differentiated in circuits 17, 18 and 19, 20, the first signal being inverted in transistor 21 and applied to transistor 22, the second signal being applied to transistor 23. Transistors 22, 23 are biased so that they pass only the negative-going portions of their inputs so that transistor 23 conducts momentarily on each trailing edge and transistor 22 on each leading edge of the limiter output pulses, Fig. 3 (b). The output developed across a resistor 24, common to the collector electrodes of transistors 22, 23, is amplified and limited in transistors 25, 26 to produce the frequency-doubled waveform, Fig. 3 (c). This signal triggers a mono-stable transistor circuit 27, 28, Fig. 2, to produce constant duration pulses, Fig. 3 (d), which are amplified at 29 and fed to a switching circuit 30 comprising a transistor 31 which conducts only when pulses are passed to it by transistor 29 rapidly to discharge a capacitor 32 which is normally charged over a resistor 33. The potential across this capacitor is thus of sawtooth form, Fig. 3 (e), of twice the frequency of the input oscillations, Fig. 3 (a), the sawtooth durations (and hence their amplitudes) having one or the other of two discrete values corresponding to the timing of the respective input waveforms of Fig. 3 (a). This voltage is applied via transistor 34 to a low-pass filter 35 whose output follows (after a short delay) the voltage envelope across capacitor 32, Fig. 3 (f). This signal is applied by way of transistor 36 to an amplifier-limiter stage 37, temperature-controlled by a thermostat 38, and providing an output having two voltage levels corresponding to the two input frequencies, Fig. 3 (a). This is inverted in transistor 37 to produce the recovered binary information output signal, Fig. 3 (g), at terminal 40. Modification. A third condition may be signalled and represented either by simultaneously sending both frequencies or neither of them. In the latter case detection is effected by additional circuitry responsive to the signals developed at the output 40 and at point 41 in the emitter circuit of transistor 36. The output at 40 is amplified without inversion by two cascade connected transistors and that at 41 is amplified by one transistor with inversion. The uninverted and inverted signals are applied to a diode switch which gives an output by following the more positive of the two signals applied thereto, and in an example, gives zero output when the third condition is signalled and a positive or negative output, respectively, for the two binary conditions.