Patent GB-1491691-A (GB)
Title: Display apparatus
IPC: G09G5/08
Filed: 1974-11-04
Abstract: 1491691 Memory addressing for a display TELETYPE CORP 4 Nov 1974 [9 Nov 1973] 47669/74 Heading G4A [Also in Division H4] A memory addressing arrangement is described for accessing data in a memory storing n rows of data for display on a display device capable of displaying only m rows of data simultaneously where m < n. As described a memory 10 stores 72 rows of data and supplies a visual display device 12, e.g. a C.R.T., capable of displaying only 24 rows at any one time. The system is controlled by instructions read from a ROM 18 by an address loaded in register 38, the address being derived either by incrementing the previous address (a pulse at input 42), or by loading an address from multiplexer 40 (a pulse at both inputs 42, 44), this address being derived either from the previous instruction (lines 52) or, in response to a signal on line 48 indicating that the previous instruction sequence is complete, from an external source 16, e.g. a keyboard. Any section of 24 rows of data may be displayed by loading the address of the first row in scroll counter 24, loading this address in row counter 26 in response to a vertical retrace signal 104 from the display indicating that a complete display has finished, and incrementing the address in counter 26 in response to horizontal retrace signals 100 from the display indicating that a row has been displayed. Should the display start at an address >49 then at some point during the display the display address will reach 72, its maximum. On the occurrence of the next horizontal retrace signal the address 72 is recognized by decoder 130, AND 132 is energized, and the contents of counter 26 are reset to the address of the first row in the memory. The address of the start of the display in scroll counter 24 may be incremented or decremented in response to commands, decoders 120 and 124 acting when the address is incremented beyond 72 and decremented below 1 to reset the address to the first and last rows respectively in a manner similar to that performed by decoder 130 for the display row address. A cursor may be displayed at an address determined by the contents of counter 34. This address may be decremented or incremented in response to commands, decoders 156 and 160 operating in the same way as decoders 120, 124 for the scroll address counter 24. To prevent the cursor being moved off the current display the address of the start of the display SOD from scroll counter 24 or the address of the end of the display, derived by generator 30, depending on whether the cursor is being moved up or down the display, is compared with the cursor row address so that, e.g. in the situation where the cursor is being moved up and has reached the first row being displayed (SOD) a match signal from comparator 36 causes the display to be shifted by decrementing the start of display address in scroll counter 24 so that the cursor is still shown on the display. A command is also provided to advance the start of display address in scroll counter 24 to the next display segment, i.e. in the case where the display (24 rows) is one third of the data (72 rows), the segments begin at the first, the twenty fifth, and the forty ninth rows respectively. To this end an instruction loop is executed which, with each loop, increments the start of display address in scroll counter 24 until a signal on one of lines 66, 68, 70 indicates that one of the segment start addresses has been reached whereupon an exit is made from the loop.