Patent GB-1321067-A (GB)
Title: Digital calculating apparatus
IPC: G06F7/552
Filed: 1970-08-13
Abstract: 1321067 Digital calculators SOLARTRON ELECTRONIC GROUP Ltd 9 Aug 1971 [13 Aug 1970] 39123/70 Heading G4A A digital calculator includes two shift registers. Each register has its output connected to its input via an adder. A number read from each register has added to it a positive or negative number, the result being fed back to the register. The operation may be repeated to give a group of N adding (or subtracting) cycles for one register, the other register simultaneously undergoing M cycles. M is less than or equal to N and may be 1. The added or subtracted number is one of a set of decreasing terms, e.g. 1, 0À1, 0À01... (referred to as a linear progression), or is the number in the register divided by one of a succession of increasing powers of the radix of the number system used, e.g. 10‹, 10<SP>1</SP>, 10<SP>2</SP> ... (referred to as an exponential progression). When the number in the first register has reached a certain value the added or subtracted number is changed according to the next term in the progression and a further group of N and M cycles is undergone. When the number in the first register has converged sufficiently closely to a predetermined (target) value the number then in the second register represents the calculator output. The calculator can multiply or divide, or form roots, log values, or trig values. In a first example, Fig. 1, for forming the square root of a binary coded decimal number x the number x is loaded into the two BCD registers 12, 12<SP>1</SP>. Considering register 12, initially gate 22 is enabled so that the number in register 12 is added to itself in a known adding circuit comprising adders 14, 16, and unit 18 which generates BCD digit 6. This operation is repeated once, i.e. N=2. If an overflow bit has not yet appeared in stage 13 of register 12 a further group of N operations occurs. When overflow occurs a bit in register 24 is moved to the next stage (p=1) to enable gate 26. The number now passed to the adding assembly via gate 26 is one tenth of the number in register 12 and is subtracted from that number. This operation is repeated once and register 24 again stepped The number fed to the adder assembly now is one hundredth of the number in register 12 and is added. Further operations occur until the bit in register 24 returns to the first stage (p=0), the number in register 12 now being close to the target value 1. The other BCD register 12<SP>1</SP> and adder assembly proceeds in a similar manner except that each operation occurs only once, i.e. M = 1. When the operations cease the number in register 12<SP>1</SP> is the square root of the original number x. In this example the number whose root is to be extracted is floated to lie in the range 0À010- 0À999. In a second example, Fig. 4 (not shown), the square root of a binary number is calculated. Each register comprises two parallel registers, the content of one register of each pair being divided by 2<SP>p</SP> before it is added to or subtracted from the content of the other register, p being 0, 1, 2, 3... The binary point is floated by circuitry described with reference to Fig. 6 (not shown).