Patent GB-1289999-A (GB)
IPC: G11B27/32
Filed: 1969-09-22
Abstract: 1289999 Dynamic memory addressing BURROUGHS CORP 22 Sept 1969 [23 Sept 1968] 46463/69 Heading G4C A dynamic data store such as magnetic or optical disc has an address track divided into prerecorded code groups each identifying a sector containing a number of storage locations on a data track, an address register for storing a number of binary digits identifying a required storage location, a means for comparing the successively accessed groups of sector identifying bits with an equal number of bits stored in the address register which form only a part of the address stored in that register, and a counting means for performing a binary count of pulses corresponding to individual storage locations in a sector for which a positive comparison has been made which count is compared with the remainder of the address register contents in order to locate the required storage location within an addressed sector. Addressing.-The sector addresses consist of four bits, corresponding to four storage locations within each sector, are read by transducer 32, and are fed via inverters to AND gates 42 and 44. Clock pulses, one for each storage location, are read from a clock track by transducer 30 and are passed via clock generator 69, synchronizing circuit 71, and counter 72, to decoder 70 which applies timing pulses T1-T4 cyclically to lines 62, 64, 66 and 68 in synchronism with the clock pulses. The pulses T1-T4 enable AND gates 50-56 in turn and the four most significant digits of a binary address stored in register 36, indicative of a required storage sector are sequentially read out and passed via OR gate 58 for comparison with the sector identification bits at AND gates 42 and 44. The clock generator 69 serves to produce two pulses t #1  and t #2  for each clock pulse read from the disc. The timing signal T 1 is sent over channel 118 to AND gates 112, 114 and 116. AND gate 112 passes a signal to flip-flop 108 on the simultaneous occurrence of signals T1, t #2 , a signal on line 120 indicating that store access is to be made, and a signal on line 22 from OR gate 48 indicating that the first digit from the register 36 and the address track have been successfully compared. Flip-flop 108 will thus be set and will remain so if the remaining three digits from store 36 and the address track are successfully compared. Thus if a complete match is obtained flip-flop 110 will become set at time T1 during the reading of the succeeding sector address and will enable AND gate 126 on line 124. It will be seen that the address track on the disc is accessed one sector prior to the corresponding data sector so that at the end of the comparison a signal is provided which will allow the correct data location to be accessed. The determination of which location within the addressed sector is required is made by means of a comparison of the contents of the two least significant places in register 36 with those of counter 72. The true and complementory outputs of counter 72 are passed via lines 100-106 to AND gates 82-92, the second inputs to which are constituted by the true and complementory values of the two least significant bits in register 36. Thus as the counter 72 advances in response to the reading of the bits of the succeeding sector address following a successful comparison, the count will be compared by gates 82-92 with the two least significant bits in register 36 which indicate, in binary, the position, 1-4, of the required bit within the sector. Gate 126 will pass a signal at the appropriate time and a data head 34 will be selected by control device 78. Synchronizing arrangements.-Successive sector addresses differ by "one"; the first (i.e. the least significant) digit of each sector address being different from that of the adjacent addresses. If the binary counter 72 is correctly synchronized with the pulses from the address track 26 the flip-flop 150, Fig. 6, will reset at the beginning of alternate sectors having a binary "1" as the first bit of their address and will set thereafter on the occurrence of a binary zero. At least one input to OR gate 164 will thus be "high" and the counter 72 will continue to function. In a non-synchronized condition the flip-flop is reset at times T2 when a "1" appears on the address track. The non-synchronized condition will be corrected during the reading of seven consecutive "1'"s in the last two address sectors when the inputs to gate 164 will be negative for a number of bit periods dependent on the correction required and the counter 72 will be inhibited for the duration of that number of bits. In a modification, Fig. 7 (not shown), an arrangement is described where the correction is made within a few bit times of the fault occurring and not at one fixed point during the rotation of the disc. Modifications.-In an embodiment a disc store, having a larger number, e.g. 2<SP>11</SP>, of bits per track is described. In this case each sector address consists of eight bits and a three bit counter is used in place of the two bit counter 72. In a further embodiment, Fig. 14 (not shown), two sets of n discs are used, each set being independently driven. One disc of each set stores the clock and sector address tracks, each sector address being up to 16 bits in length, and a four bit counter is used. A separate circuit for selecting which set of discs is to be accessed is provided, otherwise the system is analogous with that described above with reference to Fig. 1.