Patent EP-1103979-A1 (EP)
Inventor: FERRANT RICHARD
IPC: G11C11/412
Filed: 2000-11-16
Abstract: The dynamic random access memory device comprises a planar memory incorporating an array of memory cells, a read/write amplifier (AMLE) connected to the extremity of each column of array, a pair of input/output lines (IO, ION) associated with the array, and a stage of cache-memory (MCH) connected to each amplifier and located in the immediate vicinity of amplifier. The stage of cache-memory comprises a static random access memory cell connected between the read/write amplifier (AMLE) and the pair of input/output lines (IO, ION). The static random access memory cell comprises two memory transistors (TM3, TM4), a pair of first access transistors (T9, T10) connected between the amplifier and the memory transistors, and a pair of second access transistors (TA1, TA2) connected respectively between the pair of input/output lines and the memory transistors. The holding means comprise the access transistors (TA1, TA2) capable to maintain a binary datum in the cell, preliminary transferred from a memory cell via the amplifier. The access transistors (TA1, TA2) have the leakage currents more significant than other transistors of the cell. In the second variant of device, the static random access memory cell comprises a pair of auxiliary transistors, which are constantly in off-state and connected between the memory transistors and a supply voltage; the auxiliary transistors have the leakage currents more significant than other transistors of the cell, and the holding means comprise the auxiliary transistors. The access transistors (TA1, TA2) and the auxiliary transistors have the length of channel and the thickness of gate oxide layer smaller than those of other transistors of the cell. The holding means comprise a voltage regulator capable to apply a substrate effect voltage to each transistor of the cell, with the exception of second access transistors and auxiliary transistors, in order to obtain the leakage current of each auxiliary transistor or second access transistor higher, preferentially at least ten times higher, than the leakage currents of other transistors of the cell. The holding means comprise the means for the application of different biasing voltages to the nodes of second access transistors or auxiliary transistors in order to obtain the drain-source currents higher, preferentially at least ten times higher, that the leakage currents of other transistors of the cell. The array of memory cells comprises seveal sub-arrays respectively associated with the pairs of different input/output lines, where all stages of cache-memory associated with one sub-array are all connected in parallel to the pair of input/output lines associated with the sub-array. The planar memory comprises a block-memory formed by two arrays of memory cells, and the amplifiers, the stages of cache-memory and the pairs of input/output lines are common to both arrays. The planar memory comprises several block-memories, and the pairs of input/output lines are common to different block-memories. The device comprises at least two stages of cache-memory respectively connected in parallel to each amplifier. The method for reading a datum stored in a memory cell of planar memory includes the transfer of datum into the cell of static random access memory of the stage of cache-memory associated with the column containing the cell, and then reading the content of cell by the intermediary of input/output lines.