Patent RU-2106062-C1 (RU)
Title: Digital automatic signal corrector
Inventor: RUBTSOV V A
IPC: H04B3/06
Filed: 1992-12-18
Granted: 1998-02-27
Abstract: FIELD: communications. SUBSTANCE: device has non-recursive filter which comprises N+1 multipliers, which outputs are connected to inputs of adder, which output serves as filter output. In addition device has error signal detector, N-stage shift register for error signal which has N+1 terminals, N+1 gain control units, each of which has first AND gate and reverse counter. Terminals of N-stage shift register of error signal are connected to corresponding input of error signal of corresponding gain control unit, which has clock input. In addition device has linear delta-modulator for input signal, which input serves as input of digital automatic signal corrector. In addition device has serial circuit of double integrator and solving unit which output serves as output of digital automatic signal corrector. In addition device has serial circuit of low-pass filter, linear delta-modulator of error signal and delta multiplier by constant factor. In addition device has serial circuit of switch of test signal circuit and delay gate. Non-recursive filter has N-stage shift register which has N+1 terminals, which input serves as input of filter. Each of N+1 multipliers is based on XOR gate, which one input is connected to corresponding terminal of N-stage shift register and another terminal is connected to output of corresponding introduced flip-flop. Output of XOR gate serves as output of multiplier. In addition each gain control unit has second and third AND gates and delta-complete adder, which output is connected to control input of reverse counter, which counting input is connected to output of third AND gate. Outputs of first and second AND gates are connected to first and second inputs of delta-complete adder. Outputs of reverse counter serve as overflow and reset outputs of gain control unit and are connected to inputs of corresponding flip- flop which output is connected to first input of second AND gate of corresponding gain control unit. Second inputs of first, second and third AND gates serve as test signal inputs. First input of first AND gate serves as input for error signal, first input of third AND gate serves as input of clock signal in each gain control unit. Output of linear delta-modulator of input signal is connected to input of non- recursive filter which output is connected to input of double integrator. Input and output of solving unit are connected to first and second inputs of error signal detector, which output is connected to input of low-pass filter. Output of solving unit is connected to input of switch of test signal circuit. Output of delay gate is connected to inputs of test signal of N+1 gain control units which error signal inputs are connected to corresponding terminals of N- stage error signal shift register, which clock signal input is connected to inputs of clock signal of N+1 gain control units, clock inputs of linear delta-modulator of input signal, of linear delta- modulator of error signal, non-recursive filter. It also serves as first clock input of digital automatic signal corrector, which second clock input is clock input of solving unit. EFFECT: tuning by test signal before delta-modulated input signal data transmission, simplified design. 2 dwg