Patent GB-712172-A (GB)
Title: Improvements in or relating to electronic circuits for multiplying binary numbers
Inventor: WILLIAMS FREDERIC CALLAND
IPC: G06F7/52
Filed: 1949-03-14
Abstract: 712,172. Digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. March 13, 1950 [March 14, 1949; April 20, 1949], Nos. 6985/49 and 10527/49. Class 106 (1) In an electronic circuit arrangement for, and method of, multiplying two binary digital numbers, the multiplier R is repeatedly examined and a control signal is derived corresponding in turn with the " 1 " digits starting with the lowest, each control signal being used to dynamicize the multiplicand and add it in an accumulator store. The multiplicand is thus added in denominational positions of the accumulator corresponding to the significance of the multiplier digits. Provision can be made for multiplying negative numbers represented by their binary complements. General arrangement.-As shown in Fig. 3b, the multiplier R and multiplicand D are registered on separate lines of a C.R.T. store CR1 such as is described in Specifications 645,691, 657,591 and 705,474 each line having a capacity of 40 digits, and the product is registered on two lines of an accumulator C.R.T. store CR2. Each store has the usual regeneration circuit comprising an amplifier and reading and writing units. In addition, a gate 8 is provided for erasing the multiplier digits one at a time during multiplication, and an adding unit 14 in the accumulator. The apparatus is designed to be part of a computor, e.g. as described in Specification 705,479, the lines on the C.R.Ts. being scanned according to the system described in Specification 682,156 in which scan periods or "beats" alternate with action beats. Each beat comprises 45 digit periods defined by P- pulses Po-P44, see Fig. 1 (f, g, h, j); numbers or "words" are represented by pulses, Fig. 1 (k), coincident with pulses Po-P39, and are separated by black-out periods, Figs. 1(e) and 2(b), timed to permit fly-back of the main timebase wave form, Figs. 2(c) and 4(a), which is applied to CR2. Fig. 1(a-d) shows the basic waveforms usually employed with C.R.T. stores. The cycle of operations required for carrying out an instruction, normally occurring in 4 beats and called a " bar". Fig. 2(h), is initiated by a prepulse, Fig. 2(a), at the beginning of the first scan beat S1. In multiplication, the multiplicand D is written into CR1 during four beats (instruction sD, Fig. 4) but the entry of the multiplier (instruction sR) and the multiplication operation which follows automatically require a longer bar so that the prepulse is inhibited, Fig. 2(a), and a multiply-initiating " S3 gate " pulse, Fig. 2(h), is produced. Multiplying sequence.-As illustrated in Fig. 4(a) and (b), the time-base waveform applied from the generator 20, Fig. 3a, to CR1 is normally synchronous with the main time-base since if is controlled by a trigger R which is switched over by pulses P44 applied to a gate 22 and reset by pulses P39 applied to gale 24. The D line is normally scanned due to the condition of a two-state trigger circuit in the Y-shift generator 4 (see Fig. 4(c)). For instruction sR, pulses from an instruction staticisor of the associated computor at the end of beat S2 switch over the Y-shift trigger and a control trigger F, Fig. 3a, thus shifting over to the R line and producing a prepulse-inhibiting wave FR, Fig. 4(c) and (d) The multiplier R is. written in during the following beat A2 and at the end of beat S3, the gate pulse, Fig. 2(h), resets trigger F which then applies a pulse to a trigger M which remains on until the end of multiplication (see wave Mo, Fig. 4(e)). Since Mo is now negative and the inverted wave M1 positive, gates 23, 25, Fig. 3a, are opened in place of 22, 24, so that the multiplier time-base sweep, Fig. 4(c), is started in beat A3 by pulse P41 and, since line R is being scanned and wave YD (the inverse of YR) is therefore negative, the trigger R is reset, to cause fly-back of the time-base wave, by a control pulse from unit 6, Fig. 3b, when the first multiplier digit " 1 " is read. At the same time, wave R0 is passed through gate 31, Fig. 3a, to shift over to line D, Fig. 4(c). This control pulse is passed through a delay device 27 (described below) so as to switch over the trigger two digit periods later to begin the scan of the multiplicand which is read out from unit 6 and passed through a gate 15 to the adding unit 14, associated with the store CR2 of the accumulator 2, which may be of the form described in Specification 683,882. The lines of CR2 are scanned alternately during action and scan beats, part of the multiplicand being added into each line. A pause during the fly-back and line-shift period is produced by feeding the black-out wave through a gate 28 controlled by the wave Mo and a halver wave HA, Fig. 2(e). The trigger R is reset 45 digit periods later by a delay device 26 (described below) to which wave YD is applied through a gate 29 controlled by waves M1 and R1, and is switched over at the beginning of the next action beat A4 by pulse P41. The multiplier R is then scanned as in A3 but as the first digit " 1 " was erased by gate 8 (described below), the next digit " 1 " determines the timing of the read-out of the multiplicand. The process continues until no " 1 " digits remain on line R when pulse P37 during an action beat An is passed through a gate 18 controlled by waves YD and HS, Fig. 2(d), to reset trigger M and end multiplication. The Y-shift trigger is then reset by the next prepulse or by the back edge of a wave M' (the inverse of Mo, Fig. 4(f), obtained by passing Mo through a delay device 19). Multiplying negative numbers.-Figs. 5a and b show the modifications required in the arrangement of Fig. 3b where the multiplier and/or the multiplicand may be negative and represented by the binary complement. A complement-converting unit (block 34, described below) is inserted between the unit 6 and gate 8 and is controlled by a sign-registering unit (block 33) which also determines whether the product shall be added or subtracted in the accumulator 2a. Entry of the numbers D and R is effected by special instructions s' D, s' R which cause gates 41 and 43, 44 or 46, 47 to be opened during beat A2 and the following beats S1 or S3. Thus, when the multiplicand D is written into the store CR1, Fig. 3b, during a beat A2, it is also applied to gate 41 and if the highest digit, coincident with pulse P39, is a " 1 " (meaning that D is a complement) the trigger 40 will be switched over thus allowing operation of, or " unclamping ", the trigger circuit 39 by the first multiplicand digit " 1 " read out during the following scan beat. The remainder of the read output will then be passed through a "not" device 36 and gate 38, instead of gate 37, thus de-complementing or producing the original number D, and the sign is registered by a trigger 42 operated by a pulse from trigger 40 passed through gate 43, the previous sign registration being erased by the waveform of Fig. 2(g) through gate 44. At the end of the scan beat, trigger 40 is reset by wave Hs, Fig. 2(d), so that trigger 39 is " clamped" in the normal non-complementing condition. Similar operations occur for the multiplier R, the product-sign-registering trigger 45 being switched to the condition of trigger 42 when gates 46, 47 are opened and being subsequently switched by a pulse from trigger 40 if R is negative. A potential is then applied during multiplication via a gate 48 or 49 to open an add or subtract gate 35a or 35 according to whether the product is positive or negative, a subtracting unit 14b being provided in parallel with the adding unit 14a. Circuit details.-Detailed circuit diagrams are provided in the Specification for the units within blocks 3, 4, 9, 10, 33 and 34. Figs. 3a, 5a and 5b, and also for units 6, 7 and 8. The circuits for (1) the delay unit 26, (2) the delay unit 27, and (3) the gate 8, complement-converting unit and associated trigger 40, are described below as illustrating the principles employed. (1) In the 45- digit delay unit or counter 26, Fig. 43a, negative pulses from the anode of a gate valve V1301 are applied through a differentiating circuit to the anode of a valve V1302, between the dash pulses continually applied to the control grid of V1301, as soon as the waves YD, M1, R1 are all made positive thereby raising the suppressor grid potential through diodes D1301-D1303. The valve V1302 is connected in a delayed-response circuit as described in Specification 582,758, [Group XL], and is arranged to produce an output pulse at its cathode, Fig. 14(1), for every fifth applied pulse. These output pulses are applied to a similar circuit including a valve V1303 whose delay time is about 47 digit periods, Fig. 14(2), and the negative pulse at the cathode of V1303 triggers a valve circuit (not shown) of the kind described in Specification 587,364, [Group XL], (called a "santrig") to which are also applied positive resetting pulses from the screen grid of V1302. The santrig is so adjusted that it is reset by the ninth pulse after triggering occurs so that the anode potential of a valve V1306 (not shown) which was lowered when the santrig was triggered is restored 45 digit periods later, Fig. 14(3), thus providing a pulse to reset the trigger R, Fig. 3a. (2) In the delay unit 27, Figs. 3a and 15, the pulse from gate 25, Fig. 16 (3), differentiated by a circuit C1521, R1560, charges a condenser C1522 and raises the control grid potential of a valve V1507, Fig. 16(4). The next positive dash pulse, Fig. 16 (2), applied to the suppressor grid produces a negative anode pulse, Fig. 16(5), which is applied through another differentiating circuit to a condenser C1525 and the control grid of a valve V1508, Fig. 16(6). Current then flows to the screen grid whose lowered potential, Fig. 16(7), is applied to the control grid of V1507, Fig. 16(4), and the next positive dash pulse produces a negative output pulse at the anode of V1508, Fig. 16(8), which switches over the trigger R. T