Patent GB-1249119-A (GB)
Title: Improvements in or relating to electrical oscillator arrangements
Inventor: ALLEN RODNEY DAVID
IPC: H03L7/181
Filed: 1968-02-09
Abstract: 1,249,119. Automatic frequency control systems. PLESSEY CO. Ltd. 31 Jan., 1969 [9 Feb., 1968], No. 6613/68. Heading H3A. The invention relates to an arrangement whereby the frequency of a variable-frequency oscillator may be held constant when set at any frequency within its range: according to one aspect it comprises means for timing a predetermined number of pulses from the oscillator, a standard reference means for signifying a time period corresponding to a number of pulses from the variable-frequency oscillator when tuned to the desired frequency, and means for comparing the same time period with the timing of the predetermined number of pulses to derive a difference quantity utilization for the correction of the variable-frequency oscillator. The arrangement counts in counter A, Fig. 1, the number of cycles N from fixed frequency standard 12 in a time Tv necessary to fill counter B with oscillations from variable-frequency oscillator (VFO) 1; the value N is stored and subsequently the time T # <SP>1</SP> for the counter B to fill with oscillations from the variable-frequency oscillator is compared with Tv, the amount and polarity of any difference indicating the magnitude and sense of any variation in the frequency of VFO and being used to correct it. As an alternative, the number of cycles N<SP>1</SP> of the frequency standard occurring in subsequent periods T # <SP>1</SP> necessary to fill counter B may be counted and the magnitude and polarity of (N-N<SP>1</SP>) used to correct the VFO. Mode switch S 1  can be set to a " free tune " position, in which relay contacts RS 1  are open, breaking the feedback path used for correcting the VFO. With the switch in closed position contacts RS 1  are closed, completing the feedback path, and contacts RS 2  close to apply a positive potential to differentiator ciruit 3, the differentiated output of which resets frequency counters A, B, B 1 , C and also bi-stable stage X. When reset, counter B counts pulses received from VFO 1 via input lead 4 and when full an output pulse on lead 5 triggers bi-stable stage X, which produces two antiphase outputs 6, 7. Output 6 triggers gate 8 between frequency standard 12 and the " subtract " input of a reversible counter A. Output 7 triggers gates 9, 10 and provides one input to AND gate 13: gate 9 is between frequency standard 12 and the " add " input of reversible counter A and gate 10 is between frequency standard 12 and counter C. AND gate 13 provides a trigger input to gate 11 interposed between an output from VFO 1 and a further counter B 1. When bi-stable stage X is switched to its reset condition by output from differentiator 3, an output on lead 6 opens gate 8, allowing pulses from frequency standard 12 to be applied to the " subtract " input of reversible counter A, which then counts in a negative sense. When counter B becomes full an output on lead 5 triggers bi-stable stage X, transferring its output from lead 6 to 7, closing gate 8 and opening gates 9, 10. Lead 7 is also coupled to AND gate 14, the second input of which is derived from the output of counter C: when this is at zero it applies an output to gate 14 which with the signal on lead 7 resets bi-stable stages Y, Z. When counter B becomes full, the triggering of bi-stable stage X stops counter A from counting and resets bi-stable stages Y, Z so that outputs are obtained over output leads 15, 16 respectively; the output from bi-stable stage Z also forms a second input to AND gate 13. Assume when counter B is full count in counter A is -N; when bi-stable stage X triggers, gates 9, 10, 11 are opened to feed counters A, C from frequency standard 12 and counter B1 from VFO 1. The pulses fed to counter A go to its " add " input until the total count is zero, when an output is obtained on lead 17 which triggers bi-stable stage Y so that the output on lead 15 disappears. At this point counter C will have counted N pulses and counter B1 will be at some condition dependent upon the frequency of VFO 1; if this frequency has remained constant counter B1 will be full when counter A reaches zero, an output is obtained over lead 18 and bi-stable stage Z is triggered so that the output on line 16 disappears at the same time as that on lead 15. If the frequency of VFO 1 has increased, however, counter B1 will become full and trigger bistable stage Z before counter A reaches zero, while if the frequency has become lower counter B1 will be only partially full when A reaches zero. In this case the counters would continue to count until counter B1 becomes full and triggers bi-stable stage Z. The outputs from bi-stable stages Y, Z are compared in a pulse length comparator 19 to obtain a signal proportional to the difference in pulse lengths obtained over leads 15, 16; any difference is proportional to the change in frequency in VFO 1 in its amplitude and polarity and is used to apply a correction to VFO 1 via lead 20, a smoothing circuit 21 being interposed as the error detection process is not continuous. Counters A, B 1, C continue to count their respective pulses until counter C reaches zero, when reversible counter A will have counted - N pulses and counter B 1 will be at zero; counter B1 is arranged to give an output pulse over lead 18 when passing from " full condition back to zero condition, so that resetting of this counter except at the beginning is unnecessary. When an output is received from counter C, at zero count, there is an output from AND gate 14 which triggers bi-stable stages X, Z so that outputs are obtained over leads 15, 16 respectively. The process is repeated, counters A, B1 C counting until reversible counter A reaches zero and counter B1 becomes full at which time the pulse lengths of the outputs from bi-stable stages Y, Z are again compared. Counters B, B1 are identical and not used simultaneously and so could be replaced by a single counter wih suitable switching. The frequency at which VFO 1 oscillates may be indicated by feeding value N to a register control-  ling a numerical display.