Patent GB-962333-A (GB)
Title: Improvements in or relating to pulse code encoding and decoding circuits
IPC: H03M1/00
Filed: 1960-10-27
Abstract: 962,333. Pulse code modulation systems. WESTERN ELECTRIC CO. Inc. Oct. 27, 1960 [Nov. 30, 1959], No. 36881/60. Heading H4L. In a pulse code modulation system the binary coder comprises a storage capacitor for storing signal amplitude samples, means for supplying successively decreasing reference signals to the storage capacitor to reduce the amplitude of the signal sample, means for determining if the reference signal applied at any instant to the storage capacitor is of opposite polarity to the remaining portion of the signal sample, and means for transmitting an output pulse only when the remaining portion of the signal sample on the storage capacitor after each determination is of one predetermined polarity. A decoder operating in the converse manner is described. The reference signals at the coder and decoder are provided by a plurality of ferroelectric capacitors. At the coder. Fig. 1, signal samples passed by a gate 11 are stored by a capacitor 15 and supplied via AND gate 13 to control a bi-stable circuit 14 to energize lead 51 if the stored signal is positive or lead 52 if it is negative. A clock generator 29 supplies pulses to the various gate circuits in the appropriate time intervals. Assuming the signal is positive energization of lead 51 will enable gates 16, 17, upon removal of the inhibit pulses 104, 105 therefrom and an output pulse is provided on lead 10 which indicates that the signal is of positive polarity. The signal passed via gate 17 activates gate 18 and a reference signal representing - 32 units of charge is supplied by capacitor 25 which is one of a multiple ferro-electric capacitor block comprising capacitors of decreasing size 2532, 2516, 258, 254, 252, 251. A similar block 24 provides reference signals of positive potential and corresponding capacitors are connected in turn to the respective gates 18, 20 through a ring counter 28. The signal from the gate 18 is supplied to the capacitor 15 and the charge remaining on the capacitor 15, if positive operates the flip-flop 14 as before to effect a comparison with a reference signal representing -16 units from capacitor 2516 and another pulse is transmitted via gate 16 to the output circuit 10. If the signal remaining on the capacitor 15 is negative the flip-flop 14 will not be operated and lead 52 will be energized and there will be no output pulse on lead 10. The gate 19 will be operated to open gate 20 and a positive reference potential will be supplied from the appropriate capacitor of the bank 24 to the capacitor 15. This process is repeated until the charge on capacitor 15 is reduced substantially to zero and a pulse from the generator 29 then operates gates 22, 23, to re-charge the capacitors 24, 25, to the reference potentials. At the decoder, Fig. 3, incoming signals on the lead 10 are supplied to a shift register 60 which is set accordingly. The outputs of the shift register are connected to respective capacitors 71 to 76 of a bank of ferro-electric capacitors 61 graded in capacity in a similar manner to those of the coder, and to a further polarity-determining capacitor 62. Initially, the capacitors 61 are given a positive charge, and the capacitor 62 a negative charge of the same magnitude as the sum of the charges in capacitors 71 to 76 via the gates 63, 65. The presence of a " 1 " in any of the last six stages of the shift register causes the corresponding capacitors 61 to be connected via the operated gate 70 to charge the storage capacitor 40 correspondingly. The presence of a " 1 " in the first stage of the shift register 00, denoting a signal of positive polarity will cause the capacitor 62 to remain unconnected but the presence of a " 0 " will connect the capacitor 62 via the gate 68 to the storage capacitor 40 so as to provide a complementary output signal of the required negative amplitude level. Specifications 630,095, 717,104 and 921,384 are referred to.