baber/WOPTO huggingface dataset:
Patent TW-414885-B (TW)
Title: Timing parking charge system for credit card
Inventor: HUNG SHENG-WEN
IPC: G07B15/00
Filed: 2000-01-12
Granted: 2000-12-11
Abstract: The present invention utilize the present commonly set-up cable-network to connect the local parking management with the parking management information center, and obtain the authorization information of credit card by internet connection and digital lease line. The local parking management provides a sub-control room, which connects to a plurality of charge devices online beside the parking partitions communicates between the parking management information center and every parking partitions. A input/output equipments is set up therein for providing a service panel and control the network by connecting to cable television center with cable modem.
Patent TW-448110-B (TW)
Title: Caster
Inventor: WATANABE YASUKUNI
IPC: B60B33/04
Filed: 2000-02-03
Granted: 2001-08-01
Abstract: A caster in which a wheel is supported on a bracket (2) mounted on a wheelchair through a link (3), wherein the end part of the link (3) is connected to the rotating shaft of the bracket (2) through a rubber member (8) producing a torsional deformation according to an oscillating motion of the link (3), and the link (3) is connected to the bracket (2) through a hydraulic damper (20) damping the oscillating motion of the link (3).
Patent TW-504524-B (TW)
Title: Apparatus and process for spinning polymeric filaments
Inventor: NGUYEN YOUNG DUNG-THANH
IPC: D01D5/092
Filed: 2000-05-02
Granted: 2002-10-01
Abstract: A melt spinning apparatus for spinning continuous polymeric filaments including a first stage gas inlet chamber adapted to be located below a spinneret and optionally a second stage gas inlet chamber located below the first stage gas inlet chamber. The gas inlet chambers supply gas to the filaments to control the temperature of the filaments. The melt spinning apparatus also includes a tube located below the second stage gas inlet chamber for surrounding the filaments as they cool. The tube may include an interior wall having a converging section, optionally followed by a diverging section.
Patent TW-469734-B (TW)
Title: Display characteristic measurement device for CRT and the calibration method therefor
Inventor: HAMAGURI KENJI
IPC: H01J9/42
Filed: 2000-05-11
Granted: 2001-12-21
Abstract: To reduce a time and labor in the case of calibration of a display characteristic measurement device for a CRT. In the case of calibrating a display characteristic measurement device 1, a color display device 4 of a measured object applies white light emission to a calibration chart to display a prescribed calibration pattern, an image pickup device 2 picks up the image to capture image data (luminance data). A control section 33 uses the image data and the calibration data stored in a calibration data storage section 34 to calculate a display characteristic and discriminates whether or not an error of the calculation result is within a prescribed permissible range. When the measured error is within a permissible range, the calibration data are set as new calibration data for measurement, and when the measured error is at the outside of the permissible range, calibration processing to newly set calibration data is conducted. When the measurement within a prescribed error range is possible by using known calibration data, the calibration processing can be omitted by using the calibration data.
Patent TW-559791-B (TW)
Title: Recording capacity gauge and disc housing member
Inventor: ISHII HIROHISA
IPC: G11B33/04
Filed: 2000-08-24
Granted: 2003-11-01
Abstract: A recording capacity gauge for measuring the used capacity value and/or the vacant capacity value of a recording area of an optical disc, such as an optical disc or a magneto-optical disc, is disclosed. The recording capacity gauge includes an engagement unit engaged in a center opening of an optical disc, and a capacity display unit on which graduations corresponding to the format of an optical disc are demonstrated for extending along the radius of the optical disc. The capacity display unit allows for measurement of a used capacity value and/or a vacant capacity value of the optical disc based on a boundary position of the color tone difference between a recorded area and a non-recorded area of the optical disc. A disc tray for accommodating an optical disc is also disclosed.
Patent TW-573005-B (TW)
Title: Coke oven door with gas channel
Inventor: GIERTZ HANS JOSEF
IPC: C10B25/16
Filed: 2000-10-24
Granted: 2004-01-21
Abstract: A coke oven has a coke-oven chamber adapted to hold a mass of coke, defining above the mass of coke a gas-collecting chamber, and having a door opening. A door closes the door opening. A peripheral gas channel extends around the opening between the door and coke-oven chamber and has at least one outer and at least one inner door seal defining an annular space. The inner door seal is formed in both the coke-oven chamber and the gas-collecting chamber with a plurality of throughgoing holes forming fluid-communicating connections between the coke-oven chamber, the gas-collecting chamber, and the annular space at different heights of the coke-oven chamber and of the gas-collecting chamber. Thus regions of the coke-oven chamber with different gas pressures communicate with each other and with the annular space via the connections on the inner door seal to equalize pressure between the regions and the gas-collecting chamber.
Patent TW-478162-B (TW)
Title: A MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
Inventor: BOYD DIANE CATHERINE
IPC: H01L21/336
Filed: 2000-10-25
Granted: 2002-03-01
Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (K greater than 7) gate insulator, low overlap capacitance (0.35 fF/μm or below)and a channel length (sub-lithographic, e.g., 0.1 μm or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional complementary Metal oxide semiconductor (CMOS) technologies.
Patent TW-490440-B (TW)
Title: Process for preparing rare earth borates and hydroxyborocarbonates, device employing low voltage luminescence, and plasma system
Inventor: BRACONNIER JEAN-JACQUES
IPC: H01J11/02
Filed: 2001-03-06
Granted: 2002-06-11
Abstract: The invention concerns a process for preparing rare earth borates, and the use of these borates in luminescence. The preparation process is characterized in that it comprises the following steps mixing boric acid and a rare earth salt; reacting the mixture obtained with a carbonate or a bicarbonate; calcining the precipitate obtained.
Patent TW-478037-B (TW)
Title: Lithographic method utilizing a phase-shifting mask
Inventor: JIN FENG
IPC: G03F1/28
Filed: 2001-01-15
Granted: 2002-03-01
Abstract: Disclosed is a lithographic method utilizing a phase-shifting mask having a pattern comprising a plurality of substantially transparent regions and a plurality of substantially opaque regions wherein the mask pattern phase-shifts at least a portion of incident radiation and wherein the phases are substantially equally spaced, thereby increasing resolution of a given lithographic system. Further disclosed is a method for fabricating a semiconductor device utilizing the phase-shifting mask.
Patent TW-483802-B (TW)
Title: Method and apparatus for cleaning polishing surface of polisher
Inventor: INOUE TATSUO
IPC: B24B53/017
Filed: 2001-02-23
Granted: 2002-04-21
Abstract: A polishing surface cleaning method and apparatus are capable of effectively removing the polishing residue from the polishing surface of a polishing table in a polisher by using a minimal amount of cleaning liquid. In the polisher, a workpiece to be polished is pressed against the polishing surface of the polishing table to polish the workpiece by relative motion between the polishing surface and the workpiece. The polishing surface cleaning apparatus uses mixing spray nozzles for mixing together a cleaning liquid and a gas and spraying the resuiting fluid mixture on the polishing surface to clean it.
Patent TW-476621-B (TW)
Title: Immersionable plant tissue culture container using magnetic force
Inventor: WANG WEN-KAI
IPC: A01G31/00
Filed: 2001-03-01
Granted: 2002-02-21
Abstract: A magnetism permeable plant tissue cultivation container comprises a transparent plant cultivation container, a plate mounted with a magnetism permeable material and installed in the cultivation container, and an upper cover capable of tightly combined with the cultivation container, which is characterized in that the bottom of the cultivation container or the upper cover is installed with a electromagnetic generation device. When using a liquid medium for cultivation, the plate loaded with the plant culture can float on the medium. After the cultivation has been carried out for a certain period of time, a specific current is applied on the electromagnetism generation device mounted on the upper cover or the bottom of the cultivation container. The generated magnetic force sucks the plate mounted with a magnetism permeable material downwards until submerged in the liquid culture medium. After the submerged cultivation has been conducted for a certain period of time, the application of the electric current is stopped. Due to the disappearance of the magnetic force generated by the magnetism coil, the plate is once again floats on the culture medium, thereby completing a procedure of immersing a cultivated plant into the medium.
Patent TW-594590-B (TW)
Title: Split lot ID encoding system and method
Inventor: SHIE HUEI-JIE
IPC: G06F19/00
Filed: 2001-03-16
Granted: 2004-06-21
Abstract: The present invention is suitable for a semiconductor proprietor having multiple factories to provide a unique code for the product split to transfer among different factories, so that the central control system can easily trace and manage split products, thereby preventing the IDs of split products from overlapping and confusing. The inventive method comprises: encoding the split products into a main ID for identifying the initial ID of the earliest produced product; next, when the split position is not the initial factory, encoding a factory ID following the main ID to identify the factory that performs the splitting; and finally encoding a serial number in which a specific rule is applied to encode the serial number for the products with the same main ID and factory ID based on the split sequence.
Patent TW-501224-B (TW)
Title: Method of enhancing round corner by pulling back silicon nitride using SF6/HBr in the shallow trench isolation etching process
Inventor: LEE CHUN-HUNG
IPC: H01L21/76
Filed: 2001-03-26
Granted: 2002-09-01
Abstract: An isotropic etching step with high silicon nitride (Si3N4) to silicon (Si) selectivity is added to the shallow trench isolation process to pull back the silicon nitride and enhance the rounding of trench top corner at the same time. Pulling back the silicon nitride layer also enables a spacer to form as a buffer layer to protect the shallow trench insulation corner. Thus, steps of forming a polymer spacer and then removing the polymer spacer are eliminated, shallow trench corner is protected from exposing to cause electric failure, and the added rounding of the trench top corner avoids wrap round of the rounded trench top corner after the completion of the remaining trench isolation steps.
Patent TW-554197-B (TW)
Title: Irradiation device for producing polarized light for an alignment layer of a liquid crystal element
Inventor: SUZUKI SHINJI
IPC: G02F1/1337
Filed: 2001-04-18
Granted: 2003-09-21
Abstract: The present invention is related to the irradiation of polarized light for an alignment layer of a liquid crystal display element and the irradiation device for producing polarized light for optical alignment of liquid crystal. In particular, the invention is related to the polarization device for optical alignment of thin film suitable for view angle compensation. The object of the present is: glass plates are inclined at the Brewster angle with respect to the optical axis of the incident light beam and are combined with one another in a V-shape, in which the passing through S-polarized light is reduced so as to increase the extinction ratio of the polarized light that emerges from the polarization element. The solving means is described in the following. A light shielding plate 8b is disposed on the light incidence side of the polarization element 8 along a crest line formed on the light incidence side of two V-shaped glass plates 8a, so as to shield the light reflected by the glass plates 8a. Thus, the S-polarized light reflected by the surface of the glass plates 8a is incident on the opposite glass plates. Therefore, the S-polarized light passing through the polarization element 8 can be reduced, and the adverse effect of the reflection light on the extinction ratio can be reduced. Additionally, a light shielding plate 8b can be provided for each of plural glass plates, which are combined to form a V-shape.
Patent TW-556171-B (TW)
Title: Photorefractive holographic recording media
Inventor: ELLIOTT STEPHEN
IPC: G11B7/24044
Filed: 2001-05-15
Granted: 2003-10-01
Abstract: A holographic recording medium comprising an amorphous host material which undergoes a phase change from a first to a second thermodynamic phase in response to a temperature rise above a predetermined transition temperature; a plurality of photo-sensitive molecular units embedded in the host material and which can be orientated in response to illumination from a light source; whereby said molecular units may be so orientated when said host material is at a temperature equal to or above said transition temperature but retain a substantially fixed orientation at temperatures below said transition temperature.
Patent TW-480821-B (TW)
Title: Multiphase switching circuit with bidirectional switch and without false signal
Inventor: HUANG CHEN-CHIH
IPC: H03L7/081
Filed: 2001-05-29
Granted: 2002-03-21
Abstract: The present invention relates to a kind of multiphase switching circuit that is used between a multiphase signal generator and a following circuit. Multiphase signal generator simultaneously generates n multiphase clock signals distributed over 360 DEG, in which the phase of an arbitrary clock signal leads the phase of next clock signal. The multiphase switching circuit contains the followings. A selection signal generator is used for generating simultaneously n selection signals, in which only one signal of n selection signals has level ""1"" and the others have level ""0"". The selection signal generator is controlled by the UP/DN switching signal so as to change the upper neighboring or the lower neighboring selection signal of the original level ""1"" selection signal to level ""1"". A multiplexer, which is electrically connected to the multiphase signal generator, the selection signal generator and the following circuit, contains n multiphase switching units and an inverse OR gate operator. These phase switching units perform a falseness-prevention signal operation so as to further generate n output signals, respectively, after receiving the inputs of the corresponding clock signal, the upper neighboring clock signal and n selection signals. The falseness-prevention operation is described as follows. When the selection signal is at level ""0"" and the corresponding clock signal is also at level ""0"", the output signal sent by the phase switching unit is maintained at level ""0"". When the selection signal is at level ""1"" and the previous state of the selection signal is at level ""0"", the corresponding clock signal is transmitted to become the output signal sent by the phase switching unit if the corresponding clock signal is at level ""1"" and the upper neighboring clock signal is at level ""0"". The inverse OR gate operator outputs a target clock signal after receiving n output signals, which are outputted respectively by n phase switching units, and performing the operation. The target clock signal is used as the synchronous signal that is fed back to the selection signal generator and is supplied to the following circuit to perform applications.
Patent TW-522545-B (TW)
Title: Semiconductor memory
Inventor: SHIMADA YASUHIRO
IPC: H01L29/78
Filed: 2001-06-12
Granted: 2003-03-01
Abstract: The semiconductor memory of this invention includes an MFMIS transistor including a field effect transistor and a ferroelectric capacitor formed above the field effect transistor. The semiconductor memory has a characteristic that a value of (σ-p) is substantially not changed with time in a relational expression, V=(d/ε0)x(σ-p), which holds among a potential difference V between an upper electrode and a lower electrode, a surface density of charge σ of a ferroelectric film, polarization charge p of the ferroelectric film, a thickness d of the ferroelectric film and a dielectric constant ε0 of vacuum when a data is written in the MFMIS transistor and the ferroelectric film is in a polarized state.
Patent TW-512363-B (TW)
Title: Semiconductor memory device having sense amplifier and method for driving sense amplifier
Inventor: KIM SI-HONG
IPC: G11C7/06
Filed: 2001-06-28
Granted: 2002-12-01
Abstract: A semiconductor memory device with a sense amplifier of the present invention reduces an offset voltage between input and output terminals of the sense amplifier to improve sensing sensitivity, whereby improving cell density of the device as well as achieving a stable operation in low voltage. For the purpose of achieving the foregoing objects, the semiconductor memory device with the sense amplifier includes a plurality of switch means for sequentially turning an amplifying method of the sense amplifier to rapidly sense and sufficiently amplify the data loaded on a bit line in response to a plurality of switch control signals.
Patent TW-502552-B (TW)
Title: UV-cut film of organic electroluminescent display
Inventor: LEE RONG-HO
IPC: H05B33/14
Filed: 2001-07-09
Granted: 2002-09-11
Abstract: The present invention discloses an UV-cut film of organic electroluminescent display. The film is formed below the positive electrode (ITO conductive layer) or outside the glass substrate (illuminating face) of an organic electroluminescent display by sputtering. The film is able to prevent the organic electroluminescent display from shortening the lifetime due to decomposition of electroluminescent material in the display caused by illumination of external UV light in the operating process. The UV-cut film is formed by alternating stacked layers. In accordance with the present invention, the UV-cut film can filter out the incident light with a wavelength smaller than 400 nm, thereby effectively preventing the UV light from decomposing the electroluminescent material. In addition to filtering out the UV light, if the substrate of the organic electroluminescent display is a plastic substrate, the UV-cut film coated on the plastic substrate can prevent water and oxygen from entering into the electroluminescent layer via the plastic substrate, which may damage the electroluminescent material.
Patent TW-499798-B (TW)
Title: Techniques to implement two-dimensional compression
Inventor: ACHARYA TINKU
IPC: G06T9/00
Filed: 2001-07-27
Granted: 2002-08-21
Abstract: Embodiments of the present invention are disclosed in which two dimensional image compression, such as for bi-level images, is implemented. An integrated circuit comprising: digital logic circuitry and digital memories; said digital logic circuitry and digital memories being coupled so as to implement two dimensional compression of successive scan lines to be applied to said digital logic circuitry and digital memories.
Patent TW-498499-B (TW)
Title: Method of forming a buried stack capacitor for a one transistor RAM
Inventor: CHEN WEN-JENG
IPC: H01L21/8242
Filed: 2001-08-15
Granted: 2002-08-11
Abstract: A method of forming a buried stack capacitor for a one transistor RAM comprises: sequentially forming a pad oxide layer, a first nitride layer on a semiconductor substrate; removing a portion of the pad oxide layer, the first nitride layer and the semiconductor substrate to form a trench in the semiconductor substrate; depositing a trench filling material in the trench and on the first nitride layer; performing chemical mechanical polishing on the trench filling material until completely exposing the first nitride layer; forming a capacitance node oxide layer on the first nitride layer and the shallow trench type isolation region; forming a first photoresist pattern on the capacitance node oxide layer to define a buried stack capacitor region; using the first photoresist pattern as a mask and the first nitride layer as a hard mask to applying a self-aligned etching process to remove the exposed capacitance node oxide layer and the oxide layer of the shallow trench type isolation region; etching back a portion of the pad oxide layer beneath the first nitride layer near the recess region and a portion of the capacitance node oxide layer beneath the first photoresist pattern; removing the first photoresist pattern; etching back a portion of the first nitride layer adjacent to the recess region to expose a portion of the semiconductor substrate adjacent to the recess region; performing an ion implantation on the exposed semiconductor substrate to form an ion doped region; forming a first polysilicon layer on the semiconductor substrate; performing an ion implantation on the first polysilicon layer to form a first doped polysilicon layer; sequentially forming a second nitride layer, and an oxide layer on the first doped polysilicon layer; and applying a chemical mechanical polishing to remove a portion of the oxide layer, the second nitride layer, the first doped polysilicon layer and the capacitance node oxide layer, until exposing the first nitride layer and a portion of the shallow trench isolation region.
Patent TW-584971-B (TW)
Title: Light-emitting semiconductor element on GaN basis and its epitaxial production method
Inventor: BADER STEFAN
IPC: H01L33/00
Filed: 2001-08-30
Granted: 2004-04-21
Abstract: The present invention relates to a light-emitting semiconductor element on the GaN-basis with a semiconductor-body (11), which contains an n-conductive and a p-conductive side, and comprised of a plurality of GaN-based epitaxy layers. The semiconductor-body (11) is with its p-conductive side applied on a conductive carrier (5). On the n-conductive side of the semiconductor-body (11) is formed a contact-surface (12). To epitaxially manufacture such semiconductor elements, an epitaxy substrate is provided containing a substrate-body (1) and an epitaxy surface, wherein the thermal expansion coefficient of the substrate-body (1) is adjusted by that of the layer to be applied. The epitaxy surface is formed through the surface of an si (111)-layer (2).