Patent DE-102005006734-A1 (DE)
Title: Fabrication of split-gate transistor involves forming control gate structure conforming to side surface and including projecting portion that extends over portion of floating gate structure
Inventor: JEON HEE-SEOG
IPC: H01L29/423
Filed: 2005-02-02
Abstract: Split-gate transistor is fabricated by forming a control gate structure adjacent to an intermediate insulating structure. The control gate structure conforms to a side surface of intermediate insulating structure, and includes a projecting portion that extends over a portion of a floating gate structure. Fabrication of split-gate transistor involves forming an insulating structure having a sidewall surface with a concave region and a protruding region, which is positioned below the concave region. A semiconductor layer is etched using the protruding region of the insulating structure as an etch mask to form a floating gate structure (104a). An insulating layer is formed on the floating gate structure to form an intermediate insulating structure incorporating the floating gate structure and having a side surface. The side surface includes a concave region. A control gate structure (120) is formed adjacent to the intermediate insulating structure. The control gate structure conforms to the side surface and includes a projecting portion that extends over a portion of the floating gate structure. Independent claims are also included for: (a) method of forming a non-volatile split-gate memory cell; and (b) semiconductor memory cell comprising a split-gate cell structure. method of forming the non-volatile split-gate memory cell comprising: (i) forming a first insulating layer on a substrate (100); (ii) forming a first semiconductor layer on the first insulating layer; (iii) forming a second insulating layer on the first semiconductor layer; (iv) forming a third insulating layer on the second insulating layer; (v) patterning and etching the third insulating layer to form an opening of vertical sidewalls that exposes a portion of the second insulating layer; (vi) oxidizing a portion of the first semiconductor layer to form a semiconductor oxide layer; (vii) depositing a sidewall material layer; (viii) etching the sidewall material layer using an anisotropic etch to form spacers adjacent the sidewalls of the opening and to expose a portion of the semiconductor oxide layer; (ix) etching the exposed portion of the semiconductor oxide layer to expose a portion of the first semiconductor layer; (x) etching the exposed portion of the first semiconductor layer to expose a portion of the first insulating layer; (xi) implanting a dopant species through the exposed portion of the first insulating layer to form a source region in a portion of the substrate; (xii) depositing a fourth insulating layer to a thickness to fill the opening; (xiii) removing an upper portion of the fourth insulating layer to expose a surface of the third insulating layer and produce a planar surface; (xiv) removing the third insulating layer and the spacers to form an insulator structure having sidewalls that include a recessed area; (xv) removing the second insulating layer; (xvi) etching the first semiconductor layer using a remaining portion of the semiconductor oxide layer to expose the first insulating layer and form first conductor elements; (xvii) forming a fifth insulating layer on the first conductor elements; (xviii) depositing a second semiconductor layer for conforming to a surface of the insulator structure and filling the recessed area in the sidewalls; (ixx) etching the second semiconductor layer to form semiconductor spacers adjacent to the sidewalls of the insulator structure and expose a portion of the first insulating layer, in which each semiconductor spacer is a second conductor element that is paired with and partially overlays a corresponding first conductor element; (xx) implanting a dopant species through the exposed portion of the first insulating layer to form a drain region in the substrate; (xxi) depositing a sixth insulating layer to insulate the second conductor element; and (xxii) establishing separate electrical connections to the source region, the drain region and the second conductor element.