Patent GB-1231646-A (GB)
IPC: H03K3/30
Filed: 1968-05-23
Abstract: 1,231,646. F.M. demodulators; pulse generators. HONEYWELL Inc. 23 May, 1968 [26 May, 1967], No. 24582/68. Headings H3A and H3T. [Also in Division G4] A demodulator for F.M. input signals includes a pulse generator (Fig. 1) for generating at least one output pulse of a predetermined length, which is selectable by switch means 19, from at least two different lengths, in response to each cycle of the input signal and having means-FF1 for initiating the output pulse in response to an input trigger pulse, means 18 for supplying timing pulses to a pulse counter FF2-FF8 in response to initiation of an output pulse and means G10-G16, 19, G7 and FF1 terminating each output pulse when the counter has counted the particular number of timing pulses selected and an output circuit 22 to generate in operation an output signal varying in amplitude in dependence on the duration of the output pulses from the generator. A dtaa signal 103 to be recorded is applied to a tape 100 as a FM output of a voltage controlled oscillator 102. A sinusoidal signal is read from the tape and is shaped to a square wave in a limiter 105. The trigger pulse at 10 is applied via a gating circuit including NAND gate G1, differentiating networks 14, 16 and 15, 17, AND gates G2, G3 and a NOR gate G4 to the set input of a bi-stable flip-flop FF1 which may be an integrated JK circuit. With switch 13 in the X1 positon only the leading edge of the pulse from 10 produces a trigger pulse at the output of G4, whereas in the X2 position both the leading and trailing edges of the pulse from 10 each produce a trigger pulse so that the gating circuit acts as a frequency doubler. The trigger pulse at the set input changes the state of FF1 output Q to low. This triggers oscillator 18 to produce oscillations which are converted to a square wave and applied to the toggle input JK of bi-stable FF2 of a binary counter chain FF2- FF8. The timing pulses from oscillator 18 are then counted until the output from one of the counter stages enables the gate G10-G16 selected by the tape drive speed selector switch 19. The low output then at the output of inverting OR gate G7 is applied to the toggle input of FF1 which changes its state and ends the output pulse obtained via inverting gate G5. The counter is automatically reset. If the switch 13 is in the X2 position then the second trigger pulse at the output of G4 also causes the above cycle to again occur. The tape speed selector 19 is arranged to reduce the length of the output pulses with increasing tape speed. There may be a fixed delay between the start of the output pulse and the counting of timing pulses or between the start of counting and the start of the output pulses. The filter 22, which converts the output pulse duration from G5 to an output level signal indicative of the input signal frequency at 10, may be replaced by an integrator. Oscillator 18 (Fig. 2).-With a positive input Q1 and diode 54 are on to shunt diode 55 and resistor 56 and Q2 is off. When the input goes Low Q1 turns off and diodes 54 and 55 are conductive to bias Q2 on which starts to oscillate due to the inductive feedback circuit 61, 62.