Patent GB-966973-A (GB)
Title: Improvements in or relating to telecommunication systems
Inventor: CAMPENHOUT HENDRIK VAN
IPC: H04Q1/44
Filed: 1960-10-07
Abstract: 966,973. Phase measurement. DE STAAT DER NEDERLANDEN, TEN DEZE VERTEGENWOORDIGD DOOR DE DIRECTEUR-GENERAAL DER POSTERIJEN,TELEGRAFIE EN TELEFONIE. Oct. 7, 1960 [Nov. 4, 1959], No. 34377/60. Heading G1U. [Also in Division H4] Apparatus determining the service class for connection between subscribers of an automatic telephone exchange,wherein the connection is classified by a marking voltage having a predetermined phase derived from an n-phase system, and in which from the n-phase system a p-phase system is derived in which p is proportional to n and the voltages of the p-phase system are phase shifted over a given angle with respect to the voltages of the n-phase system; the voltages of the p-phase system are directed in pairs to an impulse shaping network producing a pattern of n impulses whose interpulse phase shift is determined by the phase angle between the voltages of the p-phase system, and an impulse derived at the zero point of the marking voltage is compared for coincidence with the pattern of n impulses to derive a further impulse which determines the service class of the connection. In an identification system for an automatic telecommunication exchange of the kind described in Specification 737,778, the multipled earth returns from contacts X1, X2 of the X relay are replaced by single connections to phase identification devices A, B (Fig. 1b) controlling the group marking resistance network. The lines connected to line finder OZ and selector EK are marked by voltages of an n-phase system of the kind set forth in Specification 701,447 wherein there is provided a source of reference voltages at 12 uniformly spaced phases #1 to #12 having 30 degrees mutual shift from which are derived by vectorial combination (Fig. 3a not shown) 12 intermediately spaced phase voltages #1-2 to #12-1 so that a range of marking voltages spaced 15 degrees apart in phase is provided. Fig. 7 shows an identification device (A or B in Fig. 1b) wherein pairs of adjacent derived voltages #1-2, #6-7; #2-3, #7-8 ...... #12-1, #5-6 of which the former is phase reversed are combined (Fig. 4) in each of 12 coincidence circuits C1 to C12 shown in Fig. 5a wherein the derived voltage pairs are applied to inputs A, B over half wave rectifiers to the base of transistor T1 so arranged that if A or B exceeds point C in potential the collector current will be zero, and output E will be of low potential but when A or B is in defect of C in potential, the potential of E will rise to give an output pulse symmetrical about the zero voltage point of the # phase voltages. A range of 12 reference pulses of progressively increasing phase shift are thus obtained by combination of the derived voltages in successive pairs (Fig. 6a) and are connected to the inputs K1 to K12 of corresponding coincidence memory circuits CG1 to CG12 (Fig. 8) whose other inputs J1 to J12 are energized from device CD (Fig. 5b) responsive to a marking voltage of undetermined phase applied to A whereby a pulse occurs at E when the potential at A is less than that of C during the negative half cycles (13 in Fig. 6a) which is differentiated and negative suppressed to produce a train of positive pulses coinciding with passage of the input voltage amplitude through zero (14 in Fig. 6a). In Fig. 8, the inputs J1, K1 are connected over diode circuits to the base of transistor T1 and a reset signal is diode connected to the base of transistor T2; the collectors being common earthed and the emitters being across diode connected to the opposite base circuits with relay A1 in the emitter circuit of T2. Initially T1 conducts and T2 blocks to pass current over AUP, diodes C2, C3, and R1, R2 and a positive pulse at K or J blocks C2 or C3 so that T1 remains conducting and current flows over C3, R2 or C2, R1. Simultaneous pulses at K1, J1 block C2, C3 and allow the potential at P and U to rise so that the latter exceeds A to cut off T1 and remove zero potential from point B. The base potential of T2 falls below that of A1 so T2 conducts to operate relay A1 and S and P fall to zero, so that the circuit is unaffected by signals at J1, K1 until B is zeroised by a reset pulse which opens transistor T1 and blocks T2. Relays A1 to A12 are provided responsive to CG1 to CG12 which have contacts a1<SP>1>, a1<SP>2>; a2<SP>1>, a2<SP>2>; to a12<SP>1>, a<2>12 applicable e.g. to mark the service class of a telecommunication connection. In the range of coincidence circuits if the unknown marking voltage has phase #1, the inputs of CG1 will be positive at the same time to energize relay A1 and close contacts a<1>1, a1<SP>2>; if it has phase #2 the inputs CG2 will be positive at the same time to energize relay A2 to close contacts a<1>2, a<2>2 and so on. For amplitude response the input signal # is also applied to a threshold amplifier having elements 1, 2, 3 (Fig. 10) responsive to progressively increasing levels. Graduated levels of input voltage are derived from voltage dividers R1 R2, R3 R4, and R5 R6 and applied over half wave rectifiers to the bases of transistors T1, T2, T3 whose collectors are earthed and whose emitters develop pulses on the input voltage exceeding respective predetermined thresholds. On application of marking A.C. voltages (Fig. 9 not shown) exceeding the first threshold blocks T1 on positive half cycles to produce negative pulses blocking the reset device R1 to release the identification device, and on exceeding the second threshold blocking T2 on positive half cycles to change over trigger T2 (Fig. 7), operate relay B, and change over contact b. Since the potential divider associated with transistor T3 is returned to positive, a negative half cycle exceeding the third threshold renders T3 conductive to develop a positive pulse which changes over trigger T2 to arrest call metering by operating relay C to close contact c. The relays may be applied e.g. to mark another service class. If in Fig. 7 more than one coincidence memory delivers an output voltage, a logical circuit LR receiving such voltages on inputs 1 to 12 produces a voltage to unblock the reset device and delivers pulses L1 to L12 to restore the memory circuits CG1 to CG12 after which the logical circuit restores and the reset device blocks to prepare a new test. To avoid double operation of relays A1 to A12 by coincidence between the unknown input voltage pulse and the trailing and leading edges of successive reference pulses, the latter may be critically spaced apart (Figs. 2b, 3b) by a small angular interval (Fig. 6b not shown).