baber/WOPTO huggingface dataset:
Patent JP-2010044954-A (JP)
Title: Battery pack
Inventor: SENNAMI HIROMITSU
IPC: H01M50/574
Filed: 2008-08-12
Abstract: <P>PROBLEM TO BE SOLVED: To provide a battery pack in which ESD (electrostatic discharge) resistance can be improved without largely changing the design of the battery pack and a battery housing part of an electronic apparatus body.  <P>SOLUTION: The battery pack is provided with an outer package material and a battery element housed in the outer package material. The outer package material is a laminated material having a conductive layer, and a positive electrode terminal or a negative electrode terminal of the battery element is electrically connected to the conductive layer. The conductive layer of the outer package material is set at the same potential as the positive electrode or the negative electrode of the battery element.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2010045230-A (JP)
Title: Light-emitting element chip, exposure device and image forming apparatus
Inventor: KONDO YOSHINAO
IPC: H01L21/822
Filed: 2008-08-13
Abstract: <P>PROBLEM TO BE SOLVED: To provide a light-emitting element chip that reduces complexity of routing of a signal line by using the structure of a light-emitting element array.  <P>SOLUTION: The light-emitting element chip 51a is made of a GaAs-based semiconductor, and includes a pnpn structure formed on a substrate 200. The light-emitting element chip includes a light-emitting thyristor 401 of a light-emitting portion 120, a transfer thyristor 402 of a setting portion 130, and a logical operation element 403 of a control portion 140, wherein the element chip is formed by laminating a p-type first semiconductor layer 201 and an n-type second semiconductor layer 202, a p-type third semiconductor layer 203, and an n-type fourth semiconductor layer 204 on the substrate 200, and then etching predetermined places.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2010044974-A (JP)
Title: Electromagnetic relay
Inventor: YOKOYAMA KENICHI
IPC: H01H50/14
Filed: 2008-08-15
Abstract: <P>PROBLEM TO BE SOLVED: To reduce thermal stress applied on external terminals for surface mounting in an electromagnetic relay, and improve reliability of mounting and reliability of the device on which the electromagnetic relay is mounted.  <P>SOLUTION: The electromagnetic relay 1 has a plurality of external terminals which are formed protruded from a case 5 to constitute the body. As the external terminals, a plurality of surface mounting terminals 11-18 are provided whose top end portions are formed so as to be located on a common plane. Furthermore, through-hole terminals 21-22 are provided whose top end portions extend protruded from the case 5 further than the common plane on which the top end portions of the surface mounting terminals 11-18 are located.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2010050134-A (JP)
Title: Nonvolatile semiconductor memory cell, and nonvolatile semiconductor memory device
Inventor: ASANO MASAMICHI
IPC: H01L29/788
Filed: 2008-08-19
Abstract: <P>PROBLEM TO BE SOLVED: To actualize a nonvolatile semiconductor memory element having a cell structure of one layer of polysilicon which is manufactured using a standard CMOS process, and to provide a nonvolatile semiconductor memory device which is reduced in mounting area by efficient arrangement and improved in reliability of storage maintenance.  <P>SOLUTION: The nonvolatile semiconductor memory cell 4 has a select transistor Tr41, and three memory elements Tr42, Tr43, Tr44 arranged in order at a transistor formation portion 40 in a vertical direction (in a longitudinal direction). In a memory cell array having the nonvolatile semiconductor memory cells 4 arranged in a matrix form, an n-type diffusion layer 401 forming a drain of the select transistor Tr41, a contact 418 and metal wiring 414 are shared and arranged symmetrically in the vertical direction, and further an n-type diffusion layer 405 forming a source of the memory element Tr41, a contact 422 and metal wiring 417 are shared and arranged symmetrically in the vertical direction.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2010050161-A (JP)
Title: Semiconductor device
Inventor: INOMATA HISAO
IPC: H01L29/78
Filed: 2008-08-19
Abstract: <P>PROBLEM TO BE SOLVED: To efficiently improve a breakdown voltage while securing a path for a drain current.  <P>SOLUTION: A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 100 includes an N-type epitaxial layer (semiconductor layer), a P-type (second conductivity type) base region formed on the surface of the N-type epitaxial layer, a plurality of first P-type column regions 130 formed in a matrix form in plain view in the epitaxial layer, a trench gate 112 formed on a principal surface of the epitaxial layer, enclosing four sides of each of the first column regions 130 in plain view, and provided penetrating the base region to reach the epitaxial layer, and a plurality of second P-type column regions 132 formed selectively below the trench gate 112 in four corners where the trench gate 112 encloses each first column region 130.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2010046154-A (JP)
Title: Slot machine
Inventor: ITO TOMOHIKO
IPC: A63F5/04
Filed: 2008-08-19
Abstract: <P>PROBLEM TO BE SOLVED: To indicate the winning expectation for bonus winning combinations by using a conflict announcement.  <P>SOLUTION: For a winning combination lottery table 62, the winning of bonus winning combinations (BB and RB), and the duplicated winning of a small winning combination A and a small winning combination B are provided. A reel controlling means 64 performs a control in such a manner that the small winning combination A may be won when the duplicated winning of the small winning combination A and makes the small winning combination B occur during a non-internal winning state, and performs a control in such a manner that when the duplicated winning of the small winning combination A the small winning combination B occurs during an internal winning state, the small winning combination B may be won. The slot machine includes a won small winning combination notifying means 69a which notifies a game player of the winning of the small winning combination A when the duplicated winning of the small winning combination A and the small winning combination B has occurred in the lottery of winning combinations.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2009027180-A (JP)
Title: Printed circuit board and method of mounting component on the same
Inventor: KAKU JINKYU
IPC: H05K7/06
Filed: 2008-08-20
Abstract: <P>PROBLEM TO BE SOLVED: To provide a printed circuit board capable of suppressing EMI radiation.  <P>SOLUTION: The printed circuit board includes: an integrated circuit 300 which is disposed on a surface of one of a top layer and a bottom layer and is provided with a clock pin 300a for outputting a clock signal and a first ground pin 300b; and an RC filter 310 including a resistor 320 and one capacitor 330 in order to eliminate high frequency components of the clock signal. One end of the capacitor 330 is connected to the resistor 320 by wiring, and a second ground pin 330a at the other end of the capacitor 330 is disposed to face the first ground pin 300b, and the capacitor 330 is disposed between wiring and the first ground pin 300b, and no wiring is formed on a ground fill in a current return path directly connecting the second ground pin 330a to the first ground pin 300b, and the capacitor 330 is disposed on the same layer as the integrated circuit 300, out of the top layer and the bottom layer.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2010050230-A (JP)
Title: Method of manufacturing silicon wafer, and silicon wafer
Inventor: OTSUKI TAKESHI
IPC: H01L21/02
Filed: 2008-08-20
Abstract: <P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a silicon wafer that maintains a step structure and is flat at an atom level, and to provide the silicon wafer.  <P>SOLUTION: The method of manufacturing the silicon wafer having the step structure whose flat surface (lattice) is a crystal surface includes at least a step of forming the step structure by performing a heat treatment for surface planarization on a prepared silicon wafer, and a step of forming a thermal oxide film of 1 to 2 nm on a surface of the silicon wafer having the step structure formed through the heat treatment for planarization, wherein the method is characterized in that the step of forming the thermal oxide film is performed successively to the step of the heat treatment for planarization.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2010049966-A (JP)
Title: Carrier cutting device
Inventor: SAKAGAMI SHIGERU
IPC: H01R43/048
Filed: 2008-08-22
Abstract: <P>PROBLEM TO BE SOLVED: To provide a carrier cutting device reducing crimping failures by properly cutting carriers without giving any trouble to crimping work in a terminal crimping device.  <P>SOLUTION: The carrier cutting device includes a pair of cutting blades 21 and 22 to cut a carrier C ejected from an anvil 6 of the terminal crimping device 1 and arranged in a side of the terminal crimping device 1. The pair of cutting blades 21 and 22 are constituted so as to cut the carrier C by being mutually arranged closely, and a cutting position of the carrier C is arranged approximately on an extension of the carrier C arranged on the anvil 6.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2009050704-A (JP)
Title: Surgical operating apparatus
Inventor: YANAI CHIE
IPC: A61B18/12
Filed: 2008-08-22
Abstract: <P>PROBLEM TO BE SOLVED: To provide a surgical operating apparatus, wherein a plurality of switches having different functions can be easily distinguished from each other, the switches are easily operated with the index finger of a user gripping a handle, fatigue is lessened, and the position of a treatment portion at the distal end of a treatment instrument can be prevented from moving during the operation of the switch.  <P>SOLUTION: The surgical operating apparatus comprises an insertion portion 5 which is inserted into a body; the treatment portion 1A which is disposed at the distal end of the insertion portion 5 and has a plurality of selectable treatment functions; an operation portion 4 disposed at the proximal end of the insertion portion 5; a plurality of switches 54 and 55 which are provided in the operation portion 4 and which select the treatment functions; and a bulging portion 501 which is disposed between the switches 54 and 55 and which divides the switches 54 and 55 and which doubles as a finger receiving portion.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2009226914-A (JP)
Title: Gas barrier sheet, and manufacturing method of the gas barrier sheet
Inventor: SAKAKURA OSAMU
IPC: B32B9/00
Filed: 2008-08-25
Abstract: <P>PROBLEM TO BE SOLVED: To provide a gas barrier sheet, which is superior in transparency, has high heat resistance, hardly develops curling, is superior in hard coating properties and in gas barrier properties, its manufacturing method, especially a gas barrier sheet, in which the development of curling is suppressed even after a heat cycling test, which is performed as the endurance test of an organic EL display or the like, and also its gas barrier performance is maintained, and its manufacturing method.  <P>SOLUTION: The gas barrier sheet 1 has a base material 2, an anchor film 9 provided on one surface 11 side of the base material 2, and a gas barrier film 3 provided on the anchor film 9. The anchor film 9 includes a polysiloxane polymer comprising a siloxane compound and a compound (A), the molecule of which has a functional group reactable with a hydroxyl group contained in the siloxane compound at their polymerization. The gas barrier film 3 is a SiNxOy film, wherein x=0.5-1.5 and y=0.15-1.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2010056154-A (JP)
Title: Semiconductor device
Inventor: SUGI YOSHIO
IPC: H01L29/78
Filed: 2008-08-26
Abstract: <P>PROBLEM TO BE SOLVED: To provide a semiconductor device which uses a semiconductor substrate of parallel pn structure, having a high breakdown strength and lower loss, while suppressing an increase in the number of manufacturing processes and the manufacturing cost.  <P>SOLUTION: The semiconductor device includes a parallel pn layer where an n-type drift region 2 and a p-type partition region 3 are alternately arranged. A non-active region is divided into a second non-active region 17a of unbalanced charge and a first non-active region 17b of balanced charge. In the second non-active region 17a, the width of the n-type drift region 2 is made narrower than that of the p-type partition region 3, and the overall impurity concentration of the p-type partition region 3 is made higher than that of the n-type drift region 2. Since the breakdown strength of a semiconductor substrate in the non-active region 17 increases, the breakdown strength of the semiconductor substrate in the non-active region 17 becomes higher than that of the semiconductor substrate in an active region 18, resulting in an improved overall breakdown strength of the semiconductor substrate.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2010055228-A (JP)
Title: Card processor and processing method
Inventor: IMAIZUMI ATSUHIRO
IPC: G06F21/32
Filed: 2008-08-27
Abstract: <P>PROBLEM TO BE SOLVED: To achieve update without deterioration of accuracy in authentication in update of an IC card which has a biometrics authentication function by an automatic teller machine.  <P>SOLUTION: A card processor includes a storage and a controller. The storage stores biological information read by a biological information acquisition section, when it is confirmed that a user is an owner of a card, as a result of comparison of the biological information read from the card by a card handling section with the biological information read from the user by a biological information acquisition section. The controller determines whether storing of biological information to the storage is performed for the specified number of times, and when performed, generates biological information to be stored in a newly issued card by using a plurality of pieces of biological information stored in the storage, and when not performed, directs acquisition of the biological information to the user and acquires the biological information again.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2008291645-A (JP)
Title: Humidity conditioning building material
Inventor: YAMAGUCHI FUJITO
IPC: C04B40/02
Filed: 2008-08-28
Abstract: <P>PROBLEM TO BE SOLVED: To provide a humidity conditioning building material having low specific gravity and high strength by effectively using an autoclave curing lightweight cellular concrete (ALC) waste material.  <P>SOLUTION: This humidity conditioning building material is provided by curing a mold by pressurizing and molding a dispersed-mixed inorganic powder material, by mixing and dispersing an inorganic hydraulic setting binding material, and siliceous powder and a reinforced fiber material when necessary, in finely crushed ALC fine powder, and by finely crushing the ALC waste material in a dry system. This invention can provide the humidity conditioning building material extremely superior in the appearance of a white color being extremely light in weight in specific gravity around 1.2 or not more than that and having high bending breaking strength to its low specific gravity. This humidity conditioning building material has excellent humidity conditioning performance in a medium and high-humidity area, and can impart a comfortable and healthy dwelling environment for a resident.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2009087929-A (JP)
Title: Battery separator and nonaqueous lithium-ion secondary battery using the same
Inventor: TAKE HIROYOSHI
IPC: H01M50/489
Filed: 2008-08-29
Abstract: <P>PROBLEM TO BE SOLVED: To provide a separator that provides a nonaqueous lithium secondary battery in which deposit of metal ion to negative electrode surface is reduced, and capacity deterioration is less even charge and discharge are repeated under high temperatures, and moreover, a nonaqueous lithium-ion secondary battery composed by using such a kind of separator, and a manufacturing method of the lithium-ion secondary battery composed by using such a kind of separator.  <P>SOLUTION: This is the battery separator composed by a cross-linked polymer layer which has iminodiacetate group in a side chain of polymer molecule chain and is carried by a porous resin film. The cross-linked polymer layer is preferably a substantially nonporous ionic conductive layer, and moreover, the cross-linked polymer has oxetanyl group having cationic polymerization property in the molecule.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2010059065-A (JP)
Title: Slimming cosmetic
Inventor: YAMASHITA HIROMICHI
IPC: A61K8/60
Filed: 2008-09-02
Abstract: <P>PROBLEM TO BE SOLVED: To solve a problem wherein the local parts of the body such as the belly and the legs are parts liable to have body fat, in the case of many persons, especially women, obesity is not favorable in terms of appearance, namely, beautification, obesity increases by factors such as change in eating habits in a modern society, chronic lack of exercise, increase in stress, etc., use of cosmetic such as gel for massage, cream, etc., mixed with a fat decomposing agent and a blood circulation promoter besides various exercises and dietary restriction is known for slimming, however, conventionally used cosmetics have strong irritation to the skin and there is almost no cosmetic having sufficient action.  <P>SOLUTION: The cosmetic having slimming action, cellulite improving action, improving action on swelling, etc., is prepared by mixing a skin care preparation with an extract of Vernonia cinerea (Linn.) Less. The cosmetic having a higher slimming action, cellulite improving action, improving action on swelling is prepared by mixing the extract of Vernonia cinerea (Linn.) Less. with fucoidan.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2010061776-A (JP)
Title: Semiconductor integrated circuit and semiconductor storage apparatus
Inventor: KOTABE AKIRA
IPC: H01L21/8242
Filed: 2008-09-08
Abstract: <P>PROBLEM TO BE SOLVED: To reduce the power consumption of an internal bus of a chip or an external bus for connecting the chips, and to improve a data transfer speed.  <P>SOLUTION: A semiconductor integrated circuit includes: a transmission circuit TX which encodes a plurality of buses DB[0] to DB[n-1] each capable of employing a logical level 'H' or 'L' or a middle level 'M' between them and data D[0] to D[m-1], and based thereon, drives each of the plurality of buses to one of the logical levels 'H', 'L', 'M'; and a bus equalizing circuit BEQ for short-circuiting the plurality of buses each other. When encoding the data, the transmission circuit TX uses such a combination that the number (k) of buses driven to the logical level 'H' and the number (k) of buses driven to the logical level 'L' become the same. The bus equalizing circuit BEQ precharges each bus to the logical level 'M' by performing a short circuit operation after the data are transmitted.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2010068049-A (JP)
Title: Image device
Inventor: YAMAUCHI MAKIKO
IPC: H04N5/374
Filed: 2008-09-08
Abstract: <P>PROBLEM TO BE SOLVED: To provide an image device capable of improving a correction precision rate for noise resulting from a drive pulse for reading a pixel signal from a pixel array, while shortening a period when the pixel signal is read and transferred to an output line.  <P>SOLUTION: The two-dimensional image device includes the output line, and a plurality of first and second hold means. The device operates in parallel an operation for reading out a pixel signal from a second column to the first hold means and an operation for transferring a pixel signal, which is located at each column in a first row and read to the plurality of second hold means, to the output line one by one. While a read-out means transfers the pixel signal at each column in the first row to the output line, the device supplies a drive pulse, for reading a pixel signal from a second row, to a pixel array or the read-out means. The device corrects a pixel signal at a first column in the first row transferred by the read-out means with a timing by which the drive pulse transits during a transfer period, according to a pixel signal at a first column in the second row or the level of the pixel signal of at the first column in the second row and a pixel signal surrounding it.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2009004807-A (JP)
Title: Method of manufacturing semiconductor device and apparatus for manufacturing the semiconductor device
Inventor: UOZUMI NOBUHIRO
IPC: C23F1/30
Filed: 2008-09-12
Abstract: <P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device and an apparatus for manufacturing the semiconductor device where the surface of a copper film is etched precisely, in a short time with few steps, while the surface roughness of the copper film is not progressed in the etching process of the surface of the copper film that includes oxidation of the copper film and removing the oxide thereof, with an acid or alkali.  <P>SOLUTION: The method includes a step of filling a wiring groove or a contact hole, by stacking a wiring metal in the wiring groove or the contact hole formed on the insulation film on a semiconductor substrate, a step for exposing the insulating film by polishing the wiring metal, a step of cleaning the semiconductor substrate, and a step for recess etching the surface of the wiring metal embedded in the wiring groove or the contact hole. The main component of a chemical used in at least two steps, selected from among the polishing step, the cleaning step, and the recess etching step are the same.  <P>COPYRIGHT: (C)2009,JPO&INPIT
Patent JP-2010072925-A (JP)
Title: Cash dispensing management method and cash dispensing machine
Inventor: MIMURA NORIMASA
IPC: G07D9/00
Filed: 2008-09-18
Abstract: <P>PROBLEM TO BE SOLVED: To provide a cash dispensing management method and cash dispensing machine which prevent over-storing in money collecting box at closing time.  <P>SOLUTION: The cash dispensing machine performs an accumulation processing of petty cash payments each time a petty cash payment is done while cash amount in the collecting box remains zero yen, and the machine subtracts deposit cash amount from accumulated amount of petty cash payments when a cash deposit is done while petty cash payments are accumulated. Only if deposit cash amount exceeds the accumulated amount of petty cash payments, the machine allows cash collected from a plurality of registers to be stored into the collecting box.  <P>COPYRIGHT: (C)2010,JPO&INPIT
Patent JP-2010074947-A (JP)
Title: Driving force controller
Inventor: HOSOKAWA AKIHIRO
IPC: B60L9/18
Filed: 2008-09-18
Abstract: <P>PROBLEM TO BE SOLVED: To provide a driving force controller, capable of transmitting a vibration torque to tires and reducing the tire slip ratio, without fail, when preventing the slippage of tires.  <P>SOLUTION: The driving force controller is capable of adjusting the friction coefficient between the tires and a road surface by transmitting the vibration torque from a driving force source to the tires. This controller includes a first decision means (Step S2), which decides whether control is being performed, to adjust the friction coefficient; a second decision means (Step S3) which when it is determined that control adjusting the friction coefficient is being performed, decides whether the tire slip ratio reaches a predetermined value or higher; and a correction means (Step S4, S5) which when it is determined that the tire slippage ratio reaches the predetermined value or higher, makes correction for reducing the standard torque to reduce the tire slippage ratio and changes the vibration torque, which changes based on the corrected standard torque, to be the corrected standard torque or lower.  <P>COPYRIGHT: (C)2010,JPO&INPIT