Patent GB-1306669-A (GB)
Title: Instruction execution systems
IPC: G06F9/38
Filed: 1971-09-20
Abstract: 1306669 Instruction execution systems INTERNATIONAL BUSINESS MACHINES CORP 20 Sept 1971 [22 Dec 1970] 43662/71 Heading G4A General.-An execution register 40 stores an instruction for controlling an arithmetic unit 42, Fig. 2, one of a plurality of data stores (working register stack 44) is specified for use in connection with the execution of an instruction, storage (in block 32) responds to an instruction to store an indication of the specified data store, and transform logic 32 inserts the identification of the data store held in storage into a subsequent instruction. The working registers in stack 44 consist of high and low order sections each of which is available for single operands and both of which are available for double, floating point (FP) operands. When an instruction sequence initially references a general FP register, the identity of a working register is stored in logic 32 and each subsequent, instruction in that sequence references logic 32 and uses the selected register. Before execution, instructions normally pass through a stack 34 from which they are extracted, not necessarily in sequence, by interlock logic 36. The instructions include an OP code, an RI field specifying a program-named register (usually the instruction sink), and an R2 field specifying another program-named register (source) in the case of a register to register (RR) instruction or the location of a source operand in the case of an RX instruction. The OP code is partially decoded before reaching stack 34 to specify the arithmetic facility (ADD, MUL, DIV) required by the instruction. In the execution register the transformed field RT1 normally resets a data valid tag in logic 52 corresponding to the sink register because data in that register will not be valid again until the instruction has been executed. The transformed field RT2 causes logic 54 to release the source register for use by the instruction unit in connection with the generation of subsequent instructions. By renaming registers selected from stack 44 and assigning them to specific instructions, independent sequences of instructions may be executed simultaneously and out of sequence. Transform logic, Fig. 4, selects any one of 32 registers in stack 44 as a source register for use in RX instructions or any one of the 16 double registers in stack 44 as a FP register for use by subsequent instructions. In an RX load instruction, the R1 field which identifies a particular designated FP register selects a set of gates 128 to pass the R2 field identifying a working register (selected by the instruction unit from free list logic 54) into the selected register in list 106. The earlier contents of that list register are transferred to the RT1, RT2 fields so that a working register is renamed as a FP register and the previous rename of that register is inserted in the instruction for use by interlock logic 36 while the instruction is passing through stack 34, whereby the register names cannot be released by logic 54 until the instruction reache execution register 40. In the other instructions RR, RX, the R1 and R2 fields select the rename to be passed to RT1, RT2, and the OP code and control bits are also transferred to the transformed instruction. Instruction register stack 34, Fig. 5 (not shown), consists of five registers the contents of any one of which may be gated out by interlock logic 36 (see below) and the contents of lower registers rippling up the stack to vacate the lowest register for a new instruction. Interlock logic, Figs. 6, 7 (not shown), compares the R1, R2 fields of instructions in stack 34 and prevents an instruction going to execution when it references the same working register as an earlier instruction in the stack. A data valid interlock is also performed to prevent execution of an instruction if the data in the register specified by R1, R2 is not valid, e.g. it may be the result of a previous instruction not yet executed. A MUL/DIV instruction is not allowed to go to execution before two cycles prior to completion of an operation by the MUL or DIV facility of the arithmetic unit 42, no two instructions are allowed to compete for the AU output bus at the same time, and finally, logic 36 selects the oldest instruction in stack 34 which is not otherwise interlocked. Extended precision instruction causes all instructions in stack 34 to be executed before it is transferred to the execution register.