Patent GB-1022999-A (GB)
Title: A modular data processing system
Inventor: SVOBODA ANTONIN
IPC: G06F13/38
Filed: 1964-06-03
Abstract: 1,022,999. Digital computers. VYZKUMNY USTAV MATEMATICKYCH STROJU. June 3, 1964; No. 22966/64. Heading G4A. A data processing system for the parallel processing of a plurality of independent programmes comprises a central control and processing unit, a main working memory, an auxiliary memory and various peripheral units, the auxiliary memory and peripheral units being connected to the central unit by a common output channel and a common input channel, the output channel including means for transmitting a signal indicating to which of the programmes an instruction being executed belongs. The peripheral units may comprise magnetic tape, punched tape, punched card, printers, or analogue-digital converters, all serving as inputoutput equipment for the central processor. Means are provided for assigning priorities to the various programmes depending on the particular peripheral unit with which the programme requires communication and on the current ability of that unit to honour this request. General arrangement.-The system described comprises a central processing unit 1, Fig. 1a, a main working memory unit 2, an auxiliary magnetic drum system memory 3, Fig. 1b and peripheral units 4/1 to 4/3. The central processing unit 1 includes a system control unit 11, timing control unit 12, arithmetic registers 14, instruction registers 16, auxiliary registers 15 (including index registers for modifying instructions and a programme address counter), and a memory access register 13. The main memory unit 2 includes the memory 21 and associated address register 23. An output channel 5 and input channel 6 connect the central unit 1 with the various peripheral units. The output channel 5 includes a bus 54 for transmitting a signal (#-signal) indicating that communication with a peripheral unit is required, the channel 6 including buses 63, 64 for indicating that communication is not or is possible (#-block or #-return signals). Instruction format.-The address part of an instruction employed in the central processor may indicate (a) supplementary information for the operation code (e.g. number of shifts required in an operation), (b) an operand, (c) the address in memory 2 or auxiliary memory 3 of an operand or result storage location, or (d) the operation to be carried out by a peripheral unit 4/1 to 4/3. Parallel processing.-The system described can process simultaneously five programmes I-V, each programme having assigned to it a particular part of the main memory 2 and auxiliary memory 3, together with certain of the peripheral units 4/1 &c., the programmes being performed in a sequence determined by their basic priority and by the state of the peripheral units assigned to them. Before the execution of an (a) or (b)-type instruction the control unit 11 tests to ensure that the current programme has highest priority or if not a transfer is made to another programme. In the case of a (c)-type instruction, a check is made in the address register 23 to ensure that the address required lies within the part of the memory 21 allocated to the corresponding programme. If this is not the case, the programme is stopped and an error indication given. The address register 23 is also capable of addressing different blocks of the memory 21 although the same address is supplied by the instruction being executed, thus providing a form of " relative " addressing. In a (d) type of instruction an #-signal is transmitted over line 54, the address part is transmitted over a bus 52 and signals identifying the current programme are transmitted over a bus 53, the buses 52, 53, 54 forming part of output channel 5. The address part of the instruction determines both the particular peripheral unit 4/1 &c. and the type of operation it is to perform. If the #-retum signal on bus 64 is provided, data transfer between the peripheral unit and the main memory 2 takes place over a bus 55 or 65. A signal on a bus 66 may cause a jump in the execution sequence of the programme being executed. If an #-block signal is transmitted over bus 63, a programme block signal is also transmitted over a bus 61 to block the current programme. The control unit 11 responds to the #-block signal to transfer the information associated with the current programme in the arithmetic registers 14, auxiliary registers 15 and instruction register 16 to associated " backing " storage registers 141, 151, 161. Priority arrangements.-When a programme has been cleared as described above, the control unit 11 causes transfer to the programme having highest priority or, if there is more than one such, to the next such in cyclic sequence after the programme which has just been cleared. Each programme is initially allocated one of two basic priorities, degree 1 (lower) or degree 2 (higher), priority degrees 3-6 corresponding to an interrupt request by various types of peripheral units, and priority degree 7 (the highest priority) corresponding to an intervention requested by a manual control block 18, Fig. la. The control unit 11 continuously monitors the instantaneous priorities of all the programmes and replaces the current programme whenever another programme attains a higher priority as well as when the current programme becomes blocked. Each programme may be in any one of three states: "starting," "running," or "blocked"; the " starting " state being initiated by operating the manual control block 18, Fig. 1a, to insert the initial instruction in the backing instruction register 161 associated with the programme. Peripheral unit.-Fig. 2 shows a typical peripheral unit connected between output channel 5 and input channel 6 and comprising a " discriminating " block 41, a control unit 42 and a memory unit 43. Before starting, the number of the programme to which the peripheral unit is assigned, is set up in a programme number selector 411, a number identifying the unit itself being set up in a selector 412. If the central processor requires communication with the peripheral units, this is detected by a " blocking gate " 414 which, depending on the state of the peripheral unit causes either an "#-block" signal or an "#-return" signal to be transmitted to the central processor over line 63 or 64. If the peripheral unit is free, the particular operation effected therein (e.g. data transfer, tape wind, print) is controlled by the address part of the central processor instruction transmitted over the address bus 53. If a programme intervention is necessary, a signal is transmitted back to the central processor via programme priority bus 62 to raise the priority of the programme to which the peripheral unit is assigned.  Auxiliary memory (Fig. 3, not shown).-This unit operates in a generally similar way to the peripheral units, but comprises a magnetic drum store. Initially, each of the five programmes is allocated a certain section of the auxiliary memory by means of manual switches. During operation of the central processor, the auxiliary memory is controlled by instructions which may be of one of two types called " preparatory " instructions and " executive " instructions, a preparatory instruction being effective to assign the auxiliary memory to one of the five programmes, until it is released by an executive instruction.  Central processor.-The central processor 1, Fig. 1a, comprises a series-parallel decimal computer with decimal digits represented in a 2-out-of-5 code, the word length being thirteen decimal digits, a machine cycle consisting of 13 bit times. The arithmetic registers 14 comprise two one-word registers so that doublelength operation may be employed. The auxiliary registers 15 comprise nine 1-word registers, one being the programme address counter and the others being index registers. Each register is provided with a corresponding " backing register" 141, 151 having 5-word capacity, one for each of the five programmes. The registers comprise 1-word delay lines and the backing registers 5-word delay lines. The instruction register 16 (Fig. 5, not shown) comprises a 1-word static shift register and a 5-word backing delay register. Each individual register in fact consists of five such registers operating in parallel to provide for the 2-out-of-5 code operation. Priority circuit.-A priority circuit, Fig. 16, determines the next programme to be processed after a programme transfer. A " 1 " signal on an appropriate conductor in a 5-way bus 1125 indicates that the corresponding programme has the higher of the two possible initial priority degrees 1, 2. Priorities of degrees 3-6 are indicated by signals on appropriate conductors in buses 625-628 connected to the programme priority bus 62 and manually controlled priority degree 7 is indicated on bus 1122. A signal on a lead 1136 indicates that an intervention is required, the number of the current programme being indicated on a bus 53, the numbers of those programmes which are started and also not blocked being signalled on a bus 1120, a signal on timing bus 1123 which consists of five conductors pulsed in turn indicating which programme can be initiated in the next cycle (corresponding to the location of words in the 5-word delay lines of the various computer registers). In the absence of a " 1 " signal on a control line 1148, the circuit 11081 determines during each cycle the highest priority signalled on buses 1125, 625-628, 1122 and compares this with the priority of the current programme, a signal being emitted on a lead 1153 if the two priorities are equal and a signal on a lead 1152 if they differ. If there is a " 1 " signal on line 1148, the same input priority signals are compared with the priority of the programme which is accessible during the next cycle, as indicated by bus 1123, a signal being emitted on a lead 1153, 1152 according as the priorities are equal or not.