Patent GB-1414346-A (GB)
Title: Circuit arrangement employing insulated gate field effect transistors
IPC: G11C17/12
Filed: 1973-05-15
Abstract: 1414346 FET logic and memory circuits TOKYO SHIBAURA ELECTRIC CO Ltd 15 May 1973 [16 May 1972 29 May 1972 (2)] 23124/73 Heading H3T [Also in Division G4] In a logic circuit or read only memory device having a first insulated gate field effect transistor 11 of one channel type, with first and second electrodes defining a conduction path, and at least one second insulated gate field effect transistor 12, 13 of the opposite channel type, means connects the second electrode of the first transistors 11 and the second electrode of the second transistor 12, 13 an output S is derived from the second electrode of the first transistor 11 and means supplies the gate of the first transistor 11 and the first electrode of at least one second transistor 12, 13 with a first and second clock pulse signal CP and CP which have a complementary relationship with each other and means supplies a data signal A-D to the gate electrode of the second transistor. The logic circuits 1-3 may operate as NAND or NOR circuits and as a NOT circuit if the gate 14 is formed by a single transistor. As shown in Fig. 2 P channel IGFET is 12 and 13 and N channel IGFETs 11 when the clock pulses CP1, CP1, CP2, CP2, are applied to the load transistors 11-1, 11-2, 11-3 the output load capacitances C1, C2, C3 are charged to -E. When data signals A-D have a voltage level -E and after the load transistors 11-1, 11-2 have become inoperative transistors 12-1, 12-2, 13-1 and 13-2 become conducting to discharge C1 and C2. The clock pulses CP2, CP2 are arranged to continue after clock pulses CP, CP so that the output load capacitance C3 is maintained charged to -E. This is to avoid discharge of this capacitance C3 which would otherwise have occurred if the same clock pulses had been used for all the logic circuits 1-3 since time delay in discharge of C1 and C2 cause the transistors 12-3, 13-3 to be kept operating for some time and cause the capacitance C3 to continue to be discharged to 0 presenting an erroneous output operation. Where a plurality of cascade connected logic circuits are supplied with clock pulse signals whose width progressively increases towards the terminal unit no erroneous operation will occur even though a delay occurs on generation of an output signal from any preceding logic circuits 1, 2. In a modification Fig. 4 the same clock pulse sources CP, CP may be used and erroneous operation is prevented by having inverter stages 20, 23 and an output logic circuit 3 including series connected transistors 12-3, 13-3. In a further modification of this (Fig. 6, not shown) omitting the inverter stages the outputs S1 and S2 are connected to the gates of series connected N channel FET 12-3, 13-3 and a P channel FET 11-3 is used. The logic circuits may be in integrated circuit form. The above logic arrangements may be used in read only memory ROM devices (Figs. 8, 9, and 10, not shown) as used in a digit decoder in a desk top electronic calculator. A ROM device (ROM 1) converts or decodes binary coded decimal signals (AA-D, D) into decimal signals (0 to 9). On receipt of the output signals from the ROM device (ROM 1) a ROM device (ROM 2) generates seven output signals (SA-SG) for selection of the seven electrode segments of a single digit-indicating tube. The ROM device (ROM 2) is not required where a digit-indicating tube is used which is provided with ten digit electrodes bearing the shapes of digits 0 to 9.