baber/WOPTO huggingface dataset:
Patent JP-H0962616-A (JP)
Title: Semiconductor circuit and its device
Inventor: FUKUSHI ISAO
IPC: H01L27/04
Filed: 1995-08-23
Abstract: PROBLEM TO BE SOLVED: To prevent signals from colliding without decreasing the operation speed by supplying a control signal which becomes valid to a bus driver when none of block select signals is selected and its block select signal is selected. SOLUTION: Bus drivers 4a00 -4a15 output internal data to an internal bus 8 when the control signal 2a2 of a function block 1a is valid and inhibit the output of the internal data when the control signal a2 is invalid. Respective block select signals 2b0 -2x0 for other function blocks 1b-1x and its own block select signal 2a0 are inputted from a select signal bus 2 and when none of the block select signals 2b0 -2x0 for other function blocks 1b-1x is selected and its own block select signal 2a0 is selected, the control signal 2a2 which becomes valid is supplied to the bus drivers 4a00 -4a15 . Therefore, signals can be prevented from colliding without lowering the operation speed.
Patent JP-S59105424-A (JP)
Inventor: MATSUO HIROSHI
IPC: A47J31/44
Filed: 1982-12-08
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-2000050405-A (JP)
Title: Recorder for train
Inventor: SHIMADA IKUO
IPC: B60L3/00
Filed: 1998-07-30
Abstract: PROBLEM TO BE SOLVED: To cancel a sleep state by providing a means for applying voltage to a terminal that detects the reception of a telephone cell connected to a modem in the same manner as the operation, when a signal arrives at the modem through the telephone with the supply of power to a notebook personal computer. SOLUTION: An NFB 112 is connected to a power supply circuit 111 of a target 103 to be measured for supplying power, at the same time, power is also supplied to a personal computer 102, and charging of a battery 108 is started via a power supply circuit 109. Furthermore, power is supplied to a device 101 for starting up the personal computer, a terminal CI of a serial communication port 104 being used as a terminal for detecting the signal reception of a telephone being connected to the modem is impressed, and the sleep state of the personal computer 102 is canceled, thus normally operating the personal computer 102, and hence canceling the sleep state of the personal computer 102 with the supply of power to the personal computer 102.
Patent JP-H0657515-A (JP)
Title: Spinneret
Inventor: TANIGUCHI MASAHARU
IPC: D01D4/04
Filed: 1992-08-12
Abstract: PURPOSE:To stabilize the melt-spinning process by suppressing the development and accumulation of staining substance around the polymer nozzles on the spinneret which is one of the most process-inhibitory troubles in the spinning process. CONSTITUTION:The melt-spinning process is characterized by using a spinneret which has its polymer extrusion surface or a combination thereof with the inner surfaces of individual nozzles plated 0.5 to 20mum thick with a plating composition containing 1 to 25 pts.wt. of at least one selected from fluorinated graphite particles and polytetrafluoroethylene particles of less than 10mum average particle size per 100 pts.wt. of the metal component to be plated, at least one selected from chromium, nickel and cobalt.
Patent JP-H0378084-A (JP)
Title: Pocket size electronic dictionary
Inventor: NAGAISHI MICHIHIRO
IPC: G06F17/28
Filed: 1989-08-22
Abstract: PURPOSE:To improve a recognition rate by using a neural network for character recognition. CONSTITUTION:The optical image of an original sheet surface 20 by an LED array 21 is formed to be a digital signal by a sensor 23 and a binarizing circuit 25. For the moving amount of an electronic dictionary on the sheet surface 20, the rotation of a roller 8 for encoder is transmitted to a slit plate 27 and the light of a photointerrupter 28 is intermittently cut. Then, a pulse signal is generated and with the signal as a reference, the binarized picture signal of the circuit 25 is stored while judging a period for a CPU 30 to write it into a RAM 32. The calculation of the sum of products or of a threshold value between networks is executed by a neural network calculation part 40 and speed for the calculation speed is improved.
Patent JP-2000043718-A (JP)
Title: Rolling stock
Inventor: ODA MASARU
IPC: B61D33/00
Filed: 1998-07-30
Abstract: PROBLEM TO BE SOLVED: To make getting on and off a wheelchair in safety and with ease and, helping the self-support of a person in the wheelchair on a vehicle, make rolling stock efficient and stabilize a diagram. SOLUTION: A slope 15 provided with an elevating mechanism 13 and rotation mechanism 14 is installed on the lower surface of the side door 12 of the outside of a vehicular near skirt part. The slope 15 has the thinness enterd in the gap between the vehicle 11 and a platform 10 and is stored in the cover installed on the lower surface of the side door of the vehicular outside at the unusable time. After confirming the stop of the vehicle at the platform and the stand by of the wheel chair utilizer at the platform, the slope 15 is operated by a conductor room and/or a driver's seat. The space for the wheel chair is provided in the vehicle and the mechanism for stopping the wheel chair wheel and operation board are provided here.
Patent JP-H0262603-A (JP)
Title: Working control method and controller for double spindle machine tool
Inventor: OHASHI HAJIME
IPC: G05B19/18
Filed: 1988-08-30
Abstract: PURPOSE:To reduce the production load of a working program by defining the working processes carried out at 1st and 2nd spindle stocks as a comprehensive working program without discriminating them from each other, and performing both processes in division at the machine side. CONSTITUTION:A working process is carried out based on a comprehensive working program stored in a working program memory 6. In such a case, the form data on a work 26 to be worked which is inputted as the working information is stored in the memory 6 with no consciousness of two spindle stocks 23 and 25. When the comprehensive working program is produced, an operator refers to the work form shown at a display part 7 and issues an instruction to work the stock 23 or 25. When the production is through with the comprehensive working program, a numerical controller 1 converts the working program into the proper programs of both stocks 23 and 25 according to the display of the working division instruction and makes each spindle stock carry out the concrete working respectively.
Patent JP-H0556629-A (JP)
Title: Power converter
Inventor: HIRATA AKIO
IPC: G04F10/00
Filed: 1991-08-28
Abstract: PURPOSE:To exchange parts in a preventive maintenance manner, and to obviate trouble stoppage due to deterioration of the parts by installing a part deteriorating detector and outputting an output signal from the detector to an information indicator mounted inside or outside a power converter as maintenance inspection information regarding the exchange period of the parts used. CONSTITUTION:Signals corresponding to the voltage applying time of each part or the operating time of each part are input from an input terminal 231 by a part deterioration detector 23. When the integrated time of a time integrating meter 233 reaches a value, where only the set value of a pre-information setter 235 is reduced, to the set time of an exposed lifetime setter 234, a comparator 236 detects the reduction of the integrated time and outputs pre-in formation to an output terminal 238. When the integrated time of the time integrating meter 233 is equalized to the set value of the expected lifetime setter 234, the equalization of the integrated time is detected by a comparator 237, and the excess of a partexchange period is output to an output terminal 239. These output signals are indicated by an information indicator 24, and pre-infor mation regarding the exchange of each part is output.
Patent JP-H0766110-A (JP)
Title: Correction prism unit and aligner employing it
Inventor: KOMATSU HISATAKA
IPC: G03F7/20
Filed: 1993-08-31
Abstract: PURPOSE:To allow correction of distortion between a plurality of aligners by disposing a pair of prisms on an incident optical path and then altering the attitude thereof thereby correction the distortion and the like. CONSTITUTION:A mask 21 formed with a predetermined pattern and a correction prism unit 22 comprising a pair of prisms 1, 2 are disposed on the optical path 20a of exposing light emitted from a light source 20. An attitude controller 32 receives an image signal from a TV camera 31 as the positional information of a semiconductor wafer 27 and controls the magnification and the interval of the prisms 1, 2, i.e., the beam shift, based on the positional information and the angle of arrangement of each prism 1, 2 in the prism correction unit 22. The attitude controller 32 has a function for shifting an XY table mounting the semiconductor wafer 27 depending on the beam shift. This constitution corrects distortion between aligners at the time of exposure.
Patent JP-H0761574-A (JP)
Title: Elevating conveying device
Inventor: IWAKIRI SHINICHIRO
IPC: B65G17/26
Filed: 1993-08-31
Abstract: PURPOSE:To perform elevation of an object to be conveyed at a limited space, to shorten a conveyance cycle, and to prevent breakage of the object to be conveyed. CONSTITUTION:Support rollers 1A1 and 1A2 for elevation are fixed to a chain 3R1 run around sprocket wheels 23 arranged in a vertical direction and the rollers 1A1 and 1A2 are moved around along a peripheral round track XR. A spool horizontally conveyed by an upper conveyor is received on the support rollers 1A1 and 1A2, stopped in a position situated facing the spool and through drive of the chain 3R1, the support roller 1A1 and 1A2, are moved and the spool. is lowered. When the support rollers 1A1 and 1A2, pass between the rollers of a lower conveyor, the spool is transferred to the lower conveyor. Right after the starting of lowering, drive at a comparatively high speed is executed and when the spool approaches the lower conveyor, deceleration is effected.
Patent JP-H05194077-A (JP)
Title: Method for manufacture of single crystal silicon rod
Inventor: ROJIYAA EI FUREDERITSUKU
IPC: H01L21/208
Filed: 1992-08-13
Abstract: PURPOSE: To produce a single crystal Si with a large diameter whose oxygen density and distribution are freely adjusted by combining and adjusting a change in a cusped magnetic field in a molten raw material and the number of revolutions of a molten raw material crucible and a seed single crystal silicon in the case of pulling the seed single crystal silicon from a polycrystal silicon melt to grow the silicon rod.  
     CONSTITUTION: A polycrystal Si is placed into a crucible 3 and heated by a heater 5 and the Si is molten (9). A seed single crystal silicon 15 is immersed in a polycrystal silicon melt 9, the seed single crystal 15 is pulled up slowly by rotating a cable 17 for the seed crystal Si 15 in opposite directions to the crucible 3 at a speed faster by 5 r.p.m. and a single crystal silicon rod 13 is grown at the tip. In this case, a current controlled by a control unit 43 is supplied to an upper solenoid coil 45 and a lower solenoid coil 47 provided to the outside of a device 1 from respective power supplies 49, 51 to generate a cusped magnetic field at a surface position 11 of the molten melt 9. The single crystal rod 13 with a diameter as large as 200 mm is obtained where an O 2  density and its distribution state are adjusted by adjusting the number of revolutions of the Si seed single crystal 15 and the crucible 3 and the intensity of the cusped magnetic field. 
     COPYRIGHT: (C)1993,JPO
Patent JP-S6196765-A (JP)
Title: Method for forming metal pattern
Inventor: KINOSHITA YOSHIHIRO
IPC: H01L21/302
Filed: 1984-10-17
Abstract: PURPOSE:To form a microstructure metal pattern with its vertical cross section rectangular by a method wherein a very thin, microstructure mask pattern is formed. CONSTITUTION:On the primary surface of a substrate 1, a 0.12mum-thick WN layer 5 and 0.5mum-thick Au layer 2 are formed and the entire surface of the Au layer 2 is covered by a 0.1mum-thick W layer 6 that is the first masking conductive layer. A photoresist film 7 is formed on the entire W layer 6 with the exception of a mask portion 6a. The mask portion 6a is then covered by a second masking conductive layer that is for example, a 0.1mum-thick Ti layer 8. When the photoresist film 7 is removed, the Ti layer 8 is retained only on the mask portion 6a. Etching is accomplished for removal with the Ti layer 8 serving as a mask. The Au layer 2 and the WN layer 5 positioned thereunder are subjected to an ion milling process wherein they are selectively removed with the Ti layer 8 and mask portion 6a serving as a mask, which results in the building of a gate electrode G.
Patent JP-2000030775-A (JP)
Title: Grounding component for electric light pole
Inventor: FUKUSHIMA SHIGEO
IPC: H01R4/66
Filed: 1998-07-14
Abstract: PROBLEM TO BE SOLVED: To mount a grounding member on an electric light pole prior to its erection, save time for separately burying the grounding member, and simplify work for pole erection, by providing an expandable bellows-type tubular body fittable to a lower end part of the electric light pole and mounting the grounding member made of a conductor on, at least, the outside of a lower surface part of the body. SOLUTION: This grounding component 1 for an electric light pole has a tubular body 2 made of a plastic material. This body has a hard bottom part 3 with a large thickness and a soft tube part 4 formed in a bellows shape, and integrally forms an upward opened glass shape, and the tube body 4 is expandable/contractible in the axial direction. A bolt 6 is provided on the bottom part 3 of the tube body 2 for mounting a grounding member. As the grounding member 7, a conductive metallic plate, a metallic rod, a metallic net, or the like is used. The grounding component 1 for an electric light pole is mounted on an end part of the hollow electric light pole in a force fit manner. Because of the bellows type employed, the length to cover the electric light pole can be freely adjusted.  The grounding component 1 may be mounted on the electric light pole beforehand or may be mounted on the electric light pole at a pole erection work site.
Patent JP-H0378605-A (JP)
Title: Measuring device of precision of superposition
Inventor: KINOSHITA TAKESHI
IPC: G01B11/00
Filed: 1989-08-22
Abstract: PURPOSE:To remove an effect of an auxiliary pattern for visual reading, or the like, and thereby to enable accurate measurement of the amount of slippage of superposition by determining different pattern widths by a faulty pattern discriminator and by deleting a faulty pattern. CONSTITUTION:A faulty pattern width of a first mark group is determined by a faulty pattern discriminator 22, informations (m), (m1) on the position of a faulty pattern are generated and the faulty pattern is deleted from the first mark group, while the faulty pattern is deleted also from a second mark group. A coefficient (h) of cross-correlation of these two patterns is calculated by a cross-correlator 18 and the maximum amount (i) of deviation of the coefficient (h) of the cross-correlation is determined by a peak detector 19. From this amount (i) of deviation and periods (l) and (k) of synchronous calculators 20, the amount of slippage of the two patterns is detected in a slippage amount detector 21, and therefore the amount of slippage of superposition of the patterns in a process of lithography can be measured accurately.
Patent JP-S6276688-A (JP)
Title: Laser control device
Inventor: SHIBATA MITSUHIRO
IPC: H01S3/134
Filed: 1985-09-30
Abstract: PURPOSE:To improve control accuracy and stability of a light output with respect to a light output reference signal to a large extent, by using an intermittent optical output feedback signal, and correcting the light output at every specified period. CONSTITUTION:Electric power P is converted into a laser light output Pho in correspondence with oscillating efficiency of a laser oscillator 3 itself at an arbitrary time. The light Pho is converted into a detected light output signal Pho-D through a light-output detecting circuit 5. The signal is inputted to a divider 7, where a ratio between said signal and a power feedback signal P-F is computed by an expression P-F/Pho-D. A divided output signal 12 is obtained and inputted to a memory circuit 8. A reference-state detecting circuit 10 judges and detects the steady state of the light output reference signal Pho-R. A detected reference-state signal 17 is imparted to a timing control circuit 9. A division command 15 is outputted to the divider 7 from the timing control circuit 9 so that the division is started after the detected light output signal Pho-D is settled. A correction-signal outputting command 14, by which a reference correction signal 13 is outputted at the next steady state, is outputted to a multiplier 6.
Patent JP-H0647298-A (JP)
Title: Roll mill
Inventor: KERUSEI SHII TOMU JIYUNIA
IPC: B02C4/32
Filed: 1991-01-18
Abstract: PURPOSE: To provide an adjustable roll mill having a mechanism capable of automatically adjusting the gap between two rolls by providing this mill with a primary roll and a driven roll and automatically adjusting the change in the gap between the two rolls in a driven roll drive means. CONSTITUTION: This roll mill has a pair of the adjacent primary roll 1 and driven roll 2 having the adjustable gap 20 in-between. The driven roll 2 is pressed to bearings 3' via one set of strong disk springs 10 and is pressed toward the drive roll 1 by means of a pair of precision machine screw jacks 11 lifted by jacks. The positioning of jack screws 9 is accomplished by driving jack nuts via connecting shafts 15 having rigid joints 14 to enable the elongation of the jacks 11. A controller 19 having an optical encoder 18 and a digital reader 21 enables the exact setting of the gap 20 by automatically adjusting the elongation of the machine screw jacks 11.
Patent JP-H0882812-A (JP)
Title: Optical multistage separator
Inventor: OSHIBA SAEKO
IPC: H04B10/27
Filed: 1994-09-12
Abstract: PURPOSE: To provide an optical multistage separator which is simple in constitution and is low in transmission loss. CONSTITUTION: This optical multistage separator has a light distributor 10 which distributes the respective light clock pulses of N (Hz) (N is a positive integer) in repetitive frequencies synchronized with input light signal pulses of a bit rate-B(bit/s) to N pieces of light clock pulses, N pieces of light delaying devices 12a to 12d which discretely delay the respective distributed clock pulses and N pieces of light separators 14a to 14d which are respectively connected to the output terminals of these light delaying devices.  These light separators 14a to 14d have optical multiplexers 18a to 18d which multiplex the input light signal pulses and the delayed light clock pulses delayed by the light delaying devices 12a to 12d, nonlinear means which generate fresh reproduced signals from the respective multiplexed light pulses and optical demultiplexers 20a to 20d which demultiplexthe reproduced signals from the input light signal pulses and the light clock pulses and introduce the input light signals to the light separators of the ensuing stages.
Patent JP-S6195186-A (JP)
Inventor: KAWAGISHI HIDEYUKI
IPC: E06B9/01
Filed: 1984-10-16
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H0555894-A (JP)
Title: Semiconductor device
Inventor: KOIZUMI MASANORI
IPC: H03K17/00
Filed: 1991-08-28
Abstract: PURPOSE:To prevent the increment of current consumption and the generation of a trouble in an output signal due to the drop of driving capacity by selecting an optimum output transistor(TR) out of plural different output TRs based upon an output value of a detection circuit when a power supply voltage is oscillated. CONSTITUTION:A power supply voltage detecting circuit 2 compares a constant voltage generated from a power supply voltage feeding source 1 with a divided voltage to be a reference voltage of a comparator and detects which position out of three power supply voltage positions includes the power supply voltage concerned. Output TRs 4 to 6 have respectively different TR sizes or different impurity values and respectively correspond to voltage levels approximate to respective values VN1 to VN3 V. On the other hand, output TR gate control circuits 7 to 9 are connected to the prestages of the TRs 4 to 6 as decoders for an internal output signal and an output signal from an output TR selecting circuit 10. When the output signal of the circuit 10 is '0', a gate is turned on and the output signal '1' turns off the gate. The circuit 10 decodes the comparator output signal at the time of judging the power supply voltage to select any one of the output TRs 4 to 6. Thus, a wide range power supply voltage correspondence type output circuit can be obtained.
Patent JP-S6276272-A (JP)
Inventor: HIRAI SHINICHI
IPC: H01R13/66
Filed: 1985-09-30
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S6278174-A (JP)
Inventor: TATSUMI KAZUO
IPC: C04B40/00
Filed: 1985-09-30
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H04100259-A (JP)
Title: Semiconductor substrate, its manufacture and semiconductor device
Inventor: HORIE HIROSHI
IPC: H01L21/762
Filed: 1990-08-18
Abstract: PURPOSE:To increase source.drain withstand voltage and reduce leak current, by forming a part which sandwiches polysilicon between a thin plate of silicon crystal and a substrate. CONSTITUTION:A thin plate 3 is stacked on the surface of a silicon wafer 2 so as to interpose an insulating film 17, in which a recessed part 1 of a rectangular pattern is formed. Two apertures 5 penetrating to the recessed part are formed in the thin film 3 of silicon crystal. The recessed part and the two apertures 5 sandwich insulating films 10, 11, 12, 13 composed of thermal oxide films covering the surfaces constituting the recessed part and the apertures, and are filled with polysilicon 14 doped with boron. An NMOS transistor and an PMOS transistor are formed in a thin plate 3A of silicon crystal positioned above the polysilicon 14 buried in different recessed parts and insulated. When a bias voltage of different polarity which corresponds with the kind of the transistors is applied to the buried polysilicon 14, the transistor exhibits normal characteristics of high source.drain withstand voltage.
Patent JP-H0380565-A (JP)
Title: Semiconductor device
Inventor: OBARA SHINJI
IPC: H01L21/8249
Filed: 1989-08-23
Abstract: PURPOSE:To reduce parasitic capacitance of a depletion layer and increase signal transmission speed, by arranging a low concentration N-type region between a P-type semiconductor substrate and a high concentration N-type burried layer. CONSTITUTION:After a surface protecting oxide film is formed on a main surface of a P-type semiconductor substrate 101, phosphorus is introduced by ion-implantion method, and a low concentration N-type region 102 is formed by heat treatment. Boron is introduced by ion-implantation method, and a P-type buried layer 103 is formed by heat treatment. After that, the surface protecting oxide film is eliminated, and an N-type epitaxial layer 104 is formed. By the same means as the forming of the buried layer, phosphorus and boron are introduced, and an N-type well 105 and a P-type well 106 are formed on the buried layer. A field oxide film 107 is formed by selective oxidation method. Hence the parasitic capacitance of the buried layer part is reduced, and signal transfer delay time can be decreased.