Patent SG-11201901211X-A (SG)
Title: Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory
Inventor: DERNER SCOTT J
IPC: H01L27/11502
Filed: 2017-08-02
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) CORRECTED VERSION --, (19) World Intellectual Property 11111111011110111010101111101 11010011110111011101111 1110111E011110 III1 Organization International Bureau (10) International Publication Number l i (43) International Publication Date ...../ WO 2018/044487 A8 08 March 2018 (08 03.2018) WI PO I PCT (51) International Patent Classification: AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, G11C 11/22 (2006.01) H01L 27/11502 (2017.01) CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, (21) International Application Number: DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, PCT/US2017/045182 HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, (22) International Filing Date: MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, 02 August 2017 (02.08.2017) OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, (25) Filing Language: English TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (26) Publication Language: English (84) Designated States (unless otherwise indicated, for every (30) Priority Data: kind of regional protection available): ARIPO (BW, GH, 62/381,900 31 August 2016 (31.08.2016) US GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, 8000 South Federal Way, Boise, Idaho 83716 (US). EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, (72) Inventors: DERNER, Scott J.; 5032 E. Sagewood Drive, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, Boise, Idaho 83716 (US). KAWAMURA, Christopher J.; TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, — 1778 S. Toluka Way, Boise, Idaho 83712 (US). KM, ML, MR, NE, SN, TD, TG). = (74) Agent: ENG, Kimton et al.; DORSEY & WHITNEY LLP, Published: 701 5th Ave, Suite 6100, Seattle, Washington 98104 (US). _ with international search report (Art. 21(3)) (81) Designated States (unless otherwise indicated, for every (48) Date of publication of this corrected version: kind of national protection available): AE, AG, AL, AM, 29 March 2018 (29.03.2018) = — (54) = ELECTRIC = _ Title: APPARATUSES AND METHODS INCLUDING MEMORY RESTORE 0,--.200 V 235 (-125 231 oND FERROELECTRIC MEMORY AND FOR ACCESSING FERRO- (57) : Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a SA 4 second cell plate of the capacitor, a second digit line, and a second sense node. == = — = = 232 r/s-P ISOREF -----H '-- VEIREF ' Igo '. \ -233 239 Y _ pH s The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven — +Num 1.0 to the first voltage responsive to the voltage of the first node being greater than MC(A) 205,4 ----- 220 f 0 the second node = — 224 23 , 15 (10 = WL-CB(0) Wt-CT(1) t05-\ MC 1) . : 205--, 4 1 /0 GC • - 4 230 , .15 /10 .4 wucEn_ 4._' IN GC 71' WL-CT011 105 - \ 1. 71' 71' MC(n) 110 © 4 230 , _1S 1 110 WL-CS(n) 1-1 0 N FIG. 2A C [Continued on next page] WO 2018/044487 A8 MIDEDIM310101011MOHOINIEDHOHOHEMOHMOVE# (15) Information about Correction: see Notice of 29 March 2018 (29.03.2018)