Patent GB-1321717-A (GB)
Title: Input output signal point assignment
IPC: H01L27/118
Filed: 1970-06-22
Abstract: 1321717 Programme controlled integrated circuit manufacture TEXAS INSTRUMENTS INC 22 June 1970 [15 July 1969 (3)] 30090/70 Heading G3N In the manufacture of an integrated circuit array including semi-conductor active components such as flip-flops or logic gates, conductors interconnecting such components, and inter-connections to input/output bonding pads, a computer 208, Fig. 5 is programmed to provide representations of such inter-connections on magnetic tape 212, the tape subsequently controlling a drafting machine 216 to provide guidance for a cutter over peel-coat material to provide a set of masks for circuit fabrication. Assignment of input/output points 1-7, Fig. 3 of circuit elements to bonding pads 60-73. The pad assignment unit 200, Fig. 5 of computer 208 determines the polar angle, α of each point 1-7 relative to a polar co-ordinate system, a similar angle # (not shown) relative to the same system for each of the pads 60-73 and, taking each point 1-7 in numerical turn, determines the angular differences α - # between the point and all pads not previously assigned. If the least such difference is less than a predetermined threshold angle # 1 , the pad corresponding to such difference is assigned to the point. If no such difference is less than the threshold # 1 , the point is passed without having a pad assigned. After the above procedure, a larger thereshold # 2  is selected, and the procedure is repeated for the remaining unassigned points, and further passes with yet larger thresholds are made until all points have a pad assigned thereto. Determining inter-connection paths between input/output points 1-7, Fig.4 of circuit elements and bonding pads 60, 62, 64, 73, 72, 70 and 69. Inter-connections are made in successive equally spaced channels parallel to the X axis. The in/out routing unit 202 Fig.5 of the computer considers whether each of the inter-connections from the points 1-7 in turn can be made in a first channel, nearest the outer boundary of active element rows A-G, H-M, without blocking connections from any other point, and all such connections, e.g. 1-60, 4-73, are made in the first channel. Subsequent passes of the computer routine consider, successively, second and higher channels, until all inter-connection paths are represented. Determining inter-connections within andbetween active element rows 50, 52, Fig.1. i) connections within a row, 50. Row routing unit 204, Fig.5 of computer 208 establishes (X 1 ,Y) co-ordinates of each signal point, and, having established the lengths of desired inter-connections, places the longest inter-connection path in a first stacking channel, closest to the row, and, considering the paths in order of decreasing length, assigns as many of the other paths as possible to the first channel. Subsequent passes of the routine consider further channels, parallel to the first, of increasing distances from the row, placing all remaining inter-connection, in decreasing length order, in the closest possible channels. Connections within row 52 are similarly established. ii) connections between rows 50, 52, see also Fig.2, (not shown). Inter-row routing unit 206, Fig. 5 places as many such inter-connections as possible, without blocking any other point, in the channels belonging to either one of rows 50, 52, using the technique of (i) above, the remaining connections being allocated to further channels, or, alternatively, considers all such interconnections in decreasing length order delaying establishment of any given path to a subsequent pass of the routine if it would block any other inter-connection. Fig. 6 (not shown) displays a complete circuit array in which, to carry out the computer programme, the upper and lower rows as depicted have been considered as a single row, with elements (101, 103) adjacent. Interconnection paths include sections diffused into the semi-conductor substrate, where conductor paths are crossed. Feed-through blocks, such as (126) may be provided to give connections on the outer periphery of the array, which is built up on a silicon substrate (250), Fig. 7 (not shown), by photographic, etching, and impurity diffusion methods.