Patent GB-1055962-A (GB)
Title: Improvements in or relating to data-processing apparatus
IPC: G06F11/10
Filed: 1963-07-11
Abstract: 1,055,962. Error detection and correction. HONEYWELL Inc. July 11, 1963 [July 12, 1962], No. 27592/63. Headings G4A and G4C. Apparatus for correcting data carried in a plurality of data transfer channels includes a parity transfer channel and means for identifying a data transfer channel in error and connecting the parity transfer channel and all the data transfer channels except that channel in error to a parity generator, the data in the channel in error being replaced in accordance with the output of the parity generator. Referring to Fig. 2 (not shown), the words each have six frames of eight bits and are read from magnetic tape serially by word and frame, eight bits in parallel, by reading heads 1 . . . 8. Each frame is accompanied by a parity bit (read at 9). With each pair of data words a check word is also read, each of whose bits is the modulo-two sum (without carry) of the corresponding bits in the two data words. The words are read into a memory (via gating sections 32, 34 . . . 44, 46 and a memory local register) and the bits of each frame are passed through AND gates 50, 52 . . . 62, 64 controlled by flip-flops into a parity generator 30, which gives for each frame the modulo-two sum (without carry) of the bits, which is passed to a gate 70 for comparison with the parity bit for the frame which arrives via flip-flop-controlled AND gate 68. If a parity error is present, a sub-routine is initiated in which the three words placed in the memory are read out again into an accumulator which forms the modulo-two sum (without carry) of each trio of corresponding bits. If any sum is a 1 (indicating presence of error) a corresponding one of eight six-input OR gates (one per data channel) gives a 1 output which switches a corresponding flip-flop. This has the effect, in that particular data channel, of closing the AND gate 50, 52 ... 62 or 64, of cutting the reading head off from the memory (by closing the upper AND gate of the gating section 32, 34 ... 44 or 46) and of connecting the output PG of the parity generator 30 to the memory in its place (by opening the lower AND gate of the gating section). The 1 output from the OR gate corresponding to the erroneous channel is also read into an otherwise zeroed shift register, the contents of which are then read out into a flipflop, the 1 switching the flip-flop. This has the effects of (a) connecting the parity reading head 9 to the parity generator 30 and disconnecting it from gate 70 (by means of AND-gates 66, 68); (b) enabling another AND gate so that any further 1 shifted out of the shift register will switch an uncorrectable-error indicator flip-flop to indicate that more than one channel is in error. Meanwhile, the magnetic tape has been backtracked to allow the three words to be read off again. This is now done, the data (apart from the erroneous channel) being read into the memory and parity generator 30. The parity bits are also read into the parity generator 30, the outputs of which (for the successive frames) naturally being the correct bits for the erroneous channel and are fed to the memory via the appropriate gating section 32, 34 ... 44 or 46. Orders for initiating reading (of the magnetic tape) and the accumulator operation are programmed out of the system memory into individual shift registers from which they are shifted into a control register as needed (Fig. 5, not shown). Beginning and end of record signals BOR, EOR are read off the tape for control purposes. It is mentioned that parity channels may be associated individually with each data channel to permit correction of more than one erroneous channel.