Patent GB-939449-A (GB)
Title: Electronic computer wtih abbreviated addressing of data
Inventor: SACERDOTI GIORGIO
IPC: G06F9/355
Filed: 1962-04-10
Abstract: 939,449. Digital computers. ING. C. OLIVETTI & C. S.p.A. April 10, 1962, No. 13809/62. Class 106 (1). In an electronic computer, the instruction words contain an operation part and an operand address part, the operand address part of which may consist of an abbreviated operand address, the full operand address being obtained by substituting the abbreviated operand address digits for correspondingly significant digits in the full address of the operand last employed. An economy in storage space is thus obtained. The computer described has a magnetic core matrix store M, comprising four planes for storing characters in binary coded form, a fifth plane being provided to store an end-of-word bit. Computer instructions take the form where FF represents the operation, T represents the address of an index register and the five I digits are a 5-decimal digit number representing the address of the operand, commencing with the least significant digit, the underlining mark representing an end-of-word bit. Any number of address digits, beginning with that of highest order (the last digit) may be omitted, the omitted digits being equal to the corresponding ones of the last addressed operand. The machine operates serially and in alternate preparation and execution phases, each phase consisting of a number of elementary steps controlled by a magnetic core sequencing matrix, Fig. 1, of 256 rows and 100 columns, columns 0-7 being arranged to determine the next row to be pulsed, the remaining columns supplying command signals C8-C99 to the various parts of the computer. The effect of pulsing a row may depend on the state of various "condition" windings K1, K2 &c. whose state depends on the occurrence of certain conditions in the computer. The computer is shown schematically in Figs. 2a, 2b, and comprises the store M, an arithmetic unit UA, an input unit OI, an output unit OU, and a present address register W, in addition to the control and sequencing part. An auxiliary register J1 stores the full address of the next instruction character to be addressed and an auxiliary register J2 stores the full address of the last addressed operand. A character counter CC is stepped by a command C44 and provides condition signals for the sequencing matrix on its outputs P0-P7. The preparation phase of an instruction is as follows. The sequencing matrix initially causes the contents of the register J1 to be transferred to the register W. The character addressed by the register W is then read from the store M and entered in registers RF1, RA, the contents of the register W being transferred via an " add one " circuit controlled by a gate 30 to the register J1. The contents of the register RA is then re-written into the came memory location. The content of the register J1, i.e. the address of the next instruction character, is now transferred to the register W, and the character counter CC is advanced by one step. The subsequent instruction characters are read out from the store in a similar way, the second operation character F being transferred to a register RF2. When the fourth and fifth instruction characters, i.e. the I digits are extracted, they are transferred via the register RA to the units and tens parts of the register J2. The detection of the " end-of-word " bit read out with the fifth character causes the contents of the register J2, i.e. the full operand address of the first operand character to be transferred to the register W, and the character counter CC to be reset. The address of the next sequential instruction is retained in the register J1 for future use. Specification 734,073 is referred to.