baber/WOPTO huggingface dataset:
Patent TW-358898-B (TW)
Title: Film scanner
Inventor: HOSHINO YASUSHI
IPC: H04N5/253
Filed: 1997-04-18
Granted: 1999-05-21
Abstract: A film scanner, for optic reading image data recorded on a film, including the film scanner: image data reader; the first drive, for driving the first carrier of the film and holding the second carrier holding the film cartridge; identifier, for identification of the first carrier and the second carrier, before starting the first drive of the first carrier or the second carrier; the second drive, for driving the first carrier or the second carrier; and controller, for the first drive to drive the first carrier when the identifier identifies the first carrier, and the film held by the first carrier being scanned and for the second drive to drive the second carrier when the identifier identifies the second carrier, and the film held by the second carrier being pre-scanned.
Patent TW-331692-B (TW)
Title: An improved image encoder and generator of auxiliary carrier signal
Inventor: GONG JENN-BANG
IPC: G06T9/00
Filed: 1997-05-09
Granted: 1998-05-11
Abstract: An improved image encoder includes a. an auxiliary carrier signal generator utilizing the system time clock signal to generate a first carrier signal and a second carrier signal which are all triangle waveforms and have phase shift of 90 degree b. a first modulator modulating the first image signal with the first carrier signal to obtain the first modulated signal c. a second modulator modulating the second image signal with the second carrier signal to obtain the second modulated signal d. a adder combining the above two modulated signals to obtain a combined signal e. a chopper limiting the amplitude of the combined signal and outputting a color signal.
Patent TW-322617-B (TW)
Title: Easy measurement device for memory temperature characteristic
Inventor: TSAY CHORNG-HER
IPC: H01L21/66
Filed: 1997-06-16
Granted: 1997-12-11
Abstract: An easy measurement device for memory temperature characteristic comprises: (1) one address counter; (2) one control logic whose output port is connected to input port of the above address counter; (3) one comparison logic whose input port is connected to output port of the above control logic.
Patent TW-402809-B (TW)
Title: The manufacture method of electrical charge storage structure
Inventor: HUANG GUO-TAI
IPC: H01L21/8242
Filed: 1997-10-18
Granted: 2000-08-21
Abstract: This invention provides a manufacture method of electrical charge storage structure to increase the capacitance value of electrical charge storage structure, which applies on the substrate which forms the MOS transistor. First, form an insulative layer on the substrate, and form a contact via on the insulative layer, and expose the source/drain region, then form the tungstein silicide layer on the surface of the substrate, wherein the tungstein silicide layer is used as the bottom electrode of the electric charge storage structure. Next, form a tungstein nitride on the tungstein silicide layer, and form a dielectrics on the tungstein nitride layer; the dielectrics material is used as tantalum oxide; finally, form a titanium nitride layer on the surface of the tantalum oxide wherein the titanium nitride layer is used as the upper electrode of the electrical charge storage structure.
Patent TW-380281-B (TW)
Title: Ion implantation system and method adapted for serial wafer processing
Inventor: TAMAI TADAMOTO
IPC: H01L21/677
Filed: 1997-10-29
Granted: 2000-01-21
Abstract: A serial wafer processing type ion implantation system and method suitable for small production of many product types. The ion implantation method  implants ions while a first wafer group including at least one or more wafers is rotated along a first orbital path intersecting with a path of an ion beam and while a second wafer group including at least one or more wafers is rotated along a second orbital path intersecting with the path of the ion beam, at least a portion of the second orbital path being different from the first orbital path.
Patent TW-424118-B (TW)
Title: A flat knitting machine comprising a set-up device
Inventor: IKOMA KENJI
IPC: D04B15/90
Filed: 1997-11-05
Granted: 2001-03-01
Abstract: A flat knitting machine comprising: at least a pair of front and rear needle beds defining a gap therebetween; and a set-up device disposed below said gap, said set-up device including: a plurality of setting-up needles, each having a setting-up needle base member and a setting -up needle slider member,said setting-up needle slider member being movable relative to said setting-up needle base member to selectively hold and release a set-up portion of a knitted fabric; a setting-up needle bed supporting said plurality of setting-up needles so that said plurality of setting-up needles are juxtaposed to one another and that each of said setting-up needles is movable in both a fabric pull-down direction and a direction opposite thereto; first biasing means for biasing each of said setting-up needles in said fabric pull-down direction relative to said setting-up needle bed; and setting -up needle hold and release means for moving said setting-up needle slider member relative to said setting-up needle base member to thereby control said setting-up needle slider member to hold and release said set-up portion of said knitted fabric.
Patent TW-379415-B (TW)
Title: Method of integrating via manufacture modules
Inventor: CHIANG WEN-CHUAN
IPC: H01L21/768
Filed: 1998-01-20
Granted: 2000-01-11
Abstract: A method of making deep vias having the key performance under the conventional photoresist mask and by adding a polysilicon hard mask for additionally selective etching effect while protecting the dielectric layer under the protection mask, and keeping the dielectric layer from disappearing by lossing of photoresist in the etching process, and without hurting by the etching reaction. Finally, filling photoresit in the finished deep via to avoid the residue left by the chemical mechanical polishing process in the deep via to trouble the incoming manufacture process. The key manufacture processes: 1. Forming the polysilicon hard mask, 2. Defining the deep via location, 3. Deep via etching, 4. Filling photoresist in photoresist in the finished deep via, 5. Chemical and mechanical polishing for removal of the polysilicon hard mask, 6. Removing the photoresist to complete the making of the deep via.
Patent TW-442966-B (TW)
Title: Manufacturing method of DRAM capacitor
Inventor: WANG CHIUAN-FU
IPC: H01L27/108
Filed: 1998-08-03
Granted: 2001-06-23
Abstract: A manufacturing method of DRAM capacitor comprises forming a dielectric layer and several stacked conducting layers and insulating layers sequentially on the substrate; shortly afterwards, patterning a bottom insulating layer and several conductive layers and insulating layers on top of it, so as to form openings on top of the corresponding source/drain region; next, forming a spacer on the sidewall of the insulating layer and conductive layer exposed by the openings, and using the spacer as the hard mask to etch sequentially to form a contact opening; then, defining several insulating layers and conductive layers on top of it by using the conductive layer covering on the dielectric layer as the etching stop layer; forming another conductive layer on the substrate to cover the other sidewall of the defined insulating layer and conductive layer, and fill into the contact opening; then, removing part of the conducting layer to expose the spacer; next, removing the spacer and insulating layer to expose the storage electrode structure of said conductive layer.
Patent TW-425754-B (TW)
Title: Portable power unit
Inventor: ASAI KOUICHI
IPC: H02M5/27
Filed: 1998-09-23
Granted: 2001-03-11
Abstract: A protable power unit is provided. A desired waveform signal indicative of a desired waveform having a desired frequency is generated. Switching control of a variable control bridge circuit is performed based on the desired waveform signal to cause the variable control bridge circuit to generate an alternating current output. A waveform of the alternating current output is detected to generate an output waveform signal indicative of the detected waveform of the alternating current output. A power factor is detected by comparing the desired waveform signal and the output waveform signal to generate a power factor signal indicative of the detected power factor. Voltage of the alternating current output is controlled based on the power factor signal.
Patent TW-426988-B (TW)
Title: Semiconductor integrated circuit apparatus
Inventor: MIZUNO HIROYUKI
IPC: H01L23/58
Filed: 1998-12-09
Granted: 2001-03-21
Abstract: This invention can be used to realize a semiconductor IC unit such as a microprocessor, etc. with high speed, low electrical power, reliability and include the followings: the main circuit (LOG) which is constituted by the transistors on a semiconductor and the semiconductor integrated circuit apparatus such as microprocessor; substrate voltage bias control circuit (VBC) which is used to control the bias voltage added to substrate. The main circuit has the switching transistors (MN1, MP1) which are used to control the bias voltage added to substrate. The output control signal of substrate bias voltage control circuit is imported to the gate of the switching transistors. The control signal is feedback to the substrate bias controlling circuit.
Patent TW-396439-B (TW)
Title: Manufacturing method of semiconductor device
Inventor: SUZUKI MIEKO
IPC: H01L21/304
Filed: 1998-12-10
Granted: 2000-07-01
Abstract: To remove the metal ions remained on the semiconductor substrate with chemical mechanical polishing (CMP) accurately processed in the process that the metal wires are formed on the semiconductor substrate with intermediate insulation layer. To process CMP for the semiconductor substrate 1, then, clean the polished semiconductor substrate 1 by using the clean liquid with removing effect for Fe ions remained on the semiconductor substrate 1 due to the prescribed CMP.
Patent TW-378253-B (TW)
Title: Simple improvable design for increasing the output power of a Internal combustion engine
Inventor: MEYER SIEGFNIED
IPC: F02P9/00
Filed: 1999-01-27
Granted: 2000-01-01
Abstract: In order to increase the output efficiency, this invention for an internal combustion engine provides an improvable design in its structure, mainly consisting of a cylinder, a link rod, at least one crankshaft and an output bearing, This improvable design is characterized in transversally extending an extra link member on the traditional line-shaped link rod. The extra part can join the crankshaft by its lower head. Due to adding a transversal link member, it will be helpful to avoid aligning the main body of link rod, the lower head on the extra part of link rod, and output bearing. In other words, never ignite at the time of death line for the sake of not losing most output power. This new design will not only make the explosion in the cylinder much closer to the complete combustion, but produce whole output power, reduce the fuel consumption and effectively decrease the air pollution.
Patent TW-408470-B (TW)
Title: Thin film capacitor and the manufacture method thereof
Inventor: ARITA KOJI
IPC: H01L27/108
Filed: 1999-02-24
Granted: 2000-10-11
Abstract: The topic of this invention is to provide a kind of thin film capacitor, which uses the high dielectrics coefficient oxide film, has fine capacitance characteristic and could keep fine leakage characteristic. The structure of the thin film capacitor 1 of this invention is: form sequentially at least the bottom electrode layer 102, the high dielectrics constant oxide film 103 and the upper electrode layer 105 on the semiconductor substrate 101; said upper electrode layer 105 which is a film layer 104 formed by the electrical conductive material which is processable by reactive ion etching, or a multilayered film composed of two kinds of film layers 107 and 108, which are each formed of a conductive material which is processable by at least two kinds of reactive ion etching. When a 0V-2V driving voltage is applied toward said thin film capacitor 1 after the thermal treatment of 350 DEG C, the leak current density is below 1*10<-8>A/cm<2>.
Patent TW-416131-B (TW)
Title: Integrated semiconductor-chip with lines to one or more external terminals
Inventor: BUCK MARTIN
IPC: H01L23/64
Filed: 1999-08-03
Granted: 2000-12-21
Abstract: On the lines (Z) of an integrated semiconductor-chip, the potential-oscillations can be activated by some high timed current-impulses to cause the resonance-oscillations on an internal terminal of the respective line (Z), said lines (Z) form a connection to external terminals of the power-supply voltage. In order to dampen the potential-oscillations, a resistance-value (RD) is provided for one or more lines (Z), said resistance-value (RD) is large enough to dampen the potential-oscillations, but is small enough to cause on the respective line (Z) only a pre-determined maximal allowable voltage-drop. The resistance-value (RD) can be obtained by the use of a material with a suitable specific resistance or by decreasing the cross-sections (q) of the lines with a notch (k) along the line (Z).
Patent TW-426964-B (TW)
Title: Fabrication method of copper alloy interconnects
Inventor: TSAI MING-HSING
IPC: H01L21/768
Filed: 1999-09-14
Granted: 2001-03-21
Abstract: This invention provides the fabrication method of copper alloy interconnects. On the upper surface or the lower surface of pure copper metal layer, an adjacent copper alloy layer (Cu and Zr, Al, Ti, or Sn) is formed. Thermal annealing process is used to make Zr, Al, Ti, or Sn and so on diffuse into pure copper metal layer in order to form the copper alloy interconnects. Based on the fabrication method of this invention, the oxidation of pure copper metal can be prevented. Furthermore, the electromigration resistance of interconnects can be increased.
Patent TW-425308-B (TW)
Title: Plastic sorting apparatus
Inventor: MAEHATA HIDEHIKO
IPC: B29B17/00
Filed: 1999-11-02
Granted: 2001-03-11
Abstract: Plastic pieces (2) are collectively supplied to a charge apparatus (4) by a supply amount W1 by a conveyor (3) and stirred only for a predetermined time T within the charge apparatus (4) to be charged and the charged plastic pieces (2) are collectively discharged to be continuously supplied to the surface of a drum electrode (5) by a supply amount W2 per a unit time by a screw feeder (20). At this time, when the peripheral velocity of the rotating drum electrode (5) is set to V and the width of the drum electrode (5) is set to B and the average thickness of the plastic pieces (2) supplied to the drum electrode (5) is set to H and the bulk density of the plastic pieces (2) is set to D, the supply amount W2 is set so as to satisfy W1/T ≦ W2 ≦ V x B x H x D.
Patent TW-520502-B (TW)
Title: Vertically integrated magnetic memory
Inventor: PECZALSKI ANDRZEJ
IPC: H01L43/06
Filed: 1999-12-17
Granted: 2003-02-11
Abstract: A vertically integrated magnetic memory with Hall effect sensing or reading. It has a ferromagnetic structure with a nearly enclosed magnetic path, which is a vertical structure integrated on a chip. Each memory cell has a closed magnetic field that has high strength for a strong Hall effect. The magnet is a closed loop, robust reproducible magnet. A memory array of such cells uses little power in that only few cells need to draw the read current for a short time required to read the information. A silicon or GaAs chip implementation of the memory is one embodiment, among others, wherein the field required to saturate the electrons can be achieved without excessive power.
Patent TW-436660-B (TW)
Title: Photographic film container and loading method
Inventor: CHAN YET
IPC: G03B17/00
Filed: 2000-01-29
Granted: 2001-05-28
Abstract: A photograph film container (2, 102, 202) has a housing (4, 104, 204) defining an elongate film slot through which, in use, the film may extend, and an aperture (13, 15; 113, 115; 213, 215) for insertion of a film-winding tool (42), the aperture (13, 15; 113, 115; 213, 215) being closed by a resiliently biased movable shutter plate (28). A method of loading film into such a container involves the steps of inserting a film winding tool (42) through an end cover of the container with the shutter (28) open and securing a leading end of the film extending from a further film container onto the end of a film-winding tool (42); inserting the housing over the film-winding tool and securing the end cover to the housing; enclosing the first and second film containers in a light-tight enclosure; rotating the film winding tool to wind the majority of the film out of the second film container and into the further film container; (f) removing the end of the film winding tool from the first film container and closing the movable shutter plate to close the aperture; and (g) opening the enclosure and removing the film assembly.
Patent TW-497965-B (TW)
Title: Electrical vacuum cleaner
Inventor: NAKAI KOICHI
IPC: A47L9/08
Filed: 2000-02-02
Granted: 2002-08-11
Abstract: The object of the present invention is to reduce the weight of a double hose to form an air suction flow passage and an air discharge flow passage in a vacuum cleaner of discharged air circulation type. In the electrical vacuum cleaner in which an air discharge flow passage B to circulate the air discharged from an electric fan 5 is formed together with an air suction flow passage A in a hose 2, a pipe and a suction piece to be connected to a vacuum cleaner body 1 with the electric fan 5 are built therein, and the hose 2 is of double structure. A flexible hose (one-layer and two-wire hose 2b) in which a coil wire 21 with the electric conductivity and shape keeping property is built is used for an external hose to form the air discharge flow passage B, and a flexible hose (a conduit hose 2a) in which no coil wire is built is used for an internal hose to form the air suction flow passage A.
Patent TW-439293-B (TW)
Title: Nonvolatile semiconductor memory
Inventor: TANZAWA TORU
IPC: G11C16/34
Filed: 2000-03-15
Granted: 2001-06-07
Abstract: A potential generating circuit generates two types of erasing verification threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2=EVT1+(OEVT-EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1 and is lower than OEVT. The erase verify threshold values EVT1 and EVT2 are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.
Patent TW-498357-B (TW)
Title: Magnetic ferrite film
Inventor: FUKUDA YASUTAKA
IPC: H01L43/10
Filed: 2000-04-18
Granted: 2002-08-11
Abstract: A magnetic ferrite paste is applied onto an Si substrate, and then sintered form thereon a magnetic ferrite film having a mean composition that comprises from 40 to 50 mol% of Fe2O3, from 15 to 35 mol% of ZnO, from 0 to 20 mol% of CuO, and from 0 to 10 mol% of Bi2O3 with NiO and inevitable impurities as the balance. The magnetic ferrite film thus formed on an Si substrate is for magnetic devices, and it forms a region not containing CuO or having a CuO content of at most 5 mol% around its interface directly adjacent to the surface of the Si substrate. The adhesiveness of the magnetic ferrite film to the underlying Si substrate is high, and the reliability of the magnetic device having the magnetic film is therefore high.
Patent TW-502504-B (TW)
Title: Method and apparatus for supervising a potentially gated signal in a wireless communication system
Inventor: JOU YU-CHEUN
IPC: H04B17/00
Filed: 2000-06-23
Granted: 2002-09-11
Abstract: This is a method and apparatus for supervising a potentially gated channel in a wireless communication system. The mobile station (4) maintains a counter of consecutive bad frames, COUNT1 (224), and a counter of consecutive good frames, COUNT2 (226). COUNT1 (224) and COUNT2 (226) are set to zero at the beginning of a call. For each frame received, the mobile station (4) determines if it is a good, bad, or an empty frame. If the received frame is good, COUNT1 (224) is reset to zero and COUNT2 (226) is incremented by 1. If the received frame is bad, COUNT1 (224) is incremented by one and COUNT2 (226) is reset to zero. If the received frame is empty, COUNT1 (224) and COUNT2 (226) are unchanged. If COUNT1 (224) reaches a threshold value, TH1, the mobile station (4) shall disable its transmitter. Thereafter, if COUNT2 (226) reaches a threshold value, TH2, the mobile station (4) shall re-enable its transmitter.
Patent TW-507094-B (TW)
Title: Liquid crystal display device
Inventor: YOSHIKAWA SHUKEN
IPC: G02F1/13363
Filed: 2000-08-24
Granted: 2002-10-21
Abstract: A liquid crystal display device includes a pair of phase compensation plates substantially arranged between substrates by a fixed distance for controlling the total delay of the LCD device. In addition, a wavelength dependence compensation plate is arranged for compensating the wavelength dependence of the total delay of the LCD device, thereby improving the contrast.
Patent TW-451283-B (TW)
Title: Process of high co-planarity flip chip solder bump
Inventor: CHEN JR-SHUEN
IPC: H01L21/00
Filed: 2000-09-15
Granted: 2001-08-21
Abstract: A flip chip solder bump process is employed to form arrays of solder bumps on a semiconductor chip and prevent the adjacent solder bumps from generating the electrical bridging. The process is characterized in using two steps to apply the solder. In the first step, the solder is applied by electroplating and the coated solder does not exceed the upper surface of the mask. In the second step, the solder is applied by screen printing such that the upper surface of the printed solder is substantially flush with that of the mask. The flip chip solder bump process is therefore able to prevent each formed solder bump from generating the mushroom-like upper part such that the bridging is not occurred between the adjacent solder bumps. In addition, each formed solder bump has substantially equal volume and height such that the requirement of high co-planarity can be reached.
Patent TW-498246-B (TW)
Title: Payment method and device
Inventor: YE JIA-SHUEN
Filed: 2000-10-04
Granted: 2002-08-11
Abstract: The invention brings up a payment method that is applicable to the constructed system of a computer host and terminals in connection with the computer host for processing a payment process of a purchase order (PO). The payment method includes the following procedures: providing an input screen via the terminals to get input of at least a PO parameter corresponding to the PO; following at least one receipt attribute to classify the receipts corresponding to the PO; following the PO parameter of the PO to search and open a delivery order; following the delivery order to search and open an inspection data; when the PO has the corresponding delivery order and the inspection data and the contents of the inspection data shows that the delivery order has already finished inspection, automatically generating payment bill; and generating a web page on the computer host in accordance with the delivery order, the inspection data and the payment bill to present the relevant information of the PO. In addition, after the system finishes all procedures, it will automatically inform all suppliers of the payment conditions via e-mails.