Patent GB-1015234-A (GB)
Title: Ferro-magnetic matrix storage unit
IPC: G11C7/02
Filed: 1963-10-04
Abstract: 1,015,234. Magnetic core matrix stores. STANDARD TELEPHONES & CABLES Ltd. Oct. 4, 1963 [Oct. 9, 1962], No. 39170/63. Heading G4C. [Also in Division H3] A store comprises two identical co-ordinate matrices and the writing of a word into the matrices is effected in two steps, a first portion of the word being written into the first matrix and the second portion of the word being written into the second matrix during a first step and the second portion of the word being written into the first matrix and the first portion being written into the second matrix during a second step. Similarly, reading of a word is effected in two steps. As shown in Fig. 3, the store comprises two stores S<SP>1</SP> and S<SP>11</SP> of which only the cores for the nth word are shown, read and write operations being controlled by signals TE, TL of equal duration and each being divided into six equal time periods t1 to t6. During time TE-tl the first half of the digits stored in the register RES are written in the cores of column CaN and the second half of these digits are written in the cores of the column CcN by a coincident current method. During time TE-t3 the first half and the second half of the digits are written in columns CdN and CbN respectively. Read out is achieved by applying a full select current to columns CaN and CcN at time TL-t1, when the signals appearing on the sense conductors are passed to bistable circuits of the register RES, and at time TL-t3 a further read operation is performed on columns CbN and CdN to read the word into the register RES a second time. The above arrangement eliminates the error of writing or reading of a digit " 0 " instead of a digit " 1." The circuit of Fig. 3 is included in a six-digit word store, Figs. 4, 5 which is also arranged to detect errors of the type wherein the writing or the reading of a digit " 1 " occurs where a digit " 0 " was intended. Information is read into the store S<SP>1</SP> by coincident half currents from generator GCa and row current generators L1, L3, L5 at time TE-t1 and coincident half currents from generator GCb and row current generators at time TE-t3. The generators L1, L3, L5 are activated from the logical circuits in write switching circuits LBS<SP>1</SP> which are activated at time TE-t1 for the transfer of information in the odd rank bi-stable circuits of the input/output register RES to the cores of column CaN and at time TE-t3 in the even rank bi-stable circuits to the cores of column CbN. Read out is achieved by applying a full select current to column CaN from generator GCa at time TL-t1 and a full select current to column CbN from generator GCb at time TL-t3. Outputs from the sense conductors are applied to amplifiers D1, D3, D5 and then to the logical circuits in the read switching circuit RBS<SP>1</SP> which switch the output signals towards the even or odd bi-stable circuits of the register according to whether the operation is at time TL-t1 or TL-t3. Information is read into and out of store MTS<SP>11</SP> in a similar manner. At time t5 a register clearing signal is applied over conductor 12 to all the " 0 " inputs of the register. The error detection device, Fig. 5, shown for the loop R1 of store MTS<SP>1</SP> comprises bi-stable circuit V1 which is set to its " 0 " state during time t5 and has its " 1 " input connected to the output of read out amplifier D1. If the cores S<SP>1</SP>1 or S12 are changed to their " 1 " state during a read or write operation the bi-stable circuit V1 sets to the " 1 " state and the output therefrom is then compared with the output from bi-stable circuit B1 during time t2 and with the output from bi-stable circuit B2 during time t4. If the states of the compared bi-stable circuits differ the error display circuit is set to its " 1 " state. The presence of a signal on the output of circuit M3 indicates that a " 0 " has been written instead of a " 1 " in either of the cores or a " 1 " has been read out of the cores and has been written as a " 0" in the register RES which errors are automatically corrected as explained above. The setting of the display circuit ES<SP>1</SP> also indicates that during a read operation a " 0 " has been read into the cores and that a " 1 " has been written into bi-stable circuits B1 or B2 and that during a write operation V1 has been set to the " 1 " state whereas the digit to be written in the core S<SP>1</SP>1 or S<SP>1</SP>2 is a " 0." These errors cannot be corrected but by employing a further bi-stable circuit W1, AND circuits DB11 and DB12 are blocked and the information written in the cores S<SP>1</SP>1, S<SP>1</SP>2 cannot be passed to the output register RES. Fig. 6 (not shown), indicates how a writing and re-writing circuit may be used with the store.