Patent GB-1507284-A (GB)
Title: Microprogrammed data processing apparatus
IPC: G06F9/22
Filed: 1976-09-28
Abstract: 1507284 Data processing systems INTERNATIONAL BUSINESS MACHINES CORP 28 Sept 1976 [23 Oct 1975] 40114/76 Heading G4A A processor 8, Fig. 1, gains access to user program data and macroinstructions (L type information) and microprograms (C type information) in respective backing stores 2, 4 via a high speed buffer 6 which is shared by both types of information, data being paged between buffer 6 and both of stores 2, 4 using a common control system. Allocation of space in buffer 6 to the two types of data may be controlled by user program- or microprogram-loaded limit registers 16, 18 so that the L and C type data areas are entirely separate, partially overlapping or fully overlapping. The amount of buffer storage space allocated to each type may be based on the ratio of access rate to HIT probability. In the embodiment described, the organisation of buffer 6 as 4-way associative, the buffer being divided into four columns of 64 partitions, there being four lines per partition. A processor address register 24 contains fields 24a-24e, Fig. 2, specifying the type of data required (L or C) and its logical address. The partition part of the address is used to access a corresponding line of a directory array 10 which, like the buffer, is divided into four columns, and which stores the L/C bit and block address for the data stored in a corresponding location (partition and column) of buffer 6. The requested block address and L/C bit are compared at 20 with the four block addresses and L/C bits from array 10. If the requested block of the required type is present in buffer 6, comparer 20 and coder 30 provide the appropriate column address field for combination with the request partition and line address fields 24c, 24d to access the buffer, the required byte(s) being selected by field 24e from the buffer data register 29. A HIT (= 1) signal from comparer 20 causes updating of a replacement array 12 which is organized in four columns of 64 partitions, each partition storing the corresponding buffer column numbers in order (left to right) of replacement priority as determined by a FIFO or LRU algorithm. If the requested block of the required type is not held in buffer 6, a MISS ( = O) signal from compare 20 initiates a page replacement, though this need not involve transfer out from buffer 6 since microprogram is not generally altered while in buffer 6 and user information need only be returned to backing store 2 when the associated validity and change bits dictate it. As selected by the L/C bit of the requested data, a counter 52 determines the number of columns assigned to L and C data in the selected partition of array 10 and this count is compared at 56 with the corresponding limit number of columns from the appropriate register 16 or 18. If the allotted quota for that partition has not been exhausted, the column indicated for replacement by array 12 is selected via gates 36, 62, 64. If the allotted quota has been used up, the replacement column is selected by circuits 40, 42. Decoder/selector 40 routes each L/C bit from the selected partition of array 10 to that one of its four outputs designated by a corresponding column number by array 12, e.g. if column 12a designates column 2, the L/C bit from column 2 of array 10 is gated to the left hand output of circuit 40. Priority circuit 42 combines the signals from circuit 40 indicating which columns of the selected buffer store L data and C data respectively with the L/C requests bit 24a and selects the left-most column storing the appropriate type of data via gates 60, 64.