Patent GB-1029572-A (GB)
Title: Selective lockout of computer memory
IPC: G06F12/14
Filed: 1963-06-11
Abstract: 1,029,572. Digital computers. SPERRY RAND CORPORATION. June 11, 1963 [June 22, 1962], No. 23197/63. Heading G4A. A computer having a variable memory is provided with means whereby a part of the memory can be " locked-out " i.e. if an attempt is made to write fresh information into the locked-out part, this cannot be done and an alarm or interrupt operation takes place. The particular part locked out can be varied by the computer programme. A safeguard is thus provided if a part of a computer memory is to be employed for table look-up data or for storing a subroutine which should not be altered. The computer may be as generally described in Specification 1,029,571. Instruction word format.-The computer described employs 36-bit instruction words as follows: designator: f j a b h i u bit orders:35-30 29-26 25-22 21-18 17 16 15-00 where the f bits are an operation code, the j bits can also be part of the operation code, the u bits are an operand or the memory address of an operand, and the b bits denote an index register for modifying the u bits when they represent a memory address. The a, h and i bits are irrelevant to the invention. General arrangement.-The computer described comprises an arithmetic section 10, inputoutput section 12, memory 13, control section 18, control memory 15, instruction register 28, programme counter 40, storage address register 26, memory transfer register 22, various other registers, and a section 72 concerned with the memory lock-out arrangement. The section 72 includes a memory lock-out (MLO) register 74 which can store data representing a part of the memory which is not to be altered. The memory 13 is preferably a magnetic core array capable of storing 65,536 36-bit words; alternatively the memory could comprise magnetic drums or discs, or electrostatic storage. Operation.-Fig. 2 shows the steps performed during the execution of a programme. An instruction word obtained from the memory 13 is transferred to the instruction register 28 (44, Fig. 2) and decoded at 14 (46, Fig. 2). If the instruction is a " memory lock-out " instruction, the computer control section 18 is effective to transfer the u portion of the instruction to the MLO register 74 to represent a lower and an upper limit of blocks of 2,048 addresses, the blocks within the limits corresponding to memory locations whose contents are permitted to be altered, and the blocks outside the limits forming a zone corresponding to memory locations which are not to be altered (50, Fig. 2). the next instruction is then called for (52, Fig. 2). Assuming that the next instruction is not a memory lock-out instruction, but calls for an alteration in the memory, its address is compared in a comparator 76 with the limits of the established locked-out zone (60, Fig. 2). Assuming that the address is not within the zone, a signal is produced at 84 to permit the memory to be addressed (64, Fig. 2) and the operation called for by the instruction is performed. However, if the instruction requires an alteration within the prohibited zone, no signal is produced at 84, but an alarm is signalled or a programme interrupt initiated (70, Fig. 2) to initiate corrective action by the computer. Circuit elements.-The comparator 76, MLO register 74 and part of the control section 18 are described in detail in the Specification. These circuits comprise NOR gates and flip-flops employing transistors.