baber/WOPTO huggingface dataset:
Patent JP-H01142792-A (JP)
Title: Electronic equipment
Inventor: IKUTO YOSHIICHI
IPC: G09G5/32
Filed: 1987-11-30
Abstract: PURPOSE: To easily superimpose information with a simple constitution by providing a display device main body with a storage means which is arranged so as to face a display means and where information can be stored and erased, a storage means moving means, and a read means. CONSTITUTION: Pictures, characters, or the like to be additionally written are plotted on the screen of a monitor part 8 of a display device main body 9. When a command to start an image scanner device 10 is inputted from a keyboard 2 there-after, a signal is inputted to a controller 19. The controller 19 issues commands to operate a screen take-up control part 15 and an image sensor control part 17. At this time, the screen is taken up in the direction or an arrow A. A sensor 14 reads pictures, characters, or the like on the screen. Data read by the sensor 14 is inputted to the main body 5 through a data transmission circuit 18. In this constitution, picture data read by the sensor 14 is always placed in absolute coordinates on the monitor part 8, and therefore, information is easily superimposed.
Patent JP-H11208962-A (JP)
Title: Image recording device
Inventor: KATO YASUYUKI
IPC: B65H29/58
Filed: 1998-10-23
Abstract: PROBLEM TO BE SOLVED: To provide a reversing part for reversing recording paper for double- side recording, in such a way as not to make a device large-sized. SOLUTION: A pair of reverse rollers 14 are disposed above the rear part of a paper feeding cassette 3, and a retreat path A15 for recording paper 2 to retreat is formed at the rear part of the paper feeding cassette 3. The recording paper 2 having passed a pair of reverse rollers 14 enters this retreat path A15. A retreat path B16 is formed at the lower part of the paper feeding cassette 3, and the recording paper 2 enters the retreat path B16 from the retreat path A15.
Patent JP-H09148442-A (JP)
Title: Method for designing integrated circuit
Inventor: KIMURA KAZUNARI
IPC: H01L21/82
Filed: 1995-11-21
Abstract: PROBLEM TO BE SOLVED: To provide a designing method by which a multilayered wiring structure which has a small chip size and in which timing delay hardly occurs can be obtained. SOLUTION: In a method for designing an integrated circuit having a polysilicon layer and a plurality of aluminum layers as wiring layers, signal terminals 124', 126', 127', 129', 131', 133', and 135' are arranged in the polysilicon layer and other signal terminals 125, 128, 130, 132, and 134 are arranged in some of the aluminum layers. Then a signal line 171 to which the delay of signal transmitting timing does not become an issue is selected and wires in the polysilicon layer and signal lines to which the delay becomes an issue are wired in some of the aluminum layers.
Patent JP-H08137286-A (JP)
Title: Image forming method and device therefor
Inventor: ONO TSUYOSHI
IPC: G03G15/10
Filed: 1994-11-11
Abstract: PURPOSE: To provide an image forming method capable of forming cleaning patterns for consuming the toner sticking on a developing tray of the wet type developing in the electrophotographic method. CONSTITUTION: In the image forming method that the image is formed by sticking the toner in the developer L to the latent image formed on the photosensitive material 3 by electrifying and exposing, the cleaning patterns 24 and 25 are formed by developing for consuming the excessive toner sticking on the developing tray at either the preceding stage of the image output beginning part 23A or the post stage of output completing part 23B, or at the both stages. As a result, the developing tray is held in a clean state without sticking the toner and the quality of the image formed can be maintained high.
Patent JP-2000133790-A (JP)
Title: Manufacture of semiconductor memory device
Inventor: YOGO YUKIAKI
IPC: H01L21/8247
Filed: 1998-10-23
Abstract: PROBLEM TO BE SOLVED: To simplify manufacturing steps by eliminating the contact hole forming step, which is separately needed for making contact with select transistors. SOLUTION: Polysilicon 7 comprises a gate 7c of a peripheral transistor 50 and an electrode layer 7b of the second layer are formed on a gate oxide film 6 of the peripheral transistor 50 and an insulating film 5 of a select gate transistor 40. Then after placing a resist 27 on the polysilicon 7, the gate 7c and the gate oxide film 6 of the peripheral transistor 50 are patterned by using the resist 27 as a mask, and the electrode layer 7b of the second layer and the insulating film 5 are removed to form a contact hole 12. In this way, the step for patterning the gate 7c of the peripheral transistor 50 and a step for forming the contact hole 12 in the select gate transistor 40 can be performed concurrently, and the manufacturing operation can be simplified.
Patent JP-H07160662-A (JP)
Title: Method for calculating reliability in predicted result of neural network
Inventor: YAMAMOTO SHUICHI
IPC: G06F15/18
Filed: 1993-12-02
Abstract: PURPOSE:To provide a measure capable of judging the validity of a result predicted by a neural network even by a novice by calculating final reliability from the allowable range of learning data which is the result of inference and retrieval. CONSTITUTION:Prediction data of a data base 4 are inputted to a neuro simulator 3, prediction is performed in the neuro simulator 3 and a predicted result 7 is outputted. Then, the allowable ranges of learning data output items required for a reliability calculation processing and distance definition, interference relation and weighting which are information required for an example base inference are inputted from a keyword display 8. Then, based on the predicted result 7, in an example base inference part 5, example data closest to the prediction data 7 are inferred and retrieved from the data base 1 and an inferred result 9 is outputted. Finally, the reliability to the predicted result 7 of the neural network is calculated in a reliability calculation means 6 based on predicted result 7 and the inferred result 9 and the result 10 is outputted.
Patent JP-H05144409-A (JP)
Title: Photoelectric surface and photomultiplier
Inventor: OISHI KEIICHI
IPC: H01J40/06
Filed: 1991-11-19
Abstract: PURPOSE:To lessen the dark current in a photomultiplier including a photoelectric surface, a multiplier for multiplying the photoelectrons emitted therefrom, and an anode electrode for collecting electrons, by providing a substrate thereof with a photoelectron emission material containing kalium, cesium, rubidium, and antimony on the surface of the substrate, and further adding rubidium thereto. CONSTITUTION:A manganese oxide layer 2 is formed on a substrate 1 made of, for example, glass. On this layer 2, there is provided a waste alkali photoelectric surface, i.e., photoelectron emission material layer 3. This layer 3 is formed, through activation, by superposing a first layer 31 made of antimony upon the layer 2, and superposing a second layer 32 made of kalium, cesium, and rubidium upon the first layer 31. A transmission type photomultiplication layer is prepared in this way. Then, the layer 3 is positioned on an inner surface of a light receiving surface plate 11 of a vacuum vessel 10. Within the vacuum vessel 10, dynodes 12 of plural stages are disposed, and, at the bottom thereof, anodes 13 and an external terminal 14 are provided. When, in this structure, a signal light enters, the photoelectrons from the photoelectric surface are caused to impinge, through the action of an electric field, upon first and second stages, secondary electrons emitted from which are collected by the anodes 13.
Patent JP-H05211162-A (JP)
Title: Manufacturing method of semiconductor device
Inventor: TOIDA TAKASHI
IPC: H01L21/336
Filed: 1992-10-16
Abstract: PURPOSE:To enhance the controllability of the length size of a low concentration region by a method wherein a gate oxide film and a gate electrode are formed to provide a vapor deposited film on the whole surface and after leading-in impurities to form a high concentration region, an aperture part is formed on the gate electrode sidewall and then impurities are led-in again to form a low concentration region. CONSTITUTION:A gate oxide film 13 and a gate electrode 15 are formed on a semiconductor substrate 11 and then a vapor deposited film 17 is formed by chemical vapor depositing method on the whole surface in pressure-reduced atmosphere. Next, impurities in inverse conductivity to that of the semiconductor substrate 11 are led-in by ion-implanting method to form a high concentration region 19. Next, an aperture part 23 can be formed by etching away the vapor deposited, film 17 using no etching mask at all due to the higher etching rate of the sidewall part than that of the plane part. Later, a low cencentration region 21 is formed by leading-in said impurities again by ion-implanting method. Through these procedures, the stable LDD structure can be formed without fluctuating the characteristics thereof at all.
Patent JP-H01144262-A (JP)
Title: Disk player
Inventor: FUNAHASHI TADASHI
IPC: G11B17/028
Filed: 1987-11-30
Abstract: PURPOSE:To contrive miniaturization and low cost by utilizing the rotation of a turntable and driving a centering means disposed to the opposite side to the turntable accordingly. CONSTITUTION:A disk 1 is centered by the 1st centering means 4 at the time of reproducing its surface on the side of the turntable 2. On the other hand, at the time of reproducing its surface on the opposite side to the turntable 2, the centering is performed by the 2nd centering means 12. Then, the 2nd centering means 12 is driven by utilizing the rotation of the turntable 2 as a driving means. Consequently, the need of a particular driving source for driving the 2nd centering means 12 is eliminated. By this method, the miniaturization and cost reduction are hence feasible.
Patent JP-H05144281-A (JP)
Title: Semiconductor integrated circuit device
Inventor: MIYATA TOMONOBU
IPC: G11C17/00
Filed: 1991-11-19
Abstract: PURPOSE:To suppress through current and to reduce power consumption by preventing concurrent turn ON of PMOS and NMOS transistors in a switching control circuit when a second power supply voltage exceeds a first power supply voltage. CONSTITUTION:When a second power supply voltage Vpp exceeds a first power supply voltage Vcc, a comparing circuit section l turns an NMOS transistor T2 in a switching control circuit 3 OFF. After turn OFF of the transistor T2, a timing control circuit section 4 turns a PMOS transistor T1 ON. Consequently, drain of the transistor T1 has an H level which is then delivered to a power supply switching circuit section 2, and the switching control circuit section 3 outputs the second power supply voltage Vpp based on the H level. Consequently, concurrent turn ON of the PMOS and NMOS transistors T1, T2 in the switching control circuit section 3 can be prevented when the second power supply voltage Vpp exceeds the first power supply voltage Vcc.
Patent JP-H01147208-A (JP)
Title: Secondary air pipe for gas burner
Inventor: FURUHASHI TOSHIO
IPC: F23D14/02
Filed: 1987-12-01
Abstract: PURPOSE:To make small the generated calorific value per unit area of a flame opening plate when a specified calorific value is desired, by providing a specified auxiliary pipe part along the upper edge of a secondary air pipe and projecting this auxiliary pipe part above the flame opening plate from a insertion slit. CONSTITUTION:An auxiliary pipe part 161 is formed as one body along the upper edge of a secondary air pipe 16. Said auxiliary pipe part 16 is more flat and with a narrower width than the secondary air pipe 16, and in the state of being snatched by a snatching plate 131 and gap 132, its upper section is projected from the gap 132. With this arrangement, the area of the secondary air pipe which occupies exclusively the upper side of the flame opening plate becomes narrow so that the area of the flame opening part can be made large and the calorific value generated per unit area of the flame opening plate can be made smaller than in the conventional devices for obtaining a specified calorific value.
Patent JP-H08158575-A (JP)
Title: Non-slip material
Inventor: IKEDA YOSHIO
IPC: E04F11/17
Filed: 1994-12-07
Abstract: PURPOSE: To provide a non-slip material which is used as an ordinary non-slip material at 0 deg.C or higher temperature and by which cracks are induced on an ice layer face in a state that an ice layer is laminated at 0 deg.C or lower temperature and the ice layer can be easily removed. CONSTITUTION: A non-slip material 1A is composed of a horizontal part 1 and a slant part 1'. The horizontal part 1 is made of a flat flexible rubber base material 2 and grooves 3 with a specified depth are formed on the surface to shape a specified pattern. Rubber protrusions 5 which become rigid at a low temperature, are provided in the nearly middle part of the spaces partitioned by the grooves 3. And dents corresponding thereto, made in the rear face of base material, are formed at the rear faces of the spaces.
Patent JP-H04173840-A (JP)
Title: Composite thermoplastic-resin material with high strength
Inventor: RETSUKUSU REO BOBUSEIN
IPC: C08J5/04
Filed: 1990-11-08
Abstract: PURPOSE: To provide a thermoplastic resin composite material that is highly strong, has an improved adhesiveness between the resin matrix and carbon fiber, and is useful for minute ion sensors, by combining carbon fiber, a poly(arylene sulfide) and another resin component.  
     CONSTITUTION: The desired material comprises (A) carbon fiber, (B) an amine- terminated poly(arylene sulfide) as a resin component, and (C) a second resin component comprising a poly(arylene sulfide), polyolefin, polysulfone, polyethersulfone, polyetherimide, polytherketone, polyetheretherketone, polyetherketoneketone, liquid crystal polymer, or a mixture of these resins, and is reinforced by the component A. The component A is preferably present in an amount of about 10-80% based on the amount of the whole resins in the material. 
     COPYRIGHT: (C)1992,JPO
Patent JP-H03166494-A (JP)
Title: Multiple connected underground excavator
Inventor: KASHIMA YUTAKA
IPC: E21D9/08
Filed: 1989-11-22
Abstract: PURPOSE:To construct variously shaped tunnels by disposing a plurality of excavating tools rotated by parallel link mechanisms on multiple connected sections having optional forms in such a manner that they are not collided to each other, and drilling a working face by these tools to excavate in the ground. CONSTITUTION:A hood 3 is formed in the front of a shield cylinder 2 having a cocoon sectional form, and the front is partitioned by a bulkhead 4. This is disposed by fours, and a support shaft 8 is passed in the position displaced from the center of a short cylindrical rotating body 5 rotatably supported by a bearing 6. An adding material injection hole 11 is bored in the inner part thereof and connected to one end of an injection pipe 13, and the other end is connected to a swivel joint 14. Two excavating tools 20 are synchronously controlled so that they can be synchronously operated as an identical plane, and a plurality of rotating bodies 5 are also synchronously controlled and synchronously operated to transmit the motion to the excavating tools 20. Hence, multiple connected tunnels of every form can be constructed.
Patent JP-H05122207-A (JP)
Title: N-stage jitter absorbing circuit
Inventor: FUKUZAWA SHIGEKAZU
IPC: H04L7/027
Filed: 1991-10-24
Abstract: PURPOSE:To eliminate the occurrence of an error by selecting the Q of a tank circuit to be higher as a circuit receiving an output of a flip-flop as an input is connected by n-stages so as to absorb jitter of a signal of a transmission line. CONSTITUTION:n-Stages of circuits each comprising flip-flops F1-Fn receiving a signal including jitter on a transmission line and outputting an NRZ signal, tank circuits T1-Tn receiving the signal on the transmission line to extract a clock and outputting their outputs to the flip-flops and a circuit receiving an output of the flip-flops F1-Fn are connected in cascade. However, the Q1 of the 1st stage tank circuit is selected to segment the expected input jitter without mistake, the Q2 of the 2nd stage tank circuit is selected to be higher than the Q1 so as to segment an output of the flip-flop of the pre-stage without any error. Thin the Qn of the n-th stage flip-flop is selected so as to have no high frequency jitter at its output. Thus, the jitter of the signal on the transmission line is absorbed by using the n-stage jitter absorbing circuits.
Patent JP-H03162305-A (JP)
Title: Conveyer
Inventor: MINAZU KIYOAKI
IPC: B65G21/14
Filed: 1989-11-22
Abstract: PURPOSE:To facilitate work by freely expanding and contracting the transport travel of an endless conveyer, supporting one end portion of the conveyer on a moving truck in such a manner as to freely change an angle of elevation, and controlling the expansion and contraction of the transport travel or the change of an angle of elevation, taking the height of the forward end portion and the fore and aft position as the reference. CONSTITUTION:In changing the transport height position, a longitudinal level switch is operated to control the rotation of a cylinder motor 26, whereby a belt roller 10 is moved along a line (i) in the direction of height by a designated amount. Simultaneously, an expansion and contraction driving motor 19 is controlled and rotated to control the position of the belt roller 12 for expansion and contraction, whereby the position of the belt roller 10 only in the direction of height is changed. The fore and aft position of the belt roller is changed by moving the belt roller 10 along a line (ii) by the expansion and contraction driving motor 19 and controlling the belt roller 12 not to be changed in height by the cylinder motor 26. By this arrangement, the transport leading end portion can be always positioned near a worker.
Patent JP-H03163821-A (JP)
Title: Manufacture of semiconductor device
Inventor: OKAMOTO TETSUMASA
IPC: H01L21/225
Filed: 1989-11-21
Abstract: PURPOSE:To simplify process, realize high yield and throughput, and reduce cost, by a method wherein an impurity diffusion layer is formd on the inner wall surface of a groove by forming an organic compound layer containing impurities in the groove formed in a substrate, and heat-treating said layer. CONSTITUTION:Organic compound solution containing several % boric acid, e.g. polyboron film (PBF) is used. Said solution is spread by low speed rotation, and the inside of a groove is filled with a PBF layer 4. By annealing the layer in an oxygen atmosphere at a temperature higher than or equal to 500 deg.C, organic polymer in the film is decomposed into carbon dioxide and water, and a boron oxide film 4A is formed on the inner wall surfaces of grooves 3A, 3B. By heat treatment in a nitrogen atmosphere at 800-1000 deg.C, boron is diffused, then a glass layer is eliminated, and a uniform boron diffusion layer 5 which has a specified resistance value and is free from damage is formed on the inner wall surfaces of the grooves 3A, 3B. Thereby a uniform impurity diffusion layer free from damage can easily be formed on the inside of a groove having a complicated shape, so that the high yield and the high throughput of a semiconductor device are realized and the cost can be reduced.
Patent JP-H0873811-A (JP)
Title: Precoated steel plate and its production
Inventor: AOKI SUSUMU
IPC: C09D201/02
Filed: 1994-11-15
Abstract: PURPOSE: To obtain a precoated steel plate having excellent weather resistance and stain resistance, by forming film coating layers on a steel plate such as a molten galvanized steel plate with an undercoating coating compound, option ally a middle coating compound and a topcoating coating compound having a specific composition. CONSTITUTION: A steel plate such as a hot-dip galvanized steel plate, a cold rolled steel plate or an electric galvanized steel plate is provided with an undercoating film layer by an undercoating coating compound, optionally a middle coating film layer by a coating compound of middle coating and a topcoating layer by a topcoating compound composed of one or more compositions comprising (A) a compound containing two or more functional groups of the formula (R<1> to R<3> are each H or a 1-18C organic group; R<4> is a 1-18C organic group;  Y<1> is O atom or S atom) in one molecule, (B) a compound (e.g. bisphenol type epoxy resin) containing two or more reactive functional groups (epoxy, oxazoline, silanol, amino, etc.) to be chemically bonded to the functional group of the component A by heating in one molecule and optionally (C) one or more compositions comprising a heat latent acid catalyst as essential components to give the objective steel plate.
Patent JP-H10189552-A (JP)
Title: Terminal detecting method and device of plasma processing
Inventor: KOSHIMIZU CHIEN
IPC: H01L21/3065
Filed: 1997-11-06
Abstract: PROBLEM TO BE SOLVED: To make it possible to detect the precise terminal regardless of the fluctuation in the plasma state by a method wherein the light emission intensity of the first and second active species is detected to find out the quasi approximate relational expressions of the first active species as well as the ratios and the differential values of both species from these expressions. SOLUTION: Assuming ordinate and abscissa respectively to be the light emission intensity and time, respective experimental expressions are found out by the method for least squares using the first and second wave forms 1, 2 of the light emission intensities within the mean times. Next, the quasi approximate linear relational expression A' of the first active species is found out from the approximate linear relational expression A of the first active species and the approximate linear relational expression of the second active species. Furthermore, the differential value d (A/A')/dt of the ratio A/A' is detected. The waveforms for A/A' are respectively stabilized in a specific forms before and after terminals. Finally, the terminals can be decided precisely by detecting the starting of change (slope start: S.S) and the ending of change (slope end: S.E) without fail.
Patent JP-H01150012-A (JP)
Title: Torque transmission shaft
Inventor: SAITO SHINOBU
IPC: F16C3/02
Filed: 1987-12-03
Abstract: PURPOSE:To increase the rigidity of a shaft without increasing the diameter thereof so as to reduce its weight by winding a fibrous material having a large modulus of longitudinal elasticity around a metal shaft core having flanges, and sintering it in the form of a structure integrated with the shaft core. CONSTITUTION:Flanges 1 are provided on a thin shaft core 2, while a fiber 3 having a large modulus of longitudinal elasticity is wound around the shaft core 2 in order to form a plurality of layers to a specified outer diameter D, and then the whole layers are sintered thereto so that the whole of them are integrally formed. It is therefore possible to increased rigidity without increasing a shaft diameter, so as to increase a peculiar torsional oscillation number of the shaft system to the extent that there is no interference with the response speed of a control system, and to reduce its weight.
Patent JP-H11219676-A (JP)
Title: Radiation image tube and its manufacture
Inventor: NOJI TAKASHI
IPC: C22C21/00
Filed: 1998-10-26
Abstract: PROBLEM TO BE SOLVED: To provide a radiation image tube which involves less risk of deformation of an input substrate such as twisting, excels in the resolution owing to less aberration over the whole region of an output image, and ensures a high uniformity of brightness and the contrast characteristic. SOLUTION: A radiation image tube 1a includes an input window 10 formed on one side face of a vacuum vessel 2a and allowing the given radiations to be incident into the vessel 2a, an input screen 5 which converts the incident radiations into a fluorescent image or photo-electron image, and an input substrate 4a which holds the input screen 5. The input substrate 4a consists of a clad material 13 formed by consolidating an aluminum alloy material 11 on the incident side of radiations with a pure aluminum material 12 on the side with the input screen 5.