Patent GB-1381885-A (GB)
Title: Data processing unit
IPC: G06F9/48
Filed: 1972-01-05
Abstract: 1381885 Microprgrammed data processors KOMBINAT ROBOTRON VEB 5 Jan 1972 497/72 Heading G4A In a processing unit having a plurality of digit and word address registers loadable from a microinstruction register, a program is interruptable during execution of one of its instructions by a microprogram, provided that the next microinstruction and a program settable lock are such as to allow interruption, and an interruption microprogram is then executed. System hardware.-A main store KSP, e.g. core memory with 1024 words each of 16 4-bit digits holds data and instructions which may be stored as three 5-digit instructions in each word. Words 0-15 of KSP are designated as special registers, e.g. accumulator AC, instruction register BR, instruction counter, and are addressed by register ARW1 (or by 12-bit word address register ARW2). A pair of 4-bit digit address registers ARS1, ARS2 address one of the 16 digits in the addressed word. The selection of registers ARS1, ARS2, ARW1 and ARW2 is determined by the values of bits BB13 and BB14 of the microinstructions supplied from (read only) store FWSP. The arithmetic unit RW has operand registers RR1, RR2 and a control register SR. Channels K1-K4 are respectively provided for communication with a keyboard, printer, card/tape punch/reader or magnetic tape unit, and one or more additional stores, e.g. core, read-only or magnetic disc. Interrupt.-Operation of any key of the keyboard sets a bi-stable Ual in channel K1 and bi-stable Ua2 in channel K2 is set when the printer is ready for a new character. An interrupt request is only granted when an interrupt condition UM is present (bit 17 of a microinstruction) and a program lock bi-stable KU has been reset by the microprogram. There may be priority selection between keyboard and printer interrupts. On acceptance of an interrupt, the contents of microinstruction counter MBZ are transferred to register US and a fixed address is loaded into MBZ for the start of an interrupt microprogram which enters data from keyboard into main store register ER or data for printer into channel buffers DP1, DP2. The last microinstruction of the interruption program transfers the contents of US back to MBZ to resume the interrupted microprogram. Microprogram.-The following types of microinstruction are used. (1) Transfer from a specified register (including memory address registers and I/O registers) to main register HR. (2) Transfer from main register HR to specified register (with destination ARW2 this may indude a 4-bit shift). (3) Read main store KSP (with and without re-write) into HR. (4) Write HR into KSP. Types (3) and (4) may include incrementing or decrementing of the address registers and the contents of HR. (5) Set selected address register with data in corresponding 4-bit group in microinstruction. (6) Set main register HR according to 4-bit 0 and 1 masks in microinstruction. (7) Set and reset various control bi-stables and interrupt condition bi-stable KU. (8) Jump (conditional or unconditional). The microprogram is arranged to increment the lowest digit of the instruction counter BR, and for every three instructions executed, the higher digits of BR are incremented to address a new machine word in KSP. For each instruction ARW1 and ARS1 are loaded to address the OP code digit of the instruction in the instruction register for bit by bit decoding by the microprogram. The control register SR is set according to the OP code and (bit DU) according to whether the operation is to be binary or decimal. AWR2 is set to the operand address and AWR1 to word 0, i.e. the accumulator AC. The OP bit of SR is complemented (i.e. add/ subtract) each time the sign of the operand and accumulator contents is found to be positive so as to produce a result SU with the correct sign, the operand and AC contents being transferred to RR1 and RR2 a digit at a time.