Patent GB-1147199-A (GB)
Title: Improvements in or relating to time division multiplex communication systems
Inventor: TSCHANNEN GOTTFRIED
IPC: H04L5/22
Filed: 1966-12-08
Abstract: 1,147,199. Multiplex pulse code signalling. ALBISWERK ZURICH A.G. 8 Dec., 1966, No. 54957/66. Heading H4L. A time division multiplex communication system in which a synchronizing signal is transmitted with each frame comprises means at a receiver for storing a plurality of said synchronizing signals, means for comparing the stored signals with a predetermined sequence of signals, and means for effecting a phase shift if loss of synchronism is detected. As described for a frame of 14 channels, of which numbers 1 to 13 are available as information channels, and number 14 carries synchronizing signals which alternate from mark to space in successive frames, incoming pulse coded signals at a terminal E pass via an amplifier 1 and a demodulator 2 to a bi-stable input store 3, a side T of which is made conductive by a marking signal and a side Z of which is made conductive by a spacing signal. The frequency of a local oscillator 4 is controlled by a feed from the output of the amplifier 1, and its output is taken to one input of an INHIBIT gate 5 and to one input of an AND gate 25. The other inputs of the gates 5, 25 are connected to the output of a test circuit 21. The output of the gate 5 operates a channel switching arrangement 6 and normally causes repeated progressive stepping from channel 1 to 14. The outputs from the store 3 are paralleled through AND gates (such as 7, 8, for channel 1) to the information channels, and signals are made available at the output terminals K1 to K13 via bi-stable stores and amplifiers (such as 9, 10 for channel 1). The 14th outlet of the channel switching arrangement is connected to the inputs of all four stages of a shift register 11 and output from the store 3 is also connected to the input of its first stage. Consequently, synchronizing signals progress steadily through the shift register 11 as they are received, and four consecutive signals from the sequence . . . ZTZTZT . . . are normally received. In this case, the test circuit 21, which comprises an interconnected arrangement of gates fed from the outputs of the various stages of the shift register 11, gives no output, and the gate 5 remains open and the gate 25 is blocked. If a combination of stored synchronizing signals in the register 11 exhibits only one error, there is still no output from the test circuit 21. For example, with TTZT, the AND gate 214 of the circuit 11 is opened and supplies one input to the AND gate 211. There is, however, no output from either of the AND gates 216, 217, to the other input of the gate 211, and it remains blocked. If a stored combination exhibits two errors, for example ZTTZ, then there is output from the circuit 21. In this case, the AND gates 213 and 217 are open and their outputs through the OR gates 212, 215 open the AND gate 211, output from which blocks the INHIBIT gate 5 and sets the AND gate 25. The next timing pulse from the oscillator 5 is diverted from the switching arrangement 6, resulting in a slip in the stepping, and is applied via the gate 25 to one input of the AND gates 311, 312 of a distributer network 31, whose other inputs are connected, respectively, to the T and Z outputs of the bi-stable store 9 of channel 1. Depending on the state of the store 9, one of the gates 311. 312 becomes conductive, and its output is fed through OR gates 122 to the Z or T inputs of the stages of the register 11, cross-connections being inserted in the feeds to the 1st, 2nd and 4th stages thereof. If, for example, the AND gate 312 becomes conductive the combination stored in the register will consequently be changed from ZTTZ to TTZT, when the test circuit 21 will no longer give an output, so that the gate 5 opens, the gate 25 is blocked, and normal operation re-commences. The system is stated to be especially applicable to teleprinter circuits.