Patent GB-1111701-A (GB)
Title: Digital code extractor system
IPC: G01S13/78
Filed: 1965-10-21
Abstract: 1,111,701. Pulse radar. SOCI TE NOUVELLE D'ELECTRONIQUE ET DE LA RADIO-INDUSTRIE. 21 Oct., 1965 [5 Nov.. 1964], No. 44673/65. Heading H4D. Multipositional digital code extractor apparatus comprises means responsive to the initial pulse of a code group (or a regenerated code group) to produce a train of memory pulses, each memory pulse occurring at a time corresponding to a predetermined portion of a respective position in the code group, and testing means for comparing the timing of the memory pulse train with the further pulses of the code group (or regenerated code group) whereby only those code pulses which are substantially in time phase with memory pulses are passed from the extractor apparatus. The invention is applied to a secondary radar system wherein an aircraft replies with a response code group consisting of a first framing pulse F1 followed by a pulse group extending over twelve positions affording binary-coded-position information pulses, a thirteenth position which is left blank, the second framing pulse F2 and an optional special identification pulse SPI used by military aircraft, Fig. 14 (not shown); the code extractor apparatus is placed between the radar receiver's video output and known decoding apparatus and is designed to separate response signals received from different aircraft simultaneously scanned by the radar beam: it extracts correctly decodable signals in the presence of various kinds of garbling signals and delivers to the decoder a signal indicating whether, and if so which kind, of garbling is present. Kinds of garbling.-Two code groups are considered to be separately received, i.e. non- garbled, if the leading edge of the F1 pulse of the following group follows by at least 0À25 microseconds the trailing edge of the F2 pulse from the preceding group. When two groups overlap wholly or in part, garbling is present; in one kind of garbling the pulse positions of the respective groups are interspersed but remain separate: the groups are then said to be interleaved, the extractor apparatus discriminating between them and delivering the two groups separately to the decoder and issuing a signal designated GI. When the pulse positions of the groups overlap " phase garbling " is said to be present: the extractor can then extract only the phase-leading group and issues a signal designated GPH. General system description. Fig. 1.-The reply signals at video frequency are led via a gate 11 or 11<SP>1</SP> to two identical channels 1, 1<SP>1</SP> each of which incorporates a pulse-width gauging and regenerator circuit 3, 3<SP>1</SP>, a clock pulse generator 47, a pulse phase and width memory circuit 4, 4<SP>1</SP> and a phase tester 5, 5<SP>1</SP>. Considering channel 1: circuit 3 gauges the leading and trailing edges of each incoming pulse by reference to the clock pulses and derives a leading edge spike (FAV) and a trailing edge spike (FAR) to produce anti-phase regenerated pulse trains for the phase tester; circuit 4 generates trains of spikes (FAVM, FARM) corresponding to predetermined times after the FAV, FAR spikes of the first pulse and produces a signal (FARD) if the subsequent pulse applied to channel 1 is too wide; circuit 5 compares the timing of the leading edges of the regenerated pulses with the memorized leading- edge spikes FAVM and if a substantially inphase situation exists pulses are passed to the shift register section A of logic analyzer LA. A circuit 13 controls gates 11, 11<SP>1</SP> to segregate code groups and operates under the control of . FAR, FAVM and FAVR pulses from circuits 4, 4<SP>1</SP> and of logic situations sensed in analyzer LA which carries out three investigations. Logic analyzer LA, Fig. 1.-The output of phase tester 5 is applied to section A of a digital shift register 6 of which section A has fifteen stages-positions 1A to 15A-and section B has fourteen stages-positions B1 to B14; the FAVM pulse train is the source of shift pulses. A buffer register (store) is associated with section B and feeds the fully investigated code group to a known decoder. The first investigation, circuit 8, detects " false alarm " pulses, i.e. isolated pulses which have passed phase tester 5 and may be due to, e.g. curtailed code groups ; if one, or closely consecutive false alarm pulses are detected, the circuit generates a " forget initial pulse " command which arrests the operation of memory circuit 4 and clears the channel for the entry of subsequent pulses. The second investigation, circuit 9, searches for code pulses in registers 6<SP>1</SP> of channel 1<SP>1</SP> for possible interleaving or phase garbling and checks the situation ahead of the code group being investigated to detect the occurrence of simultaneous pulses in positions 15A and B14 at any time during the progress of the investigated code group from register 6A to register 6B; circuit 9 is responsive also to the earlier detection of false alarm pulses as well as the presence of a FARD pulse from circuit 4: from the combined information a phase-garbled situation decision involving an earlier-received code group may be made. The third investigation, circuit 10, is made on a code group during the time it is moving out of register 6B (after having first been transferred into store 7); the circuit " looks " for the occurrence of coincidences in positions 1A, 15A and 15A, B14 during that time and assesses the possibility of a phasegarbled situation involving a code group received after the one being investigated.