Patent GB-1431438-A (GB)
Title: Pattern recognition systems and apparatus
IPC: G06V30/10
Filed: 1972-09-11
Abstract: 1431438 Pattern recognition systems NATIONAL RESEARCH DEVELOPMENT CORP 7 Dec 1973 [11 Sept 1972] 42111/72 Heading G4R Signals representing a matrix of elementary areas of a scanned field containing a character are examined to detect features of the character by use of n-tuple operators. At least one of the operators inspects a number of regions, each of which typically comprise a number of elementary areas, the regions being approximately symmetrically disposed in a circle about a central region, which must itself detect a portion of the character in order for the results of the inspection of the other regions to be effective. Two or more concentric arrays of regions may be involved. The operator may be as indicated in Fig. 9, and is shown inspecting a 3-branch portion of a character. Each outer region is assigned a bitstate which depends upon the result of an associated n-tuple. Thus, for example, Fig. 10 illustrates the 8-tuple which is used for region 1, and (when rotated through the appropriate angle) for regions 4, 7, and 10. Other n-tuples (Fig. 11 and 12, not shown) are employed similarly for regions 2 and 3 and, when rotated, for the other regions. Fig. 10 represents a 7 x 5 array of cells positioned so that # lies at the centre point of the array of regions. The 8- tuple detector for region 1 is designed to detect the presence of a vertical vector at V and of a vertical or diagonal vector at *. The vectors in respective cells are determined by prior circuitry involving n-tuples as described below. The vectors are weighted and summed, and if the sum is large enough the region 1 is set to bitstate 1. A further n-tuple (Fig. 13, not shown) is used to determine the bit-state of the central region B. Provided that the state of region B is 1, i.e. it is over a portion of the character as in the example illustrated, the states of regions 1- 12 are read out as a 12-bit word for recognition purposes. The word may be passed to logic circuitry (Figs. 18 or 19, not shown) which by counting the number of 1-0 and 0-1 transitions, the number of adjacent 1-bits, &c., can determine the number of limbs of the character portion currently being inspected, and can also determine the number of limbs having a particular width and the direction of each limb. The signals derived from the 12-bit words may be used to indicate ends of lines, and lines which converge or diverge, for example. This information may be associated with other information in the form of code lists derived as described in Specification 1,280,155 and used to determine the identity of the character by comparing the lists to lists representing reference characters, as described in that Specification. The vectors referred to above are derived from circuitry similar to that described in Specification 1,280,155, in which the character field is scanned by a vertical raster, and the resulting signals are shaped and quantized to 4-bit signals by analog-digital converter ADC, Fig. 8. The converter feeds a continuously stepping shift register LSR which stores the 4-bit signals pertinent to 6 vertical scan lines. Register LSR is connected to 7 shift registers SRC 1-7, having 7 stages of 4 bits each, such that these registers contain signals representing the states of a 7 x 7 array or window of elementary areas of the field. As the registers are stepped the window moves over the field. The signals in registers SRC1-SRC7 are converted to analog form by converters DAC1-DAC7, A patchboard (not shown) connects certain of the converters to combining units F1, F2, the patchboard being set up to define various n-tuples (Figs. 2-4, not shown) for detecting horizontal, vertical and diagonal segments of the character. The outputs R1-R4 of the combining units indicate, for each position of the window, which one or ones of these segments are present. The outputs R1-R4 are further processed, as disclosed in 1,280,155, to take account of contrast &c., and the resulting segment signals R1<SP>1</SP>-R4<SP>1</SP> pass to 4 respective register LSR (one shown). Each register, stepped continuously, stores the respective segment signals for 12 vertical scan lines and feeds 13 13-stage registers FSR1-FSR13 so that each such group of 13 registers contains signals representing the presence of absence of the corresponding one of the segment signals R1<SP>1</SP>-R4<SP>1</SP> at each point in a 13 x 13 window moving over the character. A patchboard (not shown) set up to define ntuples (Figs. 5-7, not shown) connects the registers to combining units Z1-Zn which detect segment ends, crossed segments, &c. The outputs of Z1-Zn are used to provide code lists as referred to in Specification 1,280,155 for recognition purposes. In one arrangement of the present invention the vectors referred to above are the segment signals R1<SP>1</SP>-R4<SP>1</SP> appearing at the outputs of each register group FSR1-FSR13 and are selected by a patchboard (not shown) defining the n-tuples, Figs. 10-13, and feeding combining units DSD1-DSD12 for regions 1-12, Fig. 9, and unit DSDB for central region DSDB. In another arrangement the vectors are the segment signals R1<SP>1</SP>-R4<SP>1</SP> at the inputs of registers LSR but in this case the mere presence of such a signal is taken into account, irrespective of its type. Thus, as shown in Fig. 8, in this case the signals are fed to OR gate GDB which feeds 13 scan line register DBSR which is connected to registers DSR1-DSR13 defining a 13 x 13 window. A patchboard connects the registers to the combining units DSD1-DSD12 and DSDB as before. Reference is made to another arrangement in which the vectors are derived directly from the scanner output.