Patent GB-868237-A (GB)
Title: Binary counter circuits
Inventor: ECKERT JOHN PRESPER
IPC: H03K23/76
Filed: 1957-06-27
Abstract: 868,237. Magnetic amplifiers. SPERRY RAND CORPORATION. June 27, 1957, No. 20267/57. Class 40 (9). A circuit comprising one or two magnetic amplifiers of the resetting type is arranged so that sequential application of single input pulses alternately produces and terminates a train of output pulses. Various embodiments are described which utilize complementing and non- complementing amplifiers of both the series and parallel types. In one form it is arranged that a given time must elapse between successive input pulses for the second pulse to be effective in terminating production of output pulses. Arrangements using non - complementing series magnetic amplifiers. The amplifier, Fig. 2, comprises a core C of rectangular hysteresisloop material the magnetization of which is alternated between its two saturation values by a bias potential - V acting over a power winding 22 and a rectifier 26, and by counter-acting power pulses PP which are applied to the same winding over a rectifier 21. Normally no output appears on lead 29 as the power pulses are totally absorbed in reversing the core magnetization, but if a control pulse is applied from a source 27 to a control-winding 26, the resetting effect of tne bias voltage is inhibited. The power winding thus presents a low impedance to the next PP pulse and an output pulse appears on lead 29. A synchronizing circuit S between the power and control pulse sources is provided so that the control pulses are only effective in the intervals between the power pulses. In an application. Fig. 3, the amplifier constitutes the component 35 of a circuit producing output pulses at a terminal 37 in response to input pulses at terminal 30, the number of output pulses being determined by the time interval between a first and second pulse, third and fourth pulse, and so on. The input pulses are applied to the amplifier directly over a gate 31 and also in complementary form by way of an inverter 33 and gate 34. These gates are controlled from the amplifier output by pulses which are applied over a delay line 36 to gate 34 directly and in complementary form over an inverter 32 to gate 31. In operation, no output is obtained at terminal 37 until a single input pulse is received at 30, in which case it passes to amplifier 35 over gate 31 which is opened by absence of output pulses. An output pulse is thus obtained which opens gate 34, and the absence of further input pulses causes inverter 33 to provide control pulses to the amplifier. Emission of output pulses therefore continues until a second input pulse is received. The inverter 33 then terminates its output, and since gate 31 is closed the output pulses at 37 cease. The circuit is shown in detail in Fig. 3B, in which gate 31 comprises rectifiers 31b, 31c which must be biased simultaneously by a position pulse from 30 and a positive potential 32c, for a potential +V at terminal 31e to be applied to the amplifier. The gate 34 is similar, while the inverters 32, 33 comprise biased pulse transformers having half-wave rectifiers in their secondary circuits. In a modification, Fig. 4 (not shown), the inverter 32 is connected in the control circuit of gate 34 and a further inverter precedes the delay line. Alternatively the delay line may precede the amplifier, Fig. 5 (not shown). A further arrangement is shown schematically in Fig. 6B and in detail in Fig. 6. A modified amplifier is used in this arrangement in which positive power pulses from alternating sources 60, 60c are applied alternately to windings 60a, 60d after conversion to unidirectional pulses by a rectifier 60g and a bias source 60f, respectively. The two gates previously described are constituted by rectifiers 63c-63f and 63r together with potential sources 62b, 63a, 63h and 63k. The power pulses from source 60 normally provide no output to a load 60b as the core C is reset in the intermediate time periods by bias potentials 61 and 61c acting in winding 61a, a further winding 66 being inoperative at this stage. When a single input pulse is applied from a signal source 62 during a resetting time period, the flow of current through winding 61a is inhibited and the windings 60a, 60d present a low impedance throughout the next pulse period. An output is thus produced in load 60b, while the zero potential condition established by pulse source 60c in opposition to bias 60f permits a pulse from a potential source 65b to pass over a resistor 65a to the winding 60d. The latter pulse also passes over a delay line 64 to the rectifier gates where it is effective, one pulse period later, in reducing the potential at points 63q and 63p. Current will then flow from source 66b through winding 66 and exactly neutralize the resetting effect of winding 61a, so that transmission of output pulses to the load continues without interruption. When a second input pulse from 62 is applied, the potential at point 63p is raised and current through winding 66 is blocked. The resetting action by winding 61a on the core will then become effective and the emission of output pulses terminate. The absence of negative pulses over the delay line increases the potential at points 63q, 63p, and terminates current flow through winding 66. In a modification, Fig. 7, the core 72 has a single power winding 72a and a centre-tapped winding 71, and the feed-back path 73c has a positive potential applied by sources 74b, 76 before the input signals are applied to lead 70. The upper part of winding 71 effects core resetting while the lower part, when operative, inhibits the resetting action. In operation, a signal pulse acting on the rectifier gates inhibits the resetting current, and subsequent resetting is neutralized by output pulses to a load circuit 72c which charge a feed-back condenser constituting the delay element. When each output pulse terminates, the condenser potential is lowered by a source 75a and current flows from source 74b. In consequence the potential of path 73c is lowered temporarily, and the reduced potential at the upper end of resistor 70h causes current flow through the lower part of winding 71 which inhibits resetting action. Output pulses continue to be produced until a further input pulse is applied. The potential at the upper end of resistor 70h is then raised and current is prevented from passing through the lower part of winding 71. Resetting again becomes effective and the output pulses terminate. Small output currents which occur when winding 72a has a high impedance are isolated from the output circuit by a rectifier 73 and source 75a. In a further modification of Fig. 6, the input pulses are applied at a terminal 80, Fig. 8, in the same time position as the power pulses from source 82b, while delay lines 83, 84 are incorporated in the circuits of the resetting and the resetting-inhibiting windings 82g, 82j so that the input pulse effectively acts in the interval when the pulses from 82b are zero. The circuits may also be arranged so that a predetermined time must elapse between two successive input pulses for the second to be effective in terminating the pulse output. In one arrangement, Fig. 11, the feed-back output from the amplifier 113 by way of delay line 114 is applied both to the amplifier input over a gate 115 and to a long delay line 116. Gate 115 when closed terminates the output pulse train and is operated over an inverter 118 only when the second input pulse and the output from the long delay line are applied simultaneously to a coincidence gate 117. A similar inoperative period occurs after the second pulse as the output from the long delay line, applied over inverter 112, prevents gate 111 from opening. A modified arrangement using additional inverters forms the subject of Fig. 11A (not shown). The Fig. 11 circuit is described in detail with reference to Fig. 12 (not shown), which Figure utilizes the inverters, gates and non-complementing series amplifier previously described. Complementing series amplifier arrangements. As shown in Fig. 9, two magnetic amplifiers 92, 94 of the complementing type are connected in cascade, and are energized by alternating pulse sources having the relative time positions shown in Fig. 9A. Sources 90b and 90e provide blocking pulses in the control circuits which inhibit induction between the power and control windings, the pulses from these sources and from source 90d being rendered unidirectional by bias potentials (not shown). Before an input pulse is applied to terminal 91, amplifier 92 provides a power pulse output over winding 92a to both a load 93 and the control winding 94d of the other amplifier 94, both windings 92b, 92c being operative at this stage. This control of amplifier 94 repeatedly resets the core and prevents the power winding 94a from supplying an output. In consequence lead 97 has the positive potential of source 95 which is applied to rectifier gates 91a-91d. The bias potentials 91e, 91h, 91l and 96 associated with the gates prevent current flow through either the control or resetting windings 92b, 92c of amplifier 92. In operation, the input pulses are applied during those intervals in which the power pulses from 90a are negative. The first input pulse passes through the rectifier gates and by cutting-off rectifier 41a causes source 91e to energize the resetting winding 92b. Amplifier 92 thereby terminates passage of pulses through winding 92a to the load and the other amplifier. As a result power output pulses are provided by amplifier 94 which lower the potential of lead 97. Rectifier 92e then becomes conductive and the pulse source 90c maintains the zero output condition of amplifier 92 by energizing the resetting winding 92c. This condition continues until a further input pulse is applied to terminal 91, in which case rectifier 92e is cut off and the resetting action terminated. The lowered potential on lead 97 prevents the input pulse from establishing rese