Patent GB-1107428-A (GB)
Title: System for automatic radio transfer of digital information and for distance computation
IPC: H04Q9/14
Filed: 1965-11-12
Abstract: 1,107,428. Radio signalling system; pulse discriminating circuits. COMPAGNIE FRANCAISE THOMSON HOUSTON-HOTCHKISS BRANDT. 12 Nov., 1965 [13 Nov., 1964], No. 48254/65. Headings H3P and H4L. A radar signalling and information transferring system, comprises a main station, Fig. 7, and a plurality of secondary stations. Fig. 3. Each secondary station is allotted a digital address number and stores this number, together with gathered information until it is interrogated by the main station with an interrogation signal, Fig. 1a, containing its address number n, whence it replies to the main station with the information and the address number. The main station interrogates each secondary station in cyclic order. As particularly described each secondary station is a radiosonde balloon determining temperature and pressure, and the main station is an artificial satellite which after having received all the gathered temperature and pressure data, retransmits it to a ground station. All the signals are transferred as P.C.M./F.M. format. The pulse code modulation found after frequency demodulation of a signal is such that the modulation is divided into keying periods, e.g. 200 Ás, Fig. 2, and a 0 digit is represented by a pulse either negative or positive going occupying the whole period, and a 1 digit is represented by a pulse occupying half said period. The interrogation signal, Fig. 2, comprises, in order, fifty four consecutive 0 digits, a start 1 digit S and the ten digit address number n of the secondary station being interrogated. At a secondary station, Fig. 3, the interrogation is received and the pulse signal of Fig. 2 derived at output 7 of FM receiver 6. The pulse signal is then passed to a time interval discriminator 8 which passes all pulses having a duration in the range 50-150 Ás-i.e. the 1 digit pulses-to an output 10, all pulses having a duration in the range 150-250 Ás-i.e. the 0 digit pulses-to an output 12, and all pulses either shorter than 50 Ás or longer the 250 Ás-i.e. interference &c. -to an output 14. The fifty-four 0 digit pulses appearing at output 12 cause a variable frequency oscillator 18 to produce a train of 200 Ás pulses at output 20 in synchronism with said 0 digit pulses by means of a feedback control loop 22 and phase shifter 16. The 1 digit pulses in address number n are fed from output 10 to a ten stage binary shift register 24. The 200 Ás pulse train at 20 is applied via AND gate 28 and OR gate 30 to the register as a shift pulse train. Thus, after ten shift pulse periods 20 Ás, the address number is stored in the register 24. The address selected for the station is stored in register 34, and is compared with that in register 24 by means of AND gates 36. When the received address number is correct, all the AND gates give an output, resulting in a transfer command output being produced by AND gate 38. One use of the transfer command signal is to enable transmitter 56. The command signal also stops the application of the shift pulses to the register 24, such that the number n remains therein, and also passes the 200 Ás pulse train to a by four divider counter 44, to produce at 45 a reply shift pulse train of 800 Ás pulses. These are fed to a 230 stage register 46 containing the derived meteorological information for feeding said information in serial bit form each 800 Ás in duration, to the frequency modulator 54 of the -transmitter 56. The information is thus transmitted to the main station. When 230 of the 800 Ás shift pulses have been produced a 230 bit counter 64 produces a signal which opens gate 68 and feeds the shift-pulses to the register 24. The number n is therefore read out and transmitted after the information. In a modification, Fig. 4, the, fifty-four synchronization pulses may include some 1 digit pulses, whereby information may be transmitted to the secondary station register 24 which is extended by fifty-four stages to accommodate this information. In a further modification, the ten digit number n may be transmitted before the information and counter 64 is accordingly replaced by a ten bit counter 74 controlling the feed of shift pulses to register 46. Any error indicating pulses on output 14 will clear counters 44 and 64 and register 24. An exclusive arrangement of two consecutive 1 digits is used in the response to indicate St, the start of the address number in the reply. The main station, Fig. 7, comprises a 1 Mc/s. clock oscillator 162, the output of which is passed to a 1 to 200 divider circuit 160 to produce a train of 200 Ás duration pulses. These pulses are further divided down in circuit 159 to produce a train of 12À8 ms. pulses and then in circuit 158 to produce a train of 256 ms. pulses. From Figs. 1 and 2 it is seen that 200 Ás is the duration of a keying period, 12À8 ms. is the duration t 1  of the interrogation signal and 256 ms. is the repetition period to of the interrogation signals. The 256 ms. pulses are fed to a nine stage counter 157 which produces a cycle of 512 consecutive address numbers representing the secondary station being interrogated. The address number stored in the counter 157 is transferred to the first nine stages of a ten stage shift register 155 on gates 151 being opened. A logic coincidence gate 154 produces a signal during the first 12À8 ms. period of the 256 ms. repetition period. This signal enables the transmitter 168 for the interrogation signal and also opens gate 152 to allow 200 Ás pulses to pass via OR gate 150 to the shift inputs of register 155, at the moment empty, such that the tenth stage of the register produces a train of 200 Ás pulses which are fed to frequency modulator 166 to modulate the transmitter and produce the synchronizing pulses I. When fifty-four of the 200 Ás pulses have been produced, a logic coincidence gate 156 produces a signal which opens gates 151 to allow the transference of the address number into register 155 and its subsequent read out by the shift 200 Ás pulses and transmission. It is also desired to determine the distance between the main station and the interrogated secondary station. In Fig. 1, (a) represents the transmitted interrogation signal, (b) represents the received interrogation signal, (c) represents the transmitted reply signal and (d) represents the received reply signal. The required distance is thus seen to be given by:- A distance counter 163 is thus provided and is fed with the 1 Mc/s. output of oscillator 162 via an AND gate 169, and this gate is opened to allow the start of the distance count by means of a set output signal from bi-stable circuit 161. The circuit 161 is put into its set condition by the output of circuit 154. The response signal is received and demodulated in receiver 174 to produce the signal shown in the lower part of Fig. 2. This signal is fed to a time interval discriminator 176 passing the 1 digits to output 178, the 0 digits to output 180 and interference pulses &c. to output 182. Oscillator 192 is caused to produce 800 Ás shifting pulses in synchronism with the received 0 digits in the same manner as oscillator 18, Fig. 3. The 1 digits are passed to a start detector 190 comprising a monostable circuit 302 which applies a signal to one input of AND gate 304 for 1000 Ás when a 1 digit is applied to the detection. Said signal is still applied therefore if, in the case of start 1 digit pulse pair St, a second 1 digit arrives at the other input of the AND gate. The gate 190 therefore produces a pulse on detecting St and this is used to reopen gates 151 and transfer the number in counter 157 to the register 155 for the second time. The output of detector 190 also sets bi-stable circuit 167 which sends an opening signal to gate 191, thus allowing shift pulses to be applied to the register 155. The number in register 155 is thus serially read out on line 205 to one input of a non- coincidence detector 196. The 1 digits of the received address number are simultaneously synchronously, fed to the second input of detector 196. Detector 196 produces an output if two input digits deviate from coincidence by more than 200 Ás, which resets circuit 167 via OR gate 165, such that the opening signal or gate is produced by detector 196, a counter 197 is allowed to count up the shift pulses until a predetermined count, as determined by logic coincidence gate 199 is reached, whence, said gate produces a signal resetting circuit 161 and stopping the distances count. By use of a suitable presetting reading on the distance counter, said counter now gives the distance to the secondary station. The information carried in the outputs 178 and 180 of discriminator 176 is determined by decoder means reached via gates 201 and 202. The time interval discriminator (8) of Fig. 3, is shown in detail in Fig. 6. The pulse train, Fig. 2, is fed to a differentiation and inverting circuit 82, which converts each transaction, whether positive or negative going, into a negative spike. In the absence of any spikes all three bi-stable circuits 94, 90 and 92 are reset (i.e. a signal appears at the hatched output) and in gates 105, 103 and 88 are all open. A first spike will thus pass through gate 88 to output 14. It will also pass through gate 103 and set circuit 94. The set output of circuit 94 is applied via OR gate 104 to keep gate 88 open, for 50 Ás, by means of feedback delay 100, so that a second spike occurring less than 50 Ás. after the first also passes to output 14. The resetting of circuit 94 at the end of the 50 Ás. period sets circuit 90 and this is reset 100 Ás. later by means of delay 96. Gate 84 is thus kept open for the required duration of 50-150 Ás. after the initial spike. The resetting of circuit 90 sets circuit 92 and this is reset 100 Ás later by means of delay 98. Gate 86 is thus kept open for the required duration of 150-250 Ás. after the initial spike. The resetting of circuit 92, also, via gate 102 and gate 104, opens gate 88 for the period grea