Patent GB-1312726-A (GB)
Title: Automatic synchronizing monitor for parallel connection fo two separate alternating current sources
IPC: H02J3/42
Filed: 1970-11-03
Abstract: 1312726 Automatic synchronizing systems AUTOMATIC SWITCH CO 3 Nov 1970 [3 Dec 1969] 52331/70 Heading H2H An automatic synchronizing apparatus comprises separate comparators wherein the phase, frequency and voltage of an existing A.C. supply and an incoming supply are compared, and a monitor producing an output signal a predetermined time before conditions for synchronizing are attained so as to allow for the finite operating time of the paralleling device. Inputs from the existing bus and the incoming generator are fed to an "AND" gate 40 by way of connections 36, 38 respectively, the output signal of the "AND" gate being a square wave of varyiug time duration and this signal forms the input signal to a pair of inverters 42, 44. The output signal from the inverter 42 is fed to a differential phase comparator 46 which generates an output signal representing the phase relationship between the bus voltage and that of the incoming generator. This output signal is fed to an impulse generator 50 by way of an amplifier 48, the signal, in itself, being unable to activate the impulse generator because of the clamped condition of a clamp circuit 54 which is also connected to the impulse generator. The generator output is connected to a voltage difference detector 58 by way of lead 60, the bus voltage also being applied to the detector 58 by way of a power supply unit 62. Whilst the voltage difference is outside prescribed limits a continuous signal is generated by the detector 58 which is fed to the clamp circuit 54 to prevent unlatching thereof and to a frequency difference detector 68 to prevent sampling of the frequency difference between the bus and generator. When the voltage difference falls within the prescribed limits the output signal from the voltage difference detector 58 disappears thus the frequency difference detector begins sampling the frequency difference between the bus and generator voltages and the clamp circuit 54 is in a condition to operate when it receives a signal from the frequency difference detector 68. The input signal to the detector 68 is from the inverter 44 and when the frequency difference is within prescribed limits the detector 68 supplies a pulse to the clamp circuit 54 which results in the unlatching of that circuit. Unlatching of the clamp circuit 54, which is indicative that the voltage and frequencies are within the limits for paralleling, allows the next pulse from the comparator 46 to activate the impulse generator 50. The impulse generator now produces an output pulse which is fed by way of an amplifier 52 to the paralleling equipment, if desired by way of a capacitor type stored energy module 56. The paralleling equipment comprises one or more relays and in the case of more than one relay, these are arranged with their contacts in parallel, one relay being of the "fast-acting" type. When the impulse amplifier 52 transmits a signal for paralleling, it also feeds a signal to the clamp circuit 54 to reset the circuit thus once more providing an "inhibit signal" to the pulse generator 50. The components in the various "blocks" the schematic diagram shown in Fig. 1, comprise numberous transistors, the phase comparator 46 comprising a differential amplifier together with an adjustable potentiometer, adjustment of which enables the output signal from the comparator to be developed a desired time before true phase synchronism depending upon the operating characteristics of the paralleling equipment.