Patent SG-11201901235T-A (SG)
Title: Instruction-based synchronization of operations including at least one simd scatter operation
Inventor: MAHURIN ERIC
IPC: G06F9/38
Filed: 2017-07-27
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 29 March 2018 (29.03.2018) WIPO I PCT omit VIII °nolo III moo IIV OH °mono oimIE (10) International Publication Number WO 2018/057113 Al (51) International Patent Classification: G06F 9 / 3 0 (2006.01) GO6F 9 / 3 8 (2006.01) (21) International Application Number: PCT/US2017/044105 (22) International Filing Date: 27 July 2017 (27.07.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/272,613 22 September 2016 (22.09.2016) US (71) Applicant: QUALCOMM INCORPORATED [US/US]; Attn: International IP Administration, 5775 Morehouse Dri- ve, San Diego, CA 92121-1714 (US). (72) Inventors: MAHURIN, Eric; 5775 Morehouse Drive, San Diego, CA 92121-1714 (US). CODRESCU, Lucian; 5775 Morehouse Drive, San Diego, CA 92121-1714 (US). (74) Agent: TOLER, Jeffrey, G. et al.; 8500 Bluffstone Cove, Suite A201, Austin, TX 78759 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(ii)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3)) (54) Title: INSTRUCTION-BASED SYNCHRONIZATION OF OPERATIONS INCLUDING AT LEAST ONE SIMD SCATTER = OPERATION W O 20 18/057 113 Al (57) : A method of determining an execution order of memory operations performed by a processor includes executing at least one single-instruction, mul- tiple-data (SIMD) scatter operation by the processor to store data to a memory. The method further includes executing one or more instructions by the processor to determine the execution order of a set of memory operations. The set of memory operations includes the at least one SIMD scatter operation. 100 104 102 Processor , 110 Instruction Cache 114, , 115 X112 ( -116 / SIMD Scatter Memory Ames Instruction Memo r y Access Instruction Instruction 1 ADD ‘tr1 a Data Cache r _ L li ( 124 r 126 / / Data / Data / /.. 120 ( 130 Scatter Detector Circuit ( 132 r 134 / ReSez t e te i r r Store- 1., / / Load- r = n re Execution Unit ( 140 Firs: Sta g e Second Sta g e 144 • • • 160 Memory ( 4 162 r : 164 ( 166 ( 168 I Region I I legion I • • • I Re g ion I I Region I FIG. 1 (- 106 Processor Processor