baber/WOPTO huggingface dataset:
Patent TW-459170-B (TW)
Title: Reference voltage generator with monitoring and start up means
Inventor: WOUTERS PATRICK AUGUST MARIA
IPC: G05F3/24
Filed: 2000-02-24
Granted: 2001-10-11
Abstract: A voltage reference generator comprising operational amplifier means (7) associated with feedback circuit (8) for providing a stable voltage reference (VBG) further includes start-up means (10) controlled by monitoring means (9) driven by said voltage reference, said monitoring means providing a voltage reference validation flag indicative of proper operation of said voltage reference generator.
Patent TW-I237988-B (TW)
Title: Cellular telephone
Inventor: KUNG SHAO-TSU
IPC: H04M1/00
Filed: 2000-03-09
Granted: 2005-08-11
Abstract: The present invention calls for a cellular telephone with a sensor. The sensor may be a GPS receiver, or a bio-medical sensor. Upon the pressing of an emergency button, or combination of buttons, the cellular telephone will begin transmitting emergency information to a base station. Alternatively, the cellular telephone will determine, based upon information from the sensor, that an emergency condition has occurred and begin transmitting emergency information to a base station.
Patent TW-495629-B (TW)
Title: Liquid crystal display element and liquid crystal display apparatus using the same
Inventor: HIROTA SHOICHI
IPC: G02F1/1335
Filed: 2000-04-05
Granted: 2002-07-21
Abstract: A reflection type liquid crystal display element, wherein dependency of color on voltage is small, relatively low voltage driving is possible, and quick response is superior, is provided. The twisted angle of the liquid crystal layer 102 held between transparent electrode and reflective electrode 101 is set at 90 DEG and the liquid crystal oriented angle is set in the range of 0 DEG to 30 DEG and 90 DEG to 120 DEG.
Patent TW-476736-B (TW)
Title: A method of treating sludge and a method of treating organic waste water using the same
Inventor: OTAKE HISAO
IPC: C05B17/00
Filed: 2000-04-13
Granted: 2002-02-21
Abstract: A method for treating organic waste water is provided, which is capable of separating and recovering phosphorous components in a liquid or solid form. According to the method of the present invention, reuse of phosphorous components can be facilitated, while the content of phosphorous components contained inside primary treated water with a large quantity can be reduced. A method of treating sludge or organic waste water is characterized in comprising the step of heating the sludge at 60 DEG C to 90 DEG C for 10 min to 120 min, to release the phosphorous components from the sludge to liquid phase.
Patent TW-492207-B (TW)
Title: Positive electrode active material, positive electrode active material composition and lithium ion secondary battery
Inventor: GOSHO ITARU
IPC: H01M10/40
Filed: 2000-05-12
Granted: 2002-06-21
Abstract: The present invention relates to a positive electrode active material, a negative electrode active material and an electrolyte that are used alone or in combination to improve charge and discharge cycle characteristic, low temperature characteristic and safety of a non-aqueous electrolyic secondary battery, particularly a lithium ion secondary battery. Specifically, a particulate Li-transition metal composite oxide having an average particle size of not less than 10 μm, wherein [20/(specific surface area x average particle size)]=7-9, is used as a positive electrode active material.
Patent TW-477100-B (TW)
Title: Motor utilizing basic factor and having generator function
Inventor: OGINO SANSHIRO
IPC: H01F7/06
Filed: 2000-05-26
Granted: 2002-02-21
Abstract: A motor which has an improved energy efficiency, is excellent in practical use and has a generator function at the same time. The motor is provided with a basic factor 15 having working surfaces 55a and 55c on both sides thereof, respectively, and movable members 57 made of a magnetic material and arranged opposite to the working surfaces, respectively. Further, the basic factor 15 is provided with an electromagnet element 17 and permanent magnets 19 arranged on both sides thereof through contact surfaces, respectively, and the working surfaces and the contact surfaces are held opposite to each other through the permanent magnets 19, respectively.
Patent TW-508835-B (TW)
Title: Epitaxial wafer for infrared light-emitting device and light-emitting device using the same
Inventor: YOSHINAGA ATSUSHI
IPC: H01L33/00
Filed: 2000-06-07
Granted: 2002-11-01
Abstract: The present invention provides an epitaxial wafer which is obtained by sequentially forming, on an n-type GaAs substrate, a first n-type GaAlAs layer; a second n-type GaAlAs layer; an n-type GaAlAs cladding layer; a p-type GaAlAs active layer which has an emission wavelength of 850-900 nm; and a p-type GaAlAs cladding layer, through liquid phase epitaxy, and, subsequently, removing the n-type GaAs substrate. In the epitaxial wafer, the p-type GaAlAs cladding layer has a thickness of 5-30 μm; the p-type GaAlAs cladding layer has an oxygen concentration of 3x10<SP>16</SP> atoms/cm<SP>3</SP> or less; the p-type GaAlAs cladding layer has a carrier concentration of 1x10<SP>17</SP> cm<SP>-3</SP> to 1x10<SP>18</SP> cm<SP>-3</SP>; the p-type GaAlAs active layer has a thickness of 0.05-0.4 μm; the peak carbon concentration of the portion in the second n-type GaAlAs layer within 2 μm of the interface between the second n-type GaAlAs layer and the first n-type GaAlAs layer is less than 1x10<SP>17</SP> atoms/cm<SP>3</SP>; the p-type GaAlAs active layer contains germanium as a predominant dopant; the n-type GaAlAs cladding layer has a Ge concentration of 3x10<SP>16</SP> atoms/cm<SP>3</SP> or less; and the second n-type GaAlAs layer has a Ge concentration of 3x10<SP>16</SP> atoms/cm<SP>3</SP> or less. The invention provides an epitaxial wafer of double-hetero structure for producing high-intensity GaAlAs infrared LEDs.
Patent TW-447089-B (TW)
Title: Flip-chip semiconductor package structure and manufacturing process
Inventor: CHIOU SHR-GUAN
IPC: H01L23/00
Filed: 2000-06-12
Granted: 2001-07-21
Abstract: This invention is about a kind of flip-chip semiconductor package technique, which can be used to manufacture flip-chip semiconductor package structure that is not easily deformed and has good heat dissipation functions. The characteristic of this flip-chip semiconductor package technique is to form a metal blocking dam structure on the surface located at the periphery of semiconductor chip on the substrate, in which the metal blocking dam structure is used to restrict the filling glue material added during the flip-chip underfilling process inside the range of a narrow band region with a predetermined width at the chip periphery so as to prevent the filling glue material from flowing to the region outside the narrow band region and make the formed fillet of flip-chip underfilling layer have the predetermined width. In addition, this metal blocking dam structure can also be used as a structure stiffener member so that the generation of deformation of the whole package structure is difficult to occur. Furthermore, this metal blocking dam structure can be further used as a heat dissipation structure to dissipate the heat generated by the chip during the operation. The functions stated above are capable of making the packaged semiconductor products which are fabricated by using this flip-chip semiconductor package technique have better quality and reliability characteristics.
Patent TW-506226-B (TW)
Title: Voice-to-remaining audio (vra) interactive hearing aid and auxiliary equipment
Inventor: VAUDREY MICHAEL A
IPC: H04R3/00
Filed: 2000-06-15
Granted: 2002-10-11
Abstract: An integrated individual listening device and decoder for receiving an audio signal including a decoder for decoding the audio signal by separating the audio signal into a voice signal and a background signal, a first end-user adjustable amplifier coupled to the voice signal and amplifying the voice signal; a second end-user adjustable amplifier coupled to the background signal and amplifying the background signal: a summing amplifier coupled to outputs of said first and second end-user adjustable amplifiers and outputting a total audio signal, said total signal being coupled to an individual listening device.
Patent TW-553973-B (TW)
Title: Process to produce polyethylene terephthahlate modified with o-phthalic acid units
Inventor: WIEGNER JENS-PETER
IPC: C08G63/181
Filed: 2000-06-30
Granted: 2003-09-21
Abstract: The invention relates to a process to produce polyethylene terephthalate modified with o-phthalic acid units while avoiding any high phthalic acid losses during esterification or polycondensation and while maintaining the favorable use properties effected by the phthalic acid. According to the present invention, a precondensate made of phthalic anhydride and ethylene glycol in a non-catalytic reaction is added in the esterification and/or polycondensation stages, whereby the ethylene glycol is used at a molar excess of 2 to 3.5 relative to the phthalic anhydride.
Patent TW-466430-B (TW)
Title: Method and apparatus of assisting and expediting the negotiation processes of business transactions
Inventor: WANG BAILU
Filed: 2000-07-14
Granted: 2001-12-01
Abstract: The present invention provides a method and apparatus for assisting and expediting the negotiation processes of business transactions. In the method of the invention, sellers can create electronic selling agents to conduct negotiation on behalf of the sellers. Buyers can create electronic buying agents to conduct negotiation on behalf of the buyers. The sellers or selling agents and the buyers or buying agents can negotiate and conduct business transactions through the assistance of electronic market places, which provide a wide variety of supports and information necessary for the transactions. The method and the apparatus are applicable to an information exchange network such as Internet and wireless information exchange network, or even a telephone network that provides similar functions of information exchange.
Patent TW-476903-B (TW)
Title: Method, system, and program for processing data from an input device
Inventor: KRAUSE TERRY ROBERT
IPC: G06F9/445
Filed: 2000-07-26
Granted: 2002-02-21
Abstract: Disclosed is a system, method, and program for managing input events to a computer. Indication of a selection of a location on a display object displayed on a computer monitor and an input event are received. A determination is made of a segment of the display object including the selected location. The display object includes at least two segments such that each segment is capable of mapping to a different input action. A determination is made of one input action for the determined segment. An application program performs a command corresponding to the determined input action.
Patent TW-498196-B (TW)
Title: Method for preventing any data damage caused by floppy diskette controller
Inventor: YANG JIN-SHIN
IPC: H04L1/22
Filed: 2000-10-17
Granted: 2002-08-11
Abstract: The present invention relates to a method for preventing any data damage caused by floppy diskette controller. Before all the byte data are written into or read from a floppy disk in direct memory access (DMA) mode, whether the maximum time interval between sending and removing the DMA request signal (DREQ) is greater than a specific time can be used to determine the possibility of any data loss/damage during data transmission. Then, the computer system will be notified to carry out some certain responding processes so to minimize the number of data losses/damages due to any delay in writing into the floppy disk.
Patent TW-472329-B (TW)
Title: Precision wide band gap semiconductor etching
Inventor: BARSKY MICHAEL E
IPC: H01L21/331
Filed: 2000-12-19
Granted: 2002-01-11
Abstract: A method for etching GaN material comprising configuring the GaN matenal as an anode in an electrochemical cell where the electrochemical cell is comprised of an anode, a cathode and an electrolyte, and applying a bias across the anode and the cathode to a level which is sufficient to induce etching of the material. The etch rate of the material is controllable by varying the bias level. The cell is additionally illuminated with a preselected level of UV light which provides for uniformity of the etching process. The present method is particularly useful for etching a GaN HBT from n-p-n GaN material.
Patent TW-564246-B (TW)
Title: 3-(1-hydroxy-pentylidene)-5-nitro-3H-benzofuran-2-one, a process for the preparation thereof and the use thereof
Inventor: SCHOUTEETEN ALAIN
IPC: C07D307/79
Filed: 2001-01-10
Granted: 2003-12-01
Abstract: A product corresponding to formula (I) or its ketonic tautomer form (II) which is 3-(1-hydroxy-pentylidene)-5-nitro-3H-benzofuran-2-one, a process for the preparation and use of the product corresponding to formula (I) or its tautomeric form (II), a process for the preparation and use, particularly for the production of synthesis intermediates.
Patent TW-494240-B (TW)
Title: Membrane probe card and method of fabricating the same
Inventor: CHOU BRUCE C S
IPC: G01R1/02
Filed: 2001-01-12
Granted: 2002-07-11
Abstract: The present invention provides a membrane probe card that is suitable for testing dynamic memory module, testing flat display panel and testing the other electronic devices. The probe card includes the followings. A flexible printed circuit board is included, in which the flexible printed circuit board (PCB) is provided with the first end and the second end located at the opposite side of the first end such that the second end is separated from the first end with a predetermined distance. At least one metal layer is located in the flexible PCB and is used to define at least one metal connecting wire, which is provided with the first end and the second end. A smaller separation is formed in between the metal connecting wires at the first end so as to match the separation of metal pads of the electronic devices under measurement. A larger separation is formed in between the metal connecting wires at the second end such that it is convenient to connect with the external measurement equipment. The metal connecting wires between the first end and the second end are completed by a radiation-shaped layout. At least one metal bump is fabricated on the at least one metal connecting wire at the first end and is used to electrically contact metal pads of the electronic device under measurement.
Patent TW-478170-B (TW)
Title: Thin film transistor
Inventor: TSUBATA TOSHIHIDE
IPC: H01L29/45
Filed: 2001-02-13
Granted: 2002-03-01
Abstract: An Ta film for use in forming a source electrode and a drain electrode and an amorphous silicon film for use in forming an amorphous silicon semiconductor layer with impurity are continuously etched without setting an etching selectivity ratio. As a result, the source electrode, the drain electrode and the amorphous silicon semiconductor can be formed by a single etching process, and in the meantime, surface protrusions and recessions can be formed in a back channel region on the order of several hundreds of Å reflecting the crystal grain diameters of the Ta film for use in forming the source electrode and the drain electrode. The resulting protrusions and recessions offers an effect of suppressing an increase in OFF-state current value of the thin film transistor and according to the foregoing method, the thin film transistor can be manufactured through a reduced number of steps at lower cost.
Patent TW-498363-B (TW)
Title: Display device comprising a deflection unit, and a deflection unit for a display device
Inventor: WASSINK MICHAEL HARJON
IPC: H01J29/76
Filed: 2001-03-01
Granted: 2002-08-11
Abstract: A colour display device comprising a cathode ray tube and a deflection unit. The display device includes magnets for correcting distortions in the raster displayed on the screen and means for providing correction currents through the coils of the correction magnets. The correction electromagnets are arranged substantially anti-mirror-symmetrically with respect to the field (vertical, y-z) deflection plane, substantially mirror-symmetrically with respect to the line (horizontal, x-z) deflection plane, and each correction coil extends along an arc portion between angles Α1 and Α2 said angles obeying the following rules: |cos(3Α1)-cos(3Α2)| ≥ 1.33 and |cos(5Α1)-cos(5Α2)| ≤ 0.5, Α1 and Α2 being taken with respect to the line (horizontal) deflection plane.
Patent TW-533613-B (TW)
Title: Power apparatus
Inventor: EMORI AKIHIKO
IPC: H02J7/02
Filed: 2001-03-13
Granted: 2003-05-21
Abstract: A power apparatus comprises a plurality of capacitors connected in series, a plurality of DC-AC conversion circuits converting each DC voltage of the plurality of capacitors to an AC signal that an AC component equivalent to the inter-terminal DC voltage of each of the capacitors is superimposed on the respective DC voltages and a plurality of condenser couplers break the respective DC voltages and output the AC components respectively, and a processing circuit detecting the inter-terminal DC voltage of the corresponding capacitor from the AC component.
Patent TW-514792-B (TW)
Title: Method and apparatus for reducing back-to-back voltage glitch on high speed data bus
Inventor: TO HING Y
IPC: G06F13/40
Filed: 2001-04-24
Granted: 2002-12-21
Abstract: An example embodiment of a method and apparatus for reducing back-to-back voltage glitch on a high speed bus is described. A pre-driver circuit receives an input voltage signal whose voltage level swings from a logically low voltage level to a logically high voltage level where the logically low voltage level approximately equals VSS and the logically high voltage level approximately equals VCC. The pre-driver circuit reduces the magnitude of the voltage swing to create a signal that when delivered to a driver transistor ensures that the driver transistor will operate in its saturation region even when the voltage on the high speed bus is at its minimum specified voltage. When the driver transistor operates in its saturation region it can sink a constant current and provide a high output impedance.
Patent TW-477032-B (TW)
Title: Method for decreasing metal interconnect cross-talk
Inventor: WANG JENG-LIE
IPC: H01L21/768
Filed: 2001-04-09
Granted: 2002-02-21
Abstract: There is provided a method for decreasing metal interconnect cross-talk. A conductor plug on a substrate includes a conductor layer and a barrier layer, wherein the width of the conductor layer is reduced by a solvent cleaning step. Next, a low-k material for use as an inter-metal dielectric layer lays over the conductor plug by the high density plasma chemical vapor deposition method, and an air gap is formed on the sidewall of the conductor layer. The air gap can decrease the dielectric constant of the inter-metal dielectric layer. Furthermore, with the air gap structure, the distance between metal lines can be increased, and the cross-talk between metal lines can be reduced.
Patent TW-517406-B (TW)
Title: Solid oxide fuel cells with symmetric composite electrodes
Inventor: BADDING MICHAEL EDWARD
IPC: H01M8/12
Filed: 2001-05-29
Granted: 2003-01-11
Abstract: The present invention relates to electrode/electrolyte assemblies for solid oxide fuel cells (SOFCs) comprising a thin electrolyte sheet interposed between opposite electrodes, and wherein the positive air electrode (cathode) and negative fuel electrode (anode) are composed of similar electronically conductive metal phases and stabilizing ceramic phases, and wherein the anode exhibits both good oxidation resistance and good catalytic activity toward fuel oxidation.
Patent TW-557445-B (TW)
Title: Semiconductor memory device
Inventor: YAHATA HIDEHARU
IPC: G11C7/10
Filed: 2001-05-31
Granted: 2003-10-11
Abstract: In a clock synchronous memory like a double data rate synchronous DRAM, a register is provided to set a value (advanced latency) for specifying an input or entry cycle for a read or write command. Furthermore, a timing adjustment register (124, 125) for delaying a signal by a predetermined cycle time according to the advanced latency set to the register is provided on a signal path in a column address system, which is formed between a column address latch circuit (110) and a column decoder (116).
Patent TW-I232409-B (TW)
Title: Apparatus and method for providing access to a data stream by a plurality of users at a same time
Inventor: COLEMAN DAVID ALLEN
IPC: H04N21/2385
Filed: 2001-07-02
Granted: 2005-05-11
Abstract: An apparatus and method for providing access to a data stream by a plurality of users at a same time. The apparatus and method include a data stream splitter manager which listens for new connections from client devices. When a new connection from a client device is identified, the data stream splitter manager generates a pseudo-terminal for the client device and adds the client device and pseudo-terminal information to a data stream splitter table. In addition, if a data stream splitter is not already established for handling data transfer between the data stream splitter manager and a requested resource, a new data stream splitter may be generated to handle the data transfer. Thereafter, the data stream splitter searches the data stream splitter table for client devices participating in a session for sharing the system resource. Data from a data stream associated with the shared system resource is sent by the data stream splitter to the pseudo-terminals associated with the client devices. Data from the client devices is sent to the pseudo-terminals and then to the data stream via the data stream splitter. In this way, each client device involved in the session has full access to the shared system resource and output from the shared system resource is provided to each of the client devices involved in the session.
Patent TW-522546-B (TW)
Title: Semiconductor memory
Inventor: NII KOJI
IPC: G11C11/417
Filed: 2001-07-04
Granted: 2003-03-01
Abstract: Provided is a semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
Patent TW-539755-B (TW)
Title: Methods of forming sputtering targets, and sputtering targets formed thereby
Inventor: KIM JAEYEON
IPC: C23C14/34
Filed: 2001-08-21
Granted: 2003-07-01
Abstract: The invention encompasses a method of forming a sputtering target. A wear profile for a sputtering target surface is determined. The wear profile is utilized to generate a desired profile for a sputtering target sputtering surface. A sputtering target is formed having a sputtering surface with the desired profile. The invention also encompasses a sputtering target having a sputtering domain which includes an edge region and a central region. The edge region of the sputtering domain is thicker than the central region.