Patent SG-11201908050T-A (SG)
Title: Multiple plate line architecture for multideck memory array
Inventor: BEDESCHI FERDINANDO
IPC: G11C11/22
Filed: 2018-03-09
Abstract: b 670-a 670-b 660 D Plate line decoder Global plate line Load plate line (WV 600 FIG. 6 W O 20 18/ 18 295 1 Al (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 04 October 2018 (04.10.2018) W I PO I PCT onion °nolo OH 11010111 ow (10) International Publication Number WO 2018/182951 Al (51) International Patent Classification: Gl1C 11/22 (2006.01) Gl1C 5/06 (2006.01) (21) International Application Number: PCT/US2018/021807 (22) International Filing Date: 09 March 2018 (09.03.2018) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/469,865 27 March 2017 (27.03.2017) US (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; 8000 South Federal Way, Boise, Idaho 83716-9632 (US). (72) Inventor: BEDESCHI, Ferdinando; 8000 South Federal Way, Boise, Idaho 83716-9632 (US). (74) Agent: HARRIS, Philip W.; Holland & Hart LLP, P.O. Box 11583, Salt Lake City, Utah 84147 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.1700) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3)) (54) Title: MULTIPLE PLATE LINE ARCHITECTURE FOR MULTIDECK MEMORY ARRAY (57) : Methods, systems, and devices for multiple plate line archi- tecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells 650 overlying a substrate layer that includes various components of support cir- 620 ‘ ,.. , ' 655-6 655-a 610-b 655-c 680-6 cuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines SO-b or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers.