Patent GB-1124974-A (GB)
Title: Capacitive digital storage matrix
IPC: G11C11/403
Filed: 1966-01-07
Abstract: 1,124,974. Capacitive digital data stores. INTERNATIONAL STANDARD ELECTRIC CORP. 7 Jan., 1966 [14 Jan., 1965], No. 788/66. Heading G4C. A capacitive binary data store includes a plurality of storage cells arranged in a coordinate array of rows and columns, each storage cell comprising a capacitor and two diodes unlike poles of which are connected to a common plate of said capacitor, the store further including means for reading data from and writing data into said cells. The store may comprise a plurality of memory planes each including a co-ordinate array of memory capacitors. Binary 1 and 0 respectively are stored by the charged and uncharged states of cells and reading is effected by driving a capacitor to its uncharged state whilst observing its output. A single plane of such a store comprising a 12 x 12 matrix, is shown in Fig. 3, and its operation will be described in terms of the storing of data at and reading data from a capacitor B2. Writing.-The column (X-co-ordinate) is selected by applying a signal at input 23-1 of column selection circuit 230-B<SP>1</SP> (which is common to column B in all planes). AND-gate formed by diodes 231-1 and 231-2 and opened by a clock pulse at input 23-2 allows transistors 235 and 232 to become saturated and the potential of write column B<SP>1</SP> at the collector of transistor 232 thereby changes from V5( + 12 volts) to approximately ground potential. The row (Y-co-ordinate) is selected by applying a signal at input 21-1 of row selection circuit 210-2 (which is common to row 2 in all planes). AND-gate formed by diodes 211-1 and 211-2 and opened by a clock pulse at input 21-2 allows transistors 215 and 212 to become saturated and the potential of row 2 thus changes from V4 ( + 6 volts) towards V5 (+12 volts). The writing of binary 1 or 0 depends on whether or not a (+12 volt) signal is applied to input 19 of input digit circuit 190-P1 (Z-coordinate), which circuit is common to all write columns 'A' to 'L' (through diodes DA<SP>1</SP> to DL<SP>1</SP>) for the plane shown. A signal at input 19 saturates transistor 195 and, since diodes 192 and 193 are blocked whereas diode 194 is not, allows V4 (+6 volts) to be connected through diodes 194 and DB<SP>1</SP>,resistance 240-B<SP>1</SP> and saturated transistor 232 to ground. Thus the potential of point M on column B<SP>1</SP> approaches + 6 volts. The potential drop across the capacitor B2, when a signal is applied to input 19, is thus equal to 6 volts. If no signal is applied to input 19 (writing binary 0) then the potential of both the row 2 and the column B becomes equal to 12 volts (column B<SP>1</SP> potential being established through diodes 192 and DB<SP>1</SP>) and there is no potential drop across the capacitor B2. On return of steady conditions diode B<SP>1</SP>2 becomes blocked, as is also diode B<SP>11</SP>2 ,  thereby preserving the charge on capacitor B2<SP>1</SP>. Heading.-The column is selected by applying a signal to input 25-1 of column selection circuit 250-B<SP>11</SP> (similar to circuit 210-2), which circuit 250-B<SP>11</SP> is common to column B in all planes. AND-gate formed by diodes 251-1 and 251-2 and opened by a clock pulse at input 25-2 allows transistors 255 and 252 to become saturated, whereby the potential of read column B<SP>11</SP>(at the collector of transistor 252) changes from V2 (-6 volts) towards V4 ( + 6 volts), the time for this to take place depending on the values of parasitic capacity 261-B<SP>11 </SP>and resistor 260-B<SP>11</SP>. Eventually diode DB<SP>11</SP> becomes unblocked and the current through it saturates transistor 185 in digit output circuit 180-P1 (which is common to all read columns in the plane shown). As diode 186 is blocked and V3 is a negative voltage close to ground potential, the emitter to base diode of transistor 185 maintains point N of read column B<SP>11</SP> substantially at ground potential. Further, the potential of output 18-1 drops from V5 (+12 volts) to zero in the absence of signal at 18-2. The row is selected by applying a signal at input 27-1 of row selection circuit 270-2 (similar to circuit 250-B<SP>11</SP>), which circuit 270-2 is common to row 2 in all planes. Transistors 275 and 272 become saturated and row 2 potential changes from V4 (+6 volts) towards ground potential. If the capacitor 82 is charged (binary 1 stored), then the potential of point N on column B<SP>11</SP> changes quickly from ground to V2 ( - 6 volts), transistor 185 blocks and the potential of output 18-1 shifts to V5, terminal 18-2 receiving a clock pulse at this time. As the capacitor B2 discharges through resistor 260-B<SP>11</SP> and saturated transistors 252, the potential of the point N increases from V2 (-6 volts) towards V4 ( + 6 volts) but is stopped close to ground potential as transistor 185 then saturates again bringing the potential of output 18-1 back to ground. If the capacitor B2 is uncharged (binary 0 stored), then transistor 185 cannot block and the potential of output 18-1 remains close to ground. Simultaneous reading and writing from different storage capacitors is possible.