Patent GB-1303461-A (GB)
IPC: H01J49/02
Filed: 1970-03-20
Abstract: 1303461 Selective signalling; squaring logic INFOTRONICS CORP 20 March 1970 [20 May 1969] 13795/70 Headings G4A and G4H A digital readout system for an analytical measuring instrument, comprises two amplitude-to-rate converters, their outputs being digitized (in the case of the first converter output, by counting) during successive periodic sampling intervals, and the results being passed to an output under control of an extreme value sensing circuit responsive to the output of the first converter. General.-An ion current (data) analogue signal from a mass spectrometer is passed via an adjustable sealing amplifier, and a voltage-tofrequency converter, to peak height logic. Analogue signals representing the accelerating voltage and magnetic field intensity of the spectrometer are passed from the spectrometer via respective adjustable scaling amplifiers and voltage-to-frequency converters to mass number logic. The peak height logic and mass number logic feed a printer via a printout register. A digital display may be fed from a main up counter in the peak height logic or from a measuring counter in the mass number logic. Peak height logic.-The ion current amplitude, in frequency-significant form, is passed during each of a succession of sampling periods (of duration pre-selected by a knob) by a sample gate to increment a main up counter (reset before each period) and decrement a main down counter (loaded before each period by non- destructive readout from a main memory). If a mode latch is in a "peak-sensing" state, and the main down counter passes through zero during a period, the main memory is loaded from the main up counter at the end of the period, i.e. this occurs if the count in this period is greater than that in the previous period. If the mode latch is in a "valleysensing" state, the loading of the main memory as above occurs if the main down counter does not pass through zero, rather than if it does, i.e. loading occurs if the count is less than in the previous period. The mode latch is controlled as follows. The output of the sample gate is passed via an adjustable rate "multiplier" (multiplication factor less than one) to increment an auxiliary up counter (reset before each sampling period). An auxiliary memory is loaded from the auxiliary up counter whenever the main memory is loaded from the main up counter. When the mode latch is in its "peaksensing" state, the output of the sample gate is also used to decrement an auxiliary down counter (loaded before each period by non-destructive read-out from the auxiliary memory). If the auxiliary down counter does not pass through zero during a period, the mode latch is switched to the "valley-sensing" state, i.e. this occurs when the ion current amplitude has decreased from its peak value by a fraction defined by the setting of the rate "multiplier". When the mode latch is in its "valley-sensing" state, the auxiliary down counter is loaded before each period by non- destructive readout from the main memory and decremented by the output of the rate "multiplier", and if it does pass through zero, the mode latch is switched to its "peak-sensing" state. When the mode latch leaves its "peaksensing" state (and if a switch is closed, also when it leaves its "valley-sensing" state) the contents of the main memory are gated to the printout register as the peak (or valley) amplitude of the ion current, except that this gating is inhibited for peaks unless (a) the peak reaches a minimum height (indicated by settirg of a flip-flop from a preselectable stage of the main up counter) and (b) at least a preselectable number of sampling periods has occurred durduring the present "peak-sensing" mode (indicated by a minimum sample counter setting a flip-flop).  Mass number logic.-During each sampling period, pulses can be fed to decrement a variably-presettable down counter, and set a flip-flop, the flip-flop being reset at a count of zero, thus producing a duration-significant pulse of duration varying inversely with the prf during the sampling period (and thus also with the number of pulses in the period). Four ganged 6-position selector switches permit any of six modes of operation to by chosen. A measuring counter is reset before each period (except in the sixth mode). In the first mode, the accelerating voltage value, in frequency-significant form, is passed via a first adjustable frequency divider to the measuring counter during each sampling period. The second mode is the same except that the magnetic field intensity value is used instead. In the third mode, the accelerating voltage value, in frequency-significant form, is fed during each sampling period to the down counter arrangement (see above) the duration-significant pulse from which is used to gate clock pulses, already frequency-divided in a second adjustable frequency divider, to the measuring counter. In the fourth mode, the magnetic field intensity value, in frequency-significant form, is gated during each sampling period via squaring logic (see below) and the second frequency divider to the measuring counter while the duration. significant pulse is present from the down counter arrangement, this being driven during each sampling period by the clock pulses, frequency-divided by ten. In the fifth mode, during each sampling period, the accelerating voltage value frequency-significant signal drives the down counter arrangement, the durationsignificant pulse from this gating to the measuring counter the magnetic field intensity value frequency-significant signal supplied via the squaring logic and the second frequency divider. Thus in the first to fifth modes respectively, the measuring counter provides results proportional to A, B, 1/A, B<SP>2</SP>, B<SP>2</SP>/A where A is the accelerating voltage value and B is the magnetic field intensity value, the latter three representing the mass number in the cases where A, B and both A and B respectively are varied in the spectrometer. Calibration using the various adjustable elements of the system and the digital display is described and permits the mass numbers to be obtained without a proportionality factor (except that the decimal point is missing). In the sixth mode, the sampling periods are counted in the measuring counter. In all modes, the measuring counter value is gated to a memory whenever the main memory in the peak height logic is loaded from the main up counter. The measuring counter value is gated from the memory to the printout register whenever the main memory is gated to the printout register (see "peak height logic"). Squaring logic.-In each of the succession of sampling periods, the frequency-significant pulse train at the input of the squaring logic is used to increment a binary counter. At the end of each sampling period, the count is transferred to a memory register, then the counter is reset. The counter stages are also connected to respective 2-input AND gates, each connected at its other input to a respective stage of the memory register but in the reverse order, i.e. the most significant stage of the counter is connected to the same AND gate as the least significant stage of the register. The AND gates feed an OR gate via respective single-shots, so each 0-to-1 transition at the output of any AND gate during the counting in any period applies a pulse to the OR gate, which gives the squarer output.