Patent GB-1155249-A (GB)
Title: Improvements in or relating to Computers.
Inventor: LUCAS PIERRE
IPC: G06F17/00
Filed: 1967-07-06
Abstract: 1,155,249. Automatic exchange systems. P. LUCAS, J. DUQUESNE, J-P. BERGER, and J-P. DISSEL. 6 July, 1967 [6 July, 1966], No. 31239/67. Heading H4K. A computer controlling a switching network governs a group of registers comprised by call stores each of which may serve a junction in the exchange and each of which records a so-called routine number #o indicating the sequence state of the connection being supervised, the program store normally being addressed at a time t o  for a sequence of orders 01, 02, 03, for execution at times t 1 , t2, t 3 , in a processing cycle but, if the scan of a junctor circuit shows a significant change in condition (such as a loop break), the program store is addressed by the routine number #0 in the register to obtain at time t o  a special directive RD from a first part of a so-called phase table by means of which the program store is addressed at time t 2  to obtain from a second part of the phase table a new routine number # for storage in the register being processed. The computer has a fast cycle PMR for network supervision and a slow cycle PML for the performance of logical operations. To cater for both calling and called sides of each junctor the cycles may be of a type PMR 0  or PMR 1  and PML o  or PML 1 , respectively. A fundamental program instruction IF 0  is employed in conditions of no change and if, in the context of a particular register being serviced, only the calling side of a junctor is active, the instruction IF o  loops back on itself. If the called side of a junction is also active an instruction 1F 1  is employed after IF o  and reverse to IF o  where no change is detected. When change is detected, sub-programs are exploited in accordance with the routine (phase) number involved and the type of change detected. As shown in Figs. 1a, 1b 1c, which join side by side in that order, the program store 1 is addressed from a register 2 and reads out to a register 3 to control a function decoder 4 by way of an interrupt analyser 9. The instruction register 2 obtains a new address from the preceding address in a store 24 as incremented from register 30, the increments running from +7 through +0 and - 0 to - 7. Otherwise an instruction may be written afresh from a transfer address register 21. The external circuits are shown as a network 11 and a magnetic drum 8 each of which are accessed by way of address registers and a buffer store 10 attached to the registers in a so-called multi-register 5. A particular register, as addressed from a principal address register 14, is read out to a store 6 where its data is available for comparison with current conditions, re-write being effected by way of a register 7. The principal address register 14 is incremented by means of an auxiliary register 15 and an adder 27. The junctors are scanned direct by the processor by way of a scanner 26 addressed from the read-out store 6. External conditions are detectable from bi-stables in a first group comprising BIR to indicate network demands, BIT for magnetic drum demands, BAR to indicate that a register scanning cycle conducted by the principal address register 14, and BDE to indicate that a register is required for a call origination. A second group of bistables comprise BDO to show that a register is employed, BDP to indicate that both sides of a junctor require supervision, E to indicate a junctor terminal state and F# to indicate a register timing function provided by incrementing a counting section of the register each time it is scanned. Each register in a 32-bit section for the calling side of a junctor carries the phase number #0 of the sequence state plus a complement Ko, the code Ao identifying the junctor, the counter section F# for discriminating persistent off-hook conditions, and one bit Eo to record the loop condition of the calling side of the junctor. A similar set of co-ordinates are employed for the called side of the junctor. The program store contains the so-called phase table as well as operating instructions and address increments. The orders 01, 02, 03 operative at itmes t 1 , t 2 , t 3  and available at time t o  relate, at time t 1 , to read out of a register and detection of currently existing external conditions; while at times t 2 , t 3 , the orders depend in their effect on the external conditions found and on their origin. The function decoder 4 has three groups of outlets each governed in a respective time slot t 1 , t 2 , t 3 . A read-out order at time t 1  is accompanied by an order to connect the first bi-stable group to the interrupt analyser 9. If no interrupt occurs at t 1 , order 02 at t 2  directs the scan of the junction indicated in the register and directs the connection of the second bi-stable group to the interrupt analyser followed by rewriting and updating of the register. With no interrupt occurring at t 1  and the second group bi-stable states known, the order 03 at t 3  faces seven possibilities. The register may be idle and not required. The register may be idle and required. The register may be in use but no activity be called for on its behalf. The remaining four possibilities concern the register being in use with service of particular sorts being required. Where the register is idle and unwanted an increment +O effects progression to the next register and retention of instruction IF 0 . If the register is wanted an increment x precipitates a transfer from register 21 to obtain a register allotting sub-routine. If the register is busy but no action is required an increment + 0 effects re-write or an increment + 1 advances to 1F 1  if the called side of the junctor also requires supervision. If the register is busy and service is required a jump is made with an increment - O to a special directive IL contained in the first part of the " phase table of the program store. The directive is obtained by using the phase number #o and a factor h from the interrupt analyser 9 as an address to the first part of the phase table. The factor h indicates merely that the calling or called side of the junctor is involved. The special directive comprises an order 01 in common with other instruction but the data corresponding to orders 02, 03 is processed as one section at t 2  and comprises a transfer address m and an order complement c. The complement c determines whether the address m is placed in transfer address register 21 either completely or in part with the record of bi-stables 39(E) and 40(E<SP>1</SP>), or whether it is placed in address register 14 to access a special register as may be required with code reception. The second part of the phase table is accessed by IL using the phase number #o and its supplement k 0  to obtain the new phase number #<SP>1</SP>. If an interruption occurs, as detected from the examination of the first group of bi-stables at t 1 , the order 02 at t 2  effects the registration of the identity of the register requiring attention in the address register 14. Order 03 at t 3  now effects a program transfer by directing an instruction from the transfer address register corresponding to input Ur if the network 11 is involved or input Ut if the magnetic drum 8 is involved.