baber/WOPTO huggingface dataset:
Patent TW-200746307-A (TW)
Title: Method for fabricating recessed gate MOS transistor device
Inventor: HUANG MING-YUAN
IPC: H01L29/423
Filed: 2006-06-05
Abstract: A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.
Patent TW-200709323-A (TW)
Title: A tool for stretching the foil of a foil carrier, a machine for removing dies from a wafer and a method for removing dies
Inventor: VAN BEUNINGEN GERARDUS WILHELMUS MARIA
IPC: H01L21/52
Filed: 2006-06-13
Abstract: The present invention relates to a tool for stretching the foil (2) of a foil carrier (1), the foil being connected to a frame (3), which tool comprises a circular inner body (6) and a circular outer body (7), the foil being stretched by supporting the frame with at least one body and moving one body with respect to the other body in axial direction, the inner body extending in the outer body, wherein coupling means (10) are provided, which couples during a rotational movement from one body in relation to the other, and which converts this rotational movement into the required axial movement stretching the foil (2). The invention furthermore also relates to a machine and a method for removing dies from a foil carrier.
Patent TW-200726767-A (TW)
Title: Chemical compounds 2
Inventor: LISIUS ANNEA
IPC: A61K31/519
Filed: 2006-06-23
Abstract: The present invention provides a compound of a formula (I): wherein the variables are defined herein; to a process for preparing such a compound; and to the use of such a compound in the treatment of a PDE4 mediated disease state.
Patent TW-200721806-A (TW)
Title: Image processing apparatus, image display and image processing method
Inventor: HARADA SHIGERU
IPC: H04N5/202
Filed: 2006-07-18
Abstract: There is provided an image processing apparatus, an image display and an image processing method which are capable of preventing an unnatural change in image quality due to image processing. A luminance distribution detecting circuit detects a luminance distribution as the histogram distribution of YUV signals. A gain calculating circuit and a gain limiter detect a gain variation on the basis of luminance distribution data. The gain limiter limits the gain variation to a gain variation threshold or less. The gain limiter and a delay circuit carry over the gain variation of a portion exceeding the gain variation threshold to the next image frame so as to modify the gain variation. A correction circuit performs image processing (contrast control) on the YUV signals on the basis of the gain variation modified.
Patent TW-200711789-A (TW)
Title: Grinding device
Inventor: SHIRAI AKIRA
IPC: B24B9/08
Filed: 2006-07-21
Abstract: The present invention can solve the inconvenience that a glass substrate carrying bench has to be replaced to correspond to the change of lateral length of the glass substrate in the conventional techniques. The present invention provides a grinding device, which comprises a moving body movable forwards and backwards by means of an advancing/retreating device; a work bench which has the function of attracting and holding a carried glass substrate, and is installed on a central area of the moving body, and is rotated by a revolving device; two support strips, which are installed in parallel on opposite sides of the top face of the work bench and are guided to approach toward or leave away from each other by a guiding device; a sliding moving device, which makes the two support strips mutually approach or leave away from each other; and rotating grinding stones arranged on opposite sides of a moving path of the moving body to grind two sides of the glass substrate; and a ascending/descending device utilized to make one of the work bench and ascending or descending.
Patent TW-200724489-A (TW)
Title: A process for preparing molecular sieves via continuous addition of nutrients
Inventor: KONRAD BRIAN S
IPC: C01B37/08
Filed: 2006-08-08
Abstract: A process for synthesizing a variety of molecular sieves has been developed. The process involves forming a reaction mixture comprising reactive sources of the framework elements plus at least one templating agent, reacting the mixture to at least partially crystallize the molecular sieve and provide a slurry of seed crystals and adding to it nutrients (sources) of the framework elements, e.g. aluminum and silicon in order to grow the seed crystals. The rate of addition of the nutrients is controlled such that it is substantially the same as the crystal growth rate and such that there is substantially no nucleation of new crystals. The seed crystals may be the same or different than the nutrients being added, thus allowing for a layered molecular sieve. When the crystals have reached a desired size, they are isolated by conventional techniques.
Patent TW-200707918-A (TW)
Title: Method of starting application software by computer keyboard
Inventor: LEE YING-CHU
IPC: G06F3/023
Filed: 2006-08-15
Abstract: A method of starting application software by computer keyboard by users includes starting application software when a direction key and its opposite direction key are actuated at the same time without other keys of keyboard being pressed or showing multiple options representing the application software and starting application software by pressing a direction key or a number key.
Patent TW-200721158-A (TW)
Title: Flash memory programming using an indication bit to interpret state
Inventor: AKAOGI TAKAO
IPC: G11C11/06
Filed: 2006-09-15
Abstract: Non-volatile memory, such as Flash memory, is programmed by writing a window (515) of information to memory. The programmed/non-programmed state of each memory cell (201) may be dynamically determined for each window and stored as an indication bit. These techniques can provide for improved average power drain and a reduced maximum current per window during programming.
Patent TW-200730264-A (TW)
Title: Particle classification apparatus and adhesive including particles classified by the apparatus
Inventor: KOYAMA KEIJI
IPC: C09J9/02
Filed: 2006-09-25
Abstract: A classification apparatus that can precisely separate the particles by their particle sizes and its adhesive that can adhere these particles to each other via lowering the pressure between electrodes and can adjust itself to the fine pole-pitch of the electrodes. This particle classification apparatus (1) comprises dispersing means for dispersing a plurality of particles (2), orienting means for orienting these dispersed particles (P) to the transport direction (X) in an isolated manner (3), measuring means for measuring each particle size of these oriented particles (4), and separating means for separating the particles (5) with a size in criterion, from others, according to the measured data for the particle size.
Patent TW-200733358-A (TW)
Title: Memory cell comprising switchable semiconductor memory element with trimmable resistance
Inventor: KUMAR TANMAY
IPC: G11C14/00
Filed: 2006-09-27
Abstract: A nonvolatile memory cell comprising doped semiconductor material and a diode can store memory states by changing the resistance of the doped semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) Set pulses are of short duration and above a threshold voltage, while reset pulses are longer duration and below a threshold voltage. In some embodiments multiple resistance states can be achieved, allowing for a multi-state cell, while restoring a prior high-resistance state allows for an rewriteable cell. In some embodiments, the diode and a switchable memory formed of doped semiconductor material are formed in series, while in other embodiments, the diode itself serves as the semiconductor switchable memory element.
Patent TW-200817585-A (TW)
Title: Application method of ultra-low temperature air-compressed rapid-freezing device
Inventor: HUANG QING-FU
IPC: F04B39/16
Filed: 2006-10-03
Abstract: The present invention relates to an application method of ultra-low temperature air-compressed rapid-freezing device three freezing systems are utilized. The low-temperature freezing system in this three freezing systems is served to proceed a front end cooling operation on the introduced air. The other two ultra-low temperature freezing systems are respectively operated with a binary freezing means, so the generated ultra-low temperature is served to cool down the passing air, and an air circulation switch is provided. Further, the problems that during freezing the air to an ultra-low temperature, the moisture in the air is frozen due to the over-cooling leading to the block inside the air passage can be solved, so the method of continuously outputting ultra-low temperature air is able to be achieved.
Patent TW-200805884-A (TW)
Title: Signal gate oxide level shifters
Inventor: HUANG SHENG-TSAI
IPC: H03K19/094
Filed: 2006-10-04
Abstract: A level shifter comprising a first inverter, a second inverter, a first switch module, and a second switch module. The first inverter is coupled between a first voltage and a second voltage, and the second inverter is coupled between the first voltage and the second voltage. The first switch module is coupled between a first data storage node of the first and second inverters and an input signal swing between the first voltage and a ground voltage. The second switch module is coupled between a second data storage node of the first and second inverters and an inverted input signal swing between the ground voltage and the first voltage. The first and second inverters and the first and second switch modules comprise one or more MOS transistors with gate oxide layers of the same thickness.
Patent TW-200730624-A (TW)
Title: Generation and profiling of fully human hucal gold-derived therapeutic antibodies specific for human CD38
Inventor: TESAR MICHAEL
IPC: A61P35/00
Filed: 2006-10-12
Abstract: The present invention provides novel antibodies and methods for using recombinant antigen-binding regions and antibodies and functional fragments containing such antigen-binding regions that are specific for CD38, which plays an integral role in various disorders or conditions. These methods take advantage of newly discovered antibodies and surprising properties of such antibodies, such as the ability to bind CD38 of minipig origin and the ability to induce, by cross-linking, specific killing of cells that express CD38. These antibodies as well as the novel methods for using those antibodies can be used to treat, for example, hematological malignancies such as multiple myeloma.
Patent TW-200820101-A (TW)
Title: Expert system of building codes
Inventor: CHANG CHIAN-YEUN
IPC: G06N5/00
Filed: 2006-10-25
Abstract: The present invention discloses an expert system of the building codes. When building contractors, interior designers and structural engineers work on ''interior decorating'' and ''examination of the interior decorating, ''the system can help them verify their working processes in order to make sure all step are legal. The holistic body of laws adopted in the present invention, comprise building laws, fire control laws, and many other codes. It is difficult for designers, contractors, and the like, to be familiar with all these laws, so they need the help from experienced experts. The process of building up the expert system includes gathering law-related design judgments from many experts, and examining the feasibility of these judgments. Then, we combine all information with the information system to build up the expert system, and we also provide the human computer interface to receive the data from users. Besides, the users can also use this system remotely by the human computer interface of the present invention.
Patent TW-200732940-A (TW)
Title: Configurable circuit with configuration data protection features
Inventor: REBLEWSKI FREDERIC
Filed: 2006-10-31
Abstract: A configurable circuit that includes configuration data protection features, and related methods, are described herein.
Patent TW-200728454-A (TW)
Title: Formulations for removing copper-containing post-etch residue from microelectronic devices
Inventor: VISINTIN PAMELA M
IPC: C23F11/00
Filed: 2006-11-08
Abstract: A method and composition for removing copper-containing post-etch and/or post-ash residue from patterned microelectronic devices is described. The removal composition includes a diluent, a solvent and a copper corrosion inhibitor, wherein the diluent may be a dense fluid or a liquid solvent. The removal compositions effectively remove the copper-containing post-etch residue from the microelectronic device without damaging exposed low-k dielectric and metal interconnect materials.
Patent TW-200823317-A (TW)
Title: Gas distribution device for treating reactor by semiconductor technological element and reactor thereof
Inventor: CHEN STEVE
IPC: H01L21/205
Filed: 2006-11-22
Abstract: The invention discloses a gas distributing device, which comprises the following parts: supplying board of reacting gas, at least one distributing board of reacting gas and transmitting panel of reacting gas, wherein the supplying board of reacting gas interconnects at least the first and second reacting gas; the distributing board of reacting gas connects the supplying board of reacting gas to make at least one reacting gas of the first and second reacting gas disperse evenly; the transmitting panel of reacting gas connects the distributing board of reacting gas; the first and second reacting gas keeps certain distance when the first and second reacting gas passes the distributing board and transmitting panel of reacting gas, which escapes the transmitting panel at even distributing pattern. The invention improves the film property sedimented on the semiconductor piece, which also provides a semiconductor piece processing reactor of the gas distributing device.
Patent TW-200805271-A (TW)
Title: Automatic balancing apparatus, rotating apparatus, disc drive apparatus, and balancer
Inventor: SHISHIDO YUJI
IPC: G11B19/20
Filed: 2006-11-24
Abstract: An automatic balancing apparatus is disclosed. The automatic balancing apparatus includes a plurality of magnets, magnetic fluid, and a rotatable housing. The magnets function as balancers. The rotatable housing has a moving path disposed along a peripheral direction of the rotation. Each of the magnets is moved through the moving path. The rotatable housing accommodates the magnets and the magnetic fluid.
Patent TW-200740920-A (TW)
Title: Polycarbonate molding compositions
Inventor: SEIDEL ANDREAS
IPC: C08L69/00
Filed: 2006-12-08
Abstract: A stabilized thermoplastic molding composition is disclosed. The composition contains (A) aromatic polycarbonate and/or polyester carbonate, (B) a rubber-modified graft polymer or its mixture with a rubber-free (co)polymer and (C) a Bronsted acid compound. The inventive composition is characterized in its improved stability under processing conditions. Also disclosed is a process for the production of the composition and its use for the production of shaped articles.
Patent TW-200738577-A (TW)
Title: Notch stop pulsing process for plasma processing system
Inventor: PANDHUMSOPORN TAMARAK
IPC: H01L21/302
Filed: 2006-12-08
Abstract: A method for etching a substrate having a silicon layer in a plasma processing chamber having a bottom electrode on which the substrate is disposed on during etching. The method includes performing a main etch step. The method also includes terminating main etch step when a predefined etch depth of at least 70 percent of thickness into silicon layer is achieved. The method further includes performing an overetch step. The overetch step including a first process step and a second process step. First process step is performed using a first bottom power level applied to bottom electrode. Second process step is performed using a second bottom power level applied to bottom electrode that is lower than first bottom power level. First process and second process steps are alternately performed a plurality of times. The method yet also includes terminating overetch step after silicon layer is etched through.
Patent TW-200814625-A (TW)
Title: Choosing parameters in a peer-to-peer communications system
Inventor: LAROIA RAJIV
IPC: H04W52/04
Filed: 2007-01-11
Abstract: Systems and methodologies are described that facilitate choosing parameters to utilize in a local area peer-to-peer network. The parameters may relate to tone spacing, cyclic prefix, symbol time and the like. Further, the parameters may be a function of a state (e.g. peer discovery state control related traffic state, data related traffic state, . . . ) associated with the local area peer-to-peer network. Moreover, the local area peer-to-peer network may share spectrum with a wide area network; as such, parameters for the peer-to-peer network may be selected based on the type of wide area network (e.g., air interface technology) and/or wide area network related parameters.
Patent TW-200737503-A (TW)
Title: Self-aligned flash memory cell and method of manufacturing the same
Inventor: KIM HAN-HEUNG
IPC: H01L27/115
Filed: 2007-02-09
Abstract: Provided a self-aligned flash memory cell and a method of manufacturing the same. The method of manufacturing the self-aligned flash memory cell includes: forming a spacer silicon nitride layer at a region where a tunnel oxide layer is to be formed; forming spacers by performing etching process on the spacer silicon nitride layer and forming one or more protrusions of a substrate in a direction of a width of a channel region of the flash memory cell by etching portions of the silicon substrate by using the spacers as masks; etching portions of an oxide layer filling trenches, sequentially forming the tunnel oxide layer and a first polysilicon layer, and performing a planarization process thereon; conformably forming a dielectric layer on the entire planarized first polysilicon layer; stacking a second polysilicon layer which is used to form a control gate on the dielectric layer formed on the substrate; and partially etching the second polysilicon layer, the dielectric layer, and the first polysilicon layer by performing a patterning process. Accordingly, the self-aligned flash memory cell has enhanced FN tunneling and is provided with a wide channel width, so that it is possible to increase a sensing margin caused from a decrease in unit cell current.
Patent TW-200834150-A (TW)
Title: A generating method of super high-frequency strobe light
Inventor: LIAO CHUNG-PIN
IPC: G02B5/20
Filed: 2007-02-12
Abstract: The invention relates to a generating method of super high frequency strobe light. Upon the substrate, it forms a pair of non-uniformity electric double layer with response for light wave, and the additionally supplementary light wave is injected to the non-uniformity electric double layer for reflective and refractive incident light wave. Moreover, the reflective and refractive incident light wave are periodic timing modulated by the additionally supplementary light wave. Eventually, it eliminates the lower light intensity of the reflective and refractive incident light wave to generate the super high frequency strobe light.
Patent TW-200740088-A (TW)
Title: Charge-pump type switching power supply apparatus
Inventor: OYAMA MANABU
IPC: H02M3/07
Filed: 2007-02-13
Abstract: A switching power supply apparatus generates a first output voltage with a reversed polarity of an input voltage and a second input voltage of double the input voltage with the reversed polarity, and then outputs them from the first output terminal and the second output terminal. A driver circuit includes a control unit and a first switch to a sixth switch. The driver circuit repeats three charging periods in a time-division manner. The three charging periods are a first charging period during which a flying capacitor is charged with the input voltage, a second charging period in which a low-potential-side terminal of the flying capacitor is connected to a ground terminal and a first output capacitor is charged with a voltage appearing at the other end of the flying capacitor, and a third charging period in which a high-potential-side of the flying capacitor is connected with the first output terminal and a second output capacitor is charged with a voltage appearing at the other end of the flying capacitor.
Patent TW-200802845-A (TW)
Title: Protection against charging damage in hybrid orientation transistors
Inventor: HOOK TERENCE B
IPC: H01L29/04
Filed: 2007-03-07
Abstract: A chip includes a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. A SOI device is disposed in a semiconductor-on-insulator ("SOI") layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. the diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.
Patent TW-200741273-A (TW)
Title: Optical connector
Inventor: SAITO DAIGO
IPC: G02B6/36
Filed: 2007-03-08
Abstract: A optical connector includes a connector body that has a first optical fiber housed in advance in a ferrule so as to project from a back end of the ferrule opposite to the connecting end surface and a anchoring fixture that anchors a second optical fiber that is to be optically connected to the first optical fiber, and by pressing the anchoring fixture into the connector body while the second optical fiber is anchored in this anchoring fixture, the anchoring fixture and the connector body are connected to optically connect the first optical fiber and the second optical fiber, and the connecting portion that connects the anchoring fixture and the connector body form a movable connecting portion that is adapted to vary the direction of the anchoring fixture with respect to the connector body.
Patent TW-200817159-A (TW)
Title: An electronic inlay module for electronic cards and tags
Inventor: SINGLETON ROBERT
IPC: G06K19/077
Filed: 2007-04-09
Abstract: The disclosed electronic inlay and the method of making such an electronic inlay includes a circuit board, a plurality of circuit components attached to the circuit board, a bottom cover sheet, a top cover sheet, and a layer of thermosetting material between the bottom and top cover sheets. The electronic inlay can be used to manufacture electronic cards while using conventional equipment to apply top and bottom overlays to the electronic inlay.