Patent GB-1370219-A (GB)
Title: Virtual storage system
IPC: G06F12/10
Filed: 1972-06-28
Abstract: 1370219 Virtual storage INTERNATIONAL BUSINESS MACHINES CORP 28 June 1972 [29 June 1971] 30202/72 Heading G4A A virtual storage system includes a relatively slow access backing store 400 (Fig. 2A) and a relatively fast access buffer store 200 (Fig. 2B) to which data from the slow store may be transferred as required, the storage locations in the fast store having a data part 220 and an address part 210, a central processor unit 100 communicating with the stores using virtual addresses and input/output channels 500 communicating using real addresses. CPU Fetch.-In a fetch operation, line 101 is energized so that the 32 bit virtual address from CPU 100 on leads 105 is fed via AND gates 102 and OR gates 106 to (1) translation unit 300, which receives bits 8-19, (2) high speed buffer 200, which receives bits 8-28 and (3) gates 148 in the addressing circuitry of the main store 400, these receiving bits 20-31. The buffer 200 uses bits 8-19 to compare the virtual page address with the virtual page addresses in address buffer 210. If the address location is contained in the buffer, bits 21-28 are used for addressing a location to read out data via AND gate 122 to the CPU data buffer 131. Address translater 300 compares the virtual page address from CPU with the virtual page addresses in associative store 320, the corresponding real page address being read out at coincidence by AND gate 152, enabled by compare circuit 150, to AND gates 146. This is used in conjunction with the output of gate 148 to address main store 400. Data is read out from the store 400 when the required data is not stored in buffer 200 since the resulting "no compare" signal on lead 213 enables AND gate 126 to connect the output bus 401 from store 400 to the input bus for the CPU 100. The read out data is also transmitted to the buffer store 200 for storage. CPU Store.-In a store operation line 103 is activated so that virtual address information on leads 105 is fed via AND gates 104 and OR gates 106 for comparison with the virtual page addresses in associative store 320 and stored page addresses in buffer 200 so that, with a "no compare" signal from buffer 200 and a "compare" signal from circuit 150, gate 128 is enabled to pass data from the CPU data bus 119 to the main store 400 for entry at the address specified by the data at gates 146, 148 and, with a "compare" signal from buffer 200 gate 120 is enabled to transmit data from the bus 119 for entry into buffer 200 and also the main store 400. When in either a fetch or store operation no virtual address comparison is achieved in circuit 150, inverter 154 enables gates 156 so that a translation sequence is initiated to derive the real page address from the main store 400. This is fed on leads 313 to address translater 300 for entry into the associative store 320 together with the corresponding virtual page address. Channel Fetch.-When a channel fetch is initiated line 501 is activated so that the real address information on lines 509 is used to read out main store 400, the requested information being fed via gate 510 to the input/output channel 500.  Channel Store.-When a channel store is required line 507 is activated so that the real address is fed via AND gate 504 to main storage 400. Bits 21-28 are also applied to the high speed buffer 200 and bits 8-19 are fed to compare circuit 170 for comparison with the real page addresses stored in associative store 320. When a comparison is achieved the corresponding virtual page address is read via AND gate 174 to buffer store 200 where it is compared with the stored virtual page addresses. If coincidence is achieved gates 514 are enabled to transmit the data on bus 519 via bus 515 to the buffer 200. The data is also fed via gates 512 to the main store 400.  High speed buffer and control circuitry.-The address buffer 210 in the high speed buffer 200 includes a matrix of 64 columns by 4 blocks. Bits 21-26 of the CPU address signal or the channel address signal are decoded by decoder 2110 (Fig. 3A, not shown) to select one of the 64 columns to address a group of 4 blocks. The signals are also decoded to address a corresponding entry in a replacement array (2164). Bits 8-19 of the CPU virtual address are fed to AND gates (2112 ... 2118) one of which is enabled to transmit the virtual address for storage in a selected block. These bits are also fed to comparators (2122-2128) receiving their other inputs from the 4 blocks of the addressed column so that if the virtual address information presented coincides with the address information in one of the blocks one of four leads is enabled to generate the "compare" signal. An encoder (2152) delivers a two bit signal representing the active line. Bits 27, 28 of the virtual address information and the channel address information are fed to inputs 8, 9 of a buffer address register (2150, Fig. 3B, not shown) and a duplicate buffer address register (2180) which together with the output of the encoder (2152) and bits 21-26 of the, CPU or channel address signal designate an address for data buffer 220 which is transmitted when a "compare" signal is generated to decoders to address a double word location in the store or to read in a double word to the selected address. Replacement array (2164) is used to maintain knowledge of the activity of the data blocks during a CPU fetch operation, the replacement array containing coded data representing the block to be replaced when new data is to be stored in the high speed buffer. Alternatively data in the buffer store may be identified by real addresses in which case translation of the virtual addresses supplied by the C.P.U. is necessary.