baber/WOPTO huggingface dataset:
Patent TW-408475-B (TW)
Title: Semiconductor device with silicide layers and fabrication method thereof
Inventor: NOBUSAWA HAJIME
IPC: H01L27/04
Filed: 1999-03-03
Granted: 2000-10-11
Abstract: A semiconductor device is provided, which is capable of high-speed operation of MOSFETs in a device section while suppressing the current leakage of MOSFETs in another device section even if the device is further miniaturized. This device is comprised of a semiconductor substrate, a first section defined on the substrate, a second section defined on the substrate, and a dielectric masking layer covering the first section while uncovering the second section. The first section includes a first MOSFET with a first pair of source/drain regions, a first gate insulating layer formed on the substrate, and a first gate electrode formed on the first gate insulating layer. No silicide layer is incorporated in each of the first pair of source/drain regions. The first MOSFET is covered with the masking layer in such a way that the first pair of source/drain regions of the first MOSFET are contacted with the masking layer. The second section includes a second MOSFET with a second pair of source/drain regions, a second gate insulating layer formed on the substrate, and a second gate electrode formed on the second gate insulating layer. A silicide layer is incorporated in each of the second pair of source/drain regions.
Patent TW-393368-B (TW)
Title: Polishing pad, method and apparatus for treating polishing pad and polishing method
Inventor: TANAKA KOICHI
IPC: B24D18/00
Filed: 1999-03-09
Granted: 2000-06-11
Abstract: A polishing pad for pressing a work to be polished to a surface thereof, comprising a structure obtained by being compressed under a temperature which is higher than an operating temperature for polishing the work and/or under a pressure which is equal or higher than an operating pressure for polishing the work.  A method for polishing a work, comprising the step of polishing the work by using the polishing pad.
Patent TW-400440-B (TW)
Title: Optical demultiplexer and method for assembling same
Inventor: NAKAMA KENICHI
IPC: G02B6/34
Filed: 1999-03-11
Granted: 2000-08-01
Abstract: An optical demultiplexer as disclosed herein comprises: optical input means; a collimator lens; a substrate having a diffraction grating formed thereon, and photodetector means for detecting light beams separated by the diffraction grating, wherein the optical input means and the photodetector means are both opposed through the collimator lens to the diffraction grating which is made into a reflective type by including a reflective surface having a light-transmissive area. In order to assemble the optical demultiplexer comprising an optical input fiber, a collimator lens, a diffraction grating having thereon a reflective surface inclusive of a light-transmissive area, and photodetector means for detecting light beams separated by the diffraction grating, a method is described which includes adjusting an optical axis of the diffraction grating while monitoring a light transmitted through the light-transmissive area.
Patent TW-409409-B (TW)
Title: Dram-cells arrangement and its production method
Inventor: GOBEL BERND
IPC: H01L21/8242
Filed: 1999-03-17
Granted: 2000-10-21
Abstract: A memory-capacitor is connected between a first source/drain-region (S/D1a) of a vertical selection-transistor and a bit-line (Ba), since the memory-capacitor and the bit-line (Ba) are arranged basically above a substrate (1a), the bit-line (Ba) can be produced from the materials with higher conductivity, and materials with high dielectric-constant can be used for the memory-capacitor. At least the first source/drain-region (S/D1a) and a channel-region (Kaa) are portions of a protrusion-shaped semiconductor-structure (STa), which is adjacent on the side by at least two edges. On the two edges can be arranged a word-line respectively. Between the channel-region (KAa) and one of the word-lines is arranged an element (Ca), which can prevent the selection-transistor from being controlled by said word-line, a second source/drain-region (S/D2a) of said selection-transistor is embedded in the substrate (1a) and is a part of a doped layer (S/a) or a grid-shaped doped region or is through an embedded contact connected with the substrate (1a). A memory-cell can be produced with an area of 4F<2> either by open bit-lines or by folded bit-lines.
Patent TW-419845-B (TW)
Title: Push-pop coin cell battery compartment
Inventor: CHOW KIT-MAN
IPC: H01M2/02
Filed: 1999-03-24
Granted: 2001-01-21
Abstract: A push-pop coin cell battery compartment, wherein a battery is exchanged without losing a stored data and without using a back-up battery, comprising: a tunnel for slidablely receiving the battery; a terminal member, provided in the tunnel and electrically connected to one of electrodes of the battery, for supporting the battery; and a terminal provided in the tunnel an electrically connected to the other one of the electrodes, so that while the battery forced out from the tunnel is electrically connected to the terminal member and the terminal, another battery pushed into the tunnel is also electrically connected to the terminal member and the terminal.
Patent TW-460502-B (TW)
Title: Novel process for the preparation of copolyesters
Inventor: YOU WU-BIN
IPC: C08G63/00
Filed: 1999-04-23
Granted: 2001-10-21
Abstract: The traditional processes for the synthesis of copolyesters are used dimethyl terephthalate (DMT) process or terephthalic acid (TPA) process. The terephthalic acid (TPA) process is made use of terephthalic acid, ethylene glycol and comonomers as starting materials, or the intermediate of terephthalic acid and ethylene glycol -bis-hydroxyethylene terephthalate (BHET) as raw materials is synthesized copolyester with comonomers. Moreover, the dimethyl terephthalate (DMT) process is used dimethyl terephthalate, ethylene glycol and comonomers as materials, or otherwise the intermediate of dimethyl terephthalate and ethylene glycol -bis-hydroxyethylene terephthalate (BHET) as raw materials is synthesized copolyester with comonomers. However, the novel process for the preparation of copolyester is used PET [poly(ethylene terephthalate)] and comononers as raw materials.
Patent TW-444066-B (TW)
Title: Method of tantalum oxide layer fabrication
Inventor: JANG SHR-JUNG
IPC: C23C16/00
Filed: 1999-05-31
Granted: 2001-07-01
Abstract: A method for fabrication of a tantalum oxide dielectric layer. The present invention uses a conventional method to form a n-channel MOSFET with source/drain area formed in a semiconductor substrate, then a doped polysilicon layer is connected to the source area to form a first electrode of the capacitor. Afterward, a remote plasma chemical vapor deposition method is used to form a oxygen-based plasma in a remote chamber, then input to the main chamber to react with vaporized organic metal compound such as Ta(OC2H5)5 or Ta(OC2H5)4(OC2H4)N(CH3)2) to form a deposition of tantalum oxide dielectric layer, then a second electrode is formed on the tantalum oxide layer to complete the invention. During the deposition of tantalum oxide dielectric layer, the excited oxygen-based plasma is reacted with organic compound impurities simultaneously and evacuates by a vacuum system, therefore a high quality tantalum oxide can be formed.
Patent TW-435035-B (TW)
Title: Method and apparatus for integrity verification, authentication, and secure linkage of software modules
Inventor: GRAUNKE GARY L
IPC: G06F21/00
Filed: 1999-07-13
Granted: 2001-05-16
Abstract: A method and apparatus of authenticating and verifying the integrity of software modules is disclosed. In one embodiment, said software modules initially establish their corresponding credentials. Then said local software module ensures its integrity by validating its own digital signature. Said local software module authenticates the integrity of said partner software module after having derived and validated certain information from said partner module's credential. In addition, secure linkage between said local software module and said partner software module is maintained.
Patent TW-432705-B (TW)
Title: Non-volatile semiconductor memory device and process for producing the same
Inventor: IWASAKI SHOTA
IPC: H01L21/8247
Filed: 1999-07-21
Granted: 2001-05-01
Abstract: In a non-volatile semiconductor memory device making electrical writing and erasing possible, source diffusion layers arranged on a substrate and along at least control gate electrodes have, in one part thereof, inclined portions having an angle larger than an ion implantation angle. According to this, device isolation technique is used to lower the resistance of the source diffusion layer.
Patent TW-480211-B (TW)
Title: Robot having multi-joint arms movable in horizontal plane
Inventor: WAKAIZUMI KIYOSHI
IPC: B25J9/04
Filed: 1999-07-28
Granted: 2002-03-21
Abstract: Disclosed is a robot with multi-joint arms movable in a horizontal plane, which is mechanically compact as well as small sized and operated with high precision and a minimum output of drive sources, substantially comprising a robot body (1), a cylindrical mount (2) movable vertically of the robot body through a guide means (3) and a slider means (4), a vertical threaded shaft (6) rotatably journaled in the robot body and operatively connected to the cylindrical mount, the vertical threaded shaft being rotated by a first drive motor (5) to vertically move the cylindrical mount therealong, a first arm (9) with one end operatively connected to the cylindrical mount so as to be turningly moved in a horizontal plane by a second drive motor (12), a second arm (10) having one end operatively connected to the opposite end of the first arm so as to be turningly moved in a horizontal plane by a third drive motor (17), and a control R shaft (11) rotatably mounted on a free end of the second arm so as to be rotated by a fourth drive motor (18).
Patent TW-455821-B (TW)
Title: Signal process method and device
Inventor: CHEN OSCAL TZYH-CHIANG
IPC: H04N7/26
Filed: 1999-09-03
Granted: 2001-09-21
Abstract: The present invention relates to a method and a device for signal process that combines coordinate axis transformation and quantization together to make input data adaptive without performing any characteristic analysis on input data in advance. For any operation result that requires combination of coordination axis transformation and quantization, the estimated operation result and quantization are used for preliminary calculation to simplify the overall calculation. By means of a quantization table, the present invention can also make calculation, image quality, and bit rate adaptive.
Patent TW-546280-B (TW)
Title: Process for preparing higher oxo alcohols
Inventor: KAIZIK ALFRED
IPC: C07C29/16
Filed: 1999-09-08
Granted: 2003-08-11
Abstract: The invention relates to a process for preparing higher oxo alcohols from mixtures of isomeric olefins having from 5 to 24 carbon atoms by hydroformylation in the presence of a catalyst at elevated temperature and at elevated pressure, in which the hydroformylation is carried out in one stage, the olefin conversion rate for one pass is restricted to from 40 to 90% the reaction mixture, expediently after catalyst removal, is selectively hydrogenated mixture is separated by distillation and the olefin fraction is recirculated to the hydroformylation.
Patent TW-504516-B (TW)
Title: Method for producing reduced iron agglomerates
Inventor: MATSUSHITA KOICHI
IPC: F27B9/16
Filed: 1999-10-22
Granted: 2002-10-01
Abstract: A moving hearth is formed by providing a layer of hearth material primarily composed of iron oxide on a base refractory in a reducing furnace and then sintering the hearth material so that the sintered moving hearth is not melted at an operational temperature in a reducing step. The moving hearth is more easily constructed compared to providing a shaped or amorphous refractory on the base refractory, has high durability, and can maintain surface flatness during operation.
Patent TW-548685-B (TW)
Title: Digital analog converter
Inventor: AZAMI MUNEHIRO
IPC: H03M1/74
Filed: 1999-11-30
Granted: 2003-08-21
Abstract: The present invention relates to a D/A converter circuit which is capable of independently controlling the output voltage amplitude VOUT and the reference voltage. The D/A converter circuit converts ""n"" bit digital data (""n"": natural number) to analog signals, wherein the respective bits of said ""n"" bit digital data control a switch, control charge and discharge of electric charges in the capacitance connected to said switch, and output analog signals with the offset potential used as a reference potential.
Patent TW-455759-B (TW)
Title: Method and apparatus for information embedding in image data
Inventor: YOSHIURA HIROSHI
IPC: H04N21/8358
Filed: 1999-12-02
Granted: 2001-09-21
Abstract: The present invention discloses a method and apparatus capable of suppressing the quality degradation of contents and increasing the survivability of embedded watermark information. When embedding the watermark information in moving picture data formed of a plurality of still picture frames arranged in time series, a motion vector representing a property specific to moving picture is detected for each of image blocks generated by dividing a target frame. According to the amount of motion, a pixel change factor specifying rule is selected for each block. Out of pixels permitted to be changed in luminance depending upon the state of an image in each block representing a property specific to still picture, a specified number by the selected rule are selected. Luminance change processing for forming watermark information is conducted on the selected pixels.
Patent TW-522651-B (TW)
Title: Delay locked loops and methods that shift the phase of a delayed clock signal based on a reference phase value
Inventor: LEE SANG-BO
IPC: G06F1/10
Filed: 2000-01-04
Granted: 2003-03-01
Abstract: A delay locked loop generates an advanced clock signal synchronized with a reference clock signal. The delay locked loop includes an input buffer, a variable delay circuit, a delay compensation circuit, a phase shifter, a delay controller, a phase sensing pump and a phase inversion controller. The variable delay circuit includes a multiplicity of delay terminals. The number of enabled delay terminals is controlled by a counting signal group. In the phase shifter, the phase of an output signal of the variable delay circuit generates the advanced clock signal with a phase of the reference clock signal. When the compared phase difference is more than π, the phase shifter inverts a delayed clock signal to generate the advanced clock signal. When the compared phase difference is less than π, the delayed clock signal is non-inverted to be generated as the advanced clock signal.
Patent TW-453062-B (TW)
Title: System for the estimation of the complex gain of a transmission channel
Inventor: LAURENT PIERRE-ANDRE
IPC: H04L27/26
Filed: 2000-02-21
Granted: 2001-09-01
Abstract: A system for the estimation of the complex gain of a transmission channel is designed for parallel type modulators/demodulators that can be used in digital radio broadcasting. The system comprises a given number N of sets of interpolators to estimate the gain on a useful symbol from known symbols constituting gain references evenly positioned in the transmitted signal, each set of interpolators being adapted to a particular situation of reception, ranging from a stable single-path channel to a channel with high temporal dispersion and high instability. The outputs of the interpolators are coupled to a selection device programmed to choose the set of interpolators that gives the weakest estimated noise during a specified length of time. Application to digital radio transmission.
Patent TW-494245-B (TW)
Title: Radio frequency identification tag device with sensor input
Inventor: SORRELLS PETER
IPC: G01S13/79
Filed: 2000-05-02
Granted: 2002-07-11
Abstract: A radio frequency identification tag device having a sensor input which modifies a tag data word bitstream read by an interrogator/tag detector. The sensor input may be a switch contact(s), digital and/or analog. The sensor input may be voltage, current, pressure, temperature, resistance, acceleration, moisture, gas and the like. Power from the radio frequency interrogator/tag reader may be used to power the circuits of the radio frequency tag device, which in turn may supply power to any sensor connected thereto.
Patent TW-555546-B (TW)
Title: Body fat meter
Inventor: CHEN JAU-CHIUAN
IPC: A61B5/107
Filed: 2000-04-19
Granted: 2003-10-01
Abstract: A body fat meter comprises an optical sensor installed on the meter body; the optical sensor comprises an emission end and a receiving end; when a user uses its sensing part to contact the optical sensor, the variation in the signals sensed by the optical sensor is recorded and converted to be displayed on at least a display on the body of the meter for the user to determine the amount of the user's body fat.
Patent TW-523567-B (TW)
Title: Crook hollow metal
Inventor: LI CHENG-YUAN
IPC: E04C5/01
Filed: 2000-06-02
Granted: 2003-03-11
Abstract: The Crook Hollow Metal was make by an external of granular as crooked and twist. It's show form looked as three-dimensional from the outside and show a hollow type at inside. Also it's got rough and uneven on the surface of the structure. When the Crook Hollow Metals were mixed with concrete and together with the structure of concrete of a integer object that could be blend them place in every nook and surface with the concrete object. Even the steel bar can not to extend and can not to reach at each corner entirety of the concrete object. Consequently the Crook Hollow Metal were intense compact with the concrete jointly together that can be substitute for compressive resistance and to strengthen resembling an efficacy as a steel bar. When the object of concrete model with mixed to blend the Crook Hollow Metals. This type had efficiency that can to make it add firm for the concrete model and to rigid them successful compressive resistance even being the case without the steel bar.
Patent TW-482699-B (TW)
Title: Method for improving lubrication in rolling
Inventor: HUTTUNEN KARI
IPC: B21B27/10
Filed: 2000-06-05
Granted: 2002-04-11
Abstract: The invention relates to a method for improving the lubrication of the edges and ends of objects to be rolled, particularly not rolled, said objects consisting of essentially planar surfaces and being for example metal sheets of strips. According to the invention, the lubricating medium is fed so that it is applied on the edge area of the object to be rolled (1, 21, 31), essentially during the whole rolling pass, and so that lubricating medium is applied, when beginning or finishing a rolling pass, essentially along the whole width of the object to be rolled (1, 21, 31), in the immediate vicinity of the ends of the object to be rolled.
Patent TW-544598-B (TW)
Title: Multidimensional database system with intermediate lockable intersections
Inventor: REDDY VENUGOPAL P
IPC: G06F17/30
Filed: 2000-09-01
Granted: 2003-08-01
Abstract: A multi-dimensional database includes hierarchical levels. The data is hierarchical, with aggregatable data measures, so that changes in a first intersection will cause changes in other intersections for the aggregated measure. Selected intersections can be locked, so that changes in aggregatable data are restricted. Constrained sets corresponding to the locked intersections limit the scope of changes which may be made, and ensure a high level of efficiency.
Patent TW-480542-B (TW)
Title: Method of manufacturing a cathode ray tube
Inventor: KHALIL MOHAMMED
IPC: H01J9/24
Filed: 2000-09-20
Granted: 2002-03-21
Abstract: To increase the strength of the glass panel of a CRT, the temperature of the glass panel is reduced during reforming from a temperature above, preferably at least 30 DEG C above the annealing point, to a temperature well below, preferably at least 80 DEG C below the strain point. This induces high surface compression in the glass panel, paired with a low rate of compaction. The glass panel is subsequently not subjected to the usual annealing step.
Patent TW-461007-B (TW)
Title: Thin film test apparatus and its test method
Inventor: JENG CHIOU-SHIUNG
IPC: H01L21/66
Filed: 2000-10-03
Granted: 2001-10-21
Abstract: The present invention provides a kind of thin film test apparatus and its test method, and is used to test an object to be tested, which has plural circuit contacts. The thin film test apparatus includes a base stage and a thin film on its top. Many conductive contacts are formed on the thin film so as to make them contact with the circuit contacts on the object to be tested and form the electric connection. A fixed stage is installed on top of the base stage, and a combining means is used to make the fixed stage move downwards and apply pressure to the object to be tested such that circuit contacts of the object to be tested are made to tightly contact with the conductive contacts of the thin film in order to perform the test by using the conductive contacts to transmit the test signal to the object to be tested. The present invention can be used to test the unpackaged chips and the integrated circuit apparatus that are packaged completely, and the application is quite widespread.
Patent TW-548896-B (TW)
Title: A sampling device having an intrinsic filter
Inventor: BANU MIHAI
IPC: H03H17/02
Filed: 2000-11-24
Granted: 2003-08-21
Abstract: A sampling device for sampling an input signal having intrinsic filter properties. The sampling device samples a continuous analog input signal according to a sampling signal. The sampling device includes a first sampling switch for sampling the input signal, in response to a sampling signal, to create a first set of samples. Furthermore, the sampling device incorporates a time delay device for time delaying the first set of samples. The sampling device also includes a phase shift device for phase shifting the input signal. The phase delayed input signal is then fed into a second sampling switch for sampling in response to the sampling signal to create a second set of samples. Further, a summer is incorporated to sum the first set of samples with the second set of samples to create the output samples.
Patent TW-499734-B (TW)
Title: Substrate with at least two metal-structures and its production method
Inventor: SCHWARZL SIEGFRIED
IPC: H01L23/522
Filed: 2000-11-28
Granted: 2002-08-21
Abstract: The metal-structure (MS) can be generated through a damascene-process and are arranged in a 1st isolated layer (I1) and a 2nd isolated layer (I2) that is arranged above the 1st isolated layer (I1). Between the metal-structures (MS) is arranged at least a hollow-space (H), which is arranged in the 1st isolated layer (I1) and is covered by a 2nd isolated layer (I2). The hollow-space (H) and the metal-structures (MS) can be generated through self-adjusted process-steps parallelly.
Patent TW-508669-B (TW)
Title: Process for fabricating a uniform gate oxide of a vertical transistor
Inventor: FALTERMEIER JOHNATHAN E
IPC: H01L21/28
Filed: 2001-03-13
Granted: 2002-11-01
Abstract: A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a 100 crystal plane and a 110 crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the 110 crystal plane of the trench side wall, but not into the 100 crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.