Patent GB-716322-A (GB)
Title: Improvements in or relating to means for electrically converting a number from the binary to the denary scale of notation
IPC: H03M7/08
Filed: 1951-07-20
Abstract: 716,322. Digital electric calculating-apparatus. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. July 20, 1951 [July 20, 1950], No. 17310/51. Class 106 (1) In an electrical apparatus for converting a number from the binary to the decimal scale, a series-mode pulse train of N terms at 1, Fig. 1, representing a binary number, is applied simultaneously to ten comparison channels in nine of which it is combined in an adding circuit 7 with N-term series-mode pulse trains, produced in devices 8, representing the complements of binary numbers corresponding to decimal reference values Y x 10<SP>M-1</SP>, Y=1-9, any carry pulse which would otherwise form a digit pulse in the N+1 position of the combined train being suppressed and diverted by means 14 to terminals 15 connected to analysing means 16 adapted to detect two consecutive comparison channels of which one but not the other produces such a carry pulse and to close a corresponding switch 12 so as to allow one of the combined trains or the input train applied to the tenth comparison channel 10, delayed by N pulse times in elements 11, to appear on return channel 13, and, after multiplication by ten at 4, to be re-applied via 3 to the comparison channel inputs. The cycle of operations is then repeated and, at each stage, an indication is given of the identity of the appropriate comparison channel corresponding to the decimal digit resulting from that part of the conversion operation, e.g. by a signal on an appro-- priate line 17 which is used to operate a register such as an oscilloscope with means for photographing the screen. Each adding circuit 7 may include carry-over pulse-train-connecting means as described in Specification 716,172, and the encoding devices 8 may be as described in Specification 679,390. As shown in Fig. 4, the analysing means comprise transformers 48 whose primaries are connected through resistors to consecutive terminals 15. Simultaneous pulses at two terminals cancel each other out but if a pulse appears on the lower but not the upper terminal associated with one transformer it will be applied to gate tube 49 which is opened at pulse time N by a positive pulse (from programming circuits, (not shown), applied to terminal 50 this pulse also being applied to transformer 48‹ to represent the " carry " from the tenth comparison channel. The output of each tube 49 is connected through a short delay element 52 to a bi-stable trigger circuit 51 which, if actuated, applies an opening potenial to associated gate tube 12 until reset by a programme impulse applied through delay element 53. The outputs of 49‹-49<SP>8</SP> are also applied to taps on a delay line 64, spaced apart by one digit pulse interval °, so as to provide on output channel 65 a position-modulated pulse representing the appropriate decimal digit. Alternatively, the line 64 can be connected directly to terminals 15 the decimal digit then being defined according to the number of pulses on the line. In a modification (Figs. 2 and 3, not shown) in which the first pulse of the series mode input train represents the sign of the binary number, this pulse is diverted to sign-registering means, and the remainder of the train is divided by two by a delay element of length (N-1) ° the reference values produced in devices 8 being halved also.