Patent EP-0096381-B1 (EP)
Title: Receiver with electronically tunable tuning circuit
IPC: H03J7/18
Filed: 1983-06-03
Granted: 1986-10-15
Abstract: 1. A consumer electronics receiver - with an electronically tunable tuner circuit (1), - also with an automatically settable tuning circuit (7, 51) connected to one tuning input (2) of the tuner circuit, comprising a start input (11) for tripping a new tuning setting, - furthermore with a data separating circuit (16) connected to a signal path (5) connected after the tuner circuit (1) which, from a composite signal present on the signal path (5), separates a station program data record (12) marked by a special type-of-record identification word (13) containing station identification words (14) and station program words (15) in digital signal form and which, moreover, transmits at one data output (D16) the data words contained in the data record, and produces at one clock output (T16) the call clock required for the data output, - and with an evaluating circuit connected to the data output and the call clock output of the data separating circuit (16), in which selected station program data are stored and in which the data of the received station program data record are evaluated with the aid of the selected station program data, characterized in - that the evaluating circuit contains a first storage circuit (18) connected to the data output (D16) of the said data separating circuit (16), for the received station program data (14, 15), with a connected read-in control circuit (20), a second storage circuit (34) for storing the selected station program data, with, connected to it, a readout control circuit (39) which is controlled by a clock pulse generator (40), and a comparator (31) connected between the data outputs (29, 33) of said two storage circuits, - that the output (T16) for the call clock of the data separating circuit is connected to one clock input (T20) of the read-in control circuit (20), - that to the read-in control circuit (20) there is connected a pulse delay circuit (26, 54) which is capable of being triggered by a signal from said read-in control circuit (20) and, after a time delay (T26) which is equal to or greater than the sum of the time remaining after the trigger signal for reading into the first storage circuit for the received station programm data and the read-out time of the two storage circuits, produces an output signal, - that the output of said pulse delay circuit (26, 54) is connected, via a gate circuit (47), to the start input (9, 52) of said tuning circuit (7), - that there is connected to the output (37) of the comparator (31) a pulse expander circuit (38) which, at its output, expands each pulse on the input side to a pulse width which is greater than the time between the beginning of two successive processes of reading into the first storage circuit (18) for the received station program data, - that the output of the pulse expander circuit is connected to the blocking input (Sp) of the gate circuit (47) and - that to one read signal output (53) of the read-in control circuit (20) and to the output of the pulse expander circuit (38) there is connected a logic operation circuit (42) which, in response to a signal appearing at one of the two outputs, puts said comparator (31) into operation.