Patent GB-1082754-A (GB)
Title: A decimal magnetic core matrix computing device
IPC: G06F7/48
Filed: 1964-09-01
Abstract: 1,082,754. Digital computers; data storage apparatus. NIPPON SIGNAL CO. Ltd. Sept. 1, 1964 [Sept. 28, 1963], No. 35724/64. Headings G4A and G4C. A decimal magnetic core matrix computing device comprises an input register, an arithmetic register, an accumulator and a plurality of totalizers, each being composed of a matrix of decimal function magnetic cores arranged to store one computer word in each horizontal line of cores, a counter for temporarily storing digital information, a pulse shaping circuit producing a train of pulses for energizing the cores, an arithmetic circuit consisting of a plurality of gates and flip-flops and a subcommand encoder producing a control signal to select the mode of operation of the arithmetic circuit. Each core has a square hysteresis loop (Fig. 2, not shown) such that a number of input pulses may be applied to it and the magnetic flux will rise to a point corresponding to the number of pulses, with the excitation current increasing sharply when 10 pulses have been applied, the increase being detected and used to form a carry. The pulses necessary to perform the storage are provided by a circuit illustrated in Fig. 4 (not shown). The appropriate row of cores to be read or written into is selected by appropriate addresses in the instruction word (Fig. 5, not shown), two four-digit addresses being given in a 14-digit word. The particular digit written or read is selected by a counter. An example of an addition operation is shown in Fig. 18. In this example numbers 56 and 27 are added together, the ith and (i+1)th digits of the read cores storing 6 and 5 respectively and the ith and (i+1)th digits of the write cores storing 7 and 2 respectively. Mathematical operations are carried out in state 3 of the machine and transfers occur in cycle T. Digit i is selected by a counter MC and a 10 counter adds pulses to the number 6 stored in the read core during read band RB 1 until number 10 is reached. At the same time counter NCC is decremented from 10 for each pulse. When the core reaches 10 flip-flop NMF is set and read band RB2 is commenced and the 10-counter continued to 10 to write the stored number back into the read core. When the 10 counter reaches 10 Write Band WB1 is selected and the write core is selected by counter MC. Flip-flop NMF is reset and Write Band WB2 is selected, whereon counter NMC which now stores the number 6 is decremented to zero and the pulses produced are added to the write core. When the write core reaches 10 a carry signal CRT is produced which sets the carry flip-flop CYF. When counter NMC reaches zero the Set Band SB is entered causing NMC to be reset to 10 and 1 to be added to counter MC Read Band RB, is entered and the 10-counter started. However, due to the carry flip-flop CYF being set the first pulse from the 10-counter resets CYF and does not decrement NMC. The rest pulses then add to the read core and decrement the counter NMC until the read core stores 10. NMC is then held at 6 while the number 5 is replaced in the read core. The write core is then incremented while NMC is decremented and finally stores 8. The result of the sum being 83=56+27. Multiplication can be carried out by repeated addition and division by repeated subtraction. Nines complements can be provided for negative operations (Fig. 20, not shown).