Patent GB-1435320-A (GB)
Title: Methods of manufacturing semi-conductor devices
IPC: H05K3/24
Filed: 1973-04-25
Abstract: 1435320 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 25 April 1973 [28 April 1972] 19596/73 Heading H1K Conductive tracks which overlie an insulating layer of a planar semi-conductor device and contact zones of the device through apertures in the layer are formed by depositing lower and upper auxiliary layers over the insulating layer, forming therein a pattern of apertures corresponding to areas where conductive tracks are not required, the apertures being somewhat larger in the lower auxiliary layer due to undercutting, depositing one or more conductive layers overall and then etching away either or both of the auxiliary layers in order to remove the overlying conductive layers to leave the desired tracks in the apertures. Particularly if the combined thickness of the auxiliary layers is greater than that of the conductive layers the undercutting causes discontinuity or thinning of the conductive layers at the edges of the apertures, this facilitating etching of the auxiliary layers and detachment of the overlying material. Further improvement is achieved by providing holes in the auxiliary layers additional to those required for the track pattern. Undercutting is facilitated by making the upper auxiliary layer much the thinner and is increased by prolonged etching of the lower layer. If sputter etching is used in forming apertures the requisite undercutting is ensured by finishing then by chemical etching. In a first embodiment the conductive tracks are of gold, preferably embrittled by inclusion of arsenic, boron, or nickel, or of aluminium. The upper auxiliary layer is of photolacquer and the lower, which is of copper or silver, is bonded to the surface by a thin layer of titanium, chromium or aluminium and subsequently etched away in nitric acid. In the preferred embodiment interdigitated emitter and base electrodes with associated bonding pads are provided for an HF silicon transistor. Aluminium and chromium respectively are used for the lower and upper auxiliary layers. The chromium, in which apertures are formed by a photolithographic technique, is used to mask the etching of the aluminium. After etching in buffered hydrofluoric acid to clear the contact holes an optional layer of aluminium or of silicide of cobalt, platinum, or palladium is provided in the holes by sputtering. Then a thin layer of titanium is sputtered or vapour deposited overall, followed by a thicker layer of gold. Optionally a layer of rhodium or platinum is interposed between them. Successive depositions are made with the source in the same position relative to the device, and any of the depositions may be confined to certain areas by masking. A simpler layer structure consisting of a layer of rhodium with a thin overlayer of gold or of a single layer of tantalum may alternatively be used. The aluminium auxiliary layer is next dissolved away in a mixture of ferric chloride and hydrochloric acid, the loosened overlying material knocked off by a jet of water, gold wire contacts provided and the device encapsulated. Various alternative materials are listed for the component auxiliary and conductive layers and layer thicknesses and etching compositions specified. The conductive layers may alternatively be deposited by electrochemical plating and reinforced by electroless plating after patterning. When providing devices in multiple on a wafer the auxiliary layers are also provided at the location of scribing lines to facilitate later subdivision.