Patent GB-889290-A (GB)
Title: Improvements in or relating to data processing equipment
IPC: G06F9/308
Filed: 1960-01-26
Abstract: 889,290. Digital electric calculating. BURROUGHS CORPORATION. Jan. 26, 1960 [Jan. 26, 1959], No. 2772/60. Class 106 (1). In a serial-mode, sequence-controlled computor the sequence and digit counters 68, 70 (Fig. 2), are stepped by a clock 60, the sequence counter only when the digit counter is at a predetermined count and the digit counter only when other than at the predetermined count, means are provided to set the digit counter at any count thus determining the number of clock intervals in any sequence count interval. The sequences of " fetch," i.e. transferring an instruction from memory 12, preferably a magnetic core store, located at the address specified by instruction counter 22, to the C- or control-register 50, and " add " are described. The sequence counter is of the binary cascade type reset to zero by a signal OC, the settings of the stages of which are interpreted in circuit 72 to mark one of the lines SC = 0 ... SC = 15. Digit counter 70 is similar but the decoding circuit 74 marks only one line representing a particular count, in this case 20. When the digit count is 20 gate 64 is open and SP pulses issue, at other counts DP pulses issue. The count of digit counter 70 may be set at any value by circuit 78 acting on circuit 80. Two typical control sub-circuits of circuit 78 are shown in Figs. 3 and 4. Fetch operation (Fig. 3). This is determined by an execute toggle 82 being in the 0 state to raise one input of controlling and circuits 84, 86 ... At SC = 0 and circuit 84 opens gate 18 (Fig. 1) to set memory 12 in the read condition by the passage of the next SP. At SC = 1 and circuit 86 opens gate 25 setting up the 4- digit address held in the counter 22 in an address buffer 14. At SC = 2 and circuit 88 opens gate 20 and the next SP transfers the instruction at the address held in buffer 14 in parallel to an instruction buffer 16. At SC = 3 the instruction is shifted from buffer 16 to C-register 50 and provision is made that if the digit in the sign position of the instruction is odd the operand address contained in the instruction is to be modified by the address in B-register 39. If the sign digit is odd line 1BSG-1 is high and and circuit 90 opens a gate 92 permitting the next SP to set a sign toggle 94 to " 1." At the same time and circuit 96 sets the digit counter 70 at the count of 16. At SC = 4, the sequence counter having been advanced by the SP that set toggle 94, and circuit 98 is operated to open the gates 26, 32 and 52 to shift pulses and the gates 30, 36 and 48 to digits of the instruction. Additionally, if the sign trigger has been set to " 1 " and if the digit counter is not at a count of 20, gate 41 is opened to shift pulses and gate 43 to the contents of the B-register. Since the output of decoder 74 is now low gate 66 is opened and DP pulses, advancing counter 70, issue. These cause the four operand address digits in the instruction in buffer 16 to be shifted into D- register 28, and through the adder 34 in synchronism with the contents of B-register 39, to the C-register 50. And circuit 104 is also operated during SC = 4 to prepare circuit 80 for setting the digit counter 70 at a count of 15. When the digit count reaches 20 and circuit 102 is operated to clear adder 34 on the occurrence of the next SP, which steps the sequence counter to SC = 5 and sets the digit counter at 15 whereupon with and circuit 98 still operated the information gates remain open and a further six digits of the instruction are transferred to the C- and D-registers 28, 50 (one digit by the SP and five digits by the digit count from 15 to 20 producing DP's). At SC = 5 and circuit also is operated to open gates 24 and 108. When the digit count reaches 20 and the next SP issues these gates pass it to step the address counter 22 and to provide the end of operation pulse OC which resets the sequence counter to zero, the execute toggle 82 to " 1 " and the sign toggle 94 to " 0." Add operation (Fig. 4). This requires that the contents of A-register 38 be added to the operand specified by the address of the instruction in C-register 50 the sum being placed in the A-register, and is determined by the execute toggle being in the " 1 " condition and an appropriate line from operation decoder 112 being marked, in which case and circuit 114 is operated. At SC = 0: gate 18 is opened by and circuit 116 to prepare the store 12 for read-out. At SC = 1: gate 54 is opened by and circuit 118 and the address in C-register 50 is set up in register 14; the sign of the word in A-register 38 is sensed and if odd (indicating a negative number) and circuit 120 operates to open gate 122 to the next SP which sets an SUT toggle 35 so that subtraction will take place in adder 34, and stores the sign in toggle 134 by switching it to " 1." At SC = 2: and circuit 126 opens gate 26 and gate 128 respectively on the next SP to transfer the operand to register 16 and clear the sign from A-register 38. At SC = 3: if the sign of the operand in register 16 is negative line 1SBG-1  is high and and circuit 130 operates the sign toggle 94 (Fig. 3); and circuit 132 prepares circuit 80 so that the next SP will set the digit counter to 9 and opens gate 134 so that the next SP clears the sign from register 16; and circuit 136, operated if the sign of the operand is negative, opens gate 138 for the next SP to switch SUT toggle 35, thus if two negative numbers are involved addition will take place in adder 34. At SC = 4: the digit counter not being at a count of 20, and circuit 140 opens gates 26, 32 and 40 for the passage of DP shift pulses and gates 30, 36, 47 and 40 to information; there follow eleven DP's during which the operation takes place; if there is no carry from the highest order of the adder on the digit counter reaching 20, the next SP issues and the sequence counter steps to SC = 5; if however there is a carry and circuit 142 operates ; if the carry is in an add operation, SUT toggle 35 being at " 0," an overflow is signalled by the next SP through gate 146 and the machine stops; if the operation is subtraction and circuit 148 operates to cause the contents of A-register 38 to be subtracted from zero; the sign toggle 124 is complemented and the digit counter set to 9 by the next SP. The complementing operation is under the control of AND circuit 152 during SC = 5. Finally, when the counter reaches 20 and circuit 154 operates to produce an end of operation signal TP which opens gates 158, 160 so that the sign in the toggle 124 is written in the A-register. Specification 750,475 is referred to.