baber/WOPTO huggingface dataset:
Patent TW-373318-B (TW)
Title: Semiconductor device and the manufacturing method thereof
Inventor: INABA SATOSHI
IPC: H01L27/04
Filed: 1998-02-18
Granted: 1999-11-01
Abstract: This invention is related to a DRAM combining the memory unit and its periphery circuits. Its main characteristics comprises of: capable of self-aligning the first insulating gate transistor on the micro gate contact hole; a second insulating gate transistor with one side capable of suppressing short channel effect and the other side capable of moderating parasitic resistance on the same substrate. The solution, for example, is the creation of following single cell regions on the semiconductor substrate applying the principle of minimum space to form even numbers of MOSFETs, and gate sidewalls for all gates using sidewall insulating film, and at least one MOSFET for the periphery circuit region with sidewall insulating film as gate sidewall.
Patent TW-360960-B (TW)
Title: Semiconductor laser package with power monitoring system
Inventor: KIELY PHILIP
IPC: H01S5/183
Filed: 1998-03-11
Granted: 1999-06-11
Abstract: A semiconductor laser package including a plastic resin housing for encapsulating a vertical cavity surface emitting laser. The semiconductor laser package including a mounting base, a surround can and a cap. The cap having integrally formed therein a power monitoring system, such as a photodetector. The vertical cavity surface emitting laser generating an emission along a path. The photodetector optically positioned to receive a portion of the emission. The power monitoring system including a plurality of layers of an amorphous silicon material and/or a germanium material.
Patent TW-408522-B (TW)
Title: Electronic circuit
Inventor: MCDONALD ADRIAN
IPC: H03K17/06
Filed: 1998-03-11
Granted: 2000-10-11
Abstract: A voltage doubling circuit provides an output voltage, for supply to a capacitive load, which is nearly double the positive supply voltage. During one phase of a clock signal, a capacitor is charged so that the positive supply voltage appears on terminal and the negative supply voltage appears on the other terminal thereof while, during the other phase of the clock signal, the terminal formerly held at the negative supply voltage is clamped to the positive supply voltage, and the output increases to nearly double the positive supply.
Patent TW-I240372-B (TW)
Title: Fabrication method for self-aligned passivation of damascene interconnect structure
Inventor: SHUE SHAU-LIN
IPC: H01L21/768
Filed: 1998-04-17
Granted: 2005-09-21
Abstract: The present invention provides a fabrication method for self-aligned passivation of damascene interconnect structure, which is characterized by using a layer of copper alloy in coordination with a planarization process of chemical-mechanical polishing to fill the copper alloy into a dishing area on conductors; the copper alloy can be in-situ self-oxidized as a self-aligned passivation to protect the metal interconnect underneath during the following deposition of inter-metal dielectric (IMD).
Patent TW-373240-B (TW)
Title: Gate electrode definition removal hard cover method
Inventor: TAO HONG-YUAN
IPC: H01L21/027
Filed: 1998-05-25
Granted: 1999-11-01
Abstract: A kind of gate electrode definition removal hard cover method: first, after forming shallow trench isolation (STI) on semiconductor substrate, and to orderly form gate electrode layer and hard cover to the entire substrate surface, and then, the said gate electrode layer and hard cover to be added with image defined gate electrode structure, and then, forming a buffer layer on the entire semiconductor substrate surface, the following step is the major point of this invention, it is in the same etch reaction room, by using 3 stage dry etch to delete the said hard cover, the said first step etching is under the environment of oxygen plasma partially etch the said buffer layer for exposing the said hard cover, following to process the second stage etch to remove the said hard cover, finally the third stage etch is to remove the remaining buffer layer, finally, processing the said self-aim silicification, forming metal silicon substance exposing gate, source and draw electrode on surfaces.
Patent TW-382711-B (TW)
Title: Semiconductor memory and information storing apparatus
Inventor: KATAYAMA KUNIHIRO
IPC: G11C16/02
Filed: 1998-05-26
Granted: 2000-02-21
Abstract: To realize multi-level memory technology without deterioration of data read characteristic and increase of chip area. A write control means 42 sets, to the relevant cell, a potential level depending on the value indicated by a bit data stream, in which the bit data stored in the buffers A5, B6 memorized in the cell are arranged in the sequence of the buffers A5, B6. The read control means 44 is provided with a discriminator corresponding to such cell. The discriminator sets the threshold voltage to the potential level depending on the number of times of discrimination for the corresponding cell and the discrimination result when the discrimination process is already performed to such cell. As a result, the bit data is discriminated in the data sequence of the buffers A5, B6 for each discrimination process for the cell.
Patent TW-434943-B (TW)
Title: Locking electrical connector
Inventor: MARSH RICHARD N
IPC: H01R4/50
Filed: 1998-07-03
Granted: 2001-05-16
Abstract: Method for the secure engagement of an electrical plug within its respective receptacle, for increasing the efficacy of the electrical contact therebetween, and apparatus to perform the method. An electrical plug, having reversibly expandable electrically conductive blades, includes an internal swage mechanism which enables the expansion of the blades within the receptacle once the blade has been inserted therein. The swage function is effective without recourse to additional tools.
Patent TW-I228120-B (TW)
Title: Process for making diaryl pyridines useful as COX-2 inhibitors
Inventor: DAVIES IAN W
IPC: C07C319/00
Filed: 1998-09-18
Granted: 2005-02-21
Abstract: The invention encompasses a process for making compounds of formula I useful in the treatment of cyclooxygenase-2 mediated diseases.
Patent TW-402775-B (TW)
Title: Method of manufacturing gate oxide
Inventor: JOU YOU-CHIANG
IPC: H01L21/76
Filed: 1998-10-15
Granted: 2000-08-21
Abstract: There is disclosed a method of manufacturing gate oxide, comprising: providing a surface layer of nitride substrate; applying oxygen into the surface layer of the substrate; proceeding rapid thermal processing (RTP); or applying nitrogen oxide gas and proceeding rapid thermal processing (RTP) to form a thin dielectric layer containing nitrogen as the gate oxide; and finally, forming a conductive layer such as boron-doped polysilicon for being provided as the conductive gate layer on the substrate. Among which, the gate oxide formed in this invention could avoid the boron atom in the conductive gate layer entering into the substrate through the gate oxide, thereby eliminating the drawback of threshold voltage change in the conventional skill. Besides, this invention does not have to lower the annealing temperature so that it could make sure the activating effect of the dopant in the conductive gate layer.
Patent TW-407308-B (TW)
Title: Method for manufacturing polysilicon gate electrodes
Inventor: LIN JIAN-TING
IPC: H01L21/28
Filed: 1999-01-11
Granted: 2000-10-01
Abstract: This invention discloses a method for manufacturing a polysilicon gate electrode by forming a stacking structure of polysilicon layer/thin silicon oxide layer/polysilicon gate electrode. Further, this invention also discloses a method for manufacturing a polysilicon gate electrode by forming a first polysilicon layer, and then after a period of time, forming a second polysilicon layer on the first polysilicon layer. There is a grain boundary between the first polysilicon layer and the second polysilicon layer. This invention further discloses a method for manufacturing a polysilicon gate electrode by depositing a polysilicon gate layer under the operation conditions at the temperature of 600-700 DEG C and the pressure of 1-5 torr, that makes the grains of the polysilicon layer smaller. The foregoing three types of polysilicon gate structures can prevent the arsenic along the grain boundary of the large polysilicon grains from directly passing through the gate and gate oxide layer into the substrate during amorphization and causing the subthreshold kink side effect.
Patent TW-534894-B (TW)
Title: Treatment process for fluorine-containing water
Inventor: KEZUKA SATOSHI
IPC: C02F1/52
Filed: 1999-02-09
Granted: 2003-06-01
Abstract: Fluorine-containing water is treated by contacting the fluorine-containing water with calcium carbonate to react the fluorine in the fluorine-containing water with the calcium carbonate and fix it as calcium fluoride. After the fluorine-containing water is contacted with the calcium salt in the reaction tank to react the fluorine in the fluorine-containing water with the calcium salt and fix it as calcium fluoride, it is subjected to solid/liquid separation, and the treated water is removed while a portion of the sludge concentrated by the solid/liquid separation is returned to the reaction tank.
Patent TW-401636-B (TW)
Title: ESD transistor structure
Inventor: SHIU JEN-TSUNG
IPC: H01L23/60
Filed: 1999-03-26
Granted: 2000-08-11
Abstract: An ESD transistor structure is disclosed, which comprises: a gate structure composed by a connecting portion, a protruding portion and an outside protruding portion on the substrate. The outmost side of the gate structure is the utside protruding portion, and the width of the outside protruding portion is larger than the protruding portion. The outside source, the source and the drain are located inside the substrate between the two lateral sides of the gate structure and the protruding portion. There is a contact window both in the source and in the drain. The joint of the substrate is connected with the outside source, and in between them, there is a joint plane. The contact window is located on the joint plane and connected to both of the outside source and the substrate joint.
Patent TW-446631-B (TW)
Title: Laminated product, application process thereof and flooring material consisting of the laminate product
Inventor: KANBAYASHI TAKASHI
IPC: B32B27/32
Filed: 1999-04-15
Granted: 2001-07-21
Abstract: This invention provides a method to manufacture a urethane resin laminate of superior dimension stability and laying properties. Flooring materials made from the laminates and the method to produce such material are described as following. Continuous reinforced fibers are oriented in one direction, and a laminate is formed of at least two sheet-shaped prepregs impregnated with thermoplastic resin so that the volume ratio of the reinforced fibers is 50% are laminated in a manner of crossing the fiber direction orthogonally, or formed of a fiber reinforced resin layer formed of nonwoven cloth laminated on its one face of both faces of the prepregs on which a urethane resin layer is laminated.
Patent TW-416222-B (TW)
Title: Circuit for stabilizing a screen voltage of a video display apparatus
Inventor: PARK KIL-SOO
IPC: H04N3/185
Filed: 1999-06-01
Granted: 2000-12-21
Abstract: A circuit for stabilizing a screen voltage of the video display apparatus capable of supplying a uniform screen voltage to the video display apparatus even though a voltage level of an output voltage from a flyback transformer is changed. Horizontal output section generates a horizontal output voltage in response to a horizontal driving signal from an outside. Flyback transformer induces a first power source from the outside to a primary winding according to the horizontal output voltage, induces a voltage of a secondary winding thereof based on a turn-ratio, and induces a voltage of a thirdly winding thereof according to the voltage induced to the secondary winding. Screen voltage generating section receives a second power source and a pulse width modulation signal from the outside, controls the voltage induced to the thirdly winding of the flyback transformer to maintain a uniform voltage level by either outputting or breaking the second power source in response to the pulse width modulation signal and outputs the voltage induced to the thirdly winding as a screen voltage. Accordingly, it is able to prevent the lightness and quality of the screen of the video display apparatus from deteriorating.
Patent TW-421973-B (TW)
Title: Fast global optimal template comparing method and program
Inventor: HUNG YI-PING
IPC: G06K9/68
Filed: 1999-06-11
Granted: 2001-02-11
Abstract: This invention is about finding the optimal match method among the plural attributes of the template and the sample. The attribute used for comparison defines an attribute space. The method includes the followings. (A) The distance value between the template and each sample is calculated in the first subspace of this attribute space, in which the dimension value of the first subspace is lower than that of the attribute space. (B) After the distance value is calculated, the smallest one among the calculated distance values is found. (C) A new distance value is calculated, in which this new distance value is the distance value in the second subspace for the sample that has the smallest distance value in the first subspace. The dimension value of the second subspace is higher than that of the first subspace. This new distance value is compared with each distance value of the other samples in the first subspace previously. (D) Step B and step C are repeated until the new calculated distance value is the smallest one among all the distance values, and in addition, the dimension value of the subspace for this new distance value is equal to the dimension value of this attribute space.
Patent TW-382039-B (TW)
Title: Chain grids positioning and assembly method for link belt tambour
Inventor: JOU MING-KE
IPC: E06B9/68
Filed: 1999-06-15
Granted: 2000-02-11
Abstract: A kind of chain grids positioning and assembly method for chain grid tambour which includes the following steps: component preparation step, preparing a plurality of chain grids and positioning rings by pressing machine in which the chain grids have penetration holes for the horizontal tubes passing through and cutting the horizontal tubes with suitable length; linking step, allocating each individual positioning ring in each chain grid and make the horizontal tube pass the penetration hole and positioning ring that the main body of chain grid tambour is composed of the chain grid and horizontal tube in horizontal and vertical linking; positioning step, adjusting the chain grid and positioning ring to suitable position and applying welding on positioning rings with horizontal tubes to become an integrated body and complete the positioning and assembly process.
Patent TW-476672-B (TW)
Title: Coatings optimization method and device
Inventor: SCHROF WOLFGANG
IPC: B05D1/26
Filed: 1999-07-22
Granted: 2002-02-21
Abstract: The present invention relates to a method of and a device for optimizing at least one coating material at least one point of a substrate surface to which the coating material is applied. The method, which is carried out with the corresponding device, comprises at least the following steps: (a) applying said at least one coating material to said at least one point of the substrate surface, (b) curing said at least one coating material at said at least one point of the substrate surface, and (c) determining the state, especially the curing and/or yellowing and/or gloss, of said coating material at said at least one point of the substrate surface, possessed by said coating material as a consequence of steps (a) and (b).
Patent TW-504766-B (TW)
Title: Method of manufacturing electronic components
Inventor: WOOLSEY ERIC J
IPC: H01L21/308
Filed: 1999-08-17
Granted: 2002-10-01
Abstract: A method of manufacturing electronic components includes disposing a top metal layer (502) comprised of solder over a bottom metal layer (201, 202) comprised of titanium or tungsten, and selectively etching the bottom metal layer (201, 202) over the top metal layer (502), with an etchant mixture (601) comprised of an etchant, an additive to control the temperature of the etchant mixture (601), and another additive to reduce the redeposition of the top layer (502).
Patent TW-431923-B (TW)
Title: Manual cable cutter
Inventor: KOBAYASHI SADAICHI
IPC: B23D29/00
Filed: 1999-08-03
Granted: 2001-05-01
Abstract: A manual cable cutter includes a pair of fixed and shaking handles joined mutually in the upper part sides thereof, a spring for urging the pair of handles in the expanding direction, a fixed cutting blade disposed continuously in the upper part of the fixed handle, a turning cutting blade having a row of teeth formed on its arcuate outer face and having a basal end part turnably supported on the leading end part of the fixed cutting blade, a holdback claw rotatably disposed in the upper part of the fixed handle and adapted to be meshed by the spring with the row of teeth, a feeding claw rotatably supported on the shaking handle and adapted to be meshed by the spring with the row of teeth, a switch device for switching the range of motion of the shaking handle between a first opening position during the course of cutting motion and a second opening position during the course of releasing motion, and a release lever rotatably formed on the fixed handle for retracting the holdback claw and the feeding claw synchronously from the row of teeth toward the upper part of the fixed handle and rotated with the shaking handle. The switch device is switched to sway the shaking handle to the second opening position to cancel the engagement of the holdback claw and the feeding claw with the row of teeth.
Patent TW-472152-B (TW)
Title: Cable length and quality indicator
Inventor: RAGHAVEN SREEN A
IPC: H04B3/46
Filed: 1999-08-31
Granted: 2002-01-11
Abstract: A receiver that calculates the length of the transmission channel cable based on the receiver parameters is presented. The cable length is calculated based on the gain of an automatic gain control circuit or is based on the multiplier coefficients of an equalizer of the receiver. A comparison between a cable length calculated using the gain from the automatic gain control circuit and a cable length calculated using the multiplier coefficients of the equalizer indicates the quality of the cable.
Patent TW-477958-B (TW)
Title: Point taking method of digital image capture system and its device
Inventor: GUO SHR-JENG
IPC: G06T3/40
Filed: 1999-09-30
Granted: 2002-03-01
Abstract: There are provided a smooth point taking method of digital image capture system and its device. The device includes: an adder; a first register whose output is fed back to the adder; a first multiplexer for outputting a ratio parameter or weighting parameter; a multiplexer for receiving the input image data and the output of the first multiplexer; and an adder/subtractor for receiving the output of the multiplexer; a second multiplexer for receiving the output of the adder/subtractor and the output of the multiplexer; and a second register for receiving the output of the second multiplexer, so as to utilize the approximation method and recursive architecture to sample the input image data in real time to be used as output image data.
Patent TW-408015-B (TW)
Title: Foldable walking-assistant device
Inventor: UCHIYAMA TOSHIFUMI
IPC: A61H3/04
Filed: 1999-10-05
Granted: 2000-10-11
Abstract: A foldable walking-assistant device with which the handle's height can be properly adjusted according to the user's height. The device itself can be used as a chair. Moreover, the device can be folded and unfolded easily by the one-touch manner. Each left and right leg body consists essentially of the horizontal leg whose longitudinal length can be adjustable, the handle pipe which is vertically placed on the horizontal leg and is adjustable as to the height of the device, and the rear pipe which is provided at the handle pipe. The leg body possesses the folding mechanism combined with the associated action of the cross bar. The hand brake is installed at the handle pipe.
Patent TW-427021-B (TW)
Title: Flash memory structure and manufacturing method thereof
Inventor: LI JIAN-SHING
IPC: H01L27/115
Filed: 1999-10-22
Granted: 2001-03-21
Abstract: A manufacturing method of flash memory is disclosed. First, provide a substrate and sequentially form gate oxide, floating gate, cap layer on the floating gate thereon. Form spacers on the sidewalls of the gate oxide, floating gate and cap layer. Then make trench on the exposed substrate between the spacer and cap layer and form source/drain area in the substrate at the bottom of the trench. Second, remove the cap layer and spacer and form conformal first dielectric layer on the substrate. Finally, form a conductive layer upon the substrate.
Patent TW-417072-B (TW)
Title: Parking charging system
Inventor: WANG MEI-FEN
IPC: G07F17/24
Filed: 2000-01-07
Granted: 2001-01-01
Abstract: The present invention provides a parking charging system which comprises a roadside parking control and management system and parking control and management system for the parking lot. The system employs the mobile phone or public switched telephone network as the control and management tool so as to accomplish the operation of parking management and charging.
Patent TW-452821-B (TW)
Title: Ionized physical vapor deposition method and apparatus with magnetic bucket and concentric plasma and material source
Inventor: VUKOVIC MIRKO
IPC: C23C14/34
Filed: 2000-02-16
Granted: 2001-09-01
Abstract: Conductive metal coating material is sputtered from a magnetron sputtering target (51), ionized in a processing space by a dense plasma with RF energy coupled, from a coil (65) outside vacuum chamber (31) behind dielectric window (61) in chamber wall (32) at the center of opening (58) in target (51). Chamber pressures are in the 10-100 mTorr range. A magnetic bucket (20) formed of an array (22) of permanent magnets (23) behind the chamber wall (32) forms a multi-cusp field repels charged particles moving from the plasma to the chamber wall (32), increasing plasma confinement and improving the plasma density and uniformity and the ionization fraction of the coating material.
Patent TW-438693-B (TW)
Title: Sub-frame structure for vehicle
Inventor: NAGAI MICHIYUKI
IPC: B60G11/16
Filed: 2000-02-23
Granted: 2001-06-07
Abstract: This invention is to provide a sub-frame structure for vehicle to properly hold an aligned condition of wheels, secure operation stability, and prevent durability from being worsened, by restraining deformation of an inclined part with a spring receiving part formed on the upper end side. This sub-frame structure for vehicle is provided with spring receiving parts 101 join-fixed to left and right side members 4 extended along a vehicular longitudinal direction X to receive road face reaction force F from rear wheels W via coil springs 31, a body width-directional extending member 1A having left and right inclined parts 102 extended from the both spring receiving parts 101 toward a lower side of a body central part side, left and right bent parts 103 formed lower ends of the both inclined parts 102 and connected with a lower arm 11, and a linear central part 104 extended from the both bent parts to the body central part side, and a reinforcing plate member 8 having a vertical plate part 801 with its end edges join-fixed to the both inclined parts 102 and the linear central part 104 of the member IA to attach a rear end of a differential gear.
Patent TW-468113-B (TW)
Title: PCI slot control apparatus with dynamic configuration for partitioned systems
Inventor: BEALKOWSKI RICHARD
IPC: G06F9/50
Filed: 2000-03-28
Granted: 2001-12-11
Abstract: A system for partitioning and allocating individual PCI slots within a primary host bridge (PHB) in a partitioned computer system is provided. An innovative PHB system is included which allows a PCI slot to be dynamically assigned to one or more partitions at a given time, allowing for more efficient allocation of system resources.