Patent GB-1381518-A (GB)
Title: Transceiver devices for syllabic compression telephony systems
IPC: H03G7/06
Filed: 1972-07-13
Abstract: 1381518 Compander THOMSON-CSF 13 July 1972 [25 Aug 1971] 32897/72 Heading H4R In a compandor system the gain of the eompressor is varied in steps and the gain setting signalled to the expander by a pilot signal whose frequency is varied in steps corresponding to the gain steps. Fig. 1 shows a compressor including an amplifier 4 having four stages each of which is switched between, two different gain settings differing respectively by 3, 6, 12, and 24 dB and controlled by the respective stages of an updown counter in the logic circuit 7 which is stepped up in response to the signal level exceeding a predetermined upper limit and down in response to the signal level not having exceeded a predetermined lower limit during a predetermined period, e.g. 12 to 13 msecs. The setting of the counter is also applied, at 11, 12, 13, 14, to control the frequency of the pilot signal generator 8, whose output is mixed with the signal output from amplifier 4, after the signal output has passed through a long time constant a g c circuit 3. At the expander, Fig. 5, the information signal and pilot signal are separated by filters 201 and 202, the pilot signal controls the condition of a counter in demodulator 205, which controls the setting of gain in the expander 204 to which the information signal is applied via a delay circuit 203. The squelch circuit 206 compares the information signal level with the pilot signal level, since during normal transmission the level ratio stays substantially constant, and switches the expander to its maximum loss condition if the ratio differs from normal. Controlled gain amplifier, Fig. 2 (not shown) each stage has a transistor (25) with the emitter collector path of a further transistor (32) in its emitter circuit, the further transistor being switched between cutoff and saturation to effect variation of emitter feedback and gain of the stage. Logic circuit, Fig. 3 (not shown), has clocked trigger circuits (71, 72) to sample the output of the comparator 6, Fig. 1. Signals over the maximum level cause immediate stepping of the up-down counter (76) in a direction to reduce the gain. Signals above the minimum level cause resetting of a 100 state counter (74) which, if it manages to complete a full cycle without being reset, causes the up-down counter to be stepped in such a direction as to increase the gain of amplifier 4, Fig. 1. Generator 8 Fig. 3, is formed by a counter Fig. 4 (not shown), whose cycle length is varied by the inputs 11, 12, 13, 14, so that when driven by a clock (10) output pulses are obtained at a frequency in the range 2560 to 2660 Hz, the actual frequency depending on the inputs 11 to 14.  Demodulator counter. Fig. 6 (not shown), has a first counter (211) which is fed with the limited pilot signal and switches on a second counter 216 to count clock pulses over sixteen periods of the pilot signal, to give an average of the pilot frequency. The second counter (216) is a divide by 16 counter feeding a third "divide by 16" counter (217) whose setting, at the end of sixteen periods of the pilot signal, will represent a demodulation of the pilot signal period which can be used directly to set the gain setting of the expander circuit via a transfer citcuit (225) and memory (219). A further counter (218) on the output of the third counter (216) has to indicate a count of 24 to validate the setting of the counter since the actual period of the pilot frequency is 24Î16+n periods of the clock frequency where n is 1 to 15 and is the setting of the compressor gain. The delay circuit, 203, Fig. 5, comprises an a to d converter of the linear delta type followed by a shift register feeding an integrator forming a d to a converter. Fig. 7 (not shown).