Patent GB-717688-A (GB)
Title: Improvements in or relating to electrical signalling systems
Inventor: BAKER GEORGE THOMAS
IPC: H04Q3/42
Filed: 1951-07-25
Abstract: 717,688. Automatic exchange systems. BRITISH TELECOMMUNICATIONS RESEARCH, Ltd. July 10, 1952 [July 25, 1951; July 25, 1951], Nos. 17676/51 and 17677/51. Class 40 (4) Digits registered in binary form on a high-speed register device, such as a magnetic drum or cathode ray tube, are transmitted by a system which reduces the registration by one each time an impulse is transmitted over an outgoing circuit. In the embodiment digits are registered on a drum in the manner described in Specification 717,687. A control track generates clock pulses, .TZ pulses corresponding to different called numbers, TY pulses to the digits and TX pulses to the unit areas. In the example the 1st and 14th Y blocks are for instructions and the 2nd-12th Y blocks for the storage of digits. Each block consists of five areas, the first for busying, the others for storing a digit in binary code. The drum rotates at six times sending speed, sending being controlled by a time pulse TSN every 100 msecs. At the end of a digit when the related store has been zeroized, an inter-digital pause is arranged by counting down from 16 to 8. Memory circuit M1 is operated in the first area of the first (instruction) block during the read scan when time pulse TSN occurs. M1 is normally reset in position X4, but if sending is to take place, a registration in the fourth area of the first instruction block (TY1, TX4) cancels the restoring potential. When next a digit block is encountered with a busy dot in position 1, the output of M1 operates M2. The binary registration in this block is reduced by 1 on each send scan by reversing the condition in all storage areas until a 1 has been changed to a 0. When 0 is detected, potential on lead SL combines with the output of M2 to pulse lead B to enter 1. When 1 is detected, M2 pulses lead A to enter 0 and potential on lead SL resets M2. The output from M2 also. resets M1 and operates M3, the output of which is effective only when blocks Y13, Y14 are being scanned to operate a pulse lengthening device PS to feed the appropriate output OP1-OPN with an impulse of normal dialling duration. M3 is reset at the beginning of the next scan over that Z group and the operation proceeds, the registration being counted down one unit each time until the digit block is zeroized, when the absence of potential on lead SL allows M2 to remain operated, its output operating M4 in the fifth area of this block. M4 then pulses lead B to write an interdigital dot in the fifth area of instruction block 14, M4 restoring at the same time. At the next scan M2 again operates and counting down from 0 to 8 takes place so timing an interdigital pause of 900 msecs., transmission to the PS circuit being prevented by the interdigital dot operating M5 to reset M3 over lead R. When the registration is reduced to 8, i.e. to a dot in area 5 only, M6 operates to enter a "remove busy" dot in the first area of instruction block 14. Immediately after that the interdigital dot is removed and M6 is reset. On the next scan the "remove busy" dot energizes an auxiliary head SL<SP>1</SP> one group in advance of the normal read head to operate M7 which removes the busy dot from the block from which the digit has just been transmitted. Subsequent digits are transmitted in like manner. The subject-matter of this Specification is identical with that of Specifications 717,734, 717,735, and 717,736, but the claims differ. Specification 681,360 also is referred to.