Patent GB-1168658-A (GB)
Title: Information Storage Systems.
IPC: G11C7/02
Filed: 1966-12-08
Abstract: 1,168,658. Memory selection circuit. WESTERN ELECTRIC CO., Inc. 8 Dec., 1966 [17 Dec., 1965(2)], No. 54983/66. Heading G4C. [Also in Division H3] In a memory system in which an access selection circuit is controlled by a binary coded address, means including a ramp generator are provided which are controlled by the binary coded address so that a strobing pulse is applied to a sense amplifier to coincide with the arrival of a read-out pulse from the selected address of the memory. The memory 10 of Fig. 1, comprises a plurality of twistor elements each comprising a central conductor wound with magnetic tape and being arranged with a return conductor 12 as shown to lie in several planes. In order to select a word for reading purposes, e.g. the bit addresses coupled to word solenoid 13, at time to address information coded signals from the access information source 18 are passed to X and Y co-ordinate access selection circuits to cause coincident currents to pass through lines 15, 14 and 16, 13 and switch core 14<SP>1</SP> and induce a drive current in 13<SP>1</SP>. Since the time of travel of output signals induced in element 11 due to the read pulse and dependent upon the information stored to sense amplifier 17 will depend upon the position of the bit addresses in the memory planes the amplifier 17 is strobed at a time taking into account the position of the bit address. In the arrangement of Fig. 1 coded signals representative of the X-co-ordinate selection conductor are applied at time t 0  from source 18 to the four inputs 2, 2<SP>1</SP>, 2<SP>2</SP>, 2<SP>3</SP> of the ramp generator 22. At time to bi-stable circuit 23 is set to turn transistor T 6  off and allow current from transistor T 5 , which was shunted therethrough to pass to capacitor C 5  and some combination of capacitors C 1  to C 4  as controlled by whichever of the associated transistors T 1  to T 4  is energized in accordance with the coded signals. Due to the charging of the capacitors a ramp voltage is developed at the emitter of transistor T 7  the slope of which is determined by the valves of the capacitors C 1  to C 5  determined by the input code and varies in angular increments in accordance with the position of the bit addresses in the memory. The ramp voltage is applied to transistor T 8  of comparator 24. When the ramp voltage reaches the value of reference voltage V 3  applied to the base of transistor T 9 , transistor T 8  conducts and a signal is passed to strobe generator 25 whereby a strobing signal is passed to transistor T 11  to cause the latter to conduct and a signal to be produced the collector of transistor T 10  if the output signal from amplifier 17 is greater than reference voltage V 4 . The circuit is reset by the output signal from the comparator 24 and the ramp voltage is terminated. Fig. 3 shows an alternative embodiment for the timing circuit and comprises a separate converter 20 and ramp generator 122. At the time to coded signals of the address bits applied via the X-access selection conductor are also applied to resistances R 1  to R 4  and R 5  of converter 20 having different values so that a voltage is developed across resistor R 5  of value dependent upon the binary coded address input and is applied to the base of transistor T21 of comparator 124. At time to a timing pulse is also applied to bi-stable circuit FF 1  of ramp generator 122 to place it in its set state and cause capacitor C 11  to charge through resistor R 6  to generate a ramp voltage of constant slope at the collector of transistor T 14 . The ramp voltage is applied to transistor T 22 , which transistor remains cut off until the ramp voltage is equal to the voltage from converter 20 when transistor T22 conducts and strobe generator 25 is triggered and strobing circuit 26 is opened. The strobe signal in both embodiments may be timed for each increment of delay introduced by the difference in distance from the sense amplifier along a kit line of each of the information addresses by increasing the number of inputs to the ramp generator 22 or the converter 20 to include the address information bits of the 7 selection conductors 16.