Patent GB-1127181-A (GB)
Title: Improvements in or relating to electrical control systems
Inventor: KEATS ALBERT BRIAN
IPC: H03K19/23
Filed: 1965-01-26
Abstract: 1,127,181. Electric selective signalling. UNITED KINGDOM ATOMIC ENERGY AUTHORITY. 25 Jan., 1966 [26 Jan., 1965], No. 3411/65. Heading G4H. [Also in Division H3] A logic circuit provides output pulses characteristic of the number of inputs present, and for the three-input basic circuits described provides a uniform series of output pulses if all inputs are present, a reduction of pulses to one third if one input is removed and no output for either one or zero input. Magnetic storage cores F 1 -F 3  are used in the basic logic circuit shown in Fig. 3, in which two storage cores are energized in opposite respects if an input A-C is present simultaneously with a respective three phase clock pulse # 1 -# 3 . If two inputs are present such as A, B, core F 1  only is switched and reset during clock pulse periods #2, #1, respectively, the other two cores being quiescent. An output pulse is then obtained during clock pulse period # 1  alone which passes through a resetting winding r. If all inputs are present then all three cores are switched and reset in turn and produce output pulses in all of the clock pulse periods # 1 , # 2  and # 3 . No output is obtained for either a single or zero input. A frequency sensitive detector connected to the output determines the number of inputs present. As shown in the lower part of the Figure the outputs of several basic devices may be combined using magnetic storage cores, these cores being connected in cascade with the first core energized for resetting by pulses #INT of three times the three-phase frequency. A combined output is obtained if each basic circuit has two or three inputs present, the frequency of the output being reduced if any one basic circuit has less than three inputs. An alternative basic circuit comprises a laddie, Fig. 5 (not shown), having hold windings (a), (b), (c) arranged in pairs on alternate rungs, each of three inputs (AA<SP>1</SP>)-(CC<SP>1</SP>) being connected to two hold windings each on a different rung. Two laddies may operate in cascade, the output winding of one being connected to the reset winding of the other. A further arrangement of laddies, Fig. 6 (not shown) is similar to Fig. 3, the combined output circuit serving as a trip line for a transducer. A number of trip lines T 1 ,T 2 ,T 3  may be combined as shown in Fig. 7, to control a transducer Z, the final coded output of any trip line being detected by frequency meters PM1-FM3 The pulsed output is converted to a D.C. signal in converter C1-C3, and is recoded to provide an output despite minority failure of the trip lines by gates 29 each energized by a different two of three phases # 1 -# 3 . These are applied to an AND gate 40 from which the loss of any one input is recognized by a 3 : 1 frequency change at meter FM4. Each of the three phases is taken from different generators 41 to prevent the network output from disappearing if one generator fails. In this arrangement the failure of a minority of inputs on any line is detectable by the pulse pattern appearing at meters FM1-FM3, while any minority of trip line failures is detected by meter FM4. Proof testing without operating the transducer may be carried out in any of the three circuits by interrupting the trip line at X. The arrangements disclosed are applicable to plant or process control.