Patent GB-843917-A (GB)
Title: Improvements in or relating to traffic control systems
IPC: G08G1/081
Filed: 1956-05-18
Abstract: 843,917. Traffic-light controllers; control systems. EASTERN INDUSTRIES Inc. May 18, 1956 [May 25, 1955], No. 4254/60. Divided out of 843,916. Classes 40(1) and 118(2). A traffic control system comprises a master controller transmitting two polyphase signals of slightly different frequency and a station controller arranged to derive two single-phase outputs one from each of the polyphase signals, and to give an output when the outputs coincide in phase. The timing of the control cycle is thus obtained and also the effect of the control cycle from the master. The method by which the above functions are carried out is disclosed in Specification 843,916. According to the present Specification the offset times of the local (station) controllers may be altered progressively by means of a homing potentiometer at the station controller. The system of this Specification is a modified version of that disclosed in Specification 843,916. As before a reference frequency FR and a control frequency FC are transmitted to the station controller and the local timing is effected by biasing a coincidence gate. FR is applied to a potentiometer PR7 to derive the offset control and this is applied to pulse former PF2 and the spike pulse passed to gate CG1. Coincidence in the gate energizes R1 for controlling the stepping motor MM. FC is applied to PRA1, PRA2 and PRB and a selected one of these supplies single phase to pulse former PF1 which supplies the second of the spike pulses to gate CG1. By energizing relay R6 from the master controller PRA1 is substituted for PRA2 on one of the remote timed sequence steps. PR7 is a homing potentiometer the control of which is described later. Spike pulse formers and coincidence gates.- Each of these formers comprises two squaring stages 145, 155 and a differentiating circuit 163, 121 to apply a sharp positive pulse to a relevant control grid in one of the gates. The gates comprise a valve with two control grids 167, 168, the lower of which is fed with the spike pulse from PF2, the upper fed as described later. The pulse formers will give both positive and negative spikes but the latter will not operate the gates. The anodes of the gates will go negative on each coincidence pulse (e.g. 400 cycles per second) and then go positive. These pulses drive cathode follower 185. The negative pulses cause the voltage across the cathode follower load resistance 193 to drop, and the accumulated excess charge in 197 discharges through the diode 195. The remainder of the time the capacitor 197 is charging through 206 and the average voltage across 206 controls a D.C. amplifier 205. When the negative pulses cease (on non-coincidence) 197 becomes fully charged through 206, the voltage across this resistance ceases to exist and the output of 205 ceases, thus releasing its relay R1. 197 is chosen to be sufficiently large to sustain the relay during the 400-cycle coincidence pulses. Gating arrangements.-CG1 is fed normally by spike pulses from PR7 (PF2) which is the offset control and by spike pulses from a PRA or PRB potentiometer (PF1) which are cycle split controls. Thus the coincidence output is equivalent to that of the gate CG1 of Fig. 2 and controls the sequence switch (W1, W2, W3, and W4 (not shown), the latter being the light switching bank). As before some sequence steps are timed by a local timer, in this case controlled by W3. A capacitor 120 is charged from positive (in the square) through selected variable resistances 276-279 each controlling the timing for one step. When 120 is sufficiently positive it exceeds the cathode bias on the gate 165, opens the gate, and allows relay R1 to pull up to energize MM. MM then closes the shunt circuit 198, ml, m2, to discharge 120 and close the gate. The de-energizing of MM causes a sequence step. Where a local timed step is to be executed W2 shorts the input to PF1. When a master controlled step is to be made W3 connects grid 167 to the common bias point 124 and the gate is only opened on coincidence of the pulses from PF1 and PF2. Homing potentiometer.-Two relays R4 and R5 are remotely controlled from the master over lines OC1, OC2 and OC to control the offset of the station cycle with respect to the master. As already explained, the offset is controlled by a homing potentiometer PR7. A selected phase output is selected by energizing both, either or none of relays R4, R5 and delivered to PF3. This pulse former derives a spike at 224 and in addition a square positive pulse at 230, the capacitor resistance network 227, 231, 228 being to improve the pulse shape. Gate CG2 is supplied with spikes from PR7 (via PF2) and from the selected one of the offset controls RS, PR6, PR5 or PR4. Obviously these will be in coincidence only if the phase of the two single-phase circuits is identical. In any other condition gate CG2 is closed and relay R2 is open to make back contact r20. This energizes the reversible motor RDM driving the homing potentiometer PR7, and the motor will cut out only when PR7 is in correspondence with the selected offset control. CG3 is supplied with the spike from PR7 (via PF2) and the square wave from PF3 (responding to the offset control selected by R4, R5). If the spike and the square wave overlap then the gate opens and R3 is energized to switch in winding CCW of the variable direction motor RDM and the potentiometer is moved counter clockwise to correspondence. If, however, the spike and pulse do not coincide (indicating that the shortest potentiometer movement to coincidence is clockwise), then R3 is not energized and so winding CW of RDM is energized through back contact r30 on R3. By this means the homing potentiometer is always driven in the shortest direction to coincidence. By suitable gearing the offset of potentiometer PR7 is changed over several timing cycles to avoid undue interference with the traffic flow.