Patent GB-756398-A (GB)
Title: Improvements in or relating to electric pulse-delay networks
IPC: G06F1/10
Filed: 1954-04-29
Abstract: 756,398. Pulse delaying circuits. SIEMENS & HALSKE AKT.-GES. April 29, 1954 [April 29, 1953], No. 12523/54. Class 40 (6). A delay network comprises a cascaded connection of normally non-conducting amplifying stages which are inter-coupled by damped resonant circuits so that when a pulse is applied at the input the stages are successively rendered conducting by the voltage derived by shockexcitation of the resonant circuit and by a series of pulses which are applied to condition each stage periodically to a state of conductivity to generate a series of delayed pulses st the outputs of the individual stages. Fig. 1 shows a delay circuit in which a train of pulses, Fig. 2 (a) from a pulse generator G is applied in parallel to gate open the discharge tubes R0<SP>11</SP>0, R0<SP>11</SP>1 ... R0<SP>11</SP>n at their suppressor grids. The pulses from G are also applied to a frequency divider stage Ft and via a switch E to the control grid of tube R0<SP>11</SP>0, the resulting negative pulse, Fig. 2 (b) at the anode and output A1 shock-excites damped tuned circuit L1, C1, D1, to produce a waveform, Fig. 2 (c), the first positive pulse of which renders tube R0<SP>11</SP>1 conducting to generate a pulse, Fig. 2 (d), at output A1. This process is continued along the chain of stages, the output of stage R0<SP>11</SP>n being phase-reversed by transformer U<SP>11</SP> and applied via feed-back path K and switch T1 to the input of stage R0<SP>11</SP>0. In a modification shown in Fig. 3, the damping of the tuned circuits L1, C1, &c. is obtained by feeding an appropriately-phased voltage from a preceding cathode to damp out all but the first complete cycle of oscillation, Fig. 4 (not shown). In a further modification shown in Fig. 5, the damping is obtained by connecting damping resistors, forming the lower portions of potentiometers Spl, Sp2, Sp3, in parallel with the tuned circuits L1, C1, &c. via rectifiers G<SP>1</SP>1, G<SP>1</SP>2, G<SP>1</SP>3 which are opened by pulses in the correct phase position. In a further modification, Fig. 7, 8 (not shown), the tuned circuits are damped by a parallel-connected resistor and a biased rectifier also connected in parallel with each tuned circuit limits the first positivegoing half-cycle of the damped wave-train produced. The tuned circuits may be coupled to their respective anode circuits, and the output pulses tapped-off via a transformer, Fig. 9 (not shown). In a modification shown in Fig. 10, the amplifier stages comprise transistors T0, T1 ... Tn and gating circuits comprising diodes G<SP>1</SP>1, G<SP>1</SP>2, G<SP>1</SP>3, &c. are opened in step with the controlling pulses from generator G to apply a pulse to the succeeding transistor stage. In a further modification shown in Fig. 11, gas tubes R0<SP>11</SP>1, R0<SP>11</SP>2, R0<SP>11</SP>3 are used gated open by pulses applied to their second grids, from generator G. When a given tube is fired the preceding tube is extinguished due to the voltage drop across the common anode load resistor Ra and the presence of cathode networks Rk1 Ck1, &c. The output pulses produced have a duration equal to twice that of the pulses from generator G, Fig. 12 (not shown). The tuned circuits may be tuned to successively lower frequencies so that progressively wider-pulses are obtained at the successive outputs. Fig. 13 shows the application to a static storage device in which the delay circuit comprising amplifiers S0, S1 ... Sn and tuned circuits L1, L2 ... Ln is associated with storage stages P0, P1 ... Pn. The storage stages are conditioned by operating key T3 or T4 when any output pulse present at the stages So ... Sn is recorded on the relevent storage stage Po ... Pn. Fig. 14 shows a marking circuit for generating a predetermined number of pulses, the controlling gating pulses from generator G being applied in parallel to all of the screen grids via resistor Rsg. When a given output 1, 2 ... n of marker M is energized a negative pulse is applied to the suppressor grid of the associated tube R0<SP>11</SP>0 ... R0<SP>11</SP>n to render it non-conductive so that when an input pulse is applied at E a predetermined number of, pulses depending upon the marker output selected is generated across the common load resistor Ra at output Aa. A pulse train, Fig. 15 (d), characteristic of the marker selected is also produced across resistor Rsg at output Asg. Fig. 16 shows a circuit for generating a succession of pulse trains the number of pulses in which increases successively up to a final value and then repeats the cycle. The delay network comprising amplifiers So ... S6 and tuned circuits L1 ... L6 is actuated by a pulse applied from generator G via frequency divider Ft cathode follower stage R0<SP>11</SP>1, and diode G<SP>1</SP>1 to the input E. This pulse passes down the delay network and is applied as a positive pulse to the first grid of coincidence tube R0<SP>11</SP>2 which is blocked at its second grid as tube R0<SP>11</SP>3 of trigger pair R0<SP>11</SP>3, R0<SP>11</SP>5 is conducting. This pulse is also applied to the coincidence tube R0<SP>11</SP>4 which conducts, the positive pulse at its cathode being fed-back to the input E of the delay network. The number of stages of the delay network and the dividing ratio of divider Ft are such that the fed-back pulse at E appears at an instant different from that at which a new pulse from Ft appears at E, thus the number of pulses passing increases successively, Fig. 17 (not shown). When the number of pulses passing is equal to the number of amplifier stages so that all of the stages are conducting rectifier G<SP>1</SP>10 conducts to change over trigger-pair R0<SP>11</SP>3. R0<SP>11</SP>5 sothat tube Ro"2 conducts and tubes R0<SP>11</SP>4 and R0<SP>11</SP>1 are cut-off, thus the input at E ceases until all pulses passing through the delay network are cleared when the cycle is repeated.