Patent GB-1198132-A (GB)
Title: Improvements in Semiconductor Bistable Switching Devices
IPC: H01L29/745
Filed: 1967-07-18
Abstract: 1,198,132. Semi-conductcr devices. SOC DE CONSTRUCTIONS ELECTROMECANIQUES JEUMONT-SCHNEIDER and S. TESZNER. 18 July, 1967 [22 July, 1966] No. 33019/67. Heading H1K. The blocking process in a bi-stable semiconductor switching device functions in a manner analogous to the mode of operation of a field-effect gridistor or bivalent triode. The device has at least four layers 80, 82/83, 86, 87 (Fig. 14) of alternating conductivity types, the layer 82/83 having embedded therein a grid 85 of opposite conductivity type to the layer 82/83. Current electrodes 81, 89 are provided respectively on the end layers 80, 87, and control electrodes 92, 93 are attached respectively to the grid 85 and the layer 82/83. The device is rendered conductive by a pulse applied between the control electrode 93 and the current terminal 81, as in conventional PNPN switches, and is rendered non-conductive by a pulse applied between the grid electrode 92 and control electrode 93. In the embodiment shown this latter pulse renders the P+ grid 85 negative relative to the surrounding N region 82/83, thereby closing the N channels 84 by the field effect. Shunting P+ channels 88 may or may not be provided through the N+ emitter region 87. A bidirectional version of this embodiment has an additional N+ end layer (29), Fig. 7 (not shown), with or without P+ shunting channels (30) therethrough. In this case an additional control electrode is provided so that the central N layer (11) carries one electrode (20, 21) on each side of the P+ grid (12), which again carries an electrode (10). Control pulses are applied as with the above embodiment, the terminal (20) or (21) being used dependent upon the polarity of the current being switched. A control circuit to determine this is described. Fig. 15 shows an alternative form of the device of Fig. 14, in which the P+ grid 96 is incorporated in one of the P + layers lying completely across the current path. The grid 96 lies within an N region 98, the blocking operation occurring due to a widening of the spacecharge region associated with the narrow portions of the P + layer 96/97 which close the meshes of the grid 96 when the grid 96 is made negative relative to the N layer 98. The control electrode 104 may be dispensed with for low operating currents and voltages, the blocking pulse being applied between the grid electrode 103 and the cathode 101. The conductive state is restored by a pulse between the cathode 101 and the grid electrode 103, whereby the grid 96 is rendered positive relative to the N+ emitter region 95. A bidirectional version of this embodiment is also described in which two symmetrically opposed P+ grids (64, 66), Fig. 11 (not shown), are provided within the central N layer (65), each grid being similar in form to that shown in Fig. 15. An additional N+ end layer (67) completes the N+P+NP+N+ structure, which carries three control electrodes, (59, 61, 60) on the P+ grids (64, 66) and central N layer (65) respectively. P+ shunting channels (63, 68) may or may not be provided through the outer N+ layers (62, 67). This device may alternatively have a PNPNP structure. Control circuits for this device are described. The devices shown may be formed in N-type Si wafers, but III-V compounds and other  group IV materials may also be used. Masked diffusion, alloying or epitaxial deposition may be used to form the various layers. In particular with regard to Fig. 14, the initial wafer lies within the lines A-B, the lower part of the P+ grid 85 being diffused therein. The upper part of the device is then epitaxially deposited, and the remaining diffusions are carried out. B and P are referred to as diffusion dopants, while Al or Au/Sb may be alloyed in. The Specification includes descriptions of the structures and modes of operation of a bipolar gridistor and a bivalent triode, the latter device operating either as an injection transistor or as a field-effect device.