Patent GB-1358193-A (GB)
Title: Integrated control circuit
IPC: H03K17/64
Filed: 1971-06-21
Abstract: 1358193 Integrated circuits; magnetic storage arrangements HONEYWELL INFORMATION SYSTEMS ITALIA SpA 21 June 1971 [20 June 1970] 29069/71 Headings H3T and H3B In an integrated circuit comprising a logic circuit having an input stage 11, 12 with a first terminal for connection to a first external voltage source +V3 and an output stage 17, 18 having a second terminal for connection to a second external voltage source + V2 higher than the first external voltage source +V3 and a switching circuit having a third terminal 24 for connection to an external source of voltage + V2  through an external resistive load 25 and comprising first and second series connected transistors 23, 28 for connecting the intermediate point 27 common to the first and second transistors to the third terminal 24 or to ground respectively, the switching circuit is connected to the output stage 17, 18 of the logic circuit so that the switching state of the switching circuit 23, 28 is controlled in dependence on the logic function performed by the logic circuit. By providing a positive relation between binary levels and signal voltages, that is, when binary "0" is zero or a low positive voltage and binary "1" is a higher positive voltage, when "1" or a positive voltage is applied to 9 and/or 10 transistors 11, 17 and/or 12, 18 conducts to provide a NOR function at 21 and an OR function at 22. If a negative relation exists between the binary levels and the signal voltages NAND and AND function are provided at 21, 22. The diodes 13, 14 prevent voltages at the inputs 9, 10 from having negative values. When the input at 9 and/or 10 is "1" or positive, transistors 17 and/or 18 conduct, 22 goes positive so that transistor 28 is on and transistors 5 and 23 are off which connects terminal 27 to ground and read source transistor RS1 is off. When both inputs 9, 10 are "0", 22 is at ground potential and 21 is almost +V2 so that transistor 28 is off and transistors 5 and 23 are on. This connects output 27 to + V2 via a precision resistor 25 so as to bias read source transistor RS1 on. The voltage at 27 is limited by the maximum voltage +V2 admitted by the integrated circuit by diode 29. Resistor 26 provides very fast turn off of transistor 23 by discharging the electrical charges stored in the base-emitter junction when this transistor was on. The circuit 7 may be used to apply power to inductive loads such as for driving source switches RS 1 of a magnetic memory f. A single external resistor 25 may be used for a plurality of circuits 7. When source transistor RS1 is driven on there is a sharp current pulse due to the stray capacitance of the line f. If however the sink switch RD 1 is open the voltage of all the electrodes of the transistor tend to read +V1, diode 29 becomes conductive to prevent this so that RS1 rapidly goes out of saturation. The integrated circuit 8 for driving the sink transistor RD1 is similar to circuit 7. However as the drive voltage required at 35 to make RD1 conduct is less than that required at 27 the collector load resistor 34 is formed in the integrated circuit. A further modification is in the connection of a resistor 33 to remove the charges stored in the base of transistor 36. Two driving circuits 7 (Fig. 6, not shown) for source switches and two driving circuits 8 for sink switches may be constructed on the same integrated circuit. Two inputs are provided for each drive circuit, one for information and the other for a clock pulse.