Patent GB-1288661-A (GB)
IPC: H04J3/06
Filed: 1970-06-22
Abstract: 1288661 Digital transmission; synchronization MULLARD Ltd 6 May 1971 [22 June 1970] 30156/70 Heading H4P A synchronizing system having bit and frame synchronizing has for frame synchronizing a generator producing a sequence of binary bits representing message start signals which on receipt are correlated with a determined sequence in a correlator giving an output proportional to the number of bits in agreement, also a threshold circuit which determines when the number of bits at least equals a determined number. A sequence pulse detector may give an output when two or more adjacent pulses have been received from the threshold circuit at the same repetition rate as the sequence, which may be of a maximal length pseudo random series. Bit synchronizing may be provided by phase lock loop at the receiver. At the transmitter.-Output from a sine wave oscillator OT feeds attenuator AT, analogue switch AS and phase modulator PM, the outputs from which are fed to a summing amplifier SA; also a limiter LM giving a square wave output forming clock pulses which trigger monostable devices MS1, MS2 and a pseudo random generator PRBS. Information IP for transmission through second analogue switch AS2 is also fed to amplifier SA. A 100 m.sec. start signal ST triggers MS1, the output from which disables information signals via NOR gate NG and AS2 and enables AS1 passing a high amplitude sinusoidal signal to line. At the trailing edge of the 100 m.sec. signal MS2 is set for 25 m.sec. and enables AND gates AG1, AG2 to pass output of PRBS to phase modulator PM which phase shifts the sine wave input by 180 degrees when PRBS issues a " 0 " and 0 degrees when PRBS issues a " 1 ". In the embodiment PRBS has four stages and a fifteen bit sequence; each time " 1111 " is reached another output is given at d, n other outputs being given in the 25 m.sec. period which are detected by an n in a row detector DE which checks that each d output is separated by the appropriate time spacing, or number of bits. In the embodiment n = 3. At the end of the 25 m.sec. period, gates AG1, AG2 also PM, DE are inhibited and AS2 is enabled passing information IP to line together with a low amplitude sine wave through attentuator AT. The three-in-a-row detector DE may comprise a 15 bit counter which on arrival of the first pulse steps at bit rate through to its first position again, by which time the second pulse should be present, and if so causes a flip-flop (not shown) to be set. Detector DE again " runs through " and if a first pulse is present at its allocated time position the flipflop is reset which issues a message start pulse. Any false pulses at other time positions will have no effect.  The receiver includes a phase lock loop of known type PLL (see Fig. 1, not shown) producing a sine wave to an analogue subtractor SUB also receiving input signals which are additionally passed in manner known per se to limiter LIM. Signals at the PLL input and an extracted clock signal are passed to a phase modulator PD connected to a 15 bit demodulator CO and thence to threshold detector TD having a biasing input Vt, issuing signals to an n-in-a-row detector (n = 3) similar to Fig. 4 which generates a " message start" signal: information signals are derived from SUB. Correlators of all digital and part analogue types giving output discretely proportional to the number of correct signals in a determined sequence of say 15 bits are described in connection with Figs. 9 and 10 (not shown). The threshold detector TD can be set to give a majority decision effect, i.e. thirteen correct signals out of fifteen or it can be set for example at fifteen out of fifteen so that there is no redundancy. It is considered that 3 Î 15 bit sequences are equivalent to a 45 bit sequence, but other sequences and repetition numbers are envisaged, the longer sequences ensuring high accuracy but longer synchronization time; 3 x 15 bits is considered a reasonable compromise and requires only a 15 bit correlator. Barker code, or other sequences, may be used alternatively to a pseudo random code. Statistical information giving the co-relation between majority decision levels, number of consecutive repeats and probability of error message loss rate is given in the Specification. If the system is used on single side band radio links, inherent audio frequency shift may be eliminated by transmitting two frequencies of difference equal to the bit rate, and preferably in harmonic relation. Alternatively crystal controlled oscillators may be used particularly with mobile H.F. systems at both ends and synchronization is performed by a message start pulses.  In certain systems, the message start signal may be the only information to be transmitted, i.e. in remote control systems, navigational aids and detonators fired by remote control.