Patent GB-1491520-A (GB)
Title: Computer with i/o control
IPC: G06F9/46
Filed: 1974-12-24
Abstract: 1491520 Program interruption HONEYWELL INFORMATION SYSTEMS ITALIA SpA 24 Dec 1974 [27 Dec 1973] 55704/74 Heading G4A In a microprogrammed computer, Fig. 1, comprising a main memory 1, a control unit 2, a priority network 3, a central processor 4, working register banks 5, 6 and peripheral units 8-11 having respective input/output channels 12-15, a program currently being executed by central processor 4 may be interrupted by a request for data transfer to or from a peripheral unit provided the request has a higher priority, as determined by priority network 3, than that of the program currently being executed. Each input/output channel has permanently assigned thereto registers 5.4-6.7 and 6.4-6.7 of the register banks 5, 6, which registers are used for storage purposes in ordinary character exchange between the central processor 4 and a peripheral unit; if the peripheral unit involved requires the use of additional registers for another type of data exchange, additional registers, e.g. 5.1, 6.1 (high priority) or 5.2, 6.2 (low priority) are assigned to the required input/output channel by means of a channel logic circuit 7. Within each input/output channel the interrupt requests are assigned predetermined relative priorities, the arrangement being such that a service being performed within a channel may be interrupted by a higher priority service on another channel; should the higher priority service be on the same channel it cannot interrupt even the lowest priority service but must wait until the service currently being performed terminates. Services of the same priority are mutually non-interruptible, be they on the same or different channels. Priority network (Fig. 7).-Interrupt signals INTA1-4 and INTB1-4, representative of two different types of interrupt requests A, B (e.g. to monitor the status of a peripheral unit or to forward a character), the numerals indicating a particular channel, are sent from a peripheral unit to the priority network where they are transferred to registers 113-115. Signals INTA1-4 are selectively passed to one of the registers 113, 114 via a switch 90 (controlled manually or by the central processor 4) having outputs 101-108, register 113 holding "fast" services in fixed relative decreasing order of priority, whereas register 114 holds "slow" services in fixed relative decreasing order of priority. Register 115 holds a third class of priorities for character exchange purposes. The outputs 126-137 of registers 113-115 are connected to a logical exclusion matrix 91 which transfers to one of its outputs 141-152 the corresponding input with the highest priority. Register 113 has a conditioning network comprising gates 92-96 which ensures that the interrupt signals INTA1-4 are mutually uninterruptable. For example, if signal INTA1 tried to interrupt a currently present signal INTA2, the outputs of AND gate 94, 93, 92 would respectively become 001, a "0" output produced by NOR gate 95 then inhibiting the reloading of register 113 (by means of a set pulse SET1 applied to AND gate 96) until the signal INTA2 is removed, i.e. until the servicing of the current interrupt request is completed. On the other hand, if INTA2 tried to interrupt INTA1, this would be prevented by the exclusion matrix 91 since INTA1 is of higher priority. Register 114 has a similar conditioning network (not shown), whereas signals INTB1-4 in register 115 are rendered mutually non- interruptible by inhibiting an AND gate 100 by means of a signal 97 (representative of a character exchange operation being in progress) applied via an inverter 163. The outputs 141, 145 and 149 of exclusion matrix 91 are fed to an OR gate 157, the output of which indicates to the control unit 2 and the central processor 4 the first channel. A similar arrangement via OR gates 159, 161 and 139 indicates the second, third and fourth channels. The outputs of further OR gates 98, 153 and 155 indicate whether a "fast" service, a "slow" service or a "character exchange" service is involved. Details of the channel logic circuit 7, the control unit 2 and the central processor 4 are given respectively in Figs. 6, 8 and 9 (not shown). The channel logic circuit 7, Fig. 6 (not shown), may transfer data in the form of a signal (DO) from a channel (43) of the central processor 4 to a peripheral unit via a register (30) and a driver (35) when that channel is enabled by a command (PS) from the priority network 7. A flip-flop (32) is set to provide, via a driver (36), a signal (CO) identifying the transfer operation as data transfer as opposed to a command or peripheral unit's address transfer, a flip-flop (33) also being set to provide, via a driver (37), a strobe signal (STO) which causes the signals (DO), (CO) to be sensed by the peripheral unit. The peripheral unit responds by means of signals (DI), (STI) and (SI) fed to respective receivers (38), (39) and (40), signals (DI) and (SI) being stored in a register (31) and by a flip-flop (34) respectively, and by means of the signals INTA, INTB fed to respective receivers (41), (42) which identify the two different types of interrupt requests. The contents of a flip-flop (56) indicate the direction of data transfer. A signal on a line (55), derived from the contents of flip-flop (56) and from the signals (STO), (STI), is monitored during data transmission; if this signal is "0", the microprogram "cycles" until data transmission is complete, the next data character being transferred when the signal has become "1". The control unit 2, Fig. 8 (not shown), comprises a read-only store (200), Fig. 8A (not shown), storing microwords and addressed by address registers (205)-(207) for respectively fast, slow and internal services. The address stored in any one of the address registers may be updated via an incrementing loop including an auxiliary address register (208) in one of four different ways. Ordinary character exchange is handled by the circuit of Fig. 8B (not shown) which includes a hardware sequencer circuit comprising cascaded flip-flops (240), (241). The outputs of the flip-flops are fed to a decoder (204) and thence to a timing network (202) to generate microcommands in conjunction with a timing circuit (201). The priority network 7 determines which one of registers (321)-(323) is to be assigned to a channel and assigns it by enabling respective gates (324)-(326), the read-out data from that register passing via a decoder (330) to the decoder (204). The central processor 4, Fig. 9 (not shown), comprises an arithmetical logic network (252) operating in parallel on two words A, B respectively received from working register banks (250), (251). Each register bank, e.g. (250), is subdivided into parts (A-SV), (A-SL), (A-CI) and (A-SC1/4) respectively dedicated to fast, slow or internal services and to character exchange services. The particular registers in register banks (250), (251) are selected by means of signals from the priority network 7 on lines (99), (154), (SCI), (158) and (160)-(162), and by microcommands on lines (256), (261).