Patent GB-1234579-A (GB)
IPC: H04Q11/04
Filed: 1968-09-24
Abstract: 1,234,579. Automatic exchange systems. ERICSSON TELEPHONES Ltd. 2 Sept., 1969 [24 Sept., 1968], No. 45406/68. Heading H4K. In a pcm switching system, in which serial signals on receive highways are set up in parallel on receive super-highways for selective connection to cord circuits from which they are passed to transmit super-highways in order to progress as serial signals on transmit highways, signals in the reverse direction being switched over the cord circuits by way of associated similar sets of highways, a spare receive and a spare transmit highway are provided by means of which signals to and from the cord circuits on the super-highways are duplicated so that faults affecting performance of the superhighways may be detected, a faulty superhighway pair being disconnected and the spare super-highways being substituted. As shown in Figs. 1, 2 and 3, receive highways R1 to Rn carry serial data in x channels which is set up over serial-to-parallel converters SP1 to SPn as parallel data in x time slots, such data being forwarded in frames F1 to Fn of x time slots each, each such frame being employed for a respective receive super-highway RS1 to RSn as well as for an associated one of the transmit super-highways TS to TSn which, over parallelto-series converters PS1 to PSn feed the highways T1 to Tn. A set of cord circutis C1 to Cm is accessible from the receive super-highways over a switching matrix RA and has access to the transmit super-highways over a switching matrix TA. For each connection set up over the system a pair of super-highways is involved giving access to and from the calling line in an odd-numbered time slot and another pair is involved in giving access to the called line in an even-numbered time slot. A cord circuit records addresses and by means of decoders D1 1 to Dm governs operation of gates in the matrices RA, TA at the appropriate time slots, operation in a time slot being divided into one half for reading out a message for transmission and a second half for writing in a message as received. The switching matrices RA, TA are augmented by switching arrays RF and TF to allow access between the cord circuits and the spare superhighways RSp and TSp in parallel with the super-highways RS1 to RSn and TS1 to TSn. In conditions of no fault a bi-stable Bp, Fig. 2, is set to open a gate GA3 to frame pulses M so as to step a binary counter BC frame-byframe and, by means of a decoder DC, to produce pulses S1 to Sn to cyclically connect the spare super-highways RSp and TSp to the highways R1 to Rn and T1 to Tn, and to connect the super-highways RS1 to RSn and TS1 to TSn to comparators RC and TC during the frames in which the super-highways are active. The spare super-highways have associated serialto-parallel and parallel-to-serial converters SPp and PSp and are also connected to the comparators RC and TC so that, should any difference arise between the data as processed over the spare highways and as processed over the other highways, a signal is delivered to gate GA1 and sent to the fault detector circuit of Fig. 3. Between successive exchange multiplex cycles of frames F1 to Fn (corresponding to pulses S1 to Sn) a period is provided for the production and utilization of control pulses SW1 to SW5 corresponding to an idle position Ao of the counter BC, Fig. 2. If a fault is attributable to a spare super-highway, or its parallel-toseries, or series-to-parallel converter, it will recur in every frame but if the fault is attributable to any other single super-highway it will recur only once in each exchange cycle. If the fault occurs on a super-highway other than a spare such highway its first effect is to set bi-stable U which in the next idle control period when SW4 occurs causes bi-stable V to be set. The following SW5 pulse resets U but leaves V set so that recurrence of the fault in the next exchange cycle sets U and enables W to be set by SW2 in the next idle control period. With W set in the next exchange cycle the reappearance of the fault signal will be gated directly over GW to operate an alarm L, to stop the counter BC by resetting the bi-stable Bp, and by resetting one of the bi-stables B1 to Bn to disconnect the output of the parallel-to-serial converter PS1 to PSn which is currently connected to the comparator by a pulse S 1 to Sn as presented by the halted counter BC. The code presented by the halted counter BC is applied to comparators AC 1 to ACm associated with each cord circuit, that cord circuit which presents the corresponding address of super-highways active in the so identified frame causing the associated comparator AC to produce a match and by inhibiting input to the associated decoder D effectively disconnecting the receive and transmit super-highways involved with the fault. The now permanently provided one of the pulses S1 to Sn holds the spare super-highways in circuit in place of the disconnected ones. If the fault is attributable to a spare superhighway it will set bi-stable Y1 on its first occurrence in frame F1 (pulse S1) and its repeated occurrence during subsequent frames will set bi-stables Y2 to Yn in turn. During the first idle control period, pulse SW4 will allow the set bi-stable U to set bi-stable V also and will open gate GZ to signal the alarm L and to stop the counter BC by resetting bi-stable Bp. As counter BC is stopped in its idle control position Ao no pulses S1 to Sn are present so the spare super-highways are disconnected without disturbing the function of the superhighways RS1 to RSn and TS1 to TSn.