Patent GB-1108003-A (GB)
Title: Signal switching system
Inventor: KIENZLE HARRY GALLAGER
IPC: H04L12/54
Filed: 1965-05-20
Abstract: 1,108,003. Automatic exchange systems; data transmission systems. WESTERN ELECTRIC CO. Inc. 20 May, 1965 [28 May, 1964], No. 21318/65. Headings H4K and H4P. A central processor governs connections set up over a time division multiplex network for digital transmissions as well as connections set up over a space division network for speech, the digital transmissions being stored and forwarded at a later time if the wanted outlet is unavailable. The central processor is the one employed in the Bell System No. 1 Electronic Switching System, the programme being expanded to control the t.d.m. digital message network and the store and forward facilities. Interconnection between the space division network and the time division network can be set up by way of analogue to digital converters. While the lay-out of the processor and network units is indicated the description is mainly concerned with the organization of the message store and forward equipment which is provided on a modular basis for ease of expansion and increased reliability. Digital message store and forward equipment.- Up to eight store and forward modules may be provided having access from and to terminal circuits of the t.d.m. network. Each module contributes 8 magnetic drum units and 8 magnetic tape units for storage of digital messages. The drum and tape units of each module are available to the input/output junctions of all modules over separate drum and tape switching networks. Each module is served by one high speed line (40À8 kilobits/sec.) and up to 24 low speed lines (2À4 kilobits/sec.) terminated on input/output circuits selectively connectible to a common data bus in accordance with instructions provided by an address register. When a digital message arrives demanding an outlet which is busy the central processor, which has a complete idle-busy plan of all store and forward equipment, selects a module and gives it a sequence of instructions to assemble the message in blocks for transfer to a particular location of drum or tape storage. The serial bit stream received over the line is gathered into uniformly sized characters stripped of supervisory bits in the line. input circuit of the module. Whenever a complete character is formed, a call is made. for the service of the module control circuit where a random access ferrite plate store is used to assemble the characters into larger blocks. The control circuit deals with service demands as queued according to order of arrival and priority as indicated by data from the central processor and stored in the module. When sufficient characters have been serviced to complete a block in the assembler store, a demand is made for drum or tape transfer in accordance with address data supplied from the central processor; the demand being queued for service by a drum or tape transfer circuit. When a digital message is to be forwarded from store the central processor specifies what equipment and storage locations are involved and causes the drum or tape record to be read out to the assembler store in the control circuit of the chosen module from which the data blocks are broken down into characters, transmission of a character producing a request for the next, and exhaustion of a block producing a request for a further block. Whereas supervisory digits are stripped from the received stream, they are inserted in the transmitted stream. Data is recorded on a drum unit in bands of three tracks each so that read-in and write-out is handled over three corresponding stepping registers so as to merge or form the three data streams. For local transmissions 63 word blocks are handled while inter-office transmissions have art additional error detection block. Transfer of data from drum to tape is handled in 256 word blocks. To address the drum store requires identification of drum unit, band number, and angular position, together with instruction as to read or write and word block size. Data is recorded on a tape unit as a stream of parallel arrays of 6 bits plus a parity bit in the seven tracks of the tape. Tape to buffer register transfers can be made over high and low clipped channels, the high clipped channel being used so long as parity signals hold true and the low clip channel being substituted if the parity of the high clip signals is false. Each record on the tape is preceded by a catalogue number by which a search can be made for the tape position.