baber/WOPTO huggingface dataset:
Patent JP-S5583145-A (JP)
Title: Ion injector
Inventor: INADA TSUGUO
IPC: H01L21/265
Filed: 1978-12-20
Abstract: PURPOSE: To prevent the mixing of unnecessary element into target thus to prevent the deterioration of the characteristic of element, by providing a slit made of silicon having an opening of predetermined area for determining the ion injection area into the target.  
     CONSTITUTION: The target 1 is a rotatable polygonal rod mountable with many sheets of specimens where a slit 4 constructed of silicon single crystal board having an opening 4' for determining the ion injection area and a slit for suppressing the secondary electron are located between the target 1 and the ion source. Said slit 4 is maintained to the ground potential to block a portion of ion beam from the ion source and to irradiate only such ion as passed through said opening 4' on the target 1 while has no blocking function on such ion beam as passed through the opening 4'. Consequently the mixing of unnecessary element into the target can be prevented. 
     COPYRIGHT: (C)1980,JPO&Japio
Patent JP-H0323639-A (JP)
Title: Thin-film transistor
Inventor: SASAKI MASAYOSHI
IPC: H01L21/84
Filed: 1989-06-21
Abstract: PURPOSE:To obtain a thin-film transistor whose carrier mobility is not lowered, whose threshold voltage is not increased and whose element characteristic is good by using a polycrystalline semiconductor thin film which contains the specific number of fluorine atoms. CONSTITUTION:Fluorine atoms of 1X10<18> to 1X10<21>cm<-3> are contained both in polycrystalline Si thin films for source.drain region use and for channel region use and in a polycrystalline Si film for gate electrode use. The fluorine may be either in a molecule state or in an atom state; in the case of atoms, an ion state is included. In order to contain the fluorine, a thin-film transistor is formed, and, after that, the fluorine is introduced into the thin film by a method to implant F<+> ions or the like.
Patent JP-S5859570-A (JP)
Inventor: YOTSUGI SANJI
IPC: H01B17/58
Filed: 1981-10-05
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H10332731-A (JP)
Title: Acceleration and deceleration visualizing device and method
Inventor: SAKURAI TAKASHI
IPC: G01P15/18
Filed: 1997-06-02
Abstract: PROBLEM TO BE SOLVED: To provide a device and a method which can quantitatively grasp a value of acceleration/deceleration with simple construction. SOLUTION: There are provided an air bubble 114 which is so constituted that it is stopped at a central reference position, the most stable due to balance of physical forces, when acceleration/deceleration does not work and that it is moved by an amount according to an acceleration/deceleration value from the reference position by an inertia force only when the acceleration/deceleration is working, and a value visualization part 11 holding the reference position in the immobile state on a relative coordinate system, maintaining the air bubble 114 and having an acceleration/deceleration value scale 115, and a value in the horizontal direction component of acceleration/deceleration can be quantitatively visualized by scale point indicated by the air bubble 114.
Patent JP-S643731-A (JP)
Title: Detecting method for film bar code
Inventor: YASUI YOICHI
IPC: G06K7/00
Filed: 1987-06-25
Abstract: PURPOSE:To reduce the cost of parts and to facilitate the maintenance through simplification by detecting the bar code information on a photographic roll film after ternalizing it and obtaining a bar code through the comparison and calculation of the ternalized data. CONSTITUTION:A bar code arithmetic processing part 17 does not process directly the 1-block data (a start bit through an end bit) as the analog data but ternalizes the 1-block data through the comparison of this data with its preceding and next data. In other words, the data is modeled into a code part, a blank part and an intermediate part of a bar code 5 so that the codes within the model data of the clock bit or the model data of the data bit corresponding to the blank is obtained. If the intermediate model data is obtained, the model data is compared with the analog data on both clock and data bits for decision of the model data on the data bit. In this case, just a single photodetector is needed for each of two tracks of the code 5 and therefore the mechanism is simplified together with the facilitated maintenance.
Patent JP-S5948744-A (JP)
Title: Back projection screen
Inventor: TAKAHASHI HIDEO
IPC: G03B21/62
Filed: 1982-09-13
Abstract: PURPOSE:To increase both a horizontal and a vertical visual-field angle, by designing a lenticular lens on an observation side so that part of incident light is totally reflected once and then projected to the observation side. CONSTITUTION:A lateral lenticular lens 3 is formed on the projection side A of a screen 1 made of a synthetic resin material having good light transmissivity such as a methacrylic resin and a longitudinal lenticular lens 2 is formed on the observation side B. Then, the longitudinal lenticular lens 2 is designed partially or entirely so that part of the incident light is totally reflected once and then projected to the observation side B. Light incident to the projection side A is expanded vertically by the lateral lenticular lens 3 and then expanded horizontally, so the lateral visual-field range is expanded simultaneously with the lateral visual-field range.
Patent JP-H0449716-A (JP)
Title: Offset setting system for oscillator output
Inventor: NAKANO TOSHIYA
IPC: H03K4/06
Filed: 1990-06-18
Abstract: PURPOSE:To automatically set offset on the arbitrary amplitude of oscillator output by supplying a voltage of 1/2 the Peak to Peak voltage of the oscillator output to an oscillator as an offset voltage, and always setting the low level of the oscillator output at ground potential. CONSTITUTION:Firstly, a change-over switch 6 is switched so as to supply the output of an arithmetic means 5 to an offset voltage generating means 2, thence, the oscillator 1 is started up. A voltage measuring means 4 measures the Peak to Peak voltage of the output voltage of the oscillator 1, and supplies it to the arithmetic means 5. The arithmetic means 5 calculates the voltage of 1/2 the Peak to Peak voltage, and supplies the value of the voltage to the offset voltage generating means 2 via the change-over switch 6. The offset voltage generating means 2 supplies the voltage of 1/2 the Peak to Peak voltage of the oscillator output to the oscillator 1 as the offset voltage. In such a way, the low level of the oscillator output is always kept at the ground potential.
Patent JP-S644190-A (JP)
Title: Chrominance signal processor for magnetic recording and reproducing device
Inventor: SATO TADANOBU
IPC: H04N9/83
Filed: 1987-06-25
Abstract: PURPOSE:To decrease a chrominance signal rising time attended with the changeover of recording/reproduction by fixing an output voltage of an APC detection circuit at the time of recording and an output voltage of an AFC detection circuit at the time of reproduction respectively to a prescribed voltage. CONSTITUTION:An output voltage of an AFC detection circuit 12 is a voltage V at the time of recording and a VCO 5 is oscillated at 320fH in this case. A fixed voltage generating circuit 15 receives an output of the AFC detection circuit 12 to output a voltage V to fix the output voltage of the APC detection circuit 11 to the voltage V via a switch S3. Thus, almost the same control voltage is applied to the VCO 5 even when the recording mode is switched to the reproduction mode. The switch S3 is changed over to the position of reproduction at the time of changeover from the reproduction to the recording and the output voltage of the AFC detection circuit 12 is fixed to the voltage V by the fixed voltage generating circuit 15.
Patent JP-S5679514-A (JP)
Title: Variable phase shifter
Inventor: FUKUHARA NAOYUKI
IPC: H03H7/20
Filed: 1979-12-03
Abstract: PURPOSE:To simplify the constitution of a variable phase shifter, by taking at least one of capacitive elements as a variable capacitive element. CONSTITUTION:A bridge T type circuit is constituted with resistors 3, 5 of resistance value R, capacitor 2 of capacitance C and a variable capacitor 4. Taking the capacitance of a variable capacitor as kC, the voltage transfer ratio when load is opened is (E2/E1)=[1-komega<2>C<2>R<2>+jomegaCR(1+k)]/[1-komega<2>C<2>R<2>+jomeg aCR(2+k)] at I2=0. By changing the capacitance kC of the variable capacitor 4, the phase between the input and output signals at an arbitrary frequency can be changed.
Patent JP-S5861440-A (JP)
Title: Loading type automatic consolidation tester
Inventor: YAMASHITA KOUICHIROU
IPC: G01N3/14
Filed: 1981-10-08
Abstract: PURPOSE:To obtain a loading type consolidation tester which loads weights on a weight-loaded part automatically and successively without the intervention of an operator through an updards and downwards moving device under the control of a control part. CONSTITUTION:A motor 16 operates by receiving a command from a microcomputer 10 to lower an upwards and downwards moving wire 15, thereby loading a weight 17A on a weight-loaded part 2. The resulting inclination of a rod lever 1 is detected by dial gauges 4 and 4', whose detection signals are inputted to the microcomputer 10; and the microcomputer 10 sends an indication to motors 6, 6', which operates to move vertical supporting levers 4 and 4' upwards and downwards. Consequently, the rod lever 1 is held horizontal to vertically load a body 13 to be tested through a loading frame 11, and the extent of the sinking of the body 13 is measured by the dial gauge 14 and stored in the microcomputer 10.
Patent JP-H097974-A (JP)
Title: Semiconductor device
Inventor: NAKAMURA TOMOMI
IPC: H01L21/301
Filed: 1995-06-26
Abstract: PURPOSE: To provide a semiconductor device which prevents notching into an integrated circuit upon timing. CONSTITUTION: Guide patterns 3, 4 are provided on first and second parts 21, 22 of a scribe line 2 between integrated circuits 1, respectively. The guide pattern 3 comprises a pair of opposing wall parts 30 to 30, and the wall part 30 is formed along the scribe line 2 and has opposite ends thereof that are opened toward the outside to guide a cutter in the direction of the scribe line 2 upon dicing. The guide pattern consists of four wall parts 41 to 41 extending to four corners 22 to 22 of an intersection from a central part of the intersection part excepting the central part, and a cutter is guided in any intersected scribe line 2 directions upon dicing. Hereby, displacement of the cutter upon the dicing is corrected and hence notching into an integrated circuit is prevented.
Patent JP-S5860970-A (JP)
Title: Preparation of mustard paste
Inventor: SUZUKI HAJIME
IPC: A23L27/18
Filed: 1981-10-08
Abstract: PURPOSE:To prepare mustard paste having little tendency to generate sulfur-like ill odor, by immersing mustard powder from the first in hot water, and then removing the most part of water therefrom. CONSTITUTION:1pt.wt. of mustard powder is immersed in 7-15pts.wt. of hot water of 60-90 deg.C, preferably 70-80 deg.C for several seconds to several minutes, preferably for <=1min, and the most part of the water attached to the mustard powder is removed by filtration, centrifugal separation, etc. The mustard plaster thus obtained is compounded with salt, vinegar, sugar spices other than mustard powder, edible oil, etc., and kneaded.
Patent JP-S5683858-A (JP)
Title: Three-stage displacement driving device
Inventor: OONUKI HIDEYO
IPC: G11B15/10
Filed: 1979-12-07
Abstract: PURPOSE: To make the device small-sized to reduce the cost, by using two electromagnetic plunfers to displace the driven material in three stages different in movement distance.  
     CONSTITUTION: The first plunger (PL) 34, the second plunger 35, lever 47, and the driven material consisting of head stand 31 and so on are provided. Lever 47 has the first action point near hole 48 to which force is given by the first PL34, the second action point near hole 49 to which force is given by the second PL35, and the third action point such as fulcrums 50 and 51 which given force to the driven material. When only the first PL34 is operated, lever 47 is rotated with the second action point as the fulcrum; and when only the second PL35 is operated, lever 47 is rotated with the first action point as the fulcrum. When the first and the second Pls 34 and 35 are operated together, the first and the second action points move in approximately equal directions, however, displacement quantities in these three cases are different from one another. 
     COPYRIGHT: (C)1981,JPO&Japio
Patent JP-S5583319-A (JP)
Title: Surface elastic wave element
Inventor: HIRABAYASHI MAKOTO
IPC: H03H9/145
Filed: 1978-12-20
Abstract: PURPOSE:To obtain needed filter characteristics by making resistance values of elements different by varying specific resistances and thicknesses of comb line electrode elements of a transducer. CONSTITUTION:On piezoelectric substrate 11, Cr film 16 is bonded in the same pattern as electrode 15 and Al film 15 is selectively stacked at parts of connection part 14 and electrode element 13. In another method, electrode element 13 is made to vary in film thickness partially or entirely with the length-directional part as to a needed electrode element. In this way, a transducer is formed which has respective elements of comb line electrode 15 varying adequately in resistance value, so that a surface elastic wave element with needed filter characteristics can be obtained.
Patent JP-S644758-A (JP)
Title: Electrostatic copying machine
Inventor: TANAKA YOSHIHISA
IPC: G03G15/00
Filed: 1987-06-29
Abstract: PURPOSE:To easily remove jammed paper by making plural receiving projections freely movable between an action position where those projections project upward through plural apertures formed on a receiving plate and a non-action position where those projections position under the receiving plate in substance. CONSTITUTION:A copying paper receiving part provides the receiving plate 144 which flatly extends in the feeding direction of the copying paper in substance and plural receiving projections 146 disposed at intervals in the width direction of the receiving plate 144. And plural receiving projections 146 can freely move between the action position where they projects upward through plural apertures formed on the receiving plate 144 and the nonaction position where those projections position under the receiving plate 144 in substance. Then, a comparatively large space can be formed between the rear part of the receiving plate 144 and a movable frame body 222. Thus, the jammed paper can be easily removed.
Patent JP-2000345584-A (JP)
Title: Slewing type excavating working car
Inventor: KOBAYASHI MASAHIKO
IPC: E02F9/08
Filed: 1999-06-07
Abstract: PROBLEM TO BE SOLVED: To improve operating efficiency, and to reduce fatigue by installing a working machine or the like, approximately equalizing size (slewing radii) from the center of a revolving superstructure to the frontest end of a working- machine mounting section and a rearest end and making the confirmation of the interference of a rear section unnecessary in the case of slewing. SOLUTION: The maximum size L1 from the center of rotation 0-0 of the working car 1 to a working-machine mounting section 6 and maximum size L2 to the rear end (substantially the rear upstanding surface of a counterweight 21) of a machine body 4 are set at approximately the same values. When a slewing motion is repeated under the state in which a working machine 7 is intruded to a workshop, on which there is a low obstruction A or a high obstruction B, and lifted and held, subsequently only a front section or a rear section may be confirmed when whether or not the working machine interferes in A or B only at first by a driver is confirmed. Relation fins are mounted on a working fluid tank besides the formation of hollowed-out holes to a boom 7A, and arm 7D or the like and lightening, and an oil temperature rise is inhibited by the outside air and workability is improved.  Accordingly, the fatigue feeling of the driven is reduced while operating efficiency can be improved.
Patent JP-S5587517-A (JP)
Title: Method and apparatus for cleaning resin-molding mold
Inventor: SHIMIZU TAKESHI
IPC: B29B13/00
Filed: 1978-12-27
Abstract: PURPOSE:To shorten molding cycle by mechanically cleaning the inside surface of a mold after resin molding without complete mold separation, in assembling process of a resin-sealed type semiconductor device. CONSTITUTION:After resin molding, the inside surface of a mold is cleaned as follows. With upper and lower molds 1 and 2 separated from each other, a protective cover is moved to cover a molded body 4 positioned in the opening, and cleanners 8 and 9 are moved following up to the movement of the cover to clean the inside surfaces of the molds 1 and 2. After cleaning, the cover is moved out of the mold, and the resin-molding mold is cleaned. Since the cleaning can be carried out easily, the molding cycle in a continuous assemly step can be shortened.
Patent JP-S5683699-A (JP)
Title: Sealing method for pipe
Inventor: IKEGAMI KIYOUZOU
IPC: B01F3/04
Filed: 1979-12-10
Abstract: PURPOSE: To achieve a sealing function with a comparatively less energy, by a method wherein, when sealing an underground pipe for conveying city gas, a sealing liquid is heated to less than a boiling point to form atomized particles which are fed into a pipe.  
     CONSTITUTION: In a heating atomizing system 7, a pipe 1 is sealed, and liquid, for example, ethyleneglycol, which prevents dispersion of the dusts in a pipe 1, is atomized and is mixed with city gas extracted through a pipe 18. A part of the ethyleneglycol is vaporized by a dielectric heating system 8 located at a pipe 6, and is fed into the pipe 1. This allows the control of the sealing range of the liquid in the pipes 1 and 2 corresponding to the vaporizing degree of the heating system 8. This permits the improvement of a sealing property through swelling of a sealing yarn 4 by the use of various types of liquids and the prevention of dust dispersion. 
     COPYRIGHT: (C)1981,JPO&Japio
Patent JP-H08328644-A (JP)
Title: Method for analyzing fluctuation in process
Inventor: TAGUCHI FUJITAKA
IPC: G06F17/15
Filed: 1995-06-03
Abstract: PURPOSE: To analyze significant fluctuation in a process systematically. CONSTITUTION: In a process having lots of process variables in which causality relations are related to each other in terms of a tree structure, the process variables are traced sequentially along a path from the resulting point toward the cause point, secular measurement data of two adjacent process variables are subjected to FFT processing at need to obtain the correlation coefficient and a weight is multiplied at need by the plural correlation coefficients along the path to obtain a geometric mean and the degree of the effect of the process variables of the cause side onto the fluctuation in the process variables of the result side is analyzed depending on the magnitude of the geometric mean obtained from all possible paths. Then the maximum geometric mean among those obtained from all possible paths is obtained and a path indicating the maximum geometric mean is extracted in this analysis.
Patent JP-H11353156-A (JP)
Title: Carry signal generating circuit
Inventor: EBATA ATSUSHI
IPC: G06F7/508
Filed: 1998-06-09
Abstract: PROBLEM TO BE SOLVED: To make an adder fast by shortening the total carry signal generation time including precedent and trailing stages as to a precedent-stage circuit and a trailing-stage circuit which constitute the carry signal generating circuit by precedently processing part of logical operation of the trailing-stage circuit by the precedent-stage circuit. SOLUTION: When carry signals for 4-bit binary data a0 a1 a2 a3 and binary data b0 b1 b2 b3 are generated, a signal p0 represented as p0 =a0 +b0 , a signal Hi ,i+1 represented as Hi ,i+1 =ai .bi +ai+1 (i=0, 2), and a signal I1.2 represented as I1 ,2 =(a1 +b1 ).(a2 +b2 ) are generated. Their signal processings can be carried out in parallel. Then those signals p0 , Hi ,i+1 , and I1 ,2 are used to generate a 4-bit carry signal C<4bit> represented as C<4bit> =p0 .(H0 ,1 +I1 ,2 +H2 ,3 ). Consequently, the number of NMOS transistors which are stacked and connected longitudinally is decreased to shorten the circuit operation time.
Patent JP-H11353673-A (JP)
Title: Optical head actuator
Inventor: TERAJIMA KOKICHI
IPC: G11B7/09
Filed: 1998-06-09
Abstract: PROBLEM TO BE SOLVED: To provide an optical head actuator capable of correcting the aberration caused by the inclination of the optical axis of an objective lens and the warpage of a disk or the like and recording and reproducing information stably. SOLUTION: In this actuator, a lens holder 4 is hung and supported displaceably by a supporting means through four pieces of first elastic members 31. In this case, the supporting means has a first supporting member 101 and a second supporting member 102 which is linearly displaceable at least in either a Z direction or a Y direction while being away in either the Z direction or the Y direction in an X-Y-Z orthogonal coordinate system with respect to the first supporting member 101 and adjacent two pieces of the four pieces of the first elastic members 31 are supported by the second supporting member 102.
Patent JP-H05331681-A (JP)
Title: Surface treated steel sheet having plural plated layers and excellent in corrosion resistance and weldability
Inventor: FURUYA HIROHIDE
IPC: C25D5/10
Filed: 1992-05-27
Abstract: PURPOSE:To provide a surface treated steel sheet excellent in corrosion resistance after coating, bare corrosion resistance (red rust resistance and white rust resistance) and weldability, furthermore good in a surface appearance and suitable as a steel sheet for a container made of steel such as a can. CONSTITUTION:On the surface of a steel sheet, a metallic chromium plated layer as a lower layer is formed by the amt. of 30 to 300mg/m<2>, on the metallic chromium plated layer, a galvanized layer as an intermediate layer is formed by the amt. of 10 to 2000mg/m<2>, on the galvanized layer, a tin plated layer as an upper layer is formed by the amt. of 50 to 2000mg/m<2> or, on the metallic chromium plated layer, a zinc-tin alloy plated layer as an upper layer constituted of 10 to 2000mg/m<2> and 50 to 2000mg/m<2> tin is formed.
Patent JP-H0451607-A (JP)
Title: Wiring method for preventing load reflection
Inventor: MIYAMOTO YOSHIHIKO
IPC: H05K3/46
Filed: 1990-06-19
Abstract: PURPOSE:To prevent reflection noise and to eliminate the need of considering noise owing to reflection at the time of design by wiring a section where a specified condition is satisfied based on net constitution and the load capacitance of LSI pins at high impedance in a very high speed net. CONSTITUTION:When net constitution is that more than one pin of drivers DR and more than two pins of receivers RC1-RVn exist, the impedance of wiring before or behind the receivers is set to be high and quantity that impedance drops is cancelled by the load capacitance. Namely, high impedance wiring is executed when loads (1, 2,..., n from a driverside) connected to respective branching points STUB on the net satisfy a following inequality without fail. Namely, it is assumed that STUB(i)>=STUB(i+1) (however (i) = 1, 2,..., n-1) and the capacitance of STUB is calculated in accordance with the expression of STUB(i)=LSI pin capacitance + intra-LSI wiring capacitance. Intra-LSI wiring capacitance is the capacitance of wiring from the pin to an initial element in LSI. Thus, the feedback of circuit design can be eliminated.