Patent GB-1363012-A (GB)
Title: Electronic scanner checking process and system
IPC: H04Q3/545
Filed: 1972-03-02
Abstract: 1363012 Automatic exchange systems INTERNATIONAL STANDARD ELECTRIC CORP 2 March 1972 [5 March 1971] 9724/72 Heading H4K In a system including a scanner which in response to the reception of a scanning order from a central unit scans step-by-step units or groups of units and in which the scanning results, when they have certain values, cause the stoppage of the scanning and the calling of the central unit, there is provided a special operation for checking the operation of the scanner which includes the reception from the central unit of a checking order, whereupon the scanner executes a step-by-step scan of said units or groups of units stopping at certain predetermined points in the scanning cycle; at each such point the scanner calls and informs the central unit that it has reached the particular predetermined point. In particular the scanner is a subscriber line circuit scanner as described in Specification 1,363,011 and for details of the normal operation of the scanner reference is directed to the above Specification. Operation.-To start a scanning operation whether it be a normal or check scan the central unit UC writes an instruction into register RO via link CRO. This instruction is a 16-bit word recorded by 16 bi-stables forming register RO. This instruction comprises a 3-bit indication OR for specifying the type of instruction to be executed, e.g. normal N, or check C; a 3-bit constant indication AD 1 giving a first part of the address of the units to be scanned; and a 6-bit variable indication AD2 giving a second part of the address of the units to be scanned. The indications AD1 and AD2 define an address corresponding to a group of 8 units which are interrogated simultaneously during a single scanning step and an incrementation circuit IN is used to step the 6-bit indication AD2 by one at the end of each step such that after receiving the initial scan instruction, the scanner automatically scans 64 groups of 8 units. For a normal scanning instruction, a decoder DO yields a signal ACSC, indicating the presence of an order, and a signal N indicating a normal scanning operation. The central unit UC then gives a starting order by setting bi-stable GO to 1 via link SGO. At this time a condition EOJ is present and signals ACSC and GO cause the clock HG to operate and deliver the time signals shown in Fig. 2. The signal BV gates the address of the group to be scanned to the scanning circuits CE, the signal RZ1 resets the results register R1, and the signal MVRS gates the result of the scanning operation to the results register R1. If the scan result RE is positive, i.e. action by the central unit is required, analysis circuit REV produces an order EV. This signal EV together with signals N and t6 cause the signal EOJ to change to EOJ which resets bi-stable GO and stops the clock. Time signal t7 is not then produced and AD2 is not incremented. The central unit reads out the contents of the registers R0 and R1 and then restarts the scanning by setting bi-stable GO to 1, the condition EOJ having reverted to EOJ at the termination of signal t6. The clock restarts, pulse t7 is produced, and the instruction AD2 increments by one. If the signal EV had not been produced, the clock would not have been stopped and the signal t7 would have been produced without the intervention of the central unit. Checking scan.-Instead of a signal N a signal C is obtained from decoder DO. The presence of this signal causes the condition EOJ to change to EOJ when the incrementation circuit IN produces signals ad00, ad21, ad42, and ad63, i.e. the scan is stopped and the central unit called up. The scan is not stopped if the condition EV is produced because the signal N is absent from AND gate pc9, i.e. the results of the scanning operation are ignored. At each of the above four predetermined stopping places the central unit reads out the contents of the address register R0. As the stopping points correspond to the 0th, 21st, 42nd and 63rd stages the reading that should be obtained for variable instruction AD2 is respectively 000000, 010101, 101010, and 111111 in binary. Hence the central unit can determine that both the clock and the 6 bi-stables forming the circuit containing the variable instruction are working correctly.