Patent GB-882525-A (GB)
Title: Improvements in or relating to magnetic information storage arrangements
Inventor: BREWSTER ARTHUR EDWARD
IPC: G11C7/02
Filed: 1958-10-23
Abstract: 882,525. Circuits employing bi-stable magnetic elements. STANDARD TELEPHONES & CABLES Ltd. Oct. 23, 1958, No. 33934/58. Class 40 (9). [Also in Group XL (c)] The pulse code modulating circuits described in Specification 849,894 are applied to a multiplex system, each channel utilizing a separate coding circuit the reading cores of which are differently biased so that each circuit transmits a coded pulse train in turn. As described in the prior Specification, an amplitude-modulated signal sets up a digit code on selected output storage cores of a coding circuit, and the digit pulses are transmitted by sequentially reversing the state of reading cores, each associated with a separate output core. The selected output cores are thereby restored to their initial state in turn, whereby a serial pulse train is generated in a common output lead. The operation of a circuit is controlled from a sampling source by two sinusoidal waves, Phase-1 and Phase-2, Fig. 1, in quadrature, and the reading operation takes place during the time that Phase-2 passes from a negative to a positive maximum. In the arrangement described four coders are allotted to a common sampling source, and other coders up to a total of 24 may be controlled in groups of four by sampling sources operating in different phase positions. By biasing the reading cores of coders 1 to 4, Fig. 2, comprising a group to different extents, the respective pulse trains occupy the spaced time positions shown during the negative to positive excursion of Phase-2. Each coder has a reading core circuit as shown in Fig. 3, comprising cores 2-9, each with a separate output winding 12. The cores are biased to different extents by main bias 14 and auxiliary bias 15, 16 windings, all the bias windings having different numbers of turns or windings, all the bias windings having different numbers of turns or winding directions so that each core is triggered in turn when the Phase-2 wave from source 11 is applied to a triggering winding 10. By operating switches 18 and 19 so as to by-pass or reverse the auxiliary bias windings, the reading core circuit is able to operate in any of the four coder time positions shown in Fig. 2. Instead of using switches, the coder terminals A-K may be connected to corresponding terminals on a plug 35, Fig. 4, to which is also connected the common output J-K from the output cores 21 and an output rectifier 36. The bias voltage source 17 and the Phase-2 source 11 are both connected to a group of four sockets 31-34, each socket being differently wired as far as the bias circuits are concerned so that the time position of the digit code generated depends on which socket is connected with the plug. A similar plug may be connected to a code simulator, Fig. 5, which combines the read-out and output core circuits. As shown, cores 2-9 are biased to different extents as previously described, but the triggering pulse from the Phase-2 source is applied to selected cores only in accordance with the positions of switches 38. Corresponding output pulses are generated in the output winding 12 which are applied directly to output terminals J and K.