baber/WOPTO huggingface dataset:
Patent TW-415135-B (TW)
Title: Process and the manufacturing device of connector
Inventor: CHEN WEN-SHIUNG
IPC: H01R43/00
Filed: 1998-12-30
Granted: 2000-12-11
Abstract: The present invention provides a process for producing a connector and a device for producing the same, which comprises the following steps and production devices: (a) motherboard press folding line: forming a main board and an auxiliary board; (b) installing fastener fastening connector: soldering a fastener of a hat-shaped metal frame on an auxiliary plate with a small amount of solder paste to fasten a connector; (c) front SMT solder furnace; (d) back SMT solder furnace; (e) removing the auxiliary plate and the fastener: folding the auxiliary plate along the folding line while detaching the fastener; or (a) installing a fastener to fasten the connector: installing a line of dots scheduled to be broken on the soldering leg of a hat-shaped metal frame so as to semi-rigidly soldering the frame on the motherboard to fasten the connector; (b) front SMT solder furnace; (c) back SMT solder furnace; (d) removing the fastener: breaking the line of dots scheduled to be broken and separating the fastener. Therefore, when undergoing an SMT operation, the connector will be fastened by the fastener and will not lop down due to the gravity per se, thereby ensuring the accuracy and stability of the soldering operation and increasing the yield of the overall production.
Patent TW-527495-B (TW)
Title: System for automatic workpiece cutting and sorting and method for controlling same
Inventor: BYUN SUNG-JOON
IPC: G02F1/136
Filed: 1999-03-15
Granted: 2003-04-11
Abstract: Disclosed are a system for automatic workpiece cutting and sorting, and a method for controlling the system. The system includes a cutting/sorting equipment for cutting a substrate having a plurality of cells to form cut substrates, and sorting the cut substrates according to a predetermined mode; and a system controller for receiving a request for operation information on the cut substrates from the cutting/sorting equipment, and transmitting the operation information and operation commands to the cutting/sorting equipment. The method includes the steps of (a) determining an operating mode of the cut substrates cut by the cutter; (b) sorting the cut substrates and supplying the sorted cut substrates to one of the plurality of cassettes according to the operating mode of the cut substrates determined in step (a); and (c) repeating steps (a) and (b) for a predetermined lot number of cut substrates.
Patent TW-432700-B (TW)
Title: Memory-cells arrangement and its production method
Inventor: REISINGER HANS
IPC: H01L27/11568
Filed: 1999-03-22
Granted: 2001-05-01
Abstract: This invention relates to a memory-cells arrangement, in which in the region of a main face of a semiconductor-substrate (10) are existent many memory-cells, said memory-cells contain respectively at least one MOS-transistor with source (29), Gate (WL1 or WL2) and drain (60), said memory-cells are arranged in basically parallel running memory-cells rows, in which the adjacent memory-cells rows are isolated by some isolation-trenches (20); the adjacent memory-cells rows contain respectively at least one bit-line (60) and the bit-lines (60) of two adjacent memory-cells rows face towards each other. According to this invention, said memory-cells arrangement is so constructed that the isolation-trench (20) penetrates more deeply into the semiconductor-substrate (10) than the bit-lines (60) and below the isolation-trench (20) is existent at least a portion of the region of said source (29) and/or said drain. This invention also relates to a method to produce said memory-cells arrangement.
Patent TW-411520-B (TW)
Title: Plasma etching process
Inventor: IIMURO SHUNICHI
IPC: H01L21/3065
Filed: 1999-05-07
Granted: 2000-11-11
Abstract: Contact holes (36a, 36b) are formed in a silicon oxide insulation film 31 by a plasma etching process so that the contact holes can extend to wiring layers 33a 33b which are embedded in the insulation film 31 at deep and shallow positions, respectively. A treatment gas containing C4F8, CO, Ar is used, and the treatment pressure is set to be 30-60 mTorr, while the partial pressure of C4F8 is set to be 0.07 to 0.35 mTorr. The treatment gas is formed into a plasma under these conditions, and the insulation film 31 is etched with the plasma to form the contact holes 36a, 36b.
Patent TW-I222983-B (TW)
Title: Epoxy resin composition for semiconductor encapsulation and semiconductor device obtained with the same
Inventor: TANIGUCHI TAKASHI
IPC: H01L23/29
Filed: 1999-06-09
Granted: 2004-11-01
Abstract: An epoxy resin composition for semiconductor encapsulation which does not cause the chip tilting attributable to resin flow during resin encapsulation, such as semiconductor element shifting and gold wire deformation, and is capable of yielding highly reliable semiconductor devices. The epoxy resin composition for semiconductor encapsulation comprises an epoxy resin, a phenolic resin, a hardening accelerator, and an inorganic filler, and has the following properties (X) to (Z): (X) the viscosity thereof as measured with a flow tester at 175 DEG C is from 50 to 500 P; (Y) the minimum melt viscosity thereof as determined from the temperature dependency of viscosity thereof as measured with a dynamic viscoelastic meter at a shear rate of 5 (1/s) is 1x10<5> P or lower; and (Z) the ratio of the viscosity thereof as measured at 90 DEG C (Z1) to that as measured at 110 DEG C (Z2) both with a dynamic viscoelastic meter at a shear rate of 5 (1/s), (Z1/Z2), is 2.0 or higher.
Patent TW-507141-B (TW)
Title: Automatic classifying system and method with embedded semantic analysis
Inventor: WU YI-CHENG
IPC: G06F17/40
Filed: 1999-06-22
Granted: 2002-10-21
Abstract: An automatic classifying system with embedded semantic analysis for automatically classifying a document, which uses a syntax analyze to generate the document object model for the document for separating the contents under each tag; then, using the ratio when the tag definition configuration data is used to define the content under each tag in selecting the key words, for finding the key words, and classifying the document based on the key words.
Patent TW-438700-B (TW)
Title: Ship of merchant marine with a hull which is specified to accept goods and/or persons
Inventor: ANDERSEN PETER
IPC: B63H1/02
Filed: 1999-07-09
Granted: 2001-06-07
Abstract: A ship of merchant marine with a hull, which is specified to accept goods and/or persons, and with at least one rotatable rudder-propeller as a drive-unit, wherein said rotatable rudder-propeller is arranged in a case-shaped connection-unit in the end-portion of the hull and wherein the necessary components to control the rudder-propeller are located in said hull, wherein the rudder-propeller has an electrical propeller-motor, the electrical and mechanical components to supply energy and to control the rudder-propeller and its electrical motor are collected at least a part in the function-modules, which are constructed as transport-containers, especially as standard-containers, these containers are fully function-testable on their construction-sites and can be taken away by some classification-companies and can be mounted in this form on any mounting-site of the ships by means of a container-bottom-construction.
Patent TW-427027-B (TW)
Title: Manufacturing method for MOS transistor
Inventor: LEE TZUNG-HAU
IPC: H01L29/772
Filed: 1999-08-18
Granted: 2001-03-21
Abstract: The present invention provides a manufacturing method for MOS transistor on the silicon substrate surface of a semiconductor chip. The inventive method is firstly forming a silicon oxide on the silicon substrate surface; and, forming a polysilicon layer and a smaller silicon nitride on the surface of silicon oxide; then, forming a silicon oxide spacer around the polysilicon layer and silicon nitride; and, removing the silicon nitride on the inner side of the spacer; forming the source and the drain of MOS transistor on the silicon substrate on the outer side of the spacer; then, uniformly forming a conductive layer on the surface of semiconductor chip and filling the gap inside the spacer; then, employing the CMP to remove the top area of the spacer so that the conductive layer inside and outside the spacer can be separated by the spacer and forming the gate of the MOS transistor and the landing pad of the source and the drain respectively.
Patent TW-390983-B (TW)
Title: Sensor type liquid level control apparatus
Inventor: CHEN BO-HUEI
IPC: G05D9/00
Filed: 1999-08-21
Granted: 2000-05-21
Abstract: The invention relates an sensor type liquid level control apparatus, in which a plurality of conductive connectors at different height are built in the water tank. A control circuit connected to each conductive connector is also constructed. The liquid level is effectively controlled by the mutual conductivity between each connector. The liquid level control apparatus can also be used with de-ionized water to expand the suitable application range and the flexibility.
Patent TW-539665-B (TW)
Title: Liquid vacuum pump seal to reduce contamination in bisphenol-A
Inventor: KISSINGER GAYLORD MICHAEL
IPC: C07C39/16
Filed: 1999-09-03
Granted: 2003-07-01
Abstract: An improved process for producing Bisphenol-A which is essentially free of sodium impurity using rotary vacuum filter pumps which utilize a liquid ring seal to effect drawing a vacuum on a Bisphenol-A/phenol slurry, the improvement is in using phenol as the liquid ring seal medium.
Patent TW-498086-B (TW)
Title: Basic-dyeable ethylene terephthalate copolyester polymer containing sodium sulfonate salt of a glycollate of isophthalic acid
Inventor: ANEJA ARUN PAL
IPC: C08G63/78
Filed: 1999-09-27
Granted: 2002-08-11
Abstract: New copolyester composition that provides excellent filament spinning and mill/yarn processing of staple fiber into fabrics having combination of excellent pilling performance as well as aesthetics and tactility (""hand""). Preferred fibers have non-round cross-sections, especially multi-grooved and scalloped-oval cross-sections that provide fabrics having outstanding comfort qualities of moisture-management, dryness and comfort, as well as minimal pilling.
Patent TW-418440-B (TW)
Title: Electron beam exposure method for double exposure
Inventor: TZ SAN-DE
IPC: H01L21/027
Filed: 1999-09-18
Granted: 2001-01-11
Abstract: An electron beam exposure method for double exposure which is used to reduce the over exposure while using the electron beam for double exposure on a photoresist layer to form a pattern. The method comprises: dividing the photoresist layer into a plurality of blocks and obtaining a pattern density for each block that each pattern density is associated with the ratio of the occupied area of the pattern in each block to the area of the block; deciding the exposure dose of each block and conducting exposure on the photoresist layer in which the deciding method of the exposure dose is: defining each block as a small pattern block, a normal pattern block or a large pattern block based on the pattern density of each block wherein the pattern density of the normal pattern block is larger than that of the small pattern density; in the normal pattern block, giving the smaller exposure dose to the blocks with larger pattern density and making the changing rate of exposure dose of the normal block larger than the changing rate of exposure dose of the small pattern block; in the large pattern block, giving the larger exposure dose to the blocks with larger pattern density.
Patent TW-525362-B (TW)
Title: Efficient system and method for forward error correction
Inventor: SCHRAMM PETER
IPC: H03M13/23
Filed: 1999-12-04
Granted: 2003-03-21
Abstract: In wireless telecommunications systems, such as wireless local area networks, a flexible, less complex, and bandwidth efficient forward error correction method can be achieved by applying a first convolutional coding scheme to the bits in a first portion of a data block and a second convolutional coding scheme to the bits in a second portion of the data block, wherein the second portion of the data block may encompass a remaining portion of the data block, excluding the first portion, or the entire data block, including the first portion. While the first coding scheme employs a first code rate, the second coding scheme employs a second code rate that is higher than the first code rate. The higher rate makes it possible to incorporate the one or more tail bits into the second portion of the data block, and therefore, avoid generating any additional symbols, such as orthogonal frequency division multiplexing symbols, to exclusively modulate the tail bits.
Patent TW-445642-B (TW)
Title: Manufacturing the reference cell of flash memory
Inventor: CHEN BING-SHIUN
IPC: H01L21/28
Filed: 1999-12-04
Granted: 2001-07-11
Abstract: A manufacturing the reference cell of flash memory is provided. First, form the floating well in the substrate and the first dielectric layer covering the substrate. Second, form a defined floating gate upon the first dielectric layer corresponding to the floating well and then form the second dielectric layer covering the substrate. Define the second dielectric layer to make a contact and expose a part of floating gate and then proceed the heavy ion implantation process to implant ions into the floating gate. Third, form the third dielectric layer to cover the substrate and fill in the contact. The floating well is used to isolate the floating gate and the isolation layer of the substrate. It can effectively prevent the possibility of contact over-etching and/or floating gate mis-alignment issues from the following processes. The doping concentration of the floating gate is increased by the heavy ion implantation and the resistance of the contact is reduced. So the RC delay is improved and so is the device operation speed.
Patent TW-454246-B (TW)
Title: Method for fabricating a semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon
Inventor: YU ZHIYI
IPC: H01L41/39
Filed: 2000-03-28
Granted: 2001-09-11
Abstract: A method for fabricating a semiconductor structure comprises the steps of providing a silicon substrate (10) having a surface (12); forming on the surface of the silicon substrate an interface (14) comprising a single atomic layer of silicon, oxygen, and a metal; and forming one or more layers of a single crystal oxide (26) on the interface. The interface comprises an atomic layer of silicon, oxygen, and a metal in the form XSiO2, where X is a metal.
Patent TW-579661-B (TW)
Title: Plasma generation device and plasma processing device
Inventor: NAKAGAMI SHINZI
IPC: H01L21/3065
Filed: 2000-04-08
Granted: 2004-03-11
Abstract: The present invention provides a plasma generation device and a plasma processing device, which comprises: a vacuum container 1 with controllable inner pressure; a gas supply mechanism 2 for supplying gas into the vacuum container 1; and, a plasma generation mechanism for emitting electromagnetic wave toward the vacuum container 1 with gas introduction to generate the plasma. The plasma generation mechanism includes: a tank-like antenna 4 for forming the tank 41of electromagnetic wave emission as a conductor; and, an AC power 5 for supplying power to the tank-like antenna 4; and, the tank-like antenna 4 can also has the shape to generate the impedance of the plasma when having low power supply frequency. Thus, the present invention can improve the plasma state without enlarging the dimension of tank-like antenna to prevent the reduction of impedance, and generate the plasma in lower frequency, so as to reduce the manufacturing cost and operation cost.
Patent TW-477879-B (TW)
Title: Bracket and spacer for mounting guide troughs
Inventor: BLASE GUNTER
IPC: H02G11/00
Filed: 2000-04-18
Granted: 2002-03-01
Abstract: The invention relates to an essentially L-shaped bracket for mounting a side section of a guide through for an energy guiding chain, having a first leg, which is essentially parallel to a floor or substructure when mounted, and a second leg, which is essentially perpendicular to the first leg and designed for fastening to the side section.
Patent TW-490641-B (TW)
Title: Disk recording medium, reproduction device and method for performing reproduction on disk recording medium
Inventor: KUTARAGI KEN
IPC: G06F21/12
Filed: 2000-04-18
Granted: 2002-06-11
Abstract: A device and method for protection of legitimate software against used software and counterfeit software in recording media. The device includes a disk is set in a main unit. A specific title code is read, and if this title code has been registered, the main unit shifts to a normal operation. If the code has not been registered, verification software is initiated, PG detection is performed, and when a PG pattern and verification data match, the code is registered in the COCT. If matching does not occur, the disk is processed as illegitimate software.
Patent TW-585887-B (TW)
Title: Method for producing moldable plastic clay
Inventor: YU CHING-KUO
IPC: C08L27/06
Filed: 2000-04-21
Granted: 2004-05-01
Abstract: A method for producing a moldable plastic clay comprises: (a) adding an excessive amount of a plasticizer into a PVC emulsified powder, heating the mixture into a fluid, and cooling the fluid to room temperature to form a viscous soft glue; (b) adding a large amount of PVC emulsified powder into the viscous soft glue, and uniformly mixing the mixture to form a viscous glue; (c) storing the viscous glue in a still state at room temperature over a long period of time so that the viscous glue and the PVC emulsified powder react with each other and gradually harden into a non-sticky and moldable plastic clay semi-product; (d) adding a siloxane raw rubber and a stabilizer into the plastic clay semi-product, followed by kneading and uniform mixing, to produce a non-sticky plastic clay product with a suitable hardness; the product can be stored for three years while maintaining good stability and softness, and is suitable for being repetitively molded; furthermore, the product, after heating, can be made into a plastic molding which is collision resistant, non-deforming and mould resistant.
Patent TW-562761-B (TW)
Title: Pop-up structure for motorcycle seat
Inventor: NIIMURA HIROYUKI
IPC: B62J1/28
Filed: 2000-09-07
Granted: 2003-11-21
Abstract: A tongue 37 is formed on a bottom plate 36 beneath a seat 14 so that it elastically deforms when pressed against a projection 35 on a storage box 12 while the seat 14 is turned down, and the seat 14 is popped up when a lock mechanism 34 is released via the resiliency of the tongue 37. The use of a thin member such as a tongue in popping up a seat can maintain a low seat height leading to an improved footing, and provide a great seat thickness ensuring an improved cushioning effect.
Patent TW-451476-B (TW)
Title: Manufacturing method of integrated circuit capacitor having self-aligned contact structure
Inventor: TZENG HUNG-HUEI
IPC: H01L27/108
Filed: 2000-10-04
Granted: 2001-08-21
Abstract: The present invention discloses a method to form capacitor, which is suitable for high density DRAM circuit. The method comprises: form a silicon dioxide layer on the integrated circuit wafer having devices. Form a contact window in the silicon dioxide layer, whose top portion is larger than the bottom portion. Then form a polysilicon layer on the sidewall and bottom portion of the contact window, form a silicon dioxide side wall layer on the polysilicon layer to leave a center hole in the contact window. Next, fill polysilicon into this center hole for forming a center cylinder, and the bottom portion of the contact window electrically contacts the polysilicon layer. Then etch the side wall layer of silicon dioxide, deposit a silicon dioxide dielectric capacitor layer on the substrate to cover the polysilicon cylinder and polysilicon layer. A polysilicon layer is then formed on the second silicon dioxide layer to form the second capacitor plate. In the first embodiment of the present invention, a semi-spherical grain (HSG) polysilicon layer is formed on the polysilicon layer to form the first capacitor plate for increasing the capacitance.
Patent TW-507275-B (TW)
Title: Wafer transfer method performed with vapor thin film growth system and wafer support member used for this method
Inventor: IWATA KATSUYUKI
IPC: H01L21/677
Filed: 2000-12-20
Granted: 2002-10-21
Abstract: There is provided a wafer transfer method, by which, when a wafer is loaded into a system, heat shock applied to the wafer can be relieved, the frequency of occurrence of crystal dislocation such as slip can be decreased, and productivity can be improved due to saving of energy and time required for heating and cooling of the system, and there is also provided a wafer support member used for this method. In this method, a step for transferring wafers so as to replace a wafer, which finishes its thin film growth process, with a following wafer, which is to be subjected to its thin film growth process, is carried out under the temperature being higher than the room temperature, while the wafer 1 is transferred integrally with a wafer support member 2 used for the thin film growth process.
Patent TW-508400-B (TW)
Title: Coating material for building finishing, panel for building finishing and method for manufacturing these materials
Inventor: SHINTOME MASAHIRO
IPC: C09D7/61
Filed: 2000-12-29
Granted: 2002-11-01
Abstract: This invention provides a coating material for building finishing and a panel for building finishing using SIRASU volcanic ash, and method for manufacturing these materials. Dry SIRASU A having a function of generating active oxygen/ free radical is used, as it is, as raw material. The dry SIRASU A in an amount of 50-60%, 30-40% binding material B, 3-10% clay C, 5-10% SIRASU balloon D, 0.08-2% adhesion reinforcing material E, 0.1-3% coloring pigment F and 1-5% thatch fiber for plastering are compounded to construct the building finishing coating material 1. Further, an adequate amount of water is added to the building finishing coating material 1, and they are kneaded. The kneaded material is applied on groundwork such as a gypsum board, a veneer board, a concrete plate, a water-proof plywood for mortar or an asbestos board, and it is subjected to surface finishing processing with various types of designs to construct the objective panel for building finishing.
Patent TW-527601-B (TW)
Title: Internal supply voltage generating circuit in a semiconductor memory device and method for controlling the same
Inventor: KOBAYASHI ISAMU
IPC: G05F3/24
Filed: 2001-01-29
Granted: 2003-04-11
Abstract: A method for controlling an internal supply voltage generating circuit reduces power consumption in an active mode. The internal supply voltage generating circuit includes a first voltage-drop regulator, which supplies a relatively large driving power to an internal circuit, and a second voltage-drop regulator, which supplies a relatively small driving power to the internal circuit. First, the second voltage-drop regulator is activated and the first voltage-drop regulator is inactivated in one of a stand-by mode and a power-down mode. Then, at least the first voltage-drop regulator is activated in an active mode, and the first voltage-drop regulator is inactivated in an active pose of the active mode. The first voltage-drop regulator is activated when the active pose is cancelled.