Patent GB-1147552-A (GB)
Title: Radio navigation receiver
IPC: G01S19/04
Filed: 1967-01-27
Abstract: 1,147,552. Radio navigation. INTERNATIONAL STANDARD ELECTRIC CORP. 27 Jan., 1967 [1 Feb., 1966] No. 4168/67. Heading H4D. The Specification describes a receiver for use in a TACAN System comprising a first digital counter 10, Fig. 1, which locks on to the received north burst signal so as to read zero when said signal is received and a second digital counter 11, which locks on to the received 15 cycle modulation envelope so as to read a maximum when said envelope is at a positive going crossover point. The count B, Fig. 2, in counter 10 linearly increases from said zero reading representing 0‹ azimuth up to a maximum, representing 360‹ azimuth at the next received north burst signal A, whence it returns to zero. The count D in counter 11 linearly decreases from said maximum, also representing 360‹ azimuth, down to zero also representing 0‹ azimuth and a return to a new maximum at the next positive going modulation crossover point. Thus if a register 13 shifts out the count in counter 10, when the count in counter 11 is zero, and/or a register 12 shifts out the Count in counter 11, when the count in counter 10 is zero, said shifted-out counts will both represent the required azimuth. Counter 10 is shown in Fig. 3, together with the circuits which phase lock it to the north burst signals. The receiver also receives the fine 135 cycle amplitude modulation and the corresponding auxiliary reference groups indicating 40, 80, 120‹ &c. The counter 10 is also phase locked to the auxiliary reference groups. Counter 10 counts the output of a pulse clock 14 through one of three gate and divider paths. The path having divider 17 feeds pulses to the counter at such a rate that it cycles at exactly 15 cycles/sec. The path having divider 15 feeds pulses at a higher rate, such that the counter cycles at quicker than 15 cycles/sec. The path having divider 19 feeds pulses at a lower rate, such that the counter cycles slower than 15 cycles/sec. A logic circuit 21 recognizes the counts of 0‹, 40‹, 80‹ ... 320‹, 360‹ in counter 21 and just prior to their occurrence sets bi-stable circuit 22. This causes gate generator 23 to generate two 2‹ gates either side of the n.40‹ point, that on line 25 and being fed to control AND gate 31 and NAND gate 33 and that on line 26 occurring after the point, and being fed to control AND gate 29 and NAND gate 32. Assuming the counter 10 to have been set approximately in phase by means of a preset input, and the count to be 0‹, the north reference pulse burst, comprising twelve pulses, will be received roughly coterminous with the two gates, and will be fed to AND gates 29 and 31. If counter 10 is counting too fast (line 2, Fig. 4), then the gates will slightly precede the twelve pulses, such that more pulses will be gated through gate 29 into counter 28 than through gate 31 into counter 30. At the finish of the two gates, NAND gates 32 and 33 become uninhibited and the counts in counters 28 and 30 are reduced to zero by pulses from clock 14. Counter 30 will reach zero earlier than counter 28, and produces a signal which sets bi-stable circuit 35. This enables gate 37 which in turn enables gate 20 and inhibits gate 18. The lower rate pulses are thus fed to the counter 10, to slow it down. Since the auxiliary reference groups comprise eleven pulses, the counts in counters 28 and 30 must always be unequal such that a switch over of the feed paths to the counter 10 always occurs at each count other than 0‹. Counter 11 and its phase locking circuits are shown in Fig. 5. These also comprise three possible feed paths between clock 38 and the counter 11. Ignoring for the moment the 135 cycle amplitude modulation, the received bearing signal, after the various reference signals have been eliminated in 59, will appear as shown at Fig. 6A. A threshold monostable circuit 45 receiving the bearing signal produces a pulse output wherever a pulse input has an amplitude above a threshold equal to the 0‹, 180‹ &c. level of the bearing signal. The output of the circuit 45 is thus as shown at Fig. 6B. A counter 60 connected to counter 11 produces positive and negative gates extending between counts of 90‹ and 270‹ (Fig. 6C). These are respectively applied to gates 48 and 49 which also receive the output of circuit 45 such that positive and negative counters 46 and 47 receive respective numbers of pulses which are only equal if counter 11 is in place with the bearing signal. Any inequality generates a gate which switches over the pulse feed path to the counter 11. When the counter 11 is phased to the 15 cycle modulation, the circuit is switched over to receive the 135 cycle amplitude modulation, Fig. 7A. The threshold of circuit 45 is now caused to follow the 15 cycle modulation in square wave fashion, Fig. 7C, such that the output of circuit 45 is as shown at Fig. 7D comprising a group of pulses for each 135 modulation cycle. Each group of pulses is distributed into the counters 46 and 47 by means of gating pulses from counter 60 occurring every 40‹ and starting at 30‹, such that, if found necessary the feed path to counter 11 can be changed every 40‹.