Patent GB-842904-A (GB)
Title: Improvements in computers
IPC: G06F7/52
Filed: 1957-02-25
Abstract: 842,904. Digital electric calculating-apparatus. ZUSE, K., [trading as ZUSE KOMM.-GES.]. Feb. 25, 1957 [Feb. 25, 1956; Feb. 29, 1956; March 7, 1956; March 23, 1956; May 20, 1956; June 23, 1956], No. 6334/57. Class 106 (1). In an electric sequence-controlled computer a memory unit stores numbers representing sets of values (field values), each set being attached to a spatial arrangement of lattice points (field), a single order of the programme controls the same operation for all lattice points of at least one whole field, and an arithmetic unit is arranged to perform, according to the programme orders, operations with corresponding field values to two fields. General; main embodiment. The computing system shown in Fig. 2 comprises a magnetic drum memory unit Sp, an arithmetic unit or accumulator Rw, multiplying unit Mr and programming unit Pg. Calculations and other operations are performed on two-dimensional arrays or " fields " of binary members. Fig. 6 shows three 5 X 5 fields I, II and III, each column of 5 numbers being recorded serially in successive sectors of a separate drum track. The operations include: doubling or halving (by shift) all the numbers in a field and other shift operations; adding, subtracting or multiplying two fields (i.e. performing such calculating operations separately on the pairs of numbers in corresponding positions in the two fields); and adding to or multiplying by a constant, each number in a field. Operations may be performed also on individual rows or columns, or individual values, in a field. A computer device Nr may be used to perform the non-field calculations. The thick lines, Fig. 2, each represent 5 parallel lines for transfer of an entire field. Circuit symbols. In the circuit diagrams the symbol of Fig. 1a indicates a drum or drum part with associated read and write heads k. Fig. 1b, left and right, indicates gates which are respectively opened and closed by signals at st. Figs. 1, c and d, indicate delay lines having delays of one and several binary digit periods, respectively. Figs. 1, e, f, g, h, indicate respectively a serial binary adder, an inverting or complementing unit, a bi-stable flip-flop circuit (" L " indicates binary " 1 ") and a pyramid selection circuit. Arithmetic unit. The unit Rw, Fig. 2, includes a drum or drum part Tr3, Fig. 4, having five tracks in which a field can be written via leads rw1 and heads K2. The field columns are read simultaneously normally by heads K4 (signal Zo) and passed via the middle gates of distributer Sv and delays Vg2 to inputs of separate adders Ad. The other inputs of the adders may simultaneously receive a field over leads rw2 from memory Sp, Fig. 2, and the adder outputs are applied to an overflow indicating device Um and via output gates St2 to leads rw3 which may be connected to the recording input leads rw1. The rows of a field may be shifted column-wise forward or backward by applying gate signals 2 - 1 or 2 + 1 which cause the field to be read by heads K3 or K5, Figs. 4 and 7, instead of K4. Similarly, the columns may be shifted by signals Sl, Sr applied to gates in Sv. Signals h, vd, respectively, cause delays Vg2 to be by-passed or add additional delays Vg1, to cause all numbers of a field to be halved or doubled. Signal n causes numbers to pass through complementers Neg before reaching the adders. Multiplication. The unit Mr, Fig. 2, includes a drum or part Tr2, Fig. 5, which receives the multiplier field over leads mr1. The multiplier digits are read out under control of counters Zw1, Zw2, operated by pulses C, S and B obtained from timing drum tracks, Fig. 3, one for every drum revolution, sector and binary digit, respectively, Zw1 is stepped on by pulse C, and Zw2 is stepped on by pulses B and reset at the beginning of each sector by a pulse S. Thus a coincidence of output is obtained for the first digit in each number during the first drum revolution of a multiplication cycle, the second digit during the second revolution and so on. For such a coincidence, signal i causes the appropriate multiplier digits to be set up on flip-flops Fl1 from which they are transferred to flip-flops Fl2 under control of pulses S, the flip-flops being cleared by associated pulses S<SP>1</SP>, <SP>1</SP>S. The outputs of Fl2 on leads mr2 control the adder input gates, Fig. 4, whereby the multiplicand numbers on leads rw2 are entered into the accumulator only at times when the operative multiplier digits are " 1 " or " L." During each drum revolution the numbers in the accumulator are shifted down or halved. Thus after a number of revolutions equal to the number of binary digits in the multiplier members, the product is registered in the accumulator, and counter Zw1 produces an output m. Other multiplying arrangements also are described (see " Modifications " below). Memory unit; selection and transfer circuits. The read heads of memory drum Tr1, Fig. 9, are connected to five selection pyramids Fw1-Fw5, as shown, whereby an entire field, selected by signal w1, may be read out via gates St1, normally opened by signal G, on to leads sp1 connected, e.g., to accumulator input leads rw1 or rw2, Fig. 2. A constant, stored in shift register or delay line Vg3, may be applied to all the leads Sp1 via gates Ke. For selecting an individual row, gate W2 is closed, and the gates St1 are controlled by sector coincidence unit Sk which compares the registration of a sector counter with a desired row number entered at W3. For column selection, gate W4 is closed, and the desired column signal is entered at W5 to select the corresponding gate St1 through pyramid Sw. Individual numbers are selected by combined action of Sk and Sw; by this selection also, an individual value obtained on lead Sp2, e.g. from computer Nr, and stored in Vg3, may be entered into any desired position in a field. Conversely, any column selected by Sw can be transferred via an element Su and lead Sp3 to a drum track Tr4 and thence to Nr. The adder output gates St2, Fig. 4, are controlled like St1, through leads rw4. Programming unit. The orders or instructions are stored on drum part TrO, Fig. 3, and are normally read out sequentially under control of counter Pz to register Ba and transferred, under control of pulse C, to control register Bc. For conditional orders, two adjacent orders are transferred in succession to registers Ba, Bb and one or the other is transferred to Bc, according to whether line q, Figs. 3 and 4, is energized, indicating an overflow. For row shift operations, sector counter Sz controls analyzer Sa to inhibit the shift signal, Z+1 or Z - 1, for the first or last row of the field. During multiplication, output bc2 switches gates, whereby the transfer to Bc of the next order is under control of signal m in place of C. Modifications. The accumulator drum Tr3, and the other storage drums also, may be increased in diameter so as to store two fields around a group of tracks. Various alternative multiplying arrangements are described, e.g. the multiplication may be performed during a single drum cycle by progressively accumulating partial products in a group of shift registers (Figs. 10 and 18, not shown); the multiplier digits of each number may be dealt with in pairs (Fig. 11, not shown); and means may be provided for multiplying negative numbers in complement form (Fig. 17, not shown). In a modified computing system, the members of a field are not arranged in a twodimensional array on the drum(s) but are stored in parallel as indicated in Fig. 12, the numbers of each of the rows Z1-Z5 being recorded sequentially; the arithmetic unit (Fig. 13, not shown), comprises a parallel binary adder and the multiplying unit, Fig. 14, comprises a pyramid whereby the tracks on drum Tr32, and thus the successive digits of each multiplier number, are selected in turn under control of drum revolution counter Zw31.