Patent SG-11201902036Y-A (SG)
Title: Pipelined high-throughput layered ldpc decoder architecture
Inventor: LONCKE VINCENT
IPC: H03M13/11
Filed: 2017-09-23
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property :::` , 1#111011110111010101111101 110 1 00111111E MIMI! I 1111011110111111 Organization International Bureau (10) International Publication Number 03 (43) International Publication Date .....•\"\"- WO 2018/084956 Al 11 May 2018 (11.05.2018) WIPO I PCT (51) International Patent Classification: (72) Inventors: LONCKE, Vincent; 5775 Morehouse Drive, H03M 13/11 (2006.01) San Diego, California 92121-1714 (US). VARATKAR, (21) International Application Number: Girish; 5775 Morehouse Drive, San Diego, California PCT/US2017/053128 92121-1714 (US). RICHARDSON, Thomas Joseph; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (22) International Filing Date: CAO, Yi; 5775 Morehouse Drive, San Diego, California 23 September 2017 (23.09.2017) 92121-1714 (US). (25) Filing Language: English (74) Agent: READ, Randol W. et al.; Patterson & Sheridan, (26) Publication Language: English L.L.P., 24 Greenway Plaza, Suite 1600, Houston, Texas 77046 (US). (30) Priority Data: (81) Designated States (unless otherwise indicated, for every 62/416,584 02 November 2016 (02.11.2016) US kind of national protection available): AE, AG, AL, AM, 15/712,845 22 September 2017 (22.09.2017) US AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, (71) Applicant: QUALCOMM INCORPORATED [US/US]; CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, ATTN: International IP Administration, 5775 Morehouse DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, Drive, San Diego, California 92121-1714 (US). HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, — (54) Title: PIPELINED HIGH-THROUGHPUT = (prior's) Bit LLR's LAYERED LDPC DECODER ARCHITECTURE Update bit LLR's — \ ‘;' • '','. • \ \:\ ;\. ••• \ Pass updated LLR's to a — Update posteriori compute stage = after 3 cycle pipeline delay = 1 bit LLR's with Ro f Update bit LLR's with R2/ = Compute a posteriori LLR's — Rn 1 1 <— v(1 O) N 1\141\1+ PCM Row 0 N 1+4\141\TUZ\ \-0 - ' ;- \-0 _0. 1 1 1 1 1 1 1 11 PCM Row 1 111111111 I ILLIM44414. PCM Row 2.PCM __LIITISEMIA4'1111111111 1111111111 Row 3 PCM Row 4 = = = — Allow a posteriori LLR computation to proceed using older bit LLR's = for the first 3 cycles until the latest bit LLR updates are avaliable = FIG. 13 1-1 _ 01 (57) : Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity ---L-, check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs solving memory consistency and conflict problems. Aspects of the present disclosure present techniques for mitigating pipeline delays, c N in for example, by relaxing the dependency between updating bit LLRs and computing check node messages, so that for a particular row, 71- the check node processing can use the latest available bit LLR's (e.g., outdated bit LLRs) rather than waiting for the latest updates (e.g., C updated bit LLRs) to occur. Memory consistency conflicts are avoided by storing the latest available bit LLRs in a LLR memory and ---- updating the bit LLRs with the difference between old and new check node messages. Furthermore, logically splitting the LLR memory W D into dual banks enables the decoder to read or write from both banks of memory at the same time, thereby increasing the read/write Il cz bandwidth. Advantageously choosing the parity check matrix row (PCM) calculation order, sorting the check node messages and the bit ei O [Continued on next page] WO 2018/084956 Al MIDEDIMOMOIDEIREEMOOMMMOIEHEROMEHOIMIE MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3)) LLR updates in memory, and/or choosing a memory bank to store the check node dependencies between rows in the PCM alleviates memory conflicts/consistency errors and reduces pipeline processing delays. messages and bit LLR updates based on, for example,