Patent EP-0125156-A1 (EP)
Inventor: MULLER BERNARD-PIERRE
IPC: G06F7/52
Filed: 1984-04-03
Abstract: 1. A multiplier of the cascade type utilizing a set of elementary operators, each elementary operator having a first Y register (101) to receive and supply a first signal of at least two bits, a second RI register (102) to receive an intermediate signal of n bits, a third X register (103) to receive a multiplicand signal of n bits and an overlap bit and to supply this multiplicand signal, D and Q decoding circuits (112 to 117) to receive a multiplying signal of three bits and to supply the high value bit of this signal, an adder (110) having a carry input and a carry output, and an S circuit (111) to supply a multiplication signal of nine bits obtained in accordance with Booth's algorithm between the multiplicand, the intermediate signal and the multiplier, characterized in that each operator comprises computing means (108) making it possible to perform partial multiplications on the groups of bits in accordance with Booth's algorithm connected with a multiplexer (109) making it possible to select the partial result necessary for effecting the full computation in accordance with the said algorithm and an adder (11) having an input and a carry output and in that in order to perform at least one multiplication using a multiplicand of 2 (n-1) bits and a multiplier of four bits, it comprises a first stage comprising a first operator (0) an a second operator (1) and a second stage comprising a third operator (2) and a fourth operator (3), in that the overlap bit and the low value bit of the multiplier signal of the first operator are at zero, that the two other bits of this multiplier signal are the two bits of low value of the multiplier, that the bit with the high value of the latter is applied to the carry input of the first operator, that the multiplier signal from the second operator is the same as that of the first one, that the X register of the first operator receives the n bits of low value of the multiplicand, that the overlap bit of the second operator copies the bit of high value received by this X register, that the X register of the second operator receives the other bits of the multiplicand of which the one with the high value is copied twice, that the intermediate signal of the first stage is equal to zero, that the register of the first operator receives the two bits of high value from the multiplier, that the carry output of the first operator is connected with the carry input of the second operator, that the D circuits of the third and the fourth operators receive the two bits of high value from the Y register of the first operator from the multiplier and from a circuit Q of the first stage of low value preceding these two bits, that the carry input of the third operator receives the bit of high value from the multiplier, that the multiplicand is directly transmitted between the outputs of the X circuits of the first and the second operators and the inputs of the X circuits of third and fourth operators, that the overlap bit of the third operator is maintained at zero and that of the fourth operator copies the bit of high value of the X register of the third operator, that the two bits of low value of the multiplication signal of the first operator are transmitted to two inputs of high value of the Y register of the fourth operator, that the other bits of this multiplication signal and the multiplication signal of the second operator are transmitted to the RI registers of the second stage with an offset to the right and a double repetition of the bit of high value, that the (m-4) outputs of high value of the Y register of the first operator and the outputs of the Y register of the second operator are connected with the inputs of the Y register of the third operator and with the (m-4) inputs of low value of the Y register of the fourth operator, and that the carry output of the third operator is connected with the carry input of the fourt operator.