Patent GB-1512058-A (GB)
Title: Control apparatus for refreshing a cathode ray tube display
IPC: G09G5/30
Filed: 1975-07-25
Abstract: 1512058 Alphanumeric display generators HEWLETT-PACKARD CO 25 July 1975 [23 Sept 1974] 31241/75 Heading H4T Cathode-ray tube control and display data is coded in 8-bit data characters and 8-bit control characters and stored in a terminal RAM 6 as a "linked list" structure. Control circuitry accesses the stored data in 16-character blocks and identifies it as representing displayed figures, video enhancement features, or programme execution path changes. The first two locations fetched (at octal addresses 37777 8  and 37776 8 ) are a link to the first 16-character block of information stored in the RAM (see Fig. 5). A data control 8, Fig. 3, accesses data characters in the RAM via an input register 43, buffers them in 80-character shift registers 12, 14 and transmits them to a circulating memory 16 and then to dot generation circuitry 18. An "interrupt set" signal 2 indicates that a new display line is to be fetched from the RAM 6, and a vertical synch pulse 4 indicates the beginning of a new frame scan. Buffers 12, 14 are loaded and rotated alternately and supply one character for every 9 dots scanned. For display rows 15 scans high, the 80-character buffers are rotated 15 times between each output of timing control 20. The data control 8 decrements an address register 22 after each character and executes the following display and control functions: LINK wherein two characters are fetched and become a next location address from which data is to be read; END OF LINE wherein the rest of a line is filled with blanks; END OF PAGE wherein the rest of a page is filled with blanks; FLAG which is used to protect data fields; DISPLAY ENHANCEMENT and INVERSE VIDEO bits; and CHARACTER in the form of a 7-bit code. After 24 lines have been fetched, the cycle repeats with register 22 again being set at 37777 8 . If the character is a display character, counter 26 is incremented and 8-bit characters are fetched until 80 display characters have accessed. The number of control characters is variable. The coding scheme is shown in Fig. 8. Data in registers 42, 44 goes into a priority encoder 46 which generates a 3-bit number 47 representing the highest bit position input which has a zero. The 3- bit number is fed into a decoder 48 having 7 outputs, one of which goes "low" whereby the nature of the character is detected. A LINK may be a 2-character control sequence (e.g. Fig. 4, not shown), interpreted by the control 8 to change the RAM address of the next character to be fetched. Thus, referring to Fig. 5, the first two locations accessed are a link to the first 16-character block of information in the RAM 6. In this first block of a line are links to the next block of that line and a link to the first block of the previous line and the next line. A processor 4 may change the structure of the display and may, e.g. delete or insert a control character. By means of a flip-flop 28, the processor turns off the control bus 30 before changing a link. The further control of bus 30 by three flip-flops from data control 8 is described in detail in the Specification. A detailed description of the control logic circuitry is also given.