Patent GB-1044739-A (GB)
Title: Electronic computer with interrupt facility
IPC: G06F9/48
Filed: 1964-11-12
Abstract: 1,044,739. Electronic digital computers. RADIO CORPORATION OF AMERICA. Nov. 12, 1964 [Dec. 11, 1963], No. 46193/64. Heading G4A. A digital computer program interrupt system has the features that the program can (1) determine the number of groups of interrupt indicators which are to be effective; (2) determine which interrupt indicators in each group are to be effective; (3) itself set an interrupt indicator to cause an interruption; (4) inhibit interruptions of one or both of two degrees of urgency; (5) cause interruption after each normal instruction for program debugging purposes. Program interrupts may be of two degrees of urgency, the interrupts of higher priority being termed " real-time " interrupts and those of lower priority being termed " general" interrupts, a general interrupt being capable of itself being interrupted only by a real-time interrupt. Computer words consist of ten 6-bit characters, an instruction word as shown in Fig. 1A in the computer memory HSM, consisting of two 4-character addresses A0-A3, B0-B3, an operation character Op and an option character N. An interrupt request causes one of 18 interrupt indicators 90, Fig. 1C, to be set, the request being normally in response to the occurrence of a particular condition in an item of the computer hardware, but indicator 6 may be set in response to a computer instruction requesting an interrupt. An interrupt signal Rr or Rg is produced according as the interrupt requested is of " real-time " or " general " urgency, provided that inhibiting signals Ir or Ig are not present (except that signal Rr can be produced even if Ig is present). The occurrence of the interrupt signal Rr or Rg causes a jump signal Jr of Jg to be produced by one of gates 52, 51, Fig. 1C, thereby causing the contents of the computer control registers 35 to be interchanged with corresponding " general " or " real-time " registers 36 or 37, thereby initiating the interrupt sub-routine. The first instruction SI of this routine causes the interrupt indicators to be scanned, the value of the option character N determining whether one, two or three 6-indicator groups of the indicators 90 is scanned. In the next cycle, the contents of the B register 35 is employed to address the memory HSM to read-out a mask character to a register D3, Fig. 1B, this character being compared at 70 with the contents of a group of interrupt indicators, which has been transferred to a register D2. If a match or matches is found, the corresponding output or outputs are applied to a priority selector 76 which allows only the highest priority output to energize a corresponding indicator identifier gate 80 whose output causes, via a coder 82, the generation of two 6-bit characters in registers C1, C2 representing two decimal digits of the indicator number, these digits being transferred to the two middle character positions in the A register in the " scratch-pad " memory 34. This cycle is repeated once or twice more if the value of the option character N in the SI instruction requires more than one group of indicators to be scanned. The contents of the A register are now employed to read from the main memory HSM the instruction of the sub-routine corresponding to the interrupt request. Programmed inhibition of interruption.-Instructions can be included in the program which can inhibit either " real-time " or " general " interruptions by setting a flip-flop 140 or 134, Fig. 1D, this inhibition continuing until a further instruction resets the flip-flop. Debugging.-A " set program test mode " instruction causes a flip-flop, Fig. 1D, to be set, thereby setting program test interrupt indicator 18 in the indicators 90, thus causing an interrupt routine after each normal instruction, the interrupt routine, e.g. comparing and pointing out the contents of an accessed memory location.