Patent GB-1391640-A (GB)
Title: Semi conductor memory device
IPC: H01L21/8247
Filed: 1972-12-14
Abstract: 1391640 Semiconductor memory devices MATSUSHITA ELECTRONICS CORP 14 Dec 1972 (17 Dec 1971 (2)] 57766/72 Heading H1K A semiconductor memory device (Fig. 4) comprises a P-type Si substrate 1 with aN-type indiffused region 2 forming a PN junction therewith. A thin SiO2 film on the remainder of the surface is covered by a film of Si3N4, and metal electrode 6 is in ohmic contact with the region 2 while an annular metal electrode 5 overlies the insulant layers. A highly doped N<+> region 10 with a stepped structure of high concentration is provided in the surface of the substrate. A reverse voltage from supply V (Fig. 5) initially biases the PN junction in reverse sense for logic 0 and then a voltage negative referred to the substrate from supply V2 is applied to electrode 5 for logic 1. Electrons in the trap level of film 4 are injected into the substrate surface by tunnel effect through film 3 to form an inversion layer 7 in the substrate surface. Removal of V2 leaves the inversion layer in situ attracted by the corresponding positive charge layer 8 in film 4 and this condition persists for the lifetime of the deep level trap in film 4. For readout, V2 is cut off and V1 is applied to electrode 6 and the level of the reverse saturation current is low for logic 0 and is increased for logic 1 due to inversion layer 7 (Fig. 6, not shown) and formation of the inversion layer 7 on write-in causes conduction between region 10 and the central indiffused region 2; while on readout application of reverse bias to the junction electrode 6 the resultant current is increased by break-down between the peripheral region 10 and the substrate 1. Erasure is produced by applying voltage V3 between electrodes 5, 11 in reverse sense to the write-in voltage. In fabrication the impurity doped substrate is masked with SiO2 on its (100) plane surface which is windowed for indiffusion of P to form a circular N-type region. After removal of the mask, an insulant film of SiO2 is vapour deposited thin enough for punch-through and a similar Si3N4 film is deposited therein by thermo-decomposition of vapourized ammonia + silane, after which the electrodes are formed by deposition and photoetching of Al. An electrode of Au-Ga is deposited on the back of the substrate and a high concentration N<+> stepped region 10 is provided in the periphery of the device by deposition through a windowed SiO2 mask, N-type Si may replace P-type Si for the substrate, when the second insulant film must have a deep acceptor level and may be of TiO2, HfO2 Ta2O3 or Al2O3 and the voltage polarities must be reversed. In a further modification (Fig. 7) the N<+> region is replaced by a P<+> region 20 with a metal electrode 21 acting as read-out electrode so that write in and erase are performed by voltage between electrode 5 and back electrode 7, and readout by voltage between electrode 21 and electrode 2 on region 2; and the inversion layer on substrate 1 produced by write-in connects the regions 20, 2 so that breakdown occurs at a low read out voltage. A N-type substrate may replace the P-type substrate with a thin SiO2 insulant layer capable of punch through, with a trap level formed therein covered with an insulant film 4 of TiO2, HfO2, Ta2O3 or Al2O3 having an acceptor level.