Patent GB-1006868-A (GB)
Title: Data processing machine
IPC: G06F7/50
Filed: 1962-08-07
Abstract: 1,006,868. Electric digital calculators. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 7, 1962 [Aug. 7, 1961], No. 30200/62. Heading G4A. In a data processing machine, data read from a store is processed and the result written back into the store after a time interval depending on the processing operation performed, control means generating writing control signals one of which is rendered effective to control such writing by operation-recognizing means responsive to signals produced by the processing unit during the performance of the processing operation. The Specification describes apparatus for performing elementary operations called count and exist. A data word comprises 72 bits grouped in 9 bytes, each of 8 bits, 8 data bytes and a parity byte. Each bit of the latter is an odd parity bit to an associated byte. A count operation (CT) adds a binary one into a specified data bit position. If the operation is a so-called CT-8 carry out of the byte including this position is neglected, whereas if the operation is CT-16 or CT-24 a carry if present is added into the next higher order byte and in CT-24 any carry out of this byte is added into the second byte above the original byte. An exist operation ors a one bit with the contents of a specified bit position. At the end of an operation parity is changed unless there issues a signal derived from the contents of the byte being operated on and the bit address. General description of operation.-Besides the operation code and a memory address an instruction contains a six bit plus parity bit address. The first three bits define one of the eight bit positions of a byte and the next three define one of the eight bytes of the data word at the memory address. The bit and byte addresses are held in address register 172 (Fig. 1c) and are decoded in circuits 188, 202 to a marking on one out of eight lines. The decoded byte address is checked by ensuring, e.g. that one of the odd numbered lines are marked if there is a one bit in the lowest order position of the byte address (Fig. 11, not shown). The bit address on line 150 provides the addend in a count operation, for the marking of one out of eight lines generates a suitably ordered one bit for addition into the selected byte. At the beginning of the operation the specified data word is read into register 100 (Fig. 1b) and its parity byte into register 102, both of which comprise bi-stable circuits. The selected byte is gated together with the bit address into a first sum generator 130 (Fig. 1a) which produces a sum and carry bit for each order of the byte, and into a count parity predict circuit 136 which produces an indication of whether the parity of the byte will be changed by the addition. The original byte and the carries generated by the addition are combined in generator 132 to determine whether there will be a carry from the highest order of the byteoverflow. If the operation is CT-8 only one byte is operated on and the signal overflow of count issues from circuit 140. The original byte together with the sums and carries from the first sum generator are combined in final sum generator 134 to produce the final sum which is sent back to the data register and to a check circuit where the parity of the sum plus new parity bit is checked as odd. If the operation is CT-16 and an overflow exists the bit address is changed to 0 so that the carry is entered into the lowest order of the next byte and the byte address is increased by one. This is done in circuits 180, 184 (Fig. 1c), without changing the contents of the address register 172. The next order byte is then processed as described above, and, if the operation is CT-24 and overflow exists, a third byte is selected and processed. In an exist operation the byte selected is treated as though there were a zero-valued addend until it reaches the final sum generator when it is orred with the bit address. Adding circuits.-For each order of the first sum generator (Fig. 22) there is an exclusive-or circuit such as 1071 to produce a sum digit, and an and circuit such as 1080 to produce a carry digit. The overflow generator (Fig. 23, not shown) ands each carry with all higher order data digits to determine whether there is a carry out of the byte. The final sum generator is shown in Fig. 24 and has as inputs the original data bits and the sum and carry bits from the first sum generator. Each digit as it is computed is entered in a latch of the set 1104 to 1111. As an example the input to latch 1108, which registers the fifth order digit of the final sum, will be considered. Or circuit 1146 produces an output if there is a carry in the fourth order of the first sum generator or if one is implied by the nature of the lower order data bits and carries. The output of the or circuit is applied together with the fifth order sum digit to exclusive-or circuit 1138. If these inputs differ the final sum digit is a one bit and is registered on latch 1108 at an appropriate time. The output of or circuit 1146 is also applied to the circuits controlling the higher order latches. In an exist operation the bit address is gated through and circuits 1180 to 1187, and through or circuits 1170 to 1177 with the output of the latches 1104 to 1111, which would be registering the original byte of data. Parity computation.-Figs. 25a to 25c show the three possible situations: adding a one into an order containing a one bit with the parity remaining the same or changing, and adding a one bit into an order containing a zero, when the parity always changes. The circuit of Fig. 25 recognizes the situation exemplified by Fig. 25a, in which parity does not change, and issues a signal inhibiting a " builtin " parity change operation. The rule is that if there is a continuous string of one bits of even length extending from the order above that operated on the parity will not change, provided that the order being operated on contains a one bit. For the lowest order this is written: which can be transformed into The expressions in parenthesis are the inputs to and circuit 1200. In the exist operation the circuit is simpler: each bit of the bit address is anded with its corresponding data bit. If any of the and circuits give an output, parity is not changed.