Patent EP-0211613-A3 (EP)
IPC: G06F15/78
Filed: 1986-07-30
Abstract: An improved memory organization for a pipelined scien­
tific vector processor is disclosed, It provides an efficient 
vector file organization with a data transfer capability which is 
adequate to support multiple program execution pipelines 
with the processor. It enables the multiple pipelines to simul­
taneously access various blocks of the overall vector file.  
     The invention provides a novel manner of segmenting 
the file storage and of addressing the various elements of the 
segments. It also provides a unique method of granting and 
maintaining memory access to the vector files.  
     The vector files themselves are programmable registers. 
There are sixteen (16) files of vector registers and each file has 
space for sixty-four 36-bit words. Each file may be formatted 
as single or double word elements.  
     A preferred embodiment of the scientific processor using 
this vector file organization is shown. It has six independent 
instruction execution pipelines. They all access the vector files 
for either source (read) operands or destination (write) oper­
ands or both. Any combination of execution pipes can be 
active at any given time. They are initiated into execution in a 
serial manner depending on the instructions encountered in a 
program.  
     The Vector Files are organized into eight independent 
blocks. Each block has a random access memory (RAM), an 
address register and a write data register. Each of the blocks 
can do a read or write operation each clock cycle. Each block 
holds certain pairs of words of each of the 16 files. The first 
block has words 0, 1, 16, 17, 32, 33, 48 and 49. The next block 
has the succeeding word pairs (each eighth pair). The pattern 
continues for the remaining 6 blocks. Only one copy of the 
vector files is usually shown, however, two are actually pro­
vided. These copies, while termed the primary and secondary 
vector files, are equal in capability. The purpose of the two 
copies is to allow reading pairs of operands, as required by 
most instructions. For example, during a vector multiply in­
struction (executed by multiply pipeline) the multiplicand is 
read from the primary copy and the multiplier is read from the 
secondary copy. The read registers are associated with a 
pipeline rather than with a vector file block. Writing of the 
corresponding multiply product element into both copies 
occurs nine clock cycles later.  
     A time slot management mechanism included in the Vec­
tor File organization consists of 8 registers and performs the 
following functions. It allocates and reserves access to the 
Vector Files by the execution pipe for each individual instruc­
tion execution. It maintains the reservation and its purpose 
(read or write) until the instruction is completed. It forms or 
selects Vector File read or write address for both primary and 
secondary copies. The address consists of the appropriate 
4-bit file number plus certain other fields. Once formed, an 
address is used to reference all 8 blocks, in what is termed a 
pass. It selectively initiates one of 5 counters used to select 
read data from the 8 RAMS. Finally, it selectively initiates one 
of 6 counters used to route write data to 1 of the 8 write data 
registers.  
     The 8 time slot registers (0-7) are connected together in a 
serial loop. All the reservation data is advanced for register to 
register each clock cycle. As each reservation is in register 0 it 
is used to form or select a Vector File address. Typically a 
reservation is maintained for 4 passes or 32 clock cycles and is 
released by being cleared upon completion of the instruction.