Patent GB-1239585-A (GB)
IPC: H03M1/18
Filed: 1968-11-13
Abstract: 1,239,585. Selective signalling. TEXAS INSTRUMENTS Inc. 13 Nov., 1968 [29 Dec., 1967], No. 53866/68. Heading G4H. [Also in Divisions H3 and H4] Signals from a plurality of seismic detectors 12, Fig. 1, are each amplified 22a, filtered 22b, and chopped 23 and passed via a digitally controlled variable gain amplifier to a multiplexer 14 which samples the processed signals sequentially. Each sample is then digitized 15 and recorded on tape 16 alongside the gain setting of the corresponding amplifier 24 and if the level of any sample falls below outside a predetermined range the gain of the associated amplifier 24 is increased or decreased by one step (= 6db), in such a direction as to bring the next sample from that channel within the range. Thus the gain setting of any amplifier 24 is a coarse measure on a logarithmic scale of the amplitude of the signal in that channel, and the output of the digitizer is a fine measure. The detailed description is concerned with the construction of the choppers 23, and the variable gain amplifiers 24. Chopper.-Signals 22, Fig. 2, to be chopped, are passed 43 direct to a gate 44, and inverted 30, 38 to a gate 39, these gates being oppositely switched 51, 52 under the control of clock pulses 26a, of e.g. 1 kc./s. The signals 22 applied to gates 39 and 44 also pass via unity gain emitter followers 60, 61 and 62, 63 respectively, to the control electrodes of these gates. The purpose of these connections is not stated. The outputs from gates 39 and 44 are commoned and passed via a spike removing filter 41 to an output 42. Variable gain amplifier.-A four-stage amplifier, Fig. 3, has its gain, which can vary from 1 to 32,768, set by a four-bit word in a register 175 ... 178, the sixteen different gains that are available for use being spaced by steps each of which is double the preceding step (i.e. approximately 6db steps). Stage I of the amplifier includes a potential divider 112 to which the input signal is applied, and which, if the input signal is V, applies V, 1/ 4 V, <SP>1</SP>/ 16 V and 1/ 64 V to FET gates 113, 114, 115 and 116 respectively. One of these gates is opened by the four-bit word 175... 178 to pass the corresponding signal to an amplifier 118 of fixed gain sixteen. Thus the overall result is that the effective gain of stage I can be 16 or 4 or 1 or 1/ 4 . Stages II and III are similar, except that the bottom tap on the potential dividers (producing 1/ 64 V) is omitted, stage IV can only produce a gain of 2 or 1. Stage I of the amplifier is shown in detail in Fig. 4. A transistor 211 is normally conducting thereby opening gate 113 letting the analogue input signal straight through to an integrated amplifier 118. The amplifier output is limited by a pair of transistors 136 which shunt a feed-back resistor 132 if the output exceeds reference voltages 234, 234. Thus normally the analogue input passes direct 110, 113, 230 to the amplifier 118 and a gain of sixteen results. However, resultant gains of 4, 1 and 1/ 4  are obtainable by opening one of gates 126, 127, 128 respectively. Thus, if for example the control word requires a gain of 1 then gate 127 is opened. This causes a transistor 213 to conduit, thereby cutting off normally conductive transistor 211 and resulting in the opening of gate 115 in place of gate 113.