Patent GB-1192562-A (GB)
Title: Electronically Controlled Display Using Continuous Scanning
IPC: G09G5/22
Filed: 1967-06-01
Abstract: 1,192,562. Cathode-ray tube displays. SOC. NOUVELLE D'ELECTRONIQUE ET DE LA RADIO-INDUSTRIE. 1 June, 1967 [8 June, 1966], No. 25381/67. Heading H4T. In an arrangement for displaying characters (e.g. Alpha Numeric characters, symbols, patterns, &c.) by selective ON-OFF switching of the beam of a cathode-ray tube during a television-type line raster scan, coded signals specifying the characters together with signals defining the X, Y co-ordinate positions of each character are stored in corresponding positions in a first memory means and then converted into signals specifying the actual ON-OFF beam condition required to display a character whilst the beam is scanning the particular co-ordinate position defined by the X, Y signals. The display provides for 512 characters in 16 horizontal lines each of 32 characters (Fig. 1), the latter being formed, as shown in Fig. 3 in respect of the characters F and L by ON-OFF switching of the tube beam during a (interlaced) line raster scan. In Fig. 3 the ON-OFF beam switching voltage V appertains to lines L 3 -L 5  of character F and to lines L 3 - L 13  of character L. Fig. 2, shows the general arrangement in which signals from a key board, a teleprinter receiver or a computer &c., and comprising character specifying coded signals K together with signals defining the co-ordinates of the character spaces X, Y are fed via a control device 2 to a first memory means 3 in which the K signals are stored in the positions defined by the X, Y signals. The K signals (each comprising a six-bit code signal) are then transferred sequentially to a second memory means 4 including a decoding device and an 18 x 32 array of two-state elements (e.g. magnetic cores or AND gates) in which they are set up as a pattern of ON-OFF conditions corresponding to the ON-OFF states of the beam in a virtual 18 x 32 matrix which the character specified by a particular K signal requires for its display. The array in memory means 4 is then "scanned" by a "line distributer" 5 supplying pulses L 5  (Fig. 3) in synchronism with the successive lines L 1 -L 18  of each character space and by a "time-distributor" 6 supplying high frequency clock pulses L 6  (4 mc/s.) in synchronism with successive line scan increments X0-X31 in each character space. In operation the transfer of the K signals to means 4 is arranged to occur when the beam of the display tube CRT (Fig. 2) is scanning the particular character space defined by the X, Y signals appertaining to a particular character (K) signal so that the pulses "released" by memory means 4, when supplied via OR gate 90 and a bi-stable device 92 (re-set by a NOR circuit 94) to the beam intensity control electrode CE cause display of the character. The latter are therefore composed of closely spaced continuous parallel line segments of incrementally controlled length and instead of displaying them as bright segments on a dark background switch means may be provided to allow the "re-set" output instead of the "set" output as shown of the bi-stable device 92 to be connected to the control electrode CE so that the characters are displayed as dark elements on a white background. Details of the arrangement of Fig. 2 are described with reference to Fig. 4 (not shown). The K signals stored in memory 3 are continuously re-recorded unless a signal from the input means 1 indicates that a new character is to be stored and in order to allow for the time lag in the decoding operation memory 3 may be so arranged that when a K signal in a particular X, Y location is to be passed to the decoder in memory means 4 that particular location is enabled for recording input information and the next location enabled for read-out. The read-write cycle of memory 3 should not exceed the time T (Fig. 3) required to scan a horizontal line segment of a character space and to ensure that the finite operational time of memory 3, when, e.g., it utilizes magnetic cores, allows of this, the number of cores may be made twice as great as the number of digits for K code signal so that two consecutive K codes can be recorded in parallel. These are then read-out simultaneously when the double storage location is specified by the X, Y signals and on the occurrence of the XY signals appertaining to the next storage location (i.e. X + 1; Y), the read-write cycle being not yet completed, no new read-write step is initiated. Read-write of two consecutive character codes thus requires a total time period of less than twice the time T and the next cycle is initiated when the location X + 2; Y is specified. One form which the memory device 4 may take utilizing ferrite cores is described with reference to Fig. 5 (not shown) and two further forms utilizing three-input AND gates and one of which is modified to accept character defining signal inputs directly from a computer are described with reference to Figs. 6 and 7 (not shown) respectively. Two or more simultaneous displays of different information or a display in colour may be provided (Fig. 8, not shown) and provision is made for varying the height, width and spacing of the characters (Figs. 9 and 10, not shown).