Patent GB-991734-A (GB)
Title: Improvements in digital calculating devices
IPC: G06F7/57
Filed: 1962-12-28
Abstract: 991,734. Parallel adders. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 28, 1962 [Dec. 28, 1961], No. 48744/62. Heading G4A. A parallel adder can operate on binary operands of varying lengths and means are provided for sorting a carry out of the highest order operated on. The operands can be a maximum length of 8 binary digits and the two operands are of the same length. Fig. 2 shows the carry storage mechanism. In the case of binary digits the oper- and length (byte length) is specified in an instruction word. This marks a select line, e.g. select 5 line 201 if the byte length is 5 bits. A carry from the fifth order of the adder marks line 202, and circuit 203 is energized and latch 208 is set. The adder can also operate on single binary-coded (1248) decimal digits and in this case the carry stored is a decimal carry. The and gates 214, 216, 217 detect those bit configurations giving a decimal number greater than 9. The Adder, as shown in Figs. 10 and 11, is of the carry lookahead type. If a particular order can transmit a carry this is done as soon as the operands are known. The operands of each order are applied to or circuits. The output of the or circuits are T signals indicating that an in-carry would generate an out-carry. These T signals are combined in and circuits with the carries to speed up the computation of sum digits. Thus and circuits A1 to A3 have as inputs T1 to T3 signals and the in-carry CO. The incarry can be applied to the 4th order after operation of only one level of or circuits and one and circuit. To economize on circuitry the adder is split into three 4-order groups, each group (Fig. 11) being connected by look-ahead circuitry in the same way as the orders. Subtraction is by complement addition. The instruction word for an addition operation includes a memory or similar address of the first bit of the operand, together with the byte length. Operands can overlap memory location boundaries and so registers are of two-word capacity. Addition always involves accumulation i.e. one of the operands is already stored in the arithmetic unit. The other operand is contained in the two words which are sent to an operand register (Fig. 1, not shown). The two words are transferred two 8-bit bytes at a time to the adder through a pair of matrices which if necessary shift the operand so that it occupies one of the bytes without overlapping into the other. Only this one byte is operated on, the other being caused to by-pass the adder. As an example: words are of 64 bits; assume that memory address A is given; a bit address of 59 and byte length of 7 bits. The words in addresses A and A + 1 are transferred to operand register. The first matrix referred to above selects from the operand register the two bytes in which the operand is embedded; bits 55 to 63 of word A and bits 0 to 7 of word A + 1. The second matrix then shifts the operand so that it occupies lines 9 to 15 of sixteen output lines 0 to 15. The data on lines 0 to 8 by-passes the adder and that on lines 0 to 15 applied to the adder. As explained above a carry out of the seventh order would be stored in latch 208.