Patent GB-799793-A (GB)
Title: Improvements in or relating to computing apparatus
Inventor: RICE JOSEPH
IPC: G06F15/78
Filed: 1955-11-04
Abstract: 799,793. Digital electric calculating-apparatus. STANDARD TELEPHONES & CABLES, Ltd. Nov. 4, 1955, No. 31595/55. Class 106 (1). In a digital electric computer having an accumulator including one-word dynamic stores the contents of which are circulated synchronously, intelligence may be transferred between the stores one digit at a time and may be directly transferred between the accumulator and general-purpose stores, the stores being formed by portions of tracks on a magnetic drum. General. The computer described comprises a magnet drum 1, Fig. 2, having 32 generalpurpose storage tracks each holding 16 words of 28 binary digits plus a 4-digit gap. Combined read/write heads one for each track are connected to store-selecting circuits 8 which may comprise transistor switching circuits as described in Specification 780,831. Further tracks ECT, WCT and CAT have permanently recorded thereon clock pulses (one for each digit period), word pulses (in the first digit position of each word) and word address numbers respectively. The latter are applied to circuits 8 for comparison with the word number portion of a required address, the track number portion being set up in register TS. The clock and word pulses are applied to a P-pulse generator (in unit 11) comprising a counting chain of bi-stable devices each including a trigger pair of crossconnected pentodes and output cathode followers, whereby outputs P1-P32 corresponding to each digit period are produced, and also the complementary outputs NP1-NP32. Numbers normally comprise 27 significant digits in positions P1-P27 followed by a sign digit (" 1 " for " - ", 0 for " + ") in position P28. Duplicate sign digits in P28, P29 are employed in some instances. Instruction words comprise a function portion, a portion containing a first address in the magnetic drum store, or a shift number for a right or left shift instruction, and a portion containing the address of the next instruction. One-word dynamic stores or carriers A-F, Fig. 1, each comprise a length of track on the drum and a recirculation path including one or more delay circuits. The accumulator comprises carriers A and B which store the most and least significant portion respectively of a doublelength number. Carrier A includes an adder/subtractor as described in Specification 783,229. During multiplication, carriers B, C and D respectively store the multiplier, multiplicand and most significant portion of a previous product. Carrier E is used to count the number of operations during a multiplication or accumulator shift operation, and F stores the current instruction. The carriers have input and output connections as shown, information being transferred to and from the general-purpose stores on 1 via input and output fuses 10 and 9. The sequence of operations is controlled by a " micro programme " circuit in 11 which comprises a diode matrix whereby a " micro-order " in a static register (PR, not shown) selects one or more gate-controlling W-waveforms (such as W16, Fig. 6) according to the function to be performed. Two further static registers (NR, FR, not shown) hold respectively the next micro-order and the function digits in the current instruction. NR may be set from FR or from additional circuitry where a function calls for a sequence of micro-orders. The input is obtained from paper tape in which decimal digits are recorded in binary-coded form by rows of holes. As the digits are read, they are converted into serial form, and the conversion to a binary number is effected by successive accumulations and multiplications by 10. A negative number is complemented as it is entered. The output arrangements are similar, binary numbers being converted to decimal form and punched on a tape which can subsequently be used to feed the input reader. A C.R.T. display unit is provided. Dynamic stores or carriers. Figs. 6 and 7 show the recirculation circuit between the read and write heads of the B carrier. A bi-stable device BS in the read circuit provides outputs BS0, BS1 corresponding to " 0 " and " 1 " respectively. These outputs normally produce a corresponding setting of bi-stable device BR via gates 2G1, 2G2 controlled by clock pulses TW, in such manner that outputs BR0, BR1 correspond to BS0, BS1 delayed by one digit period. The normal recirculation path continues via coincidence gates 2G7-2G8, 2G11- 12, buffer-circuits BPF0, BPF1, and gates 2G13-2G14 and 3G15-2G16 to the writing circuits. For right shift, waveform W2 opens gates 2G5-2G6 whereby the delay BR is bypassed, and NW2 closes gates 2G7-2G8; during P27, 2G5-2G6 are closed and the B carrier receives the least significant digit from the A carrier via 2G17-2G18. For left shift, W14 opens gates 2G9-2G10 whereby an additional one-digit delay including bi-stable device B2 is inserted in the recirculation path, 2G10 being, however, closed during P1 and " 0 " being inserted via gate 2G21; the most significant digit, at P26 in outputs BS0-BS1, is set up on bi-stable device LT for transfer to the A carrier via gates similar to 2G17-2G18. For entry of information from the A carrier, W16 opens gates 2G19, 2G20. Since the B carrier holds only the less significant half of an accumulator number, " 0 " is written in the sign digit position by applying P28 to 2G15. The B carrier is cleared by waveform W7. The A carrier is similar to B but includes also, as well as the adder/subtractor, a sign duplication circuit. The other carriers are simpler, the C carrier, for example, having no shifting facilities, and the E carrier having facilities for right shift only. Right and left shift instructions. A " 1 " is placed in such a position, in the first address portion of the instruction, that a number of right shifts in carrier E corresponding to the required number of shifts, will bring it to position P13. When a " 1 " is detected in this position in E, the shifting is stopped. Each right or left shift of a double length number in the accumulator takes place in the manner indicated above. Addition and subtraction. Such an instruction causes the number at the first address in the store to be added to or subtracted from the number in carrier A. Multiplication. Instructions V and N cause the product of the multiplicand in C and the multiplier in the store to be added and subtracted into the accumulator respectively. The sequence of operations is indicated in the block diagram of Fig. 10, each block corresponding to a micro-order (MO) whose number is indicated in the top left-hand corner. During the first micro-order MO31 of V, the multiplier is added into A, the previous contents of' A being passed to D. Instruction N differs only in that during its first micro-order MO22, the multiplier is entered subtractively into A. During the second micro-order MO55, the contents of A and B are interchanged, " 1 " is entered in position P28 in carrier E and the multiplicand is entered in C. MO52 or MO54 is then selected according to whether the least significant B-digit is " 1 " or " 0." During each of these orders the contents of A, B and of E are right-shifted, and during MO52 only, the multiplicand is added into A. This process is repeated, and the product is thus built up in the accumulator, until the " 1 " in E has been shifted to the least significant position. This " 1 " is read out at the same time as the sign digit of the multiplier in B. To correct for a negative multiplier, the negative sign (B = 1) selects MO50 during which the multiplicand is subtracted without shift. During