Patent GB-1176927-A (GB)
Title: Input/Output Control System for Electronic Computer
IPC: G06F9/48
Filed: 1967-02-02
Abstract: 1,176,927. Data processing. BURROUGHS CORP. 2 Feb., 1967 [14 Feb., 1966], No. 5044/67. Heading G4A. A computer I/O control unit has a register for addressing memory and can change the word length of information passing through. General.-Communications between one or more central processors, memory modules and I/O terminal devices are via and under the control of an I/O control module which includes one or more unbuffered I/O channels, may include one or more buffered I/O channels, and includes interrupt means. The interrupt means include an interrupt register storing interrupt requests (set by the leading edges of interrupt request signals), and an interrupt mask register set by a central processor under programme control. Gates provide a fixed memory address appropriate to the highest priority unmasked interrupt request to enter the appropriate interrupt routine, during the course of which the central processor accesses the interrupt register. Alternatively the address used may be the sum of that provided by the gates and the contents of a programme-settable interrupt base address register. The accessing of the interrupt register by the central processor mentioned is followed by clearing of the interrupt register and further interrupts are inhibited until this has been done, to prevent initiation of a new interrupt while the present interrupt is being serviced. A terminal device may cause a malfunction interrupt, and other interrupts are mentioned under "data transfer", below. Miscellaneous.-The I/O control module permits manual switches to cause performance of single instructions, stop or start on manuallyspecified addresses, and recycling of the programme between selected addresses, for programme and hardware diagnostics and debugging. Clock pulses drive a 2-bit Grey-code counter the states of which are decoded to specify four timing phases. Data transfer can occur in either direction between an I/O terminal device and a selected arithmetic register in a central processor or a memory module (via the processor), via an unbuffered channel as follows. A "device descriptor" from a central processor is stored in an "unbuffered channel register" in the I/O control module (unless it is "busy" in which case the central processor is notified) and sent to the terminal devices together with a strobe signal and preceded by a release signal. "Busy" and "I/O active" flip-flops in the I/O control module are also set. The descriptor includes a device number which the appropriate device recognizes and responds to by sending its device number back with a "received" signal. On receiving the "received" signal, or 16 Á sees. (counted) after sending the descriptor, whichever occurs first, the I/O control module compares the device number in its stored descriptor with the contents of the bus from the devices. If unequal, a release signal is sent to the devices, the "busy" and "I/O active" flip-flops are reset, and an interrupt is caused. If equal, the "busy" flip-flop is reset. The central processor sends a "control descriptor" to the I/O control module. If the "busy" flip-flop is set the processor is notified. If it is not set and the "I/O active" flip-flop is reset, a byte-size indication in the descriptor is stored in the I/O control module. On the other hand if the "busy" flip-flop is not set and the "I/O active" flip-flop is set, the byte-size indication is stored as before, and the descriptor is stored in the "unbuffered channel register" and sent to the devices with a strobe signal, the selected device storing the descriptor and sending a "received" signal back. When the selected device is ready to accept data it sends a "data transfer request" signal to the I/O control module. The module stores a data word from the processor in its "unbuffered channel register" (unless busy), and sets the "busy" flip-flop. Successive bytes of the word, selected by the byte-size indication, are sent to the device with "data strobe" signals, the device sending a "received" signal back after receiving each byte. An input device sends bytes to the I/O control module in a similar way in response to "data strobe" signals from the module produced by a "data transfer request" from the device, each byte being accompanied by a "received" signal. When a word has been built up in the "unbuffered channel register" under control of the byte-size indication, an "input data available" flip-flop is set to cause the programme to execute an instruction to accept the word, the flip-flop then being reset. A device may cause an immediate access (high priority) interrupt. A bootstrap arrangement is also described, using some of the above signals, to load programmes into memory from a paper tape reader via the unbuffered channel, the first word from the reader's controller being a memory address. Subsequent words are stored in the memory starting at that address, an output descriptor being generated by the I/O control module following storing of each word to cause the word to be returned to the reader controller for a check comparison. Inequality stops the bootstrap operation.