Patent GB-1492569-A (GB)
Title: Data processing system with move instruction
IPC: G06F9/315
Filed: 1974-12-12
Abstract: 1492569 Data processing HONEYWELL INFORMATION SYSTEMS Inc 12 Dec 1974 [13 Dec 1973] 53776/74 Heading G4A In a data processing system when a move instruction is executed to move a data field having an associated descriptor describing its characteristics from a first location to a second location, the second location also having a data descriptor describing characteristics which the data field should have, the data is reformatted if necessary to correspond with these characteristics before transfer. Data processing system.-The system comprises four semi-conductor memory modules (201, Fig. 2, not shown) interfaced via a sequencer (202) to an input/output controller (220) controlling, e.g. tape or disc stores and a CPU (200) the latter including a read only micro program store (210), a data management unit (206), an address control unit (207) and an ALU (212). A buffer (204) stores the most recently or most frequently used data in the form of pages, a directory (205) keeping an index of pages in the store (204), address control unit (307) including an associative store with the base addresses of the most recently used memory segments and their segment number. Move instruction.-This instruction comprises two words the first including the op code and an address syllable representing the source field operand and the second including two general register addresses and an address syllable representing the destination field operand. The address syllables reference three word data field descriptors for their associated operands, the first word including a segmented address and displacement to address the data field and the second and third words including characteristics of this data, bits 40-47 representing data type (e.g. type of coding, decimal, alpha numeric), bits 48-55 representing a key field (indicating for example dimensions, pounds, pounds per square foot) bits 56-63 and 64-79 representing the length of the field and bits 80-95 representing size. First the data types are tested to ensure that they are legal and compatible and the key fields are tested to ensure that they are identical. The descriptors are then stored in registers 406 (Fig. 4) of the local control unit, the second word of each descriptor being stored in one of the registers 408, 410. The data type of the first word is then determined: (1) If it is decimal (packed or unpacked) the length of both descriptors are tested to ensure that they are less than 32 digits. The source data is then fetched and checked to ensure that it contains no binary numbers greater than 9. The source operand data type is then compared with the destination operand data type and if they are different the first operand is converted to the form required by the destination data field. The lengths are next examined and the source data is truncated or extended left with zeros in dependence on whether it is longer or shorter than the length required by the destination data field, a control store being set to two if non zero digits are lost by truncating and to zero otherwise. (2) If it is alpha numeric the length fields are compared and if the destination field is larger than the source field the number of zeros to be added is held in the register Y, the smaller of the two lengths being held in the register N. Temporary locations for the source of destination data are specified and the source data is transferred from one temporary location to the other, one byte at a time with the value of the N register being decremented at each byte, this process being repeated until N=0. The contents of the Y register are then examined and if they are zero the control stored is set to zero and the operation terminates. Otherwise blank bytes are inserted and the Y register is decremented until it is zero. (3) If it is neither decimal nor alpha numeric and if a translation table is available (for example a PROM chip) the length fields are entered in registers N1, N2 and the addresses of the data in working registers are entered in registers S1, S2. The first byte of the source data is then fetched using address S1 and translated using the translation table with the result being stored in S2. The lengths N1, N2 are decremented and this process is repeated until the length N2 is zero, blanks being inserted if the length N1 becomes zero first. When N2 is zero the control store is set to zero.