Patent GB-916629-A (GB)
Title: Improvements relating to television pattern generators
Inventor: FURBY DENNIS WILLIAM
IPC: H04N17/00
Filed: 1958-11-03
Abstract: 916,629. Television. ASSOCIATED ELECTRICAL INDUSTRIES Ltd. Oct. 29, 1959 [Nov. 3, 1958], No. 35228/58. Class 40 (3). In a pattern generator for a television system utilizing interlaced scanning with a non-integral number of lines per frame the test signals, which consist of pulses having a multiple relationship with the frame synchronizing pulses and which produce a " bar " pattern, are arranged to occur in synchronous relationship with a line synchronizing pulse so that the production of " half-bars " due to the non-integral number of lines per frame is prevented. The invention, which is applicable to any system utilizing interlaced scanning with a non- integral number of lines per frame, is described in connection with a system employing 202¢ lines per frame. Fig. 1 shows one embodiment in which the test signal (f, Fig. 3) comprises the output of a first bi-stable circuit 21, the two states of which are assumed in response to the positively-going edges of signals derived by differentiating the outputs (d and e, Fig. 3) of two further bi-stable circuits 6, 13, the latter being switched from one state to the other by the positively going edges (circuit 6) and the negatively-going edges (circuit 13) of signals derived by differentiating a pulse train (c, Fig. 3), (derived via divider 4 from a master oscillator 1 operating at twice line frequency and determining the repetition rate of the test signal f, Fig. 3), and returned to the first states by the positively-going edges (circuit 6) of differentiated (negatively-going) line synchronizing signals (b, Fig. 3) and by the negatively-going edges (circuit 13) of differentiated (positively-going) line synchronizing signals from phase inverter 17. With this arrangement the leading and trailing edges of the test signal (f, Fig. 3) always coincide with the trailing edges of the line synchronizing signals so that, when it is employed to modulate a picture tube, the " bar "  pattern consists of complete lines. In a second embodiment (Fig. 5) pulses a (Fig. 7, not shown) of twice line frequency are fed to a ¸15 counter 30 comprising a binary scale 13 producing two antiphase output waveforms b, c (Fig. 7, not shown), which are differentiated and the positively-going portions applied together, as one input to a bi-stable circuit 33 having differentiated and rectified negatively-going line synchronizing pulses as a second input. Circuit 33 then produces an output waveform d (Fig. 7, not shown) which controls a further binary sealer 34 producing the waveform e (Fig. 7, not shown) which is the required test signal and corresponds to waveform f (Fig. 3). To prevent sealer 34 from producing a waveform in antiphase to e (Fig. 7, not shown), phaselocking pulses derived from the frame synchronizing pulses are fed to it. In a modification of the embodiment of Fig. 5, the bi-stable circuit 33 is controlled by an input derived from one point only of the binary sealer in counter 30 at which pulses at twice the repetition rate of the test signal occur, this signal, waveform # (Fig. 7, not shown), being differentiated and the positively-going portion fed to circuit 33 (Fig. 6, not shown). In a further embodiment producing a test pattern comprising a series of horizontal bars each consisting of two complete lines per picture, two bi-stable circuits 41, 41 are controlled as to one input by the positivelygoing trailing edges of line synchronizing pulses a (Fig. 10) fed thereto via rectifiers D2, D4, the second input to circuit 41 comprising the positively-going portion of a differentiated wave b (Fig. 10) derived from a ¸15 counter supplied with the line synchronizing pulses and the second input to circuit 42 comprising the output of circuit 41 and consisting of waveform c (Fig. 10). The required test signal consisting of waveform d (Fig. 10) is then derived from bi-stable circuit 42. A detailed circuit corresponding to Fig. 8, and employing transistors is described with reference to Fig. 9 (not shown).