Patent GB-1143202-A (GB)
Title: Improvements in electrical signalling systems using a common transmission path
Inventor: CLARK ADRIAN PERCY
IPC: H04J13/00
Filed: 1965-05-07
Abstract: 1,143,202. Pulse signalling. BRITISH TELECOMMUNICATIONS RESEARCH Ltd. 16 June, 1966 [7 May, 1965], No. 19421/65. Headings H4L and H4R. In a system for transmitting and receiving one of a plurality of separate digital coded information signals on a common transmission link, the transmitter comprises means for generating a carrier wave which is arranged to be modulated by the information signals and to occupy an address determined by a combination of time-division and frequency division (referred to as a frequency-time matrix) and means for changing the address occupied by the carrier signals to the next address in a predetermined sequence of addresses after each frequency-time matrix has been transmitted, and the receiver comprises means for demodulating the signals transmitted on a particular address, and means for changing such address to the next address in the predetermined sequence after each frequency-time matrix has been received. The code elements are divided into sub-elements which are represented by different frequencies (or sliding frequencies) appearing in succession within a code element time slot, each address being a unique combination of such frequencies and time intervals. A number of such frequency-time arrangements are described, Figs. 1 to 17 (not shown). When the sub-elements are represented by sliding frequencies the bandwidth is reduced if a sine-squared type of frequency variation is used. The more complex arrangements provide secrecy. Transmitter, Fig. 18.-Sub-element timing pulses A, Fig. 19, are generated at 105 and after frequency division at 107 produce element timing pulses B. An oscillator 109 generates a sine wave of frequency fc and an oscillator 110 generates a square wave of fundamental frequency fm equal to half the frequency distance between adjacent values of carrier frequency which provide a range of frequency components. The outputs of oscillators 109, 110 are supplied to a suppressed carrier amplitude modulator 112 whose output is supplied to a plurality of filters in a unit 113 which separate the various frequency components, means being provided for equalizing the amplitudes of the outputs of the filters. The element timing pulses B are supplied to a calling and countdown signal generator 114 which is controlled by a switch 115 held closed for the duration of a call. With the switch open the terminals 116, 117, 118 are at a negative potential but when the switch is closed a timing circuit causes first the calling and then the countdown signal to be fed via terminal 116 to the discrete address selector 119. The calling signal consists of alternate positive and negative transitions of a square wave which are synchronized to the element timing pulses, a positive element representing 0 and a negative representing 1. After the calling signal has been transmitted for a predetermined time the count-down signal consisting of a predetermined series of binary numbers is transmitted. While these signals are transmitted the terminal 117 is positive to open the gate 124 and terminal 118 remains at a negative potential. The address selector 119 is provided with a keyboard on which is typed the address of the called subscriber before switch 115 is closed, and it controls the transmission of the appropriate frequency for that subscriber in the respective sub-element time slots via frequency selector 121. In this arrangement the 0 and 1 bits in the calling signal for a particular subscriber occupy the same time slots in the frequency-matrix but use different frequencies. During the operation of the calling and count-down signal generator 119 the signals selected at 121 are supplied via gate 124 to the output stage 125 feeding either further stages in a radio link or a telephone line. A sequentially switched address generator 127 provides an output consisting of a sequence of D.C. voltages (waveform C) each of which represents one of the frequency bands of the frequency-time matrix and which via integrator 129 frequencymodulate an oscillator 130 having the same natural frequency as oscillator 109. When the last element in the count-down signal has been transmitted the terminal 117 goes negative and switches off gate 124. At the same time the terminal 118 goes positive, switching on gate 126 and via differentiator 128 resetting generator 127 which then operates to produce waveform C which is integrated at 129 to produce waveform D. The information signal is converted to p.c.m. at 131 (waveform E) and supplied via limiter 134 and OR gate 133 to a divide by two stage 148 which recodes the p.c.m. speech signals into a form in which digit 1 is represented by a change in level and digit 0 is represented by no change in level (waveform F). The output of stage 148 phase modulates the output of oscillator 130 at 149, the arrangement being such that when the coded information signal is positive the varying frequency carrier passes unchanged and when it is negative the carrier is phase-shifted by 180 degrees. The output of the phase modulator is passed via gate 126 and output stage 125 to the communication link. Receiver, Fig. 21.-An oscillator 209 and frequency divider 211 generate timing pulses A and B, Fig. 19, as in the transmitter. The incoming signal is supplied via bandpass filter to an amplifier 215 provided with A.G.C. controlled by a special constant frequency pilot signal from a separate transmitter. The output of the amplifier is supplied to address detectors 217, 218 comprising matched filters for each sub-element which detect digit 0 and digit 1 respectively of the address signal unique to that receiver, a voltage comparator 221 producing a fixed positive output if the voltage at the output of detector 217 is greater than and a fixed negative output if the voltage from detector 217 is less than that from detector 218. A circuit 222 samples the output of comparator 221 at each pulse B and produces voltages at terminals 223, 224 of fixed amplitude and the same polarity as the. sampled voltage, the voltage at terminal 224 being produced in response to small voltage values but the circuit feeding terminal 223 being less sensitive and being used to indicate the presence of a calling signal which is the pattern 101010 ... A calling signal detector 225 includes a single element store, an exclusive OR gate and a four stage binary counter, each new element received being compared by the gate with the element previously stored in the store. When the correct pattern is being received each new element will differ from the preceding element and the output from the gate will remain negative. Under these conditions element timing pulses are fed to the counter but when two adjacent pulses are either both 1 or both 0 the counter is reset to zero. When the counter is full indicating the reception of a correct calling signal pattern over 15 successive signal elements, the detector 225 provides a positive output. Initially the generator 209 is not synchronized to the incoming signal and a frequency shift circuit 226 comprising a multivibrator whose period is equal to about a hundred signal elements provides a positive pulse of duration equal to that of one element at the end of each cycle which advances the phase of the sub-element timing waveform (generator 209) by half the duration of a sub-element. On recognition of a calling signal the circuit 226 is disabled and the oscillator 209 is synchronized from the transmitter by the following means. The outputs of detectors 217, 218 are supplied via an adder 230 and filter 231, which is tuned to a frequency several times lower than the signal element rate, to a product modulator 232 which also receives via a- 90 degrees phase shifter 234 the output of an oscillator 233 generating a sine-wave of the frequency passed by the filter 231. The mean level of the signal from the adder 230 is proportional to the detected signal level and when the calling signal is received the signal level passed via filter 231 is very small. Thus the output from modulator 232 passed via filter 235 to an adder 236 is small and the output of the adder 236 is the sine wave from oscillator 233. The reception of a calling signal also causes detector 225 to open gate 237 so that the output of the adder 235 is applied to oscillator 209 to give a very small positive and negative frequency-deviation in the pulse repetition rate, this deviation being a small fraction of the duration of a sub-element. When the output of generator 209 is lagging in phase with respect to the received signal a positive control voltage is fed to generator 209 and when it is leading in phase a negative voltage is fed to the generator, giving a corresponding increase or decrease in frequency of the sub-element timing waveform. A countdown signal detector 240 receives the output from terminal 224 and calling signal detector 225 and provides an output signal when the correct count-down sequence of binary numbers has been received. This sets a bi-stable 241 which blocks gate 237 and opens gate 283 for the information signal, and gate 270, and may also operate a calling signal indicator (not shown). For controlling the demodulation of the information signal, the output of a sequentially switched address generator 250, operating in a similar manner to that at the transmitter, is integrated at 251 (waveform D) and supplied via adder 252 to frequency-modulate an oscillator 253. The output 243 of bi-stable 241 is differentiated at 254 to reset the generator 250, and is also supplied to a gate 260 receiving the output of amplifier 215 which is thereby passed to a pair of coherent detectors 261, 262 receiving a reference signal from oscillator 253 direct and via a - 90 degrees phase shifter 263 respectively. Detectors 261, 262 supply via filters 264, 265 respectively, outputs which are positive if the received signal over the previous signal element period was on the average more nearly