baber/WOPTO huggingface dataset:
Patent TW-410524-B (TW)
Title: LCD panel image quality examining device and LCD image sampling method
Inventor: AOKI HIROYUKI
IPC: H04N7/18
Filed: 1995-06-28
Granted: 2000-11-01
Abstract: The object of the invention is that, when CCD pixels of a CCD camera are used to examine a target LCD panel, the brightness of the target LCD panel image can be examined realistically with a fewer CCD pixel number. For this purpose, the invention comprises a CCD camera having a CCD area sensor and a drive to present a calibration pattern or test pattern on the target CCD panel. There is further provided a CCD address setting mechanism of LCD pixels wherein the brightness picked up by the CCD pixels undergo an A/D conversion in an image detector, the addresses of the LCD pixels and the corresponding CCD pixels are specified in terms of real number based on the points of the calibration pattern, and the real number value of the sampling address of the entire LCD pixels is obtained from the addresses of said points. In addition, a presampling treatment mechanism utilizes the sampling address to proceed with a neighborhood linear interpolation and conversion into an image having the size of the LCD pixel number.
Patent TW-365638-B (TW)
Title: Pressure equalization valve
Inventor: BHIDE YESHWANT K
IPC: F16K17/04
Filed: 1995-08-15
Granted: 1999-08-01
Abstract: A pressure equalization valve for alternatingly equalizing pressures between a first fluid source and at least two second fluid sources is disclosed. The pressure equalization valve includes a valve body, which includes a first port in fluid communication with the first fluid source and at least two second ports in fluid communication with the at least two second fluid sources, respectively, and a valve gate movable between a first equalizing position, wherein the valve gate allows fluid flow through one of the second ports and restrains fluid flow through another of the second ports to equalize substantially the fluid pressure between the first fluid source and one of the second fluid sources, and a second equalizing position, wherein the valve gate restrains fluid flow through the one of the second ports and allows fluid flow through the other of the second ports to equalize substantially the fluid pressure between the first fluid source and another of the second fluid sources. The valve further includes a chamber in the valve body between the first port and the second ports, wherein, as measured in planes perpendicular to the central axis of the first port, a largest cross sectional area of the chamber is at least 10 times larger than the smallest cross sectional area of the first port.
Patent TW-379294-B (TW)
Title: Interfacing direct memory access devices to a non-isa bus
Inventor: WANNER CHRISTOPHER C
IPC: G06F13/12
Filed: 1996-12-11
Granted: 2000-01-11
Abstract: A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.
Patent TW-315518-B (TW)
Title: High density electrical connectors
Inventor: HJALMAR HESSELBOM
IPC: H01L21/60
Filed: 1997-01-29
Granted: 1997-09-11
Abstract: The present invention relates to self-aligned, flexible high density and impedance adjusted electrical connectors used in microelectronic systems. This invention solves the problem of having electrical connection and alignment at the same time. One connector 200 having a first part 204 consists of two metal layer structures, a first signal path 212 and a first ground path 210, covering the V-groove 202. The connector also has a second part 208 consisting of corresponding metal layers, a second signal path 224 covering the elastic bump 206 and a second signal ground plane 226, which fits into the V-groove 202. The first and the second signal path 212, 224 are in contact with each other when the first and the second part 204, 208 are brought together. The contact is self aligned when put together. The electrical contact will remain even if displaced due to the thermal expansion.
Patent TW-444426-B (TW)
Title: Inverter arrangement
Inventor: HEIKKILAE SAMULI
IPC: H02P23/30
Filed: 1997-01-30
Granted: 2001-07-01
Abstract: The invention relates to an inverter arrangement for simultaneous control of a stator flux and a torque of an electric machine (M). In the invention, the inverter of the inverter arrangement is controlled on the basis of a stator voltage reference (Usref) defined on the basis of the error variable (Terr, Ψerr) of the torque and the stator flux; on the basis of the stator voltage reference, in turn, are defined reference values for the phase voltages (Uaref, Ubref, Ucref) of the stator voltage. The phase voltages (Ua, Ub, Uc) of the stator voltage supplied to the electric machine (M) are controlled by a feedback voltage controller (VAC) to correspond to the defined reference values (Uaref, Ubref, Ucref) of the phase voltages.
Patent TW-346678-B (TW)
Title: Method for producing memory cell array
Inventor: SUNG JAN-MYE
IPC: H01L21/8242
Filed: 1997-03-25
Granted: 1998-12-01
Abstract: A method of fabricating a memory cell array, comprising the steps of: (a) forming trenches in a semiconductor substrate; (b) depositing a first insulator layer, on the semiconductor substrate, including complete filling of the shallow trenches with the first insulator layer; (c) removal of the first insulator layer from the semiconductor substrate, resulting in insulator filled, trenches, thereby forming a plurality of insulator plugs; (d) depositing a second insulator layer on the plurality of insulator plugs, and on the semiconductor substrate; (e) forming an opening in the second insulator layer, exposing a corner of the plurality of insulator plugs, and also exposing a portion of the semiconductor substrate; (f) removal of the first insulator layer, from the exposed corner, of one of the insulator plugs, creating a notch; (g) depositing a doped first polysilicon layer on the second insulator layer, on the surface of the notch, and on the exposed portion of top surface of the semiconductor substrate; (h) depositing a conductive layer on the doped polysilicon layer, completely filling the notch; (I) removal of the conductive layer, of the doped polysilicon layer and a portion of the semiconductor substrate, leaving the conductive layer and the doped first polysilicon layer in the notch, thereby forming a conductive plug; (j) recessing of the conductive plug, to create a bit line; (k) depositing a third insulator layer on the conductive plug and the periphery thereby burying the bit line; (l) forming a gate insulator layer on the semiconductor substrate, and forming a gate on the gate insulator layer; (m) forming a lightly doped source/drain region on the semiconductor substrate adjacent to the gate, and the lightly doped source/drain region being distributed in the region between the third insulator layer and the plurality of trenches; (n) forming a spacer on the sides of the gate; (o) forming a heavily doped source/drain region on the semiconductor substrate adjacent to the spacer, such that the lightly doped source/drain region, the heavily doped source/drain region and the gate form a transfer transistor; (p) annealing to activate dopants in the lightly doped source/drain region, and in the heavily doped source/drain region, and in the doped polysilicon layer, to diffuse and contact with each other; (q) depositing a fourth insulator layer on each of the above layers; (r) forming a second opening on the fourth insulator layer, exposing the surface of the lightly doped source/drain region and the heavily doped source/drain region; (s) forming a second polysilicon layer on the periphery of the second opening, thereby filling up the second opening to form a lower electrode; (t) forming a dielectric layer on the lower electrode; and (u) depositing a third polysilicon layer on the dielectric layer thereby forming an upper electrode, such that the lower electrode and the upper electrode form a stacked capacitor structure.
Patent TW-354429-B (TW)
Title: A thin film transistor with low standby current and method for fabricating the same
Inventor: CHENG HENG-DIAN
IPC: H01L27/11
Filed: 1997-04-24
Granted: 1999-03-11
Abstract: A static random access memory comprising: a driving device, a source and a drain are formed on a silicon substrate, a driving gate dielectric layer for driving device formed on the substrate surface above the channel between the drain and source in the substrate, a second polysilicon layer of the driving device, after patterned, a gate of the driving device is formed; an interface polysilicon dielectric layer formed on the driving device; and a thin film transistor device formed on the interface polysilicon dielectric layer, the thin film transistor device includes a second polysilicon layer, after patterned, a gate of the thin film, transistor is formed, gate dielectric layer formed on the thin film transistor gate, a third polysilicon layer formed on the gate oxide layer of the thin film transistor defined the thin film transistor channel, a fourth polysilicon layer, after patterned, a drain is formed, the at one end of the channel, the drain is in contact with the third polysilicon layer, a source contacts with the third polysilicon layer, and an inner connecting wire for connecting the source to a supplying voltage; wherein the thin film transistor has a thin channel region and a thick source, drain and inner connecting wire.
Patent TW-343352-B (TW)
Title: Lid air bridge
Inventor: JOSE A DELGADO
IPC: H01L21/48
Filed: 1997-04-29
Granted: 1998-10-21
Abstract: An integrated circuit with an air bridge enclosure comprising: a substrate with an integrated circuit; a glass wafer with a cavity enclosing at least a portion of the integrated circuit; a metal conductor on the inside surface of the cavity and above the enclosed portion of the integrated circuit; and metal contacts coupling the metal conductor in the cavity to the integrated circuit, in which the metal conductor is preferably an inductor.
Patent TW-358870-B (TW)
Title: Oil cooler and method of manufacturing same
Inventor: HAASCH JAMES T
IPC: F28F9/02
Filed: 1997-04-30
Granted: 1999-05-21
Abstract: A sort of oil cooler, including an oil cooler casing and a cooling tube connector, which is for supplying coolant between the cooling tube and the oil cooler, and after the coolant enters into the cooling tube connector, the flow changing per the predetermined angle of the connector, including the modification of the connector: a first opening, disposed in the casing of the oil cooler; a piping unit, having a first end and a second end, with a coolant opening in between, for passage of coolant, with the second end being disposed for connection with cooling tube, for the supply of coolant; and a flange, disposed at the opening of the coolant and outside the first opening, for the coolant and the first opening to engage properly.
Patent TW-406346-B (TW)
Title: Method and apparatus for cooling a workpiece using an electrostatic chuck
Inventor: PARKHE VIJAY
IPC: H01L21/683
Filed: 1997-08-26
Granted: 2000-09-21
Abstract: Apparatus and a concomitant method for cooling a workpiece comprising a thermally conductive pedestal having a support surface upon which is affixed an electrostatic chuck for supporting and electrostatically retaining the workpiece. The electrostatic chuck retains a wafer in close contact with the pedestal such that heat conduction from the wafer to the pedestal is substantially improved over the prior art. Such close contact between the wafer and the chuck facilitates the use of a backside cooling technique to further promote the conduction of heat to the chuck.
Patent TW-359801-B (TW)
Title: Method and system for configuring an array of logic devices
Inventor: MASON MARTIN T
IPC: G06F17/50
Filed: 1997-10-23
Granted: 1999-06-01
Abstract: A system and method for partial reconfiguration of a gate array includes generating a netlist by placement and routing of a logic circuit. The netlist is accessed to modify logic cells configurations created by the place and route operation. Based on the modifications, a partial configuration bitstream containing only bitstrings which implement the modified logic cells is created. The partial configuration bitstream is downloaded to the gate array, thereby effectuating a partial reconfiguration of the gate array. In an alternate embodiment, a system in accordance with the present invention includes software utilities which allow an application program executing in a system containing a programmable gate array to reconfigure the array on-the-fly. The utilities include routines for modifying the design in response to external conditions detected during run-time. This approach obviates the need for providing a set of predetermined alternate designs, allowing the application to make that determination on its own.
Patent TW-417177-B (TW)
Title: Semiconductor device with silicide contact structure and method for producing the same
Inventor: GOHARA HIROMI
IPC: H01L23/52
Filed: 1997-11-05
Granted: 2001-01-01
Abstract: Within a contact hole 5 made in an insulating film 4; a diffusion layer 3a of a silicon substrate 1 and a conductive film 8, or a polycrystalline silicon layer 10 and conductive film 8, or a gate electrode 12 and conductive film 8 are connected through a titanium silicide film 6. The film 6 is formed by utilizing a silicide reaction between a titanium film 7 and silicon. And the upper and lower thicknesses of the titanium silicide film 6 are set at values prescribed by an internal stress of the conductive film 8 respectively.
Patent TW-375631-B (TW)
Title: Stabilization of polyolefins which are in permanent contact with extracting media
Inventor: KROEHNKE CHRISTOPH
IPC: C08K5/1535
Filed: 1997-11-17
Granted: 1999-12-01
Abstract: This invention relates to a kind of polyolefin compound that is permanently in contact with extracting media, which includes at least one benzofuran compound as stabilizing agent. The invention is about the application of benzofuran-2-ketone type of compound for improving the stability of polyolefins for long periods and ensuring permanent contact with extracting media containing polyolefins.
Patent TW-392110-B (TW)
Title: Method of reading data
Inventor: ANDO HARUO
IPC: G06F13/00
Filed: 1997-11-20
Granted: 2000-06-01
Abstract: The purpose of this invention is to solve the error rate degradation problem of data bus, of software reading in hard disk apparatus caused by the noise of data bus during the data transmission between the host computer and the memory apparatus. In the invention, the transmission of data to the host computer is temporarily stopped when data is read from the floppy disk. Data is read under the condition of no data bus noise that is going to cause the error rate degradation of software reading. When buffer is full or command information is well satisfied, data is then transmitted again.
Patent TW-344653-B (TW)
Title: Process for producing antibacterial and deodoring shoepads
Inventor: JANG YEANG-LIH
IPC: A43B17/14
Filed: 1997-12-16
Granted: 1998-11-11
Abstract: A process for producing an antibacterial and deodoring shoepad, which comprises the following processes: mixer processing: mixing an ethylene-vinyl acetate copolymer (EVA foam) with about 2% of a special antibiotic agent containing silicon dioxide, aluminum oxide, zinc, and silver, etc.; blending the mixture in a mixer and after vulcanization processing and foaming thereby producing an EVA foam, I.e. an elastomer of ethylene-vinyl acetate copolymer, having a thickness of about 25mm; slicing with a slicing machine: slicing the foam with a slicing machine into EVA foam slices each having a thickness of 5.5 mm; binding to a fabric: coating a layer of resin adhesive on the surface of the EVA foam slices; binding a special nonwoven fabric with the EVA foam slices thereby forming an integral body; hot press drying: feeding the composite body into a hot press to be dried at 195℃~205℃ and a pressure of 95~100 pounds for 30 s; secondary pressure shaping: subsequently applying a secondary pressure shaping at 80~100 pounds for 30 s; mold cutting: feeding the composite body into a mold to be cut into a shoe shape; punching with a punch machine: feeding the shoe pad into a punch machine where a row of holes are punched at the heel portion, and three rows of holes at the toe portion, thereby completing an antibacterial and deodoring shoepad.
Patent TW-385414-B (TW)
Title: Character recognition apparatus and character recognition method
Inventor: KAWAMATA TAKENORI
IPC: G06K9/46
Filed: 1997-12-17
Granted: 2000-03-21
Abstract: The invention is to sequentially recognize the object characters in high precision and high speed for on-line reading hand-writing characters even when the stroke order and number of strokes of the input characters is varying. When inputting hand-writing character ( inputted image ) on the input device 1, the stroke feature extraction device 2 will extract the features comprising the input hand-writing character. Based on the features, A feature categorizing device 4 is used to categorize the strokes into linear strokes, non-linear strokes and continuous character strokes. For the categorized stroke features, the linear stroke associating device 5 , non-linear stroke associating device 7 and continuous character stroke associating device 8 are used to correspond to the stroke features of the recognized object character ( standard image ) in the stroke feature dictionary 3;  The character evaluation apparatus 10 recognizes the hand-writing character based on this result.
Patent TW-452601-B (TW)
Title: Sputtering device and sputtering method
Inventor: KOBAYASHI MASAHIKO
IPC: C23C14/04
Filed: 1998-01-16
Granted: 2001-09-01
Abstract: A sputtering device includes a chamber equipped with an exhaust system. A sputtering power source applies specific high frequency electric power to the target. A supplemental electrode is provided so that it surrounds the flight path of sputter particles between the target and a substrate. The supplemental electrode is either maintained at a floating potential so that it is capacitively coupled with the target to which high frequency electric power has been applied, in addition, high frequency electric power of the same frequency may be applied directly to the supplemental electrode. A plasma P' is formed on the inside of the supplemental electrode, and the sputter particles released from the target are ionized. An extraction-use electric field is set up by an electric field establishment means, and is directed perpendicularly to the substrate. This construction and its associated method allow a film to be formed with good bottom coverage on the inner surfaces of holes whose aspect ratio is over 4.
Patent TW-379360-B (TW)
Title: Method of manufacturing a semiconductor device
Inventor: ONUMA HIDETO
IPC: H01L21/20
Filed: 1998-03-02
Granted: 2000-01-11
Abstract: A crystal growth 301 is carried out by diffusing a metal element, and a nickel element is moved into regions 108 and 109 which has been doped with phosphorus. An axis coincident with the moving directions 302 and 303 of the nickel element at this time is made to coincide with an axis coincident with the direction of the crystal growth, and a TFT having the regions as channel forming regions is manufactured. In the path of the region where nickel moved, since high crystallinity is obtained in the moving direction, the TFT having high characteristics can be obtained by this way.
Patent TW-418467-B (TW)
Title: Process for mounting electronic device and semiconductor device
Inventor: YAMAGIWA AKIRA
IPC: H01L23/13
Filed: 1998-03-10
Granted: 2001-01-11
Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.
Patent TW-407400-B (TW)
Title: Phase-locked loop circuit
Inventor: KIKUGAWA HIROHISA
IPC: H03L7/10
Filed: 1998-03-10
Granted: 2000-10-01
Abstract: The present invention is capable of attaining high-speed frequency transition with enhanced reliability. The solution is such that the outputs of a reference signal line (1) and voltage-controlled oscillator circuit (3) are frequency-divided by frequency divider circuits (2, 4), respectively. A phase comparator circuit (5) is provided for outputting an error signal indicative of a phase difference between these signals, if any. A window generator circuit (9) is connected for outputting a window signal; where the error signal does not fall within the range of a pulse width of this window signal, a level generator circuit generates a boost voltage having its potential near the control voltage value of the voltage-controlled oscillator (3) for use in generating of a target frequency. A low-pass filter circuit (7) is charged up in responding to receipt of both the output signal of the charge pump circuit (6) and the boost voltage so that the control voltage may rapidly increase in potential at a target value without rising up to any excess values. Whereby, undershoot and overshoot may be eliminated or at least greatly suppressed thus enabling achievement of high-speed frequency transition with increased reliability.
Patent TW-460476-B (TW)
Title: Fungicidal trifluoromethylalkylamino-triazolopyrimidines
Inventor: PEES KLAUS-JUERGEN
IPC: C07D487/04
Filed: 1998-03-16
Granted: 2001-10-21
Abstract: The novel compounds of formula I, wherein R1, R2, Hal and L1 through L5, are defined in the specification show selective fungicidal activity. The novel compounds, together with a carrier and assist agent, form a fungicidal composition. A compound of formula I, in which R1 and R2 each independently are hydrogen atom, or optionally substituted alkyl, alkenyl, alkynyl, alkadienyl, or phenyl; Hal represents a halogen atom; L1 to L5 each independently represent hydrogen or halogen atom or alkyl, alkoxyl or nitro, in which the terms alkyl, alkenyl, alkadienyl, or alkoxy represent a linear or branched group with plural to 6 carbon atoms; and in which each optionally substituted group is substituted by one or more halogen atoms, cyano, C1-C4-alkyl, C3-C6-cycloalkyl, C3-C6-cycloalkenyl, C1-C6-haloalkyl, C3-C6-halocycloalkyl, C1-C6-alkoxy, C1-C6-haloalkoxy, tri-C1-C4-alkysilyl, phenyl, halo- or bihalophenyl or pyridyl.
Patent TW-490469-B (TW)
Title: Preparation of recombinant Factor VIII in a protein free medium
Inventor: CHAN SHAM-YUEN
IPC: C12N5/00
Filed: 1998-07-29
Granted: 2002-06-11
Abstract: Recombinant Factor VIII can be produced in relatively large quantities on a continuous basis from mammalian cells in the absence of any animal-derived proteins such as albumin by culturing the cells in a protein free medium supplemented with polyol copolymers, preferably in the presence of trace metals such as copper. In very preferred embodiments, the medium includes a polyglycol known as Pluronic F-68, copper sulfate, ferrous sulfate/EDTA complex, and salts of trace metals such as manganese, molybdenum, silicon, lithium and chromium.