Patent GB-1239225-A (GB)
IPC: G06F7/52
Filed: 1968-07-11
Abstract: 1,239,225. Data processing. GENERAL ELECTRIC CO. 11 July, 1968 [14 July, 1967], No. 33077/68. Heading G4A. An arithmetic unit includes first storage means for retaining a binary multiplicand, and second storage means for retaining a binary multiplier at instruction initiation and at least. part of the product at instruction termination, logic means for performing a multiply algorithm, further logic means for selectively placing a prescribed configuration of bits in the second storage means to identify the most significant multiplier bit, the second storage means being shifted so that eventually the prescribed configuration is shifted out into additional storage means in serial communication with the second storage means, the multiply algorithm being terminated only when two conditions are satisfied, one being that the prescribed configuration is in the additional storage means and the other being dependent on the length of the multiplier and independent of the prescribed configuration. Details of floating-point multiplication.-The multiplicand and multiplier are loaded into the 48-bit B and A registers respectively, the signed mantissa occupying bits 00-38 and the signed exponent occupying bits 39-47 in each case. The exponent calculation is not described. The mantissa product sign is calculated and placed in bit 38 of a Q register. The multiplier mantissa is transferred to the Q register. The mantissa product is built up in the A and Q registers by successive addition and subtraction of the multiplicand mantissa to/from a partial product in the A and Q registers using the mantissa portion of an adder 28, together with shift of the A and Q registers. The partial product and multiplier are separated in the Q register by dummy bits 00. Subtraction is by complemented addition. Whether addition or subtraction is required and the amount of shift are decided in each case by one or more successive tests for particular bit patterns within the 6 lowest order multiplier bits in stages 00-03 and two extension stages (not shown) of the Q register according to an algorithm involving detecting strings of 0s and is and single included 0s in strings of is and minimizing the number of additions and subtractions required. Shifts of 2 or 4 bit positions to the right and of 1 bit position to the left are used, some shifting being via the adder 28. Bit positions 39-46 of the B register (" control counter ") are preset to 38 using the " exponent " portion of adder 28, complemented, then successively incremented by 1, 2 or 4 using the " exponent " portion of adder 28 as the mantissa multiplication proceeds. The control counter specifies the number of multiplier bits to be examined. The dummy bits 00 mentioned are used to force exiting from a string of 1's if present in the high order bits of the multiplier at the completion of the multiply algorithm. The product may be normalized. Other features.-Data and instructions are fed to the Fig. 2 unit (also usable for fixed-point calculations) via the gates 18 (top of Fig.) from another unit which performs instruction retrieval and address modification in parallel with operation of the Fig. 2 unit. The " control counter " can be set according to the number of bit positions to be shifted during floating point shift instructions, and can be used to determine the number of quotient bits generated in divide instructions.