Patent GB-716486-A (GB)
Title: Improvements in apparatus for electrically performing the mathematical operation of converting a number from one scale of notation into another
IPC: H03M7/08
Filed: 1951-01-29
Abstract: 716,486. Digital electric calculating-apparatus, SOC. D'ELECTRONIQUE ET D'AUTOMATISME. Jan. 29, 1951 [Jan. 28, 1950], No. 2216/51. Class 106 (1). [Also in Group XXXVIII] In apparatus for converting electrically a number from a radix A to a radix B less than A, e.g. in an electronic computer or automatic telephone system, the numbers in radix B corresponding to consecutive scale-of-A digits are staticized simultaneously or consecutively on an encoding device 22, read out successively in the form of series mode pulse trains beginning with that corresponding to the highest A-digit, and directed to an input of an adding circuit 34 forming part of a memory loop circuit which also includes two channels leading back to the input of 34, one directly, and the other via a circuit 39, 41 for multiplying the number represented by a circulating pulse train by A, and switch means 37 controlled in dependence on the introduction of a fresh pulse train into 34 temporarily disconnects the direct channel 38 and diverts the circulating train (if any) through the circuit 39/41. In the decimal-to-binary converter shown, for each decimal digit there is provided a similar encoding quadripole 22, e.g. as described in Specification 679,390, comprising a delay line with four output tappings (representing 1, 2, 4, 8 respectively) connected to contacts of a combination setting switch 26. The contacts may be relay-operated or may be replaced by electronic switches controlled by binary counters operated by dialling pulses. The read-out of successive digits by read impulses applied at 33'-333 is controlled by switches 42<SP>1</SP>- 423, the switch 37 being changed over, whenever one of the switches 42<SP>1</SP>-42<SP>3</SP> is closed, so as to pass the train circulating in the loop circuit through the tens multiplier comprising a threesection delay line 39 having output tappings as shown (corresponding to multiplication by 2 and 8 respectively) connected to a correcting carryover operator 41, e.g. as described in Specification 716,172. The adder 34 may be as described in Specification 716,312, and its output train is fed to a memory loop delay line 35 and to an output switch 43. In a modification, only one encoding device 22 is provided, the decimal digits being set up one by one and translated, if a manually-operated switch is closed, by an impulse applied at the beginning of each cycle of a computing machine in which the converter is incorporated. The switch 37 may comprise electronic gating valves controlled by a bistable trigger circuit also set by the reading impulses. The output switch 43 may also comprise a gating valve to which regularly recurring pulses are applied when the number stored in the loop circuit is to be read out. The encoding device may include permanent translating circuits such that each decimal digit may be translated by closing a single contact, Fig. 3 (not shown). Also, the decimal-digitrepresenting pulse trains may be sent to a preliminary memory circuit including a delay line long enough to hold all the trains simultaneously ; whenever entry of a new train or transmission to the loop circuit shown is to be effected, a switch is changed over so as to add an auxiliary portion of one train length or 4 # (where # is the digit delay time) onto the delay line, the timing of these operations being controlled by programming pulses.