baber/WOPTO huggingface dataset:
Patent TW-429294-B (TW)
Title: Chemical delivery system with ultrasonic fluid sensors
Inventor: BIRTCHER CHARLES MICHAEL
IPC: B01J4/00
Filed: 2000-10-09
Granted: 2001-04-11
Abstract: A chemical delivery system for delivering chemicals having at least a high purity includes at least one first reservoir for containing a fluid and at least one second reservoir for containing the fluid. The system also includes a first conduit, a first fluid sensor, and a controller. The first conduit is for transferring the fluid over time from the at least one first reservoir to the at least one second reservoir. The first conduit is metallic and has a first end in communication with the at least one first reservoir and a second end in communication with the at least one second reservoir. The fluid being transferred from the at least one first reservoir to the at least one second reservoir flows through the first conduit from the first end to the second end. The first fluid sensor is adjacent the first conduit, and the first fluid sensor is adapted to detect a presence of the fluid and to detect an absence of the fluid in the first conduit. The first fluid sensor generates at least one first signal indicative of the presence of the fluid or the absence of the fluid. The controller receives the at least one first signal. The controller is adapted to identify an empty condition in the at least one first reservoir upon receiving the at least one first signal indicative of the absence of the fluid in the first conduit or upon not receiving at least one first signal indicative of the presence of the fluid in the first conduit.
Patent TW-508757-B (TW)
Title: Semiconductor integrated circuit device and process for manufacturing the same
Inventor: YAMADA SATORU
IPC: H01L21/02
Filed: 2001-01-05
Granted: 2002-11-01
Abstract: This invention provides a semiconductor integrated circuit device including a DRAM having fine memory cells and a reduced bit line capacitance. A side wall insulating film of a gate electrode 7 (word line WL) is constructed by a side wall insulating film 10 made of silicon nitride and a side wall insulating film 11 made of silicon oxide having a dielectric constant smaller than that of the side wall insulating film made of silicon nitride, thereby reducing a capacity for a word line of a bit line formed over the gate electrode 7 (word line WL). By setting the level of the upper end of the side wall insulating film 11 made of silicon oxide to be lower than the level of the top face of a cap insulating film 9, the diameter in the upper part of a plug buried in each of spaces (contact holes 12, 13) between the gate electrodes 7 is set to be larger than the diameter in the bottom part to assure a contact area between the contact hole 13 and a through hole formed on the contact hole.
Patent TW-584905-B (TW)
Title: Method and apparatus for depositing films
Inventor: JOHNSON WAYNE LEE
IPC: C23C14/34
Filed: 2001-02-06
Granted: 2004-04-21
Abstract: A method and apparatus for performing physical vapor deposition of a layer or a substrate, composed of a deposition chamber enclosing a plasma region for containing an ionizable gas; an electromagnetic field generating system surrounding the plasma region for inductively coupling an electromagnetic field into the plasma region to ionize the gas and generate and maintain a high density, low potential plasma; a source of deposition material including a solid target constituting a source of material to be deposited onto the substrate; a unit associated with the target for electrically biasing the target in order to cause ions in the plasma to strike the target and sputter material from the target; and a substrate holder for holding the substrate at a location to permit material sputtered from the target to be deposited on the substrate.
Patent TW-473905-B (TW)
Title: Method for producing capacitor
Inventor: NI CHI-TSUNG
IPC: H01L21/70
Filed: 2001-04-16
Granted: 2002-01-21
Abstract: The present invention relates to a method for producing a capacitor. The present invention uses a porous insulative layer to replace a conventional boronphosphosilicate glass (BPSG) or plasma enhanced tetra-ethyl-ortho-silicate (PETEOS) oxide, etc. The sidewall of the contact opening formed from the porous insulative layer after a photolithography and etching process definition is coarser, thereby increasing the area of the electrode deposited subsequently and increasing the capacitance of the capacitor.
Patent TW-522296-B (TW)
Title: Communication apparatus, communication method, and recording medium used therewith
Inventor: KONDO TETSUJIRO
IPC: H04N21/236
Filed: 2001-05-16
Granted: 2003-03-01
Abstract: Encoded data that is obtained by embedding subdata in advertisement information and embedding the subdata-embedded advertisement information in main data is provided to a user. At the user side, the encoded data is decoded to reproduce the main data and the subdata-embedded advertisement information, and the subdata-embedded advertisement information is decoded to reproduce the advertisement information and the subdata embedded therein.
Patent TW-538313-B (TW)
Title: Positive photoresist composition
Inventor: SATO KENICHIRO
IPC: C08L45/00
Filed: 2001-06-12
Granted: 2003-06-21
Abstract: Provided is a positive photoresist composition which may decrease the occurrence of development deficiency during the manufacture of semiconductor devices. A positive photoresist composition comprises a resin which contains repeating units of a specific structure, the rate of the resin dissolving in an alkaline solution being increased by the action of an acid, and a compound which generates an acid upon irradiation with actinic rays or a radiation.
Patent TW-488063-B (TW)
Title: Semiconductor integrated circuit
Inventor: ITO TAKAYASU
IPC: H02H9/00
Filed: 2001-06-12
Granted: 2002-05-21
Abstract: The present invention relates to a semiconductor integrated circuit which incorporates voltage regulators for stepping down the externally-supplied power voltage and further the layout method of voltage regulator, for example a technique which is applied effectively to portable information terminals of data processing systems having their semiconductor chips required to be smaller in size and power consumption. The object of the present invention is to provide a semiconductor integrated circuit capable of suppressing the increase of a chip area caused by the incorporation of a regulator for stepping down an external power supply voltage and of stabilizing step-down voltage. To solve the problem, the semiconductor integrated circuit has an internal circuit to be operated by an internal power supply voltage (Vint) lower than an external power supply voltage (Vext). By placing regulators (150-157) for generating the internal power supply voltage in a second area (2) for locating a buffer and a protecting device, area overhead caused by making a step-down voltage power source circuit into on-chip is reduced. By using a loop-like power source line (L20) for transmitting the step-down voltage and utilizing an electrode pad or the like for connecting an external stabilized capacitor to a power source line, power consumption reduction is further promoted.
Patent TW-520515-B (TW)
Title: Memory module having programmable logic device and sTSOP
Inventor: JEON JUN-YOUNG
IPC: G11C8/12
Filed: 2001-08-01
Granted: 2003-02-11
Abstract: A memory module on a printed circuit board (PCB) has double density without increasing the area and height thereof. The memory module includes a first memory bank and a second memory bank that share data lines on the PCB. Each bank includes a group of packaged semiconductor memory devices. The memory module of the invention additionally includes a programmable logic device (PLD). The PLD outputs signals that selectively enable one of the first and second banks, in response to a bank select signal and control signals received from a memory controller. The package of the plurality of semiconductor memory devices is a shrink thin small outline package (sTSOP) or a chip size package (CSP) or plastic in which a length and a width are similar to each other.
Patent TW-546274-B (TW)
Title: Porous sintered body
Inventor: WATANABE OSAMU
IPC: C04B35/00
Filed: 2001-08-02
Granted: 2003-08-11
Abstract: A porous sintered body in which the leaching amounts of heavy metals are small and functioning, which contains 0.5-15 weight % of B2O3, and preferably contains 20-60 weight % of Al2O3, 18-60 weight % of SiO2, 1-12 weight % of the sum of Na2O, K2O, Li2O, and P2O5, 1-30 weight % of the sum of CaO, SrO, BaO, and MgO, and 0.5-15 weight % of B2O3.
Patent TW-501174-B (TW)
Title: Photoresist baking device
Inventor: CHEN KUEN-JIAN
IPC: H01L21/00
Filed: 2001-08-31
Granted: 2002-09-01
Abstract: This invention provides a photoresist baking device, which mainly consists of a reaction tank, a heating unit and at least a partition plate. The partition has or is connected to at least a warming unit to increase temperature of the partition plate and the photoresist coated substrate is heated between the heating unit and the partition plate. Therefore, the solvent vapor generated from the photoresist coated substrate during heating can remain decomposed or gaseous state, when contacting the warm-up partition plate, without condensing on the partition plate. This can ensure that there is no particle contaminant source formed on the partition plate because the vapor generated during heating can be completely removed from the reaction chamber through the ventilation hole of the partition plate.
Patent TW-531995-B (TW)
Title: Data buffer structure for asynchronously received physical channels in a CDMA system
Inventor: SHIU DA-SHAN
IPC: H04B1/707
Filed: 2001-09-06
Granted: 2003-05-11
Abstract: A receiver unit (136) for use in a CDMA system and including a channel processor (810), a buffer (512), and a data processor (516). The channel processor (510) processes samples for one or more physical channels for each time interval to provide symbols (612). The buffer is operated as a number of memory banks (Fig. 3). Each memory bank is associated with a respective time interval and stores symbols associated with that time interval. The data processor (516) retrieves symbols for a particular ""traffic"" from one or more memory banks and processes the retrieved symbols (622, 624). For the W-CDMA system, each traffic includes one or more radio frames for a particular transmission time interval. The receiver unit (136) typically further includes a controller (520) that directs the storage and retrieval of symbols (614) to and from the memory banks and a decoder (518) that decodes (624) symbols processed by the data processor. For each time interval, radio frames for physical channels received starting within that time interval can be stored (614) to permutated locations of designated sections of the memory bank (Fig. 7). Radio frames associated with a particular CCTrCH can be stored to contiguous sections of the memory bank. Symbols for a particular traffic can be retrieved from one or more memory banks in permutated order.
Patent TW-518789-B (TW)
Title: Process for producing lithium secondary battery
Inventor: SADA TSUTOMU
IPC: H01M10/05
Filed: 2001-09-27
Granted: 2003-01-21
Abstract: This invention relates to a process for producing a lithium secondary battery comprising a negative electrode, a positive electrode, and disposed therebetween a polyelectrolyte which comprises an ionically conductive polymer matrix holding a nonaqueous electrolytic solution. The process comprises applying a mixture of a nonaqueous electrolyte and a monomeric precursor for an ionically conductive polymer to each electrode after applying to each electrode a nonaqueous electrolytic solution not containing the monomeric precursor or containing it in a low concentration, and then forming the mixture applied into a polyelectrolyte layer united with each electrode.
Patent TW-I285329-B (TW)
Title: Speculative register adjustment
Inventor: ROTH CHARLES P
IPC: G06F9/30
Filed: 2001-11-01
Granted: 2007-08-11
Abstract: In one embodiment, a programmable processor is adapted to include a speculative count register. The speculative count register may be loaded with data associated with an instruction before the instruction commits. However, if the instruction is terminated before it commits, the speculative count register may be adjusted. A set of counters may monitor the difference between the speculative count register and its architectural counterpart.
Patent TW-550453-B (TW)
Title: Debugger for computer system
Inventor: TANG JR-CHIAN
IPC: G06F11/00
Filed: 2001-12-28
Granted: 2003-09-01
Abstract: The present invention provides a debugger for computer system, which is applied for a computer system, for example a notebook computer or a desktop personal computer, and the computer system at least comprises a power indicator, a battery indicator, a hard disk operation indicator, a floppy disk operation indicator, a Num Lock indicator, a Caps Lock indicator, and a Scroll Lock indicator for indicating the abnormal system conditions of the computer system with those seven indicators. The combination of seven indicators can provide at most 512 different display statuses, so as to indicate 515 different abnormal system conditions. Moreover, in the embodiment, it only needs to modify the current BIOS in the computer system without attaching any external hardware device and adaptation circuit, or modifying the existed motherboard structure. Thus, the present invention is easier to implement than the prior art, and has higher cost efficiency.
Patent TW-519703-B (TW)
Title: Manufacturing method of high-voltage device
Inventor: LIOU MU-YI
IPC: H01L21/8234
Filed: 2002-01-16
Granted: 2003-02-01
Abstract: A manufacturing method of high-voltage device is disclosed. Firstly, a substrate is provided with a gate structure of a high-voltage device is already formed on the substrate. Then, a first doped region is formed on both sides of the gate structure of the high voltage device on the substrate after proceeding the first thermal process. A spacer is formed at the side edge of the gate structure of the high-voltage device, and an oxide layer is formed on the gate structure of the high-voltage device and the surface of the first doped region. A second doped region is formed on both sides of the spacer on the substrate after proceeding the second thermal process.
Patent TW-544392-B (TW)
Title: Method for adjusting at least one pressing element of a machine for machining wood or plastic workpieces and device for carrying out the method and pressing for use with such a device element
Inventor: WAGNER RALF
IPC: B25B1/24
Filed: 2002-01-23
Granted: 2003-08-01
Abstract: Disclosed is a method for adjusting at least one pressing element of a machine for machining workpieces of wood or plastic material that adjusts the pressing element relative to a workpiece, the workpiece being transported by the machine and to be machined by the machine, wherein the pressing element (19), (20) is adjusted in an adjusting device outside the machine and is then positioned into the machine after the adjustment process. Further disclosed is a device for carrying out the method, the device comprising at least a retainer (41) for retaining at least one carrier (30). The carrier (30) is provided thereon with the pressing element (19), (20). Further disclosed is the pressing element used by the device, in which on a body (54) is provided with a pressing body (55) that is supported in a movable manner.
Patent TW-536730-B (TW)
Title: Chemical compound semiconductor switching circuit device
Inventor: ASANO TETSURO
IPC: H01P1/15
Filed: 2002-02-26
Granted: 2003-06-11
Abstract: A chemical compound semiconductor circuit device has a different arrangement from conventional devices with a large gate width Wg, and a reduced turning on-resistance of FET for minimizing an insertion loss. The device of this invention is capable of solving the problem of insufficient output power with a conventional device of the kind having the gate width of 400 mum for shrinking the chip size, while a gate width of 600 mum has been adopted in order to obtain a desired isolation. The device of this invention is focused on an asymmetric type circuit having a channel region of a high frequency band of more 2.4 GHz without a shunt FET to assure an isolation, having a transmitting side FET and a receiving side FET with a different concentration of dopant. Thus a circuit with the gate width reduced to 400 mum, and with a reduced capacitance component of the gate electrode is obtained so that a desired isolation between the two signal paths is obtained and a needed maximum power output is available.
Patent TW-544921-B (TW)
Title: Semiconductor memory device
Inventor: NII KOJI
IPC: G11C15/04
Filed: 2002-03-18
Granted: 2003-08-01
Abstract: A gate of an NMOS transistor (N1) is connected to a memory terminal (Na) and a gate of an NMOS transistor (N2) is connected to a memory terminal (Nb). Sources of the NMOS transistors (N1, N2) are commonly connected to an internal terminal (Nc) and a ground potential (GND). Potentials of backgate terminals (BN1, BN2) of the NMOS transistors (N1, N2) are set to the ground potential (GND). When PMOS transistors (P1, P2) are in ON and OFF states, respectively, the memory terminal (Na) is brought into a logical ""H"" state and the memory terminal (Nb) remains a logical ""L"" state by a gate-leak current passing from the gate of the NMOS transistor (N2) to a semiconductor substrate. With such a structure, a semiconductor memory device having a memory cell structure to ensure reduction in cell area can be achieved.
Patent TW-550821-B (TW)
Title: Semiconductor device and active matrix display device
Inventor: YAMADA TSUTOMU
IPC: H01L27/12
Filed: 2002-03-25
Granted: 2003-09-01
Abstract: Provided are a semiconductor device and an active matrix display device of which the polysiliconization by laser annealing is made properly. An active matrix type display device, such as a driver built-in type active matrix display device, has a metal layer 32 formed on a part region of transparent substrate and a buffer layer 11 covering both the forming region and non-forming region of metal layer 32. Above the buffer layer 11, a first polysilicone film and a second polysilicone film are respectively provided on forming region and the non-forming region of metal layer. Buffer layer 11 has sufficient thickness and heat capacity, and the interlayer gap between active layer and metal layer thereunder is increased, so that the heat leak due to metal layer becomes less. Therefore the first and the second polysilicone film of proper grain size are obtainable by annealing the amorphous silicone film formed on the buffer layer 11 with laser set to same condition.
Patent TW-556196-B (TW)
Title: Threshold voltage compacting for non-volatile semiconductor memory designs
Inventor: FASTOW RICHARD
IPC: G11C16/34
Filed: 2002-04-03
Granted: 2003-10-01
Abstract: A flash memory design with a compact threshold voltage distribution and a method for compacting the threshold voltage for a flash memory design are disclosed. The threshold voltage is compacted by erasing (602) a plurality of memory cells to set the threshold voltage for the memory cells substantially towards a median erased threshold voltage; verifying (604) at least one fast-erase memory cell; selectively soft-programming (606) the memory cells; and erasing (608) subsequent to selectively soft-programming.
Patent TW-I235174-B (TW)
Title: Liquid cryatal compound and phase contrast film using the same
Inventor: TANAKA KOUICHI
IPC: C09K19/38
Filed: 2002-05-09
Granted: 2005-07-01
Abstract: This invention discloses a phase contrast film formed with a liquid crystal film comprising cellulose derivative liquid crystal as the liquid crystal compound. The liquid crystal (cellulose derivative liquid crystal) is orientated at specific orientation, and the orientation is preferably being fixed. The said liquid crystal film can easily obtained a film with variety of wave dispersing characteristic, by optionally changing the molecular weight of cellulose derivative, liquid crystal composition, orientation degree, etc.. A phase contrast film satisfying the following formula (1) can be obtained without laminating several phase contrast films. Deltan450 <= Deltan550 <= Deltan650 (1), (wherein, Deltan550 represents the double refraction ratio of wave 550 nm, Deltan450 represents the double refraction ratio of wave 450 nm, Deltan650 represents the double refraction ratio of wave 650 nm). The said phase contrast film is useful in image display device with excellent anti-refraction effect, and improves the effects of contrast elevation and double refraction compensation.
Patent TW-563348-B (TW)
Title: Light source apparatus for a scanner
Inventor: HSU HSIU-O
IPC: H04N1/40
Filed: 2002-06-21
Granted: 2003-11-21
Abstract: Light source apparatus for a scanner, comprising a printed circuit board and several light emitting components. There are several electrodes and several holes on the printed circuit board, in which each hole being located between the area of electrodes. On the side of light emitting component have a couple of electrical terminals, and on the button of light emitting components have a least fixer. Light emitting components are mounted on the printed circuit board. Terminals can electrically couple to electrodes, and a fixer can contacts to holes so that light emitting components can fix on the printed circuit board exactly.
Patent TW-561701-B (TW)
Title: Frequency mixing circuit
Inventor: MIYAGI HIROSHI
IPC: H03D7/14
Filed: 2002-06-26
Granted: 2003-11-11
Abstract: It is object to provide a frequency mixing circuit capable of reducing low-frequency noise generated when the frequency mixing circuit is formed integrally on a semiconductor substrate with using a CMOS process or a MOS process. A high frequency amplification circuit 11, a mixing circuit 12, a local oscillator 13, an intermediate-frequency filters 14 and 16, an intermediate-frequency amplifier 15, a limiter circuit 17, an FM detection circuit 18 and a stereo demodulation circuit 19 that compose an FM receiver are constituted as one-chip part 10. The mixing circuit 12 is formed on a semiconductor substrate with using a CMOS process or a MOS process, and a p-channel FET is used for a transistor that constitutes the circuit.
Patent TW-552773-B (TW)
Title: Multilayered LC composite component and method for manufacturing the same
Inventor: SASAKI TOMOHIRO
IPC: H05K1/02
Filed: 2002-07-11
Granted: 2003-09-11
Abstract: A multilayered LC composite component includes a main body having a pair of side surfaces, a pair of end surfaces, and an upper surface and a lower surface. Ground-side terminal electrodes are disposed at the center of the side surfaces and hot-side terminal electrodes are disposed along edges of the side surfaces. Each of the hot-side terminal electrodes includes an end surface extended portion extending to each of the end surfaces. The end-surface extended portion is arranged so that at least the approximate center of each of the end surfaces is exposed.
Patent TW-I236450-B (TW)
Title: A combination pair of like shaped carriers and a film frame sandwiched therebetween
Inventor: NIGG JAMES
IPC: B65D85/86
Filed: 2002-07-15
Granted: 2005-07-21
Abstract: An interlockable film frame carrier has central and peripheral portions for securely storing a film frame, the film frame supporting a film, a semiconductor wafer disposed on the film. The central portion has structure for supporting the semiconductor wafer and for allowing access to a lower surface of the stored film frame. The peripheral portion of the film frame carrier includes structure for supporting a peripheral portion of the film frame and matable stacking members. When the film frame is stored, two film frame carriers are interlocked by mating the stacking members. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.