Patent GB-1119438-A (GB)
Title: Electrical data storage devices
Inventor: FEDIDA SAMUEL
IPC: H01L29/00
Filed: 1966-05-13
Abstract: 1,119,438. Data storage. ENGLISH ELECTRIC CO. Ltd. 8 May, 1967 [13 May, 1966], No. 21320/66. Heading G4C. [Also in Division H1] An electrical data storage device comprises a body of material having a plurality of insulated grids coupled thereto, the grids being energizable to create in the body a potential " well " surrounded by a region held substantially free of free charge carriers, there being means for injecting free charge carriers into the well and for detecting their presence there. Fig. 1 shows a rod 10 of intrinsic (i.e. high purity) monocrystalline silicon with five grids or meshes BG1 to BG3 embedded in it spaced along its length, each grid consisting of interconnected conductors 11 each surrounded by sapphire insulator 12. Potentials applied to the grids establish a series (two) of progressively deeper (i.e. more positive) potential wells spaced along the rod, at SG1, SG2, progressively lower potential barriers occurring at BG1, BG2, BG3. By lowering potential barriers, bunches of electrons can be admitted from electrode EL1, shifted from well to well along the rod, and passed out to electrode EL2. In this way, a bit 1 or 0 is stored in a given well as the presence or absence of a bunch of electrons respectively. Stored data could also be detected from the capacitive change in the potentials on grids SG1, SG2 on entry and exit of electron bunches to and from the wells. EL1 and BG1 could be omitted, electrons being injected by means of an electron beam. Read-out could be by injecting more electrons into the last well using an electron beam, so that the last barrier is overflowed if and only if the well already contained a bunch of electrons. Layers of P or N type impurity could be provided on the rod adjacent to the electrodes EL1, EL2 to act as transistors controlling injection of charge carriers and performing amplification at read-out. Two and three phase bidirectional shifting methods are described which obviate the necessity of progressive diminution of well and barrier potentials right along the rod, allowing use of more grids for greater storage capacity. In the two-phase method, the bit capacity is half the number of wells, viz. a quarter the number of grids. In the three-phase method, the bit capacity is a third the number of grids and the wells shift along the rod from grid to grid. Fig. 7 (not shown) shows one construction method in which a layer of silicon oxide insulator (31) is deposited over one side (except at the ends) of a rectangular plate of monocrystalline intrinsic silicon. Parallel conducting bands are then deposited on the insulator (to form the grids) and on the exposed ends of the silicon plate (to form the end electrodes). Fig. 8 shows another construction, obtained by progressive epitaxial deposition with the use of masks, on a plate 40 of intrinsic silicon, of bars 41 of sapphire insulator, bars 42 of heavily doped conducting silicon, bars 43 of sapphire insulator, a layer 44 of intrinsic silicon etc. Thus the crystal structure is maintained throughout the device. Horizontally or vertically aligned bars 42 in Fig. 8 are electrically connected in groups to form the grids, or the grids could be deposited complete. Suitable electrodes are also deposited. Gallium arsenide could be used instead of intrinsic silicon. The logical OR function could be performed by transferring the contents of two wells to one well, the quantity of charge resulting being normalized by barrier overflow. In Fig. 9, the circles 51 represent grids, the solid circles being those normally used for storage. For read-or write, the bit positions of the appropriate arm C1, C2 or C3 are shifted into the arm C4, e.g. as shown by the dashed line 52, until the required bit position is at 51D. For read-out, an electron beam 53 adds electrons to the well at 51D so that if it already contains a bunch (i.e. stores 1), the barrier at 51G is overflowed and a pulse appears at electrode EL3. For write-in, the well at 51D is emptied by lowering the barrier at 51G, then electrons are injected or not from beam 53. The data can be shifted back into the appropriate arm C1, C2 or C3. The arms C1 to C3 could be joined together at the top. A stack of devices, each as in Fig. 9, can be formed, the electron beam 53 and electrode EL3 being in common for serial read or write, or separate electrodes EL3 could be provided together with separate electrodes used for write-in, allowing parallel read or write. The device of Fig. 9 can be constructed (Fig. 10) by successive epitaxial deposition on a base of monocrystalline sapphire 60 of successive spots, layers, annuli and columns so that each grid is formed from heavily doped conducting silicon in the form of two parallel discs 61, 69 linked by a column 62, and passes through the appropriate arm of Fig. 9 constituted by intrinsic silicon 66. Sapphire insulator 63, 64, 65, 67, 68 is provided. A stack of the Fig. 9 devices can be formed integrally, the discs 69 of one device being the discs 61 of the next. Fig. 12 (not shown) shows a modification of Fig. 9 in which the vertical arms C1, C2, C3 are symmetrical about the horizontal arm shown, only one half of each being normally used for storage, and to get a given bit into the read-write position, the data in its half-arm is shifted into the other half of the arm until the bit is in the horizontal arm, then the contents of this are shifted into arm C4 as far as necessary. A one-bit storage device (Fig. 13, not shown) uses a block of silicon having one electrode and a storage grid (at which the well is positioned) the two being separated by a part-width barrier grid. Row and column addressing wires in a matrix of these devices are applied to the barrier and storage grids respectively. In this way a single device can be selected, or a set of them along a third dimension. Data being read or written is obtained from or applied to the electrodes. Fig. 18 shows a system, which can be formed in a single block as before, and uses electron beams 154, 158, for writing and reading respectively, reading being by causing overflow (see above) to the electrodes shown connected to line EL8. The data read out may be rewritten. Matrix addressing may be used instead in this embodiment. Storage could be analogue.