baber/WOPTO huggingface dataset:
Patent TW-328591-B (TW)
Title: Sense circuit
Inventor: SUYAMA JUNICHI
IPC: G11C11/407
Filed: 1997-06-12
Granted: 1998-03-21
Abstract: A sense circuit comprises: (1) A first and second sense amplifier circuit, the first and second sense amplifier circuit connect with a bit line pair, and the first and second sense amplifier circuit will sense tiny voltage difference responsive to the bit line pair of storage data of a memory cell; (2) A transfer gate for applying conductance control between said bit line pair and said first and second sense amplifier; (3) An enable signal generating circuit, in which the enable signal generating circuit is based on a given control signal to generate a first enable signal and a second enable signal with complementary level theoretically; (4) A first MOS transistor, in which the first MOS transistor is connected between said first sense amplifier and a first power voltage, the first MOS transistor is based on said first enable signal input to a gate to perform ON/OFF, the first MOS transistor will enable the first sense amplifier when in ON state; (5) A second MOS transistor, in which the second MOS transistor is connected between said second sense amplifier and a second power voltage with level higher than first one^s, the second MOS transistor will do ON/OFF operation after input said second enable signal to gate, the second MOS transistor will enable the first sense amplifier when in ON state; (6) After enabling said first and second sense amplifiers, the sense circuit will perform charge/discharge to said first and second power voltage with respect to said bit line pair, the sense circuit sets tiny voltage difference between said bit line pair to voltage difference corresponding to theoretical level of said stored data; (7) The structure of said enable signal generating circuit is setting said second MOS transistor in theoretical level of said second enable signal into theoretical level of ON state, then setting the theoretical level to intermediate level between said first power voltage and second power voltage.
Patent TW-334651-B (TW)
Title: Piezoelectric vibratory gyroscope utilizing an energy-trapping vibration mode
Inventor: YOSHIDA TETSUO
IPC: G01C19/56
Filed: 1997-06-19
Granted: 1998-06-21
Abstract: A piezoelectric vibratory gyroscope utilizing an energy-trapping vibration mode comprises a piezo-electric plate having a principal surface and polarized in a thickness direction, and first through n-th electrodes (n being an integer not smaller than three) formed in a generally central area of the principal surface at positions corresponding to first through n-th vertexes of a polygon having n angles. When the piezoelectric plate is excited in the energy-trapping vibration mode of a primary vibration, rotation of the piezoelectric plate around an axis perpendicular to the principal surface of said piezoelectric plate produces the Coriolis force to excite a secondary vibration which induces electric voltages at the first through the n-th electrodes. A voltage difference is detected for at least two of the first through the n-th electrodes.
Patent TW-353636-B (TW)
Title: Method of producing a synchronous drive belt
Inventor: GREGG MICHAEL JOHN WILLIAM
IPC: B29D29/08
Filed: 1997-08-08
Granted: 1999-03-01
Abstract: A method of producing a synchronous drive belt having teeth extending from a belt surface, the method characterized by the steps of: assembling an internal drum mold having a first set of concentric molding rings, the first set of molding rings comprising adjacent right hand and left hand rings, the right and left hand rings having teeth-forming grooves therein, the grooves on each of the right and left hand rings being separated by a pre-determined pitch; building a multi-plied belt hand around the drum mold; curing the belt hand; segmenting the cured belt band into belt widths; and removing the belt widths from the mold after the step of segmenting the belt band into widths.
Patent TW-384592-B (TW)
Title: Security method for transmissions in telecommunication networks
Inventor: RAIVISTO TOMMI
IPC: H04L9/28
Filed: 1997-09-15
Granted: 2000-03-11
Abstract: A method for providing safe communication in transmission between two parties in a communication network. The method includes the following steps: exchanging security parameters among the communicating parties, providing thus communication security for multiple messages based on the security parameters, for transmission of said messages among the communicating parties and reaching agreement with newly calculated cycles of the security parameters among the parties, for monitoring newly calculated cycles among the communicating parties, for new calculation of said security parameters for the agreed cycles and providing secured communication for the messages based on the newly calculated security parameters.
Patent TW-366568-B (TW)
Title: Manufacturing method of polysilicon loads
Inventor: LIN HAN
IPC: H01L27/11
Filed: 1997-10-27
Granted: 1999-08-11
Abstract: Manufacturing method of polysilicon loads by forming silicon diode layer for insulation to keep the high-density ion of interconnect doping from entering into the low-density ion doping or undoped load for maintaining the polysilicon in effective length and load resistance for further reduction of the size of DRAM; besides, the insulation layer keeps high-density ion from traveling or diffusing to the low-density area, without affecting the conductivity of the interconnect, for easy control of the components of higher reliability.
Patent TW-365026-B (TW)
Title: Semiconductor cathode and electron tube comprising a semiconductor cathode
Inventor: VAN ZUTPHEN TOM
IPC: H01J1/308
Filed: 1997-10-30
Granted: 1999-07-21
Abstract: Semiconductor device with a semiconductor cathode having an emissive part (pn junction) separated from a contact part which has locations at which a controlled breakdown occurs on a contact metallization at too high voltages, so that, during manufacture and operation, the emissive part in an electron tube is protected from damage.
Patent TW-459041-B (TW)
Title: Process and apparatus for catalytic partial oxidation of a hydrocarbon substrate
Inventor: PRIMDAHL IVAR IVARSEN
IPC: C01B3/38
Filed: 1997-11-07
Granted: 2001-10-11
Abstract: Process and apparatus for the preparation of a hydrogen/carbon monoxide containing synthesis gas by catalytic partial oxidation reaction of a hydrocarbon feed gas by carrying out the process in a number of separated steps. In each step only a small fraction of the stoichiometric amount of oxygen is added to the reaction and the feed gas is passed through a catalytic zone arranged in each step, so that complete conversion of the added amount of oxygen is obtained in each step.
Patent TW-375711-B (TW)
Title: Single chip multiprocessor with shared execution unit
Inventor: MELTZER DAVID
IPC: G06F15/78
Filed: 1997-12-11
Granted: 1999-12-01
Abstract: The present invention relates to multiprocessors which has several microprocessors on a single chi. Efficiency is improved by stripping certain functions that are used less freely from the microprocessor and sharing these function between several symmetric microprocessors. This method allows each CPU to occupy a smaller area while preserving complete symmetry of capability for software simplification. For example, the shared execution units can include the floating unit and multimedia execution units.
Patent TW-358721-B (TW)
Title: Clip strip
Inventor: WERNER THEODORE J
IPC: A47F5/00
Filed: 1998-03-25
Granted: 1999-05-21
Abstract: A kind of clip strip comprising: an elongated panel having a first end, a second end, a first margin, a second margin and a first surface, in which the first surface has at least one aperture; flexible support device is mounted on the first surface of the panel; clips having a first end, a middle part, a second end, a first part between the first end and the middle part, a second part between the middle part and the second end, in which the first end can be separated from the flexible support, the middle part mounted on the flexible support, the second end of the clip can be inserted into the aperture and the second end of the clip can be inserted below the surface of the panel.
Patent TW-420785-B (TW)
Title: Connector for the connection of a card with integrated circuit(s), and unit equipped with a connector of this type
Inventor: BRICAUD HERVE
IPC: H01R24/62
Filed: 1997-04-15
Granted: 2001-02-01
Abstract: The invention proposes a connector (64) for connecting a contact card (C) with integrated circuit(s) to a unit which includes a support (66) made of insulating material, characterized in that it includes a device (172) which is intended for holding the card in the position in which it is inserted into the connector and includes a lip (174) which includes a rear cut-out whose profile is complementary to that of the front transverse edge (99) of the card, and in that, in order to extract the card, irrespective of whether the extraction mode is manual or automatic, it is necessary to unlock it by acting on the lip (174) in order to move the lip vertically so as to release the card.
Patent TW-429680-B (TW)
Title: General high-resolution multi-phase clock generator
Inventor: JU HUNG-CHI
IPC: H03K3/86
Filed: 1998-05-29
Granted: 2001-04-11
Abstract: The present invention provides a structure for a general high-resolution multi-phase clock generator, which is suitable for any number of phases by using a delay difference locked loop in a delay locked loop array. In addition, the length and width of the array can be selected to approximate to the optimal values of a square, so as to increase the design margin of the delay unit and decrease the phase error due to the mismatch of the delay element.
Patent TW-385428-B (TW)
Title: The method and device for a graphic display useful in electrical-data processing product
Inventor: JANG JING-SUNG
IPC: G09G5/36
Filed: 1998-06-02
Granted: 2000-03-21
Abstract: This present invention is about a method and device for graphic display which employs a graph generator unit to generate at least one graph element onto a graph display device to constitute multi- level formed graph, and then by a CPU according the command  of the input unit to control the configuration of the graph element showing onto the graphic display device, further by a logic operator unit to recognize the contents of graph showing onto the graph display device so as to output a corresponding information to the CPU as a basis to change the showing contents onto the graphic display device, in the meantime storing the above-mentioned system information into a memory unit.
Patent TW-392337-B (TW)
Title: Method for forming selective hemi-spherical grains
Inventor: SHIE WEN-YI
IPC: H01L21/20
Filed: 1998-06-29
Granted: 2000-06-01
Abstract: A method for forming selective hemi-spherical grains in the process of manufacturing DRAM capacitors is disclosed, which includes a step of forming an amorphous silicon layer doped with ions. A polysilicon layer is then formed by annealing and diffusing processes. Simultaneously, selective hemi-spherical grains are formed on the border of the polysilicon layer, so as to increase the effective contact area of the capacitor. Next, ions are diffused to the surface area of the hemi-spherical grains by a rapid thermal process, so as to produce an uniform distribution for the ion concentration on the surface area. Therefore, with the present invention, a depletion phenomenon caused by contacting a conductor can be avoided.
Patent TW-406218-B (TW)
Title: Extended resolution phase measurement
Inventor: WANG NIAN-TSU
IPC: G01R23/10
Filed: 1998-07-03
Granted: 2000-09-21
Abstract: A circuit (10) for determining periods of and the phase relationship between waveform signals (28 and 30). A delay line (12) having a sample port (14), a set port (16), a reference port (18), and an output port (20) and further internally including a chain of delay elements (32) associated with latch elements (34) and an encoder (36). The delay line (12) receive a first signal (28) into the sample port (14), and via a switch (22) also into the set port (16). The encoder (36) then provides the period of the first signal (28) at the output port (20) of the delay line (12) in units of delay created by each delay element (32). A control unit (24) then operates the switch (22) to direct a second signal (30) into the set port (16) for comparison with the first signal (28) at the sample port (14), and values are obtained at the output port (20) relating edges of a cycle in the second signal (30) to edges of the first signal (28), from which period of the second signal (30) and the phase relationship between the signals (28 and 30) is calculated with an arithmetic unit (26).
Patent TW-395087-B (TW)
Title: Output buffer with high speed and low noise level
Inventor: HUANG JIN-CHENG
IPC: H03K19/00
Filed: 1998-07-16
Granted: 2000-06-21
Abstract: The invention provides an output buffer with high speed and low noise level. It is applicable in slew controlling the gunning transceiver logic (GTL+) signals. The last output element is driven simultaneously by both the normal and rapid driven elements. The normal and rapid driven elements will act synchronously when the input signal is changing from one state to another. The rapidly driven element will pull up the control voltage of the output element to a potential level with one potential difference less than the last potential. The potential level will then be pulled up to the last potential level by the normal driven element. The output element's operation will be rapid at first. Then, the output operation will be slow down when it is close to the last potential level. By reducing the delaying time of output buffer without causing any large echoes in output signals, high speed and low noise level can be accomplished.
Patent TW-409229-B (TW)
Title: Multi resolution quality image scanning apparatus
Inventor: LIN CHAU-TZUNG
IPC: G06K7/10
Filed: 1998-07-22
Granted: 2000-10-21
Abstract: This invention relates to a kind multi resolution quality image scanning apparatus used in the image processing apparatus, wherein it comprises: one reflected lens set; and a plurality of lens which could be catering with the reflected lens set and produce several optical outputs with various degree of resolution and various paths, and to focus various optical output on one sensor apparatus; it is characterized that: the sensor device having the number the same as that of the lens, the sensor device in corresponding to each other, which could provide at least one electric signal of the sensor device into an image processing unit through the control of the control circuit.
Patent TW-380102-B (TW)
Title: Job offset assembly
Inventor: BASKETTE MICHAEL WESLEY
IPC: B65H29/60
Filed: 1998-08-10
Granted: 2000-01-21
Abstract: A job offset assembly to separate into multiple stacks the output from a copier, printer or the like, includes a platform upon which a plurality of offset assemblies are rotatably mounted, each offset assembly including a skew roller which turns about an axis that, when the offset assemblies are rotated, is not parallel to the axis about which a drive roller associated with the skew roller turns. A gear or rack-and-pinion type offset actuation system enables the offset assemblies to rotate repeatedly back and forth between predetermined positions, so that as media encounters the skew rollers it is directed against a reference edge and into an output stack associated with the offset assembly position.
Patent TW-391115-B (TW)
Title: Method and apparatus for identifying signals for a set of communication devices in a signal stream having signals for a number of different sets of communication devices
Inventor: GOODY STEVEN H
IPC: H04L12/56
Filed: 1998-08-10
Granted: 2000-05-21
Abstract: The invention provides method and apparatus for identifying signals for a set of communication devices in a signal stream having signals for a number of different sets of communication devices. Some embodiments of the invention are methods and devices for extracting signals for a first set of communication devices from a signal stream having signals for a number of different sets of communication devices. Other embodiments of the invention are methods and devices for inserting into a signal stream signals from a first set of communication devices. Yet other embodiments of the invention are time division multiplexing and demultiplexing methods and apparatuses that use a content addressable memory to identify sets of signals for a particular set of communication devices. In addition, some embodiment of the invention are used in fiber optic telecommunication networks. These embodiments include an optical network unit that receives an integrated signal stream having signals for different types of applications. The optical network unit includes a content addressable memory that stores locations in the received signal stream of signals for a first type of  communication application.
Patent TW-369583-B (TW)
Title: Concreting rooming wall system construction method
Inventor: WU MING-YU
IPC: E04B2/86
Filed: 1998-08-31
Granted: 1999-09-11
Abstract: A kind of "concreting rooming wall system construction method", it is to draw base line to the rooming wall surface and floor surface; following by putting fixing members at on/below and left/right of the fixed proper distances on the base line, and then to fix the straight member onto the fixed members, to fix transverse materials on, in, under the straight members, next to fix the first cement board material to the transverse material, then to proceed plumbing and electrical piping, and to fix the second cement board material to transverse material at the other side, and outside the two cement board materials to place outer form straight member and outer form transverse member, and to fix the outer form straight member and outer form transverse member with fixing bars, an opening is cut on cement board material for concreting, finally to remove outer form for forming a kind of construction method of partition wall concreting rooming system. This invention provides a kind of concreting rooming wall system construction method, its characteristics is to combine and improve overall building partition wall construction, its property lies in improving existing old rooming wall that is time consuming and inconvenient, increasing the rooming wall quality.
Patent TW-393682-B (TW)
Title: Method for restoring alignment function of alignment marks
Inventor: JU JR-SHIUN
IPC: H01L21/027
Filed: 1998-10-19
Granted: 2000-06-11
Abstract: The invention provides a method for restoring alignment function of alignment marks by filling chemical etching agent in a device. Through pipeline of the device, chemical etching agent can accurately cover the film above the alignment mark so that chemical etching reaction occurs between etching agent and the film above the alignment mark. The residue from the etching reaction is extracted by pumping pipeline of the device. This method simultaneously etches and removes parts of the film above the alignment mark to restore the alignment function of alignment marks.
Patent TW-542864-B (TW)
Title: Low density resilient webs and methods of making such webs
Inventor: CHEN SHAN LIANG
IPC: D21F11/00
Filed: 1998-10-20
Granted: 2003-07-21
Abstract: A method for making a textured tissue sheet on a conventional tissue making machine using a conventional cylindrical drum dryer creates a product that is remarkably bulky, soft, and wet resilient. A combination of rush transfer and sheet molding with three-dimensional fabrics is combined with the step of web inversion to ensure that the surface of the web which was molded onto a first textured transfer fabric is the surface which is placed against the surface of the cylinder dryer. Web inversion improves machine productivity and enhances physical properties of the web.
Patent TW-405247-B (TW)
Title: Substrate for stacked module and stacked module
Inventor: KYOUGOKU YOSHITAKA
IPC: H01L25/065
Filed: 1998-10-19
Granted: 2000-09-11
Abstract: Substrates 1, 2 include chip select electrode pads B1, B2, C1, C2, and first chip select electrode pads B1, C1 are connected to chip select terminals of semiconductor chips 3, 4. The other chip select electrodes B2, C2 are connected to opposite surface side electrodes B1', C1' positioned on the opposite surface side of the chip select electrodes B1, C1 adjacent in the direction of the first chip select electrodes. The opposite surface side electrode B1' and the chip select electrode C1 of the substrate confronted therewith are connected to each other by a conductive bump 6. Thus, the substrates 1, 2 have the same structure.
Patent TW-396605-B (TW)
Title: Manufacturing method of metal capacitor constrcuture
Inventor: LI JIN-YUAN
IPC: H01L27/10
Filed: 1998-10-27
Granted: 2000-07-01
Abstract: This is a metal capacitor structure suitable for the semiconductor chip with dynamic random access memory (DRAM) and logic device. The metal capacitor structure process includes a transistor on the semiconductor substrate. The first plug, which is in contact with the respective source/drain regions, is formed in the store structure region and the bit line region. The first interconnect wire contacting the first plug is formed in the store structure region and the bit line region. Then, the multiple layer plug and interconnect wire processes are performed in the store structure region. The interlayer connective wire and the plug in each layer serves as the store nodes for the metal capacitor structure. Finally, the capacitor isolation layer and metal plates manufacturing finishes the metal capacitor structure.
Patent TW-460613-B (TW)
Title: Tin alloy plating compositions
Inventor: MOON SUNG-SOO
IPC: C25D7/00
Filed: 1998-10-29
Granted: 2001-10-21
Abstract: A tin-based, two-component alloy electroplating composition comprising 20 to 500 g/l of a tin salt, 1 to 100 g/l of a metal salt selected from the group consisting of a zinc, cobalt, bismuth and copper salt, 20 to 200 g/l of methanesulfonic acid, 10 to 300 g/l of a conductive compound, and 0.5 to 50 g/l of a complexing agent provides a plating layer having excellent corrosion resistance and solderability to electronic devices such as lead frames, connectors and printed circuit boards.
Patent TW-390985-B (TW)
Title: Semiconductor system having a master device and a slave device
Inventor: CHOI JAE-MYOUNG
IPC: G06F3/00
Filed: 1998-11-21
Granted: 2000-05-21
Abstract: A semiconductor system having a master device and a slave device. The master device and the slave device are coupled together through the data bus and control signal line. The master device inputs a calibration signal to the slave device in response to the control signal. The voltage level of the data outputted from the slave device is corrected by the calibration operation.
Patent TW-401708-B (TW)
Title: Display device
Inventor: KUYAMA KAZUTO
IPC: H04N5/45
Filed: 1998-12-30
Granted: 2000-08-11
Abstract: The present invention is to provide a display device which can display image signals with multiple formats to a CRT display device in appropriate brightness and resolution without changing driving voltage. Anode voltages A' and B' corresponding to the respective video signals A and B are switched by a first switch (15) and supplied to an anode (2). Cut-off voltages A and B corresponding to the respective video signals A and B are switched by a second switch (12) and added to a video signal by an adder (6). In a CRT (1), the luminance rises in association with the step-down of the cut-off voltage and the step-up of the anode voltage and the resolution rises in association with the step-up of the cut-off voltage and the step-up of the anode voltage. The first and second switches (15, 12) are switched in accordance with the format of the input video signal respectively, thereby properly selecting the anode voltage which is applied to the CRT (1) and the cut-off voltage. The video image can be displayed by the CRT (1) at the luminance and resolution according to the video signal without changing the driving voltage.