Patent GB-931151-A (GB)
Title: Improvements in or relating to electric pulse storage and transfer circuits
Inventor: TRIDGELL RONALD HUGH
IPC: G11C19/04
Filed: 1958-05-16
Abstract: 931,151. Circuits employing bi-stable magnetic elements. POSTMASTER GENERAL. Aug. 5, 1959 [May 16, 1958], No. 15868/58. Class 40 (9). [Also in Group XIX] A pulse storage and transfer circuit comprises a core 1, as in Fig. 1, which is set over winding 1b and is reset over winding 1c to produce an output in winding 1d which over rectifier MR3 charges capacitor C, an output gate T being enabled to discharge the capacitor when transfer is required. The gate T is a transistor enabled by short-circuiting lines X and Y. The rectifier MR3 may be replaced by the baseemitter path of a transistor. Circuits providing reset pulses followed by the connection of a low impedance across the lines XY are described, see Figs. 8 to 13 of which only Fig. 8 is shown. An input step function to capacitor C2 cuts off transistor T1 allowing capacitor C1 to charge and set core 1. When C2 is discharged T1 starts conducting again and discharges C1 to reset core 1 thus causing T3 to conduct and connect low impedance across lines XY. When core 1 is being set, winding 1b has high impedance and supplies a voltage across transistor T2 to provide a reset output DA. The input to T1 may involve a pulse lengthening circuit and be responsive to voltage spikes. The collector of T3 may be put in series with a feedback winding so that core 1 resets retractively. Fixed pattern register with automatic re-write.- As shown in Fig. 14 cores 0 to n which have been set over windings Ob to nb are reset over serially connected windings Oc to nc and each reset core charges its capacitor C from output windings Od to nd. When lines XY are shorted the charged capacitors C discharge over windings Oa, On to set the cores and provide outputs giving read-out of the register. Backward and forward stepping ring counter.- Fig. 15 shows a ring counter with stages O to n, discharge of the capacitors C associated with each core being made over transistors connected to lines YA or YS depending on whether leads X, YA, or X, YS are shorted by transistors T5, T6. To step a registration forward a pulse DA sets control core 10 and resets any set core O to n to charge the associated capacitor C. At the end of the pulse DA core 10 resets under bias on winding 10d which causes transistor T5 to short-circuit leads X and YA and causes capacitors C to discharge over transistors such as T7, T9, and T11 which set the next succeeding core. To step a registration backwards a pulse DS resets any set core O to n and sets a control core 11 which discharges capacitors C over transistors such as T8, T10, T12 which set the next preceding cores. Output from the nth stage may be made to set a further ring counter with control cores 12 and 13. Binary counter.-In Fig. 16 each of cores 21, 22, 23, 24 is connected as a pulse halving circuit to count the number of pulses DA applied to winding 21c of core 21. Each pulse DA is followed by a short-circuit across leads X, Y, and the first such short-circuit discharges capacitor C20 to set core 21. The next DA pulse resets 21 charging C21 over transistor T21. The next short-circuit of leads X, Y discharges C21 over MR21 which sets core 22 and through winding 21a prevents capacitor C20 from setting core 21. The next DA pulse is ineffective as core 21 is not set but the next short circuit of X, Y discharges C20 to set the core 21. The next DA pulse resets core 21 charging C21 and in the process resets core 22 over the collector of T21 and winding 22c. The next shortcircuit of X, Y has capacitors C20, C21 and C22, discharging at once so that only core 23 is set.