Patent GB-1063930-A (GB)
Title: Pulse signalling system
IPC: G11B20/14
Filed: 1965-12-13
Abstract: 1,063,930. Data storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 13, 1965 [Dec. 28, 1964], No. 52764/65. Heading G4C. [Also in Division H4] In a pulse signalling system, signal levels and also respective directions of transistion from one signal level to another are each representative of a respective element of a data code. In a first embodiment, an additional transition takes place between two successive data times if necessary for the correct level or transition at the second of the two times. In a second embodiment, a clocking transition always takes place between two successive data times, and if necessary for the correct level or transition at the second time, a further transition follows it. It is mentioned that the further transition may precede the clocking transition. The signals are described as being recorded on a magnetic drum, disc, tape or card, but application to radio signalling systems employing pulse code modulation is also mentioned. First embodiment (Figs. 2, 3, not shown).- Two binary data pulse trains using positive voltage for 1 and negative for 0 (S1 S2) are gated (15, 16) with the true and inverse versions respectively of a clock pulse train (square wave) which goes through one cycle per bit time. The gate outputs are ORed (18) to produce a pulse train in which negative and positive levels and negative and positive transitions respectively represent 00 (i.e. S1 is 0, S2 is 0), 11, 10, 01. This pulse train is recorded (23), and when reproduced (25) with effective differentiation, feeds positive and negative peak detectors (28, 27) the outputs of which are ORed to synchronize a clock generator (38) producing two pulses per bit time to switch a trigger (42) which enables three AND gates (34, 35, 36) to recognize the states representing 10, 01, 11 respectively, non-recognition of any of these states implying 00 (though explicit recognition means for this may be provided). The AND gates for 10 and 01 (34, 35) simply receive the outputs of the negative and positive peak detectors (27, 28) respectively. The AND gate for 11 (36) receives the clock pulses (38) delayed by 3/ 8 of a bit time (44) and the set output of a trigger (30) set through a 1/4 bit time delay (32) by the positive peak detector (28) and reset by the negative peak detector (27). The outputs of the AND gates (34, 35, 36), the first two after delay by # bit time (46, 47) are passed to OR gates (50, 51) to reconstitute the original binary pulse trains (S1, S2) on respective lines. Second embodiment (Figs. 4, 5, not shown).- A second binary data pulse train (S2) and its inverse (61) are gated (63, 64) with clock pulses (one per bit time) to feed respective 2/ 3  bit time delays (66, 67) the outputs of which gate (69, 70) a first binary data pulse train (S1) and its inverse (60) respectively, to an OR gate (79). The output of the OR gate (79) switches a recording trigger (81). The OR gate (79) also receives firstly the clock pulses delayed by 1/ 3  bit time (73), to provide the clocking transitions, and secondly the result of gating (75) with the clock pulses the exclusive-or (77) of the two data pulse trains (S1, S2), to provide the further transition. The recorded data, when reproduced (50) with effective differentiation is further differentiated (83) then feeds an inverter (87) via an overdriven amplifier (85), thus reconstituting the recording trigger output (81). The inverter (87) output feeds positive nd negative transistion detectors (89, 90) and a 1/ 2  bit time delay (97). The transistion detector (89, 90) outputs are ORed (92) to trigger a single shot (94) having a period of 5/ 6  bit time, the output of which is inverted (95) and delayed by 1/ 12  bit time (96) before being used to enable three AND gates (100, 101, 102) which reconstitute the original second and first data pulse trains (S2, S1) and clock respectively. The first AND gate (100) is fed by the negative transition detector (90), the second(101) by the 1/ 2  bit time delay (97) and the OR gate (92), and the third (102) by the OR gate (92). The single shot (94) will lock into synchronism with the clocking transitions but this may be facilitated by preceding the message with a sequence of clock transitions. Other features.-Data may be read from the record, as above, one component train (S1 or S2) revised, and the two recombined and rerecorded in the same pass, using separate read and write heads. A plurality of parallel channels, each as above, may be provided on the record.