Patent GB-777839-A (GB)
Title: Dividers for electrical digital computing engines
Inventor: CLAYDEN DAVID OSWALD
IPC: G06F7/52
Filed: 1954-05-19
Abstract: 777,839. Digital electric calculating apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Aug. 16, 1955 [May 19,1954], No. 14664/54. Class 106 (1). [Also in Group XL(c)] An electrical binary series-mode divider comprises a first store having a capacity of two words and a circulation path including an adder/subtracter and, during division, a unit delay and a gate which removes any pulse in the highest orders of the two words stored, these being (a) the dividend and then the changing remainder and (b) the quotient as it is built up, a sign-comparing circuit, and a second store arranged to feed the divisor in synchronism with the remainder to the adder/subtracter and to the sign comparing circuit, which so controls the former that the divisor is added to the remainder when the signs are different and subtracted from it when the signs are the same and which causes a unit to be added to the quotient each time the divisor is subtracted. The unit delay referred to produces a column shift of the remainder and quotient at each stage of the division. Although a unit is added to the quotient when the divisor is subtracted a unit is not subtracted from the quotient when the divisor is added and consequently after a complete quotient (in this case of 32 digits) has been built up (in this case after 64 minor cycles), that quotient is incorrect. However, it is shown that a further column shift of the quotient and the discarding of the highest order digit produces a corrected value and thus correction is achieved during a further minor cycle of the division operation. It is also shown that, even after such correction, where an exact quotient is possible, the value found is one less than the true value when the divisor is negative, and in the case of inexact quotients, the values found are always algebraically lower than the true values. The machine may be programmed to produce balanced errors. A calculation for correcting the remainder obtained after a division is also given. In a preferred embodiment, Fig. 2, the first store DLS is a mercury delay line which for 32-digit words is in fact only 63 digits long, the remaining unit delay being produced by a <SP>1</SP>/ 6  delay 36, a widener 38 which widens the pulses from <SP>1</SP>/ 3  to 1 microsec. (the digit period) as described in Specification 718,901 and consequently effectively delays them by <SP>1</SP>/ 3  period, and a <SP>1</SP>/ 2  delay 40. Under the control of a DIV signal, the column-shifting unit delay 10 is placed in the circulation path and the highest order digits of the remainder and quotient are deleted prior to the delay 10 by wide P1 pulses applied to a gate 32. The divisor is stored in a single word mercury delay line SLS and its pulses are widened at 12 and applied to the sign-comparing circuit 6 and, through a gate 18 opened during odd division minor cycles (i.e. when the remainder passes through the adder 4) by control pulses DIV and ODD, to the adder 4. Delays 14, and 20 and 26, synchronize the divisor with the remainder. The divisor and remainder pulse trains (delayed one period) are applied in the sign comparing circuit 6, to a non-equivalent gate 42 which at every even minor cycle P1 period (i.e. when the sign digits are applied to the gate 42) controls, through gates 44, 46, a trigger Z so as to put it on or off if the signs are the same or different respectively. The trigger Z, when on during division, opens a gate 54 to admit an even P1 pulse so as to add one to the quotient and causes subtraction of the divisor, as described in Specification 700,007, by negating the divisor at 22 and causing at 50 the addition of a unit in the adder 4. Division is started by the application of an even P28 pulse to a trigger DIV, Fig. 4, the output of which provides the control signals DIV, Fig. 2. This trigger through a beginning element 60 puts on a trigger L which at 62 gates not the next, but all of the following, odd P1 pulses to a modulus 32 " counter " or pulse frequency-divider 64 (see Group XL(c)). This, after 64 minor cycles, resets the trigger L which then permits the next even P1 pulse to reset the trigger DIV. Specification 717,114 also is referred to.