Patent GB-1446569-A (GB)
IPC: G06F7/00
Filed: 1973-11-21
Abstract: 1446569 Data processing HONEYWELL INFORMATION SYSTEMS Inc 21 Nov 1973 [11 Jan 1973] 54127/73 Heading G4A A digital data processing system includes a main memory and two data processors, the first being coupled to the memory for fetching the stored programme instructions and data and processing numerical data of a first type and the second being coupled to the first processor and processing data of the second type (for example floating point data), there being overlapping of execution of instructions relating to processing data of the first and second types. As well as the first central processor unit (300, Fig. 1, not shown), the second scientific processing unit (500) and memory system (100) the system includes an input/output controller (200) and a system console (400) on which operator commands may be fed in. Input/output controller.-This co-ordinates exchanges between peripherals, e.g. card reader, punch, magnetic tape, printer and disc and drum store and the memory system and comprises (1) a control section (200-10, Fig. 2, not shown) (having an input/output cycle counter (200-12) and storage registers for storing control characters, flip-flops being set in accordance with the required peripheral command), (2) a control memory section (200-30) (including a counter status control memory (200-31) (indicating the active status of read/write storage location in the central processor unit, a time slot status memory (200-34) and a control word control memory (200-40) supplying signals to the central processor unit control memory) and (3) a buffer section (200-50) (including a buffer storage memory (200-52) which may be bypassed, characters being transferred directly between sector bus lines and a memory input/ output register (200-75)). Central processor unit.-This transmits to and receives from the memory groups of four data characters (one from each memory section (M1- M4, Fig. 3, not shown) using input/output register (301) which is coupled to control section (302) and an ALU section (305). A solid state control memory (304-1) includes 64 locations storing addresses and data pertinent to input/ output data transfer instructions and non- scientific instructions, the memory being addressable under the control of the control section (302) either from the console (400) or from within the central processor unit to read out its contents via register (304-3) to memory address register (110) or to a temporary storage register (304-4) where the content may be modified before being read back. The control section (302) decodes in decoder circuits the contents of OP code register (302-1), OP code modifier register (302-2) and a character storage register (302-3) to generate a sequence of sub-command signals to perform the specified instruction. The contents of these registers may also be fed via multiplexer circuit (306) to the scientific processing unit. The multiplexer comprises four 6-bit sections each capable of multiplexing from four sources. The OP code decoder circuits determine whether an instruction being processed is a scientific instruction and whether the central processor unit can overlap the processing of that instruction with the subsequent instruction. Overlap class X specifies a registerto-register transfer in the scientific processing unit and identifies a full overlap situation where the CPU begins processing the next instruction immediately after it has extracted a scientific instruction from the main memory (format FAA). Overlap class Y specifies memory to register transfer and identifies partial overlap (format FMA). Overlap class Z identifies a category of instructions with no overlap. Scientific processor unit.-This is used for processing data in floating point representation and comprises an input bus section for applying instruction and operand information signals to various registers, a control memory section (502, Figs. 5a, 5b, not shown), an exponent section (503), mantissa section (504) and cycle control and diagnostic section (501). The control memory section includes a memory (502-6) for storing accumulated information and intermediate results required during execution of floating point operation on 48 bit words (36 bit mantissa, 12 bit exponent) stored in two consecutive locations of the accumulator. All calculations affecting the exponent portion are effective in the exponent section (503) which comprises a register (503-2) receiving its initial inputs from the control memory (502-6) and the input data bus. During manipulation it may receive its input from an exponent adder (503-8) and a register (503-6). A further register 503-4 connected to the input of the adder (503-8) is also used for storing results. Similarly the mantissa section 504 performs all calculations involving the mantissa and includes 36 bit registers (504-1-504-3) and an adder (504-4), data being shiftable left or right, one or two positions, in one of the registers (504-1) and six positions in another of the registers (504-3). The control section includes an 8 bit register (501-2) loaded with signals representing the OP code of an instruction extracted from the CPU, the value of the lowest two bits being decoded to determine if a format FAA instruction or a format FMA instruction is being executed. Operation.-To perform an input/output operation the sequence counter contents are fed from control memory (304-1) to address register (110) for the main memory resulting in four characters being read into register (301). The contents of section (N4) of the register are fed to instruction register (302-1). The sequence counter is incremented and in the next cycle four characters are fetched and transferred to the ALU, the sequence counter again being incremented by four. In the next cycle control characters, indicating for example the direction of transfer, and the OP code for the next instruction are fetched. The control characters are forwarded to the input/output controller where they are stored in the control section and decoded. When instruction extraction is completed by the controller it sends a signal to the CPU which releases it from processing the input/ output instruction, this being continued by the controller. The next instruction, e.g. a scientific instruction, may then be extracted by the CPU, the OP code being held in the register (302-1) and decoded resulting in a signal being fed to the scientific processor unit. When this unit is ready the contents of register (302-3) and the OP code are transmitted to it for loading into registers (502-2, 503-2, 501-2). If a FMA format instruction is being processed if a memoryto-register transfer is to occur the central processing unit fetches the operand. During the next cycle the exponent and lower bits of the mantissa are fed to the scientific processing unit followed, in a subsequent cycle, by the higher bits of the mantissa after which the central processor unit is released to extract the next instruction whilst the scientific processor unit is executing the scientific instruction. If a FAA format instruction is being processed it is executed simultaneously with extraction of the next instruction. An operator may display part or all of the floating point number stored in one of the storage locations of the control memory of the scientific processing unit by placing the central processing unit in the stop mode and entering the address of the location using the console. The contents of the specified location are then fed via the central processing unit to the display panel.