baber/WOPTO huggingface dataset:
Patent TW-509586-B (TW)
Title: A connector structure
Inventor: LARWS PETER
IPC: A63G19/00
Filed: 2001-03-08
Granted: 2002-11-11
Abstract: Clamp connection for support structures, in particular for play purposes, comprising a multiplicity of inter-connectable connector joints (1) and tubes (3), which display undercut pegs (9) on the surfaces to be connected, whereby said pegs (9) are connected in form-locking manner by couplings (2). These couplings (2) consist of two hemispheric coupling halves (4) and (5) which comprise grooves (10) corresponding to pegs (9). According to the invention, the connector joints (1) may consist of two connector joint halves (11) and (12) comprising grooves (10) which correspond to the pegs (9), so that the connector joints (1) can be connected directly to each other in form-locking manner by hemispheric connector elements (6).
Patent TW-469318-B (TW)
Title: Shaping method of a decorative fire-proof metallic wall panel
Inventor: LI CHIOU-TING
IPC: E04B1/94
Filed: 2001-04-23
Granted: 2001-12-21
Abstract: This invention of a shaping method of a decorative fire-proof metallic wall panel mainly includes: (1) two flat slabs to be pressed by roller pressure through a shaping device, equipped with upside and downside rolling presser, into a wall slab and a horizontal U-shaped metallic slab; (2) to convey these two slabs by a conveyor with two routes connected respectively to tanks of synthetic spray foaming agent- one loaded with coagulant and another loaded with catalyst; (3) to jet the foaming agent into the space between the wall slab and the horizontal U-shaped metallic slab; (4) to press the wall slab and the horizontal U-shaped metallic slab through rollers to build an integral shaped body; (5) to cut the integral shaped body by cutter device according to expected fire-proof and heat-insulation wall panels.
Patent TW-583143-B (TW)
Title: Degradation method of dioxins
Inventor: HONDA KATSUHISA
IPC: B09B3/00
Filed: 2001-05-16
Granted: 2004-04-11
Abstract: To provide a method for simply performing the decomposition of dioxins contained in fly ash, soil or the like without forming toxic byproducts. The decomposition method, which decomposes or dechlrinates dioxins in an object to be treated by bringing dioxins contained in the object to be treated to a Grignard reagent state, consists of a dehydration process for removing moisture of the object to be treated containing dioxins, a mixing process for mixing a magnesium powder with the object to be treated obtained in the dehydration process, a heating process for heating the object to be treated at least at one point of time selected from points of time before, after and during the mixing process and an acceleration liquid adding process for adding an acceleration liquid, which generates reducing reaction, to dioxins held to the Grignard reagent state in the object to be treated obtained after the mixing process and the heating process.
Patent TW-513699-B (TW)
Title: Controller of dual redundant array of inexpensive disks
Inventor: WU BI-LIANG
IPC: G11B20/18
Filed: 2001-05-18
Granted: 2002-12-11
Abstract: The present invention relates to a controller of dual redundant array of inexpensive disks, which is connected between a host system and a disk array. An independent channel is established to implement the data synchronous mirroring operation among buffer areas of the disk array, so as to achieve the dual redundant function. Thus, under the consideration of both the cost and efficiency of the host system operated with the disk array, the data storage system is provided with a maximum performance.
Patent TW-I285295-B (TW)
Title: Illumination optimization in lithography
Inventor: SOCHA ROBERT JOHN
IPC: H01L21/027
Filed: 2001-05-21
Granted: 2007-08-11
Abstract: A method and apparatus for microlithography. The method and apparatus include optimizing illation modes based on characteristics of a specific mask pattern. The illumination is optimized by determining an appropriate illumination mode based on diffraction orders of the reticle, and the autocorrelation of the projection optic. By elimination of parts of the illumination pattern which have no influence on modulation, excess DC light can be reduced, thereby improving depth of focus. Optimization of mask patterns includes addition of sub-resolution features to reduce pitches and discretize the probability density function of the space width.
Patent TW-533680-B (TW)
Title: Semiconductor device
Inventor: YAHIRO KATSUMI
IPC: G11C11/4076
Filed: 2001-05-29
Granted: 2003-05-21
Abstract: A semiconductor device according to the invention is composed of a counter which outputs intermediate carry signals (CARRY 0, 1, 2) and the final carry signal (CARRY END) for determining the end of a delay output signal in a period starting from a delay pulse-generating trigger signal (DPT) and continuing for a predetermined time, and a delay circuit which outputs count up signals (COUNT UP) for counting up the counter on the basis of pulse signals generated in accordance with the intermediate carry signals and the DPT. According to the aforementioned semiconductor device, the delay output signal can be outputted without using an external clock signal.
Patent TW-I286642-B (TW)
Title: Thin film transistor for liquid crystal device and method of manufacturing the same
Inventor: KIM DONG-GYU
IPC: H01L21/77
Filed: 2001-06-07
Granted: 2007-09-11
Abstract: Disclosed is a thin film transistor for an LCD and manufacturing method thereof. The thin film transistor includes a gate wiring formed on a substrate to extend in a first direction. The substrate includes a display region and a pad region positioned outside the display region. A gate insulating film is formed on the gate wiring and the substrate. An active pattern is formed on the gate insulating film. A data wiring is formed to extend in a second direction perpendicular to the first direction on the gate wiring with a gate insulating film interposed between the gate wiring and the data wiring. An organic passivation film is formed on the data wiring and the gate insulating film. The organic passivation film is patterned such that the organic passivation film is less and less sloped as it travels to an edge where a via hole is being formed, to form an organic passivation film pattern. The gate insulating film is etched by using the organic passivation film pattern as a mask to form a first via hole for exposing the data wiring and a second via hole for exposing the gate wiring. An undercut placed beneath the organic passivation film pattern is removed. A pixel electrode is formed on the organic passivation film pattern and is connected to the data wiring through the first via hole on the data wiring. A pad electrode is formed on the organic passivation film pattern and is connected to the gate wiring through the second via hole. The gate insulating film is protruded inwardly relative to the organic passivation film pattern at a bottom edge of the second via hole.
Patent TW-521434-B (TW)
Title: Thin-film semiconductor device fabrication method
Inventor: MIYASAKA MITSUTOSHI
IPC: H01L29/786
Filed: 2001-06-12
Granted: 2003-02-21
Abstract: In the thin-film semiconductor device fabrication method according to the present invention, after forming an amorphous semiconductor film, the film is crystallized in the solid phase state, and then a portion of the semiconductor film is molten by irradiating it with a pulsed laser beam having an absorption coefficient in amorphous silicon that is greater than the absorption coefficient in polysilicon. Thereby, polycrystalline thin-film semiconductor devices having superior characteristics can be fabricated at a lower temperature.
Patent TW-584815-B (TW)
Title: Method for removing noise regions in a stereo 3D display system
Inventor: LI RUEN-RUNG
IPC: H04N13/00
Filed: 2001-09-13
Granted: 2004-04-21
Abstract: The present invention relates to removing noise regions in a stereo 3D display system. The stereo 3D image includes a left image and a right image. The present invention provides a method to remove the left and right noise regions of the stereo 3D image by calculating a maximum offset value and tuning a horizontal synchronization signal and a display enable signal of the CRT timing parameters.
Patent TW-512061-B (TW)
Title: Improved protection tampon and method of making
Inventor: AGYAPONG RAYMOND KUSI
IPC: A61F13/20
Filed: 2001-10-24
Granted: 2002-12-01
Abstract: A tampon showing improved leakage protection through improved expansion characteristics is disclosed. The tampons disclosed demonstrate these improved expansion characteristics particularly in the width dimension without introducing new drawbacks. Preferred tampons are described which are compressed to an initial size comparable to current tampons, but which expand to a width exceeding that achieved by current tampons. Such increased expansion is preferably accomplished without an increase in the total absorbency of the tampon. Tampons of various absorbencies are disclosed having increased total expansion in the width direction compared to current tampons. Additionally, tampons of various absorbencies which expand to a greater degree in the width direction under pressure are also disclosed. Tampons of various absorbencies which expand at a rate exceeding that achieved previously are also disclosed. Microwave conditioning of tampon pledgets following compression is disclosed as part of the tampon formation process.
Patent TW-574409-B (TW)
Title: Method for incorporating silicon into CVD metal films
Inventor: HILLMAN JOSEPH T
IPC: C23C16/08
Filed: 2001-11-13
Granted: 2004-02-01
Abstract: A semiconductor device including a silicon-based substrate with recessed features and a tantalum barrier film having at least about 5% silicon incorporated substantially uniformly throughout the film. The device may further include a tantalum barrier film having improved conformality and decreased halogen impurity content. A method for incorporating the silicon into the tantalum barrier layer includes depositing tantalum by PECVD and interrupting deposition at least once to treat the deposited tantalum with a silane containing plasma.
Patent TW-510020-B (TW)
Title: Manufacture method of dual damascene structure
Inventor: HUANG YI-SHIUNG
IPC: H01L21/768
Filed: 2001-11-26
Granted: 2002-11-11
Abstract: This invention provides a manufacture method of dual damascene structure, which consists of following steps: firstly, forming a first dielectric layer, a second dielectric layer and a bottom anti-reflection coating (BARC) layer and a spin-on dielectric layer sequentially on a substrate with wiring formed thereon; then, defining the spin-on dielectric layer, the BARC layer and the second dielectric layer to form a hole in the second dielectric layer; forming a first trench in the spin-on dielectric layer and the BARC layer; removing the first dielectric layer exposed by the hole using the spin-on dielectric layer and the BARC layer as masks to form a via opening for exposing the substrate and concurrently removing the second dielectric layer exposed by the first trench to form a second trench exposing the first dielectric layer; removing the spin-on dielectric layer and the BARC layer; and sequentially forming a conformal barrier layer and a conductor layer in the second trench and the via opening, in which the conductor layer fully fills the second trench and the via opening.
Patent TW-508765-B (TW)
Title: Method of forming a system on chip
Inventor: LAI ERH-KUN
IPC: H01L21/8234
Filed: 2001-12-06
Granted: 2002-11-01
Abstract: An ONO dielectric layer is formed on the surface of a substrate, and then a plurality of bit lines are formed in the substrate by utilizing a photolithography and an ion implantation process. Thereafter the ONO dielectric layer in the periphery area is removed and the threshold voltage of the periphery transistor is adjusted. After the ONO dielectric layer in the read only memory area is removed, and a buried drain oxide layer and a plurality of gate oxide layers are formed atop each bit line and the surface of each device respectively. Then each word line in the memory area and each gate of each periphery transistor in the periphery area is formed so as to simultaneously form at least a nitride read only memory in the nitride read only memory area and a high, low threshold voltage device in the read only memory area. Finally the threshold voltage of the high threshold voltage device is adjusted by utilizing a ROM code implantation process.
Patent TW-564219-B (TW)
Title: System and method for producing composite or bonded metal components
Inventor: GRAHAM NEIL
IPC: B29C70/54
Filed: 2002-01-25
Granted: 2003-12-01
Abstract: System and method for producing composite or bonded metal components including: first and second pressure chambers, each pressure chamber having an elastically deformable chamber wall; means for circulating fluid at an elevated temperature and pressure through each said pressure chamber; and at least one mould assembly including at least one separate mould section providing a mould cavity within which a composite or bonded metal lay-up can be located; wherein when the system is in use, the pressure chambers are held together with the elastically deformable chamber walls located in opposing relation, the at least one mould assembly containing a said lay-up being accommodated between the chamber walls while fluid at elevated temperature and pressure is circulated through each pressure chamber such that the lay-up can be compressed and cured or formed.
Patent TW-541282-B (TW)
Title: Method of fabricating a module for at least partially intercepting a light beam propagating along a beam path, and method of fabricating device on substrate
Inventor: CHIU CHEN-WEI
IPC: B81B3/00
Filed: 2002-04-19
Granted: 2003-07-11
Abstract: A method for fabricating a module for at least partially intercepting a light beam propagating along a beam path includes providing a single crystal silicon substrate with a first substrate surface and a second substrate surface. The method further includes forming a reflector support layer on the first substrate surface. The method further includes forming a support frame and at least one reflector by etching the substrate from the second substrate surface. The method further includes forming at least one electrical conduit on the reflector support layer. The method further includes forming a reflector support by etching the reflector support layer from the first substrate surface, the reflector support mechanically coupled to the support frame and the reflector, the reflector support movable such that the reflector is movable substantially perpendicularly to the first substrate surface.
Patent TW-546736-B (TW)
Title: Structure of AlCu pad and method for manufacturing the same
Inventor: SU YEA-ZAN
IPC: H01L21/3105
Filed: 2002-06-17
Granted: 2003-08-11
Abstract: A structure of an AlCu pad and a method for manufacturing the same are disclosed. In the present method, a spacer made of dielectric materials is formed on the sidewalls of the AlCu pad ring after the AlCu pad is patterned. With the spacer on the sidewalls of the pad ring, it can avoid the pad from distortion and scratch during the transportation of wafers.
Patent TW-583665-B (TW)
Title: Thin film magnetic memory device
Inventor: HIDAKA HIDETO
IPC: H01L21/8246
Filed: 2002-06-26
Granted: 2004-04-11
Abstract: Two complementary bit lines corresponding to a selected column are pulled down to a ground voltage via each of a selected MTJ memory cell and a dummy memory cell and are pulled up to a power supply voltage via a read drive selection gate. A read gate corresponding to the selected column drives the voltages of two complementary read data buses by driving force according to the voltage of corresponding complementary two bit lines, respectively. A data reading circuit executes data reading operation on the basis of a voltage difference between the complementary two read data buses. The power supply voltage is determined in consideration of reliability of a tunneling insulating film of an MTJ memory cell.
Patent TW-536451-B (TW)
Title: Polishing composition and polishing method employing it
Inventor: OHNO KOJI
IPC: B24B37/00
Filed: 2002-07-30
Granted: 2003-06-11
Abstract: A polishing composition for polishing a semiconductor device having at least a tungsten film and an insulating film, which comprises the following components (a) to (d): (a) silicon dioxide, (b) periodic acid, (c) at least one pH controlling agent selected from the group consisting of ammonia, potassium hydroxide, sodium hydroxide, ammonium periodate, potassium periodate and sodium periodate, and (d) water.
Patent TW-550742-B (TW)
Title: Method for forming a bottle-shaped trench
Inventor: LIN SHIUAN-JR
IPC: H01L21/764
Filed: 2002-09-27
Granted: 2003-09-01
Abstract: The invention provides a method for forming a bottle-shaped trench, used for a semiconductor substrate formed with a pad stack layer on the surface of the substrate and a trench in a predetermined position. The method comprises the steps of: forming a first dielectric layer conformally on the pad stack layer and the sidewalls of the trench; filling the lower portion of the trench with a sacrificial layer; removing the first dielectric layer on the pad stack layer and the upper sidewall of the trench; removing the sacrificial layer and leaving behind the first dielectric layer located on the lower sidewalls of the trench; forming a second dielectric layer conformally on the pad stack layer, the upper sidewalls of the trench to completely cover the first dielectric layer; forming a protection layer conformally on the second dielectric layer; recessing the protection layer and leaving behind the protection layer located on the upper sidewalls of the trench to form a sidewall protection layer; removing the second dielectric layer located at the bottom of the trench to form an opening; using the sidewall protection layer as a mask to remove the first dielectric layer and the second dielectric layer located at the lower portion of the trench to expose the lower sidewalls of the trench; and wet stripping the lower sidewalls of the trench to form a bottle-shaped trench.
Patent TW-I226036-B (TW)
Title: Disc data storage apparatus with structure for preventing crack disc from being jetted out
Inventor: HUANG CHIU-AN
IPC: G11B17/04
Filed: 2002-10-25
Granted: 2005-01-01
Abstract: The present invention relates to a disc data storage apparatus with structure for preventing crack disc being jetted out. The disc data storage apparatus has a tray for holding a disc, a panel and a housing. The panel has an upper portion, a bottom portion, and a barrier portion. The barrier portion is extended inward from the bottom portion. When the disc cracks, the barrier portion is configured to stop the crack disc being jetted out.
Patent TW-I227127-B (TW)
Title: Method and apparatus for making on-line stabilized absorbent materials
Inventor: RYMER TIMOTHY JAMES
IPC: A61F13/15
Filed: 2002-11-19
Granted: 2005-02-01
Abstract: A method for forming a stabilized airlaid layer (86) can include an airforming of a substantially unbonded fibrous layer (66) which includes absorbent fibers and binder-fibers. The fibrous layer (66) is exposed to high-frequency electromagnetic energy during a distinctively short activation period to activate the binder-fibers to provide the stabilized, airlaid layer (86). In a particular aspect the activation period can be not more than about 3 sec.
Patent TW-I248994-B (TW)
Title: Machine-crimped synthetic fibers having latent three-dimensional crimping property and process for producing same
Inventor: GODA HIRONORI
IPC: D02G1/18
Filed: 2002-11-29
Granted: 2006-02-11
Abstract: The machine-crimped synthetic fibers of the present invention have a thickness of individual fibers of 0.5 to 200 dtex, a fiber length of 3 to 20 mm and the number of crimps of 1 to 13 crimps/25 mm and a crimp percentage of 2 to 20% of the individual fibers each fiber having two portions disproportional in thermal shrinkage with each other and located in two sides of the fiber divided by an imaginary interface by which the fiber is imaginarily divided along the longitudinal axis of the fiber into two side portions, to cause the fiber to have such a latent crimping property that when heat treated at a temperature of 60 to 200 DEG C, the two side portions of the fiber disproportionally shrink and the shrunk fiber exhibits three-dimensional crimps having the number of crimps of 15 to 80 crimp/25 mm and a crimp percentage of 25 to 90%. The fibers are produced by disproportionally cool-solidifying in fiber-forming procedure or by forming in an eccentric core-in-sheath type on side-by-side type composite fiber structure.
Patent TW-567396-B (TW)
Title: Method for fabricating mask pattern, computer program product, method for manufacturing photomask, and method for manufacturing semiconductor device
Inventor: TANAKA SATOSHI
IPC: G03F1/68
Filed: 2002-12-04
Granted: 2003-12-21
Abstract: The present invention is related to the method of forming mask pattern, which contains the following steps: preparation of designing mask pattern; using rough correction treatment to obtain rough correction mask pattern from the designed mask pattern; and conducting strict correction treatment through the use of strict mode of transferring image of the simulated exposure apparatus to set the correction method, so as to obtain the accurate correction mask pattern from the rough correction mask pattern.
Patent TW-I264039-B (TW)
Title: Fed cathode structure using electrophoretic deposition and method of fabrication
Inventor: TALIN ALBERT ALEC
IPC: H01J29/04
Filed: 2002-12-17
Granted: 2006-10-11
Abstract: A method of fabricating a field emission device cathode (50) using electrophoretic deposition of carbon nanotubes in which a separate step of depositing a binder material (22) onto a substrate (18), is performed prior to carbon nanotube particle (36) deposition. First, a binder layer is deposited on a substrate from a solution containing a binder material. The substrate having the binder material deposited thereon is then transferred into a carbon nanotube suspension bath allowing for coating of the carbon nanotube particles onto the substrate. Thermal processing of the coating transforms the binder layer properties which provides for the adhesion of the carbon nanotube particles to the binder material.
Patent TW-I264072-B (TW)
Title: Wafer temperature compensator having reflector
Inventor: LEE TAE-WAN
IPC: H01L21/20
Filed: 2002-12-25
Granted: 2006-10-11
Abstract: An apparatus for manufacturing a semiconductor device having a process chamber comprises a lower process chamber wall, a quartz dome over the lower process chamber wall, a pumping mean for making an interior of the process chamber vacuous, a bell-jar over the quartz dome, a bell-jar heater built in a side of the bell-jar, a susceptor on which a wafer is loaded, a susceptor heater built in the susceptor, and a wafer temperature compensator having a reflector plate and supporting elements, the reflector plate being spaced apart a certain distance from the wafer and having a larger area than that of the wafer, the supporting elements being connected to the wafer and supporting edges of a bottom surface of the wafer.