Patent GB-1510529-A (GB)
Title: Digital signal recorders
IPC: G11B20/14
Filed: 1975-09-25
Abstract: 1510529 Digital data recording and playback INTERNATIONAL BUSINESS MACHINES CORP 25 Sept 1975 [23 Dec 1974] 39211/75 Heading G4C Digitial data segments 15, 16, 17, &c, Fig. 1, recorded on a medium 10 such as magnetic tape, are interleaved with resynchronization segments 12, 13, &c. used to resynchronize a readback clock for deskviewing during playback, the medium 10 having a plurality of tracks recorded thereon and the resynchronization segments being of two different types, termed even (E) and odd (O), which alternate along the medium 10, the two different types of resynchronization segments allowing different selections of the tracks to be resynchronized. As described each data segment comprises 236 nine-bit bytes (eight bits plus a parity bit). and each resynchronization segment comprises 20 nine-bit bytes, each resynchronization segment byte being a valid data byte. Resynchronization of a track is achieved by sensing in the respective track in the resynchronization segment a long series, e.g. 18, of O's, followed by a single 1; in phase-encoded recording this single 1 is represented by a long wavelength which is used to resynchronize the readback clock. Since odd parity is used in phase-encoded recording, all of the nine tracks of a resynchronization segment cannot have such series of O's followed by single I's, and so cannot be resynchronized at once. Resynchronization is thereby achieved by resynchronizing an even number of tracks, e.g. eight or six the remaining track or tracks which are not resynchronized having all I's and being termed identifying tracks; such identifying tracks are however resynchronized every second resynchronization segment since the identifying tracks differ in the even and odd resynchronization segments. Two different embodiments are described. In each embodiment tracks are numbered from one edge 4, 6, 0, 1, 2, 8 (parity), 3, 7 and 5. Asymmetrical resynchronization, Figs. 2A, 2B (not shown), 4.-Eight tracks are resynchronized in each resynchronization segment, the identi. fying track being 8 (parity) for even segments and 2 for odd segments. A byte counter 143A, Fig. 4, counts the number of bytes exchanged with a record circuit 40, a count of 0-235 (data exchange) enabling a gate 43 to request the next data byte. A count of 236 (start of a resynchronization segment) enables a gate 51 to write all 0's into all tracks except 8 (parity) and 2, a 1 being written into either track 8 (parity) or track 2 by gates 52, 53 according to the state of an even-odd counter 58 which changes state every 256 bytes (one data segment plus one resynchronization segment). The same process as that for a count of 236 is carried out for a count of 237-254 by gates 52, 53, and finally a count of 255 enables a gate 50 to write all 1's as the last resynchronization segment byte. Symmetrical resynchronization, Fig. 4A (not shown), 3.-Six tracks are resynchronized in each resynchronization segment, the identifying tracks being 1, 8 (parity) and 7 for even segments and 0, 2 and 3 for odd segments. Writing of the resynchronization segments employs gates (50A-53A), Fig. 4A (not shown), corresponding to gates 50-53 of Fig. 4 but having differently-connected outputs feeding the record circuit 40. In this embodiment byte 0 of each resynchronization segment is an all 1's byte, which enables reading of the tape in either direction. This arrangement employing three identifying tracks in each resynchronization segment is stated to reduce the chance of loss of resynchronization owing to a single identifying track (as in Figs. 2A, 2B (not shown)) being faulty (or "deadtracked")' To this end a majority logic unit (75), Fig. 5 (not shown) may be employed in the Fig. 4A (not shown), 3 embodiment to sense whether, in an odd segment, tracks 1, 8 (parity), 7, 0, 2 and 3 are not deadtracked and whether tracks 1, 8 (parity), 7 have all 0's and tracks 0, 2 and 3 have all 1's. If four or more of these six tracks are verified, majority logic unit (75) resets deadtrack latches which have been set for those tracks of the resynchronization segments having all 1's, i.e. the identifying tracks, prior to the first data byte of the next data segment. A similar verification is applied to the even segments. The circuit of Fig. 5 (not shown) is also used in reading backwards to identify whether an even or an odd resynchronization segment has been detected, by sensing whether all 0's or all 1's are present on the appropriate identifying tracks. In both embodiments the outermost tracks 4 and 5 are never used as identifying tracks, tracks 4 and 5 being the least reliable and being resynchronized every resynchronization segment. As each resynchronization segment byte is a valid data byte, a resynchronizable tape may be recorded by a recorder not having separate resynchronizing read/write circuits. A resynchronizable tape may also be replayed on such a recorder by recognizing and detecting the resynchronization segments prior to utilizing the read-out data segments.