Patent GB-871331-A (GB)
Title: Digital phase-shift modulator
IPC: H04L5/12
Filed: 1957-07-22
Abstract: 871,331. Multiplex transmission systems. COLLINS RADIO CO. July 22, 1957 [Dec. 5, 1956], No. 23162/57. Class 40 (4). [Also in Group XL (b)] A generator, the phase of whose output can be shifted by discrete amounts, consists of a pulse generator of frequency equal to a multiple of the required output frequency, a counter circuit for counting pulses from said generator and in accordance therewith subdividing the pulse repetition frequency so as to produce an output of the desired frequency, and means for interfering with the operation of the counter to produce the desired phase shift. Thus, to produce a lag, one or more of the pulses fed to the counter is suppressed and to produce a lead one or more pulses are fed to the counter in such a way that each pulse steps the counter on two. The invention is described in connection with a twinplex telegraph system in which the four combinations of mark and space on the two channels are required respectively to advance the phase by 45 and 135 degrees and to retard the phase by 45 and 135 degrees the phase of the signal in the previous signalling condition being taken as the datum condition. As shown an oscillator 23 having a frequency of eight times the output frequency feeds a pulse forming circuit 26 whose output is fed via gate 27 to a counter 50 consisting of three bi-stable state circuits 51, 52, 53 forming a ¸ 8 circuit, so that the last stage produces a square wave output of the desired frequency which is converted to a sinusoidal output by the low-pass filter 29. To produce a phase lag of 45 or 135 degrees, one or three pulses are deleted by the closing of the gate 27. To produce a phase advance of 45 or 135 degrees one or three pulses are fed into stage 52 of the counter which is thus advanced one or three counts as compared with its state if the pulses had been fed into stage 51. Determination of the number of pulses to be added or subtracted is in accordance with the mark or space condition of channel 2. Thus a two-stage binary counter 37 is reset by pulse 38 synchronous with the mark/space periods. If the voltages on the various wires are b or a, then gates 58, 61, 63 are " or " gates and 59 is an " and " gate for the b condition. A " mark " on channel 2 corresponds to a b condition on lead 34 and an a condition on lead 35 and vice versa. Thus inverter 62 always has an a output, so that the output from gate 63 is always that of counter stage 56, which is a when the counter is unoperated. Thus gate 59 emits an a condition at this time which closes gate 27 and opens gate 28 to permit pulses to pass to the counter 37. If channel 2 is at " mark " gate 58 emits a b condition and, after one pulse, counter stage 56 also emits a b condition and therefore gate 59 emits a b condition to reopen gate 27 and close gate 28. If, however, channel 2 is at " space " gate 58 will not emit a b condition until counter stage 57 is set, i.e. after two pulses, and gate 63 will not emit a b condition until counter 56 is again set, i.e. after the third pulse. Gate 59 therefore cannot close 28 and open 27 until after three pulses. If channel 1 is at " space " at this time gate 55 is closed and a simple deletion of the appropriate number of pulses occurs at gate 27 to produce a phase lag. If, however, channel 1 is at " mark " gate 55 is open and the appropriate number of pulses is fed to stage 52 of counter 50 to produce an advance in phase. Single channel working.-The circuit is arranged so that if channel 2 is disconnected then mark and space in channel I produce 90 degrees lead and lag respectively. Thus with no input from channel 2 inverter 62 emits a permanent b condition, so that the lower input to gate 59 is a permanent b. Thus gate 59 emits an a condition for two pulses only whereupon the stage 57 emits a b condition, so that gate 59 also emits a b condition to stop the count. Thus in the case of a space two pulses are suppressed in gate 27 and in the case of a mark two pulses are fed to stage 52 thus causing a lag or lead of 90 degrees. In a further embodiment the requisite conditions are produced by deleting 1, 3, 5 or 7 pulses from the input to the counter 50 to cause lags of 45, 135, 225 or 315 degrees. Specification 828,782 is referred to.