Patent GB-1253302-A (GB)
Title: Electrical character recognition systems
Inventor: KIJI KAZUO
IPC: G06V30/10
Filed: 1969-03-10
Abstract: 1,253,302. Character recognition. NIPPON ELECTRIC CO. Ltd. 10 March. 1969. No. 12593/69. Heading G4R. A character recognition system extracts features in dependence on a count of the number of storage positions between corresponding state transitions in successive rows of a matrix store holding digitized character signals from a scanner. When a character has been scanned 1 (Fig. 2), digitized 2 and reconstituted in a matrix store 3, a signal RECP causes a generator 400 to produce a series of pulses P1 ... P15 repeated once for each row of the matrix. The pulses P1-P14 control diode matrices 50, 51 to scan the bottom row of the matrix 3 from the left and right respectively, the character signals being passed from matrices 50, 51 via OR's 53, 54 to differentiators 55, 56. Pulses P15 each shift matrix 3 down one row. Flip-flops 57, 553, 563, 566 are set from the differentiators at the first white to black transition going from the left, the first black to white from the left, the first black to white from the right, and the first white to black from the right respectively (signals LL, LR, RL, RR respectively). Pulses P15 gate the state of flip-flop 57 into flip-flop 69 and, delayed at 63, reset flip-flops 57, 553, 563, 566. Blocks 70, 71, 72, 73 receive signals LL, LR, RL, RR respectively. Considering block 70 which is typical, a counter 74 counts the pulses P1-P14, supplied via OR 66. Counts of 11, 14, 18, if reached, set respective flip-flops 75, 76, 77. A signal LL resets counter 74 and these flip-flops, but before doing this and provided flip-flop 69 is set, causes a diode matrix 83 (AND's) to set one of flip-flops 78, 79, 80, 81 according to the range in which the count at 74 lay just before resetting, as indicated by flip-flops 75, 76, 77. This count (block 70) gives a measure of the relative horizontal position of the left edge of the leftmost character stroke in two adjacent rows of matrix 3. The corresponding outputs from blocks 71, 72, 73 relate similarly to the right edge of the leftmost stroke and the left and right edges of the rightmost stroke. Flip-flops 78, 79, 80, 81 are reset by pulses P15, delayed at 63, 87. The output of differentiator 55 also feeds a stroke counter 90 (Fig. 3), the contents of which are gated out to shift registers 93, 94 by pulses P15, which delayed DP15 reset the counter. Gates 95, 96, 97, 98 respond to the shift registers to produce a signal when two adjacent rows of matrix 3 have 1 and 1, 2 and 1, 1 and 2, 2 and 2 character stroke intersections respectively. A matrix 10 in a feature recognition unit 8 responds to these signals and the outputs of blocks 70, 71, 72, 73 to recognize left and right displacements (going from one row of matrix 3 to the next) of the left and right edges of the character of 4 or more bit positions, the combination of leftward and rightward shifts of 4 or more bit positions at the left and right edges respectively, join, fork, stroke beginnings and ends to left and right of other strokes, respective feature signals going to sequential recognition logic 9. This logic also receives signals LDS, RDS, WS representing a leftward ascending stroke (diagonal), a rightward ascending stroke, and a pair of upwardlyextending strokes, produced when matrix 10 produces 3 at least of respective signals LDSE, RDSE, WSE, counted at 101, 102, 103, without other features intervening (counter resets via OR 107). A counter 901 counts pulses P15 to enable finalization of recognition at 9.