Patent SG-11201810017V-A (SG)
Title: Semiconductor die offset compensation variation
Inventor: COOTS CHARLES ANDREW
IPC: G06F17/50
Filed: 2017-06-02
Abstract: International Patent Classification: (71) Applicant: UNIVERSAL INSTRUMENTS CORPO- H01L 21/68 (2006.01) G06F 17/50 (2006.01) RATION [US/US]; 33 Broome Corporate Parkway, Con- G06F 13/10 (2006.01) H01L 21/66 (2006.01) klin, New York 13748 (US). G06F 17/30 (2006.01) H01L 21/67 (2006.01) (72) Inventors: COOTS, Charles Andrew; 1236 Cherese (21) International Application Number: PCT/US2017/035714 (22) International Filing Date: 02 June 2017 (02.06.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 62/344,820 02 June 2016 (02.06.2016) US Lane, Binghamton, New York 13905 (US). PICHURA, John Joseph; 100 Overlook Drive, Kirkwood, New York 13795 (US). FACTOUROVICH, Maxim; 43 San Marco Drive, Johnson City, New York 13790 (US). (74) Agent: OLSEN, Arlen L.; SCHMEISER, OLSEN & WATTS LLP, 22 Century Hill Drive, Suite 302, Latham, New York 12110 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, Circuitry/ Icgic 12 Controller 14 Memory Sy 8 Software Application 17 23.. Placement Hardware 19 (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 07 December 2017 (07.12.2017) WIPO I PCT (54) Title: SEMICONDUCTOR DIE OFFSET COMPENSATION VARIATION 104 omit VIII tun Hol olollm ioo mom° oimIE (10) International Publication Number WO 2017/210576 Al 100 Network 14 N O N _ N O N C FIG. 1 (57) : A method and system for improving an automated pick and place apparatus semiconductor device placement process is provided. The method includes automatically executing a shift measurement associated with an offset from an original placement of a plurality of semiconductor die of a semiconductor wafer for processing. An associated shift measurement value is retrieved and stored in a database that includes previously retrieved shift measurement values of previously measured shift measurements. Specified models are executed with respect to all shift measurement values and a predicted shift measurement value associated with a future offset for a new plurality of semiconductor die on a new semiconductor wafer for processing is determined. Placement hardware of the pick and place apparatus is placed in multiple positions for generating the new plurality of semiconductor die on the new semiconductor wafer in accordance with the predicted shift measurement value. [Continued on next page] WO 2017/210576 Al MIDEDIMOMOIDEIRMEM001101011EMEROMEMOIMIE HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))