Patent GB-904738-A (GB)
Title: Device for evaluating and testing telegraph signals of a binary code
IPC: H04L1/08
Filed: 1958-11-17
Abstract: 904,738. Printing-telegraph receiving arrangements. VIERLING, O. Nov. 17, 1958 [Nov. 16, 1957 (2); April 15, 1958; July 3, 1958; Aug. 21, 1958], No. 36978/58. Class 40 (3). In a device, for responding selectively to code combinations of pulses, including a counter having a number of stages equal to the number of code elements switched step-by-step through an input stage synchronously with the sequence of code elements, and in which each counter stage is associated with a two-condition storage stage in such manner that this stage is responsive to the incoming element sequence solely when the associated counter stage is in a switching condition different from that of the remaining stages of the counter, or is in a condition to permit sequentially the switching condition, the two-condition storage devices actuating electronic switches corresponding to the position of the code element within the signal combination, and forming a chain circuit branching in stages and arranged to provide a single output in respect of a code combination of elements, the arrangement includes an impulse-generating receiving stage, an input stage forming a start circuit for an impulse generator for the counter operation, and preferably incorporating a delaying stage for the counter operation, the counter chain via the electronic switches and the two-condition storage devices switching through the branching circuit to the final receiving member, and the counter chain is employed to perform solely the counting operation, with the storage devices formed separately, but operatively connected with the counter chain stages, or the counter chain branches in each stage and is combined with the two-condition storage devices which are connected in and form the individual branching paths of the chain circuit. The invention, which comprises modification of the arrangement described in Specification 855,363, is indicated diagrammatically in Fig. 1 (not shown), in which the input signals are applied to a start and control circuit effecting operation of the counter stages of the receiving system. In the input circuit, Fig. 2, a transistor TBO is changed over by the start element of a signal combination at the input U and controls a cadence circuit TB1 providing pulses in synchronism with the incoming signals, and rendering the transistor TBO non-responsive to incoming signals until the stop element has been received. Two included transistors TEO, TE changed over in succession by the first two pulses of the cadence circuit delay the application of biasing pulses for the significant code elements to the stages TE1 . . . TE3 of the counter chain which sequentially allow the incoming pulses to pass to the storage stages F1, F2 and F3, Fig. 3, controlling the chain K comprising transistors TK1 and TK2, TK11 . . . TK22, and TK111 . . . TK222-the latter members being connected to the final recording members RL1 . . . RL8, e.g. the printer magnets of a receiver. The positive pulses over F1 . . . F3 switch over the associated pairs of bi-stable devices (TF11, TF12), TF21, TF22), TF31, TF32 and form a selective branching path to the members RL1 . . . RL8. In a modified arrangement, Figs. 4 and 5, the successive code elements change over solely one transistor in each of the rows having progressively doubled numbers of transistors and the path to the final recording element is built up over one selected transistor for each row. Fig. 4 shows, for a 3-unit code, merely the half of the circuit which responds to an initial negative element which operates the first transistor TEK1 of two transistors responsive to the incoming elements. The switching over of the transistor TEK1 prepares a path for the next code element to transistors TEK11, TEK12, and if it is a positive element, TEK12 is switched over and prepares a path to transistors TL3, TL4, the latter being operated if the third element is positive, and energizing the final recording member RL4. The timing of the input pulses received at input J and passed to the input OI of Fig. 4 is controlled by the cadence circuit, Fig. 5, which is triggered by the start pulse, is rendered non-responsive to the code pulses, and provides timing pulses to allow the input pulses to pass over diode D1 and capacitor C1 to the input OI of Fig. 4. The initial or start pulse triggers transistor TB3 which switches transistor TB2 to form a delay circuit and to operate TB11 to allow successive code elements to pass to the input OI of Fig. 4. The circuits of the transistors TEK1, TEK11 . . . and TL1 . . . TL4 are restored to their initial states by a pulse when any of the final transistors has been operated. In an arrangement, Figs. 6 and 7, for eliminating or indicating the effects of disturbing currents, e.g. atmospherics, by the known Verdan method of signal repetition, the signal elements, assumed to be three in number, are applied via the input control circuit B and the counting stages E1 . . . E3 to the storage devices F1, F2, F3 and, when repeated, are similarly applied via circuit elements B, E11 . . . E13 to the storage devices F11 . . . F13. The corresponding signal elements are then compared in transistor circuits F21, F22, and F23 which can operate to pass the probable element, if one has been lost, selectively over sets of diodes D and D1, D2 . . . D5, D6 . . . D13, and to operate a circuit, if mutilation of one or more elements has occurred, to print the doubtful character in a colour different from normal printing. In the circuit arrangement, Fig. 7, the comparator circuit F21 is formed by two pairs of transistors TF211, TF212 and TF213, TF214 connected so that, for example, two positive pulses or two negative pulses correctly received, during the repeated transmission, operate a transistor TV1, connected to two transistors TP1, TP2 so that for a negative or a positive pulse from TV1, current flows in operating direction through a relay RD1. When disturbance has occurred, the current through TV1 may be halved, and the relay RD may be marginal and not operated by the reduced current, or two separate relays operated respectively by a current of full value and of half value. A modified error-indicating circuit is described in connection with Fig. 8 (not shown). A modified circuit arrangement, Figs. 9, 10 (not shown), for indicating or correcting signal elements disturbed in transmission employs an input circuit counter, and signal-storage circuits generally similar to those shown in Fig. 2, with a correction or error-detection stage, Fig. 10 (not shown), comprising two transistors which can be switched respectively by positive and negative elements of the received signal, and in the case of interference-free reception, the transistor which was switched by the first signal element is reversed by the repeated element to send the correct signal element to the associated storage device for the chain circuit. If a signal element in the first transmission fails or is absent through fading, the circuit passes on the element, positive or negative, as the case may be, received on the second transmission. If a positive element is followed on the second transmission by a negative element, or vice versa, the transistors operate so that the output signal is suppressed, and this condition may be used to operate an error-indicating circuit. In a modified path-selecting arrangement, Fig. 12, shown diagrammatically, which reduces the number of switching circuits controlled by the element storage devices F1, F2, F3, F4 and indicated by appropriate reference letters K in Fig. 11 (not shown) and similarly denoted in Fig. 12, the devices F1, F4 each control two two-position switches K11, K12 and K49, K50, respectively, whilst the devices F2, F3 each control an associated two-position switch K2, K3. The operation of any combination of the storage devices F1 . . . F4 closes a circuit from the battery BK to a specific one of the final recording elements N1 . . . N16, and with the switches K2, K3 . . . K49, K50 in the rest positions shown, a circuit is closed for the recording element N1 when an operating switch KO is closed at the end of reception of a code combination.