Patent SG-11201806244P-A (SG)
Title: System and method for reducing programming voltage stress on memory cell devices
Inventor: YOON SEI SEUNG
IPC: G11C17/18
Filed: 2017-02-13
Abstract: WO 17 / 15 130 2 Al r 33D CONTROLLER 350 SENSE AMPLIFIER 340 BL PROGRAMMING DECODER 320 (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (10) International Publication Number (43) International Publication Date WO 2017/151302 Al 8 September 2017 (08.09.2017) WIPO I PCT 1111111111111101110101011111010111110111011111111011101111101011111111111110111111 (51) International Patent Classification: G11C 8/08 (2006.01) G1 1C 17/16 (2006.01) G11C 8/14 (2006.01) G11C 17/18 (2006.01) G11C 8/12 (2006.01) (21) International Application Number: PCT/US2017/017725 (22) International Filing Date: 13 February 2017 (13.02.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/061,882 4 March 2016 (04.03.2016) US (71) Applicant: QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration, 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (72) Inventors: YOON, Sei Seung; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). KOTA, Anil; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). GRUBELICH, Bjorn; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (74) Agent: FOUNTAIN, George; Loza & Loza, LLP, 305 North Second Avenue #127, Upland, California 91786 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, [Continued on next page] (54) Title: SYSTEM AND METHOD FOR REDUCING PROGRAMMING VOLTAGE STRESS ON MEMORY CELL DEVICES (57) : A memory array includes a first subarray of memory cells and a second set of memory cells. The first and second subarrays of memory cells share a set of global word lines. The first and second subarrays of memory cells are coupled to first and second sets of bit lines, respectively. The first subarray includes rows of memory cells coupled to a first set of local word line drivers via a first set of local word lines, respectively. The second subarray includes rows of memory cells coupled to a second set of local word line drivers via a second set of local word lines, respectively. A selected local word line drivers generates a first asserted local word line signal for accessing at least one memory cell for reading or programming purpose in response to re- ceiving a second asserted signal via a global word line and a third as- serted signal. WO 2017/151302 Al 1#11101113101 010IR0101311011011111101n#011 GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(ii)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3))