Patent GB-1018330-A (GB)
IPC: G09C1/10
Filed: 1964-11-23
Abstract: 1,018,330. Data processors for language translation. INTERNATIONAL BUSINESS MACHINE CORPORATION. Nov. 23, 1964 [Dec. 18, 1963], No. 47502/64. Heading G4A. In a data processor, stored data groups each contain information relating to the relation of the containing group to another group, this information being used to calculate the address of another group. The invention is a processor for automatic language translation, for performing syntactic and semantic analysis on the results of a dictionary look-up of the passage to be translated. These results are stored in an addressable core memory in the form of words each comprising a character (*) indicating the beginning of the word and the end of the preceding word, followed by a backward length tag character, a forward length tag character, a character indicating the part of speech of the word, blank characters to be filled in during the processing operation, and characters representing additional information as to the word, e.g. its translated meaning or possible translated meanings. The backward and forward length tags respectively indicate the numbers to be subtracted from and added to the addresses of the tags to obtain the addresses of the beginning characters (*) of the preceding and following words respectively. Each character is a six-bit byte and addressing is by character. Processing is done with the aid of entries in table storage which is a photographic disc having a plurality of concentric tracks, each entry including two characters indicating the beginning of the entry, a prefix character indicating the operation now being performed, characters from one or more of the following three categories (a) instruction characters, (b) characters to be matched with characters stored in the core memory, (c) characters to be stored in the core memory under suitable circumstances, and also a prefix character indicating the net operation to be performed. When a given operation is to be performed, a prefix character specifying the operation is stored in a prefix region of the core memory, read out into a scan register and from there compared in compare circuits with characters read from table storage into a staticizing shift register. A transducer sensing table storage moves from track to track in a direction determined by the sense of the inequality indicated by the compare circuits until the sense of the inequality changes when a detailed search is initiated (in one direction only) of the track reached (if the track-to-track movement was to higher valued tracks) or of the next valued track (in the other case), followed in either case by a detailed search of the next lower valued track if necessary, until equality is found. Matching on further characters may then follow. In general, several entries in the table storage start with a given sequence of characters, so the principle of longest match is applied and breakpoint entries are provided (to prevent searches continuing in the absence of a match). The address used to access the core memory may be incremented or decremented (depending on the setting of a true-complement circuit) in an adder by one (from a ONE code generator), by a forward or backward length tag read out of the core memory into the scan register, or by a number read from the table storage. An example sequence of operations described in detail (Fig. 5, not shown) is for linking verbs with their complements in a sentence. The first operation is to find the end of the sentence (indicated by an end-of-sentence word following the last word of the sentence). The prefix character for this operation is stored in the prefix region of the core memory and the entries in the table storage with that prefix are located. The first word of the sentence in the core memory is compared with these entries in turn until the break-point entry is reached when the same is done for the next word in the core memory and so on until the end-of-sentence word is tried when sufficient matching to terminate the comparisons will be obtained before the breakpoint entry is reached. A search left along the sentence is then initiated for a verb in a similar manner, the prefix in prefix region of the core memory having been changed (so a different set of entries from the table storage is involved), and when a verb is found (by comparing part of speech characters) its beginning address is stored in a register for future use and a search right for a verbal complement performed. If during this right search an end-of-sentence word, a subordinate conjunction word or a predicative verb word is encountered then the verb has no complement this side of it and the system returns to the verb and searches left for a verbal complement in a similar way. If a verbal complement is found, both it and the verb are modified by writing indicator character from the table storage into their words in the core memory. A search left for another verb then starts at the first verb. This process repeats until the sentence beginning is reached. Timing.-A 6-bit counter (Fig. 3g, not shown) is driven by bit clock pulses from a timing track on the disc of the table storage and produces outputs at byte and half-byte time. The counter is synchronized by being reset every time the pair of characters indicating an entry beginning are read from the table storage. Comparison.-The compare circuits (details in Fig. 3i, not shown) compare the highest order bits of the bytes supplied to them when enabled by a signal on line 114 (not shown) and produce a signal on a line 116 or 118 (not shown and depending on which is the greater) if they are unequal and a signal to enable the next-mostsignificant bits to be compared if they are equal, and so on, absence of signals on any lines 116, 118 (not shown) indicating equality. Generation of length tags (Fig. 2, not shown).- Successive bytes of a word are read parallel-bybit, serially-by-byte, on to a magnetic drum. As each byte is read on, counters preset to counts of three and zero are incremented by one. When the asterisk byte indicating the end of the word and the beginning of the next is read on, it is also detected by an AND gate which after a one byte delay reads the count in the counter preset to three on to the drum to constitute a backward length tag, and the count in the other counter through an output register into the core memory to constitute a forward length tag. The contents of the drum then follow this tag through the output register to the core memory. Of course the tags just described are included in different (adjacent) words.