Patent UA-106262-U (UA)
Title: Generator of a single three-pulse code group with programmable gap between pulses in the group
Inventor: KOROBKOV MYKOLA HRYHOROVYCH
IPC: H03K3/78
Filed: 2015-09-21
Abstract: A generator of a single three-pulse code series programmable pause duration between pulses in series, a multiple of the period of clock pulses that are fed to the input of the shaper with the output of an external generator, includes: two reversible binary counters, each of which has an input for supplying clock pulses, the input of the debug mode summation/subtraction, enable input synchronous parallel load inputs and flow data, the enable input of the counting mode, the asynchronous input setup in the zero state, the output of the overflow; the first and second OR elements inverter; chain consisting of series-connected resistor and capacitor; a synchronous D-trigger with asynchronous input setup in the zero state, the first and second two-input AND elements the overall point of the series-connected resistor and capacitor is connected with the information input D-trigger, with inputs of the first and second two-input elements; the output of D-trigger connected to the input of the first OR element the output of which is connected to the second input of the second And element; the output of the first dual input element And is connected to the input asynchronously set D-trigger in the zero state; the output of the second OR element is connected to the enable input synchronous parallel loading of the first counter, the output of the overflow of the first counter, which forms the output of the driver connected to the input of the first OR element the input of the inverter, the output of which is connected to the enable input of the counting mode of the first counter, the output of the overflow of the second counter is connected to the input of the first element; the values of the signals at the inputs parallel load data of the first counter determines the pulse duration at the output of the shaper; inputs parallel load the second counter form inputs programming of the unit on a given pause between the pulses; the output of the second AND element are connected to the inputs of an asynchronous counter installed in the zero state; clock inputs of the first and second counters connected to create an input shaper, the inlet of a continuous periodic sequence of pulses output from the external oscillator; the clock input of D-trigger generates an input feed pulse (Start), characterized in that the introduced: double substraction counter, having an input for supplying clock pulses, the enable input of the counting mode, the asynchronous input setup in the zero state; the third OR element, the second inverter AND element, one input connected to the output of the overflow of the second counter and the input of the second OR element the second input AND-NOT element connected to the output of the first inverter and the second input of the first element; the output of AND-NOT element connected to the enable input of the counting mode of the second counter; the second input of the second OR element connected to the output of the second inverter, the input of which is connected to the input of the first OR element the output of the third OR element the first input connected to the output of a first level of the third counter and the input of the fourth bit data parallel load of the first counter, the second input of the third OR element connected to the output of the second category of the third counter and the input of the first category of data loading the first counter; input of the second data loading the first counter connected to the output of the third OR element; the entrance to the third category of data loading the first counter is connected to the level of the logical zero; input asynchronously set to the zero state of the third counter connected to the output of the second element; the clock input of the third counter connected to the input of the driver.