Patent GB-1480503-A (GB)
Title: Calculating unit for serial multiplication
IPC: G06F7/52
Filed: 1974-07-29
Abstract: 1480503 Multiplier SIEMENS AG 29 July 1974 [13 Sept 1973] 33355/74 Heading G4A A hardware, serial, binary multiplier is described for multiplying binary multiplicands by one or more fixed binary multipliers, in which, Fig. 7, the multiplicand bits are fed serially EK into a shift register SR, those stages of which correspond to binary 1's in the multiplier(s) having output taps AB1, AB3, AB4, AB5 feeding adders ADD1-ADD4 producing the product(s), or in which, Fig. 9, the multiplicand bits are fed EK into those stages of a shift register (or registers), via switches S1, S3, corresponding to binary 1's in the multiplier(s) to be added to the output of the preceding stages by adders ADD3, the output of the register(s) forming the product(s). The arrangement may be used in a digital filter where multiplication by constant factors is performed. Two embodiments are described. In the first, Fig. 7, an N bit multiplicand which ineludes one sign bit, is fed, at input EK, least significant bit first, into shift register SR, the last bit fed in being the sign bit which is also clocked, into sign bit store VR. Three binary multipliers (all <1) are provided, via 0À101, 0À00111, and 0À10111, each being represented by a tap at that stage of the shift register which corresponds to a binary 1 in the multiplier, the rightmost stage corresponding to the most significant multiplier bit. Thus, given that the first stage SRO of the register is omitted, it being unnecessary as all multipliers are <1, the taps are provided at stages SR1 corresponding to the first 1 in the first and third multiplier, SR3 corresponding to 1's in all three multipliers, and SR4 and SR5 corresponding to the last two 1's in the last two multipliers. Switches S1, S3, S4, and S5 are connected to the corresponding taps for the first N-k shift pulses following loading of a multiplicand into the register, where the tap represents the 2<SP>-k</SP>th order of the binary multiplier, and to the sign bit store VR for the remaining k shift pulses of the N pulse cycle. The various tap outputs are then combined in adders each of which has a carry bit store (not shown), to produce three product outputs A, A<SP>1</SP>, and A<SP>11</SP>, corresponding to the three multipliers, e.g. for product A<SP>11</SP> the taps from stages SR1, SR3, SR4 and SR5 are added thus combining the outputs from those taps corresponding to the multiplier 0À10111. The number of bits in the product is limited to the number of bits in the multiplicand, and certain of these bits may merely be the multiplicand sign bit. The first multiplication starts when the first multiplicand has been shifted into register SR and the product is formed as the multiplicand is shifted out of the register. During this shifting a second multiplicand may be shifted in for multiplication and so on. Arrangements are described for rounding the product using the carry bit stores in the adders, Fig. 8 (not shown). In the second embodiment, Fig. 9, the multiplicand is fed via switches S1, S3 into those stages of the shift register corresponding to 1 bits in the multiplier (in this case 0À101), the leftmost stage corresponding to the most significant multiplier bit, during, for each stage, the last N-k shift pulses of the loading cycle, where the stage represents the 2<SP>-k</SP>th order of the multiplier, the stages otherwise being supplied via the switches S1, S3 with the contents of the sign bit store VR, which in fact corresponds to the preceding multiplicand (if any). As in the first embodiment the register does not include those stages corresponding to high ordered 0's in the multiplier, e.g. as shown the multiplier is 0À101 so that stage SRO corresponding to the first 0 is omitted. The second, and any subsequent stages, having a multiplicand input, i.e. in this case SR3, are preceded by an adder ADD 3, with a carry bit store US3, to sum the multiplicand input and the output of the preceding stage. The product, A, appears at the output of the register. This embodiment may also provide for more than one multiplier and in such a case, Fig. 14 (not shown), one register is provided for each multiplier although for multipliers having a number of higher ordered bits of the same value, a series of register stages corresponding to the common bits of the multipliers are shared, e.g. for two multipliers 0À101 and 0À10111 the stages up to stage SR3 are common, there being two sets of stages SR4-SR7 one for each multiplier fed from the common stage SR3. As for the first embodiment rounding arrangements are provided by a gate G which sets the carry bit store of the adder at, in this case, the second shift pulse in the cycle when the sign bit stage contains binary 0, i.e. the sign is +ve, and the next multiplicand bit is 1. A standard module is described, Fig. 15 (not shown) for forming each of the states of the register(s) of the second embodiment, each module including a flip-flop storage stage, an adder, and logical gating circuits providing the switches 51, 53 and other required logic.