Patent JP-S5132073-B1 (JP)
IPC: G01R31/26
Filed: 1968-07-26
Abstract: 1,239,286. Amplitude and timing tests. INTERNATIONAL BUSINESS MACHINES CORP. Aag.16, 1968. [Aug. 28, 1967], No.39217/68. Heading G1U. [Also in Division H3] In a system for making either amplitude or timing tests on a recurrent waveform, such as the output pulse waveform derived in testing a transistor by applying a given input pulse train to it, sampling signals of the same frequency as the recurrent waveform are generated, of short duration relative to changes in the waveform, the generating arrangements incorporating facilities for delaying the signals relative to a given point in the waveform, Composite signals formed by superimposing the sampling signals on the recurrent waveform are applied to a tunnel diode threshold circuit which give a low or high voltage output dependant on the amplitude of the composite signal relative to a controllable bias level. This output is used to control a feedback circuit, which in voltage measuring applications controls the value of the bias such that the tunnel diode circuit attains an unstable equilibrium condition wherein it oscillates between high and low voltage states, while in timing measurements the feedback circuit controls the sample signal delay until it selects a point on the recurrent waveform having an amplitude corresponding to a fixed bias applied to the tunnel diode. The feedback voltage is measured to indicate either the amplitude at a selected point on the waveform, or the time at which the waveform has a selected value. Pulses from a clock source 6 Fig. 1 are applied to a waveform generator 7 whose output pulses are applied to a transistor under test 1. The pulses are also fed to switch an input bi-stable stage 56 of controllable delay system which provides reset and strobe pulses 33, 25 at its output 20. These strobe pulses, together with the output from the device under test are applied together with a bias from a control circuit 28 to a tunnel diode sampling circuit 12. If the peak current value of the sum of these three signals exceeds the switching current of the tunnel diode, the diode sets in its high voltage state and stays there until the next reset pulse. The tunnel diode output is applied to a decision circuit 27 which contains an integrator which develops a continuously varying output voltage from a constant input. This output is inverted and passed via a switching circuit 62 to control either the bias circuit 28 (for voltage measurement) or, via diode 65 the strobe pulse delay system (for timing measurements). According to the setting of the switching circuit 62, the meter 35 indicates the amplitude of the test signal at a strobed position determined by the reference voltage 63 which is switched to control the delay system, or the time at which the signal attains a particular value, as set by the source 63, which is switched to control the bias on the tunnel diode. Controllable delay circuit (also Figs. 9 and 10 not shown). The pulses from the clock 6 are applied to the bi-stable circuit 56 which incorporates a tunnel diode (78) which is set to its high voltage condition. This causes the generator 57 to drive current into the sink 58, which orginally received current from an input applied via the switching circuit 62 (either the reference or decision circuit output) and from a generator 64. The output node B of this generator is orginally held at the voltage of the switching circuit input. The first generator output cuts off the diode 66, so that the node B rises to earth potential, in a time determined by its original voltage and by the capacitance of the ranging circuit 67. When it reaches earth potential, the current through the level comparator 68 (Fig. 10) is switched from a path through transistor (88) to one through transistor (87). This initiates voltage changes at two nodes (D and F). The first is fed back to reset the bi-stable circuit 56, while the second is passed via a waveshaper 69 and differentiator 70 to provide the reset and strobe current pulses 33 and 35. The spacing of these is determined by a pair of open and short circuit lines (96, 97). Sampling and decision circuits Fig. 7: The test strobe and bias currents are applied to the tunnel diode 13 via resistors 46, 47, 48 to produce a composite waveform 26, If the peak of this is sufficiently large to set the diode, a relatively high voltage is established across the diode and applied to the input of an integrating amplifier 29. This provides a steadily varying output voltage which is inverted at 30 and applied to the switching circuit 62. If this is set in the voltage measurement position, the voltage from 30 is applied to the bias control amplifier 31 and thence to the bias input. The feedback capacitor 99 of the integrating amplifier 29 has coupled across it a further capacitor and diode circuit 100-103. When the bias voltage is close to the proper value the voltage at the point 104 will be between the drops of the diodes 100, 101 and the capacitances 102, 103 are effectively coupled in parallel with 99 to smooth any ripple in the bias. When the bias is some way from the correct value, the capacitors 102, 103 are shorted to earth, enabling a more rapid approach to the proper value to be established by the integrating system. A mode control system Fig. 8 (not shown) is associated with the output of the decision circuit for use in time measuring arrangements such that the strobe may only be moved within a particular range to find a peak within that range. Two similar arrangements of delay and sampling circuits may be associated in one system so that pairs of measurements, at different points on the test waveform, may be made concurrently (Fig.3). Circuits are given (Figs.13 and 14) of a sampling arrangement providing a digital approximation system to provide a digital output.