Patent GB-1160969-A (GB)
Title: Dynamic Test System
IPC: G01R31/3193
Filed: 1966-08-24
Abstract: 1,160,969. Circuit testing. TEXAS INSTRUMENTS Inc. Aug.24, 1966 [Dec. 7, 1965], No. 37970/66. Heading G1U. [Also in Division G3] Test apparatus for automatically making amplitude and time measurements when carrying out dynamic testing of e. g. integrated circuits incorporates a test station including D. C. bias supplies and a pulse generator producing a repetitive waveform, switching circuits for selectively connecting the bias supplies and the pulse generator to a test specimen a system for responding to the dynamic output of the specimen and a sensing circuit for selectively connecting this system to the specimen; a measuring circuit connected to the test station output for making time and amplitude measurements to produce a pulse train representing the magnitude measured and a count data signal defining a measuring period, a data readout circuit including a counter for counting the pulses during the count data signal and a programmable control incorporating a memory, for automatically operating the apparatus. A complex system for carrying out both static and dynamic tests on an electronic device is described in detail. When making dynamic tests on the device by subjecting it to a repetitive waveform, two main types of measurement are made. (i) amplitude measurements - e.g. peak voltages, voltage differences between waveforms in corresponding positions, voltages relative to reference levels or percent levels. Voltage measurement is effected by comparing an input with a stepped reference and counting the steps until a transition occurs. (ii) Time measurements are effected by using pulses at the beginning and end of a time period of interest to gate a counter on and off. The integrated circuit 10 under test is plugged into a socket 22 on the test station 25 on a socket board 24 which has coded contracts at the end to ensure that the control system carries out the tests appropriate to the circuit. The socket is connected to banks of relays LR, nine for each lead of the device, and these are connected via spring contacts 68 to a performance board 28. This board is so mounted that it is easily removable by lowering the rotatable cams 96 and withdrawing the tray 98 so that a board appropriate to the device under test is easily inserted. Measurements are made in accordance with a programmed sequence. Each measurement has two major scan periods, a measurement being made in each with respect to the same reference, and the two compared. Each scan includes normalizing periods for storing reference voltages on two capacitor memories and for stabilization, and then ten interlace scans, each step of each scan being one unit in excess of that in the previous scan. Transistions are detected in each scan and the total count averaged. In reading out, counts in the first major scan are subtracted and in the second added, and comparators determine whether the differential output measurement is less or greater than minimum and maximum selected values. Programming system: The test station memory stores programmes for the two major scans and for controlling the bias supplies and measurement relays, and the information is gated through test station interfaces to the test relay drivers by the scans from a dynamic sequence timetable. The memories M1-M10 store information which determines the magnitude and operating times of related D.C. bias supplies. The pulse generator memories 243-244 are programmed with information relating to rise and fall times amplitude and width &c. The test start memory 296 determines when the test start signal occurs. The measurement type and range memory 294 determines whether the test is static or dynamic and whether an amplitude or time measurement is to be made. Programme information is fed to the static test control 292, the fast ramp generator, the dynamic sequence timetable and range and type decoder. The digital sync. memory and interface 311 is programmed for the periods and delays of various clocks in the system. Operating sequence Control unit 250 routes programming information from the unit 251 to the shift register memories of the system, synchronised by the control unit clock 242. Thereafter the bi-directional counter 240 counts clock pulses in the forward direction and brings up the sequence lines 1-10 to the '1' level. The sequence lines and programme line gate a test start signal from memory 296 to a delay timer 255, which permits the device under test to stabilize. Thereafter test read signals are sent to the static test control 292 and dynamic sequence timetable 470, start measurement signals then being generated in these subsystems. When the measurements are completed, a test complete signal is sent back to the control unit 250 to generate a record results signal and reverse the bi-directional counter, to ripple down the sequence lines in reverse order, and terminate the start and read signals. As soon as sequence line 1 has returned to '0', programme information for the next test is fed to the shift register memories, and the operating sequence starts again for this test. Static tests To make measurements on the signal outputs derived in static tests, the outputs are switched to the lines RO, RC and applied to an amplifier 252. The measuring voltage range is controlled by switching in the appropriate resistor V1-V5, while current measuring ranges are altered by switchings S1-S9 and I1-I10. The amplifier output passes through a voltage-frequence converter 274 and pulse shaper 278 to provide pulses which are gated at 280 with a pulse of standard width, so that the number provided indicates the measured signal. These pulses pass to the output data control system. Dynamic tests In carrying out dynamic tests, high frequency repetitive stimuli are applied to the device and the device outputs sampled at a much lower synchronized frequency. A synchronizing system defines a repetition period in which occurs a number of variable clock pulses and delayed pulses. A sample clock pulse may be programmed to occur at any time within this period. This pulse initiates a fast ramp voltage with programmable slope from circuit 322 and each successive ramp is compared in amplifier 354 with a staircase generator output 358 operating in a count mode, to produce a strobe pulse at equality from generators 374, 376. Sampling circuit: A sample is initiated when the ramp voltage, derived from the circuit 322, equals the voltage from the staircase generator 358, as indicated by the comparator 354. This operates the sampling bridge 378, via the pulse and strobe pulse generators 374, 376. A proportion of the sample is stored on capacitor 392 and is passed via channel 396 to a comparator amplifier 400. The output from this may be passed either to capacitor 404 or 408, though the switch 402 to the capacitor 404 is normally open. Thereafter the two signals pass via unity gain amplifiers 412, 414, to opposite ends of a potentiometer 416, whose tapping is fed back to the comparator amplifier 400. The switches 402, 406 are operated in synchronism with the sampling switch 378 so that their normal positions are momentarily reversed when a sample is taken. Further, the output from the amplifier 412 is fed back to the input capacitor 392 via the resistor 422. This system operates so as to compensate for lack of 100% efficiency in the sampling bridge. Reference and comparison circuit: The sample is fed to one input of a comparator amplifier 434 whose output is selectively connectible to either capacitors 442 or 452, one storing the maximum and the other the minimum. The outputs from these are fed via unity gain amplifiers to the opposite ends of a percent DAC potential divider, 456, whose tapping is connected back to the other input of the comparator amplifier to provide the feedback reference. The output of the comparator amplifier is at one or other logic level, depending on the relation of the input to the reference, and a change in this level operates the transition detector 464. A clock referenced to the strobe pulses operates a counter in conjunction with this and if the counter does not reach a particular count before a further reverse transition occurs, the transition is false the counter is reset and no output produced. Timing measurements are carried out by feeding back appropriate references e.g. the 15% level and 85% levels derived from a preceding pulse and determining by the transition detector when the sampled voltage passes through these levels, the occurrence of transistions being used to control a counter whose output is transmitted to the readout arrangements. Voltage measurements are carried out by using the reference and comparison circuit to store a sampled value and then applying to it the step waveform from the ladder network, the number of steps being counted to establish the value of the voltage. The difference between this and a reference may be similarly determined. Synchronization system: A logic circuit (Figs. 13a-13c) feeds signals from a master clock to a number of circuits via a pulse transformer which maintains precise synchronization between pulses, and matches all impedance (Fig. 14a). Pulses from this transformer are fed to an increment counter (Fig. 15) which is reset when programmed counts are reached. This resetting determines the rate at which sample clock pulses are generated by the synchronization system. The pulses activate particular strobe pulse generators; as determined by the programme in accordance with the particular probe which is active. The signal sampled by the bridge 378 is multiplexed through an appropriate channel in accordance with this. Details of the sampling circuits are given (Figs. 16a-c). Results from either static or dynamic tests are fed as pulses to a data counter control 284 and thereafter to a data counter 286, whose output is compared with both programmed maximum and minimum values in the comparators 502, 504. T