Patent GB-1206344-A (GB)
Title: A cathode ray tube line generator
Inventor: HOLLAND TERENCE JOHN
IPC: G09G1/10
Filed: 1968-03-13
Abstract: 1,206,344. Cathode-ray tube circuits. A. C. COSSOR Ltd. 13 Dec., 1968 [13 March, 1968], No. 12259/68. Heading H4T. A generator providing the X and Y deflection signals required to deflect the beam of a cathoderay tube to trace a straight line the initial and terminal co-ordinates of which are specified digitally comprises respective accumulators storing the initial X and Y co-ordinates in binary valves, respective shift registers storing binary valves of #X and #Y (where X + #X and Y + #Y are the terminal co-ordinates) means for shifting each of the #X and #Y values concurrently in the direction of increasing significance until the most significant bit of the larger assumes a predetermined location in the register, means for adding (or subtracting) the shifted contents of each shift register to (or from) the contents of the corresponding accumulator a number of times inversely related to the number of shifts and respective digital-toanalogue converters connected to the accumulators and providing the respective X and Y deflection signals. The invention operates by (in effect) dividing each quantity #X and #Y into N incremental quantities # X and # Y (see Fig. 1) which are then added (or subtracted) N times to (or from) the contents of the corresponding accumulators. As shown in Fig. 2, 10-bit binary numbers representative of the initial co-ordinates X, Y and of #X, #Y are supplied from an information source 10 (e.g. a computer) to respective accumulators 12, 14 and 16, 18 together with, in the ease of #X and #Y, respective sign bits. When a succession of connected lines are to be drawn source 10 supplies the initial co-ordinates X, Y of the first line only since the terminal co-ordinates of this and of subsequent lines which also specify the initial co-ordinates of the second and subsequent lines will be in the accumulators. In operation (considering the adding mode when the sign bits 30, 32 are positive) shift pulses derived from a clock 54 via AND gates 56 and 58 shift the contents of registers 16 and 18 towards the more significant end until a "1" appears in the 2<SP>9</SP> position or until seven shifts have been effected whichever is the smaller. This is effected by means of a seven stage counter 26 initially set 1111111 and which is counted down by feeding "0'<SP>s</SP>" in from the 2<SP>6</SP> position by ends clock pulse. When a "1" appears in the 2<SP>9</SP> position of either or both registers 16, 18 a NOR gate 62 operates to inhibit AND gate 58 to terminate the shift of the latter registers and the counting down of counter 26. When seven clock pulses have occured the output of a 4-bit counter 60 inhibits AND gate 62 and enables NOR gate 64 which enables an AND gate 66 to pass clock pulses to counter 26. The latter is then counted down from the count remaining when the "1" appeared in stage 2<SP>9</SP> of register 16 or 18 (or both) to a count of 0000000 and during the counting down pulses are supplied on a line 28 to accumulators 12, 14 which on the occurrence of each pulse add the #X and #Y quantities in registers 16, 18 to the numbers already therein. After counter 26 has reached 0000000 a bi-stable circuit 72 and an AND gate 68 allow one further clock pulse to reach the accumulators so that N (see Fig. 1) is always 1, 2, 4, 8 ... or 128. Assuming that M shifts occurred in registers 16, and 18 the number remaining in counter 26 is 2<SP>(7-M)</SP> which is the number of times the contents of registers 16, 18 are added to the contents of the accumulators i.e. the number N (see Fig. 1). Since the 2<SP>9</SP> stages of registers 16, 18 feed into the 2<SP>2</SP> stage of the corresponding accumulator the latter treat the values #X and #Y as #X/2<SP>(7-M)</SP> and #Y/2<SP>(7-M)</SP> which is the same as #X/N = #X and #Y/N = #Y (see Fig. 1). Thus the numbers in the accumulators are increased by #X and #Y during the occurrence of each of N clock pulses. On each addition the output of the accumulators "jump" to a new value and such outputs (from the 11 most significant stages) are supplied to digital-to-analogue converters 34, 36 which provide, via smoothing filters 38, 40 and amplifiers 42, 44 the required X and Y deflection waveforms for the tube 48. Since N only varies by factors of 2 the segments 8X, #Y can vary in length by a factor of 2 and since all segments are traced in constant units of time the beam intensity must be controlled so that all segments have uniform brightness. This is achieved by means of the control circuit 52 which includes a digital comparator 100 (Fig. 3) supplying an output which if 8 X is greater than #Y, switches on transistor pairs 104, 108 and 106, 110 whereas if #Y is greater than #X, transistor pairs 112, 116 and 114, 118 are switched on resulting in the application of voltages of either 5À8V + V1 (#X>#Y) or 5À8V + 0À3V1 (8Y>8X), where V 1  is a reference voltage, to the lines 96, 98 feeding digital-to-analogue converters supplied with the 5 most significant bits of #X and #Y. A voltage is thus developed across resistor 80 which is approximately proportional to the length of the actual traced segment #L = ##X<SP>2</SP> + #Y<SP>2</SP>the approximation being that the length #L is approximately equal to the sum of the larger plus 0À3 of the smaller of the quantities #X, #Y. This voltage is then supplied to the brightness control electrode of the tube via amplifiers 53 during periods determined by gating pulses from a bi-stable circuit 74. Dashed lines may be produced by means of an arrangement which periodically interrupts the application of the brightness control voltage to the tube at a rate proportional to the segment length #L (Fig. 4, not shown).