Patent GB-862257-A (GB)
Title: Improvements in or relating to computers
IPC: G06V10/20
Filed: 1959-04-22
Abstract: 862,257. Electric processing of spatial patterns. WESTERN ELECTRIC CO. Inc. April 22, 1959 [April 25, 1958], No. 13661/59. Class 106 (1). In apparatus for processing patterns represented by electric signals in an array of cells, each cell or module has means for storing a number of binary signals and logic and arithmetic circuitry, means are provided for entering signals into each cell and a central control applies orders to the cells. In the example shown in Fig. 2, the bottom left-hand corner of the pattern is found by applying identical orders to each module of the array. Each module, Fig. 4, comprises an accumulator register 32 and subordinate a, b and c registers 34, 36 and 38. Each register consists of a bi-stable circuit with set and reset inputs and " 1 " and " 0 " outputs. Each has connections to adjacent modules 40, 42 and internal connections through gates so that the stored signals can be shifted, inverted, added or multiplied. In adding, if any term is " 1 " the result is " 1." In multiplication, if any term is " 0 " the result is "0." In Fig. 2 (A) the original pattern is transferred from the accumulator registers 32 to the a registers 34. The signals are then shifted into the accumulator registers of the adjacent right-hand module, i.e. the pattern is shifted to the right as shown in Fig. 2 (B). These signals are stored in the b registers. The original pattern is then transferred from the a to the accumulator registers, Fig. 2 (C) and is shifted vertically, Fig. 2 (D). These signals are then added to the signals in the b registers Fig. 2 (B), that is the D and B patterns are superimposed, Fig. 2 (E). The resulting pattern is inverted, Fig. 2 (F), and stored in the b registers. The original pattern from the a registers is again entered into the accumulator registers, Fig. 2 (G), and this pattern is multiplied by pattern F and by itself shifted down and by itself shifted left. The result is a signal in a single module, this being the lower lefthand corner of the pattern. The inputs are from an array of input cells individually connected to the input lines 88, Fig. 4, of corresponding modules. The input signal passes through Or gate 52 to the set input of the accumulator register 32. The operations used in the above sequence (Fig. 2) will be briefly described, signals being applied to the control leads from a central control device in which instructions are successively registered to perform the required programme. The pattern is transferred to the a registers by opening all gates 80, 82 by signals on lines 76, 78 and enabling the entry gates to a registers 34 by signals on lines 56. Shifting the pattern to the right is effected by gating the contents of each cell into the cell to the right. " Left " connection line 84 is energized to read out the " 1 " and " 0 " terminals of store 42. These pass through multiplier Or gate 60, 66, through And gates 62, 68 enabled by signals on lines 54, 70, through gates 50, 52 to set input of store 32. This signal is passed into the b register by enabling gate 82 and by an enabling signal on b entry line 72. The signal from the a register 34 is passed by to the register 32 by a signal on line 56 which opens gate 64 and a signal on line 70 which opens gate 68. The pattern is shifted vertically upwards by gating connections in similar manner to the register 40 of the module above. The B and D patterns, Fig. 2, are superimposed by adding the " 1 "s in each module present in the b register and the accumulator register. The b register is selected for read-out by line 72 and a signal on Add line 70 passes the signal from the '' 1 " side, if present, to the set input of accumulator register 32. This pattern is inverted by opening gates 46, 48 by a signal on invert lead 44 so that the contents of the " 1 " stage are entered via Or gate 50 into the '' 0 " stage and vice versa. This new pattern is passed to the b register 36 and the original pattern in the a registers is passed back to the accumulator register 32. Pattern G is multiplied by the pattern F by enabling the multiply line 54 and reading out the b register. Gate 62 passes "0's" only since the presence of a "0" always makes the product "0." The pattern in the accumulator registers is simultaneously multiplied with that of the adjacent module 40 above (equivalent to pattern G shifted down) and to the right (equivalent to pattern G shifted to the left). " Up " line 86 is energized to read out the accumulator register 40 above the presence of a " 0 " in which will cause a signal to pass through gate 62 to the reset input of register 32. Similarly the module to the right is read out by a signal on the R line and the "0," if present, rests the register 32. Link circuits.-As shown in Fig. 5, each module 100 may be connected by link circuits 111-118 to the modules 101-108 above, below, on each side and diagonally adjacent. Each link circuit has a bi-stable register which is set at '' 1 " if both the associated cells are "1." This allows the link circuit to become operative subsequently so that when an " expand " order is given link connections are made between cells which originally were not both "1." In Fig. 7 (A) link circuits are enabled between the indicated positions. When an expand order is given the pattern in the c registers, Fig. 7 (B), which consists of a single mark can be expanded horizontally, Fig. 7 (C) and then vertically, Fig. 7 (D). If the horizontal and vertical link circuits were energized simultaneously the pattern of Fig. 7 (A) would have been reproduced. Provision may be made for connecting the output of the right-hand module in each row with the input of the left-hand row of the row above. The bits to be stored can then be entered serially and shifted through the rows in turn until the proper disposition is reached. The apparatus may be applied to the identification of character patterns. It is suggested that arrays in three or more dimensions may be constructed.