Patent GB-1493878-A (GB)
Title: Apparatus for organizing tasks on peripheral devices
IPC: G06F9/26
Filed: 1975-02-19
Abstract: 1493878 Digital computers COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII-HONEYWELL BULL 19 Feb 1975 [20 Feb 1974] 7039/75 Heading G4A In a data processing system, a peripheral controller uses first level EV1 and second level EV2 priority microprocesses and so-called ordinary microprocesses, all for controlling I/O data transfers between a CPU and one or other of a plurality of peripheral devices, the controller having means for enabling the first level EV1 priority microprocesses to interrupt ordinary microprocesses and a dispatcher (including means for storing tables and parameters) for scanning the ordinary microprocesses in the order of levels of priority assigned to them for selecting one having the highest level of priority present and for interrupting the running microprocess if of lower priority and replacing it with the selected microprocess, there being means for completing the interrupted microprocess after the selected microprocess has been terminated. Fig. 2 shows the peripheral controller, having a memory M containing microprogrammes for the microprocesses, tables and control blocks (see below). EV1 level interrupt requests from peripheral device adaptors DA1-DAn and a timer clock 230 are detected by an OR 220 (top) to cause interrupt of the running microprocess (unless masked under microprogramme control by a bi-stable 215), a bi-stable 217 preventing one EV1 request interrupting another. The identity of the highest priority one of the EV1 requests present at any time is encoded at a coder 221 to load a register DNR to select the appropriate microprocess to deal with the interrupt. DNR is also used, via a decoder 222, to select one of the device adaptors DA1-DAn or a gate 232 in a port PSI from the CPU or a gate 223. The gates 232, 223, 214 are used in looking for EV2 level interrupt requests from the CPU (instruction waiting or channel programme waiting) or adaptors DA1-DAn, this looking for EV2 requests being under microprogramme control. Two sets of working registers URB, LRB are provided, EV1 jobs using one set and ordinary jobs using the other, to avoid a save transfer for them on interrupt. The contents of DNR are saved at ADNR. Ordinary microprocesses can be entered in a "ready" queue (one per priority level) or a "timer" queue. The microprocesses in the "ready" queue are chained together in both forward and reverse directions, the queue having a head pointer and a tail pointer. The microprocesses in the "timer" queue are chained together in a loop, in both forward and reverse directions, the queue having a pointer which points towards the microprocess the call time of which is closest: the "timer" queue is for microprocesses to be used after specified delays. When an EV1 timer interrupt occurs, the "timer" queue is checked to see whether the call time of the first microprocess has been reached. If so, it is transferred to the "ready" queue, and the "timer" queue is updated. Gate 214 is then tested to see if there are any EV2 interrupt requests. If so, their corresponding microprocesses are executed in turn. Then the "ready" queue is scanned to find a microprocess of the highest priority present, which is executed, followed by testing for EV2 interrupt requests again, and so on. Apart from the masking of all EV1 interrupt requests by bistable 215 under microprogramme control, those from the adaptors DA1-DAn can also be masked individually by further bi-stables (not shown), one per adaptor. Any ordinary microprocess can be interrupted by an ordinary microprocess of higher priority, and of course by EV1 and EV2 microprocesses. Ordinary microprocesses may be masked (by microinstruction) against interrupt by another microprocess, despite priority. Masking an EV2 mioroprocess is also possible, by microinstruction. Each adaptor DA1-DAn has a respective control block in memory M, specifying starting addresses for the corresponding EV1 and EV2 microprocesses, and respective data addresses, a logical channel number, the number of logical channels associated with the adaptor, the address of the first microprocess control block (see below) associated with the adaptor, and EV2 mask and total-stop bits for the adaptor. Each microprocess has a respective control block in memory M, specifying the number of adaptors connected to the block, priority level, fields for chaining into "ready" or "timer" queue, a timer quantity, microprocess starting address and address of associated work field, and various state and event bits. For each level of priority, the despatcher has a table in memory M, this table containing head and tail pointers for an associated "ready" queue, a bit indicating that a microprocess at that level has been started but not terminated, and various saving fields. The memory M also has fields containing the level of the running microprocess, various state and event bits, "timer" queue pointer, the maximum number of logical channels in the peripheral controller, and for each logical channel the number of the associated adaptor and the address of the first microprocess control block corresponding to that logical channel.