Patent GB-1141653-A (GB)
Title: Sense amplifier, particularly for magnetic core memory
Inventor: MORRIS DAVID JOSEPH
IPC: G11C11/06
Filed: 1967-01-02
Abstract: 1,141,653. Amplifiers for magnetic memories. ENGLISH ELECTRIC COMPUTERS Ltd. 1 April, 1968 [2 Jan., 1967], No. 35/67. Heading H3B. A sense amplifier circuit for detecting the presence or absence of sense signals during predetermined intervals includes a first gating circuit which permits the passage of signals in response to a relatively wide strobe pulse, to strobe out noise signals distantly preceding each predetermined interval, an amplifying circuit and a second gating circuit which permits the passage of signals in response to a relatively narrow strobe pulse which strobes out noise signals closely preceding each interval. In Fig. 2, inhibit-sense lines D11, D21 are connected in a differential arrangement to transformer 13. Line 15 is normally at a negative voltage so that diodes 16, 17 are back biased, and during the write interval noise signals due to unbalance of the arrangement are not passed by the first gate. At the beginning of the read interval the negative bias on line 15 is removed and the resulting noise and sense signals are amplified at 18, passed to summing amplifier 19 and further amplified at 20. The output from amplifier 20 is supplied to AND-gate 21 which is strobed at the time when the maximum sense signal is expected. In the multi-plane magnetic core memory described (Fig. 1) inhibit-sense lines D and row lines Y each extend through all the planes. Each plane includes a plurality of words in each row, each word being threaded by a word group line WG common to the corresponding words in the other rows of a plane. Data is written by coincident energization of a row line Y and a word group line Y to write a " 1 " in each bit position of the selected word unless the inhibit line in that position is simultaneously energized. For read out the selected word group line is energized with a pulse having a gently rising wavefront. The first gate in the sense amplifier is strobed when the WG pulse reaches its maximum, after which the appropriate row line Y is pulsed to read out the data. The sense amplifier preferably has a D.C. restoration circuit to ensure that the senseinhibit lines do not remain charged after energization, due to stray capacitances. Such an arrangement is included in Fig. 4 (not shown), in which a potentiometer is provided at junction 12, so that the circuit can be finely balanced, and the centre tap of transformer primary 13A is earthed. In addition the cathodes of diodes 16, 17 are interconnected by a pair of inductors and by a pair of matched resistors, the junctions of the inductors and resistors being earthed. A further matched resistor is connected in series with each diode on the output ide of the circuit, and these resistors are interconnected by a potentiometer having its centre tap at a low negative voltage, the potentiometer being adjustable to compensate for resistive unbalance between the transformer 13 and amplifier 18. Summing amplifier 19 receives inputs from further similar circuits coupled to inhibit-sense lines for the first digits of the remaining pairs of word groups. The primary winding 14A of inhibit transformer 14 and line 15 of each circuit may be connected to selection circuitry so that the inhibit and first strobe pulses are applied only to the relevant circuit.