Patent GB-975224-A (GB)
Title: Data storage systems
IPC: G06F11/10
Filed: 1963-10-22
Abstract: 975,224. Digital data storage. RADIO CORPORATION OF AMERICA. Oct. 22, 1963 [Nov. 14, 1962], No. 41711/63. Heading G4C. In a system for reproducing signals stored on a record medium in phase-modulated form, only the peak signals which occur at the beginning of a group of "1"s or a group of "0"s and which are of greater amplitude than the intermediate peak signals are detected, the polarity of the detected signals indicating whether the succeeding bit or bits constitute a group of "1"s or of "0"s. As described, data is stored on a moving medium 10 which may be a magnetic drum, disc or tape or a ferroelectric record medium, in the form of 6-bit data words each followed as shown in Fig. 2 by (1) a space bit, (2) a parity bit for the number of groups of "0"s in the word (3) a parity bit for the number of groups of "1"s in the word, (4) an "end" bit. Writing circuit.To record a data word 110100, Fig. 2 (a), an input waveform, Fig. 2(e), in which a "1" is represented by a pulse and a "0" by the absence of a pulse, is applied to the input terminal 16, Fig. 1, of a writing circuit 12. Each input "1" sets a flip-flop 20 thereby causing a writing amplifier 24 to produce a bipolar recording signal representing a "1", each input "0" resetting the flipflop 20 to cause the amplifier 24 to produce a bipolar recording signal representing a "0". A flipflop 28 is triggered by the "1" output of the flipflop 20 and provides a parity count of the number of groups of "1" 's in the input signal, and if this number is odd, an AND gate 32 causes a "1" to be recorded at clock pulse time CP 9 . A flip-flop 30 similarly provides a parity bit for the number of groups of "0" 's in the input signal, this parity bit being recorded at time CP 8 . At time CP 7 , flip-flop 20 is triggered to record a "space" bit of opposite value to the last (6th) data bit this "space" bit being included in the appropriate parity count; at times CP 8 , CP 9 , parity bits are recorded as described above, and at time CP 10 , flip-flop 20 is reset to cause a "0" to be recorded as an "end" bit. Reading circuit. The information recorded as described is read by a head 40 and produces a playback signal, Fig. 2(d), which is fed to a threshold level detector 44 which detects only those peak amplitudes P1, P4, P5 &C which correspond to the first bit in a group of "1" 's or "0"s, the detector 44 setting a flip-flop 48 at the beginning of each group of "1"s thereby causing "1"s synchronized with clock pulses to be produced at an output 52, the flip-flop 48 being reset at the beginning of a group of "0" 's so that the output at 52, Fig. 2(f), corresponds to the input data. Error detection. Flip-flops 54, 56 count the number of "1" and "0" groups respectively, the totals being compared with the group parity bits recorded at times CP 9 , CP 8  in AND gates 60, 62, 63, 64 an "error" output being produced at a terminal 70 if a difference is detected. In a modified errordetection arrangement (Fig. 3, not shown) no parity bits are recorded, but a circuit comprising a flipflop is provided in the reading circuit responsive to the omission or erroneous addition of a detected peak playback signal, such signals being alternately of opposite polarity if the circuit is functioning correctly.