baber/WOPTO huggingface dataset:
Patent TW-I253470-B (TW)
Title: Polypeptides for increasing protein phosphorylation and nucleic acid moleculars encoding the same
Inventor: WELCHER ANDREW
IPC: G01N33/50
Filed: 2000-12-08
Granted: 2006-04-21
Abstract: The present invention provides interferon-like (IFN-L) polypeptides and nucleic acid molecules encoding the same. The invention also provides selective binding agents, vectors, host cells, and methods for producing IFN-L polypeptides. The invention further provides pharmaceutical compositions and methods for the diagnosis, treatment, amelioration, and/or prevention of diseases, disorders, and conditions associated with IFN-L polypeptides.
Patent TW-512214-B (TW)
Title: Luminaire
Inventor: LAMMERS LIANE
IPC: F21V29/00
Filed: 2000-12-08
Granted: 2002-12-01
Abstract: A luminaire for projecting an image comprises a housing (1) having a light emission window (2). The housing (1) accommodates a light source (3), an optical system (4) for directing light originating from the light source (3) along a longitudinal axis (5), and an image-forming surface (6) which is positioned orthogonally with respect to the longitudinal axis (5). According to the invention, the light source is a LED (3), and the optical system (4) comprises a collimating element (14) for collimating the light originating from the LED (3). Preferably, the luminaire comprises only one LED (3) which, during operation, has a luminous flux of at least 5 1m. Preferably, the housing (1) also comprises a focusing lens (15) for focusing the collimated light originating from the collimating element (14) on the image-forming surface (6) and, preferably, a projection lens (7, 7') for projecting an image of the image-forming surface (6). Preferably, parts of the collimating element show total internal reflection. The luminaire according to the invention is a compact, lightweight, low-energy and low-maintenance luminaire.
Patent TW-517278-B (TW)
Title: Substrate film thickness measurement method, substrate film thickness measurement apparatus and substrate processing apparatus
Inventor: KIMBA TOSHIFUMI
IPC: B24B37/013
Filed: 2000-12-13
Granted: 2003-01-11
Abstract: A jet of water in a cylindrical form is supplied from a jet nozzle onto a measurement surface of a substrate to form a column of the water extending between the nozzle and the measurement surface. Light is emitted from an irradiation fiber and transmitted through the column of water to the measurement surface. The light reflected by the measurement surface is received by a light-receiving fiber through the column of water. A measurement calculation unit measures the thickness of a film formed on the substrate, based on the intensity of the reflected light.
Patent TW-548589-B (TW)
Title: Method for realizing downloading automatic document correlation using registration mechanism on electronic device
Inventor: CHEN HUAI-YAN
IPC: G06F9/355
Filed: 2000-12-22
Granted: 2003-08-21
Abstract: The present invention is a method for realizing downloading automatic document correlation using registration mechanism on electronic device, which uses the download function of the electronic device for downloading the data document and playing engine into the device; and, using an automatic registration mechanism previously stored therein to recognize the data document corresponding to the playing engine, respectively; wherein, the playing engine is registered in a registration table with a type name to be automatically correlated with the matched data document. The data document can find the matched type name in the registration table, and find the matched playing engine based on the type name, so that the electronic device can use the playing engine to explain and execute the data document, and can realize automatically correlating the downloaded data document to the matched playing engine.
Patent TW-473959-B (TW)
Title: Method for packaging flip-chip ball-grid-array chip
Inventor: TSAI YING-JOU
IPC: H01L23/28
Filed: 2001-01-03
Granted: 2002-01-21
Abstract: A method for packaging flip-chip ball-grid-array chip, which can achieve flip chip underfill in the molding process of molded compound by molded underfill without mold flash of the molded compound on the bottom surface of the package unit. The method for packaging flip-chip ball-grid-array is characterized that a dummy pad is formed on the exhaust via on the back side of the substrate, thereby a pad surface with raised height is formed on the solder mask; a trench is then formed on the pad surface of the solder mask. In the molding process, since the molded compound may be completely incorporated by the trench when flowing to the outlet of the exhaust via, it's difficult for it to penetrate to adjacent solder ball. This advantage could ensure the appearance quality of the package unit produced. It also ensures the operating reliability of the semiconductor chip packaged by well electrically soldering the ball-grid-array on the solder pad.
Patent TW-533135-B (TW)
Title: Ink container having pressure regulation device
Inventor: HOU I-CHUNG
IPC: B41J2/175
Filed: 2001-01-08
Granted: 2003-05-21
Abstract: The present invention provides an ink container for an ink jet printing device. The ink container is comprised of a casing in which an ink reservoir is provided for storage of ink. A first venthole, a second venthole, and an ink outlet are provided on the casing. An air bag is provided in the ink reservoir communicated with the first venthole. The first venthole can guide the external air into f the air bag to regulate the pressure in the ink reservoir. The ink container further comprises a resilient constraining device for constraining the air bag to prevent the ink contained in the ink reservoir from leaking out through the ink outlet. An actuation bar is movably provided in the ink reservoir of the casing. A blocking device is provided on the actuation bar in coupling manner for blocking the second venthole of the casing. When the air bag inside the ink reservoir expands to a predetermined extent due to the consumption of the ink of the ink reservoir through the ink outlet, the air bag causes the actuation bar to move. At this moment, the actuation bar pull the blocking device away from the second venthole and then enable the external air to enter the ink reservoir through the second venthole to reduce the volume of the air bag. When the air bag stops moving the actuation bar, the actuation bar returns to its original position, and then enable the blockage device to block the second venthole again.
Patent TW-472422-B (TW)
Title: Semiconductor laser apparatus and method of producing the same
Inventor: KOHASHI IKUO
IPC: H01S5/023
Filed: 2001-02-06
Granted: 2002-01-11
Abstract: In a method of producing a semiconductor laser apparatus, a conductive die-bonding paste is applied to a bonding surface in a predetermined position thereof and then preheated at a temperature equal to or higher than a temperature at which a diluent of the conductive die-bonding paste starts to transpire, but lower than a temperature at which the conductive die-bonding paste starts a thermosetting reaction. Then, with a semiconductor laser chip placed on the preheated conductive die-bonding paste, the latter is heated to be hardened. In the thus produced semiconductor laser apparatus, a highest position at which the conductive die-bonding paste adheres to end surfaces of the semiconductor laser chip is at a height of more than 0.01 mm from the bonding surface, but is below lightemitting points of the semiconductor laser chip.
Patent TW-476049-B (TW)
Title: Coin sending-out apparatus
Inventor: MAKI TADANORI
IPC: G07D1/00
Filed: 2001-03-13
Granted: 2002-02-11
Abstract: This coin sending-out apparatus is equipped with a drum-shaped rotating body that can accommodate not only coin of a specific size but also coin of tolerable different sizes. This drum-shaped rotating body (1) rotates in a plane parallel to a vertical plane with a plurality of coins (CN) accommodated therein. Coin receptacle portions (6) and coin press-holding projections (12) for pressing a coin (CN) in the coin receptacle portion (6) are provided at the inner surface of the peripheral wall (2) of the drum-shaped rotating body (1). In accordance with the rotation of the drum-shaped rotating body (1), the coin (CN) is pressed against the inner surface of the peripheral wall (2) by coin press-holding projection (12), and then released at the upper portion of the drum-shaped rotating body (1). Immediately before the release, a coin hitting member hits the coin (CN) and the coin press-holding projection (12) urges the coin (CN) toward the side of the drum-shaped rotating body (1), i.e., toward the front of the coin sending-out apparatus (A). Thus, the coin (CN) jumps out of the apparatus.
Patent TW-518868-B (TW)
Title: Transmission circuit and its method, reception circuit and its method, and data communication apparatus
Inventor: KUMATA ICHIRO
IPC: H04L7/02
Filed: 2001-04-03
Granted: 2003-01-21
Abstract: The object of the present invention is to provide a data communication apparatus of a new configuration which is able to transmit data while carrying out frame synchronization. To achieve the object, the transmission circuit of the data communication apparatus converts parallel data TXD0-7 equivalent to one frame into serial data based on load signal TXLD, and then sends out the serial data in a manner corresponding to the clock signal. Following the serial data, the transmitting circuit immediately transmits frame synchronization data (/TXD7, TXD7) varying several times in the interval a-b from an edge of a clock signal SCK to an edge of the next clock signal. When the value of the data SD transmitted from a signal line is changed for two or more times in the time interval a-b, the receiving circuit generates load signal RXLD. The transmission circuit sequentially performs latch operations on the serial data from the signal line in a manner corresponding to the clock signal SCK, and then converts the latched serial data into parallel data RXD0-7 based on the load signal RXLD.
Patent TW-552668-B (TW)
Title: Methods for forming an integrated circuit and an electronic device and methods for defining an electronic circuit from an electronic device array and defining an electronic device from a substrate or an electronic device array
Inventor: SIRRINGHAUS HENNING
IPC: H01L21/76
Filed: 2001-04-20
Granted: 2003-09-11
Abstract: A method for forming an integrated circuit including at least two interconnected electronic switching devices, the method comprising forming at least part of the electronic switching devices by ink-jet printing.
Patent TW-555671-B (TW)
Title: Apparatus and method for manufacturing high tension bag material
Inventor: SHIU TSAI-CHI
IPC: B65B47/02
Filed: 2001-05-16
Granted: 2003-10-01
Abstract: Discloses is an apparatus and a method for manufacturing high tension bag material, the apparatus including: a first material feeding mechanism; a second material feeding mechanism provided in a feeding path of the first material feeding mechanism; a corresponding rolling mechanism provided at a downstream of the second material feeding mechanism; and a material reeling mechanism provided at a downstream of the rolling mechanism for delivering a reeled net placed in the first material feeding mechanism. A plastic film is fed by the second material feeding mechanism in the process of delivering the net. The rolling mechanism then heats up and rolls over the net and plastic form by thermal pressing. The sub-assembly is then cooled off by a cooling device to join the plastic film to the net. The final assembly is then reeled up by a material reeling mechanism to accomplish a method for manufacturing high tension bag material.
Patent TW-517222-B (TW)
Title: Method and apparatus for reducing aliasing in cascaded filter banks
Inventor: SCHULLER GERALD DIETRICH THOMA
IPC: G10L25/18
Filed: 2001-06-01
Granted: 2003-01-11
Abstract: A method and apparatus are disclosed for reducing aliasing between neighboring subbands in cascaded filter banks. An alias reduction filter bank is included to reduce the aliasing components between different subbands. Generally, the magnitude response and phase of the alias reduction filter bank is similar to the magnitude response of the synthesis filter bank of the first stage filter bank. The alias reduction filter bank filters and adds the signals from a set of M2 subbands from the M1 subbands of the first stage analysis filter bank. A higher frequency resolution is obtained after the alias reduction stage by a following analysis filter bank. The signals of these subbands are first fed into an alias reduction filter bank to reduce the aliasing. If the first stage filter bank is a modulated uniform filter bank with M1 bands, and the stage for alias reduction has M2 bands, then to obtain alias cancellation, the alias reduction filter bank has to have a similar frequency response as the synthesis filter bank for the first stage, but with the frequency scaled by the ratio of the sampling rates, M1/M2. After the alias reduction filter stage, an analysis filter bank to obtain a higher frequency resolution follows. A synthesis filter bank for the first stage analysis filter bank can be ""thinned out"" by keeping only every M1/M2<SP>th</SP> sub-structure to obtain the alias reduction filter bank.
Patent TW-506128-B (TW)
Title: Manufacturing method of high-quality thin film type bulk acoustic wave device
Inventor: LIN TZUNG-SHIAN
IPC: H03H3/02
Filed: 2001-06-15
Granted: 2002-10-11
Abstract: A manufacturing method of high-quality thin film type bulk acoustic wave device is disclosed, wherein locally defining the bottom electrode passivation layer or the one without the bottom electrode passivation layer is utilized to increase the quality factor of the bulk acoustic wave device, which comprises the following steps: deposit on the substrate and define the sacrificial layer; form the supporting layer, bottom electrode pattern, bottom electrode passivation layer; the bottom electrode passivation layer is defined by using microlithography technology so that the bottom electrode passivation layer can contact with the piezoelectric layer afterwards; deposit the piezoelectric layer and apply microlithography technology to define its shape; deposit and define the shape of upper electrode; open the etch window of the etch sacrificial layer; remove the sacrificial layer in the way of dry etching or wet etching to create the sacrificial layer cavity; and etch the substrate by using positive etching.
Patent TW-531850-B (TW)
Title: Buried bit line-field plate isolation defined active semiconductor areas
Inventor: MANDELMAN JACK A
IPC: H01L27/108
Filed: 2001-06-15
Granted: 2003-05-11
Abstract: Active areas of a dynamic random access memory (DRAM) formed on a semiconductor substrate are defined by buried bit lines on two sides and by conductors separated from the semiconductor substrate by electrically insulating layers on two other sides. The conductors are electrically biased during operation of the DRAM to cause portions of the semiconductor substrate therebelow to increase in majority carrier concentration and thus to inhibit inversion thereof. Each buried bit line is formed in a trench in the semiconductor substrate. Each trench houses a separate bit line and is lined with an electrical insulator and has a conductor in a bottom portion thereof.
Patent TW-506047-B (TW)
Title: Integrated circuit vertical trench device and method of forming therof
Inventor: TEWS HELMUT HORST
IPC: H01L21/8242
Filed: 2001-07-03
Granted: 2002-10-11
Abstract: A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.
Patent TW-548932-B (TW)
Title: Method for controlling information, information processing apparatus, and information control system
Inventor: NAKANO TAKEHIKO
IPC: H04L12/64
Filed: 2001-08-13
Granted: 2003-08-21
Abstract: The object of the present invention is to allow the information equipment to properly operate from control equipment side even when the information equipment has a plurality of sections to be controlled and a plurality of control equipments exist. When the information equipment 1 selects a section that the control equipment 10 wants to control from a controlled section selecting means supplied to the control equipment 10, the selected information and the identification information of the selected control equipment 10 are transmitted to the information equipment 1. Upon receiving the information, the equipment 1 preserves the identification information of the selected section to be controlled and the identification information of the control equipment 10 as a control table in a RAM 1(5) by correlating the information with each other. Whenever the control equipment 10 selects a section to be controlled, the information equipment 1 repeats the selection, transmission, and preservation. When the information equipment 1 receives a control request from the control equipment 10, the equipment 1 controls the section to be controlled corresponding to the identification information issued from the control requester by referring to the preserved control table.
Patent TW-I235381-B (TW)
Title: Non-volatile semiconductor memory device
Inventor: KOJIMA MAKOTO
IPC: G11C7/00
Filed: 2001-08-28
Granted: 2005-07-01
Abstract: The present invention provides a non-volatile semiconductor memory device that won't generate over-erase and has an excellent repair efficiency even if the semiconductor memory unit along the bit direction is replaced. The memory device includes erase bias circuits 101-10n for erasing the data in regular memory unit arrays 71-7n and lengthy memory unit array 8, erase decode circuits 121-12(n-1) for decoding the bad address data, and lengthy control circuits 111-11(n-1) receiving the bad address in accordance with an erase decode signal so as to switch and control the erase bias circuits and serially connected in a way using the front end to control the back end. While erasing data, the lengthy control circuit will switch and control the erase bias circuit to prevent from applying the erase bias to the bit lines and the source lines 9, 9R. The bit lines and the source lines 9, 9R are connected to the regular memory unit arrays replaced by the lengthy memory unit array or to a control gate of the unused lengthy memory unit array.
Patent TW-I244513-B (TW)
Title: Poly(trimethylene terephthalate) tetrachannel cross-section staple fiber
Inventor: HERNANDEZ ISMAEL A
IPC: D03D15/00
Filed: 2001-08-30
Granted: 2005-12-01
Abstract: Poly(trimethylene terephthalate) tetrachannel cross-section staple fibers and their manufacture, as well as yarn, fiberfill webs or batts, and fabrics made therewith.
Patent TW-555948-B (TW)
Title: Jetting cooling device and method of controlling same
Inventor: KUO JU-CHIA
IPC: F24F3/048
Filed: 2001-09-04
Granted: 2003-10-01
Abstract: This invention provides a jetting cooling device and method of controlling same, wherein the jetting cooling device is implemented in a low-temperature warehouse and includes: a cooler, a first sensor, a second sensor and a control valve. The cooler includes an air outlet provided in the low-temperature warehouse. The first sensor is used to detect the temperature (or wind velocity) at the air outlet of the cooler. The second sensor is used to defect the temperature (or wind velocity) at a preset location of the low-temperature warehouse. The controller is electrically connected to each of the cooler, first sensor and second senor to determine whether to adjust the size of the air outlet of the cooler based on the temperature (or wind velocity) deviation between the temperatures (or wind velocities) measured by the first and second sensors. The method of controlling the jetting cooling device uses the above jetting cooling device and includes the steps of: setting the maximum and minimum temperature (or wind velocity) deviation of the controller; determining the temperature (or wind velocity) deviation between the temperatures (or wind velocities) measured by the first and second sensors; adjusting the size of the air outlet of the cooler when the temperature (or wind velocity) deviation is greater than the maximum temperature (or wind velocity) deviation or less than the minimum temperature (or wind velocity) deviation, so as to change to an appropriate jetting distance and to ensure even temperature throughout the low-temperature warehouse.
Patent TW-523849-B (TW)
Title: Inspection device and manufacturing method for semiconductor integrated circuit device
Inventor: BAN NAOTO
IPC: G01R1/073
Filed: 2001-09-27
Granted: 2003-03-11
Abstract: The present invention provides a low cost inspection device and manufacturing method for semiconductor integrated circuit device, wherein, for wafer welding, the method can completely contact the separated contactors with the wafer, and correct each contactor to improve the yield of the contactors to reduce the manufacturing cost. In the cassette structure with mechanical pressing are composed of a plurality of separated silicon contactor blocks 1 and the unified guide frame 2, wherein using the whole wafer contacting method with unified separated contactors, each silicon contactor block 1 operating independently will be mechanically pressed during the wafer welding, so that each probe of the silicon contactors and each inspection pad for each chip of the inspected wafer 4 are uniformly contacted with a specific pressure to supply the testing control signal to each chip, and conducting welding inspection with the resulting test signal.
Patent TW-548660-B (TW)
Title: Super low-power generator system for embedded applications
Inventor: HSU LOUIS LU-CHEN
IPC: G11C8/08
Filed: 2001-09-28
Granted: 2003-08-21
Abstract: A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.
Patent TW-I257849-B (TW)
Title: Pesticidal composition
Inventor: KNAUF WERNER
IPC: A01N53/00
Filed: 2001-09-28
Granted: 2006-07-11
Abstract: Pesticidal compositions comprising deltamethrin and acetamiprid.