Patent GB-1222656-A (GB)
Title: Improvements in or relating to pulse corrector circuits
Inventor: BARRETT JOHN ALBERT
IPC: H04Q1/36
Filed: 1968-03-13
Abstract: 1,222,656. Impulse correction in telephone systems. PLESSEY TELECOMMUNICATIONS RESEARCH Ltd. 12 June, 1969 [13 March, 1968], No. 12303/68. Heading H4K. An impulse corrector comprises two delay circuits 18, 19, time out of 19 initiating the timing action of 18, and is such that, if the sum of the mark and space intervals of a received pulse train exceeds the sum of the delay circuit timed intervals, the regenerated pulse train has break pulses of a duration equal to the timing period of delay 18, while if the mark-space sum of received pulses is less than the sum of the delay circuit times the regenerated pulse train has make intervals equal to the timing period of delay circuit 19. NAND gates are employed such that produce a negative output only if both inputs are positive. The delay circuits respond to a negative input to produce a negative output for the period of the delay. Circuit 1 with delay circuit 16, inverter 10, and NAND 11, produces a negative output if a negative make signal is applied to for a period in excess of the timing circuit 16. Occurrence of a break following a make switches the output of 11 to positive without delay. Circuit 2 relays the make signals and ignores breaks unless they exceed the duration of delay circuit 17. The received impulse train, tested for duration of make intervals and cleaned of transient breaks, is passed with inverted polarity (breaks negative and makes positive) to the pulse correcting circuit 3 where a bi-stable 4 gives the regenerated pulse train output and where capacitors 20, 21 in combination with the bi-stable are such the bi-stable is set or reset over the capacitors only in response to negative going changes of voltage. A continuous break input is repeated by 4 as the negative input to circuit 3 sets off delay 19 and while its initial occurrence sets 4 to state M over capacitor 20, 4 is set to B when 19 times out and switches from negative to positive output, inverter 15 giving the required bi-stable input. Delay 18 is set off when bistable 4 is switched to B but, as the negative break input persists, gate 14 is necessarily closed and time out of 18 has no effect. An off-hook make input resets bi-stable 4 directly to M as gate 14 is primed with positive from delay 18 when inactive. The first break impulse starts delay timer 19 and is relayed over capacitor 20 without effect as bi-stable 4 is already set to M. When 19 times out bi-stable 4 is set to B and delay timer 18 is started. If the break impulse is still present when 18 starts timing but is absent when it times out, gate 14 receives positive inputs and switches its output to negative to switch 4 to M having measured a regenerated break impulse equal to the delay 18. The next received break impulse sets of 19 and 18 in sequence to produce a similarly timed regenerated break impulse, and so on for further received impulses. If, however, the received break impulse has ceased already by the time that 18 starts timing the usurping make interval will find gate 14 primed positive by 18 but has no effect as 4 is already set to M. When 19 times out 4 is set to B. In these circumstances 18 times out in the presence of the next occurring break impulse which over 20 sets 4 to M direct at the same time as it starts up the timing of delay 19. The make intervals for a regenerated pulse train of such higher repetition rate are therefore of the duration of the delay time of circuit 19. Figs. 4 and 5 (not shown) illustrate a design for the arrangement of Fig. 1 which provides a bipolar output for the regenerated pulse train and does not employ the capacitors 20, 21, such design being suited to production by micro-electronic techniques.