Patent GB-1284257-A (GB)
Title: Semiconductor logical circuits
Inventor: BERGER HORST HEINZ
IPC: G11C11/411
Filed: 1971-04-19
Abstract: 1284257 Semi-conductor integrated logic circuits INTERNATIONAL BUSINESS MACHINES CORP 19 April 1971 [5 May 1970] 26988/71 Heading H3T [Also in Division H1] A monolithic semi-conductor logic circuit includes a first layer of one conductivity type containing two spaced regions of the opposite conductivity type forming the emitter and collector of a lateral transistor structure, the collector region of the lateral transistor serving as the base region of a vertical transistor structure and containing a zone of the first conductivity type serving as the collector of the vertical transistor, part of the first layer serving as the base region of the lateral transistor and as the emitter of the vertical transistor. The circuit is operated by connecting the first layer to a reference potential and connecting a current source to the emitter of the lateral transistor, the input being connected to the base of the vertical transistor and the output being taken from the collector of the vertical transistor. This basic device operates as a current sinking NOT circuit and the outputs of two or more such devices may be connected directly together to produce a positive logic NOR gate. The output is connected directly to the input of the next gate, no "pull-up" device being necessary. No isolation is required between the separate devices. As shown, Fig. lb, a NOR gate comprises an N-type substrate N1, diffused P-type regions P1, P2, P3 and diffused N+-type regions N2, N3 and N + . One basic device comprises a lateral transistor T1 formed of regions P1-NI-P2 and a vertical transistor T2 formed of regions N1-P2-N2. The second basic device comprises a lateral transistor T3 formed of regions P1-N1-P3 and vertical transistor T4 formed of regions N1-P2-N3. The substrate is earthed via contact N + and a constant current is fed to region P1 which forms the emitter of both lateral transistors T1, T3. The collector regions N2, N3 of the vertical transistor are connected together and form the output of the circuit. When the input terminal E1 of the first device is earthed the bias current I flows between region P1 and terminal E1 and transistor T2 is cut off. When the input terminal E1 is allowed to float the bias current I flows into region P2 and forward biases the emitter junction of transistor T2 which saturates. The second basic device T3, T4 responds in the same way to inputs applied to terminal E2 so that the output at terminal A is low whenever either of the inputs is floating and high (floating) only when both inputs are earthed. The basic device may be modified by providing each vertical transistor with two or more collector regions which are effectively decoupled from one another so that they can be independently connected to other devices to form different logic functions. A single P-type region may provide the emitter region of several lateral transistors. Suitable circuit layouts for a half adder, Fig. 3 (not shown), and a three input decoder, Fig. 5 (not shown), are described.  The substrate may comprise an N- or N - type body, an N -type epitaxial layer on an N + -type body, an N-type epitaxial layer on a P-type body or a three layer structure comprising an N-type epitaxial layer formed on a diffused N+-type sublayer diffused into the surface of an N- or P-type body. The circuit may be improved by forming an N+-type ring surrounding the base region of the vertical NPN transistors and these base regions may extend as far as an N+-type buried layer. The emitters of the lateral transistors may be fed from separate sources or may be fed in parallel from a voltage source by means of a single external or internal resistor.