Patent GB-1378648-A (GB)
Title: Optical data transmission system
IPC: H04L7/033
Filed: 1971-12-07
Abstract: 1378648 Optical data link COMPUTER TRANSMISSION CORP 7 Dec 1971 [25 Jan 1971] 56739/71 Heading G1A The invention relates to a data transmission system in which communication is provided between a central computer and remote terminals over optical links.  Construction of transmitter/receiver assembly. Two arrangements (10, 30) Fig. 1 (not shown), of optical transmitter/receivers are mounted in aligned relationship on roof tops. Each is connected by cable (35) to a computer interface unit (13, 34) by cables (12, 35). A unit (10 or 30) comprises a side-by-side arrangement of an optical diode, e.g. of gallium arsenide, at one end and a collimating lens at the other, and a receiver using a photo-responsive, e.g. silicon, diode. The preferred wavelength range is infrared at 900nm. The assemblies are fitted with telescopes and are adjustable in position, Figs. 4-6 (not shown). General circuit, transmitter/receiver assembly, Fig. 3. The transmitter logic 70 in the interface unit 11  receives clock, frame and data inputs, and controls transmitter amplifier 76. The receiver amplifier 84 feeds computer interface 11 at phase-locked loop circuit 90 and data detector 91, to provide data, clock and frame outputs from receiver logic 92, and indicate any errors at 100 if error logic 96 detects these (e.g. out-of-synchronism, loss of signal etc). Immediate transmitter and receiver circuitry. The transmitter circuit includes a pulse shaper feeding an inverter and two stage amplifier applying pulses across the photo-emitter diode, Fig. 11 (not shown). The receiver circuit comprises a two field-effect transistor amplifier 140, with Zener diode voltage regulation 144, followed by two amplifier stages and impedance matching transistor 143. Transmitter interface, Figs. 7, 8. The purpose of the circuit is to transform input data in the form of a sequence of bits (two level signal) into a sequence of pulses, the phase of a pulse within its cycle representing a respective binary digit. (Pulse in third quarter of cycle, O; in first quarter of cycle, 1). Thus the circuit transforms waveform A to waveform J, Fig. 8. Input data bits are supplied on lines 73 to AND gates 78, 79. The bits are to be synchronized either with pulses from internal clock 74 or those supplied on line 73C from the data source. Receiver interface, Fig. 9. Detected radiation produces a pulse sequence on line 85 which is fed to synchronous detector 140 which is also supplied with a reference waveform derived from the phase lock loop circuit 90. Thereby, a signal D representing the data as in J, Fig. 8, is provided. To translate this into a form suitable for the computer (i.e. as A in Fig. 8), the signal passes via AND gate 156, and flip flop 162 to four stage shift register 163. The content of this is sampled for each bit of information to check that it contains a valid pulse sequence, by comparing it with clock pulses J derived via phase lock loop 90 and circuit 153. If the valid code is detected in time with clock J, the data pulse sequence is enabled to advance from lead 95. If the timing is incorrect a lamp 100 is lit and a clock adjusting pulse over 171 to gate 170 is provided. The phase lock circuit 90 is provided for detecting the phase of the incoming pulses to provide clock pulses and reference signals so that the data bits may be detected. Provision for testing internal and loop operation, e.g. by coupling the receiver to its associated transmitter, is comprised by circuits 180-183. (For Figures see next page)