Patent GB-1408635-A (GB)
Title: Display systems
IPC: G09G5/00
Filed: 1972-09-15
Abstract: 1408635 Digital data storage TEXAS INSTRUMENTS Inc 15 Sept 1972 [22 Sept 1971] 42957/72 Heading G4C [Also in Division H4] Relates to a system for displaying a twodimensional field of view by scanning said field to produce corresponding time varying video signals which are converted to corresponding sequential digital data words which are stored in a digital memory and then repeatedly read out to the display, the memory locations being specified by an address code having two parts corresponding to the two co-ordinates, e.g. range and azimuth, of corresponding image segments and each address part having a predetermined range of values. According to the present invention during data storage the value of the first part of the address code is varied through its entire range for each discrete value of the second part of the address code and during data read-out this sequence is inverted, i.e. the value of the second part is varied through its entire range for each discrete value of the first part, so that the storage and read-out modes are orthogonal. The sequential values of the two parts of the address code are derived from separate (interconnected) counters 32, 34 and preferably separate pairs of counters 32B, 34A and 32A, 34B, Figs. 4A and 4B, are used for storage and read-out.  The invention is described as applied to producing a flicker-free sector PPI cathode-ray tube (CRT) display for an azimuth-scanning pulse radar (or equivalent infra-red system), in which the memory read-out period, e.g. 0À016 sees, is much less then the radar sector scan period, e.g. 0À5 sees. Considering a system in which the radar sector display, Fig. 2, is divided into 65,536 image segments 29 defined by the intersection of 512 range scan segments 26 and 128 azimuth scan segments 28 with 16 range scans per azimuth scan segment, during each range scan period the radar video is converted at 20 into 512 3-bit range data words and during each azimuth scan segment period the 16 words corresponding to any one range scan segment are integrated at 22, the resultant 512 integrated words being then transferred sequentially to a main random access digital memory 24 via a logic unit 30 controlled by range and azimuth address counters 32, 34, and the duration of the transfer-storage period, e.g. 150 Ás being much less than the azimuth scan segment period, e.g. 4ms. The high-speed orthogonal read-out is interrupted only during the short transfer-storage periods and the sequential set of read-out data words corresponding to any one range segment are applied via a D/A converter 40 to the CRT display 27 to intensity modulate an arcuate trace (of radius corresponding to said range segment), produced by deflection circuits 48 controlled by a digital differential analyser 36 responsive to the logic unit 30, the position of the origin O, Fig. 2, of the display being controlled by bias signals on line 54. The display may be "frozen" at any time by inhibiting updating of the memory 24. In order to reduce the number of range and azimuth addresses to 256 and 32 respectively, Figs. 4 and 5 (not shown), the data corresponding to two adjacent range segments x, (x + 1) and four adjacent azimuth segments z, z + 1, z + 2, z + 3 are combined in a single 24 (= 2 Î 4 x 3) bit composite memory word, Fig. 3 (not shown). Each transfer-storage period is now divided into 256 sequential cycle-time periods each of duration 0À6Ás and during any one cycle-time period the corresponding two range data word components in the appropriate azimuth segment portion of the corresponding composite memory word are updated, the selection of the appropriate azimuth segment portion being effected by a divide by four counters 41, Fig. 4A, interconnecting the storage range and azimuth address counters 32B, 34A. Similarly during the display read-out periods the appropriate azimuth and range components of each composite memory word are selected by dividers 45 and 43, Fig. 4B, coupled to the read-out azimuth and range address counters 34B, 32A.