Patent GB-1181983-A (GB)
Title: Improvements in or relating to Data Processing Circuit Arrangements
Inventor: ARNOLD JOHN SPENCER
IPC: G06F11/18
Filed: 1967-06-28
Abstract: 1,181,983. Automatic exchange systems. AUTOMATIC TELEPHONE & ELECTRIC CO. Ltd. 15 Aug., 1968 [28 June, 1967], No. 29961/67. Heading H4K. [Also in Division G4] A data processing system includes a plurality of pairs of processors and a number of functional units, a first pair of processors being capable of addressing successively the functional units of a first group of such units and of a second group, and a second pair of processors being capable of addressing successively the functional units of the first group and of a third group. First, second and third groups of outgoing junction reed-relay sets in an automatic telephone exchange have 16, 64, 64 relay sets, respectively. Each of four processors executes an 80-step addressing cycle. The first 16 steps in each processor are used for addressing the 16 relay sets of the first group respectively. The remaining 64 steps of the first and fourth processors are used for addressing the 64 relay sets of the second group, respectively, and the remaining 64 steps of the second and third processors are used for addressing the 64 relay sets of the third group, respectively. In each processor a 256-step clock-driven sequence counter controlling operations is cycled through for each step of the addressing cycle, steps 3-253 of the counter being skipped if no change is required in the addressed relay set, the 256th step incrementing two binary counters (having 5 and 16 steps respectively) used for 2-co-ordinate addressing of the relay sets served by this processor. The sequence counter causes a word corresponding to the relay set to be read from memory, the word containing an identifier for the programme routine currently being used to control the addressed relay set, and a meter count. The routine causes control signals to be sent to the relay set if necessary (steps 3-253 of the sequence counter not being skipped in this case), and the word is updated if necessary and written back into memory. Updating of the routine identifier in the word is in accordance with jump instructions in the current routine and two information signals from the addressed relay set. During the first 16 steps of the addressing cycle, the control signals (if any) sent to the relay sets by the processors are compared by comparison of the first processor with the second, the second with the third, the third with the fourth, and the fourth with the first, a faulty processor being identified and taken out of service. For example, disparity between the first and second, and between the fourth and first together indicate the first is faulty. The control signals are sent to the relay sets on the row wires used in the co-ordinate addressing, so the comparisons check these wires. The column wires are effectively checked since a fault will eventually alter the information signals referred to causing incorrect jumps between the programme routines which will produce disparity in the comparisons. All the row and column wires can be checked in this way since all the wires can be used in the first 16 steps of addressing cycles. The relay sets may be controlled in the above way for metering, and sending N.U. tone. The sequence counters in the different processors are synchronized periodically.