Patent GB-1386716-A (GB)
Title: Traffic signal control system
IPC: G08G1/081
Filed: 1973-03-14
Abstract: 1386716 Traffic signal control systems OMRON TATEISI ELECTRONICS CO 14 March 1973 [16 March 1972] 12252/73 Heading G4Q In a system for controlling traffic signals 600, 601, 602 (Fig. 1) at a multiplicity of intersections, a computer 100 counts the phase times and generates phase-advance signals upon each phase time count-out, a fail-safe apparatus 200, in which phase times are preset, receives the signals generated by the computer, commences to count phase times in synchronism with said computer and generates phase-advance signals in synchronism with said count-out and switching means operates, to transmit to the traffic signals, the signals from the computer while the latter is operating normally and the signals from the fail-safe apparatus when the computer fails. The switching function is derived from signals S1 provided by the computer : signals S1 are present at AND-gates 500, 501, 502 when the computer is operating to block the passage of phase-advance signals SF1-SF3 from the fail-safe apparatus, and are absent when the computer fails. When the computer is operating, phase-advance signals SC1-SC3 generated thereby pass to OR-gates 400, 401, 402 whose second inputs are connected to the outputs of AND-gates 501, 502, 503, and control parameters pass from the computer to the fail-safe apparatus via bus and control lines BL, CL. In the fail-safe apparatus (Fig. 2), the times of phases are set in registers 1-6, being transmitted thereto via bus line BL1 from the computer. A counter 7, which counts the phase times, is advanced by pulses from a clock 8 and is reset each time a counter 9 advances to open, successively, AND-gates 31-36 connected to the outputs of registers 1-6. The output from a register 1-6 is thus passed to a coincidence circuit 17 which also receives inputs from counter 7. Thus, when the count produced by the counter 7 is equal to the preset phase time transmitted from a register 1-6, coincidence circuit 17 produces an output which is a phaseadvance signal. Pulses from clock 8 are converted to "percent pulses" by a frequency divider 10 controlled by a decoder 11 which receives signals from the computer via a bus BL2. The "per cent pulses" are gated into counter 7 by gate circuits 12-14 of which the circuit 13 receives, at one input, signals from a flip-flop 15 which is set by the phase-advance signals SC from the computer and reset from the coincidence circuit 17. Since the counter 7 is reset by the computer phase advance signals SC, the signal at the output of the coincidence circuit 17 appears simultaneously with the computer signals SC. When the computer fails, counter 7 continues to advance in accordance with the "per cent pulses" regardless of the state of flipflop 15 and, since the phase state of the fail-safe apparatus is exactly in step with the phase state of the traffic signals at every time, the switching of the control from the computer to the fail safe apparatus proceeds smoothly. The system can provide off-set signals for controlling a plurality of traffic signals along a traffic flow route. The times preset in the registers 1-6 may, as an alternative to being set by the computer, be set manually.