Patent GB-1333873-A (GB)
Title: Synchronising pulse separator
IPC: H04N5/08
Filed: 1971-01-15
Abstract: 1333873 Television PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 15 Jan 1971 [19 Jan 1970] 2045/71 Heading H4F In a sync pulse separator comprising a peak level detector and a porch level detector the outputs of which are combined to form a reference level for an amplitude selection circuit so that the sync pulses are sliced at a level between the peak and porch levels, the porch level detector is controlled by a periodically recurring selection signal obtained from the video input by a second amplitude selection circuit which forms part of the peak level detector. Both the peak and porch level detectors may be constructed as D.C. restorers. As shown, Fig. 3, the peak detector 9 is connected to the video signal input 1 and contains a transistor 87 which conducts during the sync pulses to charge capacitor 93 to the peak level and produce negative going sync pulses at terminal 97. The porch detector 5 is also connected to the video signal input 1 and contains a transistor 73 which conducts except when cut off by the negative going sync pulses produced by the peak detector so that the signal at its collector is the input video signal with the sync pulses inverted and the porch level becomes the most negative part of the waveform so that this level is stored on capacitor 83. The outputs of the two detectors are combined by resistors 101 and 103 to produce a voltage between peak and porch levels which is applied as a reference to amplitude selection circuit 13 in which transistor 111 is cut off or saturated depending on whether the input video signal is above or below the reference level thus producing separated sync pulses at output 57. Since the porch detector capacitor 83 is in a circuit with a long time constant it can not follow relatively fast variations (e.g. hum) in the porch level and to overcome this capacitor 83 is supplied with the peak level voltage by means of emitter followers 105, 107 from capacitor 93 which is in a shorter time constant circuit. In a modification, Fig. 4 (not shown), the detectors are arranged as D.C. restorers. The peak level detector passes a video signal in which the peaks of the sync pulses are held at a reference voltage level. The output of the peak detector is applied to the porch detector which passes a video signal in which the porch level is held at the reference voltage level, this detector including a capacitor charged by a circuit including a transistor switch which is cut off during the sync pulses which are obtained from the peak detector. The outputs of the peak and porch detectors are combined to give a video signal in which a point between the peak and porch levels is held at the reference voltage level and this signal is then applied to the amplitude selector which slices it at the reference voltage level. A switch may be included between the porch or peak detector and the combining network or in the input of the porch detector to disable the circuit without disturbing the charges on the detector capacitors during interference suppression pulses which may have removed the sync pulses in the video signal so that false sync pulses are not generated. in Fig. 1 (not shown), which is used to explain the operation of the basic circuit, simple porch and peak detectors are used and the amplitude selection circuit comprises a differential amplifier.