Patent GB-1415860-A (GB)
Title: Time division multiplex communication systems
IPC: G11C19/08
Filed: 1972-11-28
Abstract: 1415860 Automatic exchange systems WESTERN ELECTRIC CO 28 Nov 1972 [2 Dec 1971 27 Dec 1971] 54868/72 Heading H4K In a TDM switching system, each time slot includes one bit position whose content indicates the free/busy state of the slot. The state information is utilized in path finding logic circuits associated with central stages of a multistage network in order to find a free path without invoking time or space in an overall system controller whether this be of the wired logic or stored programme type. The invention is particularly applicable to systems using singlewall magnetic domain devices as time slot interchangers. System description Fig. 1.-A plurality of groups of subscribers 33 are connected to respective multiplexons 31 which have appearances on the first stage TSI 1  of a time division switching network. Each multiplexon has an associated circuit 36 which is effective to write, a "1" or a "0" in the busy bit position of every time slot emitter by the multiplexor in dependence on whether or not that slot is in use for a connection. "Useage" here means "allocated to a call" it being irrelevant whether there is any actual information contained in the slot. The interchangers TSI 1  shift the relative positions of N incoming slots and emit them in a frame of M slots (the value of M determines the network blocking, M = 2N being the non-blocking criteria) to a parallel serial converter SP1. This causes like-numbered slots in all the highways 11 to be inserted serial fashion into a respective one of the second stage time slot interchangers  TSI 2 . The opposite of the above processes occurs through the rest of the network.  System operation.-A processor 16 armed with calling and called party addresses enables selection logic 23 and 27 to hunt for free time slots at the output and input respectively of the first and last switching stages by examining the condition of each slot's busy bit. AND gate 26 notes any coincidences and notifies logic 17 which then inserts the just found slot identity and the calling and called side's slot numbers into recirculating control memories for the first and last stage switches and also the identities of the corresponding slots through the central stage in the latter's control memory. The call continues until the calling party hangs up whereupon the removal of the busy bit from his time slot leads to the break-down of the connection by removal of the information in the control memories. A more detailed description of the network, which utilizes magnetic domain structures, will be found in the Specifications 1,415,859 and 1,415,858. Time slot interchanger Fig. 3 converts incoming serial data bits on a highway 11 into parallel data bits each of which is switched separately. The bits of each data channel, i.e. a time slot, are shifted through shift register 60 and then read-out in parallel at the end of each time slot into respective interchangers 67 ... 68. The latter each comprise an input shift register 69 which has the capacity to store a full frame of like-numbered bits taken one from each slot of the frame. At the end of each frame the register 69 is read out into buffer 73 whereafter the bits are read out selectively via gates 76 ... 77 into a shift register 78 so as to obtain the desired time slot interchange. The control of each gate 76-77 is vested in a respective recirculating memory 80-81. It will be appreciated that likenumbered gates in all the interchangers 67-68 are operated in synchronism so as to ensure that the bits of a same time slot are shifted through the network together. Interchanger control circuits Fig. 3.-When a new connection is to be set up via the interchanger, the processor primes a monostable multivibrator 92 so that at the start of the next frame signals are injected into shift registers 69<SP>1</SP> and 6911. Both registers are gated to respective buffers 73<SP>1</SP> and 73<SP>11</SP> in response to a signal TSi which occurs at a time corresponding to that of the time slot of the incoming channel on highway 11. During the course of the succeeding frame, buffer 73<SP>11</SP> is gated to a shift register 77<SP>11</SP> at a time TS 0  corresponding to the time slot of the outgoing to which the incoming channel must be connected. The bit thus transferred into 78<SP>11</SP> traverses therein the complement with respect to its passage through 69<SP>11</SP> and eventually is able to gate open buffer 73<SP>1</SP>. One of gates 76<SP>1</SP>-77<SP>1</SP> is thereby opened in order that a control bit may be inserted into a corresponding recirculating memory 80-81 whereby a respective transfer gate 76-77 may thereafter be repeatedly opened by the appearance of the bit at the output of the memory. It will be remembered that one bit position of each time slot indicates the free/busy state of the slot and it is assumed that this bit corresponds to the gate 63 output of input shift register 60. In the course of a frame, shift register 88 is filled with a pattern of channel free/busy bits from gate 63 and this pattern is held by buffer 89 during the succeeding frame in order to open gates 86-87 in the recirculation paths of memories 80-81. It is suggested that the busy bit of every slot be artifically marked busy by injection gate 102 (which may alternatively be located in the path 106 from gate 63 to register 103) during 99 out of every 100 frames. This would prevent a control memory from being emptied inadvertently due to the loss of a genuine busy bit in its passage through the system, at least during 99% of frames. Since there is no control bit an a memory 80-81 for a free time slot there is no possibility of the artificial busy bit being sent on by the interchanger even though it does get as far as a buffer 73. It is further suggested that as no regard is paid to the contents of the busy bit position for 99 frames then this position may be used for other supervisory purposes during these frames. It is not however reconciled how path finding can be effected in these circumstances. Pathfinder Fig. 4.-In this arrangement the outputs and inputs respectively of parallelserial converter SP 1  and SP 2  are examined for free time slots rather than their inputs and outputs respectively as was the case in Fig. 1. In addition time addressing rather than space addressing is adopted by the processor thus reducing the wiring requirements. In operation, the processor, during a first frame, provides the identity of the caller's highway during the busy bit time phase on lead 112 so as to gate the busy bits corresponding to all the output time slots of the interchanger TSI 1  in the caller's highway into a buffer 120 (It will be remembered that SP 1  takes the like numbered slots from a plurality of highways and injects them in serial order into an interchanger TSI 2 . The effect at the end of a frame is then that all like-numbered slots in the interchangers TSI 2  pertain to a single input interchanger TSI 1 , i.e. pertain to a frame of slots from a single input highway). During the same frame the busy bits from all the slots on the called party's highway are examined in selector 117. At the start of the next frame the contents of buffer 120 are gated into shift register 128 so that they can be compared with the contents of selector 117 in gate 127. Coincidence causes destructive read-out of a shift register 126 which contains a bit injected at the the start of the second frame. The bit is thus directed to a particular one of the second stage interchangers TSI 2  as a priming signal (see above description of Fig. 3). The input TS 1  and output TS 0  time slots of the TSI 2  interchanger are given by the identities of the calling and called party highways and these are supplied to the interchanger's control circuit during the relevant frames thanks to delay circuits 140 and 141. The method of inserting priming and TS 1 , TS 0  information into the relevant TSI 1  and TSI 3  interchangers can be easily deduced from the drawing.