Patent CA-1141495-A (CA)
Inventor: MAZZOCCHI GABRIELE
IPC: G06F5/16
Filed: 1979-11-05
Granted: 1983-02-15
Abstract: ABSTRACT OF THE DISCLOSURE:         The present invention relates to a demultiplexer for an incoming bit stream organized in a succession of frames of m time slots each encompassing a group of n bits arriving over a signal path.  This demultiplexer comprises an input register connected to the signal path for temporarily receiving successive n-bit groups;  a synchronization. extractor also connected to the signal path for extracting a train of first clock pulses with cycles T', corresponding to the time slots, from the incoming bit stream;  a local source of second clock pulses with cycles T" ? T';  a bit store including a pair of substantially identical memories, each provided with m cells accommodating respective n-bit groups, communicating via a common loading connection with the input register;  an output register linked by a common unloading connection to each of the memories for receiving successive n-bit groups from the bit store;  a distributing device connected to the output register for routing the n-bit groups to different outgoing channels;  a first address-generator stepped by the first clock pulses every cycle T' for identifying a pair of homologous cells of the memories in one of which an n-bit group present in the input register is to be written via the loading connection;  and a second address-generator stepped by the second clock pulses every cycle T" for identifying a pair of homologous cells of the memories from one of which an n-bit group is to be read out to the output register via the unloading connection.  The demultiplexer of the invention further comprises a first timing device driven by the first clock pulses for generating a series of writing commands accompanied by a first square wave having half-cycles coinciding with respective incoming-frame periods [2]mT'; and a second timing device driven by said second clock pulses for generating a series of reading commands, these reading commands being interleaved with the writing commands and being accompanied by a second square-wave having half-cycles coinciding with respective outgoing-frame periods [2]mT". A switching device is also provided and is responsive to the first and second timing devices for connecting an address input of each of the memories -to the first address-generator while feeding a sample of the first square wave in relatively inverted form to respective enabling inputs of the memories in the presence of each writing command and for connecting the address input of each of -the memories to the second address-generator while feeding a sample of the second square wave in relatively inverted form to -the respective enabling inputs in the presence of each reading command. The demultiplexer is finally provided with a control circuit connected to the first and second timing devices for detecting a near-coincidence between corresponding half-cycles of the first and second square waves and thereupon relatively inverting the square waves, one of the timing device emitting a monitoring pulse at the beginning of every full cycle of the square wave generated thereby, the other of the timing device emitting a reference pulse at the beginning of every half-cycle of the square wave generated thereby.  The control circuit further comprises a logical circuitry responsive to a coincidence of a monitoring pulse with a reference pulse in the presence of a predetermined level of the last-mentioned square wave for shifting the latter by 180°.