Patent GB-855609-A (GB)
Title: Improvements in or relating to pulse code modulation encoders
IPC: H03M1/00
Filed: 1959-06-17
Abstract: 855,609. Analogue - to - digital converters. WESTERN ELECTRIC CO. Inc. June 17, 1959 [June 24, 1958], No. 20736/59. Class 40 (1). [Also in Group XL (c)] A binary coder comprises a plurality of comparison channels, each of which corresponds to a respective one of the digit intervals in a code group and supplies a reference pulse to a bus-bar 51, Fig. 1, in its respective digit interval through a weighted summing network, and means for regenerating a particular reference pulse in each succeeding digit interval in a code group whenever the difference between the combined reference pulse appearing on bus-bar 51 and the signal to be coded assumes a predetermined polarity in the digit interval in which that reference pulse is first produced. Fig. 1 shows, by way of example, a four-digit coder in which the signal to be coded is applied to bus-bar 51 in the form of amplitude modulated pulses of opposite polarity to the reference pulses produced across weighted resistors R, 2R, 4R, 8R by the comparison channels. The first comparison channel comprises diodes 11, 12, AND gate 13, regenerative amplifier 14, e.g. a blocking oscillator, transistor switch 18 and resistor 20. Gate 13 is opened in the first digit interval of each code group by negative inputs to diodes 11, 12, waveforms - D1 + D2, Fig. 2 (a), (b), from a pulse distributer 10, amplifier 14 is triggered, and a negative-going first reference pulse of 8 units amplitude appears on bus-bar 51, no other reference pulses being produced in this interval. With a signal level of 11 units, a net positive voltage of 3 units is applied to inverting amplifier 52, no output is obtained from comparator 54, and regenerative amplifier 55 is not triggered. In the second digit interval, the output pulse from amplifier 14, fed back over one-digit delay network 15, unblocks diode 16, diode 11 being blocked. Diode 12 is blocked by the positive pulse from waveform + D2, but diode 17 is unblocked by the normal negative output of amplifier 55. Thus gate 13 is again opened and the first reference pulse is regenerated. At the same time, gate 23 of the second comparison channel is opened by waveform - D2, +D3, Fig. 2 (c), (d), and a second reference pulse of 4 units amplitude is applied to bus-bar 51 over resistor 2R. The combined reference pulse in the second digit interval is thus 12 units, a negative voltage of 1 unit is applied to amplifier 52, comparator 54 produces an output after a delay of 1 digit interval and triggers amplifier 55 to produce a positive pulse in the third digit interval. Thus in the third interval, gate 13 is again opened . since diodes 12, 16 are unblocked, gate 23 is closed since diodes 22, 27 are blocked, and gate 33 is opened since diodes 31, 32 are unblocked by waveforms - D3, +D4, Fig. 2 (e), (j). The resulting combined reference pulse is thus 10 units so that a one-unit positive input is supplied to amplifier 52 and the normal negative output of amplifier 55 is obtained in the fourth interval. Thus in the fourth interval, gate 13 is again opened, gate 23 is closed since no pulse is fed back over delay network 25, gate 33 is opened through diodes 36, 37 and amplifier 44 of the fourth channel is triggered by waveform - D4, Fig. 2 (g). The combined reference pulse in the fourth interval is thus 11 units, equal to the signal sample, and the normal negative output is again obtained from amplifier 55. The code group produced at the output of amplifier 56 is the inverse of the simple binary code and is delayed by one digit interval. The Specification describes in detail a circuit for producing a 7-digit code, Fig. 3, 4 (not shown).