Patent GB-1377724-A (GB)
Title: Multilevel code transmission system
IPC: H04L25/48
Filed: 1973-02-05
Abstract: 1377724 Digital transmission; multi-level systems NIPPON ELECTRIC CO Ltd 5 Feb 1973 [4 Feb 1972] 5619/73 Heading H4P A N level transmission system has one or more monitors each detecting 1st and 2nd complementary (i.e. i and N - i) levels where i is an integer less than N, and differential coding means responsive to each monitoring means providing an output at a 1st level when a 1st or 2nd level is detected at the same level as the preceding output signal, and output signal at the second level when a first or second level is detected at the level complementary to the level of the preceding output signal, and transmitting to a receiver a partial response encoded signal representative of a N level transmission signal comprising the output signals of the or each differential coding means combined with those levels of the N level input signal not detected by the first monitoring means. The system includes a receiver recoding received signals into original form. In Fig. 1 (not shown) converter (1) converts input signals into N parallel binary signals where N = no. of levels of output signal, which applies to a differential coding circuit (2) to a partial response coding circuit comprising multilevel pulse generators forming a base band signal subject to a.m.s.s.b. modulation at (5) where a pilot signal is superimposed. At the receiver a demodulator (6) performs synchronous detection and extracts the base band signal; discriminator (7) identifies each digit with respect to (2N-1) levels. The resultant signal is decoded into a multi-level signal of N levels by partial response decoding circuit (8) which performs a modulo-N sum of the signal and N which is converted into binary by parallel/series converter (10) by inverse converting circuit (9) for the differential coding operation. Fig. 2 includes a differential coding block 100 and a by-passing block 200 for signals at 0 level when N = odd or N/2 where N is even with block 500 collecting signals and providing an output. Through terminals 60-64 binary signals indicative of multi-level signals are supplied to pattern detecting circuits 101, 102, 201 through terminals 60-64. When the pattern of signals is coincident with a specific code pattern, the detecting circuits generate a 1 output. These circuits are made up of AND gates and 101 &c. detect the (N-i) level, the i level and zero level respectively and cause corresponding circuits 112, 113, 212 to give parallel outputs of specific pattern when input is 1 or all zeros when input is 0. Fig. 4 (not shown) shows a differential inverse block corresponding to Fig. 2 comprising pattern detector circuits (301, 302, 401) corresponding to (N-i), i, 0 levels with pattern generators 112, 113, 212 (also corresponding to Fig. 2). In an example given, only the 1st and 3rd levels are differentially coded; when the input is at 1st level output remains at 1st or 3rd level. When the input is 3rd level the preceding output at inverted level is delivered. Signals at input levels 0 and 2 are transmitted directly. The arrangement is stated to allow more effective use of transmission channel frequency band and provide correct reception of signals even when demodulated carrier is 180 degrees out of phase.