Patent GB-1140830-A (GB)
Title: A magnetic memory
IPC: G11C11/155
Filed: 1967-10-13
Abstract: 1,140,830. Magnetic storage apparatus; transistor switching and logic. NATIONAL CASH REGISTER CO. 13 Oct., 1967 [7 Nov., 1966], No. 46714/67. Headings H3B and H3T. In a magnetic memory matrix comprising a plurality of electrically conductive rods coated with anisotropic magnetic thin film material a row of word lines are each coupled at one end through a selection switch and diode to a common line which is connected to a constant current source comprising a transistor having an inductor as part of its load circuit. A three-dimensional memory array, Fig. 1, comprises magnetic thin film coated rods 12 arranged in planes P1-Pn and coupled by word solenoids 14 connected in series to form a word line 15 as shown, In a memory operating cycle a read period is followed by a write period. During the read period a word current is applied to a selected word line to provide a magnetic field along the hard axis, the subsequent rotation of the magnetization of the rod 12 producing an output signal in the corresponding sense digit line 30, Fig. 3. The magnetic film rods 12 are connected in a transposed noisecancelling pattern in which the sense amplifier SA1 is connected to bridge the sense / digit line in the middle and a digit driver DR1 is coupled to opposite ends of the digit sense line 30. During the write period a write current and appropriate polarity digit pulse from the digit driver are coincidently applied to the rod 12. The memory operates in a non-destructive mode by amplifying the output signals and passing them through appropriate logic current M1, Fig. 3a (not shown), and Fig. 3b to drive the appropriate drive circuit DR to re-write the information read out. Word selection, Figs. 1, 2.-In order to select a word line a corresponding set of one of the column drivers Y1 to Yn and one of the row drivers X1 to Xn are activated under the control of column and row decoding circuits so that one of the word line transistors is saturated and word current flows from a constant current square U through the corresponding common line 27, diode 25, transistor 17 and word line 15. If the word line 12a is to be selected then as shown in Fig. 2 appropriate voltage levels are applied from the decoder to the Y1 driver so that transistor 36 is switched off and transistor 37 is switched on causing transistor amplifier 40 to be switched off and transistor 41 to be switched on. When transistor 41 is switched on drive line transistor 17a is rapidly saturated. At the same time as the column driver Y1 circuit is activated the row driver circuit X1 is also activated by the row decoding circuit whereby transistor 37a is switched off, transistor 34 is switched on and transistors 26 are turned off causing constant current from source U1 to be switched to row bus 27 and the word line 15a selected by column driver Y1. The constant current source U1 comprises a pair of emitter coupled transistors 30 having an inductor 29 and resistor 32 connected in parallel in the collector circuit thereof, the inductor being made sufficiently large to maintain a portion of the word current at the instant of switching from the path through transistors 26 to the word line 15a, the remaining current being provided by high speed transistor circuit 30. Logic circuit M1, Fig. 3b.-The logic circuit M1 used in the digit sense circuit of Fig. 3 comprises a pair of emitter coupled logic circuits. Logic inputs are applied to input terminal 72 so that if an upper level signal is applied transistor 70 conducts and reference transistor 71 is switched off and output transistor 73 produces a voltage drop lowering NOR output 77 to the low logic level. Since no current flows through transistor 71 the OR output terminal 78 will be at its high logical level. By connecting input transistor 74, 75, 76 in parallel with input transistor 70 a logical gating circuit is formed such that if any one of the logical inputs is at the higher logical level the OR output will be at the higher level and the NOR output at the lower level. If all four inputs are at the lower level the converse applies.