Patent GB-831408-A (GB)
Title: Circuit arrangement for marking the points of intersection of a resistance-diode matrix
IPC: H03K17/62
Filed: 1958-04-25
Abstract: 831,408. Electric selective signalling circuits. STANDARD TELEPHONES & CABLES Ltd. April 25, 1958 [April 27, 1957], No. 13216/58. Class 40 (1). [Also in Group XL (c)] In a co-ordinate resistor-diode matrix having a set of row wires and a set of column wires with a series combination of a resistor and a diode interconnecting the row wire and the column at each intersection between a row wire and a column wire and in which the selection of one or more of said series combinations is effected by selectively energizing the appropriate row and column wires, means are provided to prevent spurious selections when several selections are being made simultaneously. A matrix suitable for single selections is shown in Fig. 1, selection of intersection 7 being effected by causing corresponding row and column selecting transistors SR and SC to become conductors. When this occurs current flows through both the column conductor and the row conductor and their associated resistors RC and RR respectively to raise their potentials and hence to raise the potential of intersection 7. If, however, several row conductors are selected simultaneously, thereby raising their potentials, currents will flow from their rows via the interconnecting diodes to the column conductors, and in particular to the first column conductor, and then via their associated resistors RC to earth, and if sufficient row conductors are selected the total current through resistor RC may be such as to raise the potential of the column conductor to what it would be had it been selected. Thus the matrix of Fig. 1 may give spurious selections if several are made simultaneously. According to the invention, in order to prevent a rise in potential of a column conductor when several row conductors are selected unless the column conductor is also selected, the resistor RC of each column conductor is shunted by one or more transistors S1, S1<1> &c., Fig. 3, and transistor SC is controlled, not directly via its base as in Fig. 1, but via a further transistor S4. In Fig. 3 the actual column conductor is not shown but, as in Fig. 1, it is connected to the junction of resistor RC and the collector of transistor SC. The row conductor associated with the diode D is joined to a point marked X. In operation, in the absence of a column selecting signal, which is applied to the base of transistor S4, the emitter-collector circuits of transistor S1, S1<1> &c. are in low impedance states so that the column conductor is held substantially at the negative potential - V6, and hence even if several row conductors are selected the column conductors will not rise appreciably in potential. If a column selecting signal is applied to the base of normally conducting transistor S4 the result is to render this transistor non-conductive which in turn renders both transistor SC and a shunt control transistor S2 conductive and the effect of the latter is to raise the impedance of transistors S1 and S1<1> &c. to thereby in effect remove the shunt across resistor RC. Also the circuit is so arranged that transistor S2 conducts before transistor SC. Thus the result of applying a column select signal to the base of transistor S4 is firstly to remove the shunt across resistor RC and secondly to cause transistor SC to conduct and develop a potential across resistor RC thereby raising the column potential. In a second embodiment (Fig. 4, not shown) transistor S4 is replaced by two transistors, one for controlling transistor SC and one for controlling transistor S2.