Patent GB-1386168-A (GB)
Title: Data sensing system
IPC: G06K7/12
Filed: 1972-12-06
Abstract: 1386168 Coded tag reader NCR CORP 6 Dec 1972 [7 Dec 1971] 56313/72 Heading G4M A data tag used in a retail store carries binary information indicated by green, black or white bars and also carries human readable printing. The tag is scanned by a hand held light pen feeding data to logic circuitry. The tag carries data fields each having a white background, has a " 1 " bit at the start of a field, has a four bit data size indicator, two bit indentification code, then from 2 to 28 B.C.D. characters, a D.C.C. parity code, a modulo 3 parity code, a back size code and a bit DB which is the same value as the front bit D.B. If the tag is read in reverse order the code used (Figs. 4A, 4B) causes the bits to be inverted and to appear in reverse order. Between each of the fields is a space greater than the length of one of the data bars. Light from the reader is transmitted via. a fibre optic bundle to a colour detector 68 giving signals on output lines WHL, GNL, BKL with a " 0 " on the line corresponding to the colour being scanned and a " 1 " on the other lines. A data decoder 70 then feeds an input buffer 72 and when 8 bits have been received they are fed to character position 1 of Main Buffer 74. This includes two 136 bit Buffers A76 and B78 and respective controls. Buffer A stores single field tags or the first field of double field tags and Buffer B stores the second field. The signals from the colour detector are also fed to Beginning of Field and End of Field counters and to a transition detector. The BOF counter counts the time the WHL background signal is 0 and compares this to the time the next GNL or BKL is 0. If the latter is less than  of the former BOF becomes 1. The EOF counter similarly compares the last BKL or GNL with the following WHL signal. The transition detector feeds a BC8 counter and enables Input Buffer 72, and BC8 counter 96 indicates the number of bits in Buffer 72. A free running register position counter 98 keeps track of information in the recirculating Main Buffer 74, and Index Register Counter 100 fed by BC8 Counter loads and unloads data into or from Main Buffer 74. Limit Register Counter is used to compare length of data, to detect the end of data and to initiate parity check.  When the counts in counters 98, 100 coincide Compare circuit 106 provides an 8 bit long signal to enable transfer into and out of the main Buffer. When a field has been read the Front size code is in Output Buffer 86 and the Back Size Code is in Input Buffer 72. These are compared in Size Code check 112. The size code is stored in the limit register counter (this is 2 less than the number of 8 bit characters in the field) and is incremented by 2. The count in Index Register Counter which is 1 less than the number of 8 bit characters since one character is still in Input Buffer 72 is incremented by 1 and the counters are compared. This enables size Code check 112 to produce an EOD signal. If either size Code check fails a PENUP signal occurring when the WHL signals occurs for a predetermined time interval causes a EOD signal. The B.C.C. and Mod 3 parity signals are then checked. When the data is completely checked it is transmitted to utilization device 89. If the data is read in the reverse direction data is read out using down counter 122 and the characters read out are complemented. More detailed circuitry controlling the circuit of Fig. 5 is illustrated in Figs. 14A-14L (not shown).