Patent ES-371476-A1 (ES)
Title: Synchronisation circuit in a pcm central exchange
IPC: H04J3/06
Filed: 1969-09-12
Abstract: Specification describes a synchronizing arrangement for a P.C.M. switching centre, similar to that described in "P.C.M. telephone exchange switches digital data like a computer", pp 119-126, "Electronics" October 3, 1966. The described centre, Fig. 2, involves groups of eight highways G1 &c., each highway carrying frames of 24 channels, each channel carrying a word of 8 digits. The words are converted from serial to parallel format by individual highway synchro-junctions. Fig. 3, and the 64 lines are fed to a 192 row (each an 8-bit word) group data memory (MDG1, Fig. 2 or 130, Fig. 4). The outputs of the data memories are supermultiplexed highways and are fed to a matrix switching means SW. To connect a word from G1 to G2, the word is read out of group data memory MDG1 according to its row (time) position tsx and stored in memory MDJ. Memory MDJ is read out at time tsy and applied via connection C5R2 to the group circuit G2. The errors in synchronization can be of three kinds: (a) Slow drift or a difference in phase of the local centre clock signals and the P.C.M. timing signals. They are caused by modifications in the propagation paths. The phase difference varies with a period of 104-105 seconds so that any misregister of the received P.C.M. signal has the same sign for a long time and is thus cumulative. (b) Phase jitter, or quick drifting of signals on either side of time positions they should occupy if only subject to slow drift. They are caused by cross-talk. (c) Synchronization loss occurs when slow drift becomes uncontrollable. The synchronization code is made up of the first digit of the messages of the channels 9 through 24 of frame number 2, the frames repeating on every fourth. For the removal of slow drift, a signal Y at the average frequency of the received P.C.M. signals L n , Fig. 3, is compared with the digit clock signal for phase. Due to the very small amounts involved, a digital method is used. The error signal is used to modify the writing and/or reading times of a phase corrector buffer memory 111, also performing the serial to parallel digit format change. The received signals are thus stored in the correct addresses in the data memory 130. From the removal of jitter, it is seen that the duration of each digit is less than the digit time but can be anywhere in that digit time due to jitter. Each digit time is divided into four equal sub pulses, a, b, c, d d is further divided into two d 1, d 2. The digits are stored in real time in memory 111 but are read at constant time b, thereby removing jitter. If the synchronization code is lost for five consecutive frames the writing in the phase corrector memory 111 jumps up one step. This is repeated every five frames until synchronism is restored. The determination of the slow drift phase error &c. is carried out in a recirculating group instruction memory 170, Fig. 4, having a memory portion 140, a register portion 150 and a signal modifying portion 160. Each portion is split into six to give six sub circulatory paths. The functions of these paths are as follows: (a) 141,151,161 This operates as a channel counter of the clock signals and provides clock channel defining pulses V1-V24. (b) 142,152,162 This operates as a frame counter for use in loss of synchronism detection. (c) 143,153,163 This determines whether to advance or delay the timing of phase corrector 111 to remove drift. (d) 144,154,164 This determines the row number of phase correctors 111. (e) 145,155,165 This determines the number of times the synchronization is in error. (f) 146, 156,166 This produces a circuit out of order signal in response to (e).