Patent GB-748771-A (GB)
Title: Electrical binary-digital pulse signalling systems
Inventor: CLAYDEN DAVID OSWALD
IPC: H04L7/10
Filed: 1953-04-20
Abstract: 748,771. Electric selective signalling. NATIONAL RESEARCH DEVELOPMENT CORPORATION. April 13, 1954 [April 20, 1953], No. 10726/53. Class 40(1) The invention relates to binary digital signalling systems, e.g. as described in Specification 707,634, [Group XIX], in which as shown in Fig. 2(a), e.g. each digit "one" signal changes from a first voltage level to a second' level at the middle of the digit period, and each digit "zero" signal changes from the second voltage level to the first at the middle of the digit period. According to the invention a binary digital signalling train of the kind in question is translated into a conventional binary digital pulse train, in which "one" is represented by a pulse and "zero" by the absence of a pulse or vice versa. The ininput signal train S1 derived, e.g. from a magnetic computor store via a read unit R U, Fig. 1, is fed to a beginning element B and an end element E which produce pulses, Fig. 2(b), when the output S1 changes in level. These pulses set a trigger T, provided it is not already set, and the trigger output, Fig. 2(c), is fed to a beginning element B3 through a delay unit D to produce pulses, Fig. 2(d), delayed by threequarters of a digit period after the trigger is set. These pulses reset the trigger i.e. to "off", as shown in Fig. 2(c). As soon as two successive digit signals in the train S1 are of different type, the trigger T sets and resets itself at times which bear a known time relationship to the digit periods. As shown, the trigger reset pulses, Fig. 2(d), occur, for all digit periods after the third digit of the signal S1, in the middle of the first half of each digit period, and may be used as clock pulses for controlling a coincidence gate G to which the signal S1 is applied. The gate output S2, Fig. 2(e), is then a binary digital train in which the digit 1 is represented by a purse and zero by absence of a pulse. This train is in error until two successive different digits occur in the train S1 when, as above mentioned, the trigger commences to operate in timed relationship to the digit periods. To prevent such erroneous transmission at the beginning of a signal train the message may be preceded by a syncsignal which brings the trigger T into correct step, and is suppressed as described below. Synchronizing; Figs. 4, 5. The sync-signal Fig. 5(a) corresponds to the binary number 01011 which brings the trigger T, Fig. 4, into step as described above. The trigger input pulses, Fig. 5(b), are also fed to a gate G2 controlled by the trigger output. Fig. 5(c), slightly delayed if necessary so that the gates passes only those pulses from the lements B, E, occuring at the beginning of a digit period. The first such pulse, Fig. 5(d), occurs at the end of the sync-signal when the signal 1 is repeated. This output after being delayed at D2 by threequarters of a digit period sets a trigger T2 the output of which, Fig. 5(e), is fed to a gate G3 through which the clock pulses CP, Fig. 5(f), produced as in Fig. 1, are passed only when the trigger T2 is "on". This occurs during the first digit period of the message proper. Fig. 5 (g), so that the output S2, Fig. 5(h), from the gate G commences only with the message. Circuitry. Fig. 3 shows some of the elements of Fig. 1. The input train Sl is applied to the grid of a triode V1 which conducts alternately with V2 the conducting valve changing in time with the changes of voltage amplitude of the signal S1. The differentiating coils L1, L2 produce short-duration positive pulses, Fig. 2(b), when the associated valves cease to conduct, which are phase inverted in triodes V3, V4 and fed as negative pulses to the trcode V5 which with V6 functions as the trigger T, Fig. 1, and its resetting loop. Trcode V5 is cut off by the negative pulses (if not already blocked), and cause V6 to conduct for threequarters of a digital period-determined by the discharge time of a condenser C. Positive clock pulses CP are taken from the anode of V6 by virtue of a differentiating coil L3; negative pulses which would normally be produced as the trigger is set, i.e. as V6 conducts are suppressed by a rectifier W3. The trigger shown has a constant resetting period but this may be changed automatically in proportion with the signal repitition rate by removing rectifier W2, and by circuit changes as shown in broken lines. Specification 717,114, [Group XIX], also is referred to.