Patent GB-1173781-A (GB)
Title: Improvements in or relating to Communication Switching Systems
IPC: H04Q11/04
Filed: 1967-01-26
Abstract: 1,173,781. Automatic exchange systems. WESTERN ELECTRIC CO. Inc. 26 Jan., 1967 [3 Feb., 1966], No. 3936/67. Heading H4K. A telephone exchange in which speech paths are established over a time division multiplex highway or, in an alternative embodiment, over a ferreed matrix, is provided with a time shared common control connected to all terminal circuits over a store-write bus, each terminal circuit having a fixed time slot and the common control effecting a connection between two terminals by storing the identity of each circuit in the time slot of the other, the terminal identities being obtained for storage from a cyclic word counter gated to the stores by pulses from the terminal circuits sent over the storewrite bus. The common control is also connected to the terminal circuits by a supervisory bus for the maintenance of connections and by an erase bus for release. In the drawings, with the exception of some control leads, the hundreds digit of each reference indicates the Figure of the drawings in which the reference occurs. The common control.-This comprises a delay line 525 in which connection data circulates in the time slots allocated to each line circuit, main exchange circuit, busy tone trunk circuit, and register trunk circuit. A total of 26 such terminal circuits is envisaged. Each time slot comprises a 10 bit word: 5 bits being a terminal address, 4 bits having an unspecified control function, and one bit being a transmission bit which when present sanctions speech over the t.d.m. highway. A clock 501 operates on a stop-start basis. Start circuit 500 injects a bit or, to prevent spurious operation, injects a code into delay line 525. Each time the start bit or code emerges on read register 526 it starts the clock which steps a word counter 502 over a complete exchange cycle, the counter providing a binary code output identifying each terminal circuit in the time slot of that circuit. When the cycle is complete the counter stops the clock which waits for the start bit or code before setting off on the next exchange cycle. This process of synchronizing the clock in each cycle allows for temperature and other variations in the performance of the delay line which works at a 2À6 megacycle bit rate and a delay of 100Á secs. The binary code output of the word counter 502 is decoded in an originating selector 503 to mark an individual wire, such as 504, to each terminal circuit to prime an array of AND gates such as 232, 237, 238 and 230, giving access to the control circuit buses and controlling the transmission gates in the time slot of each terminal circuit. The 5-bit binary address in the read register 526 at the delay line output is decoded in a terminating selector 540 to mark an individual wire such as 541 to control the terminal circuit so indicated in the time slot of the circuit to which it is connected or is to be connected. The terminating selector is only employed when the supervisory bus sanctions an input over gates 539. The common control also comprises a call originating register connector section in Fig. 3, and has a call termination section in Fig. 4 including a busy tone selector. Connection of calling line to register.-The off-hook condition of a calling line brings up relays A and B which latter sets a bi-stable circuit 203 to extend the calling condition to a scanner 301. The scanner 301 is stepped word by word by the output of word counter 502 and when the scanner encounters a calling state the word counter provides the code of the calling line circuit. A detector 303 responds to a calling state to halt the scanner by setting a bi-stable circuit 304 to cut-off the word counter input at gates 305. Before so doing, however, the detector signals control circuits 315, 330 of selectors 320, 335, the former being connected to the word counter output to register the calling line circuit code and the latter recording a code identifying a free register. The idle/busy conditions of registers are present on leads 770 to the control circuit 330 which selects the first idle marking and injects the corresponding code in selector 335. The code identifying the calling line circuit is also registered in calling number store 325 to await employment by the register. When the word counter has cycled back to its zero count a gate 339 is opened and activates a write control 340. Write control causes the calling number selector to mark its output lead 321 corresponding to the registered code of the calling line circuit wherein bi-stable 210 is set to prime gate 230 on the store-write bus and to reset bi-stable 203 to free the scanner. Write control also causes selector 335 to mark its output lead 336 to register 700 (supposing this to be the register seized for use) where a bi-stable 772 is set to activate a timing circuit 773 and operate a relay D which removes the idle mark on lead 770. The timing circuit 773 causes the code of the calling line circuit to be transferred from store 325 to store 710. Timing circuit 773 also sets bi-stable 706 to open gates 711 thereby passing the calling line circuit code to a calling number selector 405 in the call termination section. When the word counter 502 again reaches the calling line circuit code, originating selector 503 marks lead 504 to open gate 230 to the store-write bus and consequently opens gate 509 to move a stepping register 510 to its first stage in which it gates the code of the calling line circuit to a register 521 preparatory to the insertion of this code into the delay line 525 in the time slot of the register 700. When, in the same exchange cycle, the word counter 502 reaches the code of register 700, originating selector marks lead 505 to the trunk circuit 600 associated with the register and this mark along with the set output of bi-stable 772 opens gate 650 to the storewrite bus. Gate 509 is again opened to shift register 510 to its second stage where it gates the register code presented by word counter 502 to write register 520 preparatory to the insertion of this code into delay line 525 in the time slot of the calling line circuit. Register 510 when at its second stage also opens gate 513 to place the calling line circuit code into the delay line 525, this being in the time slot of register 700. At the head of the write register 521 a transmission mark is automatically inserted so that in subsequent occurrences of the register time slot all terminal circuits are pulsed on leads to gates such as 232, 652, thus permitting operation of the transmission gate 655 by the mark on lead 505 from the originating selector to trunk circuit 600. Insertion of new data into delay line 525 causes an inverter 533 to erase any existing data attempting to circulate. The next significant event in this process occurs when the word counter has entered the next exchange cycle and reaches the code of the calling line circuit. Originating selector at this point marks lead 504 to open gate 230 to the store-write bus, the set output of bistable 210 having been lost at the end of the preceding exchange cycle but restored by the zero output of the word counter which activates write control 450 to elicit the necessary setting output from calling number selector 405. The pulse on the store-write bus, together with the still existing output of timing circuit 310, opens gate 509 to move shift register 510 to its third stage in which it opens gate 511 to transfer the code of the register 700 contained therein to the delay line 525. No transmission mark accompanies the code of register 700 which circulates from now on in the time slot of the calling line circuit. The stepping register 510 resets itself and timing circuit 310 retires to free the control circuit for further originations. On the next occurrence of the calling line circuit code in word counter 502 lead 504 is marked and gate 237 opens to pulse the supervisory bus, relay A providing the necessary other input. The supervisory bus was similarly active in earlier cycles but without effect; when active at this point, however, the bus opens gates 539 so that the code of the register 700 (and associated trunk circuit 600) is applied to terminating selector 540 from delay line read register 526. In consequence, lead 542 to the trunk circuit 600 is marked to activate timer 625 which operates and holds relay M, the timer being reactivated in each succeeding calling line circuit time slot. A relay N follows M and primes gate 660 to the supervisory bus and also connects a dial tone source 610 to the transmission gate 655. In the next and succeeding occurrences of the time slot of the register 700 its code from counter 502 to originating selector 503 marks lead 505 to open gate 660 and pulse the supervisory bus. The calling line circuit code present in delay line read register 526 at this time is consequently gated to the terminating selector to mark lead 541 to the calling line circuit where it effects operation of the transmission gate 235. The presence of a transmission mark in register 526 at this time also operates gate 652 to operate transmission gate 655 in the trunk circuit. Dial tone is therefore connected over the transmission bus to the calling line in the time slot of the register 700. The time slot of the calling line is employed to hold the relay M in trunk 600. Reception of dialled digits.-Multifrequency key sending received at circuit 615 over the transmission bus, is sent forward to a steering circuit 720 for storage in called number register 725. If loop disconnect impulse sending is employed the relay A in the line circuit follows the impulses and gate 237 to the supervisory bus is opened and closed following A. Since, without pulses on the supervisory bus to the gates 539, no signal is sent from the terminating selector 540 to lead 542 of register trunk 600. Relay M, in consequence, falls and restores to follow the dialled impulses. Contacts of M are employed to o