baber/WOPTO huggingface dataset:
Patent JP-2000317306-A (JP)
Title: Gas adsorbing element
Inventor: MURAOKA KATSUNORI
IPC: B01J20/32
Filed: 1999-05-06
Abstract: PROBLEM TO BE SOLVED: To easily produce a highly hydrophobic adsorbent by making the plasma of carbon tetrafluoride act on a honeycomb body to which a raw adsorbent having hydroxyl groups is adsorbed and by replacing at least part of hydroxyl groups of the raw adsorbent fixed to a honeycomb body with fluorine. SOLUTION: Y-shaped zeolite is, for example, dispersed in a silica sol, a honeycomb body is immersed in the dispersed solution and is dried after picking up from the solution so as to obtain a honeycomb body 1 fixed with an adsorbent. The whole honeycomb body 1 is heated by a heating block 11 through a holder 13 with placing on a mesh-plate 14 in a chamber 4 of a reduced pressure by a vacuum pump 17. Then, high frequency current flows from the power source 9 of high frequency to an upper electrode 5 and carbon tetrafluoride is fed to the lower face of the upper electrode 4 from a pipe 8, with an alternating electric field generated between the upper electrode 5 and the mesh-plate 14, so as to create plasma.
Patent JP-S615500-A (JP)
Title: Memory integrated circuit
Inventor: TOOYAMA OSAMU
IPC: G11C29/04
Filed: 1984-06-19
Abstract: PURPOSE:To improve the reliability of a memory integrated circuit with simple constitution by reading the same data written in the entire data width of plural bits, selecting the odd-number pcs. of data, stopping an output of an erroneous bit after the prescribed processing is applied and simultaneously selecting not- used bits. CONSTITUTION:The same data written in the entire data width of four bits, etc., read out from a memory cell 14 is stored in a data output buffer 21. The data of three bits, etc., is selected through an output selection circuit 22 controlled by an erroneous bit memory circuit 27, and outputted through a majority decision circuit 24. When the data of three bits has errors, the circuit 22 controlled by the circuit 27 stops the output of bits where errors exist, and selects and outputs non-used bits. Thus the reliability of a memory integrated circuit can be improved with simple constitution where a code generator circuit, code decoding circuit, data correction circuit, etc., need not be made complicated along with an increase in bits.
Patent JP-H01293631-A (JP)
Title: Manufacture of insulating film
Inventor: NAKANISHI AKISHIGE
IPC: H01L21/768
Filed: 1988-05-23
Abstract: PURPOSE:To prevent the generation of asperity and a high-quality insulation film to be formed by forming a heated nitriding silicon film performing annealing of an HTO film within a high-temperature ammonium gas environment and by allowing this heated nitriding silicon oxide film to be subject to heated oxidation. CONSTITUTION:A thin gate insulation film 4 is formed on the channel area between a source area 2 and a drain area 3. After an HTO film 6 is accumulated on a first layer polysilicon electrode 5 on it by the CVD method, the HTO film 6 is annealed within a high-temperature ammonium gas environment and a heated nitriding silicon oxide film 7 is formed. The oxide film 7 on the HTO film 6 is subject to heated oxidation to form a thin oxide film 8. A second-layer polysilicon electrode 9 is accumulated on it. It prevents the generation of asperity of polysilicon and allows an insulation film of high film quality to be formed.
Patent JP-S62282281-A (JP)
Title: Iron loss measuring device
Inventor: KAWABATA TAKAO
IPC: G01R33/12
Filed: 1986-05-30
Abstract: PURPOSE:To actually measure or estimate an iron loss value accurately even when voltage having arbitrary frequency of an arbitrary square wave is applied, by calculating the iron loss value of a semi-cycle or one cycle from the timewise change rate and change quantity of magnetic flux density. CONSTITUTION:An iron loss converter 11 has not only a change quantity output means 11a but also an iron loss characteristic wherein the timewise change rate dB/dt of magnetic flux density and the Joule loss per a unit wt. of an iron core are set on a coordinates axis by setting the change quantity DELTAB of magnetic flux density B as a parameter. The square wave voltage from a transformer 3 tested is inputted to the converter 11 through an integrator 5 and also inputted to a counter 6 for measuring the time width of a square wave and, thereafter, the time width of the semi-cycle of the rectangular wave is inputted to a divider 8 being a time change rate output means. The divider 8 outputs the timewise change rate dB/dt of magnetic flux density and the converter 11 outputs an iron loss value per a semi-cycle or one cycle as Joule loss per a unit wt. from said output and the change quantity DELTAB of magnetic flux density B based on magnetic flux output 9.
Patent JP-S5749840-A (JP)
Title: Detecting method for projection defect part on surface of linear object
Inventor: ABE FUMIHIKO
IPC: G01N19/08
Filed: 1980-09-10
Abstract: PURPOSE:To enable to detect a projection defect part on the surface of a linear object without causing variations at all times, by detecting force acting on a die by means of a hollow and cylindrical load cell provided on the upper part of the die. CONSTITUTION:A core 1, after passing through a varnish bath 2 filled with varnish, enters into a baking furnace 10 via a convex defect part detecting device 3, and here it is baked to become an enameled wire. Existence of the convex defect part on the surface of the core 1, when it passes through a restriction 6 having a prescribed diameter of a die 4, increases frictional resistance due to contact of one part of the defect part with a sidewall of said restriction 6. Accordingly, the die 4 is pushed up, thereby a load cell 8 is pressed down with pressure. The area of a waveform of an electric signal ei in responce to the force from said load cell 8 acting upon the die is calculated with a signal processing circuit 12, thereby magnitude of the convex defect part is detected. Hereby, a need for adjustment can be avoided, and further variations of the data can also be eliminated.
Patent JP-H0419755-A (JP)
Title: Color developer
Inventor: OKADO KENJI
IPC: G03G9/10
Filed: 1990-05-15
Abstract: PURPOSE:To contrive the improvement of the stability in triboelectrification by using organic resin particles for which external additive having a specific particle size and a relative electric resistance and which are electrostatically charged with an inverse polarity against the resin particle incorporating a coloring agent at the triboelectrification, covering a core material with a mixture incorporating in the specified amount of an organic resin having a specific electric resistance as a carrier and preparing a specific particle size. CONSTITUTION:The external additive is 20-200mum in a particle size and has 10<6>-10<14>OMEGAcm of a relative electric resistance and is the organic resin particle electrostatically charged with an inverse polarity against the resin particle incorporating the coloring agent when triboelectrified with the carrier. The carrier is the organic resin whose relative electric resistance is in a range of 10<6>-10<14>OMEGAcm or a covered carrier having 25-65mum of a weight average particle size covered the carrier core material with a mixture incorporating >=70wt.% of the organic resin, at 0.05-10wt.% for the weight of the carrier material. Thus the rise of electrification and the level of an saturated charge capacity of the toner are improved in the various environments and can be maintained safely.
Patent JP-H06335826-A (JP)
Title: Wire electrode feeding device
Inventor: TERADA YUTAKA
IPC: B23H7/10
Filed: 1993-05-27
Abstract: PURPOSE:To provide a wire electrode feeding device in which the attachment and detachment of a highly heavy wire bobbin are facilitated, even an inexpensive highly heavy wire bobbin can be commonly used with the same structure, and a wire electrode delivered from the wire bobbin can be stably supplied to a wire discharge working machine body without causing fluctuation of tension. CONSTITUTION:A wire electrode feeding device has two ore more wire bobbin supporting rollers 1a, 1b arranged in parallel to each other, and the wire bobbin 12 of a wire electrode 11 is placed thereon and rotatably supported thereby without being fixed and held. This rotating means makes the wire bobbin removable from the wire electrode feeding device body and movable at any time according to the residual quantity of the wire electrode 11.
Patent JP-H05321431-A (JP)
Title: Construction method of interior with beam cover
Inventor: SAKURAI HIDEO
IPC: E04F13/08
Filed: 1992-05-19
Abstract: PURPOSE:To perform the construction of interior with a beam cover without requiring a professional workman and make the inside of the beam cover easily usable for piping and wiring. CONSTITUTION:Upper runners 12 with packings 13 disposed at appropriate spaces apart on the upper faces thereof are fixed into the specified positions of the ceiling face 1a and the lower face 3a of a beam part 3, and a lower runner 14 is fixed into the specified position of the floor face 15. A ribbed wall-side panel 16 is rigidly fixed across the lower runner 14 and the upper runner 12 fixed to the lower face 3a of the beam part 3. A runner 18 is rigidly fixed into the specified position of the upper edge part of the wall side panel 16, and the upper edge part of a beam side panel 19 with plural longitudinal ribs 19a disposed at appropriate spaces apart on the back face thereof is fixed to the upper runner 12 provided at the ceiling face 1a. A beam bottom panel 20 with a square bar 20a, jointed to the lower edge part of the beam side panel 19, rigidly fixed to one side edge thereof is rigidly fixed in contact between the runner 18 fixed to the upper edge part of the wall side panel 16 and the lower edge part of the beam side panel 19.
Patent JP-H01293618-A (JP)
Title: Plasma etching device
Inventor: ODA TAKAFUMI
IPC: H01L21/302
Filed: 1988-05-23
Abstract: PURPOSE:To effectively eliminate damage of a semiconductor substrate by providing irradiating means for irradiating ultraviolet rays or near ultraviolet rays within a chamber and by irradiating this light onto a semiconductor substrate where a damage has occurred. CONSTITUTION:A transparent port 9 is provided in a chamber 6 and a light source 8 for irradiating ultraviolet rays or near ultraviolet rays 7 opposing a port 9 is provided. After etching is completed by plasma, the light source 8 is turned on and ultraviolet rays or near ultraviolet rays are introduced into the chamber 6. Then, energy of ultraviolet rays or near ultraviolet rays 7 is given to a semiconductor substrate 3. It allows damage (for example, chargeup, neutral electron trap into gate film or induction of positive charge) positive charge produced on the substrate 3 to be effectively eliminated.
Patent JP-S6018550-A (JP)
Title: Production of pigment
Inventor: WAKASA MASANOBU
IPC: C09C1/42
Filed: 1983-07-12
Abstract: PURPOSE:To obtain a pigment having excellent coloring power and free from the problems such as carcinogenicity and miscibility with vehicles, etc., by using an ion-exchanging clay powder as the base, immersing the clay in an aqueous solution of a polyvalent metallic salt to effect the ion exchange, contacting with a liquid organic compound, and heating at a specific temperature. CONSTITUTION:The powder of an ion-exchanging clay (preferably having a cation exchange capacity of 80-500mg-eq/100g of clay, and having particle diameter of 0.2-500mu) is immersed in an aqueous solution of a polyvalent metallic salt (e.g. sulfate, chloride, etc. of Fe, Cr, V, etc. preferably having a concentration of 0.01-2mol/1) to effect the ion exchange reaction. The product is made to contact with a liquid organic compound (preferably a compound having a melting point of <=200 deg.C and a boiling point of >=20 deg.C, e.g. n-heptane). The treated clay powder is heated at 350-700 deg.C for e.g. 10min-3hr in a muffle furnace to obtain the objective pigment.
Patent JP-H07329451-A (JP)
Title: Automatic page feed mechanism
Inventor: SARUTANI MAKOTO
IPC: G07D9/00
Filed: 1994-06-08
Abstract: PURPOSE:To prevent the involution of a page and to enable the reduction of power consumption and miniaturization by simple constitution. CONSTITUTION:A page feed roller 10 is fixed to a center shaft 10a and the outer peripheral part thereof is allowed to protrude to a feed passage and the press roller 13a pressing a passbook to the page feed roller 10 is provided in opposed relation to the roller 10. A right guide 33 is supported so as to be revolvable around the center shaft and a left guide 34 is also supported so as to be revolvable around the center shaft in the same way as the right guide and both guides are made openable and closable at about 135 deg. by a stepping motor. The right guide 33 (or left guide 34) is brought to an open state at the time of page feed operation and, thereafter, middle paper is turned over upwardly by the page feed roller. After turning-over, the left guide is rotated in a closing direction by definite quantity to prevent the contact of the page feed roller 10 and the middle paper.
Patent JP-S63289998-A (JP)
Title: Multilayer circuit substrate
Inventor: ARAI TAKAFUMI
IPC: H05K3/46
Filed: 1987-05-22
Abstract: PURPOSE:To obtain a multilayer circuit substrate having excellent heat resistance and fire retardant property by containing in a resin layer fatty bromide and/or alicyclic bromide in polyimide resin and containing aromatic bromide. CONSTITUTION:Resin of a multilayer circuit substrate formed by integrally laminating a laminate in which an outer layer material is arranged through a resin layer on the upper and/or lower layers of an inner layer material contains in polyimide resin fatty bromide and/or alicyclic bromide, and also contains aromatic bromide. For example, two resin-impregnated base materials 2 obtained by impregnating a glass cloth having 0.1 mm of thickness with polyimide resin varnish made of polyimide, tetrabromethane, bromide diphenylether, N-methylpyrrolidone are arranged on the upper and lower surfaces of an inner layer material formed with circuits on both side surfaces of a both-side polyimide resin copper-extended circuit substrate, and copper foils having 0.035mm of thickness are arranged on the outside to prepare a laminate. The laminate is formed at 170 deg.C, and then aftercured at 200 deg.C to obtain a 4-layer circuit substrate.
Patent JP-S62282220-A (JP)
Title: Apparatus for measuring displacement of leading pipe in medium and small caliber propelling construction method
Inventor: MIKAMI TADAO
IPC: E21D9/06
Filed: 1986-05-30
Abstract: PURPOSE:To survey displacement without almost receiving restriction due to a small caliber pipe, by providing a target having an extremely small size to a leading pipe. CONSTITUTION:A target 2 is arranged to a leading pipe 3 so that two bright points 1, 1 are positioned within a vertical plane right-angled to the center line of the leading pipe 3 and the image thereof is picked up by the TV camera 5 mounted to the transit 6 anchored on a propelling planning line or the straight line parallel thereto. That is, the image of the target can be picked up if said target 2 has an extremely small size of about 2cm square and only a space capable of being viewed by the rearward TV camera 5 is secured. When the image signal of the TV camera 5 is inputted to a moving matter position measuring apparatus 7, the center-of-gravity position of moving matter (bright points 1, 1) is measured at every one TV frame and the data thereof is outputted to a personal computer (operational processor) 8. At the same time, the image signals of two bright points 1, 1 are visibly displayed on the X, Y coordinates picture of monitor TV12.
Patent JP-S5916464-A (JP)
Title: Shading correction device
Inventor: KURATA MASAMI
IPC: H04N1/401
Filed: 1982-07-20
Abstract: PURPOSE:To attain reproduction of an original with fidelity, by providing a programmable attenuator to the transmission line of a picture signal after photoelectric conversion for performing shading correction at each bit of the picture signal. CONSTITUTION:A correcting data indicating the degree attenuating the level corresponding to each bit of the picture signal is stored in a memory 11 so that the picture signal to a reference white section applied with photoelectric conversion at an original reader is brought to a constant level relating to the main scanning direction. An addressable latch circuit 7 reads out the correcting data from the memory 11 in synchronizing with the bit transmission speed of the picture signal. A programmable attenuator 3 is provided to a transmission line of the picture signal and corrects the level of the picture signal at each bit based on the read- out correcting data.
Patent JP-H08318851-A (JP)
Title: Control valve device in pneumatic brake system for backup
Inventor: EDOWAADO DABURIYU GOOGIYAN
IPC: B60T15/42
Filed: 1996-05-22
Abstract: PROBLEM TO BE SOLVED: To provide a control valve assembly for omitting a normal service part for a standard AB type cargo vehicle brake control valve, to utilize an emergency part only for controlling a backup pneumatic brake to an electropneumatic brake system. SOLUTION: In refilling a brake tube succeeding emergency brake actuation, a control chamber, for a restraining valve 42 into which brake cylinder pressure is supplied via high-pressure spool valve, is ventilated to the atmosphere, or brake cylinder pressure in a reverse damping passage 72 is separated from a brake tube, to ventilate a void 74 for a check valve to the atmosphere by using a plug 70 instead of a quick action emergency relaxing sheck valve. A means for discharging the brake cylinder pressure via the passage 72 can be realized, by displacing a reverse damp and spool valve to a relaxing position by an emergency piston during refilling the brake valve succeeding the emergency brake action.
Patent JP-H03277298-A (JP)
Title: Kit for saccharide-related enzyme activity determination and activity determination using the same
Inventor: ENDO MASAHIKO
IPC: C12Q1/48
Filed: 1990-05-18
Abstract: PURPOSE:To accomplish the title determination simply, accurately and in high sensitivity by incorporating the reduced terminal of a saccharide with a saccharide PA derivative with 2-pyridylamino group directly bound thereto. CONSTITUTION:About 10nmol of a saccharide PA derivative of formula I (G is galactose; GN is N-acetylglucosamine; Glc is a compound of formula II) is dissolved in ca.1ml of a 0.1M of sodium cacodylate buffer solution (pH ca.6.8) to obtain the objective kit for determining the activity of saccharide-related enzyme (e.g. endo-beta-galactosidase). Second, (1) 0.1-10mM of a sugar nucleotide (e.g. cytidine 5'-phosphate-N-acetylneuraminic acid) as donor and (2) a specimen containing a saccharide-related enzyme (e.g. blood, urine) are added to this kit followed by reaction at 10-50 deg.C and pH4-9 into a reaction product. Third, this reaction product is adsorbed and separated using e.g. an ion exchange technique followed by eluation. Thence, the resulting component is detected using e.g. a fluorescence detection technique, thus determining saccharide-related enzyme activity.
Patent JP-S616853-A (JP)
Title: Manufacture of semiconductor device
Inventor: KANDA AKIHIRO
IPC: H01L27/08
Filed: 1984-06-20
Abstract: PURPOSE:To increase the concentration of an emitter in a pnp transistor, and to obtain a high current amplification factor by newly adding an ion implantation process as the characteristics of a self-alignment system for a conventional emitter contact, etc. are left as they are. CONSTITUTION:A resist 77 is formed without considering allowance on a mask alignment, boron ions are implanted through only a nitride film 75, and an emitter 78 in a pnp transistor is shaped apart from the formation of an npn transistor, thus increasing the concentration of the emitter 78 in the pnp transistor. Consequently, the concentration of a base 65 can also be elevated, thus ensuring a high current amplification factor, then obtaining sufficiently high punch- through voltage even when base width is reduced in order to acquire the high current amplification factor. Since the concentration of the base 65 can be increased, base resistance can be reduced. Conventional characteristics in which a base contact, an emitter contact, etc. for the pnp transistor are self-aligned and density thereof is elevated are left as they are.
Patent JP-H11318153-A (JP)
Title: Vegetable harvester
Inventor: YANO NORIHIRO
IPC: A01D57/00
Filed: 1998-05-11
Abstract: PROBLEM TO BE SOLVED: To eliminate the problem of a pulling type root vegetable harvester lacking safety and permitting the adhesion and stagnation of withered stem leaves thereto, because a cover is not disposed. SOLUTION: The travel vehicle body of a vegetable harvester has a travel device whose power is transmitted from a travel mission device, and further has a harvesting and carrying device 4 disposed from a front lower position to a rear upper position. The harvesting and carrying device 4 comprises a pair of right and left nipping belts and is used for forcibly pulling out and carrying vegetables planted in a field. Neck-arranging belts 5 are disposed below the rear and high position portions of the nipping belts. Leaf-discharging belts 6 are disposed at a place below the final ends of the neck-arranging belts. A cutting device 7 is disposed behind the final ends of the neck-arranging belts. The cutting device, the neck-arranging belts and the leaf-discharging belts are covered with covers 9 from both the right and left sides in the vegetable harvester.
Patent JP-S5828665-A (JP)
Title: Watthour meter
Inventor: TODA MASAYOSHI
IPC: G01R22/00
Filed: 1981-08-13
Abstract: PURPOSE:To increase the processing speed of a circuit and to realize the application of a low-cost IC, by correcting the offset output at each prescribed time or each end of a prescribed number of times of use when the electric power is counted from the digital voltage or digital current of a circuit to be measured. CONSTITUTION:The voltage and current of a circuit to be measured are applied to the input terminals 1 and 2, and the terminals 1 and 2 are connected to the sample holding circuits 6 and 7 via the electronic switches 3 and 4 which are controlled by the output of an output circuit 5. A CPU10 feeds the outputs of the A/D converting circuits 8 and 9 to a storage device 12, and a prescribed program is set to an ROM13. The difference is obtained between the outputs  subjected to the A/D conversions 8 and 9 and the offset output obtained in the non- signal mode. These outputs are then delivered to an output circuit 14 after  multiplication, addition and accumulation. This offset output is stored, and the  working frequency is set at a prescribed level. The offset output is corrected  with each end of a prescribed working frequency. Thus the arithmetic speed is  increased for the CPU, and a low-cost IC can be applied for a circuit.
Patent JP-S5555491-A (JP)
Title: Address selection system of serial storage device
Inventor: YAMAMOTO TOMINOBU
IPC: G11C19/00
Filed: 1978-10-16
Abstract: PURPOSE:To shorten the average latency time of a storage device by controlling the shift clock frequency of a shift register so that the designated bit position in a storage loop may reach the I/O gate rapidly. CONSTITUTION:Address information is divided into two to input a loop selecting address and a bit position number address in the storage loop for location to address registers 50 and 51 respectively, and loop selecting shift register 40, location gate 30... are selected through counters 52 and 53 and subtractor circuits 67 and 77. Outputs of these substractor circuits 67 and 77 are subjected to a prescribed multiplication by multipliers 81 and 82 and are applied to comparator 83 as loop and location selection residual times; and if it is forecasted that location end is earlier than loop selection end, shift registers 10, 11, 12 and 13 for storage are shifted in a high speed through clock switching gate 57 by high-speed clocks till loop selection end, and then, the incoincidence generation frequency of location is reduced at a read/ write start time to shorten the average latency time.