Patent GB-874944-A (GB)
Title: Memory systems
IPC: G21C17/04
Filed: 1957-11-01
Abstract: 874,944. Circuits employing bi-stable magnetic elements. RADIO CORPORATION OF AMERICA. Nov. 1, 1957 [Dec. 31, 1956 (2)], No. 34236/57. Class 40 (9). [Also in Group XIX] Spaced pulses of intense amplitude and short duration are applied to a core formed of rectangular hysteresis loop material, each pulse producing a magnetizing force which is considerably in excess of the coercive force of the core material, and having a duration which is sufficiently short as to cause a momentary variation of the core flux without effecting any significant permanent change of the remanent magnetism. In an amplifying and gating arrangement, Fig. 4, short duration and intense amplitude pulses are applied from a drive source 44 to windings 51, 52 on a pair of cores 40, 42. When the core 42 is magnetized to a state N by D.C. energization of a set winding 48, the short-duration pulses each produce a momentary flux excursion towards state P and a large output pulse comprising positive and negative halves is induced in a winding 54. Output pulse generation is terminated by D.C. energization of a reset winding 50 which reverses the core magnetization to state P, and flux excursions in the saturated region due to the short-duration pulses generate only small output pulses in winding 42. The output is applied to a load 46 by way of a kicking winding 53 on core 40 and a rectifying and smoothing circuit 80, 86, the core 40 being magnetized in the P state by a reset winding (not shown) so as to suppress the small output pulses in the load circuit. The short-duration, pulses may also be utilized in a co-ordinate memory array, Fig. 6, comprising storage cores 100 and row and column windings 110, 116. In operation, coded signals representing two binary digits of order 2 and 21 are applied to a crystal diode decoder 102 the four-way output of which selectively enables one of four separate row driver gates in a word-selection switch 104. A pulse from an interrogation source 106 or a read-write source 108 is then able to pass to a selected row winding. Information stored in the memory is read out by applying a positive read pulse 124 to the desired row of cores through the selection switch 104, and the resultant output signals generated in the column windings by driving all the row cores to state P are applied to sensing amplifiers S1-S8. This phase is followed by a writing operation in which a negative pulse 120 is applied over the selection switch to a desired row, while a positive inhibiting pulse 126 passes over a digit driver circuit 112 to selected column windings in accordance with information applied to digit lines 115. Only those cores which receive a negative row pulse alone change to state N. The stored information is determined non-destructively by applying an intense amplitude and short-duration pulse 130 from the interrogation source 106 to a selected row winding. A further memory array is shown in Fig. 7 in which row and column windings 110, 220 are respectively associated with pulse driver circuits P1-P4, D1-D4, while a sensing winding 222 connected to an amplifier 244 is common to all the cores. Each pulse driver comprises a pair of pentode valves supplying a centre-tapped transformer, Fig. 8, and provides a positive (read) or a negative (write) pulse to a column or a row winding when energized simultaneously by a four-way decoder unit 234, 236 and a control pulse on a read lead 228, 229 or a write lead 230, 231. The control pulse originates in a control unit 232 which also operates the decoder units by way of an address register 238. In operation, a selected core is first read by applying intense amplitude, shortduration pulses to both the read lead 228 and the read lead 229, these pulses being spaced apart, and the pulse trains 249, 252 in the two leads interlaced as shown in Fig. 9. The core at the intersection of the pulse-energized row and column winding is thus subjected to a long duration and continuous magnetizing pulse 254 which drives it to a remanent state representing binary zero. The writing operation then takes place by applying the same pulse trains to write leads 230, 231, so producing a reversal of the characterizing state of the core if a binary one is to be registered. As the pulses applied to an unselected core by way of a row or a column winding are spaced apart by intervals t 2 , their intense amplitude and short duration is without practical effect on the remanent state. It is stated that the memory may be extended in a third dimension, in which case all the planes except the one containing the selected core are subjected to inhibiting pulses comprising negative-polarity pulse trains of the form shown in Fig. 9. Selection of a core in a two-dimensional array may also be effected by applying coincident, intense amplitude and short-duration pulses 291, 293, Fig. 10, to a row and a column winding, in which case the cumulative effect is sufficient to reverse the core state. As higher pulse amplitudes must be used in this case, each coincident pulse in the read or write leads is followed by non-coincident pulses 296, 295 of opposite polarity the purpose of which is to restore partially affected non-selected cores to their initial remanent state. An alternative pulsing arrangement is shown in Fig. 11 in which non-coincident pulses 297, 299 together have a sufficient duration and amplitude to reverse the state of a core, while their effect on unselected cores is neutralized by coincident pulses 301, 302. The two pulses in each train may both be coincident, Fig. 12, in which case the state in which a selected core is left is determined by application of the pulses as shown either directly or inverted. In a further arrangement, Fig. 13, a complete cycle of interlaced pulses 310, 316 provides effective read and write pulses 320, 330 at the selected core.