Patent GB-1450212-A (GB)
Title: Vertical deflection circuits
IPC: H03K4/72
Filed: 1973-11-09
Abstract: 1450212 Generating vertical deflection signals SANYO ELECTRIC CO Ltd 9 Nov 1973 [11 Nov 1972 (2)] 52224/73 Heading H3T A circuit for generating vertical deflection signals comprises means for generating a pulse train in response to vertical synchronizing pulses and means for producing from the pulses of the train a sawtooth deflection signal, the cycles of which each have a pulse component: the generating means includes control means for producing a control signal having values dependent upon other pulses produced in the generating means, or on the widths of said pulse components, and controlled means using such a control signal to control the widths of the pulses of the pulse train to a substantially constant value. Negative going rectangular pulses, the positions of the leading edges of which are determined by the frame synchronizing signals, but in which the trailing edge position is not accurately determined, are derived from vertical oscillator 4, Fig. 4, and applied to the base of transistor Tr5; the leading edge of each pulse turns it off and consequently the collector potential rises and transistor Tr6 is turned on. The pulses are also applied to transistor Tr1: each leading edge turns if off and allows capacitor C1 to charge via resistor R1. When the voltage across capacitor C1 is sufficient to turn transistor Tr2 on, its collector potential falls, turning transistor Tr3 on: consequently transistor Tr4 is turned on, whereupon transistor Tr6 is turned off again. The rectangular pulses of fixed width from the collector of transistor Tr6 are applied to sawtooth generator circuit 5 which drives deflection coil D via an amplifier comprising transistors Tr10, Tr11, Tr12. A second embodiment differs in that capacitor C1, Fig. 7 is coupled to the base of transistor Tr13 which derives emitter bias from transistor Tr14 with which it forms an emitter coupled pair. In addition resistor R6 over which capacitor C1 is charged is returned, not to a point of fixed potential, but via resistor R5 and smoothing circuit 11 to the output point J6: in this way, any change in output pulse width causes a voltage change which varies the rate at which capacitor C1 is charged up in such a way as to tend to counteract the change in pulse width (Fig. 8, not shown). In a third arrangement, transistor Tr15, Fig. 9 is normally non-conductive and consequently transistor Tr1 conductive, so that the base of transistor Tr13 is earthed and it is non-conductive: the other transistor Tr14 of the long-tailed pair is then conductive. A positive-going pulse from vertical oscillator 4 biases transistor 15 conductive, so that transistor Tr1 goes non-conductive and capacitor C1 starts to charge up via a constantcurrent source comprising transistor Tr16. When the voltage across capacitor C1 becomes sufficient to bias transistor Tr13 conductive, transistor 14 becomes non-conductive and its collector goes positive. At the end of the pulse from oscillator 4 the circuit reverts to its original state. The positive-going pulses at the collector of transistor Trl4 drive saw-tooth generator 5, the output of which is applied to drive circuit 7 driving output stage 8. The voltage across deflection coil D is smoothed by smoothing circuit 11 and constitutes the bias for transistor Tr14; the wider the pulses from transistor Tr14 the greater the bias on transistor Tr14 and so the higher the voltage necessary across capacitor C1 for transistor Tr13 to turn on and turn transistor Trl4 off (Fig. 8, not shown). In a fourth embodiment, in the pulse generator 4, Fig. 12, the capacitor C3 is uncharged at switch on, transistor Tr23 non-conductive and consequently transistor Tr22 conductive: transistor Tr24 biased from the collector of transistor Tr23 is non-conductive, rendering transistors Tr21 and Tr25 non-conductive. As a consequence transistor Tr28 is conductive rendering transistor Tr26 non-conductive. Transistor Tr22 receives a bias determined by resistors R21, R22, R23. Capacitor C3 charges up via repetition-frequency adjusting variable resistor VR until transistor Tr23 becomes conductive; this renders transistor Tr22 non-conductive and transistor Tr24 conductive whereby transistors Tr21, Tr25 are biased conductive. Conduction in transistor Tr21 reduces the base bias on transistor Tr21 by short-circuiting resistor R23. When transistor Tr25 becomes conductive a negative-going pulse is transmitted to sawtooth generator 5 and transistor Tr28 is rendered non-conductive. Transistor Tr26 then receives a positive bias from the network comprising constant-current generator transistor Tr27, resistor R26 and diode D, and its collector circuit provides a path for the rapid discharge of capacitor C3. When the voltage across capacitor C3 falls below the value at which transistor Tr23 is conductive, the circuit resets and the cycle is then repeated. The oscillations are synchronized by the application of positive pulses to the base of transistor Tr21 from integrator 2. Sawtooth generator 5 feeds drive circuit 7 coupled to output stage 8 and the output voltage at point J6 is integrated by smoothing network 11 to provide base bias for transistor Tr29: from its collector circuit transistor Tr27 is biased. The narrower the pulses from pulse generator 4, the less positive is the base bias of transistor Tr29 and consequently the less the bias of transistor Tr27: consequently a smaller bias is applied to transistor Tr26 and capacitor C3 takes longer to discharge (Fig. 13, not shown).