Patent GB-1399660-A (GB)
Title: Detector having a constant false alarm rate and a method for providing same
IPC: H03K3/013
Filed: 1972-09-29
Abstract: 1399660 Pulse radar; pulse circuits SPERRY RAND CORP 29 Sept 1972 [14 Oct 1971] 45024/72 Headings H3T and H4D A constant false alarm receiver comprises a first variable threshold circuit receiving wanted signals plus noise and providing output signals in response to wanted signals and noise exceeding the instantaneous threshold level, storage means poviding an output signal whose amplitude varies at a rate proportional to the rate at the the first threshold signals are provided, second threshold means providing an indication signal when said amplitude exceeds a preset value and means coupled between the storage means and the first threshold means to control the threshold value such that it produces a constant first rate of output in response to noise signals and a second rate of output in response to wanted signals. In a radar receiver the first threshold circuit is provided by an avalanche transistor 20 whose breakdown is dependent on its quiescent collector current. The transistor is range gated by a negative pulse 25A from monostable 25 triggered by generator 11 which also supplies the transmitter pulses 13. Input signals 15 which exceed the threshold cause transistor 20 to discharge capacitor 27 thereby triggering monostable 32. This pulse is read into an N-bit shift register 33 clocked at the transmitter prf. The N outputs therefrom are fed on one hand to an AND gate 36 which provides an indicator signal if all the outputs are "1", and also to a summing circuit 35 which provides an analogue output proportional to the number of "1" outputs from register 33. This analogue output determines the collector current of transistor 40 which is fed in parallel with transistor 20 from a power supply V+. When register 33 is empty, all the current drawn from supply V+ passes to transistor 20 which breaks down feeding a pulse into the store 33. The output of summer 35 adjusts the bias of transistor 40 drawing some of the collector current from transistor 20, which is now very sensitive to input signals (i.e. low threshold). The feedback is designed such that if only noise is present at the input an average of K "1" outputs are present in store 33. If the number stored is different from K transistor 40 adjusts the collector current of transistor 20 to adjust its sensitivity. Low pass filter 44 ensures that the adjustment of the sensitivity is slow such that rapid changes in the register content i.e. due to real targets do not immediately affect the sensitivity. If a real target is detected register 33 fills quickly and gate 36 indicates a target. In a first realization of the circuit (Figs. 3a-3b, not shown) the store 33 is formed by two cascaded eight bit shift registers and gate 36 by two eight input gates, two inverters and a two input gate. Monostables 32, 25 are formed from integrated circuits. In a second realization (Fig. 4, not shown) a binary up-down counter and N bit delay is used. Output signals from monostable 32 pass to the up input and then via the delay to the down input. Thus the counter content is the sum of the results of the last N transmissions. The counter outputs are monitored by logic circuits to give a target indication if the counter content is greater than M. The counter outputs are also fed via weighting resistors to a summing circuit to provide the feedback control.