Patent GB-906292-A (GB)
IPC: H04Q3/545
Abstract: 906,292. Automatic exchange systems. ERICSSON TELEPHONES Ltd. April 17, 1961 [Jan. 16, 1960], No. 1660/60. Class 40 (4). A number of magnetic core registers, any one of which can be seized by a calling line, are served by common control circuits and a translator, one core in each register being set to sense the loop condition of the associated calling line and all such registers being scanned cyclically to connect them one at a time to the common control circuits which modify the register content if a change of loop condition is detected but otherwise leave the content unchanged, the control circuits including counters which each deal with a particular dialled code or numerical digit in accordance with their connection to a register under control of magnetic core gates, magnetic core decoding matrices being supplied with code digit markings so as to provide a single input to a translator the magnetic core matrix of which thereafter governs the transmission of routing digits. General arrangement.-As seen schematically in Fig. 1 each register comprises a column of cores in a matrix the columns of which are read out cyclically by a full read pulse Ro. Each column has a core to mark the register busy, a core to sense an associated line's loop condition, five cores to time the loop closed condition, five cores to count the incoming digit trains, seven sets of five cores to store the incoming digits; all these cores being associated with a section of the common control circuits termed an "in computer " the remaining section of which is termed an " out computer." The out computer supervises the transmission of digits and works with cores in each register comprising a 100 ms. counter for timing impulses using five cores, five cores to time an inter-train pause, five cores to register a digit for transmission, five cores to record the rank of digits sent and the next to be sent, two cores to control the impulsing of the line, two cores to supervise normal release and four cores working in conjunction with normal release to conduct forced release, and three cores timing intervals of 30 seconds to initiate forced release of the register and translator. Each interrogation of a register is initiated by a full read pulse Ro, best seen in Fig. 8b. During read-out a so-called process pulse R1 gates the information to the common circuits where operations are governed by reset pulses R2, R3 and R4. At the end of a control period, which lasts for 140 microseconds, a re-write pulse RW in coincidence with a halfwrite pulse on the register column passes information from the common control circuit back to the register until the next interrogation in the cycle. Pulses TP1, TP2, one coincident with R3 and one lagging slightly, read out complete code digits from the common circuits to the translator. Counting circuits.-In its association with the common control circuits each register section, such as that shown in Fig. 4(a) of four cores storing 2 out of 4 code, is associated with two triangular arrays of cores into each of which the 2-out-of-4 code is written in the corresponding 1-out-of-6 code. Read out by Ro energizes two of the leads a, b, c, d, and in each triangular array biases all cores but one. The application of a pulse R1, coincident but slightly lagging RO, on a wire in common to both arrays in consequence switches the one core in each array which is unbiased. Read-out wires from each array, shown with distinctive dot-dash line combinations, provide half-write pulses on each of a particular pair of row wires in the register section depending on which core of an array is read out. For the left-hand array, called the " repeat matrix," read-out of a switched core provides half-write pulses to restore the information originally read out of the register. For the right-hand array, called the " advance " matrix, read out of a switched core provides half-write pulses to advance the information originally read out to the next code combination. Whether the information is repeated or advanced depends on a signal d which enables gates G1, G2 so that pulse R3 clears the repeat matrix and RW reads out the advance matrix. With α absent gates G3, G4 are open to clear the advance matrix with R3 and read out the repeat matrix with RW. The gates G1 to G4 are, in fact, cores 1 to 4 shown in Fig. 6a and the bi-stable circuit FF is inherent in the action of the cores. Normally cores 1 to 4 are set in the direction of pulses R3 and RW. With a absent cores 1 and 2 are reset by R1 so that subsequently R3 drives wire X to clear the advance matrix and RW drives wire Y to read out the repeat matrix. With α present cores 1 and 2 are biased against R1 while cores 3 and 4 are switched so that R3 clears the repeat matrix over Y and RW reads out the advance matrix over X. The symbolism used for repeat and advance matrices can be seen from the " phase counter " at the top of Fig. 13 where the ten cores of an array accepting a 2-out-of-5 code from a register section are shown as a row of two state elements numbered according to their code significance. The connections between the arrays and the register are not included in the symbolism. Switching between matrices is symbolized by the two pole switch GP with inputs, in this instance, R4 and RW. Auxiliary inputs may be applied, as with the signal # to disturb the normal function of a matrix. The matrices need not be confined to regular repeat and advance functions but may act anomalously as is shown in Fig. 7a where read-out of an element of a matrix writes the code indicated below the element by an encircled number. Seizure of free register by calling line.-Each register has a so-called access unit connected individually to the seizure and sensing core of its register and connected in common to the row wires of the release and outgoing impulse sections of the matrix formed by all registers. An idle access unit (see Fig. 15, not shown) is seized for a call over a conventional A-digit hunter in a 1st code selector. Once taken into use the access unit biases the seizure core of its register so that it ceases to provide its normal output on interrogation. The normal output of a seizure core inhibits the supply of process pulses R1 to the common control circuits, which cannot, therefore, register read out from the register, and establishes in the register an appropriate initial record called the " free pattern." With the seizure core biased the common control circuits take notice of interrogation and watch for changes in line condition. Detection of dialled impulses.-As shown in Fig. 7a the closed loop condition of a calling line is timed and registered on 5 cores of a so-called " make length " counter. The counter comprises a " break " and a " make " matrix employing only eight of the possible 2-out-of-5 codes. The break or make matrix is employed depending on the switch GML which has the position shown if the loop is closed and the register sensing core is biased to prevent a normally generated output and which throws over if the loop opens before interrogation. Initially the loop is closed and the make matrix registers 8 which it automatically re-writes. When the first dialled impulse is encountered the 8 registered in the break matrix is read out to write unity in the register. When unity is read back at the next interrogation the pulse R2 clears the make matrix of unity and generates a dial pulse signal. Pulse RW subsequently reads out the break matrix which writes 2 and continues to do so for the rest of the impulse. When the loop closes, the make matrix is read out for as long as it is closed and advances from a registration of 2 to a registration of at least 3 and at most 6 for the interval between impulses of a train. Whether the next impulse comes at 3, 4, 5 or 6 the break matrix is connected up and writes 1 in the register which is read out to signal the pulse as before followed by idling with the registration 2. An inter-train pause enables the make matrix to advance beyond the registration 6 and the reading of 7 from the register and its clearing from the break matrix gives an end of digit signal I.T.P. Distribution and registration of digits. As shown at the top of Fig. 8a the eight-core repeat and advance matrices of a distributer cooperate with a 2-out-of-5 code section of the register to count the end-of-digit signals I.T.P. The registration in the distributer determines which one of the seven register digit sections and associated repeat and advance matrices are employed to register a digit. The occurrence of a dial pulse signal determines whether a digit section advances. With the distributer normally registering unity the digit register sections are all read out and repeated, the repeat matrices being gated over cores, shown as two-state elements, that are set at R1 and turned over at RW. The advance matrices are cleared by drive from a core DC-C9 which is set at R1 and restored at R4, each advance matrix having a clearing drive core such as CDA-C2 which is set at R3 and turned back at R4. If a digit signal is received a core DC-C8 is set by it at R2 and turned over at R3 so that a gate marked by unity cleared out of the distributer advance matrix at R3 allows core DC-C1 to set and be turned back at R4 to clear down the 1st code digit repeat matrix and all but the 1st code digit advance matrices. By this means the 1st digit register stores unity. Further digit signals are counted in the same manner. At the end of the digit a pulse I.T.P. advances the distributer to register 2 and by removing the setting input of drive core CDA-C2 prevents further advance of the completed digit. A control core DC-C2 is now marked to gate digit signals so as to clear down the second digit repeat matrix and all advance matrices of digits beyond the second. The seven digits are registered by this means and the last end of digit signal I.T.P. advances the distribute