Patent GB-1420548-A (GB)
Title: Control apparatus for controlling a display
IPC: G06F3/147
Filed: 1974-06-06
Abstract: 1420548 Displays INTERNATIONAL BUSINESS MACHINES CORP 6 June 1974 [26 June 1973] 25104/74 Heading G4H Apparatus for controlling a crosspoint panel display includes a command decoder, a decoder to decode signals identifying the crosspoint at which a pattern starts, pattern storage means operative to store representations of patterns one of which can be selected in response to a decoded command, and counter means operative to generate a sequence of control signals which select the crosspoint at which the pattern starts and subsequently the remaining crosspoints of the pattern. In Fig. 1, a processor 10 via an interface 12 can supply command and data bytes to a data flow chip 26 on a bus 32 and address character images in a ROS 30 which also feeds the data flow chip 26 on bus 32. A control chip 28 interacts with the data flow chip 26, and they can set bi-stable vertical and horizontal line drivers 18, 19 of the gas discharge, electroluminescent or liquid crystal panel display 15 via isolation circuits 20, 22 to select which lines will be energized by sustain, write or erase signals from analog power circuits 24 controlled by the control chip 28. Figs. 3A, 3B show the data flow chip 26. The commands which can be received on bus 32 (top left, Fig. 3A) are four initial position commands (vertical and horizontal coarse and fine), write character, write slice, erase data, and erase panel. The commands are decoded at 34. Write and erase commands are encoded at 62 and sent to the control chip 28. Position commands set respective latches 36, 38, 40, 42 which in conjunction with a decoder 44 (bottom left, Fig. 3A) responsive to the control chip 28, route a data byte following the position command via a store register 66 into the coarse or fine section of the horizontal or vertical position register 56, 54 as appropriate (only the least significant bit is used in the case of coarse bytes). A write character command is followed by a character byte which is converted into the ROS address of the first slice (horizontal line) of the required character, this address being stored in an address register in the interface 12. The vertical position at which the first slice of the character is to be displayed is read from position register 54 (into which previous position commands inserted it) and loaded into a counter 76 which, in part via a decoder 78, sets the appropriate horizontal line driver. Counter 76 is then incremented and the count gated back into position register 54. The contents of a slice register 82 (Fig. 3B), initially reset to zero, are inserted into a counter 74 and sent to the interface 12 to increment the ROS address (by zero this time). The slice from the ROS is loaded into register 66. The contents of counter 74 are incremented by one and stored in the slice register 82. The horizontal start position of the character is passed from position register 56 into counter 76, and counter 74 is preset with "7". Counters 74, 76 are incremented together until counter 76 reaches "15", and at each count, counter 76, via decoder 78 &c., sets the corresponding vertical line driver if a bit position in register 66 selected by counter 74 at a decoder 84 is "1". Write and sustain signals are then applied to the panel. The above procedure is now repeated to obtain and display successive slices of the character, until a stop bit is detected in the slice from the ROS. A write slice command is similar, mutatis mutandis, except that the byte following the command is the slice to be displayed. A single such command may be followed by a series of bytes to be displayed. Graphics, &c. not available from the ROS may thus be provided by the processor. An erase data command is followed by a byte containing the numbers (4 bits each, in 15-complement form) of vertical and horizontal lines to be erased, starting at the position previously loaded into the position registers 54, 56 by position commands. Counter 76 is loaded from position register 56 and the number of vertical lines to be erased is loaded from register 66 into counter 74, the two counters being incremented together until counter 74 reaches "15". At each count, decoder 78 &c. sets the vertical line driver specified by counter 76. The appropriate horizontal line drivers are then set by a similar procedure using the same counters. Erase signals are then supplied, followed by sustain signals for the rest of the panel. An erase panel command causes the whole panel to be erased.