Patent GB-1120500-A (GB)
Abstract: 1,120,500. Multiplex pulse code signalling; automatic exchange systems. WESTERN ELECTRIC CO. Inc. 16 May, 1967 [24 May, 1966 (2)], No. 22652/67. Headings H4K and H4L. In a time division multiplex pulse code modulation system wherein a distinctive framing pattern is transmitted and an additional digit space is provided for each channel for the transmission of ringing and other signalling information, binary digits are inserted in predetermined ones of the additional digit spaces in such manner as to prevent the simulation of the framing pattern. As shown, in Fig. 2, the input signal on, for example, channel 1 in terminal W is supplied to a signalling detector 11 which is sensitive to the signalling states applied to the channel by the associated central office switching equipment and converts the detected signalling state to digital form on leads A1, A, four different states being provided for by combinations of binary 1 and binary 0 on the two leads. A signalling regenerator 12 converts the different combinations of binary 1 and binary 0 from terminal E into the corresponding signal states on leads B1, B for application to the central office switching equipment. Encoder-decoder unit 13 includes a hybrid network for each channel to separate the two directions of transmission, a sampling gate for each channel to interleave samples from successive channels in time division multiplex, a common encoder, and a common decoder with its associated distributer. The bit stream from unit 13 is transmitted via line 14, which includes pulse regenerators 15, 16 spaced at regular intervals, to similar equipment at terminal E. Transmission from terminal E to terminal W is via line 20 which includes pulse regenerators 21, 22 &c. The output of a framing and common signalling transmitting unit 23, terminal W, is connected to the encoder output of unit 13 and receives the signals on leads A1, A, a similar unit 24 being connected to the encoder output of unit 17 in terminal E. To recover the signalling information received via line 14 at terminal E, a common signalling receiving unit 25 is connected to the output of line 14 and supplies signals via leads B1, B to the corresponding input leads of the channel signalling regenerator 18 &c., unit 26 operating similarly at terminal W. Each terminal includes conventional framing circuitry for recovering the frame sync. signal consisting of alternate binary 1 and binary 0 in successive frames. In units 23, 24 a binary counter 31 is supplied with a pulse during each framing digit space FR, the state of the counter being reversed by each pulse to provide a waveform F1, F0, F1, F0, where F1 is a positive voltage lasting for a full frame and F0 is zero voltage lasting for a full frame. To generate the alternate binary 1 and binary 0 for the framing signal the input FR and the " 1 " output of the counter 31 are supplied to an AND gate 32 whose output is passed via an OR gate 39 to the output circuit. The " 1 " output of counter 31 is also supplied to a counter 34 and an AND gate 35, the " 1 " output of counter 34 (F1, F1 F0, F0) providing the second input to AND gate 35. The " 0 " output of counter 31 (F0, F1, F0, F1) is supplied to an AND gate 36 together with the " 1 " output of counter 34. The output of AND gate 35 (F1, F0, F0, F0) is thus positive only during the first frame of each group of four frames and is supplied to an AND gate 37 to control the transmission of the signalling information on lead A1 of unit 23, Fig. 2. Similarly, the output of AND gate 36 (F0, F1, F0, FO) is positive only during the second frame of each group of four and controls via AND gate 38 the transmission of signalling information on lead A of unit 23. The third inputs of AND gates 37, 38 are supplied with gating pulses in every signalling digit space of each channel, the outputs of gates 37, 38 being supplied via OR gate 39 to the output circuits, the waveforms from gates 35, 36 inserting binary 0 in the signalling digit space in the last two frames of each group of four successive frames to ensure that a false framing signal is not generated. A logic circut for the common signalling receivers 25, 26 also is described, Fig. 4 (not shown).