Patent GB-1156641-A (GB)
Title: Controlling Interchanges between a Computer and Many Communications Lines
IPC: G06F13/12
Filed: 1967-03-13
Abstract: 1,156,641. Computer control unit. RADIO CORPORATION OF AMERICA. 13 March, 1967 [18 March, 1966], No. 11577/67. Heading G4A. A communications control unit for controlling the interchange of data between a computer processor and many line buffers of a number of respective communication systems, where at least one of the systems uses message protection control characters includes a memory for the storage of as many line status words as there are communication buffers, a line scanner sequentially accessing the line status words and logic means responsive to control words to generate commands causing data to be conveyed and identified to the computer processor or to direct the performance of message protection functions. In the processor shown in the figure data and control lines to and from the computer are on the left, to and from the buffers are on the right. A high speed random access memory HSM stores the line status words in memory addresses corresponding to the address of the appropriate buffer and also stores as many operation words as there are different sets of control functions to be performed in response to control characters received from or sent to the many communication lines. The line status words are sequentially accessed by scanners controlled by a sequencer SEQ, the words read out being supplied to a number of registers connected to logic units L 1 , L 2 , L 3 . Data to and from the processor passes along lines DIN and DOUT respectively, the source and destination respectively of the data being determined by a switch SW enabling data to pass along the appropriate line. Loading of memory.-The special address of a logic unit L 6  is sent from the processor to an address decoder AD. A MC output causes a logic unit L 4  to condition paths for loading the memory with words supplied by the processor. Thereafter logic unit L 4  sends a service request on line SR each time it is ready to receive another character. When the memory is completely loaded unit L 4  sends an end signal, and then a read word returned from the processor causes unit L 3  to put the scan units into operation. Activation of buffers.-The processor sends a buffer address to the memory causing the line status word associated with that buffer to be read out. The contents of register SDB, relating status and historical information, are sent to the processor and a read or write comment returned and stored in the C&C register. The contents of all the line status words are then returned to the memory. This is repeated for all the buffers. The sequencer then reads out all the words in turn and the selected and commanded buffer is put in condition to receive or transmit information over its communication line. Character transfer.-Transfer from the processor is accomplished when scan unit P accesses the appropriate line status word. Character register CHAR is assured to be empty and causes logic unit L 1  to send a service request to the processor. The address of the line status word is then sent to the processor to be identified as the address for a buffer which was commanded to send messages to its communications line. The processor then sends a data message character to be stored in register CHAR. The line status word is then returned to memory. Subsequently each time the line status word is accessed the word in register CHAR is sensed by logic unit L, and modified in number of bits and parity, if required, to meet the code required by the appropriate receiving station and the word is transferred to the register A & D. The buffer sends a ready signal and one bit is transferred. The process is repeated next time the line status word is accessed. A similar procedure occurs when data. is transferred from the buffer to the processor, one bit of the word during each accessing of the line status word. Data transfer interruption.-If a block of memory space in the processor memory is filled the processor automatically obtains a new block but may require notification. The first character transfer to the new block causes an interrupt reading to be set in the register SDB. The cycle concludes with the return of the line status word to the high speed memory. At the end of each cycle of the scan unit P the sequencer SEQ initiates a cycle of the interrupt scan unit I. When the unit I accesses a word containing an interrupt pending indication logic unit L 2  sends an interrupt signal to the processor. This dentifies the line status word and receives the contents of the SDB register. The logic unit L 2  resets the interrupt pending location and tha processor initiates an interrupt routine to deal with the interrupt. Communications control characters. - The various systems may have characters concerned with synchronizing, beginning and end of transmissions, attention, cancel, repeat and may be different in different systems. Thus a control character appearing in register CHAR is identified by logic unit L 1  and the particular system using the character identified by register SYST is recognized by L 1  causing register AG to supply the address of operation word used to control the message protection functions called for by the communications control character. The operation word accessed may require the computer to be informed of special conditions requiring action by the processor. This need is indicated by bits of the word stored in register OP and decoded by decoder L 5  to supply a communications message required to a sequence control unit SCU. This issues a service request and enables gate 5. The address of logic unit L 6  stored in unit AL6 is passed to the processor which enables switch SW to pass the address of the accessed buffer to the processor which is then stored in a location assigned to logic unit L 6 . The processor then repeats the sequence of receiving a service request, an address (of unit AL 6 ) and a data character (a communications receiving byte). The processor is then sent an INTL signal indicating an interrupt condition (a communications reporting message). After every cycle of scan unit P and before the I cycle sequencer SEQ sends a sense interrupt signal. If INTL is set an interrupt signal passes gate G6 on the INTOT line, and switches S 1 , S 2  engage positions. The processor identifies logic unit L 6  and causes gate G 7  to pass the contents of register SDB 2  to the processor which is then alerted and enters the appropriate routine. The communications system may be synchronous or asynchronous, be magnetic tape or drums, printers, card punches and readers or tape punches and readers and may include a multiplexing unit.