Patent GB-869586-A (GB)
Title: Non-synchronous to synchronous binary code converter
IPC: H04L7/04
Filed: 1959-01-05
Abstract: 869,586. Code telegraphy. COLLINS RADIO CO. Jan. 5, 1959 [May 5, 1958], No. 378/59. Class 40(3) ' In an arrangement for converting "-character code combinations comprising a plurality of baud periods, or code elements from an incoming non-synchronous form to an outgoing synchronous form by means of one or more sets of synchronous sampling pulses, parallel paths are provided for the non-synchronous signals which are delayed in one of the paths for a fraction of an element period, the time phasing of the sampling pulses in relation to the general mid portion of the element periods of the signals on each path is ascertained, and the path with the signals having their mid portions more nearly in phase withthe sampling pulses is utilized to produce the synchronous outgoing signals. In a modified arrangement, the incoming data is scrutinized by two sets of sampling pulses interleaved and relatively displaced by half an element period, to ascertain which of the sets has its pulses occurring in the central portion of a code element period. The set fulfilling this condition is employed to sample the incoming non-synchronous signals to provide the synchronous output. In the diagrammatic arrangement, Fig. 3, the non-synchronous input is fed over line 31 to a switching circuit 36 over line 32 to a circuit 37 providing an output conductor 39, a -delay equal to half an element period, and over connection 33 to a circuit 38 which determines whether the normal or delayed input shall be sampled to provide the synchronous output. The circuit 38 receives the sampling pulses B and a further set of synchronous pulses A displaced from the pulses B by half an element period. If the circuit 38 indicates that one of the pulses B occurs in the central part of the start element, the non-delayed input over line 31 is to be sampled, and a signal from the circuit 38 moves the switch SW to the left-hand position. If, however, a pulse A occurs in the mid-portion of the start element, indicating that the delayed input on conductor 39 is to be sampled by the B pulses, the switch SW is not moved from its position shown. The actual or delayed input signals are passed over line 40 to gate 43 controlled by the sampling pulses B to operate a circuit 44 to produce the appropriate synchronous binary output at 45. In a modified arrangement, Fig. 4, the non-synchronous input at 30 is applied to a gate 63 in the switching means 36, and also to a gate 51 which samples the input by means of the synchronous pulses A separated from the B sampling pulses by half of the time period of a signal element. The output of the gate 51 is applied to a synchronous storage device having its output fed to a further gate 62 in the switching means 36. The incoming signals are also applied to an arrangement 71 producing a delay of about one quarter of an element period and connected at input 91 to the fourth stage of a counter 70 which in its normal condition at the end of a signal provides an output a closing the gate 72 to the synchronous pulses A. The delayed start pulse reverses the stage 4 of the counter so that it provides a b output to open the gate 72 to the "A" pulses. The reversal of stage 4 by the delayed start pulse also reverses stage 1 of the counter so that its normal b output is replaced by an a output which in combination with the existing a outputs from stages 2 and 3 of the counter operates "AND" gate 76 to provide a pulse to open gate 77. The gate 77 remains open until the first A pulse after the delayed star pulse steps the counter so that the three a inputs are no longer available to operate the "AND" gate 76. If a B pulse appears whilst the gate 77 is open it passes to the decision flip-flop 82 to reverse its outputs and open gate 63 whilst at the same time closing gate 62 to the output of the storage device 56. The non-synchronous input passes through gate 63, "OR" gate 66 to a gate 43 opened by the B synchronous pulses, slightly delayed at 50, to control the flip-flop 44 to provide the synchronous output signals. If, after the delayed start signal element, an A pulse occurs before a B pulse and the counter 70 makes one step, the gate 77 is closed to the B pulses, the flip-flop 82 is not switched over and gate 62 is open to the input sampled by A pulses which is passed by the "OR" gate 66 to the gate 43 which in effect samples the centre portion of the pulses produced by the A pulses and so controls the flip-flop 44 to pass the synchronous output to terminal 45. If flip-flop 82 has been triggered by a B pulse through gate 77 it is returned by a pulse b from the third counter when its condition is changed over on the 7th pulse A following the delayed start signal element. A modification, Fig. 6 (not shown), of Fig. 4 employs a one-shot multivibrator to produce the pulse corresponding to the start pulse delayed by one quarter of an element period and this circuit in addition to the storage and decision flip-flops comprises transistors, together with differentiating circuits included to provide operating pulses of appropriate polarity. The arrangement of Fig. 6 (not shown) also operates to suppress a false start. A bistable trigger circuit and a one-shot multivibrator circuit, each including transistors, are described respectively in connection with Figs. 8, 9 (not shown).