Patent GB-841063-A (GB)
Title: Improvements relating to register-translator arrangements
IPC: H04Q3/42
Filed: 1957-09-08
Abstract: 841,063. Automatic exchange systems; circuits using saturable magnetic elements. SIEMENS EDISON SWAN Ltd. Sept. 8, 1958 [Sept. 9, 1957], No. 28380/57. Classes 40 (4) and 40 (9). Each of a number of translation digits produced from a magnetic drum in response to dialled code digits passes to a register-sender over a group of gates corresponding to the order of the translation digit, the groups of gates being opened in turn by a counter which is stepped at each revolution of the drum, the register selecting the required translations over a further common gate which is opened each time the appropriate address code agrees with the dialled code and the counter indicates the next wanted order of translation digit. The magnetic drum store.-Information is stored on the drum for parallel access, 1000 addresses being stored in the 30 A, B and C tracks, Fig. 1, or alternatively, in one track, Fig. 7, and eight sets of seven tracks containing control signals and a maximum of eight translation digits. Four out of each of the sets of seven tracks register a translation digit and the remaining three cope with indications of digit cut-off, to mark the end of a translation digit train; code only conditions where code digits such as TIM are not followed by numerical digits: and spare code where no translation is registered at an address. The address of each storage space produces a mark on one of each of the three sets of ten wires A, B, and C ; the A wires being commoned to particular sets of registers while the B and C wires are commoned to all registers. If the thirty address tracks of Fig. 1 are used the address code is stored in an obvious manner but it is shown in Fig. 7 that one track is sufficient if it produces a pulse from each address and steps three decimal counter stages to mark the A, B and C wires. The A digit seizes a register in a group associated with a particular A wire while the B and C digits connect the B and C wires to selected contacts of switches BS and CS in the register. Whenever the address marking corresponding to the connected A, B and C wires occurs, a gate MMG has three input wires marked and to be opened requires a further mark from a counter CC. The counter CC repeatedly counts eight revolutions of the drum and only opens MMG when, as determined by a switch TDS, the counter also opens the appropriate set of gates 1G to 8G for the wanted order of translation digit. With MMG open a common set of gates GR is opened to transmit a translation digit or control signal to the register. Receipt of dialled digits.-Following the A, B and C digits four numerical digits are received and stored as binary complements in rows of bi-stable cores DS1 to DS4 after being counted into the binary counter RC. As each digit after the A digit is received the switch RD is stepped and sends the B digit to magnet mbs of switch BS, the C digit to magnet mcs of switch CS, and for the remaining four digits connects up impulsing relay AA. In response to late restoring contacts c3 of the C relay a monostable circuit MT is triggered to bring up relay R and to produce a positive followed by a negative pulse on line col from capacitor CC2. The positive pulse on col is a read-out pulse and the negative pulse sets all the cores of counter RC to a zero state. To provide a longer switching time the bottom cores have twice the material and conveniently comprise two cores wound together. Digits repeated by aal are applied over lead pl as earth pulses which by discharge of capacitor CC1 switch an input core C to switch both cores of the first stage of RC, the output windings owr of which are connected in opposition and consequently produce no net output. A continuous bias over bwr restores the top core of the state to zero leaving the bottom core switched to one. The next pulse again switches the top core and the consequent output in its winding owr triggers the bottom core to reset as a single stroke blocking oscillator with transistor trr conducting. Resetting of a bottom core provides an input to the next stage and so forth. At the end of the digit train and before late closing contacts c3 restore contacts c2 restore to connect a priming bias over switch bank rdl to the cores of store DS1 so that when c3 restores monostable circuit MT is triggered and a positive pulse switches all the cores of counter RC to one. This causes all bottom cores of the register not at one to switch so that their associated transistors conduct and drive column wires to register the binary complement of the dialled number in DS1. At the end of each pulse train RD steps to switch bias to stores DS2, DS3, and DS4, in turn. - Transmission of digits.-Over the third contact of rd2 relay CO responds and operates BG by discharge of capacitor CC4 in conjunction with transistor tel. When the wanted address marks the A, B and C wires and the counter CC marks the first contact of the distributer TDS (which is level sd2 of switch SD) MMG opens gates GR while CC opens gates 1G and over leads ol the first translated digit is written into the cores of a store DS5. To read the digit, gate TMG is opened to trigger monostable circuit MS and operate relay RR which over switch bank sd1 puts a resetting bias on the store DS5 to produce putputs from the set cores over rectifiers rf to transfer the digit to a counter SC of the same type as counter RC. A relay pulse generator P counts out the digit registered in SC and repeats the pulses to line by contacts p2. When the last stage of SC is switched an output is produced in winding owxa of auxiliary core X which operates relay AG and releases BG. When AG operates, a pulse over capacitor CC3 switches the unstrapped ones of the cores in a store DS6 to produce an output in the column wires to set counter SC to a predetermined digit which is counted out in a time which constitutes the inter-digital pause. A contact of AG masks the impulse contacts p2. Core X is again switched at the end of the pause and an output from winding owxb operates relay BG and drops AG which steps magnet msd of switch SD. As each outlet of sd2 is reached a translation digit is transmitted until a digit cut-off pulse is picked up and over gate GR5 opens gate SMG to trip bi-stable circuit TT1 which holds mono-stable circuit MS and relay RR operated. Contacts rr1 now connect read-out bias to stores DS1 to DS4 in turn over switch bank sd1 and transfers each digit to counter SC which is pulsed out in the same way as with translation digits with relays AG, BG, interacting to step SD. On its last contact sdl operates DD to halt impulse generator P. Should fewer than eight translation digits be involved further digit cut-off signals are sent over GR5 to gate IIG which is uninhibited in the empty digit spaces and allows relay DA to respond and step SD until the first numerical digit contact is reached when TT2 releases DA. During the blank digit spaces MMG is inhibited. Spare code and code only conditions.-When no translation exists for a dialled code a signal is picked up over GR7 to operate TT3 and energize relay DB to disconnect pulse generator P and revert NU tone. When codes such as TIM and 999 are used a signal is picked up over gate GR6 to operate TT4 which energizes relay DC to halt impulse generator P. Saturable transformer gates.-Each set of seven translation digit and control pick-up heads of the magnetic drum may be connected to a saturable core gate as shown in Fig. 6, all the cores being normally biased to saturation so as to effect no inductive coupling. The gates G01, for instance, are opened by a counteracting bias on lead Pl1 switched from counter CC to move the cores from saturation, signals from heads lh being coupled with output windings ow and a row of cores Ro being also desaturated by contacts cco to couple the signals with amplifiers Ta. Leads Pl1 to Pe8 are connected to counter bias in sequence by counter CC. As digit cut-off and spare code signals are mutually exclusive they may be registered in a single track the outputs being gated to amplifiers TA5 or TA6 depending on which of the auxiliary cores R0<SP>1</SP>, R0<SP>11</SP>, is desaturated from control terminals tt, tt<SP>1</SP>.