Patent GB-1046805-A (GB)
Title: Electrical coding circuit
IPC: G06F11/10
Filed: 1963-08-02
Abstract: 1,046,805. Circuits employing bi-stable magnetic elements. STANDARD TELEPHONES & CABLES Ltd. Aug. 2, 1963 [Aug. 8, 1962], No. 30726/63. Heading H3B. [Also in Division G4] The arrangement shown in Fig. 3 of an exclusive OR gate is extended to form electrical coding or decoding circuits. The basic circuit of Fig. 3 comprises two cores A, B each provided with a set 1, 4, inhibition 2, 5 and an output winding 3, 6. If source PS 1  delivers a pulse with switch S open core A is inhibited and core B set and capacitor C is charged first with a high time constant due to the impedance of winding 4 and then with a low one after the core B has been switched. On closing switch S the capacitor is discharged through windings 1, 4 and resets core B. The circuit of Fig. 3 may be extended to form a decoder circuit, Fig. 4 (not shown), for decoding a complementary two-outof-five code into a decimal system, which circuit comprises a single discharge circuit and five charging circuits for the capacitor C, the complementary code being applied to input terminals A 1 -E 1 . Figs. 5, 6 (not shown) are extensions of Fig. 4 forming binary-to-decimal decoders. Figs. 7, 8, 9 (not shown) show how the basic circuit may be applied to three different forms of code comparators. The sequential selector circuit of Fig. 10 (not shown), selects one of several variables in the " 1 " condition from a set of input binary variables applied to terminals A to E according to the preferential order XYZUV. Three exclusive OR circuits of the type shown in Fig. 3 may be connected together, Fig. 11 (not shown). The binary-todecimal decoder may be included in a pure binary to two-out-of-five code converter, Fig. 12 (not shown), which may be extended to form a pulse counter, Fig. 13 (not shown), in which a two-out-of-five code is decoded into a numerical code having a value K by a decoder circuit, which code is afterwards converted into a two-out-of-five code corresponding to a numerical value K + 1. Static Memory Unit.-Fig. 14 comprises a memory matrix, interrogation circuit and a read out information detection circuit, the interrogation circuit including a two-out-of-five decoder circuit of the type disclosed in Fig. 4 having cores 0 to 9. When a particular input address is applied to input terminals A<SP>1</SP>B<SP>1</SP>C<SP>1</SP>D<SP>1</SP>E<SP>1</SP> one of the cores 0 to 9 is set, e.g. core 0, and during the reset period whilst storage capacitor C1 is discharging through switch S a blocking oscillator T0 associated with core 0 is triggered and the read current pulse produced at the collector thereof is delivered to the first row r0 of the memory matrix M. All the cores in the " 1 " state in this row are switched to their " 0 " state and simultaneously capacitor C2 is charged and a pulse is induced in all the column conductors C0-9 wound on the cores which have had their states changed. Each of these pulses renders an associated transistor T0<SP>1</SP>-T9<SP>1</SP> conductive and the resulting pulse at the collector thereof sets the associated column core Q0-Q9 having an output winding W and charges the associated storage capacitor C3. After the first row has been read switch S2 is closed so as to discharge capacitor C2 through row conductor r0, diode d2 and resistance R, supplying a first half amplitude write pulse in conductor r0 The closure of this switch S2 also causes capacitor C3 to discharge through diode d3 and resistance R to produce a second half-amplitude write pulse in the second column wire C0<SP>1</SP>-C9<SP>1</SP>.