Patent EP-0051075-A1 (EP)
Inventor: MISKIN LESLIE
IPC: H04N9/66
Filed: 1980-10-30
Abstract: 1. Television receiver comprising at least one digital integrated circuit for processing the composite color signal, - with a square-wave clock generator used as a chrominance-subcarrier oscillator and generating at least four clock signals (F1, F2, F3, F4) the first of which (F1) has four times the chrominance-subcarrier frequency, and the second to fourth of which (F2, F3, F4) have the chrominance-subcarrier frequency, the first and second clock signals (F1, F2) having a mark/space ratio of 1 : 1, - with a stage providing the digital chrominance signal (C), - with a first parallel multiplier (M1) one input signal of which is the digital chrominance signal (C), and the other input signal of which is a digital chroma control signal (SE), - with at least one buffer memory to which the digital chrominance signal (C) and the third clock signal (F3) are fed, and - with binary computing stages, such as parallel adders and parallel subtracters, characterized by the following subcircuits and features serving to effect digital amplitude control of the received chrominance-subcarrier wave, digital PAL identification and color killer action as well as digital chroma control : - the chrominance-subcarrier oscillator generates a fifth clock signal (F5) having twice the chrominance-subcarrier frequency and a mark/space ratio of 1:3 ; - the third and fourth clock signals (F3, F4) have a mark/space ratio of 1:7 and are 180 degrees out of phase with respect to each other ; - leading edges of the first, second, and fifth clock signals (F1, F2, F5), coincide, while the leading edges of the fourth clock signal (F4) lead those leading edges by the period (T) of the first clock signal (F1) ; - the output of the first parallel multiplier (M1) is connected to the inputs of a first buffer memory (PS1) and a second buffer memory (PS2) whose enable inputs are fed with the third clock signal (F3), and the fourth clock signal (F4), respectively ; - the minuend input of a first parallel subtracter (ST1) is connected to the output of the first buffer memory (PS1), and the subtrachend input of the first parallel subtracter (ST1) is connected to the output of the second buffer memory (PS2) ; - the output of the first parallel subtracter (ST1) is connected to the minuend input of a first parallel comparator (K1) and to the inputs of a third buffer memory (PS3) and a fourth buffer memory (PS4), whose enable input is fed with the fifth clock signal (F5) ; - the subtrahend input of the first parallel comparator (K1) is connected to the output of the third buffer memory (PS3), and the minuend-greater-thansubtrahend output of the first parallel comparator (K1) is connected to the enable input of the third buffer memory (PS3), whose clear input is fed with the inverted burst gating signal (~B) ; - the first input of a parallel adder (AD) is connected to the output of the third buffer memory (PS3) and the second input of the parallel adder (AD) is connected to the output of the fourth buffer memory (PS4) ; - the minuend inputs of a second parallel comparator (K2) and a third parallel comparator (K3) are connected to the output of the parallel adder (AD), while the subtrahend input of the second parallel comparator (K2) is connected to the output of a first programmable read-only memory (FS1), and the subtrahend input of the third parallel comparator (K3) is connected to the output of a second programmable read-only memory (FS2), the first and second programmable read-only memories (FS1, FS2) holding an upper reference value and a lower reference value, respectively, which determine the amplitude control ; - the minuend-greater-than-subtrahend output of the second parallel comparator (K2) is connected to the count-up enable input of a first up-down counter (Z1), and the minuend-smaller-than-subtrahend output of the third parallel comparator (K3) is connected to the count-down enable input of the first up-down counter (Z1), whose count input is fed with horizontalfrequency pulses (H), while the "up" zero-crossing output and the "down" zero-crossing output of the first up-down counter (Z1) are connected, respectively, to the up input and the down input of a second up-down counter (Z2) ; - the outputs of the second up-down counter (Z2) are connected to the first inputs of a second parallel multiplier (M2) and an electronic multiple switch (US) having its second input connected to the output of the second parallel multiplier (M2), while its control input is fed with the burst gating signal (B) ; - the digital chroma control signal (SE) is applied to the input of a fifth buffer memory (PS5), whose enable input is fed with the burst gating signal (B) ; - the second input of the second parallel multiplier (M2) is connected to the output of the fifth buffer memory (PS5) ; - the output of the multiple switch (US) is connected to the second input of the first multiplier (M1), whose enable input is fed with the first clock signal (F1) ; - the minuend-equal-to-subtrahend output and the minuend-smaller-than-subtrahend output of the first parallel subtracter (ST1) are connected to the inputs of an OR gate (OD), whose output is connected via an inverter (IV) to the first input of a first AND gate (U1) and directly to the first input of a second AND gate (U2), the second inputs of which AND gates (U1, U2) are fed with the fourth clock signal (F4) ; - the outputs of the first AND gate (U1) and the second AND gate (U2) are connected, respectively, to the up input and the down input of a third up-down counter (Z3), whose "up" and "down" zero-crossing outputs are connected, respectively, to the R input and the S input of a first RS flip-flop (FF1) ; - a few, preferably three, most significant bits of the output signal of the second up-down counter (Z2) are applied to the inputs of a NAND gate (NG), and - a few, preferably five, most significant bits of the output signal of the first parallel multiplier (M1) are applied to the inputs of a multiple-input AND gate (VU), whose other inputs are connected to the output of the NAND gate (NG) and to the Q output of the first RS flip-flop (FF1), and whose output provides the controlled digital chrominance signal (CG).