baber/WOPTO huggingface dataset:
Patent TW-495584-B (TW)
Title: Port structure for internal combustion engines
Inventor: ASAKURA TAKAFUMI
IPC: F02M69/04
Filed: 2001-09-26
Granted: 2002-07-21
Abstract: To provide a port structure for internal combustion engines which can easily be connected to an intake/exhaust system without a step, is made up of a small number of parts, and can be assembled with ease. A port liner 20 has an end cast in a cylinder head 5 or a cylinder block and another end projecting from the cylinder head 5 or the cylinder block and connected to an intake system or an exhaust system.
Patent TW-533731-B (TW)
Title: Original reader
Inventor: UCHIDA TORU
IPC: H04N1/107
Filed: 2001-10-30
Granted: 2003-05-21
Abstract: An illuminant for converting ultraviolet rays directly radiated outside from an opening of a glass tube into visible light is disposed outside a light source. The light source and the illuminant are disposed in approximately symmetrical positions sandwiching a vertical surface orthogonal to a moving direction of the light source, that is, a direction of Y and including an original reading position.
Patent TW-525221-B (TW)
Title: Substrate processing method
Inventor: KONDO FUMIO
IPC: B24B37/04
Filed: 2001-12-04
Granted: 2003-03-21
Abstract: A substrate processing method comprising steps for forming a copper film on a surface of a substrate. These steps includes the step of filling a first metal in the trenches so as to form a plated film of the first metal on an entire surface of the substrate by electroplating, wherein the electromagnetic field is adjusted by the virtual anode so that differences of thickness of the plated film between the central portion and the peripheral portion of the substrate being minimized, and polishing and removing the plated film by pressing the substrate to the polishing surface, wherein the pressures pressing the substrate to the polishing surface at a central portion and a peripheral portion are adjusted.
Patent TW-554626-B (TW)
Title: Interpolation device for scanning lines
Inventor: KAWAMURA HIDEAKI
IPC: G09G5/391
Filed: 2001-12-05
Granted: 2003-09-21
Abstract: The present invention discloses an interpolation device for scanning lines, which uses the vertical interpolation circuit to conduct the interpolation process for the pixels above and below the vertical direction of the interpolated pixels, and to output the interpolation values in the vertical direction; the average value operation portion in the slanted direction is used to calculate the average of the pixels in the slanted direction for the interpolated pixels based on the angle signal at the edge in the slanted direction, and output the results as the average value in the slanted direction; the differential absolute value operation portion for slanted direction is used to calculate the differential absolute value for the pixel values in the slanted direction for the interpolated pixels, and output the results as the differential values in the slanted direction; and, the mixing portion is used to output the interpolation value in the vertical direction, the average value in the slanted direction, and the mixed value of these values as the interpolated pixel values based on the differential absolute values in the slanted direction.
Patent TW-538332-B (TW)
Title: Power on-off periods auto-testing system of computer equipment and the method thereof
Inventor: JAN YI-SHIN
IPC: G06F1/28
Filed: 2001-12-27
Granted: 2003-06-21
Abstract: A power on-off periods auto-testing system for computer equipment comprises a remote host computer, a data bus circuit, a plurality of data access transmission circuit, a plurality of data transmission lines, a power on-off periods switching unit. With these circuit arrangement, the present invention conducts the automatic testing on power on-off periods for a plurality of tested computers. The testing computer will transmit the generated power-on-testing error codes to the data input port of the data bus circuit through the connected data access transmission circuit in the on-off cycles of the testing power, and transmit to and record on the remote host computer with the power-on-testing error code transmitted from each testing computer through the data access transmission circuit.
Patent TW-527795-B (TW)
Title: Method for automatically updating data of currency exchange rate
Inventor: LAI CHENG-SHING
IPC: G06F13/00
Filed: 2001-12-28
Granted: 2003-04-11
Abstract: A method for automatically updating data of currency exchange rate is used in an information appliances (IA). The method can be triggered by a time setting method or a manual method and the IA has a data of currency exchange rate. The method comprises first connecting to internet, and sending a download request to one server in internet for downloading currency exchange rate, then downloading and updating the data of currency exchange rate in IA. The downloaded data of currency exchange rate at specified time can maintain a real-time data update that avoids the inconvenience resulting from manual input data of currency exchange rate and result in less chance of manual input mistake, thereby keeping the consistency of data of currency exchange rate in the IA and the data of currency exchange rate in the market.
Patent TW-538450-B (TW)
Title: Method and apparatus for the determination of mask rules using scatterometry
Inventor: NIU XINHUI
IPC: G03F1/00
Filed: 2002-01-23
Granted: 2003-06-21
Abstract: A method and apparatus for determining optical mask corrections for photolithography. A plurality of grating patterns is printed onto a wafer utilizing a photomask having at least one grating. Each grating pattern within the plurality of grating patterns is associated with known photolithographic settings. Each grating pattern is illuminated independently with a light source, so that light is diffracted off each grating pattern. The diffracted light is measured utilizing scatterometry techniques to determine measured diffracted values. The measured diffracted values are compared to values in a library to determine a profile match. A 2-dimensional profile description is assigned to each grating pattern based on the profile match. A database is compiled of the profile descriptions for the plurality of grating patterns. Photomask design rules are then generated by accessing the database containing the 2-dimensional profile descriptions. In preferred embodiments, the design rules are used to create and correct masks containing OPC corrections, phase-shifting mask corrections and binary masks. In a preferred embodiment the at least one grating is a bi-periodic grating. In a preferred embodiment, the scatterometry technique is optical digital profilometry utilizing a reflectometer or ellipsometer.
Patent TW-531908-B (TW)
Title: Group-III nitride semiconductor device and group-III nitride semiconductor substrate
Inventor: SASAOKA CHIAKI
IPC: H01L21/205
Filed: 2002-02-21
Granted: 2003-05-11
Abstract: A group-III nitride semiconductor laser has an AlGaN cladding layer with a reduced defect density. Over a GaN substrate 501, there are sequentially grown an n-type cladding layer 502, an n-type optical confinement layer 503, a 3-periods multiple quantum well (MQW) layer 504, a cap layer 505, a p-type optical confinement layer 506 comprising Mg-doped p-GaN, a p-AlGaN cladding layer 507, and a p-type contact layer 508 comprising Mg-doped p-GaN, whereby an LD-structure is formed. The p-AlGaN cladding layer 507 has a multi-layered structure, wherein three Mg-doped GaN crystal recovery layers (thickness: 5nm) are inserted at a constant pitch into Mg-doped p-Al0.1Ga0.9N (Mg concentration: 2x10<19> cm<-3>/thickness: 0.5 micrometers).
Patent TW-544939-B (TW)
Title: Thin film semiconductor device, production process and information display
Inventor: HATANO MUTSUKO
IPC: H01L21/84
Filed: 2002-06-13
Granted: 2003-08-01
Abstract: This invention provides a kind of semiconductor thin film device, a production method thereof and information display device, which can control grain boundary, grain size, and orientation of crystal on an insulation substrate. A thin film semiconductor device has a semiconductor thin film with a film thickness of 200 nm or less. The semiconductor thin film is formed over a dielectric substrate with a warping point of 600 degrees or lower. The semiconductor thin film has a region in which a first semiconductor thin film region with the defect density of 1x10<17> cm<-3> or less and a second semiconductor thin film region with the defect density of 1x10<17> cm<-3> or more are disposed alternately in the form of stripes. The width of the first semiconductor thin film region is larger than the width of the semiconductor thin film region. Therefore, a high quality thin film semiconductor device is obtained.
Patent TW-579593-B (TW)
Title: Elevated pore phase-change memory
Inventor: LOWREY TYLER A
IPC: H01L27/105
Filed: 2002-08-21
Granted: 2004-03-11
Abstract: An elevated phase-change memory cell (10) facilitates manufacture of phase-change memories by physically separating the fabrication of the phase-change memory components from the rest of the semiconductor substrate (12). In one embodiment, a contact (16) in the substrate (12) may be electrically coupled to a cup-shaped conductor (18) filled with an insulator (20). The conductor (18) couples current up to the elevated pore while the insulator (20) thermally and electrically isolates the pore.
Patent TW-578304-B (TW)
Title: Multiple operating voltage vertical replacement-gate (VRG) transistor
Inventor: LAYMAN PAUL ARTHUR
IPC: H01L27/04
Filed: 2002-08-22
Granted: 2004-03-01
Abstract: An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A third doped region forming a channel of different conductivity type than the first region is positioned over the first region. A fourth doped region of a different conductivity and forming a channel is positioned over the second region. The process of creating the gate structure for each of the two transistors allows for the formation of oxide layers of different thickness between the two transistors. The transistors are therefore capable of operating at different operating voltages (including different threshold voltages). Each transistor further includes fifth and sixth layers positioned respectively over the third and fourth regions and having an opposite conductivity type with respect to the third and fourth regions. In an associated method of manufacturing the semiconductor device, a first and second source/drain regions are formed in a semiconductor layer. A first field-effect transistor gate region, including a channel and a gate electrode is formed over the first source drain region and a second field-effect transistor gate region is formed over the second source/drain region. Fifth and sixth source/drain regions are then formed for each of the first and second field-effect transistors and further having the appropriate conductivity type. Variable thickness gate oxides are created by appropriately masking, etching, and regrowing gate oxides. As a result, the formed transistors operate at different operating voltages. Thus a plurality of such transistors operating at different operating voltage (as a function of the gate oxide thickness) can be formed in an integrated circuit.
Patent TW-593613-B (TW)
Title: Assembly system for stationing semiconductor wafer suitable for processing and process for manufacturing semiconductor wafer
Inventor: WANAT STANLEY F
IPC: B24B37/30
Filed: 2002-10-11
Granted: 2004-06-21
Abstract: Disclosed is an assembly system for stationing a semiconductor wafer suitable for processing said wafer, said system comprising: (a) a holding block; (b) a semiconductor wafer; and (c) an aqueous adhesive composition interposed between said ceramic block and said semiconductor wafer, said adhesive composition comprising water; at least one release agent selected from the group consisting of polyethylene glycols, fluorine-free ethoxylated surfactants, fluorosurfactants, and silicone polymers; and at least one resin selected from the group consisting of (meth)acrylic acid or (meth)acrylate based polymers, vinyl acetate polymers, rosin-modified maleic resins, novolak resins, and polymers represented by the formula wherein each R1, R2, and R3 independently is hydrogen or methyl; R is a hydrocarbyl group of 1 to 4 carbon atoms; each R4 and R5 independently is hydrogen or a hydrocarbyl group of 1 to 4 carbon atoms; R6 is hydrocarbyl group of 1 to 20 carbon atoms; w, x, y, and z independently are a number from 1 to 100; wherein said adhesive composition adheres more strongly to said holding block than to said semiconductor wafer. Also disclosed is a process for manufacturing a semiconductor wafer, comprising the steps of: (a) providing a holding block; (b) providing a semiconductor wafer; (c) coating said holding block or one side of said semiconductor wafer with the foregoing aqueous adhesive composition; (d) contacting one side of said semiconductor wafer to said coated holding block or said coated side of said semiconductor wafer to said holding block, such that said semiconductor wafer adheres to said coated holding block; (e) polishing the other side of said semiconductor wafer; and (f) removing the semiconductor wafer from the coated ceramic holding block.
Patent TW-573351-B (TW)
Title: Electrostatic discharge protection scheme for flip-chip packaged integrated circuits
Inventor: KER MING-DOU
IPC: H01L23/50
Filed: 2002-12-06
Granted: 2004-01-21
Abstract: An electrostatic discharge (ESD) protection scheme. The scheme utilizes traces in a package substrate to bridge a power ESD clamp circuit and a protected circuit, and comprises a conductive trace in a package substrate and a chip die. The chip die has a protected circuit powered by a first high power rail and a first low power rail, and a power ESD clamp circuit coupled between a second high power rail and a second low power rail. The first high, first low, second high and second low power rails are all fabricated on the IC chip die. The first high power rail is separated from the second high power rail on the chip die, and, during an ESD event, is coupled to the second high power rail through the conductive trace in the package substrate.
Patent TW-592015-B (TW)
Title: Method of fabricating a high-layer-count backplane
Inventor: GOERGEN JOEL R
IPC: H05K1/02
Filed: 2003-02-06
Granted: 2004-06-11
Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.
Patent TW-583892-B (TW)
Title: Testing structure of OLED panel and manufacturing method thereof
Inventor: SUNG JAU-CHIN
IPC: H05B33/10
Filed: 2003-02-11
Granted: 2004-04-11
Abstract: The present invention relates to a testing structure of OLED (organic light-emitting display) panel and manufacturing method thereof. The testing structure is provided to adjust and test the OLED panel when the OLED panel is manufactured. The OLED panel comprises plural data lines, the data lines comprise plural red data lines, green data lines, and blue data lines alternatively arranged on a substrate. The testing structure is electrically connected to the red data lines, green data lines, and blue data lines through a red aging line, a green aging line, and a blue aging line respectively. The OLED panel is tested by conducting currents with a predetermined magnitude through them the aging lines respectively.
Patent TW-I257403-B (TW)
Title: Woody synthetic resin compositions
Inventor: MAEDA MUTSUMI
IPC: C08L23/06
Filed: 2003-02-20
Granted: 2006-07-01
Abstract: Woody synthetic resin compositions comprising: (A) from 5 to 95 parts by weight of a thermoplastic resin; (C) from 5 to 95 parts by weight of a vegetable cellulose; and (B) from 0.1 to 10 parts by weight, based on 100 parts by weight of (A)+(C) of an ultrahigh molecular weight polymer having a viscosity-average molecular weight of 1,200,000 or above, are provided, in which the thermoplastic resin (A) is made of a polyolefin-based composition (J). Use of these woody synthetic resin compositions makes it possible to stably produce molded woody synthetic resin articles which are comparable to natural woody materials in secondary processing characteristics (nailing, sawing, screwing, etc.), excellent in strength and rigidity, free from surface roughness and favorable in appearance.
Patent TW-595156-B (TW)
Title: Intelligent network time display system
Inventor: LIN CHING-JIANG
IPC: H04L12/16
Filed: 2003-03-11
Granted: 2004-06-21
Abstract: An intelligent network display system primarily targets at utilizing an Ethernet network to fully share the standard time signal with all time display equipment in a local area network (LAN) and synchronizing time servers on the same layer to provide synchronization of sub-network time equipment. Another function of the invention is to instantaneously control the display equipment to power on or off based on the conditions all around to save unnecessary energy waste and to display text message by converting it to a text control mode.
Patent TW-I263720-B (TW)
Title: Process for increasing the dry strength of paper
Inventor: KLAISNER CONSTANCE
IPC: D21H17/28
Filed: 2003-04-04
Granted: 2006-10-11
Abstract: Addition of a premixed aqueous mixture of anionic dry strength resin and cationic or amphoteric starch to a paper making pulp slurry yields paper with higher dry strength than paper that is the same except that the starch and dry strength resin are added separately.
Patent TW-I246842-B (TW)
Title: Node B and RNC actions during a serving HSDPA cell change
Inventor: CHAO YI-JU
IPC: H04L29/02
Filed: 2003-04-04
Granted: 2006-01-01
Abstract: A system and method in accordance with the present invention reduce the amount of data that is stalled in a source Node B after a serving HS-DSCH cell change in a communication system that includes a serving RNC and at least one Node B. In a first embodiment, the RNC temporarily suspends data transmissions from the RNC to the Node B. In a second embodiment, the activation time is used in data scheduling. In a third embodiment, a more robust MCS level is selected. In a fourth embodiment flow control is employed for the data transmitted between the RNC and the Node B.
Patent TW-594742-B (TW)
Title: Semiconductor memory device
Inventor: TANAKA SHINJI
IPC: G11C11/406
Filed: 2003-04-22
Granted: 2004-06-21
Abstract: A sense amplifier band arranged between two memory cell arrays includes sense amplifiers, and spare memory cells usable as backup spare memory cells for memory cells included in the memory cell arrays. Using the spare memory cells, a refresh operation is executed while being divided into two stages. Namely, refresh target data read to sense amplifiers is temporarily stored in one of the spare memory cells, read again and written to the original memory cell. As a result, high rate operation is realized at low cost and area penalty is small.
Patent TW-586911-B (TW)
Title: Process and apparatus for separating hypocotyls from beans
Inventor: SHEIH I-CHUAN
IPC: A23L11/00
Filed: 2003-04-29
Granted: 2004-05-11
Abstract: Non-swelled beans having two hypocotyls such as soybeans are projected to a surface, so that a portion thereof are separated into halves by a single collision. The resulting intermediate from the collision is collected and sieved to obtain an under-sieve portion having hypocotyls as a major thereof. The present invention also provides an apparatus for separating hypocotyls from beans by single collision.
Patent TW-I273230-B (TW)
Title: Diffraction-based diagnostic devices
Inventor: COHEN DAVID
IPC: G01N21/17
Filed: 2003-05-02
Granted: 2007-02-11
Abstract: A biosensor includes a substrate with areas of active receptive material disposed thereon. The receptive material is specific for an analyte of interest. A pattern of active areas is defined on the substrate by an oxidizing photo-masking process.
Patent TW-I289791-B (TW)
Title: Method for providing events to the application program and the electric device using the same
Inventor: KAMIYA DAI
IPC: H04M1/72451
Filed: 2003-05-16
Granted: 2007-11-11
Abstract: The present invention is a method for providing events to the application program, wherein the event obtaining portion 121 obtains the events occurred in the event occurring portion, and supplies to the event providing portion 122. When the event providing portion 122 in the action mode is in the action mode A, it will provide to the application program corresponding to the event by referring to the event table T1. When the event is provided to the communication AP131, the communication AP131 is started before the provision. On the other end, in the action mode B, the event providing portion 122 provides the event to the Java execution environment 140. Moreover, if the switching button CB is pressed, the event providing portion 122 will switch the action mode.
Patent TW-586336-B (TW)
Title: Electrode substrate of flat panel display
Inventor: CHAO CHIN-HSIAO
IPC: G02F1/1343
Filed: 2003-06-30
Granted: 2004-05-01
Abstract: An electrode substrate of a flat panel display comprises a substrate, an electrode layer, a conductive layer, and a barrier layer. In this invention, the electrode layer is set on the substrate. The conductive layer is set on the electrode layer. The material of the conductive layer is Ag, Ag alloy, Al, Al alloy, Cu or Cu alloy. The barrier layer is set on the conductive layer. The material of the barrier layer is Ti, Ti alloy, Mo, Cr, Si, SiO2 or TiO2.
Patent TW-I257034-B (TW)
Title: A method for converting a cleanerless toner cartridge to a conventional toner cartridge having an organic photoconductive drum, and a remanufactured toner cartridge
Inventor: MEYER BRENTON L
IPC: G03G15/08
Filed: 2003-07-09
Granted: 2006-06-21
Abstract: A noncontact cleanerless system toner cartridge that uses an injection charging roller and toner with conductive particles is remanufactured into a conventional toner cartridge. The injection charging roller (220) is removed and replaced with a primary charge roller (203). A cleaning blade (230) to remove the residual toner from the organic photoconductive drum (201) is added along with a seal (240) to form a toner waste hopper area (225). The toner (205) with the conductive particles is replaced with toner having magnetic particles.