Patent GB-1519001-A (GB)
Title: Arrangements for digitising an anologue electric input signal
IPC: H01L29/762
Filed: 1975-05-16
Abstract: 1519001 Semiconductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 16 May 1975 [20 May 1974] 20844/75 Heading H1K [Also in Division H3] A semiconductor analog to digital converter consists of a linear array of discrete zones of one conductivity type formed at one surface of a region or body of opposite conductivity type, which zones can be connected in turn to a common connection zone via an inversion region formed beneath an increasing portion of the length of an insulated gate electrode in response to an increasing analog voltage applied to the gate. The zones may be permanently present at the surface or formed temporarily by application of a suitable voltage to an overlying electrode structure. The inversion threshold voltage may be varied along the gate by providing a corresponding variation in doping of the substrate surface or in the dielectric constant or thickness of the gate insulation. In one type of device (e.g. Fig. 11) the P zones 6, formed in an epitaxial N layer reverse biased with respect to an underlying P substrate are initially charged capacitively by suitably biasing the gate electrode and a number of them determined by the level of analog input signal V a  are connected in sequence to a P region 13 connected to earth via load resistor 15 by applying a combination of level setting voltage 23, triangular or sawtooth wave form voltage 22 and the input signal V a  to a resistive gate 8 along which a sensitivity determining voltage gradient is maintained by voltage 12, the gate being of polysilicon more lightly doped between than over the zones 19. The output at connection 18 consists of voltage pulses the number of which per cycle is determined by the number of zones connected superimposed on a slowly varying voltage due to gradual expansion of the inversion region, and is subtracted from the output of the balancing structure 60, 61 consisting only of the slowly varying voltage before application to a counter. In the absence of the balancing structure the output from 18 is applied to the counter via a high-pass filter. In another embodiment, Fig. 6, the zones 50 of the array are connected to voltage 41 via zone 40 by the inversion region generated under resistive gate 47 and to corresponding zones 32, mutually isolated by channel stopper regions 46 formed by N type diffusions or by local thickening of the gate insulation, and separately connected to inputs of read-only memory 43 having a binary digital output by the inversion region generated under second resistive gate 34. The voltage gradients along the two gates are opposed and the analog input signal fed in antiphase to the gates so that for a given value of input signal the inverse regions overlap both ends of only one of zones 50 to connect the associated memory input conductor to voltage 41 representing logic "1". If desired integrated amplifiers may be connected in the lines 45 between zones 32 and the memory, and zones 50 may be dispensed with if adjacent edges of electrodes 34 and 47 are arranged to overlap. Suggested modifications are use of aluminium and lead oxide as gate materials and a gate structure in the form of a comb with a resistive spine and conductive teeth.