Patent GB-1117230-A (GB)
Title: Data processors
Inventor: ULRICH WERNER
IPC: G06F9/355
Filed: 1965-10-06
Abstract: 1,117,230. Data processor. WESTERN ELECTRIC CO. Inc. 6 Oct., 1965 [7 Oct., 1964], No. 42346/65. Heading G4A. A digital electric processor in eludes a plurality of registers means for representing an instruc tion word, an index adder, means for transmitting to the index adder a variable portion of the instruction word, data contained in one of the registers and part of data contained in another of the registers in accordance with the instruction word. Instruction words from a program store 40 are transmitted to an order word register 28. The address of the word in store 4 is contained in a program address register 38 and continuously incremented by 1 or transmitted to register 38 over cable 52 if order cable XFR is energized. Each instruction word comprises operation, DA or data/ address, IR or index register and LPA fields. Decoder-distributer determines from the operation field the order to be executed and energizes one of the four order cables to execute the order. The DA field can be in two parts, DA 1 , DA 2 . The DA 1  portion is transmitted directly to the index adder 32 which is used only to modify the DA field of an instruction word. DA 2  is transmitted via gate 30 which is normally enabled, to the index adder and the two parts DA 1 , DA 2  may form a single word specifying either data or an address. The index adder adds the word to the contents of a register L, X, Y, Z or buffer register 12 specified by the IR field and read by register reader 16, the word from the index adder being transmitted to the unit enabled by the energized one of the four order cables. Whenever a new word directed by the register director 44 is written in the Y register it is added to the word in the Z register by adder 42 and the result is stored in the Z register, the new word remaining in the Y register. The words may be masked in the masking circuit 14 the masking being determined by a word stored in the L register, a one in any bit position of this word allowing the corresponding bit in the word to be masked to pass and a zero stopping the corresponding bit from passing. The masking circuit is bidirectional so that a word from register reader 16 on line 56 can be masked as well as a word from buffer register 12. Masking only occurs if bit L in the LPA field is a " 1 ". Assuming that the LPA field is zero, a transfer order controls a transfer to a new instruction out of sequence. Order cable XFR is energized by an instruction XFR, 500, Y, 000. Thus the entire DA field, 500, is transmitted to the index adder 32 since P is 0. The contents of the Y register, say 25, are also transmitted to the index adder to produce a sum 525 which is transmitted to data store 10 and gate 74 and to program address register 38. However the data store and gate 79 are not enabled by cable XFR. Thus the next instruction transmitted to the order register is that from location 525. When a word contained in the DA field is to be written in one of the registers order cable W(R) is energized the (R) specifying the register. In operation the contents of the register specified by the IR field are again added to the DA field before the word is written in the appropriate register. The M(R) instruction causes a word in memory to be written in the register specified by the (R) term. The DA field again may be indexed. The (R)M causes a word in one of the registers to be written in the memory. When the P field contains a 1 the above operations are amended. Gate 30 is not inhibited, only the DA 1  field passes to the index adder and the DA 2  field passes the now enabled gate 26 to the shift and read circuits. Read circuit 74 is connected to the stages of the Z register containing the least significant bits, the exact number depending on the maximum number of bits to be transmitted from the Z register in any given application. The DA 2  subfield specifies a number of bits, e.g. 4 and the read circuit reads the four least significant bits in the Z register to the index adder, to be added to the contents of the register specified by the IR field and to the DA 1  field. After the operation of the read circuit the shift circuit operates to shift the contents of the Z register, e.g. four places to the right, i.e. in the direction of least significance to remove the previous four bits and place the next bits to be specified by the DA 2  field in position.