Patent GB-853551-A (GB)
Title: Improvements in data transmission systems
IPC: G06F11/10
Filed: 1957-04-17
Abstract: 853,551. Digital data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. April 17, 1957 [April 17, 1956 (3); May 21, 1956], No. 12506/57. Class 106(1). A signal transmission system comprises a digital data signal source adapted to produce electric signals representative of messages, each having a plurality of words containing a number of digital positions greater than one and a storage device arranged to receive and store a message prior to transmission to a transmission channel, including checking means adapted to prevent transmission of electric signals representative of a message by said transmission channel when said message does not contain a predetermined number of words and a counter for producing signals representative of the number of words of a given message, which have been stored in said storage device associated with said signal source. The apparatus describes transfers messages, each comprising five words, between a number of computers or other devices via a selected one of five transmission channels, each word being parity checked and each message being checked to ensure that it contains five words before a message is actually transmitted. The transmission is serial by bit, with the five words of a message are interlaced. For each computer, or other device, the transfer circuit to the transmission channels is as shown in Figs. 3a, 3b, and comprises principally a buffer drum store 32 into which words from the computer are put as they are synthesized, various reading and de-coding circuits, three core matrix buffer stores, section 1 array, section 2 array and section 3 array, only the circuitry for the section 2 array being shown in Fig. 3 as the others are similar, and five five-stage shifting registers 420, 422, 424, 426 and 428, one for each transmission channel, into which first all the one bits of a message are entered in parallel from and read-out to a transmission channel in serial form, and then all the two bits of the message are entered and serialized and so on. The operation of the transfer circuit is cyclic and in respect of the section 2 array is controlled by a section 2 control unit 84, other control units being provided for the other sections. During each cycle words are read into one of the section 2 arrays, either array A or array B, and read out of the other. The operation of the transfer circuit is as follows. Cycles of operation are numbered and counted by a " burst counter " 258 and each word, Fig. 2, specified by a burst number the cycle in which it is to be transferred. Since words are entered into the buffer drum by the computer as soon as they are synthesized, a search of the drum has to be made each cycle to select only those words containing the burst number of the particular cycle being performed. This is done by staticizing each word in a drum word register, effecting a parity check and comparing the burst number of the word with the burst counter. Once a wanted word is found the data portion is then routed to the array specified by its section address, Fig. 2, which, it is assumed, specifies section 2, and within the specified array the data portion is registered at the address specified by its array address digits. Each array contains five groups of five address positions (25 in all) each group being associated with a particular transmission channel via one of the five-stage shift registers. Thus the array address digits of a word determine the channel over which the word is to be transmitted. At the end of a cycle a completed message control unit 460 opens those of gates 442, 444, 446, 448 and 450 that correspond to groups of the array that have received complete messages (that is five words) so that during the following cycle these messages may be transmitted while the other section 2 array is being filled. The completed message control unit, Fig. 10, to which Claim 1 is directed, comprises five six-stage shifting registers corresponding to the five groups of addresses in each array. At the beginning of each cycle these shift registers are set with their first cores in their one states. Each time an address is selected (that is written into) in an array the corresponding shift register is advanced one stage and thus if all five addresses in a group are written into the corresponding shift register will have advanced to its last stage and will cause the associated flip-flop 587 to be set on thereby opening one of the transmission channel gates 442-450, Fig. 3b. Once a message is transmitted the particular computer or other device that accepts it is determined by the last 5 digits of the fourth word of the message, that is every device accepts every message as far as the last five digits of word 4, after which it is either immediately rejected and cleared-out or the remainder of the message is also accepted. When the message is accepted its five words are arranged as shown in Fig. 15 by means of shifting registers to form with time tag bits (indicating the time of acceptance) and site tag bits (indicating the origin of the message) to form three full-length words, which are stored on the buffer drum of the accepting device prior to being used. Specification 800,186, which describes a magnetic core counter, is referred to.