Patent GB-809152-A (GB)
Title: Improvements in or relating to apparatus for the reception of information in the form of pulses
Inventor: BROADHURST SIDNEY WALTER
IPC: H04Q11/04
Filed: 1954-02-24
Abstract: 809,152. Digital electric calculating apparatus. POSTMASTER GENERAL. Feb. 18, 1955 [Feb. 24, 1954], No. 5504/54. Class 106 (1). [Also in Group XXXIX] An arrangement is described for counting pulses indicative of dialled digits in a telephone system (see Group XXXIX), the digits being stored in binary form on consecutive pulse positions in a circulating delay line system. Arrangements are also provided for reading out the digits. Consecutive digits are stored on successive delay line systems, the first of which is also used for reading out purposes, so that when a digit has been read out of this system a shift of all remaining digits to a delay line of higher denomination is effected and the next digit is read out of the first delay line. The arrangement is capable of dealing with 99 such sets of information simultaneously, each information source being allocated a pulse CTP1, CTP2 ... (Fig. 4) of duration 12 Á.sec. and recurrence period 1200 Á.sec. Each CTP period coincides with six 2 Á.sec. pulses PP1 ... PP6. The pulses to be counted are received as PP1 pulses on lead PL6 and are stored in binary form on positions PP3 ... PP6. An " end of digit " signal is also supplied in the form of a PP1 pulse on lead PL4. The pulses received from a circuit associated with pulse CTP1 are received in period CTP2 (owing to delay inherent in the preceding timing apparatus (see Group XXXIX)) and the storage system is designed to correct for this. Storage. The first digit is stored in binary form on pulse positions PP3 ... PP6 (CTP2) in a circulating system comprising a 1188 Á.sec. delay line D51 and a 12 Á.sec. delay line D52. Thus pulses entering D51 as CTP2 pulses emerge from it as CTP1 pulses. Pulses in position PP1 (CTP2) representing the digits received on PL6 are delayed to position PP3 by delay line D55 and fed to the 2 Á.sec. circulating system D56 which registers the digits on a binary scale. Thus when a pulse is received it is allowed to circulate via gate PCG55 for as many consecutive pulse positions as are present in the circulating system, each time deleting the pulse from the circulating system in gate PSG53; after it passes through the gate PCG55 for the last time it inserts a pulse in the next position via gate PSG71 which is now open for the first time. Thus each incoming pulse on PL6 increases the number stored by one. A PP1 pulse on PL4 indicating the end of the digit is also inserted into the system via lead P44 and gate PSG53. This pulse at gate PSG70 prevents the insertion of further digits into the D51, D52 circulating system, but diverts them via PCG70 into a second similar circulating system D53, D75. A third digit is similarly inserted into the circulating system D54, D76 (and so on). Reading out.-When PP1 is stored in the first circulating system it passes via PCG56 and PCG69, which is opened by an XP5 pulse, and a 2 Á.sec. delay line D57 to PSG53 where it enters the circulating system as a PP2 pulse. XP5 is a 1200 Á.sec. pulse whose repetition period is equal to the intertrain pause required. During the next XP5 pulse PCG57 is opened to pass a pulse in position PP2 (CTP2) to the third circulating system via PSG58. Coincidence between the PP2 pulses in the first and third circulating systems (obtained from D51 and D54 during a CTP1 period) open gate PCG62 to pass a PP2 pulse, during the pulses XP8, to the 2 Á.sec. circulating system D66. XP8 is a 1200 Á.sec. pulse of repetition frequency equal to the required of the dial impulses, i.e. 10 per second. Each PP2 pulse applied to D66 causes it to produce pulses PP3 ... PP6 in succession corresponding to the binary number 1111 which is added in the circuit comprising gates PCG63, PCG64, PSG72 and 2 Á.sec. delay line D67 to the number already circulating in the system (any carry from the highest denomination being suppressed). This is equivalent to subtracting 1 from the number stored. At the same time a PP6 pulse from the circulating system D66 is fed via PSG54 and 4 Á.see. delay line to the second circulating system wherein it is permitted to circulate until suppressed in gate PSG73 by the occurrence of a 1200 Á.sec. XP9 pulse. This occurs 66 2/3 m.sec. after the XP8 pulse. The PP2 pulse is thus circulating for this period and passes via gate PCG75 to suppress the PP2 pulse on lead PL2 thereby restoring trigger T1 and releasing Y to provide a 66 2/3 m.sec. dial break on leads L3, L4. Impulsing thus continues until 0000 is registered in the first circulating system, i.e. lead PL17 carries the number 1111. In this case gate PCG68, which is fed directly and via 2, 4 and 6 Á.sec. delay lines D68, D69, D70, registers a coincidence at PP6. Its output causes the circulating system D63 to generate pulses PP1 ...PP6 which remove all pulses stored in the first circulating system at gate PSG61. The PP6 pulse also closes gate PSG63 to prevent further PP2 pulses being inserted into the second circulating system. The PP1 ... PP6 pulses from D63 also delete the pulses stored in the second circulating system at gate PSG60 and transfer them via gate PCG60 to the first circulating system. Similar transfer of pulses stored in the third system to the second also takes place, the PP2 pulse, however, being deleted in gate PSG73 by the output from gate PCG77 since this pulse must be present in the second system only during the period of the outgoing dial break. The transmission of the second digit now present in the first circulating system now proceeds in the same manner and so on. During the transmission of each digit the PP2 pulse from gate PCG62 is applied over lead PL14 to operate the trigger T2 of the appropriate circuit to bring up Z to which provides a clean impulsing loop over L3, L4. When release occurs the set of six releasing pulses PP1 ... PP6 on PL8 are applied to suppression gates PSG53, PSG73, PSG58 to remove all the pulses from the respective circulating systems. Arrangements are also described for registering incoming digits on combinations of two out of five delay lines, each digital source being allocated a pulse position, the appropriate pulse being inserted in the appropriate delay line combination. Specification 804,691, [Group XXXIX], is referred to.