Patent GB-1116675-A (GB)
Title: General purpose digital computer
IPC: G11C21/00
Filed: 1966-09-12
Abstract: 1,116,675. General purpose digital computer. S. P. FRANKEL. 12 Sept., 1966 [1 Oct., 1965), No. 40621/66. Heading G4A. In a general purpose digital computer having a circulating memory for storing data organized in data words, each word having a plurality of bits, processing means for operating on data words according to a stored programme, and means for transferring data words from the processing means to the memory and vice versa in a format such that the data words are interleaved bit by bit in pairs, the processing means include a temporary storage device for storing at least two data words, also in the interleaved bit format and further includes means for serially operating on the bits of the words in the temporary storage device, the operations including operations involving two interleaved words in the temporary storage device and including further operations with or without concurrent transfer of a word between the memory and the temporary storage device, whereby the identification of the storage location for the next transfer of a word between the memory and the temporary storage device is determined by the number of operations without a transfer following the preceding transfer between the memory and the temporary storage device. In the embodiment shown (Fig. 1) comprising a delay line 10 of relatively long recirculation period for storing data (referred to as the M-register) and a delay line 20 of relatively short period of processing data (referred to as the R-register), all data being stored in an interlaced manner, logic circuitry 100 including flip-flops A, B, C, E and R is provided for controlling said processing and the input and output of data (via R-register) determined by instructions extracted from R-register and held temporarily in a static register 50 (referred to as V-Z register). The idle recirculation path (Fig. 2, not shown) for data in R-register is by way of output transducer 22, flip-flops Q and R, input transducer 21 and the delay line 20. Similarly, the idle circulation path for data in M-register is by way of output transducer 12, flip-flop M, input transducer 11 and delay line 10. Input equipment may include a keyboard and a tape reader. Output equipment may comprise a typewriter. All operations are synchronized with timing pulses P, F, G and I (Fig. 4) issued by timing chain logic circuit 30 (cf. also Fig. 3, not shown) driven by an oscillator clock 31. Referring to the timing diagram of Fig. 4 the recirculation period of R-register is divided into two-word periods designated I and #I. Each word period is divided into 40 P-periods and 40 P-periods corresponding to two 40-bit interlaced words. The R-register thus accommodates four 40-bit words which are separately interlaced in pairs. The M-register stores data in a similar interlaced manner but its recirculation period corresponds to an odd number (45 is preferred) of word periods so that during each two successive M-cycles each word therein appears. (in the M flip-flop) in synchronism with both of the R-register words (in the R flip-flop). Thus, by suitable timing of instructions, transfer of words between R- and M-registers can be achieved in any desired manner. Programming by means of orders operating on words in a fixed predetermined manner entails so timing operations that the required operands are in the required predetermined positions at the time of execution thereof. Words and bits are referred to by the time at which they are in flip-flop R. Thus, the four words in R-register are referred to as IP, I#P, #IP and #IP words. An IP word in M-register after one M-cycle becomes an #IP word. Words are circulated in a least to most significant order. Instruction orders comprise 5 bits each (referred to as a syllable) so that eight orders are accommodated in each instruction word. The eight order syllables of the #IP word (always an instruction word) are transferred in turn from R-register into the V-Z register where they remain for an integral number of R-cycles unless this sequence is disturbed, for example, by a conditional jump order. Orders are transferred into V-Z register by including this register (which is a shift register) in the recirculation path for the #IP bits only so that during the execution of the eight orders of an instruction word, the contents of the #IP word, together with the initial contents of the V-Z register, are gradually shifted around in a cyclic manner. The orders are executed in the inverse order to the circulation order. The orders which are available are of three types. (1) Single orders, for which #V or #W#X=1 (as illustrated in the order code chart of Fig. 6, not shown) are placed in V-Z register in one I period and executed in the subsequent I period (i.e. one complete R-cycle). (2) Double orders, for which V#WX=1, take two complete R-cycles for loading and execution, normal order cycling being suppressed during the second R-cycle by the fact that flip-flop E is set at the end of the loading period (IGFP time) and is not re-set until the next IGFP time. (3) Long orders, for which VW = 1, take a variable integral number of R-cycles, the number of cycles being determined by a count-number which is stored in the syllable following the order to which it relates and which is incremented (in flipflop A) by one for each R-cycle until the all-zero state is reached. As the syllables comprise five bits each, a count of up to 32 can thus be obtained and by using the Z-bit of the order code as well counts up to 64 are possible, thereby enabling long shifts and waits to be achieved. The zeroized count number which is transferred into V-Z register after completion of the long order is treated as a blank order and has no effect, other than introducing a delay of one R-cycle. The orders which are available and the decoding of which is described in detail (Figs. 7-18, not shown) are as follows:- Bring (single order) duplicates either IP or #IP word from M into R-register. Record (single order) transfers either #IP or #IP from R to M- register, with or without suppression of original word in R-register. Bring double and Record double are similar to the corresponding single orders, but both IP and #IP words are transferred. Unconditional fill (double order) duplicates #IP word from M into R-register, i.e. loads instruction word into R-register. A single fill instruction, after execution of the eight orders of one instruction word and on being reloaded in V-Z register, may cause a further instruction word to be loaded into R-register and so on for other subsequent words-it then becomes an inherited fill order. Conditional fill is similar to previous instruction but is only obeyed if flip-flop C previously set. Exchange (single order) causes interchange of the two words IP and #IP in R-register. Single Shift (single order) moves all 40-bits of #IP word in R-register to next more significant position, the old most significant bit going to flip-flop C and the new least significant bit coming from flip-flop C. Long shift (1-64 R-cycles) shifts the 80 IP and #IP bits a variable number of places, as determined by the corresponding count number. No bits are lost and none are introduced. Blank (single order) introduces a single R-cycle delay. Long Wait (1-64 R-cycles) introduces a variable length delay so as to obtain the required synchronism between M and R- registers. Add (single order) sums the #IP word in M-register to the #Ip word in R-register and leaves the result as the #IP word in R-register. Subtract (single order) is exactly analogous to the add order. Double length words may be added or subtracted by programming. Multiply (1-64 R-cycles) operates on words #IP and IP and leaves the product in #IP or #IP and IP, all in R-register. Extended multiplier words are possible if the multiplicand is correspondingly short. Accumulative multiplication is possible (i.e. #IP initial not zero). Divide (1-64 R-cycles) operates on an 80-bit dividend (#IP and IP words) and a 40-bit divisor (#IP word), leaving the quotient (40-bits) in IP and a remainder in #IP which may require correcting depending on sign bit in flip-flop C. Test orders which check the setting of switches on the keyboard and set or reset flip-flop C accordingly (for use with conditional fill order). Loading mode which inhibits order cycling (E = 1) and changes the computer from its entirely synchronous computing mode to a partly asynchronous loading mode comprising eight phases. Data input or Loading: As shown (Fig. 19) new data may be stored as marks 221, 222 on a tape 220, the marks 221 representing binary 0 being wider than the marks 222 representing binary 1. The reading equipment (which may be photo-electric but is not shown in detail) is arranged to produce by differentiation positive pulses t+ (Fig. 20 corresponding to the leading edges and t - corresponding to the trailing edges. The timing is so arranged that in the case of the marks 221 (binary 0) the interval t + to t - is considerably longer than one R-cycle, whereas the corresponding interval for marks 222 is shorter. Thus, by means of a delay device which is started on detection of a t + pulse and controls the setting of flip-flop B by the t - pulses, the two types of marks are discriminated. After discrimination, the contents of flip-flop B are entered into R-register, the previous contents being shifted along one bit position to make room. The data on the tape is interlaced just as it is required in R and M registers. After loading of 160 bits (as detected by return of a marker bit in the previously cleared R-register, to flip-flop B), the contents of the IP, #IP and #IP words (120 bits) in R-register are transferred to M-register under control of instructions which have just been loaded into the #IP word position of R-register. During loading a marker block of 160 binary 1 bits are circulated in M register for reference purposes. Computing mode res