Patent GB-1491453-A (GB)
Title: Computer system
IPC: G06F9/46
Filed: 1974-12-02
Abstract: 1491453 Data processing COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII-HONEYWELL BULL 2 Dec 1974 [30 Nov 1973 (3)] 52132/74 Heading G4A In a multi-programming computer system having a central processing unit with a plurality of processes one of which is in a running state, the remainder being in the ready, waiting or suspended states, a process control block in virtual memory stores information relating to the states of the processes this being used when a process switches from a running state to a waiting state or to a suspended state. The address of the process control block is defined by two integers J, P, entry J or a J table containing the absolute address of a P table, entry P of which contains the absolute location of the process control block. The integers J, P for the current process are held in system base. Basic system (Fig. 1, not shown).-The basic system comprises a central processing unit (101), peripheral sub-systems (103) and a semiconductor (capacitive) modular memory subsystem (102). The central processing unit includes base, scientific and general registers, a main memory synchronizer, a computational unit, a control unit, an emulation unit, a buffer store, an address control unit, and an associative store used to store the base address and segment numbers of the most recently used segments in main memory. The control unit receives microinstructions to control the processor in native, emulation or diagnostic modes. It comprises an integrated circuit read-only memory and a read/ write random access memory. Process control block (Fig. 4).-Each process control block includes, at byte positions 0-15, four 32 bit process main words PMW0-PMW3. The first word PMW0 includes a capability byte, a priority byte, a state byte and a data extension byte. The capability byte includes an accounting mode bit (to indicate if time accounting is being performed), a scientific mode bit and a code mode bit, the remaining 5 bits being zero. The priority byte sets the priority level of the associated process (one of 16 levels), the last 4 bits being zero. The state byte includes an active bit, set to "1" when the process is activated, a suspend bit, a 2 bit sub-state field, 00, 01, 10, 11, indicating, respectively, that the process is inactive, waiting on a queue of ready processes, waiting on a semaphore in a queue of semaphores (i.e. waiting for an event to happen or a resource to become available), or being executed, an interruption bit, an extended decor mode bit (indicating that the process is operating in an emulation mode) and 2 zero bits. The fourth byte contains the decor extension number DEXT used when the system is in the emulation mode. The second word PMW1 comprises a status byte storing the status register contents, a multi-processor byte, used only in a multiprocessor system and 2 bytes which are normally zero. The third word PMW2 contains in bit positions 4-32 the logical address (SEG, SRA) of the semaphore to which the process control block of a suspended or waiting process is linked, part of the address bits 16-31 indicating the class and type of the exception which caused the process to be suspended. The fourth word PMW3 points to a data extension table and comprises a DETFZ field (bits 0-7) defining the number of entries in the table (no decor extension being allowed if this is zero) and DETA field (bits 8-21) containing the absolute add-on of the table. (Each entry in the table is one byte size and has the value 0 or 1 indicating the capability of the process to operate in that decor extension mode.) The process control block also includes 2 address space words ASW0, ASW1, each containing a pointer to an array of segment table words (indicating segments assigned to processes), bits 0-7 defining the size of the array and bits 8-31 the absolute address of the array (in units of 16 bytes). An exception word EXW includes a zero field (bits 0-3) and an address field (bits 4-31) containing a pointer to an exception class table defining the action to be taken when a process exception occurs. A stack word SKW contains the value of the top of a T register of a stack, the stack being formed whenever one procedure calls another. It also includes a ring number (2 bits) for protection purposes, there being 4 levels of protection 0-3. An instruction counter word ICW includes the ring number (bits 2, 3) of the current process for determining access rights to main storage and the segment number and segment relative address (bits 4- 31) which define the address of the next instruction. A further word MBZ is tested every time the block is accessed and unless it is zero an exception occurs. Stack words SBW contain a segmented address of the first bytes of three stack segments assigned to ring levels 0, 1, 2 and utilized during stack operations. Further bytes are reserved for saving the contents of base, scientific and general registers. Above the zero address (which is the address pointed to by the P table) 5 double words are provided for time accounting purposes, a residual time out word RTO, (containing the time spent on the process before a time out exception), a running time word RUA and if the accounting mode bit is set a waiting time word, a ready time word (specifying the time a process is in the ready state) and a current entry time. System base (Fig. 6).-A boundary address register points to an address BAR in the system base at which is stored the size (bits 0-7 and absolute address (bits 8-31) of the J table. A G table word includes the size and absolute address of a G table in which entries are 2 word segment descriptors of segments containing semaphores. The system base includes 9 exception cell words, one per class of exception, each containing the system name (G, bits 8-15, D bits 16-31). A channel exception cell contains the name of a semaphore used when a channel exception occurs. An internal processor queue word IPQW points to the head of the processor's ready queue, it comprising a 16 bit number representing the displacement from the base of the GO segment. Re-try count words hold the number of times instruction re-try is to be executed when a machine error occurs. The running process word RPW holds the name of the current process (bits 16-31) together with its priority (bits 8-11). Accessing of a user segment, a system segment and the GO segment using the system base and process control block is described with reference to Fig. 12 (not shown). When a new process (i.e. is the head of the ready queue) has priority over the currently running process a roll-out operation is effected in which information relating to the running process is transferred from the general registers, base registers, scientific registers, T register, status registers and instruction counter to the process control block of the current process. This is followed by a roll-in operation in which the name of the new process is entered in the system base, the new process is de-queued and control information is supplied from the process control block to the registers of the processor.