Patent GB-1528332-A (GB)
Title: Central processing unit employing microprogrammable control in a data processing system
IPC: G06F9/22
Filed: 1975-09-23
Abstract: 1528332 Microprogramming DATA GENERAL CORP 23 Sept 1975 [25 Sept 1974] 39039/75 Heading G4A  In a microprogrammed data processing system, a micro-instruction is transferred to a micro-instruction buffer 108, whence it is decoded at 69, either directly from a microinstruction memory 107 or directly from the main memory bus via logic 112, the logic 112 being enabled in response to predetermined micro-instruction signals from the logic 69. Such enabling of the logic 112 occurs when a new program instruction has been loaded into an instruction register 65, the micro-instruction memory 107 being disabled whilst a special micro-instruction is generated as the first micro-instruction for executing that program instruction. Thereafter the logic 112 is disabled and the micro-instruction memory 107 is enabled for generating the remaining microinstructions for executing that program instruction. This saves the period of time (one clock period) required to read the first microinstruction into the micro-instruction buffer 108 from the micro-instruction memory 107. The system operates on sixteen-bit words using an ALU followed by a shifter, each comprising integrated circuit chips, Figs. 3, 4 (not shown). Each word may be interpreted as a logical word, an address, a pair of eight-bit bytes or a sixteen-bit signed or unsigned binary number. A pair of inputs of the ALU is connected to a register bank, comprising eight twoinput-port, two-output-port registers coupled in parallel. Either the output of the ALU or one output of the register bank is coupled to the memory bus, enabling the ALU to be used for address calculation while the register bank is used to transfer data to the memory bus and thence to the main memory.  In the preferred embodiment the microinstruction memory 107 is a read-only memory, but a further writable micro-instruction memory may be connected in parallel with the memory 107, the memory 107 automatically being disabled upon the connection of the writable microinstruction memory in the system. Addresses for the micro-instruction memory 107 are obtained from a read-only memory 105 fed with the opcodes of instructions stored either in the register 65 or in a register 102, the latter register storing instructions executable only by means of microinstructions (not software). Each micro-instruction, Fig. 11 (not shown) consists of fifteen fields used, inter alia, to route data, control the function of the ALU and of the shifter, and select the next microinstruction. Selected parts of a microinstruction in the micro-instruction buffer 108 are used to address the micro-instruction memory 107 to select the next micro-instruction, either directly, via a register 111 or via a register 109. Register 111 is used for subroutine jumps, a current address being saved while a new address is jumped to. Register 10 causes a true address field of the micro-instruction in the micro-instruction buffer 108 to be used for addressing the next micro-instruction in the micro-instruction memory 107. The true address field is used for addressing one of four pages of read-only memory of the micro-instruction memory 107, whereas a false address field is used for addressing the current page. One of the special micro-instructions may cause a program counter to be incremented to skip the current instruction. Others may be used for effective and final address calculations and for beginning the execution of instructions executable only by means of micro-instructions. A signal DEC 2 obtained from the microinstruction in the micro-instruction buffer 108 allows the read-only memory 105 to produce alternative sets of addresses for addressing the micro-instruction memory 107. Detection of a particular configuration of a micro-instruction field may cause either the left or the right hand byte of a word fed to the ALU to be set to all zeroes or to all ones, for use as a marker. Specification 1,528,333 is divided from this Specification, and is referred to. Specification 1,528,331 is also referred to.