Patent GB-1113222-A (GB)
Title: Improvements in or relating to error detecting circuits
Inventor: GILL JOHN STEWART
IPC: G06J1/00
Filed: 1964-09-15
Abstract: 1,113,222. Pitch detectors; transistor comparators. MINISTER OF TECHNOLOGY. 6 Sept., 1965 [15 Sept., 1964], No. 37595/64. Headings H3T and H4R. In an error detecting apparatus a sequence of signals representing the results of consecutive measurements of a variable, e.g. the pitch period of speech as determined by the apparatus of Specification 1,113,224, are fed sequentially through a number of storage locations, one of which is termed a principal location, and a number of comparison circuits each operate to compare the value of the measurement stored in the principal location with the value stored in a respective one of the other locations and to provide an output dependent on the difference between the values. The outputs of the comparison circuits are added and, if the sum is such as to suggest that the value in the principal location is in error, the value in the principal location is modified. Values known to be in error, or where no measurement was obtained, are gated out of the comparison circuits and cause the operation of a compensating circuit to feed a value to the summation circuit equivalent to an average correspondence. Fig. 2 shows an embodiment in which six digit numbers representing, in binary form, the lengths of successive pitch periods in speech are fed sequentially through the storage locations S1 to S5, shifting from one location to the next under the control of a clock pulse on line 3. The signal in each store is converted to analogue form in digital to analogue converter DA1- DA5 and the value in the principal location S3 is compared with the values in each of the other stores in a respective comparison circuit CC1- CC4. The comparison circuits CC1-CC4 (see below) are arranged so that if the two inputs are within a predetermined range of each other no current is fed on to line 5 by the respective comparison circuit while if the difference between the values exceeds a predetermined amount a current, e.g. of 1À5 mA., is fed on to the line 5 from the respective comparison circuit. If the correlation is good the voltage level of line 5 is such as not to trigger the trigger circuit TC but if the correlation is poor, indicating that the value in store S3 is probably due to a measurement error, a signal is applied via gates G6 and G7 to a reset circuit RS which resets the stored number in store 3 to 000001, which is a number reserved for values presumed incorrect. Each store S1, S2, S4 and S5 has an OR gate G11, G12, G14 or G15 associated with it which has, as inputs, a line from each of the first five digit positions of the stored number. If a 1 appears in any of these digit positions the OR gate produces an output which enables the respective gate G1, G2, G4 or G5 to allow the measurement value to pass to the comparison circuit. If, however, the number stored is 000000, indicating no measurement, or 000001, indicating an incorrect measurement, the input to the comparison unit is inhibited by the respective gate and a constant current generator E1, E2, E4 or E5, which normally supplies a current of 0À75 mA., is inhibited to apply a signal on to line 5 corresponding to an average correlation as detected by a correlation circuit. Incorrect values in the subsidiary stores do not therefore cause the modification of a value in the principal store which may be correct. A " NOR " gate G13 is provided for the principal store S3 to monitor all digit positions in this store and to inhibit gate G6 if the number stored is 000000, indicating no measurement made. During periods of silence or unvoiced sounds a signal is applied to line 12 which is applied via gate G8; which is enabled as is G7 by the delayed shift pulse on line 3, to the reset circuit RS to change the number stored in S3 to 000000 if, due to an error of measurement, it is not that already. In an alternative arrangement, Fig. 1 (not shown), analogue signals may be processed and the comparison circuits supply a signal when the correlation is good rather than inhibiting a signal as in the embodiment of Fig. 2. Comparison circuit, Fig. 4, used for CC1- CC4 in Figs. 1 and 2, comprises a transistor long-tailed pair, consisting of transistors T1 and T2 with transistor T3 stabilizing the total current current, with a diode network MR1- MR4 and MR6 to which the signals to be compared are applied at terminals 6 and 7. The diode network is such that Tl conducts for all voltage conditions except when the voltage applied to transistor 6 is within a predetermined range of that applied to terminal 7. The voltage range over which the transistor T2 conducts may be varied by changing the number or characteristics of the diodes connected between points 8 and 9 and the respective transistor bases. In the embodiments described the circuit of Fig. 4 is used for circuits CC1 and CC4 while a similar circuit with diode MR6 omitted is used for circuits CC2 and CC3 to reduce the range over which T2 conducts so that, for an output signal to be obtained, a closer correlation is required between immediately adjacent measurements than is required on spaced measurements.