Patent GB-1342362-A (GB)
Title: Trigger pulse generator
IPC: G01R13/32
Filed: 1971-04-19
Abstract: 1342362 Trigger pulse generators SOLARTRON ELECTRONIC GROUP Ltd 19 April 1971 [12 March 1970] 11997/70 Heading H3T In a trigger pulse generator 12 having a hold off circuit 14, 16 arranged to enable a two state circuit 38 (Fig. 4) a predetermined interval of time after each trigger pulse generated by an output circuit 44 which is enabled by the two state circuit 38, means 60, 48 is provided for applying a trigger signal 10 to the two state circuit 38 and a delayed trigger signal to the output circuit 44 so that the two state circuit 38 switches its state in response to the trigger signal when enabled and the output circuit 44 generates a trigger pulse in response to the delayed trigger signal when enabled. Assuming a trigger pulse is generated by tunnel diode 44, this pulse is coupled via drive circuit 18 and line 76 to saturate transistor 86. This turns transistor 84, of the monostable hold circuit 14, off and brings transistor 78 out of saturation. Capacitor 88 charges through resistors 90, 92 until transistor 84 again conducts to turn on transistor 78 and reset the monostable circuit 14, the delay time of which can be altered by switch 96. When transistor 78 turns on a Zener diode 102 conducts and transistor 98 of the second monostable hold circuit 16, which is normally biased off, turns on after a delay determined by the Zener diode 102, resistors 100, 104 and capacitor 106. The tunnel diodes 38, 44, 54 are reset via an input 70 from a drive circuit 30 (Fig. 1). Conduction of transistor 98 fires tunnel diode 54 and this enables tunnel diode 38 so that the next trigger signal 10 via delay line 60 fires diode 38. This enables diode 44 so that the trigger signal, which is delayed longer by line 48, fires diode 44 to produce the output trigger pulse at 52. This operates the monostable hold circuits 14, 16 so as to inhibit operation of the two state diode 38 and output circuit 44 until after the delay period of these circuits when the above operation is repeated. The trigger levels of the tunnel diodes may be adjusted by resistors 68 and 66. Jitter in operating the trigger circuit is eliminated by using the two state and output circuits 38, 44 and input circuit 54 which may be omitted and the use of a second monostable circuit 16 eliminates jitter in the hold off time. A sampling time base circuit of a sampling oscilloscope (Fig. 1) uses the trigger pulse from generator 12 of Fig. 4 to start a ramp generator 20. When the ramp reaches the level of a stepped waveform from 24 the tunnel diode comparator 22 provides an output via a drive circuit 26 at 28 which is used to sample the trigger signal and a second input signal in the case of a dual beam scope. The output from the drive circuit 30 at 32 is used to operate memory gates which store the two samples taken and provides the vertical drive signals to the dual beam scope. Drive circuit 30 also pulses the staircase generator 24 and resets the compare for 22 and trigger generator 12. In an alternative embodiment of the trigger generator (Fig. 5, not shown) at the end of the hold period of the monostable circuit 14 an AND gate (116) is enabled and the trigger signal is passed to set a bi-stable (118). This enables an AND gate (122) and a delayed trigger signal via delay (124) sets a further bi-stable (120) which produces the trigger pulse to trigger a sweep generator (126) and the monostable hold circuit 14. The bi-stable (118) is then reset by the hold circuit 14 and the end of the sweep is detected by an end of ramp detector (130) which resets the further bi-stable (120). Specification 1,342,363 is referred to.