Patent GB-1455821-A (GB)
Title: Generation and monitoring of freuqencies related by a rational  ratio
IPC: H04N7/26
Filed: 1972-11-02
Abstract: 1455821 Frequency dividers BRITISH BROADCASTING CORP 31 Jan 1974 [3 Nov 1972] 50599/72 Heading G4D [Also in Division H4] Frequency conversion apparatus for dividing the frequency of an input signal by a non-integral ratio (e.g. 125 : 81 for 625 to 405 television line signal conversion or 709379 : 2500 for PAL colour subcarrier to line frequency conversion), comprises an adder having a plurality of stages and a first input thereto at which it receives a variable numerical operator, a clocked register having stages which are connected to a second input of the adder and also a carry stage, and means coupled to the carry stage of the register for causing the variable operator to take a selected value. In a first embodiment Fig. 3A for dividing an input frequency by a ratio P : q, i.e. 3 : 5 a three stage binary adder (n=3, 2<SP>n</SP>=8) is used with a four stage binary register. The number added by the adder to the register content is one of two numbers depending on the presence or absence of a carry term in the register. Where there is no carry term the output Q of the carry stage is activated and the adder input operator is P, i.e. 3 or in binary 011. However when there is a carry term the adder operator is P+2<SP>n</SP>-q' i.e. 6 or in binary 110, the Q output of the carry stage being activated to provide the required adder input. The register counts modulo 2<SP>n</SP> and the sequence is as follows: Provided P is less than q and q is not more than 2<SP>n</SP>, an n-bit binary adder and an n+1 bit binary register are sufficient to generate both the residue and carrier sequence. Fig. 4 shows apparatus where P=81 and q=125 which is the ratio between line rate 625 and 405. For this n=7 and where there is no carry term the number P (81 or in binary 1010001) is added in the adder, and where there is a carry term the number P+2<SP>n</SP>-q=81 or in binary 1010100 is added in the adder. The register counts modulo 2<SP>n</SP> and generates a carry when it reaches 128. When used in a 625/405 line standards converter the carry sequence is used to control the generation of the 81 new output lines made from every 125 input lines, and the residue sequence to control the interpolation coefficients and pattern of use of the storage units. The distribution of these 81 among the 125 follows the beat pattern of regular sequences in this ratio, equivalent to the 81 carry terms arising during 125 additions of 81 modulo 125. If P is greater than q it may be expressed in the form P = m. q+r where 0<r<q and m is a positive integer. Thus counting in steps of P modulo q is equivalent to counting in steps of r modulo q with the addition of m carry terms every count. Thus Fig. 3A may be used with P=23, q=5 with the addition of 4 carry terms every count. The PAL subcarrier and line rate are related by the ratio 709379 : 2500 which gives 709379=283. 2500+1879. Thus in counting subcarrier cycles referenced to line rate there will be either 283 or 284 subcarrier events between line rate events, and the occurrence of 284 will correspond to the occurrence of the carry when counting in steps of 1879 modulo 2500, i.e, counter 22, Fig. 5, the subcarrier source 24 being applied to a counter 20 which divides by 283 if there is no carry output from counter 22 and by 284 if there is a carry output. The mean frequency of the pulses at the output of counter 20 will be equal to the line rate, although there will be a slight jitter on these pulses, in that their timing will not be exactly constant. The output of counter 20 is applied to a phase comparator 26 where it is compared in phase with the output of a line rate source 28, and the comparator output is applied as a feedback signal to the line rate source. However because of jitter it is preferred to apply the comparator output to an adder 30 to which the output of D/A converter 32 supplied with the residue output from counter 22 is applied. The output from adder 30 thus accurately represents the phase difference between the line rate source 28 and the line rate signals which are ideally generated from the subcarrier source 24. Switch 34 directs this error signal to either the line rate source or the subcarrier source depending on which is the master source. Switch 34 has a third position for use when the relationship between the two sources is being monitored but not controlled. The error signal is applied to a threshold circuit 36 so that when the error exceeds a preset amount an error indication is given over line 38 and counter 20 is reset. A 3-times subcarrier oscillation may be related to line rate with 851 or 852 programmable divider and a modulo 2500 counter counting in steps of 637. More complex arrangements of deriving line rate from the subcarrier rate or line and frame rates from 3-times the subcarrier rate are respectively described with reference to Figs. 6 and 7, not shown. Reference is made to generating complete PCM digital television waveforms, PAL type encoded colour signal triplets, colour bars, coloured captions, wipers, cross-fades and split-screen effects.