Patent GB-948972-A (GB)
Title: Electric voltage comparison means
Inventor: ALLMARK REGINALD HUGH
IPC: G01R31/26
Filed: 1961-10-20
Abstract: 948,972. Voltage comparison; transistor testing. ENGLISH ELECTRIC CO. Ltd. Oct. 19, 1962 [Oct.20, 19611, No. 37791/61. Heading G1U. [Also in Division H3] Current for voltage comparison comprises two similar transistors with parallelled emitter collector circuits to a common load; each transistor having positive feedback between the collector and emitter circuits accelerating any change in collector current, with an output to each feedback circuit providing a signal on change of the appropriate collector current; input comparison D.C. signals applied to the respective base emitter circuits, and an auxiliary circuit interconnecting the junction of the common emitter load with the transistor emitter circuits to a bias source and a superimposed pulse generator, whereby the transistor whose base potential is nearer the bias potential rapidly changes between conduction and nonconduction on energization from an appropriate D.C.source. Fig. 1 shows a comparator circuit which comprises two PNP transistors 13,14 with emitter/ collector circuits parallelled to common load 10 and transformer positive feedback paths accelerating changes of collector current, from which tertiary windings 19, 21 derive output signals. Transformer 25 in series with a negative bias source 29 injects pulses into the parallel emitter/collector circuits over diode 26 preventing inflow of current thereto, and the output voltages of the transistors are limited by biasing their collectors negatively over diodes 32, 33. Comparison voltages are applied negatively to the transistor bases over terminals 30, 31 and the bias over transformer 25 is adjusted to slightly exceed the magnitudes of the comparison voltages, and in absence of a pulse on transformer 25 the voltage drop across diode 26 is small so that the emitters are held negative to the bases, and no current flows in the collector circuits so that no input appears on either winding 19 or 21. On pulsing transformer 25 to reduce the current flow in diode 26, the emitter potentials rise, and on exceeding the potential of the base carrying the greater negative potential, base and collector currents flow in the appropriate transistor to arrest any further rise of potential at junction 23. Diode 26 is cut off by the pulse, and the remaining transistor is inhibited from conduction by positive feedback across the conducting transistor which increases its own current and reduces that of the other. A pulse of output current then appears in the tertiary winding 19 and 21 of the conducting transistor and denotes the base input carrying the greater potential. On termination of the pulse on transformer 25, the circuit returns to its quiescent condition with transistors nonconducting. The input signals may alternatively be positive in the range between the potential of source 29 and the maximum cathode potential of diode 26 when transformer 25 is pulsed. NPN transistors may be used with reversal of the applied potentials. In Fig. 2 the voltage comparator 35 of Fig. 1 has outputs 39, 40 energizing the 'set' and 'reset' inputs of a bi-stable device 36 having 'true' and 'complement' output circuits 37, 38; the former being operated on energization of the 'set' input persist until energization of the 'reset' input, when the latter is operated to persist until reenergization of the 'set' input. Comparison voltage input 31 is held at negative bias and input 30 is normally held at zero and driven negatively from a pulse generator 41 of amplitude twice that of the bias on 31. Pulse generator 42 energizing transformer 25 is synchronized to generator 41 with a slight time delay, and an output is produced from transistor 13 or 14 on each pulse of 42 to indicate which has the greater base potential. In absence of a pulse on 30, transistor 14 conducts and energizes the reset circuit to develop an output signal at the 'complement' output 38 and if a pulse is present at 30, transistor 13 conducts to energize the 'set' circuit and develop a signal at the 'true' output 37. The apparatus is applicable to readout of a ferrite core storage device replacing pulse generator 41; a zero producing an output at 'complement' circuit 38 and a unit producing an output at 'true' circuit 37. For acceptance of readout pulses of either polarity, a third transistor feedback circuit similar to those shown in Fig. 1 is connected to junction 23; the output winding energizing an OR gate also energized from the output winding 19 of transformer 17 with its output circuit connected to the 'set' circuit of device 36. The transistor circuit base input is derived from terminal 30 so that a negative pulse holds the transistor circuit nonconducting and a positive pulse holds transistor 13 nonconducting while operating the third transistor to pulse the 'set' circuit of 36. The third transistor may alternatively be parallelled in the transistor 13 but made responsive to positive pulses. In apparatus for testing the saturation current gain of a transistor (Fig. 4) a voltage comparator 43 as shown in Fig. 1 is similarly connected to a bi-stable output device whose 'true' and complement' circuits control indicator lamps 49, 50. The test transistor 51 is connected with its collector circuit energized from a negative pulse generator 56 over variable resistance 53 and its base circuit energized from a negative D. C. source over variable resistor 55; the emitter being connected to zero of the D.C. source. The generator pulses are adjustably delayed at 57 to energize transformer 25 of the comparator circuit, and inputs 30, 31 thereof are respectively energized from the collector circuit and a variable negative bias source 58. Base circuit current is adjusted by 55 to a preset valve and the current amplitude of pulses from 56 is adjusted by 53 to a preset value corresponding to a selected base circuit current value. Negative reference bias on 31 is adjusted to the maximum permissible collector potential for the test conditions and delay 57 is adjusted to regulate the instant of pulsing transformer 25 over the duration of each pulse applied to collector circuit 52, so that the collector potential of the test transistor is compared with the reference voltage during the whole range. If saturation current gain exceeds a specified value, collector potential remains less negative than the reference potential so that lamp 50 remains illuminated, but if in defect of the reference value the collector to emitter potential exceeds saturation value during each collector current pulse, so that during the range of delay adjustment the collector potential falls below reference and lamp 49 is illuminated instead of 50. Base circuit current is then adjustable by 55 to the minimum value at which collector potential does not fall below the reference potential at any instant during a collector current pulse.