Patent GB-1172842-A (GB)
Title: Improvements in or relating to Calculating Machines.
Inventor: DRAGE JAMES JOHN
IPC: G06F3/023
Filed: 1966-01-03
Abstract: 1,172,842. Electronic keyboard calculators. BELL PUNCH CO. Ltd. 3 Jan., 1967 [3 Jan., 1966; 31 March, 1966], Nos 42/66 and 385/67. Heading G4A. An electronic calculating machine with a single set of ten digit keys, a register comprising a plurality of pulse counting stages and a means for visually displaying the number stored in the register is further provided with means including a timing circuit and switch means for entering the digits of a number represented by successive key depressions into successive register stages starting from the high denomination end. As shown (Figs. 5 and 5a) an electronic calculating machine comprises a keyboard including a single set of decimal digit keys 11, a visual register 29 comprising a plurality of decimal pulse counting stages connected to a corresponding plurality of digit display tubes (Fig. 1, not shown), two store registers 38 and 39, each consisting of a plurality of decimal pulsecounting stages, and a timing circuit (Fig. 4) comprising an oscillator 14 connected to a decade counting tube 13. The tenth output P9 of the outputs P0-P9 of this tube 13 is connected to a register timer circuit 15 having 15 states corresponding to outputs To, TD and T1-T13. The P9 output is also connected through AND gates 19 and 20 to a keyboard timer circuit 18 having 13 states corresponding to outputs t1-t13, the gates 19 and 20 being controlled so that the circuit 15 has a counting cycle of 1 more than the circuit 18. Entering numbers.-The timing circuits 15 and 18 are initialized to their To and t1 states respectively by depression of a function key 9. Depression of a selected digit key generates signals to reset a bi-stable circuit 26 to its C-state. Depending on which key is selected, a corresponding one of the pulses P0-P8 during a t12 period opens a gate 25, sets the bi-stable circuit 26 to its C+state and opens a gate 27 to allow a corresponding number of P-pulses on line 9<SP>1</SP> to pass by way of an amplifier in a buffer circuit 135 and a highway 28 into one of the stages R1-R13 of the visual register 29, the particular stage involved being determined by the coincidence of the t12 pulse with one of the T1-T13 pulses. The first digit of a number is fed into stage R12, R13 being provided for storing carries. After entering each digit, the timing of circuits 15 and 18 shifts relatively by one step so that successive digits are fed into successive R-stages of lower denomination. Operation of the oscillator 14 is inhibited between key depressions by a gate 13a. Clear and enter.-After a number has been entered into the visual register 29 it may be transferred into a selected store register and the visual register cleared. This operation is effected stage by stage on corresponding stages of the registers 29 and 38 or 39, the store register involved being selected by function keys R1 and R2 on the calculator keyboard (Fig. 1, not shown). During this operation (selected by a key CE) the signals # and CE are positive and a signal # CE negative. The timing circuits 15 and 18 are initially reset (as before) so as to run in step and are inhibited during alternate cycles of counter 13 by a gate 17 so that the processing of each pair of corresponding register stages selected by the coincidence of t and T timing signals corresponds to the generation of two groups of ten GD pulses. During the first half cycle (in which C - is positive) for each pair of stages, the first group of ten GD pulses is fed to the stages of both registers by respective gates 125 and 41. Carry pulses CO1 and CO2 emitted by respective carry circuits 33 and 30 as the respective stages reach a count of zero are fed to difference sensing gates 129, 130 which control the input of pulses to a decade counter forming a further part of the buffer circuit 135. Depending on which gate 129 or 130 is opened first, a bistable circuit 131 receives a setting signal on line α or #. The counter of circuit 135 thus stores the difference between the digits in the two register stages and the circuit 131 indicates which is the greater of the two. The tenth pulse P9 of said first group then sets bi-stable circuit 26 (through a gate 137) to initiate the second half cycle in which signal C + is positive. Gate 125 now supplies a second group of ten GD pulses to increment the counter of circuit 135 and the respective stage of the visual register 29. As soon as the visual register stage reaches zero, signal CO1 opens a gate 155 to inhibit transfer of further pulses along highway 28. As soon as the counter of circuit 135 reaches zero, signal B = O issues which, by way of an inverter 144, closes a gate 142 to inhibit further action of the counter 135 and also changes the potential on output line y of bi-stable circuit 131 whereby a gate 34 which controls the supply of GD pulses to the respective store register stage is either closed or opened (depending on the initial setting of circuit 131) whereby either a number of pulses equal to said difference or the complement of this number are fed to the respective store register stage. The above is repeated for each stage in turn, the unmatched stages R1 and R2 merely being recycled. Exchange.-The contents of the visual register and a selected store register may be exchanged in a similar manner to the above but with signals CE and # CE having the reverse polarity. Gate 155 is thus inhibited by gate 150 and a gate 132 is effective to control passage of pulses from each said second groups to the visual register stages in a manner similar to gate 34 for the store register. Decimal point and arithmetic operations.- The position of the decimal point is indicated by lamps 8 (Fig. 1, not shown) and counters VDPC and IPDPC are provided in association with the registers for obtaining alignment of registers (by shifting timing circuit 18 relative to circuit 15) prior to or during arithmetic operations, as described in Specification 1,172,844. As well as addition and subtraction, multiplication and division operations are also referred to briefly. In all these operations the final result is stored in the visual register.