Patent GB-791156-A (GB)
Title: Electrical computer
IPC: G11B20/16
Filed: 1956-02-10
Abstract: 791,156. Digital electric calculating-apparatus. STANDARD TELEPHONES & CABLES, Ltd. Feb. 10, 1956 [Feb. 12, 1955], No. 4263/56. Class 106 (1). The arrangement shown in Fig. 1 performs a computation of the form AÎB+C+R where A, B, C, R are decimal digits normally representing a multiplicand, multiplier, partial product and carry respectively. The digits are represented in a 4-digit binary combination code so that the numbers A, B, C may each be stored, e.g. in 4 parallel stepping registers comprising chains of cold cathode tubes as described in Specification 663,574, [Group XL (c)], which may be associated with magnetic tape and drum memories. The code comprises a binary portion and a 3- digit quinary portion and is such that the 9's complement can effectively be obtained by reversing the binary and one of the quinary digits; various alternative codes are discussed. The coded decimal digits are set up on bistable flip-flop devices such as BSA. and BSA1-3 in assembly AI. Device BSA registers the binary portion of digit A which energizes one of terminals A0, A1, and devices BSA1-3 register the quinary portion which is translated by a network TR of coincidence gates so as to energize one of terminals A<SP>1</SP>0 - 4. Digits B, R, C are similarly registered and translated in devices BSB, BSR, BSC, and assemblies BI, RI, CI. The A and B terminals are connected to multiplication table TM (Figs. 2-6, not shown), which produces the two-digit sum in similar bi-quinary form on units and tens terminals U<SP>1</SP>0-4, U0-1, D<SP>1</SP>0-4, D0-1. The C and R terminals are connected to addition table TA1 which energizes one of quinary sum output terminals T0-4 and one of terminals S0-3 representing multiples of " 5 ". These terminals and the units product terminals are connected to addition table TA2 which produces a new digit C in the 4-binary-digit form on output terminals CO1-8 which may be applied to the 4 parallel registers for C, and also energizes one of terminals W0-2 representing multiples of " 10 ". These terminals and the tens product terminals are connected to carry tables TR1, TR2 to produce a new carry digit R on output terminals RO1-8 which may be connected via a delay circuit to BSR and RI. A repetitive process for multiplying multi-digit numbers A and B is described in which A is multiplied by each digit of B in turn by appropriate stepping of the registers for A, B and C, the A registers being ring- connected and a fourth set of registers receiving the lower significant result digits as they are stepped out of the C registers. For addition, the B digit is made " 1 " and the numbers to be added are entered in the A and C registers. Subtraction is similarly effected except that the C digits are supplied via a complementing circuit (Fig. 10, not shown), and the result is adjusted according to whether a final carry digit is obtained. The tables employed each comprise a network of coincidence followed by buffer gates, the gates comprising, e.g. selenium rectifiers. The gate connections are discussed with reference to numerical tables such as Fig. 13 which indicates the values of the binary portion U of the units product digit, the four quadrants corresponding to different values of the binary portions A, B of the input digits being dealt with separately in the table TM. Specifications 766,318 and 791,157 also are referred to.