Patent EP-0053798-A2 (EP)
Inventor: PERNYESZI JOSEPH
IPC: H02K5/02
Filed: 1981-12-03
Abstract: 1. Monolithic integrated inverter-buffer using enhancement- and depletion-mode insulated-gate field-effect transistors (E, D) and comprising an output stage (ES) consisting of two transistors (Q10, Q11) having their controlled current paths connected in series between ground and a supply voltage (VD ), the transistor (Q10) connected to the supply voltage (VD ) being a depletion-mode output transistor, characterized by the following features : - A first prestage (V1) consists of a first enhancement-mode load inverter (EI1) and a first depletion-mode load inverter (DI1), and a second prestage (V2) consists of a second enhancement-mode load inverter (EI2) and a second depletion-mode load inverter (DI2), with the load inverters connected between the supply voltage (VD ) and an auxiliary voltage (VB ) of opposite polarity, wherein a first depletion-mode transistor (Q6, Q6') in the first and second enhancement-mode load inverters (EI1, EI2) has its source and gate connected to the auxiliary voltage (VB ), wherein the depletion-mode transistor (Q8, Q8') in the first and second depletion-mode load inverters (DI1, DI2) is connected to the supply voltage (VD ), wherein the first depletion-mode transistors (Q6, Q6') are connected in parallel with the enhancement-mode transistors (Q7, Q7') in the first and second enhancement-mode load inverters (EI1, EI2), respectively, and wherein the gates of the enhancement-mode transistors (Q7, Q7'), whose sources are coupled to the auxiliary voltage (VB ), are connected to the drains, and their drains to the gates, of the enhancement-mode transistors (Q9, Q9') of the first depletion-mode load inverter (DI1) and the second depletion-mode load inverter (DI2), respectively ; - the output stage (ES) consists of a series combination of the depletion-mode output transistor (Q10), which is connected to the supply voltage (VD ), and a grounded depletion-mode output transistor (Q11), the gates of which are connected to the outputs of the first depletion-mode load inverter (DI1) and the second depletion-mode load inverter (DI2), respectively, and - the input (1) is connected either directly to the gate of the enhancement-mode transistor (Q5) of the first enhancement-mode load inverter (E11) and to that of the depletion-mode transistor (Q8') of the second depletion-mode load inverter (DI2), and through an inverter (2) to the gate of the enhancement-mode transistor (Q5') of the second enhancement-mode load inverter (EI2) and to that of the depletion-mode transistor (Q8) of the first depletion-mode load inverter (DI1) (Fig. 1), or directly to the gate of the enhancement-mode transistor (Q5) of the first enhancement-mode load inverter (EI1) and through the inverter (2) to the gate of the enhancement-mode transistor (Q5') of the second enhancement-mode load inverter (EI2), with the gate of the depletion-mode transistor (Q8) of the first depletion-mode load inverter (DI1) and the gate of the depletion-mode transistor (Q8') of the second depletion-mode load inverter (DI2) connected to the output of the respective depletion-mode load inverter (Fig. 2), or to the gate of the depletion-mode transistor (Q8) of the first depletion-mode load inverter (DI1) and to the gate of the enhancement-mode transistor (Q5') of the second enhancement-mode load inverter (EI2), with the gate of the enhancement-mode transistor (Q5) of the first enhancement-mode load inverter (EI1) and the gate of the depletion-mode transistor (Q8') of the second depletion-mode load inverter (DI2) coupled to the output of the second depletion-mode load inverter (DI2) (Fig. 3).