Patent GB-785568-A (GB)
Title: Improvements in or relating to frequency divider circuits
IPC: H03B19/00
Filed: 1955-09-16
Abstract: 785,568. Pulse frequency-divider circuit. WESTERN ELECTRIC CO., Inc. Sept. 16, 1955 [Sept. 17, 1954], No. 26561/55. Class 40 (6). A pulse frequency-divider circuit comprises means for transmitting a single pulse at intervals of n digits of a clock frequency. The single pulses being applied to an adder circuit and the output of the adder circuit being connected to its input via a delay means of n/k digits, a gate transmitting an output pulse only on occurrence of both a pulse from the transmitting means and from the adder circuit which occurs on accumulation of a predetermined number of pulses in the circuit. Fig. 1 shows a twostage frequency divider where the division ratio is 1/(n)(2<SP>n</SP>) where n is any digit. A single pulse is applied from generator 10 to a delay line register frequency divider 11 which has a division ratio of n, the output is applied to a second stage of division including an adder circuit 12 which may be either a full or half adder. The output from this is connected through an n digit delay line 13 back to the input of the adder circuit. When the n digit delay line 13 is filled a gate 14 is enabled and a single output pulse appears on lead 16, the adder circuit being reset to begin the next cycle of division on receipt of a pulse from divider 11. In a modification shown in Fig. 2, 1 n equals 4 so that a division of - of the clock 64 frequency is obtained. The clock frequency is not shown in Fig. 2 but it is to be understood that clock signals are applied to various components such as amplifiers so that the pulses occur during the positive cycles of the clock frequency and in synchronism therewith, the clock frequency thus defining the digit interval of the circuit. The initiating pulse from single pulse generator 10 is applied to a divide by 4 stage 11 which may be of the delay line register type. The output at b, Fig. 3 (b), is applied via an OR circuit 18 to a half adder circuit 19, which gives an output on a first lead if one of two but not both inputs is present and an output on a second lead if both inputs are present, the first output appearing at point c, Fig. 3 (c), and the second at point e, Fig. 3 (e). The pulses at c, Fig. 3 (c), appear in the four digit time slots or intervals defined by the clock frequency. The pulses at c are passed through delay line 21 having 4 digits of delay and then applied as second input at point d, Fig. 3 (d), to the half adder circuit 19, thus the input at d is the output at c delayed by four digits of the clock frequency (four digits would probably represent one word or information message unit). When the pulse at b and a pulse at d coincide the output of the half adder 19 is a pulse at point e, Fig. 3 (e), this is a carry pulse is passed through 1 digit delay by line 22 to OR circuit 18 to produce a delay pulse at f, Fig. 3 (f). Thus an output appears at c if there is an input at d or an input at b or f or at b and f, but not if there is an input at d and at b or f and an output appears at e if there is an input at d and an input at b or f. When the output at c is a train of pulses corresponding to the capacity of delay line 21 a pulse is to be gated to output lead 16. This is attained by AND circuits 24 and 25 and 1 digit delay line 26. The output of the AND circuit at h, Fig. 3 (h), is delayed 1 digit by line 26 and applied at point k, Fig. 3 (k), as input to the AND circuit 25. Thus the gate circuit includes OR circuit 28, AND circuits 24, 25 and digit delay line 26. This is in effect a memory circuit which is triggered during the first digit interval by a pulse from point b through OR circuit 28 if there is an output at c and which circulates a pulse as long as there is an output at c for each digit interval. If this occurs the pulse is gated to output lead 16 during the first digit interval of the next number by a pulse from b applied to AND circuit 25. This circuit thus requires that each digit interval be filled before a pulse can be gated to the output lead. In the example shown this only occurs when n equals 4 when the binary half adder has counted up to 16. Thus an output pulse is gated for every sixteen input pulses which in turn are applied one for every 4 digits of the clock frequency. In a modification, Fig. 4 (a) (not shown), the amplifiers and compensatory delay lines have been added and the delay of the lines modified to take account of the inherent delay in components such as amplifiers of the circuit. The amplifiers may be of the transistor regenerative type, Fig. 4 (b) (not shown) and the AND or logical circuit may comprise a pair of diode elements such as varistors suitably biased. If n is a large number the first stage delay line frequency divider may comprise, Fig. 5 (not shown), two short circuited delay lines combined in an AND circuit. If the delay in the first divider stage is n digits and the accumulation in the second divider stage is k digits then the frequency division attainable may be In a further modification, Fig. 6 (not shown), all the possible frequency divisions of the word frequency or of the input of the second stage may be attained by precessing a number A into the second stage frequency divider so that the division attainable is times the clock frequency. The number A is preset into the half adder of the second stage frequency divider so that this accumulates pulses but the accumulation is finished A pulses earlier than previously described. In a further modification, Fig. 7 (not shown), the output is a train of pulses occurring once every digit for the first half of the cycle of the low frequency output of the second stage frequency divider. Thus these pulses provide essentially a square wave which after filtering can give a desired sine wave. Fig. 9 shows a modification of the first stage of frequency division in which a train of clock frequency pulses are appled from source 70 to an inhibitor circuit 71. The output pulse of which is applied to the input via parallel delay lines 75, each having integral digit time delays. The outputs of the delay lines applied to the input of the inhibitor prevent the appearance on its output lead of a pulse for the next (n - 1) digit times accordingly the circuit has a division of n cycles of the clock frequency. Other types of pulse train generators may be connected in place of the digit delay line 75.