Patent GB-632893-A (GB)
Title: Improvements in or relating to two-way electric pulse communication systems
IPC: H04B14/02
Filed: 1947-11-26
Abstract: 632,893. Duplex pulse signalling; gating circuits. STANDARD TELEPHONES & CABLES, Ltd., and SCULLY, C. T. Nov. 26, 1947, No. 31303. [Classes 40 (v) and 40 (vi)] In a two-way pulse repeater having similar pulse amplifiers connected oppositely between two transmission circuits, a plurality of parallel paths are provided connecting each transmission circuit to the input of the corresponding amplifier. Retransmitted pulses from the other amplifier are passed over one of said paths to the transmission circuit but prevented from gaining access to the first amplifier over any of the paths, whilst there is always access for input pulses to the first amplifier over at least one of the paths. In one embodiment, for use when the pulse duration is less than the pulse interval, two pulse amplifiers 1E, 1W, Fig. 1, are used for repeating pulses to the adjacent stations to the east and west respectively. Terminal 2E receives pulses from and transmits pulses to the west station and is connected to amplifier 1E by two parallel paths including, respectively, delay networks 3E, 4E, and gate circuits 5E, 6E. Amplifier lE comprises, in succession, a blocking circuit 7E, amplifier 8E, delay circuit 10E and amplifier 9E. A switching pulse from the output of circuit 10E controls the blocking circuit 7E through a pulse lengthening circuit 12E, if necessary, and a delay circuit 11E. This pulse also controls the gate circuits 5W, 6W, of the east-to-west amplifier input paths. The output of amplifier 1E is connected.to the other terminal 2W of the repeater through the delay circuit 4W, corresponding to circuit 4E already referred to. The west repeating half of the repeater is identically arranged, corresponding elements being given the same numerical references with the distinguishing letter W. The gate circuit 5E is normally closed and 6E is normally open so that received pulses normally reach the amplifier over circuit 4E. When a transmitted pulse is delivered from conductor 15W, at the same time a switching pulse is applied over conductor 13W to shut gate 6E and open gate 5E, so that received pulses now reach amplifier 1E over circuit 3E. The transmitted pulse cannot pass gate 6E and reaches 5E after delay in circuits 4E, 3E so that 5E is then closed again. If a transmitted pulse arrives during a received pulse, part of the latter will pass through path 4E, 6E and part through path 3E, 5E being re-united in conductor 14E, the delays of circuits 3E, 4E being equal. The blocking circuit 7E is necessary if amplified pulses are transmitted from the repeater in both directions over the same medium, the terminals 2E, 2W then being effectively connected together. In a modification for use with pulses of any desired maximum duration or minimum spacing, the terminal 2E, Fig. 3, is connected to conductor 14E feeding the amplifier, through n+ 1 parallel paths, n being the integer equal to or just greater than T/t, where T is the maximum pulse duration and t is the minimum pulse spacing. In the case illustrated, there are four paths including gate circuits 21E ... 24E respectively, all of which are normally open. The first path includes three similar delay networks 25E ... 27E, each of delay time t/2. The inputs of these networks are connected to the gate circuits 22E ... 24E through delay networks 28E ... 30E respectively having delay times t/2, t and 3t/2 respectively. The gate circuits are operated in succession at intervals of t by a switching pulse from conductor 13W and delay circuits 31E ... 33E. At least one of the paths will always be open for received pulses, but transmitted pulses from conductor 15W will be unable to pass any gate circuit as the latter are closed in succession at the time the pulse reaches them. In a modification of this embodiment, Fig. 7 (not shown), all the delay networks introduce the same delay t, circuits 28E ... 30E being omitted and replaced by delay circuits connected between each adjacent pair of gate output circuits. In another embodiment, in which the transmitted and received pulses have opposite signs, terminal 2E, Fig. 8, is connected to the first of three cascaded delay networks 115E ... 117E. The conductor 14E feeding the amplifier is connected to the output of three cascaded delay networks 118E ... 120E and rectifiers 121E ... 124E connect the input and output sides of corresponding networks of the two series. Resistances 125E ... 132E are terminations for the networks. The conductor 15W conveying the transmitted pulses is connected to the output of the network 117E and no switching pulses are necessary. A positive received pulse can pass to conductor 14E through each of the four paths, of delay time 3t, including the four rectifiers, when no transmitted pulse is present. A negative transmitted pulse from conductor 15W blocks each of the rectifiers in turn on its passage to terminal 2E, but at least one path is always open to the received pulses. Gating circuits.-Complete circuits are described, Figs. 4 and 6 (not shown), for the systems shown in Figs. 1 and 3. They include gating circuits of two types. In one, a pentode valve has the signal pulse applied to the suppressor grid and the gating pulse to the control grid or vice versa. In the other type, a cathode-follower triode has the signal pulses applied to the control grid and the valve is gated " on " by a pulse applied to the anode.