Patent GB-1045571-A (GB)
Title: Improvements relating to data storage devices
Inventor: HOUNSFIELD GODFREY NEWBOLD
IPC: G11C11/06
Filed: 1961-11-04
Abstract: 1,045,571. Magnetic storage circuits. ELECTRIC & MUSICAL INDUSTRIES Ltd. Oct. 18, 1962 [Nov. 4, 1961], No. 39564/61. Heading H3B. In a magnetic storage matrix in which a selected storage unit is read out by applying coincident switching currents to a row and a column winding, each row switching current comprises either a single pulse or twosuccessive pulses, and each column switching current comprises a single pulse commencing before and terminating after the row switching current, the initial state of the storage unit being identified by the characteristics of the voltage developed across the column winding during the passage of the row current. Arrangement using row switching current comprising two pulses. A magnetic storage matrix 20 is shown in Fig. 8 in which the sets of row and column windings are connected to respective drive selectors 21, 22, each column winding including a resistor 23, 24 at opposite ends. The column windings are connected by isolating rectifiers 25 to a common output conductor 26 and the voltage developed across any of these windings during read out is detected across resistor 27. The characteristics of the various currents and voltages are shown in Figs 9(a) to 9(1), the corresponding encircled references in Fig. 8 indicating the position in the circuit to which each characteristic applies. The first row pulse, Fig. 9(b) in time period t 3 -t 7  coacts with the column current, Fig. 9(a), to switch the storage core to the zero state, and a voltage pulse in conductor 26 is produced in the same time period as shown in Fig. 9(c). The second row drive pulse in time t 8 -t 12  again acts in the zero switching sense. Consequently if the core was originally in the one state, the characteristics of the two output voltage pulses in periods t 3 -t 7  and t 8 -t 12  respectively will be different in the trailing region, as shown. On the other hand if a zero was originally stored the voltage pulses will be the same. The remainder of the circuit apart from transistor 29 is devoted to developing a read-out signal if the storage core originally has a one registration. A muting switch 32 is opened for the duration of the read operation, Fig. 9(d) and the voltages pass through a condenser 30, Fig. 9(f) and amplifier 31 to a condenser 34. This condenser is normally short-circuited and is effective only during time periods t 4 -t 6  and t 9  to t 11  when a switch 35 is opened, Fig. 9(g). The voltage builds up across condenser 34 in each of the two time periods as shown in Fig. 9(i), the higher voltage being indicative of the initial binary one state. The final condenser voltage in each case is applied in time positions t 5 -t 6  and t 10 -t 11  to a condenser K over a switch 37, as shown in Fig. 9(j). If the first and second voltages over switch 37 are the same, no output is developed across resistor 39. If the two voltages differ, the condenser 38 is first charged and then partially discharged, Fig. 9(k), and an output pulse is developed across resistor 39 which is amplified at 42. If a zero state was read out the condenser would remain charged at a steady lower value. For writing in the row and column currents are followed by negative and positive half-switching current pulses, Figs. 9(a) and 9(b), in time positions t 14 -t 16  and t 16  to t 17 , the first coincident pulses switching the core to state one. If a one is to be stored, a pulse is applied to transistor 29, Fig. 9(e) which causes the column half-switching pulse to by-pass the column winding. Thus the switched core stays in the one state. If a zero is to be stored the transistor is inoperative and the core is switched by coincident row and column pulses. Arrangement using a single pulse row current. As shown in Fig. 10, each storage unit comprises two cores which are set to opposite states to store a binary digit. Two windings are provided for each column of storage units which are connected through isolating rectifiers 25 to respective output conductors. Two writing switches 29 are provided which are selectively closed to register a binary one and a binary zero respectively. In this sytem only a single row pulse is needed for reading out as the relative positions of the one and zero value voltage waveforms in the two output conductors gives an immediate identification of the digit stored. Construction. The matrix, Fig. 1, may comprise two glass sheets 1, 2 each having parallel grooves accommodating a thin film layer 5, 6 and a conductor 9, 10, the glass plates being spaced by a magnetic and insulating layer 3 with the respective sets of grooves orthogonally positioned. Each intersection of the film layers forms a closed magnetic circuit threaded by two co-ordinate conductors, the easy areas of the respective magnetic layers being parallel and at an angle of 45 degrees to the grooves. Alternatively, in another embodiment, Fig. 4, strips of deposited magnetic thin film 15 have thickened edge portions 16 and accommodate conductors 17, one sheet being covered by an insulating film 18. Alternative shapes and arrangements of films and conductors are briefly described, Figs. 5 to 7 (not shown). Unselected columns may have pulses of reversed polarity applied so that an increased pulse value may be used in the selected row.