Patent GB-845120-A (GB)
Title: Improvements in or relating to semiconductor devices and to circuits utilizing them
IPC: G11C11/35
Filed: 1957-03-29
Abstract: 845,120. Semi-conductor switching and multistable state circuits. WESTERN ELECTRIC CO. Inc. March 29, 1957 [April-18, 1956], No. 10359/57. Class 40(6). [Also in Groups XIX, XXXVI and XXXVIII] In a device comprising a semi-conductor body including a plurality of separate conducting paths each having a high impedance state and a low impedance state the paths are so arranged relative to one another that operation of one path in its low impedance state primes an adjacent path for transfer to its low impedance state. In the device shown in Fig. 1 each path comprises separate P and N portions 11 A-D and 27A-D, and common P and N zones 13, 14. The separate N type zones are asymmetrically arranged with respect to the separate P type zones so that when path B for instance, is operating in its low impedance state carriers are traversing the part of the common P type zone beneath the extension 27C of the N type zone associated with the adjacent conduction path C. Consequently when a potential greater than the minimum sustaining potential for low impedance operation of path C is applied to that path by throwing switch 21 to its lower position current is diverted from N type zone 27B to the extremity or starter portion of N type zone 27C. Current flow then advances along the junction 17 to the preferred path of conduction immediately beneath the junction 15C. This effect occurs only if the switching action takes less time than the lifetime of an electron in zone 13 and the transit time of electrons across the zone. Current path A remains in its high impedance state since the starter portion of its N type zone 27A is too remote from current path B to be primed. The lateral extent of the region of the junction 17 through which minority carriers are emitted when the current path B is in its low impedance state, as shown in Fig. 2 depends on the lateral resistance of the zone 13 and determines the maximum spacing between the edge of junction 16B and the edge of starter portion 27C for which priming occurs. The Specification includes a mathematical treatment of the effects described above. It is stated that the existence of two stable conduction states in each path is due to change of the current multiplication α with current. Such changes of α may be enhanced by introduction of impurities, such as iron in silicon or nickel in germanium, or by bombarding with high or intermediate energy particles to produce crystal dislocations. In an alternative arrangement suitable for use as a ring counter (Fig. 7) the separate P and N portions of four conducting paths are disposed, as shown, along the edges of the upper face of a wafer comprising common P and N portions. Loads 73 and 74 are chosen small compared with 72 so that when section 1 is operating in its low impedance state as in the starting position the voltage applied to the remaining sections is below the breakdown voltage but above the minimum sustaining voltage for low impedance operation of the sections. The operation of the illustrated circuit is as follows: when an impulse poled to forward bias the outer junctions of the four zone sections 2 and 4 is applied via condenser 77 section 2 goes into its low impedance state. Section 1 reverts to its high impedance condition because the impulse current through resistor 72 reduces the potential across it to below the minimum level required to sustain the low impedance condition. At the end of the input pulse when conditions return to normal section 3 enters the low impedance state since it is primed by the current in section 2 whereas section 1 is not. A circuit for decoding a three digit binary number comprising a stepping device according to the invention is shown in Fig. 8. The device comprises a branched array of four zone stepping sections each of the type shown in Fig. 1. The stepping sections are arranged in pairs of banks each bank representing a binary digit and comprising bank sections and a pair of routing sections for each transfer section, one routing section of each pair being connected to line 110 and the other to line 111. Initially the circuit is set so that section 114 is in the low impedance condition and routing sections 115, 116 primed. Operation of the circuit is as follows: A pulse train PQ consisting of positive pulses 101, 112 and negative pulse 102 and representing the number five is fed to a pulse forming circuit 103. This circuit provides positive output pulses on lines 110 and 111 for positive and negative input pulses respectively so that on receipt of the first pulse 101 routing section 115 is triggered to its low impedance state and section 114 is cut off by the voltage developed across resistor 72 by the current impulse. The discharge in section 115 primes transfer section 117 so that when the pulse is removed and original conditions restored section 117 becomes conductive. On receipt of negative pulse 102 the positive output pulse 106 applied to primed section 118 renders it conductive and as before section 119 is triggered to its low impedance state on removal of the pulse. Finally the positive pulse 113 triggers the primed section 120 to its low impedance state and primes section 121 so that on removal of the pulse current flows through section 121 to resistor R5, thereby completing the decoding process. All the above described arrangements can be reset by applying a voltage pulse to the first section only of the array high enough to cause avalanche breakdown of the reverse biased junction and hence trigger it into its low impedance state. The pulse steals current from the conducting section by virtue of the voltage drop in resistor 72.