Patent GB-1017057-A (GB)
Title: Solid-state translation device
Inventor: WRIGHT GORDAN THOMAS
IPC: H01L29/00
Filed: 1962-03-14
Abstract: 1,017,057. Solid state devices. NATIONAL RESEARCH DEVELOPMENT CORPORATION. March 14, 1963 [March 14, 1962], No. 9875/62. Heading H1K. A solid state translation device comprises an emitter region 2, Fig. 1, of highly resistive material having a wide gap d, Fig. 2, between its conduction and valence energy levels a and b respectively, a collector region 3 of material having a smaller gap e between its conduction and valence energy levels than the corresponding gap of the emitter material, an emitter electrode 5 for injecting charge carriers of one type into the emitter region, a collector electrode 7 for collecting charge carriers of the same type from the collector region, a gate region 9 positioned between the emitter region and the collector region and consisting of semiconductor material containing charge carriers of the opposite conductivity type to the charge carriers injected by the emitter electrode and in which the difference c in energy level between the collector and emitter regions for charged carriers of the type injected by the gate region is sufficiently great to prevent substantial flow of charge carriers of the lastmentioned type between the gate and emitter regions so that said charge carriers are constrained within the gate region and serve to control current flow between emitter and collector regions by space-charge-limitation in the emitter region. In the embodiment of Figs. 1 and 2, the emitter and collector electrodes are of N-type conductivity material such that current flow is by means of electrons. The material of the emitter region may be silicon having a gap d of 1À1 eV or gallium arsenide having a gap d of 1À4 eV. Recommended values for energies e and c are 0À6 eV and 0À5 eV respectively. The thickness of the gate region 9 may be 0À1 Á- 1À0 Á whereby the recombination rate of emitter electrons with gate holes is so low that the gate region is virtually transparent to the emitter electrons. The dimension of the emitter region (1 Á-100 Á), the dimension of the collector region and the positive potentials applied to the gate region and collector electrode are such that the potential gradient in the collector region is much steeper than in the emitter region, causing acceleration of the electrons in the collector region, such that the electrons transfer across the gate region by diffusion. In a second embodiment, Figs. 3 and 4, the emitter and collector electrodes are of P-type conductivity material such that the current carriers are holes. The collector region 14 comprises a layer of weakly P-type germanium 1 Á-10 Á thick, with two layers 13 and 11 of heavily P-type germanium forming the collector electrode, the former layer being 10 Á-20 Á thick. A strongly N-type layer of germanium is deposited on layer 14, or is produced by impurity diffusion into layer 14, to produce a gate region 0.1 Á-1À0Á thick. An annular electrode 19 makes contact with the gate region. A layer 16 of intrinsic gallium arsenide is deposited on to layer 15 to form the emitter region 10 Á thick. A further layer 17 of gallium arsenide, strongly P-type, is deposited on layer 16 to form the emitter electrode. A positive potential is applied to the emitter electrode, whence the energy level diagram of Fig. 4 is produced. The electrons in the gate region are prevented from passing into the emitter region by the sudden 0À6 cV jump in the conduction level. The translation devices of the invention are stated to exhibit pentode-like characteristics. Gallium phosphide and silicon may be used for the emitter and collector regions. Where the materials of the two regions have similar crystal structures the collector region may be manufactured from a mixed crystal so that by controlling the constitution of the crystal its internal potential and therefore the positions of its energy levels can be adjusted. The devices of the inventions may be manufactured by the halide carrier process of depositing successive epitaxial layers of semi-conductor. Reference has been directed by the Comptroller to Specification 756,339.