baber/WOPTO huggingface dataset:
Patent TW-445594-B (TW)
Title: Fabricating process for read only region and pad region of mask read only memory defined by using single programmable mask
Inventor: LEE CHEN-JUI
IPC: H01L21/8246
Filed: 1999-07-13
Granted: 2001-07-11
Abstract: The present invention discloses the fabricating process for the read only region and pad region of mask read only memory (ROM) defined by using single programmable mask. This invention includes the following steps: providing semiconductor substrate of the first type, in which the first type semiconductor substrate is divided into one read only region and one pad region; forming a plurality of the first gates and a plurality of the second gates inside the read only region and pad region, respectively; forming a second type source/drain region inside the substrate on both sides of each one of the first gates located in the read only region; sequentially forming the first insulating layer and the second insulating layer on the surface of read only region and pad region; using photolithographic procedure and etching technique to define the first insulating layer and the second insulating layer so as to form the contact opening that exposes the first gate and surface of the second type source/drain; forming plural metal patterns which are aligned with the second gate on the second insulating layer; forming a passivation layer on the second insulating layer to cover these metal patterns; forming a photoresist layer on the passivation layer such that this photoresist layer has the first opening and the second opening aligned with the first gate and the second gate; using this photoresist layer as the etching mask to etch back the passivation layer under the first opening, part of the second insulating layer and the passivation layer under the second opening; performing a channel implantation step such that the first type dopant can pass through the first opening to penetrate the first gate and form a channel region inside the substrate under said first gate; and conducting a thermal annealing treatment.
Patent TW-439096-B (TW)
Title: Scanning electron microscope for directly monitoring whether the semiconductor manufacturing process is good or not
Inventor: LIN HAU-JOU
IPC: H01L21/00
Filed: 1999-07-17
Granted: 2001-06-07
Abstract: There is provided a scanning electron microscope for directly monitoring whether the semiconductor manufacturing process is good or not, which uses the reverse difference effect of passive voltage to scan a test key having one end connected to the base and the other end electrically floated for manufacture control and monitor. In accordance with the intensity of the surface electronic signal produced by the surface of the test key, or the image contrast displayed by the intensity of the surface electronic signal, it is determined whether the related manufacturing processes of the test key are good or not.
Patent TW-425604-B (TW)
Title: Complementary bipolar/CMOS epitaxial structure and process
Inventor: DROBNY VLADIMIR F
IPC: H01L21/8228
Filed: 1999-09-02
Granted: 2001-03-11
Abstract: An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850 DEG C. The substrate is heated to a temperature of 1050 DEG C and N+ dopant gas is injected into the carrier gas. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080 DEG C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080 DEG C. Then an N- epitaxial layer is deposited on the second cap layer at 1080 DEG C. The harmful effects of a dip in the dopant concentration profile at the bottoms of the collectors of the NPN transistors are avoided by the process.
Patent TW-457470-B (TW)
Title: Instrument analysis and synthesis device and its learning method
Inventor: SU ALVIN WEN-YU
IPC: G10H1/00
Filed: 1999-09-16
Granted: 2001-10-01
Abstract: This invention provides three kinds of instrument synthesis model, wherein the first is the musical analysis and synthesis model for stringed instruments, the second is the wind instrument analysis and synthesis model, and the third is the low cost instrument synthesis model. It is able to be the training data for the instrument synthesis by the instrument sound that the microphone measures. The well-trained instrument synthesis model is able to be accessed to the playing sound of the real instrument. The calculation amount of proceeding instrument synthesis stage of the low cost instrument synthesis model is very profitable for the sound synthesizer of productive products.
Patent TW-495801-B (TW)
Title: Semiconductor device fabricating method and system for carrying out the same
Inventor: YAMAZAKI HIDEAKI
IPC: H01L21/3205
Filed: 1999-10-26
Granted: 2002-07-21
Abstract: A semiconductor device fabricating method includes a preparatory process that brings a first source gas containing tungsten atoms into contact with a workpiece and that does not bring a second source gas containing nitrogen atoms into contact with the workpiece, and a film forming process that forms a tungsten nitride film on the workpiece by using the first and the second source gases so as to fabricate a semiconductor device. The semiconductor device fabricating method is capable of preventing the tungsten nitride film from peeling off from a layer underlying the same when the tungsten nitride film is subjected to heat treatment.
Patent TW-459199-B (TW)
Title: Method of clearing the BIOS startup password
Inventor: LI YUNG-FU
IPC: G06F9/06
Filed: 1999-11-23
Granted: 2001-10-11
Abstract: This invention is a method of clearing the BIOS startup password. The computer system determines if the user requires checking or setting the password when the BIOS proceeds self-testing. If yes, the computer system checks if the key disk with the motherboard serial number is located in the disk driver or not. If yes, it reads the motherboard serial number of the key disk and compares the motherboard serial number with the original one stored in the computer system. If they are the same, the computer system writes the selected bit value (like 00) into the address that stores the password in the CMOS RAM. Therefore, the user is able to clear the original password without removing the computer housing.
Patent TW-490333-B (TW)
Title: Continuous casting nozzle
Inventor: MUROI TOSHIYUKI
IPC: B22D11/10
Filed: 1999-12-17
Granted: 2002-06-11
Abstract: A continuous casting nozzle for molten steel comprises an inner hole surface layer in contact with molten steel comprising a composition consisting of 15 to 60 wt% of an aggregate consisting of Al2O3 or an aggregate mainly consisting of Al2O3 and having a melting point of 1800 DEG C or higher, and the balance of agalmatolite, and is produced by blending, forming and sintering in an inert atmosphere.
Patent TW-432428-B (TW)
Title: Color cathode ray tube having electrostatic quadrupole lenses
Inventor: UCHIDA GO
IPC: H01J29/50
Filed: 1999-12-18
Granted: 2001-05-01
Abstract: A color cathode ray tube includes third, fourth and fifth electrodes and an anode in its electron beam focusing section. A first-type electrostatic quadrupole lens is formed between first and second members of the fifth electrode for focusing electron beams in one of horizontally and vertically and diffusing the electron beams in the other of horizontally and vertically increasingly with decreasing beam deflection, and a second-type electrostatic quadrupole lens is formed between first and second members of the third electrode for focusing the electron beams in the other of horizontally and vertically and diffusing the electron beams in the one of horizontally and vertically increasingly with the decreasing beam deflection, and an electron lens is formed between the fourth electrode and a first aperture formed in a first surface of the second member of the third electrode adjacent to the fourth electrode, the first surface being on a side of the second member of the third electrode opposite from the fourth electrode, for diffusing the electron beams horizontally and focusing the electron beam vertically increasingly with the decreasing beam deflection.
Patent TW-487591-B (TW)
Title: Dart video game device and shooting result display method of dart video game
Inventor: KUKINO MASAAKI
IPC: A63F13/00
Filed: 2000-02-01
Granted: 2002-05-21
Abstract: The present invention provides a dart video game device, which is used to make game full of reality, so as to make it more funny. In other words, the dart video game device includes: a picture display device for displaying a three-dimensional game scene with enemy players on the monitor screen; and a zooming-in picture display device arranged in the liquid crystal unit of the telescope of the emulating gun for zooming in and displaying a small area of the picture corresponding to the part directed by the emulating gun.
Patent TW-I228116-B (TW)
Title: Monoamine reuptake inhibitors for treatment of CNS disorders
Inventor: ELLIOTT MARK L
IPC: A61P25/24
Filed: 2000-02-17
Granted: 2005-02-21
Abstract: The present invention relates to compounds that are useful exhibit activity as serotonin, norepinephrine and dopamine reuptake inhibitors, and their pharmaceutically acceptable salts, and their use in the treatment of central nervous system and other disorders.
Patent TW-588283-B (TW)
Title: Processing method for changing keyboard command input mode
Inventor: DAI REN-WEN
IPC: G06F9/44
Filed: 2000-02-25
Granted: 2004-05-21
Abstract: A processing method for changing keyboard command input mode, after being loaded with software, makes the auxiliary keypad more intelligent and delicate in return of no enforced request for any of main keyboard or auxiliary keypad being a constant state. Regardless of the state of main keyboard or auxiliary keypad, the auxiliary keypad software will firstly use a status flag to memorize the current state of the main keyboard and auxiliary keypad; when pressing any key of auxiliary keypad, the auxiliary keypad software will determine if the status of the main keyboard existing in the internal flag of auxiliary keypad is identical to the status of auxiliary keypad; if yes, then directly forward the keyboard code of the auxiliary keypad; if no, then forward the num lock code to the computer host, making the status of main keyboard become the same as that of the auxiliary keypad in effort to receive keyboard code; subsequently send out the keyboard code to the host computer, and then forward the num lock code to the host computer to recover the state of main keyboard, while the auxiliary keypad still maintains the original state.
Patent TW-445523-B (TW)
Title: Method for connecting portions within a semiconductive device
Inventor: RADIUS ROLAND F
IPC: H01L21/74
Filed: 2000-03-01
Granted: 2001-07-11
Abstract: A method process for forming a buried implanted layer in a semiconductive substrate that includes a tapered edge portion that extends to the surface of the substrate uses a mask having a tapered edge to define the area of implantation.
Patent TW-472440-B (TW)
Title: Methods and apparatus for noise shaping a mixed signal power output
Inventor: DELANO CARY L
IPC: H03F3/68
Filed: 2000-03-07
Granted: 2002-01-11
Abstract: A signal processing circuit and method for processing an input signal are described. The circuit includes a frequency selective network, an amplification stage, and at least one continuous-time feedback path from the output of the amplification stage to the frequency selective network. The amplification stage includes a switching amplifier and an analog amplifier. Switching circuitry alternately enables the switching and analog amplifiers for processing of the input signal.
Patent TW-436382-B (TW)
Title: Wafer holding head, wafer polishing apparatus, and method for making wafers
Inventor: KOBAYASHI TATSUNORI
IPC: B24B37/30
Filed: 2000-03-09
Granted: 2001-05-28
Abstract: The present invention provides wafer polishing apparatus in which the wafer holding head comprises a diaphragm substantially vertically expanded to the head axis in the head body; a carrier, which is fixed to the diaphragm and provided so as to be able to displace along the head axis direction together with the diaphragm; a retainer ring fixed to the diaphragm in a concentric relation to the carrier; a pressure adjusting mechanism for controlling the pressure of a fluid chamber formed between the diaphragm and the head body; a plurality of carrier torque transfer mechanisms provided between the head body and the carrier for communicating the torque of the head body to the carrier; a plurality of carrier sensors, which is provided at individual carrier torque transfer mechanism, for observing the force along the direction of rotation acting on the wafer; and a processor, which is connected to each carrier sensor, for calculating the force acting on the wafer based on the output from these carrier sensors.
Patent TW-451465-B (TW)
Title: Semiconductor memory device having multi-bank and global data bus
Inventor: SAITOH SATORU
IPC: G11C7/10
Filed: 2000-03-27
Granted: 2001-08-21
Abstract: Connections of global data buses GDB0 and GDB1 to local data buses LDB00 to LDB04 in a bank 1 are reverse to those in a bank 0. That is, the global data bus GDB0 is connected to every other local data bus LDB00, LDB02 and LDB04 including both sides in the bank 0, and to every other local data buses LDB11 and LDB13 excluding both sides in the bank 1, while the global data bus GDB1 is connected to every other local data buses LDB01 and LDB03 excluding both sides in the bank 0, and to every other local data bus LDB10, LDB12 and LDB14 including both sides. Further, bit line patterns obliquely traversing sense amplifier rows are reverse to each other with respect to the banks 0 and 1.
Patent TW-527273-B (TW)
Title: Biaxially oriented polyester film and magnetic recording medium
Inventor: KOBAYASHI IEYASU
IPC: G11B5/73
Filed: 2000-06-09
Granted: 2003-04-11
Abstract: A biaxially oriented polyester film for magnetic recording media, which has (1) a dimensional change between before treated and after treated in a width direction of 0.40% or less when the film is treated at 49 DEG C and 90% RH under a load of 170 (g/12.65 mm) in a longitudinal direction for 72 hours, (2) a crystallinity of 27 to 45%, (3) a temperature expansion coefficient alphat (x 10<-6>/DEG C) and a humidity expansion coefficient alphah (x 10<-6>/%RH) in a width direction of the film which satisfy the relationship (alphat + 2alphah) <= 45, (4) a heat shrinkage factor in a width direction of the film of 0 to 0.7%, and (5) a thickness of 3 to 7 mum. This film is useful particularly for digital data storage of a linear track system, is almost free from an error caused by track dislocation due to a dimensional change in the width of a tape and improves output characteristics.
Patent TW-468325-B (TW)
Title: Integrated system of paging PDA and mobile phone module
Inventor: JUANG CHING-LANG
IPC: H04M11/00
Filed: 2000-06-14
Granted: 2001-12-11
Abstract: The invention is an integrated system of paging PDA and mobile phone module, which can use pager to receive the message from system operator via a data server for real-time broadcasting 24 hours around the clock. With a built-in pager and PDA with mobile phone mechanism for further display, let user to get latest and effective data at any time. Further use the built-in mobile phone system (GSM/DCS) of the PDA to become a full-duplex PDA for voice and data transmission along with broadcasting data reception.
Patent TW-I235380-B (TW)
Title: Output multiplexing implementation for a simultaneous operation flash memory device
Inventor: KURIHARA KAZUHIRO
IPC: G11C16/26
Filed: 2000-07-24
Granted: 2005-07-01
Abstract: A flash memory chip including a synchronization circuit for multiplexed sense amplifier output signal paths is disclosed. The synchronization circuit includes a signal generator, sense amplifiers and an output multiplexer. The arrival of data from the sense amplifiers to the output multiplexer is equalized. Equalization is achieved by adjusting the signal path length, and thereby the resistance and capacitance, of the signal paths from the signal generator to the sense amplifiers which carry the signal to cause the sense amplifiers to transmit their data to the output multiplexers.
Patent TW-447036-B (TW)
Title: Etching method using reactive ions
Inventor: WU JAU-JIUE
IPC: H01L21/306
Filed: 2000-08-17
Granted: 2001-07-21
Abstract: The present invention provides an etching method using reactive ions, comprising the following steps. At the beginning, a semiconductor substrate is provided on which a material layer to be etched is formed. Thereafter, the semiconductor substrate is moved into a reactive ion etching chamber having a first electrode and a second electrode used to load the semiconductor substrate. Next, the material layer is selectively etched, wherein the etching process at least comprises a first phase and a second phase. During the first phase of the etching process, there is a first gap between the first electrode and the second electrode. During the second phase of the etching process, there is a second gap between the first electrode and the second electrode. The present invention discloses that in the different etching phases, the gaps between the electrodes are adjusted so that the etching uniformity for every part of the semiconductor wafer is enhanced by using the same etching steps (conditions) and the performance of the semiconductor device is maintained.
Patent TW-484228-B (TW)
Title: Non-volatile semiconductor memory device and the manufacturing method thereof
Inventor: SHIMIZU KAZUHIRO
IPC: H01L27/115
Filed: 2000-08-29
Granted: 2002-04-21
Abstract: The non-volatile semiconductor device according to the present invention can reduce the deviation of capacitance coupling for the layered gates and achieve the fineness for the memory cells, which is characterized in: forming the device separating insulation film, which is used to separate the device forming area formed on the semiconductor substrate; arranging the memory cells to form a memory cell array in array form, wherein the memory cells comprises: a first gate, which is formed by separating with the first gate insulation film; and, a second gate, which is on the first gate, and formed by separating with the second gate insulation film; the first gate of the memory cells are formed in a pattern with a partially overlapped manner from the device forming area to the device separating insulation film; and, allocating with the protective insulation film on the device separating insulation film adjacent to the first gate and sandwiched with the device forming area; furthermore, the non-volatile semiconductor memory device with the smaller embedded aspect ratio for the device separating insulation film, the smaller device separating space for the memory cells, and provided with excellent machining controllability, low cost, high density, which is to make the charge accumulating layer for the non-volatile semiconductor memory cell as a layered structure with at least two conductive layers, wherein the end surface position for the lowest conductive layer is consistent with the end position of the device separating area, and the upmost conductive layer has the same width as or wider than the bottom conductive layer. Because the first conductive layer is thinner, the embedded aspect ratio is lowered, and the second conductive layer is made with a necessary film thickness to make the capacitance with the control gate as the expected value. The upmost layer may be self-integrated with the device separating area and formed. Moreover, the isotropic etching can be used to widen the width of the upmost layer.
Patent TW-I270730-B (TW)
Title: Liquid crystal display and method of fabricating the same
Inventor: MARUYAMA MUNEO
IPC: G02F1/136
Filed: 2000-08-31
Granted: 2007-01-11
Abstract: Band-shaped data lines are arranged in parallel with each other so as to cross address lines via a gate insulating film formed over the address lines. An upper insulating film is formed over the data lines, and pixel electrodes are formed on the upper insulating film. Storage capacitance section includes common electrode and storage capacitance electrode. The common electrode is extended from the address line of adjacent pixel region. The storage capacitance electrode sandwiches the gate insulating film with the common electrode to store capacitance therebetween. The storage capacitance electrodes and the pixel electrodes are connected to each other via conductive through hole piercing through the upper insulating film. Besides, the storage capacitance electrode, source electrode of the thin film transistor section and a wiring connecting them are integrally formed of the same metal films.
Patent TW-466712-B (TW)
Title: Manufacturing method of miniaturized non-volatile semiconductor memory device with dual-sided erasing electrode
Inventor: WU CHING-YUAN
IPC: H01L21/8247
Filed: 2000-10-17
Granted: 2001-12-01
Abstract: The present invention provides a high-density and high-speed non-volatile semiconductor memory device structure capable of being applied in large storage, and its manufacturing method, wherein there are disclosed a method capable of simultaneously manufacturing field oxide insulation and floating gate with high coupling ratio and dual-sided erasing electrode, and a method capable of manufacturing miniaturized split-gate non-volatile semiconductor memory device. The present invention utilizes a special multi-layer oxide mask structure to form a field oxide isolation, wherein the influence of the field ion implantation invasion and the bird's beak extension to the device area with minimum line width can be eliminated, and the smaller isolation area combined with the dual-sided erasing electrode can be used to manufacture the miniaturized split-gate non-volatile semiconductor memory device of the present invention. The present manufacturing method of miniaturized split-gate non-volatile semiconductor memory device is different from the conventional method, and is not restricted by the photo etching line, wherein the channel lengths of the control gate and the floating gate can be respectively controlled by using pad layer formation method, so that the respective channel length is much smaller the minimum line width set by the manufacture technique. Because the whole channel length of the present miniaturized split-gate non-volatile semiconductor memory device can be smaller than the minimum line width set by the manufacture technique, the present invention is able to eliminate the major drawbacks of the conventional miniaturized split-gate non-volatile semiconductor memory device. Furthermore, the present invention utilizes the self-aligned silicide technique to manufacture the gate/control gate, source/common buried source and drain/common buried drain of the memory device or other device, so as to decrease the resistance of the contact point and the internal connection wire, and utilizes the technique of forming silicon nitride pad layer on the device side wall to obtain a self-aligned contact, thereby further the pitch between the contact point and the device. Accordingly, the present invention is able to manufacture an ultra small split-gate memory cell, and thus manufacture high-density and high-speed non-volatile semiconductor memory system required by the large storage application.