Patent GB-1356270-A (GB)
Title: Digital data handling system
IPC: G06F13/42
Filed: 1971-09-25
Abstract: 1356270 I/O module control INTERNATIONAL BUSINESS MACHINES CORP 25 Sept 1971 44777/71 Heading G4A A digital data processing system includes a central controller connected to several peripheral units via respective input/output control modules which are adapted to respond to an instruction from the controller determining the timing of a subsequent input or output operation on their associated peripheral.  General.-The controller may be any stored program processor and the I/O modules are connected to it in the manner described in Specification 1,356,269 which is referred to. Data from a peripheral is received at the associated input/output module in parallel and is converted to serial by three shift registers 8. The data may be immediately transmitted via line 13 and bus 11 or lodged in a buffer 14 also consisting of three shift registers. Data from the controller is received by converter 10 where it is converted to parallel. The module comprises three sense units 18-20, a timer 16, a sequence unit 27, and an interface control 29 all of which are described. A peripheral may be served by more than one module. Sense units.-The sense units, see Fig. 4 (not shown) include an input register and associated decoder for data received from the associated peripheral, each of the three units handling one byte of a three byte word. Two registers are connected to a masking logic circuit arranged to detect specific changes in the data in the sense input register, one register being loaded with l's indicating that changes in the corresponding bits in the input register from 1-0 are to be signalled, the other register being used to detect 0-1 changes. The unit is adapted to generate high or low priority interrupt signals when a required change is detected in response to an instruction decoded by the sequence unit. The sense units in more than one module may be interconnected to handle larger words. Sequence unit.-The sequence unit, see Fig. 6 (not shown), includes an eight bit instruction register connected to control a set of gates via a logic network. The gates issue signals to actuate a particular sense unit, activate buffer 14, activate converter 10, and generally to issue operating instruction to the units within the module. Timer.-The timer, see Fig. 3 (not shown), includes a frequency divider controlled in response to a portion of an instruction word stored in a register and receiving clock pulses. The divider feeds a counter whose output signals are passed to a comparator together with signals from a pair of registers loaded by the controller. The comparator output, which indicates that the counter contents are equal to the contents of one of the registers, is passed to a control circuit which, in response to the remainder of the stored instruction, generates high or low priority interrupt signals or control signals. Interface control unit.-The interface control unit, see Fig. 5 (not shown), comprises an instruction register, a data register, and an identity register all receiving data from the data bus 11. Two status registers deliver data to the bus 11. Control signals 40a are generated in response to the instruction register contents and low and high priority interrupt signals are generated by two OR gates having inputs connected to the high and low priority interrupt outputs of the three sense units, the timer, and the sequence unit. Further details.-The interrupt signals issued by the interface control units are handled as is described in Specification 1,356,269. The controller may issue one of three different types of message. In the first, unit 29 is caused to carry out some action not involving data transfer to and from the module, e.g. start timer. In the second, the unit 29 is informed of the location in the module where input data is to be routed, e.g. "select", where data on bus 11 is compared with module identity data for module addressing, or "immediate output", where data on bus 11 is routed via buffer 10, to latches 9. In the third, the instruction specifies the register whose contents are to be transferred to the central controller, e.g. "read input buffer-byte". Within these three types various instructions are possible several of which are enumerated, e.g. "immediate input or output", immediate "set" or "reset" where the data portion, in this case byte 1, is used as a mask, and various timing signals. In the last case three modes are possible, viz. where the receiver can accept data faster than it can be transmitted, and vice versa, and where the speeds are approximately matched. In the first case the transmitter provides a signal indicating a valid transmission and a different signal during the changeover between characters, in the second the receiver issues a signal instructing the transmitter when to present the next character, and in the third case both these procedures are used together. Deferred I/O operation are performed on the occurrence of a signal either from the peripheral device or from the module timers. The peripheral units may be typewriters, printers, tape units &c., a deferred I/O operation being used for example to energize a selected print hammer at a particular time for a particular period.