Patent TW-201714281-A (TW)
Title: Five-transistor static random access memory capable of effectively increasing the standby performance for the single-port SRAM and effectively reducing the half-selected cell disturbance during a reading operation
Inventor: SHIAU MING-CHUEN
IPC: H01L27/11
Filed: 2015-10-07
Abstract: The present invention provides a five-transistor (5T) static random access memory, which comprises a memory array, a plurality of control circuits (2), a plurality of pre-charge circuits (3), a standby starting circuit (4) and a plurality of word line voltage level conversion circuits (5). The memory array is comprised of a plurality of rows of memory cells and a plurality of columns of memory cells. Each row of memory cells is provided with one control circuit and one word line voltage level conversion circuit (5), and each memory cell (1) includes a first inverter (comprised of a first PMOS transistor P11 and a first NMOS transistor N11), a second inverter (comprised of a second PMOS transistor P12 and a second NMOS transistor N12) and an access transistor (comprised of a third NMOS transistor N13). Each control unit (2) is connected to the source of the first NMOS transistor (N11) of each memory cell in the corresponding row of memory cells and the source of the second NMOS transistor (N12), so as to control the source voltage of the first NMOS transistor (N11) and the source voltage of the second NMOS transistor (N12) in response to different operating modes. In the first stage of a reading mode, the source of the first NMOS transistor (N11) close to the bit line (BL) is changed from the original ground voltage to a voltage lower than the ground voltage. At this moment, the first NMOS transistor (N11) and the second NMOS transistor (N12) with smaller channel aspect ratio can be configured to complete the reading operation. Furthermore, in reading a logic 0, the second NMOS transistor (N12) distant from the bit line (BL) will not be turned on instantly to hinder the reading operation. In the second stage of the reading mode, the source of the first NMOS transistor (N11) is changed from the voltage lower than the ground voltage back to the ground voltage, so as to reduce unnecessary power consumption. In a writing mode, the source of the first NMOS transistor (N11) close to the bit line (BL) is maintained at the original ground voltage. Because there are configured with the first NMOS transistor (N11) and the second NMOS transistor (N12) with smaller channel aspect ratio, this invention can effectively avoid the rather problem of writing logic 1 to the prior single-port SRAM with a single bit line. In a standby mode, the current leakage can be effectively reduced and, in a maintaining mode, the original electrical characteristic can be maintained. Furthermore, the design of the standby starting circuit (4)enables to effectively facilitate the single-port SRAM to quickly enter the standby mode, thereby effectively increasing the standby performance for the single-port SRAM. In addition, the design of the plurality of word line voltage level conversion circuits (5) enables to increase the turn-on resistance of the third NMOS transistor (N13) in the reading mode, thereby effectively reducing the half-selected cell disturbance during a reading operation.