Patent GB-1444783-A (GB)
IPC: G06F13/00
Filed: 1973-09-27
Abstract: 1444783 Data transfer systems RCA CORPORATION 27 Sept 1973 [4 Oct 19721 45271/73 Heading G4A A communications channel 34 (Fig. 2) over which data is sent to and from buffers obtains line scan words by stealing memory cycles of a main memory 26, each scan word including the address of a buffer to determine its service time, individual data unit transfers between the memory and channel 34 being accomplished by interrupting the program currently being executed by processor 20 and switching to a data transfer routine. Transfer between input/ output devices in the memory is effected using a selector channel which transfers data by memory cycle stealing between cycles used by the processor in the execution of its current program, the program being interrupted when a predetermined quantity of data has been transferred to execute a routine to determine that a successful termination of the transfer request has been accomplished. When a communication channel interrupt request is received the high order address bits of the new program are fed from interrupt network (22, Fig. 3, not shown) to the address register of a scratch pad memory (SPM) the low order bits being fed from an instruction register (IR) receiving its input from the main memory. Interrupt logic (Fig. 4).-An interrupt pending register IPR has four stages 2<SP>0</SP>-2<SP>3</SP>, the 2<SP>3</SP> stage being reserved for highest priority inter rupts (e.g. for power failure) from the processor. The middle two stages are reserved for the communication channel interrupts and the lower stage 2‹ is reserved for the processor. Priority logic 50 gives a signal to one of four AND gates 62<SP>1</SP> corresponding to the highest set stage. A first stage interrupts initiated register IIR is similarly connected to priority logic 52 to give an output corresponding to the highest interrupt which has been started to an address generator 56 which supplies address signals to the scratch pad memory. The outputs of the logic circuit 50, 52 are compared to give a signal HPIP if a pending interrupt is of higher priority than the program currently in progress. This results in a signal on line 60 priming AND gate 60<SP>1</SP> so that the storage of the register IIR assocciated with the interrupt in progress is reset and the signal on line 62 is then fed to gate 62<SP>1</SP> to cause the highest priority interrupt signal to set the associated stage of the register IIR to cause a new address to be read out. Communications channel (Fig. 5, not shown). -A control unit (73) provides five transfer enabling signals, the first of which permits an address in the first register (71) to be supplied to the main memory address register to read out a line scan word. This includes an address portion of the next scan word which is read via a gate (83) into a second address register (70) and a control portion which is fed to a control register (72). The second signal permits the address in register 71 to be fed to the buffers to activate a selected buffer to for example transfer data to a data register (74) in which case an interrupt is effected to request the processor to receive the data. The third signal permits, during servicing of an even numbered buffer a look-ahead at the next odd numbered buffer to be addressed to see if it needs service in which case during the fifth signal gates are enabled for the transfer of information, the fourth signal performing look-ahead when an odd numbered devices is currently being addressed.