Patent GB-1011873-A (GB)
Title: Improvements in and relating to phase-modulation of a carrier wave
IPC: H04L27/20
Filed: 1962-06-15
Abstract: 1,011,873. Phase-shift data transmission systems. WESTERN ELECTRIC CO. Inc. June 15, 1962 [June 28, 1961], No. 23043/62. Headings H4L and H4P. Relates to apparatus for incrementally phase-shifting a carrier wave in accordance with a binary data signal in a pulse transmission system. The incoming serial binary signal is arranged in pairs of binary digits (dibits) each dibit consisting of two successive digits and the four possible combinations 00, 01, 11 and 10 are represented by phase-shifts of 1, 3, 5 or 7 times 45 degrees. Alternatively these combinations may represent two independent but synchronized data channels. The phase of the carrier for a particular dibit is shifted a corresponding predetermined increment with respect to the phase transmitted for the previous dibit. Two carrier sources are provided which differ in phase by an odd multiple of 45 degrees and are operated upon alternately by successive dibits, the outputs being combined to form a single modulated signal. As shown in Fig. 2, digital signals E are supplied to an AND gate 31 controlled by pulses D derived from timing circuits 15 under the control of a master oscillator 14. An additional AND gate 32 may be provided which is controlled by a " clear-tosend " signal. A binary counter 33 is operated by each " 1 " in the input signal F but when it reaches a count of two, i.e. at the end of each dibit period, is reset by a pulse from monostable device 34. The output H of the counter 33 is supplied via an AND gate 36 controlled by pulses D and a dibit timing wave supplied through inverter 35 to an OR gate 38 controlling a further counter 39. Thus the output I indicates an odd count on counter 33 for a paired mark and space but for double marking or double spacing bits the counter 33 returns to or remains in its reset condition. The output F is also supplied to an AND gate 37 controlled by the dibit timing wave before inversion and an output G is produced every time the first bit of a dibit is a " 1." The combined outputs on leads I and G represent a reflected code since the four dibits 00, 01, 10, 11 are converted to 00, 01, 11, 10. Phase-shifting is controlled by three binary counters 39, 40, 41 in series, counts of 1, 3, 5 and 7 producing phase-shifts of 45, 135, 225 and 315 degrees corresponding to the four possible dibits. Instead of producing 3, 5 or 7 pulses during a dibit period control pulses are applied to other than the initial stages of the counter chain. Thus a pulse applied to the second stage is equivalent to two pulses applied to the first stage and a pulse applied to the third stage is equivalent to four pulses applied to the first stage. By suitable combinations of single pulses applied to the respective stages the correct counts can be obtained. It is found that a pulse is required for the input to the first stage for all the dibits, for the second stage when the two bits in a dibit differ, and for the third stage if the first bit in a dibit is a " 1." Conversion to the reflected code reduces the phase logic requirements to two counting stages as the first bit corresponds to the third counting stage input and the second bit of a dibit corresponds to the second stage input and an input is always required for the first stage. The first counter 41 provides through monostable device 42 an output pulse J at the beginning of every other dibit period. The OR gate 38 passes a pulse every other dibit period and also pulses I when they are present to the counter 39. The output L from counter 39 is supplied to counter 40 which also receives pulses G from AND gate 37. The carrier wave is generated in two separate channels controlled by the master oscillator and a common counter stage 16 which produces oppositely phased output N<SP>1</SP> and N at 7200 c/s. forming inputs to the A and B channel counting chains respectively. Channel A includes counters 50, 51 and channel B counters 52, 53, the two counting chains always being out of phase by an odd multiple of 45 degrees. Reference setting signals J and K are supplied from monostable devices-42 and 43 respectively, placing counter 50 in the set position and counter 51 in the reset condition, both counters 52, 53 in the set position, and counter 16 in the reset position. The pulses of set J occur every odd dibit period and those of set K occur every even dibit period so that while one channel is being reset the other is operating under the control of the master oscillator. Immediately after each reference setting operation an appropriate pair of AND gates 46, 48 or 47, 49 is enabled to transfer the outputs of the counters 39, 40 to the corresponding channel counters. The arrangement is such that a pulse applied to the second stage of the respective channel counter effects a 90 degrees phase change, a pulse applied to the last stage effects a 180 degrees shift and a pulse applied to these two stages simultaneously effects a 270 degrees phase shift. The phasemodulated output Q of the channel A is amplitude modulated at 25 by a " raised cosine " wave S with a period equal to half the dibit period derived from the 600 c/s. counter 41 via a low pass filter 24. A similar wave U in antiphase to wave S amplitude modulates the output R and after passing through respective low pass filters 27, 28 the signals T, V are combined at 29 and the resultant phase modulated wave W, which contains no abrupt phase transitions, is passed to the output line W. Specification 981,400 is referred to.