Patent GB-1408180-A (GB)
Title: Semiconductor device manufacture
IPC: H01L29/78
Filed: 1972-11-17
Abstract: 1408180 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 17 Nov 1972 [20 Nov 1971] 53203/72 Heading H1K A tetrode FET having two insulated gate electrodes 9, 10 and an intermediate island 14 with source and drain zones 12, 13 all with electrical connections is equivalent to a combination of two transistors each having a gate electrode (Fig. 2). In manufacture a semi-conductor body 1 having a P-type silicon region 2 is oxidized to a masked insulant pattern 3 of SiO 2  inset into the silicon to surround a surface region 4, and the masking medium is removed. A first insulant layer 6 of SiO 2  is thermally oxidized thereon and covered with a second insulant layer 7 of Si 3 N 4  deposited thermally from an atmosphere of NH 3  + SiH 4 . (Fig. 4, not shown) and covered with a polycrystal silicon layer by decomposition of a gaseous silicon compound and diffusion doped with phosphorus (Fig. 5, not shown). Gate electrodes 9, 10 are formed by photolithographic etching of the polycrystal layer (Fig. 6) which also forms interconnections (not shown). Electrodes 9, 10 are thermally oxidized in moist O 2  into an insulant oxide layer 11 and the superfluous areas of layers 6, 7 are etched off; phosphorus being indiffused to the exposed silicon surface to form N-type source and drain zones 12, 13 and island 14 between the electrodes, with lateral indiffusion beneath layers 6, 7 to form PN junctions underlying 15, 16, 17 with surface intersection collinear with the edges of electrodes 9, 10 (Fig. 9, not shown); a layer of phosphosilicate glass being formed on the exposed silicon surface. Contact windows 19, 20, 21 to zones 12, 13, 14 are etched over a photoresist mask leaving oxide layers 3, 11 unaltered (Fig. 11) and contact windows 24, 25 (Fig. 1) are etched over a photoresist mask in oxide layer 11, and aluminium electrodes 26, 27 for source and drain zones 12, 13; 28 for island 14, and 24, 25 for gates 9, 10 are vapour deposited and etched. Alternatively prior to removal of layers 6, 7 dopant may be implanted by ionic bombardment through the layers to form zones 12, 13, 14 using pattern 3 and layers 11 as masks, and etching the zones to remove layers 6, 7. The semi-conductor may be other than silicon, and pattern 3 may be a nitride or other insulant compound of the substrate, and the conductive layer 8 may be of aluminium or zirconium with insulant layer 11 formed of their oxides. The polycrystalline silicon may be acceptor doped to obtain a required threshold voltage. A part of the oxide layer 6 may be etched out to assist in aligning the PN junction diffused below the layer with the edge of the gate electrode 9 (Fig. 12, not shown). The source zone may surround the drain zone. The P-type region may be epitaxially deposited on a substrate of opposite conductivity type and the source and drain zones insulant pattern 3 may extend through its full thickness (Fig. 13, not shown). Also the IGFET may be provided in a region bounded by an insulant pocket forming a PN junction with the adjacent substrate in an integrated monolithic circuit. A N-type substrate 41 (Fig. 17) is locally oxidized to an inset insulant pattern 3 and boron is indiffused or ion implanted over a mask to define P-type pocket 42. Successive SiO 2 , Si 3 N 4  and polycrystal silicon layers 6, 7, 8 are deposited successively (Fig. 15, not shown) and etched to form gate electrodes and interconnections, and then donor or acceptor doped. Electrodes 8 are oxidized at 11 and the nitride and oxide layers are etched off for diffusion or implantation of N zones 43, 44 in the N-channel transistor, while oxide layer 6 is etched for the formation of P-type source and drain zones 45, 46 in the P-channel transistor, e.g. by boron diffusion. Metal layers 47, 48, 49, 50 are applied to contact the transistors. Bipolar transistors can be formed in the same substrate and interconnected over metal layers or layers of polycrystalline doped silicon.