Patent GB-1314394-A (GB)
Title: Electronic computer
IPC: G06F12/02
Filed: 1970-06-19
Abstract: 1314394 Digital computer; shift register ING C OLIVETTI & C SpA 19 June 1970 [2 June 1969] 58583/72 Divided out of 1314393 Headings G4A and G4C A digital computer has a cyclic serial memory 11 containing instructions on a multi-track tape loop and has a random access magnetic core memory 19 containing data to be operated on. Consecutively accessed instructions are spaced on the tape by a distance such that the previous instruction has been performed, in general, before the next instruction reaches the read head so that the tape can, in most cases, be run non- stop in accessing instructions. The instructions are transferred to instruction register 13 which holds four 4-bit characters, the first character being a general operation code which determines the interpretation of the remaining characters. Each instruction has an associated address, each address on the tape being compared in comparator 39 with an address in an 8-bit register in memory 19, the instruction having the required address being read out when coincidence occurs if the previous instruction has been completed. The address in memory 19 is normally incremented by 1 using an adder 25. Addition or subtraction. - The second instruction character defines an arithmetical operation while the third and fourth define registers in memory 19. In this case operations are performed on the contents of an I/O register 23 and a register Ra, the contents being compared to see which is the larger if a subtraction is to take place so that the smaller number is subtracted from the larger. The digits are examined a bit at a time under control of counter 51 which selects a row in the memory, counter 55 which selects a column and counter 57 which selects the four bits of each character. In a first memory cycle a bit from the I/O register is transferred to a flip-flop in the arithmetic unit, in a second cycle the corresponding bit from Ra is transferred to a second flip-flop. The bits are added or subtracted and returned to Ra during the second half of the second cycle. Multiplication is performed between the contents of I/O register and register Ra addressed by the third character and the product is stored in Rb addressed by the fourth character. The contents of I/O 23 are added to Rb a number of times specified by the least significant digit of Ra, Ra and Rb are shifted and the process repeated until a counter shows that the least significant digit of Rb is in the least significant digit position. Shifting or circulating is performed (Fig. 6) by shifting the contents of the least significant character in a register to a one character store 71 which previously has been set to zero. The shift occurs during the first half of each memory cycle and during the second half the previous contents of 71 are shifted to the character place just read out. The most significant digit P is then read into 71 and replaced with the least significant and successively characters are then replaced with their next most significant character. Matrix memory 19 has a plurality of columns each containing 8 4-bit characters, the columns being addressed by a counter 55, the characters in each column being selected by a counter 51. The columns contain 8 character words and have portions forming the I/O register, an indirect address register 29 used when the third or fourth address characters are zero to replace the third or fourth address characters and a service area. The keyboard enters characters in the store 19, and communicates with a printer or a tape punch.