baber/WOPTO huggingface dataset:
Patent JP-H04310150-A (JP)
Title: Address generator
Inventor: YAMASHITA NORIFUMI
IPC: G06F12/02
Filed: 1991-04-08
Abstract: PURPOSE:To provide the address generator which generates addresses so as to utilize an address memory part efficiently. CONSTITUTION:The address generator consists of a microprogram counter 1 generating addresses, an offset generator 2 outputting offset numbers up to a branch transfer destination address corresponding to the condition from the address, and an address adder 3 which generates the next address by adding the output of the microprogram counter 1 and the offset generator 2. Thus, associated with the condition branch processing, the memory which is not to be used effectively is not generated in the address memory part so that the utility efficiency of the address memory part can be improved.
Patent JP-S62260243-A (JP)
Title: Memory bank setting system
Inventor: MINAMINO NOBUYUKI
IPC: G06F12/06
Filed: 1986-05-07
Abstract: PURPOSE:To automatically set the bank value to each memory block by using a means to set the bank value given from a CPU. CONSTITUTION:A CPU1 is connected to each memory block 2 in a daisy chain via a control signal line 4. In a system rise mode a memory block circuit 3 delivers a setting request signal 100 of its own memory block to the CPU1 via the line 4. The CPU1 receives the signal 100 and outputs a request reception signal 200 to the block 2 that delivered the signal 100 and at the same time delivers the bank value to to a memory bus 5. The circuit 3 sets said bank value as the read bank value when the signal 200 is supplied. Furthermore the circuit 3 forms a daisy chain therefore, intermediates the signal 100 of another memory block.
Patent JP-S582703-A (JP)
Inventor: JIRI FUORUMANEKU
IPC: G01C5/04
Filed: 1982-06-17
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H02295996-A (JP)
Title: Preparation of glucosaminyl-epi-podophyllotoxin derivative
Inventor: TSUENETSUKU KOORARU
IPC: A61K31/7042
Filed: 1990-04-20
Abstract: PURPOSE: To obtain a compound useful as an anticancer drug simply in a high yield by a process in which an α-OH type glucosamine derivative is reacted with a specified podophyllotoxin derivative, and the product is treated specifically.  
     CONSTITUTION: First, an α-OH type glucosamine derivative of formula I (R 1 , R 3  are each an acyl protective group; R 2  is H; A is a 1-4C alkyl) is reacted with a podophyllotoxin derivative of formula II (R 4  is CH 3 , a benzyloxycarbonyl protective group) at -50 to 20°C in the presence of a promotor and an anhydrous organic solvent to obtain a compound of formula III. Next, the benzyloxycarbonyl protective group is removed by hydrocracking with a palladium catalyst in an organic solvent, and acetyl protective group and a halogenated acetyl protective group are removed by zinc dichloride and a basic anion exchange resin, respectively, and free amino group is reacted with a 1-4C aldehyde under reductive alkylation conditions in the presence of hydride to obtain the objective compound in which R 1  is H; R 2 , R 3  are each H, a 1-4C alkyl; R 4  is H. 
     COPYRIGHT: (C)1990,JPO
Patent JP-S60246654-A (JP)
Title: Three-dimensional integrated circuit
Inventor: SEKIKAWA TOSHIHIRO
IPC: H01L21/822
Filed: 1984-05-22
Abstract: PURPOSE:To simplify the construction of interlayer coupling means for transferring signals between first and second active layers and to remarkably simplify the process of providing an interlayer wiring in the manufacturing processes, by electrically coupling first and second active layers through electrostatic capacity. CONSTITUTION:Interlayer coupling electrodes ILE1 and ILE2 are arranged closely to be opposed to each other near field effect transistors FET1 and FET2. The electrodes ILE1 and ILE2 are formed of semiconductor material having an impurity diffused in high density, of metallic material, or of metal silicide. A thin layer of insulating material ILI is interposed between these electrodes, the insulating material consisting of an oxide such as SiO2, silicon nitride or semi-insulating semiconductor crystals of which upper and lower active layers AL2 and AL1 are formed. The electrodes ILE1, ILE2 and the insulating material ILI thus constitute an interlayer coupling having electrostatic capacity. Since there is no need of providing ohmic contact, the manufacturing process can be simplified remarkably and the yield can be improved substantially.
Patent JP-S5437483-A (JP)
Title: Electronic device of electronic watch
Inventor: ODAGIRI HIROYUKI
IPC: H01L21/8238
Filed: 1977-08-29
Abstract: PURPOSE: To obtain the crossed Al wiring which is free from the voltage drop by forming the mutual connection between N-and p-channel MOS transistors formed on the Si substrate plus other necessary wirings simultaneously with the singleand plural-insulation layers. 
     COPYRIGHT: (C)1979,JPO&Japio
Patent JP-S588408-A (JP)
Title: Large pneumatic rubber tire for bad road
Inventor: KOUNO MITSUJI
IPC: B60C11/117
Filed: 1981-07-02
Abstract: PURPOSE:To prevent the local abnormal temperature rise of a tire for a construction vehicle or the like, by providing auxiliary grooves oblique to main grooves, to divide the tread into a central and lateral regions to make the temperature distribution of the tire uniform. CONSTITUTION:Auxiliary grooves 2 are obliquely provided on the tread T of a tire so that the auxiliary grooves 2 are continuous to main grooves 1 adjacent to each other in the circumferential direction of the tire and the obliqueness of the auxiliary grooves to the circumferential center line M-M is opposite to that of the main grooves to the line. The tread T is divided into a central region W1 and two lateral regions W2 by the main and the auxiliary grooves 1, 2 so that the width of the area having the grooves is relatively large and the central and the lateral regions are further divided into central and lateral blocks 3, 4 of almost the same form.
Patent JP-H01273433-A (JP)
Title: On-vehicle audio equipment
Inventor: SAKAKIBARA MANABU
IPC: B60R11/02
Filed: 1988-04-26
Abstract: PURPOSE:To eliminate a sense of disorder given to passengers by inhibiting a voice output from a speaker receiving a difference signal forcibly when the reception state of a radio wave is deteriorated. CONSTITUTION:A control circuit 27 receives a detection signal of a reception state detection circuit 25 and when the reception state (electric field strength E) of a radio wave is deteriorated and to be equal to or less than the setting value K (E<=K), a couple of changeover contacts 20a, 20b of a switching circuit 20 are thrown to the closed position. Then a difference signal of left/right channel signals from power amplifiers 18a, 18b is inhibited from being given to left/right pillow speakers 11a, 11b and the left/right channel signals are inputted as conventionally. Thus, while the electric field strength E is fluctuated in the vicinity of E=K, since the input of the difference signal to the pillow speakers 11a, 11b is inhibited forcibly, the intermittent output of the voice is prevented and the sense of disorder to passengers is avoided.
Patent JP-S59228441-A (JP)
Title: Clock forming circuit of pcm recording and reproducing device
Inventor: ITOI TETSUSHI
IPC: H03M13/00
Filed: 1983-06-10
Abstract: PURPOSE:To ensure the operation when input/output clocks are incoming at the same time by giving priority to the input and output clocks in a PCM recording and reproducing device using an RAM. CONSTITUTION:An input address generating circuit 4 and an input address control circuit 5 receive an input clock, decides an input address of the RAM1, and on the other hand, an output address generating circuit 6 and an output address control circuit 7 receive an output clock and decides an output address. A clock forming circuit 8 is a circuit so as to transmit an address signal from the control circuits 5, 7 to an address bus 2 and forms a control signal B7 and its inverting signal. This clock forming circuit 8 consists of four counters, two flip-flops and two NAND circuits to decide the priority among input and output addresses. That is, the control signal B7 for the output address is generated at a half period when an input clock signal incoming at first in intermediate 6-period of each word of the output clock goes to logical 1.
Patent JP-S586114-A (JP)
Title: Winding device for demagnetizing coil
Inventor: KATAGIRI HIROSHI
IPC: B65H81/00
Filed: 1981-07-04
Abstract: PURPOSE:To increase tightness and to exactly control the number of windings by a method wherein an insulating wire is held while pressing by an auxiliary roller having a projected line surface engaged with the recessed groove of a driving roller and the insulating wire is fed into a tube. CONSTITUTION:In a winding device installed with a counter device on a supporting base 1, an insulating wire 9 is held between the recessed groove surface 7 of a driving roller 4 and the projected line surface 8 of an auxiliary roller 5 and the auxiliary roller 5 is pressed to the driving roller 4 by an air cylinder 6 to feed out the insulating wire 9 by the rotation of the driving roller 4. A counter device consisting of a counter wheel 11 and an auxiliary wheel 12 pressed by an air cylinder 13 is installed between the rollers 4.5 and a line feeding device 2 and the number of windings is measured by converting the rotation of the counter wheel 11 into pulses while maintaining the insulating wire 9 at fixed tension strength and the number of windings controlled at the predetermined value.
Patent JP-S61259708-A (JP)
Inventor: RIN II ATSUPURUGEITO
IPC: B01D63/02
Filed: 1986-05-08
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S61260084-A (JP)
Inventor: JIEEMUZU ROBAATO FUINO
IPC: C07D311/00
Filed: 1986-05-08
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H043434-A (JP)
Title: Field effect transistor and manufacture thereof
Inventor: NODA MINORU
IPC: H01L29/423
Filed: 1990-04-19
Abstract: PURPOSE:To obtain a field effect transistor with an asymmetrical gate FET which can be formed with improved accuracy and reproducibility by making a diffusion layer for drain to be at a shallower concentration than a diffusion layer for source and separating only the diffusion layer for drain from a gate. CONSTITUTION:After an Si ion is implanted onto a GaAs substrate 1 or AlN, SiN, SiON, or SiO, etc., is provided on a substrate surface by approximately 100-1000Angstrom , the Si ion is implanted through it, thus forming an n<-> channel region 3. After that, a heat-resistant metal such as tungsten silicide is provided on an entire surface of the substrate, thus machining into a gate shape 2. Then, an SiON 6 is deposited on the surface of the substrate 1 and on the surface of the heat-resistant gate 2 and then a resist pattern 7 with an opening 8 at a source region side is formed on it. Then, an insulation film 6 is eliminated by etching. After that, after eliminating the resist 7, a resist pattern 7' is formed, Si, ion is implanted with it as a mask, thus forming a shallow and low- concentration n<+> layer for drain 5 and a deep and high-concentration n<+> layer for source 4. Then, a source electrode 41 and a drain electrode 51 are formed by eliminating the resist 7' and the insulation film 6.
Patent JP-S58221145-A (JP)
Title: Cleaning device of sampling nozzle of automatic analyzing apparatus of electrolyte
Inventor: MATSUDA TAKEHIDE
IPC: G01N35/10
Filed: 1982-06-17
Abstract: PURPOSE:To wash surely the outer circumference face of a sampling nozzle with simple constitution, by providing a cleaning roll which is in close contact with both sides at right angles to the moving direction of a sampling nozzle and rotates in the same direction as the moving direction of the nozzle. CONSTITUTION:Cleaning rolls 9 made of a cylindrical elastic moisture-absorbing material 12 and a water-absorbing filter paper 13 enclosing the outer circumference part are provided in close contact with both sides at right angle to the moving direction of a sampling nozzle 6 among a standard solution vessel, a vessel to be inspected and a testing vessel. This rolls 9 are rotated in the same direction as the moving direction of the nozzle 6. By this simple constitution, the body to be inspected which is stuck to the outer circumference face of the nozzle 6 is washed surely thus an accurate analytical measurement is performed.
Patent JP-S5227634-A (JP)
Title: Focus plate
Inventor: ISE KATSUHIRO
IPC: G03B13/24
Filed: 1975-08-27
Abstract: PURPOSE: To provide a focus plate which has a little dim or obscure field when a diaphragm is actuated to the full by providing irregular indentations on a gimlet, anger or an inclined plane so as to give a bright defocus image nearly equal to the dimness or obscurity shown in the film. 
     COPYRIGHT: (C)1977,JPO&Japio
Patent JP-H11296261-A (JP)
Title: Connection confirmation device for connector
Inventor: OISHI SHIGEO
IPC: G06F3/00
Filed: 1998-04-15
Abstract: PROBLEM TO BE SOLVED: To easily detect a defect in contacting when a printed circuit board is inserted into a mother board/back panel by switching the connection of a signal line connecting the printed circuit board and mother board/back panel with a switch. SOLUTION: In normal operation mode, switch parts 211 and 224 have switches A set on and switches B set off and in connection confirmation mode, the said switches A are set off and the switches B are set off. Consequently, the output of a detection signal generation part 221 is connected to a signal line (a) by the switch part 224, the switch part 211 connects the signal line (a) to other signal lines (b) to (e), and the switch part 224 connects the signal lines (b) to (e) to a signal detection part 222. Namely, the output signal of the detection signal generation part 221 is distributed to the signal lines (b) to (e) through the signal line (8a) and inputted to the signal detection part 222. The connection between the printed circuit board 21 and mother board 22 can be verified by confirming this input signal.
Patent JP-H04333189-A (JP)
Title: Information equipment
Inventor: NISHIMURA AKIMASA
IPC: G06K17/00
Filed: 1991-05-09
Abstract: PURPOSE:To avoid the failure of data transmission by providing a circuit in an information equipment mainbody, which recognizes the connection of two contact pairs at both ends among a lot of contact pairs for connecting a memory card with the information equipment mainbody. CONSTITUTION:When the pairs of the contacts 12a and 20a and 12b and 20b at the both ends among the connection contacts of a camera mainbody 10 and the memory card 12 are connected, a confirmation signal from a card fitting confirmation signal generating circuit inside the memory card 12 is impressed on a control circuit 22 and the control circuit 22 corresponds to this so as to permit an image pick-up element 16 and a process circuit 18 to be working possible. In the mean time, the confirmation signal from the card fitting confirmation signal generating circuit of the memory card 12 is not supplied to the control circuit 22 when the memory card 12 is not appropriately fitted to the camera mainbody. Therefore, the connection defective of the memory card 12 is recognized and the control circuit 22 prohibits photographing by prohibiting the working of the image pick-up element 16 and/or the process circuit 18, for example, or gives specified warning.
Patent JP-H043535-A (JP)
Title: Method for preventing interference due to same frequency
Inventor: ICHITSUBO SHINICHI
IPC: H04B7/26
Filed: 1990-04-19
Abstract: PURPOSE:To eliminate interference due to a disturbing wave by obtaining a reception level ratio between a reception level of a communication channel and a reception level of a control channel at a mobile station and allowing a base station making communication to convert the communication channel frequency when the ratio is less than a prescribed value. CONSTITUTION:A channel control section 42 receives a reception level of a desired wave f1 from a communication level detection section 40 and receives a reception level of control channel frequencies fb, fc of an interference base station from an interference level detection section 43. Then a ratio D/U is obtained from each of the frequencies, where D is a reception level of a desired wave and U is a reception level of disturbing waves and whether or not the reception level ratio D/U is less than a predetermined reference value is discriminated. When the D/U is less than the reference level, a request signal revising the communication channel frequency f1 of a desired base station 11 into other frequency is sent so as to revise the frequency of the desired wave into a frequency different from those of the disturbing waves. Thus, the interference due to the disturbing wave is prevented with simple constitution.
Patent JP-H01279599-A (JP)
Title: Gas discharge lamp ignitor
Inventor: DEBITSUDO JIYON KOTSUKURAMU
IPC: H05B41/18
Filed: 1988-04-28
Abstract: PURPOSE: To continuously rate an ignitor at a low cost by automatically supplying ignition pulse to a discharge lamp all times when the voltage of a power supply exceeds a preset level. CONSTITUTION: When a discharge lamp 12 is turned off, a circuit is connected to a main power supply. The voltage of the main power supply is accumulated in a voltage multiplier 18 at a preset coefficient. The voltage of the main power supply is applied to a voltage detector/regulator 20 to grant regulated power obtained from increased output voltage to an oscillator/trigger circuit 22 when the voltage of the main power supply exceeds a preset level. In this way, the oscillator is automatically started to give trigger pulse to a resonance circuit network 24. The circuit network 24 boosts the trigger pulse and applies the high voltage pulse to the discharge lamp 12 to cause ignition.  When the ignition is achieved, discharge lamp load drops the input voltage of an ignitor 10 to a preset threshold value level or less for the voltage detector/regulator 20 with the output of the voltage multiplier 18. The ignition pulse is thus stopped.
Patent JP-2000289139-A (JP)
Title: Blister bottom material
Inventor: HASEGAWA SATORU
IPC: B32B7/00
Filed: 1999-04-12
Abstract: PROBLEM TO BE SOLVED: To avoid contamination and at the same time, eliminate the possibilities that an interaction between a drug or food and a blister bottom material might occur by forming the blister bottom material of a plurality of laminated resin layers and an ultraviolet screening layer between the resin layers. SOLUTION: A plurality of recessed parts 3 are formed in a transparent polypropylene sheet 1 and a capsulated tablet 4 is encased in the recessed parts 3 as pockets and further, a lid material 2 is stuck over. The bliaster bottom material used for packaging with PTP(press through pack) comprises an ultraviolet screening layer 5 containing a pigment or an ultraviolet absorber laminated on the surface of a polypropylene sheet A with a thickness of 10-200 μm and further, a polypropylene sheet B with a thickness of 50-400 μm laminated on the ultraviolet screening layer 5. Thus it is possible to avoid a contamination and eliminate the possibilities that an interaction between a drug or food and the blister bottom material might occur.
Patent JP-S61263154-A (JP)
Title: Mis type semiconductor memory device
Inventor: YASUI NORIMASA
IPC: H01L27/04
Filed: 1986-05-09
Abstract: PURPOSE:To reduce an occupying area by forming a power supply line and load elements for memory cells from polycrystalline silicon layers integrally shaped onto semiconductor substrate through an insulating film and using each load element as resistance regions formed in branching sections. CONSTITUTION:A power supply line (a VDD line) is shaped by a polycrystalline silicon layer 2a, and each load element (R1 or R2) for memory cells is branched and extended from the polycrystalline silicon layer 2a for the power supply line strentched on a substrate. The load elements are formed by branching sections (3b or 3a) in the polycrystalline silicon layer being in contact directly in regions 7a or 7b in drain semiconductor regions in MISFETs (Q1 or Q2) for driving. The polycrystalline silicon layers in the power supply line 2a and the branching sections 3b, 3a for the line 2a are shaped integrally. Connections among drains in a pair of FETs for driving or drains in a pair of MISFETs for transmission and the load elements for the memory cells are brought into contact directly by the polycrystalline silicon layers to which resistance regions in the load elements are formed, thus omitting mutual wirings among these circuit elements.
Patent JP-H09274777-A (JP)
Title: Recording and reproducing method for word length variable digital data, and recording and reproducing device for word length variable digital data
Inventor: KOIZUMI TOSHIO
IPC: G11B20/18
Filed: 1996-04-02
Abstract: PROBLEM TO BE SOLVED: To enable division without linking with a galois field in a recording and reproducing method for a word length variable digital data performing encoding on a galois field. SOLUTION: A division unit bit length N which is not linked with a galois field is selected for a galois field, one sampling sample of quantized bit length M (M is integer) is made M/L pieces of divided data of L bit length (L is integer) which can be divided as integer, the divided data divided from two sampling sample or more is rearranged, and M/L pieces of symbol of N bit length are constituted. M/L pieces of symbol are arranged on M/L pieces of code words being different respectively and a code word is constituted, and an error correction code word is constituted with a unit of data of N bit length from a code word.
Patent JP-S61262491-A (JP)
Title: Flux cored wire for gas shielded arc welding
Inventor: TAKEUCHI HIROKIMI
IPC: B23K35/368
Filed: 1985-05-16
Abstract: PURPOSE:To improve removability of slag by incorporating elements of >=2 kinds among Bi, Pb, Sb and Ti into a wire in a specific % range by the total weight of the wire. CONSTITUTION:The elements of >=2 kinds selected from Bi, Pb, Sb and Ti are incorporated into the flux cored wire for gas shielded arc welding in a 0.001-0.06% by the total weight thereof. The steel sheath of the wire is preferably controlled to <=0.10% C, <=1.00% Si, <=2.00% Mn and <=0.03% both P and S. On the other hand, the compsn. range of the flux consists preferably of 3.5-8.5% TiO2 and 1.0-3.7% Mn and others such as Al, Si, Al2O3, Mg, ZrO2 and SiO2 are preferably incorporated therein at a prescribed ratio each. The removability of the slag from beads is remarkably improved by the above- mentioned method as Bi, Pb, Sb, etc. are incorporated into the wire.
Patent JP-H046178-A (JP)
Title: Structure for joining carbon material and metallic material
Inventor: MATSUNAGA MASAHARU
IPC: C04B37/02
Filed: 1990-04-20
Abstract: PURPOSE:To improve joinability by joining a carbon material and metallic material disposed with active metals (hydrides) on one or both joint surfaces via a specific brazing material. CONSTITUTION:The foil or paste 3 of an active metal (hydride) of Ti, Zr, etc., is disposed on the joint surface of the carbon material 1 and the Pd brazing material 4 contg. 4.j0 to 7.0wt.% silicon is superposed thereon. The metallic material disposed 2 with the foil or paste 3 on the joint surface 2a at need is butted onto this material and the materials are heated and brazed in a vac uum atmosphere kept at <= 10<-3> Torr. The joined body formed by joining the carbon material 1 and the metallic material 2 via the brazing material part 5 including the active metal (hydride) interposed there between is thus obtd.