Patent GB-1263281-A (GB)
Title: Improvements relating to character display arrangements
IPC: G09G5/22
Filed: 1969-02-13
Abstract: 1,263,281. Cathode-ray tube displays. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 13 Feb., 1969 [16 Feb., 1968], No. 7913/69. Heading H4T. In a cathode-ray tube display arrangement for characters specified by digital information the characters being displayed by selective bright-up of dot positions on a conventional television linescanned raster, the digital information, derived e.g. from a computer etc., is stored in a buffer memory and then transferred to a recirculating memory device under control of devices which count the number of characters-per-line and the number of lines in a display field and cause the digital information specifying a complete line of characters to be transferred to the recirculating memory during a period of time which is not greater than the time of scanning the space between successive lines of characters. Fig. 1 shows one embodiment in which the buffer memory 1, fed with character-specifying digital information from a computer etc. over lines 11 (or alternatively, forming part of the computer) supplies, in response to command from a selection circuit 2 controlled by a character address device 3, output information to a register 5. This information, comprising 6 bits specifying a character and 2 parity bits, is fed-back via lines 13 to the input of the memory from the output of the register and the 6 character-specifying bits in stages 51 to 56 are fed via respective gates 61a ... 66a to the inputs of respective recirculating memories 61 ... 66. The cycle time of the buffer memory 1 is 6 Á sec. and a clock pulse on line C shifts the contents of the memories 61 ... 66 through one stage every 6 Ásec. A character per-line counter 42 counts the number of characters (assuming that each character has a maximum of six dots in width and is spaced by two dots from the next character and that a television line scan period is 64 Ásecs.) which occur in the number of scan lines utilized for vertical spacing of the rows of characters. Assuming that two scan lines are utilized for spacing, 128 Ásecs. ( = 2 x 64 Ásecs.) are available to load the recirculating memories 61 ... 66 with the data specifying a complete line of characters and since the cycle time of the buffer memory 1 is 6 Ásecs. 20 characters, requiring 6 Î 20 = 120 Ásecs. for loading, is about the maximum which may be loaded within the 128 Ásecs. of the space period. The counter 42 controls the address device 3 to load the 20 characters into the memories 61 ... 66 and when the two line space period has ended the frequency of the clock pulses on line C is doubled and the digital information in the memories 61 ... 66 is circulated at a rate corresponding to the line scan period. Each character is reproduced with a vertical dimension corresponding to eight (horizontal) scan lines and the information for each character in memories 61 ... 66 is therefore recirculated eight times during the display cycle. On each circulation the bits specifying each character are fed to a register 60 the output of which is decoded in 7 to provide "bright-up" signals for the beam of a monoscope tube 8 the beam being additionally controlled by means of digital-to-analogue converters 7a, 7b providing deflection signals to cause the beam to select a desired character on the target of the monoscope which is then scanned, by scanning waveforms supplied from device 4 over lines 83, 84, to produce corresponding video signals. These signals are then amplified at 9 and combined with synchronizing signals in a device 10 to provide signals suitable for a conventional television receiver TV. In the embodiment of Fig. 1, the capacity of the recirculating memories is not fully utilized and a smaller number of such memories may be made to suffice. Fig 2, shows an embodiment in which three recirculating memories 261, 262, 263 only are utilized and in which 8 scan lines are utilized as spacing between the lines of character during the scanning of which digital information specifying a complete line of characters is loaded into the memories. The loading is effected as follows. The 1st, 3rd and 5th bits b 1 , b 1 <SP>3</SP> and b 1 <SP>5</SP> of the first character to be loaded (derived from stages 51, 53 and 55 of register 5) are first loaded simultaneously into the respective memories 261, 262 and 263 after which the 2nd, 4th and 6th bits b 1 <SP>2</SP>, b 1 <SP>4</SP> and b 1 <SP>6</SP> of this character (from stages 52, 54 and 56 of register 5) are loaded simultaneously) into the respective memories 261, 262 which are shifted by about one bit space between the two loading operations. At the end of 6 Ásec. (the cycle time of the buffer memory 1) the memories will have circulated through about eight bit spaces so that the loading of the next character occurs after an unused space equivalent to 6 bits. For this loading cycle the address device 3 is operated to supply to register 5 the six bits b 9 <SP>1</SP> to b 9 <SP>6</SP> of the character b 9  which should occupy the ninth position in the row of characters. These bits are then loaded in the order b 9 <SP>1</SP>, b 9 <SP>3</SP>, b 9 <SP>5</SP> and b 9 <SP>2</SP>, b 9 <SP>4</SP>, b 9 <SP>6</SP> in the manner described for the bits of the first character b 1  and on subsequent loading cycles the bits of characters b 17  ... b 57  are loaded. At this point the second circulation cycle of the memories commences and the bits of characters b 21 , b 18  ... b 58  are loaded and the operation continues in this manner until, at the end of the 8 line space interval, the bits b 1  to b 64  of all 64 characters have been loaded into the memories in the "interleaved" fashion described. The display cycle then commences and the gates 267, 268 and 269 are controlled to pass the character bits to register 60 in the desired display order i.e. b 1 , b 2  ... b 64 . The output of register 60 is then supplied via decoder 7 to the character generator 8 as described in connection with the arrangement of Fig. 1. The form of display is shown in Fig. 7 in respect of the character K. The recirculating memories may comprise glass delay lines or lumped component delay lines and the character generator may, alternatively comprise a diode matrix (Fig. 8, not shown) which is so used that some of the elements may be utilized in the production of a number of different characters which have subparts (limbs) of the same configuration. An embodiment utilizing six recirculating memories and a diode matrix character generator and employing the techniques of the embodiment of Fig. 2 is described with reference to Fig. 3 (not shown) which also gives details of the devices 3, 4, 41, 42, of Figs. 1 and 2. An arrangement providing timing pulses, a circuit providing the actual bright-up pulses for the beam of the display tube and a circulating memory delay line with input and output circuits are described with reference to Figs. 4, 5 and 6 respectively (not shown).