Patent GB-937861-A (GB)
Title: Improvements in high speed data processing system
IPC: G06F7/38
Filed: 1959-10-22
Abstract: 937,861. Digital data storage apparatus. GENERAL ELECTRIC CO. Oct. 22, 1959 [Oct. 24, 1958], No. 35808/59. Class 106 (1). Data in recirculatory delay stores of a parametron-type computer is interlaced, a desired word from a number of interlaced words being selected by an appropriate refer ence signal which is phased to represent " 1 " at the appropriate word bit times and " 0 " at all other word bit times. As described, each store contains four interlaced words each of 32 bits, each bit consisting of 10 cycles of 10,000 Mc/s of appropriate phase (thus lasting 1 millimicrosec.) and being followed by an " insignificant " 1 millimicrosec. in which the phase of the signal is adjusted for the next bit. The clock period is thus 2 millimicrosecs. Fig. 2 shows a storage loop consisting of an oscillator 110 tuned to 10,000 Mc/s., and excited at twice this frequency, a hybrid junction 112 at which an output is obtainable, delay elements 114 and 256, and " and " gate 124 held open while recirculation is desired, " or " gate 126, and amplifier 128. A reference oscillator (not shown) provides a signal at 10,000 Mc/s., the phase of which is that of a series of binary 0's; this is connected at 136 so that the store may be cleared by closing 135. " And " gates are enabled by a signal in antiphase (i.e. representing a string of 1's). Fig. 4 shows schematically the circuitry used for obtaining timing pulses for gating the data in and out of stores. A recirculating loop 150 having a total delay equal to the store recirculation time generates and circulates a single R.F. pulse (as described in Proc. I.R.E., vol 43, pages 140-8), which is synchronized in phase and timing at 162, 163 and which is read out at four spaced points in delay element 172 to produce at the output of " or " gate 178 four consecutive bit pulses representing 1's. These signals are fed into delay element 180 which has 32 taps corresponding in time to the 32 bit-block positions, so that the output at each tap consists of four bit pulses for the four words in that bit denomination. Units such as 186 convert these pulses to phased signals representing 1's, and produce phased signals representing 0's at all other bit times. These signals may be applied, for example, to terminal 125, Fig. 2, in inverted form to erase data in a desired bit-block and permit entry of new data, or to gate out data from such a register. Fig. 5 (not shown), illustrates a tapped delay element with outputs gated by three bits from an order register, so that data may be shifted to another word position, or doubled by a delay of four bit positions, and Fig. 6 (not shown), illustrates a similar time advance network and means for -testing the most significant digit of any of the four words by selecting an appropriate tap under control of any other word. Entry of data using the apparatus of Fig. 4 may be effected by reading into flip-flops 760-764 as a 32-bit data word in conventional binary (pulse-no pulse) form (e.g. from a slower computer) the output of which control phase-shifting networks 750- 754 arranged so that the shift they cause produces a pulse train from "or" gate 662 representing the input number in serial form for conversion to phase representation by unit 756. Specification 937,862 is referred to.