Patent GB-1246503-A (GB)
Title: Spectrum analyzer
IPC: G01R23/16
Filed: 1968-08-21
Abstract: 1,246,503. Computing power spectral density; data processor. INDUSTRIAL NUCLEONICS CORP. 21 Aug., 1968 [1 Sept., 1967], No. 9834/71. Divided out of 1,246,501. Headings G4A and G4H. The apparatus of the invention computes the power spectral density at a frequency # for a function f(t) analytic in the interval t 1  # t # t n  when f(t) is approximated as a linear function: where y n  = f(t n ) and #t = t n+1  - t n , the power spectral density at a frequency # then being given by where and where: A n  = y n+1  - y n , B n  = nA n  + D n , C n  = - (n - 1) An - D n  and D n  = ny n  - (n - 1)y n+1 . In the embodiment described the input waveform y = f(t) is sampled at regular intervals by a sample and hold circuit 22 (Figs. 2a, 2b), and each sample digitized under the control of a clock 24. The resulting N digital signals y n  are stored in a memory 25 and additionally the average #y is simultaneously found by dividing the sum of the y n  by N. The values y n  are then subtracted from the average value in subtractor 35 and the new values #y - y n  stored. To compute the coefficients A n  the stored values are sequentially fed in pairs on leads 34, 36 to a digital subtractor matrix 37 under the control of clock 31, the coefficients being stored in a memory 38. To compute the coefficients D n  register 41 counts pulses from clock 31 the counter having two outputs for deriving values n and n-1, these being fed to multipliers 42, 43. The multipliers also receive the signals on leads 34, 36 to form ny n  and (n-1)y n+1  these signals being fed to subtractor 44 the outputs from which represent the components D n  which are stored in memory 45. Subtractor 37 includes a delay so that the values of the nth coefficients A n , D n  are stored simultaneously. After all the coefficients have been computed and stored, memory 38 is activated to read out all its contents to a prewired multiplier matrix 47 which computes for all n, A n .n and A n .n-1 and feeds the signals to the nth cell of accumulator stores 48, 49 respectively together with signals D n  to form the components B n  and - C n . Read only memory 13 includes four N cell sections 61, 62, 63, 64 the nth cell respectively storing for a selected frequency #m, (cos # m n#t - cos # m  For each value of # m  the nth outputs of each of the memory sections 61-64 are multiplied by the coefficients A n , A n , B n , B n  respectively in multiplier arrays 51, 52, 53, 55 simultaneously for all n. The n-1th outputs of memory 63, 64 are combined in multipliers 54, 56 with the C n  outputs of memory 49. The memories include polarity indicating outputs, the outputs of memory 54, 56 always being reversed since C n  is negative. The memories are connected to digital adders 65.1, 66.1 to form for a given frequency # m  the portions forming the sum of the real and imaginary components R(#) and I(# m ). These signals are fed to squaring networks 67, 68 to form the spectral density #(# m ) for a selected frequency. Clock 65 then advances the count in a register 66 so that the signals associated with the next value of # are read out to the multiplier. The M values #(# m ) are fed via a sealer 71 to a recorder. The sealer (Fig. 3, not shown) comprises M shift registers 82 and 91 the contents of which are sequentially compared with a maximum response signal representing the full scale deflection of the recorder and the contents of all the registers are shifted until all the values #(# m ) scaled by the same factor are less than the maximum response signal. The scaling factor is also fed to the recorder. To determine if a particular frequency is periodic a computing element 73 computes This is then multiplied by a factor dependent on the degree of certainty required, e.g. 6.6 for a 99% probability that the frequency is periodic and compared with each of the values #(# m ) the frequency # m  being periodic if #(# m ) is greater than 6.6 #(# AV ). This computation is effected with the circuitry of Fig. 4 (not shown) in which the successive values #(# m ) are summed in a register (133) and also stored in M locations of a memory (132). The sum in the register (133) divided by M and multiplied by the selected factor is compared with the values #(# m ) in M comparators, the comparators giving 1 or 0 outputs in dependence on the relative values of the input. The comparator outputs are applied to the recorder.