Patent GB-1519985-A (GB)
Title: Computer momories
IPC: G11C16/04
Filed: 1975-07-14
Abstract: 1519985 Electric digital data storage SPERRY RAND CORP 14 July 1975 [15 July 1974] 29478/75 Heading G4C A digital memory system comprises a memory array 11, Fig. 1, of variable threshold IGFETs, the array being 2<SP>n</SP> block rows and m word columns arranged on a common substrate (n=7 and m=64 in the Fig.), the block rows within the array 11 being selected for reading or writing by address signals X 1 -X 7 , and their complements, applied to a block decoder 13 which in turn feeds a buffer circuit 15, transfer of the words of a selected block in memory array 11 to or form a data output or data input taking place via a shift register 19 having stages each corresponding to a respective word column, all of the words of the selected block being simultaneously strobed to or form the shift register 19 via voltage applied to transistors 35, whereas data is input or output to or from shift register 19 in serial form by means of four-phase timing pulses # 1 -# 4  applied thereto. Each block row has the gates of its IGFETs commonly connected to a respective output of the buffer circuit 15, the drains of all IGFETs of each word column being commonly connected via a respective transistor 31 to a voltage source V WLD , whereas the sources of all IGFETs of each word column are commonly connected to a respective stage of the shift register 19. The stages of the shift register 19, as shown in detail in Fig. 4, are arranged in first and second groups, the stages of the first group comprising the odd word columns 1-63, whereas those of the second group comprise theeven word columns 2-64, each of the first and second groups having a respective input stage 45 and 37 to which data fed to the data input is alternately clocked by the timing pulses # 3 , # 4  and # 1 , # 2 , each group further including respective output stages 47, 41 from which data may be output to a buffer 21 under the control of respective timing pulses # 2 , # 4  and from which data may be recirculated to the input stages 45, 37 via respective feedback lines 51<SP>1</SP>, 49. Each stage of the shift register 19 comprises first and second transistor divider networks energized by respective timing pulses # 1 , # 2  and # 3 , # 4 , so that each complete cycle # 1 -# 4  of timing pulses clocks the data one stage along the shift register. R identical memory arrays 11 and R identical shift registers 19 may be incorporated in a memory system able to handle R-bit data words (Fig. 2, not shown). Reading from memory array 11. In the first or access phase of the reading cycle, data from an addressed block memory array 11 is read into the shift register 19, at the end of which phase the array is isolated from the register by the transistors 35. m Repetitive sequences of timing pulses # 1 -# 4  are then applied to the shift register 19 to read out the data serially therefrom, the data also being recirculated via feedback lines 51<SP>1</SP>, 49 and the enabled transistor divider networks. When the last bit of data has been read out, the shift register 19 is clocked by half a clock cycle to obtain the identical state as at the end of the access phase; the memory array 11 is then reconnected to the shift register 19 and the data from register 19 rewritten into array 11. During the time the memory array 11 is isolated from the shift register 19, the IGFETs of the addressed block are cleared to 0 prior to the rewriting phase. Writing into memory array 11.-Apart from the fact that no access phase is required, this is similar to the reading process. The transistor divider networks of input stages 45, 37 are enabled to receive serial data from the data input, recirculation of the data on feedback lines 51<SP>1</SP>, 49 being inhibited. m Repetitive sequences of timing pulses # 1 -# 4  are then applied to write the data into shift register 19. During this time, the memory array 11 is isolated from shift register 19 and the IGFETs of the addressed block are prepared for writing thereinto by a process similar to that used in reading. When the last bit of data has been written into shift register 19, it is connected to the memory array 11 and the data is written into the addressed block of the array. Timing diagrams for the reading and writing processes are given in Figs. 5 and 6 (not shown).