Patent GB-1468019-A (GB)
Title: Phase comparison radio navigation systems
IPC: G01S5/10
Filed: 1973-11-16
Abstract: 1468019 Radio navigation DECCA Ltd 18 Nov 1974 [16 Nov 1973] 53231/73 Heading H4D In a receiver for a phase comparison radio navigation system of the kind in which spaced transmitting stations radiate phase-locked signals in a time-shared sequence, said receiver has oscillators each phase-locked to a received signal from one of the transmitting stations to provide a phase memory, so enabling comparison signals of the same frequency to be simultaneously available for phase comparison. The receiver also comprises two or more display units, each having a digital phase comparator including a counter and a decimal digital display for indicating the phase relationship between two inputs to the comparator. The outputs from the phase memory oscillators are connected in pairs, as required, to the phase comparators by a selector means, which may be manually operable. As described, each transmission sequence, Fig. 1 (not shown), is commenced by a prime station with a 20 msec. synchronizing signal of frequency f1, two portions of which, each of 5 msec. duration, are displaced in phase from the remainder by 72 degrees. The prime station continues by transmitting an unmodulated signal of frequency f1 for 20 msec., and then an unmodulated signal of frequency f2 for 20 msec. Secondary stations, to a maximum number of five, follow in turn, each transmitting only the unmodulated signals of frequencies f1 and f2 and durations each of 20 msec. The said frequencies lie in the range 1À6 to 5À0 MHz, f2 being a few per cent less than f1, and the differences between phase angle determinations at the two frequencies provide a coarse pattern of position lines for resolving ambiguities. At a receiver a voltage controlled 10 MHz oscillator with an associated 100/1 frequency divider is provided for each transmission of different frequency (i.e. f1 and f2) for each station. As shown in Fig. 4, the 10 MHz oscillator 111 controlled by signals of frequency f1 received from the prime station feeds two synthesizers 107, 108 which develop outputs of respective frequencies F1 (=f1+100 kHz) and F2 (=f2+100 kHz). These are heterodyned with incoming signals in a mixer 103, which provides an output of frequency 100 kHz. After processing in a squarer 105, said output is applied to a phaselock discriminator 106, a second input to which is obtained from the frequency divider of the 10 MHz oscillator corresponding to the station and frequency being received, by operation of the appropriate logic gate of a gating circuit 150. The error output of the discriminator 106 is fed through a switching circuit 153 to the said 10 MHz oscillator, so that it becomes phase-locked to the received signal. The gating and switching circuits 150, 153 are operated by a timing control unit 151, which receives an input of frequency 4 kHz from the synthesizer 107. Synchronizing is effected by output from a discriminator 172, which detects the phase modulation in the synchonizing signal from the prime station, and gives a reset signal to the timing control unit 151. Outputs from the twelve frequency dividers 112, 124 to 134 are coupled by leads 160 to 171 to three identical digitizer and phase measurement units 180, 181, 182 each of which includes a phase measuring circuit 183 and a counter 184. Each of these units also includes manually operable switches whereby any two of the said outputs may be selected. The phase measurement is conveniently effected using a double-D type bi-stable which give two phase time intervals, i.e. a first using signals locked to f1 transmissions, and a second using signals locked to f2 transmissions from the same pair of stations. The intervals are measured by a pulse count of 10 MHz signals obtained from the oscillator 111 on a lead 187. Since the comparison signals have a frequency of 100 kHz, the count is inherently in one hundredths of a lane. The f1 pattern phase measurement is fed via the comparator into a phase angle fraction display store. The comparator updates the store by the minimum number of bits that are required and provides steering and carry data for the display lane counter. The f2 pattern phase measurement is also stored. The complement of the f2 store is added to the f1 pattern store so generating a difference in phase between the two signals for the coarse pattern display. The two counts are fed to a unit 186, which features a six-digit display for the fine pattern, and a two-digit display for the coarse pattern. Initial setting of the lane reading counts of the three displays is effected manually. For this purpose, there are provided a set push button 185, a digit select thumbwheel 188 for each display, and a digit set thumbwheel 189 which selects the particular digit in a display which is to be set.