Patent GB-1519002-A (GB)
Title: Memory circuits
IPC: G11C17/00
Filed: 1975-06-09
Abstract: 1519002 Digital memories SPERRY RAND CORP 9 June 1975 [10 June 1974] 24619/75 Heading G4C A digital memory 10 comprises a semiconductor substrate having an array 43, e.g. 16x16, of variable threshold field effect transistors, e.g. 44-46, formed thereon, each of the transistors having a first conduction threshold (indicative of binary 0) established by applying a clearing potential, e.g. + 30V, to the gates of the transistors via a terminal V c  of an address buffer circuit 33, the address buffer circuit being isolated from the remainder of the substrate by an isolation region 40, and a second conduction threshold (indicative of binary 1) established by applying a writing potential of opposite polarity to the clearing potential, to a terminal V R/w  of the address buffer circuit; the address buffer circuit 33 comprising fixed threshold transistors, e.g. 36, 37, and being coupled to the outputs, e.g. 22, 23, of address decoders, e.g. 21, which decoders receive address bits 2<SP>0</SP>-2<SP>3</SP> on respective terminals 11-14 to address the rows of the memory, In the case where the substrate comprises a relatively thick layer of P-type material overlain with a relatively thin layer of N-type material, the isolation region 40 takes the form of a deep diffusion of the P-type material through the entire thickness of the N- type material. It is stated that when the clearing potential is applied to terminal V c  the isolation region 40 becomes reverse biased and prevents the clearing potential from reaching the remainder of the substrate, and in particular the memory array 43, which enables the clearing potential to be applied to the gates of the memory transistors, e.g. 44-46, to effect a "bulk clear" operation on the memory. The sources of transistors corresponding to transistor 36 are commonly connected to terminal V c , the gates and drains of transistors corresponding to transistor 37 being commonly connected to terminal V R/W , with the junctions between transistors, e.g. 36, 37, being connected to the gates of the transistors of memory array 43. Alternatively, the substrate may be formed of a relatively thick layer of sapphire with a superposed relatively thin layer of semi-conductor material, the isolation region 40 taking the form of a moat in the semi-conductor layer. The address bits 2<SP>0</SP>-2<SP>3</SP>, and their complements formed in four address inverters, e.g. 15, are applied to eight address decoders each identical with the decoder 21 to address the sixteen rows of the memory array 43; reading and writing from or into the sixteen columns of array 43 is achieved via sixteen identical sets of I/O control and buffer circuits 47, 50. In operation, a "bulk clear" operation is followed by a programmed "write" operation, which enab'es the memory to be used in subsequent "read" operations as a read-only memory. Bulk clear.-A voltage V CLEAR  of approximately + 30V applied to terminal V c  renders all the transistors 36 conductive irrespective of word select signals applied to the gates thereof on lines 22, 23. The voltage V CLEAR  is thus applied to all the gates of the memory transistors of array 43, altering them to the first conduction threshold, i.e. clearing the memory. Write.-A low signal applied to a terminal 75 of a control circuit 74 and a voltage V WRITE  of approximately - 30V applied to terminal V R/w  of address buffer circuit 33 and to a terminal 57 of I/O control circuit 47 enable the address decoders 21, and render transistors 53, 63, 66 and 70 of circuits 47, 50 non-conductive, and transistor 65 conductive, thereby permitting a common drain line 55 of a column of array 43 to be driven by an I/O bit 1 terminal 51 to control information written into the addressed row of column 1 of the array 43. A similar operation takes place with columns 2-16 of the array 43. Writing into a particular location of the array 43 is accomplished by supplying a high signal to terminal 51, a low signal applied thereto having no effect on the array 43. Read.-A high signal applied to terminal 75 and a voltage V READ  of approximately -12V applied to terminals V R/W  and 57 enable address decoders 21 and render transistors 53, 63 and 70 conductive. The voltage V READ  is thus applied to the gates of the memory transistors via transistors 37. If the first conduction threshold has been established in a memory transistor, this is greater than V READ , so that the memory transistor remains enabled and places a high signal on drain line 55; this renders transistor 65 non-conductive and transistor 66 conductive, pulling terminal 51 to ground potential (binary 0). If however the memory transistor had been set to the second conduction threshold, drain line 55 receives a low signal, enabling transistor 65 and placing a high signal on terminal 51 (binary 1).