baber/WOPTO huggingface dataset:
Patent JP-H11313220-A (JP)
Title: High voltage power supply circuit
Inventor: OTA HIROYUKI
IPC: H04N3/18
Filed: 1998-04-28
Abstract: PROBLEM TO BE SOLVED: To prevent the response of the circuit against a sudden change in a load of a CRT from being deteriorated by quickening a rising time of the CRT when a power switch of a monitor is closed. SOLUTION: A high speed processing circuit 10 connects to a detection line 6 through which a feedbacks signal is fed from a high voltage detection circuit 5 to a high voltage stabilizing circuit 1, a pnp transistor(TR) 12 of the high speed processing circuit 10 is conductive to connect a resistor 11 connecting to the detection line 6 to ground so as to forcibly decrease a detected high voltage. Thus, the high voltage stabilizing circuit 1 allows a resonance power supply circuit 2 to increase a peak level of a flyback pulse as a higher pulse voltage so as to quicken a rising time of the high voltage output fed to an anode of a CRT.  When a voltage across a capacitor 13 charged via a resistor 14 is nearly higher than a voltage at a point A after the lapse of a prescribed time, the pnp TR 12 is non-conductive and the resistor 11 is disconnected from ground and then a sudden change of a load of the CRT does not slow down the response of the circuit.
Patent JP-S61274914-A (JP)
Title: Method for taking out and conveying molded product
Inventor: SHIMA YOSHIHARU
IPC: B65H20/00
Filed: 1985-05-31
Abstract: PURPOSE:To enable the detection and removal of an inferior product, by demolding a molded product along with a take-out tape comprising paper or a synthetic resin at the time of mold opening to feed the same to the outside of a mold and removing an inferior molded product, which was detected by the quality discrimination device of a molding machine side, from the take-out tape by an inferior product removing apparatus operated by an inferior product detection signal. CONSTITUTION:An inferior product removing apparatus 11 operated by the signal from the quality discrimination device 10 mounted to a molding machine is provided between a mold 5 and a transfer apparatus 6 and provided at a position twofold or several fold the feed pitch of a take-out tape from a cavity and has the guide part 11a of the take-out tape and a cylinder 11b scraping off an inferior product 9a from the take-out tape while an inferior product recovery box 21 is provided under said apparatus 11. The inferior product 9a, which was judged by the quality discrimination device 10 of the molding machine side, is transferred along with the take-out tape to reach the inferior product removing apparatus 11 and, at this point of time,a the cylinder is operated to scrape off the inferior product. By this method, the molded product transferred to the next process comprises only a good product.
Patent JP-H02294841-A (JP)
Title: Logical simulation system
Inventor: TOBINAGA SATOSHI
IPC: G06F11/25
Filed: 1989-05-10
Abstract: PURPOSE:To confirm logic elements following a logic element whose abnormality is detected and to efficiently analyze simulation by setting an expected value for an internal logic element even if abnormality is detected in the result regarding the logical element which specifies a time chart display during the logical simulation. CONSTITUTION:An expected value setting part 7 takes out and sets the expected value of the corresponding logic element according to an expected value inputted by an expected value input part 2 for the internal logic element whose simulation result is noncoincident. A resimulation part 8 performs simulation as to the internal logic element whose expected value is set and a result comparison part 9 compares the simulation result outputted by the resimulation part 8 with the result obtained with the expected value inputted by the expected value input part 2. A time chart display part 10 displays a time chart where the output of the logic element and the output of a simulation model are compared and a time chart outputted by the resimulation part 8. Consequently, an analysis regarding logic up to the logic element and logic after the logic element can be taken.
Patent JP-H01288270-A (JP)
Title: Instillation liquid completion annunciator
Inventor: WATABE SUSUMU
IPC: A61M5/00
Filed: 1988-05-14
Abstract: PURPOSE:To speedily inform a concerned person of the completion of an instillation liquid and to receive a safe medical care by sensing the completion of the instillation liquid by means of a sensor. CONSTITUTION:For a main body 1, a sensor 10 is installed in a center, a 1C substrate 13 is fitted to a deep part, a battery 11 is located at a left lower side, a buzzer 14, etc., are located on it, and in an external part, an infrared radiation display lamp 2, a 2P connector 4 and a power switch 3 are fitted to an upper part. An instillation liquid 7 passes an instillation hose 6, the main body 1 is fitted in the course to flow to an injection needle 13, the completion of the instillation liquid is sensed by a sensor 11, the infrared radiation lamp 2 is lighted up, and the completion of the instillation liquid is informed of by the buzzer 14. In such a way, an instillation completion annunciator is safe, small-sized and easy-to-handle, and the concerned person can be informed of the completion of the instillation liquid.
Patent JP-S5242307-A (JP)
Title: Subscriber answering detection system
Inventor: MORI HIDEYASU
IPC: H04M3/02
Filed: 1975-09-30
Abstract: PURPOSE: To enable sure identification of receiver hook up at the transmission of call signal, by detecting the presence of developed voltage of line circuit at a part of period of positive cycle for call signal. 
     COPYRIGHT: (C)1977,JPO&Japio
Patent JP-H0414042-A (JP)
Title: Photosensitive material processing device and water adding method in this device
Inventor: MOGI FUMIO
IPC: G03D3/06
Filed: 1990-05-08
Abstract: PURPOSE:To improve the accuracy of liquid level detection by providing overflow tanks each having an overflow sensor. CONSTITUTION:The respective processing tanks 10 of this processing device are provided with the overflow tanks 46 respectively adjacent thereto. The self-exothermic type temp. sensor 52 is disposed in each tank 46. The tank 10 is so formed that the processing liquid therein flows over a vertical wall 48 and along the sensor 52. The temp. of the sensor part 54 which generates heat by itself is changed by the processing liquid, by which the presence or absence of the processing liquid is detected.
Patent JP-H01288490-A (JP)
Title: Memory card
Inventor: AKATSUCHI OSAMU
IPC: B42D15/10
Filed: 1988-05-17
Abstract: PURPOSE:To make a memory card thin and to reduce the cost without sacrifice of commodity value, by coupling first and second frames integrally through screwing while holding a printedboard between them. CONSTITUTION:A memory card comprises a block body 1, upper and lower plates 3 and a cell cover 4. The block body 1 comprises an upper frame 5, a printedboard 6, a connector 7 and a lower frame 8. When the printedboard 6 is contained in the upper frame 5, the reinforce rib 10 of the upper frame 5 is inserted into a gap between rows of circuit elements 16 so that the upper face of the upper frame 5 will be flush with the upper face of each circuit element 16. When the lower frame 8 is mounted on the printedboard 6 and the engage pawl 24 of the lower frame 8 is engaged with the engage step section 25 of the upper frame 5, the upper and lower frames 5, 8 are coupled temporarily through the printedboard 6. When a nut 32 is tightened to a screw 23 under the condition where the engage pawl 24 and the engage step section 25 are engaged, the upper and lower frames 5, 8 are coupled integrally through the printedboard 6 and a connector 7.
Patent JP-H02297957-A (JP)
Title: Lead frame for semiconductor device
Inventor: YOSHIMORI KENZO
IPC: H01L23/50
Filed: 1989-05-11
Abstract: PURPOSE:To eliminate the problems due to lack in strength during handling in production or inspection of a semiconductor device or mounting of a substrate by providing sites with two or more mutually different sites at a lead frame for a semiconductor device. CONSTITUTION:A lead frame 2 for a semiconductor device 1 is formed by placing a die pad 4 lower for the surface of the lead frame 2 by press machining and resin tape 10, etc., is applied to the surface of an inner lead 5a to prevent the inner lead 5a from being deformed. A rail 8 and a crosspiece 9 of this lead frame 2 are made thicker to prevent deformation caused by contact of the inner lead 5a of the upper and lower neighboring lead frames 2 and a depressed die pad 4, etc., when piling up the lead frames 2. Then, sites with two or more mutually different thickness are provided at the lead frame 2, thus eliminating the trouble due to lack in strength during handling of semiconductor device.
Patent JP-S5642147-A (JP)
Title: Method and device for measuring flow speed
Inventor: MORI YASUO
IPC: G01P5/165
Filed: 1979-09-14
Abstract: PURPOSE: To measure the flow speed of the fluid to be measured and enable the stable measurement for a long period by detecting the air pressure inside both pipes for measuring the total pressure and static pressure having air-jetting prifices respectively in the parallel and rectangular directions to the flow of the fluid.  
     CONSTITUTION: The air under the required pressure is setn into both pipes 3 and 4 for measuring the total and the static pressure and is jetted out from the jetting orifices 5 and 6 of both measuring pipes 3 and 4 into the flow of the fluid 2 to be measured, i.e. from the total-pressure measuring pipe 3 it is jetted out in parallel to the direction of the flow of the fluid, while from the static-pressure measuring pipe 4 at right angle to the direction of the flow thereof. And, by measuring the difference in the voltage on the secondary side of orifices 12 and 13 in both measuring pipes 3 and 4, the flow speed of the fluid 2 is measured. In addition, the jetting orifices 5 and 6 are free from filling with solid substances in the fluid 2 since the air is jetted out therefrom, and thus the stable measurement for long period can be secured. 
     COPYRIGHT: (C)1981,JPO&Japio
Patent JP-S5923125-A (JP)
Inventor: BAATON SUTANREE ROOCHI
IPC: F16D3/50
Filed: 1983-07-01
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-2000271906-A (JP)
Title: Precut fabrication of wood and device therefor
Inventor: NAKAJIMA MINORU
IPC: B23Q17/20
Filed: 1999-03-23
Abstract: PROBLEM TO BE SOLVED: To prevent an erroneously fabricated wood from being shipped and realize a useful application to quality control by measuring the length of a precut wood and comparing the measured length with fabrication length data already inputted in a computer and perform a subsequent fabrication process using data which interprets the comparison result an inside or outside a reference value as quality control data for each precut wood. SOLUTION: A wood 1 loaded into the loading part 2 of a precut fabricating device is fed to a cutting means 4 after a length fabrication size with an optimal yield is worked out based on fabrication data already inputted in a computer using judging means 3. At the same time, data on the fabrication size data of a mortise or the like to be formed in the side face or the cross section of a wood, is transferred to a side face fabricating device 5 or an end fabricating device 7, and the length fabrication size data is transferred to a length inspecting part 6.  The precut wood 1 is cut based on the length fabrication size data using a cutter 4 and then a mortise or the like is formed in the side face using the side face fabricating device 5 and further, the length is measured by the length inspecting part 6 to measure whether an error between the measure length and the already entered data stays within a tolerable range for use. This measurement is recorded together with the judgment data. Thus it is possible to prevent the wood outside the tolerable range from being shipped.
Patent JP-S61278365-A (JP)
Inventor: HAGIWARA TATSUO
IPC: B02C15/04
Filed: 1985-05-31
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S5820021-A (JP)
Title: Filter device for surface acoustic wave
Inventor: CHIBA TAKAO
IPC: H03H3/08
Filed: 1981-07-30
Abstract: PURPOSE:To realize optionally desired band characteristics with a linear phase, by combining at least two surface acoustic wave filters and then securing the overlap or adjacency between the pass bands of both filters. CONSTITUTION:Flat band pass characteristics having center frequencies f1, f2 and the transition regions overlapping to each other are provided to the surface acoustic wave filters 1 and 2. Then an input signal is branched into two parts to be applied to these filters 1 and 2 via the matching circuits 3 and 4, respectively. Furthermore the output signals of the filters 1 and 2 are added together at an equal level via the matching circuits 5 and 6. Thus both filters 1 and 2 have a linear phase within each pass band through a symmetrical structure of a pair of the transmitting and receiving electrodes.
Patent JP-H0475583-A (JP)
Title: Hybridoma cell and monoclonal antibody produced by said cell
Inventor: BARACHIYANDORAN NARAYANASUWAMI
IPC: C12N15/02
Filed: 1990-05-07
Abstract: PURPOSE: To obtain a monoclonal antibody specific to a HHV-6 infectious cell, a HHV-6 protein, a polypeptide or a HHV-6 glycoprotein, by culturing a prescribed hybridoma-based cell.  
     CONSTITUTION: Infectious cells of 3×10 7  are intraperitoneally administered to a BALB/C mouse 4-6 weeks after birth at intervals of three weeks to immunize the mouse. The spleen of the mouse is fused with an Sp 2 /OAg. 14 myeloma cell by a method (4.7) described in documents. Some fused cells capable of producing HHV-6 specific monoclonal antibody are initially selected based on specific reactivity of the cells to HHV-6 infectious cells by an enzyme immunity method (ELISA) and an immunofluorescence method. A supernatant liquid of the culture solution derived from the clone of the fused cells is used for an immunoprecipitation of an uninfected and an infected cells labeled with [ 35 S]methionine and the fused cell clone, the HHV-6 specific peptide is cloned again and reselected. 
     COPYRIGHT: (C)1992,JPO
Patent JP-H0415263-A (JP)
Title: Preparation of phthalocyanine compound
Inventor: OGUCHI TAKAHISA
IPC: C07D259/00
Filed: 1990-05-10
Abstract: PURPOSE:To obtain a halogenated alkoxyphthalocyanine which is useful as a near-infrared absorbing agent for a DRAW type CD (CD-WO) by reacting an alkoxyphthalocyanine with a halogenating agent at a specified condition. CONSTITUTION:A phthalocyanine compd. of formula II (wherein R is a substd. or unsubstd. alkyl group; Met is two hydrogen atoms, a divalent metal atom, a substd. trivalent metal atom or a disubstd. tetravalent metal atom; X is chlorine, bromine or iodine; (n) is 1<=n<=4) is obtd. by reacting a phthalocyanine compd. of formula I (wherein R and Met are the same as in the case of formula II) with a halogenating agent in acetic acid at 20-90 deg.C. It is pref. that 10- to 200-fold by wt. acetic acid and 1-6 molar ratio halogenating agent are, subjected to react with the phthalocyanine compd. of formula I.
Patent JP-S5452408-A (JP)
Title: Radiotelephone set
Inventor: MASUDA YOSHIO
IPC: H04B1/46
Filed: 1977-10-04
Abstract: PURPOSE: To make an alternation from a hand-free service to a handset service easily by outputting an alarm, by enabling a mobile radio telephone set to detect and discriminate a reception level.  
     CONSTITUTION: An operator makes a call by way of microphone 7, amplifier 8, variable attenuator 11, transmitter 6, commonuse unit 2, and antenna 1, and monitors a reception signal by way of receiver 3, variable attenuator 10, amplifier 4, and speaker 5. Attenuators 10 and 11, controlled by switch 14 operating corresponding to the levels of the reception signal transmission signal, prevent the howling during a mutual call. Detecting a voltage proportional to the reception level of receiver 3, reception-level detection circuit 15 compares it with a set reference value to make a decision, thereby operating alarm circuit 16 by its output. Consequently, the user makes an alternation from a hand-free service to handset service 
     COPYRIGHT: (C)1979,JPO&Japio
Patent JP-S63283099-A (JP)
Title: Manufacture of printed wiring board
Inventor: YONEZAWA NAOAKI
IPC: H05K3/18
Filed: 1987-05-14
Abstract: PURPOSE:To obtain a wiring board containing a flawless circuit part by a method wherein a copper-plated part is formed on a solder-plated part as a resist for etching use in order to protect the solder-plated part from being dissolved during an exfoliation process of the alkaline-exfoliating resist for etching use. CONSTITUTION:A resist 3 for plating use is formed on a copper layer 2 formed on a substrate 1; the resist for plating use only in a part where a circuit is to be formed is removed. A solder-plated part 4 is formed at least on the part where the circuit is to be formed; a copper-plated part 5 is formed on the part. The resist for plating use is exfoliated; a circuit substrate 6 is formed; lastly, the copper-plated part 5 on the solder-plated part 4 and the copper layer 2 other than the part where the circuit is to be formed are etched; the circuit is formed. By this setup, it is possible to protect the solder-plated part 4 from being dissolved by an alkaline-exfoliating solution during a process to exfoliate the alkaline-exfoliating resist for plating use. As a result, a wiring board containing a flawless circuit part is obtained.
Patent JP-S5819952-A (JP)
Title: Sequence error detection
Inventor: OONUKI TOSHIKIYO
IPC: G06F9/22
Filed: 1981-07-29
Abstract: PURPOSE:To provide holding function for an error address at the generation  time of a sequence error with a simple and economically advantageous constitution, by using the already provided hardware effectively. CONSTITUTION:CS data read out from a control storage CS101 in accordance with the CS address selected by an address selector 102 is loaded to a CS data register 105. Simultaneously, the CS address is loaded to a parity error address register 108, and the CS address incremented (+1) by an address adder 103 is  loaded to a microaddress register 104. In respect to determination of the CS  address, an output (a) of the microaddress register 104, a part (b) of the output of the CS data register 105, or another signal (c) is selected by the address selector 102 in accordance with the micro instruction in the CS data register 105.
Patent JP-H05315871-A (JP)
Title: Step attenuator
Inventor: SEKINE KENJI
IPC: H03H11/24
Filed: 1992-05-12
Abstract: PURPOSE:To reduce the number of switches against the number of steps by connecting a fixed attenuation element switchfing attenuator in series to a resistance division type attenuator in which plural number of series connection circuits comprising resistors and switches are connected in parallel between a source of a FET and ground. CONSTITUTION:A signal at an input terminal 1 passes through an attenuation element 4 or a line 3 by changeover switches 2a, 2b and is inputted to a gate of a FET 5. Circuits each comprising series connection of resistors (R1-R4) and switches (8a-8d) are connected in parallel between a source and ground. Through the constitution above, four stages of the switch attenuators are realized by the changeover of the switches 8a-8d and 8-stages of switch attenuators are realized by the combination of a 2-way changeover switch provided to its pre-stage with the former switch attenuator.
Patent JP-H05313080-A (JP)
Title: Optical switch
Inventor: OZAWA KAZUMASA
IPC: G02B6/28
Filed: 1992-05-12
Abstract: PURPOSE:To provide an optical switch having a positioning measurement equipment only in one optical waveguide. CONSTITUTION:An optical switch is constituted in such a way that a beam splitter 5 which transmits signal light having a wave length (lambda1) and reflects reference light having a wave length (lambda2) is arranged in a line of a master side fiber 3, and the master side fiber 3 is coupled with a positioning measurement device 4 through this beam splitter 5. Since this measurement device 4 has a light source 7 to radiate the reference light (lambda2) to the coupling edge surface 1c of an optical fiber 1 and a detector 8 to detect a light quantity of return light from the coupling edge surface 1c, a master side connector is positioned relatively to the optical fiber 1 so that the light quantity of the return light detected by the detector 8 becomes minimum.
Patent JP-H06164382-A (JP)
Title: Phase-locked loop
Inventor: SHIRAZUI GADEI
IPC: H03L7/107
Filed: 1993-04-21
Abstract: PURPOSE: To attain high selectivity by acquiring a lock within 5 milliseconds after switching the mode to a normal mode. CONSTITUTION: In accordance with the selection cancellation of a fraction 'N' integrated circuit 40, *CE returns to +Vcc , and then, the conduction of a diode D1 is stopped and the diode D1 returns to a high-impedance state. Therefore, a capacitor C1 is charged to +Vcc . As a result, the conducting route passing through a transistor Q1 is restricted and a resistor R3 is disconnected. In addition, the serial circuit of a resistor R4 becomes the only resistor that is connected to the bias input 41 of an internal charge pump. In a normal mode, the variation of the resistor connected to the input 41 generates a gradual and continuous reduction of a gain. Therefore, the time required for acquiring a lock is saved, because an output frequency can be acquired at a high speed. High selectivity is attained by providing technically fast initial locking time and a narrow band width.
Patent JP-H06318604-A (JP)
Title: Bipolar silicon semiconductor device and its manufacture
Inventor: TSUDA HIROSHI
IPC: H01L21/331
Filed: 1993-04-22
Abstract: PURPOSE:To achieve a high fr and then suppress a base resistance rbb' low by constituting an intrinsic base region with an epitaxial layer and then isolating an external base region for leading out the intrinsic base region from the intrin sic base region. CONSTITUTION:A silicon oxide film 105 is selectively etched by the RIE method to form an emitter opening 106 and a p<+>-type epitaxial layer 104 is formed through it. Also, heat treatment is performed within nitrogen atmosphere to form an n<+>-type diffusion layer 109 which becomes an emitter region, thus making similar the sectional shape of a p-type epitaxial layer which becomes an intrinsic base layer and that of an emitter diffusion region 109 for improved breakdown voltage. Also, by constituting the intrinsic base region and the external base region with another epitaxial layer, a high fr is achieved and at the same time the base resistance rbb' can be suppressed low.
Patent JP-H09300028-A (JP)
Title: Device for caulking nut into glow plug
Inventor: OTSUKA YOSHIJI
IPC: F02P19/00
Filed: 1996-05-14
Abstract: PROBLEM TO BE SOLVED: To avoid such trouble that a caulking edge is not come out from a nut caused by biting of the caulking edge into the nut by forming the caulking edge used to the caulking of the nut to the shape having thicker edge tip part than the edge root part. SOLUTION: At the time of fixing the round nut 2 laid on an insulating body 32 on a glow plug 3, the cross section of the caulking edge 11 is changed from the conventional shape having the fixed thickness (A) to the reverse tapered shape (B), (C) having thicker edge tip part than the edge root part. By this shape, the development of such a phenomenon that the caulking edge 11 bits into the nut 2 and at the time of pulling out the caulking edge 11, this edge is not come out from the round nut 2 caused by galling of the nut material, is reduced. The reverse tapered angle of the caulking edge 11 is made to about 2-10 deg. angle to the horizontal plane and can be formed to either one of both side surfaces (B) or the one side surface (C) of the edge surface.  Further, at the time of mutually butting the caulking edge 11, square or hexagonal caulking space is formed at the outside surface of the round nut 2 at the butting center.