Patent GB-1163789-A (GB)
Title: Driver-Sense Circuit Arrangements in Memory Systems
IPC: G11C11/412
Filed: 1966-12-21
Abstract: 1,163,789. Matrix stores. RADIO CORPORATION OF AMERICA. 21 Dec., 1966 [30 Dec., 1965], No. 572l7/66 Heading G4C. [Also in Division H3] Each bi-stable circuit of a word organized matrix store described has a common input output line connected through a gate to a potential source controlled by the output of the bi-stable circuit and also coupled to a low impedance device which during reading senses the output current and also serves to maintain the output potential constant. Fig. 2 shows an insulated gate field effect transistor bi-stable circuit comprising a bridge arrangement of complementary transistors 32, 34, 40, 42, so cross-coupled that diagonally opposite transistors conduct together. Setting is effected by applying a pulse to the write line X so as to cause transistor 50 to break the feed-back loop and a transistor 56 to conduct the "0" or "1" write signal from the digit line D 1  to the gates of transistor 32 and 34. Read-out is effected by applying a pulse to the read-line X so that transistor 70 will conduct to digit line D 1  a "0" or "1" current depending upon the condition of the bi-stable circuit. The common read-write digit line D 1  is connected to a transistor 80 and to a constant current transistor 94 which provide the "0" and "1" write signals in accordance with the level of the data signal from 112 and are also arranged rapidly to charge or discharge the digit line capacitance 78 during writing. During reading the voltage from 112 at the base of transistor 80 is near to earth so that 80 acts as a common base amplifier of low input impedance for the signal read-out. Only a small change in emitter potential can occur and accordingly the digit line capacitance does not have to be charged or discharged. Fig. 3 shows an alternative bi-stable circuit having separate "0", "1" digit driver lines D 1a , D 1b  connected to driver transistor circuits, not shown, similar to 80, 94 Fig. 2 except that only the circuit connected to driver line D 1b  acts also for the read-out signals. The bi-stable circuit 30<SP>1</SP> again comprises a cross-coupled bridge of complementary transistors. To write a "1" into the circuit the word line X is pulsed, rendering 134 conducting and cutting off 122 and 124. Simultaneously the digit drive and sensing line D 1b  is pulsed to cut-off transistor 126 and render 132 conducting. This causes circuit to be set into the state in which transistors 34 and 40 conduct. Setting to "0" is similarly effected by applying pulses to the word line and digit line D 1a . Non-destructive read-out is effected by applying a pulse to the word line X. This causes transistor 142 to conduct a "0" or "1" current to line D 1b  depending on the state of the circuit and this passes to the output line through the previously described transistor circuit. A matrix of either circuit may be formed into a word organized memory array (Fig. 1, not shown) with the common input output line arranged to serve all the memory elements in one column. If the Fig. 3 circuit is used an additional column line is required for writing in a "0".