Patent GB-1441816-A (GB)
Title: Electronic digital data processing systems
IPC: G06F9/34
Filed: 1973-07-18
Abstract: 1441816 Memory overlay arrangements INTERNATIONAL COMPUTERS Ltd 18 July 1973 [18 July 1973] 34215/73 Heading G4A Information of at least two categories is written into two stacks 25, 26 in a store 11, Fig. 2, the stacks advancing towards each other from respective bases SB, UB as information is added to them. As described, store 11, Fig. 1, is a microprogram store which includes a "primitive interface" 13 of normally permanent microprogram material, the remainder 14 of the store being able to receive overlay blocks 16 of additional micro-program material from a main store 10 which retains master copies 15. The overlay blocks may be in either of two categories, "system" which extends section 13, e.g. for emulation or supervisory functions, and "user" which performs special application tasks, e.g. square roots. When a program requires a particular overlay it issues a call instruction which places a descriptor (overlay type VT and an index value VN) in a register 21. The index value VN is added to the base address VTBA of an overlay table 17 forming part of main store 10 to access an entry 20 corresponding to the required overlay. If the overlay is already in store 11, a VA field of the accessed entry points to the start of the required overlay 16 in store 11 so that it may be utilized immediately by controller unit 12. If the overlay is not in store 11, the VA field of the accessed entry in table 17 is zero and points to the zero location in store 11 which contains a jump instruction to a routine in section 13 for loading the required overlay from main store 10. The overlay load routine checks that there is sufficient space X, Fig. 2 between the stacks to accommodate the new overlay (the length VL of which is specified in its entry 20 in table 17), loads the overlay on to the top of stack 25 or 26 according to the overlay type VT in descriptor register 21, updates the corresponding table 17 entry and top of stack address UP or SP, and, in the case of an added "sytem" overlay, adds one to a count ST representing the number of such overlays in stack 25. If the vacant space X is insufficient to accommodate the required additional overlay, all overlays currently in user stack 26 are removed, table 17 is updated and top of stack address UP set equal to UB. If X is still not large enough, an interrupt signal is generated Overlays may be removed one by one from stack 25 on a lastin first-out basis in response to a special instruction which specifies the number of overlays to be removed under control of a routine in micro-program section 13, table 17, address SP and count ST being updated accordingly. It is also possible to alter the base address SB of stack 25 so that one or more system overlays are temporarily included in the "permanent" section 13 of store 11. Another category of overlays, e.g. emulation overlays, may be written in a third stack in store 11 starting from a base address EB above UB and advancing towards the other stacks. This additional stack may be given priority over the other stacks 25, 26. It is also mentioned that main store 10 and micro-program store 11 may be common to two processors. An interrupt signal 23 may be generated if the table index value VN of a descriptor is greater than the length VTL of the table 17.