Patent GB-1384020-A (GB)
Title: Voltage tunable frequency threshold circuit
IPC: H04L27/156
Filed: 1972-06-15
Abstract: 1384020 Frequency threshold circuits; pulse circuits; digital tsansmission-FSK systems BENDIX CORP 15 June 1972 [12 July 1971] 28107/72 Headings H3A H3T and H4P An adjustable frequency threshold circuit for incorporation in a system, e.g. an adaptive FSK dmodulator, in which the input frequency has an initial value corresponding to that of either of a pair of signal frequencies located on either side of a centre frequency comprises an arrangement 12, 14, 16 (see Fig. 3), for generating a first voltage level inversely proportional to the input frequency which is compared at 18 with a reference voltage level proportional to a threshold frequency and an arrangement 115- 120 (see Fig. 4), responsive to the initial value of the input frequency for sweeping the reference voltage and holding it at a level proportional to the above centre frequency. The frequency threshold circuit (see Fig. 3), comprises a capacitor 68 periodically discharged by a transistor 64 driven by a monostable circuit 14 and charged via a resistor 66 ot produce a ramp voltage having a peak value inversely proportional to the input frequency. The monostable circuit 14 is driven by a further monostable circuit 12 which also energizes an amplitude comparator 18 which compares the instantaneous ramp voltage output with a reference voltage.  A monostable circuit 12 (see Fig. 3), comprises first transistor 40 turned on by the input voltage when a threshold set by diodes 42, 43 is exceeded and which remains latched in the on state by current supplied from a further transistor 36 until the input voltage falls sufficiently negative. As transistor 40 becomes conductive, a third transistor 47 is turned off for a period determined by the charging of a capacitor to produce the desired pulse which is applied to control via a further monostable circuit 14 the charging and discharging of a capacitor 68 in a ramp generator 16. The output of monostable circuit 12 applied via 12b acts as a strobe pulse to energize transistors 70, 72 of a comparator 18 which compares the instantaneous magnitude of the ramp output with a reference voltage applied at 20 only when the strobe pulse is present to provide a yes-no type of output directly or via a flip-flop 22. Speed-up transistors 78, 80 connected to 70, 72 ensure that the output does not change for the duration of the strobe pulse. In an FSK demodulator (see Fig. 4), an initialization circuit 120 inhibits, in the absence of an input signal, a frequency threshold circuit 106, an integrate and hold circuit 118 and a search circuit 117. When a tone signal immediately preceding the message is received, the inhibiting action is removed and the search circuit 117 slowly sweeps a reference voltage from a high value to a low value. At the same time a ramp output of a capacitor having a peak value inversely proportional to the input frequency is compared with a reference voltage in the threshold circuit 106, When the reference voltage is swept to a slightly lower value than the maximum ramp voltage, the sweep signal is disabled and the instantaneous reference voltage is displaced slightly upward to approximate a reference voltage proportional to the centre frequency. A logic circuit 115 applies hold signals to the circuits 117, 118. The output of the threshold circuit 106 may be applied to a majority decision circuit comprising a shift register 110 and a weighting gate 112. The arrangement may also be used in a non-adaptive mode. Fig. 5 (not shown) indicates the actual circuits used in the embodiment of Fig. 4.