Patent GB-1503540-A (GB)
Title: Matrix module and switching network
IPC: H04Q3/52
Filed: 1975-06-20
Abstract: 1503540 Automatic exchange systems PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 20 June 1975 [1 July 1974] 26310/75 Heading H4K A matrix of the type in which the crosspoints, e.g. 204, 205 connected to the same vertical, e.g. 202 have their gate electrodes connected in common to a gate control circuit, e.g. 208 which also has an input connected directly to the same vertical, is characterized by the provision of a selection input 217 and further control logic 214 which logic controls the operation of the gate control circuits. The arrangement is designed for fabrication as a single integrated circuit chip, the crosspoints being PNPN thyristors triggered by enabling a transistor (Fig. 3(b)) or a pair of transistors (Fig. 5b, not shown) connected to the gate of the thyristor. Path finding.-In the following description the number of + or - in front of a voltage indicates its magnitude relative to the other voltages similarly designated, an idle link having a potential-LIP and a busy link a potential + LCP. The network is assumed to have three stages (A, B, C, Fig. 1, not shown). To select a path a free right hand terminal circuit 219 is selected and a mark applied to circuit 234 to cause a potential of --LTP to be applied to diode 233. As the terminal circuit is free diode 233 conducts and the potential on the links connecting the terminal circuit to stage C drops to --LTP. NB. Circuit 219 may be multipled to several C stages. In the C stages to which the mark - - LTP is extended, e.g. on links such as 202, 203, the gate control circuits such as 208, 209 detect the potential --LTP and give an indication via terminal 216 to central control which proceeds to apply a mark to terminal 217 of all the C stages providing the indication. Diodes such as 212, 213 associated with free BC links are thus forward biased and thus the mark --LTP is extended from right to left through the B and A matrices via all free links giving access to terminal circuit 219. A left hand terminal circuit, e.g. 223 producing the mark --LTP is chosen and the marks or the terminals 217 of all the A switches are removed to be replaced one at a time until the mark reappears at the chosen terminal circuit 223. The same standard procedure is repeated for the B and C stages until only one matrix remains marked in each stage. Path switch-through.-Switch 228 in the chosen left hand terminal circuit is closed to apply a voltage +++LMP to link 200. A mark is extended to terminals 218 of all switching stages. In the gate control circuits of the chosen A, B and C stages the presence of the mark on terminal 218, the voltage -LTP on the vertical, e.g. 202 and an enabling voltage from control logic 214 due to the selection mark on terminal 217, causes the voltage applied to the thyristor gates of the corresponding vertical to change from + + + + GIP to + + GMP. In stage A the thyristor 204 is turned on to extend the voltage + + + LMP to the B stages and likewise to stage C. Finally the voltage appears at the emitter of transistor 220 in the chosen terminal circuit to switch it on; the potential on the path switched through then dropping to +LCP. The absence of the voltage --LTP on the links then causes the gate control circuits to return the gates to the potential ++++GIP and the indications on terminals 216 are removed. Various modifications of the arrangement of the control circuits 208, 209, 214, 215 are discussed.