Patent UA-46669-U (UA)
Title: Phased antenna array
Inventor: HULEHA LEONID HRYHOROVYCH
IPC: G06F17/00
Filed: 2009-09-08
Abstract: A phased array comprises M receiving channels each of which includes following series-connected components: an antenna element, a receiving amplifier and an all-pass network, as well as a reference oscillator of harmonic waves, a beam processor comprising M-channel n-digit analog-to-digital convertors united in m groups (byin each) and a digital processing unit. The an all-pass network of each receiving channel is performed as a phase splitter of receiving amplifiers output signals, which splits signals to in-phase and quadrature components, “in-phase” inputs of phase splitters of M receiving channels are connected to each other and to "cos" output of the reference oscillator of harmonic waves, ”quadrature”(QUADR) inputs of phase-splitters are connected to each other and to “sin” output of the reference oscillator of harmonic waves output of which ” Signal of heterodyne” (Sg.Get.) is connected to heterodyne inputs (Get.inp.) of receiving amplifiers connected to each other, the digital processing unit for the beam processor is performed as a control device including a multiphase clock oscillator, a modulo J counter of beam number with input being connected to F2 output of the multiphase clock oscillator, F4 output of which is connected to sync inputs ofchannel analog-to-digital converters, an arithmetic unit comprising m adders ofphased, n-bit channel signals as m devices of-bit addressed permanent memory (PM) of partial sums, address inputs of m adders are connected by-bit buses to n outputs of channel analog-to-digital converters of corresponding groups. Sync inputs are united and connected to F5 output of the multiphase clock pulse generator, the adder of m counts ofpartial sums as a device of-addressed permanent memory ofcounts, input of which by- bit wide bus is connected to- bit inputs of m group adders, sync input is connected to F6 output of the multiphase clock generator,-bit output is output of the antenna array,-channel digit-analog phase changers are additionally incorporated in the beam processor, each of which comprises a time digitizer of in-phase signal and a time digitizer of quadrature signal connected by inputs correspondingly to sync and quadrature outputs of corresponding receiving channel, strobing sync inputs of sync and quadrature signals of digitizers are united and connected to strobing sync inputs of digitizers of digit-analog phase changers of other receiving channels and connected to F1 output of the multiphase clock oscillator, as well as comprising a first and a second digitally controlled attenuators having analog inputs connected correspondingly to outputs of the time digitizer of in-phase signal and the time digitizer of quadrature signal, PM of complex coefficients of amplitude-phase distribution of the corresponding receiving channel connected by output of low-order digit (including real part of complex coefficients of amplitude-phase distribution) to control input of the first digitally controlled attenuator and high-order digit (including imaginary part of complex coefficients) to control input of the second digitally controlled attenuator which is connected by addressing input to addressing inputs of PMs of phase changers of other receiving channels and connected by “Reading” sync input to output of the beam number counter, connected to PM sync input “Reading” of complex coefficients of amplitude-phase distribution of receiving channels phase changers and F2output of the multiphase clock oscillator, as well as comprising an analog signal adder, inputs of which are correspondingly connected to outputs of the first and second digitally controlled attenuators, output is connected to input of corresponding channel analog-to-digital converter.