Patent GB-1432222-A (GB)
Title: Superheterodyne receivers
IPC: H03J1/04
Filed: 1973-04-05
Abstract: 1432222 Digital tuning display; measuring frequency SIEMENS AG 5 April 1973 [10 April 1972] 16239/73 Headings H3Q and H3H In a superhet receiver having a digital display R1-R5 of the receiving frequency, a counter having cascade stages Z1-Z5 counts the oscillations of the local oscillator 3 and takes into account the frequency displacement f ZF  of the local oscillator frequency in relation to the receiving frequency. A carry pulse is fed from one stage to the next when any one stage has complated a cycle and a correction circuit 14 is controlled from the output of a selected counter stage Z3 to cause the final count to indicate the received frequency by blocking the following counter stage or stages Z4, Z5 to reduce the final count as necessary by means of a blocking signal during the occurrence of a predetermined number of carry pulses P proportional to the frequency displacement if the local oscillator is operated at a frequency above the receiving frequency or to cause the following counter stage or stages Z4, Z5 to be supplied with an appropriate number of additionally produced counter pulses after the occurrence of the first carry pulse to increase the final count as necessary if the frequency of the local oscillator is operated at a frequency below the receiving frequency. As shown the output of the local oscillator 3 is applied to the counter stages Z1-Z5 via a Schmitt trigger 8 and a NAND gate 9 during the presence of a gate pulse 11. With stages Z1- Z3 and Z5 reset and stage Z4 blocked by the output from the connection circuit 14 carry pulses P are counted by a counter stage 16 and JK flip-flops 17 and 18. In a receiver where the local oscillator frequency is above the receiving frequency when a given number of carry pulses P proportional to the intermediate frequency displacement Z F  have been counted the change in putput of the connection circuit 14 unblocks stage Z4 so that the final count output from the stages Z1-Z5 is fed via decoders D1-D5 to digit display tubes R1-R5 which displays the receiving frequency. If the connection circuit 14 has not completed its count by the end of the gate pulse 11 an incorrect receiving frequency is displaced and the counter stage 16 is not reset. Incorrect display can be avoided by keying the display means R1-R5 only to be illuminated when the blocking signal is disconnected from 13. To obtain reliable resetting of the counter stage 16 a modification is disclosed (Fig. 2, not shown) so that the stage 16 is reset by a common resetting and blocking signal applied at 12. The components of the connection circuit 14 can be arranged on a plug-in circuit board or a separable component forming part of an integrated semi-conductor circuit. When the connection circuit 14 is removed the local oscillator frequency is displayed. In an alternative receiver circuit where the local oscillator frequency is below the receiving frequency one or more counter stages are supplied with a number of additional generated counter pulses proportional to the frequency displacement Z F  after the occurrence of the first carry pulse P of the controlling counter stage so as to display the received frequency.