Patent GB-1153420-A (GB)
Title: Improvements in Data Processing Systems
Inventor: ARULPRAGASAM JEGANANDARAJ AMAL
IPC: G06F9/48
Filed: 1968-05-10
Abstract: 1,153,420. Computer interrupt. INTERNATIONAL BUSINESS MACHINES CORP. 10 May, 1968, No. 22177/68. Heading G4A. In a data processing system, an interrupt condition causes the status of the current programme to be stored in a first area, a second area to be allocated to a new programme, and the address of the first area to be entered into the second area. In a two-processor microprogramme-controlled system, the highest priority interrupt request not masked by a status register selects a double-word from a (stored) interrupt list according to the class of interrupt. The doubleword includes a bit-pair and an address. If the bit-pair is 01, 10 or 11, the address is that of an interrupt class list. If the bit-pair is 01, the interrupt code (which gives details of the interrupt) is shifted and used to select another double-word from the interrupt class list. If the bit-pair is 10, the interrupt code is decremented by a so-called "mask" in the interrupt class list and one of two double-words selected from this list according as the result is negative or not. If the bit-pair is 11, the interrupt code is ANDed with the "mask" and one of the two doublewords selected according as the result is zero or not. If the bit-pair is 00, the address is that of a status load block. In this way a sequence of one or more double-words is selected until one is reached with the bit-pair 00 to obtain the address of a status load block. In the above, if the interrupt code is decremented, it is the decremented interrupt code which is used, if necessary, in connection with the next double-word, but if it is ANDed, it is the code before ANDing which is used. The status load block is used to initialize the system to execute the programme for dealing with the interrupt, after storing the current status data (relating to the interrupted programme) in a current programme status block (storage area), to enable subsequent resumption of the interrupted programme. A programme status block is obtained for the new programme, the address of this block being obtained from the head of the interrupt list which specifies the address of the first block of a free list of such blocks, each block in the list containing the address of the next so that they are chained together. The "first block" address in the interrupt list is then updated. While the interrupt list is being used by one processor, a lock byte and the identity of the processor are stored in it (the list) to prevent the other processor using it and to enable this processor to find out why use is prevented. The programme status block (which is loaded With status data for its programme when that programme is interrupted) holds interrupt masking bits, storage protection key (for comparison with a key associated with each block of storage to prevent access unless they are equal or one is zero), instruction length indicator, indication of conditions which will cause branch, next instruction address, indications of which local storage registers have had their contents saved (determined by the doubleword with bit-pair 00 referred to above), addresses of locations where various registers can be dumped in the event of an interrupt, the address of the programme status block of the previously running programme, class of interrupt, identity of processor to which the current interruption is related, interrupt code, and extended interrupt code giving more information on the interrupt. Provision is made for dealing with exhaustion of the free list. Conventional types of interrupt are described. The interrupt list, interrupt class lists and status load blocks are settable under control of a supervisor programme. Besides the two processors, the system includes two memories with a unified addressing scheme and the effective configuration of the system is controlled by configuration control data stored in the various units.