Patent GB-1486900-A (GB)
Title: Data processing system
IPC: G06F9/46
Filed: 1974-11-28
Abstract: 1486900 Data processing COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL 28 Nov 1974 [30 Nov 1973 (3)] 51652/74 Heading G4A In a data processing system an instruction switches the operating mode of a process from a first mode to a specified function in a second mode. A non-native mode may be entered from the native mode of the processor in response to a 32 bit native mode instruction called the execute decor extension instruction EXDE. Bits 0-7 are the OP code for the instruction. Bits 8-15 define the DEXT field, i.e. decor extension number (not zero, zero indicating an illegal condition) and represent emulation of different types of processor. Some numbers may indicate for example an additional hardware option not normally included in the system. The 8 bit field corresponds to 256 locations in a decor extension table, each location indicating, if a 1 bit is stored, that a specified function is allowable. Bits 16-31 are the DEA field and act as the input to the specified decor extension hardware. This field may have two sub-fields, bits 16-23 being an OP code and indicating for example that data must be moved from one register to another and bits 24-31 finding the route for the transfer. The system provides data and procedure protection by preventing processes from interfering with each other or sharing address space in an unauthorized manner. Processes use a segmented address, hardware checking that the address is part of the space assigned to the process. Each process has its own process control block in main memory used to save CPU status. It is accessed from the system base the latter including a job step number, a process group number (for the currently running programme) and a pointer for indirectly addressing the process control block. The block includes process main words for use with the decor extension instruction, these being examined to see if processing in the required extension mode is allowed. The central processor unit.-The control unit in the central processor unit includes a control store unit 1301 (Figs. 7a, 7b) receiving microinstructions from a control store loader 1303 via a control and load unit 1304 and a control store interface adaptor 1302. Four modes of operation of the CPU are available (1) native mode, (2) emulation mode, (3) concurrent native and emulation mode and (4) diagnostic mode. Also within the CPU are an emulation unit 1316, an arithmetic/logic unit 1317, an instruction fetch unit 1318, a data management unit 1321, an address control unit 1319, general registers 1307, base registers 1308 scratch pad registers 1309 and miscellaneous registers. The general registers are used to manipulate fixed point binary numbers and consist of 16 32-bit registers. The base registers are used during address computation and comprise 8 32-bit registers. The scientific registers comprise four 8 byte registers and the miscellaneous registers include an instruction register, status register stack register, boundary address register and a hardware mask. The control store comprises an integrated circuit read-only memory and a read/write random axis store, each location holding one 84-bit microinstruction controlling I CPU cycle and decoded to provide control signals. The data management unit 1321 provides the interface between the CPU and the main memory/buffer store. The instruction fetch unit includes a 12 byte register normally holding more than one instruction. The address control unit 1319 includes an associative memory 1319a storing the base address of the eight most recently used memory segments together with their segment members and examined at every memory request to determine if the base address of the required segment is stored. Dispatcher.-The dispatcher is a firmware/ hardware unit which manages the queues of processes and switching between processes and delivers messages to waiting processes. When a process is waiting in the ready queue and a process is currently running on the CPU dispatcher determines which has priority by fetching the priority byte of the current process either from the system base or from the process control block for comparison with the priority of the process at the head of the ready queue. If the current processor has priority and is running in decor extension mode the next instruction is executed in emulation mode. Otherwise the next instruction is run on native mode. If the waiting process has priority a firmware sub-routine first controls the rolling out of the current processor, relevant data being stored in the CPU registers before the new process is rolled in. The hardware of the CPU is then supplied with control information from the process control block of the new process. Execution of an FXDE instruction.-On receipt of this instruction by detector 1518 (Fig. 11) the DEXT and DEA fields are temporarily stored in buffer 1520. The DEXT field is compared with zero and if there is no comparison gates 1530, 1532 are enabled to cause read out from process control block 400 of DETSZ field (which defines the number of possible entries in the decor extension table) and DETA field (which gives the absolute address of the decor extension table) to buffers 1534, 1536. The sizes of the DEXT and DETSZ fields are compared and as long as the DEXT field is the smaller, gates 1544, 1546 are enabled to permit selection of the appropriate bit in the decor extension table 1548. Provided the selected bit is not zero gate 1554 is enabled to permit comparison of the DEXT number with the numbers 1, 2 ... M, at comparison OR gate 1566 being enabled to enable AND gate 1570, 1572 to permit read out of the OP code and DEA argument from buffer 1520 to the emulation unit. The OR gate also primes AND gate 1568 so that the DEXT number can be stored in a process control block 400 if a further signal on line 1574 is received indicating that the non- native mode is to be entered for more than one instruction. This enables the DEXT number to be saved if an interrupt occurs.