Patent GB-902449-A (GB)
Title: Incremental computers
Inventor: OWEN PHILLIP LANCE
IPC: G06F7/66
Filed: 1960-05-23
Abstract: 902,449. Digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. May 23, 1961 [May 23, 1960], No. 18178/60. Class 106 (1). The invention relates to a consecutive binary digital incremental computer in which each integrator has its own integrand and remainder stores, but time-shares an arithmetic unit with the others. The computer includes first and second sets of connector terminal groups, a separate group of each set being associated with each integrator and means for controlling during integrator selection periods the passage of incremental signals from selected integrators as incremental inputs to another integrator in accordance with timing pulses derived from the first set of connector terminals and received by correspondingly selected groups of connector terminals in the second set. As described, a consecutive computer having n integrators has groups SI1 to SIn and further groups SO to SOn of connector terminal sockets, the eight sockets in each group SO1 to SOn being connected together in parallel and the outputs applied to " and " gates G1-Gn whose other inputs are supplied by triggers T1-Tn which act as stores for the single digit #z integral incremental outputs of the various integrators under the control of servicing period pulses I1 to In produced by a control pulse generator (not shown). At the beginning of its servicing period, the corresponding trigger is put off and is put on if a positive increment #z is supplied from the arithmetic unit (not shown). The outputs of the gates G1 to Gn are applied through an inhibiting gate H1 to a reversible #y counter C and through a gate Gx to a trigger Tx. Each group of sockets SI, Fig. 2, is supplied with a corresponding selection period pulse A1, A2, &c., Fig. 4, and gates Ga-Gh are supplied with respective pulses D1-D8, Fig. 4. To select an incremental input for an integrator, a plugged lead is connected from an appropriate socket in the group SI1 to SIn associated with the integrator to which the increment is to be fed to any one of the sockets in that group SO1 to SOn associated with the integrator from which the increment is to be taken. If the incremental input is of the independent variable #x, the connection is made to the appropriate socket S1, and the increment is stored in the trigger Tx which is put on for a positive increment to condition a buffer store (not shown) in the arithmetic unit. The reversible counter C is reset and its contents transferred to the arithmetic unit early in each selection period for use in the corresponding servicing period. If  an integrand increment is desired, a connection is made from any one of the sockets S2 to S8 in a selected group SI1 to SIn to which the increment is to be fed to any one of the sockets of a selected one of the group of sockets SO1 to SOn corresponding to the integrator from which the - increment is to be taken. The counter C then steps on or back by one unit according to the sign of the increment digit #z. By connecting up to seven of the groups of sockets SO1 to SOn to the group SIn up to seven increments stored in the triggers T1 to Tn may be transferred. Modifications.-The groups of sockets SI1 to SIn may have twelve sockets in each group (Fig. 5, not shown), four of the sockets being fed with the selection period pulse A appropriate to the group. An arrangement similar to Fig. 1 but modified for ternary transfer of increments instead of binary is described (Fig. 6, not shown). Specifications 717,114 and 892,750 are referred to.