Patent GB-1359979-A (GB)
Title: Input transient protection for complementary insulated gate field effect transistor integrated circuit device
IPC: H01L27/02
Filed: 1973-03-27
Abstract: 1359979 Semi-conductor devices RCA CORPORATION 27 March 1973 [27 March 1972] 14689/73 Heading H1K An integrated circuit device 32<SP>1</SP> includes IGFETS 12<SP>1</SP>, 14<SP>1</SP>, in a surface 36<SP>1</SP> of an, e.g. N-type semi-conductor body having respective source and drain regions 38<SP>1</SP>, 39<SP>1</SP> (P+ ) and source and drain regions 42<SP>1</SP>, 43<SP>1</SP> (N+) in a diffused, e.g. P-type well; gate electrodes 20<SP>1</SP>, 22<SP>1</SP> being spaced from the body by insulant layers 44<SP>1</SP>, 45<SP>1</SP> and N+, P + guard rings being provided. A N+ region 68 of similar conductivity to the body defines an elongated resistor region and is formed simultaneously with regions 42<SP>1</SP>, 43<SP>1</SP> and is disposed within a P-type region 69 formed simultaneously with the well to give a PN junction 70 between 68, 69 and another 71 between 69 and the body. An N+ region 72 in region 69 defines a PN junction 73, and is connected over a surface conductor 74 to a N+ region 75 defining a PN junction 76 in the well; the gates 20<SP>1</SP>, 22<SP>1</SP> being interconnected over 77 to region 68 whose other end is connected over 78 to an input terminal (not shown). In detail (Fig. 4) region 68 is elongated at 80 and with end enlargements 81, 82 to which contact is made; which provide high capacitance for PN junction 70 between regions 68, 69; to establish a preset RC time constant for protection means 66 exceeding the expected duration of transients destructive of the gate insulant. In operation (Fig. 5) transistors 12<SP>1</SP>, 14<SP>1</SP> utilized as a complementary pair inverter are series connected between terminals 16<SP>1</SP>, 18<SP>1</SP> supplied with voltages V DD , V ss  with drains 12<SP>1</SP>, 141 interconnected to output 23<SP>1</SP>, while input 24<SP>1 </SP>is connected to gates 20<SP>1</SP> 22<SP>1</SP> over resistor 84 defined by region 68. Protective means 66 comprises PN junction 70 which defines a distributed diode represented by diodes 85 . . . 86 whose anodes defined by region 69 are anodic of a further diode 87 at junction 71 of regions 69 and the body, returned to terminal 16<SP>1</SP>. P-type region 69 provides the anode of diode 88 at the PN junction 73 between 69 and 72, backed by diode 89 at PN junction 69 between region 75 and the well; so that diodes 85-86 and 88 are back to back across the insulant of transistor 141. A destructive positive pulse between input 24<SP>1</SP> and terminal 16<SP>1</SP> reverse biases diode 85-86 to breakdown at a given voltage. and the voltage across the insulant of transistor 12<SP>1</SP> is limited. If the transient is positively applied between terminal 18<SP>1</SP> and input 24, diode 88 conducts at its reverse breakdown voltage and limits voltage across the insulant of transistor 14<SP>1</SP>; the diode 89 preventing clamping of region 69 to V ss  during positive input excursions above breakdown. Input voltage is allowed to swing by the full N+ to P breakdown voltage above and below the respective values of V DD  and V ss . The device is applicable to the protection of other COS/MOS circuits.