Patent GB-1402809-A (GB)
Title: Semiconductor circuit elements
IPC: H01L27/07
Filed: 1973-11-23
Abstract: 1402809 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 23 Nov 1973 [20 Dec 1972] 54512/73 Heading H1K [Also in Division H3] A switching transistor T 1  (Fig. 2) has emitter terminal E and collector C forming output logic circuit, and complementary transistor T 2  with collector and base respectively connected to base and emitter of T 1 , which is a Schottky collector transistor with emitter P 1  base N 2  and Schottky barrier contact M 0  as collector on the base zone. Further Schottky barrier contacts M 1  to M n  on the base zone define diodes D 1  to D n , whose free electrodes are connected to logic input terminals B 1  to B n . The Schottky collector transistor T 1  operating as a switching transistor is current energized from transistor T 2 , forward biased between terminals E and S as a constant current source injecting current over its collector N 2  into the base N 2  of T 1 . Logic "0" potential at which diodes D 1  to D n  are blocked is applied to each logic input B 1  to B n  to produce an impressed current into the base of T 1 , which conducts; and logic "1" signal appears on collector terminal C. When logic "1" potential at which diodes D 1  to D n  conduct is applied to one or several inputs B 1  to B n , the impressed current is discharged through the conductive diodes, Schottky collector T 1  is blocked, and a logic "0" potential appears on collector terminal C so that the circuit produces a "NOR" function, and plural basic circuits may be combined into complex logic networks. Plural collector terminals C of different such basic circuits may be combined to produce an "OR" function. In Fig. 4, three basic circuits are combined as an inverter chain having Schottky collector transistors T 11 , T 12 , T 13  as switching transistors with potentials on common terminals E, S and constant current in transistors T 21 , T 22 , T 23 . Each basic circuit has an input diode D 11 , D 12 , D 13  connected to input terminal B 11 , B 12 , B 13 ; and the output collector terminals C 1 , C 2 , C 3  are linked with the subsequent inputs. Logic "1" signal is applied to input B 11  and transistor T 11  is blocked for logic "0" signal on output C 1  and input B 12 . Transistor T 12  conducts for logic "1" on output C 2  and input B 13 . Consequently transistor T 13  is blocked for logic "0" at output C 3 . Structurally in the basic circuit (Fig. 5) a semi-conductor layer N 1  is overlain by an opposed conductivity layer P 1  and a similar conductivity layer N 2 , with Schottky contacts M 1  to M n  forming diodes D 1  to D n  positioned on layer N 2 . Also thereon is Schottky collector contact M c  and layers P 1  and N 1  are ohmically connected to terminals E, S; layer N 1  forming emitter of T 2 , layer P 1  the base of T 2  and emitter of T 1 , and layer N 2  the base of T 1  and collector of T 2 ; to define P 1 N 1 M c  Schottky collector switching transistor T 1  and complementary N 1 P 1 N 2  transistor T 2  with input decoupling diodes (Fig. 2). In a modification (Fig. 6) layer N 2  is mesa etched in isolation zones I, I<SP>1</SP> with a partial region N 2 <SP>1</SP> accommodating the diode Schottky contacts and a partial area N 2 <SP>11</SP> accommodating the collector Schottky contact. A buried highly doped N<SP>+</SP> zone underlies partial area N 2 <SP>1</SP> and extends into partial area N 2 <SP>11</SP>, and layer P 1  is contacted over highly doped contact zone P<SP>+</SP> intersecting layer N<SP>2</SP>. Insulant material, e.g. semi-conductor oxide may fill the isolation zones (Fig. 7, not shown). Partial areas N 2 <SP>1</SP>, N 2 <SP>11</SP> may be separated by a N<SP>+</SP> semi-conductor frame zone surrounding partial area N 2 <SP>1</SP> and a P<SP>+</SP> frame zone surrounding the entire structure and contacting the intermediate P 1  layer (Fig. 8, not shown). The first semi-conductor layer N<SP>+</SP> is replaceable by a similar semi-conductor zone within a P<SP>+</SP> isolation frame zone in semi-conductor zone N 2  so that the vertical N 1 P 1 N 2  transistor T 2  is replaced by a lateral N 1 <SP>1</SP>P 1 N 2  transistor (Fig. 9, not shown).