Patent GB-1372012-A (GB)
Title: Binary counting means
IPC: H03K23/44
Filed: 1972-12-06
Abstract: 1372012 Electronic counters NCR CORP 6 Dec 1972 [7 Dec 1971] 56314/72 Headings G4D D7X D6Y D6C1 and D6C2 A binary counter of a kind comprising a recirculating shift register of N stages arranged to count through 2<SP>N</SP> states is provided with a de-coder 32 which provides an output to set a bi-stable circuit 36 when the full count is reached. The counter employs four phase logic circuitry with MOSFETs; this involves four differently phased signals (# 1 -# 4 ), Fig. 2 (not shown), a pulse of each of which occurs during one clock period. Four basic logic circuits, Figs. 3-6 (not shown), are described two of which provide an output after a delay of half a clock period (Figs. 3, 5), while the others provide an immediate output (Figs. 4, 6); the gates may be coupled only in a certain order, Fig. 7 (not shown). Fig. 8 shows a particular example of the (Fig. 3) gate connected to a particular example of the (Fig. 5) gate to produce a logic function one clock period after the inputs appear. Each gate comprises an (upper) load transistor connected to the # 1  or # 3  signal a (middle) isolation transistor connected to the # 2  or # 4  signal and a (lower) group of transistors providing the logic function. In the first gate transistors in series 144, 146 provide an AND operation while those in parallel, 148, an OR operation. All four gates cause inversion so the second gate in Fig. 8 with a single logic transistor is simply an inverter. Suitable logic equations are given for each stage of the counter shown in Fig. 1 and it is stated that all may be provided by the basic circuits.  The counter comprises an eight-stage shift register 14-28, the contents of which is shifted (to the right) once each clock_period. The true and inverted outputs B1 and B1 of the lowest order stage 28 are returned to the inputs of the highest order 14 and one or other is shifted in depending on whether a latch circuit 30 is reset or set. If there is no input to the counter, B1 is shifted to B8 in each clock period. If an input is applied at ADD when a timing pulse TB8 (once every eight clock periods) is present the latch 30 is set; it is reset by the next zero state shifted from B1. Thus, if the counter is empty (B1-B8 all zero) then the next time a TB8 signal appears with an ADD input the latch 30 is set and in the next clock period B1 is shifted to B8 which becomes 1 and the latch 30 is reset. After seven more clock periods this 1 state reaches B1; the counter can than be read out as 00000001. In the next clock period another TB8 signal appears and if there is a further input at ADD the latch 30 is again set so that in the next clock period B1 is transferred to B8 which becomes 0 and the latch remains set. And in the next clock period Bl is shifted to B8 which becomes 1 and the latch 30 is reset. At the end of the second cycle the counter reads 00000010. If there is then a further input B8 again becomes 1 and the latch is immediately reset so at the end of the third period the counter reads 00000011 and so on. Thus the counter counts clock periods while a continuous 1 state appears at ADD. After 255 counts all B1-B8 are 1. A de-code latch 32 is arranged so that if B1 remains 1 for a whole cycle (eight clock periods) then at next TB8 the latch is set and a B9SET signal is produced to set B9 latch 36. The next time the counter is full B9SET is again produced to reset B9 latch through logic 34 and set a B10 latch. The third time B9 latch is again set and the fourth time a reset signal is produced by an AND gate (not shown) to reset both B9, B10 latches so the whole counter returns to zero after 1024 clock periods. Further latch circuits 36, 38 can be added in like manner.