Patent GB-1066246-A (GB)
Title: Improvements in or relating to coincident-current memory matrices
IPC: G11C11/06
Filed: 1963-09-20
Abstract: 1,066,246. Circuits employing bi-stable magnetic elements. NIPPON ELECTRIC CO. Ltd. Sept. 20, 1963 [Sept. 22, 1962 (3)], No. 37133/63. Heading H3B. [Also in Division G4] In order to compensate, in a coincident current memory, for the difference in the propagation times of drive pulses from the driver to the memory elements and from the memory elements to the sense amplifier, delay means are incorporated to delay the appropriate pulses. Memory matrix 32 is provided with a 4-bit word address selection register 1 connected to decoders 5, 6 associated with coincidence circuits 16 to 31 so that under the control of a pulse from generator 11 only one of the corresponding circuits a to p and hence of address wires 33 of the matrix are energized. Reading in information to the memory is achieved by supplying coincident currents to the appropriate write line a to p and drive lines 34, 35, 36, 37. Since the propagation times of the pulses from the drivers 39, 40, 41, 42 along the drive lines depend upon the position of the magnetic cores at the intersection of the wires, the coincident pulses may not be in fact coincident, Fig. 3 (not shown). Similarly, during read out, the pulses induced in the wires 34 to 37 by applying read-out pulses to selected groups of four cores 38 have different propagation times along the digit drive wires dependent on the position of the cores switched, so that the outputs of the sense amplifiers 75 to 78 may arrive at gates 79 to 82 after the gating pulse from delay 47 with the result that an incomplete output signal is obtained, Fig. 2 (not shown). The above difficulties are overcome by varying the times at which the driving pulses are applied to the different groups of the wires a to p. In the arrangement of Fig. 4 the delay circuit 47 of Fig. 1 is replaced by the arrangement shown within the broken line rectangle which provides a different delay between the wires 48 and 49 depending upon which of the word drivers 7, 8, 9, 10 is energized. The four outputs 59 to 62 of the decoder 5 corresponding to drivers 7, 8, 9, 10 are connected as shown to AND gates 54-57 so that during read out the delay of the gating pulse applied to line 49 from 48 and thence to gates 79 to 82 depends upon which of the drivers 7 to 10 is energized, i.e. the delay is shortest for coincident circuits a to d and longest for circuits m to p. During writing in of information the signal in wire 48 passes through wire 48a and single delay line 50a to reach gate 57, through two delay lines 50a and 53 to reach gate 56, with the result that irrespective of which group of wires 33 is energized the pulses from drivers 39 to 42 arrive at the respective elements coincident with pulses from drivers 7 to 10. In the embodiment of Fig. 5 (not shown) the delay between wires 48, 49 is determined using the most significant digit of register 1. In the arrangement of Fig. 6 (not shown) the time for opening the gates for signal selection or the time for operating the digit drivers is fixed whilst the timing pulse from the control pulse generator (11) to be supplied to the driving pulse current generating circuits (7) to (10) is caused to vary successively. The total delay provided by the lines (68), (69), (70) is substantially equal to the pulse propagation time along a digit wire from block m to p to block a to d so that the times of signals arriving at the sense or read-out amplifiers (75) to (78) become substantially constant with no relation to the position of the memory cores to be read out. For writing in purposes connection (48a) is made so that the delay is increased from driver (7) to driver (10). The sense amplifiers may have their effective threshold levels varied, Fig. 9 (not shown), or the gain of a preamplifier preceding a threshold amplifier may be adjusted. The matrix may be a code translating matrix, a control signal generating matrix, or a fixed memory. Reference has been directed by the Comptroller to Specification 1,017,600.