Patent GB-1201277-A (GB)
Title: Method and apparatus for testing jitter
IPC: G01R29/26
Filed: 1967-12-19
Abstract: 1,201,277. Testing jitter. INTERNATIONAL BUSINESS MACHINES CORP. Dec.19, 1967 [Dec.29, 1966], No.57737/67. Heading G1U. The specification describes a system for testing "jitter" produced in pulse trains passing through a device such as a magnetostrictive delay line, fitter being defined as the variation in pulse delay through the device which is dependent upon the pulse sequence in a serial pattern of pulses. To test the device a train of constant frequency constant width reference pulses is produced and synchronized with this a serial pattern of input pulses selected to provide maximum jitter conditions is also produced. This serial pattern is applied to the device in a green phase relation between the reference and input pulses. The pulses at the output of the device are standardized in width, the reference pulse width being preselected to this standardized width plus the maximum allowable jitter. The phase relation between the reference and input pulses is successively changed, by relatively delaying the reference pulses, and it is determined if there is a phase relation at which no part of an output pulse occurs before or after the corresponding reference pulse. Clock pulse are derived from the generator 2, 17 and passed to a main pattern generator 3 and variable delay line 15. The pattern from the generator 3 consist of series of pulse trains of sixteen bit positions in sequence such that all possible combinations of the sixteen bits are produced, to ensure maximum jitter conditions. The series is passed through the magnetostrictive delay line under test 4 to the pulse width standardizer 5. An inverter 7 and second standardizer 6 may be incorporated in parallel with the standardizer 5 for use where the pulse train is of the non return to zero type. The outputs from the standardizers are negative and are passed to one input of an AND invert circuit 9. The pulses tapped from the delay line at 18 are passed via a level detector to a blocking pulse generator, which produces positive reference pulses whose width is controlled by a calibrated delay 20 such that the pulses are the width of those from the standardizers 5 or 6 plus the maximum permissible jitter. These blocking pulses are applied to the other input of the AND invert circuit 9. Provided that jitter is not excessive, the blocking pulses will cover all the standardized output pulses from the line in at least one position of the delay line tap 18. Any output from the circuit 9 shows that the blocking pulses do not fully cover the output pulses and is used to actuate an advance motor control circuit 25 so that this produces an output pulse which energizes the control circuit 26 to operate the stepping motor 16 and change the position of the delay tap 18. The presence or absence of jitter is detected in a circuit 27 where the output from the AND invert circuit 9 is observed between successive pulses from a cycle timer 30 which indicate the beginning and end of a full cycle of the test pattern. If no jitter is detected, the forward reverse trigger 28 is actuated to operate the motor control to step the tap 18 back to its initial position. The forward and reverse stop circuits 34, 32 respectively produce output when the tap reaches its extreme positions, to set the trigger 28 to an appropriate state. Should the tap 18 reach the end of its travel and the trigger 28 reverse without a no fitter condition being detected a filter detector latch is energized to indicate that the delay line has failed the test. More detailed logic circuits are described, particularly for the pattern generator Figs.2a-2d (not shown).