Patent GB-1158897-A (GB)
Title: Space-Charge-Limited Current Triode Device
IPC: H01L29/00
Filed: 1966-10-24
Abstract: 1,158,897. Space-charge-limited current triode. HUGHES AIRCRAFT CO. 24 Oct., 1966 [12 Nov., 1965], No. 47654/66. Heading H1K. A space-charge-limited current triode device comprises a body of semi-conductor material, said body including a source region and a drain region both of a first conductivity type separated by a gate region comprising one or more intrinsic portions, and means for providing electrical connections to each of said source, drain and intrinsic gate portion or portions, the device being such that when suitable electric potentials are applied to said source region, said drain region and said intrinsic gate portion or portions a depletion layer is set up in said source region adjacent said gate region and majority carriers flow across said depletion layer and said intrinsic gate portion or portions from said source region to said drain region under space-charge-limited conditions, the magnitude of the current resulting from said flow of majority carriers being dependent upon the width of said depletion layer across which they must flow, and said width being dependent upon the magnitude of the potential difference between said source region and said intrinsic gate portion or portions. An N-type silicon body 4 is degeneratively doped 2 to form the source. A rectilinear grid of P <SP>+</SP> -type regions 6 are then diffused in through an oxide mask. Alternatively the grid 6 may be circular. Etching with HC1 at 1000-1200 C. produces intrinsic gate regions 6<SP>1</SP>. A layer 4<SP>1</SP> of N-type Si is epitaxially deposited by decomposition of PCl 3  and SiCl 4  in H 2  at 1200 C. during which further diffusion of the P<SP>+</SP> -type regions 6 into the gate regions 6<SP>1</SP> occur and the regions 6 become spherical. An annular P<SP>+</SP> -type region 10 of boron impurities is diffused in to provide a contact for the gate region 6, 6<SP>1</SP>, by oxide masking techniques. A drain 8 is formed using further oxide masking techniques with arsenic as the impurity. Alternatively Au/Sb alloy may be alloyed on the surface of the device to form drain 8. The upper surface of the device is re-oxidized and portions of it etched with HF to provide exposed regions for electrical contacts. The contacts may be made by vapourdeposition, soldering, thermo-compression or pulse-bonding. In another embodiment (Fig. 9, not shown) the gate 6<SP>1</SP> may be a layer of intrinsic Si formed by epitaxial deposition on or by out-diffusion of region 4. A mesa configuration (Fig. 10, not shown) may be made wherein the regions 4, 6, 6<SP>1</SP>, 4<SP>1</SP>, and 8 form the raised portion and the connections to the gate are made at the side of the body and not the top. The electrical characteristics of the device are described with the aid of a Fig. 11, (not shown). It is stated that since the device includes a NPN structure it may be operated either as a space-charge-limited triode or a bipolar transistor simply by reversing the negative input voltage polarity to a positive one. The bipolar operation is only possible below the punchthrough voltage.