Patent GB-1228854-A (GB)
IPC: H01L21/8222
Filed: 1968-05-10
Abstract: 1,228,854. Semi-conductor devices. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 10 May, 1968 [13 May, 1967], No. 22279/68. Heading H1K. The invention relates to a method of making a lamina which consists locally throughout its thickness of silicon and elsewhere of silicon oxide and has at least one junction forming part of a semi-conductor component extending throughout the thickness of the silicon perpendicular to the faces of the lamina. The oxide parts of the lamina, which in the finished article is carried by a support, are formed by selectively oxidizing the surface of a silicon layer which forms or previously formed the surface of a thicker semi-conductor body. The lamina may be formed from the epitaxial N type layer of an NN + silicon wafer either by selectively oxidizing the N face or by providing a support for the body on that face, reducing the body thickness to that of the desired lamina by grinding or etching from the N+ face and then selectively oxidizing throughout the thickness of the remaining material. The support may consist of polycrystalline silicon vapour deposited over an intermediate layer of oxide. In both processes the layer to be selectively oxidized is coated first with silicon nitride by reaction of gaseous silane and ammonia and then with silica. The nitride is formed into a mask by patterning the oxide using photoresist and etching steps and etching away the exposed nitride areas with phosphoric acid. Steam is then passed over the layer to oxidize the silicon areas exposed through the mask. This is done in two stages, the first of which is followed by etching in hydrofluoric acid. To form the junctions impurity may be diffused through further apertures formed in the nitride layer, but it is preferred to remove the nitride entirely and then form an oxide mask for the diffusion of boron in the case where the N + layer is still present at this stage. Interconnections between some of the semiconductor zones may next be made by deposition and back etching of aluminium. The treated surface is next heat pressed to a support of glass, alumina or oxide-coated silicon 12 using powdered polyvinyl acetate 32 as adhesive. Since the diffused regions extend well below the oxide layer 9 removal of silicon down to this layer leaves junctions 8 extending perpendicular to the faces of the lamina. Electrolytic and chemical etching are used to remove the N+, and oxide and N layers, respectively to give the structure shown in Fig. 2 consisting of an interconnected pair of transistors with exposed contact pads, two 21, 25, of which are shown in the Fig. Silicon oxide is finally deposited over the lamina and further interconnections, possibly crossing those on the other face may be provided on the oxide. Where the silicon is reduced to lamina thickness before the selective oxidation the diffusion and/or provision of interconnections on one face may be effected before attachment to a support as described above, the interconnections being made of tungsten if provided before the diffusion steps. Essentially similar processes to produce IGFETs with two gates, one on each face of the lamina, and JUGFETs in which the channel runs perpendicular to the lamina faces are described, and it is also suggested to form integrated circuits including diodes, resistors in the form of semi-conductor patterns or printed metal tracks, and capacitors using layer 9 as dielectric.