Patent GB-1495793-A (GB)
Title: Peripheral controller in a data processing system
IPC: G06F13/12
Filed: 1975-02-12
Abstract: 1495793 Peripheral control units COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII-HONEYWELL BULL 12 Feb 1975 [20 Feb 1974] 6004/75 Heading G4A A peripheral controller, Fig. 3, in a digital data processing system can connect any of a set of peripherals, e.g. a card reader, a paper tape reader, an optical document reader, amagnetic cassette reader, a paper-tape puncher or a printer to a central processing unit, each peripheral having a respective peripheral adaptor incorporating its own control microinstructions, each microinstruction being stored in one or other of a read/write store or a read-only store. The peripheral controller ICU incorporates a multi-processing unit MPU and has an interface ICU/PSI, Fig. 6A (not shown) with the central processing unit, an interface ICU/ DAI, Fig. 7A (not shown) with the peripheral adaptors, and an interface ICU/TIMER, Fig. 8 (not shown) with a timer module. Microinstructions are stored in one or other of a readwrite store 302 and a read-only store 303, one of the stores being addressed according to the state of a flip-flop 313 fed from a register 304. A register 305 receives the read-out microinstruction which provides control words ACLI and CTLI (see later) for I/O operations, controls an ALU 311, and tests, at an AND gate 314, whether a signal UEV 2s  is present, the signal indicating whether an "event" EV 2  of priority level 2 has occurred at a peripheral adaptor, the events EV each having one of two different priority levels 1 and 2. If the signal UEV 2s  is present, a conditional branch is made to another address for initiation of an interrupt routine, e.g. by means of an adder 306 adding the contents of registers 304 and 305. Incrementing of the address in register 304 in units of 1 is also possible by means of an incrementing network 307. A register 308 stores the number of the peripheral adaptor at which a job is being performed or is to be performed, the register 308 being loaded initially from a register bank 310. In the event of an interruption, register 308 is loaded by means of a signal CEV 1  from the ICU, a register 309 acting as a safeguarding register by storing the same starting address as register 308 during the interruption, register 308 being reloaded from register 309 subsequent to the interruption. The signal CEV 1  is present when an event EV 1  of priority level 1 occurs in any one of the peripheral adaptors, the event EV 1  signal being capable of being masked temporarily by means of a flip-flop 315 so as not to interrupt the microinstruction currently being executed. A register 312 stores error messages from the ALU 311 and also contains parameters required for initiating a fresh sub-programme. The signals ACLI and CTLI respectively indicate the nature of the data crossing the interfaces and the type of operation being performed by the ALU 311. The signals EV 1  from the peripheral adaptors are fed to a priority network, Fig. 5D, which produces the signal CEV 1  indicative of which peripheral adaptor has the highest priority, the various peripheral adaptors being assigned priorities, e.g. 0-15, which decrease with increase of peripheral adaptor number. The priority network comprises inverter-amplifiers 500-505, AND gates 506-510 and OR gates 511-514 connected as shown, each of the AND gates 506-510 having one more input than its predecessor (506 having the smallest number of inputs). The arrangement is such that if, e.g. signal EV 1 P 0  is present from peripheral adaptor 0, gate 511 is enabled but gates 512-514 are not, thus producing the signal CEV 1  = DCBA = 0001. Fig. 9 (not shown) illustrates an application of the invention to the particular case of a card reader as one of the peripherals, wherein the signal UEV 1  corresponds to a column of a card having been read and the signal UEV 2  corresponds to the last column of the card having been read.