Patent SG-11201907437U-A (SG)
Title: Efficient utilization of memory die area
Inventor: LAURENT CHRISTOPHE VINCENT ANTOINE
IPC: H01L45/00
Filed: 2018-02-07
Abstract: WO 18/ 15 1987 Al (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 23 August 2018 (23.08.2018) WIP0 I PCT omit IIl °nolo onm mo Imo oimIE (10) International Publication Number WO 2018/151987 Al (51) International Patent Classification: HO1L 27/24 (2006.01) H01L 27/11585 (2017.01) HO1L 27/108 (2006.01) HO1L 43/08 (2006.01) HO1L 27/11 (2006.01) HO1L 45/00 (2006.01) HO1L 27/11502 (2017.01) (21) International Application Number: PCT/US2018/017204 (22) International Filing Date: 07 February 2018 (07.02.2018) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/434,395 16 February 2017 (16.02.2017) US (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; 8000 South Federal Way, Boise, Idaho 83716-9632 (US). (72) Inventor: LAURENT, Christophe Vincent Antoine; 8000 S. Federal Way, Boise, Idaho 83716-9632 (US). (74) Agent: HARRIS, Philip W.; Holland & Hart LLP, P.O. Box 11583, Salt Lake City, Utah 84147 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(ii)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) (54) Title: EFFICIENT UTILIZATION OF MEMORY DIE AREA (57) : Methods, systems, and apparatus that support efficient uti- 415 lization of die area for crosspoint memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain types of support circuitry, such as decoders and sense amplifiers. Boundary tiles, which may be portions of an array having a different configuration from other portions of the array, may be positioned on one side of an array of memory tiles. The bound- ary tiles may include support components to access both memory cells of neighboring memory tiles and memory cells overlying the boundary tiles. Column lines and column line decoders may be integrated as part of a boundary tile. Access lines, such as row lines may be truncated or omitted at or near borders of the memory portion of the memory device. • Core portion Boundary portion FIG. 9 ▪ Control circuit portion 900 [Continued on next page] 1 11 I vino, I i I, 1111 ' . 114tn- / WO 2018/151987 Al MIDEDIM01101 DIDEVE31111111111111111111111111111111111111111111 Published: — with international search report (Art. 21(3))