Patent EP-0121004-A1 (EP)
Inventor: ELMIS HERBERT DIPL-ING
IPC: H04N5/06
Filed: 1983-08-09
Abstract: 1. Digital circuit for synchronizing a pulse train (fi) obtained as an output signal of a presettable frequency divider (ft) for a clock signal (ts) having a frequency at least one order of magnitude higher than that of the pulse train (fi) with horizontal synchronizing pulses (hs) contained in received standard television signal which, after being demodulated in the television receiver, is present as the composite colour signal, which is applied to an analog-to-digital converter (aw) clocked by the clock signal (ts), the divisor of the frequency divider (ft) being set depending on the phase difference between the the pulse train (fi) and the horizontal synchronizing pulses (hs) which is averaged over an averaging time equal to a major number of periods of the horizontal synchronizing pulses (hs), and a switching signal with a 1 : 1 mark-to-space ratio being derived from the frequency divider (ft) in the middle of the horizontal synchronizing pulse (hs), characterized by the following features if a positive composite colour signal is to be processed : The output of the analog-to-digital converter (aw) is connected to the input of a threshold stage (ws) having a threshold value equal to the desired black level (sw), to the input of a black-level-measuring stage (sm) to whose enable input (en) a pulse (kp), the keying pulse, is applied in each line during the burst, to the minuend input (m) of a first comparator (k1), and to the input of a first buffer memory (ps1) having its output connected to the subtrahend input (s) of the first comparator (k1), whose minuend-greater-than subtrahend ouptut (m > s) is connected to the enable input (eu) of the first buffer memory (ps1) ; the ouptut of the black-level-measuring stage (sm) or the output of a reprogrammable nonvolatile memory (rm) containing the desired black level (sw) and the output of the first buffer memory (ps1) are connected to the subtrahend input (s) and the minuend input (m), respectively, of a substracter (st) having its output connected to the dividend input (dd) of a first divider (d1) via a first limiter (b1) which limits its output to a positive numerical value near zero ; the output of the threshold stage (ws) is connected to the augend/minuend input (m) of an adder-substracer (a/s) having its output coupled to the input of a second buffer memory (ps2) whose output is connected to the addend/subtrahend input (s) of the adder-substracter (a/s) and to the dividend input (dd) of a second divider (d2) ; the output of the second divider (d2) is connected to the first input of a first adder (ad1) havint its output connected to the input of a digital low-pass filter (tp) via a second limiter (b2) which limits its output to the numerical value of the phase error required for a predetermined capture range of the synchronization ; p low-order terminals (nb) of the m-digit output of the low-pass filter (tp) are connected to the first input of a second adder (ad2) havint its output coupled to the input of a third buffer memory (ps3) ; the output of the third buffer memory (ps3) is connected to the second inputs of the first adder (ad1) and  the second adder (ad2) and to the set input (es) of a digitally settable delay line (v) which consists of 2**p stages providing the same delay (tv) and whose setting-step size is equal to this delay (tv) and to the period (t) of the clock signal (ts) divided by 2**p, the input of this delay line (v) being also connected to the maximum-count output (am) of a presettable counter (vz) to whose count input the clock signal (ts) is applied and the output of the delay line (v) providing the synchronized pulse train (fi) ; the overflow output (ao) of the second adder (ad2) is connected to the least significant terminal (Ib) of the first input of a third adder (ad3) having its second input connected to the m-p remaining terminals (gb) of the low-pass-filter output, the third input of the third adder (ad3) being fed with the integral part of the desired value of the divisor, ad the output of the third adder (ad3) being connected to the present input (ev) of the presettable counter (vz) ; the enable input (eu) of the third buffer memory (ps3) is connected to one of those outputs (an) of the presettable counter (vz) lying before the maximumcount output (am) ; to derive the switching signal from the frequency divider (ft), the output of the third adder (ad3) is connected to the first input of a first coincidence gate (kg1) and, through a divide-by-two divider (2d), to the first input of a second coincidence gate (kg2), and the second inputs of the coincidence gates (kg1, kg2) are connected to the outputs of the presettable counter (vz), while their outputs are connected to the add enable input (ae) and the substract enable input (es), respectively, of the adder-substract (a/s), and the divisor input (dr) of the first divider (d1) is presented with the numerical value 2**p.