Patent GB-776581-A (GB)
Title: Pulse-translating system
IPC: G01S13/78
Filed: 1955-05-16
Abstract: 776,581. Pulse radar; pulse circuits. HAZELTINE CORPORATION. May 16, 1955 [June 8, 1954], No. 14074/55. Classes 40(5) 40(6) and 40(7) Relates to a secondary radar system in which a transponder responds to interrogating pulse pairs of predetermined spacing, e.g. 10 Á-sec, Fig. 2a, code I, and emits corresponding reply pulse pairs which are selected at the response by a decoder and applied to an automatic ranging circuit which may be of the type disclosed in Specifications 652,666 and 703,667. When other transponders are operating simultaneously with different spacing codes, e.g. 5, 15 and 20 Á-sec, codes II, III and IV, Fig. 2a, the reply pulses from these other transponders may produce at the responser random pulss pairs having the desired spacing, i.e. 10 Á-sec, and according to the present invention the decoder includes means for discriminating against such random pulse pairs; similar means may also be included in the transponder to prevent it being triggered by random pulse pairs formed.by the combination of interrogating pulse pairs from interrogators operating in the other codes. In the first embodiment, Fig. 1a and Fig. 1 (not shown), the second pulse of every received pulse pair corresponding to the unwanted codes II, III and IV is cancelled. Thus if the unwanted pulses comprise two interleaved code III pulse pairs a, c and b, d, Fig. 2c, which would give rise to two spurious code I pulse pairs a, b and c, d, pulses c and d are cancelled leaving only one spurious code I pulse pair. In 'general the spurious pulse pairs are reduced by one quarter. The decoder comprises a delay line 49 having four sections 52-55 each producing a 5 Á-sec delay and four coincidence pentodes 50, 55, 56, 57- which produce a negative pulse output in response to received pulse pair codes I, II, III and IV respectively. The negative input pulses at terminals 41 are inverted in valve 48 and applied through capacitator 64 to the input terminal 3 of the delay line 49 and are inverted in valve 58 and applied through capacitor 73 to the suppressor grids of pentodes 55, 56 and 57 whose control grids are connected respectively to tappings 4 and 6 and end terminal 7 of the line 49, the anodes being connected to a common load 70 which is coupled through diode 71 to the anode of valve 48. Thus when a code II pulse pair is applied to input terminals 41, pentode 55 produces a negative output pulse coincident with the second pulse of the pair and at the anode of V48 this ouput, pulse connects the second pulse of the positive code II pulse pair so that only a single pulse is applied to line 49; a similar cancellation for codes III and IV is effected by pentodes 56 and 57. The suppressor and control grids of pentode 50 are connected respectively to terminal 3 and tapping 5 of line 49 so that pentode 50 produces a negative output pulse at terminals 42 in response to all code I pulse pairs reaching the input 3 of line 49. A short delay line 47, e.g. delay time equal to 1 Á-sec, is inserted between terminals 41 and valve 48 to compensate for the delay in valve 58. In the second embodiment, Fig. 3a and Figs. 3 and 4 (not shown) every input code I pulse pair (wanted or spurious) results in a single positive pulse delayed 20 Ásec relative to the first pulse of the input pair and every input code II, III or IV pulse pair results in a corresponding pair of negative pulses delayed 20 Á-sec relative to the input pulse pair so that every positive output pulse due to a spurious code I input pulse pair will be cancelled by one of the 9 negative pulses produced by the unwanted pulse. pairs. As shown the decoder comprises a four section delay line 49 and four coincidence pentodes 50, 55, 56 and 57 similar to those in Fig. la and an additional four section delay line 80 (section delay equal to 5 Á-sec). The input pulses at terminals 41 are applied only to the input of line 49 and the inputs to the code I pentode 50 are taken from tapping 3 and end terminal 5 of line 49, the negative output pulse from pentode 50 being applied through diode 91 and inverter 103 to give a positive pulse which is applied through diode 106 and amplifier 92 to the output terminals 42. The suppressor grids of pentodes 55, 56 and 57 are connected to the end terminal 5 of line 49, the control grids are connected respectively to input terminal 1 and tappings 2 and 4 of line 49 and the anodes are connected through the right-hand sections of the double diodes 87. 88 and 89 to the control grid of a pentode 98 and through the left-hand section of the double diodes to input 6 and tappings 7 and 9 respectively of line 80 whose output is connected to the suppressor of pentode 98; the anode output from pentode 98 is applied via inverter 101 to the anode of valve 103. Thus a code IV input rulse pair (20 Á-sec spacing) produces at the anode of pentode 55, a 20 Á-sec delayed negative pulse which is converted into a 20 Á-sec pulse pair by line 80, and corresponding pulse pairs for input codes III and II are produced by pentodes 56 and 57 respectively. The resultant negative pulse pairs are inverted in pentodes 98 and again in triode 101 to give negative pulses which cancel in the anode circuit of valve 103 any positive pulses due to spurious code I inputs.