Patent AU-2021203231-B2 (AU)
Title: Josephson polarity and logical inverter gates
Inventor: HERR QUENTIN P
IPC: H03K19/195
Filed: 2021-05-20
Granted: 2022-06-02
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) 
(19) World Intellectual Property 
(1) Organization11111111111111111111111I1111111111111ii111liiili 
International Bureau (10) International Publication Number 
(43) International Publication Date W O 2019/152243 Al 
08 August 2019 (08.08.2019) W IPO I PCT 
(51) InternationalPatent Classification: (81) Designated States (unless otherwise indicated, for every 
H03K19/195 (2006.01) G06N10/00 (2019.01) kind of national protection available): AE, AG, AL, AM, 
(21) International Application Number: AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, 
PCT/US2019/014803 CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, 
DZ, EC, EE, EG, ES, Fl, GB, GD, GE, GH, GM, GT, HN, 
(22) International Filing Date: HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, 
23 January 2019 (23.01.2019) KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, 
MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, 
(25)FilingOLanguage: English M, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, 
(26) Publication Language: English SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, 
(30) Priority Data: TR, TT, TZ, UA, 
UG, US, UZ, VC, VN, ZA, ZM, ZW.  
15/887,524 02 February 2018 (02.02.2018) US (84) Designated States (unless otherwise indicated, for every 
kind of regional protection available): ARIPO (BW, GH, 
(71)Applicant: NORTHROP GRUMMAN SYSTEMS GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, 
CORPORATION [US/US];2980 Fairview Park Drive UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, 
FallsChurch,Virginia22042-4511(US). TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, 
(72) Inventor: HERR, Quentin P.; 8987 Furrow Avenue, Elli- EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, 
cott City, Maryland 21042 (US). MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, 
TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, 
(74) Agent: HARRIS, Christopher P.; Tarolli, Sundheim, KM, ML, MR, NE, SN, TD, TG).  
Covell & Tunmino, LLP, 1300 East Ninth Street, Suite 
1700, Cleveland, Ohio 44114 (US).  
(54) Title: JOSEPHSON POLARITY AND LOGICAL INVERTER GATES 
JOSEPHSON 
INVERTER GATE 
100 
HALF-TWISTED JTL 
- 106 
IN JJ1 JJ2 JJ3 JJ4 OUT 
102 8108-1 1082 108-3 108-4 104 
1144 1 110U 112 116 
DC DC 
INPUT-SIDE OUTPUT-SIDE 
AC BIAS AC BIAS 
FIG. 1A 
CA (57) Abstract: A Josephson inverter gate circuit provides efficient implementation of polarity or logical inversion while eliminating the 
need for physically large high-efficiency magnetic transformers in the signal path. The circuit can consist of a half-twisted Josephson 
transmission line (JTL) or a JTL with an unshunted floating Josephson junction that produces two single flux quantum (SFQ) pulses 
when triggered by an SFQ input signal, which results in an output SFQ signal of reversed polarity. Implemented as a logical inverter, 
proper initialization of the circuit is accomplished within the signal inversion stage with flux biasing.
W O 20 19/152243 A 1 |||||||||||11111||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 
Declarations under Rule 4.17: 
- as to the identity ofthe inventor (Rule 4.17(1)) 
- as to the applicant's entitlement to claim the priority of the 
earlier application (Rule 4.17(iii)) 
Published: 
- with international search report (Art. 21(3)) 
- before the expiration of the time limit for amending the 
claims and to be republished in the event of receipt of 
amendments (Rule 48.2(h))