Patent GB-1220785-A (GB)
Title: Improvements in or relating to telecommunication exchange systems
IPC: G06F9/48
Filed: 1969-05-23
Abstract: 1,220,785. Automatic exchange systems. SIEMENS A.G. 23 May, 1969 [24 May, 1968], No. 26360/69. Heading H4K. In a programme controlled exchange, the timing of a plurality of functions is controlled by a single stepping register which has for each stage a store in which are located the addresses of the function to be performed at the time defined by the stage. A new address arriving at an arbitrary time is inserted into the relevant store by calculating the number of stages which must be stepped through before the start of the function at the new address. The calculation and consequent address insertion are performed after completion of the jobs allocated to the stage at which the register stands when the new address arrives. The functions may be: the production of metering pulses at a certain rate, e.g. day or night, for supply to calling subscribers' meters; the monitoring and registration of incoming dialling impulses; and the monitoring and sending of outgoing dialling impulses. Where specialized functions are required such as in metering pulse production an individual register having its stepping rate attuned to the function is preferred. In this case the number of stages in the counter may be altered to discriminate between fast rate day and low rate night metering, the stores associated with unused stages (during the day) being commandeered by the active stages. It should be noted here that although only a single function is effected, nonetheless metering pulses are provided for a pluralityof subscriber sets at a time and possibly at a rate which is unique for each. General description (Fig. 2).-The register Z1 comprises n stages and is stepped by pulses recurring at 1 m.sec. intervals-as supplied for example by the system clock T. It is assumed that the register is stopped at stage 2. The store in Sp1 associated with this stage is read-out to obtain the first address An-AD (see also Fig. 3) of a set of storage locations in an auxiliary store Sp2. These locations contain further addresses, e.g. of peripheral units or of programmes that must be operated-on or put into effect at the time indicated by the stage reached in the register. When all these operations have been initiated and preferably acknowledged by the return of a signal over lead be (Fig. 2b) to the register's control logic, the insertion of new addresses arriving in register REG into the storage locations is allowed. With each new address a central control supplies an indication of the time or times which should elapse before any action is demanded. The control logic determines the register stage which will be reached after the elapsed time and causes the store associated with this stage to be read-out by stepping the register on while storing its (correct) current position in store Puf. If it is assumed that action is required in 3 m.secs. time then the logic causes read-out from stage 5's store. On this occasion the data L-AD (Fig. 3) is of more significance since it effectively indicates the next empty location in the set of auxiliary storage locations (The entry 50 in L-AD at stage 5 indicates that the first auxiliary location is in use so ADD-1 logic determines that the next free location is 51.) The contents of L-AD are updated and-after all the other new addresses have been similarly dealt with-the register is returned to stage 2 so that with the appearance of the next clock pulse it can be stepped on to stage 3. It is suggested that stepping of the register by clock pulses be inhibited during the processes described above and it is implied that such inhibition will not unduly influence the operation of the system. The control logic is described with reference to Figs. 2a, 2b. Of some interest is the use of a plurality of self-stepping registers, e.g. t3, t4, t5, which effectively control all the various logical possibilities inherent in the above described processes. In order to allow for long-delayed operations, e.g. of the order of seconds, a plurality of stepping registers may be connected in series so as to effectively provide delays measured in units, tens, hundreds . . . times the basic stepping rate. The associated stores of each register's stages contain sufficient data to provide "fractional" delays, e.g. of 2, 3, 4 m.secs. (Fig. 4, not shown). The address data in each store (main and/or auxiliary) may be erased and rewritten (modified or unmodified) under central control's authority whenever it is read-out by a register stepping pulse, or, it may be automatically rewritten (modified or unmodified) by the register's control logic until either it is cancelled by central control or is selfcancelled, e.g. as a result of a series of modifications (Fig. 5, not shown). Application to impulse receiving and sending (Fig. 8, not shown).-Since this is a specialized function a stepping register (Fig. 5, not shown) having a 10 m.sec. stepping rate is utilized. Each digit receiver/sender is allocated a set of storage locations in the system's call store. Impulses of a train normally arrive at a 100 m.sec. rate and these are directed to one location of the corresponding receiver's set of such locations. With the first impulse of a train, the central control requests the stepping register to investigate the corresponding location every 50 m.secs. This is effected by writing the address of this location in the auxiliary store at a position which corresponds to a stage that is 5 stages removed from its currently active station-all this is described hereinabove. Another location in the set keeps a record of the number of occasions in which there is no change in the contents of the first location. When there has been no change after three scans by the stepping register an interdigital pause is presumed. The addresses in the stepping register's stores are cleared and the accumulated digit in the first location is transferred to another location of the set in dependence on whether it is the first, second, third, &c. digit that has been received. Allowance is made for impulses that arrive just before or just after the occurrence of a scan by the stepping register so that a clear interval of 150 m.secs. is always obtained before an intertrain pause is presumed. In order to send digits, each digit is entered in turn into a storage location of the set and is then counted down under the control of the stepping register which is seized by central control in an analogous manner to its seizure during digit reception. Before counting down can take place, however, the stepping register scans must be synchronized with the pulses from a central impulse generator so that only the correct number of impulses will be sent via the sender. The stepping register is not dismissed between digits as it was during reception but is used to time an interdigital pause by, e.g. counting down from the digit 10 whilst simultaneously inhibiting the transmission of impulses to the sender. It is suggested that the set of storage locations used for digit sending/receiving could be comprised in the auxiliary store instead of in the call store.