Patent GB-718983-A (GB)
Title: Improvements in or relating to electrical digital computers
IPC: G06F7/498
Filed: 1952-02-27
Abstract: 718,983. Digital electric calculating-apparatus. SOC. D'ELECTRONIQUE & D'AUTOMATISME. Feb. 27, 1952 [Feb. 27, 1951], No. 5211/52. Class 106 (1) For an electrical digital computer utilizing number-representing pulse trains in which successive decimal digits occur in series mode, a correcting "carry-over operator ", Fig. 9, comprises a decimal counter including an input 39, a units portion 71-74 and a tens portion 91-94, means for transferring the tens count to the units portion and a count related to the units count to an auxiliary counter 101-104, and read-out means associated with the auxiliary counter for deriving therefrom a series of pulses representing by their number the units count. The read-out means thus produces the corrected form of a pulse train applied to the input 39. In the computer described, numbers are applied to adding and multiplying circuits in the form, Fig. I (b), in which each decimal digit is represented during an associated decade or minor cycle U, D, C, &c., each comprising-ten equal digit periods #=r/10, by a corresponding number of pulses, but may be obtained, e:g., from a magnetic storage drum, in the pulse-position-coded form of Fig. 1 (a). For conversion to the pulse-number code, the pulses of Fig. 1 (a) (in negative form) are employed to reset a bi-stable trigger circuit 10, Fig. 2, which is actuated at the beginning of each minor cycle by a (negative) pulse, Fig. 1 (c), and, whi'e actuated, applies an opening potential to gate valve 21 to the control grid of which are applied clock pu'ses, Fig. 1 (d). The storage drum may have a period of revolution corresponding to a major cycle or largest number time T. Addition.-Two pu'se trains, Figs. 3 (b) and (e), representing numbers to be added, are relatively staggered by delay element 29 (see Fig. 3 (f)) and applied to a mixing circuit 26, 27, Fig. 4, whose output, Fig. 3 (g), is passed through carry-over onerator 30 to produce the corrected sum-train, Fig 3 (h). Carry-over operator. The counter 101-104. and each of the counter portions 71-74, 91-94, Fig. 9, comprises four series-connected bi-stable trigger pairs of valves (of which the one conductive in the reset condition is indicated by shading). The units counting portion includes feed-back connections 84, 85 whereby the normal count of 16 is reduced to 10; and the auxiliary counter includes feed-back connections 154-156 whereby the normal count is reduced by 7. In operation, at the beginning of each minor cycle, a pulse, Fig. 1 (c), is applied to terminals 79, 90, 118, 139 and 161. The pulse at 139 is applied to gates 135-138 controlled by triggers 71-74, to cause the nines complement of the units decimal value to be added in the auxiliary counter, staggering delays 144, 145 being provided, and the pulse at 118 similarly causes the tens value to be transferred from triggers 91-94 to the units triggers 71-74, delays 123-126, longer than 80, ensuring that these triggers are previously reset by the pulse at 79. The pu'se at 90 applied through de'ay 95 resets the tens triggers 91-94, and the pulse at 161, through delay 162, actuates a trigger 163 to open a gate 159 (similar to 21, Fig. 2) to which pulses (similar to those of Fig. 1 (d) ate applied from terminal 160. These pulses arc passed to output channel 31, Figs. 4 and 9, and also to the auxiliary Counter until the latter produces an output pulse on line 164 which resets trigger 163 and closes the gate. When e.g., the 13 units-denomination pulses, Fig. 3 (g)-cycle U, are applied at 39 the tens and units counter portions will register " 1 " and " 3 " respectively. At the beginning of the next cycle D, the carry digit " 1 " is transferred to the units portion and " 6 " (complement of " 3 ") is added in the auxiliary counter. Thus after 3 (16-7-6) pulses from the gate 159 the count will be completed so that the output is as shown at Fig. 3 (h)- cycle U. Multiplication; programming.-In the multiplying circuit, Fig. 6, the digit portions of a multiplicand pulse train are applied in turn from terminal 34 to a counter 35 comprising nine series-connected bi-stable trigger circuits with feed-back connections such that the number of triggers actuated (lower tube conductive) equals the number of pulses received. The actuated triggers open corresponding gates 41-49 to allow a multiplier train at 32, whose pulses are reduced in width in timing and shaping circuit 33, to be applied to separate tappings. preferably spaced by #/10, on a delay line 37 whose output (the number of pu'ses in which represents a partial product) is passed to a carry-over operator 30. The correct partial-product train is returned to the input 30 through a delay 50 of T-2r (which may comprise a track on a magnetic drum) and a shaping circuit 52 so as to be added, with a lead of one minor cycle r, to the next partial-product train corresponding to set-up of the next multiplicand digit on counter 35. When the final product has been formed an output gate is opened through programming circuits (Fig. 10, not shown). These circuits also include separate gates for the multiplicand and multiplier which are stored on a single track of a magnetic drum with interposition of a pilot signal (S), and means including frequency-dividers for deriving control pulses from clock pulses, Fig. 1 (d), also obtained from a magnetic track. When one progressively stepped control pulse coincides with the signal S, an end-of-multiplication signal is produced and passed to program control equipment from which a multiply-instruction signal was previously obtained.