Patent GB-1260391-A (GB)
Title: Storage and scanning, e.g. for computer control
IPC: G06F13/22
Filed: 1969-02-05
Abstract: 1,260,391. Data processor. TELEFONAKTIEBOLAGET L. M. ERICSSON. 5 Feb., 1969 [7 Feb., 1968; 17 June, 1968], No. 6298/69. Heading G4A. The invention relates to a processor indicating the location of elements, such as switching relays in a telecommunications system, which have changed state. A first memory contains locations, each corresponding to an element, which are set to "1" if the element changes state. The locations have an initial starting address B0 and an index corresponding to the index of the element. As shown 32 x 16 bit words are used as the locations. A second memory contains locations corresponding to the words in the first area with a second location being set if a word in the first memory contains a "1". The second memory commences at address B 1 and the index of each location is related to the index of the element. As described the four least significant bits of the index in binary form define the position of a required bit in a word in the first area and the remainder of the index is added to B0 to define the required word in the primary area. The four least significant bits of the said remainder define the position of the required bit in a word in the secondary area and the rest of the said remainder is added to M0 to define the required word in the secondary area. A store DM contains a primary storage area commencing with address B0 and a secondary storage area commencing with address B1. The primary area contains e.g. 32 x 16-bit words each bit representing the state of e.g. line relays in a telecommunications system. The secondary area contains e.g. 2 16-bit words each bit corresponding to a different one of the 32 words in the primary area and indicating whether one or more of the bits in the word are set to "1". The operation of the system is controlled by words taken from Instruction Memory IM which produce a microprogramme shown in controlling unit SE. A word in Order Register OR is decoded in Units AKl-3 to select an appropriate microprogramme from SE (three programmes are indicated in Figs. 2b, 3b, 4b). If on scanning of the relays one is found to have changed state e.g. one identified by an index number 38, then the corresponding bit in the primary area and the bit indicating the corresponding bit in the secondary area are changed. Figs. 2a, 2b indicate how this process is carried out The programme steps indicated in SE are followed consecutively, the gates indicated on the right being rendered conductive so that the index 38 in R2 is transferred to the adder shifted right four places, the four least significant bits being held in B0R (step 202) and BA (step 205). The base address B0 is obtained from memory DM by using the read input L and is transferred to an adder AE where it is added to the shifted index and supplied to address register 1. The word held in the address is read out to R4 (step 207). A flip-flop FV is set or reset depending on whether the word containing index 38 already has a location set to "1" or not and the appropriate location is set to "1" the location being determined by the address in BA. The updated word is returned to the memory. If the word had previously contained a "1" FU would be reset and the corresponding location in the secondary area would also be set so a new routine N12 would commence. If no other bit was "1" the address in Rl would be supplied to the adder, shifted four places right, the least significant four bits being received in B0R (step 214) and the shifted signal added to address M0, (M0 = Bl - B0) to give the address of the word containing the required bit. This word is supplied to R4 and the appropriate bit defined by the address in B0R is set to 1 (step 220). The word is returned to memory and a new routine commenced. The Specification also gives routines determining the index of positions set to "1" (Fig. 3b, not shown) and resetting positions set to "1" (Fig. 4b, not shown).