Patent GB-809871-A (GB)
Title: Improvements in or relating to automatic telecommunication exchanges
Inventor: BRAY FREDERICK HARRY
IPC: A45D8/38
Filed: 1956-09-07
Abstract: 809,871. Multiplex transmission; automatic exchange systems. STANDARD TELEPHONES & CABLES Ltd. Sept. 7, 1956, No. 27464/56. Class 40 (4). In a time division multiplex signalling system for signalling between a number of first circuits and a number of second circuits in which a signalling channel on the multiplex highway is permanently allocated to each first channel via first gating means, the identity of a second circuit to which a channel is to be temporarily allocated is stored in a store associated with that channel, and each such store is scanned at the time position of its channel, the detection of the identity of a second circuit in a store causing second gating means to interconnect that second circuit and the multiplex highway at the time position at which the store was scanned, so that a first circuit and a second circuit are interconnected by the first gating means, the highway, and the second gating means at the time position forming the channel allocated to that first circuit. General description, Figs. 1, 2.-The timedivision multiplex system described is used to convey the supervisory signals in a telephone exchange such as that of Specification 794,812, and has two multiplex highways H1 and H2 employed for " go " and " return " signals, respectively. Each highway provides 2000 channels, one of which is permanently allotted to each of the first links of the exchange. Each channel is allotted a row of 26 storage elements in a co-ordinate magnetic matrix store CS which controls both highways, of which row elements Nos. 1 to 9 store the partial identity of a calling subscriber connected to the first link pertaining to that row, elements Nos. 10 to 12 store the call fee, elements Nos. 13 to 25 store of the identity of the final link of the exchange to which the connection has been extended, and element No. 26 is the metering element. There is one column circuit CC for each column of the matrix CS and all reading of and writing in a row takes place via the column circuits. A scanning device, the read access switch RAS, pulses the rows of the matrix CS, each at the time position in the multiplex cycle which forms the channel to which that row pertains. The outputs from column circuits Nos. 1 to 12 and 26 extend to the input circuit IC for the temporary meter store MS, and those from column circuits Nos. 13 to 25 to the final link access switch FLAS. Each element of the matrix CS is formed by the magnetic material surrounding a small hole in a ferrite block. Each vertical is a wire passing through the corresponding holes in all the rows and functions as a reading winding and as a write/rewrite winding for those elements. The horizontal wires, each of which passes through all the holes of a row, are pulsed sequentially by pulse combinations consisting of a 2 Á sec. read pulse followed after approximately 5 Á sec. by a 4 Á sec. half-write pulse of opposite polarity. When a row is pulsed by a read pulse the data stored is read out destructively over the column wires and if it is to be retained it is re-applied to the column wires at a time to coincide with the half-write row pulse and thus to re-write the data. When a connection has been extended from a first link to a fmal link the partial identity of the calling line, the meter fee, and the identity of the seized final link are recorded in the seized first link's row of CS over inputs W, X, and Y from a calling line marker, a called line marker, and the seized final link, respectively. The latter identity is read from the matrix store and transmitted to FLAS to energize an output individual to the seized final link at the time position of the seized first link's channel. The " go " multiplex system has at the sending end a gate, e.g. GL1, per first link which is pulsed, at the same time as the first link's row, over leads such as RP1, and is thus opened at the first link's time position in the multiplex cycle. The second control A of each GL gate is energized. as long as the A relay in the corresponding first link, which is operated on seizure of the link and remains so until the calling party hangs up, is energized. Consequently, until the collar hangs up, a pulse at the time position of the first link he has seized is applied to the highway HI. The output from the final link access switch FLAS opens, at the time position of the seized first link, via a lead such as FL1 the gate such as GF1 for the seized final link which thus passes the pulse from the GL gate to operate a bistable trigger such as BT1 of that final link to its set condition. This pulse also inhibits the reset gate such as GR1 for the same trigger. The reset gate has all the row pulses applied to it and so the trigger is reset by the next row pulse and continues to be set and reset on each cycle until, when the caller hangs up, no pulse arrives over H1 at the time position of the seized first link and the trigger is then not set. The " return " multiplex system operates in like manner, the final link gates having their D inputs energized as long as the D relays of the final links, which are operated on seizure of the final link and remain so until the final link is released, are energized. Metering.-When a called party answers, " 1 " is recorded in column 26 of the row of CS concerned. The first time during the scanning of the rows of CS that a row with a " 1 " in column 26 is read at which IC and MS are free, the data in columns 1 to 12 is transferred to IC, and, at the same time, RAS passes to IC information to complete the identification of the calling line. All this information passes to MS for recording. Detailed description; row access switch, Fig. 4. This consists of three closed ring counters DU, DT, and DH, of which the first two are 10-unit counters and the last a 20-unit counter. DU is driven by 2 Á sec. read pulses, DT by the output of stage 1 of DU, and DH by the output of stage 1 of DT. For each row of the matrix CS a gate RG is controlled by the outputs of the corresponding stages of the three counters to pass a row pulse in the time position of that row. Column circuits, Figs. 5, 6.-The control circuits for the columns are shown schematically in Fig. 5, the blocks 1 to 25 of which each includes the reading/writing/re-writing circuit of Fig. 6. In the exchange a calling subscriber is temporarily associated with a calling line marker serving fifty lines having the same tens and units digit combination and thus the identity of the calling line marker partially identifies the caller. For each such marker there is a delay element DE (Fig. 5) via which a pulse is passed when the marker is in use to a combination of the leads incoming to column circuits 1 to 9 indicative of that marker, thus providing to the " new inf. " leads (Fig. 6) of those column circuits a half-write input which persists for longer than the multiplex scan time. When a first link is seized, its relay S (not shown) is operated and there is a short period in which a first link's relay S is operated and the calling line marker is engaged by the line which caused the seizure of that first link. During this period energizing potential is applied over that first link's lead SM (Fig. 5) to a beginning element BE1 which produces an output signal which starts when the input potential starts and persists for a fixed period long enough to ensure that it exists coincidently with the output from DE for more than one scan. The output of BE1 is applied via a gate G1, which is opened by the row access pulse of that link, to the " write/re-write " leads (Fig. 6) of column circuits 1 to 9. In each column circuit this input is applied to gates G6 and G8 so that when a first link has just been seized the DE output is gated by G8 to G7. To the lead CWP (Fig. 6) of each column circuit is applied a column write pulse coincident with the write portion of a row access pulse and provided the cancel lead is not energized the new information from DE is written into the relevant columns. During normal reading and re-writing the information read on the row read pulse appears across the column impedance and is applied to the end element EE1 which produces an output signal lasting for a fixed period and starting at the end of the input signal. The output of EE1 is applied to G6 and, in the absence of energization of the write/ re-write lead, passes to G7 to produce similar results to those produced by the new information input from G8. When a first link is not in use its lead SE (Fig. 5) is energized, so that the row access pulses are gated by G2 to the cancel leads of gates G7 (Fig. 6), thus preventing writing or re-writing in the columns. The new information leads of column circuits 10 to 12 are marked by the called line marker in accordance with the call fee and when the register causes the first link to mark forward and the called line marker (or junction circuit) causes the final link to mark backward, gate G3 (Fig. 5) opens and via beginning element BE2 opens gate G4 to pass the row access pulse of the first link to the write/re-write leads of columns circuits 10 to 25. Just after the seizure of the final link its SZ relay is operated and its HA relay not operated so that G5 (Fig. 5) of that link opens and via beginning element BE3 marks a combination of the " new inf. " leads of column circuits 13 to 25 indicative of that final link, which in combination with the pulse from G4 and the CWP pulse writes the identity of the final link in elements 13 to 25 of the seized first link's row of the matrix. Metering column circuit 26, Fig. 7.-In the exchange the reply of the called party causes a transient signal to be returned from the final link (or outgoing junction) to a slow release element SR1 (Fig. 7), which produces an output starting at the beginning of the input signal and ceasing a fixed time after the end of the input signal. The output is applied to a bistable element T1 which responds to the end of