Patent SE-329864-B (SE)
Inventor: BECKER F
IPC: H03D1/24
Filed: 1966-05-27
Abstract: 1,153,126. Digital transmission systems; automatic phase control; transistor pulse circuits. WESTERN ELECTRIC CO. Inc. 27 May, 1966 [28 May, 1965], No. 23774/66. Headings H3A, H3T, H4P and H4R. A demodulator for suppressed carrier amplitude-modulated multilevel data comprises means responsive to the low frequency components in the demodulator output for phase-adjusting the carrier fed to the demodulator so that it is in the required phase. The data, which is accompanied by pilot frequencies and is preceded by carrier frequency and starting pulses, feeds first and second balanced modulators (29, 32), Fig. 2 (not shown), which are also fed by carriers 90 degrees apart. The carriers are derived from a circuit fed by the received signals, and pass via a phase shifter (22) to the modulators. Low frequency components in the modulator outputs, when their amplitude is high enough as determined by threshold units (42, 43), allow low frequency clock pulses to step a reversible counter (39) whose output passes via a digital to analog converter (40) to control the phase shifter (22). These components are also fed to an exclusive OR circuit (36) which controls the direction of the counting. The first modulator (29), which is fed by carrier in phase with the received signals, provides data output to the remainder of the receiver system, which includes error detecting means. In the event of high error rate, such as may occur when the phase of the carrier is reversed, the error detector causes the carrier phase to be reversed. During the starting period, when carrier and pilots alone are received, the filter (38) which selects the low frequency components from the first modulator (29) is connected not to the modulator but to a D.C. source of potential equal to that that the modulator provides when the derived carrier has been adjusted to the correct phase. Transistor circuits. Balanced modulators, Fig. 5. Transformer 81 of the in-phase modulator 29 receives the input a.m. signal, demodulated signals being taken from tap 83a. Positive potential applied to the emitters of transistors 87, 88 counteract junction offset voltages. The bases of 87, 88 are fed by in-phase carrier from multivibrator 98, which is the same as that shown at 99. The quadrature modulator 32 is similar but since its output is not used in the data decoding process offset compensation is not provided. Capacitor 91 and potentiometer 83 which give improved balance in the data output in modulator 29 are also omitted from modulator 32. Phase shifter, Fig. 6. The multilevel output from the digital-analog converter, which controls the phase shift, feeds a number of stages, all as at 189, via resistor 183. Each stage is a trigger circuit and is coupled to the next by a delay network. The control signal adjusts the triggering threshold. The carrier harmonic square-wave to be shifted passes via amplifier 187 so that a positive pulse discharges capacitor 193. At the end of the pulse transistor 190 conducts for a period determined by 193, 202. Then 197 charges, eventually turning on transistor 191 and hence 192 off, the latter giving a positive transition to the next stage. The pulse from the final stage turns transistor 207 on, so providing a negative pulse to the multivibrator circuit 99, Fig. 5. Threshold circuits, Fig. 8. The low frequency components from the associated modulator feeds phase-inverting differential amplifier 147, 148, the threshold being set by rheostat 159. When the amplifier output is high enough to drive rectifier bridge 160 to conduction an output signal appears at the collector of transistor 162. The setting of tap 151 and the threshold of the bridge 160 combine with the effect of a low-pass filter in the modulator output to define the band of the low frequency components which take part in the phase adjustment.