Patent GB-851040-A (GB)
Title: Improvements in or relating to magnetic core storage systems
Inventor: WILLIAMS FREDERIC CALLAND
IPC: G11C11/06
Filed: 1955-11-30
Abstract: 851,040. Circuits employing bi-stable magnetic elements. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Nov. 26, 1956 [Nov. 30, 1955], No. 34321/55. Class 40 (9). [Also in Group XIX] Magnetic cores are arranged in pairs in a storage matrix like that described in Specification 851,039. Each pair comprises a storage core and a switching core linked by a common winding Z so that a change of state in one core tends to drive the other core to the same final state but produces only 60% of the saturation flux. The storage cores A1-An, B1-Bn, C1-Cn are linked in rows and columns by conductors YA-YC, R1-Rn, the latter set being used for reading only. The switching cores a1-cn are linked in columns only by conductors X1-Xn over which the binary digits 1, 0 may be entered into the cores. Operation.-A controlling waveform applied to lead YA, YB or YC over switch SM1 consists of two consecutive pulses y1, y2, Fig. 2 (a), of opposite polarity. Assume that the storage cores linked with lead YB store the binary number 101 and that after reading, a number 011 is entered in the same row. The initial and the final states of the cores are shown in lines (1) and (4b) of Fig. 3. Reading.-The negative pulse y1, Fig. 2 (a), drives all the storage cores B1-Bn to state 0 and the switching cores b1-bn remain in state 0. Pulses r1, Fig. 2 (c), are transmitted over leads R1, Rn, linked with cores B1, Bn, which have changed from 1 to 0. A low-level pulse r2 is transmitted over lead R2 linked with core B2 which is driven from 60% of the maximum or saturation flux to 100% flux. Signal receivers SE1-SEn discriminate between the pulses r1, r2 signalling the digits 1 and 0. In Fig. 2, the chain lines indicate the flux level in the core to which the pulses are applied. Writing.-The first half (a) of the second pulse y2 drives all the storage cores and the switching cores to state 1 (see line (3), Fig. 3), and a pulse r3 is transmitted over all the leads R1-Rn. The switches DV2, DVn are set to digit 1 and during the second half (b) of pulse y2, pulses x1, Fig. 2 (b1) derived from lead 12 drive cores b2, bn to the normal state 0, leaving the storage cores B2, Bn held in state 1 by pulse y2 (b) (see line (4a), Fig. 3). Switch DV1 is set to digit 0 and pulse x2 derived from lead 14 drives core b1 to normal state 0 and core B1 follows with only 60% of maximum flux. At this stage, the digit 0 is signalled by a pulse r4 when the storage core changes from 1 (100% positive flux) to 0 (60% negative flux). Interpretation of signals.-In one arrangement, not shown, a signal received by SE1 is amplified and applied to a pentode which is biased back so as to conduct in response to signals greater than r2 and less than r1 during sampling periods determined by pulses S1, Fig. 2 (g), applied to the suppressor grid. In another arrangement, the output on lead R1 is integrated for the period of pulses y1 and y2 (a). The time integrals on reading cores storing the digits 0 and 1 are shown in Figs. 2 (d) and (e). The time integrals are sampled during the period of a pulse S2, Fig. 2 (f). A zero signal indicates the digit 1 and a positive signal indicates the digit 0. In a third arrangement the time integrals of Figs. 2 (d) and (e) are integrated again for a sampling period determined by pulse S3, Fig. 2 (h).