Patent GB-1290534-A (GB)
IPC: H03K19/084
Filed: 1969-09-26
Abstract: 1290534 Selective signalling TOKYO SHIBAURA ELECTRIC CO Ltd 26 Sept 1969 [26 Sept 1968(2) 14 Nov 1968 15 Nov 1968 20 Nov 1968] 47405/69 Heading G4H A digital to analogue converter Fig. 3b comprises a network having a plurality of terminals, one for each input bit, and is characterized in that to each. terminal one of the voltages +E, 0, and E is applied in accordance with both the value of the associated input bit b j  and the value of the most significant input bit b 0  (which in the embodiments is a sign bit). The Specification discusses at length the errors associated with a known ladder network; Fig. 2b, to each rung of which is applied either + E or - E in accordance with the associated bit, and shows that by using a three-voltage ladder as in Fig. 3b considerably less error is produced in the output signal for a given degree of tolerance in the ladder resistors. The ladder shown in Fig. 3b (characteristic Fig 5) has n - 1 stages for n - 1 magnitude bits b 1  b 2  . . . b n-1 , and the potential applied to run j is (2b 0-1 )b j E, where b 0  is a sign bit, i.e. the potential is either zero if the associated bit b j  is 0 or + E or - E in accordance with the sign bit b 0 . (It should be noted that whereas the known ladder of Fig. 2b is designed to be controlled by: a word C 0  C 1  . . . C n-1  in which C 0  is a sign bit and the bits C 1  C 2  . . . C n-1  either indicate the magnitude of the number of the ones complement thereof, for the ladder of Fig. 3b the bits b 1  b 2  . . . b n-1  always indicate the magnitude of the number independently of the sign bit b 0 ) A modification of the ladder of Fig. 3b is shown in Fig. 6 (characteristic Fig. 7) having an additional rung S n  control by the sign bit b 0 , the result being to increase or decrease the output signal by half an increment in accordance with whether the sign is positive or negative respectively. However when this ladder is used in conjunction with a companding system for speech encoding, e.g. a system in which a range which would be covered linearly by an 11-bit signed number b 0  b 1  . . . b 10  is covered non-linearly by 7-bit signed number do d 1  . . . d 6 , (d 0  = sign d 1  d 2  d 3  = segment, d 4  d 5  d 6  = position within segment) the 7-bits being expanded digitally to 11-bits, then successive values in the non-linear system are as shown in Fig. 8 from which it can be seen that there is an abrupt change in the average trend (shown dotted) when going from segment II to segment III. This is stated to cause third order distortion and is removed by a modification (Fig. 9 not shown) by controlling the additional stage S n  of Fig. 6 in a more complex manner so that the bias of half an increment introduced by it is only produced during the first two segments (i.e. when b 1 = b 2  = b 3  = b 4  = b 5  = b 6  = 0). This results in a smoother characteristic as shown in Fig. 10. Details of the digital companding considered are as follows. The complete range covered by an 11-bit number b 0  b 1  . . . b 10 , bit b 0  being a sign bit and being virtually ignorable as far as manipulations upon the other bits are concerned, is divided into eight segments numbered VIII, VII . . . II, I, in Fig. 4A, determined by the position of the most significant 1-bit. In segment VIII it is b 1 , in segment VII b 2 , and so on. In the companded form Fig. 4B a sign bit d 0  corresponds to the sign bit b 0 , 3-bits d 1  d 2  d 3  indicate the segment number, and 3-bits d 4  d 5  d 6  correspond to the 3-bits following the most significant 1-bit. The companded bits d 0  d 1  . . . d 6  are expanded digitally, see Fig. 4C, to produce a sign bit b<SP>1</SP> 0  corresponding to bit d 0 , then a group of bits (e.g. bits b<SP>1</SP> 1  b<SP>1</SP> 2  ...b<SP>1</SP> 5  for segment IV) that correspond to the segment bits d 1  d 2  d 3 , then 3-bits that correspond to bits d 4  d 5  d 6  and finally (if necessary) a 1-bit followed by 0-bits. Following the theoretical discussion the specification describes five switching circuits for voltage driven ladders and eleven switching circuits for current driven ladders. Two examples for voltage driven ladders are as follows. Fig. 12 shows a switch controlled by input bits C 0 , C j  of a ones complement type code, which applies either - E, 0, or + E to a terminal 9 at the end of one of the rungs of the ladder. The potential of terminal 9 is given by the following table where V is greater than E. Fig. 15 shows a switch controlled by input bits b 0 , b j  (the inverse bit b j  is also utilized) which applies a potential to a terminal 9 given by a following table.