Patent SG-11201900375Y-A (SG)
Title: Link error correction in memory system
Inventor: SUH JUNGWON
IPC: G06F11/10
Filed: 2017-07-07
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property 1 MI 10H 0 ill 010 la 01 110 1 0 0111E011H H 0111 0011110 1111 OEN Organization International Bureau (10) International Publication Number (43) International Publication Date .....0\"\"\"1 WO 2018/038813 Al 01 March 2018 (01.03.2018) W I PO I PCT (51) International Patent Classification: (72) Inventor: SUH, Jungwon; QUALCOMM INCORPO- GO6F 11/10 (2006.01) RATED, 5775 Morehouse Drive, San Diego, California (21) International Application Number: 92121-1714 (US). PCT/US2017/041129 (74) Agent: OLDS, Mark E. et al.; Muncy, Geissler, Olds & (22) International Filing Date: Lowe, P.C., 4000 Legato Road, Suite 310, Fairfax, Virginia 07 July 2017 (07.07.2017) 22033 (US). (25) Filing Language: English (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, (26) Publication Language: English AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, (30) Priority Data: CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, 62/380,104 26 August 2016 (26.08.2016) US DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, 15/643,455 06 July 2017 (06.07.2017) US HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, (71) Applicant: QUALCOMM INCORPORATED [US/US]; MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, ATTN: International IP Administration, 5775 Morehouse OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, Drive, San Diego, California 92121-1714 (US). SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. = (54) Title: LINK ERROR CORRECTION IN MEMORY SYSTEM 400 490 , 460 _ .------N DQ[0 7] w — DM ► I = / DATA CK 432 READ STROBE CK ► 464 = 4 = 434 462 = COMMAND & ADDRESS CA[0 n] / ► = ► r. 6. = _ CA CK = — _ = — 420 430 410 450 —,,....._ 470 Il FIG. 4 M 1-1 of (57) : Conventional link error correction techniques in memory subsystems include either widening the I/O width or increasing Op the burst length. However, both techniques have drawbacks. In one or more aspects, it is proposed to incorporate link error correction C in both the host and the memory devices to address the drawbacks associated with the conventional techniques. The proposed memory ---, subsystem is advantageous in that the interface architecture of conventional memory systems can be maintained. Also, the link error 0 1-1 0 correction is capability is provided with the proposed memory subsystem without increasing the I/O width and without increasing the cz burst length. N C [Continued on next page] WO 2018/038813 Al MIDEDIMOMOIDEIREIHNIMIOMBHOMMOVOIS (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))